1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", isa);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3002 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3003 ix86_tls_dialect = TLS_DIALECT_SUN;
3005 error ("bad value (%s) for %stls-dialect=%s %s",
3006 ix86_tls_dialect_string, prefix, suffix, sw);
3009 if (ix87_precision_string)
3011 i = atoi (ix87_precision_string);
3012 if (i != 32 && i != 64 && i != 80)
3013 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3018 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3020 /* Enable by default the SSE and MMX builtins. Do allow the user to
3021 explicitly disable any of these. In particular, disabling SSE and
3022 MMX for kernel code is extremely useful. */
3023 if (!ix86_arch_specified)
3025 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3026 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3029 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3033 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3035 if (!ix86_arch_specified)
3037 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3039 /* i386 ABI does not specify red zone. It still makes sense to use it
3040 when programmer takes care to stack from being destroyed. */
3041 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3042 target_flags |= MASK_NO_RED_ZONE;
3045 /* Keep nonleaf frame pointers. */
3046 if (flag_omit_frame_pointer)
3047 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3048 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3049 flag_omit_frame_pointer = 1;
3051 /* If we're doing fast math, we don't care about comparison order
3052 wrt NaNs. This lets us use a shorter comparison sequence. */
3053 if (flag_finite_math_only)
3054 target_flags &= ~MASK_IEEE_FP;
3056 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3057 since the insns won't need emulation. */
3058 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3059 target_flags &= ~MASK_NO_FANCY_MATH_387;
3061 /* Likewise, if the target doesn't have a 387, or we've specified
3062 software floating point, don't use 387 inline intrinsics. */
3064 target_flags |= MASK_NO_FANCY_MATH_387;
3066 /* Turn on MMX builtins for -msse. */
3069 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3070 x86_prefetch_sse = true;
3073 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3074 if (TARGET_SSE4_2 || TARGET_ABM)
3075 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3077 /* Validate -mpreferred-stack-boundary= value or default it to
3078 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3079 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3080 if (ix86_preferred_stack_boundary_string)
3082 i = atoi (ix86_preferred_stack_boundary_string);
3083 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3084 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3085 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3087 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3090 /* Set the default value for -mstackrealign. */
3091 if (ix86_force_align_arg_pointer == -1)
3092 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3094 /* Validate -mincoming-stack-boundary= value or default it to
3095 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3096 if (ix86_force_align_arg_pointer)
3097 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3099 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3100 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3101 if (ix86_incoming_stack_boundary_string)
3103 i = atoi (ix86_incoming_stack_boundary_string);
3104 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3105 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3106 i, TARGET_64BIT ? 4 : 2);
3109 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3110 ix86_incoming_stack_boundary
3111 = ix86_user_incoming_stack_boundary;
3115 /* Accept -msseregparm only if at least SSE support is enabled. */
3116 if (TARGET_SSEREGPARM
3118 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3120 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3121 if (ix86_fpmath_string != 0)
3123 if (! strcmp (ix86_fpmath_string, "387"))
3124 ix86_fpmath = FPMATH_387;
3125 else if (! strcmp (ix86_fpmath_string, "sse"))
3129 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3130 ix86_fpmath = FPMATH_387;
3133 ix86_fpmath = FPMATH_SSE;
3135 else if (! strcmp (ix86_fpmath_string, "387,sse")
3136 || ! strcmp (ix86_fpmath_string, "387+sse")
3137 || ! strcmp (ix86_fpmath_string, "sse,387")
3138 || ! strcmp (ix86_fpmath_string, "sse+387")
3139 || ! strcmp (ix86_fpmath_string, "both"))
3143 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3144 ix86_fpmath = FPMATH_387;
3146 else if (!TARGET_80387)
3148 warning (0, "387 instruction set disabled, using SSE arithmetics");
3149 ix86_fpmath = FPMATH_SSE;
3152 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3155 error ("bad value (%s) for %sfpmath=%s %s",
3156 ix86_fpmath_string, prefix, suffix, sw);
3159 /* If the i387 is disabled, then do not return values in it. */
3161 target_flags &= ~MASK_FLOAT_RETURNS;
3163 /* Use external vectorized library in vectorizing intrinsics. */
3164 if (ix86_veclibabi_string)
3166 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_svml;
3168 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3169 ix86_veclib_handler = ix86_veclibabi_acml;
3171 error ("unknown vectorization library ABI type (%s) for "
3172 "%sveclibabi=%s %s", ix86_veclibabi_string,
3173 prefix, suffix, sw);
3176 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3177 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3179 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3181 /* ??? Unwind info is not correct around the CFG unless either a frame
3182 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3183 unwind info generation to be aware of the CFG and propagating states
3185 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3186 || flag_exceptions || flag_non_call_exceptions)
3187 && flag_omit_frame_pointer
3188 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3190 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3191 warning (0, "unwind tables currently require either a frame pointer "
3192 "or %saccumulate-outgoing-args%s for correctness",
3194 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3197 /* If stack probes are required, the space used for large function
3198 arguments on the stack must also be probed, so enable
3199 -maccumulate-outgoing-args so this happens in the prologue. */
3200 if (TARGET_STACK_PROBE
3201 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3203 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3204 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3205 "for correctness", prefix, suffix);
3206 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3209 /* For sane SSE instruction set generation we need fcomi instruction.
3210 It is safe to enable all CMOVE instructions. */
3214 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3217 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3218 p = strchr (internal_label_prefix, 'X');
3219 internal_label_prefix_len = p - internal_label_prefix;
3223 /* When scheduling description is not available, disable scheduler pass
3224 so it won't slow down the compilation and make x87 code slower. */
3225 if (!TARGET_SCHEDULE)
3226 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3228 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3229 set_param_value ("simultaneous-prefetches",
3230 ix86_cost->simultaneous_prefetches);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3232 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3233 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3234 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3235 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3236 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3238 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3239 can be optimized to ap = __builtin_next_arg (0). */
3241 targetm.expand_builtin_va_start = NULL;
3245 ix86_gen_leave = gen_leave_rex64;
3246 ix86_gen_pop1 = gen_popdi1;
3247 ix86_gen_add3 = gen_adddi3;
3248 ix86_gen_sub3 = gen_subdi3;
3249 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3250 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3251 ix86_gen_monitor = gen_sse3_monitor64;
3252 ix86_gen_andsp = gen_anddi3;
3256 ix86_gen_leave = gen_leave;
3257 ix86_gen_pop1 = gen_popsi1;
3258 ix86_gen_add3 = gen_addsi3;
3259 ix86_gen_sub3 = gen_subsi3;
3260 ix86_gen_sub3_carry = gen_subsi3_carry;
3261 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3262 ix86_gen_monitor = gen_sse3_monitor;
3263 ix86_gen_andsp = gen_andsi3;
3267 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 target_flags |= MASK_CLD & ~target_flags_explicit;
3272 /* Save the initial options in case the user does function specific options */
3274 target_option_default_node = target_option_current_node
3275 = build_target_option_node ();
3278 /* Save the current options */
3281 ix86_function_specific_save (struct cl_target_option *ptr)
3283 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3284 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3285 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3286 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3287 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3289 ptr->arch = ix86_arch;
3290 ptr->schedule = ix86_schedule;
3291 ptr->tune = ix86_tune;
3292 ptr->fpmath = ix86_fpmath;
3293 ptr->branch_cost = ix86_branch_cost;
3294 ptr->tune_defaulted = ix86_tune_defaulted;
3295 ptr->arch_specified = ix86_arch_specified;
3296 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3297 ptr->target_flags_explicit = target_flags_explicit;
3300 /* Restore the current options */
3303 ix86_function_specific_restore (struct cl_target_option *ptr)
3305 enum processor_type old_tune = ix86_tune;
3306 enum processor_type old_arch = ix86_arch;
3307 unsigned int ix86_arch_mask, ix86_tune_mask;
3310 ix86_arch = ptr->arch;
3311 ix86_schedule = ptr->schedule;
3312 ix86_tune = ptr->tune;
3313 ix86_fpmath = ptr->fpmath;
3314 ix86_branch_cost = ptr->branch_cost;
3315 ix86_tune_defaulted = ptr->tune_defaulted;
3316 ix86_arch_specified = ptr->arch_specified;
3317 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3318 target_flags_explicit = ptr->target_flags_explicit;
3320 /* Recreate the arch feature tests if the arch changed */
3321 if (old_arch != ix86_arch)
3323 ix86_arch_mask = 1u << ix86_arch;
3324 for (i = 0; i < X86_ARCH_LAST; ++i)
3325 ix86_arch_features[i]
3326 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3329 /* Recreate the tune optimization tests */
3330 if (old_tune != ix86_tune)
3332 ix86_tune_mask = 1u << ix86_tune;
3333 for (i = 0; i < X86_TUNE_LAST; ++i)
3334 ix86_tune_features[i]
3335 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3339 /* Print the current options */
3342 ix86_function_specific_print (FILE *file, int indent,
3343 struct cl_target_option *ptr)
3346 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3347 NULL, NULL, NULL, false);
3349 fprintf (file, "%*sarch = %d (%s)\n",
3352 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3353 ? cpu_names[ptr->arch]
3356 fprintf (file, "%*stune = %d (%s)\n",
3359 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3360 ? cpu_names[ptr->tune]
3363 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3364 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3365 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3366 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3370 fprintf (file, "%*s%s\n", indent, "", target_string);
3371 free (target_string);
3376 /* Inner function to process the attribute((target(...))), take an argument and
3377 set the current options from the argument. If we have a list, recursively go
3381 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3386 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3387 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3388 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3389 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3404 enum ix86_opt_type type;
3409 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3410 IX86_ATTR_ISA ("abm", OPT_mabm),
3411 IX86_ATTR_ISA ("aes", OPT_maes),
3412 IX86_ATTR_ISA ("avx", OPT_mavx),
3413 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3414 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3415 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3416 IX86_ATTR_ISA ("sse", OPT_msse),
3417 IX86_ATTR_ISA ("sse2", OPT_msse2),
3418 IX86_ATTR_ISA ("sse3", OPT_msse3),
3419 IX86_ATTR_ISA ("sse4", OPT_msse4),
3420 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3421 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3422 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3423 IX86_ATTR_ISA ("sse5", OPT_msse5),
3424 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3426 /* string options */
3427 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3428 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3429 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3432 IX86_ATTR_YES ("cld",
3436 IX86_ATTR_NO ("fancy-math-387",
3437 OPT_mfancy_math_387,
3438 MASK_NO_FANCY_MATH_387),
3440 IX86_ATTR_NO ("fused-madd",
3442 MASK_NO_FUSED_MADD),
3444 IX86_ATTR_YES ("ieee-fp",
3448 IX86_ATTR_YES ("inline-all-stringops",
3449 OPT_minline_all_stringops,
3450 MASK_INLINE_ALL_STRINGOPS),
3452 IX86_ATTR_YES ("inline-stringops-dynamically",
3453 OPT_minline_stringops_dynamically,
3454 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3456 IX86_ATTR_NO ("align-stringops",
3457 OPT_mno_align_stringops,
3458 MASK_NO_ALIGN_STRINGOPS),
3460 IX86_ATTR_YES ("recip",
3466 /* If this is a list, recurse to get the options. */
3467 if (TREE_CODE (args) == TREE_LIST)
3471 for (; args; args = TREE_CHAIN (args))
3472 if (TREE_VALUE (args)
3473 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3479 else if (TREE_CODE (args) != STRING_CST)
3482 /* Handle multiple arguments separated by commas. */
3483 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3485 while (next_optstr && *next_optstr != '\0')
3487 char *p = next_optstr;
3489 char *comma = strchr (next_optstr, ',');
3490 const char *opt_string;
3491 size_t len, opt_len;
3496 enum ix86_opt_type type = ix86_opt_unknown;
3502 len = comma - next_optstr;
3503 next_optstr = comma + 1;
3511 /* Recognize no-xxx. */
3512 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3521 /* Find the option. */
3524 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3526 type = attrs[i].type;
3527 opt_len = attrs[i].len;
3528 if (ch == attrs[i].string[0]
3529 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3530 && memcmp (p, attrs[i].string, opt_len) == 0)
3533 mask = attrs[i].mask;
3534 opt_string = attrs[i].string;
3539 /* Process the option. */
3542 error ("attribute(target(\"%s\")) is unknown", orig_p);
3546 else if (type == ix86_opt_isa)
3547 ix86_handle_option (opt, p, opt_set_p);
3549 else if (type == ix86_opt_yes || type == ix86_opt_no)
3551 if (type == ix86_opt_no)
3552 opt_set_p = !opt_set_p;
3555 target_flags |= mask;
3557 target_flags &= ~mask;
3560 else if (type == ix86_opt_str)
3564 error ("option(\"%s\") was already specified", opt_string);
3568 p_strings[opt] = xstrdup (p + opt_len);
3578 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3581 ix86_valid_target_attribute_tree (tree args)
3583 const char *orig_arch_string = ix86_arch_string;
3584 const char *orig_tune_string = ix86_tune_string;
3585 const char *orig_fpmath_string = ix86_fpmath_string;
3586 int orig_tune_defaulted = ix86_tune_defaulted;
3587 int orig_arch_specified = ix86_arch_specified;
3588 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3591 struct cl_target_option *def
3592 = TREE_TARGET_OPTION (target_option_default_node);
3594 /* Process each of the options on the chain. */
3595 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3598 /* If the changed options are different from the default, rerun override_options,
3599 and then save the options away. The string options are are attribute options,
3600 and will be undone when we copy the save structure. */
3601 if (ix86_isa_flags != def->ix86_isa_flags
3602 || target_flags != def->target_flags
3603 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3604 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3605 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3607 /* If we are using the default tune= or arch=, undo the string assigned,
3608 and use the default. */
3609 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3610 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3611 else if (!orig_arch_specified)
3612 ix86_arch_string = NULL;
3614 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3615 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3616 else if (orig_tune_defaulted)
3617 ix86_tune_string = NULL;
3619 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3620 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3621 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3622 else if (!TARGET_64BIT && TARGET_SSE)
3623 ix86_fpmath_string = "sse,387";
3625 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3626 override_options (false);
3628 /* Add any builtin functions with the new isa if any. */
3629 ix86_add_new_builtins (ix86_isa_flags);
3631 /* Save the current options unless we are validating options for
3633 t = build_target_option_node ();
3635 ix86_arch_string = orig_arch_string;
3636 ix86_tune_string = orig_tune_string;
3637 ix86_fpmath_string = orig_fpmath_string;
3639 /* Free up memory allocated to hold the strings */
3640 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3641 if (option_strings[i])
3642 free (option_strings[i]);
3648 /* Hook to validate attribute((target("string"))). */
3651 ix86_valid_target_attribute_p (tree fndecl,
3652 tree ARG_UNUSED (name),
3654 int ARG_UNUSED (flags))
3656 struct cl_target_option cur_target;
3658 tree old_optimize = build_optimization_node ();
3659 tree new_target, new_optimize;
3660 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3662 /* If the function changed the optimization levels as well as setting target
3663 options, start with the optimizations specified. */
3664 if (func_optimize && func_optimize != old_optimize)
3665 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3667 /* The target attributes may also change some optimization flags, so update
3668 the optimization options if necessary. */
3669 cl_target_option_save (&cur_target);
3670 new_target = ix86_valid_target_attribute_tree (args);
3671 new_optimize = build_optimization_node ();
3678 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3680 if (old_optimize != new_optimize)
3681 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3684 cl_target_option_restore (&cur_target);
3686 if (old_optimize != new_optimize)
3687 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3693 /* Hook to determine if one function can safely inline another. */
3696 ix86_can_inline_p (tree caller, tree callee)
3699 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3700 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3702 /* If callee has no option attributes, then it is ok to inline. */
3706 /* If caller has no option attributes, but callee does then it is not ok to
3708 else if (!caller_tree)
3713 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3714 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3716 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3717 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3719 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3720 != callee_opts->ix86_isa_flags)
3723 /* See if we have the same non-isa options. */
3724 else if (caller_opts->target_flags != callee_opts->target_flags)
3727 /* See if arch, tune, etc. are the same. */
3728 else if (caller_opts->arch != callee_opts->arch)
3731 else if (caller_opts->tune != callee_opts->tune)
3734 else if (caller_opts->fpmath != callee_opts->fpmath)
3737 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3748 /* Remember the last target of ix86_set_current_function. */
3749 static GTY(()) tree ix86_previous_fndecl;
3751 /* Establish appropriate back-end context for processing the function
3752 FNDECL. The argument might be NULL to indicate processing at top
3753 level, outside of any function scope. */
3755 ix86_set_current_function (tree fndecl)
3757 /* Only change the context if the function changes. This hook is called
3758 several times in the course of compiling a function, and we don't want to
3759 slow things down too much or call target_reinit when it isn't safe. */
3760 if (fndecl && fndecl != ix86_previous_fndecl)
3762 tree old_tree = (ix86_previous_fndecl
3763 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3766 tree new_tree = (fndecl
3767 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3770 ix86_previous_fndecl = fndecl;
3771 if (old_tree == new_tree)
3776 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3782 struct cl_target_option *def
3783 = TREE_TARGET_OPTION (target_option_current_node);
3785 cl_target_option_restore (def);
3792 /* Return true if this goes in large data/bss. */
3795 ix86_in_large_data_p (tree exp)
3797 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3800 /* Functions are never large data. */
3801 if (TREE_CODE (exp) == FUNCTION_DECL)
3804 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3806 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3807 if (strcmp (section, ".ldata") == 0
3808 || strcmp (section, ".lbss") == 0)
3814 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3816 /* If this is an incomplete type with size 0, then we can't put it
3817 in data because it might be too big when completed. */
3818 if (!size || size > ix86_section_threshold)
3825 /* Switch to the appropriate section for output of DECL.
3826 DECL is either a `VAR_DECL' node or a constant of some sort.
3827 RELOC indicates whether forming the initial value of DECL requires
3828 link-time relocations. */
3830 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3834 x86_64_elf_select_section (tree decl, int reloc,
3835 unsigned HOST_WIDE_INT align)
3837 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3838 && ix86_in_large_data_p (decl))
3840 const char *sname = NULL;
3841 unsigned int flags = SECTION_WRITE;
3842 switch (categorize_decl_for_section (decl, reloc))
3847 case SECCAT_DATA_REL:
3848 sname = ".ldata.rel";
3850 case SECCAT_DATA_REL_LOCAL:
3851 sname = ".ldata.rel.local";
3853 case SECCAT_DATA_REL_RO:
3854 sname = ".ldata.rel.ro";
3856 case SECCAT_DATA_REL_RO_LOCAL:
3857 sname = ".ldata.rel.ro.local";
3861 flags |= SECTION_BSS;
3864 case SECCAT_RODATA_MERGE_STR:
3865 case SECCAT_RODATA_MERGE_STR_INIT:
3866 case SECCAT_RODATA_MERGE_CONST:
3870 case SECCAT_SRODATA:
3877 /* We don't split these for medium model. Place them into
3878 default sections and hope for best. */
3880 case SECCAT_EMUTLS_VAR:
3881 case SECCAT_EMUTLS_TMPL:
3886 /* We might get called with string constants, but get_named_section
3887 doesn't like them as they are not DECLs. Also, we need to set
3888 flags in that case. */
3890 return get_section (sname, flags, NULL);
3891 return get_named_section (decl, sname, reloc);
3894 return default_elf_select_section (decl, reloc, align);
3897 /* Build up a unique section name, expressed as a
3898 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3899 RELOC indicates whether the initial value of EXP requires
3900 link-time relocations. */
3902 static void ATTRIBUTE_UNUSED
3903 x86_64_elf_unique_section (tree decl, int reloc)
3905 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3906 && ix86_in_large_data_p (decl))
3908 const char *prefix = NULL;
3909 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3910 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3912 switch (categorize_decl_for_section (decl, reloc))
3915 case SECCAT_DATA_REL:
3916 case SECCAT_DATA_REL_LOCAL:
3917 case SECCAT_DATA_REL_RO:
3918 case SECCAT_DATA_REL_RO_LOCAL:
3919 prefix = one_only ? ".ld" : ".ldata";
3922 prefix = one_only ? ".lb" : ".lbss";
3925 case SECCAT_RODATA_MERGE_STR:
3926 case SECCAT_RODATA_MERGE_STR_INIT:
3927 case SECCAT_RODATA_MERGE_CONST:
3928 prefix = one_only ? ".lr" : ".lrodata";
3930 case SECCAT_SRODATA:
3937 /* We don't split these for medium model. Place them into
3938 default sections and hope for best. */
3940 case SECCAT_EMUTLS_VAR:
3941 prefix = targetm.emutls.var_section;
3943 case SECCAT_EMUTLS_TMPL:
3944 prefix = targetm.emutls.tmpl_section;
3949 const char *name, *linkonce;
3952 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3953 name = targetm.strip_name_encoding (name);
3955 /* If we're using one_only, then there needs to be a .gnu.linkonce
3956 prefix to the section name. */
3957 linkonce = one_only ? ".gnu.linkonce" : "";
3959 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3961 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3965 default_unique_section (decl, reloc);
3968 #ifdef COMMON_ASM_OP
3969 /* This says how to output assembler code to declare an
3970 uninitialized external linkage data object.
3972 For medium model x86-64 we need to use .largecomm opcode for
3975 x86_elf_aligned_common (FILE *file,
3976 const char *name, unsigned HOST_WIDE_INT size,
3979 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3980 && size > (unsigned int)ix86_section_threshold)
3981 fprintf (file, ".largecomm\t");
3983 fprintf (file, "%s", COMMON_ASM_OP);
3984 assemble_name (file, name);
3985 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3986 size, align / BITS_PER_UNIT);
3990 /* Utility function for targets to use in implementing
3991 ASM_OUTPUT_ALIGNED_BSS. */
3994 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3995 const char *name, unsigned HOST_WIDE_INT size,
3998 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3999 && size > (unsigned int)ix86_section_threshold)
4000 switch_to_section (get_named_section (decl, ".lbss", 0));
4002 switch_to_section (bss_section);
4003 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4004 #ifdef ASM_DECLARE_OBJECT_NAME
4005 last_assemble_variable_decl = decl;
4006 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4008 /* Standard thing is just output label for the object. */
4009 ASM_OUTPUT_LABEL (file, name);
4010 #endif /* ASM_DECLARE_OBJECT_NAME */
4011 ASM_OUTPUT_SKIP (file, size ? size : 1);
4015 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4017 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4018 make the problem with not enough registers even worse. */
4019 #ifdef INSN_SCHEDULING
4021 flag_schedule_insns = 0;
4025 /* The Darwin libraries never set errno, so we might as well
4026 avoid calling them when that's the only reason we would. */
4027 flag_errno_math = 0;
4029 /* The default values of these switches depend on the TARGET_64BIT
4030 that is not known at this moment. Mark these values with 2 and
4031 let user the to override these. In case there is no command line option
4032 specifying them, we will set the defaults in override_options. */
4034 flag_omit_frame_pointer = 2;
4035 flag_pcc_struct_return = 2;
4036 flag_asynchronous_unwind_tables = 2;
4037 flag_vect_cost_model = 1;
4038 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4039 SUBTARGET_OPTIMIZATION_OPTIONS;
4043 /* Decide whether we can make a sibling call to a function. DECL is the
4044 declaration of the function being targeted by the call and EXP is the
4045 CALL_EXPR representing the call. */
4048 ix86_function_ok_for_sibcall (tree decl, tree exp)
4053 /* If we are generating position-independent code, we cannot sibcall
4054 optimize any indirect call, or a direct call to a global function,
4055 as the PLT requires %ebx be live. */
4056 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4063 func = TREE_TYPE (CALL_EXPR_FN (exp));
4064 if (POINTER_TYPE_P (func))
4065 func = TREE_TYPE (func);
4068 /* Check that the return value locations are the same. Like
4069 if we are returning floats on the 80387 register stack, we cannot
4070 make a sibcall from a function that doesn't return a float to a
4071 function that does or, conversely, from a function that does return
4072 a float to a function that doesn't; the necessary stack adjustment
4073 would not be executed. This is also the place we notice
4074 differences in the return value ABI. Note that it is ok for one
4075 of the functions to have void return type as long as the return
4076 value of the other is passed in a register. */
4077 a = ix86_function_value (TREE_TYPE (exp), func, false);
4078 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4080 if (STACK_REG_P (a) || STACK_REG_P (b))
4082 if (!rtx_equal_p (a, b))
4085 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4087 else if (!rtx_equal_p (a, b))
4090 /* If this call is indirect, we'll need to be able to use a call-clobbered
4091 register for the address of the target function. Make sure that all
4092 such registers are not used for passing parameters. */
4093 if (!decl && !TARGET_64BIT)
4097 /* We're looking at the CALL_EXPR, we need the type of the function. */
4098 type = CALL_EXPR_FN (exp); /* pointer expression */
4099 type = TREE_TYPE (type); /* pointer type */
4100 type = TREE_TYPE (type); /* function type */
4102 if (ix86_function_regparm (type, NULL) >= 3)
4104 /* ??? Need to count the actual number of registers to be used,
4105 not the possible number of registers. Fix later. */
4110 /* Dllimport'd functions are also called indirectly. */
4111 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4113 && decl && DECL_DLLIMPORT_P (decl)
4114 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4117 /* If we need to align the outgoing stack, then sibcalling would
4118 unalign the stack, which may break the called function. */
4119 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4122 /* Otherwise okay. That also includes certain types of indirect calls. */
4126 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4127 calling convention attributes;
4128 arguments as in struct attribute_spec.handler. */
4131 ix86_handle_cconv_attribute (tree *node, tree name,
4133 int flags ATTRIBUTE_UNUSED,
4136 if (TREE_CODE (*node) != FUNCTION_TYPE
4137 && TREE_CODE (*node) != METHOD_TYPE
4138 && TREE_CODE (*node) != FIELD_DECL
4139 && TREE_CODE (*node) != TYPE_DECL)
4141 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4142 IDENTIFIER_POINTER (name));
4143 *no_add_attrs = true;
4147 /* Can combine regparm with all attributes but fastcall. */
4148 if (is_attribute_p ("regparm", name))
4152 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4154 error ("fastcall and regparm attributes are not compatible");
4157 cst = TREE_VALUE (args);
4158 if (TREE_CODE (cst) != INTEGER_CST)
4160 warning (OPT_Wattributes,
4161 "%qs attribute requires an integer constant argument",
4162 IDENTIFIER_POINTER (name));
4163 *no_add_attrs = true;
4165 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4167 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4168 IDENTIFIER_POINTER (name), REGPARM_MAX);
4169 *no_add_attrs = true;
4177 /* Do not warn when emulating the MS ABI. */
4178 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4179 warning (OPT_Wattributes, "%qs attribute ignored",
4180 IDENTIFIER_POINTER (name));
4181 *no_add_attrs = true;
4185 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4186 if (is_attribute_p ("fastcall", name))
4188 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4190 error ("fastcall and cdecl attributes are not compatible");
4192 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4194 error ("fastcall and stdcall attributes are not compatible");
4196 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4198 error ("fastcall and regparm attributes are not compatible");
4202 /* Can combine stdcall with fastcall (redundant), regparm and
4204 else if (is_attribute_p ("stdcall", name))
4206 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4208 error ("stdcall and cdecl attributes are not compatible");
4210 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4212 error ("stdcall and fastcall attributes are not compatible");
4216 /* Can combine cdecl with regparm and sseregparm. */
4217 else if (is_attribute_p ("cdecl", name))
4219 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4221 error ("stdcall and cdecl attributes are not compatible");
4223 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4225 error ("fastcall and cdecl attributes are not compatible");
4229 /* Can combine sseregparm with all attributes. */
4234 /* Return 0 if the attributes for two types are incompatible, 1 if they
4235 are compatible, and 2 if they are nearly compatible (which causes a
4236 warning to be generated). */
4239 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4241 /* Check for mismatch of non-default calling convention. */
4242 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4244 if (TREE_CODE (type1) != FUNCTION_TYPE
4245 && TREE_CODE (type1) != METHOD_TYPE)
4248 /* Check for mismatched fastcall/regparm types. */
4249 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4250 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4251 || (ix86_function_regparm (type1, NULL)
4252 != ix86_function_regparm (type2, NULL)))
4255 /* Check for mismatched sseregparm types. */
4256 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4257 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4260 /* Check for mismatched return types (cdecl vs stdcall). */
4261 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4262 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4268 /* Return the regparm value for a function with the indicated TYPE and DECL.
4269 DECL may be NULL when calling function indirectly
4270 or considering a libcall. */
4273 ix86_function_regparm (const_tree type, const_tree decl)
4276 int regparm = ix86_regparm;
4278 static bool error_issued;
4282 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4284 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4287 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4291 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4293 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4295 /* We can't use regparm(3) for nested functions because
4296 these pass static chain pointer in %ecx register. */
4297 if (!error_issued && regparm == 3
4298 && decl_function_context (decl)
4299 && !DECL_NO_STATIC_CHAIN (decl))
4301 error ("nested functions are limited to 2 register parameters");
4302 error_issued = true;
4310 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4313 /* Use register calling convention for local functions when possible. */
4314 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4317 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4318 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4321 int local_regparm, globals = 0, regno;
4324 /* Make sure no regparm register is taken by a
4325 fixed register variable. */
4326 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4327 if (fixed_regs[local_regparm])
4330 /* We can't use regparm(3) for nested functions as these use
4331 static chain pointer in third argument. */
4332 if (local_regparm == 3
4333 && decl_function_context (decl)
4334 && !DECL_NO_STATIC_CHAIN (decl))
4337 /* If the function realigns its stackpointer, the prologue will
4338 clobber %ecx. If we've already generated code for the callee,
4339 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4340 scanning the attributes for the self-realigning property. */
4341 f = DECL_STRUCT_FUNCTION (decl);
4342 /* Since current internal arg pointer won't conflict with
4343 parameter passing regs, so no need to change stack
4344 realignment and adjust regparm number.
4346 Each fixed register usage increases register pressure,
4347 so less registers should be used for argument passing.
4348 This functionality can be overriden by an explicit
4350 for (regno = 0; regno <= DI_REG; regno++)
4351 if (fixed_regs[regno])
4355 = globals < local_regparm ? local_regparm - globals : 0;
4357 if (local_regparm > regparm)
4358 regparm = local_regparm;
4365 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4366 DFmode (2) arguments in SSE registers for a function with the
4367 indicated TYPE and DECL. DECL may be NULL when calling function
4368 indirectly or considering a libcall. Otherwise return 0. */
4371 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4373 gcc_assert (!TARGET_64BIT);
4375 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4376 by the sseregparm attribute. */
4377 if (TARGET_SSEREGPARM
4378 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4385 error ("Calling %qD with attribute sseregparm without "
4386 "SSE/SSE2 enabled", decl);
4388 error ("Calling %qT with attribute sseregparm without "
4389 "SSE/SSE2 enabled", type);
4397 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4398 (and DFmode for SSE2) arguments in SSE registers. */
4399 if (decl && TARGET_SSE_MATH && !profile_flag)
4401 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4402 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4404 return TARGET_SSE2 ? 2 : 1;
4410 /* Return true if EAX is live at the start of the function. Used by
4411 ix86_expand_prologue to determine if we need special help before
4412 calling allocate_stack_worker. */
4415 ix86_eax_live_at_start_p (void)
4417 /* Cheat. Don't bother working forward from ix86_function_regparm
4418 to the function type to whether an actual argument is located in
4419 eax. Instead just look at cfg info, which is still close enough
4420 to correct at this point. This gives false positives for broken
4421 functions that might use uninitialized data that happens to be
4422 allocated in eax, but who cares? */
4423 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4426 /* Value is the number of bytes of arguments automatically
4427 popped when returning from a subroutine call.
4428 FUNDECL is the declaration node of the function (as a tree),
4429 FUNTYPE is the data type of the function (as a tree),
4430 or for a library call it is an identifier node for the subroutine name.
4431 SIZE is the number of bytes of arguments passed on the stack.
4433 On the 80386, the RTD insn may be used to pop them if the number
4434 of args is fixed, but if the number is variable then the caller
4435 must pop them all. RTD can't be used for library calls now
4436 because the library is compiled with the Unix compiler.
4437 Use of RTD is a selectable option, since it is incompatible with
4438 standard Unix calling sequences. If the option is not selected,
4439 the caller must always pop the args.
4441 The attribute stdcall is equivalent to RTD on a per module basis. */
4444 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4448 /* None of the 64-bit ABIs pop arguments. */
4452 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4454 /* Cdecl functions override -mrtd, and never pop the stack. */
4455 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4457 /* Stdcall and fastcall functions will pop the stack if not
4459 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4460 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4463 if (rtd && ! stdarg_p (funtype))
4467 /* Lose any fake structure return argument if it is passed on the stack. */
4468 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4469 && !KEEP_AGGREGATE_RETURN_POINTER)
4471 int nregs = ix86_function_regparm (funtype, fundecl);
4473 return GET_MODE_SIZE (Pmode);
4479 /* Argument support functions. */
4481 /* Return true when register may be used to pass function parameters. */
4483 ix86_function_arg_regno_p (int regno)
4486 const int *parm_regs;
4491 return (regno < REGPARM_MAX
4492 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4494 return (regno < REGPARM_MAX
4495 || (TARGET_MMX && MMX_REGNO_P (regno)
4496 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4497 || (TARGET_SSE && SSE_REGNO_P (regno)
4498 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4503 if (SSE_REGNO_P (regno) && TARGET_SSE)
4508 if (TARGET_SSE && SSE_REGNO_P (regno)
4509 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4513 /* TODO: The function should depend on current function ABI but
4514 builtins.c would need updating then. Therefore we use the
4517 /* RAX is used as hidden argument to va_arg functions. */
4518 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4521 if (DEFAULT_ABI == MS_ABI)
4522 parm_regs = x86_64_ms_abi_int_parameter_registers;
4524 parm_regs = x86_64_int_parameter_registers;
4525 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4526 : X86_64_REGPARM_MAX); i++)
4527 if (regno == parm_regs[i])
4532 /* Return if we do not know how to pass TYPE solely in registers. */
4535 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4537 if (must_pass_in_stack_var_size_or_pad (mode, type))
4540 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4541 The layout_type routine is crafty and tries to trick us into passing
4542 currently unsupported vector types on the stack by using TImode. */
4543 return (!TARGET_64BIT && mode == TImode
4544 && type && TREE_CODE (type) != VECTOR_TYPE);
4547 /* It returns the size, in bytes, of the area reserved for arguments passed
4548 in registers for the function represented by fndecl dependent to the used
4551 ix86_reg_parm_stack_space (const_tree fndecl)
4553 int call_abi = SYSV_ABI;
4554 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4555 call_abi = ix86_function_abi (fndecl);
4557 call_abi = ix86_function_type_abi (fndecl);
4558 if (call_abi == MS_ABI)
4563 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4566 ix86_function_type_abi (const_tree fntype)
4568 if (TARGET_64BIT && fntype != NULL)
4571 if (DEFAULT_ABI == SYSV_ABI)
4572 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4574 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4582 ix86_function_abi (const_tree fndecl)
4586 return ix86_function_type_abi (TREE_TYPE (fndecl));
4589 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4592 ix86_cfun_abi (void)
4594 if (! cfun || ! TARGET_64BIT)
4596 return cfun->machine->call_abi;
4600 extern void init_regs (void);
4602 /* Implementation of call abi switching target hook. Specific to FNDECL
4603 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4604 for more details. */
4606 ix86_call_abi_override (const_tree fndecl)
4608 if (fndecl == NULL_TREE)
4609 cfun->machine->call_abi = DEFAULT_ABI;
4611 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4614 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4615 re-initialization of init_regs each time we switch function context since
4616 this is needed only during RTL expansion. */
4618 ix86_maybe_switch_abi (void)
4621 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4625 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4626 for a call to a function whose data type is FNTYPE.
4627 For a library call, FNTYPE is 0. */
4630 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4631 tree fntype, /* tree ptr for function decl */
4632 rtx libname, /* SYMBOL_REF of library name or 0 */
4635 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4636 memset (cum, 0, sizeof (*cum));
4639 cum->call_abi = ix86_function_abi (fndecl);
4641 cum->call_abi = ix86_function_type_abi (fntype);
4642 /* Set up the number of registers to use for passing arguments. */
4644 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4645 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4646 cum->nregs = ix86_regparm;
4649 if (cum->call_abi != DEFAULT_ABI)
4650 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4655 cum->sse_nregs = SSE_REGPARM_MAX;
4658 if (cum->call_abi != DEFAULT_ABI)
4659 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4660 : X64_SSE_REGPARM_MAX;
4664 cum->mmx_nregs = MMX_REGPARM_MAX;
4665 cum->warn_avx = true;
4666 cum->warn_sse = true;
4667 cum->warn_mmx = true;
4669 /* Because type might mismatch in between caller and callee, we need to
4670 use actual type of function for local calls.
4671 FIXME: cgraph_analyze can be told to actually record if function uses
4672 va_start so for local functions maybe_vaarg can be made aggressive
4674 FIXME: once typesytem is fixed, we won't need this code anymore. */
4676 fntype = TREE_TYPE (fndecl);
4677 cum->maybe_vaarg = (fntype
4678 ? (!prototype_p (fntype) || stdarg_p (fntype))
4683 /* If there are variable arguments, then we won't pass anything
4684 in registers in 32-bit mode. */
4685 if (stdarg_p (fntype))
4696 /* Use ecx and edx registers if function has fastcall attribute,
4697 else look for regparm information. */
4700 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4706 cum->nregs = ix86_function_regparm (fntype, fndecl);
4709 /* Set up the number of SSE registers used for passing SFmode
4710 and DFmode arguments. Warn for mismatching ABI. */
4711 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4715 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4716 But in the case of vector types, it is some vector mode.
4718 When we have only some of our vector isa extensions enabled, then there
4719 are some modes for which vector_mode_supported_p is false. For these
4720 modes, the generic vector support in gcc will choose some non-vector mode
4721 in order to implement the type. By computing the natural mode, we'll
4722 select the proper ABI location for the operand and not depend on whatever
4723 the middle-end decides to do with these vector types.
4725 The midde-end can't deal with the vector types > 16 bytes. In this
4726 case, we return the original mode and warn ABI change if CUM isn't
4729 static enum machine_mode
4730 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4732 enum machine_mode mode = TYPE_MODE (type);
4734 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4736 HOST_WIDE_INT size = int_size_in_bytes (type);
4737 if ((size == 8 || size == 16 || size == 32)
4738 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4739 && TYPE_VECTOR_SUBPARTS (type) > 1)
4741 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4743 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4744 mode = MIN_MODE_VECTOR_FLOAT;
4746 mode = MIN_MODE_VECTOR_INT;
4748 /* Get the mode which has this inner mode and number of units. */
4749 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4750 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4751 && GET_MODE_INNER (mode) == innermode)
4753 if (size == 32 && !TARGET_AVX)
4755 static bool warnedavx;
4762 warning (0, "AVX vector argument without AVX "
4763 "enabled changes the ABI");
4765 return TYPE_MODE (type);
4778 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4779 this may not agree with the mode that the type system has chosen for the
4780 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4781 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4784 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4789 if (orig_mode != BLKmode)
4790 tmp = gen_rtx_REG (orig_mode, regno);
4793 tmp = gen_rtx_REG (mode, regno);
4794 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4795 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4801 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4802 of this code is to classify each 8bytes of incoming argument by the register
4803 class and assign registers accordingly. */
4805 /* Return the union class of CLASS1 and CLASS2.
4806 See the x86-64 PS ABI for details. */
4808 static enum x86_64_reg_class
4809 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4811 /* Rule #1: If both classes are equal, this is the resulting class. */
4812 if (class1 == class2)
4815 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4817 if (class1 == X86_64_NO_CLASS)
4819 if (class2 == X86_64_NO_CLASS)
4822 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4823 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4824 return X86_64_MEMORY_CLASS;
4826 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4827 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4828 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4829 return X86_64_INTEGERSI_CLASS;
4830 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4831 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4832 return X86_64_INTEGER_CLASS;
4834 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4836 if (class1 == X86_64_X87_CLASS
4837 || class1 == X86_64_X87UP_CLASS
4838 || class1 == X86_64_COMPLEX_X87_CLASS
4839 || class2 == X86_64_X87_CLASS
4840 || class2 == X86_64_X87UP_CLASS
4841 || class2 == X86_64_COMPLEX_X87_CLASS)
4842 return X86_64_MEMORY_CLASS;
4844 /* Rule #6: Otherwise class SSE is used. */
4845 return X86_64_SSE_CLASS;
4848 /* Classify the argument of type TYPE and mode MODE.
4849 CLASSES will be filled by the register class used to pass each word
4850 of the operand. The number of words is returned. In case the parameter
4851 should be passed in memory, 0 is returned. As a special case for zero
4852 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4854 BIT_OFFSET is used internally for handling records and specifies offset
4855 of the offset in bits modulo 256 to avoid overflow cases.
4857 See the x86-64 PS ABI for details.
4861 classify_argument (enum machine_mode mode, const_tree type,
4862 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4864 HOST_WIDE_INT bytes =
4865 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4866 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4868 /* Variable sized entities are always passed/returned in memory. */
4872 if (mode != VOIDmode
4873 && targetm.calls.must_pass_in_stack (mode, type))
4876 if (type && AGGREGATE_TYPE_P (type))
4880 enum x86_64_reg_class subclasses[MAX_CLASSES];
4882 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4886 for (i = 0; i < words; i++)
4887 classes[i] = X86_64_NO_CLASS;
4889 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4890 signalize memory class, so handle it as special case. */
4893 classes[0] = X86_64_NO_CLASS;
4897 /* Classify each field of record and merge classes. */
4898 switch (TREE_CODE (type))
4901 /* And now merge the fields of structure. */
4902 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4904 if (TREE_CODE (field) == FIELD_DECL)
4908 if (TREE_TYPE (field) == error_mark_node)
4911 /* Bitfields are always classified as integer. Handle them
4912 early, since later code would consider them to be
4913 misaligned integers. */
4914 if (DECL_BIT_FIELD (field))
4916 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4917 i < ((int_bit_position (field) + (bit_offset % 64))
4918 + tree_low_cst (DECL_SIZE (field), 0)
4921 merge_classes (X86_64_INTEGER_CLASS,
4926 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4927 TREE_TYPE (field), subclasses,
4928 (int_bit_position (field)
4929 + bit_offset) % 256);
4932 for (i = 0; i < num; i++)
4935 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4937 merge_classes (subclasses[i], classes[i + pos]);
4945 /* Arrays are handled as small records. */
4948 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4949 TREE_TYPE (type), subclasses, bit_offset);
4953 /* The partial classes are now full classes. */
4954 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4955 subclasses[0] = X86_64_SSE_CLASS;
4956 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4957 && !((bit_offset % 64) == 0 && bytes == 4))
4958 subclasses[0] = X86_64_INTEGER_CLASS;
4960 for (i = 0; i < words; i++)
4961 classes[i] = subclasses[i % num];
4966 case QUAL_UNION_TYPE:
4967 /* Unions are similar to RECORD_TYPE but offset is always 0.
4969 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4971 if (TREE_CODE (field) == FIELD_DECL)
4975 if (TREE_TYPE (field) == error_mark_node)
4978 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4979 TREE_TYPE (field), subclasses,
4983 for (i = 0; i < num; i++)
4984 classes[i] = merge_classes (subclasses[i], classes[i]);
4995 /* When size > 16 bytes, if the first one isn't
4996 X86_64_SSE_CLASS or any other ones aren't
4997 X86_64_SSEUP_CLASS, everything should be passed in
4999 if (classes[0] != X86_64_SSE_CLASS)
5002 for (i = 1; i < words; i++)
5003 if (classes[i] != X86_64_SSEUP_CLASS)
5007 /* Final merger cleanup. */
5008 for (i = 0; i < words; i++)
5010 /* If one class is MEMORY, everything should be passed in
5012 if (classes[i] == X86_64_MEMORY_CLASS)
5015 /* The X86_64_SSEUP_CLASS should be always preceded by
5016 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5017 if (classes[i] == X86_64_SSEUP_CLASS
5018 && classes[i - 1] != X86_64_SSE_CLASS
5019 && classes[i - 1] != X86_64_SSEUP_CLASS)
5021 /* The first one should never be X86_64_SSEUP_CLASS. */
5022 gcc_assert (i != 0);
5023 classes[i] = X86_64_SSE_CLASS;
5026 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5027 everything should be passed in memory. */
5028 if (classes[i] == X86_64_X87UP_CLASS
5029 && (classes[i - 1] != X86_64_X87_CLASS))
5033 /* The first one should never be X86_64_X87UP_CLASS. */
5034 gcc_assert (i != 0);
5035 if (!warned && warn_psabi)
5038 inform (input_location,
5039 "The ABI of passing union with long double"
5040 " has changed in GCC 4.4");
5048 /* Compute alignment needed. We align all types to natural boundaries with
5049 exception of XFmode that is aligned to 64bits. */
5050 if (mode != VOIDmode && mode != BLKmode)
5052 int mode_alignment = GET_MODE_BITSIZE (mode);
5055 mode_alignment = 128;
5056 else if (mode == XCmode)
5057 mode_alignment = 256;
5058 if (COMPLEX_MODE_P (mode))
5059 mode_alignment /= 2;
5060 /* Misaligned fields are always returned in memory. */
5061 if (bit_offset % mode_alignment)
5065 /* for V1xx modes, just use the base mode */
5066 if (VECTOR_MODE_P (mode) && mode != V1DImode
5067 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5068 mode = GET_MODE_INNER (mode);
5070 /* Classification of atomic types. */
5075 classes[0] = X86_64_SSE_CLASS;
5078 classes[0] = X86_64_SSE_CLASS;
5079 classes[1] = X86_64_SSEUP_CLASS;
5089 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5093 classes[0] = X86_64_INTEGERSI_CLASS;
5096 else if (size <= 64)
5098 classes[0] = X86_64_INTEGER_CLASS;
5101 else if (size <= 64+32)
5103 classes[0] = X86_64_INTEGER_CLASS;
5104 classes[1] = X86_64_INTEGERSI_CLASS;
5107 else if (size <= 64+64)
5109 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5117 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5121 /* OImode shouldn't be used directly. */
5126 if (!(bit_offset % 64))
5127 classes[0] = X86_64_SSESF_CLASS;
5129 classes[0] = X86_64_SSE_CLASS;
5132 classes[0] = X86_64_SSEDF_CLASS;
5135 classes[0] = X86_64_X87_CLASS;
5136 classes[1] = X86_64_X87UP_CLASS;
5139 classes[0] = X86_64_SSE_CLASS;
5140 classes[1] = X86_64_SSEUP_CLASS;
5143 classes[0] = X86_64_SSE_CLASS;
5146 classes[0] = X86_64_SSEDF_CLASS;
5147 classes[1] = X86_64_SSEDF_CLASS;
5150 classes[0] = X86_64_COMPLEX_X87_CLASS;
5153 /* This modes is larger than 16 bytes. */
5161 classes[0] = X86_64_SSE_CLASS;
5162 classes[1] = X86_64_SSEUP_CLASS;
5163 classes[2] = X86_64_SSEUP_CLASS;
5164 classes[3] = X86_64_SSEUP_CLASS;
5172 classes[0] = X86_64_SSE_CLASS;
5173 classes[1] = X86_64_SSEUP_CLASS;
5180 classes[0] = X86_64_SSE_CLASS;
5186 gcc_assert (VECTOR_MODE_P (mode));
5191 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5193 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5194 classes[0] = X86_64_INTEGERSI_CLASS;
5196 classes[0] = X86_64_INTEGER_CLASS;
5197 classes[1] = X86_64_INTEGER_CLASS;
5198 return 1 + (bytes > 8);
5202 /* Examine the argument and return set number of register required in each
5203 class. Return 0 iff parameter should be passed in memory. */
5205 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5206 int *int_nregs, int *sse_nregs)
5208 enum x86_64_reg_class regclass[MAX_CLASSES];
5209 int n = classify_argument (mode, type, regclass, 0);
5215 for (n--; n >= 0; n--)
5216 switch (regclass[n])
5218 case X86_64_INTEGER_CLASS:
5219 case X86_64_INTEGERSI_CLASS:
5222 case X86_64_SSE_CLASS:
5223 case X86_64_SSESF_CLASS:
5224 case X86_64_SSEDF_CLASS:
5227 case X86_64_NO_CLASS:
5228 case X86_64_SSEUP_CLASS:
5230 case X86_64_X87_CLASS:
5231 case X86_64_X87UP_CLASS:
5235 case X86_64_COMPLEX_X87_CLASS:
5236 return in_return ? 2 : 0;
5237 case X86_64_MEMORY_CLASS:
5243 /* Construct container for the argument used by GCC interface. See
5244 FUNCTION_ARG for the detailed description. */
5247 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5248 const_tree type, int in_return, int nintregs, int nsseregs,
5249 const int *intreg, int sse_regno)
5251 /* The following variables hold the static issued_error state. */
5252 static bool issued_sse_arg_error;
5253 static bool issued_sse_ret_error;
5254 static bool issued_x87_ret_error;
5256 enum machine_mode tmpmode;
5258 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5259 enum x86_64_reg_class regclass[MAX_CLASSES];
5263 int needed_sseregs, needed_intregs;
5264 rtx exp[MAX_CLASSES];
5267 n = classify_argument (mode, type, regclass, 0);
5270 if (!examine_argument (mode, type, in_return, &needed_intregs,
5273 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5276 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5277 some less clueful developer tries to use floating-point anyway. */
5278 if (needed_sseregs && !TARGET_SSE)
5282 if (!issued_sse_ret_error)
5284 error ("SSE register return with SSE disabled");
5285 issued_sse_ret_error = true;
5288 else if (!issued_sse_arg_error)
5290 error ("SSE register argument with SSE disabled");
5291 issued_sse_arg_error = true;
5296 /* Likewise, error if the ABI requires us to return values in the
5297 x87 registers and the user specified -mno-80387. */
5298 if (!TARGET_80387 && in_return)
5299 for (i = 0; i < n; i++)
5300 if (regclass[i] == X86_64_X87_CLASS
5301 || regclass[i] == X86_64_X87UP_CLASS
5302 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5304 if (!issued_x87_ret_error)
5306 error ("x87 register return with x87 disabled");
5307 issued_x87_ret_error = true;
5312 /* First construct simple cases. Avoid SCmode, since we want to use
5313 single register to pass this type. */
5314 if (n == 1 && mode != SCmode)
5315 switch (regclass[0])
5317 case X86_64_INTEGER_CLASS:
5318 case X86_64_INTEGERSI_CLASS:
5319 return gen_rtx_REG (mode, intreg[0]);
5320 case X86_64_SSE_CLASS:
5321 case X86_64_SSESF_CLASS:
5322 case X86_64_SSEDF_CLASS:
5323 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5324 case X86_64_X87_CLASS:
5325 case X86_64_COMPLEX_X87_CLASS:
5326 return gen_rtx_REG (mode, FIRST_STACK_REG);
5327 case X86_64_NO_CLASS:
5328 /* Zero sized array, struct or class. */
5333 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5334 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5335 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5337 && regclass[0] == X86_64_SSE_CLASS
5338 && regclass[1] == X86_64_SSEUP_CLASS
5339 && regclass[2] == X86_64_SSEUP_CLASS
5340 && regclass[3] == X86_64_SSEUP_CLASS
5342 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5345 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5346 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5347 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5348 && regclass[1] == X86_64_INTEGER_CLASS
5349 && (mode == CDImode || mode == TImode || mode == TFmode)
5350 && intreg[0] + 1 == intreg[1])
5351 return gen_rtx_REG (mode, intreg[0]);
5353 /* Otherwise figure out the entries of the PARALLEL. */
5354 for (i = 0; i < n; i++)
5358 switch (regclass[i])
5360 case X86_64_NO_CLASS:
5362 case X86_64_INTEGER_CLASS:
5363 case X86_64_INTEGERSI_CLASS:
5364 /* Merge TImodes on aligned occasions here too. */
5365 if (i * 8 + 8 > bytes)
5366 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5367 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5371 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5372 if (tmpmode == BLKmode)
5374 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5375 gen_rtx_REG (tmpmode, *intreg),
5379 case X86_64_SSESF_CLASS:
5380 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5381 gen_rtx_REG (SFmode,
5382 SSE_REGNO (sse_regno)),
5386 case X86_64_SSEDF_CLASS:
5387 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5388 gen_rtx_REG (DFmode,
5389 SSE_REGNO (sse_regno)),
5393 case X86_64_SSE_CLASS:
5401 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5411 && regclass[1] == X86_64_SSEUP_CLASS
5412 && regclass[2] == X86_64_SSEUP_CLASS
5413 && regclass[3] == X86_64_SSEUP_CLASS);
5420 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5421 gen_rtx_REG (tmpmode,
5422 SSE_REGNO (sse_regno)),
5431 /* Empty aligned struct, union or class. */
5435 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5436 for (i = 0; i < nexps; i++)
5437 XVECEXP (ret, 0, i) = exp [i];
5441 /* Update the data in CUM to advance over an argument of mode MODE
5442 and data type TYPE. (TYPE is null for libcalls where that information
5443 may not be available.) */
5446 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5447 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5463 cum->words += words;
5464 cum->nregs -= words;
5465 cum->regno += words;
5467 if (cum->nregs <= 0)
5475 /* OImode shouldn't be used directly. */
5479 if (cum->float_in_sse < 2)
5482 if (cum->float_in_sse < 1)
5499 if (!type || !AGGREGATE_TYPE_P (type))
5501 cum->sse_words += words;
5502 cum->sse_nregs -= 1;
5503 cum->sse_regno += 1;
5504 if (cum->sse_nregs <= 0)
5517 if (!type || !AGGREGATE_TYPE_P (type))
5519 cum->mmx_words += words;
5520 cum->mmx_nregs -= 1;
5521 cum->mmx_regno += 1;
5522 if (cum->mmx_nregs <= 0)
5533 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5534 tree type, HOST_WIDE_INT words, int named)
5536 int int_nregs, sse_nregs;
5538 /* Unnamed 256bit vector mode parameters are passed on stack. */
5539 if (!named && VALID_AVX256_REG_MODE (mode))
5542 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5543 cum->words += words;
5544 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5546 cum->nregs -= int_nregs;
5547 cum->sse_nregs -= sse_nregs;
5548 cum->regno += int_nregs;
5549 cum->sse_regno += sse_nregs;
5552 cum->words += words;
5556 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5557 HOST_WIDE_INT words)
5559 /* Otherwise, this should be passed indirect. */
5560 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5562 cum->words += words;
5571 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5572 tree type, int named)
5574 HOST_WIDE_INT bytes, words;
5576 if (mode == BLKmode)
5577 bytes = int_size_in_bytes (type);
5579 bytes = GET_MODE_SIZE (mode);
5580 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5583 mode = type_natural_mode (type, NULL);
5585 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5586 function_arg_advance_ms_64 (cum, bytes, words);
5587 else if (TARGET_64BIT)
5588 function_arg_advance_64 (cum, mode, type, words, named);
5590 function_arg_advance_32 (cum, mode, type, bytes, words);
5593 /* Define where to put the arguments to a function.
5594 Value is zero to push the argument on the stack,
5595 or a hard register in which to store the argument.
5597 MODE is the argument's machine mode.
5598 TYPE is the data type of the argument (as a tree).
5599 This is null for libcalls where that information may
5601 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5602 the preceding args and about the function being called.
5603 NAMED is nonzero if this argument is a named parameter
5604 (otherwise it is an extra parameter matching an ellipsis). */
5607 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5608 enum machine_mode orig_mode, tree type,
5609 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5611 static bool warnedsse, warnedmmx;
5613 /* Avoid the AL settings for the Unix64 ABI. */
5614 if (mode == VOIDmode)
5630 if (words <= cum->nregs)
5632 int regno = cum->regno;
5634 /* Fastcall allocates the first two DWORD (SImode) or
5635 smaller arguments to ECX and EDX if it isn't an
5641 || (type && AGGREGATE_TYPE_P (type)))
5644 /* ECX not EAX is the first allocated register. */
5645 if (regno == AX_REG)
5648 return gen_rtx_REG (mode, regno);
5653 if (cum->float_in_sse < 2)
5656 if (cum->float_in_sse < 1)
5660 /* In 32bit, we pass TImode in xmm registers. */
5667 if (!type || !AGGREGATE_TYPE_P (type))
5669 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5672 warning (0, "SSE vector argument without SSE enabled "
5676 return gen_reg_or_parallel (mode, orig_mode,
5677 cum->sse_regno + FIRST_SSE_REG);
5682 /* OImode shouldn't be used directly. */
5691 if (!type || !AGGREGATE_TYPE_P (type))
5694 return gen_reg_or_parallel (mode, orig_mode,
5695 cum->sse_regno + FIRST_SSE_REG);
5704 if (!type || !AGGREGATE_TYPE_P (type))
5706 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5709 warning (0, "MMX vector argument without MMX enabled "
5713 return gen_reg_or_parallel (mode, orig_mode,
5714 cum->mmx_regno + FIRST_MMX_REG);
5723 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5724 enum machine_mode orig_mode, tree type, int named)
5726 /* Handle a hidden AL argument containing number of registers
5727 for varargs x86-64 functions. */
5728 if (mode == VOIDmode)
5729 return GEN_INT (cum->maybe_vaarg
5730 ? (cum->sse_nregs < 0
5731 ? (cum->call_abi == DEFAULT_ABI
5733 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5734 : X64_SSE_REGPARM_MAX))
5749 /* Unnamed 256bit vector mode parameters are passed on stack. */
5755 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5757 &x86_64_int_parameter_registers [cum->regno],
5762 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5763 enum machine_mode orig_mode, int named,
5764 HOST_WIDE_INT bytes)
5768 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5769 We use value of -2 to specify that current function call is MSABI. */
5770 if (mode == VOIDmode)
5771 return GEN_INT (-2);
5773 /* If we've run out of registers, it goes on the stack. */
5774 if (cum->nregs == 0)
5777 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5779 /* Only floating point modes are passed in anything but integer regs. */
5780 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5783 regno = cum->regno + FIRST_SSE_REG;
5788 /* Unnamed floating parameters are passed in both the
5789 SSE and integer registers. */
5790 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5791 t2 = gen_rtx_REG (mode, regno);
5792 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5793 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5794 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5797 /* Handle aggregated types passed in register. */
5798 if (orig_mode == BLKmode)
5800 if (bytes > 0 && bytes <= 8)
5801 mode = (bytes > 4 ? DImode : SImode);
5802 if (mode == BLKmode)
5806 return gen_reg_or_parallel (mode, orig_mode, regno);
5810 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5811 tree type, int named)
5813 enum machine_mode mode = omode;
5814 HOST_WIDE_INT bytes, words;
5816 if (mode == BLKmode)
5817 bytes = int_size_in_bytes (type);
5819 bytes = GET_MODE_SIZE (mode);
5820 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5822 /* To simplify the code below, represent vector types with a vector mode
5823 even if MMX/SSE are not active. */
5824 if (type && TREE_CODE (type) == VECTOR_TYPE)
5825 mode = type_natural_mode (type, cum);
5827 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5828 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5829 else if (TARGET_64BIT)
5830 return function_arg_64 (cum, mode, omode, type, named);
5832 return function_arg_32 (cum, mode, omode, type, bytes, words);
5835 /* A C expression that indicates when an argument must be passed by
5836 reference. If nonzero for an argument, a copy of that argument is
5837 made in memory and a pointer to the argument is passed instead of
5838 the argument itself. The pointer is passed in whatever way is
5839 appropriate for passing a pointer to that type. */
5842 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5843 enum machine_mode mode ATTRIBUTE_UNUSED,
5844 const_tree type, bool named ATTRIBUTE_UNUSED)
5846 /* See Windows x64 Software Convention. */
5847 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5849 int msize = (int) GET_MODE_SIZE (mode);
5852 /* Arrays are passed by reference. */
5853 if (TREE_CODE (type) == ARRAY_TYPE)
5856 if (AGGREGATE_TYPE_P (type))
5858 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5859 are passed by reference. */
5860 msize = int_size_in_bytes (type);
5864 /* __m128 is passed by reference. */
5866 case 1: case 2: case 4: case 8:
5872 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5878 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5881 contains_aligned_value_p (tree type)
5883 enum machine_mode mode = TYPE_MODE (type);
5884 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5888 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5890 if (TYPE_ALIGN (type) < 128)
5893 if (AGGREGATE_TYPE_P (type))
5895 /* Walk the aggregates recursively. */
5896 switch (TREE_CODE (type))
5900 case QUAL_UNION_TYPE:
5904 /* Walk all the structure fields. */
5905 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5907 if (TREE_CODE (field) == FIELD_DECL
5908 && contains_aligned_value_p (TREE_TYPE (field)))
5915 /* Just for use if some languages passes arrays by value. */
5916 if (contains_aligned_value_p (TREE_TYPE (type)))
5927 /* Gives the alignment boundary, in bits, of an argument with the
5928 specified mode and type. */
5931 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5936 /* Since canonical type is used for call, we convert it to
5937 canonical type if needed. */
5938 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5939 type = TYPE_CANONICAL (type);
5940 align = TYPE_ALIGN (type);
5943 align = GET_MODE_ALIGNMENT (mode);
5944 if (align < PARM_BOUNDARY)
5945 align = PARM_BOUNDARY;
5946 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5947 natural boundaries. */
5948 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5950 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5951 make an exception for SSE modes since these require 128bit
5954 The handling here differs from field_alignment. ICC aligns MMX
5955 arguments to 4 byte boundaries, while structure fields are aligned
5956 to 8 byte boundaries. */
5959 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5960 align = PARM_BOUNDARY;
5964 if (!contains_aligned_value_p (type))
5965 align = PARM_BOUNDARY;
5968 if (align > BIGGEST_ALIGNMENT)
5969 align = BIGGEST_ALIGNMENT;
5973 /* Return true if N is a possible register number of function value. */
5976 ix86_function_value_regno_p (int regno)
5983 case FIRST_FLOAT_REG:
5984 /* TODO: The function should depend on current function ABI but
5985 builtins.c would need updating then. Therefore we use the
5987 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5989 return TARGET_FLOAT_RETURNS_IN_80387;
5995 if (TARGET_MACHO || TARGET_64BIT)
6003 /* Define how to find the value returned by a function.
6004 VALTYPE is the data type of the value (as a tree).
6005 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6006 otherwise, FUNC is 0. */
6009 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6010 const_tree fntype, const_tree fn)
6014 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6015 we normally prevent this case when mmx is not available. However
6016 some ABIs may require the result to be returned like DImode. */
6017 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6018 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6020 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6021 we prevent this case when sse is not available. However some ABIs
6022 may require the result to be returned like integer TImode. */
6023 else if (mode == TImode
6024 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6025 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6027 /* 32-byte vector modes in %ymm0. */
6028 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6029 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6031 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6032 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6033 regno = FIRST_FLOAT_REG;
6035 /* Most things go in %eax. */
6038 /* Override FP return register with %xmm0 for local functions when
6039 SSE math is enabled or for functions with sseregparm attribute. */
6040 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6042 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6043 if ((sse_level >= 1 && mode == SFmode)
6044 || (sse_level == 2 && mode == DFmode))
6045 regno = FIRST_SSE_REG;
6048 /* OImode shouldn't be used directly. */
6049 gcc_assert (mode != OImode);
6051 return gen_rtx_REG (orig_mode, regno);
6055 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6060 /* Handle libcalls, which don't provide a type node. */
6061 if (valtype == NULL)
6073 return gen_rtx_REG (mode, FIRST_SSE_REG);
6076 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6080 return gen_rtx_REG (mode, AX_REG);
6084 ret = construct_container (mode, orig_mode, valtype, 1,
6085 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6086 x86_64_int_return_registers, 0);
6088 /* For zero sized structures, construct_container returns NULL, but we
6089 need to keep rest of compiler happy by returning meaningful value. */
6091 ret = gen_rtx_REG (orig_mode, AX_REG);
6097 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6099 unsigned int regno = AX_REG;
6103 switch (GET_MODE_SIZE (mode))
6106 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6107 && !COMPLEX_MODE_P (mode))
6108 regno = FIRST_SSE_REG;
6112 if (mode == SFmode || mode == DFmode)
6113 regno = FIRST_SSE_REG;
6119 return gen_rtx_REG (orig_mode, regno);
6123 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6124 enum machine_mode orig_mode, enum machine_mode mode)
6126 const_tree fn, fntype;
6129 if (fntype_or_decl && DECL_P (fntype_or_decl))
6130 fn = fntype_or_decl;
6131 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6133 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6134 return function_value_ms_64 (orig_mode, mode);
6135 else if (TARGET_64BIT)
6136 return function_value_64 (orig_mode, mode, valtype);
6138 return function_value_32 (orig_mode, mode, fntype, fn);
6142 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6143 bool outgoing ATTRIBUTE_UNUSED)
6145 enum machine_mode mode, orig_mode;
6147 orig_mode = TYPE_MODE (valtype);
6148 mode = type_natural_mode (valtype, NULL);
6149 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6153 ix86_libcall_value (enum machine_mode mode)
6155 return ix86_function_value_1 (NULL, NULL, mode, mode);
6158 /* Return true iff type is returned in memory. */
6160 static int ATTRIBUTE_UNUSED
6161 return_in_memory_32 (const_tree type, enum machine_mode mode)
6165 if (mode == BLKmode)
6168 size = int_size_in_bytes (type);
6170 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6173 if (VECTOR_MODE_P (mode) || mode == TImode)
6175 /* User-created vectors small enough to fit in EAX. */
6179 /* MMX/3dNow values are returned in MM0,
6180 except when it doesn't exits. */
6182 return (TARGET_MMX ? 0 : 1);
6184 /* SSE values are returned in XMM0, except when it doesn't exist. */
6186 return (TARGET_SSE ? 0 : 1);
6188 /* AVX values are returned in YMM0, except when it doesn't exist. */
6190 return TARGET_AVX ? 0 : 1;
6199 /* OImode shouldn't be used directly. */
6200 gcc_assert (mode != OImode);
6205 static int ATTRIBUTE_UNUSED
6206 return_in_memory_64 (const_tree type, enum machine_mode mode)
6208 int needed_intregs, needed_sseregs;
6209 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6212 static int ATTRIBUTE_UNUSED
6213 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6215 HOST_WIDE_INT size = int_size_in_bytes (type);
6217 /* __m128 is returned in xmm0. */
6218 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6219 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6222 /* Otherwise, the size must be exactly in [1248]. */
6223 return (size != 1 && size != 2 && size != 4 && size != 8);
6227 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6229 #ifdef SUBTARGET_RETURN_IN_MEMORY
6230 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6232 const enum machine_mode mode = type_natural_mode (type, NULL);
6236 if (ix86_function_type_abi (fntype) == MS_ABI)
6237 return return_in_memory_ms_64 (type, mode);
6239 return return_in_memory_64 (type, mode);
6242 return return_in_memory_32 (type, mode);
6246 /* Return false iff TYPE is returned in memory. This version is used
6247 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6248 but differs notably in that when MMX is available, 8-byte vectors
6249 are returned in memory, rather than in MMX registers. */
6252 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6255 enum machine_mode mode = type_natural_mode (type, NULL);
6258 return return_in_memory_64 (type, mode);
6260 if (mode == BLKmode)
6263 size = int_size_in_bytes (type);
6265 if (VECTOR_MODE_P (mode))
6267 /* Return in memory only if MMX registers *are* available. This
6268 seems backwards, but it is consistent with the existing
6275 else if (mode == TImode)
6277 else if (mode == XFmode)
6283 /* When returning SSE vector types, we have a choice of either
6284 (1) being abi incompatible with a -march switch, or
6285 (2) generating an error.
6286 Given no good solution, I think the safest thing is one warning.
6287 The user won't be able to use -Werror, but....
6289 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6290 called in response to actually generating a caller or callee that
6291 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6292 via aggregate_value_p for general type probing from tree-ssa. */
6295 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6297 static bool warnedsse, warnedmmx;
6299 if (!TARGET_64BIT && type)
6301 /* Look at the return type of the function, not the function type. */
6302 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6304 if (!TARGET_SSE && !warnedsse)
6307 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6310 warning (0, "SSE vector return without SSE enabled "
6315 if (!TARGET_MMX && !warnedmmx)
6317 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6320 warning (0, "MMX vector return without MMX enabled "
6330 /* Create the va_list data type. */
6332 /* Returns the calling convention specific va_list date type.
6333 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6336 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6338 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6340 /* For i386 we use plain pointer to argument area. */
6341 if (!TARGET_64BIT || abi == MS_ABI)
6342 return build_pointer_type (char_type_node);
6344 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6345 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6347 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6348 unsigned_type_node);
6349 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6350 unsigned_type_node);
6351 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6353 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6356 va_list_gpr_counter_field = f_gpr;
6357 va_list_fpr_counter_field = f_fpr;
6359 DECL_FIELD_CONTEXT (f_gpr) = record;
6360 DECL_FIELD_CONTEXT (f_fpr) = record;
6361 DECL_FIELD_CONTEXT (f_ovf) = record;
6362 DECL_FIELD_CONTEXT (f_sav) = record;
6364 TREE_CHAIN (record) = type_decl;
6365 TYPE_NAME (record) = type_decl;
6366 TYPE_FIELDS (record) = f_gpr;
6367 TREE_CHAIN (f_gpr) = f_fpr;
6368 TREE_CHAIN (f_fpr) = f_ovf;
6369 TREE_CHAIN (f_ovf) = f_sav;
6371 layout_type (record);
6373 /* The correct type is an array type of one element. */
6374 return build_array_type (record, build_index_type (size_zero_node));
6377 /* Setup the builtin va_list data type and for 64-bit the additional
6378 calling convention specific va_list data types. */
6381 ix86_build_builtin_va_list (void)
6383 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6385 /* Initialize abi specific va_list builtin types. */
6389 if (DEFAULT_ABI == MS_ABI)
6391 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6392 if (TREE_CODE (t) != RECORD_TYPE)
6393 t = build_variant_type_copy (t);
6394 sysv_va_list_type_node = t;
6399 if (TREE_CODE (t) != RECORD_TYPE)
6400 t = build_variant_type_copy (t);
6401 sysv_va_list_type_node = t;
6403 if (DEFAULT_ABI != MS_ABI)
6405 t = ix86_build_builtin_va_list_abi (MS_ABI);
6406 if (TREE_CODE (t) != RECORD_TYPE)
6407 t = build_variant_type_copy (t);
6408 ms_va_list_type_node = t;
6413 if (TREE_CODE (t) != RECORD_TYPE)
6414 t = build_variant_type_copy (t);
6415 ms_va_list_type_node = t;
6422 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6425 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6434 int regparm = ix86_regparm;
6436 if (cum->call_abi != DEFAULT_ABI)
6437 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6439 /* GPR size of varargs save area. */
6440 if (cfun->va_list_gpr_size)
6441 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6443 ix86_varargs_gpr_size = 0;
6445 /* FPR size of varargs save area. We don't need it if we don't pass
6446 anything in SSE registers. */
6447 if (cum->sse_nregs && cfun->va_list_fpr_size)
6448 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6450 ix86_varargs_fpr_size = 0;
6452 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6455 save_area = frame_pointer_rtx;
6456 set = get_varargs_alias_set ();
6458 for (i = cum->regno;
6460 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6463 mem = gen_rtx_MEM (Pmode,
6464 plus_constant (save_area, i * UNITS_PER_WORD));
6465 MEM_NOTRAP_P (mem) = 1;
6466 set_mem_alias_set (mem, set);
6467 emit_move_insn (mem, gen_rtx_REG (Pmode,
6468 x86_64_int_parameter_registers[i]));
6471 if (ix86_varargs_fpr_size)
6473 /* Now emit code to save SSE registers. The AX parameter contains number
6474 of SSE parameter registers used to call this function. We use
6475 sse_prologue_save insn template that produces computed jump across
6476 SSE saves. We need some preparation work to get this working. */
6478 label = gen_label_rtx ();
6479 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6481 /* Compute address to jump to :
6482 label - eax*4 + nnamed_sse_arguments*4 Or
6483 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6484 tmp_reg = gen_reg_rtx (Pmode);
6485 nsse_reg = gen_reg_rtx (Pmode);
6486 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6487 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6488 gen_rtx_MULT (Pmode, nsse_reg,
6491 /* vmovaps is one byte longer than movaps. */
6493 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6494 gen_rtx_PLUS (Pmode, tmp_reg,
6500 gen_rtx_CONST (DImode,
6501 gen_rtx_PLUS (DImode,
6503 GEN_INT (cum->sse_regno
6504 * (TARGET_AVX ? 5 : 4)))));
6506 emit_move_insn (nsse_reg, label_ref);
6507 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6509 /* Compute address of memory block we save into. We always use pointer
6510 pointing 127 bytes after first byte to store - this is needed to keep
6511 instruction size limited by 4 bytes (5 bytes for AVX) with one
6512 byte displacement. */
6513 tmp_reg = gen_reg_rtx (Pmode);
6514 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6515 plus_constant (save_area,
6516 ix86_varargs_gpr_size + 127)));
6517 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6518 MEM_NOTRAP_P (mem) = 1;
6519 set_mem_alias_set (mem, set);
6520 set_mem_align (mem, BITS_PER_WORD);
6522 /* And finally do the dirty job! */
6523 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6524 GEN_INT (cum->sse_regno), label));
6529 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6531 alias_set_type set = get_varargs_alias_set ();
6534 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6538 mem = gen_rtx_MEM (Pmode,
6539 plus_constant (virtual_incoming_args_rtx,
6540 i * UNITS_PER_WORD));
6541 MEM_NOTRAP_P (mem) = 1;
6542 set_mem_alias_set (mem, set);
6544 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6545 emit_move_insn (mem, reg);
6550 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6551 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6554 CUMULATIVE_ARGS next_cum;
6557 /* This argument doesn't appear to be used anymore. Which is good,
6558 because the old code here didn't suppress rtl generation. */
6559 gcc_assert (!no_rtl);
6564 fntype = TREE_TYPE (current_function_decl);
6566 /* For varargs, we do not want to skip the dummy va_dcl argument.
6567 For stdargs, we do want to skip the last named argument. */
6569 if (stdarg_p (fntype))
6570 function_arg_advance (&next_cum, mode, type, 1);
6572 if (cum->call_abi == MS_ABI)
6573 setup_incoming_varargs_ms_64 (&next_cum);
6575 setup_incoming_varargs_64 (&next_cum);
6578 /* Checks if TYPE is of kind va_list char *. */
6581 is_va_list_char_pointer (tree type)
6585 /* For 32-bit it is always true. */
6588 canonic = ix86_canonical_va_list_type (type);
6589 return (canonic == ms_va_list_type_node
6590 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6593 /* Implement va_start. */
6596 ix86_va_start (tree valist, rtx nextarg)
6598 HOST_WIDE_INT words, n_gpr, n_fpr;
6599 tree f_gpr, f_fpr, f_ovf, f_sav;
6600 tree gpr, fpr, ovf, sav, t;
6603 /* Only 64bit target needs something special. */
6604 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6606 std_expand_builtin_va_start (valist, nextarg);
6610 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6611 f_fpr = TREE_CHAIN (f_gpr);
6612 f_ovf = TREE_CHAIN (f_fpr);
6613 f_sav = TREE_CHAIN (f_ovf);
6615 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6616 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6617 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6618 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6619 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6621 /* Count number of gp and fp argument registers used. */
6622 words = crtl->args.info.words;
6623 n_gpr = crtl->args.info.regno;
6624 n_fpr = crtl->args.info.sse_regno;
6626 if (cfun->va_list_gpr_size)
6628 type = TREE_TYPE (gpr);
6629 t = build2 (MODIFY_EXPR, type,
6630 gpr, build_int_cst (type, n_gpr * 8));
6631 TREE_SIDE_EFFECTS (t) = 1;
6632 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6635 if (TARGET_SSE && cfun->va_list_fpr_size)
6637 type = TREE_TYPE (fpr);
6638 t = build2 (MODIFY_EXPR, type, fpr,
6639 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6640 TREE_SIDE_EFFECTS (t) = 1;
6641 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6644 /* Find the overflow area. */
6645 type = TREE_TYPE (ovf);
6646 t = make_tree (type, crtl->args.internal_arg_pointer);
6648 t = build2 (POINTER_PLUS_EXPR, type, t,
6649 size_int (words * UNITS_PER_WORD));
6650 t = build2 (MODIFY_EXPR, type, ovf, t);
6651 TREE_SIDE_EFFECTS (t) = 1;
6652 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6654 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6656 /* Find the register save area.
6657 Prologue of the function save it right above stack frame. */
6658 type = TREE_TYPE (sav);
6659 t = make_tree (type, frame_pointer_rtx);
6660 if (!ix86_varargs_gpr_size)
6661 t = build2 (POINTER_PLUS_EXPR, type, t,
6662 size_int (-8 * X86_64_REGPARM_MAX));
6663 t = build2 (MODIFY_EXPR, type, sav, t);
6664 TREE_SIDE_EFFECTS (t) = 1;
6665 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6669 /* Implement va_arg. */
6672 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6675 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6676 tree f_gpr, f_fpr, f_ovf, f_sav;
6677 tree gpr, fpr, ovf, sav, t;
6679 tree lab_false, lab_over = NULL_TREE;
6684 enum machine_mode nat_mode;
6687 /* Only 64bit target needs something special. */
6688 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6689 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6691 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6692 f_fpr = TREE_CHAIN (f_gpr);
6693 f_ovf = TREE_CHAIN (f_fpr);
6694 f_sav = TREE_CHAIN (f_ovf);
6696 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6697 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6698 valist = build_va_arg_indirect_ref (valist);
6699 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6700 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6701 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6703 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6705 type = build_pointer_type (type);
6706 size = int_size_in_bytes (type);
6707 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6709 nat_mode = type_natural_mode (type, NULL);
6718 /* Unnamed 256bit vector mode parameters are passed on stack. */
6719 if (ix86_cfun_abi () == SYSV_ABI)
6726 container = construct_container (nat_mode, TYPE_MODE (type),
6727 type, 0, X86_64_REGPARM_MAX,
6728 X86_64_SSE_REGPARM_MAX, intreg,
6733 /* Pull the value out of the saved registers. */
6735 addr = create_tmp_var (ptr_type_node, "addr");
6736 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6740 int needed_intregs, needed_sseregs;
6742 tree int_addr, sse_addr;
6744 lab_false = create_artificial_label ();
6745 lab_over = create_artificial_label ();
6747 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6749 need_temp = (!REG_P (container)
6750 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6751 || TYPE_ALIGN (type) > 128));
6753 /* In case we are passing structure, verify that it is consecutive block
6754 on the register save area. If not we need to do moves. */
6755 if (!need_temp && !REG_P (container))
6757 /* Verify that all registers are strictly consecutive */
6758 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6762 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6764 rtx slot = XVECEXP (container, 0, i);
6765 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6766 || INTVAL (XEXP (slot, 1)) != i * 16)
6774 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6776 rtx slot = XVECEXP (container, 0, i);
6777 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6778 || INTVAL (XEXP (slot, 1)) != i * 8)
6790 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6791 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6792 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6793 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6796 /* First ensure that we fit completely in registers. */
6799 t = build_int_cst (TREE_TYPE (gpr),
6800 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6801 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6802 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6803 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6804 gimplify_and_add (t, pre_p);
6808 t = build_int_cst (TREE_TYPE (fpr),
6809 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6810 + X86_64_REGPARM_MAX * 8);
6811 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6812 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6813 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6814 gimplify_and_add (t, pre_p);
6817 /* Compute index to start of area used for integer regs. */
6820 /* int_addr = gpr + sav; */
6821 t = fold_convert (sizetype, gpr);
6822 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6823 gimplify_assign (int_addr, t, pre_p);
6827 /* sse_addr = fpr + sav; */
6828 t = fold_convert (sizetype, fpr);
6829 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6830 gimplify_assign (sse_addr, t, pre_p);
6835 tree temp = create_tmp_var (type, "va_arg_tmp");
6838 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6839 gimplify_assign (addr, t, pre_p);
6841 for (i = 0; i < XVECLEN (container, 0); i++)
6843 rtx slot = XVECEXP (container, 0, i);
6844 rtx reg = XEXP (slot, 0);
6845 enum machine_mode mode = GET_MODE (reg);
6846 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6847 tree addr_type = build_pointer_type (piece_type);
6848 tree daddr_type = build_pointer_type_for_mode (piece_type,
6852 tree dest_addr, dest;
6854 if (SSE_REGNO_P (REGNO (reg)))
6856 src_addr = sse_addr;
6857 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6861 src_addr = int_addr;
6862 src_offset = REGNO (reg) * 8;
6864 src_addr = fold_convert (addr_type, src_addr);
6865 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6866 size_int (src_offset));
6867 src = build_va_arg_indirect_ref (src_addr);
6869 dest_addr = fold_convert (daddr_type, addr);
6870 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6871 size_int (INTVAL (XEXP (slot, 1))));
6872 dest = build_va_arg_indirect_ref (dest_addr);
6874 gimplify_assign (dest, src, pre_p);
6880 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6881 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6882 gimplify_assign (gpr, t, pre_p);
6887 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6888 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6889 gimplify_assign (fpr, t, pre_p);
6892 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6894 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6897 /* ... otherwise out of the overflow area. */
6899 /* When we align parameter on stack for caller, if the parameter
6900 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6901 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6902 here with caller. */
6903 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6904 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6905 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6907 /* Care for on-stack alignment if needed. */
6908 if (arg_boundary <= 64
6909 || integer_zerop (TYPE_SIZE (type)))
6913 HOST_WIDE_INT align = arg_boundary / 8;
6914 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6915 size_int (align - 1));
6916 t = fold_convert (sizetype, t);
6917 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6919 t = fold_convert (TREE_TYPE (ovf), t);
6921 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6922 gimplify_assign (addr, t, pre_p);
6924 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6925 size_int (rsize * UNITS_PER_WORD));
6926 gimplify_assign (unshare_expr (ovf), t, pre_p);
6929 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6931 ptrtype = build_pointer_type (type);
6932 addr = fold_convert (ptrtype, addr);
6935 addr = build_va_arg_indirect_ref (addr);
6936 return build_va_arg_indirect_ref (addr);
6939 /* Return nonzero if OPNUM's MEM should be matched
6940 in movabs* patterns. */
6943 ix86_check_movabs (rtx insn, int opnum)
6947 set = PATTERN (insn);
6948 if (GET_CODE (set) == PARALLEL)
6949 set = XVECEXP (set, 0, 0);
6950 gcc_assert (GET_CODE (set) == SET);
6951 mem = XEXP (set, opnum);
6952 while (GET_CODE (mem) == SUBREG)
6953 mem = SUBREG_REG (mem);
6954 gcc_assert (MEM_P (mem));
6955 return (volatile_ok || !MEM_VOLATILE_P (mem));
6958 /* Initialize the table of extra 80387 mathematical constants. */
6961 init_ext_80387_constants (void)
6963 static const char * cst[5] =
6965 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6966 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6967 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6968 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6969 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6973 for (i = 0; i < 5; i++)
6975 real_from_string (&ext_80387_constants_table[i], cst[i]);
6976 /* Ensure each constant is rounded to XFmode precision. */
6977 real_convert (&ext_80387_constants_table[i],
6978 XFmode, &ext_80387_constants_table[i]);
6981 ext_80387_constants_init = 1;
6984 /* Return true if the constant is something that can be loaded with
6985 a special instruction. */
6988 standard_80387_constant_p (rtx x)
6990 enum machine_mode mode = GET_MODE (x);
6994 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6997 if (x == CONST0_RTX (mode))
6999 if (x == CONST1_RTX (mode))
7002 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7004 /* For XFmode constants, try to find a special 80387 instruction when
7005 optimizing for size or on those CPUs that benefit from them. */
7007 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7011 if (! ext_80387_constants_init)
7012 init_ext_80387_constants ();
7014 for (i = 0; i < 5; i++)
7015 if (real_identical (&r, &ext_80387_constants_table[i]))
7019 /* Load of the constant -0.0 or -1.0 will be split as
7020 fldz;fchs or fld1;fchs sequence. */
7021 if (real_isnegzero (&r))
7023 if (real_identical (&r, &dconstm1))
7029 /* Return the opcode of the special instruction to be used to load
7033 standard_80387_constant_opcode (rtx x)
7035 switch (standard_80387_constant_p (x))
7059 /* Return the CONST_DOUBLE representing the 80387 constant that is
7060 loaded by the specified special instruction. The argument IDX
7061 matches the return value from standard_80387_constant_p. */
7064 standard_80387_constant_rtx (int idx)
7068 if (! ext_80387_constants_init)
7069 init_ext_80387_constants ();
7085 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7089 /* Return 1 if mode is a valid mode for sse. */
7091 standard_sse_mode_p (enum machine_mode mode)
7108 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7109 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7110 modes and AVX is enabled. */
7113 standard_sse_constant_p (rtx x)
7115 enum machine_mode mode = GET_MODE (x);
7117 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7119 if (vector_all_ones_operand (x, mode))
7121 if (standard_sse_mode_p (mode))
7122 return TARGET_SSE2 ? 2 : -2;
7123 else if (VALID_AVX256_REG_MODE (mode))
7124 return TARGET_AVX ? 3 : -3;
7130 /* Return the opcode of the special instruction to be used to load
7134 standard_sse_constant_opcode (rtx insn, rtx x)
7136 switch (standard_sse_constant_p (x))
7139 switch (get_attr_mode (insn))
7142 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7144 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7146 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7148 return "vxorps\t%x0, %x0, %x0";
7150 return "vxorpd\t%x0, %x0, %x0";
7152 return "vpxor\t%x0, %x0, %x0";
7158 switch (get_attr_mode (insn))
7163 return "vpcmpeqd\t%0, %0, %0";
7169 return "pcmpeqd\t%0, %0";
7174 /* Returns 1 if OP contains a symbol reference */
7177 symbolic_reference_mentioned_p (rtx op)
7182 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7185 fmt = GET_RTX_FORMAT (GET_CODE (op));
7186 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7192 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7193 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7197 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7204 /* Return 1 if it is appropriate to emit `ret' instructions in the
7205 body of a function. Do this only if the epilogue is simple, needing a
7206 couple of insns. Prior to reloading, we can't tell how many registers
7207 must be saved, so return 0 then. Return 0 if there is no frame
7208 marker to de-allocate. */
7211 ix86_can_use_return_insn_p (void)
7213 struct ix86_frame frame;
7215 if (! reload_completed || frame_pointer_needed)
7218 /* Don't allow more than 32 pop, since that's all we can do
7219 with one instruction. */
7220 if (crtl->args.pops_args
7221 && crtl->args.size >= 32768)
7224 ix86_compute_frame_layout (&frame);
7225 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7228 /* Value should be nonzero if functions must have frame pointers.
7229 Zero means the frame pointer need not be set up (and parms may
7230 be accessed via the stack pointer) in functions that seem suitable. */
7233 ix86_frame_pointer_required (void)
7235 /* If we accessed previous frames, then the generated code expects
7236 to be able to access the saved ebp value in our frame. */
7237 if (cfun->machine->accesses_prev_frame)
7240 /* Several x86 os'es need a frame pointer for other reasons,
7241 usually pertaining to setjmp. */
7242 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7245 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7246 the frame pointer by default. Turn it back on now if we've not
7247 got a leaf function. */
7248 if (TARGET_OMIT_LEAF_FRAME_POINTER
7249 && (!current_function_is_leaf
7250 || ix86_current_function_calls_tls_descriptor))
7259 /* Record that the current function accesses previous call frames. */
7262 ix86_setup_frame_addresses (void)
7264 cfun->machine->accesses_prev_frame = 1;
7267 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7268 # define USE_HIDDEN_LINKONCE 1
7270 # define USE_HIDDEN_LINKONCE 0
7273 static int pic_labels_used;
7275 /* Fills in the label name that should be used for a pc thunk for
7276 the given register. */
7279 get_pc_thunk_name (char name[32], unsigned int regno)
7281 gcc_assert (!TARGET_64BIT);
7283 if (USE_HIDDEN_LINKONCE)
7284 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7286 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7290 /* This function generates code for -fpic that loads %ebx with
7291 the return address of the caller and then returns. */
7294 ix86_file_end (void)
7299 for (regno = 0; regno < 8; ++regno)
7303 if (! ((pic_labels_used >> regno) & 1))
7306 get_pc_thunk_name (name, regno);
7311 switch_to_section (darwin_sections[text_coal_section]);
7312 fputs ("\t.weak_definition\t", asm_out_file);
7313 assemble_name (asm_out_file, name);
7314 fputs ("\n\t.private_extern\t", asm_out_file);
7315 assemble_name (asm_out_file, name);
7316 fputs ("\n", asm_out_file);
7317 ASM_OUTPUT_LABEL (asm_out_file, name);
7321 if (USE_HIDDEN_LINKONCE)
7325 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7327 TREE_PUBLIC (decl) = 1;
7328 TREE_STATIC (decl) = 1;
7329 DECL_ONE_ONLY (decl) = 1;
7331 (*targetm.asm_out.unique_section) (decl, 0);
7332 switch_to_section (get_named_section (decl, NULL, 0));
7334 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7335 fputs ("\t.hidden\t", asm_out_file);
7336 assemble_name (asm_out_file, name);
7337 fputc ('\n', asm_out_file);
7338 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7342 switch_to_section (text_section);
7343 ASM_OUTPUT_LABEL (asm_out_file, name);
7346 xops[0] = gen_rtx_REG (Pmode, regno);
7347 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7348 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7349 output_asm_insn ("ret", xops);
7352 if (NEED_INDICATE_EXEC_STACK)
7353 file_end_indicate_exec_stack ();
7356 /* Emit code for the SET_GOT patterns. */
7359 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7365 if (TARGET_VXWORKS_RTP && flag_pic)
7367 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7368 xops[2] = gen_rtx_MEM (Pmode,
7369 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7370 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7372 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7373 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7374 an unadorned address. */
7375 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7376 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7377 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7381 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7383 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7385 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7388 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7390 output_asm_insn ("call\t%a2", xops);
7393 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7394 is what will be referenced by the Mach-O PIC subsystem. */
7396 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7399 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7400 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7403 output_asm_insn ("pop%z0\t%0", xops);
7408 get_pc_thunk_name (name, REGNO (dest));
7409 pic_labels_used |= 1 << REGNO (dest);
7411 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7412 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7413 output_asm_insn ("call\t%X2", xops);
7414 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7415 is what will be referenced by the Mach-O PIC subsystem. */
7418 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7420 targetm.asm_out.internal_label (asm_out_file, "L",
7421 CODE_LABEL_NUMBER (label));
7428 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7429 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7431 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7436 /* Generate an "push" pattern for input ARG. */
7441 return gen_rtx_SET (VOIDmode,
7443 gen_rtx_PRE_DEC (Pmode,
7444 stack_pointer_rtx)),
7448 /* Return >= 0 if there is an unused call-clobbered register available
7449 for the entire function. */
7452 ix86_select_alt_pic_regnum (void)
7454 if (current_function_is_leaf && !crtl->profile
7455 && !ix86_current_function_calls_tls_descriptor)
7458 /* Can't use the same register for both PIC and DRAP. */
7460 drap = REGNO (crtl->drap_reg);
7463 for (i = 2; i >= 0; --i)
7464 if (i != drap && !df_regs_ever_live_p (i))
7468 return INVALID_REGNUM;
7471 /* Return 1 if we need to save REGNO. */
7473 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7475 if (pic_offset_table_rtx
7476 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7477 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7479 || crtl->calls_eh_return
7480 || crtl->uses_const_pool))
7482 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7487 if (crtl->calls_eh_return && maybe_eh_return)
7492 unsigned test = EH_RETURN_DATA_REGNO (i);
7493 if (test == INVALID_REGNUM)
7501 && regno == REGNO (crtl->drap_reg))
7504 return (df_regs_ever_live_p (regno)
7505 && !call_used_regs[regno]
7506 && !fixed_regs[regno]
7507 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7510 /* Return number of saved general prupose registers. */
7513 ix86_nsaved_regs (void)
7518 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7519 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7524 /* Return number of saved SSE registrers. */
7527 ix86_nsaved_sseregs (void)
7532 if (ix86_cfun_abi () != MS_ABI)
7534 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7535 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7540 /* Given FROM and TO register numbers, say whether this elimination is
7541 allowed. If stack alignment is needed, we can only replace argument
7542 pointer with hard frame pointer, or replace frame pointer with stack
7543 pointer. Otherwise, frame pointer elimination is automatically
7544 handled and all other eliminations are valid. */
7547 ix86_can_eliminate (int from, int to)
7549 if (stack_realign_fp)
7550 return ((from == ARG_POINTER_REGNUM
7551 && to == HARD_FRAME_POINTER_REGNUM)
7552 || (from == FRAME_POINTER_REGNUM
7553 && to == STACK_POINTER_REGNUM));
7555 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7558 /* Return the offset between two registers, one to be eliminated, and the other
7559 its replacement, at the start of a routine. */
7562 ix86_initial_elimination_offset (int from, int to)
7564 struct ix86_frame frame;
7565 ix86_compute_frame_layout (&frame);
7567 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7568 return frame.hard_frame_pointer_offset;
7569 else if (from == FRAME_POINTER_REGNUM
7570 && to == HARD_FRAME_POINTER_REGNUM)
7571 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7574 gcc_assert (to == STACK_POINTER_REGNUM);
7576 if (from == ARG_POINTER_REGNUM)
7577 return frame.stack_pointer_offset;
7579 gcc_assert (from == FRAME_POINTER_REGNUM);
7580 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7584 /* In a dynamically-aligned function, we can't know the offset from
7585 stack pointer to frame pointer, so we must ensure that setjmp
7586 eliminates fp against the hard fp (%ebp) rather than trying to
7587 index from %esp up to the top of the frame across a gap that is
7588 of unknown (at compile-time) size. */
7590 ix86_builtin_setjmp_frame_value (void)
7592 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7595 /* Fill structure ix86_frame about frame of currently computed function. */
7598 ix86_compute_frame_layout (struct ix86_frame *frame)
7600 HOST_WIDE_INT total_size;
7601 unsigned int stack_alignment_needed;
7602 HOST_WIDE_INT offset;
7603 unsigned int preferred_alignment;
7604 HOST_WIDE_INT size = get_frame_size ();
7606 frame->nregs = ix86_nsaved_regs ();
7607 frame->nsseregs = ix86_nsaved_sseregs ();
7610 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7611 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7613 /* MS ABI seem to require stack alignment to be always 16 except for function
7615 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7617 preferred_alignment = 16;
7618 stack_alignment_needed = 16;
7619 crtl->preferred_stack_boundary = 128;
7620 crtl->stack_alignment_needed = 128;
7623 gcc_assert (!size || stack_alignment_needed);
7624 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7625 gcc_assert (preferred_alignment <= stack_alignment_needed);
7627 /* During reload iteration the amount of registers saved can change.
7628 Recompute the value as needed. Do not recompute when amount of registers
7629 didn't change as reload does multiple calls to the function and does not
7630 expect the decision to change within single iteration. */
7631 if (!optimize_function_for_size_p (cfun)
7632 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7634 int count = frame->nregs;
7636 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7637 /* The fast prologue uses move instead of push to save registers. This
7638 is significantly longer, but also executes faster as modern hardware
7639 can execute the moves in parallel, but can't do that for push/pop.
7641 Be careful about choosing what prologue to emit: When function takes
7642 many instructions to execute we may use slow version as well as in
7643 case function is known to be outside hot spot (this is known with
7644 feedback only). Weight the size of function by number of registers
7645 to save as it is cheap to use one or two push instructions but very
7646 slow to use many of them. */
7648 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7649 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7650 || (flag_branch_probabilities
7651 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7652 cfun->machine->use_fast_prologue_epilogue = false;
7654 cfun->machine->use_fast_prologue_epilogue
7655 = !expensive_function_p (count);
7657 if (TARGET_PROLOGUE_USING_MOVE
7658 && cfun->machine->use_fast_prologue_epilogue)
7659 frame->save_regs_using_mov = true;
7661 frame->save_regs_using_mov = false;
7664 /* Skip return address and saved base pointer. */
7665 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7667 frame->hard_frame_pointer_offset = offset;
7669 /* Set offset to aligned because the realigned frame starts from
7671 if (stack_realign_fp)
7672 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7674 /* Register save area */
7675 offset += frame->nregs * UNITS_PER_WORD;
7677 /* Align SSE reg save area. */
7678 if (frame->nsseregs)
7679 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7681 frame->padding0 = 0;
7683 /* SSE register save area. */
7684 offset += frame->padding0 + frame->nsseregs * 16;
7687 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7688 offset += frame->va_arg_size;
7690 /* Align start of frame for local function. */
7691 frame->padding1 = ((offset + stack_alignment_needed - 1)
7692 & -stack_alignment_needed) - offset;
7694 offset += frame->padding1;
7696 /* Frame pointer points here. */
7697 frame->frame_pointer_offset = offset;
7701 /* Add outgoing arguments area. Can be skipped if we eliminated
7702 all the function calls as dead code.
7703 Skipping is however impossible when function calls alloca. Alloca
7704 expander assumes that last crtl->outgoing_args_size
7705 of stack frame are unused. */
7706 if (ACCUMULATE_OUTGOING_ARGS
7707 && (!current_function_is_leaf || cfun->calls_alloca
7708 || ix86_current_function_calls_tls_descriptor))
7710 offset += crtl->outgoing_args_size;
7711 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7714 frame->outgoing_arguments_size = 0;
7716 /* Align stack boundary. Only needed if we're calling another function
7718 if (!current_function_is_leaf || cfun->calls_alloca
7719 || ix86_current_function_calls_tls_descriptor)
7720 frame->padding2 = ((offset + preferred_alignment - 1)
7721 & -preferred_alignment) - offset;
7723 frame->padding2 = 0;
7725 offset += frame->padding2;
7727 /* We've reached end of stack frame. */
7728 frame->stack_pointer_offset = offset;
7730 /* Size prologue needs to allocate. */
7731 frame->to_allocate =
7732 (size + frame->padding1 + frame->padding2
7733 + frame->outgoing_arguments_size + frame->va_arg_size);
7735 if ((!frame->to_allocate && frame->nregs <= 1)
7736 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7737 frame->save_regs_using_mov = false;
7739 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7740 && current_function_is_leaf
7741 && !ix86_current_function_calls_tls_descriptor)
7743 frame->red_zone_size = frame->to_allocate;
7744 if (frame->save_regs_using_mov)
7745 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7746 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7747 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7750 frame->red_zone_size = 0;
7751 frame->to_allocate -= frame->red_zone_size;
7752 frame->stack_pointer_offset -= frame->red_zone_size;
7754 fprintf (stderr, "\n");
7755 fprintf (stderr, "size: %ld\n", (long)size);
7756 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7757 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7758 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7759 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7760 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7761 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7762 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7763 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7764 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7765 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7766 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7767 (long)frame->hard_frame_pointer_offset);
7768 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7769 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7770 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7771 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7775 /* Emit code to save registers in the prologue. */
7778 ix86_emit_save_regs (void)
7783 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7784 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7786 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7787 RTX_FRAME_RELATED_P (insn) = 1;
7791 /* Emit code to save registers using MOV insns. First register
7792 is restored from POINTER + OFFSET. */
7794 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7799 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7800 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7802 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7804 gen_rtx_REG (Pmode, regno));
7805 RTX_FRAME_RELATED_P (insn) = 1;
7806 offset += UNITS_PER_WORD;
7810 /* Emit code to save registers using MOV insns. First register
7811 is restored from POINTER + OFFSET. */
7813 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7819 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7820 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7822 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7823 set_mem_align (mem, 128);
7824 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7825 RTX_FRAME_RELATED_P (insn) = 1;
7830 /* Expand prologue or epilogue stack adjustment.
7831 The pattern exist to put a dependency on all ebp-based memory accesses.
7832 STYLE should be negative if instructions should be marked as frame related,
7833 zero if %r11 register is live and cannot be freely used and positive
7837 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7842 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7843 else if (x86_64_immediate_operand (offset, DImode))
7844 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7848 /* r11 is used by indirect sibcall return as well, set before the
7849 epilogue and used after the epilogue. ATM indirect sibcall
7850 shouldn't be used together with huge frame sizes in one
7851 function because of the frame_size check in sibcall.c. */
7853 r11 = gen_rtx_REG (DImode, R11_REG);
7854 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7856 RTX_FRAME_RELATED_P (insn) = 1;
7857 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7861 RTX_FRAME_RELATED_P (insn) = 1;
7864 /* Find an available register to be used as dynamic realign argument
7865 pointer regsiter. Such a register will be written in prologue and
7866 used in begin of body, so it must not be
7867 1. parameter passing register.
7869 We reuse static-chain register if it is available. Otherwise, we
7870 use DI for i386 and R13 for x86-64. We chose R13 since it has
7873 Return: the regno of chosen register. */
7876 find_drap_reg (void)
7878 tree decl = cfun->decl;
7882 /* Use R13 for nested function or function need static chain.
7883 Since function with tail call may use any caller-saved
7884 registers in epilogue, DRAP must not use caller-saved
7885 register in such case. */
7886 if ((decl_function_context (decl)
7887 && !DECL_NO_STATIC_CHAIN (decl))
7888 || crtl->tail_call_emit)
7895 /* Use DI for nested function or function need static chain.
7896 Since function with tail call may use any caller-saved
7897 registers in epilogue, DRAP must not use caller-saved
7898 register in such case. */
7899 if ((decl_function_context (decl)
7900 && !DECL_NO_STATIC_CHAIN (decl))
7901 || crtl->tail_call_emit)
7904 /* Reuse static chain register if it isn't used for parameter
7906 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7907 && !lookup_attribute ("fastcall",
7908 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7915 /* Update incoming stack boundary and estimated stack alignment. */
7918 ix86_update_stack_boundary (void)
7920 /* Prefer the one specified at command line. */
7921 ix86_incoming_stack_boundary
7922 = (ix86_user_incoming_stack_boundary
7923 ? ix86_user_incoming_stack_boundary
7924 : ix86_default_incoming_stack_boundary);
7926 /* Incoming stack alignment can be changed on individual functions
7927 via force_align_arg_pointer attribute. We use the smallest
7928 incoming stack boundary. */
7929 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7930 && lookup_attribute (ix86_force_align_arg_pointer_string,
7931 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7932 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7934 /* The incoming stack frame has to be aligned at least at
7935 parm_stack_boundary. */
7936 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7937 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7939 /* Stack at entrance of main is aligned by runtime. We use the
7940 smallest incoming stack boundary. */
7941 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7942 && DECL_NAME (current_function_decl)
7943 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7944 && DECL_FILE_SCOPE_P (current_function_decl))
7945 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7947 /* x86_64 vararg needs 16byte stack alignment for register save
7951 && crtl->stack_alignment_estimated < 128)
7952 crtl->stack_alignment_estimated = 128;
7955 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7956 needed or an rtx for DRAP otherwise. */
7959 ix86_get_drap_rtx (void)
7961 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7962 crtl->need_drap = true;
7964 if (stack_realign_drap)
7966 /* Assign DRAP to vDRAP and returns vDRAP */
7967 unsigned int regno = find_drap_reg ();
7972 arg_ptr = gen_rtx_REG (Pmode, regno);
7973 crtl->drap_reg = arg_ptr;
7976 drap_vreg = copy_to_reg (arg_ptr);
7980 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7981 RTX_FRAME_RELATED_P (insn) = 1;
7988 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7991 ix86_internal_arg_pointer (void)
7993 return virtual_incoming_args_rtx;
7996 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7997 This is called from dwarf2out.c to emit call frame instructions
7998 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8000 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8002 rtx unspec = SET_SRC (pattern);
8003 gcc_assert (GET_CODE (unspec) == UNSPEC);
8007 case UNSPEC_REG_SAVE:
8008 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8009 SET_DEST (pattern));
8011 case UNSPEC_DEF_CFA:
8012 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8013 INTVAL (XVECEXP (unspec, 0, 0)));
8020 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8021 to be generated in correct form. */
8023 ix86_finalize_stack_realign_flags (void)
8025 /* Check if stack realign is really needed after reload, and
8026 stores result in cfun */
8027 unsigned int incoming_stack_boundary
8028 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8029 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8030 unsigned int stack_realign = (incoming_stack_boundary
8031 < (current_function_is_leaf
8032 ? crtl->max_used_stack_slot_alignment
8033 : crtl->stack_alignment_needed));
8035 if (crtl->stack_realign_finalized)
8037 /* After stack_realign_needed is finalized, we can't no longer
8039 gcc_assert (crtl->stack_realign_needed == stack_realign);
8043 crtl->stack_realign_needed = stack_realign;
8044 crtl->stack_realign_finalized = true;
8048 /* Expand the prologue into a bunch of separate insns. */
8051 ix86_expand_prologue (void)
8055 struct ix86_frame frame;
8056 HOST_WIDE_INT allocate;
8058 ix86_finalize_stack_realign_flags ();
8060 /* DRAP should not coexist with stack_realign_fp */
8061 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8063 ix86_compute_frame_layout (&frame);
8065 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8066 of DRAP is needed and stack realignment is really needed after reload */
8067 if (crtl->drap_reg && crtl->stack_realign_needed)
8070 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8071 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8072 ? 0 : UNITS_PER_WORD);
8074 gcc_assert (stack_realign_drap);
8076 /* Grab the argument pointer. */
8077 x = plus_constant (stack_pointer_rtx,
8078 (UNITS_PER_WORD + param_ptr_offset));
8081 /* Only need to push parameter pointer reg if it is caller
8083 if (!call_used_regs[REGNO (crtl->drap_reg)])
8085 /* Push arg pointer reg */
8086 insn = emit_insn (gen_push (y));
8087 RTX_FRAME_RELATED_P (insn) = 1;
8090 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8091 RTX_FRAME_RELATED_P (insn) = 1;
8093 /* Align the stack. */
8094 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8096 GEN_INT (-align_bytes)));
8097 RTX_FRAME_RELATED_P (insn) = 1;
8099 /* Replicate the return address on the stack so that return
8100 address can be reached via (argp - 1) slot. This is needed
8101 to implement macro RETURN_ADDR_RTX and intrinsic function
8102 expand_builtin_return_addr etc. */
8104 x = gen_frame_mem (Pmode,
8105 plus_constant (x, -UNITS_PER_WORD));
8106 insn = emit_insn (gen_push (x));
8107 RTX_FRAME_RELATED_P (insn) = 1;
8110 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8111 slower on all targets. Also sdb doesn't like it. */
8113 if (frame_pointer_needed)
8115 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8116 RTX_FRAME_RELATED_P (insn) = 1;
8118 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8119 RTX_FRAME_RELATED_P (insn) = 1;
8122 if (stack_realign_fp)
8124 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8125 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8127 /* Align the stack. */
8128 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8130 GEN_INT (-align_bytes)));
8131 RTX_FRAME_RELATED_P (insn) = 1;
8134 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8136 if (!frame.save_regs_using_mov)
8137 ix86_emit_save_regs ();
8139 allocate += frame.nregs * UNITS_PER_WORD;
8141 /* When using red zone we may start register saving before allocating
8142 the stack frame saving one cycle of the prologue. However I will
8143 avoid doing this if I am going to have to probe the stack since
8144 at least on x86_64 the stack probe can turn into a call that clobbers
8145 a red zone location */
8146 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8147 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8148 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8149 && !crtl->stack_realign_needed)
8150 ? hard_frame_pointer_rtx
8151 : stack_pointer_rtx,
8152 -frame.nregs * UNITS_PER_WORD);
8156 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8157 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8158 GEN_INT (-allocate), -1);
8161 /* Only valid for Win32. */
8162 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8166 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8168 if (cfun->machine->call_abi == MS_ABI)
8171 eax_live = ix86_eax_live_at_start_p ();
8175 emit_insn (gen_push (eax));
8176 allocate -= UNITS_PER_WORD;
8179 emit_move_insn (eax, GEN_INT (allocate));
8182 insn = gen_allocate_stack_worker_64 (eax, eax);
8184 insn = gen_allocate_stack_worker_32 (eax, eax);
8185 insn = emit_insn (insn);
8186 RTX_FRAME_RELATED_P (insn) = 1;
8187 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8188 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8189 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8190 t, REG_NOTES (insn));
8194 if (frame_pointer_needed)
8195 t = plus_constant (hard_frame_pointer_rtx,
8198 - frame.nregs * UNITS_PER_WORD);
8200 t = plus_constant (stack_pointer_rtx, allocate);
8201 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8205 if (frame.save_regs_using_mov
8206 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8207 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8209 if (!frame_pointer_needed
8210 || !frame.to_allocate
8211 || crtl->stack_realign_needed)
8212 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8214 + frame.nsseregs * 16 + frame.padding0);
8216 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8217 -frame.nregs * UNITS_PER_WORD);
8219 if (!frame_pointer_needed
8220 || !frame.to_allocate
8221 || crtl->stack_realign_needed)
8222 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8225 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8226 - frame.nregs * UNITS_PER_WORD
8227 - frame.nsseregs * 16
8230 pic_reg_used = false;
8231 if (pic_offset_table_rtx
8232 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8235 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8237 if (alt_pic_reg_used != INVALID_REGNUM)
8238 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8240 pic_reg_used = true;
8247 if (ix86_cmodel == CM_LARGE_PIC)
8249 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8250 rtx label = gen_label_rtx ();
8252 LABEL_PRESERVE_P (label) = 1;
8253 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8254 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8255 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8256 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8257 pic_offset_table_rtx, tmp_reg));
8260 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8263 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8266 /* In the pic_reg_used case, make sure that the got load isn't deleted
8267 when mcount needs it. Blockage to avoid call movement across mcount
8268 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8270 if (crtl->profile && pic_reg_used)
8271 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8273 if (crtl->drap_reg && !crtl->stack_realign_needed)
8275 /* vDRAP is setup but after reload it turns out stack realign
8276 isn't necessary, here we will emit prologue to setup DRAP
8277 without stack realign adjustment */
8278 int drap_bp_offset = UNITS_PER_WORD * 2;
8279 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8280 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8283 /* Prevent instructions from being scheduled into register save push
8284 sequence when access to the redzone area is done through frame pointer.
8285 The offset betweeh the frame pointer and the stack pointer is calculated
8286 relative to the value of the stack pointer at the end of the function
8287 prologue, and moving instructions that access redzone area via frame
8288 pointer inside push sequence violates this assumption. */
8289 if (frame_pointer_needed && frame.red_zone_size)
8290 emit_insn (gen_memory_blockage ());
8292 /* Emit cld instruction if stringops are used in the function. */
8293 if (TARGET_CLD && ix86_current_function_needs_cld)
8294 emit_insn (gen_cld ());
8297 /* Emit code to restore saved registers using MOV insns. First register
8298 is restored from POINTER + OFFSET. */
8300 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8301 int maybe_eh_return)
8304 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8306 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8307 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8309 /* Ensure that adjust_address won't be forced to produce pointer
8310 out of range allowed by x86-64 instruction set. */
8311 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8315 r11 = gen_rtx_REG (DImode, R11_REG);
8316 emit_move_insn (r11, GEN_INT (offset));
8317 emit_insn (gen_adddi3 (r11, r11, pointer));
8318 base_address = gen_rtx_MEM (Pmode, r11);
8321 emit_move_insn (gen_rtx_REG (Pmode, regno),
8322 adjust_address (base_address, Pmode, offset));
8323 offset += UNITS_PER_WORD;
8327 /* Emit code to restore saved registers using MOV insns. First register
8328 is restored from POINTER + OFFSET. */
8330 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8331 int maybe_eh_return)
8334 rtx base_address = gen_rtx_MEM (TImode, pointer);
8337 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8338 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8340 /* Ensure that adjust_address won't be forced to produce pointer
8341 out of range allowed by x86-64 instruction set. */
8342 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8346 r11 = gen_rtx_REG (DImode, R11_REG);
8347 emit_move_insn (r11, GEN_INT (offset));
8348 emit_insn (gen_adddi3 (r11, r11, pointer));
8349 base_address = gen_rtx_MEM (TImode, r11);
8352 mem = adjust_address (base_address, TImode, offset);
8353 set_mem_align (mem, 128);
8354 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8359 /* Restore function stack, frame, and registers. */
8362 ix86_expand_epilogue (int style)
8366 struct ix86_frame frame;
8367 HOST_WIDE_INT offset;
8369 ix86_finalize_stack_realign_flags ();
8371 /* When stack is realigned, SP must be valid. */
8372 sp_valid = (!frame_pointer_needed
8373 || current_function_sp_is_unchanging
8374 || stack_realign_fp);
8376 ix86_compute_frame_layout (&frame);
8378 /* See the comment about red zone and frame
8379 pointer usage in ix86_expand_prologue. */
8380 if (frame_pointer_needed && frame.red_zone_size)
8381 emit_insn (gen_memory_blockage ());
8383 /* Calculate start of saved registers relative to ebp. Special care
8384 must be taken for the normal return case of a function using
8385 eh_return: the eax and edx registers are marked as saved, but not
8386 restored along this path. */
8387 offset = frame.nregs;
8388 if (crtl->calls_eh_return && style != 2)
8390 offset *= -UNITS_PER_WORD;
8391 offset -= frame.nsseregs * 16 + frame.padding0;
8393 /* If we're only restoring one register and sp is not valid then
8394 using a move instruction to restore the register since it's
8395 less work than reloading sp and popping the register.
8397 The default code result in stack adjustment using add/lea instruction,
8398 while this code results in LEAVE instruction (or discrete equivalent),
8399 so it is profitable in some other cases as well. Especially when there
8400 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8401 and there is exactly one register to pop. This heuristic may need some
8402 tuning in future. */
8403 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8404 || (TARGET_EPILOGUE_USING_MOVE
8405 && cfun->machine->use_fast_prologue_epilogue
8406 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8407 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8408 || (frame_pointer_needed && TARGET_USE_LEAVE
8409 && cfun->machine->use_fast_prologue_epilogue
8410 && (frame.nregs + frame.nsseregs) == 1)
8411 || crtl->calls_eh_return)
8413 /* Restore registers. We can use ebp or esp to address the memory
8414 locations. If both are available, default to ebp, since offsets
8415 are known to be small. Only exception is esp pointing directly
8416 to the end of block of saved registers, where we may simplify
8419 If we are realigning stack with bp and sp, regs restore can't
8420 be addressed by bp. sp must be used instead. */
8422 if (!frame_pointer_needed
8423 || (sp_valid && !frame.to_allocate)
8424 || stack_realign_fp)
8426 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8427 frame.to_allocate, style == 2);
8428 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8430 + frame.nsseregs * 16
8431 + frame.padding0, style == 2);
8435 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8436 offset, style == 2);
8437 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8439 + frame.nsseregs * 16
8440 + frame.padding0, style == 2);
8443 /* eh_return epilogues need %ecx added to the stack pointer. */
8446 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8448 /* Stack align doesn't work with eh_return. */
8449 gcc_assert (!crtl->stack_realign_needed);
8451 if (frame_pointer_needed)
8453 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8454 tmp = plus_constant (tmp, UNITS_PER_WORD);
8455 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8457 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8458 emit_move_insn (hard_frame_pointer_rtx, tmp);
8460 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8465 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8466 tmp = plus_constant (tmp, (frame.to_allocate
8467 + frame.nregs * UNITS_PER_WORD
8468 + frame.nsseregs * 16
8470 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8473 else if (!frame_pointer_needed)
8474 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8475 GEN_INT (frame.to_allocate
8476 + frame.nregs * UNITS_PER_WORD
8477 + frame.nsseregs * 16
8480 /* If not an i386, mov & pop is faster than "leave". */
8481 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8482 || !cfun->machine->use_fast_prologue_epilogue)
8483 emit_insn ((*ix86_gen_leave) ());
8486 pro_epilogue_adjust_stack (stack_pointer_rtx,
8487 hard_frame_pointer_rtx,
8490 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8495 /* First step is to deallocate the stack frame so that we can
8498 If we realign stack with frame pointer, then stack pointer
8499 won't be able to recover via lea $offset(%bp), %sp, because
8500 there is a padding area between bp and sp for realign.
8501 "add $to_allocate, %sp" must be used instead. */
8504 gcc_assert (frame_pointer_needed);
8505 gcc_assert (!stack_realign_fp);
8506 pro_epilogue_adjust_stack (stack_pointer_rtx,
8507 hard_frame_pointer_rtx,
8508 GEN_INT (offset), style);
8509 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8510 frame.to_allocate, style == 2);
8511 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8512 GEN_INT (frame.nsseregs * 16), style);
8514 else if (frame.to_allocate || frame.nsseregs)
8516 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8519 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8520 GEN_INT (frame.to_allocate
8521 + frame.nsseregs * 16
8522 + frame.padding0), style);
8525 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8526 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8527 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8528 if (frame_pointer_needed)
8530 /* Leave results in shorter dependency chains on CPUs that are
8531 able to grok it fast. */
8532 if (TARGET_USE_LEAVE)
8533 emit_insn ((*ix86_gen_leave) ());
8536 /* For stack realigned really happens, recover stack
8537 pointer to hard frame pointer is a must, if not using
8539 if (stack_realign_fp)
8540 pro_epilogue_adjust_stack (stack_pointer_rtx,
8541 hard_frame_pointer_rtx,
8543 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8548 if (crtl->drap_reg && crtl->stack_realign_needed)
8550 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8551 ? 0 : UNITS_PER_WORD);
8552 gcc_assert (stack_realign_drap);
8553 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8555 GEN_INT (-(UNITS_PER_WORD
8556 + param_ptr_offset))));
8557 if (!call_used_regs[REGNO (crtl->drap_reg)])
8558 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8562 /* Sibcall epilogues don't want a return instruction. */
8566 if (crtl->args.pops_args && crtl->args.size)
8568 rtx popc = GEN_INT (crtl->args.pops_args);
8570 /* i386 can only pop 64K bytes. If asked to pop more, pop
8571 return address, do explicit add, and jump indirectly to the
8574 if (crtl->args.pops_args >= 65536)
8576 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8578 /* There is no "pascal" calling convention in any 64bit ABI. */
8579 gcc_assert (!TARGET_64BIT);
8581 emit_insn (gen_popsi1 (ecx));
8582 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8583 emit_jump_insn (gen_return_indirect_internal (ecx));
8586 emit_jump_insn (gen_return_pop_internal (popc));
8589 emit_jump_insn (gen_return_internal ());
8592 /* Reset from the function's potential modifications. */
8595 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8596 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8598 if (pic_offset_table_rtx)
8599 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8601 /* Mach-O doesn't support labels at the end of objects, so if
8602 it looks like we might want one, insert a NOP. */
8604 rtx insn = get_last_insn ();
8607 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8608 insn = PREV_INSN (insn);
8612 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8613 fputs ("\tnop\n", file);
8619 /* Extract the parts of an RTL expression that is a valid memory address
8620 for an instruction. Return 0 if the structure of the address is
8621 grossly off. Return -1 if the address contains ASHIFT, so it is not
8622 strictly valid, but still used for computing length of lea instruction. */
8625 ix86_decompose_address (rtx addr, struct ix86_address *out)
8627 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8628 rtx base_reg, index_reg;
8629 HOST_WIDE_INT scale = 1;
8630 rtx scale_rtx = NULL_RTX;
8632 enum ix86_address_seg seg = SEG_DEFAULT;
8634 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8636 else if (GET_CODE (addr) == PLUS)
8646 addends[n++] = XEXP (op, 1);
8649 while (GET_CODE (op) == PLUS);
8654 for (i = n; i >= 0; --i)
8657 switch (GET_CODE (op))
8662 index = XEXP (op, 0);
8663 scale_rtx = XEXP (op, 1);
8667 if (XINT (op, 1) == UNSPEC_TP
8668 && TARGET_TLS_DIRECT_SEG_REFS
8669 && seg == SEG_DEFAULT)
8670 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8699 else if (GET_CODE (addr) == MULT)
8701 index = XEXP (addr, 0); /* index*scale */
8702 scale_rtx = XEXP (addr, 1);
8704 else if (GET_CODE (addr) == ASHIFT)
8708 /* We're called for lea too, which implements ashift on occasion. */
8709 index = XEXP (addr, 0);
8710 tmp = XEXP (addr, 1);
8711 if (!CONST_INT_P (tmp))
8713 scale = INTVAL (tmp);
8714 if ((unsigned HOST_WIDE_INT) scale > 3)
8720 disp = addr; /* displacement */
8722 /* Extract the integral value of scale. */
8725 if (!CONST_INT_P (scale_rtx))
8727 scale = INTVAL (scale_rtx);
8730 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8731 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8733 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8734 if (base_reg && index_reg && scale == 1
8735 && (index_reg == arg_pointer_rtx
8736 || index_reg == frame_pointer_rtx
8737 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8740 tmp = base, base = index, index = tmp;
8741 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8744 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8745 if ((base_reg == hard_frame_pointer_rtx
8746 || base_reg == frame_pointer_rtx
8747 || base_reg == arg_pointer_rtx) && !disp)
8750 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8751 Avoid this by transforming to [%esi+0].
8752 Reload calls address legitimization without cfun defined, so we need
8753 to test cfun for being non-NULL. */
8754 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8755 && base_reg && !index_reg && !disp
8757 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8760 /* Special case: encode reg+reg instead of reg*2. */
8761 if (!base && index && scale && scale == 2)
8762 base = index, base_reg = index_reg, scale = 1;
8764 /* Special case: scaling cannot be encoded without base or displacement. */
8765 if (!base && !disp && index && scale != 1)
8777 /* Return cost of the memory address x.
8778 For i386, it is better to use a complex address than let gcc copy
8779 the address into a reg and make a new pseudo. But not if the address
8780 requires to two regs - that would mean more pseudos with longer
8783 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8785 struct ix86_address parts;
8787 int ok = ix86_decompose_address (x, &parts);
8791 if (parts.base && GET_CODE (parts.base) == SUBREG)
8792 parts.base = SUBREG_REG (parts.base);
8793 if (parts.index && GET_CODE (parts.index) == SUBREG)
8794 parts.index = SUBREG_REG (parts.index);
8796 /* Attempt to minimize number of registers in the address. */
8798 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8800 && (!REG_P (parts.index)
8801 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8805 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8807 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8808 && parts.base != parts.index)
8811 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8812 since it's predecode logic can't detect the length of instructions
8813 and it degenerates to vector decoded. Increase cost of such
8814 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8815 to split such addresses or even refuse such addresses at all.
8817 Following addressing modes are affected:
8822 The first and last case may be avoidable by explicitly coding the zero in
8823 memory address, but I don't have AMD-K6 machine handy to check this
8827 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8828 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8829 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8835 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8836 this is used for to form addresses to local data when -fPIC is in
8840 darwin_local_data_pic (rtx disp)
8842 return (GET_CODE (disp) == UNSPEC
8843 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8846 /* Determine if a given RTX is a valid constant. We already know this
8847 satisfies CONSTANT_P. */
8850 legitimate_constant_p (rtx x)
8852 switch (GET_CODE (x))
8857 if (GET_CODE (x) == PLUS)
8859 if (!CONST_INT_P (XEXP (x, 1)))
8864 if (TARGET_MACHO && darwin_local_data_pic (x))
8867 /* Only some unspecs are valid as "constants". */
8868 if (GET_CODE (x) == UNSPEC)
8869 switch (XINT (x, 1))
8874 return TARGET_64BIT;
8877 x = XVECEXP (x, 0, 0);
8878 return (GET_CODE (x) == SYMBOL_REF
8879 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8881 x = XVECEXP (x, 0, 0);
8882 return (GET_CODE (x) == SYMBOL_REF
8883 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8888 /* We must have drilled down to a symbol. */
8889 if (GET_CODE (x) == LABEL_REF)
8891 if (GET_CODE (x) != SYMBOL_REF)
8896 /* TLS symbols are never valid. */
8897 if (SYMBOL_REF_TLS_MODEL (x))
8900 /* DLLIMPORT symbols are never valid. */
8901 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8902 && SYMBOL_REF_DLLIMPORT_P (x))
8907 if (GET_MODE (x) == TImode
8908 && x != CONST0_RTX (TImode)
8914 if (x == CONST0_RTX (GET_MODE (x)))
8922 /* Otherwise we handle everything else in the move patterns. */
8926 /* Determine if it's legal to put X into the constant pool. This
8927 is not possible for the address of thread-local symbols, which
8928 is checked above. */
8931 ix86_cannot_force_const_mem (rtx x)
8933 /* We can always put integral constants and vectors in memory. */
8934 switch (GET_CODE (x))
8944 return !legitimate_constant_p (x);
8947 /* Determine if a given RTX is a valid constant address. */
8950 constant_address_p (rtx x)
8952 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8955 /* Nonzero if the constant value X is a legitimate general operand
8956 when generating PIC code. It is given that flag_pic is on and
8957 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8960 legitimate_pic_operand_p (rtx x)
8964 switch (GET_CODE (x))
8967 inner = XEXP (x, 0);
8968 if (GET_CODE (inner) == PLUS
8969 && CONST_INT_P (XEXP (inner, 1)))
8970 inner = XEXP (inner, 0);
8972 /* Only some unspecs are valid as "constants". */
8973 if (GET_CODE (inner) == UNSPEC)
8974 switch (XINT (inner, 1))
8979 return TARGET_64BIT;
8981 x = XVECEXP (inner, 0, 0);
8982 return (GET_CODE (x) == SYMBOL_REF
8983 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8984 case UNSPEC_MACHOPIC_OFFSET:
8985 return legitimate_pic_address_disp_p (x);
8993 return legitimate_pic_address_disp_p (x);
9000 /* Determine if a given CONST RTX is a valid memory displacement
9004 legitimate_pic_address_disp_p (rtx disp)
9008 /* In 64bit mode we can allow direct addresses of symbols and labels
9009 when they are not dynamic symbols. */
9012 rtx op0 = disp, op1;
9014 switch (GET_CODE (disp))
9020 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9022 op0 = XEXP (XEXP (disp, 0), 0);
9023 op1 = XEXP (XEXP (disp, 0), 1);
9024 if (!CONST_INT_P (op1)
9025 || INTVAL (op1) >= 16*1024*1024
9026 || INTVAL (op1) < -16*1024*1024)
9028 if (GET_CODE (op0) == LABEL_REF)
9030 if (GET_CODE (op0) != SYMBOL_REF)
9035 /* TLS references should always be enclosed in UNSPEC. */
9036 if (SYMBOL_REF_TLS_MODEL (op0))
9038 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9039 && ix86_cmodel != CM_LARGE_PIC)
9047 if (GET_CODE (disp) != CONST)
9049 disp = XEXP (disp, 0);
9053 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9054 of GOT tables. We should not need these anyway. */
9055 if (GET_CODE (disp) != UNSPEC
9056 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9057 && XINT (disp, 1) != UNSPEC_GOTOFF
9058 && XINT (disp, 1) != UNSPEC_PLTOFF))
9061 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9062 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9068 if (GET_CODE (disp) == PLUS)
9070 if (!CONST_INT_P (XEXP (disp, 1)))
9072 disp = XEXP (disp, 0);
9076 if (TARGET_MACHO && darwin_local_data_pic (disp))
9079 if (GET_CODE (disp) != UNSPEC)
9082 switch (XINT (disp, 1))
9087 /* We need to check for both symbols and labels because VxWorks loads
9088 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9090 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9091 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9093 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9094 While ABI specify also 32bit relocation but we don't produce it in
9095 small PIC model at all. */
9096 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9097 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9099 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9101 case UNSPEC_GOTTPOFF:
9102 case UNSPEC_GOTNTPOFF:
9103 case UNSPEC_INDNTPOFF:
9106 disp = XVECEXP (disp, 0, 0);
9107 return (GET_CODE (disp) == SYMBOL_REF
9108 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9110 disp = XVECEXP (disp, 0, 0);
9111 return (GET_CODE (disp) == SYMBOL_REF
9112 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9114 disp = XVECEXP (disp, 0, 0);
9115 return (GET_CODE (disp) == SYMBOL_REF
9116 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9122 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9123 memory address for an instruction. The MODE argument is the machine mode
9124 for the MEM expression that wants to use this address.
9126 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9127 convert common non-canonical forms to canonical form so that they will
9131 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9132 rtx addr, int strict)
9134 struct ix86_address parts;
9135 rtx base, index, disp;
9136 HOST_WIDE_INT scale;
9137 const char *reason = NULL;
9138 rtx reason_rtx = NULL_RTX;
9140 if (ix86_decompose_address (addr, &parts) <= 0)
9142 reason = "decomposition failed";
9147 index = parts.index;
9149 scale = parts.scale;
9151 /* Validate base register.
9153 Don't allow SUBREG's that span more than a word here. It can lead to spill
9154 failures when the base is one word out of a two word structure, which is
9155 represented internally as a DImode int. */
9164 else if (GET_CODE (base) == SUBREG
9165 && REG_P (SUBREG_REG (base))
9166 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9168 reg = SUBREG_REG (base);
9171 reason = "base is not a register";
9175 if (GET_MODE (base) != Pmode)
9177 reason = "base is not in Pmode";
9181 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9182 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9184 reason = "base is not valid";
9189 /* Validate index register.
9191 Don't allow SUBREG's that span more than a word here -- same as above. */
9200 else if (GET_CODE (index) == SUBREG
9201 && REG_P (SUBREG_REG (index))
9202 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9204 reg = SUBREG_REG (index);
9207 reason = "index is not a register";
9211 if (GET_MODE (index) != Pmode)
9213 reason = "index is not in Pmode";
9217 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9218 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9220 reason = "index is not valid";
9225 /* Validate scale factor. */
9228 reason_rtx = GEN_INT (scale);
9231 reason = "scale without index";
9235 if (scale != 2 && scale != 4 && scale != 8)
9237 reason = "scale is not a valid multiplier";
9242 /* Validate displacement. */
9247 if (GET_CODE (disp) == CONST
9248 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9249 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9250 switch (XINT (XEXP (disp, 0), 1))
9252 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9253 used. While ABI specify also 32bit relocations, we don't produce
9254 them at all and use IP relative instead. */
9257 gcc_assert (flag_pic);
9259 goto is_legitimate_pic;
9260 reason = "64bit address unspec";
9263 case UNSPEC_GOTPCREL:
9264 gcc_assert (flag_pic);
9265 goto is_legitimate_pic;
9267 case UNSPEC_GOTTPOFF:
9268 case UNSPEC_GOTNTPOFF:
9269 case UNSPEC_INDNTPOFF:
9275 reason = "invalid address unspec";
9279 else if (SYMBOLIC_CONST (disp)
9283 && MACHOPIC_INDIRECT
9284 && !machopic_operand_p (disp)
9290 if (TARGET_64BIT && (index || base))
9292 /* foo@dtpoff(%rX) is ok. */
9293 if (GET_CODE (disp) != CONST
9294 || GET_CODE (XEXP (disp, 0)) != PLUS
9295 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9296 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9297 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9298 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9300 reason = "non-constant pic memory reference";
9304 else if (! legitimate_pic_address_disp_p (disp))
9306 reason = "displacement is an invalid pic construct";
9310 /* This code used to verify that a symbolic pic displacement
9311 includes the pic_offset_table_rtx register.
9313 While this is good idea, unfortunately these constructs may
9314 be created by "adds using lea" optimization for incorrect
9323 This code is nonsensical, but results in addressing
9324 GOT table with pic_offset_table_rtx base. We can't
9325 just refuse it easily, since it gets matched by
9326 "addsi3" pattern, that later gets split to lea in the
9327 case output register differs from input. While this
9328 can be handled by separate addsi pattern for this case
9329 that never results in lea, this seems to be easier and
9330 correct fix for crash to disable this test. */
9332 else if (GET_CODE (disp) != LABEL_REF
9333 && !CONST_INT_P (disp)
9334 && (GET_CODE (disp) != CONST
9335 || !legitimate_constant_p (disp))
9336 && (GET_CODE (disp) != SYMBOL_REF
9337 || !legitimate_constant_p (disp)))
9339 reason = "displacement is not constant";
9342 else if (TARGET_64BIT
9343 && !x86_64_immediate_operand (disp, VOIDmode))
9345 reason = "displacement is out of range";
9350 /* Everything looks valid. */
9357 /* Return a unique alias set for the GOT. */
9359 static alias_set_type
9360 ix86_GOT_alias_set (void)
9362 static alias_set_type set = -1;
9364 set = new_alias_set ();
9368 /* Return a legitimate reference for ORIG (an address) using the
9369 register REG. If REG is 0, a new pseudo is generated.
9371 There are two types of references that must be handled:
9373 1. Global data references must load the address from the GOT, via
9374 the PIC reg. An insn is emitted to do this load, and the reg is
9377 2. Static data references, constant pool addresses, and code labels
9378 compute the address as an offset from the GOT, whose base is in
9379 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9380 differentiate them from global data objects. The returned
9381 address is the PIC reg + an unspec constant.
9383 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9384 reg also appears in the address. */
9387 legitimize_pic_address (rtx orig, rtx reg)
9394 if (TARGET_MACHO && !TARGET_64BIT)
9397 reg = gen_reg_rtx (Pmode);
9398 /* Use the generic Mach-O PIC machinery. */
9399 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9403 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9405 else if (TARGET_64BIT
9406 && ix86_cmodel != CM_SMALL_PIC
9407 && gotoff_operand (addr, Pmode))
9410 /* This symbol may be referenced via a displacement from the PIC
9411 base address (@GOTOFF). */
9413 if (reload_in_progress)
9414 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9415 if (GET_CODE (addr) == CONST)
9416 addr = XEXP (addr, 0);
9417 if (GET_CODE (addr) == PLUS)
9419 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9421 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9424 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9425 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9427 tmpreg = gen_reg_rtx (Pmode);
9430 emit_move_insn (tmpreg, new_rtx);
9434 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9435 tmpreg, 1, OPTAB_DIRECT);
9438 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9440 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9442 /* This symbol may be referenced via a displacement from the PIC
9443 base address (@GOTOFF). */
9445 if (reload_in_progress)
9446 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9447 if (GET_CODE (addr) == CONST)
9448 addr = XEXP (addr, 0);
9449 if (GET_CODE (addr) == PLUS)
9451 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9453 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9456 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9457 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9458 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9462 emit_move_insn (reg, new_rtx);
9466 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9467 /* We can't use @GOTOFF for text labels on VxWorks;
9468 see gotoff_operand. */
9469 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9471 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9473 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9474 return legitimize_dllimport_symbol (addr, true);
9475 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9476 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9477 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9479 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9480 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9484 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9486 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9487 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9488 new_rtx = gen_const_mem (Pmode, new_rtx);
9489 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9492 reg = gen_reg_rtx (Pmode);
9493 /* Use directly gen_movsi, otherwise the address is loaded
9494 into register for CSE. We don't want to CSE this addresses,
9495 instead we CSE addresses from the GOT table, so skip this. */
9496 emit_insn (gen_movsi (reg, new_rtx));
9501 /* This symbol must be referenced via a load from the
9502 Global Offset Table (@GOT). */
9504 if (reload_in_progress)
9505 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9506 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9507 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9509 new_rtx = force_reg (Pmode, new_rtx);
9510 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9511 new_rtx = gen_const_mem (Pmode, new_rtx);
9512 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9515 reg = gen_reg_rtx (Pmode);
9516 emit_move_insn (reg, new_rtx);
9522 if (CONST_INT_P (addr)
9523 && !x86_64_immediate_operand (addr, VOIDmode))
9527 emit_move_insn (reg, addr);
9531 new_rtx = force_reg (Pmode, addr);
9533 else if (GET_CODE (addr) == CONST)
9535 addr = XEXP (addr, 0);
9537 /* We must match stuff we generate before. Assume the only
9538 unspecs that can get here are ours. Not that we could do
9539 anything with them anyway.... */
9540 if (GET_CODE (addr) == UNSPEC
9541 || (GET_CODE (addr) == PLUS
9542 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9544 gcc_assert (GET_CODE (addr) == PLUS);
9546 if (GET_CODE (addr) == PLUS)
9548 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9550 /* Check first to see if this is a constant offset from a @GOTOFF
9551 symbol reference. */
9552 if (gotoff_operand (op0, Pmode)
9553 && CONST_INT_P (op1))
9557 if (reload_in_progress)
9558 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9559 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9561 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9562 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9563 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9567 emit_move_insn (reg, new_rtx);
9573 if (INTVAL (op1) < -16*1024*1024
9574 || INTVAL (op1) >= 16*1024*1024)
9576 if (!x86_64_immediate_operand (op1, Pmode))
9577 op1 = force_reg (Pmode, op1);
9578 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9584 base = legitimize_pic_address (XEXP (addr, 0), reg);
9585 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9586 base == reg ? NULL_RTX : reg);
9588 if (CONST_INT_P (new_rtx))
9589 new_rtx = plus_constant (base, INTVAL (new_rtx));
9592 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9594 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9595 new_rtx = XEXP (new_rtx, 1);
9597 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9605 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9608 get_thread_pointer (int to_reg)
9612 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9616 reg = gen_reg_rtx (Pmode);
9617 insn = gen_rtx_SET (VOIDmode, reg, tp);
9618 insn = emit_insn (insn);
9623 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9624 false if we expect this to be used for a memory address and true if
9625 we expect to load the address into a register. */
9628 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9630 rtx dest, base, off, pic, tp;
9635 case TLS_MODEL_GLOBAL_DYNAMIC:
9636 dest = gen_reg_rtx (Pmode);
9637 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9639 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9641 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9644 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9645 insns = get_insns ();
9648 RTL_CONST_CALL_P (insns) = 1;
9649 emit_libcall_block (insns, dest, rax, x);
9651 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9652 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9654 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9656 if (TARGET_GNU2_TLS)
9658 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9660 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9664 case TLS_MODEL_LOCAL_DYNAMIC:
9665 base = gen_reg_rtx (Pmode);
9666 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9668 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9670 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9673 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9674 insns = get_insns ();
9677 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9678 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9679 RTL_CONST_CALL_P (insns) = 1;
9680 emit_libcall_block (insns, base, rax, note);
9682 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9683 emit_insn (gen_tls_local_dynamic_base_64 (base));
9685 emit_insn (gen_tls_local_dynamic_base_32 (base));
9687 if (TARGET_GNU2_TLS)
9689 rtx x = ix86_tls_module_base ();
9691 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9692 gen_rtx_MINUS (Pmode, x, tp));
9695 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9696 off = gen_rtx_CONST (Pmode, off);
9698 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9700 if (TARGET_GNU2_TLS)
9702 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9704 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9709 case TLS_MODEL_INITIAL_EXEC:
9713 type = UNSPEC_GOTNTPOFF;
9717 if (reload_in_progress)
9718 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9719 pic = pic_offset_table_rtx;
9720 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9722 else if (!TARGET_ANY_GNU_TLS)
9724 pic = gen_reg_rtx (Pmode);
9725 emit_insn (gen_set_got (pic));
9726 type = UNSPEC_GOTTPOFF;
9731 type = UNSPEC_INDNTPOFF;
9734 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9735 off = gen_rtx_CONST (Pmode, off);
9737 off = gen_rtx_PLUS (Pmode, pic, off);
9738 off = gen_const_mem (Pmode, off);
9739 set_mem_alias_set (off, ix86_GOT_alias_set ());
9741 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9743 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9744 off = force_reg (Pmode, off);
9745 return gen_rtx_PLUS (Pmode, base, off);
9749 base = get_thread_pointer (true);
9750 dest = gen_reg_rtx (Pmode);
9751 emit_insn (gen_subsi3 (dest, base, off));
9755 case TLS_MODEL_LOCAL_EXEC:
9756 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9757 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9758 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9759 off = gen_rtx_CONST (Pmode, off);
9761 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9763 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9764 return gen_rtx_PLUS (Pmode, base, off);
9768 base = get_thread_pointer (true);
9769 dest = gen_reg_rtx (Pmode);
9770 emit_insn (gen_subsi3 (dest, base, off));
9781 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9784 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9785 htab_t dllimport_map;
9788 get_dllimport_decl (tree decl)
9790 struct tree_map *h, in;
9794 size_t namelen, prefixlen;
9800 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9802 in.hash = htab_hash_pointer (decl);
9803 in.base.from = decl;
9804 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9805 h = (struct tree_map *) *loc;
9809 *loc = h = GGC_NEW (struct tree_map);
9811 h->base.from = decl;
9812 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9813 DECL_ARTIFICIAL (to) = 1;
9814 DECL_IGNORED_P (to) = 1;
9815 DECL_EXTERNAL (to) = 1;
9816 TREE_READONLY (to) = 1;
9818 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9819 name = targetm.strip_name_encoding (name);
9820 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9821 ? "*__imp_" : "*__imp__";
9822 namelen = strlen (name);
9823 prefixlen = strlen (prefix);
9824 imp_name = (char *) alloca (namelen + prefixlen + 1);
9825 memcpy (imp_name, prefix, prefixlen);
9826 memcpy (imp_name + prefixlen, name, namelen + 1);
9828 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9829 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9830 SET_SYMBOL_REF_DECL (rtl, to);
9831 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9833 rtl = gen_const_mem (Pmode, rtl);
9834 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9836 SET_DECL_RTL (to, rtl);
9837 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9842 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9843 true if we require the result be a register. */
9846 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9851 gcc_assert (SYMBOL_REF_DECL (symbol));
9852 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9854 x = DECL_RTL (imp_decl);
9856 x = force_reg (Pmode, x);
9860 /* Try machine-dependent ways of modifying an illegitimate address
9861 to be legitimate. If we find one, return the new, valid address.
9862 This macro is used in only one place: `memory_address' in explow.c.
9864 OLDX is the address as it was before break_out_memory_refs was called.
9865 In some cases it is useful to look at this to decide what needs to be done.
9867 MODE and WIN are passed so that this macro can use
9868 GO_IF_LEGITIMATE_ADDRESS.
9870 It is always safe for this macro to do nothing. It exists to recognize
9871 opportunities to optimize the output.
9873 For the 80386, we handle X+REG by loading X into a register R and
9874 using R+REG. R will go in a general reg and indexing will be used.
9875 However, if REG is a broken-out memory address or multiplication,
9876 nothing needs to be done because REG can certainly go in a general reg.
9878 When -fpic is used, special handling is needed for symbolic references.
9879 See comments by legitimize_pic_address in i386.c for details. */
9882 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9887 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9889 return legitimize_tls_address (x, (enum tls_model) log, false);
9890 if (GET_CODE (x) == CONST
9891 && GET_CODE (XEXP (x, 0)) == PLUS
9892 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9893 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9895 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9896 (enum tls_model) log, false);
9897 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9900 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9902 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9903 return legitimize_dllimport_symbol (x, true);
9904 if (GET_CODE (x) == CONST
9905 && GET_CODE (XEXP (x, 0)) == PLUS
9906 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9907 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9909 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9910 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9914 if (flag_pic && SYMBOLIC_CONST (x))
9915 return legitimize_pic_address (x, 0);
9917 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9918 if (GET_CODE (x) == ASHIFT
9919 && CONST_INT_P (XEXP (x, 1))
9920 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9923 log = INTVAL (XEXP (x, 1));
9924 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9925 GEN_INT (1 << log));
9928 if (GET_CODE (x) == PLUS)
9930 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9932 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9933 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9934 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9937 log = INTVAL (XEXP (XEXP (x, 0), 1));
9938 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9939 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9940 GEN_INT (1 << log));
9943 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9944 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9945 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9948 log = INTVAL (XEXP (XEXP (x, 1), 1));
9949 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9950 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9951 GEN_INT (1 << log));
9954 /* Put multiply first if it isn't already. */
9955 if (GET_CODE (XEXP (x, 1)) == MULT)
9957 rtx tmp = XEXP (x, 0);
9958 XEXP (x, 0) = XEXP (x, 1);
9963 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9964 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9965 created by virtual register instantiation, register elimination, and
9966 similar optimizations. */
9967 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9970 x = gen_rtx_PLUS (Pmode,
9971 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9972 XEXP (XEXP (x, 1), 0)),
9973 XEXP (XEXP (x, 1), 1));
9977 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9978 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9979 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9980 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9981 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9982 && CONSTANT_P (XEXP (x, 1)))
9985 rtx other = NULL_RTX;
9987 if (CONST_INT_P (XEXP (x, 1)))
9989 constant = XEXP (x, 1);
9990 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9992 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9994 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9995 other = XEXP (x, 1);
10003 x = gen_rtx_PLUS (Pmode,
10004 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10005 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10006 plus_constant (other, INTVAL (constant)));
10010 if (changed && legitimate_address_p (mode, x, FALSE))
10013 if (GET_CODE (XEXP (x, 0)) == MULT)
10016 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10019 if (GET_CODE (XEXP (x, 1)) == MULT)
10022 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10026 && REG_P (XEXP (x, 1))
10027 && REG_P (XEXP (x, 0)))
10030 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10033 x = legitimize_pic_address (x, 0);
10036 if (changed && legitimate_address_p (mode, x, FALSE))
10039 if (REG_P (XEXP (x, 0)))
10041 rtx temp = gen_reg_rtx (Pmode);
10042 rtx val = force_operand (XEXP (x, 1), temp);
10044 emit_move_insn (temp, val);
10046 XEXP (x, 1) = temp;
10050 else if (REG_P (XEXP (x, 1)))
10052 rtx temp = gen_reg_rtx (Pmode);
10053 rtx val = force_operand (XEXP (x, 0), temp);
10055 emit_move_insn (temp, val);
10057 XEXP (x, 0) = temp;
10065 /* Print an integer constant expression in assembler syntax. Addition
10066 and subtraction are the only arithmetic that may appear in these
10067 expressions. FILE is the stdio stream to write to, X is the rtx, and
10068 CODE is the operand print code from the output string. */
10071 output_pic_addr_const (FILE *file, rtx x, int code)
10075 switch (GET_CODE (x))
10078 gcc_assert (flag_pic);
10083 if (! TARGET_MACHO || TARGET_64BIT)
10084 output_addr_const (file, x);
10087 const char *name = XSTR (x, 0);
10089 /* Mark the decl as referenced so that cgraph will
10090 output the function. */
10091 if (SYMBOL_REF_DECL (x))
10092 mark_decl_referenced (SYMBOL_REF_DECL (x));
10095 if (MACHOPIC_INDIRECT
10096 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10097 name = machopic_indirection_name (x, /*stub_p=*/true);
10099 assemble_name (file, name);
10101 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10102 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10103 fputs ("@PLT", file);
10110 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10111 assemble_name (asm_out_file, buf);
10115 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10119 /* This used to output parentheses around the expression,
10120 but that does not work on the 386 (either ATT or BSD assembler). */
10121 output_pic_addr_const (file, XEXP (x, 0), code);
10125 if (GET_MODE (x) == VOIDmode)
10127 /* We can use %d if the number is <32 bits and positive. */
10128 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10129 fprintf (file, "0x%lx%08lx",
10130 (unsigned long) CONST_DOUBLE_HIGH (x),
10131 (unsigned long) CONST_DOUBLE_LOW (x));
10133 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10136 /* We can't handle floating point constants;
10137 PRINT_OPERAND must handle them. */
10138 output_operand_lossage ("floating constant misused");
10142 /* Some assemblers need integer constants to appear first. */
10143 if (CONST_INT_P (XEXP (x, 0)))
10145 output_pic_addr_const (file, XEXP (x, 0), code);
10147 output_pic_addr_const (file, XEXP (x, 1), code);
10151 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10152 output_pic_addr_const (file, XEXP (x, 1), code);
10154 output_pic_addr_const (file, XEXP (x, 0), code);
10160 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10161 output_pic_addr_const (file, XEXP (x, 0), code);
10163 output_pic_addr_const (file, XEXP (x, 1), code);
10165 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10169 gcc_assert (XVECLEN (x, 0) == 1);
10170 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10171 switch (XINT (x, 1))
10174 fputs ("@GOT", file);
10176 case UNSPEC_GOTOFF:
10177 fputs ("@GOTOFF", file);
10179 case UNSPEC_PLTOFF:
10180 fputs ("@PLTOFF", file);
10182 case UNSPEC_GOTPCREL:
10183 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10184 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10186 case UNSPEC_GOTTPOFF:
10187 /* FIXME: This might be @TPOFF in Sun ld too. */
10188 fputs ("@GOTTPOFF", file);
10191 fputs ("@TPOFF", file);
10193 case UNSPEC_NTPOFF:
10195 fputs ("@TPOFF", file);
10197 fputs ("@NTPOFF", file);
10199 case UNSPEC_DTPOFF:
10200 fputs ("@DTPOFF", file);
10202 case UNSPEC_GOTNTPOFF:
10204 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10205 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10207 fputs ("@GOTNTPOFF", file);
10209 case UNSPEC_INDNTPOFF:
10210 fputs ("@INDNTPOFF", file);
10213 case UNSPEC_MACHOPIC_OFFSET:
10215 machopic_output_function_base_name (file);
10219 output_operand_lossage ("invalid UNSPEC as operand");
10225 output_operand_lossage ("invalid expression as operand");
10229 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10230 We need to emit DTP-relative relocations. */
10232 static void ATTRIBUTE_UNUSED
10233 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10235 fputs (ASM_LONG, file);
10236 output_addr_const (file, x);
10237 fputs ("@DTPOFF", file);
10243 fputs (", 0", file);
10246 gcc_unreachable ();
10250 /* Return true if X is a representation of the PIC register. This copes
10251 with calls from ix86_find_base_term, where the register might have
10252 been replaced by a cselib value. */
10255 ix86_pic_register_p (rtx x)
10257 if (GET_CODE (x) == VALUE)
10258 return (pic_offset_table_rtx
10259 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10261 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10264 /* In the name of slightly smaller debug output, and to cater to
10265 general assembler lossage, recognize PIC+GOTOFF and turn it back
10266 into a direct symbol reference.
10268 On Darwin, this is necessary to avoid a crash, because Darwin
10269 has a different PIC label for each routine but the DWARF debugging
10270 information is not associated with any particular routine, so it's
10271 necessary to remove references to the PIC label from RTL stored by
10272 the DWARF output code. */
10275 ix86_delegitimize_address (rtx orig_x)
10278 /* reg_addend is NULL or a multiple of some register. */
10279 rtx reg_addend = NULL_RTX;
10280 /* const_addend is NULL or a const_int. */
10281 rtx const_addend = NULL_RTX;
10282 /* This is the result, or NULL. */
10283 rtx result = NULL_RTX;
10290 if (GET_CODE (x) != CONST
10291 || GET_CODE (XEXP (x, 0)) != UNSPEC
10292 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10293 || !MEM_P (orig_x))
10295 return XVECEXP (XEXP (x, 0), 0, 0);
10298 if (GET_CODE (x) != PLUS
10299 || GET_CODE (XEXP (x, 1)) != CONST)
10302 if (ix86_pic_register_p (XEXP (x, 0)))
10303 /* %ebx + GOT/GOTOFF */
10305 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10307 /* %ebx + %reg * scale + GOT/GOTOFF */
10308 reg_addend = XEXP (x, 0);
10309 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10310 reg_addend = XEXP (reg_addend, 1);
10311 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10312 reg_addend = XEXP (reg_addend, 0);
10315 if (!REG_P (reg_addend)
10316 && GET_CODE (reg_addend) != MULT
10317 && GET_CODE (reg_addend) != ASHIFT)
10323 x = XEXP (XEXP (x, 1), 0);
10324 if (GET_CODE (x) == PLUS
10325 && CONST_INT_P (XEXP (x, 1)))
10327 const_addend = XEXP (x, 1);
10331 if (GET_CODE (x) == UNSPEC
10332 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10333 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10334 result = XVECEXP (x, 0, 0);
10336 if (TARGET_MACHO && darwin_local_data_pic (x)
10337 && !MEM_P (orig_x))
10338 result = XVECEXP (x, 0, 0);
10344 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10346 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10350 /* If X is a machine specific address (i.e. a symbol or label being
10351 referenced as a displacement from the GOT implemented using an
10352 UNSPEC), then return the base term. Otherwise return X. */
10355 ix86_find_base_term (rtx x)
10361 if (GET_CODE (x) != CONST)
10363 term = XEXP (x, 0);
10364 if (GET_CODE (term) == PLUS
10365 && (CONST_INT_P (XEXP (term, 1))
10366 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10367 term = XEXP (term, 0);
10368 if (GET_CODE (term) != UNSPEC
10369 || XINT (term, 1) != UNSPEC_GOTPCREL)
10372 return XVECEXP (term, 0, 0);
10375 return ix86_delegitimize_address (x);
10379 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10380 int fp, FILE *file)
10382 const char *suffix;
10384 if (mode == CCFPmode || mode == CCFPUmode)
10386 enum rtx_code second_code, bypass_code;
10387 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10388 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10389 code = ix86_fp_compare_code_to_integer (code);
10393 code = reverse_condition (code);
10444 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10448 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10449 Those same assemblers have the same but opposite lossage on cmov. */
10450 if (mode == CCmode)
10451 suffix = fp ? "nbe" : "a";
10452 else if (mode == CCCmode)
10455 gcc_unreachable ();
10471 gcc_unreachable ();
10475 gcc_assert (mode == CCmode || mode == CCCmode);
10492 gcc_unreachable ();
10496 /* ??? As above. */
10497 gcc_assert (mode == CCmode || mode == CCCmode);
10498 suffix = fp ? "nb" : "ae";
10501 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10505 /* ??? As above. */
10506 if (mode == CCmode)
10508 else if (mode == CCCmode)
10509 suffix = fp ? "nb" : "ae";
10511 gcc_unreachable ();
10514 suffix = fp ? "u" : "p";
10517 suffix = fp ? "nu" : "np";
10520 gcc_unreachable ();
10522 fputs (suffix, file);
10525 /* Print the name of register X to FILE based on its machine mode and number.
10526 If CODE is 'w', pretend the mode is HImode.
10527 If CODE is 'b', pretend the mode is QImode.
10528 If CODE is 'k', pretend the mode is SImode.
10529 If CODE is 'q', pretend the mode is DImode.
10530 If CODE is 'x', pretend the mode is V4SFmode.
10531 If CODE is 't', pretend the mode is V8SFmode.
10532 If CODE is 'h', pretend the reg is the 'high' byte register.
10533 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10534 If CODE is 'd', duplicate the operand for AVX instruction.
10538 print_reg (rtx x, int code, FILE *file)
10541 bool duplicated = code == 'd' && TARGET_AVX;
10543 gcc_assert (x == pc_rtx
10544 || (REGNO (x) != ARG_POINTER_REGNUM
10545 && REGNO (x) != FRAME_POINTER_REGNUM
10546 && REGNO (x) != FLAGS_REG
10547 && REGNO (x) != FPSR_REG
10548 && REGNO (x) != FPCR_REG));
10550 if (ASSEMBLER_DIALECT == ASM_ATT)
10555 gcc_assert (TARGET_64BIT);
10556 fputs ("rip", file);
10560 if (code == 'w' || MMX_REG_P (x))
10562 else if (code == 'b')
10564 else if (code == 'k')
10566 else if (code == 'q')
10568 else if (code == 'y')
10570 else if (code == 'h')
10572 else if (code == 'x')
10574 else if (code == 't')
10577 code = GET_MODE_SIZE (GET_MODE (x));
10579 /* Irritatingly, AMD extended registers use different naming convention
10580 from the normal registers. */
10581 if (REX_INT_REG_P (x))
10583 gcc_assert (TARGET_64BIT);
10587 error ("extended registers have no high halves");
10590 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10593 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10596 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10599 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10602 error ("unsupported operand size for extended register");
10612 if (STACK_TOP_P (x))
10621 if (! ANY_FP_REG_P (x))
10622 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10627 reg = hi_reg_name[REGNO (x)];
10630 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10632 reg = qi_reg_name[REGNO (x)];
10635 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10637 reg = qi_high_reg_name[REGNO (x)];
10642 gcc_assert (!duplicated);
10644 fputs (hi_reg_name[REGNO (x)] + 1, file);
10649 gcc_unreachable ();
10655 if (ASSEMBLER_DIALECT == ASM_ATT)
10656 fprintf (file, ", %%%s", reg);
10658 fprintf (file, ", %s", reg);
10662 /* Locate some local-dynamic symbol still in use by this function
10663 so that we can print its name in some tls_local_dynamic_base
10667 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10671 if (GET_CODE (x) == SYMBOL_REF
10672 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10674 cfun->machine->some_ld_name = XSTR (x, 0);
10681 static const char *
10682 get_some_local_dynamic_name (void)
10686 if (cfun->machine->some_ld_name)
10687 return cfun->machine->some_ld_name;
10689 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10691 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10692 return cfun->machine->some_ld_name;
10694 gcc_unreachable ();
10697 /* Meaning of CODE:
10698 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10699 C -- print opcode suffix for set/cmov insn.
10700 c -- like C, but print reversed condition
10701 E,e -- likewise, but for compare-and-branch fused insn.
10702 F,f -- likewise, but for floating-point.
10703 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10705 R -- print the prefix for register names.
10706 z -- print the opcode suffix for the size of the current operand.
10707 * -- print a star (in certain assembler syntax)
10708 A -- print an absolute memory reference.
10709 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10710 s -- print a shift double count, followed by the assemblers argument
10712 b -- print the QImode name of the register for the indicated operand.
10713 %b0 would print %al if operands[0] is reg 0.
10714 w -- likewise, print the HImode name of the register.
10715 k -- likewise, print the SImode name of the register.
10716 q -- likewise, print the DImode name of the register.
10717 x -- likewise, print the V4SFmode name of the register.
10718 t -- likewise, print the V8SFmode name of the register.
10719 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10720 y -- print "st(0)" instead of "st" as a register.
10721 d -- print duplicated register operand for AVX instruction.
10722 D -- print condition for SSE cmp instruction.
10723 P -- if PIC, print an @PLT suffix.
10724 X -- don't print any sort of PIC '@' suffix for a symbol.
10725 & -- print some in-use local-dynamic symbol name.
10726 H -- print a memory address offset by 8; used for sse high-parts
10727 Y -- print condition for SSE5 com* instruction.
10728 + -- print a branch hint as 'cs' or 'ds' prefix
10729 ; -- print a semicolon (after prefixes due to bug in older gas).
10733 print_operand (FILE *file, rtx x, int code)
10740 if (ASSEMBLER_DIALECT == ASM_ATT)
10745 assemble_name (file, get_some_local_dynamic_name ());
10749 switch (ASSEMBLER_DIALECT)
10756 /* Intel syntax. For absolute addresses, registers should not
10757 be surrounded by braces. */
10761 PRINT_OPERAND (file, x, 0);
10768 gcc_unreachable ();
10771 PRINT_OPERAND (file, x, 0);
10776 if (ASSEMBLER_DIALECT == ASM_ATT)
10781 if (ASSEMBLER_DIALECT == ASM_ATT)
10786 if (ASSEMBLER_DIALECT == ASM_ATT)
10791 if (ASSEMBLER_DIALECT == ASM_ATT)
10796 if (ASSEMBLER_DIALECT == ASM_ATT)
10801 if (ASSEMBLER_DIALECT == ASM_ATT)
10806 /* 387 opcodes don't get size suffixes if the operands are
10808 if (STACK_REG_P (x))
10811 /* Likewise if using Intel opcodes. */
10812 if (ASSEMBLER_DIALECT == ASM_INTEL)
10815 /* This is the size of op from size of operand. */
10816 switch (GET_MODE_SIZE (GET_MODE (x)))
10825 #ifdef HAVE_GAS_FILDS_FISTS
10835 if (GET_MODE (x) == SFmode)
10850 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10854 #ifdef GAS_MNEMONICS
10869 gcc_unreachable ();
10886 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10888 PRINT_OPERAND (file, x, 0);
10889 fputs (", ", file);
10894 /* Little bit of braindamage here. The SSE compare instructions
10895 does use completely different names for the comparisons that the
10896 fp conditional moves. */
10899 switch (GET_CODE (x))
10902 fputs ("eq", file);
10905 fputs ("eq_us", file);
10908 fputs ("lt", file);
10911 fputs ("nge", file);
10914 fputs ("le", file);
10917 fputs ("ngt", file);
10920 fputs ("unord", file);
10923 fputs ("neq", file);
10926 fputs ("neq_oq", file);
10929 fputs ("ge", file);
10932 fputs ("nlt", file);
10935 fputs ("gt", file);
10938 fputs ("nle", file);
10941 fputs ("ord", file);
10944 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10950 switch (GET_CODE (x))
10954 fputs ("eq", file);
10958 fputs ("lt", file);
10962 fputs ("le", file);
10965 fputs ("unord", file);
10969 fputs ("neq", file);
10973 fputs ("nlt", file);
10977 fputs ("nle", file);
10980 fputs ("ord", file);
10983 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10989 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10990 if (ASSEMBLER_DIALECT == ASM_ATT)
10992 switch (GET_MODE (x))
10994 case HImode: putc ('w', file); break;
10996 case SFmode: putc ('l', file); break;
10998 case DFmode: putc ('q', file); break;
10999 default: gcc_unreachable ();
11006 if (!COMPARISON_P (x))
11008 output_operand_lossage ("operand is neither a constant nor a "
11009 "condition code, invalid operand code "
11013 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11016 if (!COMPARISON_P (x))
11018 output_operand_lossage ("operand is neither a constant nor a "
11019 "condition code, invalid operand code "
11023 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11024 if (ASSEMBLER_DIALECT == ASM_ATT)
11027 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11030 /* Like above, but reverse condition */
11032 /* Check to see if argument to %c is really a constant
11033 and not a condition code which needs to be reversed. */
11034 if (!COMPARISON_P (x))
11036 output_operand_lossage ("operand is neither a constant nor a "
11037 "condition code, invalid operand "
11041 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11044 if (!COMPARISON_P (x))
11046 output_operand_lossage ("operand is neither a constant nor a "
11047 "condition code, invalid operand "
11051 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11052 if (ASSEMBLER_DIALECT == ASM_ATT)
11055 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11059 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11063 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11067 /* It doesn't actually matter what mode we use here, as we're
11068 only going to use this for printing. */
11069 x = adjust_address_nv (x, DImode, 8);
11077 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11080 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11083 int pred_val = INTVAL (XEXP (x, 0));
11085 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11086 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11088 int taken = pred_val > REG_BR_PROB_BASE / 2;
11089 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11091 /* Emit hints only in the case default branch prediction
11092 heuristics would fail. */
11093 if (taken != cputaken)
11095 /* We use 3e (DS) prefix for taken branches and
11096 2e (CS) prefix for not taken branches. */
11098 fputs ("ds ; ", file);
11100 fputs ("cs ; ", file);
11108 switch (GET_CODE (x))
11111 fputs ("neq", file);
11114 fputs ("eq", file);
11118 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11122 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11126 fputs ("le", file);
11130 fputs ("lt", file);
11133 fputs ("unord", file);
11136 fputs ("ord", file);
11139 fputs ("ueq", file);
11142 fputs ("nlt", file);
11145 fputs ("nle", file);
11148 fputs ("ule", file);
11151 fputs ("ult", file);
11154 fputs ("une", file);
11157 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11164 fputs (" ; ", file);
11171 output_operand_lossage ("invalid operand code '%c'", code);
11176 print_reg (x, code, file);
11178 else if (MEM_P (x))
11180 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11181 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11182 && GET_MODE (x) != BLKmode)
11185 switch (GET_MODE_SIZE (GET_MODE (x)))
11187 case 1: size = "BYTE"; break;
11188 case 2: size = "WORD"; break;
11189 case 4: size = "DWORD"; break;
11190 case 8: size = "QWORD"; break;
11191 case 12: size = "XWORD"; break;
11193 if (GET_MODE (x) == XFmode)
11199 gcc_unreachable ();
11202 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11205 else if (code == 'w')
11207 else if (code == 'k')
11210 fputs (size, file);
11211 fputs (" PTR ", file);
11215 /* Avoid (%rip) for call operands. */
11216 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11217 && !CONST_INT_P (x))
11218 output_addr_const (file, x);
11219 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11220 output_operand_lossage ("invalid constraints for operand");
11222 output_address (x);
11225 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11230 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11231 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11233 if (ASSEMBLER_DIALECT == ASM_ATT)
11235 fprintf (file, "0x%08lx", (long unsigned int) l);
11238 /* These float cases don't actually occur as immediate operands. */
11239 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11243 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11244 fprintf (file, "%s", dstr);
11247 else if (GET_CODE (x) == CONST_DOUBLE
11248 && GET_MODE (x) == XFmode)
11252 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11253 fprintf (file, "%s", dstr);
11258 /* We have patterns that allow zero sets of memory, for instance.
11259 In 64-bit mode, we should probably support all 8-byte vectors,
11260 since we can in fact encode that into an immediate. */
11261 if (GET_CODE (x) == CONST_VECTOR)
11263 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11269 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11271 if (ASSEMBLER_DIALECT == ASM_ATT)
11274 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11275 || GET_CODE (x) == LABEL_REF)
11277 if (ASSEMBLER_DIALECT == ASM_ATT)
11280 fputs ("OFFSET FLAT:", file);
11283 if (CONST_INT_P (x))
11284 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11286 output_pic_addr_const (file, x, code);
11288 output_addr_const (file, x);
11292 /* Print a memory operand whose address is ADDR. */
11295 print_operand_address (FILE *file, rtx addr)
11297 struct ix86_address parts;
11298 rtx base, index, disp;
11300 int ok = ix86_decompose_address (addr, &parts);
11305 index = parts.index;
11307 scale = parts.scale;
11315 if (ASSEMBLER_DIALECT == ASM_ATT)
11317 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11320 gcc_unreachable ();
11323 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11324 if (TARGET_64BIT && !base && !index)
11328 if (GET_CODE (disp) == CONST
11329 && GET_CODE (XEXP (disp, 0)) == PLUS
11330 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11331 symbol = XEXP (XEXP (disp, 0), 0);
11333 if (GET_CODE (symbol) == LABEL_REF
11334 || (GET_CODE (symbol) == SYMBOL_REF
11335 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11338 if (!base && !index)
11340 /* Displacement only requires special attention. */
11342 if (CONST_INT_P (disp))
11344 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11345 fputs ("ds:", file);
11346 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11349 output_pic_addr_const (file, disp, 0);
11351 output_addr_const (file, disp);
11355 if (ASSEMBLER_DIALECT == ASM_ATT)
11360 output_pic_addr_const (file, disp, 0);
11361 else if (GET_CODE (disp) == LABEL_REF)
11362 output_asm_label (disp);
11364 output_addr_const (file, disp);
11369 print_reg (base, 0, file);
11373 print_reg (index, 0, file);
11375 fprintf (file, ",%d", scale);
11381 rtx offset = NULL_RTX;
11385 /* Pull out the offset of a symbol; print any symbol itself. */
11386 if (GET_CODE (disp) == CONST
11387 && GET_CODE (XEXP (disp, 0)) == PLUS
11388 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11390 offset = XEXP (XEXP (disp, 0), 1);
11391 disp = gen_rtx_CONST (VOIDmode,
11392 XEXP (XEXP (disp, 0), 0));
11396 output_pic_addr_const (file, disp, 0);
11397 else if (GET_CODE (disp) == LABEL_REF)
11398 output_asm_label (disp);
11399 else if (CONST_INT_P (disp))
11402 output_addr_const (file, disp);
11408 print_reg (base, 0, file);
11411 if (INTVAL (offset) >= 0)
11413 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11417 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11424 print_reg (index, 0, file);
11426 fprintf (file, "*%d", scale);
11434 output_addr_const_extra (FILE *file, rtx x)
11438 if (GET_CODE (x) != UNSPEC)
11441 op = XVECEXP (x, 0, 0);
11442 switch (XINT (x, 1))
11444 case UNSPEC_GOTTPOFF:
11445 output_addr_const (file, op);
11446 /* FIXME: This might be @TPOFF in Sun ld. */
11447 fputs ("@GOTTPOFF", file);
11450 output_addr_const (file, op);
11451 fputs ("@TPOFF", file);
11453 case UNSPEC_NTPOFF:
11454 output_addr_const (file, op);
11456 fputs ("@TPOFF", file);
11458 fputs ("@NTPOFF", file);
11460 case UNSPEC_DTPOFF:
11461 output_addr_const (file, op);
11462 fputs ("@DTPOFF", file);
11464 case UNSPEC_GOTNTPOFF:
11465 output_addr_const (file, op);
11467 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11468 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11470 fputs ("@GOTNTPOFF", file);
11472 case UNSPEC_INDNTPOFF:
11473 output_addr_const (file, op);
11474 fputs ("@INDNTPOFF", file);
11477 case UNSPEC_MACHOPIC_OFFSET:
11478 output_addr_const (file, op);
11480 machopic_output_function_base_name (file);
11491 /* Split one or more DImode RTL references into pairs of SImode
11492 references. The RTL can be REG, offsettable MEM, integer constant, or
11493 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11494 split and "num" is its length. lo_half and hi_half are output arrays
11495 that parallel "operands". */
11498 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11502 rtx op = operands[num];
11504 /* simplify_subreg refuse to split volatile memory addresses,
11505 but we still have to handle it. */
11508 lo_half[num] = adjust_address (op, SImode, 0);
11509 hi_half[num] = adjust_address (op, SImode, 4);
11513 lo_half[num] = simplify_gen_subreg (SImode, op,
11514 GET_MODE (op) == VOIDmode
11515 ? DImode : GET_MODE (op), 0);
11516 hi_half[num] = simplify_gen_subreg (SImode, op,
11517 GET_MODE (op) == VOIDmode
11518 ? DImode : GET_MODE (op), 4);
11522 /* Split one or more TImode RTL references into pairs of DImode
11523 references. The RTL can be REG, offsettable MEM, integer constant, or
11524 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11525 split and "num" is its length. lo_half and hi_half are output arrays
11526 that parallel "operands". */
11529 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11533 rtx op = operands[num];
11535 /* simplify_subreg refuse to split volatile memory addresses, but we
11536 still have to handle it. */
11539 lo_half[num] = adjust_address (op, DImode, 0);
11540 hi_half[num] = adjust_address (op, DImode, 8);
11544 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11545 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11550 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11551 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11552 is the expression of the binary operation. The output may either be
11553 emitted here, or returned to the caller, like all output_* functions.
11555 There is no guarantee that the operands are the same mode, as they
11556 might be within FLOAT or FLOAT_EXTEND expressions. */
11558 #ifndef SYSV386_COMPAT
11559 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11560 wants to fix the assemblers because that causes incompatibility
11561 with gcc. No-one wants to fix gcc because that causes
11562 incompatibility with assemblers... You can use the option of
11563 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11564 #define SYSV386_COMPAT 1
11568 output_387_binary_op (rtx insn, rtx *operands)
11570 static char buf[40];
11573 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11575 #ifdef ENABLE_CHECKING
11576 /* Even if we do not want to check the inputs, this documents input
11577 constraints. Which helps in understanding the following code. */
11578 if (STACK_REG_P (operands[0])
11579 && ((REG_P (operands[1])
11580 && REGNO (operands[0]) == REGNO (operands[1])
11581 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11582 || (REG_P (operands[2])
11583 && REGNO (operands[0]) == REGNO (operands[2])
11584 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11585 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11588 gcc_assert (is_sse);
11591 switch (GET_CODE (operands[3]))
11594 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11595 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11603 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11604 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11612 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11613 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11621 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11622 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11630 gcc_unreachable ();
11637 strcpy (buf, ssep);
11638 if (GET_MODE (operands[0]) == SFmode)
11639 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11641 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11645 strcpy (buf, ssep + 1);
11646 if (GET_MODE (operands[0]) == SFmode)
11647 strcat (buf, "ss\t{%2, %0|%0, %2}");
11649 strcat (buf, "sd\t{%2, %0|%0, %2}");
11655 switch (GET_CODE (operands[3]))
11659 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11661 rtx temp = operands[2];
11662 operands[2] = operands[1];
11663 operands[1] = temp;
11666 /* know operands[0] == operands[1]. */
11668 if (MEM_P (operands[2]))
11674 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11676 if (STACK_TOP_P (operands[0]))
11677 /* How is it that we are storing to a dead operand[2]?
11678 Well, presumably operands[1] is dead too. We can't
11679 store the result to st(0) as st(0) gets popped on this
11680 instruction. Instead store to operands[2] (which I
11681 think has to be st(1)). st(1) will be popped later.
11682 gcc <= 2.8.1 didn't have this check and generated
11683 assembly code that the Unixware assembler rejected. */
11684 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11686 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11690 if (STACK_TOP_P (operands[0]))
11691 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11693 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11698 if (MEM_P (operands[1]))
11704 if (MEM_P (operands[2]))
11710 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11713 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11714 derived assemblers, confusingly reverse the direction of
11715 the operation for fsub{r} and fdiv{r} when the
11716 destination register is not st(0). The Intel assembler
11717 doesn't have this brain damage. Read !SYSV386_COMPAT to
11718 figure out what the hardware really does. */
11719 if (STACK_TOP_P (operands[0]))
11720 p = "{p\t%0, %2|rp\t%2, %0}";
11722 p = "{rp\t%2, %0|p\t%0, %2}";
11724 if (STACK_TOP_P (operands[0]))
11725 /* As above for fmul/fadd, we can't store to st(0). */
11726 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11728 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11733 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11736 if (STACK_TOP_P (operands[0]))
11737 p = "{rp\t%0, %1|p\t%1, %0}";
11739 p = "{p\t%1, %0|rp\t%0, %1}";
11741 if (STACK_TOP_P (operands[0]))
11742 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11744 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11749 if (STACK_TOP_P (operands[0]))
11751 if (STACK_TOP_P (operands[1]))
11752 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11754 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11757 else if (STACK_TOP_P (operands[1]))
11760 p = "{\t%1, %0|r\t%0, %1}";
11762 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11768 p = "{r\t%2, %0|\t%0, %2}";
11770 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11776 gcc_unreachable ();
11783 /* Return needed mode for entity in optimize_mode_switching pass. */
11786 ix86_mode_needed (int entity, rtx insn)
11788 enum attr_i387_cw mode;
11790 /* The mode UNINITIALIZED is used to store control word after a
11791 function call or ASM pattern. The mode ANY specify that function
11792 has no requirements on the control word and make no changes in the
11793 bits we are interested in. */
11796 || (NONJUMP_INSN_P (insn)
11797 && (asm_noperands (PATTERN (insn)) >= 0
11798 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11799 return I387_CW_UNINITIALIZED;
11801 if (recog_memoized (insn) < 0)
11802 return I387_CW_ANY;
11804 mode = get_attr_i387_cw (insn);
11809 if (mode == I387_CW_TRUNC)
11814 if (mode == I387_CW_FLOOR)
11819 if (mode == I387_CW_CEIL)
11824 if (mode == I387_CW_MASK_PM)
11829 gcc_unreachable ();
11832 return I387_CW_ANY;
11835 /* Output code to initialize control word copies used by trunc?f?i and
11836 rounding patterns. CURRENT_MODE is set to current control word,
11837 while NEW_MODE is set to new control word. */
11840 emit_i387_cw_initialization (int mode)
11842 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11845 enum ix86_stack_slot slot;
11847 rtx reg = gen_reg_rtx (HImode);
11849 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11850 emit_move_insn (reg, copy_rtx (stored_mode));
11852 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11853 || optimize_function_for_size_p (cfun))
11857 case I387_CW_TRUNC:
11858 /* round toward zero (truncate) */
11859 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11860 slot = SLOT_CW_TRUNC;
11863 case I387_CW_FLOOR:
11864 /* round down toward -oo */
11865 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11866 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11867 slot = SLOT_CW_FLOOR;
11871 /* round up toward +oo */
11872 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11873 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11874 slot = SLOT_CW_CEIL;
11877 case I387_CW_MASK_PM:
11878 /* mask precision exception for nearbyint() */
11879 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11880 slot = SLOT_CW_MASK_PM;
11884 gcc_unreachable ();
11891 case I387_CW_TRUNC:
11892 /* round toward zero (truncate) */
11893 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11894 slot = SLOT_CW_TRUNC;
11897 case I387_CW_FLOOR:
11898 /* round down toward -oo */
11899 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11900 slot = SLOT_CW_FLOOR;
11904 /* round up toward +oo */
11905 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11906 slot = SLOT_CW_CEIL;
11909 case I387_CW_MASK_PM:
11910 /* mask precision exception for nearbyint() */
11911 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11912 slot = SLOT_CW_MASK_PM;
11916 gcc_unreachable ();
11920 gcc_assert (slot < MAX_386_STACK_LOCALS);
11922 new_mode = assign_386_stack_local (HImode, slot);
11923 emit_move_insn (new_mode, reg);
11926 /* Output code for INSN to convert a float to a signed int. OPERANDS
11927 are the insn operands. The output may be [HSD]Imode and the input
11928 operand may be [SDX]Fmode. */
11931 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11933 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11934 int dimode_p = GET_MODE (operands[0]) == DImode;
11935 int round_mode = get_attr_i387_cw (insn);
11937 /* Jump through a hoop or two for DImode, since the hardware has no
11938 non-popping instruction. We used to do this a different way, but
11939 that was somewhat fragile and broke with post-reload splitters. */
11940 if ((dimode_p || fisttp) && !stack_top_dies)
11941 output_asm_insn ("fld\t%y1", operands);
11943 gcc_assert (STACK_TOP_P (operands[1]));
11944 gcc_assert (MEM_P (operands[0]));
11945 gcc_assert (GET_MODE (operands[1]) != TFmode);
11948 output_asm_insn ("fisttp%z0\t%0", operands);
11951 if (round_mode != I387_CW_ANY)
11952 output_asm_insn ("fldcw\t%3", operands);
11953 if (stack_top_dies || dimode_p)
11954 output_asm_insn ("fistp%z0\t%0", operands);
11956 output_asm_insn ("fist%z0\t%0", operands);
11957 if (round_mode != I387_CW_ANY)
11958 output_asm_insn ("fldcw\t%2", operands);
11964 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11965 have the values zero or one, indicates the ffreep insn's operand
11966 from the OPERANDS array. */
11968 static const char *
11969 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11971 if (TARGET_USE_FFREEP)
11972 #if HAVE_AS_IX86_FFREEP
11973 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11976 static char retval[] = ".word\t0xc_df";
11977 int regno = REGNO (operands[opno]);
11979 gcc_assert (FP_REGNO_P (regno));
11981 retval[9] = '0' + (regno - FIRST_STACK_REG);
11986 return opno ? "fstp\t%y1" : "fstp\t%y0";
11990 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11991 should be used. UNORDERED_P is true when fucom should be used. */
11994 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11996 int stack_top_dies;
11997 rtx cmp_op0, cmp_op1;
11998 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12002 cmp_op0 = operands[0];
12003 cmp_op1 = operands[1];
12007 cmp_op0 = operands[1];
12008 cmp_op1 = operands[2];
12013 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12014 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12015 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12016 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12018 if (GET_MODE (operands[0]) == SFmode)
12020 return &ucomiss[TARGET_AVX ? 0 : 1];
12022 return &comiss[TARGET_AVX ? 0 : 1];
12025 return &ucomisd[TARGET_AVX ? 0 : 1];
12027 return &comisd[TARGET_AVX ? 0 : 1];
12030 gcc_assert (STACK_TOP_P (cmp_op0));
12032 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12034 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12036 if (stack_top_dies)
12038 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12039 return output_387_ffreep (operands, 1);
12042 return "ftst\n\tfnstsw\t%0";
12045 if (STACK_REG_P (cmp_op1)
12047 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12048 && REGNO (cmp_op1) != FIRST_STACK_REG)
12050 /* If both the top of the 387 stack dies, and the other operand
12051 is also a stack register that dies, then this must be a
12052 `fcompp' float compare */
12056 /* There is no double popping fcomi variant. Fortunately,
12057 eflags is immune from the fstp's cc clobbering. */
12059 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12061 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12062 return output_387_ffreep (operands, 0);
12067 return "fucompp\n\tfnstsw\t%0";
12069 return "fcompp\n\tfnstsw\t%0";
12074 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12076 static const char * const alt[16] =
12078 "fcom%z2\t%y2\n\tfnstsw\t%0",
12079 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12080 "fucom%z2\t%y2\n\tfnstsw\t%0",
12081 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12083 "ficom%z2\t%y2\n\tfnstsw\t%0",
12084 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12088 "fcomi\t{%y1, %0|%0, %y1}",
12089 "fcomip\t{%y1, %0|%0, %y1}",
12090 "fucomi\t{%y1, %0|%0, %y1}",
12091 "fucomip\t{%y1, %0|%0, %y1}",
12102 mask = eflags_p << 3;
12103 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12104 mask |= unordered_p << 1;
12105 mask |= stack_top_dies;
12107 gcc_assert (mask < 16);
12116 ix86_output_addr_vec_elt (FILE *file, int value)
12118 const char *directive = ASM_LONG;
12122 directive = ASM_QUAD;
12124 gcc_assert (!TARGET_64BIT);
12127 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12131 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12133 const char *directive = ASM_LONG;
12136 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12137 directive = ASM_QUAD;
12139 gcc_assert (!TARGET_64BIT);
12141 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12142 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12143 fprintf (file, "%s%s%d-%s%d\n",
12144 directive, LPREFIX, value, LPREFIX, rel);
12145 else if (HAVE_AS_GOTOFF_IN_DATA)
12146 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12148 else if (TARGET_MACHO)
12150 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12151 machopic_output_function_base_name (file);
12152 fprintf(file, "\n");
12156 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12157 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12160 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12164 ix86_expand_clear (rtx dest)
12168 /* We play register width games, which are only valid after reload. */
12169 gcc_assert (reload_completed);
12171 /* Avoid HImode and its attendant prefix byte. */
12172 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12173 dest = gen_rtx_REG (SImode, REGNO (dest));
12174 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12176 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12177 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12179 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12180 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12186 /* X is an unchanging MEM. If it is a constant pool reference, return
12187 the constant pool rtx, else NULL. */
12190 maybe_get_pool_constant (rtx x)
12192 x = ix86_delegitimize_address (XEXP (x, 0));
12194 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12195 return get_pool_constant (x);
12201 ix86_expand_move (enum machine_mode mode, rtx operands[])
12204 enum tls_model model;
12209 if (GET_CODE (op1) == SYMBOL_REF)
12211 model = SYMBOL_REF_TLS_MODEL (op1);
12214 op1 = legitimize_tls_address (op1, model, true);
12215 op1 = force_operand (op1, op0);
12219 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12220 && SYMBOL_REF_DLLIMPORT_P (op1))
12221 op1 = legitimize_dllimport_symbol (op1, false);
12223 else if (GET_CODE (op1) == CONST
12224 && GET_CODE (XEXP (op1, 0)) == PLUS
12225 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12227 rtx addend = XEXP (XEXP (op1, 0), 1);
12228 rtx symbol = XEXP (XEXP (op1, 0), 0);
12231 model = SYMBOL_REF_TLS_MODEL (symbol);
12233 tmp = legitimize_tls_address (symbol, model, true);
12234 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12235 && SYMBOL_REF_DLLIMPORT_P (symbol))
12236 tmp = legitimize_dllimport_symbol (symbol, true);
12240 tmp = force_operand (tmp, NULL);
12241 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12242 op0, 1, OPTAB_DIRECT);
12248 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12250 if (TARGET_MACHO && !TARGET_64BIT)
12255 rtx temp = ((reload_in_progress
12256 || ((op0 && REG_P (op0))
12258 ? op0 : gen_reg_rtx (Pmode));
12259 op1 = machopic_indirect_data_reference (op1, temp);
12260 op1 = machopic_legitimize_pic_address (op1, mode,
12261 temp == op1 ? 0 : temp);
12263 else if (MACHOPIC_INDIRECT)
12264 op1 = machopic_indirect_data_reference (op1, 0);
12272 op1 = force_reg (Pmode, op1);
12273 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12275 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12276 op1 = legitimize_pic_address (op1, reg);
12285 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12286 || !push_operand (op0, mode))
12288 op1 = force_reg (mode, op1);
12290 if (push_operand (op0, mode)
12291 && ! general_no_elim_operand (op1, mode))
12292 op1 = copy_to_mode_reg (mode, op1);
12294 /* Force large constants in 64bit compilation into register
12295 to get them CSEed. */
12296 if (can_create_pseudo_p ()
12297 && (mode == DImode) && TARGET_64BIT
12298 && immediate_operand (op1, mode)
12299 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12300 && !register_operand (op0, mode)
12302 op1 = copy_to_mode_reg (mode, op1);
12304 if (can_create_pseudo_p ()
12305 && FLOAT_MODE_P (mode)
12306 && GET_CODE (op1) == CONST_DOUBLE)
12308 /* If we are loading a floating point constant to a register,
12309 force the value to memory now, since we'll get better code
12310 out the back end. */
12312 op1 = validize_mem (force_const_mem (mode, op1));
12313 if (!register_operand (op0, mode))
12315 rtx temp = gen_reg_rtx (mode);
12316 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12317 emit_move_insn (op0, temp);
12323 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12327 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12329 rtx op0 = operands[0], op1 = operands[1];
12330 unsigned int align = GET_MODE_ALIGNMENT (mode);
12332 /* Force constants other than zero into memory. We do not know how
12333 the instructions used to build constants modify the upper 64 bits
12334 of the register, once we have that information we may be able
12335 to handle some of them more efficiently. */
12336 if (can_create_pseudo_p ()
12337 && register_operand (op0, mode)
12338 && (CONSTANT_P (op1)
12339 || (GET_CODE (op1) == SUBREG
12340 && CONSTANT_P (SUBREG_REG (op1))))
12341 && standard_sse_constant_p (op1) <= 0)
12342 op1 = validize_mem (force_const_mem (mode, op1));
12344 /* We need to check memory alignment for SSE mode since attribute
12345 can make operands unaligned. */
12346 if (can_create_pseudo_p ()
12347 && SSE_REG_MODE_P (mode)
12348 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12349 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12353 /* ix86_expand_vector_move_misalign() does not like constants ... */
12354 if (CONSTANT_P (op1)
12355 || (GET_CODE (op1) == SUBREG
12356 && CONSTANT_P (SUBREG_REG (op1))))
12357 op1 = validize_mem (force_const_mem (mode, op1));
12359 /* ... nor both arguments in memory. */
12360 if (!register_operand (op0, mode)
12361 && !register_operand (op1, mode))
12362 op1 = force_reg (mode, op1);
12364 tmp[0] = op0; tmp[1] = op1;
12365 ix86_expand_vector_move_misalign (mode, tmp);
12369 /* Make operand1 a register if it isn't already. */
12370 if (can_create_pseudo_p ()
12371 && !register_operand (op0, mode)
12372 && !register_operand (op1, mode))
12374 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12378 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12381 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12382 straight to ix86_expand_vector_move. */
12383 /* Code generation for scalar reg-reg moves of single and double precision data:
12384 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12388 if (x86_sse_partial_reg_dependency == true)
12393 Code generation for scalar loads of double precision data:
12394 if (x86_sse_split_regs == true)
12395 movlpd mem, reg (gas syntax)
12399 Code generation for unaligned packed loads of single precision data
12400 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12401 if (x86_sse_unaligned_move_optimal)
12404 if (x86_sse_partial_reg_dependency == true)
12416 Code generation for unaligned packed loads of double precision data
12417 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12418 if (x86_sse_unaligned_move_optimal)
12421 if (x86_sse_split_regs == true)
12434 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12443 switch (GET_MODE_CLASS (mode))
12445 case MODE_VECTOR_INT:
12447 switch (GET_MODE_SIZE (mode))
12450 op0 = gen_lowpart (V16QImode, op0);
12451 op1 = gen_lowpart (V16QImode, op1);
12452 emit_insn (gen_avx_movdqu (op0, op1));
12455 op0 = gen_lowpart (V32QImode, op0);
12456 op1 = gen_lowpart (V32QImode, op1);
12457 emit_insn (gen_avx_movdqu256 (op0, op1));
12460 gcc_unreachable ();
12463 case MODE_VECTOR_FLOAT:
12464 op0 = gen_lowpart (mode, op0);
12465 op1 = gen_lowpart (mode, op1);
12470 emit_insn (gen_avx_movups (op0, op1));
12473 emit_insn (gen_avx_movups256 (op0, op1));
12476 emit_insn (gen_avx_movupd (op0, op1));
12479 emit_insn (gen_avx_movupd256 (op0, op1));
12482 gcc_unreachable ();
12487 gcc_unreachable ();
12495 /* If we're optimizing for size, movups is the smallest. */
12496 if (optimize_insn_for_size_p ())
12498 op0 = gen_lowpart (V4SFmode, op0);
12499 op1 = gen_lowpart (V4SFmode, op1);
12500 emit_insn (gen_sse_movups (op0, op1));
12504 /* ??? If we have typed data, then it would appear that using
12505 movdqu is the only way to get unaligned data loaded with
12507 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12509 op0 = gen_lowpart (V16QImode, op0);
12510 op1 = gen_lowpart (V16QImode, op1);
12511 emit_insn (gen_sse2_movdqu (op0, op1));
12515 if (TARGET_SSE2 && mode == V2DFmode)
12519 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12521 op0 = gen_lowpart (V2DFmode, op0);
12522 op1 = gen_lowpart (V2DFmode, op1);
12523 emit_insn (gen_sse2_movupd (op0, op1));
12527 /* When SSE registers are split into halves, we can avoid
12528 writing to the top half twice. */
12529 if (TARGET_SSE_SPLIT_REGS)
12531 emit_clobber (op0);
12536 /* ??? Not sure about the best option for the Intel chips.
12537 The following would seem to satisfy; the register is
12538 entirely cleared, breaking the dependency chain. We
12539 then store to the upper half, with a dependency depth
12540 of one. A rumor has it that Intel recommends two movsd
12541 followed by an unpacklpd, but this is unconfirmed. And
12542 given that the dependency depth of the unpacklpd would
12543 still be one, I'm not sure why this would be better. */
12544 zero = CONST0_RTX (V2DFmode);
12547 m = adjust_address (op1, DFmode, 0);
12548 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12549 m = adjust_address (op1, DFmode, 8);
12550 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12554 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12556 op0 = gen_lowpart (V4SFmode, op0);
12557 op1 = gen_lowpart (V4SFmode, op1);
12558 emit_insn (gen_sse_movups (op0, op1));
12562 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12563 emit_move_insn (op0, CONST0_RTX (mode));
12565 emit_clobber (op0);
12567 if (mode != V4SFmode)
12568 op0 = gen_lowpart (V4SFmode, op0);
12569 m = adjust_address (op1, V2SFmode, 0);
12570 emit_insn (gen_sse_loadlps (op0, op0, m));
12571 m = adjust_address (op1, V2SFmode, 8);
12572 emit_insn (gen_sse_loadhps (op0, op0, m));
12575 else if (MEM_P (op0))
12577 /* If we're optimizing for size, movups is the smallest. */
12578 if (optimize_insn_for_size_p ())
12580 op0 = gen_lowpart (V4SFmode, op0);
12581 op1 = gen_lowpart (V4SFmode, op1);
12582 emit_insn (gen_sse_movups (op0, op1));
12586 /* ??? Similar to above, only less clear because of quote
12587 typeless stores unquote. */
12588 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12589 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12591 op0 = gen_lowpart (V16QImode, op0);
12592 op1 = gen_lowpart (V16QImode, op1);
12593 emit_insn (gen_sse2_movdqu (op0, op1));
12597 if (TARGET_SSE2 && mode == V2DFmode)
12599 m = adjust_address (op0, DFmode, 0);
12600 emit_insn (gen_sse2_storelpd (m, op1));
12601 m = adjust_address (op0, DFmode, 8);
12602 emit_insn (gen_sse2_storehpd (m, op1));
12606 if (mode != V4SFmode)
12607 op1 = gen_lowpart (V4SFmode, op1);
12608 m = adjust_address (op0, V2SFmode, 0);
12609 emit_insn (gen_sse_storelps (m, op1));
12610 m = adjust_address (op0, V2SFmode, 8);
12611 emit_insn (gen_sse_storehps (m, op1));
12615 gcc_unreachable ();
12618 /* Expand a push in MODE. This is some mode for which we do not support
12619 proper push instructions, at least from the registers that we expect
12620 the value to live in. */
12623 ix86_expand_push (enum machine_mode mode, rtx x)
12627 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12628 GEN_INT (-GET_MODE_SIZE (mode)),
12629 stack_pointer_rtx, 1, OPTAB_DIRECT);
12630 if (tmp != stack_pointer_rtx)
12631 emit_move_insn (stack_pointer_rtx, tmp);
12633 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12635 /* When we push an operand onto stack, it has to be aligned at least
12636 at the function argument boundary. */
12637 set_mem_align (tmp,
12638 ix86_function_arg_boundary (mode, NULL_TREE));
12640 emit_move_insn (tmp, x);
12643 /* Helper function of ix86_fixup_binary_operands to canonicalize
12644 operand order. Returns true if the operands should be swapped. */
12647 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12650 rtx dst = operands[0];
12651 rtx src1 = operands[1];
12652 rtx src2 = operands[2];
12654 /* If the operation is not commutative, we can't do anything. */
12655 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12658 /* Highest priority is that src1 should match dst. */
12659 if (rtx_equal_p (dst, src1))
12661 if (rtx_equal_p (dst, src2))
12664 /* Next highest priority is that immediate constants come second. */
12665 if (immediate_operand (src2, mode))
12667 if (immediate_operand (src1, mode))
12670 /* Lowest priority is that memory references should come second. */
12680 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12681 destination to use for the operation. If different from the true
12682 destination in operands[0], a copy operation will be required. */
12685 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12688 rtx dst = operands[0];
12689 rtx src1 = operands[1];
12690 rtx src2 = operands[2];
12692 /* Canonicalize operand order. */
12693 if (ix86_swap_binary_operands_p (code, mode, operands))
12697 /* It is invalid to swap operands of different modes. */
12698 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12705 /* Both source operands cannot be in memory. */
12706 if (MEM_P (src1) && MEM_P (src2))
12708 /* Optimization: Only read from memory once. */
12709 if (rtx_equal_p (src1, src2))
12711 src2 = force_reg (mode, src2);
12715 src2 = force_reg (mode, src2);
12718 /* If the destination is memory, and we do not have matching source
12719 operands, do things in registers. */
12720 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12721 dst = gen_reg_rtx (mode);
12723 /* Source 1 cannot be a constant. */
12724 if (CONSTANT_P (src1))
12725 src1 = force_reg (mode, src1);
12727 /* Source 1 cannot be a non-matching memory. */
12728 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12729 src1 = force_reg (mode, src1);
12731 operands[1] = src1;
12732 operands[2] = src2;
12736 /* Similarly, but assume that the destination has already been
12737 set up properly. */
12740 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12741 enum machine_mode mode, rtx operands[])
12743 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12744 gcc_assert (dst == operands[0]);
12747 /* Attempt to expand a binary operator. Make the expansion closer to the
12748 actual machine, then just general_operand, which will allow 3 separate
12749 memory references (one output, two input) in a single insn. */
12752 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12755 rtx src1, src2, dst, op, clob;
12757 dst = ix86_fixup_binary_operands (code, mode, operands);
12758 src1 = operands[1];
12759 src2 = operands[2];
12761 /* Emit the instruction. */
12763 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12764 if (reload_in_progress)
12766 /* Reload doesn't know about the flags register, and doesn't know that
12767 it doesn't want to clobber it. We can only do this with PLUS. */
12768 gcc_assert (code == PLUS);
12773 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12774 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12777 /* Fix up the destination if needed. */
12778 if (dst != operands[0])
12779 emit_move_insn (operands[0], dst);
12782 /* Return TRUE or FALSE depending on whether the binary operator meets the
12783 appropriate constraints. */
12786 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12789 rtx dst = operands[0];
12790 rtx src1 = operands[1];
12791 rtx src2 = operands[2];
12793 /* Both source operands cannot be in memory. */
12794 if (MEM_P (src1) && MEM_P (src2))
12797 /* Canonicalize operand order for commutative operators. */
12798 if (ix86_swap_binary_operands_p (code, mode, operands))
12805 /* If the destination is memory, we must have a matching source operand. */
12806 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12809 /* Source 1 cannot be a constant. */
12810 if (CONSTANT_P (src1))
12813 /* Source 1 cannot be a non-matching memory. */
12814 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12820 /* Attempt to expand a unary operator. Make the expansion closer to the
12821 actual machine, then just general_operand, which will allow 2 separate
12822 memory references (one output, one input) in a single insn. */
12825 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12828 int matching_memory;
12829 rtx src, dst, op, clob;
12834 /* If the destination is memory, and we do not have matching source
12835 operands, do things in registers. */
12836 matching_memory = 0;
12839 if (rtx_equal_p (dst, src))
12840 matching_memory = 1;
12842 dst = gen_reg_rtx (mode);
12845 /* When source operand is memory, destination must match. */
12846 if (MEM_P (src) && !matching_memory)
12847 src = force_reg (mode, src);
12849 /* Emit the instruction. */
12851 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12852 if (reload_in_progress || code == NOT)
12854 /* Reload doesn't know about the flags register, and doesn't know that
12855 it doesn't want to clobber it. */
12856 gcc_assert (code == NOT);
12861 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12862 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12865 /* Fix up the destination if needed. */
12866 if (dst != operands[0])
12867 emit_move_insn (operands[0], dst);
12870 /* Return TRUE or FALSE depending on whether the unary operator meets the
12871 appropriate constraints. */
12874 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12875 enum machine_mode mode ATTRIBUTE_UNUSED,
12876 rtx operands[2] ATTRIBUTE_UNUSED)
12878 /* If one of operands is memory, source and destination must match. */
12879 if ((MEM_P (operands[0])
12880 || MEM_P (operands[1]))
12881 && ! rtx_equal_p (operands[0], operands[1]))
12886 /* Post-reload splitter for converting an SF or DFmode value in an
12887 SSE register into an unsigned SImode. */
12890 ix86_split_convert_uns_si_sse (rtx operands[])
12892 enum machine_mode vecmode;
12893 rtx value, large, zero_or_two31, input, two31, x;
12895 large = operands[1];
12896 zero_or_two31 = operands[2];
12897 input = operands[3];
12898 two31 = operands[4];
12899 vecmode = GET_MODE (large);
12900 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12902 /* Load up the value into the low element. We must ensure that the other
12903 elements are valid floats -- zero is the easiest such value. */
12906 if (vecmode == V4SFmode)
12907 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12909 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12913 input = gen_rtx_REG (vecmode, REGNO (input));
12914 emit_move_insn (value, CONST0_RTX (vecmode));
12915 if (vecmode == V4SFmode)
12916 emit_insn (gen_sse_movss (value, value, input));
12918 emit_insn (gen_sse2_movsd (value, value, input));
12921 emit_move_insn (large, two31);
12922 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12924 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12925 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12927 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12928 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12930 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12931 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12933 large = gen_rtx_REG (V4SImode, REGNO (large));
12934 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12936 x = gen_rtx_REG (V4SImode, REGNO (value));
12937 if (vecmode == V4SFmode)
12938 emit_insn (gen_sse2_cvttps2dq (x, value));
12940 emit_insn (gen_sse2_cvttpd2dq (x, value));
12943 emit_insn (gen_xorv4si3 (value, value, large));
12946 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12947 Expects the 64-bit DImode to be supplied in a pair of integral
12948 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12949 -mfpmath=sse, !optimize_size only. */
12952 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12954 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12955 rtx int_xmm, fp_xmm;
12956 rtx biases, exponents;
12959 int_xmm = gen_reg_rtx (V4SImode);
12960 if (TARGET_INTER_UNIT_MOVES)
12961 emit_insn (gen_movdi_to_sse (int_xmm, input));
12962 else if (TARGET_SSE_SPLIT_REGS)
12964 emit_clobber (int_xmm);
12965 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12969 x = gen_reg_rtx (V2DImode);
12970 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12971 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12974 x = gen_rtx_CONST_VECTOR (V4SImode,
12975 gen_rtvec (4, GEN_INT (0x43300000UL),
12976 GEN_INT (0x45300000UL),
12977 const0_rtx, const0_rtx));
12978 exponents = validize_mem (force_const_mem (V4SImode, x));
12980 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12981 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12983 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12984 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12985 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12986 (0x1.0p84 + double(fp_value_hi_xmm)).
12987 Note these exponents differ by 32. */
12989 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12991 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12992 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12993 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12994 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12995 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12996 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12997 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12998 biases = validize_mem (force_const_mem (V2DFmode, biases));
12999 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13001 /* Add the upper and lower DFmode values together. */
13003 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13006 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13007 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13008 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13011 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13014 /* Not used, but eases macroization of patterns. */
13016 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13017 rtx input ATTRIBUTE_UNUSED)
13019 gcc_unreachable ();
13022 /* Convert an unsigned SImode value into a DFmode. Only currently used
13023 for SSE, but applicable anywhere. */
13026 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13028 REAL_VALUE_TYPE TWO31r;
13031 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13032 NULL, 1, OPTAB_DIRECT);
13034 fp = gen_reg_rtx (DFmode);
13035 emit_insn (gen_floatsidf2 (fp, x));
13037 real_ldexp (&TWO31r, &dconst1, 31);
13038 x = const_double_from_real_value (TWO31r, DFmode);
13040 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13042 emit_move_insn (target, x);
13045 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13046 32-bit mode; otherwise we have a direct convert instruction. */
13049 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13051 REAL_VALUE_TYPE TWO32r;
13052 rtx fp_lo, fp_hi, x;
13054 fp_lo = gen_reg_rtx (DFmode);
13055 fp_hi = gen_reg_rtx (DFmode);
13057 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13059 real_ldexp (&TWO32r, &dconst1, 32);
13060 x = const_double_from_real_value (TWO32r, DFmode);
13061 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13063 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13065 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13068 emit_move_insn (target, x);
13071 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13072 For x86_32, -mfpmath=sse, !optimize_size only. */
13074 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13076 REAL_VALUE_TYPE ONE16r;
13077 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13079 real_ldexp (&ONE16r, &dconst1, 16);
13080 x = const_double_from_real_value (ONE16r, SFmode);
13081 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13082 NULL, 0, OPTAB_DIRECT);
13083 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13084 NULL, 0, OPTAB_DIRECT);
13085 fp_hi = gen_reg_rtx (SFmode);
13086 fp_lo = gen_reg_rtx (SFmode);
13087 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13088 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13089 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13091 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13093 if (!rtx_equal_p (target, fp_hi))
13094 emit_move_insn (target, fp_hi);
13097 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13098 then replicate the value for all elements of the vector
13102 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13109 v = gen_rtvec (4, value, value, value, value);
13110 return gen_rtx_CONST_VECTOR (V4SImode, v);
13114 v = gen_rtvec (2, value, value);
13115 return gen_rtx_CONST_VECTOR (V2DImode, v);
13119 v = gen_rtvec (4, value, value, value, value);
13121 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13122 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13123 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13127 v = gen_rtvec (2, value, value);
13129 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13130 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13133 gcc_unreachable ();
13137 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13138 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13139 for an SSE register. If VECT is true, then replicate the mask for
13140 all elements of the vector register. If INVERT is true, then create
13141 a mask excluding the sign bit. */
13144 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13146 enum machine_mode vec_mode, imode;
13147 HOST_WIDE_INT hi, lo;
13152 /* Find the sign bit, sign extended to 2*HWI. */
13158 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13159 lo = 0x80000000, hi = lo < 0;
13165 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13166 if (HOST_BITS_PER_WIDE_INT >= 64)
13167 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13169 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13174 vec_mode = VOIDmode;
13175 if (HOST_BITS_PER_WIDE_INT >= 64)
13178 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13185 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13189 lo = ~lo, hi = ~hi;
13195 mask = immed_double_const (lo, hi, imode);
13197 vec = gen_rtvec (2, v, mask);
13198 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13199 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13206 gcc_unreachable ();
13210 lo = ~lo, hi = ~hi;
13212 /* Force this value into the low part of a fp vector constant. */
13213 mask = immed_double_const (lo, hi, imode);
13214 mask = gen_lowpart (mode, mask);
13216 if (vec_mode == VOIDmode)
13217 return force_reg (mode, mask);
13219 v = ix86_build_const_vector (mode, vect, mask);
13220 return force_reg (vec_mode, v);
13223 /* Generate code for floating point ABS or NEG. */
13226 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13229 rtx mask, set, use, clob, dst, src;
13230 bool use_sse = false;
13231 bool vector_mode = VECTOR_MODE_P (mode);
13232 enum machine_mode elt_mode = mode;
13236 elt_mode = GET_MODE_INNER (mode);
13239 else if (mode == TFmode)
13241 else if (TARGET_SSE_MATH)
13242 use_sse = SSE_FLOAT_MODE_P (mode);
13244 /* NEG and ABS performed with SSE use bitwise mask operations.
13245 Create the appropriate mask now. */
13247 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13256 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13257 set = gen_rtx_SET (VOIDmode, dst, set);
13262 set = gen_rtx_fmt_e (code, mode, src);
13263 set = gen_rtx_SET (VOIDmode, dst, set);
13266 use = gen_rtx_USE (VOIDmode, mask);
13267 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13268 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13269 gen_rtvec (3, set, use, clob)));
13276 /* Expand a copysign operation. Special case operand 0 being a constant. */
13279 ix86_expand_copysign (rtx operands[])
13281 enum machine_mode mode;
13282 rtx dest, op0, op1, mask, nmask;
13284 dest = operands[0];
13288 mode = GET_MODE (dest);
13290 if (GET_CODE (op0) == CONST_DOUBLE)
13292 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13294 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13295 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13297 if (mode == SFmode || mode == DFmode)
13299 enum machine_mode vmode;
13301 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13303 if (op0 == CONST0_RTX (mode))
13304 op0 = CONST0_RTX (vmode);
13309 if (mode == SFmode)
13310 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13311 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13313 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13315 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13318 else if (op0 != CONST0_RTX (mode))
13319 op0 = force_reg (mode, op0);
13321 mask = ix86_build_signbit_mask (mode, 0, 0);
13323 if (mode == SFmode)
13324 copysign_insn = gen_copysignsf3_const;
13325 else if (mode == DFmode)
13326 copysign_insn = gen_copysigndf3_const;
13328 copysign_insn = gen_copysigntf3_const;
13330 emit_insn (copysign_insn (dest, op0, op1, mask));
13334 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13336 nmask = ix86_build_signbit_mask (mode, 0, 1);
13337 mask = ix86_build_signbit_mask (mode, 0, 0);
13339 if (mode == SFmode)
13340 copysign_insn = gen_copysignsf3_var;
13341 else if (mode == DFmode)
13342 copysign_insn = gen_copysigndf3_var;
13344 copysign_insn = gen_copysigntf3_var;
13346 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13350 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13351 be a constant, and so has already been expanded into a vector constant. */
13354 ix86_split_copysign_const (rtx operands[])
13356 enum machine_mode mode, vmode;
13357 rtx dest, op0, op1, mask, x;
13359 dest = operands[0];
13362 mask = operands[3];
13364 mode = GET_MODE (dest);
13365 vmode = GET_MODE (mask);
13367 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13368 x = gen_rtx_AND (vmode, dest, mask);
13369 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13371 if (op0 != CONST0_RTX (vmode))
13373 x = gen_rtx_IOR (vmode, dest, op0);
13374 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13378 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13379 so we have to do two masks. */
13382 ix86_split_copysign_var (rtx operands[])
13384 enum machine_mode mode, vmode;
13385 rtx dest, scratch, op0, op1, mask, nmask, x;
13387 dest = operands[0];
13388 scratch = operands[1];
13391 nmask = operands[4];
13392 mask = operands[5];
13394 mode = GET_MODE (dest);
13395 vmode = GET_MODE (mask);
13397 if (rtx_equal_p (op0, op1))
13399 /* Shouldn't happen often (it's useless, obviously), but when it does
13400 we'd generate incorrect code if we continue below. */
13401 emit_move_insn (dest, op0);
13405 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13407 gcc_assert (REGNO (op1) == REGNO (scratch));
13409 x = gen_rtx_AND (vmode, scratch, mask);
13410 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13413 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13414 x = gen_rtx_NOT (vmode, dest);
13415 x = gen_rtx_AND (vmode, x, op0);
13416 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13420 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13422 x = gen_rtx_AND (vmode, scratch, mask);
13424 else /* alternative 2,4 */
13426 gcc_assert (REGNO (mask) == REGNO (scratch));
13427 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13428 x = gen_rtx_AND (vmode, scratch, op1);
13430 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13432 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13434 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13435 x = gen_rtx_AND (vmode, dest, nmask);
13437 else /* alternative 3,4 */
13439 gcc_assert (REGNO (nmask) == REGNO (dest));
13441 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13442 x = gen_rtx_AND (vmode, dest, op0);
13444 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13447 x = gen_rtx_IOR (vmode, dest, scratch);
13448 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13451 /* Return TRUE or FALSE depending on whether the first SET in INSN
13452 has source and destination with matching CC modes, and that the
13453 CC mode is at least as constrained as REQ_MODE. */
13456 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13459 enum machine_mode set_mode;
13461 set = PATTERN (insn);
13462 if (GET_CODE (set) == PARALLEL)
13463 set = XVECEXP (set, 0, 0);
13464 gcc_assert (GET_CODE (set) == SET);
13465 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13467 set_mode = GET_MODE (SET_DEST (set));
13471 if (req_mode != CCNOmode
13472 && (req_mode != CCmode
13473 || XEXP (SET_SRC (set), 1) != const0_rtx))
13477 if (req_mode == CCGCmode)
13481 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13485 if (req_mode == CCZmode)
13496 gcc_unreachable ();
13499 return (GET_MODE (SET_SRC (set)) == set_mode);
13502 /* Generate insn patterns to do an integer compare of OPERANDS. */
13505 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13507 enum machine_mode cmpmode;
13510 cmpmode = SELECT_CC_MODE (code, op0, op1);
13511 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13513 /* This is very simple, but making the interface the same as in the
13514 FP case makes the rest of the code easier. */
13515 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13516 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13518 /* Return the test that should be put into the flags user, i.e.
13519 the bcc, scc, or cmov instruction. */
13520 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13523 /* Figure out whether to use ordered or unordered fp comparisons.
13524 Return the appropriate mode to use. */
13527 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13529 /* ??? In order to make all comparisons reversible, we do all comparisons
13530 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13531 all forms trapping and nontrapping comparisons, we can make inequality
13532 comparisons trapping again, since it results in better code when using
13533 FCOM based compares. */
13534 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13538 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13540 enum machine_mode mode = GET_MODE (op0);
13542 if (SCALAR_FLOAT_MODE_P (mode))
13544 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13545 return ix86_fp_compare_mode (code);
13550 /* Only zero flag is needed. */
13551 case EQ: /* ZF=0 */
13552 case NE: /* ZF!=0 */
13554 /* Codes needing carry flag. */
13555 case GEU: /* CF=0 */
13556 case LTU: /* CF=1 */
13557 /* Detect overflow checks. They need just the carry flag. */
13558 if (GET_CODE (op0) == PLUS
13559 && rtx_equal_p (op1, XEXP (op0, 0)))
13563 case GTU: /* CF=0 & ZF=0 */
13564 case LEU: /* CF=1 | ZF=1 */
13565 /* Detect overflow checks. They need just the carry flag. */
13566 if (GET_CODE (op0) == MINUS
13567 && rtx_equal_p (op1, XEXP (op0, 0)))
13571 /* Codes possibly doable only with sign flag when
13572 comparing against zero. */
13573 case GE: /* SF=OF or SF=0 */
13574 case LT: /* SF<>OF or SF=1 */
13575 if (op1 == const0_rtx)
13578 /* For other cases Carry flag is not required. */
13580 /* Codes doable only with sign flag when comparing
13581 against zero, but we miss jump instruction for it
13582 so we need to use relational tests against overflow
13583 that thus needs to be zero. */
13584 case GT: /* ZF=0 & SF=OF */
13585 case LE: /* ZF=1 | SF<>OF */
13586 if (op1 == const0_rtx)
13590 /* strcmp pattern do (use flags) and combine may ask us for proper
13595 gcc_unreachable ();
13599 /* Return the fixed registers used for condition codes. */
13602 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13609 /* If two condition code modes are compatible, return a condition code
13610 mode which is compatible with both. Otherwise, return
13613 static enum machine_mode
13614 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13619 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13622 if ((m1 == CCGCmode && m2 == CCGOCmode)
13623 || (m1 == CCGOCmode && m2 == CCGCmode))
13629 gcc_unreachable ();
13659 /* These are only compatible with themselves, which we already
13665 /* Split comparison code CODE into comparisons we can do using branch
13666 instructions. BYPASS_CODE is comparison code for branch that will
13667 branch around FIRST_CODE and SECOND_CODE. If some of branches
13668 is not required, set value to UNKNOWN.
13669 We never require more than two branches. */
13672 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13673 enum rtx_code *first_code,
13674 enum rtx_code *second_code)
13676 *first_code = code;
13677 *bypass_code = UNKNOWN;
13678 *second_code = UNKNOWN;
13680 /* The fcomi comparison sets flags as follows:
13690 case GT: /* GTU - CF=0 & ZF=0 */
13691 case GE: /* GEU - CF=0 */
13692 case ORDERED: /* PF=0 */
13693 case UNORDERED: /* PF=1 */
13694 case UNEQ: /* EQ - ZF=1 */
13695 case UNLT: /* LTU - CF=1 */
13696 case UNLE: /* LEU - CF=1 | ZF=1 */
13697 case LTGT: /* EQ - ZF=0 */
13699 case LT: /* LTU - CF=1 - fails on unordered */
13700 *first_code = UNLT;
13701 *bypass_code = UNORDERED;
13703 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13704 *first_code = UNLE;
13705 *bypass_code = UNORDERED;
13707 case EQ: /* EQ - ZF=1 - fails on unordered */
13708 *first_code = UNEQ;
13709 *bypass_code = UNORDERED;
13711 case NE: /* NE - ZF=0 - fails on unordered */
13712 *first_code = LTGT;
13713 *second_code = UNORDERED;
13715 case UNGE: /* GEU - CF=0 - fails on unordered */
13717 *second_code = UNORDERED;
13719 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13721 *second_code = UNORDERED;
13724 gcc_unreachable ();
13726 if (!TARGET_IEEE_FP)
13728 *second_code = UNKNOWN;
13729 *bypass_code = UNKNOWN;
13733 /* Return cost of comparison done fcom + arithmetics operations on AX.
13734 All following functions do use number of instructions as a cost metrics.
13735 In future this should be tweaked to compute bytes for optimize_size and
13736 take into account performance of various instructions on various CPUs. */
13738 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13740 if (!TARGET_IEEE_FP)
13742 /* The cost of code output by ix86_expand_fp_compare. */
13766 gcc_unreachable ();
13770 /* Return cost of comparison done using fcomi operation.
13771 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13773 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13775 enum rtx_code bypass_code, first_code, second_code;
13776 /* Return arbitrarily high cost when instruction is not supported - this
13777 prevents gcc from using it. */
13780 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13781 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13784 /* Return cost of comparison done using sahf operation.
13785 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13787 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13789 enum rtx_code bypass_code, first_code, second_code;
13790 /* Return arbitrarily high cost when instruction is not preferred - this
13791 avoids gcc from using it. */
13792 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13794 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13795 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13798 /* Compute cost of the comparison done using any method.
13799 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13801 ix86_fp_comparison_cost (enum rtx_code code)
13803 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13806 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13807 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13809 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13810 if (min > sahf_cost)
13812 if (min > fcomi_cost)
13817 /* Return true if we should use an FCOMI instruction for this
13821 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13823 enum rtx_code swapped_code = swap_condition (code);
13825 return ((ix86_fp_comparison_cost (code)
13826 == ix86_fp_comparison_fcomi_cost (code))
13827 || (ix86_fp_comparison_cost (swapped_code)
13828 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13831 /* Swap, force into registers, or otherwise massage the two operands
13832 to a fp comparison. The operands are updated in place; the new
13833 comparison code is returned. */
13835 static enum rtx_code
13836 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13838 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13839 rtx op0 = *pop0, op1 = *pop1;
13840 enum machine_mode op_mode = GET_MODE (op0);
13841 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13843 /* All of the unordered compare instructions only work on registers.
13844 The same is true of the fcomi compare instructions. The XFmode
13845 compare instructions require registers except when comparing
13846 against zero or when converting operand 1 from fixed point to
13850 && (fpcmp_mode == CCFPUmode
13851 || (op_mode == XFmode
13852 && ! (standard_80387_constant_p (op0) == 1
13853 || standard_80387_constant_p (op1) == 1)
13854 && GET_CODE (op1) != FLOAT)
13855 || ix86_use_fcomi_compare (code)))
13857 op0 = force_reg (op_mode, op0);
13858 op1 = force_reg (op_mode, op1);
13862 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13863 things around if they appear profitable, otherwise force op0
13864 into a register. */
13866 if (standard_80387_constant_p (op0) == 0
13868 && ! (standard_80387_constant_p (op1) == 0
13872 tmp = op0, op0 = op1, op1 = tmp;
13873 code = swap_condition (code);
13877 op0 = force_reg (op_mode, op0);
13879 if (CONSTANT_P (op1))
13881 int tmp = standard_80387_constant_p (op1);
13883 op1 = validize_mem (force_const_mem (op_mode, op1));
13887 op1 = force_reg (op_mode, op1);
13890 op1 = force_reg (op_mode, op1);
13894 /* Try to rearrange the comparison to make it cheaper. */
13895 if (ix86_fp_comparison_cost (code)
13896 > ix86_fp_comparison_cost (swap_condition (code))
13897 && (REG_P (op1) || can_create_pseudo_p ()))
13900 tmp = op0, op0 = op1, op1 = tmp;
13901 code = swap_condition (code);
13903 op0 = force_reg (op_mode, op0);
13911 /* Convert comparison codes we use to represent FP comparison to integer
13912 code that will result in proper branch. Return UNKNOWN if no such code
13916 ix86_fp_compare_code_to_integer (enum rtx_code code)
13945 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13948 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13949 rtx *second_test, rtx *bypass_test)
13951 enum machine_mode fpcmp_mode, intcmp_mode;
13953 int cost = ix86_fp_comparison_cost (code);
13954 enum rtx_code bypass_code, first_code, second_code;
13956 fpcmp_mode = ix86_fp_compare_mode (code);
13957 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13960 *second_test = NULL_RTX;
13962 *bypass_test = NULL_RTX;
13964 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13966 /* Do fcomi/sahf based test when profitable. */
13967 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13968 && (bypass_code == UNKNOWN || bypass_test)
13969 && (second_code == UNKNOWN || second_test))
13971 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13972 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13978 gcc_assert (TARGET_SAHF);
13981 scratch = gen_reg_rtx (HImode);
13982 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13984 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13987 /* The FP codes work out to act like unsigned. */
13988 intcmp_mode = fpcmp_mode;
13990 if (bypass_code != UNKNOWN)
13991 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13992 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13994 if (second_code != UNKNOWN)
13995 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13996 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14001 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14002 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14003 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14005 scratch = gen_reg_rtx (HImode);
14006 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14008 /* In the unordered case, we have to check C2 for NaN's, which
14009 doesn't happen to work out to anything nice combination-wise.
14010 So do some bit twiddling on the value we've got in AH to come
14011 up with an appropriate set of condition codes. */
14013 intcmp_mode = CCNOmode;
14018 if (code == GT || !TARGET_IEEE_FP)
14020 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14025 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14026 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14027 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14028 intcmp_mode = CCmode;
14034 if (code == LT && TARGET_IEEE_FP)
14036 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14037 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14038 intcmp_mode = CCmode;
14043 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14049 if (code == GE || !TARGET_IEEE_FP)
14051 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14056 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14057 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14064 if (code == LE && TARGET_IEEE_FP)
14066 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14067 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14068 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14069 intcmp_mode = CCmode;
14074 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14080 if (code == EQ && TARGET_IEEE_FP)
14082 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14083 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14084 intcmp_mode = CCmode;
14089 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14096 if (code == NE && TARGET_IEEE_FP)
14098 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14099 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14105 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14111 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14115 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14120 gcc_unreachable ();
14124 /* Return the test that should be put into the flags user, i.e.
14125 the bcc, scc, or cmov instruction. */
14126 return gen_rtx_fmt_ee (code, VOIDmode,
14127 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14132 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14135 op0 = ix86_compare_op0;
14136 op1 = ix86_compare_op1;
14139 *second_test = NULL_RTX;
14141 *bypass_test = NULL_RTX;
14143 if (ix86_compare_emitted)
14145 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14146 ix86_compare_emitted = NULL_RTX;
14148 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14150 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14151 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14152 second_test, bypass_test);
14155 ret = ix86_expand_int_compare (code, op0, op1);
14160 /* Return true if the CODE will result in nontrivial jump sequence. */
14162 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14164 enum rtx_code bypass_code, first_code, second_code;
14167 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14168 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14172 ix86_expand_branch (enum rtx_code code, rtx label)
14176 /* If we have emitted a compare insn, go straight to simple.
14177 ix86_expand_compare won't emit anything if ix86_compare_emitted
14179 if (ix86_compare_emitted)
14182 switch (GET_MODE (ix86_compare_op0))
14188 tmp = ix86_expand_compare (code, NULL, NULL);
14189 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14190 gen_rtx_LABEL_REF (VOIDmode, label),
14192 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14201 enum rtx_code bypass_code, first_code, second_code;
14203 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14204 &ix86_compare_op1);
14206 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14208 /* Check whether we will use the natural sequence with one jump. If
14209 so, we can expand jump early. Otherwise delay expansion by
14210 creating compound insn to not confuse optimizers. */
14211 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14213 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14214 gen_rtx_LABEL_REF (VOIDmode, label),
14215 pc_rtx, NULL_RTX, NULL_RTX);
14219 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14220 ix86_compare_op0, ix86_compare_op1);
14221 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14222 gen_rtx_LABEL_REF (VOIDmode, label),
14224 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14226 use_fcomi = ix86_use_fcomi_compare (code);
14227 vec = rtvec_alloc (3 + !use_fcomi);
14228 RTVEC_ELT (vec, 0) = tmp;
14230 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14232 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14235 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14237 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14246 /* Expand DImode branch into multiple compare+branch. */
14248 rtx lo[2], hi[2], label2;
14249 enum rtx_code code1, code2, code3;
14250 enum machine_mode submode;
14252 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14254 tmp = ix86_compare_op0;
14255 ix86_compare_op0 = ix86_compare_op1;
14256 ix86_compare_op1 = tmp;
14257 code = swap_condition (code);
14259 if (GET_MODE (ix86_compare_op0) == DImode)
14261 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14262 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14267 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14268 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14272 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14273 avoid two branches. This costs one extra insn, so disable when
14274 optimizing for size. */
14276 if ((code == EQ || code == NE)
14277 && (!optimize_insn_for_size_p ()
14278 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14283 if (hi[1] != const0_rtx)
14284 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14285 NULL_RTX, 0, OPTAB_WIDEN);
14288 if (lo[1] != const0_rtx)
14289 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14290 NULL_RTX, 0, OPTAB_WIDEN);
14292 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14293 NULL_RTX, 0, OPTAB_WIDEN);
14295 ix86_compare_op0 = tmp;
14296 ix86_compare_op1 = const0_rtx;
14297 ix86_expand_branch (code, label);
14301 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14302 op1 is a constant and the low word is zero, then we can just
14303 examine the high word. Similarly for low word -1 and
14304 less-or-equal-than or greater-than. */
14306 if (CONST_INT_P (hi[1]))
14309 case LT: case LTU: case GE: case GEU:
14310 if (lo[1] == const0_rtx)
14312 ix86_compare_op0 = hi[0];
14313 ix86_compare_op1 = hi[1];
14314 ix86_expand_branch (code, label);
14318 case LE: case LEU: case GT: case GTU:
14319 if (lo[1] == constm1_rtx)
14321 ix86_compare_op0 = hi[0];
14322 ix86_compare_op1 = hi[1];
14323 ix86_expand_branch (code, label);
14331 /* Otherwise, we need two or three jumps. */
14333 label2 = gen_label_rtx ();
14336 code2 = swap_condition (code);
14337 code3 = unsigned_condition (code);
14341 case LT: case GT: case LTU: case GTU:
14344 case LE: code1 = LT; code2 = GT; break;
14345 case GE: code1 = GT; code2 = LT; break;
14346 case LEU: code1 = LTU; code2 = GTU; break;
14347 case GEU: code1 = GTU; code2 = LTU; break;
14349 case EQ: code1 = UNKNOWN; code2 = NE; break;
14350 case NE: code2 = UNKNOWN; break;
14353 gcc_unreachable ();
14358 * if (hi(a) < hi(b)) goto true;
14359 * if (hi(a) > hi(b)) goto false;
14360 * if (lo(a) < lo(b)) goto true;
14364 ix86_compare_op0 = hi[0];
14365 ix86_compare_op1 = hi[1];
14367 if (code1 != UNKNOWN)
14368 ix86_expand_branch (code1, label);
14369 if (code2 != UNKNOWN)
14370 ix86_expand_branch (code2, label2);
14372 ix86_compare_op0 = lo[0];
14373 ix86_compare_op1 = lo[1];
14374 ix86_expand_branch (code3, label);
14376 if (code2 != UNKNOWN)
14377 emit_label (label2);
14382 gcc_unreachable ();
14386 /* Split branch based on floating point condition. */
14388 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14389 rtx target1, rtx target2, rtx tmp, rtx pushed)
14391 rtx second, bypass;
14392 rtx label = NULL_RTX;
14394 int bypass_probability = -1, second_probability = -1, probability = -1;
14397 if (target2 != pc_rtx)
14400 code = reverse_condition_maybe_unordered (code);
14405 condition = ix86_expand_fp_compare (code, op1, op2,
14406 tmp, &second, &bypass);
14408 /* Remove pushed operand from stack. */
14410 ix86_free_from_memory (GET_MODE (pushed));
14412 if (split_branch_probability >= 0)
14414 /* Distribute the probabilities across the jumps.
14415 Assume the BYPASS and SECOND to be always test
14417 probability = split_branch_probability;
14419 /* Value of 1 is low enough to make no need for probability
14420 to be updated. Later we may run some experiments and see
14421 if unordered values are more frequent in practice. */
14423 bypass_probability = 1;
14425 second_probability = 1;
14427 if (bypass != NULL_RTX)
14429 label = gen_label_rtx ();
14430 i = emit_jump_insn (gen_rtx_SET
14432 gen_rtx_IF_THEN_ELSE (VOIDmode,
14434 gen_rtx_LABEL_REF (VOIDmode,
14437 if (bypass_probability >= 0)
14439 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14440 GEN_INT (bypass_probability),
14443 i = emit_jump_insn (gen_rtx_SET
14445 gen_rtx_IF_THEN_ELSE (VOIDmode,
14446 condition, target1, target2)));
14447 if (probability >= 0)
14449 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14450 GEN_INT (probability),
14452 if (second != NULL_RTX)
14454 i = emit_jump_insn (gen_rtx_SET
14456 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14458 if (second_probability >= 0)
14460 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14461 GEN_INT (second_probability),
14464 if (label != NULL_RTX)
14465 emit_label (label);
14469 ix86_expand_setcc (enum rtx_code code, rtx dest)
14471 rtx ret, tmp, tmpreg, equiv;
14472 rtx second_test, bypass_test;
14474 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14475 return 0; /* FAIL */
14477 gcc_assert (GET_MODE (dest) == QImode);
14479 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14480 PUT_MODE (ret, QImode);
14485 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14486 if (bypass_test || second_test)
14488 rtx test = second_test;
14490 rtx tmp2 = gen_reg_rtx (QImode);
14493 gcc_assert (!second_test);
14494 test = bypass_test;
14496 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14498 PUT_MODE (test, QImode);
14499 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14502 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14504 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14507 /* Attach a REG_EQUAL note describing the comparison result. */
14508 if (ix86_compare_op0 && ix86_compare_op1)
14510 equiv = simplify_gen_relational (code, QImode,
14511 GET_MODE (ix86_compare_op0),
14512 ix86_compare_op0, ix86_compare_op1);
14513 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14516 return 1; /* DONE */
14519 /* Expand comparison setting or clearing carry flag. Return true when
14520 successful and set pop for the operation. */
14522 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14524 enum machine_mode mode =
14525 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14527 /* Do not handle DImode compares that go through special path. */
14528 if (mode == (TARGET_64BIT ? TImode : DImode))
14531 if (SCALAR_FLOAT_MODE_P (mode))
14533 rtx second_test = NULL, bypass_test = NULL;
14534 rtx compare_op, compare_seq;
14536 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14538 /* Shortcut: following common codes never translate
14539 into carry flag compares. */
14540 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14541 || code == ORDERED || code == UNORDERED)
14544 /* These comparisons require zero flag; swap operands so they won't. */
14545 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14546 && !TARGET_IEEE_FP)
14551 code = swap_condition (code);
14554 /* Try to expand the comparison and verify that we end up with
14555 carry flag based comparison. This fails to be true only when
14556 we decide to expand comparison using arithmetic that is not
14557 too common scenario. */
14559 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14560 &second_test, &bypass_test);
14561 compare_seq = get_insns ();
14564 if (second_test || bypass_test)
14567 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14568 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14569 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14571 code = GET_CODE (compare_op);
14573 if (code != LTU && code != GEU)
14576 emit_insn (compare_seq);
14581 if (!INTEGRAL_MODE_P (mode))
14590 /* Convert a==0 into (unsigned)a<1. */
14593 if (op1 != const0_rtx)
14596 code = (code == EQ ? LTU : GEU);
14599 /* Convert a>b into b<a or a>=b-1. */
14602 if (CONST_INT_P (op1))
14604 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14605 /* Bail out on overflow. We still can swap operands but that
14606 would force loading of the constant into register. */
14607 if (op1 == const0_rtx
14608 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14610 code = (code == GTU ? GEU : LTU);
14617 code = (code == GTU ? LTU : GEU);
14621 /* Convert a>=0 into (unsigned)a<0x80000000. */
14624 if (mode == DImode || op1 != const0_rtx)
14626 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14627 code = (code == LT ? GEU : LTU);
14631 if (mode == DImode || op1 != constm1_rtx)
14633 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14634 code = (code == LE ? GEU : LTU);
14640 /* Swapping operands may cause constant to appear as first operand. */
14641 if (!nonimmediate_operand (op0, VOIDmode))
14643 if (!can_create_pseudo_p ())
14645 op0 = force_reg (mode, op0);
14647 ix86_compare_op0 = op0;
14648 ix86_compare_op1 = op1;
14649 *pop = ix86_expand_compare (code, NULL, NULL);
14650 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14655 ix86_expand_int_movcc (rtx operands[])
14657 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14658 rtx compare_seq, compare_op;
14659 rtx second_test, bypass_test;
14660 enum machine_mode mode = GET_MODE (operands[0]);
14661 bool sign_bit_compare_p = false;;
14664 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14665 compare_seq = get_insns ();
14668 compare_code = GET_CODE (compare_op);
14670 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14671 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14672 sign_bit_compare_p = true;
14674 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14675 HImode insns, we'd be swallowed in word prefix ops. */
14677 if ((mode != HImode || TARGET_FAST_PREFIX)
14678 && (mode != (TARGET_64BIT ? TImode : DImode))
14679 && CONST_INT_P (operands[2])
14680 && CONST_INT_P (operands[3]))
14682 rtx out = operands[0];
14683 HOST_WIDE_INT ct = INTVAL (operands[2]);
14684 HOST_WIDE_INT cf = INTVAL (operands[3]);
14685 HOST_WIDE_INT diff;
14688 /* Sign bit compares are better done using shifts than we do by using
14690 if (sign_bit_compare_p
14691 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14692 ix86_compare_op1, &compare_op))
14694 /* Detect overlap between destination and compare sources. */
14697 if (!sign_bit_compare_p)
14699 bool fpcmp = false;
14701 compare_code = GET_CODE (compare_op);
14703 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14704 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14707 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14710 /* To simplify rest of code, restrict to the GEU case. */
14711 if (compare_code == LTU)
14713 HOST_WIDE_INT tmp = ct;
14716 compare_code = reverse_condition (compare_code);
14717 code = reverse_condition (code);
14722 PUT_CODE (compare_op,
14723 reverse_condition_maybe_unordered
14724 (GET_CODE (compare_op)));
14726 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14730 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14731 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14732 tmp = gen_reg_rtx (mode);
14734 if (mode == DImode)
14735 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14737 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14741 if (code == GT || code == GE)
14742 code = reverse_condition (code);
14745 HOST_WIDE_INT tmp = ct;
14750 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14751 ix86_compare_op1, VOIDmode, 0, -1);
14764 tmp = expand_simple_binop (mode, PLUS,
14766 copy_rtx (tmp), 1, OPTAB_DIRECT);
14777 tmp = expand_simple_binop (mode, IOR,
14779 copy_rtx (tmp), 1, OPTAB_DIRECT);
14781 else if (diff == -1 && ct)
14791 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14793 tmp = expand_simple_binop (mode, PLUS,
14794 copy_rtx (tmp), GEN_INT (cf),
14795 copy_rtx (tmp), 1, OPTAB_DIRECT);
14803 * andl cf - ct, dest
14813 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14816 tmp = expand_simple_binop (mode, AND,
14818 gen_int_mode (cf - ct, mode),
14819 copy_rtx (tmp), 1, OPTAB_DIRECT);
14821 tmp = expand_simple_binop (mode, PLUS,
14822 copy_rtx (tmp), GEN_INT (ct),
14823 copy_rtx (tmp), 1, OPTAB_DIRECT);
14826 if (!rtx_equal_p (tmp, out))
14827 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14829 return 1; /* DONE */
14834 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14837 tmp = ct, ct = cf, cf = tmp;
14840 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14842 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14844 /* We may be reversing unordered compare to normal compare, that
14845 is not valid in general (we may convert non-trapping condition
14846 to trapping one), however on i386 we currently emit all
14847 comparisons unordered. */
14848 compare_code = reverse_condition_maybe_unordered (compare_code);
14849 code = reverse_condition_maybe_unordered (code);
14853 compare_code = reverse_condition (compare_code);
14854 code = reverse_condition (code);
14858 compare_code = UNKNOWN;
14859 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14860 && CONST_INT_P (ix86_compare_op1))
14862 if (ix86_compare_op1 == const0_rtx
14863 && (code == LT || code == GE))
14864 compare_code = code;
14865 else if (ix86_compare_op1 == constm1_rtx)
14869 else if (code == GT)
14874 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14875 if (compare_code != UNKNOWN
14876 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14877 && (cf == -1 || ct == -1))
14879 /* If lea code below could be used, only optimize
14880 if it results in a 2 insn sequence. */
14882 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14883 || diff == 3 || diff == 5 || diff == 9)
14884 || (compare_code == LT && ct == -1)
14885 || (compare_code == GE && cf == -1))
14888 * notl op1 (if necessary)
14896 code = reverse_condition (code);
14899 out = emit_store_flag (out, code, ix86_compare_op0,
14900 ix86_compare_op1, VOIDmode, 0, -1);
14902 out = expand_simple_binop (mode, IOR,
14904 out, 1, OPTAB_DIRECT);
14905 if (out != operands[0])
14906 emit_move_insn (operands[0], out);
14908 return 1; /* DONE */
14913 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14914 || diff == 3 || diff == 5 || diff == 9)
14915 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14917 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14923 * lea cf(dest*(ct-cf)),dest
14927 * This also catches the degenerate setcc-only case.
14933 out = emit_store_flag (out, code, ix86_compare_op0,
14934 ix86_compare_op1, VOIDmode, 0, 1);
14937 /* On x86_64 the lea instruction operates on Pmode, so we need
14938 to get arithmetics done in proper mode to match. */
14940 tmp = copy_rtx (out);
14944 out1 = copy_rtx (out);
14945 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14949 tmp = gen_rtx_PLUS (mode, tmp, out1);
14955 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14958 if (!rtx_equal_p (tmp, out))
14961 out = force_operand (tmp, copy_rtx (out));
14963 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14965 if (!rtx_equal_p (out, operands[0]))
14966 emit_move_insn (operands[0], copy_rtx (out));
14968 return 1; /* DONE */
14972 * General case: Jumpful:
14973 * xorl dest,dest cmpl op1, op2
14974 * cmpl op1, op2 movl ct, dest
14975 * setcc dest jcc 1f
14976 * decl dest movl cf, dest
14977 * andl (cf-ct),dest 1:
14980 * Size 20. Size 14.
14982 * This is reasonably steep, but branch mispredict costs are
14983 * high on modern cpus, so consider failing only if optimizing
14987 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14988 && BRANCH_COST (optimize_insn_for_speed_p (),
14993 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14998 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15000 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15002 /* We may be reversing unordered compare to normal compare,
15003 that is not valid in general (we may convert non-trapping
15004 condition to trapping one), however on i386 we currently
15005 emit all comparisons unordered. */
15006 code = reverse_condition_maybe_unordered (code);
15010 code = reverse_condition (code);
15011 if (compare_code != UNKNOWN)
15012 compare_code = reverse_condition (compare_code);
15016 if (compare_code != UNKNOWN)
15018 /* notl op1 (if needed)
15023 For x < 0 (resp. x <= -1) there will be no notl,
15024 so if possible swap the constants to get rid of the
15026 True/false will be -1/0 while code below (store flag
15027 followed by decrement) is 0/-1, so the constants need
15028 to be exchanged once more. */
15030 if (compare_code == GE || !cf)
15032 code = reverse_condition (code);
15037 HOST_WIDE_INT tmp = cf;
15042 out = emit_store_flag (out, code, ix86_compare_op0,
15043 ix86_compare_op1, VOIDmode, 0, -1);
15047 out = emit_store_flag (out, code, ix86_compare_op0,
15048 ix86_compare_op1, VOIDmode, 0, 1);
15050 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15051 copy_rtx (out), 1, OPTAB_DIRECT);
15054 out = expand_simple_binop (mode, AND, copy_rtx (out),
15055 gen_int_mode (cf - ct, mode),
15056 copy_rtx (out), 1, OPTAB_DIRECT);
15058 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15059 copy_rtx (out), 1, OPTAB_DIRECT);
15060 if (!rtx_equal_p (out, operands[0]))
15061 emit_move_insn (operands[0], copy_rtx (out));
15063 return 1; /* DONE */
15067 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15069 /* Try a few things more with specific constants and a variable. */
15072 rtx var, orig_out, out, tmp;
15074 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15075 return 0; /* FAIL */
15077 /* If one of the two operands is an interesting constant, load a
15078 constant with the above and mask it in with a logical operation. */
15080 if (CONST_INT_P (operands[2]))
15083 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15084 operands[3] = constm1_rtx, op = and_optab;
15085 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15086 operands[3] = const0_rtx, op = ior_optab;
15088 return 0; /* FAIL */
15090 else if (CONST_INT_P (operands[3]))
15093 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15094 operands[2] = constm1_rtx, op = and_optab;
15095 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15096 operands[2] = const0_rtx, op = ior_optab;
15098 return 0; /* FAIL */
15101 return 0; /* FAIL */
15103 orig_out = operands[0];
15104 tmp = gen_reg_rtx (mode);
15107 /* Recurse to get the constant loaded. */
15108 if (ix86_expand_int_movcc (operands) == 0)
15109 return 0; /* FAIL */
15111 /* Mask in the interesting variable. */
15112 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15114 if (!rtx_equal_p (out, orig_out))
15115 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15117 return 1; /* DONE */
15121 * For comparison with above,
15131 if (! nonimmediate_operand (operands[2], mode))
15132 operands[2] = force_reg (mode, operands[2]);
15133 if (! nonimmediate_operand (operands[3], mode))
15134 operands[3] = force_reg (mode, operands[3]);
15136 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15138 rtx tmp = gen_reg_rtx (mode);
15139 emit_move_insn (tmp, operands[3]);
15142 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15144 rtx tmp = gen_reg_rtx (mode);
15145 emit_move_insn (tmp, operands[2]);
15149 if (! register_operand (operands[2], VOIDmode)
15151 || ! register_operand (operands[3], VOIDmode)))
15152 operands[2] = force_reg (mode, operands[2]);
15155 && ! register_operand (operands[3], VOIDmode))
15156 operands[3] = force_reg (mode, operands[3]);
15158 emit_insn (compare_seq);
15159 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15160 gen_rtx_IF_THEN_ELSE (mode,
15161 compare_op, operands[2],
15164 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15165 gen_rtx_IF_THEN_ELSE (mode,
15167 copy_rtx (operands[3]),
15168 copy_rtx (operands[0]))));
15170 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15171 gen_rtx_IF_THEN_ELSE (mode,
15173 copy_rtx (operands[2]),
15174 copy_rtx (operands[0]))));
15176 return 1; /* DONE */
15179 /* Swap, force into registers, or otherwise massage the two operands
15180 to an sse comparison with a mask result. Thus we differ a bit from
15181 ix86_prepare_fp_compare_args which expects to produce a flags result.
15183 The DEST operand exists to help determine whether to commute commutative
15184 operators. The POP0/POP1 operands are updated in place. The new
15185 comparison code is returned, or UNKNOWN if not implementable. */
15187 static enum rtx_code
15188 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15189 rtx *pop0, rtx *pop1)
15197 /* We have no LTGT as an operator. We could implement it with
15198 NE & ORDERED, but this requires an extra temporary. It's
15199 not clear that it's worth it. */
15206 /* These are supported directly. */
15213 /* For commutative operators, try to canonicalize the destination
15214 operand to be first in the comparison - this helps reload to
15215 avoid extra moves. */
15216 if (!dest || !rtx_equal_p (dest, *pop1))
15224 /* These are not supported directly. Swap the comparison operands
15225 to transform into something that is supported. */
15229 code = swap_condition (code);
15233 gcc_unreachable ();
15239 /* Detect conditional moves that exactly match min/max operational
15240 semantics. Note that this is IEEE safe, as long as we don't
15241 interchange the operands.
15243 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15244 and TRUE if the operation is successful and instructions are emitted. */
15247 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15248 rtx cmp_op1, rtx if_true, rtx if_false)
15250 enum machine_mode mode;
15256 else if (code == UNGE)
15259 if_true = if_false;
15265 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15267 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15272 mode = GET_MODE (dest);
15274 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15275 but MODE may be a vector mode and thus not appropriate. */
15276 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15278 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15281 if_true = force_reg (mode, if_true);
15282 v = gen_rtvec (2, if_true, if_false);
15283 tmp = gen_rtx_UNSPEC (mode, v, u);
15287 code = is_min ? SMIN : SMAX;
15288 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15291 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15295 /* Expand an sse vector comparison. Return the register with the result. */
15298 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15299 rtx op_true, rtx op_false)
15301 enum machine_mode mode = GET_MODE (dest);
15304 cmp_op0 = force_reg (mode, cmp_op0);
15305 if (!nonimmediate_operand (cmp_op1, mode))
15306 cmp_op1 = force_reg (mode, cmp_op1);
15309 || reg_overlap_mentioned_p (dest, op_true)
15310 || reg_overlap_mentioned_p (dest, op_false))
15311 dest = gen_reg_rtx (mode);
15313 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15314 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15319 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15320 operations. This is used for both scalar and vector conditional moves. */
15323 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15325 enum machine_mode mode = GET_MODE (dest);
15328 if (op_false == CONST0_RTX (mode))
15330 op_true = force_reg (mode, op_true);
15331 x = gen_rtx_AND (mode, cmp, op_true);
15332 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15334 else if (op_true == CONST0_RTX (mode))
15336 op_false = force_reg (mode, op_false);
15337 x = gen_rtx_NOT (mode, cmp);
15338 x = gen_rtx_AND (mode, x, op_false);
15339 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15341 else if (TARGET_SSE5)
15343 rtx pcmov = gen_rtx_SET (mode, dest,
15344 gen_rtx_IF_THEN_ELSE (mode, cmp,
15351 op_true = force_reg (mode, op_true);
15352 op_false = force_reg (mode, op_false);
15354 t2 = gen_reg_rtx (mode);
15356 t3 = gen_reg_rtx (mode);
15360 x = gen_rtx_AND (mode, op_true, cmp);
15361 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15363 x = gen_rtx_NOT (mode, cmp);
15364 x = gen_rtx_AND (mode, x, op_false);
15365 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15367 x = gen_rtx_IOR (mode, t3, t2);
15368 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15372 /* Expand a floating-point conditional move. Return true if successful. */
15375 ix86_expand_fp_movcc (rtx operands[])
15377 enum machine_mode mode = GET_MODE (operands[0]);
15378 enum rtx_code code = GET_CODE (operands[1]);
15379 rtx tmp, compare_op, second_test, bypass_test;
15381 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15383 enum machine_mode cmode;
15385 /* Since we've no cmove for sse registers, don't force bad register
15386 allocation just to gain access to it. Deny movcc when the
15387 comparison mode doesn't match the move mode. */
15388 cmode = GET_MODE (ix86_compare_op0);
15389 if (cmode == VOIDmode)
15390 cmode = GET_MODE (ix86_compare_op1);
15394 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15396 &ix86_compare_op1);
15397 if (code == UNKNOWN)
15400 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15401 ix86_compare_op1, operands[2],
15405 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15406 ix86_compare_op1, operands[2], operands[3]);
15407 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15411 /* The floating point conditional move instructions don't directly
15412 support conditions resulting from a signed integer comparison. */
15414 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15416 /* The floating point conditional move instructions don't directly
15417 support signed integer comparisons. */
15419 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15421 gcc_assert (!second_test && !bypass_test);
15422 tmp = gen_reg_rtx (QImode);
15423 ix86_expand_setcc (code, tmp);
15425 ix86_compare_op0 = tmp;
15426 ix86_compare_op1 = const0_rtx;
15427 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15429 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15431 tmp = gen_reg_rtx (mode);
15432 emit_move_insn (tmp, operands[3]);
15435 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15437 tmp = gen_reg_rtx (mode);
15438 emit_move_insn (tmp, operands[2]);
15442 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15443 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15444 operands[2], operands[3])));
15446 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15447 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15448 operands[3], operands[0])));
15450 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15451 gen_rtx_IF_THEN_ELSE (mode, second_test,
15452 operands[2], operands[0])));
15457 /* Expand a floating-point vector conditional move; a vcond operation
15458 rather than a movcc operation. */
15461 ix86_expand_fp_vcond (rtx operands[])
15463 enum rtx_code code = GET_CODE (operands[3]);
15466 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15467 &operands[4], &operands[5]);
15468 if (code == UNKNOWN)
15471 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15472 operands[5], operands[1], operands[2]))
15475 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15476 operands[1], operands[2]);
15477 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15481 /* Expand a signed/unsigned integral vector conditional move. */
15484 ix86_expand_int_vcond (rtx operands[])
15486 enum machine_mode mode = GET_MODE (operands[0]);
15487 enum rtx_code code = GET_CODE (operands[3]);
15488 bool negate = false;
15491 cop0 = operands[4];
15492 cop1 = operands[5];
15494 /* SSE5 supports all of the comparisons on all vector int types. */
15497 /* Canonicalize the comparison to EQ, GT, GTU. */
15508 code = reverse_condition (code);
15514 code = reverse_condition (code);
15520 code = swap_condition (code);
15521 x = cop0, cop0 = cop1, cop1 = x;
15525 gcc_unreachable ();
15528 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15529 if (mode == V2DImode)
15534 /* SSE4.1 supports EQ. */
15535 if (!TARGET_SSE4_1)
15541 /* SSE4.2 supports GT/GTU. */
15542 if (!TARGET_SSE4_2)
15547 gcc_unreachable ();
15551 /* Unsigned parallel compare is not supported by the hardware. Play some
15552 tricks to turn this into a signed comparison against 0. */
15555 cop0 = force_reg (mode, cop0);
15564 /* Perform a parallel modulo subtraction. */
15565 t1 = gen_reg_rtx (mode);
15566 emit_insn ((mode == V4SImode
15568 : gen_subv2di3) (t1, cop0, cop1));
15570 /* Extract the original sign bit of op0. */
15571 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15573 t2 = gen_reg_rtx (mode);
15574 emit_insn ((mode == V4SImode
15576 : gen_andv2di3) (t2, cop0, mask));
15578 /* XOR it back into the result of the subtraction. This results
15579 in the sign bit set iff we saw unsigned underflow. */
15580 x = gen_reg_rtx (mode);
15581 emit_insn ((mode == V4SImode
15583 : gen_xorv2di3) (x, t1, t2));
15591 /* Perform a parallel unsigned saturating subtraction. */
15592 x = gen_reg_rtx (mode);
15593 emit_insn (gen_rtx_SET (VOIDmode, x,
15594 gen_rtx_US_MINUS (mode, cop0, cop1)));
15601 gcc_unreachable ();
15605 cop1 = CONST0_RTX (mode);
15609 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15610 operands[1+negate], operands[2-negate]);
15612 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15613 operands[2-negate]);
15617 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15618 true if we should do zero extension, else sign extension. HIGH_P is
15619 true if we want the N/2 high elements, else the low elements. */
15622 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15624 enum machine_mode imode = GET_MODE (operands[1]);
15625 rtx (*unpack)(rtx, rtx, rtx);
15632 unpack = gen_vec_interleave_highv16qi;
15634 unpack = gen_vec_interleave_lowv16qi;
15638 unpack = gen_vec_interleave_highv8hi;
15640 unpack = gen_vec_interleave_lowv8hi;
15644 unpack = gen_vec_interleave_highv4si;
15646 unpack = gen_vec_interleave_lowv4si;
15649 gcc_unreachable ();
15652 dest = gen_lowpart (imode, operands[0]);
15655 se = force_reg (imode, CONST0_RTX (imode));
15657 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15658 operands[1], pc_rtx, pc_rtx);
15660 emit_insn (unpack (dest, operands[1], se));
15663 /* This function performs the same task as ix86_expand_sse_unpack,
15664 but with SSE4.1 instructions. */
15667 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15669 enum machine_mode imode = GET_MODE (operands[1]);
15670 rtx (*unpack)(rtx, rtx);
15677 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15679 unpack = gen_sse4_1_extendv8qiv8hi2;
15683 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15685 unpack = gen_sse4_1_extendv4hiv4si2;
15689 unpack = gen_sse4_1_zero_extendv2siv2di2;
15691 unpack = gen_sse4_1_extendv2siv2di2;
15694 gcc_unreachable ();
15697 dest = operands[0];
15700 /* Shift higher 8 bytes to lower 8 bytes. */
15701 src = gen_reg_rtx (imode);
15702 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15703 gen_lowpart (TImode, operands[1]),
15709 emit_insn (unpack (dest, src));
15712 /* This function performs the same task as ix86_expand_sse_unpack,
15713 but with sse5 instructions. */
15716 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15718 enum machine_mode imode = GET_MODE (operands[1]);
15719 int pperm_bytes[16];
15721 int h = (high_p) ? 8 : 0;
15724 rtvec v = rtvec_alloc (16);
15727 rtx op0 = operands[0], op1 = operands[1];
15732 vs = rtvec_alloc (8);
15733 h2 = (high_p) ? 8 : 0;
15734 for (i = 0; i < 8; i++)
15736 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15737 pperm_bytes[2*i+1] = ((unsigned_p)
15739 : PPERM_SIGN | PPERM_SRC2 | i | h);
15742 for (i = 0; i < 16; i++)
15743 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15745 for (i = 0; i < 8; i++)
15746 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15748 p = gen_rtx_PARALLEL (VOIDmode, vs);
15749 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15751 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15753 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15757 vs = rtvec_alloc (4);
15758 h2 = (high_p) ? 4 : 0;
15759 for (i = 0; i < 4; i++)
15761 sign_extend = ((unsigned_p)
15763 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15764 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15765 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15766 pperm_bytes[4*i+2] = sign_extend;
15767 pperm_bytes[4*i+3] = sign_extend;
15770 for (i = 0; i < 16; i++)
15771 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15773 for (i = 0; i < 4; i++)
15774 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15776 p = gen_rtx_PARALLEL (VOIDmode, vs);
15777 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15779 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15781 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15785 vs = rtvec_alloc (2);
15786 h2 = (high_p) ? 2 : 0;
15787 for (i = 0; i < 2; i++)
15789 sign_extend = ((unsigned_p)
15791 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15792 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15793 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15794 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15795 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15796 pperm_bytes[8*i+4] = sign_extend;
15797 pperm_bytes[8*i+5] = sign_extend;
15798 pperm_bytes[8*i+6] = sign_extend;
15799 pperm_bytes[8*i+7] = sign_extend;
15802 for (i = 0; i < 16; i++)
15803 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15805 for (i = 0; i < 2; i++)
15806 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15808 p = gen_rtx_PARALLEL (VOIDmode, vs);
15809 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15811 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15813 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15817 gcc_unreachable ();
15823 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15824 next narrower integer vector type */
15826 ix86_expand_sse5_pack (rtx operands[3])
15828 enum machine_mode imode = GET_MODE (operands[0]);
15829 int pperm_bytes[16];
15831 rtvec v = rtvec_alloc (16);
15833 rtx op0 = operands[0];
15834 rtx op1 = operands[1];
15835 rtx op2 = operands[2];
15840 for (i = 0; i < 8; i++)
15842 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15843 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15846 for (i = 0; i < 16; i++)
15847 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15849 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15850 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15854 for (i = 0; i < 4; i++)
15856 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15857 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15858 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15859 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15862 for (i = 0; i < 16; i++)
15863 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15865 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15866 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15870 for (i = 0; i < 2; i++)
15872 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15873 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15874 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15875 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15876 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15877 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15878 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15879 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15882 for (i = 0; i < 16; i++)
15883 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15885 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15886 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15890 gcc_unreachable ();
15896 /* Expand conditional increment or decrement using adb/sbb instructions.
15897 The default case using setcc followed by the conditional move can be
15898 done by generic code. */
15900 ix86_expand_int_addcc (rtx operands[])
15902 enum rtx_code code = GET_CODE (operands[1]);
15904 rtx val = const0_rtx;
15905 bool fpcmp = false;
15906 enum machine_mode mode = GET_MODE (operands[0]);
15908 if (operands[3] != const1_rtx
15909 && operands[3] != constm1_rtx)
15911 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15912 ix86_compare_op1, &compare_op))
15914 code = GET_CODE (compare_op);
15916 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15917 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15920 code = ix86_fp_compare_code_to_integer (code);
15927 PUT_CODE (compare_op,
15928 reverse_condition_maybe_unordered
15929 (GET_CODE (compare_op)));
15931 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15933 PUT_MODE (compare_op, mode);
15935 /* Construct either adc or sbb insn. */
15936 if ((code == LTU) == (operands[3] == constm1_rtx))
15938 switch (GET_MODE (operands[0]))
15941 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15944 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15947 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15950 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15953 gcc_unreachable ();
15958 switch (GET_MODE (operands[0]))
15961 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15964 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15967 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15970 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15973 gcc_unreachable ();
15976 return 1; /* DONE */
15980 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15981 works for floating pointer parameters and nonoffsetable memories.
15982 For pushes, it returns just stack offsets; the values will be saved
15983 in the right order. Maximally three parts are generated. */
15986 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15991 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15993 size = (GET_MODE_SIZE (mode) + 4) / 8;
15995 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15996 gcc_assert (size >= 2 && size <= 4);
15998 /* Optimize constant pool reference to immediates. This is used by fp
15999 moves, that force all constants to memory to allow combining. */
16000 if (MEM_P (operand) && MEM_READONLY_P (operand))
16002 rtx tmp = maybe_get_pool_constant (operand);
16007 if (MEM_P (operand) && !offsettable_memref_p (operand))
16009 /* The only non-offsetable memories we handle are pushes. */
16010 int ok = push_operand (operand, VOIDmode);
16014 operand = copy_rtx (operand);
16015 PUT_MODE (operand, Pmode);
16016 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16020 if (GET_CODE (operand) == CONST_VECTOR)
16022 enum machine_mode imode = int_mode_for_mode (mode);
16023 /* Caution: if we looked through a constant pool memory above,
16024 the operand may actually have a different mode now. That's
16025 ok, since we want to pun this all the way back to an integer. */
16026 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16027 gcc_assert (operand != NULL);
16033 if (mode == DImode)
16034 split_di (&operand, 1, &parts[0], &parts[1]);
16039 if (REG_P (operand))
16041 gcc_assert (reload_completed);
16042 for (i = 0; i < size; i++)
16043 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16045 else if (offsettable_memref_p (operand))
16047 operand = adjust_address (operand, SImode, 0);
16048 parts[0] = operand;
16049 for (i = 1; i < size; i++)
16050 parts[i] = adjust_address (operand, SImode, 4 * i);
16052 else if (GET_CODE (operand) == CONST_DOUBLE)
16057 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16061 real_to_target (l, &r, mode);
16062 parts[3] = gen_int_mode (l[3], SImode);
16063 parts[2] = gen_int_mode (l[2], SImode);
16066 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16067 parts[2] = gen_int_mode (l[2], SImode);
16070 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16073 gcc_unreachable ();
16075 parts[1] = gen_int_mode (l[1], SImode);
16076 parts[0] = gen_int_mode (l[0], SImode);
16079 gcc_unreachable ();
16084 if (mode == TImode)
16085 split_ti (&operand, 1, &parts[0], &parts[1]);
16086 if (mode == XFmode || mode == TFmode)
16088 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16089 if (REG_P (operand))
16091 gcc_assert (reload_completed);
16092 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16093 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16095 else if (offsettable_memref_p (operand))
16097 operand = adjust_address (operand, DImode, 0);
16098 parts[0] = operand;
16099 parts[1] = adjust_address (operand, upper_mode, 8);
16101 else if (GET_CODE (operand) == CONST_DOUBLE)
16106 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16107 real_to_target (l, &r, mode);
16109 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16110 if (HOST_BITS_PER_WIDE_INT >= 64)
16113 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16114 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16117 parts[0] = immed_double_const (l[0], l[1], DImode);
16119 if (upper_mode == SImode)
16120 parts[1] = gen_int_mode (l[2], SImode);
16121 else if (HOST_BITS_PER_WIDE_INT >= 64)
16124 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16125 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16128 parts[1] = immed_double_const (l[2], l[3], DImode);
16131 gcc_unreachable ();
16138 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16139 Return false when normal moves are needed; true when all required
16140 insns have been emitted. Operands 2-4 contain the input values
16141 int the correct order; operands 5-7 contain the output values. */
16144 ix86_split_long_move (rtx operands[])
16149 int collisions = 0;
16150 enum machine_mode mode = GET_MODE (operands[0]);
16151 bool collisionparts[4];
16153 /* The DFmode expanders may ask us to move double.
16154 For 64bit target this is single move. By hiding the fact
16155 here we simplify i386.md splitters. */
16156 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16158 /* Optimize constant pool reference to immediates. This is used by
16159 fp moves, that force all constants to memory to allow combining. */
16161 if (MEM_P (operands[1])
16162 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16163 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16164 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16165 if (push_operand (operands[0], VOIDmode))
16167 operands[0] = copy_rtx (operands[0]);
16168 PUT_MODE (operands[0], Pmode);
16171 operands[0] = gen_lowpart (DImode, operands[0]);
16172 operands[1] = gen_lowpart (DImode, operands[1]);
16173 emit_move_insn (operands[0], operands[1]);
16177 /* The only non-offsettable memory we handle is push. */
16178 if (push_operand (operands[0], VOIDmode))
16181 gcc_assert (!MEM_P (operands[0])
16182 || offsettable_memref_p (operands[0]));
16184 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16185 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16187 /* When emitting push, take care for source operands on the stack. */
16188 if (push && MEM_P (operands[1])
16189 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16190 for (i = 0; i < nparts - 1; i++)
16191 part[1][i] = change_address (part[1][i],
16192 GET_MODE (part[1][i]),
16193 XEXP (part[1][i + 1], 0));
16195 /* We need to do copy in the right order in case an address register
16196 of the source overlaps the destination. */
16197 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16201 for (i = 0; i < nparts; i++)
16204 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16205 if (collisionparts[i])
16209 /* Collision in the middle part can be handled by reordering. */
16210 if (collisions == 1 && nparts == 3 && collisionparts [1])
16212 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16213 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16215 else if (collisions == 1
16217 && (collisionparts [1] || collisionparts [2]))
16219 if (collisionparts [1])
16221 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16222 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16226 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16227 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16231 /* If there are more collisions, we can't handle it by reordering.
16232 Do an lea to the last part and use only one colliding move. */
16233 else if (collisions > 1)
16239 base = part[0][nparts - 1];
16241 /* Handle the case when the last part isn't valid for lea.
16242 Happens in 64-bit mode storing the 12-byte XFmode. */
16243 if (GET_MODE (base) != Pmode)
16244 base = gen_rtx_REG (Pmode, REGNO (base));
16246 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16247 part[1][0] = replace_equiv_address (part[1][0], base);
16248 for (i = 1; i < nparts; i++)
16250 tmp = plus_constant (base, UNITS_PER_WORD * i);
16251 part[1][i] = replace_equiv_address (part[1][i], tmp);
16262 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16263 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16264 emit_move_insn (part[0][2], part[1][2]);
16266 else if (nparts == 4)
16268 emit_move_insn (part[0][3], part[1][3]);
16269 emit_move_insn (part[0][2], part[1][2]);
16274 /* In 64bit mode we don't have 32bit push available. In case this is
16275 register, it is OK - we will just use larger counterpart. We also
16276 retype memory - these comes from attempt to avoid REX prefix on
16277 moving of second half of TFmode value. */
16278 if (GET_MODE (part[1][1]) == SImode)
16280 switch (GET_CODE (part[1][1]))
16283 part[1][1] = adjust_address (part[1][1], DImode, 0);
16287 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16291 gcc_unreachable ();
16294 if (GET_MODE (part[1][0]) == SImode)
16295 part[1][0] = part[1][1];
16298 emit_move_insn (part[0][1], part[1][1]);
16299 emit_move_insn (part[0][0], part[1][0]);
16303 /* Choose correct order to not overwrite the source before it is copied. */
16304 if ((REG_P (part[0][0])
16305 && REG_P (part[1][1])
16306 && (REGNO (part[0][0]) == REGNO (part[1][1])
16308 && REGNO (part[0][0]) == REGNO (part[1][2]))
16310 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16312 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16314 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16316 operands[2 + i] = part[0][j];
16317 operands[6 + i] = part[1][j];
16322 for (i = 0; i < nparts; i++)
16324 operands[2 + i] = part[0][i];
16325 operands[6 + i] = part[1][i];
16329 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16330 if (optimize_insn_for_size_p ())
16332 for (j = 0; j < nparts - 1; j++)
16333 if (CONST_INT_P (operands[6 + j])
16334 && operands[6 + j] != const0_rtx
16335 && REG_P (operands[2 + j]))
16336 for (i = j; i < nparts - 1; i++)
16337 if (CONST_INT_P (operands[7 + i])
16338 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16339 operands[7 + i] = operands[2 + j];
16342 for (i = 0; i < nparts; i++)
16343 emit_move_insn (operands[2 + i], operands[6 + i]);
16348 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16349 left shift by a constant, either using a single shift or
16350 a sequence of add instructions. */
16353 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16357 emit_insn ((mode == DImode
16359 : gen_adddi3) (operand, operand, operand));
16361 else if (!optimize_insn_for_size_p ()
16362 && count * ix86_cost->add <= ix86_cost->shift_const)
16365 for (i=0; i<count; i++)
16367 emit_insn ((mode == DImode
16369 : gen_adddi3) (operand, operand, operand));
16373 emit_insn ((mode == DImode
16375 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16379 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16381 rtx low[2], high[2];
16383 const int single_width = mode == DImode ? 32 : 64;
16385 if (CONST_INT_P (operands[2]))
16387 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16388 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16390 if (count >= single_width)
16392 emit_move_insn (high[0], low[1]);
16393 emit_move_insn (low[0], const0_rtx);
16395 if (count > single_width)
16396 ix86_expand_ashl_const (high[0], count - single_width, mode);
16400 if (!rtx_equal_p (operands[0], operands[1]))
16401 emit_move_insn (operands[0], operands[1]);
16402 emit_insn ((mode == DImode
16404 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16405 ix86_expand_ashl_const (low[0], count, mode);
16410 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16412 if (operands[1] == const1_rtx)
16414 /* Assuming we've chosen a QImode capable registers, then 1 << N
16415 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16416 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16418 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16420 ix86_expand_clear (low[0]);
16421 ix86_expand_clear (high[0]);
16422 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16424 d = gen_lowpart (QImode, low[0]);
16425 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16426 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16427 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16429 d = gen_lowpart (QImode, high[0]);
16430 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16431 s = gen_rtx_NE (QImode, flags, const0_rtx);
16432 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16435 /* Otherwise, we can get the same results by manually performing
16436 a bit extract operation on bit 5/6, and then performing the two
16437 shifts. The two methods of getting 0/1 into low/high are exactly
16438 the same size. Avoiding the shift in the bit extract case helps
16439 pentium4 a bit; no one else seems to care much either way. */
16444 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16445 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16447 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16448 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16450 emit_insn ((mode == DImode
16452 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16453 emit_insn ((mode == DImode
16455 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16456 emit_move_insn (low[0], high[0]);
16457 emit_insn ((mode == DImode
16459 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16462 emit_insn ((mode == DImode
16464 : gen_ashldi3) (low[0], low[0], operands[2]));
16465 emit_insn ((mode == DImode
16467 : gen_ashldi3) (high[0], high[0], operands[2]));
16471 if (operands[1] == constm1_rtx)
16473 /* For -1 << N, we can avoid the shld instruction, because we
16474 know that we're shifting 0...31/63 ones into a -1. */
16475 emit_move_insn (low[0], constm1_rtx);
16476 if (optimize_insn_for_size_p ())
16477 emit_move_insn (high[0], low[0]);
16479 emit_move_insn (high[0], constm1_rtx);
16483 if (!rtx_equal_p (operands[0], operands[1]))
16484 emit_move_insn (operands[0], operands[1]);
16486 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16487 emit_insn ((mode == DImode
16489 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16492 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16494 if (TARGET_CMOVE && scratch)
16496 ix86_expand_clear (scratch);
16497 emit_insn ((mode == DImode
16498 ? gen_x86_shift_adj_1
16499 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16503 emit_insn ((mode == DImode
16504 ? gen_x86_shift_adj_2
16505 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16509 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16511 rtx low[2], high[2];
16513 const int single_width = mode == DImode ? 32 : 64;
16515 if (CONST_INT_P (operands[2]))
16517 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16518 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16520 if (count == single_width * 2 - 1)
16522 emit_move_insn (high[0], high[1]);
16523 emit_insn ((mode == DImode
16525 : gen_ashrdi3) (high[0], high[0],
16526 GEN_INT (single_width - 1)));
16527 emit_move_insn (low[0], high[0]);
16530 else if (count >= single_width)
16532 emit_move_insn (low[0], high[1]);
16533 emit_move_insn (high[0], low[0]);
16534 emit_insn ((mode == DImode
16536 : gen_ashrdi3) (high[0], high[0],
16537 GEN_INT (single_width - 1)));
16538 if (count > single_width)
16539 emit_insn ((mode == DImode
16541 : gen_ashrdi3) (low[0], low[0],
16542 GEN_INT (count - single_width)));
16546 if (!rtx_equal_p (operands[0], operands[1]))
16547 emit_move_insn (operands[0], operands[1]);
16548 emit_insn ((mode == DImode
16550 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16551 emit_insn ((mode == DImode
16553 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16558 if (!rtx_equal_p (operands[0], operands[1]))
16559 emit_move_insn (operands[0], operands[1]);
16561 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16563 emit_insn ((mode == DImode
16565 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16566 emit_insn ((mode == DImode
16568 : gen_ashrdi3) (high[0], high[0], operands[2]));
16570 if (TARGET_CMOVE && scratch)
16572 emit_move_insn (scratch, high[0]);
16573 emit_insn ((mode == DImode
16575 : gen_ashrdi3) (scratch, scratch,
16576 GEN_INT (single_width - 1)));
16577 emit_insn ((mode == DImode
16578 ? gen_x86_shift_adj_1
16579 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16583 emit_insn ((mode == DImode
16584 ? gen_x86_shift_adj_3
16585 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16590 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16592 rtx low[2], high[2];
16594 const int single_width = mode == DImode ? 32 : 64;
16596 if (CONST_INT_P (operands[2]))
16598 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16599 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16601 if (count >= single_width)
16603 emit_move_insn (low[0], high[1]);
16604 ix86_expand_clear (high[0]);
16606 if (count > single_width)
16607 emit_insn ((mode == DImode
16609 : gen_lshrdi3) (low[0], low[0],
16610 GEN_INT (count - single_width)));
16614 if (!rtx_equal_p (operands[0], operands[1]))
16615 emit_move_insn (operands[0], operands[1]);
16616 emit_insn ((mode == DImode
16618 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16619 emit_insn ((mode == DImode
16621 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16626 if (!rtx_equal_p (operands[0], operands[1]))
16627 emit_move_insn (operands[0], operands[1]);
16629 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16631 emit_insn ((mode == DImode
16633 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16634 emit_insn ((mode == DImode
16636 : gen_lshrdi3) (high[0], high[0], operands[2]));
16638 /* Heh. By reversing the arguments, we can reuse this pattern. */
16639 if (TARGET_CMOVE && scratch)
16641 ix86_expand_clear (scratch);
16642 emit_insn ((mode == DImode
16643 ? gen_x86_shift_adj_1
16644 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16648 emit_insn ((mode == DImode
16649 ? gen_x86_shift_adj_2
16650 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16654 /* Predict just emitted jump instruction to be taken with probability PROB. */
16656 predict_jump (int prob)
16658 rtx insn = get_last_insn ();
16659 gcc_assert (JUMP_P (insn));
16661 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16666 /* Helper function for the string operations below. Dest VARIABLE whether
16667 it is aligned to VALUE bytes. If true, jump to the label. */
16669 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16671 rtx label = gen_label_rtx ();
16672 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16673 if (GET_MODE (variable) == DImode)
16674 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16676 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16677 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16680 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16682 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16686 /* Adjust COUNTER by the VALUE. */
16688 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16690 if (GET_MODE (countreg) == DImode)
16691 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16693 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16696 /* Zero extend possibly SImode EXP to Pmode register. */
16698 ix86_zero_extend_to_Pmode (rtx exp)
16701 if (GET_MODE (exp) == VOIDmode)
16702 return force_reg (Pmode, exp);
16703 if (GET_MODE (exp) == Pmode)
16704 return copy_to_mode_reg (Pmode, exp);
16705 r = gen_reg_rtx (Pmode);
16706 emit_insn (gen_zero_extendsidi2 (r, exp));
16710 /* Divide COUNTREG by SCALE. */
16712 scale_counter (rtx countreg, int scale)
16715 rtx piece_size_mask;
16719 if (CONST_INT_P (countreg))
16720 return GEN_INT (INTVAL (countreg) / scale);
16721 gcc_assert (REG_P (countreg));
16723 piece_size_mask = GEN_INT (scale - 1);
16724 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16725 GEN_INT (exact_log2 (scale)),
16726 NULL, 1, OPTAB_DIRECT);
16730 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16731 DImode for constant loop counts. */
16733 static enum machine_mode
16734 counter_mode (rtx count_exp)
16736 if (GET_MODE (count_exp) != VOIDmode)
16737 return GET_MODE (count_exp);
16738 if (GET_CODE (count_exp) != CONST_INT)
16740 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16745 /* When SRCPTR is non-NULL, output simple loop to move memory
16746 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16747 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16748 equivalent loop to set memory by VALUE (supposed to be in MODE).
16750 The size is rounded down to whole number of chunk size moved at once.
16751 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16755 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16756 rtx destptr, rtx srcptr, rtx value,
16757 rtx count, enum machine_mode mode, int unroll,
16760 rtx out_label, top_label, iter, tmp;
16761 enum machine_mode iter_mode = counter_mode (count);
16762 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16763 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16769 top_label = gen_label_rtx ();
16770 out_label = gen_label_rtx ();
16771 iter = gen_reg_rtx (iter_mode);
16773 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16774 NULL, 1, OPTAB_DIRECT);
16775 /* Those two should combine. */
16776 if (piece_size == const1_rtx)
16778 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16780 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16782 emit_move_insn (iter, const0_rtx);
16784 emit_label (top_label);
16786 tmp = convert_modes (Pmode, iter_mode, iter, true);
16787 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16788 destmem = change_address (destmem, mode, x_addr);
16792 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16793 srcmem = change_address (srcmem, mode, y_addr);
16795 /* When unrolling for chips that reorder memory reads and writes,
16796 we can save registers by using single temporary.
16797 Also using 4 temporaries is overkill in 32bit mode. */
16798 if (!TARGET_64BIT && 0)
16800 for (i = 0; i < unroll; i++)
16805 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16807 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16809 emit_move_insn (destmem, srcmem);
16815 gcc_assert (unroll <= 4);
16816 for (i = 0; i < unroll; i++)
16818 tmpreg[i] = gen_reg_rtx (mode);
16822 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16824 emit_move_insn (tmpreg[i], srcmem);
16826 for (i = 0; i < unroll; i++)
16831 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16833 emit_move_insn (destmem, tmpreg[i]);
16838 for (i = 0; i < unroll; i++)
16842 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16843 emit_move_insn (destmem, value);
16846 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16847 true, OPTAB_LIB_WIDEN);
16849 emit_move_insn (iter, tmp);
16851 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16853 if (expected_size != -1)
16855 expected_size /= GET_MODE_SIZE (mode) * unroll;
16856 if (expected_size == 0)
16858 else if (expected_size > REG_BR_PROB_BASE)
16859 predict_jump (REG_BR_PROB_BASE - 1);
16861 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16864 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16865 iter = ix86_zero_extend_to_Pmode (iter);
16866 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16867 true, OPTAB_LIB_WIDEN);
16868 if (tmp != destptr)
16869 emit_move_insn (destptr, tmp);
16872 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16873 true, OPTAB_LIB_WIDEN);
16875 emit_move_insn (srcptr, tmp);
16877 emit_label (out_label);
16880 /* Output "rep; mov" instruction.
16881 Arguments have same meaning as for previous function */
16883 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16884 rtx destptr, rtx srcptr,
16886 enum machine_mode mode)
16892 /* If the size is known, it is shorter to use rep movs. */
16893 if (mode == QImode && CONST_INT_P (count)
16894 && !(INTVAL (count) & 3))
16897 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16898 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16899 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16900 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16901 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16902 if (mode != QImode)
16904 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16905 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16906 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16907 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16908 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16909 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16913 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16914 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16916 if (CONST_INT_P (count))
16918 count = GEN_INT (INTVAL (count)
16919 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16920 destmem = shallow_copy_rtx (destmem);
16921 srcmem = shallow_copy_rtx (srcmem);
16922 set_mem_size (destmem, count);
16923 set_mem_size (srcmem, count);
16927 if (MEM_SIZE (destmem))
16928 set_mem_size (destmem, NULL_RTX);
16929 if (MEM_SIZE (srcmem))
16930 set_mem_size (srcmem, NULL_RTX);
16932 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16936 /* Output "rep; stos" instruction.
16937 Arguments have same meaning as for previous function */
16939 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16940 rtx count, enum machine_mode mode,
16946 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16947 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16948 value = force_reg (mode, gen_lowpart (mode, value));
16949 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16950 if (mode != QImode)
16952 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16953 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16954 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16957 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16958 if (orig_value == const0_rtx && CONST_INT_P (count))
16960 count = GEN_INT (INTVAL (count)
16961 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16962 destmem = shallow_copy_rtx (destmem);
16963 set_mem_size (destmem, count);
16965 else if (MEM_SIZE (destmem))
16966 set_mem_size (destmem, NULL_RTX);
16967 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16971 emit_strmov (rtx destmem, rtx srcmem,
16972 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16974 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16975 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16976 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16979 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16981 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16982 rtx destptr, rtx srcptr, rtx count, int max_size)
16985 if (CONST_INT_P (count))
16987 HOST_WIDE_INT countval = INTVAL (count);
16990 if ((countval & 0x10) && max_size > 16)
16994 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16995 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16998 gcc_unreachable ();
17001 if ((countval & 0x08) && max_size > 8)
17004 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17007 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17008 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17012 if ((countval & 0x04) && max_size > 4)
17014 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17017 if ((countval & 0x02) && max_size > 2)
17019 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17022 if ((countval & 0x01) && max_size > 1)
17024 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17031 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17032 count, 1, OPTAB_DIRECT);
17033 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17034 count, QImode, 1, 4);
17038 /* When there are stringops, we can cheaply increase dest and src pointers.
17039 Otherwise we save code size by maintaining offset (zero is readily
17040 available from preceding rep operation) and using x86 addressing modes.
17042 if (TARGET_SINGLE_STRINGOP)
17046 rtx label = ix86_expand_aligntest (count, 4, true);
17047 src = change_address (srcmem, SImode, srcptr);
17048 dest = change_address (destmem, SImode, destptr);
17049 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17050 emit_label (label);
17051 LABEL_NUSES (label) = 1;
17055 rtx label = ix86_expand_aligntest (count, 2, true);
17056 src = change_address (srcmem, HImode, srcptr);
17057 dest = change_address (destmem, HImode, destptr);
17058 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17059 emit_label (label);
17060 LABEL_NUSES (label) = 1;
17064 rtx label = ix86_expand_aligntest (count, 1, true);
17065 src = change_address (srcmem, QImode, srcptr);
17066 dest = change_address (destmem, QImode, destptr);
17067 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17068 emit_label (label);
17069 LABEL_NUSES (label) = 1;
17074 rtx offset = force_reg (Pmode, const0_rtx);
17079 rtx label = ix86_expand_aligntest (count, 4, true);
17080 src = change_address (srcmem, SImode, srcptr);
17081 dest = change_address (destmem, SImode, destptr);
17082 emit_move_insn (dest, src);
17083 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17084 true, OPTAB_LIB_WIDEN);
17086 emit_move_insn (offset, tmp);
17087 emit_label (label);
17088 LABEL_NUSES (label) = 1;
17092 rtx label = ix86_expand_aligntest (count, 2, true);
17093 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17094 src = change_address (srcmem, HImode, tmp);
17095 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17096 dest = change_address (destmem, HImode, tmp);
17097 emit_move_insn (dest, src);
17098 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17099 true, OPTAB_LIB_WIDEN);
17101 emit_move_insn (offset, tmp);
17102 emit_label (label);
17103 LABEL_NUSES (label) = 1;
17107 rtx label = ix86_expand_aligntest (count, 1, true);
17108 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17109 src = change_address (srcmem, QImode, tmp);
17110 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17111 dest = change_address (destmem, QImode, tmp);
17112 emit_move_insn (dest, src);
17113 emit_label (label);
17114 LABEL_NUSES (label) = 1;
17119 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17121 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17122 rtx count, int max_size)
17125 expand_simple_binop (counter_mode (count), AND, count,
17126 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17127 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17128 gen_lowpart (QImode, value), count, QImode,
17132 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17134 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17138 if (CONST_INT_P (count))
17140 HOST_WIDE_INT countval = INTVAL (count);
17143 if ((countval & 0x10) && max_size > 16)
17147 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17148 emit_insn (gen_strset (destptr, dest, value));
17149 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17150 emit_insn (gen_strset (destptr, dest, value));
17153 gcc_unreachable ();
17156 if ((countval & 0x08) && max_size > 8)
17160 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17161 emit_insn (gen_strset (destptr, dest, value));
17165 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17166 emit_insn (gen_strset (destptr, dest, value));
17167 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17168 emit_insn (gen_strset (destptr, dest, value));
17172 if ((countval & 0x04) && max_size > 4)
17174 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17175 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17178 if ((countval & 0x02) && max_size > 2)
17180 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17181 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17184 if ((countval & 0x01) && max_size > 1)
17186 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17187 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17194 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17199 rtx label = ix86_expand_aligntest (count, 16, true);
17202 dest = change_address (destmem, DImode, destptr);
17203 emit_insn (gen_strset (destptr, dest, value));
17204 emit_insn (gen_strset (destptr, dest, value));
17208 dest = change_address (destmem, SImode, destptr);
17209 emit_insn (gen_strset (destptr, dest, value));
17210 emit_insn (gen_strset (destptr, dest, value));
17211 emit_insn (gen_strset (destptr, dest, value));
17212 emit_insn (gen_strset (destptr, dest, value));
17214 emit_label (label);
17215 LABEL_NUSES (label) = 1;
17219 rtx label = ix86_expand_aligntest (count, 8, true);
17222 dest = change_address (destmem, DImode, destptr);
17223 emit_insn (gen_strset (destptr, dest, value));
17227 dest = change_address (destmem, SImode, destptr);
17228 emit_insn (gen_strset (destptr, dest, value));
17229 emit_insn (gen_strset (destptr, dest, value));
17231 emit_label (label);
17232 LABEL_NUSES (label) = 1;
17236 rtx label = ix86_expand_aligntest (count, 4, true);
17237 dest = change_address (destmem, SImode, destptr);
17238 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17239 emit_label (label);
17240 LABEL_NUSES (label) = 1;
17244 rtx label = ix86_expand_aligntest (count, 2, true);
17245 dest = change_address (destmem, HImode, destptr);
17246 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17247 emit_label (label);
17248 LABEL_NUSES (label) = 1;
17252 rtx label = ix86_expand_aligntest (count, 1, true);
17253 dest = change_address (destmem, QImode, destptr);
17254 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17255 emit_label (label);
17256 LABEL_NUSES (label) = 1;
17260 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17261 DESIRED_ALIGNMENT. */
17263 expand_movmem_prologue (rtx destmem, rtx srcmem,
17264 rtx destptr, rtx srcptr, rtx count,
17265 int align, int desired_alignment)
17267 if (align <= 1 && desired_alignment > 1)
17269 rtx label = ix86_expand_aligntest (destptr, 1, false);
17270 srcmem = change_address (srcmem, QImode, srcptr);
17271 destmem = change_address (destmem, QImode, destptr);
17272 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17273 ix86_adjust_counter (count, 1);
17274 emit_label (label);
17275 LABEL_NUSES (label) = 1;
17277 if (align <= 2 && desired_alignment > 2)
17279 rtx label = ix86_expand_aligntest (destptr, 2, false);
17280 srcmem = change_address (srcmem, HImode, srcptr);
17281 destmem = change_address (destmem, HImode, destptr);
17282 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17283 ix86_adjust_counter (count, 2);
17284 emit_label (label);
17285 LABEL_NUSES (label) = 1;
17287 if (align <= 4 && desired_alignment > 4)
17289 rtx label = ix86_expand_aligntest (destptr, 4, false);
17290 srcmem = change_address (srcmem, SImode, srcptr);
17291 destmem = change_address (destmem, SImode, destptr);
17292 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17293 ix86_adjust_counter (count, 4);
17294 emit_label (label);
17295 LABEL_NUSES (label) = 1;
17297 gcc_assert (desired_alignment <= 8);
17300 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17301 ALIGN_BYTES is how many bytes need to be copied. */
17303 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17304 int desired_align, int align_bytes)
17307 rtx src_size, dst_size;
17309 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17310 if (src_align_bytes >= 0)
17311 src_align_bytes = desired_align - src_align_bytes;
17312 src_size = MEM_SIZE (src);
17313 dst_size = MEM_SIZE (dst);
17314 if (align_bytes & 1)
17316 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17317 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17319 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17321 if (align_bytes & 2)
17323 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17324 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17325 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17326 set_mem_align (dst, 2 * BITS_PER_UNIT);
17327 if (src_align_bytes >= 0
17328 && (src_align_bytes & 1) == (align_bytes & 1)
17329 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17330 set_mem_align (src, 2 * BITS_PER_UNIT);
17332 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17334 if (align_bytes & 4)
17336 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17337 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17338 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17339 set_mem_align (dst, 4 * BITS_PER_UNIT);
17340 if (src_align_bytes >= 0)
17342 unsigned int src_align = 0;
17343 if ((src_align_bytes & 3) == (align_bytes & 3))
17345 else if ((src_align_bytes & 1) == (align_bytes & 1))
17347 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17348 set_mem_align (src, src_align * BITS_PER_UNIT);
17351 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17353 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17354 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17355 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17356 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17357 if (src_align_bytes >= 0)
17359 unsigned int src_align = 0;
17360 if ((src_align_bytes & 7) == (align_bytes & 7))
17362 else if ((src_align_bytes & 3) == (align_bytes & 3))
17364 else if ((src_align_bytes & 1) == (align_bytes & 1))
17366 if (src_align > (unsigned int) desired_align)
17367 src_align = desired_align;
17368 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17369 set_mem_align (src, src_align * BITS_PER_UNIT);
17372 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17374 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17379 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17380 DESIRED_ALIGNMENT. */
17382 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17383 int align, int desired_alignment)
17385 if (align <= 1 && desired_alignment > 1)
17387 rtx label = ix86_expand_aligntest (destptr, 1, false);
17388 destmem = change_address (destmem, QImode, destptr);
17389 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17390 ix86_adjust_counter (count, 1);
17391 emit_label (label);
17392 LABEL_NUSES (label) = 1;
17394 if (align <= 2 && desired_alignment > 2)
17396 rtx label = ix86_expand_aligntest (destptr, 2, false);
17397 destmem = change_address (destmem, HImode, destptr);
17398 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17399 ix86_adjust_counter (count, 2);
17400 emit_label (label);
17401 LABEL_NUSES (label) = 1;
17403 if (align <= 4 && desired_alignment > 4)
17405 rtx label = ix86_expand_aligntest (destptr, 4, false);
17406 destmem = change_address (destmem, SImode, destptr);
17407 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17408 ix86_adjust_counter (count, 4);
17409 emit_label (label);
17410 LABEL_NUSES (label) = 1;
17412 gcc_assert (desired_alignment <= 8);
17415 /* Set enough from DST to align DST known to by aligned by ALIGN to
17416 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17418 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17419 int desired_align, int align_bytes)
17422 rtx dst_size = MEM_SIZE (dst);
17423 if (align_bytes & 1)
17425 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17427 emit_insn (gen_strset (destreg, dst,
17428 gen_lowpart (QImode, value)));
17430 if (align_bytes & 2)
17432 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17433 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17434 set_mem_align (dst, 2 * BITS_PER_UNIT);
17436 emit_insn (gen_strset (destreg, dst,
17437 gen_lowpart (HImode, value)));
17439 if (align_bytes & 4)
17441 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17442 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17443 set_mem_align (dst, 4 * BITS_PER_UNIT);
17445 emit_insn (gen_strset (destreg, dst,
17446 gen_lowpart (SImode, value)));
17448 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17449 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17450 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17452 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17456 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17457 static enum stringop_alg
17458 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17459 int *dynamic_check)
17461 const struct stringop_algs * algs;
17462 bool optimize_for_speed;
17463 /* Algorithms using the rep prefix want at least edi and ecx;
17464 additionally, memset wants eax and memcpy wants esi. Don't
17465 consider such algorithms if the user has appropriated those
17466 registers for their own purposes. */
17467 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17469 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17471 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17472 || (alg != rep_prefix_1_byte \
17473 && alg != rep_prefix_4_byte \
17474 && alg != rep_prefix_8_byte))
17475 const struct processor_costs *cost;
17477 /* Even if the string operation call is cold, we still might spend a lot
17478 of time processing large blocks. */
17479 if (optimize_function_for_size_p (cfun)
17480 || (optimize_insn_for_size_p ()
17481 && expected_size != -1 && expected_size < 256))
17482 optimize_for_speed = false;
17484 optimize_for_speed = true;
17486 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17488 *dynamic_check = -1;
17490 algs = &cost->memset[TARGET_64BIT != 0];
17492 algs = &cost->memcpy[TARGET_64BIT != 0];
17493 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17494 return stringop_alg;
17495 /* rep; movq or rep; movl is the smallest variant. */
17496 else if (!optimize_for_speed)
17498 if (!count || (count & 3))
17499 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17501 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17503 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17505 else if (expected_size != -1 && expected_size < 4)
17506 return loop_1_byte;
17507 else if (expected_size != -1)
17510 enum stringop_alg alg = libcall;
17511 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17513 /* We get here if the algorithms that were not libcall-based
17514 were rep-prefix based and we are unable to use rep prefixes
17515 based on global register usage. Break out of the loop and
17516 use the heuristic below. */
17517 if (algs->size[i].max == 0)
17519 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17521 enum stringop_alg candidate = algs->size[i].alg;
17523 if (candidate != libcall && ALG_USABLE_P (candidate))
17525 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17526 last non-libcall inline algorithm. */
17527 if (TARGET_INLINE_ALL_STRINGOPS)
17529 /* When the current size is best to be copied by a libcall,
17530 but we are still forced to inline, run the heuristic below
17531 that will pick code for medium sized blocks. */
17532 if (alg != libcall)
17536 else if (ALG_USABLE_P (candidate))
17540 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17542 /* When asked to inline the call anyway, try to pick meaningful choice.
17543 We look for maximal size of block that is faster to copy by hand and
17544 take blocks of at most of that size guessing that average size will
17545 be roughly half of the block.
17547 If this turns out to be bad, we might simply specify the preferred
17548 choice in ix86_costs. */
17549 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17550 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17553 enum stringop_alg alg;
17555 bool any_alg_usable_p = true;
17557 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17559 enum stringop_alg candidate = algs->size[i].alg;
17560 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17562 if (candidate != libcall && candidate
17563 && ALG_USABLE_P (candidate))
17564 max = algs->size[i].max;
17566 /* If there aren't any usable algorithms, then recursing on
17567 smaller sizes isn't going to find anything. Just return the
17568 simple byte-at-a-time copy loop. */
17569 if (!any_alg_usable_p)
17571 /* Pick something reasonable. */
17572 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17573 *dynamic_check = 128;
17574 return loop_1_byte;
17578 alg = decide_alg (count, max / 2, memset, dynamic_check);
17579 gcc_assert (*dynamic_check == -1);
17580 gcc_assert (alg != libcall);
17581 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17582 *dynamic_check = max;
17585 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17586 #undef ALG_USABLE_P
17589 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17590 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17592 decide_alignment (int align,
17593 enum stringop_alg alg,
17596 int desired_align = 0;
17600 gcc_unreachable ();
17602 case unrolled_loop:
17603 desired_align = GET_MODE_SIZE (Pmode);
17605 case rep_prefix_8_byte:
17608 case rep_prefix_4_byte:
17609 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17610 copying whole cacheline at once. */
17611 if (TARGET_PENTIUMPRO)
17616 case rep_prefix_1_byte:
17617 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17618 copying whole cacheline at once. */
17619 if (TARGET_PENTIUMPRO)
17633 if (desired_align < align)
17634 desired_align = align;
17635 if (expected_size != -1 && expected_size < 4)
17636 desired_align = align;
17637 return desired_align;
17640 /* Return the smallest power of 2 greater than VAL. */
17642 smallest_pow2_greater_than (int val)
17650 /* Expand string move (memcpy) operation. Use i386 string operations when
17651 profitable. expand_setmem contains similar code. The code depends upon
17652 architecture, block size and alignment, but always has the same
17655 1) Prologue guard: Conditional that jumps up to epilogues for small
17656 blocks that can be handled by epilogue alone. This is faster but
17657 also needed for correctness, since prologue assume the block is larger
17658 than the desired alignment.
17660 Optional dynamic check for size and libcall for large
17661 blocks is emitted here too, with -minline-stringops-dynamically.
17663 2) Prologue: copy first few bytes in order to get destination aligned
17664 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17665 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17666 We emit either a jump tree on power of two sized blocks, or a byte loop.
17668 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17669 with specified algorithm.
17671 4) Epilogue: code copying tail of the block that is too small to be
17672 handled by main body (or up to size guarded by prologue guard). */
17675 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17676 rtx expected_align_exp, rtx expected_size_exp)
17682 rtx jump_around_label = NULL;
17683 HOST_WIDE_INT align = 1;
17684 unsigned HOST_WIDE_INT count = 0;
17685 HOST_WIDE_INT expected_size = -1;
17686 int size_needed = 0, epilogue_size_needed;
17687 int desired_align = 0, align_bytes = 0;
17688 enum stringop_alg alg;
17690 bool need_zero_guard = false;
17692 if (CONST_INT_P (align_exp))
17693 align = INTVAL (align_exp);
17694 /* i386 can do misaligned access on reasonably increased cost. */
17695 if (CONST_INT_P (expected_align_exp)
17696 && INTVAL (expected_align_exp) > align)
17697 align = INTVAL (expected_align_exp);
17698 /* ALIGN is the minimum of destination and source alignment, but we care here
17699 just about destination alignment. */
17700 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17701 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17703 if (CONST_INT_P (count_exp))
17704 count = expected_size = INTVAL (count_exp);
17705 if (CONST_INT_P (expected_size_exp) && count == 0)
17706 expected_size = INTVAL (expected_size_exp);
17708 /* Make sure we don't need to care about overflow later on. */
17709 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17712 /* Step 0: Decide on preferred algorithm, desired alignment and
17713 size of chunks to be copied by main loop. */
17715 alg = decide_alg (count, expected_size, false, &dynamic_check);
17716 desired_align = decide_alignment (align, alg, expected_size);
17718 if (!TARGET_ALIGN_STRINGOPS)
17719 align = desired_align;
17721 if (alg == libcall)
17723 gcc_assert (alg != no_stringop);
17725 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17726 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17727 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17732 gcc_unreachable ();
17734 need_zero_guard = true;
17735 size_needed = GET_MODE_SIZE (Pmode);
17737 case unrolled_loop:
17738 need_zero_guard = true;
17739 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17741 case rep_prefix_8_byte:
17744 case rep_prefix_4_byte:
17747 case rep_prefix_1_byte:
17751 need_zero_guard = true;
17756 epilogue_size_needed = size_needed;
17758 /* Step 1: Prologue guard. */
17760 /* Alignment code needs count to be in register. */
17761 if (CONST_INT_P (count_exp) && desired_align > align)
17763 if (INTVAL (count_exp) > desired_align
17764 && INTVAL (count_exp) > size_needed)
17767 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17768 if (align_bytes <= 0)
17771 align_bytes = desired_align - align_bytes;
17773 if (align_bytes == 0)
17774 count_exp = force_reg (counter_mode (count_exp), count_exp);
17776 gcc_assert (desired_align >= 1 && align >= 1);
17778 /* Ensure that alignment prologue won't copy past end of block. */
17779 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17781 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17782 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17783 Make sure it is power of 2. */
17784 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17788 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17790 /* If main algorithm works on QImode, no epilogue is needed.
17791 For small sizes just don't align anything. */
17792 if (size_needed == 1)
17793 desired_align = align;
17800 label = gen_label_rtx ();
17801 emit_cmp_and_jump_insns (count_exp,
17802 GEN_INT (epilogue_size_needed),
17803 LTU, 0, counter_mode (count_exp), 1, label);
17804 if (expected_size == -1 || expected_size < epilogue_size_needed)
17805 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17807 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17811 /* Emit code to decide on runtime whether library call or inline should be
17813 if (dynamic_check != -1)
17815 if (CONST_INT_P (count_exp))
17817 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17819 emit_block_move_via_libcall (dst, src, count_exp, false);
17820 count_exp = const0_rtx;
17826 rtx hot_label = gen_label_rtx ();
17827 jump_around_label = gen_label_rtx ();
17828 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17829 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17830 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17831 emit_block_move_via_libcall (dst, src, count_exp, false);
17832 emit_jump (jump_around_label);
17833 emit_label (hot_label);
17837 /* Step 2: Alignment prologue. */
17839 if (desired_align > align)
17841 if (align_bytes == 0)
17843 /* Except for the first move in epilogue, we no longer know
17844 constant offset in aliasing info. It don't seems to worth
17845 the pain to maintain it for the first move, so throw away
17847 src = change_address (src, BLKmode, srcreg);
17848 dst = change_address (dst, BLKmode, destreg);
17849 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17854 /* If we know how many bytes need to be stored before dst is
17855 sufficiently aligned, maintain aliasing info accurately. */
17856 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17857 desired_align, align_bytes);
17858 count_exp = plus_constant (count_exp, -align_bytes);
17859 count -= align_bytes;
17861 if (need_zero_guard
17862 && (count < (unsigned HOST_WIDE_INT) size_needed
17863 || (align_bytes == 0
17864 && count < ((unsigned HOST_WIDE_INT) size_needed
17865 + desired_align - align))))
17867 /* It is possible that we copied enough so the main loop will not
17869 gcc_assert (size_needed > 1);
17870 if (label == NULL_RTX)
17871 label = gen_label_rtx ();
17872 emit_cmp_and_jump_insns (count_exp,
17873 GEN_INT (size_needed),
17874 LTU, 0, counter_mode (count_exp), 1, label);
17875 if (expected_size == -1
17876 || expected_size < (desired_align - align) / 2 + size_needed)
17877 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17879 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17882 if (label && size_needed == 1)
17884 emit_label (label);
17885 LABEL_NUSES (label) = 1;
17887 epilogue_size_needed = 1;
17889 else if (label == NULL_RTX)
17890 epilogue_size_needed = size_needed;
17892 /* Step 3: Main loop. */
17898 gcc_unreachable ();
17900 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17901 count_exp, QImode, 1, expected_size);
17904 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17905 count_exp, Pmode, 1, expected_size);
17907 case unrolled_loop:
17908 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17909 registers for 4 temporaries anyway. */
17910 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17911 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17914 case rep_prefix_8_byte:
17915 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17918 case rep_prefix_4_byte:
17919 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17922 case rep_prefix_1_byte:
17923 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17927 /* Adjust properly the offset of src and dest memory for aliasing. */
17928 if (CONST_INT_P (count_exp))
17930 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17931 (count / size_needed) * size_needed);
17932 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17933 (count / size_needed) * size_needed);
17937 src = change_address (src, BLKmode, srcreg);
17938 dst = change_address (dst, BLKmode, destreg);
17941 /* Step 4: Epilogue to copy the remaining bytes. */
17945 /* When the main loop is done, COUNT_EXP might hold original count,
17946 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17947 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17948 bytes. Compensate if needed. */
17950 if (size_needed < epilogue_size_needed)
17953 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17954 GEN_INT (size_needed - 1), count_exp, 1,
17956 if (tmp != count_exp)
17957 emit_move_insn (count_exp, tmp);
17959 emit_label (label);
17960 LABEL_NUSES (label) = 1;
17963 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17964 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17965 epilogue_size_needed);
17966 if (jump_around_label)
17967 emit_label (jump_around_label);
17971 /* Helper function for memcpy. For QImode value 0xXY produce
17972 0xXYXYXYXY of wide specified by MODE. This is essentially
17973 a * 0x10101010, but we can do slightly better than
17974 synth_mult by unwinding the sequence by hand on CPUs with
17977 promote_duplicated_reg (enum machine_mode mode, rtx val)
17979 enum machine_mode valmode = GET_MODE (val);
17981 int nops = mode == DImode ? 3 : 2;
17983 gcc_assert (mode == SImode || mode == DImode);
17984 if (val == const0_rtx)
17985 return copy_to_mode_reg (mode, const0_rtx);
17986 if (CONST_INT_P (val))
17988 HOST_WIDE_INT v = INTVAL (val) & 255;
17992 if (mode == DImode)
17993 v |= (v << 16) << 16;
17994 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17997 if (valmode == VOIDmode)
17999 if (valmode != QImode)
18000 val = gen_lowpart (QImode, val);
18001 if (mode == QImode)
18003 if (!TARGET_PARTIAL_REG_STALL)
18005 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18006 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18007 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18008 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18010 rtx reg = convert_modes (mode, QImode, val, true);
18011 tmp = promote_duplicated_reg (mode, const1_rtx);
18012 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18017 rtx reg = convert_modes (mode, QImode, val, true);
18019 if (!TARGET_PARTIAL_REG_STALL)
18020 if (mode == SImode)
18021 emit_insn (gen_movsi_insv_1 (reg, reg));
18023 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18026 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18027 NULL, 1, OPTAB_DIRECT);
18029 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18031 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18032 NULL, 1, OPTAB_DIRECT);
18033 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18034 if (mode == SImode)
18036 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18037 NULL, 1, OPTAB_DIRECT);
18038 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18043 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18044 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18045 alignment from ALIGN to DESIRED_ALIGN. */
18047 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18052 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18053 promoted_val = promote_duplicated_reg (DImode, val);
18054 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18055 promoted_val = promote_duplicated_reg (SImode, val);
18056 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18057 promoted_val = promote_duplicated_reg (HImode, val);
18059 promoted_val = val;
18061 return promoted_val;
18064 /* Expand string clear operation (bzero). Use i386 string operations when
18065 profitable. See expand_movmem comment for explanation of individual
18066 steps performed. */
18068 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18069 rtx expected_align_exp, rtx expected_size_exp)
18074 rtx jump_around_label = NULL;
18075 HOST_WIDE_INT align = 1;
18076 unsigned HOST_WIDE_INT count = 0;
18077 HOST_WIDE_INT expected_size = -1;
18078 int size_needed = 0, epilogue_size_needed;
18079 int desired_align = 0, align_bytes = 0;
18080 enum stringop_alg alg;
18081 rtx promoted_val = NULL;
18082 bool force_loopy_epilogue = false;
18084 bool need_zero_guard = false;
18086 if (CONST_INT_P (align_exp))
18087 align = INTVAL (align_exp);
18088 /* i386 can do misaligned access on reasonably increased cost. */
18089 if (CONST_INT_P (expected_align_exp)
18090 && INTVAL (expected_align_exp) > align)
18091 align = INTVAL (expected_align_exp);
18092 if (CONST_INT_P (count_exp))
18093 count = expected_size = INTVAL (count_exp);
18094 if (CONST_INT_P (expected_size_exp) && count == 0)
18095 expected_size = INTVAL (expected_size_exp);
18097 /* Make sure we don't need to care about overflow later on. */
18098 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18101 /* Step 0: Decide on preferred algorithm, desired alignment and
18102 size of chunks to be copied by main loop. */
18104 alg = decide_alg (count, expected_size, true, &dynamic_check);
18105 desired_align = decide_alignment (align, alg, expected_size);
18107 if (!TARGET_ALIGN_STRINGOPS)
18108 align = desired_align;
18110 if (alg == libcall)
18112 gcc_assert (alg != no_stringop);
18114 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18115 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18120 gcc_unreachable ();
18122 need_zero_guard = true;
18123 size_needed = GET_MODE_SIZE (Pmode);
18125 case unrolled_loop:
18126 need_zero_guard = true;
18127 size_needed = GET_MODE_SIZE (Pmode) * 4;
18129 case rep_prefix_8_byte:
18132 case rep_prefix_4_byte:
18135 case rep_prefix_1_byte:
18139 need_zero_guard = true;
18143 epilogue_size_needed = size_needed;
18145 /* Step 1: Prologue guard. */
18147 /* Alignment code needs count to be in register. */
18148 if (CONST_INT_P (count_exp) && desired_align > align)
18150 if (INTVAL (count_exp) > desired_align
18151 && INTVAL (count_exp) > size_needed)
18154 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18155 if (align_bytes <= 0)
18158 align_bytes = desired_align - align_bytes;
18160 if (align_bytes == 0)
18162 enum machine_mode mode = SImode;
18163 if (TARGET_64BIT && (count & ~0xffffffff))
18165 count_exp = force_reg (mode, count_exp);
18168 /* Do the cheap promotion to allow better CSE across the
18169 main loop and epilogue (ie one load of the big constant in the
18170 front of all code. */
18171 if (CONST_INT_P (val_exp))
18172 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18173 desired_align, align);
18174 /* Ensure that alignment prologue won't copy past end of block. */
18175 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18177 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18178 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18179 Make sure it is power of 2. */
18180 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18182 /* To improve performance of small blocks, we jump around the VAL
18183 promoting mode. This mean that if the promoted VAL is not constant,
18184 we might not use it in the epilogue and have to use byte
18186 if (epilogue_size_needed > 2 && !promoted_val)
18187 force_loopy_epilogue = true;
18190 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18192 /* If main algorithm works on QImode, no epilogue is needed.
18193 For small sizes just don't align anything. */
18194 if (size_needed == 1)
18195 desired_align = align;
18202 label = gen_label_rtx ();
18203 emit_cmp_and_jump_insns (count_exp,
18204 GEN_INT (epilogue_size_needed),
18205 LTU, 0, counter_mode (count_exp), 1, label);
18206 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18207 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18209 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18212 if (dynamic_check != -1)
18214 rtx hot_label = gen_label_rtx ();
18215 jump_around_label = gen_label_rtx ();
18216 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18217 LEU, 0, counter_mode (count_exp), 1, hot_label);
18218 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18219 set_storage_via_libcall (dst, count_exp, val_exp, false);
18220 emit_jump (jump_around_label);
18221 emit_label (hot_label);
18224 /* Step 2: Alignment prologue. */
18226 /* Do the expensive promotion once we branched off the small blocks. */
18228 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18229 desired_align, align);
18230 gcc_assert (desired_align >= 1 && align >= 1);
18232 if (desired_align > align)
18234 if (align_bytes == 0)
18236 /* Except for the first move in epilogue, we no longer know
18237 constant offset in aliasing info. It don't seems to worth
18238 the pain to maintain it for the first move, so throw away
18240 dst = change_address (dst, BLKmode, destreg);
18241 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18246 /* If we know how many bytes need to be stored before dst is
18247 sufficiently aligned, maintain aliasing info accurately. */
18248 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18249 desired_align, align_bytes);
18250 count_exp = plus_constant (count_exp, -align_bytes);
18251 count -= align_bytes;
18253 if (need_zero_guard
18254 && (count < (unsigned HOST_WIDE_INT) size_needed
18255 || (align_bytes == 0
18256 && count < ((unsigned HOST_WIDE_INT) size_needed
18257 + desired_align - align))))
18259 /* It is possible that we copied enough so the main loop will not
18261 gcc_assert (size_needed > 1);
18262 if (label == NULL_RTX)
18263 label = gen_label_rtx ();
18264 emit_cmp_and_jump_insns (count_exp,
18265 GEN_INT (size_needed),
18266 LTU, 0, counter_mode (count_exp), 1, label);
18267 if (expected_size == -1
18268 || expected_size < (desired_align - align) / 2 + size_needed)
18269 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18271 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18274 if (label && size_needed == 1)
18276 emit_label (label);
18277 LABEL_NUSES (label) = 1;
18279 promoted_val = val_exp;
18280 epilogue_size_needed = 1;
18282 else if (label == NULL_RTX)
18283 epilogue_size_needed = size_needed;
18285 /* Step 3: Main loop. */
18291 gcc_unreachable ();
18293 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18294 count_exp, QImode, 1, expected_size);
18297 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18298 count_exp, Pmode, 1, expected_size);
18300 case unrolled_loop:
18301 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18302 count_exp, Pmode, 4, expected_size);
18304 case rep_prefix_8_byte:
18305 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18308 case rep_prefix_4_byte:
18309 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18312 case rep_prefix_1_byte:
18313 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18317 /* Adjust properly the offset of src and dest memory for aliasing. */
18318 if (CONST_INT_P (count_exp))
18319 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18320 (count / size_needed) * size_needed);
18322 dst = change_address (dst, BLKmode, destreg);
18324 /* Step 4: Epilogue to copy the remaining bytes. */
18328 /* When the main loop is done, COUNT_EXP might hold original count,
18329 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18330 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18331 bytes. Compensate if needed. */
18333 if (size_needed < epilogue_size_needed)
18336 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18337 GEN_INT (size_needed - 1), count_exp, 1,
18339 if (tmp != count_exp)
18340 emit_move_insn (count_exp, tmp);
18342 emit_label (label);
18343 LABEL_NUSES (label) = 1;
18346 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18348 if (force_loopy_epilogue)
18349 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18350 epilogue_size_needed);
18352 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18353 epilogue_size_needed);
18355 if (jump_around_label)
18356 emit_label (jump_around_label);
18360 /* Expand the appropriate insns for doing strlen if not just doing
18363 out = result, initialized with the start address
18364 align_rtx = alignment of the address.
18365 scratch = scratch register, initialized with the startaddress when
18366 not aligned, otherwise undefined
18368 This is just the body. It needs the initializations mentioned above and
18369 some address computing at the end. These things are done in i386.md. */
18372 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18376 rtx align_2_label = NULL_RTX;
18377 rtx align_3_label = NULL_RTX;
18378 rtx align_4_label = gen_label_rtx ();
18379 rtx end_0_label = gen_label_rtx ();
18381 rtx tmpreg = gen_reg_rtx (SImode);
18382 rtx scratch = gen_reg_rtx (SImode);
18386 if (CONST_INT_P (align_rtx))
18387 align = INTVAL (align_rtx);
18389 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18391 /* Is there a known alignment and is it less than 4? */
18394 rtx scratch1 = gen_reg_rtx (Pmode);
18395 emit_move_insn (scratch1, out);
18396 /* Is there a known alignment and is it not 2? */
18399 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18400 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18402 /* Leave just the 3 lower bits. */
18403 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18404 NULL_RTX, 0, OPTAB_WIDEN);
18406 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18407 Pmode, 1, align_4_label);
18408 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18409 Pmode, 1, align_2_label);
18410 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18411 Pmode, 1, align_3_label);
18415 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18416 check if is aligned to 4 - byte. */
18418 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18419 NULL_RTX, 0, OPTAB_WIDEN);
18421 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18422 Pmode, 1, align_4_label);
18425 mem = change_address (src, QImode, out);
18427 /* Now compare the bytes. */
18429 /* Compare the first n unaligned byte on a byte per byte basis. */
18430 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18431 QImode, 1, end_0_label);
18433 /* Increment the address. */
18434 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18436 /* Not needed with an alignment of 2 */
18439 emit_label (align_2_label);
18441 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18444 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18446 emit_label (align_3_label);
18449 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18452 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18455 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18456 align this loop. It gives only huge programs, but does not help to
18458 emit_label (align_4_label);
18460 mem = change_address (src, SImode, out);
18461 emit_move_insn (scratch, mem);
18462 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18464 /* This formula yields a nonzero result iff one of the bytes is zero.
18465 This saves three branches inside loop and many cycles. */
18467 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18468 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18469 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18470 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18471 gen_int_mode (0x80808080, SImode)));
18472 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18477 rtx reg = gen_reg_rtx (SImode);
18478 rtx reg2 = gen_reg_rtx (Pmode);
18479 emit_move_insn (reg, tmpreg);
18480 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18482 /* If zero is not in the first two bytes, move two bytes forward. */
18483 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18484 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18485 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18486 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18487 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18490 /* Emit lea manually to avoid clobbering of flags. */
18491 emit_insn (gen_rtx_SET (SImode, reg2,
18492 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18494 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18495 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18496 emit_insn (gen_rtx_SET (VOIDmode, out,
18497 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18504 rtx end_2_label = gen_label_rtx ();
18505 /* Is zero in the first two bytes? */
18507 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18508 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18509 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18510 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18511 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18513 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18514 JUMP_LABEL (tmp) = end_2_label;
18516 /* Not in the first two. Move two bytes forward. */
18517 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18518 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18520 emit_label (end_2_label);
18524 /* Avoid branch in fixing the byte. */
18525 tmpreg = gen_lowpart (QImode, tmpreg);
18526 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18527 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18528 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18530 emit_label (end_0_label);
18533 /* Expand strlen. */
18536 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18538 rtx addr, scratch1, scratch2, scratch3, scratch4;
18540 /* The generic case of strlen expander is long. Avoid it's
18541 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18543 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18544 && !TARGET_INLINE_ALL_STRINGOPS
18545 && !optimize_insn_for_size_p ()
18546 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18549 addr = force_reg (Pmode, XEXP (src, 0));
18550 scratch1 = gen_reg_rtx (Pmode);
18552 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18553 && !optimize_insn_for_size_p ())
18555 /* Well it seems that some optimizer does not combine a call like
18556 foo(strlen(bar), strlen(bar));
18557 when the move and the subtraction is done here. It does calculate
18558 the length just once when these instructions are done inside of
18559 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18560 often used and I use one fewer register for the lifetime of
18561 output_strlen_unroll() this is better. */
18563 emit_move_insn (out, addr);
18565 ix86_expand_strlensi_unroll_1 (out, src, align);
18567 /* strlensi_unroll_1 returns the address of the zero at the end of
18568 the string, like memchr(), so compute the length by subtracting
18569 the start address. */
18570 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18576 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18577 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18580 scratch2 = gen_reg_rtx (Pmode);
18581 scratch3 = gen_reg_rtx (Pmode);
18582 scratch4 = force_reg (Pmode, constm1_rtx);
18584 emit_move_insn (scratch3, addr);
18585 eoschar = force_reg (QImode, eoschar);
18587 src = replace_equiv_address_nv (src, scratch3);
18589 /* If .md starts supporting :P, this can be done in .md. */
18590 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18591 scratch4), UNSPEC_SCAS);
18592 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18593 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18594 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18599 /* For given symbol (function) construct code to compute address of it's PLT
18600 entry in large x86-64 PIC model. */
18602 construct_plt_address (rtx symbol)
18604 rtx tmp = gen_reg_rtx (Pmode);
18605 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18607 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18608 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18610 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18611 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18616 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18618 rtx pop, int sibcall)
18620 rtx use = NULL, call;
18621 enum calling_abi function_call_abi;
18623 if (callarg2 && INTVAL (callarg2) == -2)
18624 function_call_abi = MS_ABI;
18626 function_call_abi = SYSV_ABI;
18627 if (pop == const0_rtx)
18629 gcc_assert (!TARGET_64BIT || !pop);
18631 if (TARGET_MACHO && !TARGET_64BIT)
18634 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18635 fnaddr = machopic_indirect_call_target (fnaddr);
18640 /* Static functions and indirect calls don't need the pic register. */
18641 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18642 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18643 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18644 use_reg (&use, pic_offset_table_rtx);
18647 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18649 rtx al = gen_rtx_REG (QImode, AX_REG);
18650 emit_move_insn (al, callarg2);
18651 use_reg (&use, al);
18654 if (ix86_cmodel == CM_LARGE_PIC
18655 && GET_CODE (fnaddr) == MEM
18656 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18657 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18658 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18659 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18661 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18662 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18664 if (sibcall && TARGET_64BIT
18665 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18668 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18669 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18670 emit_move_insn (fnaddr, addr);
18671 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18674 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18676 call = gen_rtx_SET (VOIDmode, retval, call);
18679 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18680 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18681 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18682 gcc_assert (ix86_cfun_abi () != MS_ABI || function_call_abi != SYSV_ABI);
18684 /* We need to represent that SI and DI registers are clobbered
18686 if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI)
18688 static int clobbered_registers[] = {
18689 XMM6_REG, XMM7_REG, XMM8_REG,
18690 XMM9_REG, XMM10_REG, XMM11_REG,
18691 XMM12_REG, XMM13_REG, XMM14_REG,
18692 XMM15_REG, SI_REG, DI_REG
18695 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18696 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18697 UNSPEC_MS_TO_SYSV_CALL);
18701 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18702 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18705 (SSE_REGNO_P (clobbered_registers[i])
18707 clobbered_registers[i]));
18709 call = gen_rtx_PARALLEL (VOIDmode,
18710 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18714 call = emit_call_insn (call);
18716 CALL_INSN_FUNCTION_USAGE (call) = use;
18720 /* Clear stack slot assignments remembered from previous functions.
18721 This is called from INIT_EXPANDERS once before RTL is emitted for each
18724 static struct machine_function *
18725 ix86_init_machine_status (void)
18727 struct machine_function *f;
18729 f = GGC_CNEW (struct machine_function);
18730 f->use_fast_prologue_epilogue_nregs = -1;
18731 f->tls_descriptor_call_expanded_p = 0;
18732 f->call_abi = DEFAULT_ABI;
18737 /* Return a MEM corresponding to a stack slot with mode MODE.
18738 Allocate a new slot if necessary.
18740 The RTL for a function can have several slots available: N is
18741 which slot to use. */
18744 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18746 struct stack_local_entry *s;
18748 gcc_assert (n < MAX_386_STACK_LOCALS);
18750 /* Virtual slot is valid only before vregs are instantiated. */
18751 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18753 for (s = ix86_stack_locals; s; s = s->next)
18754 if (s->mode == mode && s->n == n)
18755 return copy_rtx (s->rtl);
18757 s = (struct stack_local_entry *)
18758 ggc_alloc (sizeof (struct stack_local_entry));
18761 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18763 s->next = ix86_stack_locals;
18764 ix86_stack_locals = s;
18768 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18770 static GTY(()) rtx ix86_tls_symbol;
18772 ix86_tls_get_addr (void)
18775 if (!ix86_tls_symbol)
18777 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18778 (TARGET_ANY_GNU_TLS
18780 ? "___tls_get_addr"
18781 : "__tls_get_addr");
18784 return ix86_tls_symbol;
18787 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18789 static GTY(()) rtx ix86_tls_module_base_symbol;
18791 ix86_tls_module_base (void)
18794 if (!ix86_tls_module_base_symbol)
18796 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18797 "_TLS_MODULE_BASE_");
18798 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18799 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18802 return ix86_tls_module_base_symbol;
18805 /* Calculate the length of the memory address in the instruction
18806 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18809 memory_address_length (rtx addr)
18811 struct ix86_address parts;
18812 rtx base, index, disp;
18816 if (GET_CODE (addr) == PRE_DEC
18817 || GET_CODE (addr) == POST_INC
18818 || GET_CODE (addr) == PRE_MODIFY
18819 || GET_CODE (addr) == POST_MODIFY)
18822 ok = ix86_decompose_address (addr, &parts);
18825 if (parts.base && GET_CODE (parts.base) == SUBREG)
18826 parts.base = SUBREG_REG (parts.base);
18827 if (parts.index && GET_CODE (parts.index) == SUBREG)
18828 parts.index = SUBREG_REG (parts.index);
18831 index = parts.index;
18836 - esp as the base always wants an index,
18837 - ebp as the base always wants a displacement. */
18839 /* Register Indirect. */
18840 if (base && !index && !disp)
18842 /* esp (for its index) and ebp (for its displacement) need
18843 the two-byte modrm form. */
18844 if (addr == stack_pointer_rtx
18845 || addr == arg_pointer_rtx
18846 || addr == frame_pointer_rtx
18847 || addr == hard_frame_pointer_rtx)
18851 /* Direct Addressing. */
18852 else if (disp && !base && !index)
18857 /* Find the length of the displacement constant. */
18860 if (base && satisfies_constraint_K (disp))
18865 /* ebp always wants a displacement. */
18866 else if (base == hard_frame_pointer_rtx)
18869 /* An index requires the two-byte modrm form.... */
18871 /* ...like esp, which always wants an index. */
18872 || base == stack_pointer_rtx
18873 || base == arg_pointer_rtx
18874 || base == frame_pointer_rtx)
18881 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18882 is set, expect that insn have 8bit immediate alternative. */
18884 ix86_attr_length_immediate_default (rtx insn, int shortform)
18888 extract_insn_cached (insn);
18889 for (i = recog_data.n_operands - 1; i >= 0; --i)
18890 if (CONSTANT_P (recog_data.operand[i]))
18893 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18897 switch (get_attr_mode (insn))
18908 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18913 fatal_insn ("unknown insn mode", insn);
18919 /* Compute default value for "length_address" attribute. */
18921 ix86_attr_length_address_default (rtx insn)
18925 if (get_attr_type (insn) == TYPE_LEA)
18927 rtx set = PATTERN (insn);
18929 if (GET_CODE (set) == PARALLEL)
18930 set = XVECEXP (set, 0, 0);
18932 gcc_assert (GET_CODE (set) == SET);
18934 return memory_address_length (SET_SRC (set));
18937 extract_insn_cached (insn);
18938 for (i = recog_data.n_operands - 1; i >= 0; --i)
18939 if (MEM_P (recog_data.operand[i]))
18941 return memory_address_length (XEXP (recog_data.operand[i], 0));
18947 /* Compute default value for "length_vex" attribute. It includes
18948 2 or 3 byte VEX prefix and 1 opcode byte. */
18951 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18956 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18957 byte VEX prefix. */
18958 if (!has_0f_opcode || has_vex_w)
18961 /* We can always use 2 byte VEX prefix in 32bit. */
18965 extract_insn_cached (insn);
18967 for (i = recog_data.n_operands - 1; i >= 0; --i)
18968 if (REG_P (recog_data.operand[i]))
18970 /* REX.W bit uses 3 byte VEX prefix. */
18971 if (GET_MODE (recog_data.operand[i]) == DImode)
18976 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18977 if (MEM_P (recog_data.operand[i])
18978 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18985 /* Return the maximum number of instructions a cpu can issue. */
18988 ix86_issue_rate (void)
18992 case PROCESSOR_PENTIUM:
18996 case PROCESSOR_PENTIUMPRO:
18997 case PROCESSOR_PENTIUM4:
18998 case PROCESSOR_ATHLON:
19000 case PROCESSOR_AMDFAM10:
19001 case PROCESSOR_NOCONA:
19002 case PROCESSOR_GENERIC32:
19003 case PROCESSOR_GENERIC64:
19006 case PROCESSOR_CORE2:
19014 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19015 by DEP_INSN and nothing set by DEP_INSN. */
19018 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19022 /* Simplify the test for uninteresting insns. */
19023 if (insn_type != TYPE_SETCC
19024 && insn_type != TYPE_ICMOV
19025 && insn_type != TYPE_FCMOV
19026 && insn_type != TYPE_IBR)
19029 if ((set = single_set (dep_insn)) != 0)
19031 set = SET_DEST (set);
19034 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19035 && XVECLEN (PATTERN (dep_insn), 0) == 2
19036 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19037 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19039 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19040 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19045 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19048 /* This test is true if the dependent insn reads the flags but
19049 not any other potentially set register. */
19050 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19053 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19059 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19060 address with operands set by DEP_INSN. */
19063 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19067 if (insn_type == TYPE_LEA
19070 addr = PATTERN (insn);
19072 if (GET_CODE (addr) == PARALLEL)
19073 addr = XVECEXP (addr, 0, 0);
19075 gcc_assert (GET_CODE (addr) == SET);
19077 addr = SET_SRC (addr);
19082 extract_insn_cached (insn);
19083 for (i = recog_data.n_operands - 1; i >= 0; --i)
19084 if (MEM_P (recog_data.operand[i]))
19086 addr = XEXP (recog_data.operand[i], 0);
19093 return modified_in_p (addr, dep_insn);
19097 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19099 enum attr_type insn_type, dep_insn_type;
19100 enum attr_memory memory;
19102 int dep_insn_code_number;
19104 /* Anti and output dependencies have zero cost on all CPUs. */
19105 if (REG_NOTE_KIND (link) != 0)
19108 dep_insn_code_number = recog_memoized (dep_insn);
19110 /* If we can't recognize the insns, we can't really do anything. */
19111 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19114 insn_type = get_attr_type (insn);
19115 dep_insn_type = get_attr_type (dep_insn);
19119 case PROCESSOR_PENTIUM:
19120 /* Address Generation Interlock adds a cycle of latency. */
19121 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19124 /* ??? Compares pair with jump/setcc. */
19125 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19128 /* Floating point stores require value to be ready one cycle earlier. */
19129 if (insn_type == TYPE_FMOV
19130 && get_attr_memory (insn) == MEMORY_STORE
19131 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19135 case PROCESSOR_PENTIUMPRO:
19136 memory = get_attr_memory (insn);
19138 /* INT->FP conversion is expensive. */
19139 if (get_attr_fp_int_src (dep_insn))
19142 /* There is one cycle extra latency between an FP op and a store. */
19143 if (insn_type == TYPE_FMOV
19144 && (set = single_set (dep_insn)) != NULL_RTX
19145 && (set2 = single_set (insn)) != NULL_RTX
19146 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19147 && MEM_P (SET_DEST (set2)))
19150 /* Show ability of reorder buffer to hide latency of load by executing
19151 in parallel with previous instruction in case
19152 previous instruction is not needed to compute the address. */
19153 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19154 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19156 /* Claim moves to take one cycle, as core can issue one load
19157 at time and the next load can start cycle later. */
19158 if (dep_insn_type == TYPE_IMOV
19159 || dep_insn_type == TYPE_FMOV)
19167 memory = get_attr_memory (insn);
19169 /* The esp dependency is resolved before the instruction is really
19171 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19172 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19175 /* INT->FP conversion is expensive. */
19176 if (get_attr_fp_int_src (dep_insn))
19179 /* Show ability of reorder buffer to hide latency of load by executing
19180 in parallel with previous instruction in case
19181 previous instruction is not needed to compute the address. */
19182 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19183 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19185 /* Claim moves to take one cycle, as core can issue one load
19186 at time and the next load can start cycle later. */
19187 if (dep_insn_type == TYPE_IMOV
19188 || dep_insn_type == TYPE_FMOV)
19197 case PROCESSOR_ATHLON:
19199 case PROCESSOR_AMDFAM10:
19200 case PROCESSOR_GENERIC32:
19201 case PROCESSOR_GENERIC64:
19202 memory = get_attr_memory (insn);
19204 /* Show ability of reorder buffer to hide latency of load by executing
19205 in parallel with previous instruction in case
19206 previous instruction is not needed to compute the address. */
19207 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19208 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19210 enum attr_unit unit = get_attr_unit (insn);
19213 /* Because of the difference between the length of integer and
19214 floating unit pipeline preparation stages, the memory operands
19215 for floating point are cheaper.
19217 ??? For Athlon it the difference is most probably 2. */
19218 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19221 loadcost = TARGET_ATHLON ? 2 : 0;
19223 if (cost >= loadcost)
19236 /* How many alternative schedules to try. This should be as wide as the
19237 scheduling freedom in the DFA, but no wider. Making this value too
19238 large results extra work for the scheduler. */
19241 ia32_multipass_dfa_lookahead (void)
19245 case PROCESSOR_PENTIUM:
19248 case PROCESSOR_PENTIUMPRO:
19258 /* Compute the alignment given to a constant that is being placed in memory.
19259 EXP is the constant and ALIGN is the alignment that the object would
19261 The value of this function is used instead of that alignment to align
19265 ix86_constant_alignment (tree exp, int align)
19267 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19268 || TREE_CODE (exp) == INTEGER_CST)
19270 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19272 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19275 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19276 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19277 return BITS_PER_WORD;
19282 /* Compute the alignment for a static variable.
19283 TYPE is the data type, and ALIGN is the alignment that
19284 the object would ordinarily have. The value of this function is used
19285 instead of that alignment to align the object. */
19288 ix86_data_alignment (tree type, int align)
19290 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19292 if (AGGREGATE_TYPE_P (type)
19293 && TYPE_SIZE (type)
19294 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19295 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19296 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19297 && align < max_align)
19300 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19301 to 16byte boundary. */
19304 if (AGGREGATE_TYPE_P (type)
19305 && TYPE_SIZE (type)
19306 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19307 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19308 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19312 if (TREE_CODE (type) == ARRAY_TYPE)
19314 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19316 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19319 else if (TREE_CODE (type) == COMPLEX_TYPE)
19322 if (TYPE_MODE (type) == DCmode && align < 64)
19324 if ((TYPE_MODE (type) == XCmode
19325 || TYPE_MODE (type) == TCmode) && align < 128)
19328 else if ((TREE_CODE (type) == RECORD_TYPE
19329 || TREE_CODE (type) == UNION_TYPE
19330 || TREE_CODE (type) == QUAL_UNION_TYPE)
19331 && TYPE_FIELDS (type))
19333 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19335 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19338 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19339 || TREE_CODE (type) == INTEGER_TYPE)
19341 if (TYPE_MODE (type) == DFmode && align < 64)
19343 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19350 /* Compute the alignment for a local variable or a stack slot. TYPE is
19351 the data type, MODE is the widest mode available and ALIGN is the
19352 alignment that the object would ordinarily have. The value of this
19353 macro is used instead of that alignment to align the object. */
19356 ix86_local_alignment (tree type, enum machine_mode mode,
19357 unsigned int align)
19359 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19360 register in MODE. We will return the largest alignment of XF
19364 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19365 align = GET_MODE_ALIGNMENT (DFmode);
19369 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19370 to 16byte boundary. */
19373 if (AGGREGATE_TYPE_P (type)
19374 && TYPE_SIZE (type)
19375 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19376 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19377 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19380 if (TREE_CODE (type) == ARRAY_TYPE)
19382 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19384 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19387 else if (TREE_CODE (type) == COMPLEX_TYPE)
19389 if (TYPE_MODE (type) == DCmode && align < 64)
19391 if ((TYPE_MODE (type) == XCmode
19392 || TYPE_MODE (type) == TCmode) && align < 128)
19395 else if ((TREE_CODE (type) == RECORD_TYPE
19396 || TREE_CODE (type) == UNION_TYPE
19397 || TREE_CODE (type) == QUAL_UNION_TYPE)
19398 && TYPE_FIELDS (type))
19400 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19402 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19405 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19406 || TREE_CODE (type) == INTEGER_TYPE)
19409 if (TYPE_MODE (type) == DFmode && align < 64)
19411 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19417 /* Emit RTL insns to initialize the variable parts of a trampoline.
19418 FNADDR is an RTX for the address of the function's pure code.
19419 CXT is an RTX for the static chain value for the function. */
19421 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19425 /* Compute offset from the end of the jmp to the target function. */
19426 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19427 plus_constant (tramp, 10),
19428 NULL_RTX, 1, OPTAB_DIRECT);
19429 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19430 gen_int_mode (0xb9, QImode));
19431 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19432 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19433 gen_int_mode (0xe9, QImode));
19434 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19439 /* Try to load address using shorter movl instead of movabs.
19440 We may want to support movq for kernel mode, but kernel does not use
19441 trampolines at the moment. */
19442 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19444 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19445 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19446 gen_int_mode (0xbb41, HImode));
19447 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19448 gen_lowpart (SImode, fnaddr));
19453 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19454 gen_int_mode (0xbb49, HImode));
19455 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19459 /* Load static chain using movabs to r10. */
19460 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19461 gen_int_mode (0xba49, HImode));
19462 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19465 /* Jump to the r11 */
19466 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19467 gen_int_mode (0xff49, HImode));
19468 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19469 gen_int_mode (0xe3, QImode));
19471 gcc_assert (offset <= TRAMPOLINE_SIZE);
19474 #ifdef ENABLE_EXECUTE_STACK
19475 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19476 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19480 /* Codes for all the SSE/MMX builtins. */
19483 IX86_BUILTIN_ADDPS,
19484 IX86_BUILTIN_ADDSS,
19485 IX86_BUILTIN_DIVPS,
19486 IX86_BUILTIN_DIVSS,
19487 IX86_BUILTIN_MULPS,
19488 IX86_BUILTIN_MULSS,
19489 IX86_BUILTIN_SUBPS,
19490 IX86_BUILTIN_SUBSS,
19492 IX86_BUILTIN_CMPEQPS,
19493 IX86_BUILTIN_CMPLTPS,
19494 IX86_BUILTIN_CMPLEPS,
19495 IX86_BUILTIN_CMPGTPS,
19496 IX86_BUILTIN_CMPGEPS,
19497 IX86_BUILTIN_CMPNEQPS,
19498 IX86_BUILTIN_CMPNLTPS,
19499 IX86_BUILTIN_CMPNLEPS,
19500 IX86_BUILTIN_CMPNGTPS,
19501 IX86_BUILTIN_CMPNGEPS,
19502 IX86_BUILTIN_CMPORDPS,
19503 IX86_BUILTIN_CMPUNORDPS,
19504 IX86_BUILTIN_CMPEQSS,
19505 IX86_BUILTIN_CMPLTSS,
19506 IX86_BUILTIN_CMPLESS,
19507 IX86_BUILTIN_CMPNEQSS,
19508 IX86_BUILTIN_CMPNLTSS,
19509 IX86_BUILTIN_CMPNLESS,
19510 IX86_BUILTIN_CMPNGTSS,
19511 IX86_BUILTIN_CMPNGESS,
19512 IX86_BUILTIN_CMPORDSS,
19513 IX86_BUILTIN_CMPUNORDSS,
19515 IX86_BUILTIN_COMIEQSS,
19516 IX86_BUILTIN_COMILTSS,
19517 IX86_BUILTIN_COMILESS,
19518 IX86_BUILTIN_COMIGTSS,
19519 IX86_BUILTIN_COMIGESS,
19520 IX86_BUILTIN_COMINEQSS,
19521 IX86_BUILTIN_UCOMIEQSS,
19522 IX86_BUILTIN_UCOMILTSS,
19523 IX86_BUILTIN_UCOMILESS,
19524 IX86_BUILTIN_UCOMIGTSS,
19525 IX86_BUILTIN_UCOMIGESS,
19526 IX86_BUILTIN_UCOMINEQSS,
19528 IX86_BUILTIN_CVTPI2PS,
19529 IX86_BUILTIN_CVTPS2PI,
19530 IX86_BUILTIN_CVTSI2SS,
19531 IX86_BUILTIN_CVTSI642SS,
19532 IX86_BUILTIN_CVTSS2SI,
19533 IX86_BUILTIN_CVTSS2SI64,
19534 IX86_BUILTIN_CVTTPS2PI,
19535 IX86_BUILTIN_CVTTSS2SI,
19536 IX86_BUILTIN_CVTTSS2SI64,
19538 IX86_BUILTIN_MAXPS,
19539 IX86_BUILTIN_MAXSS,
19540 IX86_BUILTIN_MINPS,
19541 IX86_BUILTIN_MINSS,
19543 IX86_BUILTIN_LOADUPS,
19544 IX86_BUILTIN_STOREUPS,
19545 IX86_BUILTIN_MOVSS,
19547 IX86_BUILTIN_MOVHLPS,
19548 IX86_BUILTIN_MOVLHPS,
19549 IX86_BUILTIN_LOADHPS,
19550 IX86_BUILTIN_LOADLPS,
19551 IX86_BUILTIN_STOREHPS,
19552 IX86_BUILTIN_STORELPS,
19554 IX86_BUILTIN_MASKMOVQ,
19555 IX86_BUILTIN_MOVMSKPS,
19556 IX86_BUILTIN_PMOVMSKB,
19558 IX86_BUILTIN_MOVNTPS,
19559 IX86_BUILTIN_MOVNTQ,
19561 IX86_BUILTIN_LOADDQU,
19562 IX86_BUILTIN_STOREDQU,
19564 IX86_BUILTIN_PACKSSWB,
19565 IX86_BUILTIN_PACKSSDW,
19566 IX86_BUILTIN_PACKUSWB,
19568 IX86_BUILTIN_PADDB,
19569 IX86_BUILTIN_PADDW,
19570 IX86_BUILTIN_PADDD,
19571 IX86_BUILTIN_PADDQ,
19572 IX86_BUILTIN_PADDSB,
19573 IX86_BUILTIN_PADDSW,
19574 IX86_BUILTIN_PADDUSB,
19575 IX86_BUILTIN_PADDUSW,
19576 IX86_BUILTIN_PSUBB,
19577 IX86_BUILTIN_PSUBW,
19578 IX86_BUILTIN_PSUBD,
19579 IX86_BUILTIN_PSUBQ,
19580 IX86_BUILTIN_PSUBSB,
19581 IX86_BUILTIN_PSUBSW,
19582 IX86_BUILTIN_PSUBUSB,
19583 IX86_BUILTIN_PSUBUSW,
19586 IX86_BUILTIN_PANDN,
19590 IX86_BUILTIN_PAVGB,
19591 IX86_BUILTIN_PAVGW,
19593 IX86_BUILTIN_PCMPEQB,
19594 IX86_BUILTIN_PCMPEQW,
19595 IX86_BUILTIN_PCMPEQD,
19596 IX86_BUILTIN_PCMPGTB,
19597 IX86_BUILTIN_PCMPGTW,
19598 IX86_BUILTIN_PCMPGTD,
19600 IX86_BUILTIN_PMADDWD,
19602 IX86_BUILTIN_PMAXSW,
19603 IX86_BUILTIN_PMAXUB,
19604 IX86_BUILTIN_PMINSW,
19605 IX86_BUILTIN_PMINUB,
19607 IX86_BUILTIN_PMULHUW,
19608 IX86_BUILTIN_PMULHW,
19609 IX86_BUILTIN_PMULLW,
19611 IX86_BUILTIN_PSADBW,
19612 IX86_BUILTIN_PSHUFW,
19614 IX86_BUILTIN_PSLLW,
19615 IX86_BUILTIN_PSLLD,
19616 IX86_BUILTIN_PSLLQ,
19617 IX86_BUILTIN_PSRAW,
19618 IX86_BUILTIN_PSRAD,
19619 IX86_BUILTIN_PSRLW,
19620 IX86_BUILTIN_PSRLD,
19621 IX86_BUILTIN_PSRLQ,
19622 IX86_BUILTIN_PSLLWI,
19623 IX86_BUILTIN_PSLLDI,
19624 IX86_BUILTIN_PSLLQI,
19625 IX86_BUILTIN_PSRAWI,
19626 IX86_BUILTIN_PSRADI,
19627 IX86_BUILTIN_PSRLWI,
19628 IX86_BUILTIN_PSRLDI,
19629 IX86_BUILTIN_PSRLQI,
19631 IX86_BUILTIN_PUNPCKHBW,
19632 IX86_BUILTIN_PUNPCKHWD,
19633 IX86_BUILTIN_PUNPCKHDQ,
19634 IX86_BUILTIN_PUNPCKLBW,
19635 IX86_BUILTIN_PUNPCKLWD,
19636 IX86_BUILTIN_PUNPCKLDQ,
19638 IX86_BUILTIN_SHUFPS,
19640 IX86_BUILTIN_RCPPS,
19641 IX86_BUILTIN_RCPSS,
19642 IX86_BUILTIN_RSQRTPS,
19643 IX86_BUILTIN_RSQRTPS_NR,
19644 IX86_BUILTIN_RSQRTSS,
19645 IX86_BUILTIN_RSQRTF,
19646 IX86_BUILTIN_SQRTPS,
19647 IX86_BUILTIN_SQRTPS_NR,
19648 IX86_BUILTIN_SQRTSS,
19650 IX86_BUILTIN_UNPCKHPS,
19651 IX86_BUILTIN_UNPCKLPS,
19653 IX86_BUILTIN_ANDPS,
19654 IX86_BUILTIN_ANDNPS,
19656 IX86_BUILTIN_XORPS,
19659 IX86_BUILTIN_LDMXCSR,
19660 IX86_BUILTIN_STMXCSR,
19661 IX86_BUILTIN_SFENCE,
19663 /* 3DNow! Original */
19664 IX86_BUILTIN_FEMMS,
19665 IX86_BUILTIN_PAVGUSB,
19666 IX86_BUILTIN_PF2ID,
19667 IX86_BUILTIN_PFACC,
19668 IX86_BUILTIN_PFADD,
19669 IX86_BUILTIN_PFCMPEQ,
19670 IX86_BUILTIN_PFCMPGE,
19671 IX86_BUILTIN_PFCMPGT,
19672 IX86_BUILTIN_PFMAX,
19673 IX86_BUILTIN_PFMIN,
19674 IX86_BUILTIN_PFMUL,
19675 IX86_BUILTIN_PFRCP,
19676 IX86_BUILTIN_PFRCPIT1,
19677 IX86_BUILTIN_PFRCPIT2,
19678 IX86_BUILTIN_PFRSQIT1,
19679 IX86_BUILTIN_PFRSQRT,
19680 IX86_BUILTIN_PFSUB,
19681 IX86_BUILTIN_PFSUBR,
19682 IX86_BUILTIN_PI2FD,
19683 IX86_BUILTIN_PMULHRW,
19685 /* 3DNow! Athlon Extensions */
19686 IX86_BUILTIN_PF2IW,
19687 IX86_BUILTIN_PFNACC,
19688 IX86_BUILTIN_PFPNACC,
19689 IX86_BUILTIN_PI2FW,
19690 IX86_BUILTIN_PSWAPDSI,
19691 IX86_BUILTIN_PSWAPDSF,
19694 IX86_BUILTIN_ADDPD,
19695 IX86_BUILTIN_ADDSD,
19696 IX86_BUILTIN_DIVPD,
19697 IX86_BUILTIN_DIVSD,
19698 IX86_BUILTIN_MULPD,
19699 IX86_BUILTIN_MULSD,
19700 IX86_BUILTIN_SUBPD,
19701 IX86_BUILTIN_SUBSD,
19703 IX86_BUILTIN_CMPEQPD,
19704 IX86_BUILTIN_CMPLTPD,
19705 IX86_BUILTIN_CMPLEPD,
19706 IX86_BUILTIN_CMPGTPD,
19707 IX86_BUILTIN_CMPGEPD,
19708 IX86_BUILTIN_CMPNEQPD,
19709 IX86_BUILTIN_CMPNLTPD,
19710 IX86_BUILTIN_CMPNLEPD,
19711 IX86_BUILTIN_CMPNGTPD,
19712 IX86_BUILTIN_CMPNGEPD,
19713 IX86_BUILTIN_CMPORDPD,
19714 IX86_BUILTIN_CMPUNORDPD,
19715 IX86_BUILTIN_CMPEQSD,
19716 IX86_BUILTIN_CMPLTSD,
19717 IX86_BUILTIN_CMPLESD,
19718 IX86_BUILTIN_CMPNEQSD,
19719 IX86_BUILTIN_CMPNLTSD,
19720 IX86_BUILTIN_CMPNLESD,
19721 IX86_BUILTIN_CMPORDSD,
19722 IX86_BUILTIN_CMPUNORDSD,
19724 IX86_BUILTIN_COMIEQSD,
19725 IX86_BUILTIN_COMILTSD,
19726 IX86_BUILTIN_COMILESD,
19727 IX86_BUILTIN_COMIGTSD,
19728 IX86_BUILTIN_COMIGESD,
19729 IX86_BUILTIN_COMINEQSD,
19730 IX86_BUILTIN_UCOMIEQSD,
19731 IX86_BUILTIN_UCOMILTSD,
19732 IX86_BUILTIN_UCOMILESD,
19733 IX86_BUILTIN_UCOMIGTSD,
19734 IX86_BUILTIN_UCOMIGESD,
19735 IX86_BUILTIN_UCOMINEQSD,
19737 IX86_BUILTIN_MAXPD,
19738 IX86_BUILTIN_MAXSD,
19739 IX86_BUILTIN_MINPD,
19740 IX86_BUILTIN_MINSD,
19742 IX86_BUILTIN_ANDPD,
19743 IX86_BUILTIN_ANDNPD,
19745 IX86_BUILTIN_XORPD,
19747 IX86_BUILTIN_SQRTPD,
19748 IX86_BUILTIN_SQRTSD,
19750 IX86_BUILTIN_UNPCKHPD,
19751 IX86_BUILTIN_UNPCKLPD,
19753 IX86_BUILTIN_SHUFPD,
19755 IX86_BUILTIN_LOADUPD,
19756 IX86_BUILTIN_STOREUPD,
19757 IX86_BUILTIN_MOVSD,
19759 IX86_BUILTIN_LOADHPD,
19760 IX86_BUILTIN_LOADLPD,
19762 IX86_BUILTIN_CVTDQ2PD,
19763 IX86_BUILTIN_CVTDQ2PS,
19765 IX86_BUILTIN_CVTPD2DQ,
19766 IX86_BUILTIN_CVTPD2PI,
19767 IX86_BUILTIN_CVTPD2PS,
19768 IX86_BUILTIN_CVTTPD2DQ,
19769 IX86_BUILTIN_CVTTPD2PI,
19771 IX86_BUILTIN_CVTPI2PD,
19772 IX86_BUILTIN_CVTSI2SD,
19773 IX86_BUILTIN_CVTSI642SD,
19775 IX86_BUILTIN_CVTSD2SI,
19776 IX86_BUILTIN_CVTSD2SI64,
19777 IX86_BUILTIN_CVTSD2SS,
19778 IX86_BUILTIN_CVTSS2SD,
19779 IX86_BUILTIN_CVTTSD2SI,
19780 IX86_BUILTIN_CVTTSD2SI64,
19782 IX86_BUILTIN_CVTPS2DQ,
19783 IX86_BUILTIN_CVTPS2PD,
19784 IX86_BUILTIN_CVTTPS2DQ,
19786 IX86_BUILTIN_MOVNTI,
19787 IX86_BUILTIN_MOVNTPD,
19788 IX86_BUILTIN_MOVNTDQ,
19790 IX86_BUILTIN_MOVQ128,
19793 IX86_BUILTIN_MASKMOVDQU,
19794 IX86_BUILTIN_MOVMSKPD,
19795 IX86_BUILTIN_PMOVMSKB128,
19797 IX86_BUILTIN_PACKSSWB128,
19798 IX86_BUILTIN_PACKSSDW128,
19799 IX86_BUILTIN_PACKUSWB128,
19801 IX86_BUILTIN_PADDB128,
19802 IX86_BUILTIN_PADDW128,
19803 IX86_BUILTIN_PADDD128,
19804 IX86_BUILTIN_PADDQ128,
19805 IX86_BUILTIN_PADDSB128,
19806 IX86_BUILTIN_PADDSW128,
19807 IX86_BUILTIN_PADDUSB128,
19808 IX86_BUILTIN_PADDUSW128,
19809 IX86_BUILTIN_PSUBB128,
19810 IX86_BUILTIN_PSUBW128,
19811 IX86_BUILTIN_PSUBD128,
19812 IX86_BUILTIN_PSUBQ128,
19813 IX86_BUILTIN_PSUBSB128,
19814 IX86_BUILTIN_PSUBSW128,
19815 IX86_BUILTIN_PSUBUSB128,
19816 IX86_BUILTIN_PSUBUSW128,
19818 IX86_BUILTIN_PAND128,
19819 IX86_BUILTIN_PANDN128,
19820 IX86_BUILTIN_POR128,
19821 IX86_BUILTIN_PXOR128,
19823 IX86_BUILTIN_PAVGB128,
19824 IX86_BUILTIN_PAVGW128,
19826 IX86_BUILTIN_PCMPEQB128,
19827 IX86_BUILTIN_PCMPEQW128,
19828 IX86_BUILTIN_PCMPEQD128,
19829 IX86_BUILTIN_PCMPGTB128,
19830 IX86_BUILTIN_PCMPGTW128,
19831 IX86_BUILTIN_PCMPGTD128,
19833 IX86_BUILTIN_PMADDWD128,
19835 IX86_BUILTIN_PMAXSW128,
19836 IX86_BUILTIN_PMAXUB128,
19837 IX86_BUILTIN_PMINSW128,
19838 IX86_BUILTIN_PMINUB128,
19840 IX86_BUILTIN_PMULUDQ,
19841 IX86_BUILTIN_PMULUDQ128,
19842 IX86_BUILTIN_PMULHUW128,
19843 IX86_BUILTIN_PMULHW128,
19844 IX86_BUILTIN_PMULLW128,
19846 IX86_BUILTIN_PSADBW128,
19847 IX86_BUILTIN_PSHUFHW,
19848 IX86_BUILTIN_PSHUFLW,
19849 IX86_BUILTIN_PSHUFD,
19851 IX86_BUILTIN_PSLLDQI128,
19852 IX86_BUILTIN_PSLLWI128,
19853 IX86_BUILTIN_PSLLDI128,
19854 IX86_BUILTIN_PSLLQI128,
19855 IX86_BUILTIN_PSRAWI128,
19856 IX86_BUILTIN_PSRADI128,
19857 IX86_BUILTIN_PSRLDQI128,
19858 IX86_BUILTIN_PSRLWI128,
19859 IX86_BUILTIN_PSRLDI128,
19860 IX86_BUILTIN_PSRLQI128,
19862 IX86_BUILTIN_PSLLDQ128,
19863 IX86_BUILTIN_PSLLW128,
19864 IX86_BUILTIN_PSLLD128,
19865 IX86_BUILTIN_PSLLQ128,
19866 IX86_BUILTIN_PSRAW128,
19867 IX86_BUILTIN_PSRAD128,
19868 IX86_BUILTIN_PSRLW128,
19869 IX86_BUILTIN_PSRLD128,
19870 IX86_BUILTIN_PSRLQ128,
19872 IX86_BUILTIN_PUNPCKHBW128,
19873 IX86_BUILTIN_PUNPCKHWD128,
19874 IX86_BUILTIN_PUNPCKHDQ128,
19875 IX86_BUILTIN_PUNPCKHQDQ128,
19876 IX86_BUILTIN_PUNPCKLBW128,
19877 IX86_BUILTIN_PUNPCKLWD128,
19878 IX86_BUILTIN_PUNPCKLDQ128,
19879 IX86_BUILTIN_PUNPCKLQDQ128,
19881 IX86_BUILTIN_CLFLUSH,
19882 IX86_BUILTIN_MFENCE,
19883 IX86_BUILTIN_LFENCE,
19886 IX86_BUILTIN_ADDSUBPS,
19887 IX86_BUILTIN_HADDPS,
19888 IX86_BUILTIN_HSUBPS,
19889 IX86_BUILTIN_MOVSHDUP,
19890 IX86_BUILTIN_MOVSLDUP,
19891 IX86_BUILTIN_ADDSUBPD,
19892 IX86_BUILTIN_HADDPD,
19893 IX86_BUILTIN_HSUBPD,
19894 IX86_BUILTIN_LDDQU,
19896 IX86_BUILTIN_MONITOR,
19897 IX86_BUILTIN_MWAIT,
19900 IX86_BUILTIN_PHADDW,
19901 IX86_BUILTIN_PHADDD,
19902 IX86_BUILTIN_PHADDSW,
19903 IX86_BUILTIN_PHSUBW,
19904 IX86_BUILTIN_PHSUBD,
19905 IX86_BUILTIN_PHSUBSW,
19906 IX86_BUILTIN_PMADDUBSW,
19907 IX86_BUILTIN_PMULHRSW,
19908 IX86_BUILTIN_PSHUFB,
19909 IX86_BUILTIN_PSIGNB,
19910 IX86_BUILTIN_PSIGNW,
19911 IX86_BUILTIN_PSIGND,
19912 IX86_BUILTIN_PALIGNR,
19913 IX86_BUILTIN_PABSB,
19914 IX86_BUILTIN_PABSW,
19915 IX86_BUILTIN_PABSD,
19917 IX86_BUILTIN_PHADDW128,
19918 IX86_BUILTIN_PHADDD128,
19919 IX86_BUILTIN_PHADDSW128,
19920 IX86_BUILTIN_PHSUBW128,
19921 IX86_BUILTIN_PHSUBD128,
19922 IX86_BUILTIN_PHSUBSW128,
19923 IX86_BUILTIN_PMADDUBSW128,
19924 IX86_BUILTIN_PMULHRSW128,
19925 IX86_BUILTIN_PSHUFB128,
19926 IX86_BUILTIN_PSIGNB128,
19927 IX86_BUILTIN_PSIGNW128,
19928 IX86_BUILTIN_PSIGND128,
19929 IX86_BUILTIN_PALIGNR128,
19930 IX86_BUILTIN_PABSB128,
19931 IX86_BUILTIN_PABSW128,
19932 IX86_BUILTIN_PABSD128,
19934 /* AMDFAM10 - SSE4A New Instructions. */
19935 IX86_BUILTIN_MOVNTSD,
19936 IX86_BUILTIN_MOVNTSS,
19937 IX86_BUILTIN_EXTRQI,
19938 IX86_BUILTIN_EXTRQ,
19939 IX86_BUILTIN_INSERTQI,
19940 IX86_BUILTIN_INSERTQ,
19943 IX86_BUILTIN_BLENDPD,
19944 IX86_BUILTIN_BLENDPS,
19945 IX86_BUILTIN_BLENDVPD,
19946 IX86_BUILTIN_BLENDVPS,
19947 IX86_BUILTIN_PBLENDVB128,
19948 IX86_BUILTIN_PBLENDW128,
19953 IX86_BUILTIN_INSERTPS128,
19955 IX86_BUILTIN_MOVNTDQA,
19956 IX86_BUILTIN_MPSADBW128,
19957 IX86_BUILTIN_PACKUSDW128,
19958 IX86_BUILTIN_PCMPEQQ,
19959 IX86_BUILTIN_PHMINPOSUW128,
19961 IX86_BUILTIN_PMAXSB128,
19962 IX86_BUILTIN_PMAXSD128,
19963 IX86_BUILTIN_PMAXUD128,
19964 IX86_BUILTIN_PMAXUW128,
19966 IX86_BUILTIN_PMINSB128,
19967 IX86_BUILTIN_PMINSD128,
19968 IX86_BUILTIN_PMINUD128,
19969 IX86_BUILTIN_PMINUW128,
19971 IX86_BUILTIN_PMOVSXBW128,
19972 IX86_BUILTIN_PMOVSXBD128,
19973 IX86_BUILTIN_PMOVSXBQ128,
19974 IX86_BUILTIN_PMOVSXWD128,
19975 IX86_BUILTIN_PMOVSXWQ128,
19976 IX86_BUILTIN_PMOVSXDQ128,
19978 IX86_BUILTIN_PMOVZXBW128,
19979 IX86_BUILTIN_PMOVZXBD128,
19980 IX86_BUILTIN_PMOVZXBQ128,
19981 IX86_BUILTIN_PMOVZXWD128,
19982 IX86_BUILTIN_PMOVZXWQ128,
19983 IX86_BUILTIN_PMOVZXDQ128,
19985 IX86_BUILTIN_PMULDQ128,
19986 IX86_BUILTIN_PMULLD128,
19988 IX86_BUILTIN_ROUNDPD,
19989 IX86_BUILTIN_ROUNDPS,
19990 IX86_BUILTIN_ROUNDSD,
19991 IX86_BUILTIN_ROUNDSS,
19993 IX86_BUILTIN_PTESTZ,
19994 IX86_BUILTIN_PTESTC,
19995 IX86_BUILTIN_PTESTNZC,
19997 IX86_BUILTIN_VEC_INIT_V2SI,
19998 IX86_BUILTIN_VEC_INIT_V4HI,
19999 IX86_BUILTIN_VEC_INIT_V8QI,
20000 IX86_BUILTIN_VEC_EXT_V2DF,
20001 IX86_BUILTIN_VEC_EXT_V2DI,
20002 IX86_BUILTIN_VEC_EXT_V4SF,
20003 IX86_BUILTIN_VEC_EXT_V4SI,
20004 IX86_BUILTIN_VEC_EXT_V8HI,
20005 IX86_BUILTIN_VEC_EXT_V2SI,
20006 IX86_BUILTIN_VEC_EXT_V4HI,
20007 IX86_BUILTIN_VEC_EXT_V16QI,
20008 IX86_BUILTIN_VEC_SET_V2DI,
20009 IX86_BUILTIN_VEC_SET_V4SF,
20010 IX86_BUILTIN_VEC_SET_V4SI,
20011 IX86_BUILTIN_VEC_SET_V8HI,
20012 IX86_BUILTIN_VEC_SET_V4HI,
20013 IX86_BUILTIN_VEC_SET_V16QI,
20015 IX86_BUILTIN_VEC_PACK_SFIX,
20018 IX86_BUILTIN_CRC32QI,
20019 IX86_BUILTIN_CRC32HI,
20020 IX86_BUILTIN_CRC32SI,
20021 IX86_BUILTIN_CRC32DI,
20023 IX86_BUILTIN_PCMPESTRI128,
20024 IX86_BUILTIN_PCMPESTRM128,
20025 IX86_BUILTIN_PCMPESTRA128,
20026 IX86_BUILTIN_PCMPESTRC128,
20027 IX86_BUILTIN_PCMPESTRO128,
20028 IX86_BUILTIN_PCMPESTRS128,
20029 IX86_BUILTIN_PCMPESTRZ128,
20030 IX86_BUILTIN_PCMPISTRI128,
20031 IX86_BUILTIN_PCMPISTRM128,
20032 IX86_BUILTIN_PCMPISTRA128,
20033 IX86_BUILTIN_PCMPISTRC128,
20034 IX86_BUILTIN_PCMPISTRO128,
20035 IX86_BUILTIN_PCMPISTRS128,
20036 IX86_BUILTIN_PCMPISTRZ128,
20038 IX86_BUILTIN_PCMPGTQ,
20040 /* AES instructions */
20041 IX86_BUILTIN_AESENC128,
20042 IX86_BUILTIN_AESENCLAST128,
20043 IX86_BUILTIN_AESDEC128,
20044 IX86_BUILTIN_AESDECLAST128,
20045 IX86_BUILTIN_AESIMC128,
20046 IX86_BUILTIN_AESKEYGENASSIST128,
20048 /* PCLMUL instruction */
20049 IX86_BUILTIN_PCLMULQDQ128,
20052 IX86_BUILTIN_ADDPD256,
20053 IX86_BUILTIN_ADDPS256,
20054 IX86_BUILTIN_ADDSUBPD256,
20055 IX86_BUILTIN_ADDSUBPS256,
20056 IX86_BUILTIN_ANDPD256,
20057 IX86_BUILTIN_ANDPS256,
20058 IX86_BUILTIN_ANDNPD256,
20059 IX86_BUILTIN_ANDNPS256,
20060 IX86_BUILTIN_BLENDPD256,
20061 IX86_BUILTIN_BLENDPS256,
20062 IX86_BUILTIN_BLENDVPD256,
20063 IX86_BUILTIN_BLENDVPS256,
20064 IX86_BUILTIN_DIVPD256,
20065 IX86_BUILTIN_DIVPS256,
20066 IX86_BUILTIN_DPPS256,
20067 IX86_BUILTIN_HADDPD256,
20068 IX86_BUILTIN_HADDPS256,
20069 IX86_BUILTIN_HSUBPD256,
20070 IX86_BUILTIN_HSUBPS256,
20071 IX86_BUILTIN_MAXPD256,
20072 IX86_BUILTIN_MAXPS256,
20073 IX86_BUILTIN_MINPD256,
20074 IX86_BUILTIN_MINPS256,
20075 IX86_BUILTIN_MULPD256,
20076 IX86_BUILTIN_MULPS256,
20077 IX86_BUILTIN_ORPD256,
20078 IX86_BUILTIN_ORPS256,
20079 IX86_BUILTIN_SHUFPD256,
20080 IX86_BUILTIN_SHUFPS256,
20081 IX86_BUILTIN_SUBPD256,
20082 IX86_BUILTIN_SUBPS256,
20083 IX86_BUILTIN_XORPD256,
20084 IX86_BUILTIN_XORPS256,
20085 IX86_BUILTIN_CMPSD,
20086 IX86_BUILTIN_CMPSS,
20087 IX86_BUILTIN_CMPPD,
20088 IX86_BUILTIN_CMPPS,
20089 IX86_BUILTIN_CMPPD256,
20090 IX86_BUILTIN_CMPPS256,
20091 IX86_BUILTIN_CVTDQ2PD256,
20092 IX86_BUILTIN_CVTDQ2PS256,
20093 IX86_BUILTIN_CVTPD2PS256,
20094 IX86_BUILTIN_CVTPS2DQ256,
20095 IX86_BUILTIN_CVTPS2PD256,
20096 IX86_BUILTIN_CVTTPD2DQ256,
20097 IX86_BUILTIN_CVTPD2DQ256,
20098 IX86_BUILTIN_CVTTPS2DQ256,
20099 IX86_BUILTIN_EXTRACTF128PD256,
20100 IX86_BUILTIN_EXTRACTF128PS256,
20101 IX86_BUILTIN_EXTRACTF128SI256,
20102 IX86_BUILTIN_VZEROALL,
20103 IX86_BUILTIN_VZEROUPPER,
20104 IX86_BUILTIN_VZEROUPPER_REX64,
20105 IX86_BUILTIN_VPERMILVARPD,
20106 IX86_BUILTIN_VPERMILVARPS,
20107 IX86_BUILTIN_VPERMILVARPD256,
20108 IX86_BUILTIN_VPERMILVARPS256,
20109 IX86_BUILTIN_VPERMILPD,
20110 IX86_BUILTIN_VPERMILPS,
20111 IX86_BUILTIN_VPERMILPD256,
20112 IX86_BUILTIN_VPERMILPS256,
20113 IX86_BUILTIN_VPERM2F128PD256,
20114 IX86_BUILTIN_VPERM2F128PS256,
20115 IX86_BUILTIN_VPERM2F128SI256,
20116 IX86_BUILTIN_VBROADCASTSS,
20117 IX86_BUILTIN_VBROADCASTSD256,
20118 IX86_BUILTIN_VBROADCASTSS256,
20119 IX86_BUILTIN_VBROADCASTPD256,
20120 IX86_BUILTIN_VBROADCASTPS256,
20121 IX86_BUILTIN_VINSERTF128PD256,
20122 IX86_BUILTIN_VINSERTF128PS256,
20123 IX86_BUILTIN_VINSERTF128SI256,
20124 IX86_BUILTIN_LOADUPD256,
20125 IX86_BUILTIN_LOADUPS256,
20126 IX86_BUILTIN_STOREUPD256,
20127 IX86_BUILTIN_STOREUPS256,
20128 IX86_BUILTIN_LDDQU256,
20129 IX86_BUILTIN_MOVNTDQ256,
20130 IX86_BUILTIN_MOVNTPD256,
20131 IX86_BUILTIN_MOVNTPS256,
20132 IX86_BUILTIN_LOADDQU256,
20133 IX86_BUILTIN_STOREDQU256,
20134 IX86_BUILTIN_MASKLOADPD,
20135 IX86_BUILTIN_MASKLOADPS,
20136 IX86_BUILTIN_MASKSTOREPD,
20137 IX86_BUILTIN_MASKSTOREPS,
20138 IX86_BUILTIN_MASKLOADPD256,
20139 IX86_BUILTIN_MASKLOADPS256,
20140 IX86_BUILTIN_MASKSTOREPD256,
20141 IX86_BUILTIN_MASKSTOREPS256,
20142 IX86_BUILTIN_MOVSHDUP256,
20143 IX86_BUILTIN_MOVSLDUP256,
20144 IX86_BUILTIN_MOVDDUP256,
20146 IX86_BUILTIN_SQRTPD256,
20147 IX86_BUILTIN_SQRTPS256,
20148 IX86_BUILTIN_SQRTPS_NR256,
20149 IX86_BUILTIN_RSQRTPS256,
20150 IX86_BUILTIN_RSQRTPS_NR256,
20152 IX86_BUILTIN_RCPPS256,
20154 IX86_BUILTIN_ROUNDPD256,
20155 IX86_BUILTIN_ROUNDPS256,
20157 IX86_BUILTIN_UNPCKHPD256,
20158 IX86_BUILTIN_UNPCKLPD256,
20159 IX86_BUILTIN_UNPCKHPS256,
20160 IX86_BUILTIN_UNPCKLPS256,
20162 IX86_BUILTIN_SI256_SI,
20163 IX86_BUILTIN_PS256_PS,
20164 IX86_BUILTIN_PD256_PD,
20165 IX86_BUILTIN_SI_SI256,
20166 IX86_BUILTIN_PS_PS256,
20167 IX86_BUILTIN_PD_PD256,
20169 IX86_BUILTIN_VTESTZPD,
20170 IX86_BUILTIN_VTESTCPD,
20171 IX86_BUILTIN_VTESTNZCPD,
20172 IX86_BUILTIN_VTESTZPS,
20173 IX86_BUILTIN_VTESTCPS,
20174 IX86_BUILTIN_VTESTNZCPS,
20175 IX86_BUILTIN_VTESTZPD256,
20176 IX86_BUILTIN_VTESTCPD256,
20177 IX86_BUILTIN_VTESTNZCPD256,
20178 IX86_BUILTIN_VTESTZPS256,
20179 IX86_BUILTIN_VTESTCPS256,
20180 IX86_BUILTIN_VTESTNZCPS256,
20181 IX86_BUILTIN_PTESTZ256,
20182 IX86_BUILTIN_PTESTC256,
20183 IX86_BUILTIN_PTESTNZC256,
20185 IX86_BUILTIN_MOVMSKPD256,
20186 IX86_BUILTIN_MOVMSKPS256,
20188 /* TFmode support builtins. */
20190 IX86_BUILTIN_FABSQ,
20191 IX86_BUILTIN_COPYSIGNQ,
20193 /* SSE5 instructions */
20194 IX86_BUILTIN_FMADDSS,
20195 IX86_BUILTIN_FMADDSD,
20196 IX86_BUILTIN_FMADDPS,
20197 IX86_BUILTIN_FMADDPD,
20198 IX86_BUILTIN_FMSUBSS,
20199 IX86_BUILTIN_FMSUBSD,
20200 IX86_BUILTIN_FMSUBPS,
20201 IX86_BUILTIN_FMSUBPD,
20202 IX86_BUILTIN_FNMADDSS,
20203 IX86_BUILTIN_FNMADDSD,
20204 IX86_BUILTIN_FNMADDPS,
20205 IX86_BUILTIN_FNMADDPD,
20206 IX86_BUILTIN_FNMSUBSS,
20207 IX86_BUILTIN_FNMSUBSD,
20208 IX86_BUILTIN_FNMSUBPS,
20209 IX86_BUILTIN_FNMSUBPD,
20210 IX86_BUILTIN_PCMOV,
20211 IX86_BUILTIN_PCMOV_V2DI,
20212 IX86_BUILTIN_PCMOV_V4SI,
20213 IX86_BUILTIN_PCMOV_V8HI,
20214 IX86_BUILTIN_PCMOV_V16QI,
20215 IX86_BUILTIN_PCMOV_V4SF,
20216 IX86_BUILTIN_PCMOV_V2DF,
20217 IX86_BUILTIN_PPERM,
20218 IX86_BUILTIN_PERMPS,
20219 IX86_BUILTIN_PERMPD,
20220 IX86_BUILTIN_PMACSSWW,
20221 IX86_BUILTIN_PMACSWW,
20222 IX86_BUILTIN_PMACSSWD,
20223 IX86_BUILTIN_PMACSWD,
20224 IX86_BUILTIN_PMACSSDD,
20225 IX86_BUILTIN_PMACSDD,
20226 IX86_BUILTIN_PMACSSDQL,
20227 IX86_BUILTIN_PMACSSDQH,
20228 IX86_BUILTIN_PMACSDQL,
20229 IX86_BUILTIN_PMACSDQH,
20230 IX86_BUILTIN_PMADCSSWD,
20231 IX86_BUILTIN_PMADCSWD,
20232 IX86_BUILTIN_PHADDBW,
20233 IX86_BUILTIN_PHADDBD,
20234 IX86_BUILTIN_PHADDBQ,
20235 IX86_BUILTIN_PHADDWD,
20236 IX86_BUILTIN_PHADDWQ,
20237 IX86_BUILTIN_PHADDDQ,
20238 IX86_BUILTIN_PHADDUBW,
20239 IX86_BUILTIN_PHADDUBD,
20240 IX86_BUILTIN_PHADDUBQ,
20241 IX86_BUILTIN_PHADDUWD,
20242 IX86_BUILTIN_PHADDUWQ,
20243 IX86_BUILTIN_PHADDUDQ,
20244 IX86_BUILTIN_PHSUBBW,
20245 IX86_BUILTIN_PHSUBWD,
20246 IX86_BUILTIN_PHSUBDQ,
20247 IX86_BUILTIN_PROTB,
20248 IX86_BUILTIN_PROTW,
20249 IX86_BUILTIN_PROTD,
20250 IX86_BUILTIN_PROTQ,
20251 IX86_BUILTIN_PROTB_IMM,
20252 IX86_BUILTIN_PROTW_IMM,
20253 IX86_BUILTIN_PROTD_IMM,
20254 IX86_BUILTIN_PROTQ_IMM,
20255 IX86_BUILTIN_PSHLB,
20256 IX86_BUILTIN_PSHLW,
20257 IX86_BUILTIN_PSHLD,
20258 IX86_BUILTIN_PSHLQ,
20259 IX86_BUILTIN_PSHAB,
20260 IX86_BUILTIN_PSHAW,
20261 IX86_BUILTIN_PSHAD,
20262 IX86_BUILTIN_PSHAQ,
20263 IX86_BUILTIN_FRCZSS,
20264 IX86_BUILTIN_FRCZSD,
20265 IX86_BUILTIN_FRCZPS,
20266 IX86_BUILTIN_FRCZPD,
20267 IX86_BUILTIN_CVTPH2PS,
20268 IX86_BUILTIN_CVTPS2PH,
20270 IX86_BUILTIN_COMEQSS,
20271 IX86_BUILTIN_COMNESS,
20272 IX86_BUILTIN_COMLTSS,
20273 IX86_BUILTIN_COMLESS,
20274 IX86_BUILTIN_COMGTSS,
20275 IX86_BUILTIN_COMGESS,
20276 IX86_BUILTIN_COMUEQSS,
20277 IX86_BUILTIN_COMUNESS,
20278 IX86_BUILTIN_COMULTSS,
20279 IX86_BUILTIN_COMULESS,
20280 IX86_BUILTIN_COMUGTSS,
20281 IX86_BUILTIN_COMUGESS,
20282 IX86_BUILTIN_COMORDSS,
20283 IX86_BUILTIN_COMUNORDSS,
20284 IX86_BUILTIN_COMFALSESS,
20285 IX86_BUILTIN_COMTRUESS,
20287 IX86_BUILTIN_COMEQSD,
20288 IX86_BUILTIN_COMNESD,
20289 IX86_BUILTIN_COMLTSD,
20290 IX86_BUILTIN_COMLESD,
20291 IX86_BUILTIN_COMGTSD,
20292 IX86_BUILTIN_COMGESD,
20293 IX86_BUILTIN_COMUEQSD,
20294 IX86_BUILTIN_COMUNESD,
20295 IX86_BUILTIN_COMULTSD,
20296 IX86_BUILTIN_COMULESD,
20297 IX86_BUILTIN_COMUGTSD,
20298 IX86_BUILTIN_COMUGESD,
20299 IX86_BUILTIN_COMORDSD,
20300 IX86_BUILTIN_COMUNORDSD,
20301 IX86_BUILTIN_COMFALSESD,
20302 IX86_BUILTIN_COMTRUESD,
20304 IX86_BUILTIN_COMEQPS,
20305 IX86_BUILTIN_COMNEPS,
20306 IX86_BUILTIN_COMLTPS,
20307 IX86_BUILTIN_COMLEPS,
20308 IX86_BUILTIN_COMGTPS,
20309 IX86_BUILTIN_COMGEPS,
20310 IX86_BUILTIN_COMUEQPS,
20311 IX86_BUILTIN_COMUNEPS,
20312 IX86_BUILTIN_COMULTPS,
20313 IX86_BUILTIN_COMULEPS,
20314 IX86_BUILTIN_COMUGTPS,
20315 IX86_BUILTIN_COMUGEPS,
20316 IX86_BUILTIN_COMORDPS,
20317 IX86_BUILTIN_COMUNORDPS,
20318 IX86_BUILTIN_COMFALSEPS,
20319 IX86_BUILTIN_COMTRUEPS,
20321 IX86_BUILTIN_COMEQPD,
20322 IX86_BUILTIN_COMNEPD,
20323 IX86_BUILTIN_COMLTPD,
20324 IX86_BUILTIN_COMLEPD,
20325 IX86_BUILTIN_COMGTPD,
20326 IX86_BUILTIN_COMGEPD,
20327 IX86_BUILTIN_COMUEQPD,
20328 IX86_BUILTIN_COMUNEPD,
20329 IX86_BUILTIN_COMULTPD,
20330 IX86_BUILTIN_COMULEPD,
20331 IX86_BUILTIN_COMUGTPD,
20332 IX86_BUILTIN_COMUGEPD,
20333 IX86_BUILTIN_COMORDPD,
20334 IX86_BUILTIN_COMUNORDPD,
20335 IX86_BUILTIN_COMFALSEPD,
20336 IX86_BUILTIN_COMTRUEPD,
20338 IX86_BUILTIN_PCOMEQUB,
20339 IX86_BUILTIN_PCOMNEUB,
20340 IX86_BUILTIN_PCOMLTUB,
20341 IX86_BUILTIN_PCOMLEUB,
20342 IX86_BUILTIN_PCOMGTUB,
20343 IX86_BUILTIN_PCOMGEUB,
20344 IX86_BUILTIN_PCOMFALSEUB,
20345 IX86_BUILTIN_PCOMTRUEUB,
20346 IX86_BUILTIN_PCOMEQUW,
20347 IX86_BUILTIN_PCOMNEUW,
20348 IX86_BUILTIN_PCOMLTUW,
20349 IX86_BUILTIN_PCOMLEUW,
20350 IX86_BUILTIN_PCOMGTUW,
20351 IX86_BUILTIN_PCOMGEUW,
20352 IX86_BUILTIN_PCOMFALSEUW,
20353 IX86_BUILTIN_PCOMTRUEUW,
20354 IX86_BUILTIN_PCOMEQUD,
20355 IX86_BUILTIN_PCOMNEUD,
20356 IX86_BUILTIN_PCOMLTUD,
20357 IX86_BUILTIN_PCOMLEUD,
20358 IX86_BUILTIN_PCOMGTUD,
20359 IX86_BUILTIN_PCOMGEUD,
20360 IX86_BUILTIN_PCOMFALSEUD,
20361 IX86_BUILTIN_PCOMTRUEUD,
20362 IX86_BUILTIN_PCOMEQUQ,
20363 IX86_BUILTIN_PCOMNEUQ,
20364 IX86_BUILTIN_PCOMLTUQ,
20365 IX86_BUILTIN_PCOMLEUQ,
20366 IX86_BUILTIN_PCOMGTUQ,
20367 IX86_BUILTIN_PCOMGEUQ,
20368 IX86_BUILTIN_PCOMFALSEUQ,
20369 IX86_BUILTIN_PCOMTRUEUQ,
20371 IX86_BUILTIN_PCOMEQB,
20372 IX86_BUILTIN_PCOMNEB,
20373 IX86_BUILTIN_PCOMLTB,
20374 IX86_BUILTIN_PCOMLEB,
20375 IX86_BUILTIN_PCOMGTB,
20376 IX86_BUILTIN_PCOMGEB,
20377 IX86_BUILTIN_PCOMFALSEB,
20378 IX86_BUILTIN_PCOMTRUEB,
20379 IX86_BUILTIN_PCOMEQW,
20380 IX86_BUILTIN_PCOMNEW,
20381 IX86_BUILTIN_PCOMLTW,
20382 IX86_BUILTIN_PCOMLEW,
20383 IX86_BUILTIN_PCOMGTW,
20384 IX86_BUILTIN_PCOMGEW,
20385 IX86_BUILTIN_PCOMFALSEW,
20386 IX86_BUILTIN_PCOMTRUEW,
20387 IX86_BUILTIN_PCOMEQD,
20388 IX86_BUILTIN_PCOMNED,
20389 IX86_BUILTIN_PCOMLTD,
20390 IX86_BUILTIN_PCOMLED,
20391 IX86_BUILTIN_PCOMGTD,
20392 IX86_BUILTIN_PCOMGED,
20393 IX86_BUILTIN_PCOMFALSED,
20394 IX86_BUILTIN_PCOMTRUED,
20395 IX86_BUILTIN_PCOMEQQ,
20396 IX86_BUILTIN_PCOMNEQ,
20397 IX86_BUILTIN_PCOMLTQ,
20398 IX86_BUILTIN_PCOMLEQ,
20399 IX86_BUILTIN_PCOMGTQ,
20400 IX86_BUILTIN_PCOMGEQ,
20401 IX86_BUILTIN_PCOMFALSEQ,
20402 IX86_BUILTIN_PCOMTRUEQ,
20407 /* Table for the ix86 builtin decls. */
20408 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20410 /* Table of all of the builtin functions that are possible with different ISA's
20411 but are waiting to be built until a function is declared to use that
20413 struct builtin_isa GTY(())
20415 tree type; /* builtin type to use in the declaration */
20416 const char *name; /* function name */
20417 int isa; /* isa_flags this builtin is defined for */
20418 bool const_p; /* true if the declaration is constant */
20421 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20424 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20425 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20426 * function decl in the ix86_builtins array. Returns the function decl or
20427 * NULL_TREE, if the builtin was not added.
20429 * If the front end has a special hook for builtin functions, delay adding
20430 * builtin functions that aren't in the current ISA until the ISA is changed
20431 * with function specific optimization. Doing so, can save about 300K for the
20432 * default compiler. When the builtin is expanded, check at that time whether
20435 * If the front end doesn't have a special hook, record all builtins, even if
20436 * it isn't an instruction set in the current ISA in case the user uses
20437 * function specific options for a different ISA, so that we don't get scope
20438 * errors if a builtin is added in the middle of a function scope. */
20441 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20443 tree decl = NULL_TREE;
20445 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20447 ix86_builtins_isa[(int) code].isa = mask;
20449 if ((mask & ix86_isa_flags) != 0
20450 || (lang_hooks.builtin_function
20451 == lang_hooks.builtin_function_ext_scope))
20454 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20456 ix86_builtins[(int) code] = decl;
20457 ix86_builtins_isa[(int) code].type = NULL_TREE;
20461 ix86_builtins[(int) code] = NULL_TREE;
20462 ix86_builtins_isa[(int) code].const_p = false;
20463 ix86_builtins_isa[(int) code].type = type;
20464 ix86_builtins_isa[(int) code].name = name;
20471 /* Like def_builtin, but also marks the function decl "const". */
20474 def_builtin_const (int mask, const char *name, tree type,
20475 enum ix86_builtins code)
20477 tree decl = def_builtin (mask, name, type, code);
20479 TREE_READONLY (decl) = 1;
20481 ix86_builtins_isa[(int) code].const_p = true;
20486 /* Add any new builtin functions for a given ISA that may not have been
20487 declared. This saves a bit of space compared to adding all of the
20488 declarations to the tree, even if we didn't use them. */
20491 ix86_add_new_builtins (int isa)
20496 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20498 if ((ix86_builtins_isa[i].isa & isa) != 0
20499 && ix86_builtins_isa[i].type != NULL_TREE)
20501 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20502 ix86_builtins_isa[i].type,
20503 i, BUILT_IN_MD, NULL,
20506 ix86_builtins[i] = decl;
20507 ix86_builtins_isa[i].type = NULL_TREE;
20508 if (ix86_builtins_isa[i].const_p)
20509 TREE_READONLY (decl) = 1;
20514 /* Bits for builtin_description.flag. */
20516 /* Set when we don't support the comparison natively, and should
20517 swap_comparison in order to support it. */
20518 #define BUILTIN_DESC_SWAP_OPERANDS 1
20520 struct builtin_description
20522 const unsigned int mask;
20523 const enum insn_code icode;
20524 const char *const name;
20525 const enum ix86_builtins code;
20526 const enum rtx_code comparison;
20530 static const struct builtin_description bdesc_comi[] =
20532 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20534 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20536 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20537 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20538 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20539 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20540 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20541 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20542 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20543 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20558 static const struct builtin_description bdesc_pcmpestr[] =
20561 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20562 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20563 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20564 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20565 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20566 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20567 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20570 static const struct builtin_description bdesc_pcmpistr[] =
20573 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20574 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20575 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20576 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20577 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20578 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20579 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20582 /* Special builtin types */
20583 enum ix86_special_builtin_type
20585 SPECIAL_FTYPE_UNKNOWN,
20587 V32QI_FTYPE_PCCHAR,
20588 V16QI_FTYPE_PCCHAR,
20590 V8SF_FTYPE_PCFLOAT,
20592 V4DF_FTYPE_PCDOUBLE,
20593 V4SF_FTYPE_PCFLOAT,
20594 V2DF_FTYPE_PCDOUBLE,
20595 V8SF_FTYPE_PCV8SF_V8SF,
20596 V4DF_FTYPE_PCV4DF_V4DF,
20597 V4SF_FTYPE_V4SF_PCV2SF,
20598 V4SF_FTYPE_PCV4SF_V4SF,
20599 V2DF_FTYPE_V2DF_PCDOUBLE,
20600 V2DF_FTYPE_PCV2DF_V2DF,
20602 VOID_FTYPE_PV2SF_V4SF,
20603 VOID_FTYPE_PV4DI_V4DI,
20604 VOID_FTYPE_PV2DI_V2DI,
20605 VOID_FTYPE_PCHAR_V32QI,
20606 VOID_FTYPE_PCHAR_V16QI,
20607 VOID_FTYPE_PFLOAT_V8SF,
20608 VOID_FTYPE_PFLOAT_V4SF,
20609 VOID_FTYPE_PDOUBLE_V4DF,
20610 VOID_FTYPE_PDOUBLE_V2DF,
20612 VOID_FTYPE_PINT_INT,
20613 VOID_FTYPE_PV8SF_V8SF_V8SF,
20614 VOID_FTYPE_PV4DF_V4DF_V4DF,
20615 VOID_FTYPE_PV4SF_V4SF_V4SF,
20616 VOID_FTYPE_PV2DF_V2DF_V2DF
20619 /* Builtin types */
20620 enum ix86_builtin_type
20623 FLOAT128_FTYPE_FLOAT128,
20625 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20626 INT_FTYPE_V8SF_V8SF_PTEST,
20627 INT_FTYPE_V4DI_V4DI_PTEST,
20628 INT_FTYPE_V4DF_V4DF_PTEST,
20629 INT_FTYPE_V4SF_V4SF_PTEST,
20630 INT_FTYPE_V2DI_V2DI_PTEST,
20631 INT_FTYPE_V2DF_V2DF_PTEST,
20663 V4SF_FTYPE_V4SF_VEC_MERGE,
20672 V2DF_FTYPE_V2DF_VEC_MERGE,
20683 V16QI_FTYPE_V16QI_V16QI,
20684 V16QI_FTYPE_V8HI_V8HI,
20685 V8QI_FTYPE_V8QI_V8QI,
20686 V8QI_FTYPE_V4HI_V4HI,
20687 V8HI_FTYPE_V8HI_V8HI,
20688 V8HI_FTYPE_V8HI_V8HI_COUNT,
20689 V8HI_FTYPE_V16QI_V16QI,
20690 V8HI_FTYPE_V4SI_V4SI,
20691 V8HI_FTYPE_V8HI_SI_COUNT,
20692 V8SF_FTYPE_V8SF_V8SF,
20693 V8SF_FTYPE_V8SF_V8SI,
20694 V4SI_FTYPE_V4SI_V4SI,
20695 V4SI_FTYPE_V4SI_V4SI_COUNT,
20696 V4SI_FTYPE_V8HI_V8HI,
20697 V4SI_FTYPE_V4SF_V4SF,
20698 V4SI_FTYPE_V2DF_V2DF,
20699 V4SI_FTYPE_V4SI_SI_COUNT,
20700 V4HI_FTYPE_V4HI_V4HI,
20701 V4HI_FTYPE_V4HI_V4HI_COUNT,
20702 V4HI_FTYPE_V8QI_V8QI,
20703 V4HI_FTYPE_V2SI_V2SI,
20704 V4HI_FTYPE_V4HI_SI_COUNT,
20705 V4DF_FTYPE_V4DF_V4DF,
20706 V4DF_FTYPE_V4DF_V4DI,
20707 V4SF_FTYPE_V4SF_V4SF,
20708 V4SF_FTYPE_V4SF_V4SF_SWAP,
20709 V4SF_FTYPE_V4SF_V4SI,
20710 V4SF_FTYPE_V4SF_V2SI,
20711 V4SF_FTYPE_V4SF_V2DF,
20712 V4SF_FTYPE_V4SF_DI,
20713 V4SF_FTYPE_V4SF_SI,
20714 V2DI_FTYPE_V2DI_V2DI,
20715 V2DI_FTYPE_V2DI_V2DI_COUNT,
20716 V2DI_FTYPE_V16QI_V16QI,
20717 V2DI_FTYPE_V4SI_V4SI,
20718 V2DI_FTYPE_V2DI_V16QI,
20719 V2DI_FTYPE_V2DF_V2DF,
20720 V2DI_FTYPE_V2DI_SI_COUNT,
20721 V2SI_FTYPE_V2SI_V2SI,
20722 V2SI_FTYPE_V2SI_V2SI_COUNT,
20723 V2SI_FTYPE_V4HI_V4HI,
20724 V2SI_FTYPE_V2SF_V2SF,
20725 V2SI_FTYPE_V2SI_SI_COUNT,
20726 V2DF_FTYPE_V2DF_V2DF,
20727 V2DF_FTYPE_V2DF_V2DF_SWAP,
20728 V2DF_FTYPE_V2DF_V4SF,
20729 V2DF_FTYPE_V2DF_V2DI,
20730 V2DF_FTYPE_V2DF_DI,
20731 V2DF_FTYPE_V2DF_SI,
20732 V2SF_FTYPE_V2SF_V2SF,
20733 V1DI_FTYPE_V1DI_V1DI,
20734 V1DI_FTYPE_V1DI_V1DI_COUNT,
20735 V1DI_FTYPE_V8QI_V8QI,
20736 V1DI_FTYPE_V2SI_V2SI,
20737 V1DI_FTYPE_V1DI_SI_COUNT,
20738 UINT64_FTYPE_UINT64_UINT64,
20739 UINT_FTYPE_UINT_UINT,
20740 UINT_FTYPE_UINT_USHORT,
20741 UINT_FTYPE_UINT_UCHAR,
20742 V8HI_FTYPE_V8HI_INT,
20743 V4SI_FTYPE_V4SI_INT,
20744 V4HI_FTYPE_V4HI_INT,
20745 V8SF_FTYPE_V8SF_INT,
20746 V4SI_FTYPE_V8SI_INT,
20747 V4SF_FTYPE_V8SF_INT,
20748 V2DF_FTYPE_V4DF_INT,
20749 V4DF_FTYPE_V4DF_INT,
20750 V4SF_FTYPE_V4SF_INT,
20751 V2DI_FTYPE_V2DI_INT,
20752 V2DI2TI_FTYPE_V2DI_INT,
20753 V2DF_FTYPE_V2DF_INT,
20754 V16QI_FTYPE_V16QI_V16QI_V16QI,
20755 V8SF_FTYPE_V8SF_V8SF_V8SF,
20756 V4DF_FTYPE_V4DF_V4DF_V4DF,
20757 V4SF_FTYPE_V4SF_V4SF_V4SF,
20758 V2DF_FTYPE_V2DF_V2DF_V2DF,
20759 V16QI_FTYPE_V16QI_V16QI_INT,
20760 V8SI_FTYPE_V8SI_V8SI_INT,
20761 V8SI_FTYPE_V8SI_V4SI_INT,
20762 V8HI_FTYPE_V8HI_V8HI_INT,
20763 V8SF_FTYPE_V8SF_V8SF_INT,
20764 V8SF_FTYPE_V8SF_V4SF_INT,
20765 V4SI_FTYPE_V4SI_V4SI_INT,
20766 V4DF_FTYPE_V4DF_V4DF_INT,
20767 V4DF_FTYPE_V4DF_V2DF_INT,
20768 V4SF_FTYPE_V4SF_V4SF_INT,
20769 V2DI_FTYPE_V2DI_V2DI_INT,
20770 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20771 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20772 V2DF_FTYPE_V2DF_V2DF_INT,
20773 V2DI_FTYPE_V2DI_UINT_UINT,
20774 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20777 /* Special builtins with variable number of arguments. */
20778 static const struct builtin_description bdesc_special_args[] =
20781 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20784 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20789 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20791 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20792 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20793 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20796 /* SSE or 3DNow!A */
20797 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20798 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20801 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20802 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20803 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20815 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20818 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20821 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20822 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20827 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
20844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20857 /* Builtins with variable number of arguments. */
20858 static const struct builtin_description bdesc_args[] =
20861 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20862 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20863 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20864 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20865 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20866 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20868 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20869 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20870 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20871 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20872 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20873 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20874 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20875 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20877 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20878 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20880 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20881 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20886 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20887 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20890 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20893 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20894 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20896 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20897 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20899 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20900 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20901 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20903 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20905 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20906 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20907 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20908 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20909 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20910 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20912 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20913 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20914 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20915 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20919 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20920 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20921 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20925 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20926 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20927 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20928 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20930 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20931 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20932 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20933 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20934 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20935 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20936 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20937 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20938 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20939 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20940 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20941 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20942 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20943 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20944 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20947 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20948 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20949 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20950 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20951 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20952 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20957 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20959 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20963 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20965 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20966 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20970 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20971 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20972 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20986 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20987 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20993 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20994 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21002 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21003 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21007 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21009 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21010 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21020 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21022 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21028 /* SSE MMX or 3Dnow!A */
21029 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21030 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21031 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21033 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21034 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21035 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21036 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21038 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21039 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21041 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21055 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21060 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21062 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21063 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21069 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21070 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21071 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21072 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21100 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21107 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21113 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21115 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21116 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21117 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21118 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21119 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21120 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21121 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21122 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21133 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21134 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21136 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21139 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21151 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21152 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21153 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21169 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21178 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21183 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21184 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21185 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21186 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21187 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21188 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21191 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21192 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21193 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21194 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21195 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21196 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21198 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21199 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21200 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21201 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21209 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21210 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21215 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21216 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21219 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21220 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21222 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21223 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21224 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21225 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21226 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21227 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21230 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21231 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21232 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21233 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21234 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21235 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21237 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21238 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21239 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21240 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21241 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21242 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21243 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21244 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21245 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21246 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21247 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21248 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21251 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21252 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21253 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21254 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21255 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21258 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21259 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21260 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21263 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21264 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21267 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21270 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21271 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21272 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21273 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21274 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21275 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21276 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21278 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21279 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21280 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21281 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21282 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21283 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21284 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21285 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21286 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21287 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21288 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21289 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21293 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21294 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21295 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21296 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21297 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21298 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21299 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21300 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21301 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21302 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21303 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21305 /* SSE4.1 and SSE5 */
21306 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21307 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21308 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21309 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21311 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21312 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21313 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21316 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21317 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21318 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21319 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21320 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21323 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21324 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21325 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21326 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21330 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21335 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21341 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21342 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21343 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21344 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21345 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21346 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21347 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21348 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21349 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21350 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21351 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21352 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21353 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21354 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21355 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21356 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21357 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21358 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21359 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21360 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21361 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21362 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21363 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21364 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21365 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21366 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21374 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21378 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21379 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21384 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21395 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21400 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21412 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21414 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21416 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21439 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21451 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21456 enum multi_arg_type {
21466 MULTI_ARG_3_PERMPS,
21467 MULTI_ARG_3_PERMPD,
21474 MULTI_ARG_2_DI_IMM,
21475 MULTI_ARG_2_SI_IMM,
21476 MULTI_ARG_2_HI_IMM,
21477 MULTI_ARG_2_QI_IMM,
21478 MULTI_ARG_2_SF_CMP,
21479 MULTI_ARG_2_DF_CMP,
21480 MULTI_ARG_2_DI_CMP,
21481 MULTI_ARG_2_SI_CMP,
21482 MULTI_ARG_2_HI_CMP,
21483 MULTI_ARG_2_QI_CMP,
21506 static const struct builtin_description bdesc_multi_arg[] =
21508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21576 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21661 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21668 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21669 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21673 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21674 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21676 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21677 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21682 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21690 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21738 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21744 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21745 in the current target ISA to allow the user to compile particular modules
21746 with different target specific options that differ from the command line
21749 ix86_init_mmx_sse_builtins (void)
21751 const struct builtin_description * d;
21754 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21755 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21756 tree V1DI_type_node
21757 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21758 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21759 tree V2DI_type_node
21760 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21761 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21762 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21763 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21764 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21765 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21766 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21768 tree pchar_type_node = build_pointer_type (char_type_node);
21769 tree pcchar_type_node
21770 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21771 tree pfloat_type_node = build_pointer_type (float_type_node);
21772 tree pcfloat_type_node
21773 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21774 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21775 tree pcv2sf_type_node
21776 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21777 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21778 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21781 tree int_ftype_v4sf_v4sf
21782 = build_function_type_list (integer_type_node,
21783 V4SF_type_node, V4SF_type_node, NULL_TREE);
21784 tree v4si_ftype_v4sf_v4sf
21785 = build_function_type_list (V4SI_type_node,
21786 V4SF_type_node, V4SF_type_node, NULL_TREE);
21787 /* MMX/SSE/integer conversions. */
21788 tree int_ftype_v4sf
21789 = build_function_type_list (integer_type_node,
21790 V4SF_type_node, NULL_TREE);
21791 tree int64_ftype_v4sf
21792 = build_function_type_list (long_long_integer_type_node,
21793 V4SF_type_node, NULL_TREE);
21794 tree int_ftype_v8qi
21795 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21796 tree v4sf_ftype_v4sf_int
21797 = build_function_type_list (V4SF_type_node,
21798 V4SF_type_node, integer_type_node, NULL_TREE);
21799 tree v4sf_ftype_v4sf_int64
21800 = build_function_type_list (V4SF_type_node,
21801 V4SF_type_node, long_long_integer_type_node,
21803 tree v4sf_ftype_v4sf_v2si
21804 = build_function_type_list (V4SF_type_node,
21805 V4SF_type_node, V2SI_type_node, NULL_TREE);
21807 /* Miscellaneous. */
21808 tree v8qi_ftype_v4hi_v4hi
21809 = build_function_type_list (V8QI_type_node,
21810 V4HI_type_node, V4HI_type_node, NULL_TREE);
21811 tree v4hi_ftype_v2si_v2si
21812 = build_function_type_list (V4HI_type_node,
21813 V2SI_type_node, V2SI_type_node, NULL_TREE);
21814 tree v4sf_ftype_v4sf_v4sf_int
21815 = build_function_type_list (V4SF_type_node,
21816 V4SF_type_node, V4SF_type_node,
21817 integer_type_node, NULL_TREE);
21818 tree v2si_ftype_v4hi_v4hi
21819 = build_function_type_list (V2SI_type_node,
21820 V4HI_type_node, V4HI_type_node, NULL_TREE);
21821 tree v4hi_ftype_v4hi_int
21822 = build_function_type_list (V4HI_type_node,
21823 V4HI_type_node, integer_type_node, NULL_TREE);
21824 tree v2si_ftype_v2si_int
21825 = build_function_type_list (V2SI_type_node,
21826 V2SI_type_node, integer_type_node, NULL_TREE);
21827 tree v1di_ftype_v1di_int
21828 = build_function_type_list (V1DI_type_node,
21829 V1DI_type_node, integer_type_node, NULL_TREE);
21831 tree void_ftype_void
21832 = build_function_type (void_type_node, void_list_node);
21833 tree void_ftype_unsigned
21834 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21835 tree void_ftype_unsigned_unsigned
21836 = build_function_type_list (void_type_node, unsigned_type_node,
21837 unsigned_type_node, NULL_TREE);
21838 tree void_ftype_pcvoid_unsigned_unsigned
21839 = build_function_type_list (void_type_node, const_ptr_type_node,
21840 unsigned_type_node, unsigned_type_node,
21842 tree unsigned_ftype_void
21843 = build_function_type (unsigned_type_node, void_list_node);
21844 tree v2si_ftype_v4sf
21845 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21846 /* Loads/stores. */
21847 tree void_ftype_v8qi_v8qi_pchar
21848 = build_function_type_list (void_type_node,
21849 V8QI_type_node, V8QI_type_node,
21850 pchar_type_node, NULL_TREE);
21851 tree v4sf_ftype_pcfloat
21852 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21853 tree v4sf_ftype_v4sf_pcv2sf
21854 = build_function_type_list (V4SF_type_node,
21855 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21856 tree void_ftype_pv2sf_v4sf
21857 = build_function_type_list (void_type_node,
21858 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21859 tree void_ftype_pfloat_v4sf
21860 = build_function_type_list (void_type_node,
21861 pfloat_type_node, V4SF_type_node, NULL_TREE);
21862 tree void_ftype_pdi_di
21863 = build_function_type_list (void_type_node,
21864 pdi_type_node, long_long_unsigned_type_node,
21866 tree void_ftype_pv2di_v2di
21867 = build_function_type_list (void_type_node,
21868 pv2di_type_node, V2DI_type_node, NULL_TREE);
21869 /* Normal vector unops. */
21870 tree v4sf_ftype_v4sf
21871 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21872 tree v16qi_ftype_v16qi
21873 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21874 tree v8hi_ftype_v8hi
21875 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21876 tree v4si_ftype_v4si
21877 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21878 tree v8qi_ftype_v8qi
21879 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21880 tree v4hi_ftype_v4hi
21881 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21883 /* Normal vector binops. */
21884 tree v4sf_ftype_v4sf_v4sf
21885 = build_function_type_list (V4SF_type_node,
21886 V4SF_type_node, V4SF_type_node, NULL_TREE);
21887 tree v8qi_ftype_v8qi_v8qi
21888 = build_function_type_list (V8QI_type_node,
21889 V8QI_type_node, V8QI_type_node, NULL_TREE);
21890 tree v4hi_ftype_v4hi_v4hi
21891 = build_function_type_list (V4HI_type_node,
21892 V4HI_type_node, V4HI_type_node, NULL_TREE);
21893 tree v2si_ftype_v2si_v2si
21894 = build_function_type_list (V2SI_type_node,
21895 V2SI_type_node, V2SI_type_node, NULL_TREE);
21896 tree v1di_ftype_v1di_v1di
21897 = build_function_type_list (V1DI_type_node,
21898 V1DI_type_node, V1DI_type_node, NULL_TREE);
21899 tree v1di_ftype_v1di_v1di_int
21900 = build_function_type_list (V1DI_type_node,
21901 V1DI_type_node, V1DI_type_node,
21902 integer_type_node, NULL_TREE);
21903 tree v2si_ftype_v2sf
21904 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21905 tree v2sf_ftype_v2si
21906 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21907 tree v2si_ftype_v2si
21908 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21909 tree v2sf_ftype_v2sf
21910 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21911 tree v2sf_ftype_v2sf_v2sf
21912 = build_function_type_list (V2SF_type_node,
21913 V2SF_type_node, V2SF_type_node, NULL_TREE);
21914 tree v2si_ftype_v2sf_v2sf
21915 = build_function_type_list (V2SI_type_node,
21916 V2SF_type_node, V2SF_type_node, NULL_TREE);
21917 tree pint_type_node = build_pointer_type (integer_type_node);
21918 tree pdouble_type_node = build_pointer_type (double_type_node);
21919 tree pcdouble_type_node = build_pointer_type (
21920 build_type_variant (double_type_node, 1, 0));
21921 tree int_ftype_v2df_v2df
21922 = build_function_type_list (integer_type_node,
21923 V2DF_type_node, V2DF_type_node, NULL_TREE);
21925 tree void_ftype_pcvoid
21926 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21927 tree v4sf_ftype_v4si
21928 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21929 tree v4si_ftype_v4sf
21930 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21931 tree v2df_ftype_v4si
21932 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21933 tree v4si_ftype_v2df
21934 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21935 tree v4si_ftype_v2df_v2df
21936 = build_function_type_list (V4SI_type_node,
21937 V2DF_type_node, V2DF_type_node, NULL_TREE);
21938 tree v2si_ftype_v2df
21939 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21940 tree v4sf_ftype_v2df
21941 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21942 tree v2df_ftype_v2si
21943 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21944 tree v2df_ftype_v4sf
21945 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21946 tree int_ftype_v2df
21947 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21948 tree int64_ftype_v2df
21949 = build_function_type_list (long_long_integer_type_node,
21950 V2DF_type_node, NULL_TREE);
21951 tree v2df_ftype_v2df_int
21952 = build_function_type_list (V2DF_type_node,
21953 V2DF_type_node, integer_type_node, NULL_TREE);
21954 tree v2df_ftype_v2df_int64
21955 = build_function_type_list (V2DF_type_node,
21956 V2DF_type_node, long_long_integer_type_node,
21958 tree v4sf_ftype_v4sf_v2df
21959 = build_function_type_list (V4SF_type_node,
21960 V4SF_type_node, V2DF_type_node, NULL_TREE);
21961 tree v2df_ftype_v2df_v4sf
21962 = build_function_type_list (V2DF_type_node,
21963 V2DF_type_node, V4SF_type_node, NULL_TREE);
21964 tree v2df_ftype_v2df_v2df_int
21965 = build_function_type_list (V2DF_type_node,
21966 V2DF_type_node, V2DF_type_node,
21969 tree v2df_ftype_v2df_pcdouble
21970 = build_function_type_list (V2DF_type_node,
21971 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21972 tree void_ftype_pdouble_v2df
21973 = build_function_type_list (void_type_node,
21974 pdouble_type_node, V2DF_type_node, NULL_TREE);
21975 tree void_ftype_pint_int
21976 = build_function_type_list (void_type_node,
21977 pint_type_node, integer_type_node, NULL_TREE);
21978 tree void_ftype_v16qi_v16qi_pchar
21979 = build_function_type_list (void_type_node,
21980 V16QI_type_node, V16QI_type_node,
21981 pchar_type_node, NULL_TREE);
21982 tree v2df_ftype_pcdouble
21983 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21984 tree v2df_ftype_v2df_v2df
21985 = build_function_type_list (V2DF_type_node,
21986 V2DF_type_node, V2DF_type_node, NULL_TREE);
21987 tree v16qi_ftype_v16qi_v16qi
21988 = build_function_type_list (V16QI_type_node,
21989 V16QI_type_node, V16QI_type_node, NULL_TREE);
21990 tree v8hi_ftype_v8hi_v8hi
21991 = build_function_type_list (V8HI_type_node,
21992 V8HI_type_node, V8HI_type_node, NULL_TREE);
21993 tree v4si_ftype_v4si_v4si
21994 = build_function_type_list (V4SI_type_node,
21995 V4SI_type_node, V4SI_type_node, NULL_TREE);
21996 tree v2di_ftype_v2di_v2di
21997 = build_function_type_list (V2DI_type_node,
21998 V2DI_type_node, V2DI_type_node, NULL_TREE);
21999 tree v2di_ftype_v2df_v2df
22000 = build_function_type_list (V2DI_type_node,
22001 V2DF_type_node, V2DF_type_node, NULL_TREE);
22002 tree v2df_ftype_v2df
22003 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22004 tree v2di_ftype_v2di_int
22005 = build_function_type_list (V2DI_type_node,
22006 V2DI_type_node, integer_type_node, NULL_TREE);
22007 tree v2di_ftype_v2di_v2di_int
22008 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22009 V2DI_type_node, integer_type_node, NULL_TREE);
22010 tree v4si_ftype_v4si_int
22011 = build_function_type_list (V4SI_type_node,
22012 V4SI_type_node, integer_type_node, NULL_TREE);
22013 tree v8hi_ftype_v8hi_int
22014 = build_function_type_list (V8HI_type_node,
22015 V8HI_type_node, integer_type_node, NULL_TREE);
22016 tree v4si_ftype_v8hi_v8hi
22017 = build_function_type_list (V4SI_type_node,
22018 V8HI_type_node, V8HI_type_node, NULL_TREE);
22019 tree v1di_ftype_v8qi_v8qi
22020 = build_function_type_list (V1DI_type_node,
22021 V8QI_type_node, V8QI_type_node, NULL_TREE);
22022 tree v1di_ftype_v2si_v2si
22023 = build_function_type_list (V1DI_type_node,
22024 V2SI_type_node, V2SI_type_node, NULL_TREE);
22025 tree v2di_ftype_v16qi_v16qi
22026 = build_function_type_list (V2DI_type_node,
22027 V16QI_type_node, V16QI_type_node, NULL_TREE);
22028 tree v2di_ftype_v4si_v4si
22029 = build_function_type_list (V2DI_type_node,
22030 V4SI_type_node, V4SI_type_node, NULL_TREE);
22031 tree int_ftype_v16qi
22032 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22033 tree v16qi_ftype_pcchar
22034 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22035 tree void_ftype_pchar_v16qi
22036 = build_function_type_list (void_type_node,
22037 pchar_type_node, V16QI_type_node, NULL_TREE);
22039 tree v2di_ftype_v2di_unsigned_unsigned
22040 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22041 unsigned_type_node, unsigned_type_node,
22043 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22044 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22045 unsigned_type_node, unsigned_type_node,
22047 tree v2di_ftype_v2di_v16qi
22048 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22050 tree v2df_ftype_v2df_v2df_v2df
22051 = build_function_type_list (V2DF_type_node,
22052 V2DF_type_node, V2DF_type_node,
22053 V2DF_type_node, NULL_TREE);
22054 tree v4sf_ftype_v4sf_v4sf_v4sf
22055 = build_function_type_list (V4SF_type_node,
22056 V4SF_type_node, V4SF_type_node,
22057 V4SF_type_node, NULL_TREE);
22058 tree v8hi_ftype_v16qi
22059 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22061 tree v4si_ftype_v16qi
22062 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22064 tree v2di_ftype_v16qi
22065 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22067 tree v4si_ftype_v8hi
22068 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22070 tree v2di_ftype_v8hi
22071 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22073 tree v2di_ftype_v4si
22074 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22076 tree v2di_ftype_pv2di
22077 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22079 tree v16qi_ftype_v16qi_v16qi_int
22080 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22081 V16QI_type_node, integer_type_node,
22083 tree v16qi_ftype_v16qi_v16qi_v16qi
22084 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22085 V16QI_type_node, V16QI_type_node,
22087 tree v8hi_ftype_v8hi_v8hi_int
22088 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22089 V8HI_type_node, integer_type_node,
22091 tree v4si_ftype_v4si_v4si_int
22092 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22093 V4SI_type_node, integer_type_node,
22095 tree int_ftype_v2di_v2di
22096 = build_function_type_list (integer_type_node,
22097 V2DI_type_node, V2DI_type_node,
22099 tree int_ftype_v16qi_int_v16qi_int_int
22100 = build_function_type_list (integer_type_node,
22107 tree v16qi_ftype_v16qi_int_v16qi_int_int
22108 = build_function_type_list (V16QI_type_node,
22115 tree int_ftype_v16qi_v16qi_int
22116 = build_function_type_list (integer_type_node,
22122 /* SSE5 instructions */
22123 tree v2di_ftype_v2di_v2di_v2di
22124 = build_function_type_list (V2DI_type_node,
22130 tree v4si_ftype_v4si_v4si_v4si
22131 = build_function_type_list (V4SI_type_node,
22137 tree v4si_ftype_v4si_v4si_v2di
22138 = build_function_type_list (V4SI_type_node,
22144 tree v8hi_ftype_v8hi_v8hi_v8hi
22145 = build_function_type_list (V8HI_type_node,
22151 tree v8hi_ftype_v8hi_v8hi_v4si
22152 = build_function_type_list (V8HI_type_node,
22158 tree v2df_ftype_v2df_v2df_v16qi
22159 = build_function_type_list (V2DF_type_node,
22165 tree v4sf_ftype_v4sf_v4sf_v16qi
22166 = build_function_type_list (V4SF_type_node,
22172 tree v2di_ftype_v2di_si
22173 = build_function_type_list (V2DI_type_node,
22178 tree v4si_ftype_v4si_si
22179 = build_function_type_list (V4SI_type_node,
22184 tree v8hi_ftype_v8hi_si
22185 = build_function_type_list (V8HI_type_node,
22190 tree v16qi_ftype_v16qi_si
22191 = build_function_type_list (V16QI_type_node,
22195 tree v4sf_ftype_v4hi
22196 = build_function_type_list (V4SF_type_node,
22200 tree v4hi_ftype_v4sf
22201 = build_function_type_list (V4HI_type_node,
22205 tree v2di_ftype_v2di
22206 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22208 tree v16qi_ftype_v8hi_v8hi
22209 = build_function_type_list (V16QI_type_node,
22210 V8HI_type_node, V8HI_type_node,
22212 tree v8hi_ftype_v4si_v4si
22213 = build_function_type_list (V8HI_type_node,
22214 V4SI_type_node, V4SI_type_node,
22216 tree v8hi_ftype_v16qi_v16qi
22217 = build_function_type_list (V8HI_type_node,
22218 V16QI_type_node, V16QI_type_node,
22220 tree v4hi_ftype_v8qi_v8qi
22221 = build_function_type_list (V4HI_type_node,
22222 V8QI_type_node, V8QI_type_node,
22224 tree unsigned_ftype_unsigned_uchar
22225 = build_function_type_list (unsigned_type_node,
22226 unsigned_type_node,
22227 unsigned_char_type_node,
22229 tree unsigned_ftype_unsigned_ushort
22230 = build_function_type_list (unsigned_type_node,
22231 unsigned_type_node,
22232 short_unsigned_type_node,
22234 tree unsigned_ftype_unsigned_unsigned
22235 = build_function_type_list (unsigned_type_node,
22236 unsigned_type_node,
22237 unsigned_type_node,
22239 tree uint64_ftype_uint64_uint64
22240 = build_function_type_list (long_long_unsigned_type_node,
22241 long_long_unsigned_type_node,
22242 long_long_unsigned_type_node,
22244 tree float_ftype_float
22245 = build_function_type_list (float_type_node,
22250 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22252 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22254 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22256 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22258 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22260 tree v8sf_ftype_v8sf
22261 = build_function_type_list (V8SF_type_node,
22264 tree v8si_ftype_v8sf
22265 = build_function_type_list (V8SI_type_node,
22268 tree v8sf_ftype_v8si
22269 = build_function_type_list (V8SF_type_node,
22272 tree v4si_ftype_v4df
22273 = build_function_type_list (V4SI_type_node,
22276 tree v4df_ftype_v4df
22277 = build_function_type_list (V4DF_type_node,
22280 tree v4df_ftype_v4si
22281 = build_function_type_list (V4DF_type_node,
22284 tree v4df_ftype_v4sf
22285 = build_function_type_list (V4DF_type_node,
22288 tree v4sf_ftype_v4df
22289 = build_function_type_list (V4SF_type_node,
22292 tree v8sf_ftype_v8sf_v8sf
22293 = build_function_type_list (V8SF_type_node,
22294 V8SF_type_node, V8SF_type_node,
22296 tree v4df_ftype_v4df_v4df
22297 = build_function_type_list (V4DF_type_node,
22298 V4DF_type_node, V4DF_type_node,
22300 tree v8sf_ftype_v8sf_int
22301 = build_function_type_list (V8SF_type_node,
22302 V8SF_type_node, integer_type_node,
22304 tree v4si_ftype_v8si_int
22305 = build_function_type_list (V4SI_type_node,
22306 V8SI_type_node, integer_type_node,
22308 tree v4df_ftype_v4df_int
22309 = build_function_type_list (V4DF_type_node,
22310 V4DF_type_node, integer_type_node,
22312 tree v4sf_ftype_v8sf_int
22313 = build_function_type_list (V4SF_type_node,
22314 V8SF_type_node, integer_type_node,
22316 tree v2df_ftype_v4df_int
22317 = build_function_type_list (V2DF_type_node,
22318 V4DF_type_node, integer_type_node,
22320 tree v8sf_ftype_v8sf_v8sf_int
22321 = build_function_type_list (V8SF_type_node,
22322 V8SF_type_node, V8SF_type_node,
22325 tree v8sf_ftype_v8sf_v8sf_v8sf
22326 = build_function_type_list (V8SF_type_node,
22327 V8SF_type_node, V8SF_type_node,
22330 tree v4df_ftype_v4df_v4df_v4df
22331 = build_function_type_list (V4DF_type_node,
22332 V4DF_type_node, V4DF_type_node,
22335 tree v8si_ftype_v8si_v8si_int
22336 = build_function_type_list (V8SI_type_node,
22337 V8SI_type_node, V8SI_type_node,
22340 tree v4df_ftype_v4df_v4df_int
22341 = build_function_type_list (V4DF_type_node,
22342 V4DF_type_node, V4DF_type_node,
22345 tree v8sf_ftype_pcfloat
22346 = build_function_type_list (V8SF_type_node,
22349 tree v4df_ftype_pcdouble
22350 = build_function_type_list (V4DF_type_node,
22351 pcdouble_type_node,
22353 tree pcv4sf_type_node
22354 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22355 tree pcv2df_type_node
22356 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22357 tree v8sf_ftype_pcv4sf
22358 = build_function_type_list (V8SF_type_node,
22361 tree v4df_ftype_pcv2df
22362 = build_function_type_list (V4DF_type_node,
22365 tree v32qi_ftype_pcchar
22366 = build_function_type_list (V32QI_type_node,
22369 tree void_ftype_pchar_v32qi
22370 = build_function_type_list (void_type_node,
22371 pchar_type_node, V32QI_type_node,
22373 tree v8si_ftype_v8si_v4si_int
22374 = build_function_type_list (V8SI_type_node,
22375 V8SI_type_node, V4SI_type_node,
22378 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22379 tree void_ftype_pv4di_v4di
22380 = build_function_type_list (void_type_node,
22381 pv4di_type_node, V4DI_type_node,
22383 tree v8sf_ftype_v8sf_v4sf_int
22384 = build_function_type_list (V8SF_type_node,
22385 V8SF_type_node, V4SF_type_node,
22388 tree v4df_ftype_v4df_v2df_int
22389 = build_function_type_list (V4DF_type_node,
22390 V4DF_type_node, V2DF_type_node,
22393 tree void_ftype_pfloat_v8sf
22394 = build_function_type_list (void_type_node,
22395 pfloat_type_node, V8SF_type_node,
22397 tree void_ftype_pdouble_v4df
22398 = build_function_type_list (void_type_node,
22399 pdouble_type_node, V4DF_type_node,
22401 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22402 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22403 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22404 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22405 tree pcv8sf_type_node
22406 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22407 tree pcv4df_type_node
22408 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22409 tree v8sf_ftype_pcv8sf_v8sf
22410 = build_function_type_list (V8SF_type_node,
22411 pcv8sf_type_node, V8SF_type_node,
22413 tree v4df_ftype_pcv4df_v4df
22414 = build_function_type_list (V4DF_type_node,
22415 pcv4df_type_node, V4DF_type_node,
22417 tree v4sf_ftype_pcv4sf_v4sf
22418 = build_function_type_list (V4SF_type_node,
22419 pcv4sf_type_node, V4SF_type_node,
22421 tree v2df_ftype_pcv2df_v2df
22422 = build_function_type_list (V2DF_type_node,
22423 pcv2df_type_node, V2DF_type_node,
22425 tree void_ftype_pv8sf_v8sf_v8sf
22426 = build_function_type_list (void_type_node,
22427 pv8sf_type_node, V8SF_type_node,
22430 tree void_ftype_pv4df_v4df_v4df
22431 = build_function_type_list (void_type_node,
22432 pv4df_type_node, V4DF_type_node,
22435 tree void_ftype_pv4sf_v4sf_v4sf
22436 = build_function_type_list (void_type_node,
22437 pv4sf_type_node, V4SF_type_node,
22440 tree void_ftype_pv2df_v2df_v2df
22441 = build_function_type_list (void_type_node,
22442 pv2df_type_node, V2DF_type_node,
22445 tree v4df_ftype_v2df
22446 = build_function_type_list (V4DF_type_node,
22449 tree v8sf_ftype_v4sf
22450 = build_function_type_list (V8SF_type_node,
22453 tree v8si_ftype_v4si
22454 = build_function_type_list (V8SI_type_node,
22457 tree v2df_ftype_v4df
22458 = build_function_type_list (V2DF_type_node,
22461 tree v4sf_ftype_v8sf
22462 = build_function_type_list (V4SF_type_node,
22465 tree v4si_ftype_v8si
22466 = build_function_type_list (V4SI_type_node,
22469 tree int_ftype_v4df
22470 = build_function_type_list (integer_type_node,
22473 tree int_ftype_v8sf
22474 = build_function_type_list (integer_type_node,
22477 tree int_ftype_v8sf_v8sf
22478 = build_function_type_list (integer_type_node,
22479 V8SF_type_node, V8SF_type_node,
22481 tree int_ftype_v4di_v4di
22482 = build_function_type_list (integer_type_node,
22483 V4DI_type_node, V4DI_type_node,
22485 tree int_ftype_v4df_v4df
22486 = build_function_type_list (integer_type_node,
22487 V4DF_type_node, V4DF_type_node,
22489 tree v8sf_ftype_v8sf_v8si
22490 = build_function_type_list (V8SF_type_node,
22491 V8SF_type_node, V8SI_type_node,
22493 tree v4df_ftype_v4df_v4di
22494 = build_function_type_list (V4DF_type_node,
22495 V4DF_type_node, V4DI_type_node,
22497 tree v4sf_ftype_v4sf_v4si
22498 = build_function_type_list (V4SF_type_node,
22499 V4SF_type_node, V4SI_type_node, NULL_TREE);
22500 tree v2df_ftype_v2df_v2di
22501 = build_function_type_list (V2DF_type_node,
22502 V2DF_type_node, V2DI_type_node, NULL_TREE);
22506 /* Add all special builtins with variable number of operands. */
22507 for (i = 0, d = bdesc_special_args;
22508 i < ARRAY_SIZE (bdesc_special_args);
22516 switch ((enum ix86_special_builtin_type) d->flag)
22518 case VOID_FTYPE_VOID:
22519 type = void_ftype_void;
22521 case V32QI_FTYPE_PCCHAR:
22522 type = v32qi_ftype_pcchar;
22524 case V16QI_FTYPE_PCCHAR:
22525 type = v16qi_ftype_pcchar;
22527 case V8SF_FTYPE_PCV4SF:
22528 type = v8sf_ftype_pcv4sf;
22530 case V8SF_FTYPE_PCFLOAT:
22531 type = v8sf_ftype_pcfloat;
22533 case V4DF_FTYPE_PCV2DF:
22534 type = v4df_ftype_pcv2df;
22536 case V4DF_FTYPE_PCDOUBLE:
22537 type = v4df_ftype_pcdouble;
22539 case V4SF_FTYPE_PCFLOAT:
22540 type = v4sf_ftype_pcfloat;
22542 case V2DI_FTYPE_PV2DI:
22543 type = v2di_ftype_pv2di;
22545 case V2DF_FTYPE_PCDOUBLE:
22546 type = v2df_ftype_pcdouble;
22548 case V8SF_FTYPE_PCV8SF_V8SF:
22549 type = v8sf_ftype_pcv8sf_v8sf;
22551 case V4DF_FTYPE_PCV4DF_V4DF:
22552 type = v4df_ftype_pcv4df_v4df;
22554 case V4SF_FTYPE_V4SF_PCV2SF:
22555 type = v4sf_ftype_v4sf_pcv2sf;
22557 case V4SF_FTYPE_PCV4SF_V4SF:
22558 type = v4sf_ftype_pcv4sf_v4sf;
22560 case V2DF_FTYPE_V2DF_PCDOUBLE:
22561 type = v2df_ftype_v2df_pcdouble;
22563 case V2DF_FTYPE_PCV2DF_V2DF:
22564 type = v2df_ftype_pcv2df_v2df;
22566 case VOID_FTYPE_PV2SF_V4SF:
22567 type = void_ftype_pv2sf_v4sf;
22569 case VOID_FTYPE_PV4DI_V4DI:
22570 type = void_ftype_pv4di_v4di;
22572 case VOID_FTYPE_PV2DI_V2DI:
22573 type = void_ftype_pv2di_v2di;
22575 case VOID_FTYPE_PCHAR_V32QI:
22576 type = void_ftype_pchar_v32qi;
22578 case VOID_FTYPE_PCHAR_V16QI:
22579 type = void_ftype_pchar_v16qi;
22581 case VOID_FTYPE_PFLOAT_V8SF:
22582 type = void_ftype_pfloat_v8sf;
22584 case VOID_FTYPE_PFLOAT_V4SF:
22585 type = void_ftype_pfloat_v4sf;
22587 case VOID_FTYPE_PDOUBLE_V4DF:
22588 type = void_ftype_pdouble_v4df;
22590 case VOID_FTYPE_PDOUBLE_V2DF:
22591 type = void_ftype_pdouble_v2df;
22593 case VOID_FTYPE_PDI_DI:
22594 type = void_ftype_pdi_di;
22596 case VOID_FTYPE_PINT_INT:
22597 type = void_ftype_pint_int;
22599 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22600 type = void_ftype_pv8sf_v8sf_v8sf;
22602 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22603 type = void_ftype_pv4df_v4df_v4df;
22605 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22606 type = void_ftype_pv4sf_v4sf_v4sf;
22608 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22609 type = void_ftype_pv2df_v2df_v2df;
22612 gcc_unreachable ();
22615 def_builtin (d->mask, d->name, type, d->code);
22618 /* Add all builtins with variable number of operands. */
22619 for (i = 0, d = bdesc_args;
22620 i < ARRAY_SIZE (bdesc_args);
22628 switch ((enum ix86_builtin_type) d->flag)
22630 case FLOAT_FTYPE_FLOAT:
22631 type = float_ftype_float;
22633 case INT_FTYPE_V8SF_V8SF_PTEST:
22634 type = int_ftype_v8sf_v8sf;
22636 case INT_FTYPE_V4DI_V4DI_PTEST:
22637 type = int_ftype_v4di_v4di;
22639 case INT_FTYPE_V4DF_V4DF_PTEST:
22640 type = int_ftype_v4df_v4df;
22642 case INT_FTYPE_V4SF_V4SF_PTEST:
22643 type = int_ftype_v4sf_v4sf;
22645 case INT_FTYPE_V2DI_V2DI_PTEST:
22646 type = int_ftype_v2di_v2di;
22648 case INT_FTYPE_V2DF_V2DF_PTEST:
22649 type = int_ftype_v2df_v2df;
22651 case INT64_FTYPE_V4SF:
22652 type = int64_ftype_v4sf;
22654 case INT64_FTYPE_V2DF:
22655 type = int64_ftype_v2df;
22657 case INT_FTYPE_V16QI:
22658 type = int_ftype_v16qi;
22660 case INT_FTYPE_V8QI:
22661 type = int_ftype_v8qi;
22663 case INT_FTYPE_V8SF:
22664 type = int_ftype_v8sf;
22666 case INT_FTYPE_V4DF:
22667 type = int_ftype_v4df;
22669 case INT_FTYPE_V4SF:
22670 type = int_ftype_v4sf;
22672 case INT_FTYPE_V2DF:
22673 type = int_ftype_v2df;
22675 case V16QI_FTYPE_V16QI:
22676 type = v16qi_ftype_v16qi;
22678 case V8SI_FTYPE_V8SF:
22679 type = v8si_ftype_v8sf;
22681 case V8SI_FTYPE_V4SI:
22682 type = v8si_ftype_v4si;
22684 case V8HI_FTYPE_V8HI:
22685 type = v8hi_ftype_v8hi;
22687 case V8HI_FTYPE_V16QI:
22688 type = v8hi_ftype_v16qi;
22690 case V8QI_FTYPE_V8QI:
22691 type = v8qi_ftype_v8qi;
22693 case V8SF_FTYPE_V8SF:
22694 type = v8sf_ftype_v8sf;
22696 case V8SF_FTYPE_V8SI:
22697 type = v8sf_ftype_v8si;
22699 case V8SF_FTYPE_V4SF:
22700 type = v8sf_ftype_v4sf;
22702 case V4SI_FTYPE_V4DF:
22703 type = v4si_ftype_v4df;
22705 case V4SI_FTYPE_V4SI:
22706 type = v4si_ftype_v4si;
22708 case V4SI_FTYPE_V16QI:
22709 type = v4si_ftype_v16qi;
22711 case V4SI_FTYPE_V8SI:
22712 type = v4si_ftype_v8si;
22714 case V4SI_FTYPE_V8HI:
22715 type = v4si_ftype_v8hi;
22717 case V4SI_FTYPE_V4SF:
22718 type = v4si_ftype_v4sf;
22720 case V4SI_FTYPE_V2DF:
22721 type = v4si_ftype_v2df;
22723 case V4HI_FTYPE_V4HI:
22724 type = v4hi_ftype_v4hi;
22726 case V4DF_FTYPE_V4DF:
22727 type = v4df_ftype_v4df;
22729 case V4DF_FTYPE_V4SI:
22730 type = v4df_ftype_v4si;
22732 case V4DF_FTYPE_V4SF:
22733 type = v4df_ftype_v4sf;
22735 case V4DF_FTYPE_V2DF:
22736 type = v4df_ftype_v2df;
22738 case V4SF_FTYPE_V4SF:
22739 case V4SF_FTYPE_V4SF_VEC_MERGE:
22740 type = v4sf_ftype_v4sf;
22742 case V4SF_FTYPE_V8SF:
22743 type = v4sf_ftype_v8sf;
22745 case V4SF_FTYPE_V4SI:
22746 type = v4sf_ftype_v4si;
22748 case V4SF_FTYPE_V4DF:
22749 type = v4sf_ftype_v4df;
22751 case V4SF_FTYPE_V2DF:
22752 type = v4sf_ftype_v2df;
22754 case V2DI_FTYPE_V2DI:
22755 type = v2di_ftype_v2di;
22757 case V2DI_FTYPE_V16QI:
22758 type = v2di_ftype_v16qi;
22760 case V2DI_FTYPE_V8HI:
22761 type = v2di_ftype_v8hi;
22763 case V2DI_FTYPE_V4SI:
22764 type = v2di_ftype_v4si;
22766 case V2SI_FTYPE_V2SI:
22767 type = v2si_ftype_v2si;
22769 case V2SI_FTYPE_V4SF:
22770 type = v2si_ftype_v4sf;
22772 case V2SI_FTYPE_V2DF:
22773 type = v2si_ftype_v2df;
22775 case V2SI_FTYPE_V2SF:
22776 type = v2si_ftype_v2sf;
22778 case V2DF_FTYPE_V4DF:
22779 type = v2df_ftype_v4df;
22781 case V2DF_FTYPE_V4SF:
22782 type = v2df_ftype_v4sf;
22784 case V2DF_FTYPE_V2DF:
22785 case V2DF_FTYPE_V2DF_VEC_MERGE:
22786 type = v2df_ftype_v2df;
22788 case V2DF_FTYPE_V2SI:
22789 type = v2df_ftype_v2si;
22791 case V2DF_FTYPE_V4SI:
22792 type = v2df_ftype_v4si;
22794 case V2SF_FTYPE_V2SF:
22795 type = v2sf_ftype_v2sf;
22797 case V2SF_FTYPE_V2SI:
22798 type = v2sf_ftype_v2si;
22800 case V16QI_FTYPE_V16QI_V16QI:
22801 type = v16qi_ftype_v16qi_v16qi;
22803 case V16QI_FTYPE_V8HI_V8HI:
22804 type = v16qi_ftype_v8hi_v8hi;
22806 case V8QI_FTYPE_V8QI_V8QI:
22807 type = v8qi_ftype_v8qi_v8qi;
22809 case V8QI_FTYPE_V4HI_V4HI:
22810 type = v8qi_ftype_v4hi_v4hi;
22812 case V8HI_FTYPE_V8HI_V8HI:
22813 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22814 type = v8hi_ftype_v8hi_v8hi;
22816 case V8HI_FTYPE_V16QI_V16QI:
22817 type = v8hi_ftype_v16qi_v16qi;
22819 case V8HI_FTYPE_V4SI_V4SI:
22820 type = v8hi_ftype_v4si_v4si;
22822 case V8HI_FTYPE_V8HI_SI_COUNT:
22823 type = v8hi_ftype_v8hi_int;
22825 case V8SF_FTYPE_V8SF_V8SF:
22826 type = v8sf_ftype_v8sf_v8sf;
22828 case V8SF_FTYPE_V8SF_V8SI:
22829 type = v8sf_ftype_v8sf_v8si;
22831 case V4SI_FTYPE_V4SI_V4SI:
22832 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22833 type = v4si_ftype_v4si_v4si;
22835 case V4SI_FTYPE_V8HI_V8HI:
22836 type = v4si_ftype_v8hi_v8hi;
22838 case V4SI_FTYPE_V4SF_V4SF:
22839 type = v4si_ftype_v4sf_v4sf;
22841 case V4SI_FTYPE_V2DF_V2DF:
22842 type = v4si_ftype_v2df_v2df;
22844 case V4SI_FTYPE_V4SI_SI_COUNT:
22845 type = v4si_ftype_v4si_int;
22847 case V4HI_FTYPE_V4HI_V4HI:
22848 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22849 type = v4hi_ftype_v4hi_v4hi;
22851 case V4HI_FTYPE_V8QI_V8QI:
22852 type = v4hi_ftype_v8qi_v8qi;
22854 case V4HI_FTYPE_V2SI_V2SI:
22855 type = v4hi_ftype_v2si_v2si;
22857 case V4HI_FTYPE_V4HI_SI_COUNT:
22858 type = v4hi_ftype_v4hi_int;
22860 case V4DF_FTYPE_V4DF_V4DF:
22861 type = v4df_ftype_v4df_v4df;
22863 case V4DF_FTYPE_V4DF_V4DI:
22864 type = v4df_ftype_v4df_v4di;
22866 case V4SF_FTYPE_V4SF_V4SF:
22867 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22868 type = v4sf_ftype_v4sf_v4sf;
22870 case V4SF_FTYPE_V4SF_V4SI:
22871 type = v4sf_ftype_v4sf_v4si;
22873 case V4SF_FTYPE_V4SF_V2SI:
22874 type = v4sf_ftype_v4sf_v2si;
22876 case V4SF_FTYPE_V4SF_V2DF:
22877 type = v4sf_ftype_v4sf_v2df;
22879 case V4SF_FTYPE_V4SF_DI:
22880 type = v4sf_ftype_v4sf_int64;
22882 case V4SF_FTYPE_V4SF_SI:
22883 type = v4sf_ftype_v4sf_int;
22885 case V2DI_FTYPE_V2DI_V2DI:
22886 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22887 type = v2di_ftype_v2di_v2di;
22889 case V2DI_FTYPE_V16QI_V16QI:
22890 type = v2di_ftype_v16qi_v16qi;
22892 case V2DI_FTYPE_V4SI_V4SI:
22893 type = v2di_ftype_v4si_v4si;
22895 case V2DI_FTYPE_V2DI_V16QI:
22896 type = v2di_ftype_v2di_v16qi;
22898 case V2DI_FTYPE_V2DF_V2DF:
22899 type = v2di_ftype_v2df_v2df;
22901 case V2DI_FTYPE_V2DI_SI_COUNT:
22902 type = v2di_ftype_v2di_int;
22904 case V2SI_FTYPE_V2SI_V2SI:
22905 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22906 type = v2si_ftype_v2si_v2si;
22908 case V2SI_FTYPE_V4HI_V4HI:
22909 type = v2si_ftype_v4hi_v4hi;
22911 case V2SI_FTYPE_V2SF_V2SF:
22912 type = v2si_ftype_v2sf_v2sf;
22914 case V2SI_FTYPE_V2SI_SI_COUNT:
22915 type = v2si_ftype_v2si_int;
22917 case V2DF_FTYPE_V2DF_V2DF:
22918 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22919 type = v2df_ftype_v2df_v2df;
22921 case V2DF_FTYPE_V2DF_V4SF:
22922 type = v2df_ftype_v2df_v4sf;
22924 case V2DF_FTYPE_V2DF_V2DI:
22925 type = v2df_ftype_v2df_v2di;
22927 case V2DF_FTYPE_V2DF_DI:
22928 type = v2df_ftype_v2df_int64;
22930 case V2DF_FTYPE_V2DF_SI:
22931 type = v2df_ftype_v2df_int;
22933 case V2SF_FTYPE_V2SF_V2SF:
22934 type = v2sf_ftype_v2sf_v2sf;
22936 case V1DI_FTYPE_V1DI_V1DI:
22937 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22938 type = v1di_ftype_v1di_v1di;
22940 case V1DI_FTYPE_V8QI_V8QI:
22941 type = v1di_ftype_v8qi_v8qi;
22943 case V1DI_FTYPE_V2SI_V2SI:
22944 type = v1di_ftype_v2si_v2si;
22946 case V1DI_FTYPE_V1DI_SI_COUNT:
22947 type = v1di_ftype_v1di_int;
22949 case UINT64_FTYPE_UINT64_UINT64:
22950 type = uint64_ftype_uint64_uint64;
22952 case UINT_FTYPE_UINT_UINT:
22953 type = unsigned_ftype_unsigned_unsigned;
22955 case UINT_FTYPE_UINT_USHORT:
22956 type = unsigned_ftype_unsigned_ushort;
22958 case UINT_FTYPE_UINT_UCHAR:
22959 type = unsigned_ftype_unsigned_uchar;
22961 case V8HI_FTYPE_V8HI_INT:
22962 type = v8hi_ftype_v8hi_int;
22964 case V8SF_FTYPE_V8SF_INT:
22965 type = v8sf_ftype_v8sf_int;
22967 case V4SI_FTYPE_V4SI_INT:
22968 type = v4si_ftype_v4si_int;
22970 case V4SI_FTYPE_V8SI_INT:
22971 type = v4si_ftype_v8si_int;
22973 case V4HI_FTYPE_V4HI_INT:
22974 type = v4hi_ftype_v4hi_int;
22976 case V4DF_FTYPE_V4DF_INT:
22977 type = v4df_ftype_v4df_int;
22979 case V4SF_FTYPE_V4SF_INT:
22980 type = v4sf_ftype_v4sf_int;
22982 case V4SF_FTYPE_V8SF_INT:
22983 type = v4sf_ftype_v8sf_int;
22985 case V2DI_FTYPE_V2DI_INT:
22986 case V2DI2TI_FTYPE_V2DI_INT:
22987 type = v2di_ftype_v2di_int;
22989 case V2DF_FTYPE_V2DF_INT:
22990 type = v2df_ftype_v2df_int;
22992 case V2DF_FTYPE_V4DF_INT:
22993 type = v2df_ftype_v4df_int;
22995 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22996 type = v16qi_ftype_v16qi_v16qi_v16qi;
22998 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22999 type = v8sf_ftype_v8sf_v8sf_v8sf;
23001 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23002 type = v4df_ftype_v4df_v4df_v4df;
23004 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23005 type = v4sf_ftype_v4sf_v4sf_v4sf;
23007 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23008 type = v2df_ftype_v2df_v2df_v2df;
23010 case V16QI_FTYPE_V16QI_V16QI_INT:
23011 type = v16qi_ftype_v16qi_v16qi_int;
23013 case V8SI_FTYPE_V8SI_V8SI_INT:
23014 type = v8si_ftype_v8si_v8si_int;
23016 case V8SI_FTYPE_V8SI_V4SI_INT:
23017 type = v8si_ftype_v8si_v4si_int;
23019 case V8HI_FTYPE_V8HI_V8HI_INT:
23020 type = v8hi_ftype_v8hi_v8hi_int;
23022 case V8SF_FTYPE_V8SF_V8SF_INT:
23023 type = v8sf_ftype_v8sf_v8sf_int;
23025 case V8SF_FTYPE_V8SF_V4SF_INT:
23026 type = v8sf_ftype_v8sf_v4sf_int;
23028 case V4SI_FTYPE_V4SI_V4SI_INT:
23029 type = v4si_ftype_v4si_v4si_int;
23031 case V4DF_FTYPE_V4DF_V4DF_INT:
23032 type = v4df_ftype_v4df_v4df_int;
23034 case V4DF_FTYPE_V4DF_V2DF_INT:
23035 type = v4df_ftype_v4df_v2df_int;
23037 case V4SF_FTYPE_V4SF_V4SF_INT:
23038 type = v4sf_ftype_v4sf_v4sf_int;
23040 case V2DI_FTYPE_V2DI_V2DI_INT:
23041 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23042 type = v2di_ftype_v2di_v2di_int;
23044 case V2DF_FTYPE_V2DF_V2DF_INT:
23045 type = v2df_ftype_v2df_v2df_int;
23047 case V2DI_FTYPE_V2DI_UINT_UINT:
23048 type = v2di_ftype_v2di_unsigned_unsigned;
23050 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23051 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23053 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23054 type = v1di_ftype_v1di_v1di_int;
23057 gcc_unreachable ();
23060 def_builtin_const (d->mask, d->name, type, d->code);
23063 /* pcmpestr[im] insns. */
23064 for (i = 0, d = bdesc_pcmpestr;
23065 i < ARRAY_SIZE (bdesc_pcmpestr);
23068 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23069 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23071 ftype = int_ftype_v16qi_int_v16qi_int_int;
23072 def_builtin_const (d->mask, d->name, ftype, d->code);
23075 /* pcmpistr[im] insns. */
23076 for (i = 0, d = bdesc_pcmpistr;
23077 i < ARRAY_SIZE (bdesc_pcmpistr);
23080 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23081 ftype = v16qi_ftype_v16qi_v16qi_int;
23083 ftype = int_ftype_v16qi_v16qi_int;
23084 def_builtin_const (d->mask, d->name, ftype, d->code);
23087 /* comi/ucomi insns. */
23088 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23089 if (d->mask == OPTION_MASK_ISA_SSE2)
23090 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23092 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23095 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23096 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23098 /* SSE or 3DNow!A */
23099 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23102 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23104 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23105 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23108 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23109 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23112 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23113 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23114 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23115 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23116 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23117 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23120 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23123 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23124 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23126 /* Access to the vec_init patterns. */
23127 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23128 integer_type_node, NULL_TREE);
23129 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23131 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23132 short_integer_type_node,
23133 short_integer_type_node,
23134 short_integer_type_node, NULL_TREE);
23135 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23137 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23138 char_type_node, char_type_node,
23139 char_type_node, char_type_node,
23140 char_type_node, char_type_node,
23141 char_type_node, NULL_TREE);
23142 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23144 /* Access to the vec_extract patterns. */
23145 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23146 integer_type_node, NULL_TREE);
23147 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23149 ftype = build_function_type_list (long_long_integer_type_node,
23150 V2DI_type_node, integer_type_node,
23152 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23154 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23155 integer_type_node, NULL_TREE);
23156 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23158 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23159 integer_type_node, NULL_TREE);
23160 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23162 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23163 integer_type_node, NULL_TREE);
23164 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23166 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23167 integer_type_node, NULL_TREE);
23168 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23170 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23171 integer_type_node, NULL_TREE);
23172 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23174 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23175 integer_type_node, NULL_TREE);
23176 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23178 /* Access to the vec_set patterns. */
23179 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23181 integer_type_node, NULL_TREE);
23182 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23184 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23186 integer_type_node, NULL_TREE);
23187 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23189 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23191 integer_type_node, NULL_TREE);
23192 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23194 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23196 integer_type_node, NULL_TREE);
23197 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23199 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23201 integer_type_node, NULL_TREE);
23202 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23204 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23206 integer_type_node, NULL_TREE);
23207 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23209 /* Add SSE5 multi-arg argument instructions */
23210 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23212 tree mtype = NULL_TREE;
23217 switch ((enum multi_arg_type)d->flag)
23219 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23220 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23221 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23222 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23223 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23224 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23225 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23226 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23227 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23228 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23229 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23230 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23231 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23232 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23233 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23234 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23235 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23236 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23237 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23238 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23239 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23240 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23241 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23242 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23243 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23244 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23245 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23246 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23247 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23248 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23249 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23250 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23251 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23252 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23253 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23254 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23255 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23256 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23257 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23258 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23259 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23260 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23261 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23262 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23263 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23264 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23265 case MULTI_ARG_UNKNOWN:
23267 gcc_unreachable ();
23271 def_builtin_const (d->mask, d->name, mtype, d->code);
23275 /* Internal method for ix86_init_builtins. */
23278 ix86_init_builtins_va_builtins_abi (void)
23280 tree ms_va_ref, sysv_va_ref;
23281 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23282 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23283 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23284 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23288 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23289 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23290 ms_va_ref = build_reference_type (ms_va_list_type_node);
23292 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23295 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23296 fnvoid_va_start_ms =
23297 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23298 fnvoid_va_end_sysv =
23299 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23300 fnvoid_va_start_sysv =
23301 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23303 fnvoid_va_copy_ms =
23304 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23306 fnvoid_va_copy_sysv =
23307 build_function_type_list (void_type_node, sysv_va_ref,
23308 sysv_va_ref, NULL_TREE);
23310 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23311 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23312 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23313 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23314 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23315 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23316 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23317 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23318 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23319 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23320 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23321 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23325 ix86_init_builtins (void)
23327 tree float128_type_node = make_node (REAL_TYPE);
23330 /* The __float80 type. */
23331 if (TYPE_MODE (long_double_type_node) == XFmode)
23332 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23336 /* The __float80 type. */
23337 tree float80_type_node = make_node (REAL_TYPE);
23339 TYPE_PRECISION (float80_type_node) = 80;
23340 layout_type (float80_type_node);
23341 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23345 /* The __float128 type. */
23346 TYPE_PRECISION (float128_type_node) = 128;
23347 layout_type (float128_type_node);
23348 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23351 /* TFmode support builtins. */
23352 ftype = build_function_type (float128_type_node, void_list_node);
23353 decl = add_builtin_function ("__builtin_infq", ftype,
23354 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23356 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23358 /* We will expand them to normal call if SSE2 isn't available since
23359 they are used by libgcc. */
23360 ftype = build_function_type_list (float128_type_node,
23361 float128_type_node,
23363 decl = add_builtin_function ("__builtin_fabsq", ftype,
23364 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23365 "__fabstf2", NULL_TREE);
23366 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23367 TREE_READONLY (decl) = 1;
23369 ftype = build_function_type_list (float128_type_node,
23370 float128_type_node,
23371 float128_type_node,
23373 decl = add_builtin_function ("__builtin_copysignq", ftype,
23374 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23375 "__copysigntf3", NULL_TREE);
23376 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23377 TREE_READONLY (decl) = 1;
23379 ix86_init_mmx_sse_builtins ();
23381 ix86_init_builtins_va_builtins_abi ();
23384 /* Errors in the source file can cause expand_expr to return const0_rtx
23385 where we expect a vector. To avoid crashing, use one of the vector
23386 clear instructions. */
23388 safe_vector_operand (rtx x, enum machine_mode mode)
23390 if (x == const0_rtx)
23391 x = CONST0_RTX (mode);
23395 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23398 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23401 tree arg0 = CALL_EXPR_ARG (exp, 0);
23402 tree arg1 = CALL_EXPR_ARG (exp, 1);
23403 rtx op0 = expand_normal (arg0);
23404 rtx op1 = expand_normal (arg1);
23405 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23406 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23407 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23409 if (VECTOR_MODE_P (mode0))
23410 op0 = safe_vector_operand (op0, mode0);
23411 if (VECTOR_MODE_P (mode1))
23412 op1 = safe_vector_operand (op1, mode1);
23414 if (optimize || !target
23415 || GET_MODE (target) != tmode
23416 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23417 target = gen_reg_rtx (tmode);
23419 if (GET_MODE (op1) == SImode && mode1 == TImode)
23421 rtx x = gen_reg_rtx (V4SImode);
23422 emit_insn (gen_sse2_loadd (x, op1));
23423 op1 = gen_lowpart (TImode, x);
23426 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23427 op0 = copy_to_mode_reg (mode0, op0);
23428 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23429 op1 = copy_to_mode_reg (mode1, op1);
23431 pat = GEN_FCN (icode) (target, op0, op1);
23440 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23443 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23444 enum multi_arg_type m_type,
23445 enum insn_code sub_code)
23450 bool comparison_p = false;
23452 bool last_arg_constant = false;
23453 int num_memory = 0;
23456 enum machine_mode mode;
23459 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23463 case MULTI_ARG_3_SF:
23464 case MULTI_ARG_3_DF:
23465 case MULTI_ARG_3_DI:
23466 case MULTI_ARG_3_SI:
23467 case MULTI_ARG_3_SI_DI:
23468 case MULTI_ARG_3_HI:
23469 case MULTI_ARG_3_HI_SI:
23470 case MULTI_ARG_3_QI:
23471 case MULTI_ARG_3_PERMPS:
23472 case MULTI_ARG_3_PERMPD:
23476 case MULTI_ARG_2_SF:
23477 case MULTI_ARG_2_DF:
23478 case MULTI_ARG_2_DI:
23479 case MULTI_ARG_2_SI:
23480 case MULTI_ARG_2_HI:
23481 case MULTI_ARG_2_QI:
23485 case MULTI_ARG_2_DI_IMM:
23486 case MULTI_ARG_2_SI_IMM:
23487 case MULTI_ARG_2_HI_IMM:
23488 case MULTI_ARG_2_QI_IMM:
23490 last_arg_constant = true;
23493 case MULTI_ARG_1_SF:
23494 case MULTI_ARG_1_DF:
23495 case MULTI_ARG_1_DI:
23496 case MULTI_ARG_1_SI:
23497 case MULTI_ARG_1_HI:
23498 case MULTI_ARG_1_QI:
23499 case MULTI_ARG_1_SI_DI:
23500 case MULTI_ARG_1_HI_DI:
23501 case MULTI_ARG_1_HI_SI:
23502 case MULTI_ARG_1_QI_DI:
23503 case MULTI_ARG_1_QI_SI:
23504 case MULTI_ARG_1_QI_HI:
23505 case MULTI_ARG_1_PH2PS:
23506 case MULTI_ARG_1_PS2PH:
23510 case MULTI_ARG_2_SF_CMP:
23511 case MULTI_ARG_2_DF_CMP:
23512 case MULTI_ARG_2_DI_CMP:
23513 case MULTI_ARG_2_SI_CMP:
23514 case MULTI_ARG_2_HI_CMP:
23515 case MULTI_ARG_2_QI_CMP:
23517 comparison_p = true;
23520 case MULTI_ARG_2_SF_TF:
23521 case MULTI_ARG_2_DF_TF:
23522 case MULTI_ARG_2_DI_TF:
23523 case MULTI_ARG_2_SI_TF:
23524 case MULTI_ARG_2_HI_TF:
23525 case MULTI_ARG_2_QI_TF:
23530 case MULTI_ARG_UNKNOWN:
23532 gcc_unreachable ();
23535 if (optimize || !target
23536 || GET_MODE (target) != tmode
23537 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23538 target = gen_reg_rtx (tmode);
23540 gcc_assert (nargs <= 4);
23542 for (i = 0; i < nargs; i++)
23544 tree arg = CALL_EXPR_ARG (exp, i);
23545 rtx op = expand_normal (arg);
23546 int adjust = (comparison_p) ? 1 : 0;
23547 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23549 if (last_arg_constant && i == nargs-1)
23551 if (GET_CODE (op) != CONST_INT)
23553 error ("last argument must be an immediate");
23554 return gen_reg_rtx (tmode);
23559 if (VECTOR_MODE_P (mode))
23560 op = safe_vector_operand (op, mode);
23562 /* If we aren't optimizing, only allow one memory operand to be
23564 if (memory_operand (op, mode))
23567 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23570 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23572 op = force_reg (mode, op);
23576 args[i].mode = mode;
23582 pat = GEN_FCN (icode) (target, args[0].op);
23587 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23588 GEN_INT ((int)sub_code));
23589 else if (! comparison_p)
23590 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23593 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23597 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23602 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23606 gcc_unreachable ();
23616 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23617 insns with vec_merge. */
23620 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23624 tree arg0 = CALL_EXPR_ARG (exp, 0);
23625 rtx op1, op0 = expand_normal (arg0);
23626 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23627 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23629 if (optimize || !target
23630 || GET_MODE (target) != tmode
23631 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23632 target = gen_reg_rtx (tmode);
23634 if (VECTOR_MODE_P (mode0))
23635 op0 = safe_vector_operand (op0, mode0);
23637 if ((optimize && !register_operand (op0, mode0))
23638 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23639 op0 = copy_to_mode_reg (mode0, op0);
23642 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23643 op1 = copy_to_mode_reg (mode0, op1);
23645 pat = GEN_FCN (icode) (target, op0, op1);
23652 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23655 ix86_expand_sse_compare (const struct builtin_description *d,
23656 tree exp, rtx target, bool swap)
23659 tree arg0 = CALL_EXPR_ARG (exp, 0);
23660 tree arg1 = CALL_EXPR_ARG (exp, 1);
23661 rtx op0 = expand_normal (arg0);
23662 rtx op1 = expand_normal (arg1);
23664 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23665 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23666 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23667 enum rtx_code comparison = d->comparison;
23669 if (VECTOR_MODE_P (mode0))
23670 op0 = safe_vector_operand (op0, mode0);
23671 if (VECTOR_MODE_P (mode1))
23672 op1 = safe_vector_operand (op1, mode1);
23674 /* Swap operands if we have a comparison that isn't available in
23678 rtx tmp = gen_reg_rtx (mode1);
23679 emit_move_insn (tmp, op1);
23684 if (optimize || !target
23685 || GET_MODE (target) != tmode
23686 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23687 target = gen_reg_rtx (tmode);
23689 if ((optimize && !register_operand (op0, mode0))
23690 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23691 op0 = copy_to_mode_reg (mode0, op0);
23692 if ((optimize && !register_operand (op1, mode1))
23693 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23694 op1 = copy_to_mode_reg (mode1, op1);
23696 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23697 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23704 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23707 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23711 tree arg0 = CALL_EXPR_ARG (exp, 0);
23712 tree arg1 = CALL_EXPR_ARG (exp, 1);
23713 rtx op0 = expand_normal (arg0);
23714 rtx op1 = expand_normal (arg1);
23715 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23716 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23717 enum rtx_code comparison = d->comparison;
23719 if (VECTOR_MODE_P (mode0))
23720 op0 = safe_vector_operand (op0, mode0);
23721 if (VECTOR_MODE_P (mode1))
23722 op1 = safe_vector_operand (op1, mode1);
23724 /* Swap operands if we have a comparison that isn't available in
23726 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23733 target = gen_reg_rtx (SImode);
23734 emit_move_insn (target, const0_rtx);
23735 target = gen_rtx_SUBREG (QImode, target, 0);
23737 if ((optimize && !register_operand (op0, mode0))
23738 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23739 op0 = copy_to_mode_reg (mode0, op0);
23740 if ((optimize && !register_operand (op1, mode1))
23741 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23742 op1 = copy_to_mode_reg (mode1, op1);
23744 pat = GEN_FCN (d->icode) (op0, op1);
23748 emit_insn (gen_rtx_SET (VOIDmode,
23749 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23750 gen_rtx_fmt_ee (comparison, QImode,
23754 return SUBREG_REG (target);
23757 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23760 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23764 tree arg0 = CALL_EXPR_ARG (exp, 0);
23765 tree arg1 = CALL_EXPR_ARG (exp, 1);
23766 rtx op0 = expand_normal (arg0);
23767 rtx op1 = expand_normal (arg1);
23768 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23769 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23770 enum rtx_code comparison = d->comparison;
23772 if (VECTOR_MODE_P (mode0))
23773 op0 = safe_vector_operand (op0, mode0);
23774 if (VECTOR_MODE_P (mode1))
23775 op1 = safe_vector_operand (op1, mode1);
23777 target = gen_reg_rtx (SImode);
23778 emit_move_insn (target, const0_rtx);
23779 target = gen_rtx_SUBREG (QImode, target, 0);
23781 if ((optimize && !register_operand (op0, mode0))
23782 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23783 op0 = copy_to_mode_reg (mode0, op0);
23784 if ((optimize && !register_operand (op1, mode1))
23785 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23786 op1 = copy_to_mode_reg (mode1, op1);
23788 pat = GEN_FCN (d->icode) (op0, op1);
23792 emit_insn (gen_rtx_SET (VOIDmode,
23793 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23794 gen_rtx_fmt_ee (comparison, QImode,
23798 return SUBREG_REG (target);
23801 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23804 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23805 tree exp, rtx target)
23808 tree arg0 = CALL_EXPR_ARG (exp, 0);
23809 tree arg1 = CALL_EXPR_ARG (exp, 1);
23810 tree arg2 = CALL_EXPR_ARG (exp, 2);
23811 tree arg3 = CALL_EXPR_ARG (exp, 3);
23812 tree arg4 = CALL_EXPR_ARG (exp, 4);
23813 rtx scratch0, scratch1;
23814 rtx op0 = expand_normal (arg0);
23815 rtx op1 = expand_normal (arg1);
23816 rtx op2 = expand_normal (arg2);
23817 rtx op3 = expand_normal (arg3);
23818 rtx op4 = expand_normal (arg4);
23819 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23821 tmode0 = insn_data[d->icode].operand[0].mode;
23822 tmode1 = insn_data[d->icode].operand[1].mode;
23823 modev2 = insn_data[d->icode].operand[2].mode;
23824 modei3 = insn_data[d->icode].operand[3].mode;
23825 modev4 = insn_data[d->icode].operand[4].mode;
23826 modei5 = insn_data[d->icode].operand[5].mode;
23827 modeimm = insn_data[d->icode].operand[6].mode;
23829 if (VECTOR_MODE_P (modev2))
23830 op0 = safe_vector_operand (op0, modev2);
23831 if (VECTOR_MODE_P (modev4))
23832 op2 = safe_vector_operand (op2, modev4);
23834 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23835 op0 = copy_to_mode_reg (modev2, op0);
23836 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23837 op1 = copy_to_mode_reg (modei3, op1);
23838 if ((optimize && !register_operand (op2, modev4))
23839 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23840 op2 = copy_to_mode_reg (modev4, op2);
23841 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23842 op3 = copy_to_mode_reg (modei5, op3);
23844 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23846 error ("the fifth argument must be a 8-bit immediate");
23850 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23852 if (optimize || !target
23853 || GET_MODE (target) != tmode0
23854 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23855 target = gen_reg_rtx (tmode0);
23857 scratch1 = gen_reg_rtx (tmode1);
23859 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23861 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23863 if (optimize || !target
23864 || GET_MODE (target) != tmode1
23865 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23866 target = gen_reg_rtx (tmode1);
23868 scratch0 = gen_reg_rtx (tmode0);
23870 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23874 gcc_assert (d->flag);
23876 scratch0 = gen_reg_rtx (tmode0);
23877 scratch1 = gen_reg_rtx (tmode1);
23879 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23889 target = gen_reg_rtx (SImode);
23890 emit_move_insn (target, const0_rtx);
23891 target = gen_rtx_SUBREG (QImode, target, 0);
23894 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23895 gen_rtx_fmt_ee (EQ, QImode,
23896 gen_rtx_REG ((enum machine_mode) d->flag,
23899 return SUBREG_REG (target);
23906 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23909 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23910 tree exp, rtx target)
23913 tree arg0 = CALL_EXPR_ARG (exp, 0);
23914 tree arg1 = CALL_EXPR_ARG (exp, 1);
23915 tree arg2 = CALL_EXPR_ARG (exp, 2);
23916 rtx scratch0, scratch1;
23917 rtx op0 = expand_normal (arg0);
23918 rtx op1 = expand_normal (arg1);
23919 rtx op2 = expand_normal (arg2);
23920 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23922 tmode0 = insn_data[d->icode].operand[0].mode;
23923 tmode1 = insn_data[d->icode].operand[1].mode;
23924 modev2 = insn_data[d->icode].operand[2].mode;
23925 modev3 = insn_data[d->icode].operand[3].mode;
23926 modeimm = insn_data[d->icode].operand[4].mode;
23928 if (VECTOR_MODE_P (modev2))
23929 op0 = safe_vector_operand (op0, modev2);
23930 if (VECTOR_MODE_P (modev3))
23931 op1 = safe_vector_operand (op1, modev3);
23933 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23934 op0 = copy_to_mode_reg (modev2, op0);
23935 if ((optimize && !register_operand (op1, modev3))
23936 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23937 op1 = copy_to_mode_reg (modev3, op1);
23939 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23941 error ("the third argument must be a 8-bit immediate");
23945 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23947 if (optimize || !target
23948 || GET_MODE (target) != tmode0
23949 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23950 target = gen_reg_rtx (tmode0);
23952 scratch1 = gen_reg_rtx (tmode1);
23954 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23956 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23958 if (optimize || !target
23959 || GET_MODE (target) != tmode1
23960 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23961 target = gen_reg_rtx (tmode1);
23963 scratch0 = gen_reg_rtx (tmode0);
23965 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23969 gcc_assert (d->flag);
23971 scratch0 = gen_reg_rtx (tmode0);
23972 scratch1 = gen_reg_rtx (tmode1);
23974 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23984 target = gen_reg_rtx (SImode);
23985 emit_move_insn (target, const0_rtx);
23986 target = gen_rtx_SUBREG (QImode, target, 0);
23989 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23990 gen_rtx_fmt_ee (EQ, QImode,
23991 gen_rtx_REG ((enum machine_mode) d->flag,
23994 return SUBREG_REG (target);
24000 /* Subroutine of ix86_expand_builtin to take care of insns with
24001 variable number of operands. */
24004 ix86_expand_args_builtin (const struct builtin_description *d,
24005 tree exp, rtx target)
24007 rtx pat, real_target;
24008 unsigned int i, nargs;
24009 unsigned int nargs_constant = 0;
24010 int num_memory = 0;
24014 enum machine_mode mode;
24016 bool last_arg_count = false;
24017 enum insn_code icode = d->icode;
24018 const struct insn_data *insn_p = &insn_data[icode];
24019 enum machine_mode tmode = insn_p->operand[0].mode;
24020 enum machine_mode rmode = VOIDmode;
24022 enum rtx_code comparison = d->comparison;
24024 switch ((enum ix86_builtin_type) d->flag)
24026 case INT_FTYPE_V8SF_V8SF_PTEST:
24027 case INT_FTYPE_V4DI_V4DI_PTEST:
24028 case INT_FTYPE_V4DF_V4DF_PTEST:
24029 case INT_FTYPE_V4SF_V4SF_PTEST:
24030 case INT_FTYPE_V2DI_V2DI_PTEST:
24031 case INT_FTYPE_V2DF_V2DF_PTEST:
24032 return ix86_expand_sse_ptest (d, exp, target);
24033 case FLOAT128_FTYPE_FLOAT128:
24034 case FLOAT_FTYPE_FLOAT:
24035 case INT64_FTYPE_V4SF:
24036 case INT64_FTYPE_V2DF:
24037 case INT_FTYPE_V16QI:
24038 case INT_FTYPE_V8QI:
24039 case INT_FTYPE_V8SF:
24040 case INT_FTYPE_V4DF:
24041 case INT_FTYPE_V4SF:
24042 case INT_FTYPE_V2DF:
24043 case V16QI_FTYPE_V16QI:
24044 case V8SI_FTYPE_V8SF:
24045 case V8SI_FTYPE_V4SI:
24046 case V8HI_FTYPE_V8HI:
24047 case V8HI_FTYPE_V16QI:
24048 case V8QI_FTYPE_V8QI:
24049 case V8SF_FTYPE_V8SF:
24050 case V8SF_FTYPE_V8SI:
24051 case V8SF_FTYPE_V4SF:
24052 case V4SI_FTYPE_V4SI:
24053 case V4SI_FTYPE_V16QI:
24054 case V4SI_FTYPE_V4SF:
24055 case V4SI_FTYPE_V8SI:
24056 case V4SI_FTYPE_V8HI:
24057 case V4SI_FTYPE_V4DF:
24058 case V4SI_FTYPE_V2DF:
24059 case V4HI_FTYPE_V4HI:
24060 case V4DF_FTYPE_V4DF:
24061 case V4DF_FTYPE_V4SI:
24062 case V4DF_FTYPE_V4SF:
24063 case V4DF_FTYPE_V2DF:
24064 case V4SF_FTYPE_V4SF:
24065 case V4SF_FTYPE_V4SI:
24066 case V4SF_FTYPE_V8SF:
24067 case V4SF_FTYPE_V4DF:
24068 case V4SF_FTYPE_V2DF:
24069 case V2DI_FTYPE_V2DI:
24070 case V2DI_FTYPE_V16QI:
24071 case V2DI_FTYPE_V8HI:
24072 case V2DI_FTYPE_V4SI:
24073 case V2DF_FTYPE_V2DF:
24074 case V2DF_FTYPE_V4SI:
24075 case V2DF_FTYPE_V4DF:
24076 case V2DF_FTYPE_V4SF:
24077 case V2DF_FTYPE_V2SI:
24078 case V2SI_FTYPE_V2SI:
24079 case V2SI_FTYPE_V4SF:
24080 case V2SI_FTYPE_V2SF:
24081 case V2SI_FTYPE_V2DF:
24082 case V2SF_FTYPE_V2SF:
24083 case V2SF_FTYPE_V2SI:
24086 case V4SF_FTYPE_V4SF_VEC_MERGE:
24087 case V2DF_FTYPE_V2DF_VEC_MERGE:
24088 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24089 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24090 case V16QI_FTYPE_V16QI_V16QI:
24091 case V16QI_FTYPE_V8HI_V8HI:
24092 case V8QI_FTYPE_V8QI_V8QI:
24093 case V8QI_FTYPE_V4HI_V4HI:
24094 case V8HI_FTYPE_V8HI_V8HI:
24095 case V8HI_FTYPE_V16QI_V16QI:
24096 case V8HI_FTYPE_V4SI_V4SI:
24097 case V8SF_FTYPE_V8SF_V8SF:
24098 case V8SF_FTYPE_V8SF_V8SI:
24099 case V4SI_FTYPE_V4SI_V4SI:
24100 case V4SI_FTYPE_V8HI_V8HI:
24101 case V4SI_FTYPE_V4SF_V4SF:
24102 case V4SI_FTYPE_V2DF_V2DF:
24103 case V4HI_FTYPE_V4HI_V4HI:
24104 case V4HI_FTYPE_V8QI_V8QI:
24105 case V4HI_FTYPE_V2SI_V2SI:
24106 case V4DF_FTYPE_V4DF_V4DF:
24107 case V4DF_FTYPE_V4DF_V4DI:
24108 case V4SF_FTYPE_V4SF_V4SF:
24109 case V4SF_FTYPE_V4SF_V4SI:
24110 case V4SF_FTYPE_V4SF_V2SI:
24111 case V4SF_FTYPE_V4SF_V2DF:
24112 case V4SF_FTYPE_V4SF_DI:
24113 case V4SF_FTYPE_V4SF_SI:
24114 case V2DI_FTYPE_V2DI_V2DI:
24115 case V2DI_FTYPE_V16QI_V16QI:
24116 case V2DI_FTYPE_V4SI_V4SI:
24117 case V2DI_FTYPE_V2DI_V16QI:
24118 case V2DI_FTYPE_V2DF_V2DF:
24119 case V2SI_FTYPE_V2SI_V2SI:
24120 case V2SI_FTYPE_V4HI_V4HI:
24121 case V2SI_FTYPE_V2SF_V2SF:
24122 case V2DF_FTYPE_V2DF_V2DF:
24123 case V2DF_FTYPE_V2DF_V4SF:
24124 case V2DF_FTYPE_V2DF_V2DI:
24125 case V2DF_FTYPE_V2DF_DI:
24126 case V2DF_FTYPE_V2DF_SI:
24127 case V2SF_FTYPE_V2SF_V2SF:
24128 case V1DI_FTYPE_V1DI_V1DI:
24129 case V1DI_FTYPE_V8QI_V8QI:
24130 case V1DI_FTYPE_V2SI_V2SI:
24131 if (comparison == UNKNOWN)
24132 return ix86_expand_binop_builtin (icode, exp, target);
24135 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24136 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24137 gcc_assert (comparison != UNKNOWN);
24141 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24142 case V8HI_FTYPE_V8HI_SI_COUNT:
24143 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24144 case V4SI_FTYPE_V4SI_SI_COUNT:
24145 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24146 case V4HI_FTYPE_V4HI_SI_COUNT:
24147 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24148 case V2DI_FTYPE_V2DI_SI_COUNT:
24149 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24150 case V2SI_FTYPE_V2SI_SI_COUNT:
24151 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24152 case V1DI_FTYPE_V1DI_SI_COUNT:
24154 last_arg_count = true;
24156 case UINT64_FTYPE_UINT64_UINT64:
24157 case UINT_FTYPE_UINT_UINT:
24158 case UINT_FTYPE_UINT_USHORT:
24159 case UINT_FTYPE_UINT_UCHAR:
24162 case V2DI2TI_FTYPE_V2DI_INT:
24165 nargs_constant = 1;
24167 case V8HI_FTYPE_V8HI_INT:
24168 case V8SF_FTYPE_V8SF_INT:
24169 case V4SI_FTYPE_V4SI_INT:
24170 case V4SI_FTYPE_V8SI_INT:
24171 case V4HI_FTYPE_V4HI_INT:
24172 case V4DF_FTYPE_V4DF_INT:
24173 case V4SF_FTYPE_V4SF_INT:
24174 case V4SF_FTYPE_V8SF_INT:
24175 case V2DI_FTYPE_V2DI_INT:
24176 case V2DF_FTYPE_V2DF_INT:
24177 case V2DF_FTYPE_V4DF_INT:
24179 nargs_constant = 1;
24181 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24182 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24183 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24184 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24185 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24188 case V16QI_FTYPE_V16QI_V16QI_INT:
24189 case V8HI_FTYPE_V8HI_V8HI_INT:
24190 case V8SI_FTYPE_V8SI_V8SI_INT:
24191 case V8SI_FTYPE_V8SI_V4SI_INT:
24192 case V8SF_FTYPE_V8SF_V8SF_INT:
24193 case V8SF_FTYPE_V8SF_V4SF_INT:
24194 case V4SI_FTYPE_V4SI_V4SI_INT:
24195 case V4DF_FTYPE_V4DF_V4DF_INT:
24196 case V4DF_FTYPE_V4DF_V2DF_INT:
24197 case V4SF_FTYPE_V4SF_V4SF_INT:
24198 case V2DI_FTYPE_V2DI_V2DI_INT:
24199 case V2DF_FTYPE_V2DF_V2DF_INT:
24201 nargs_constant = 1;
24203 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24206 nargs_constant = 1;
24208 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24211 nargs_constant = 1;
24213 case V2DI_FTYPE_V2DI_UINT_UINT:
24215 nargs_constant = 2;
24217 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24219 nargs_constant = 2;
24222 gcc_unreachable ();
24225 gcc_assert (nargs <= ARRAY_SIZE (args));
24227 if (comparison != UNKNOWN)
24229 gcc_assert (nargs == 2);
24230 return ix86_expand_sse_compare (d, exp, target, swap);
24233 if (rmode == VOIDmode || rmode == tmode)
24237 || GET_MODE (target) != tmode
24238 || ! (*insn_p->operand[0].predicate) (target, tmode))
24239 target = gen_reg_rtx (tmode);
24240 real_target = target;
24244 target = gen_reg_rtx (rmode);
24245 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24248 for (i = 0; i < nargs; i++)
24250 tree arg = CALL_EXPR_ARG (exp, i);
24251 rtx op = expand_normal (arg);
24252 enum machine_mode mode = insn_p->operand[i + 1].mode;
24253 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24255 if (last_arg_count && (i + 1) == nargs)
24257 /* SIMD shift insns take either an 8-bit immediate or
24258 register as count. But builtin functions take int as
24259 count. If count doesn't match, we put it in register. */
24262 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24263 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24264 op = copy_to_reg (op);
24267 else if ((nargs - i) <= nargs_constant)
24272 case CODE_FOR_sse4_1_roundpd:
24273 case CODE_FOR_sse4_1_roundps:
24274 case CODE_FOR_sse4_1_roundsd:
24275 case CODE_FOR_sse4_1_roundss:
24276 case CODE_FOR_sse4_1_blendps:
24277 case CODE_FOR_avx_blendpd256:
24278 case CODE_FOR_avx_vpermilv4df:
24279 case CODE_FOR_avx_roundpd256:
24280 case CODE_FOR_avx_roundps256:
24281 error ("the last argument must be a 4-bit immediate");
24284 case CODE_FOR_sse4_1_blendpd:
24285 case CODE_FOR_avx_vpermilv2df:
24286 error ("the last argument must be a 2-bit immediate");
24289 case CODE_FOR_avx_vextractf128v4df:
24290 case CODE_FOR_avx_vextractf128v8sf:
24291 case CODE_FOR_avx_vextractf128v8si:
24292 case CODE_FOR_avx_vinsertf128v4df:
24293 case CODE_FOR_avx_vinsertf128v8sf:
24294 case CODE_FOR_avx_vinsertf128v8si:
24295 error ("the last argument must be a 1-bit immediate");
24298 case CODE_FOR_avx_cmpsdv2df3:
24299 case CODE_FOR_avx_cmpssv4sf3:
24300 case CODE_FOR_avx_cmppdv2df3:
24301 case CODE_FOR_avx_cmppsv4sf3:
24302 case CODE_FOR_avx_cmppdv4df3:
24303 case CODE_FOR_avx_cmppsv8sf3:
24304 error ("the last argument must be a 5-bit immediate");
24308 switch (nargs_constant)
24311 if ((nargs - i) == nargs_constant)
24313 error ("the next to last argument must be an 8-bit immediate");
24317 error ("the last argument must be an 8-bit immediate");
24320 gcc_unreachable ();
24327 if (VECTOR_MODE_P (mode))
24328 op = safe_vector_operand (op, mode);
24330 /* If we aren't optimizing, only allow one memory operand to
24332 if (memory_operand (op, mode))
24335 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24337 if (optimize || !match || num_memory > 1)
24338 op = copy_to_mode_reg (mode, op);
24342 op = copy_to_reg (op);
24343 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24348 args[i].mode = mode;
24354 pat = GEN_FCN (icode) (real_target, args[0].op);
24357 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24360 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24364 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24365 args[2].op, args[3].op);
24368 gcc_unreachable ();
24378 /* Subroutine of ix86_expand_builtin to take care of special insns
24379 with variable number of operands. */
24382 ix86_expand_special_args_builtin (const struct builtin_description *d,
24383 tree exp, rtx target)
24387 unsigned int i, nargs, arg_adjust, memory;
24391 enum machine_mode mode;
24393 enum insn_code icode = d->icode;
24394 bool last_arg_constant = false;
24395 const struct insn_data *insn_p = &insn_data[icode];
24396 enum machine_mode tmode = insn_p->operand[0].mode;
24397 enum { load, store } klass;
24399 switch ((enum ix86_special_builtin_type) d->flag)
24401 case VOID_FTYPE_VOID:
24402 emit_insn (GEN_FCN (icode) (target));
24404 case V2DI_FTYPE_PV2DI:
24405 case V32QI_FTYPE_PCCHAR:
24406 case V16QI_FTYPE_PCCHAR:
24407 case V8SF_FTYPE_PCV4SF:
24408 case V8SF_FTYPE_PCFLOAT:
24409 case V4SF_FTYPE_PCFLOAT:
24410 case V4DF_FTYPE_PCV2DF:
24411 case V4DF_FTYPE_PCDOUBLE:
24412 case V2DF_FTYPE_PCDOUBLE:
24417 case VOID_FTYPE_PV2SF_V4SF:
24418 case VOID_FTYPE_PV4DI_V4DI:
24419 case VOID_FTYPE_PV2DI_V2DI:
24420 case VOID_FTYPE_PCHAR_V32QI:
24421 case VOID_FTYPE_PCHAR_V16QI:
24422 case VOID_FTYPE_PFLOAT_V8SF:
24423 case VOID_FTYPE_PFLOAT_V4SF:
24424 case VOID_FTYPE_PDOUBLE_V4DF:
24425 case VOID_FTYPE_PDOUBLE_V2DF:
24426 case VOID_FTYPE_PDI_DI:
24427 case VOID_FTYPE_PINT_INT:
24430 /* Reserve memory operand for target. */
24431 memory = ARRAY_SIZE (args);
24433 case V4SF_FTYPE_V4SF_PCV2SF:
24434 case V2DF_FTYPE_V2DF_PCDOUBLE:
24439 case V8SF_FTYPE_PCV8SF_V8SF:
24440 case V4DF_FTYPE_PCV4DF_V4DF:
24441 case V4SF_FTYPE_PCV4SF_V4SF:
24442 case V2DF_FTYPE_PCV2DF_V2DF:
24447 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24448 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24449 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24450 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24453 /* Reserve memory operand for target. */
24454 memory = ARRAY_SIZE (args);
24457 gcc_unreachable ();
24460 gcc_assert (nargs <= ARRAY_SIZE (args));
24462 if (klass == store)
24464 arg = CALL_EXPR_ARG (exp, 0);
24465 op = expand_normal (arg);
24466 gcc_assert (target == 0);
24467 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24475 || GET_MODE (target) != tmode
24476 || ! (*insn_p->operand[0].predicate) (target, tmode))
24477 target = gen_reg_rtx (tmode);
24480 for (i = 0; i < nargs; i++)
24482 enum machine_mode mode = insn_p->operand[i + 1].mode;
24485 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24486 op = expand_normal (arg);
24487 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24489 if (last_arg_constant && (i + 1) == nargs)
24495 error ("the last argument must be an 8-bit immediate");
24503 /* This must be the memory operand. */
24504 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24505 gcc_assert (GET_MODE (op) == mode
24506 || GET_MODE (op) == VOIDmode);
24510 /* This must be register. */
24511 if (VECTOR_MODE_P (mode))
24512 op = safe_vector_operand (op, mode);
24514 gcc_assert (GET_MODE (op) == mode
24515 || GET_MODE (op) == VOIDmode);
24516 op = copy_to_mode_reg (mode, op);
24521 args[i].mode = mode;
24527 pat = GEN_FCN (icode) (target, args[0].op);
24530 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24533 gcc_unreachable ();
24539 return klass == store ? 0 : target;
24542 /* Return the integer constant in ARG. Constrain it to be in the range
24543 of the subparts of VEC_TYPE; issue an error if not. */
24546 get_element_number (tree vec_type, tree arg)
24548 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24550 if (!host_integerp (arg, 1)
24551 || (elt = tree_low_cst (arg, 1), elt > max))
24553 error ("selector must be an integer constant in the range 0..%wi", max);
24560 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24561 ix86_expand_vector_init. We DO have language-level syntax for this, in
24562 the form of (type){ init-list }. Except that since we can't place emms
24563 instructions from inside the compiler, we can't allow the use of MMX
24564 registers unless the user explicitly asks for it. So we do *not* define
24565 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24566 we have builtins invoked by mmintrin.h that gives us license to emit
24567 these sorts of instructions. */
24570 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24572 enum machine_mode tmode = TYPE_MODE (type);
24573 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24574 int i, n_elt = GET_MODE_NUNITS (tmode);
24575 rtvec v = rtvec_alloc (n_elt);
24577 gcc_assert (VECTOR_MODE_P (tmode));
24578 gcc_assert (call_expr_nargs (exp) == n_elt);
24580 for (i = 0; i < n_elt; ++i)
24582 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24583 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24586 if (!target || !register_operand (target, tmode))
24587 target = gen_reg_rtx (tmode);
24589 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24593 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24594 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24595 had a language-level syntax for referencing vector elements. */
24598 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24600 enum machine_mode tmode, mode0;
24605 arg0 = CALL_EXPR_ARG (exp, 0);
24606 arg1 = CALL_EXPR_ARG (exp, 1);
24608 op0 = expand_normal (arg0);
24609 elt = get_element_number (TREE_TYPE (arg0), arg1);
24611 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24612 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24613 gcc_assert (VECTOR_MODE_P (mode0));
24615 op0 = force_reg (mode0, op0);
24617 if (optimize || !target || !register_operand (target, tmode))
24618 target = gen_reg_rtx (tmode);
24620 ix86_expand_vector_extract (true, target, op0, elt);
24625 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24626 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24627 a language-level syntax for referencing vector elements. */
24630 ix86_expand_vec_set_builtin (tree exp)
24632 enum machine_mode tmode, mode1;
24633 tree arg0, arg1, arg2;
24635 rtx op0, op1, target;
24637 arg0 = CALL_EXPR_ARG (exp, 0);
24638 arg1 = CALL_EXPR_ARG (exp, 1);
24639 arg2 = CALL_EXPR_ARG (exp, 2);
24641 tmode = TYPE_MODE (TREE_TYPE (arg0));
24642 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24643 gcc_assert (VECTOR_MODE_P (tmode));
24645 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24646 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24647 elt = get_element_number (TREE_TYPE (arg0), arg2);
24649 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24650 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24652 op0 = force_reg (tmode, op0);
24653 op1 = force_reg (mode1, op1);
24655 /* OP0 is the source of these builtin functions and shouldn't be
24656 modified. Create a copy, use it and return it as target. */
24657 target = gen_reg_rtx (tmode);
24658 emit_move_insn (target, op0);
24659 ix86_expand_vector_set (true, target, op1, elt);
24664 /* Expand an expression EXP that calls a built-in function,
24665 with result going to TARGET if that's convenient
24666 (and in mode MODE if that's convenient).
24667 SUBTARGET may be used as the target for computing one of EXP's operands.
24668 IGNORE is nonzero if the value is to be ignored. */
24671 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24672 enum machine_mode mode ATTRIBUTE_UNUSED,
24673 int ignore ATTRIBUTE_UNUSED)
24675 const struct builtin_description *d;
24677 enum insn_code icode;
24678 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24679 tree arg0, arg1, arg2;
24680 rtx op0, op1, op2, pat;
24681 enum machine_mode mode0, mode1, mode2;
24682 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24684 /* Determine whether the builtin function is available under the current ISA.
24685 Originally the builtin was not created if it wasn't applicable to the
24686 current ISA based on the command line switches. With function specific
24687 options, we need to check in the context of the function making the call
24688 whether it is supported. */
24689 if (ix86_builtins_isa[fcode].isa
24690 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24692 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24693 NULL, NULL, false);
24696 error ("%qE needs unknown isa option", fndecl);
24699 gcc_assert (opts != NULL);
24700 error ("%qE needs isa option %s", fndecl, opts);
24708 case IX86_BUILTIN_MASKMOVQ:
24709 case IX86_BUILTIN_MASKMOVDQU:
24710 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24711 ? CODE_FOR_mmx_maskmovq
24712 : CODE_FOR_sse2_maskmovdqu);
24713 /* Note the arg order is different from the operand order. */
24714 arg1 = CALL_EXPR_ARG (exp, 0);
24715 arg2 = CALL_EXPR_ARG (exp, 1);
24716 arg0 = CALL_EXPR_ARG (exp, 2);
24717 op0 = expand_normal (arg0);
24718 op1 = expand_normal (arg1);
24719 op2 = expand_normal (arg2);
24720 mode0 = insn_data[icode].operand[0].mode;
24721 mode1 = insn_data[icode].operand[1].mode;
24722 mode2 = insn_data[icode].operand[2].mode;
24724 op0 = force_reg (Pmode, op0);
24725 op0 = gen_rtx_MEM (mode1, op0);
24727 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24728 op0 = copy_to_mode_reg (mode0, op0);
24729 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24730 op1 = copy_to_mode_reg (mode1, op1);
24731 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24732 op2 = copy_to_mode_reg (mode2, op2);
24733 pat = GEN_FCN (icode) (op0, op1, op2);
24739 case IX86_BUILTIN_LDMXCSR:
24740 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24741 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24742 emit_move_insn (target, op0);
24743 emit_insn (gen_sse_ldmxcsr (target));
24746 case IX86_BUILTIN_STMXCSR:
24747 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24748 emit_insn (gen_sse_stmxcsr (target));
24749 return copy_to_mode_reg (SImode, target);
24751 case IX86_BUILTIN_CLFLUSH:
24752 arg0 = CALL_EXPR_ARG (exp, 0);
24753 op0 = expand_normal (arg0);
24754 icode = CODE_FOR_sse2_clflush;
24755 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24756 op0 = copy_to_mode_reg (Pmode, op0);
24758 emit_insn (gen_sse2_clflush (op0));
24761 case IX86_BUILTIN_MONITOR:
24762 arg0 = CALL_EXPR_ARG (exp, 0);
24763 arg1 = CALL_EXPR_ARG (exp, 1);
24764 arg2 = CALL_EXPR_ARG (exp, 2);
24765 op0 = expand_normal (arg0);
24766 op1 = expand_normal (arg1);
24767 op2 = expand_normal (arg2);
24769 op0 = copy_to_mode_reg (Pmode, op0);
24771 op1 = copy_to_mode_reg (SImode, op1);
24773 op2 = copy_to_mode_reg (SImode, op2);
24774 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24777 case IX86_BUILTIN_MWAIT:
24778 arg0 = CALL_EXPR_ARG (exp, 0);
24779 arg1 = CALL_EXPR_ARG (exp, 1);
24780 op0 = expand_normal (arg0);
24781 op1 = expand_normal (arg1);
24783 op0 = copy_to_mode_reg (SImode, op0);
24785 op1 = copy_to_mode_reg (SImode, op1);
24786 emit_insn (gen_sse3_mwait (op0, op1));
24789 case IX86_BUILTIN_VEC_INIT_V2SI:
24790 case IX86_BUILTIN_VEC_INIT_V4HI:
24791 case IX86_BUILTIN_VEC_INIT_V8QI:
24792 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24794 case IX86_BUILTIN_VEC_EXT_V2DF:
24795 case IX86_BUILTIN_VEC_EXT_V2DI:
24796 case IX86_BUILTIN_VEC_EXT_V4SF:
24797 case IX86_BUILTIN_VEC_EXT_V4SI:
24798 case IX86_BUILTIN_VEC_EXT_V8HI:
24799 case IX86_BUILTIN_VEC_EXT_V2SI:
24800 case IX86_BUILTIN_VEC_EXT_V4HI:
24801 case IX86_BUILTIN_VEC_EXT_V16QI:
24802 return ix86_expand_vec_ext_builtin (exp, target);
24804 case IX86_BUILTIN_VEC_SET_V2DI:
24805 case IX86_BUILTIN_VEC_SET_V4SF:
24806 case IX86_BUILTIN_VEC_SET_V4SI:
24807 case IX86_BUILTIN_VEC_SET_V8HI:
24808 case IX86_BUILTIN_VEC_SET_V4HI:
24809 case IX86_BUILTIN_VEC_SET_V16QI:
24810 return ix86_expand_vec_set_builtin (exp);
24812 case IX86_BUILTIN_INFQ:
24814 REAL_VALUE_TYPE inf;
24818 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24820 tmp = validize_mem (force_const_mem (mode, tmp));
24823 target = gen_reg_rtx (mode);
24825 emit_move_insn (target, tmp);
24833 for (i = 0, d = bdesc_special_args;
24834 i < ARRAY_SIZE (bdesc_special_args);
24836 if (d->code == fcode)
24837 return ix86_expand_special_args_builtin (d, exp, target);
24839 for (i = 0, d = bdesc_args;
24840 i < ARRAY_SIZE (bdesc_args);
24842 if (d->code == fcode)
24845 case IX86_BUILTIN_FABSQ:
24846 case IX86_BUILTIN_COPYSIGNQ:
24848 /* Emit a normal call if SSE2 isn't available. */
24849 return expand_call (exp, target, ignore);
24851 return ix86_expand_args_builtin (d, exp, target);
24854 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24855 if (d->code == fcode)
24856 return ix86_expand_sse_comi (d, exp, target);
24858 for (i = 0, d = bdesc_pcmpestr;
24859 i < ARRAY_SIZE (bdesc_pcmpestr);
24861 if (d->code == fcode)
24862 return ix86_expand_sse_pcmpestr (d, exp, target);
24864 for (i = 0, d = bdesc_pcmpistr;
24865 i < ARRAY_SIZE (bdesc_pcmpistr);
24867 if (d->code == fcode)
24868 return ix86_expand_sse_pcmpistr (d, exp, target);
24870 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24871 if (d->code == fcode)
24872 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24873 (enum multi_arg_type)d->flag,
24876 gcc_unreachable ();
24879 /* Returns a function decl for a vectorized version of the builtin function
24880 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24881 if it is not available. */
24884 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24887 enum machine_mode in_mode, out_mode;
24890 if (TREE_CODE (type_out) != VECTOR_TYPE
24891 || TREE_CODE (type_in) != VECTOR_TYPE)
24894 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24895 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24896 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24897 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24901 case BUILT_IN_SQRT:
24902 if (out_mode == DFmode && out_n == 2
24903 && in_mode == DFmode && in_n == 2)
24904 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24907 case BUILT_IN_SQRTF:
24908 if (out_mode == SFmode && out_n == 4
24909 && in_mode == SFmode && in_n == 4)
24910 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24913 case BUILT_IN_LRINT:
24914 if (out_mode == SImode && out_n == 4
24915 && in_mode == DFmode && in_n == 2)
24916 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24919 case BUILT_IN_LRINTF:
24920 if (out_mode == SImode && out_n == 4
24921 && in_mode == SFmode && in_n == 4)
24922 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24929 /* Dispatch to a handler for a vectorization library. */
24930 if (ix86_veclib_handler)
24931 return (*ix86_veclib_handler)(fn, type_out, type_in);
24936 /* Handler for an SVML-style interface to
24937 a library with vectorized intrinsics. */
24940 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24943 tree fntype, new_fndecl, args;
24946 enum machine_mode el_mode, in_mode;
24949 /* The SVML is suitable for unsafe math only. */
24950 if (!flag_unsafe_math_optimizations)
24953 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24954 n = TYPE_VECTOR_SUBPARTS (type_out);
24955 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24956 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24957 if (el_mode != in_mode
24965 case BUILT_IN_LOG10:
24967 case BUILT_IN_TANH:
24969 case BUILT_IN_ATAN:
24970 case BUILT_IN_ATAN2:
24971 case BUILT_IN_ATANH:
24972 case BUILT_IN_CBRT:
24973 case BUILT_IN_SINH:
24975 case BUILT_IN_ASINH:
24976 case BUILT_IN_ASIN:
24977 case BUILT_IN_COSH:
24979 case BUILT_IN_ACOSH:
24980 case BUILT_IN_ACOS:
24981 if (el_mode != DFmode || n != 2)
24985 case BUILT_IN_EXPF:
24986 case BUILT_IN_LOGF:
24987 case BUILT_IN_LOG10F:
24988 case BUILT_IN_POWF:
24989 case BUILT_IN_TANHF:
24990 case BUILT_IN_TANF:
24991 case BUILT_IN_ATANF:
24992 case BUILT_IN_ATAN2F:
24993 case BUILT_IN_ATANHF:
24994 case BUILT_IN_CBRTF:
24995 case BUILT_IN_SINHF:
24996 case BUILT_IN_SINF:
24997 case BUILT_IN_ASINHF:
24998 case BUILT_IN_ASINF:
24999 case BUILT_IN_COSHF:
25000 case BUILT_IN_COSF:
25001 case BUILT_IN_ACOSHF:
25002 case BUILT_IN_ACOSF:
25003 if (el_mode != SFmode || n != 4)
25011 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25013 if (fn == BUILT_IN_LOGF)
25014 strcpy (name, "vmlsLn4");
25015 else if (fn == BUILT_IN_LOG)
25016 strcpy (name, "vmldLn2");
25019 sprintf (name, "vmls%s", bname+10);
25020 name[strlen (name)-1] = '4';
25023 sprintf (name, "vmld%s2", bname+10);
25025 /* Convert to uppercase. */
25029 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25030 args = TREE_CHAIN (args))
25034 fntype = build_function_type_list (type_out, type_in, NULL);
25036 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25038 /* Build a function declaration for the vectorized function. */
25039 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25040 TREE_PUBLIC (new_fndecl) = 1;
25041 DECL_EXTERNAL (new_fndecl) = 1;
25042 DECL_IS_NOVOPS (new_fndecl) = 1;
25043 TREE_READONLY (new_fndecl) = 1;
25048 /* Handler for an ACML-style interface to
25049 a library with vectorized intrinsics. */
25052 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25054 char name[20] = "__vr.._";
25055 tree fntype, new_fndecl, args;
25058 enum machine_mode el_mode, in_mode;
25061 /* The ACML is 64bits only and suitable for unsafe math only as
25062 it does not correctly support parts of IEEE with the required
25063 precision such as denormals. */
25065 || !flag_unsafe_math_optimizations)
25068 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25069 n = TYPE_VECTOR_SUBPARTS (type_out);
25070 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25071 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25072 if (el_mode != in_mode
25082 case BUILT_IN_LOG2:
25083 case BUILT_IN_LOG10:
25086 if (el_mode != DFmode
25091 case BUILT_IN_SINF:
25092 case BUILT_IN_COSF:
25093 case BUILT_IN_EXPF:
25094 case BUILT_IN_POWF:
25095 case BUILT_IN_LOGF:
25096 case BUILT_IN_LOG2F:
25097 case BUILT_IN_LOG10F:
25100 if (el_mode != SFmode
25109 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25110 sprintf (name + 7, "%s", bname+10);
25113 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25114 args = TREE_CHAIN (args))
25118 fntype = build_function_type_list (type_out, type_in, NULL);
25120 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25122 /* Build a function declaration for the vectorized function. */
25123 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25124 TREE_PUBLIC (new_fndecl) = 1;
25125 DECL_EXTERNAL (new_fndecl) = 1;
25126 DECL_IS_NOVOPS (new_fndecl) = 1;
25127 TREE_READONLY (new_fndecl) = 1;
25133 /* Returns a decl of a function that implements conversion of an integer vector
25134 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25135 side of the conversion.
25136 Return NULL_TREE if it is not available. */
25139 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25141 if (TREE_CODE (type) != VECTOR_TYPE)
25147 switch (TYPE_MODE (type))
25150 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25155 case FIX_TRUNC_EXPR:
25156 switch (TYPE_MODE (type))
25159 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25169 /* Returns a code for a target-specific builtin that implements
25170 reciprocal of the function, or NULL_TREE if not available. */
25173 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25174 bool sqrt ATTRIBUTE_UNUSED)
25176 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25177 && flag_finite_math_only && !flag_trapping_math
25178 && flag_unsafe_math_optimizations))
25182 /* Machine dependent builtins. */
25185 /* Vectorized version of sqrt to rsqrt conversion. */
25186 case IX86_BUILTIN_SQRTPS_NR:
25187 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25193 /* Normal builtins. */
25196 /* Sqrt to rsqrt conversion. */
25197 case BUILT_IN_SQRTF:
25198 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25205 /* Store OPERAND to the memory after reload is completed. This means
25206 that we can't easily use assign_stack_local. */
25208 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25212 gcc_assert (reload_completed);
25213 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25215 result = gen_rtx_MEM (mode,
25216 gen_rtx_PLUS (Pmode,
25218 GEN_INT (-RED_ZONE_SIZE)));
25219 emit_move_insn (result, operand);
25221 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25227 operand = gen_lowpart (DImode, operand);
25231 gen_rtx_SET (VOIDmode,
25232 gen_rtx_MEM (DImode,
25233 gen_rtx_PRE_DEC (DImode,
25234 stack_pointer_rtx)),
25238 gcc_unreachable ();
25240 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25249 split_di (&operand, 1, operands, operands + 1);
25251 gen_rtx_SET (VOIDmode,
25252 gen_rtx_MEM (SImode,
25253 gen_rtx_PRE_DEC (Pmode,
25254 stack_pointer_rtx)),
25257 gen_rtx_SET (VOIDmode,
25258 gen_rtx_MEM (SImode,
25259 gen_rtx_PRE_DEC (Pmode,
25260 stack_pointer_rtx)),
25265 /* Store HImodes as SImodes. */
25266 operand = gen_lowpart (SImode, operand);
25270 gen_rtx_SET (VOIDmode,
25271 gen_rtx_MEM (GET_MODE (operand),
25272 gen_rtx_PRE_DEC (SImode,
25273 stack_pointer_rtx)),
25277 gcc_unreachable ();
25279 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25284 /* Free operand from the memory. */
25286 ix86_free_from_memory (enum machine_mode mode)
25288 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25292 if (mode == DImode || TARGET_64BIT)
25296 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25297 to pop or add instruction if registers are available. */
25298 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25299 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25304 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25305 QImode must go into class Q_REGS.
25306 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25307 movdf to do mem-to-mem moves through integer regs. */
25309 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25311 enum machine_mode mode = GET_MODE (x);
25313 /* We're only allowed to return a subclass of CLASS. Many of the
25314 following checks fail for NO_REGS, so eliminate that early. */
25315 if (regclass == NO_REGS)
25318 /* All classes can load zeros. */
25319 if (x == CONST0_RTX (mode))
25322 /* Force constants into memory if we are loading a (nonzero) constant into
25323 an MMX or SSE register. This is because there are no MMX/SSE instructions
25324 to load from a constant. */
25326 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25329 /* Prefer SSE regs only, if we can use them for math. */
25330 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25331 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25333 /* Floating-point constants need more complex checks. */
25334 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25336 /* General regs can load everything. */
25337 if (reg_class_subset_p (regclass, GENERAL_REGS))
25340 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25341 zero above. We only want to wind up preferring 80387 registers if
25342 we plan on doing computation with them. */
25344 && standard_80387_constant_p (x))
25346 /* Limit class to non-sse. */
25347 if (regclass == FLOAT_SSE_REGS)
25349 if (regclass == FP_TOP_SSE_REGS)
25351 if (regclass == FP_SECOND_SSE_REGS)
25352 return FP_SECOND_REG;
25353 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25360 /* Generally when we see PLUS here, it's the function invariant
25361 (plus soft-fp const_int). Which can only be computed into general
25363 if (GET_CODE (x) == PLUS)
25364 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25366 /* QImode constants are easy to load, but non-constant QImode data
25367 must go into Q_REGS. */
25368 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25370 if (reg_class_subset_p (regclass, Q_REGS))
25372 if (reg_class_subset_p (Q_REGS, regclass))
25380 /* Discourage putting floating-point values in SSE registers unless
25381 SSE math is being used, and likewise for the 387 registers. */
25383 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25385 enum machine_mode mode = GET_MODE (x);
25387 /* Restrict the output reload class to the register bank that we are doing
25388 math on. If we would like not to return a subset of CLASS, reject this
25389 alternative: if reload cannot do this, it will still use its choice. */
25390 mode = GET_MODE (x);
25391 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25392 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25394 if (X87_FLOAT_MODE_P (mode))
25396 if (regclass == FP_TOP_SSE_REGS)
25398 else if (regclass == FP_SECOND_SSE_REGS)
25399 return FP_SECOND_REG;
25401 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25407 static enum reg_class
25408 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25409 enum machine_mode mode,
25410 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25412 /* QImode spills from non-QI registers require
25413 intermediate register on 32bit targets. */
25414 if (!in_p && mode == QImode && !TARGET_64BIT
25415 && (rclass == GENERAL_REGS
25416 || rclass == LEGACY_REGS
25417 || rclass == INDEX_REGS))
25426 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25427 regno = true_regnum (x);
25429 /* Return Q_REGS if the operand is in memory. */
25437 /* If we are copying between general and FP registers, we need a memory
25438 location. The same is true for SSE and MMX registers.
25440 To optimize register_move_cost performance, allow inline variant.
25442 The macro can't work reliably when one of the CLASSES is class containing
25443 registers from multiple units (SSE, MMX, integer). We avoid this by never
25444 combining those units in single alternative in the machine description.
25445 Ensure that this constraint holds to avoid unexpected surprises.
25447 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25448 enforce these sanity checks. */
25451 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25452 enum machine_mode mode, int strict)
25454 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25455 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25456 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25457 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25458 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25459 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25461 gcc_assert (!strict);
25465 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25468 /* ??? This is a lie. We do have moves between mmx/general, and for
25469 mmx/sse2. But by saying we need secondary memory we discourage the
25470 register allocator from using the mmx registers unless needed. */
25471 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25474 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25476 /* SSE1 doesn't have any direct moves from other classes. */
25480 /* If the target says that inter-unit moves are more expensive
25481 than moving through memory, then don't generate them. */
25482 if (!TARGET_INTER_UNIT_MOVES)
25485 /* Between SSE and general, we have moves no larger than word size. */
25486 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25494 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25495 enum machine_mode mode, int strict)
25497 return inline_secondary_memory_needed (class1, class2, mode, strict);
25500 /* Return true if the registers in CLASS cannot represent the change from
25501 modes FROM to TO. */
25504 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25505 enum reg_class regclass)
25510 /* x87 registers can't do subreg at all, as all values are reformatted
25511 to extended precision. */
25512 if (MAYBE_FLOAT_CLASS_P (regclass))
25515 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25517 /* Vector registers do not support QI or HImode loads. If we don't
25518 disallow a change to these modes, reload will assume it's ok to
25519 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25520 the vec_dupv4hi pattern. */
25521 if (GET_MODE_SIZE (from) < 4)
25524 /* Vector registers do not support subreg with nonzero offsets, which
25525 are otherwise valid for integer registers. Since we can't see
25526 whether we have a nonzero offset from here, prohibit all
25527 nonparadoxical subregs changing size. */
25528 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25535 /* Return the cost of moving data of mode M between a
25536 register and memory. A value of 2 is the default; this cost is
25537 relative to those in `REGISTER_MOVE_COST'.
25539 This function is used extensively by register_move_cost that is used to
25540 build tables at startup. Make it inline in this case.
25541 When IN is 2, return maximum of in and out move cost.
25543 If moving between registers and memory is more expensive than
25544 between two registers, you should define this macro to express the
25547 Model also increased moving costs of QImode registers in non
25551 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25555 if (FLOAT_CLASS_P (regclass))
25573 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25574 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25576 if (SSE_CLASS_P (regclass))
25579 switch (GET_MODE_SIZE (mode))
25594 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25595 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25597 if (MMX_CLASS_P (regclass))
25600 switch (GET_MODE_SIZE (mode))
25612 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25613 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25615 switch (GET_MODE_SIZE (mode))
25618 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25621 return ix86_cost->int_store[0];
25622 if (TARGET_PARTIAL_REG_DEPENDENCY
25623 && optimize_function_for_speed_p (cfun))
25624 cost = ix86_cost->movzbl_load;
25626 cost = ix86_cost->int_load[0];
25628 return MAX (cost, ix86_cost->int_store[0]);
25634 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25636 return ix86_cost->movzbl_load;
25638 return ix86_cost->int_store[0] + 4;
25643 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25644 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25646 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25647 if (mode == TFmode)
25650 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25652 cost = ix86_cost->int_load[2];
25654 cost = ix86_cost->int_store[2];
25655 return (cost * (((int) GET_MODE_SIZE (mode)
25656 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25661 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25663 return inline_memory_move_cost (mode, regclass, in);
25667 /* Return the cost of moving data from a register in class CLASS1 to
25668 one in class CLASS2.
25670 It is not required that the cost always equal 2 when FROM is the same as TO;
25671 on some machines it is expensive to move between registers if they are not
25672 general registers. */
25675 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25676 enum reg_class class2)
25678 /* In case we require secondary memory, compute cost of the store followed
25679 by load. In order to avoid bad register allocation choices, we need
25680 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25682 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25686 cost += inline_memory_move_cost (mode, class1, 2);
25687 cost += inline_memory_move_cost (mode, class2, 2);
25689 /* In case of copying from general_purpose_register we may emit multiple
25690 stores followed by single load causing memory size mismatch stall.
25691 Count this as arbitrarily high cost of 20. */
25692 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25695 /* In the case of FP/MMX moves, the registers actually overlap, and we
25696 have to switch modes in order to treat them differently. */
25697 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25698 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25704 /* Moves between SSE/MMX and integer unit are expensive. */
25705 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25706 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25708 /* ??? By keeping returned value relatively high, we limit the number
25709 of moves between integer and MMX/SSE registers for all targets.
25710 Additionally, high value prevents problem with x86_modes_tieable_p(),
25711 where integer modes in MMX/SSE registers are not tieable
25712 because of missing QImode and HImode moves to, from or between
25713 MMX/SSE registers. */
25714 return MAX (8, ix86_cost->mmxsse_to_integer);
25716 if (MAYBE_FLOAT_CLASS_P (class1))
25717 return ix86_cost->fp_move;
25718 if (MAYBE_SSE_CLASS_P (class1))
25719 return ix86_cost->sse_move;
25720 if (MAYBE_MMX_CLASS_P (class1))
25721 return ix86_cost->mmx_move;
25725 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25728 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25730 /* Flags and only flags can only hold CCmode values. */
25731 if (CC_REGNO_P (regno))
25732 return GET_MODE_CLASS (mode) == MODE_CC;
25733 if (GET_MODE_CLASS (mode) == MODE_CC
25734 || GET_MODE_CLASS (mode) == MODE_RANDOM
25735 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25737 if (FP_REGNO_P (regno))
25738 return VALID_FP_MODE_P (mode);
25739 if (SSE_REGNO_P (regno))
25741 /* We implement the move patterns for all vector modes into and
25742 out of SSE registers, even when no operation instructions
25743 are available. OImode move is available only when AVX is
25745 return ((TARGET_AVX && mode == OImode)
25746 || VALID_AVX256_REG_MODE (mode)
25747 || VALID_SSE_REG_MODE (mode)
25748 || VALID_SSE2_REG_MODE (mode)
25749 || VALID_MMX_REG_MODE (mode)
25750 || VALID_MMX_REG_MODE_3DNOW (mode));
25752 if (MMX_REGNO_P (regno))
25754 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25755 so if the register is available at all, then we can move data of
25756 the given mode into or out of it. */
25757 return (VALID_MMX_REG_MODE (mode)
25758 || VALID_MMX_REG_MODE_3DNOW (mode));
25761 if (mode == QImode)
25763 /* Take care for QImode values - they can be in non-QI regs,
25764 but then they do cause partial register stalls. */
25765 if (regno <= BX_REG || TARGET_64BIT)
25767 if (!TARGET_PARTIAL_REG_STALL)
25769 return reload_in_progress || reload_completed;
25771 /* We handle both integer and floats in the general purpose registers. */
25772 else if (VALID_INT_MODE_P (mode))
25774 else if (VALID_FP_MODE_P (mode))
25776 else if (VALID_DFP_MODE_P (mode))
25778 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25779 on to use that value in smaller contexts, this can easily force a
25780 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25781 supporting DImode, allow it. */
25782 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25788 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25789 tieable integer mode. */
25792 ix86_tieable_integer_mode_p (enum machine_mode mode)
25801 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25804 return TARGET_64BIT;
25811 /* Return true if MODE1 is accessible in a register that can hold MODE2
25812 without copying. That is, all register classes that can hold MODE2
25813 can also hold MODE1. */
25816 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25818 if (mode1 == mode2)
25821 if (ix86_tieable_integer_mode_p (mode1)
25822 && ix86_tieable_integer_mode_p (mode2))
25825 /* MODE2 being XFmode implies fp stack or general regs, which means we
25826 can tie any smaller floating point modes to it. Note that we do not
25827 tie this with TFmode. */
25828 if (mode2 == XFmode)
25829 return mode1 == SFmode || mode1 == DFmode;
25831 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25832 that we can tie it with SFmode. */
25833 if (mode2 == DFmode)
25834 return mode1 == SFmode;
25836 /* If MODE2 is only appropriate for an SSE register, then tie with
25837 any other mode acceptable to SSE registers. */
25838 if (GET_MODE_SIZE (mode2) == 16
25839 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25840 return (GET_MODE_SIZE (mode1) == 16
25841 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25843 /* If MODE2 is appropriate for an MMX register, then tie
25844 with any other mode acceptable to MMX registers. */
25845 if (GET_MODE_SIZE (mode2) == 8
25846 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25847 return (GET_MODE_SIZE (mode1) == 8
25848 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25853 /* Compute a (partial) cost for rtx X. Return true if the complete
25854 cost has been computed, and false if subexpressions should be
25855 scanned. In either case, *TOTAL contains the cost result. */
25858 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25860 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25861 enum machine_mode mode = GET_MODE (x);
25862 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25870 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25872 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25874 else if (flag_pic && SYMBOLIC_CONST (x)
25876 || (!GET_CODE (x) != LABEL_REF
25877 && (GET_CODE (x) != SYMBOL_REF
25878 || !SYMBOL_REF_LOCAL_P (x)))))
25885 if (mode == VOIDmode)
25888 switch (standard_80387_constant_p (x))
25893 default: /* Other constants */
25898 /* Start with (MEM (SYMBOL_REF)), since that's where
25899 it'll probably end up. Add a penalty for size. */
25900 *total = (COSTS_N_INSNS (1)
25901 + (flag_pic != 0 && !TARGET_64BIT)
25902 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25908 /* The zero extensions is often completely free on x86_64, so make
25909 it as cheap as possible. */
25910 if (TARGET_64BIT && mode == DImode
25911 && GET_MODE (XEXP (x, 0)) == SImode)
25913 else if (TARGET_ZERO_EXTEND_WITH_AND)
25914 *total = cost->add;
25916 *total = cost->movzx;
25920 *total = cost->movsx;
25924 if (CONST_INT_P (XEXP (x, 1))
25925 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25927 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25930 *total = cost->add;
25933 if ((value == 2 || value == 3)
25934 && cost->lea <= cost->shift_const)
25936 *total = cost->lea;
25946 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25948 if (CONST_INT_P (XEXP (x, 1)))
25950 if (INTVAL (XEXP (x, 1)) > 32)
25951 *total = cost->shift_const + COSTS_N_INSNS (2);
25953 *total = cost->shift_const * 2;
25957 if (GET_CODE (XEXP (x, 1)) == AND)
25958 *total = cost->shift_var * 2;
25960 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25965 if (CONST_INT_P (XEXP (x, 1)))
25966 *total = cost->shift_const;
25968 *total = cost->shift_var;
25973 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25975 /* ??? SSE scalar cost should be used here. */
25976 *total = cost->fmul;
25979 else if (X87_FLOAT_MODE_P (mode))
25981 *total = cost->fmul;
25984 else if (FLOAT_MODE_P (mode))
25986 /* ??? SSE vector cost should be used here. */
25987 *total = cost->fmul;
25992 rtx op0 = XEXP (x, 0);
25993 rtx op1 = XEXP (x, 1);
25995 if (CONST_INT_P (XEXP (x, 1)))
25997 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25998 for (nbits = 0; value != 0; value &= value - 1)
26002 /* This is arbitrary. */
26005 /* Compute costs correctly for widening multiplication. */
26006 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26007 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26008 == GET_MODE_SIZE (mode))
26010 int is_mulwiden = 0;
26011 enum machine_mode inner_mode = GET_MODE (op0);
26013 if (GET_CODE (op0) == GET_CODE (op1))
26014 is_mulwiden = 1, op1 = XEXP (op1, 0);
26015 else if (CONST_INT_P (op1))
26017 if (GET_CODE (op0) == SIGN_EXTEND)
26018 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26021 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26025 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26028 *total = (cost->mult_init[MODE_INDEX (mode)]
26029 + nbits * cost->mult_bit
26030 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26039 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26040 /* ??? SSE cost should be used here. */
26041 *total = cost->fdiv;
26042 else if (X87_FLOAT_MODE_P (mode))
26043 *total = cost->fdiv;
26044 else if (FLOAT_MODE_P (mode))
26045 /* ??? SSE vector cost should be used here. */
26046 *total = cost->fdiv;
26048 *total = cost->divide[MODE_INDEX (mode)];
26052 if (GET_MODE_CLASS (mode) == MODE_INT
26053 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26055 if (GET_CODE (XEXP (x, 0)) == PLUS
26056 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26057 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26058 && CONSTANT_P (XEXP (x, 1)))
26060 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26061 if (val == 2 || val == 4 || val == 8)
26063 *total = cost->lea;
26064 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26065 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26066 outer_code, speed);
26067 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26071 else if (GET_CODE (XEXP (x, 0)) == MULT
26072 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26074 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26075 if (val == 2 || val == 4 || val == 8)
26077 *total = cost->lea;
26078 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26079 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26083 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26085 *total = cost->lea;
26086 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26087 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26088 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26095 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26097 /* ??? SSE cost should be used here. */
26098 *total = cost->fadd;
26101 else if (X87_FLOAT_MODE_P (mode))
26103 *total = cost->fadd;
26106 else if (FLOAT_MODE_P (mode))
26108 /* ??? SSE vector cost should be used here. */
26109 *total = cost->fadd;
26117 if (!TARGET_64BIT && mode == DImode)
26119 *total = (cost->add * 2
26120 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26121 << (GET_MODE (XEXP (x, 0)) != DImode))
26122 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26123 << (GET_MODE (XEXP (x, 1)) != DImode)));
26129 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26131 /* ??? SSE cost should be used here. */
26132 *total = cost->fchs;
26135 else if (X87_FLOAT_MODE_P (mode))
26137 *total = cost->fchs;
26140 else if (FLOAT_MODE_P (mode))
26142 /* ??? SSE vector cost should be used here. */
26143 *total = cost->fchs;
26149 if (!TARGET_64BIT && mode == DImode)
26150 *total = cost->add * 2;
26152 *total = cost->add;
26156 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26157 && XEXP (XEXP (x, 0), 1) == const1_rtx
26158 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26159 && XEXP (x, 1) == const0_rtx)
26161 /* This kind of construct is implemented using test[bwl].
26162 Treat it as if we had an AND. */
26163 *total = (cost->add
26164 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26165 + rtx_cost (const1_rtx, outer_code, speed));
26171 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26176 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26177 /* ??? SSE cost should be used here. */
26178 *total = cost->fabs;
26179 else if (X87_FLOAT_MODE_P (mode))
26180 *total = cost->fabs;
26181 else if (FLOAT_MODE_P (mode))
26182 /* ??? SSE vector cost should be used here. */
26183 *total = cost->fabs;
26187 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26188 /* ??? SSE cost should be used here. */
26189 *total = cost->fsqrt;
26190 else if (X87_FLOAT_MODE_P (mode))
26191 *total = cost->fsqrt;
26192 else if (FLOAT_MODE_P (mode))
26193 /* ??? SSE vector cost should be used here. */
26194 *total = cost->fsqrt;
26198 if (XINT (x, 1) == UNSPEC_TP)
26209 static int current_machopic_label_num;
26211 /* Given a symbol name and its associated stub, write out the
26212 definition of the stub. */
26215 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26217 unsigned int length;
26218 char *binder_name, *symbol_name, lazy_ptr_name[32];
26219 int label = ++current_machopic_label_num;
26221 /* For 64-bit we shouldn't get here. */
26222 gcc_assert (!TARGET_64BIT);
26224 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26225 symb = (*targetm.strip_name_encoding) (symb);
26227 length = strlen (stub);
26228 binder_name = XALLOCAVEC (char, length + 32);
26229 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26231 length = strlen (symb);
26232 symbol_name = XALLOCAVEC (char, length + 32);
26233 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26235 sprintf (lazy_ptr_name, "L%d$lz", label);
26238 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26240 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26242 fprintf (file, "%s:\n", stub);
26243 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26247 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26248 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26249 fprintf (file, "\tjmp\t*%%edx\n");
26252 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26254 fprintf (file, "%s:\n", binder_name);
26258 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26259 fprintf (file, "\tpushl\t%%eax\n");
26262 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26264 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26266 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26267 fprintf (file, "%s:\n", lazy_ptr_name);
26268 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26269 fprintf (file, "\t.long %s\n", binder_name);
26273 darwin_x86_file_end (void)
26275 darwin_file_end ();
26278 #endif /* TARGET_MACHO */
26280 /* Order the registers for register allocator. */
26283 x86_order_regs_for_local_alloc (void)
26288 /* First allocate the local general purpose registers. */
26289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26290 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26291 reg_alloc_order [pos++] = i;
26293 /* Global general purpose registers. */
26294 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26295 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26296 reg_alloc_order [pos++] = i;
26298 /* x87 registers come first in case we are doing FP math
26300 if (!TARGET_SSE_MATH)
26301 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26302 reg_alloc_order [pos++] = i;
26304 /* SSE registers. */
26305 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26306 reg_alloc_order [pos++] = i;
26307 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26308 reg_alloc_order [pos++] = i;
26310 /* x87 registers. */
26311 if (TARGET_SSE_MATH)
26312 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26313 reg_alloc_order [pos++] = i;
26315 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26316 reg_alloc_order [pos++] = i;
26318 /* Initialize the rest of array as we do not allocate some registers
26320 while (pos < FIRST_PSEUDO_REGISTER)
26321 reg_alloc_order [pos++] = 0;
26324 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26325 struct attribute_spec.handler. */
26327 ix86_handle_abi_attribute (tree *node, tree name,
26328 tree args ATTRIBUTE_UNUSED,
26329 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26331 if (TREE_CODE (*node) != FUNCTION_TYPE
26332 && TREE_CODE (*node) != METHOD_TYPE
26333 && TREE_CODE (*node) != FIELD_DECL
26334 && TREE_CODE (*node) != TYPE_DECL)
26336 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26337 IDENTIFIER_POINTER (name));
26338 *no_add_attrs = true;
26343 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26344 IDENTIFIER_POINTER (name));
26345 *no_add_attrs = true;
26349 /* Can combine regparm with all attributes but fastcall. */
26350 if (is_attribute_p ("ms_abi", name))
26352 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26354 error ("ms_abi and sysv_abi attributes are not compatible");
26359 else if (is_attribute_p ("sysv_abi", name))
26361 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26363 error ("ms_abi and sysv_abi attributes are not compatible");
26372 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26373 struct attribute_spec.handler. */
26375 ix86_handle_struct_attribute (tree *node, tree name,
26376 tree args ATTRIBUTE_UNUSED,
26377 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26380 if (DECL_P (*node))
26382 if (TREE_CODE (*node) == TYPE_DECL)
26383 type = &TREE_TYPE (*node);
26388 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26389 || TREE_CODE (*type) == UNION_TYPE)))
26391 warning (OPT_Wattributes, "%qs attribute ignored",
26392 IDENTIFIER_POINTER (name));
26393 *no_add_attrs = true;
26396 else if ((is_attribute_p ("ms_struct", name)
26397 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26398 || ((is_attribute_p ("gcc_struct", name)
26399 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26401 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26402 IDENTIFIER_POINTER (name));
26403 *no_add_attrs = true;
26410 ix86_ms_bitfield_layout_p (const_tree record_type)
26412 return (TARGET_MS_BITFIELD_LAYOUT &&
26413 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26414 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26417 /* Returns an expression indicating where the this parameter is
26418 located on entry to the FUNCTION. */
26421 x86_this_parameter (tree function)
26423 tree type = TREE_TYPE (function);
26424 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26429 const int *parm_regs;
26431 if (ix86_function_type_abi (type) == MS_ABI)
26432 parm_regs = x86_64_ms_abi_int_parameter_registers;
26434 parm_regs = x86_64_int_parameter_registers;
26435 return gen_rtx_REG (DImode, parm_regs[aggr]);
26438 nregs = ix86_function_regparm (type, function);
26440 if (nregs > 0 && !stdarg_p (type))
26444 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26445 regno = aggr ? DX_REG : CX_REG;
26453 return gen_rtx_MEM (SImode,
26454 plus_constant (stack_pointer_rtx, 4));
26457 return gen_rtx_REG (SImode, regno);
26460 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26463 /* Determine whether x86_output_mi_thunk can succeed. */
26466 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26467 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26468 HOST_WIDE_INT vcall_offset, const_tree function)
26470 /* 64-bit can handle anything. */
26474 /* For 32-bit, everything's fine if we have one free register. */
26475 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26478 /* Need a free register for vcall_offset. */
26482 /* Need a free register for GOT references. */
26483 if (flag_pic && !(*targetm.binds_local_p) (function))
26486 /* Otherwise ok. */
26490 /* Output the assembler code for a thunk function. THUNK_DECL is the
26491 declaration for the thunk function itself, FUNCTION is the decl for
26492 the target function. DELTA is an immediate constant offset to be
26493 added to THIS. If VCALL_OFFSET is nonzero, the word at
26494 *(*this + vcall_offset) should be added to THIS. */
26497 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26498 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26499 HOST_WIDE_INT vcall_offset, tree function)
26502 rtx this_param = x86_this_parameter (function);
26505 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26506 pull it in now and let DELTA benefit. */
26507 if (REG_P (this_param))
26508 this_reg = this_param;
26509 else if (vcall_offset)
26511 /* Put the this parameter into %eax. */
26512 xops[0] = this_param;
26513 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26514 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26517 this_reg = NULL_RTX;
26519 /* Adjust the this parameter by a fixed constant. */
26522 xops[0] = GEN_INT (delta);
26523 xops[1] = this_reg ? this_reg : this_param;
26526 if (!x86_64_general_operand (xops[0], DImode))
26528 tmp = gen_rtx_REG (DImode, R10_REG);
26530 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26532 xops[1] = this_param;
26534 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26537 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26540 /* Adjust the this parameter by a value stored in the vtable. */
26544 tmp = gen_rtx_REG (DImode, R10_REG);
26547 int tmp_regno = CX_REG;
26548 if (lookup_attribute ("fastcall",
26549 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26550 tmp_regno = AX_REG;
26551 tmp = gen_rtx_REG (SImode, tmp_regno);
26554 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26556 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26558 /* Adjust the this parameter. */
26559 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26560 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26562 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26563 xops[0] = GEN_INT (vcall_offset);
26565 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26566 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26568 xops[1] = this_reg;
26569 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26572 /* If necessary, drop THIS back to its stack slot. */
26573 if (this_reg && this_reg != this_param)
26575 xops[0] = this_reg;
26576 xops[1] = this_param;
26577 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26580 xops[0] = XEXP (DECL_RTL (function), 0);
26583 if (!flag_pic || (*targetm.binds_local_p) (function))
26584 output_asm_insn ("jmp\t%P0", xops);
26585 /* All thunks should be in the same object as their target,
26586 and thus binds_local_p should be true. */
26587 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26588 gcc_unreachable ();
26591 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26592 tmp = gen_rtx_CONST (Pmode, tmp);
26593 tmp = gen_rtx_MEM (QImode, tmp);
26595 output_asm_insn ("jmp\t%A0", xops);
26600 if (!flag_pic || (*targetm.binds_local_p) (function))
26601 output_asm_insn ("jmp\t%P0", xops);
26606 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26607 tmp = (gen_rtx_SYMBOL_REF
26609 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26610 tmp = gen_rtx_MEM (QImode, tmp);
26612 output_asm_insn ("jmp\t%0", xops);
26615 #endif /* TARGET_MACHO */
26617 tmp = gen_rtx_REG (SImode, CX_REG);
26618 output_set_got (tmp, NULL_RTX);
26621 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26622 output_asm_insn ("jmp\t{*}%1", xops);
26628 x86_file_start (void)
26630 default_file_start ();
26632 darwin_file_start ();
26634 if (X86_FILE_START_VERSION_DIRECTIVE)
26635 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26636 if (X86_FILE_START_FLTUSED)
26637 fputs ("\t.global\t__fltused\n", asm_out_file);
26638 if (ix86_asm_dialect == ASM_INTEL)
26639 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26643 x86_field_alignment (tree field, int computed)
26645 enum machine_mode mode;
26646 tree type = TREE_TYPE (field);
26648 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26650 mode = TYPE_MODE (strip_array_types (type));
26651 if (mode == DFmode || mode == DCmode
26652 || GET_MODE_CLASS (mode) == MODE_INT
26653 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26654 return MIN (32, computed);
26658 /* Output assembler code to FILE to increment profiler label # LABELNO
26659 for profiling a function entry. */
26661 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26665 #ifndef NO_PROFILE_COUNTERS
26666 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26669 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26670 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26672 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26676 #ifndef NO_PROFILE_COUNTERS
26677 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26678 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26680 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26684 #ifndef NO_PROFILE_COUNTERS
26685 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26686 PROFILE_COUNT_REGISTER);
26688 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26692 /* We don't have exact information about the insn sizes, but we may assume
26693 quite safely that we are informed about all 1 byte insns and memory
26694 address sizes. This is enough to eliminate unnecessary padding in
26698 min_insn_size (rtx insn)
26702 if (!INSN_P (insn) || !active_insn_p (insn))
26705 /* Discard alignments we've emit and jump instructions. */
26706 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26707 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26710 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26711 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26714 /* Important case - calls are always 5 bytes.
26715 It is common to have many calls in the row. */
26717 && symbolic_reference_mentioned_p (PATTERN (insn))
26718 && !SIBLING_CALL_P (insn))
26720 if (get_attr_length (insn) <= 1)
26723 /* For normal instructions we may rely on the sizes of addresses
26724 and the presence of symbol to require 4 bytes of encoding.
26725 This is not the case for jumps where references are PC relative. */
26726 if (!JUMP_P (insn))
26728 l = get_attr_length_address (insn);
26729 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26738 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26742 ix86_avoid_jump_misspredicts (void)
26744 rtx insn, start = get_insns ();
26745 int nbytes = 0, njumps = 0;
26748 /* Look for all minimal intervals of instructions containing 4 jumps.
26749 The intervals are bounded by START and INSN. NBYTES is the total
26750 size of instructions in the interval including INSN and not including
26751 START. When the NBYTES is smaller than 16 bytes, it is possible
26752 that the end of START and INSN ends up in the same 16byte page.
26754 The smallest offset in the page INSN can start is the case where START
26755 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26756 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26758 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26761 nbytes += min_insn_size (insn);
26763 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26764 INSN_UID (insn), min_insn_size (insn));
26766 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26767 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26775 start = NEXT_INSN (start);
26776 if ((JUMP_P (start)
26777 && GET_CODE (PATTERN (start)) != ADDR_VEC
26778 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26780 njumps--, isjump = 1;
26783 nbytes -= min_insn_size (start);
26785 gcc_assert (njumps >= 0);
26787 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26788 INSN_UID (start), INSN_UID (insn), nbytes);
26790 if (njumps == 3 && isjump && nbytes < 16)
26792 int padsize = 15 - nbytes + min_insn_size (insn);
26795 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26796 INSN_UID (insn), padsize);
26797 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26802 /* AMD Athlon works faster
26803 when RET is not destination of conditional jump or directly preceded
26804 by other jump instruction. We avoid the penalty by inserting NOP just
26805 before the RET instructions in such cases. */
26807 ix86_pad_returns (void)
26812 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26814 basic_block bb = e->src;
26815 rtx ret = BB_END (bb);
26817 bool replace = false;
26819 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26820 || optimize_bb_for_size_p (bb))
26822 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26823 if (active_insn_p (prev) || LABEL_P (prev))
26825 if (prev && LABEL_P (prev))
26830 FOR_EACH_EDGE (e, ei, bb->preds)
26831 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26832 && !(e->flags & EDGE_FALLTHRU))
26837 prev = prev_active_insn (ret);
26839 && ((JUMP_P (prev) && any_condjump_p (prev))
26842 /* Empty functions get branch mispredict even when the jump destination
26843 is not visible to us. */
26844 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26849 emit_insn_before (gen_return_internal_long (), ret);
26855 /* Implement machine specific optimizations. We implement padding of returns
26856 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26860 if (TARGET_PAD_RETURNS && optimize
26861 && optimize_function_for_speed_p (cfun))
26862 ix86_pad_returns ();
26863 if (TARGET_FOUR_JUMP_LIMIT && optimize
26864 && optimize_function_for_speed_p (cfun))
26865 ix86_avoid_jump_misspredicts ();
26868 /* Return nonzero when QImode register that must be represented via REX prefix
26871 x86_extended_QIreg_mentioned_p (rtx insn)
26874 extract_insn_cached (insn);
26875 for (i = 0; i < recog_data.n_operands; i++)
26876 if (REG_P (recog_data.operand[i])
26877 && REGNO (recog_data.operand[i]) > BX_REG)
26882 /* Return nonzero when P points to register encoded via REX prefix.
26883 Called via for_each_rtx. */
26885 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26887 unsigned int regno;
26890 regno = REGNO (*p);
26891 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26894 /* Return true when INSN mentions register that must be encoded using REX
26897 x86_extended_reg_mentioned_p (rtx insn)
26899 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26900 extended_reg_mentioned_1, NULL);
26903 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26904 optabs would emit if we didn't have TFmode patterns. */
26907 x86_emit_floatuns (rtx operands[2])
26909 rtx neglab, donelab, i0, i1, f0, in, out;
26910 enum machine_mode mode, inmode;
26912 inmode = GET_MODE (operands[1]);
26913 gcc_assert (inmode == SImode || inmode == DImode);
26916 in = force_reg (inmode, operands[1]);
26917 mode = GET_MODE (out);
26918 neglab = gen_label_rtx ();
26919 donelab = gen_label_rtx ();
26920 f0 = gen_reg_rtx (mode);
26922 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26924 expand_float (out, in, 0);
26926 emit_jump_insn (gen_jump (donelab));
26929 emit_label (neglab);
26931 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26933 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26935 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26937 expand_float (f0, i0, 0);
26939 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26941 emit_label (donelab);
26944 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26945 with all elements equal to VAR. Return true if successful. */
26948 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26949 rtx target, rtx val)
26951 enum machine_mode hmode, smode, wsmode, wvmode;
26966 val = force_reg (GET_MODE_INNER (mode), val);
26967 x = gen_rtx_VEC_DUPLICATE (mode, val);
26968 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26974 if (TARGET_SSE || TARGET_3DNOW_A)
26976 val = gen_lowpart (SImode, val);
26977 x = gen_rtx_TRUNCATE (HImode, val);
26978 x = gen_rtx_VEC_DUPLICATE (mode, x);
26979 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27001 /* Extend HImode to SImode using a paradoxical SUBREG. */
27002 tmp1 = gen_reg_rtx (SImode);
27003 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27004 /* Insert the SImode value as low element of V4SImode vector. */
27005 tmp2 = gen_reg_rtx (V4SImode);
27006 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27007 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27008 CONST0_RTX (V4SImode),
27010 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27011 /* Cast the V4SImode vector back to a V8HImode vector. */
27012 tmp1 = gen_reg_rtx (V8HImode);
27013 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27014 /* Duplicate the low short through the whole low SImode word. */
27015 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27016 /* Cast the V8HImode vector back to a V4SImode vector. */
27017 tmp2 = gen_reg_rtx (V4SImode);
27018 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27019 /* Replicate the low element of the V4SImode vector. */
27020 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27021 /* Cast the V2SImode back to V8HImode, and store in target. */
27022 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27033 /* Extend QImode to SImode using a paradoxical SUBREG. */
27034 tmp1 = gen_reg_rtx (SImode);
27035 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27036 /* Insert the SImode value as low element of V4SImode vector. */
27037 tmp2 = gen_reg_rtx (V4SImode);
27038 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27039 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27040 CONST0_RTX (V4SImode),
27042 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27043 /* Cast the V4SImode vector back to a V16QImode vector. */
27044 tmp1 = gen_reg_rtx (V16QImode);
27045 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27046 /* Duplicate the low byte through the whole low SImode word. */
27047 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27048 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27049 /* Cast the V16QImode vector back to a V4SImode vector. */
27050 tmp2 = gen_reg_rtx (V4SImode);
27051 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27052 /* Replicate the low element of the V4SImode vector. */
27053 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27054 /* Cast the V2SImode back to V16QImode, and store in target. */
27055 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27063 /* Replicate the value once into the next wider mode and recurse. */
27064 val = convert_modes (wsmode, smode, val, true);
27065 x = expand_simple_binop (wsmode, ASHIFT, val,
27066 GEN_INT (GET_MODE_BITSIZE (smode)),
27067 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27068 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27070 x = gen_reg_rtx (wvmode);
27071 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27072 gcc_unreachable ();
27073 emit_move_insn (target, gen_lowpart (mode, x));
27096 rtx tmp = gen_reg_rtx (hmode);
27097 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27098 emit_insn (gen_rtx_SET (VOIDmode, target,
27099 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27108 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27109 whose ONE_VAR element is VAR, and other elements are zero. Return true
27113 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27114 rtx target, rtx var, int one_var)
27116 enum machine_mode vsimode;
27119 bool use_vector_set = false;
27124 /* For SSE4.1, we normally use vector set. But if the second
27125 element is zero and inter-unit moves are OK, we use movq
27127 use_vector_set = (TARGET_64BIT
27129 && !(TARGET_INTER_UNIT_MOVES
27135 use_vector_set = TARGET_SSE4_1;
27138 use_vector_set = TARGET_SSE2;
27141 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27148 use_vector_set = TARGET_AVX;
27151 /* Use ix86_expand_vector_set in 64bit mode only. */
27152 use_vector_set = TARGET_AVX && TARGET_64BIT;
27158 if (use_vector_set)
27160 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27161 var = force_reg (GET_MODE_INNER (mode), var);
27162 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27178 var = force_reg (GET_MODE_INNER (mode), var);
27179 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27180 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27185 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27186 new_target = gen_reg_rtx (mode);
27188 new_target = target;
27189 var = force_reg (GET_MODE_INNER (mode), var);
27190 x = gen_rtx_VEC_DUPLICATE (mode, var);
27191 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27192 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27195 /* We need to shuffle the value to the correct position, so
27196 create a new pseudo to store the intermediate result. */
27198 /* With SSE2, we can use the integer shuffle insns. */
27199 if (mode != V4SFmode && TARGET_SSE2)
27201 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27203 GEN_INT (one_var == 1 ? 0 : 1),
27204 GEN_INT (one_var == 2 ? 0 : 1),
27205 GEN_INT (one_var == 3 ? 0 : 1)));
27206 if (target != new_target)
27207 emit_move_insn (target, new_target);
27211 /* Otherwise convert the intermediate result to V4SFmode and
27212 use the SSE1 shuffle instructions. */
27213 if (mode != V4SFmode)
27215 tmp = gen_reg_rtx (V4SFmode);
27216 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27221 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27223 GEN_INT (one_var == 1 ? 0 : 1),
27224 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27225 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27227 if (mode != V4SFmode)
27228 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27229 else if (tmp != target)
27230 emit_move_insn (target, tmp);
27232 else if (target != new_target)
27233 emit_move_insn (target, new_target);
27238 vsimode = V4SImode;
27244 vsimode = V2SImode;
27250 /* Zero extend the variable element to SImode and recurse. */
27251 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27253 x = gen_reg_rtx (vsimode);
27254 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27256 gcc_unreachable ();
27258 emit_move_insn (target, gen_lowpart (mode, x));
27266 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27267 consisting of the values in VALS. It is known that all elements
27268 except ONE_VAR are constants. Return true if successful. */
27271 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27272 rtx target, rtx vals, int one_var)
27274 rtx var = XVECEXP (vals, 0, one_var);
27275 enum machine_mode wmode;
27278 const_vec = copy_rtx (vals);
27279 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27280 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27288 /* For the two element vectors, it's just as easy to use
27289 the general case. */
27293 /* Use ix86_expand_vector_set in 64bit mode only. */
27316 /* There's no way to set one QImode entry easily. Combine
27317 the variable value with its adjacent constant value, and
27318 promote to an HImode set. */
27319 x = XVECEXP (vals, 0, one_var ^ 1);
27322 var = convert_modes (HImode, QImode, var, true);
27323 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27324 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27325 x = GEN_INT (INTVAL (x) & 0xff);
27329 var = convert_modes (HImode, QImode, var, true);
27330 x = gen_int_mode (INTVAL (x) << 8, HImode);
27332 if (x != const0_rtx)
27333 var = expand_simple_binop (HImode, IOR, var, x, var,
27334 1, OPTAB_LIB_WIDEN);
27336 x = gen_reg_rtx (wmode);
27337 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27338 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27340 emit_move_insn (target, gen_lowpart (mode, x));
27347 emit_move_insn (target, const_vec);
27348 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27352 /* A subroutine of ix86_expand_vector_init_general. Use vector
27353 concatenate to handle the most general case: all values variable,
27354 and none identical. */
27357 ix86_expand_vector_init_concat (enum machine_mode mode,
27358 rtx target, rtx *ops, int n)
27360 enum machine_mode cmode, hmode = VOIDmode;
27361 rtx first[8], second[4];
27401 gcc_unreachable ();
27404 if (!register_operand (ops[1], cmode))
27405 ops[1] = force_reg (cmode, ops[1]);
27406 if (!register_operand (ops[0], cmode))
27407 ops[0] = force_reg (cmode, ops[0]);
27408 emit_insn (gen_rtx_SET (VOIDmode, target,
27409 gen_rtx_VEC_CONCAT (mode, ops[0],
27429 gcc_unreachable ();
27445 gcc_unreachable ();
27450 /* FIXME: We process inputs backward to help RA. PR 36222. */
27453 for (; i > 0; i -= 2, j--)
27455 first[j] = gen_reg_rtx (cmode);
27456 v = gen_rtvec (2, ops[i - 1], ops[i]);
27457 ix86_expand_vector_init (false, first[j],
27458 gen_rtx_PARALLEL (cmode, v));
27464 gcc_assert (hmode != VOIDmode);
27465 for (i = j = 0; i < n; i += 2, j++)
27467 second[j] = gen_reg_rtx (hmode);
27468 ix86_expand_vector_init_concat (hmode, second [j],
27472 ix86_expand_vector_init_concat (mode, target, second, n);
27475 ix86_expand_vector_init_concat (mode, target, first, n);
27479 gcc_unreachable ();
27483 /* A subroutine of ix86_expand_vector_init_general. Use vector
27484 interleave to handle the most general case: all values variable,
27485 and none identical. */
27488 ix86_expand_vector_init_interleave (enum machine_mode mode,
27489 rtx target, rtx *ops, int n)
27491 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27494 rtx (*gen_load_even) (rtx, rtx, rtx);
27495 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27496 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27501 gen_load_even = gen_vec_setv8hi;
27502 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27503 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27504 inner_mode = HImode;
27505 first_imode = V4SImode;
27506 second_imode = V2DImode;
27507 third_imode = VOIDmode;
27510 gen_load_even = gen_vec_setv16qi;
27511 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27512 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27513 inner_mode = QImode;
27514 first_imode = V8HImode;
27515 second_imode = V4SImode;
27516 third_imode = V2DImode;
27519 gcc_unreachable ();
27522 for (i = 0; i < n; i++)
27524 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27525 op0 = gen_reg_rtx (SImode);
27526 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27528 /* Insert the SImode value as low element of V4SImode vector. */
27529 op1 = gen_reg_rtx (V4SImode);
27530 op0 = gen_rtx_VEC_MERGE (V4SImode,
27531 gen_rtx_VEC_DUPLICATE (V4SImode,
27533 CONST0_RTX (V4SImode),
27535 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27537 /* Cast the V4SImode vector back to a vector in orignal mode. */
27538 op0 = gen_reg_rtx (mode);
27539 emit_move_insn (op0, gen_lowpart (mode, op1));
27541 /* Load even elements into the second positon. */
27542 emit_insn ((*gen_load_even) (op0,
27543 force_reg (inner_mode,
27547 /* Cast vector to FIRST_IMODE vector. */
27548 ops[i] = gen_reg_rtx (first_imode);
27549 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27552 /* Interleave low FIRST_IMODE vectors. */
27553 for (i = j = 0; i < n; i += 2, j++)
27555 op0 = gen_reg_rtx (first_imode);
27556 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27558 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27559 ops[j] = gen_reg_rtx (second_imode);
27560 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27563 /* Interleave low SECOND_IMODE vectors. */
27564 switch (second_imode)
27567 for (i = j = 0; i < n / 2; i += 2, j++)
27569 op0 = gen_reg_rtx (second_imode);
27570 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27573 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27575 ops[j] = gen_reg_rtx (third_imode);
27576 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27578 second_imode = V2DImode;
27579 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27583 op0 = gen_reg_rtx (second_imode);
27584 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27587 /* Cast the SECOND_IMODE vector back to a vector on original
27589 emit_insn (gen_rtx_SET (VOIDmode, target,
27590 gen_lowpart (mode, op0)));
27594 gcc_unreachable ();
27598 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27599 all values variable, and none identical. */
27602 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27603 rtx target, rtx vals)
27605 rtx ops[32], op0, op1;
27606 enum machine_mode half_mode = VOIDmode;
27613 if (!mmx_ok && !TARGET_SSE)
27625 n = GET_MODE_NUNITS (mode);
27626 for (i = 0; i < n; i++)
27627 ops[i] = XVECEXP (vals, 0, i);
27628 ix86_expand_vector_init_concat (mode, target, ops, n);
27632 half_mode = V16QImode;
27636 half_mode = V8HImode;
27640 n = GET_MODE_NUNITS (mode);
27641 for (i = 0; i < n; i++)
27642 ops[i] = XVECEXP (vals, 0, i);
27643 op0 = gen_reg_rtx (half_mode);
27644 op1 = gen_reg_rtx (half_mode);
27645 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27647 ix86_expand_vector_init_interleave (half_mode, op1,
27648 &ops [n >> 1], n >> 2);
27649 emit_insn (gen_rtx_SET (VOIDmode, target,
27650 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27654 if (!TARGET_SSE4_1)
27662 /* Don't use ix86_expand_vector_init_interleave if we can't
27663 move from GPR to SSE register directly. */
27664 if (!TARGET_INTER_UNIT_MOVES)
27667 n = GET_MODE_NUNITS (mode);
27668 for (i = 0; i < n; i++)
27669 ops[i] = XVECEXP (vals, 0, i);
27670 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27678 gcc_unreachable ();
27682 int i, j, n_elts, n_words, n_elt_per_word;
27683 enum machine_mode inner_mode;
27684 rtx words[4], shift;
27686 inner_mode = GET_MODE_INNER (mode);
27687 n_elts = GET_MODE_NUNITS (mode);
27688 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27689 n_elt_per_word = n_elts / n_words;
27690 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27692 for (i = 0; i < n_words; ++i)
27694 rtx word = NULL_RTX;
27696 for (j = 0; j < n_elt_per_word; ++j)
27698 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27699 elt = convert_modes (word_mode, inner_mode, elt, true);
27705 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27706 word, 1, OPTAB_LIB_WIDEN);
27707 word = expand_simple_binop (word_mode, IOR, word, elt,
27708 word, 1, OPTAB_LIB_WIDEN);
27716 emit_move_insn (target, gen_lowpart (mode, words[0]));
27717 else if (n_words == 2)
27719 rtx tmp = gen_reg_rtx (mode);
27720 emit_clobber (tmp);
27721 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27722 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27723 emit_move_insn (target, tmp);
27725 else if (n_words == 4)
27727 rtx tmp = gen_reg_rtx (V4SImode);
27728 gcc_assert (word_mode == SImode);
27729 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27730 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27731 emit_move_insn (target, gen_lowpart (mode, tmp));
27734 gcc_unreachable ();
27738 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27739 instructions unless MMX_OK is true. */
27742 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27744 enum machine_mode mode = GET_MODE (target);
27745 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27746 int n_elts = GET_MODE_NUNITS (mode);
27747 int n_var = 0, one_var = -1;
27748 bool all_same = true, all_const_zero = true;
27752 for (i = 0; i < n_elts; ++i)
27754 x = XVECEXP (vals, 0, i);
27755 if (!(CONST_INT_P (x)
27756 || GET_CODE (x) == CONST_DOUBLE
27757 || GET_CODE (x) == CONST_FIXED))
27758 n_var++, one_var = i;
27759 else if (x != CONST0_RTX (inner_mode))
27760 all_const_zero = false;
27761 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27765 /* Constants are best loaded from the constant pool. */
27768 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27772 /* If all values are identical, broadcast the value. */
27774 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27775 XVECEXP (vals, 0, 0)))
27778 /* Values where only one field is non-constant are best loaded from
27779 the pool and overwritten via move later. */
27783 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27784 XVECEXP (vals, 0, one_var),
27788 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27792 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27796 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27798 enum machine_mode mode = GET_MODE (target);
27799 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27800 enum machine_mode half_mode;
27801 bool use_vec_merge = false;
27803 static rtx (*gen_extract[6][2]) (rtx, rtx)
27805 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27806 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27807 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27808 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27809 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27810 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27812 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27814 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27815 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27816 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27817 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27818 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27819 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27829 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27830 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27832 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27834 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27835 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27841 use_vec_merge = TARGET_SSE4_1;
27849 /* For the two element vectors, we implement a VEC_CONCAT with
27850 the extraction of the other element. */
27852 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27853 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27856 op0 = val, op1 = tmp;
27858 op0 = tmp, op1 = val;
27860 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27861 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27866 use_vec_merge = TARGET_SSE4_1;
27873 use_vec_merge = true;
27877 /* tmp = target = A B C D */
27878 tmp = copy_to_reg (target);
27879 /* target = A A B B */
27880 emit_insn (gen_sse_unpcklps (target, target, target));
27881 /* target = X A B B */
27882 ix86_expand_vector_set (false, target, val, 0);
27883 /* target = A X C D */
27884 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27885 GEN_INT (1), GEN_INT (0),
27886 GEN_INT (2+4), GEN_INT (3+4)));
27890 /* tmp = target = A B C D */
27891 tmp = copy_to_reg (target);
27892 /* tmp = X B C D */
27893 ix86_expand_vector_set (false, tmp, val, 0);
27894 /* target = A B X D */
27895 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27896 GEN_INT (0), GEN_INT (1),
27897 GEN_INT (0+4), GEN_INT (3+4)));
27901 /* tmp = target = A B C D */
27902 tmp = copy_to_reg (target);
27903 /* tmp = X B C D */
27904 ix86_expand_vector_set (false, tmp, val, 0);
27905 /* target = A B X D */
27906 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27907 GEN_INT (0), GEN_INT (1),
27908 GEN_INT (2+4), GEN_INT (0+4)));
27912 gcc_unreachable ();
27917 use_vec_merge = TARGET_SSE4_1;
27921 /* Element 0 handled by vec_merge below. */
27924 use_vec_merge = true;
27930 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27931 store into element 0, then shuffle them back. */
27935 order[0] = GEN_INT (elt);
27936 order[1] = const1_rtx;
27937 order[2] = const2_rtx;
27938 order[3] = GEN_INT (3);
27939 order[elt] = const0_rtx;
27941 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27942 order[1], order[2], order[3]));
27944 ix86_expand_vector_set (false, target, val, 0);
27946 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27947 order[1], order[2], order[3]));
27951 /* For SSE1, we have to reuse the V4SF code. */
27952 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27953 gen_lowpart (SFmode, val), elt);
27958 use_vec_merge = TARGET_SSE2;
27961 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27965 use_vec_merge = TARGET_SSE4_1;
27972 half_mode = V16QImode;
27978 half_mode = V8HImode;
27984 half_mode = V4SImode;
27990 half_mode = V2DImode;
27996 half_mode = V4SFmode;
28002 half_mode = V2DFmode;
28008 /* Compute offset. */
28012 gcc_assert (i <= 1);
28014 /* Extract the half. */
28015 tmp = gen_reg_rtx (half_mode);
28016 emit_insn ((*gen_extract[j][i]) (tmp, target));
28018 /* Put val in tmp at elt. */
28019 ix86_expand_vector_set (false, tmp, val, elt);
28022 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28031 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28032 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28033 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28037 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28039 emit_move_insn (mem, target);
28041 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28042 emit_move_insn (tmp, val);
28044 emit_move_insn (target, mem);
28049 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28051 enum machine_mode mode = GET_MODE (vec);
28052 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28053 bool use_vec_extr = false;
28066 use_vec_extr = true;
28070 use_vec_extr = TARGET_SSE4_1;
28082 tmp = gen_reg_rtx (mode);
28083 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28084 GEN_INT (elt), GEN_INT (elt),
28085 GEN_INT (elt+4), GEN_INT (elt+4)));
28089 tmp = gen_reg_rtx (mode);
28090 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28094 gcc_unreachable ();
28097 use_vec_extr = true;
28102 use_vec_extr = TARGET_SSE4_1;
28116 tmp = gen_reg_rtx (mode);
28117 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28118 GEN_INT (elt), GEN_INT (elt),
28119 GEN_INT (elt), GEN_INT (elt)));
28123 tmp = gen_reg_rtx (mode);
28124 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28128 gcc_unreachable ();
28131 use_vec_extr = true;
28136 /* For SSE1, we have to reuse the V4SF code. */
28137 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28138 gen_lowpart (V4SFmode, vec), elt);
28144 use_vec_extr = TARGET_SSE2;
28147 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28151 use_vec_extr = TARGET_SSE4_1;
28155 /* ??? Could extract the appropriate HImode element and shift. */
28162 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28163 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28165 /* Let the rtl optimizers know about the zero extension performed. */
28166 if (inner_mode == QImode || inner_mode == HImode)
28168 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28169 target = gen_lowpart (SImode, target);
28172 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28176 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28178 emit_move_insn (mem, vec);
28180 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28181 emit_move_insn (target, tmp);
28185 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28186 pattern to reduce; DEST is the destination; IN is the input vector. */
28189 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28191 rtx tmp1, tmp2, tmp3;
28193 tmp1 = gen_reg_rtx (V4SFmode);
28194 tmp2 = gen_reg_rtx (V4SFmode);
28195 tmp3 = gen_reg_rtx (V4SFmode);
28197 emit_insn (gen_sse_movhlps (tmp1, in, in));
28198 emit_insn (fn (tmp2, tmp1, in));
28200 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28201 GEN_INT (1), GEN_INT (1),
28202 GEN_INT (1+4), GEN_INT (1+4)));
28203 emit_insn (fn (dest, tmp2, tmp3));
28206 /* Target hook for scalar_mode_supported_p. */
28208 ix86_scalar_mode_supported_p (enum machine_mode mode)
28210 if (DECIMAL_FLOAT_MODE_P (mode))
28212 else if (mode == TFmode)
28215 return default_scalar_mode_supported_p (mode);
28218 /* Implements target hook vector_mode_supported_p. */
28220 ix86_vector_mode_supported_p (enum machine_mode mode)
28222 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28224 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28226 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28228 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28230 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28235 /* Target hook for c_mode_for_suffix. */
28236 static enum machine_mode
28237 ix86_c_mode_for_suffix (char suffix)
28247 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28249 We do this in the new i386 backend to maintain source compatibility
28250 with the old cc0-based compiler. */
28253 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28254 tree inputs ATTRIBUTE_UNUSED,
28257 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28259 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28264 /* Implements target vector targetm.asm.encode_section_info. This
28265 is not used by netware. */
28267 static void ATTRIBUTE_UNUSED
28268 ix86_encode_section_info (tree decl, rtx rtl, int first)
28270 default_encode_section_info (decl, rtl, first);
28272 if (TREE_CODE (decl) == VAR_DECL
28273 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28274 && ix86_in_large_data_p (decl))
28275 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28278 /* Worker function for REVERSE_CONDITION. */
28281 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28283 return (mode != CCFPmode && mode != CCFPUmode
28284 ? reverse_condition (code)
28285 : reverse_condition_maybe_unordered (code));
28288 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28292 output_387_reg_move (rtx insn, rtx *operands)
28294 if (REG_P (operands[0]))
28296 if (REG_P (operands[1])
28297 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28299 if (REGNO (operands[0]) == FIRST_STACK_REG)
28300 return output_387_ffreep (operands, 0);
28301 return "fstp\t%y0";
28303 if (STACK_TOP_P (operands[0]))
28304 return "fld%z1\t%y1";
28307 else if (MEM_P (operands[0]))
28309 gcc_assert (REG_P (operands[1]));
28310 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28311 return "fstp%z0\t%y0";
28314 /* There is no non-popping store to memory for XFmode.
28315 So if we need one, follow the store with a load. */
28316 if (GET_MODE (operands[0]) == XFmode)
28317 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28319 return "fst%z0\t%y0";
28326 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28327 FP status register is set. */
28330 ix86_emit_fp_unordered_jump (rtx label)
28332 rtx reg = gen_reg_rtx (HImode);
28335 emit_insn (gen_x86_fnstsw_1 (reg));
28337 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28339 emit_insn (gen_x86_sahf_1 (reg));
28341 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28342 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28346 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28348 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28349 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28352 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28353 gen_rtx_LABEL_REF (VOIDmode, label),
28355 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28357 emit_jump_insn (temp);
28358 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28361 /* Output code to perform a log1p XFmode calculation. */
28363 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28365 rtx label1 = gen_label_rtx ();
28366 rtx label2 = gen_label_rtx ();
28368 rtx tmp = gen_reg_rtx (XFmode);
28369 rtx tmp2 = gen_reg_rtx (XFmode);
28371 emit_insn (gen_absxf2 (tmp, op1));
28372 emit_insn (gen_cmpxf (tmp,
28373 CONST_DOUBLE_FROM_REAL_VALUE (
28374 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28376 emit_jump_insn (gen_bge (label1));
28378 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28379 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28380 emit_jump (label2);
28382 emit_label (label1);
28383 emit_move_insn (tmp, CONST1_RTX (XFmode));
28384 emit_insn (gen_addxf3 (tmp, op1, tmp));
28385 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28386 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28388 emit_label (label2);
28391 /* Output code to perform a Newton-Rhapson approximation of a single precision
28392 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28394 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28396 rtx x0, x1, e0, e1, two;
28398 x0 = gen_reg_rtx (mode);
28399 e0 = gen_reg_rtx (mode);
28400 e1 = gen_reg_rtx (mode);
28401 x1 = gen_reg_rtx (mode);
28403 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28405 if (VECTOR_MODE_P (mode))
28406 two = ix86_build_const_vector (SFmode, true, two);
28408 two = force_reg (mode, two);
28410 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28412 /* x0 = rcp(b) estimate */
28413 emit_insn (gen_rtx_SET (VOIDmode, x0,
28414 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28417 emit_insn (gen_rtx_SET (VOIDmode, e0,
28418 gen_rtx_MULT (mode, x0, b)));
28420 emit_insn (gen_rtx_SET (VOIDmode, e1,
28421 gen_rtx_MINUS (mode, two, e0)));
28423 emit_insn (gen_rtx_SET (VOIDmode, x1,
28424 gen_rtx_MULT (mode, x0, e1)));
28426 emit_insn (gen_rtx_SET (VOIDmode, res,
28427 gen_rtx_MULT (mode, a, x1)));
28430 /* Output code to perform a Newton-Rhapson approximation of a
28431 single precision floating point [reciprocal] square root. */
28433 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28436 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28439 x0 = gen_reg_rtx (mode);
28440 e0 = gen_reg_rtx (mode);
28441 e1 = gen_reg_rtx (mode);
28442 e2 = gen_reg_rtx (mode);
28443 e3 = gen_reg_rtx (mode);
28445 real_from_integer (&r, VOIDmode, -3, -1, 0);
28446 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28448 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28449 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28451 if (VECTOR_MODE_P (mode))
28453 mthree = ix86_build_const_vector (SFmode, true, mthree);
28454 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28457 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28458 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28460 /* x0 = rsqrt(a) estimate */
28461 emit_insn (gen_rtx_SET (VOIDmode, x0,
28462 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28465 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28470 zero = gen_reg_rtx (mode);
28471 mask = gen_reg_rtx (mode);
28473 zero = force_reg (mode, CONST0_RTX(mode));
28474 emit_insn (gen_rtx_SET (VOIDmode, mask,
28475 gen_rtx_NE (mode, zero, a)));
28477 emit_insn (gen_rtx_SET (VOIDmode, x0,
28478 gen_rtx_AND (mode, x0, mask)));
28482 emit_insn (gen_rtx_SET (VOIDmode, e0,
28483 gen_rtx_MULT (mode, x0, a)));
28485 emit_insn (gen_rtx_SET (VOIDmode, e1,
28486 gen_rtx_MULT (mode, e0, x0)));
28489 mthree = force_reg (mode, mthree);
28490 emit_insn (gen_rtx_SET (VOIDmode, e2,
28491 gen_rtx_PLUS (mode, e1, mthree)));
28493 mhalf = force_reg (mode, mhalf);
28495 /* e3 = -.5 * x0 */
28496 emit_insn (gen_rtx_SET (VOIDmode, e3,
28497 gen_rtx_MULT (mode, x0, mhalf)));
28499 /* e3 = -.5 * e0 */
28500 emit_insn (gen_rtx_SET (VOIDmode, e3,
28501 gen_rtx_MULT (mode, e0, mhalf)));
28502 /* ret = e2 * e3 */
28503 emit_insn (gen_rtx_SET (VOIDmode, res,
28504 gen_rtx_MULT (mode, e2, e3)));
28507 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28509 static void ATTRIBUTE_UNUSED
28510 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28513 /* With Binutils 2.15, the "@unwind" marker must be specified on
28514 every occurrence of the ".eh_frame" section, not just the first
28517 && strcmp (name, ".eh_frame") == 0)
28519 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28520 flags & SECTION_WRITE ? "aw" : "a");
28523 default_elf_asm_named_section (name, flags, decl);
28526 /* Return the mangling of TYPE if it is an extended fundamental type. */
28528 static const char *
28529 ix86_mangle_type (const_tree type)
28531 type = TYPE_MAIN_VARIANT (type);
28533 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28534 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28537 switch (TYPE_MODE (type))
28540 /* __float128 is "g". */
28543 /* "long double" or __float80 is "e". */
28550 /* For 32-bit code we can save PIC register setup by using
28551 __stack_chk_fail_local hidden function instead of calling
28552 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28553 register, so it is better to call __stack_chk_fail directly. */
28556 ix86_stack_protect_fail (void)
28558 return TARGET_64BIT
28559 ? default_external_stack_protect_fail ()
28560 : default_hidden_stack_protect_fail ();
28563 /* Select a format to encode pointers in exception handling data. CODE
28564 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28565 true if the symbol may be affected by dynamic relocations.
28567 ??? All x86 object file formats are capable of representing this.
28568 After all, the relocation needed is the same as for the call insn.
28569 Whether or not a particular assembler allows us to enter such, I
28570 guess we'll have to see. */
28572 asm_preferred_eh_data_format (int code, int global)
28576 int type = DW_EH_PE_sdata8;
28578 || ix86_cmodel == CM_SMALL_PIC
28579 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28580 type = DW_EH_PE_sdata4;
28581 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28583 if (ix86_cmodel == CM_SMALL
28584 || (ix86_cmodel == CM_MEDIUM && code))
28585 return DW_EH_PE_udata4;
28586 return DW_EH_PE_absptr;
28589 /* Expand copysign from SIGN to the positive value ABS_VALUE
28590 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28593 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28595 enum machine_mode mode = GET_MODE (sign);
28596 rtx sgn = gen_reg_rtx (mode);
28597 if (mask == NULL_RTX)
28599 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28600 if (!VECTOR_MODE_P (mode))
28602 /* We need to generate a scalar mode mask in this case. */
28603 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28604 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28605 mask = gen_reg_rtx (mode);
28606 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28610 mask = gen_rtx_NOT (mode, mask);
28611 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28612 gen_rtx_AND (mode, mask, sign)));
28613 emit_insn (gen_rtx_SET (VOIDmode, result,
28614 gen_rtx_IOR (mode, abs_value, sgn)));
28617 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28618 mask for masking out the sign-bit is stored in *SMASK, if that is
28621 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28623 enum machine_mode mode = GET_MODE (op0);
28626 xa = gen_reg_rtx (mode);
28627 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28628 if (!VECTOR_MODE_P (mode))
28630 /* We need to generate a scalar mode mask in this case. */
28631 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28632 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28633 mask = gen_reg_rtx (mode);
28634 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28636 emit_insn (gen_rtx_SET (VOIDmode, xa,
28637 gen_rtx_AND (mode, op0, mask)));
28645 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28646 swapping the operands if SWAP_OPERANDS is true. The expanded
28647 code is a forward jump to a newly created label in case the
28648 comparison is true. The generated label rtx is returned. */
28650 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28651 bool swap_operands)
28662 label = gen_label_rtx ();
28663 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28664 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28665 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28666 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28667 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28668 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28669 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28670 JUMP_LABEL (tmp) = label;
28675 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28676 using comparison code CODE. Operands are swapped for the comparison if
28677 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28679 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28680 bool swap_operands)
28682 enum machine_mode mode = GET_MODE (op0);
28683 rtx mask = gen_reg_rtx (mode);
28692 if (mode == DFmode)
28693 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28694 gen_rtx_fmt_ee (code, mode, op0, op1)));
28696 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28697 gen_rtx_fmt_ee (code, mode, op0, op1)));
28702 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28703 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28705 ix86_gen_TWO52 (enum machine_mode mode)
28707 REAL_VALUE_TYPE TWO52r;
28710 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28711 TWO52 = const_double_from_real_value (TWO52r, mode);
28712 TWO52 = force_reg (mode, TWO52);
28717 /* Expand SSE sequence for computing lround from OP1 storing
28720 ix86_expand_lround (rtx op0, rtx op1)
28722 /* C code for the stuff we're doing below:
28723 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28726 enum machine_mode mode = GET_MODE (op1);
28727 const struct real_format *fmt;
28728 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28731 /* load nextafter (0.5, 0.0) */
28732 fmt = REAL_MODE_FORMAT (mode);
28733 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28734 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28736 /* adj = copysign (0.5, op1) */
28737 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28738 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28740 /* adj = op1 + adj */
28741 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28743 /* op0 = (imode)adj */
28744 expand_fix (op0, adj, 0);
28747 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28750 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28752 /* C code for the stuff we're doing below (for do_floor):
28754 xi -= (double)xi > op1 ? 1 : 0;
28757 enum machine_mode fmode = GET_MODE (op1);
28758 enum machine_mode imode = GET_MODE (op0);
28759 rtx ireg, freg, label, tmp;
28761 /* reg = (long)op1 */
28762 ireg = gen_reg_rtx (imode);
28763 expand_fix (ireg, op1, 0);
28765 /* freg = (double)reg */
28766 freg = gen_reg_rtx (fmode);
28767 expand_float (freg, ireg, 0);
28769 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28770 label = ix86_expand_sse_compare_and_jump (UNLE,
28771 freg, op1, !do_floor);
28772 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28773 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28774 emit_move_insn (ireg, tmp);
28776 emit_label (label);
28777 LABEL_NUSES (label) = 1;
28779 emit_move_insn (op0, ireg);
28782 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28783 result in OPERAND0. */
28785 ix86_expand_rint (rtx operand0, rtx operand1)
28787 /* C code for the stuff we're doing below:
28788 xa = fabs (operand1);
28789 if (!isless (xa, 2**52))
28791 xa = xa + 2**52 - 2**52;
28792 return copysign (xa, operand1);
28794 enum machine_mode mode = GET_MODE (operand0);
28795 rtx res, xa, label, TWO52, mask;
28797 res = gen_reg_rtx (mode);
28798 emit_move_insn (res, operand1);
28800 /* xa = abs (operand1) */
28801 xa = ix86_expand_sse_fabs (res, &mask);
28803 /* if (!isless (xa, TWO52)) goto label; */
28804 TWO52 = ix86_gen_TWO52 (mode);
28805 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28807 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28808 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28810 ix86_sse_copysign_to_positive (res, xa, res, mask);
28812 emit_label (label);
28813 LABEL_NUSES (label) = 1;
28815 emit_move_insn (operand0, res);
28818 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28821 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28823 /* C code for the stuff we expand below.
28824 double xa = fabs (x), x2;
28825 if (!isless (xa, TWO52))
28827 xa = xa + TWO52 - TWO52;
28828 x2 = copysign (xa, x);
28837 enum machine_mode mode = GET_MODE (operand0);
28838 rtx xa, TWO52, tmp, label, one, res, mask;
28840 TWO52 = ix86_gen_TWO52 (mode);
28842 /* Temporary for holding the result, initialized to the input
28843 operand to ease control flow. */
28844 res = gen_reg_rtx (mode);
28845 emit_move_insn (res, operand1);
28847 /* xa = abs (operand1) */
28848 xa = ix86_expand_sse_fabs (res, &mask);
28850 /* if (!isless (xa, TWO52)) goto label; */
28851 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28853 /* xa = xa + TWO52 - TWO52; */
28854 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28855 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28857 /* xa = copysign (xa, operand1) */
28858 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28860 /* generate 1.0 or -1.0 */
28861 one = force_reg (mode,
28862 const_double_from_real_value (do_floor
28863 ? dconst1 : dconstm1, mode));
28865 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28866 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28867 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28868 gen_rtx_AND (mode, one, tmp)));
28869 /* We always need to subtract here to preserve signed zero. */
28870 tmp = expand_simple_binop (mode, MINUS,
28871 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28872 emit_move_insn (res, tmp);
28874 emit_label (label);
28875 LABEL_NUSES (label) = 1;
28877 emit_move_insn (operand0, res);
28880 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28883 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28885 /* C code for the stuff we expand below.
28886 double xa = fabs (x), x2;
28887 if (!isless (xa, TWO52))
28889 x2 = (double)(long)x;
28896 if (HONOR_SIGNED_ZEROS (mode))
28897 return copysign (x2, x);
28900 enum machine_mode mode = GET_MODE (operand0);
28901 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28903 TWO52 = ix86_gen_TWO52 (mode);
28905 /* Temporary for holding the result, initialized to the input
28906 operand to ease control flow. */
28907 res = gen_reg_rtx (mode);
28908 emit_move_insn (res, operand1);
28910 /* xa = abs (operand1) */
28911 xa = ix86_expand_sse_fabs (res, &mask);
28913 /* if (!isless (xa, TWO52)) goto label; */
28914 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28916 /* xa = (double)(long)x */
28917 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28918 expand_fix (xi, res, 0);
28919 expand_float (xa, xi, 0);
28922 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28924 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28925 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28926 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28927 gen_rtx_AND (mode, one, tmp)));
28928 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28929 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28930 emit_move_insn (res, tmp);
28932 if (HONOR_SIGNED_ZEROS (mode))
28933 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28935 emit_label (label);
28936 LABEL_NUSES (label) = 1;
28938 emit_move_insn (operand0, res);
28941 /* Expand SSE sequence for computing round from OPERAND1 storing
28942 into OPERAND0. Sequence that works without relying on DImode truncation
28943 via cvttsd2siq that is only available on 64bit targets. */
28945 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28947 /* C code for the stuff we expand below.
28948 double xa = fabs (x), xa2, x2;
28949 if (!isless (xa, TWO52))
28951 Using the absolute value and copying back sign makes
28952 -0.0 -> -0.0 correct.
28953 xa2 = xa + TWO52 - TWO52;
28958 else if (dxa > 0.5)
28960 x2 = copysign (xa2, x);
28963 enum machine_mode mode = GET_MODE (operand0);
28964 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28966 TWO52 = ix86_gen_TWO52 (mode);
28968 /* Temporary for holding the result, initialized to the input
28969 operand to ease control flow. */
28970 res = gen_reg_rtx (mode);
28971 emit_move_insn (res, operand1);
28973 /* xa = abs (operand1) */
28974 xa = ix86_expand_sse_fabs (res, &mask);
28976 /* if (!isless (xa, TWO52)) goto label; */
28977 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28979 /* xa2 = xa + TWO52 - TWO52; */
28980 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28981 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28983 /* dxa = xa2 - xa; */
28984 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28986 /* generate 0.5, 1.0 and -0.5 */
28987 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28988 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28989 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28993 tmp = gen_reg_rtx (mode);
28994 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28995 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28996 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28997 gen_rtx_AND (mode, one, tmp)));
28998 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28999 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29000 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29001 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29002 gen_rtx_AND (mode, one, tmp)));
29003 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29005 /* res = copysign (xa2, operand1) */
29006 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29008 emit_label (label);
29009 LABEL_NUSES (label) = 1;
29011 emit_move_insn (operand0, res);
29014 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29017 ix86_expand_trunc (rtx operand0, rtx operand1)
29019 /* C code for SSE variant we expand below.
29020 double xa = fabs (x), x2;
29021 if (!isless (xa, TWO52))
29023 x2 = (double)(long)x;
29024 if (HONOR_SIGNED_ZEROS (mode))
29025 return copysign (x2, x);
29028 enum machine_mode mode = GET_MODE (operand0);
29029 rtx xa, xi, TWO52, label, res, mask;
29031 TWO52 = ix86_gen_TWO52 (mode);
29033 /* Temporary for holding the result, initialized to the input
29034 operand to ease control flow. */
29035 res = gen_reg_rtx (mode);
29036 emit_move_insn (res, operand1);
29038 /* xa = abs (operand1) */
29039 xa = ix86_expand_sse_fabs (res, &mask);
29041 /* if (!isless (xa, TWO52)) goto label; */
29042 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29044 /* x = (double)(long)x */
29045 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29046 expand_fix (xi, res, 0);
29047 expand_float (res, xi, 0);
29049 if (HONOR_SIGNED_ZEROS (mode))
29050 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29052 emit_label (label);
29053 LABEL_NUSES (label) = 1;
29055 emit_move_insn (operand0, res);
29058 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29061 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29063 enum machine_mode mode = GET_MODE (operand0);
29064 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29066 /* C code for SSE variant we expand below.
29067 double xa = fabs (x), x2;
29068 if (!isless (xa, TWO52))
29070 xa2 = xa + TWO52 - TWO52;
29074 x2 = copysign (xa2, x);
29078 TWO52 = ix86_gen_TWO52 (mode);
29080 /* Temporary for holding the result, initialized to the input
29081 operand to ease control flow. */
29082 res = gen_reg_rtx (mode);
29083 emit_move_insn (res, operand1);
29085 /* xa = abs (operand1) */
29086 xa = ix86_expand_sse_fabs (res, &smask);
29088 /* if (!isless (xa, TWO52)) goto label; */
29089 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29091 /* res = xa + TWO52 - TWO52; */
29092 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29093 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29094 emit_move_insn (res, tmp);
29097 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29099 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29100 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29101 emit_insn (gen_rtx_SET (VOIDmode, mask,
29102 gen_rtx_AND (mode, mask, one)));
29103 tmp = expand_simple_binop (mode, MINUS,
29104 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29105 emit_move_insn (res, tmp);
29107 /* res = copysign (res, operand1) */
29108 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29110 emit_label (label);
29111 LABEL_NUSES (label) = 1;
29113 emit_move_insn (operand0, res);
29116 /* Expand SSE sequence for computing round from OPERAND1 storing
29119 ix86_expand_round (rtx operand0, rtx operand1)
29121 /* C code for the stuff we're doing below:
29122 double xa = fabs (x);
29123 if (!isless (xa, TWO52))
29125 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29126 return copysign (xa, x);
29128 enum machine_mode mode = GET_MODE (operand0);
29129 rtx res, TWO52, xa, label, xi, half, mask;
29130 const struct real_format *fmt;
29131 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29133 /* Temporary for holding the result, initialized to the input
29134 operand to ease control flow. */
29135 res = gen_reg_rtx (mode);
29136 emit_move_insn (res, operand1);
29138 TWO52 = ix86_gen_TWO52 (mode);
29139 xa = ix86_expand_sse_fabs (res, &mask);
29140 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29142 /* load nextafter (0.5, 0.0) */
29143 fmt = REAL_MODE_FORMAT (mode);
29144 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29145 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29147 /* xa = xa + 0.5 */
29148 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29149 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29151 /* xa = (double)(int64_t)xa */
29152 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29153 expand_fix (xi, xa, 0);
29154 expand_float (xa, xi, 0);
29156 /* res = copysign (xa, operand1) */
29157 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29159 emit_label (label);
29160 LABEL_NUSES (label) = 1;
29162 emit_move_insn (operand0, res);
29166 /* Validate whether a SSE5 instruction is valid or not.
29167 OPERANDS is the array of operands.
29168 NUM is the number of operands.
29169 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29170 NUM_MEMORY is the maximum number of memory operands to accept.
29171 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29174 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29175 bool uses_oc0, int num_memory, bool commutative)
29181 /* Count the number of memory arguments */
29184 for (i = 0; i < num; i++)
29186 enum machine_mode mode = GET_MODE (operands[i]);
29187 if (register_operand (operands[i], mode))
29190 else if (memory_operand (operands[i], mode))
29192 mem_mask |= (1 << i);
29198 rtx pattern = PATTERN (insn);
29200 /* allow 0 for pcmov */
29201 if (GET_CODE (pattern) != SET
29202 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29204 || operands[i] != CONST0_RTX (mode))
29209 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29210 a memory operation. */
29211 if (num_memory < 0)
29213 num_memory = -num_memory;
29214 if ((mem_mask & (1 << (num-1))) != 0)
29216 mem_mask &= ~(1 << (num-1));
29221 /* If there were no memory operations, allow the insn */
29225 /* Do not allow the destination register to be a memory operand. */
29226 else if (mem_mask & (1 << 0))
29229 /* If there are too many memory operations, disallow the instruction. While
29230 the hardware only allows 1 memory reference, before register allocation
29231 for some insns, we allow two memory operations sometimes in order to allow
29232 code like the following to be optimized:
29234 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29236 or similar cases that are vectorized into using the fmaddss
29238 else if (mem_count > num_memory)
29241 /* Don't allow more than one memory operation if not optimizing. */
29242 else if (mem_count > 1 && !optimize)
29245 else if (num == 4 && mem_count == 1)
29247 /* formats (destination is the first argument), example fmaddss:
29248 xmm1, xmm1, xmm2, xmm3/mem
29249 xmm1, xmm1, xmm2/mem, xmm3
29250 xmm1, xmm2, xmm3/mem, xmm1
29251 xmm1, xmm2/mem, xmm3, xmm1 */
29253 return ((mem_mask == (1 << 1))
29254 || (mem_mask == (1 << 2))
29255 || (mem_mask == (1 << 3)));
29257 /* format, example pmacsdd:
29258 xmm1, xmm2, xmm3/mem, xmm1 */
29260 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29262 return (mem_mask == (1 << 2));
29265 else if (num == 4 && num_memory == 2)
29267 /* If there are two memory operations, we can load one of the memory ops
29268 into the destination register. This is for optimizing the
29269 multiply/add ops, which the combiner has optimized both the multiply
29270 and the add insns to have a memory operation. We have to be careful
29271 that the destination doesn't overlap with the inputs. */
29272 rtx op0 = operands[0];
29274 if (reg_mentioned_p (op0, operands[1])
29275 || reg_mentioned_p (op0, operands[2])
29276 || reg_mentioned_p (op0, operands[3]))
29279 /* formats (destination is the first argument), example fmaddss:
29280 xmm1, xmm1, xmm2, xmm3/mem
29281 xmm1, xmm1, xmm2/mem, xmm3
29282 xmm1, xmm2, xmm3/mem, xmm1
29283 xmm1, xmm2/mem, xmm3, xmm1
29285 For the oc0 case, we will load either operands[1] or operands[3] into
29286 operands[0], so any combination of 2 memory operands is ok. */
29290 /* format, example pmacsdd:
29291 xmm1, xmm2, xmm3/mem, xmm1
29293 For the integer multiply/add instructions be more restrictive and
29294 require operands[2] and operands[3] to be the memory operands. */
29296 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29298 return (mem_mask == ((1 << 2) | (1 << 3)));
29301 else if (num == 3 && num_memory == 1)
29303 /* formats, example protb:
29304 xmm1, xmm2, xmm3/mem
29305 xmm1, xmm2/mem, xmm3 */
29307 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29309 /* format, example comeq:
29310 xmm1, xmm2, xmm3/mem */
29312 return (mem_mask == (1 << 2));
29316 gcc_unreachable ();
29322 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29323 hardware will allow by using the destination register to load one of the
29324 memory operations. Presently this is used by the multiply/add routines to
29325 allow 2 memory references. */
29328 ix86_expand_sse5_multiple_memory (rtx operands[],
29330 enum machine_mode mode)
29332 rtx op0 = operands[0];
29334 || memory_operand (op0, mode)
29335 || reg_mentioned_p (op0, operands[1])
29336 || reg_mentioned_p (op0, operands[2])
29337 || reg_mentioned_p (op0, operands[3]))
29338 gcc_unreachable ();
29340 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29341 the destination register. */
29342 if (memory_operand (operands[1], mode))
29344 emit_move_insn (op0, operands[1]);
29347 else if (memory_operand (operands[3], mode))
29349 emit_move_insn (op0, operands[3]);
29353 gcc_unreachable ();
29359 /* Table of valid machine attributes. */
29360 static const struct attribute_spec ix86_attribute_table[] =
29362 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29363 /* Stdcall attribute says callee is responsible for popping arguments
29364 if they are not variable. */
29365 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29366 /* Fastcall attribute says callee is responsible for popping arguments
29367 if they are not variable. */
29368 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29369 /* Cdecl attribute says the callee is a normal C declaration */
29370 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29371 /* Regparm attribute specifies how many integer arguments are to be
29372 passed in registers. */
29373 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29374 /* Sseregparm attribute says we are using x86_64 calling conventions
29375 for FP arguments. */
29376 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29377 /* force_align_arg_pointer says this function realigns the stack at entry. */
29378 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29379 false, true, true, ix86_handle_cconv_attribute },
29380 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29381 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29382 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29383 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29385 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29386 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29387 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29388 SUBTARGET_ATTRIBUTE_TABLE,
29390 /* ms_abi and sysv_abi calling convention function attributes. */
29391 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29392 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29394 { NULL, 0, 0, false, false, false, NULL }
29397 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29399 x86_builtin_vectorization_cost (bool runtime_test)
29401 /* If the branch of the runtime test is taken - i.e. - the vectorized
29402 version is skipped - this incurs a misprediction cost (because the
29403 vectorized version is expected to be the fall-through). So we subtract
29404 the latency of a mispredicted branch from the costs that are incured
29405 when the vectorized version is executed.
29407 TODO: The values in individual target tables have to be tuned or new
29408 fields may be needed. For eg. on K8, the default branch path is the
29409 not-taken path. If the taken path is predicted correctly, the minimum
29410 penalty of going down the taken-path is 1 cycle. If the taken-path is
29411 not predicted correctly, then the minimum penalty is 10 cycles. */
29415 return (-(ix86_cost->cond_taken_branch_cost));
29421 /* This function returns the calling abi specific va_list type node.
29422 It returns the FNDECL specific va_list type. */
29425 ix86_fn_abi_va_list (tree fndecl)
29430 return va_list_type_node;
29431 gcc_assert (fndecl != NULL_TREE);
29432 abi = ix86_function_abi ((const_tree) fndecl);
29435 return ms_va_list_type_node;
29437 return sysv_va_list_type_node;
29440 /* Returns the canonical va_list type specified by TYPE. If there
29441 is no valid TYPE provided, it return NULL_TREE. */
29444 ix86_canonical_va_list_type (tree type)
29448 /* Resolve references and pointers to va_list type. */
29449 if (INDIRECT_REF_P (type))
29450 type = TREE_TYPE (type);
29451 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29452 type = TREE_TYPE (type);
29456 wtype = va_list_type_node;
29457 gcc_assert (wtype != NULL_TREE);
29459 if (TREE_CODE (wtype) == ARRAY_TYPE)
29461 /* If va_list is an array type, the argument may have decayed
29462 to a pointer type, e.g. by being passed to another function.
29463 In that case, unwrap both types so that we can compare the
29464 underlying records. */
29465 if (TREE_CODE (htype) == ARRAY_TYPE
29466 || POINTER_TYPE_P (htype))
29468 wtype = TREE_TYPE (wtype);
29469 htype = TREE_TYPE (htype);
29472 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29473 return va_list_type_node;
29474 wtype = sysv_va_list_type_node;
29475 gcc_assert (wtype != NULL_TREE);
29477 if (TREE_CODE (wtype) == ARRAY_TYPE)
29479 /* If va_list is an array type, the argument may have decayed
29480 to a pointer type, e.g. by being passed to another function.
29481 In that case, unwrap both types so that we can compare the
29482 underlying records. */
29483 if (TREE_CODE (htype) == ARRAY_TYPE
29484 || POINTER_TYPE_P (htype))
29486 wtype = TREE_TYPE (wtype);
29487 htype = TREE_TYPE (htype);
29490 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29491 return sysv_va_list_type_node;
29492 wtype = ms_va_list_type_node;
29493 gcc_assert (wtype != NULL_TREE);
29495 if (TREE_CODE (wtype) == ARRAY_TYPE)
29497 /* If va_list is an array type, the argument may have decayed
29498 to a pointer type, e.g. by being passed to another function.
29499 In that case, unwrap both types so that we can compare the
29500 underlying records. */
29501 if (TREE_CODE (htype) == ARRAY_TYPE
29502 || POINTER_TYPE_P (htype))
29504 wtype = TREE_TYPE (wtype);
29505 htype = TREE_TYPE (htype);
29508 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29509 return ms_va_list_type_node;
29512 return std_canonical_va_list_type (type);
29515 /* Iterate through the target-specific builtin types for va_list.
29516 IDX denotes the iterator, *PTREE is set to the result type of
29517 the va_list builtin, and *PNAME to its internal type.
29518 Returns zero if there is no element for this index, otherwise
29519 IDX should be increased upon the next call.
29520 Note, do not iterate a base builtin's name like __builtin_va_list.
29521 Used from c_common_nodes_and_builtins. */
29524 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29530 *ptree = ms_va_list_type_node;
29531 *pname = "__builtin_ms_va_list";
29534 *ptree = sysv_va_list_type_node;
29535 *pname = "__builtin_sysv_va_list";
29543 /* Initialize the GCC target structure. */
29544 #undef TARGET_RETURN_IN_MEMORY
29545 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29547 #undef TARGET_ATTRIBUTE_TABLE
29548 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29549 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29550 # undef TARGET_MERGE_DECL_ATTRIBUTES
29551 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29554 #undef TARGET_COMP_TYPE_ATTRIBUTES
29555 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29557 #undef TARGET_INIT_BUILTINS
29558 #define TARGET_INIT_BUILTINS ix86_init_builtins
29559 #undef TARGET_EXPAND_BUILTIN
29560 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29562 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29563 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29564 ix86_builtin_vectorized_function
29566 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29567 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29569 #undef TARGET_BUILTIN_RECIPROCAL
29570 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29572 #undef TARGET_ASM_FUNCTION_EPILOGUE
29573 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29575 #undef TARGET_ENCODE_SECTION_INFO
29576 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29577 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29579 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29582 #undef TARGET_ASM_OPEN_PAREN
29583 #define TARGET_ASM_OPEN_PAREN ""
29584 #undef TARGET_ASM_CLOSE_PAREN
29585 #define TARGET_ASM_CLOSE_PAREN ""
29587 #undef TARGET_ASM_ALIGNED_HI_OP
29588 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29589 #undef TARGET_ASM_ALIGNED_SI_OP
29590 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29592 #undef TARGET_ASM_ALIGNED_DI_OP
29593 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29596 #undef TARGET_ASM_UNALIGNED_HI_OP
29597 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29598 #undef TARGET_ASM_UNALIGNED_SI_OP
29599 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29600 #undef TARGET_ASM_UNALIGNED_DI_OP
29601 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29603 #undef TARGET_SCHED_ADJUST_COST
29604 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29605 #undef TARGET_SCHED_ISSUE_RATE
29606 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29607 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29608 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29609 ia32_multipass_dfa_lookahead
29611 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29612 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29615 #undef TARGET_HAVE_TLS
29616 #define TARGET_HAVE_TLS true
29618 #undef TARGET_CANNOT_FORCE_CONST_MEM
29619 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29620 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29621 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29623 #undef TARGET_DELEGITIMIZE_ADDRESS
29624 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29626 #undef TARGET_MS_BITFIELD_LAYOUT_P
29627 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29630 #undef TARGET_BINDS_LOCAL_P
29631 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29633 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29634 #undef TARGET_BINDS_LOCAL_P
29635 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29638 #undef TARGET_ASM_OUTPUT_MI_THUNK
29639 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29640 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29641 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29643 #undef TARGET_ASM_FILE_START
29644 #define TARGET_ASM_FILE_START x86_file_start
29646 #undef TARGET_DEFAULT_TARGET_FLAGS
29647 #define TARGET_DEFAULT_TARGET_FLAGS \
29649 | TARGET_SUBTARGET_DEFAULT \
29650 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29652 #undef TARGET_HANDLE_OPTION
29653 #define TARGET_HANDLE_OPTION ix86_handle_option
29655 #undef TARGET_RTX_COSTS
29656 #define TARGET_RTX_COSTS ix86_rtx_costs
29657 #undef TARGET_ADDRESS_COST
29658 #define TARGET_ADDRESS_COST ix86_address_cost
29660 #undef TARGET_FIXED_CONDITION_CODE_REGS
29661 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29662 #undef TARGET_CC_MODES_COMPATIBLE
29663 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29665 #undef TARGET_MACHINE_DEPENDENT_REORG
29666 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29668 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29669 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29671 #undef TARGET_BUILD_BUILTIN_VA_LIST
29672 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29674 #undef TARGET_FN_ABI_VA_LIST
29675 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29677 #undef TARGET_CANONICAL_VA_LIST_TYPE
29678 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29680 #undef TARGET_EXPAND_BUILTIN_VA_START
29681 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29683 #undef TARGET_MD_ASM_CLOBBERS
29684 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29686 #undef TARGET_PROMOTE_PROTOTYPES
29687 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29688 #undef TARGET_STRUCT_VALUE_RTX
29689 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29690 #undef TARGET_SETUP_INCOMING_VARARGS
29691 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29692 #undef TARGET_MUST_PASS_IN_STACK
29693 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29694 #undef TARGET_PASS_BY_REFERENCE
29695 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29696 #undef TARGET_INTERNAL_ARG_POINTER
29697 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29698 #undef TARGET_UPDATE_STACK_BOUNDARY
29699 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29700 #undef TARGET_GET_DRAP_RTX
29701 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29702 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29703 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29704 #undef TARGET_STRICT_ARGUMENT_NAMING
29705 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29707 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29708 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29710 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29711 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29713 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29714 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29716 #undef TARGET_C_MODE_FOR_SUFFIX
29717 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29720 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29721 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29724 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29725 #undef TARGET_INSERT_ATTRIBUTES
29726 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29729 #undef TARGET_MANGLE_TYPE
29730 #define TARGET_MANGLE_TYPE ix86_mangle_type
29732 #undef TARGET_STACK_PROTECT_FAIL
29733 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29735 #undef TARGET_FUNCTION_VALUE
29736 #define TARGET_FUNCTION_VALUE ix86_function_value
29738 #undef TARGET_SECONDARY_RELOAD
29739 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29741 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29742 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29744 #undef TARGET_SET_CURRENT_FUNCTION
29745 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29747 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29748 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29750 #undef TARGET_OPTION_SAVE
29751 #define TARGET_OPTION_SAVE ix86_function_specific_save
29753 #undef TARGET_OPTION_RESTORE
29754 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29756 #undef TARGET_OPTION_PRINT
29757 #define TARGET_OPTION_PRINT ix86_function_specific_print
29759 #undef TARGET_OPTION_CAN_INLINE_P
29760 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29762 #undef TARGET_EXPAND_TO_RTL_HOOK
29763 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29765 struct gcc_target targetm = TARGET_INITIALIZER;
29767 #include "gt-i386.h"
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