1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #include "tm-constrs.h"
56 static int x86_builtin_vectorization_cost (bool);
58 #ifndef CHECK_STACK_LIMIT
59 #define CHECK_STACK_LIMIT (-1)
62 /* Return index of given mode in mult and division cost tables. */
63 #define MODE_INDEX(mode) \
64 ((mode) == QImode ? 0 \
65 : (mode) == HImode ? 1 \
66 : (mode) == SImode ? 2 \
67 : (mode) == DImode ? 3 \
70 /* Processor costs (relative to an add) */
71 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
72 #define COSTS_N_BYTES(N) ((N) * 2)
74 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
77 struct processor_costs size_cost = { /* costs for tuning for size */
78 COSTS_N_BYTES (2), /* cost of an add instruction */
79 COSTS_N_BYTES (3), /* cost of a lea instruction */
80 COSTS_N_BYTES (2), /* variable shift costs */
81 COSTS_N_BYTES (3), /* constant shift costs */
82 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
83 COSTS_N_BYTES (3), /* HI */
84 COSTS_N_BYTES (3), /* SI */
85 COSTS_N_BYTES (3), /* DI */
86 COSTS_N_BYTES (5)}, /* other */
87 0, /* cost of multiply per each bit set */
88 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
89 COSTS_N_BYTES (3), /* HI */
90 COSTS_N_BYTES (3), /* SI */
91 COSTS_N_BYTES (3), /* DI */
92 COSTS_N_BYTES (5)}, /* other */
93 COSTS_N_BYTES (3), /* cost of movsx */
94 COSTS_N_BYTES (3), /* cost of movzx */
97 2, /* cost for loading QImode using movzbl */
98 {2, 2, 2}, /* cost of loading integer registers
99 in QImode, HImode and SImode.
100 Relative to reg-reg move (2). */
101 {2, 2, 2}, /* cost of storing integer registers */
102 2, /* cost of reg,reg fld/fst */
103 {2, 2, 2}, /* cost of loading fp registers
104 in SFmode, DFmode and XFmode */
105 {2, 2, 2}, /* cost of storing fp registers
106 in SFmode, DFmode and XFmode */
107 3, /* cost of moving MMX register */
108 {3, 3}, /* cost of loading MMX registers
109 in SImode and DImode */
110 {3, 3}, /* cost of storing MMX registers
111 in SImode and DImode */
112 3, /* cost of moving SSE register */
113 {3, 3, 3}, /* cost of loading SSE registers
114 in SImode, DImode and TImode */
115 {3, 3, 3}, /* cost of storing SSE registers
116 in SImode, DImode and TImode */
117 3, /* MMX or SSE register to integer */
118 0, /* size of l1 cache */
119 0, /* size of l2 cache */
120 0, /* size of prefetch block */
121 0, /* number of parallel prefetches */
123 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
124 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
125 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
126 COSTS_N_BYTES (2), /* cost of FABS instruction. */
127 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
128 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
129 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
130 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 1, /* scalar_stmt_cost. */
134 1, /* scalar load_cost. */
135 1, /* scalar_store_cost. */
136 1, /* vec_stmt_cost. */
137 1, /* vec_to_scalar_cost. */
138 1, /* scalar_to_vec_cost. */
139 1, /* vec_align_load_cost. */
140 1, /* vec_unalign_load_cost. */
141 1, /* vec_store_cost. */
142 1, /* cond_taken_branch_cost. */
143 1, /* cond_not_taken_branch_cost. */
146 /* Processor costs (relative to an add) */
148 struct processor_costs i386_cost = { /* 386 specific costs */
149 COSTS_N_INSNS (1), /* cost of an add instruction */
150 COSTS_N_INSNS (1), /* cost of a lea instruction */
151 COSTS_N_INSNS (3), /* variable shift costs */
152 COSTS_N_INSNS (2), /* constant shift costs */
153 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
154 COSTS_N_INSNS (6), /* HI */
155 COSTS_N_INSNS (6), /* SI */
156 COSTS_N_INSNS (6), /* DI */
157 COSTS_N_INSNS (6)}, /* other */
158 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
159 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
160 COSTS_N_INSNS (23), /* HI */
161 COSTS_N_INSNS (23), /* SI */
162 COSTS_N_INSNS (23), /* DI */
163 COSTS_N_INSNS (23)}, /* other */
164 COSTS_N_INSNS (3), /* cost of movsx */
165 COSTS_N_INSNS (2), /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of storing fp registers
177 in SFmode, DFmode and XFmode */
178 2, /* cost of moving MMX register */
179 {4, 8}, /* cost of loading MMX registers
180 in SImode and DImode */
181 {4, 8}, /* cost of storing MMX registers
182 in SImode and DImode */
183 2, /* cost of moving SSE register */
184 {4, 8, 16}, /* cost of loading SSE registers
185 in SImode, DImode and TImode */
186 {4, 8, 16}, /* cost of storing SSE registers
187 in SImode, DImode and TImode */
188 3, /* MMX or SSE register to integer */
189 0, /* size of l1 cache */
190 0, /* size of l2 cache */
191 0, /* size of prefetch block */
192 0, /* number of parallel prefetches */
194 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
195 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
196 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
197 COSTS_N_INSNS (22), /* cost of FABS instruction. */
198 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
199 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
200 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
201 DUMMY_STRINGOP_ALGS},
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 1, /* scalar_stmt_cost. */
205 1, /* scalar load_cost. */
206 1, /* scalar_store_cost. */
207 1, /* vec_stmt_cost. */
208 1, /* vec_to_scalar_cost. */
209 1, /* scalar_to_vec_cost. */
210 1, /* vec_align_load_cost. */
211 2, /* vec_unalign_load_cost. */
212 1, /* vec_store_cost. */
213 3, /* cond_taken_branch_cost. */
214 1, /* cond_not_taken_branch_cost. */
218 struct processor_costs i486_cost = { /* 486 specific costs */
219 COSTS_N_INSNS (1), /* cost of an add instruction */
220 COSTS_N_INSNS (1), /* cost of a lea instruction */
221 COSTS_N_INSNS (3), /* variable shift costs */
222 COSTS_N_INSNS (2), /* constant shift costs */
223 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
224 COSTS_N_INSNS (12), /* HI */
225 COSTS_N_INSNS (12), /* SI */
226 COSTS_N_INSNS (12), /* DI */
227 COSTS_N_INSNS (12)}, /* other */
228 1, /* cost of multiply per each bit set */
229 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
230 COSTS_N_INSNS (40), /* HI */
231 COSTS_N_INSNS (40), /* SI */
232 COSTS_N_INSNS (40), /* DI */
233 COSTS_N_INSNS (40)}, /* other */
234 COSTS_N_INSNS (3), /* cost of movsx */
235 COSTS_N_INSNS (2), /* cost of movzx */
236 15, /* "large" insn */
238 4, /* cost for loading QImode using movzbl */
239 {2, 4, 2}, /* cost of loading integer registers
240 in QImode, HImode and SImode.
241 Relative to reg-reg move (2). */
242 {2, 4, 2}, /* cost of storing integer registers */
243 2, /* cost of reg,reg fld/fst */
244 {8, 8, 8}, /* cost of loading fp registers
245 in SFmode, DFmode and XFmode */
246 {8, 8, 8}, /* cost of storing fp registers
247 in SFmode, DFmode and XFmode */
248 2, /* cost of moving MMX register */
249 {4, 8}, /* cost of loading MMX registers
250 in SImode and DImode */
251 {4, 8}, /* cost of storing MMX registers
252 in SImode and DImode */
253 2, /* cost of moving SSE register */
254 {4, 8, 16}, /* cost of loading SSE registers
255 in SImode, DImode and TImode */
256 {4, 8, 16}, /* cost of storing SSE registers
257 in SImode, DImode and TImode */
258 3, /* MMX or SSE register to integer */
259 4, /* size of l1 cache. 486 has 8kB cache
260 shared for code and data, so 4kB is
261 not really precise. */
262 4, /* size of l2 cache */
263 0, /* size of prefetch block */
264 0, /* number of parallel prefetches */
266 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
267 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
268 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
269 COSTS_N_INSNS (3), /* cost of FABS instruction. */
270 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
271 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
272 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
273 DUMMY_STRINGOP_ALGS},
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 1, /* scalar_stmt_cost. */
277 1, /* scalar load_cost. */
278 1, /* scalar_store_cost. */
279 1, /* vec_stmt_cost. */
280 1, /* vec_to_scalar_cost. */
281 1, /* scalar_to_vec_cost. */
282 1, /* vec_align_load_cost. */
283 2, /* vec_unalign_load_cost. */
284 1, /* vec_store_cost. */
285 3, /* cond_taken_branch_cost. */
286 1, /* cond_not_taken_branch_cost. */
290 struct processor_costs pentium_cost = {
291 COSTS_N_INSNS (1), /* cost of an add instruction */
292 COSTS_N_INSNS (1), /* cost of a lea instruction */
293 COSTS_N_INSNS (4), /* variable shift costs */
294 COSTS_N_INSNS (1), /* constant shift costs */
295 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
296 COSTS_N_INSNS (11), /* HI */
297 COSTS_N_INSNS (11), /* SI */
298 COSTS_N_INSNS (11), /* DI */
299 COSTS_N_INSNS (11)}, /* other */
300 0, /* cost of multiply per each bit set */
301 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
302 COSTS_N_INSNS (25), /* HI */
303 COSTS_N_INSNS (25), /* SI */
304 COSTS_N_INSNS (25), /* DI */
305 COSTS_N_INSNS (25)}, /* other */
306 COSTS_N_INSNS (3), /* cost of movsx */
307 COSTS_N_INSNS (2), /* cost of movzx */
308 8, /* "large" insn */
310 6, /* cost for loading QImode using movzbl */
311 {2, 4, 2}, /* cost of loading integer registers
312 in QImode, HImode and SImode.
313 Relative to reg-reg move (2). */
314 {2, 4, 2}, /* cost of storing integer registers */
315 2, /* cost of reg,reg fld/fst */
316 {2, 2, 6}, /* cost of loading fp registers
317 in SFmode, DFmode and XFmode */
318 {4, 4, 6}, /* cost of storing fp registers
319 in SFmode, DFmode and XFmode */
320 8, /* cost of moving MMX register */
321 {8, 8}, /* cost of loading MMX registers
322 in SImode and DImode */
323 {8, 8}, /* cost of storing MMX registers
324 in SImode and DImode */
325 2, /* cost of moving SSE register */
326 {4, 8, 16}, /* cost of loading SSE registers
327 in SImode, DImode and TImode */
328 {4, 8, 16}, /* cost of storing SSE registers
329 in SImode, DImode and TImode */
330 3, /* MMX or SSE register to integer */
331 8, /* size of l1 cache. */
332 8, /* size of l2 cache */
333 0, /* size of prefetch block */
334 0, /* number of parallel prefetches */
336 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
337 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
338 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
339 COSTS_N_INSNS (1), /* cost of FABS instruction. */
340 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
341 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
342 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
343 DUMMY_STRINGOP_ALGS},
344 {{libcall, {{-1, rep_prefix_4_byte}}},
345 DUMMY_STRINGOP_ALGS},
346 1, /* scalar_stmt_cost. */
347 1, /* scalar load_cost. */
348 1, /* scalar_store_cost. */
349 1, /* vec_stmt_cost. */
350 1, /* vec_to_scalar_cost. */
351 1, /* scalar_to_vec_cost. */
352 1, /* vec_align_load_cost. */
353 2, /* vec_unalign_load_cost. */
354 1, /* vec_store_cost. */
355 3, /* cond_taken_branch_cost. */
356 1, /* cond_not_taken_branch_cost. */
360 struct processor_costs pentiumpro_cost = {
361 COSTS_N_INSNS (1), /* cost of an add instruction */
362 COSTS_N_INSNS (1), /* cost of a lea instruction */
363 COSTS_N_INSNS (1), /* variable shift costs */
364 COSTS_N_INSNS (1), /* constant shift costs */
365 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
366 COSTS_N_INSNS (4), /* HI */
367 COSTS_N_INSNS (4), /* SI */
368 COSTS_N_INSNS (4), /* DI */
369 COSTS_N_INSNS (4)}, /* other */
370 0, /* cost of multiply per each bit set */
371 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
372 COSTS_N_INSNS (17), /* HI */
373 COSTS_N_INSNS (17), /* SI */
374 COSTS_N_INSNS (17), /* DI */
375 COSTS_N_INSNS (17)}, /* other */
376 COSTS_N_INSNS (1), /* cost of movsx */
377 COSTS_N_INSNS (1), /* cost of movzx */
378 8, /* "large" insn */
380 2, /* cost for loading QImode using movzbl */
381 {4, 4, 4}, /* cost of loading integer registers
382 in QImode, HImode and SImode.
383 Relative to reg-reg move (2). */
384 {2, 2, 2}, /* cost of storing integer registers */
385 2, /* cost of reg,reg fld/fst */
386 {2, 2, 6}, /* cost of loading fp registers
387 in SFmode, DFmode and XFmode */
388 {4, 4, 6}, /* cost of storing fp registers
389 in SFmode, DFmode and XFmode */
390 2, /* cost of moving MMX register */
391 {2, 2}, /* cost of loading MMX registers
392 in SImode and DImode */
393 {2, 2}, /* cost of storing MMX registers
394 in SImode and DImode */
395 2, /* cost of moving SSE register */
396 {2, 2, 8}, /* cost of loading SSE registers
397 in SImode, DImode and TImode */
398 {2, 2, 8}, /* cost of storing SSE registers
399 in SImode, DImode and TImode */
400 3, /* MMX or SSE register to integer */
401 8, /* size of l1 cache. */
402 256, /* size of l2 cache */
403 32, /* size of prefetch block */
404 6, /* number of parallel prefetches */
406 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
407 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
408 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
409 COSTS_N_INSNS (2), /* cost of FABS instruction. */
410 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
411 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
412 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
413 the alignment). For small blocks inline loop is still a noticeable win, for bigger
414 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
415 more expensive startup time in CPU, but after 4K the difference is down in the noise.
417 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
418 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
419 DUMMY_STRINGOP_ALGS},
420 {{rep_prefix_4_byte, {{1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, libcall}}},
422 DUMMY_STRINGOP_ALGS},
423 1, /* scalar_stmt_cost. */
424 1, /* scalar load_cost. */
425 1, /* scalar_store_cost. */
426 1, /* vec_stmt_cost. */
427 1, /* vec_to_scalar_cost. */
428 1, /* scalar_to_vec_cost. */
429 1, /* vec_align_load_cost. */
430 2, /* vec_unalign_load_cost. */
431 1, /* vec_store_cost. */
432 3, /* cond_taken_branch_cost. */
433 1, /* cond_not_taken_branch_cost. */
437 struct processor_costs geode_cost = {
438 COSTS_N_INSNS (1), /* cost of an add instruction */
439 COSTS_N_INSNS (1), /* cost of a lea instruction */
440 COSTS_N_INSNS (2), /* variable shift costs */
441 COSTS_N_INSNS (1), /* constant shift costs */
442 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
443 COSTS_N_INSNS (4), /* HI */
444 COSTS_N_INSNS (7), /* SI */
445 COSTS_N_INSNS (7), /* DI */
446 COSTS_N_INSNS (7)}, /* other */
447 0, /* cost of multiply per each bit set */
448 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
449 COSTS_N_INSNS (23), /* HI */
450 COSTS_N_INSNS (39), /* SI */
451 COSTS_N_INSNS (39), /* DI */
452 COSTS_N_INSNS (39)}, /* other */
453 COSTS_N_INSNS (1), /* cost of movsx */
454 COSTS_N_INSNS (1), /* cost of movzx */
455 8, /* "large" insn */
457 1, /* cost for loading QImode using movzbl */
458 {1, 1, 1}, /* cost of loading integer registers
459 in QImode, HImode and SImode.
460 Relative to reg-reg move (2). */
461 {1, 1, 1}, /* cost of storing integer registers */
462 1, /* cost of reg,reg fld/fst */
463 {1, 1, 1}, /* cost of loading fp registers
464 in SFmode, DFmode and XFmode */
465 {4, 6, 6}, /* cost of storing fp registers
466 in SFmode, DFmode and XFmode */
468 1, /* cost of moving MMX register */
469 {1, 1}, /* cost of loading MMX registers
470 in SImode and DImode */
471 {1, 1}, /* cost of storing MMX registers
472 in SImode and DImode */
473 1, /* cost of moving SSE register */
474 {1, 1, 1}, /* cost of loading SSE registers
475 in SImode, DImode and TImode */
476 {1, 1, 1}, /* cost of storing SSE registers
477 in SImode, DImode and TImode */
478 1, /* MMX or SSE register to integer */
479 64, /* size of l1 cache. */
480 128, /* size of l2 cache. */
481 32, /* size of prefetch block */
482 1, /* number of parallel prefetches */
484 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
485 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
486 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
487 COSTS_N_INSNS (1), /* cost of FABS instruction. */
488 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
489 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
490 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
491 DUMMY_STRINGOP_ALGS},
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 1, /* scalar_stmt_cost. */
495 1, /* scalar load_cost. */
496 1, /* scalar_store_cost. */
497 1, /* vec_stmt_cost. */
498 1, /* vec_to_scalar_cost. */
499 1, /* scalar_to_vec_cost. */
500 1, /* vec_align_load_cost. */
501 2, /* vec_unalign_load_cost. */
502 1, /* vec_store_cost. */
503 3, /* cond_taken_branch_cost. */
504 1, /* cond_not_taken_branch_cost. */
508 struct processor_costs k6_cost = {
509 COSTS_N_INSNS (1), /* cost of an add instruction */
510 COSTS_N_INSNS (2), /* cost of a lea instruction */
511 COSTS_N_INSNS (1), /* variable shift costs */
512 COSTS_N_INSNS (1), /* constant shift costs */
513 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
514 COSTS_N_INSNS (3), /* HI */
515 COSTS_N_INSNS (3), /* SI */
516 COSTS_N_INSNS (3), /* DI */
517 COSTS_N_INSNS (3)}, /* other */
518 0, /* cost of multiply per each bit set */
519 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
520 COSTS_N_INSNS (18), /* HI */
521 COSTS_N_INSNS (18), /* SI */
522 COSTS_N_INSNS (18), /* DI */
523 COSTS_N_INSNS (18)}, /* other */
524 COSTS_N_INSNS (2), /* cost of movsx */
525 COSTS_N_INSNS (2), /* cost of movzx */
526 8, /* "large" insn */
528 3, /* cost for loading QImode using movzbl */
529 {4, 5, 4}, /* cost of loading integer registers
530 in QImode, HImode and SImode.
531 Relative to reg-reg move (2). */
532 {2, 3, 2}, /* cost of storing integer registers */
533 4, /* cost of reg,reg fld/fst */
534 {6, 6, 6}, /* cost of loading fp registers
535 in SFmode, DFmode and XFmode */
536 {4, 4, 4}, /* cost of storing fp registers
537 in SFmode, DFmode and XFmode */
538 2, /* cost of moving MMX register */
539 {2, 2}, /* cost of loading MMX registers
540 in SImode and DImode */
541 {2, 2}, /* cost of storing MMX registers
542 in SImode and DImode */
543 2, /* cost of moving SSE register */
544 {2, 2, 8}, /* cost of loading SSE registers
545 in SImode, DImode and TImode */
546 {2, 2, 8}, /* cost of storing SSE registers
547 in SImode, DImode and TImode */
548 6, /* MMX or SSE register to integer */
549 32, /* size of l1 cache. */
550 32, /* size of l2 cache. Some models
551 have integrated l2 cache, but
552 optimizing for k6 is not important
553 enough to worry about that. */
554 32, /* size of prefetch block */
555 1, /* number of parallel prefetches */
557 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
558 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
559 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
560 COSTS_N_INSNS (2), /* cost of FABS instruction. */
561 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
562 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
563 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
564 DUMMY_STRINGOP_ALGS},
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 1, /* scalar_stmt_cost. */
568 1, /* scalar load_cost. */
569 1, /* scalar_store_cost. */
570 1, /* vec_stmt_cost. */
571 1, /* vec_to_scalar_cost. */
572 1, /* scalar_to_vec_cost. */
573 1, /* vec_align_load_cost. */
574 2, /* vec_unalign_load_cost. */
575 1, /* vec_store_cost. */
576 3, /* cond_taken_branch_cost. */
577 1, /* cond_not_taken_branch_cost. */
581 struct processor_costs athlon_cost = {
582 COSTS_N_INSNS (1), /* cost of an add instruction */
583 COSTS_N_INSNS (2), /* cost of a lea instruction */
584 COSTS_N_INSNS (1), /* variable shift costs */
585 COSTS_N_INSNS (1), /* constant shift costs */
586 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
587 COSTS_N_INSNS (5), /* HI */
588 COSTS_N_INSNS (5), /* SI */
589 COSTS_N_INSNS (5), /* DI */
590 COSTS_N_INSNS (5)}, /* other */
591 0, /* cost of multiply per each bit set */
592 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
593 COSTS_N_INSNS (26), /* HI */
594 COSTS_N_INSNS (42), /* SI */
595 COSTS_N_INSNS (74), /* DI */
596 COSTS_N_INSNS (74)}, /* other */
597 COSTS_N_INSNS (1), /* cost of movsx */
598 COSTS_N_INSNS (1), /* cost of movzx */
599 8, /* "large" insn */
601 4, /* cost for loading QImode using movzbl */
602 {3, 4, 3}, /* cost of loading integer registers
603 in QImode, HImode and SImode.
604 Relative to reg-reg move (2). */
605 {3, 4, 3}, /* cost of storing integer registers */
606 4, /* cost of reg,reg fld/fst */
607 {4, 4, 12}, /* cost of loading fp registers
608 in SFmode, DFmode and XFmode */
609 {6, 6, 8}, /* cost of storing fp registers
610 in SFmode, DFmode and XFmode */
611 2, /* cost of moving MMX register */
612 {4, 4}, /* cost of loading MMX registers
613 in SImode and DImode */
614 {4, 4}, /* cost of storing MMX registers
615 in SImode and DImode */
616 2, /* cost of moving SSE register */
617 {4, 4, 6}, /* cost of loading SSE registers
618 in SImode, DImode and TImode */
619 {4, 4, 5}, /* cost of storing SSE registers
620 in SImode, DImode and TImode */
621 5, /* MMX or SSE register to integer */
622 64, /* size of l1 cache. */
623 256, /* size of l2 cache. */
624 64, /* size of prefetch block */
625 6, /* number of parallel prefetches */
627 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
628 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
629 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
630 COSTS_N_INSNS (2), /* cost of FABS instruction. */
631 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
632 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
633 /* For some reason, Athlon deals better with REP prefix (relative to loops)
634 compared to K8. Alignment becomes important after 8 bytes for memcpy and
635 128 bytes for memset. */
636 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
637 DUMMY_STRINGOP_ALGS},
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 1, /* scalar_stmt_cost. */
641 1, /* scalar load_cost. */
642 1, /* scalar_store_cost. */
643 1, /* vec_stmt_cost. */
644 1, /* vec_to_scalar_cost. */
645 1, /* scalar_to_vec_cost. */
646 1, /* vec_align_load_cost. */
647 2, /* vec_unalign_load_cost. */
648 1, /* vec_store_cost. */
649 3, /* cond_taken_branch_cost. */
650 1, /* cond_not_taken_branch_cost. */
654 struct processor_costs k8_cost = {
655 COSTS_N_INSNS (1), /* cost of an add instruction */
656 COSTS_N_INSNS (2), /* cost of a lea instruction */
657 COSTS_N_INSNS (1), /* variable shift costs */
658 COSTS_N_INSNS (1), /* constant shift costs */
659 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
660 COSTS_N_INSNS (4), /* HI */
661 COSTS_N_INSNS (3), /* SI */
662 COSTS_N_INSNS (4), /* DI */
663 COSTS_N_INSNS (5)}, /* other */
664 0, /* cost of multiply per each bit set */
665 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
666 COSTS_N_INSNS (26), /* HI */
667 COSTS_N_INSNS (42), /* SI */
668 COSTS_N_INSNS (74), /* DI */
669 COSTS_N_INSNS (74)}, /* other */
670 COSTS_N_INSNS (1), /* cost of movsx */
671 COSTS_N_INSNS (1), /* cost of movzx */
672 8, /* "large" insn */
674 4, /* cost for loading QImode using movzbl */
675 {3, 4, 3}, /* cost of loading integer registers
676 in QImode, HImode and SImode.
677 Relative to reg-reg move (2). */
678 {3, 4, 3}, /* cost of storing integer registers */
679 4, /* cost of reg,reg fld/fst */
680 {4, 4, 12}, /* cost of loading fp registers
681 in SFmode, DFmode and XFmode */
682 {6, 6, 8}, /* cost of storing fp registers
683 in SFmode, DFmode and XFmode */
684 2, /* cost of moving MMX register */
685 {3, 3}, /* cost of loading MMX registers
686 in SImode and DImode */
687 {4, 4}, /* cost of storing MMX registers
688 in SImode and DImode */
689 2, /* cost of moving SSE register */
690 {4, 3, 6}, /* cost of loading SSE registers
691 in SImode, DImode and TImode */
692 {4, 4, 5}, /* cost of storing SSE registers
693 in SImode, DImode and TImode */
694 5, /* MMX or SSE register to integer */
695 64, /* size of l1 cache. */
696 512, /* size of l2 cache. */
697 64, /* size of prefetch block */
698 /* New AMD processors never drop prefetches; if they cannot be performed
699 immediately, they are queued. We set number of simultaneous prefetches
700 to a large constant to reflect this (it probably is not a good idea not
701 to limit number of prefetches at all, as their execution also takes some
703 100, /* number of parallel prefetches */
705 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
706 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
707 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
708 COSTS_N_INSNS (2), /* cost of FABS instruction. */
709 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
710 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
711 /* K8 has optimized REP instruction for medium sized blocks, but for very small
712 blocks it is better to use loop. For large blocks, libcall can do
713 nontemporary accesses and beat inline considerably. */
714 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
715 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
716 {{libcall, {{8, loop}, {24, unrolled_loop},
717 {2048, rep_prefix_4_byte}, {-1, libcall}}},
718 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 4, /* scalar_stmt_cost. */
720 2, /* scalar load_cost. */
721 2, /* scalar_store_cost. */
722 5, /* vec_stmt_cost. */
723 0, /* vec_to_scalar_cost. */
724 2, /* scalar_to_vec_cost. */
725 2, /* vec_align_load_cost. */
726 3, /* vec_unalign_load_cost. */
727 3, /* vec_store_cost. */
728 3, /* cond_taken_branch_cost. */
729 2, /* cond_not_taken_branch_cost. */
732 struct processor_costs amdfam10_cost = {
733 COSTS_N_INSNS (1), /* cost of an add instruction */
734 COSTS_N_INSNS (2), /* cost of a lea instruction */
735 COSTS_N_INSNS (1), /* variable shift costs */
736 COSTS_N_INSNS (1), /* constant shift costs */
737 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
738 COSTS_N_INSNS (4), /* HI */
739 COSTS_N_INSNS (3), /* SI */
740 COSTS_N_INSNS (4), /* DI */
741 COSTS_N_INSNS (5)}, /* other */
742 0, /* cost of multiply per each bit set */
743 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
744 COSTS_N_INSNS (35), /* HI */
745 COSTS_N_INSNS (51), /* SI */
746 COSTS_N_INSNS (83), /* DI */
747 COSTS_N_INSNS (83)}, /* other */
748 COSTS_N_INSNS (1), /* cost of movsx */
749 COSTS_N_INSNS (1), /* cost of movzx */
750 8, /* "large" insn */
752 4, /* cost for loading QImode using movzbl */
753 {3, 4, 3}, /* cost of loading integer registers
754 in QImode, HImode and SImode.
755 Relative to reg-reg move (2). */
756 {3, 4, 3}, /* cost of storing integer registers */
757 4, /* cost of reg,reg fld/fst */
758 {4, 4, 12}, /* cost of loading fp registers
759 in SFmode, DFmode and XFmode */
760 {6, 6, 8}, /* cost of storing fp registers
761 in SFmode, DFmode and XFmode */
762 2, /* cost of moving MMX register */
763 {3, 3}, /* cost of loading MMX registers
764 in SImode and DImode */
765 {4, 4}, /* cost of storing MMX registers
766 in SImode and DImode */
767 2, /* cost of moving SSE register */
768 {4, 4, 3}, /* cost of loading SSE registers
769 in SImode, DImode and TImode */
770 {4, 4, 5}, /* cost of storing SSE registers
771 in SImode, DImode and TImode */
772 3, /* MMX or SSE register to integer */
774 MOVD reg64, xmmreg Double FSTORE 4
775 MOVD reg32, xmmreg Double FSTORE 4
777 MOVD reg64, xmmreg Double FADD 3
779 MOVD reg32, xmmreg Double FADD 3
781 64, /* size of l1 cache. */
782 512, /* size of l2 cache. */
783 64, /* size of prefetch block */
784 /* New AMD processors never drop prefetches; if they cannot be performed
785 immediately, they are queued. We set number of simultaneous prefetches
786 to a large constant to reflect this (it probably is not a good idea not
787 to limit number of prefetches at all, as their execution also takes some
789 100, /* number of parallel prefetches */
791 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
792 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
793 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
794 COSTS_N_INSNS (2), /* cost of FABS instruction. */
795 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
796 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
798 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
799 very small blocks it is better to use loop. For large blocks, libcall can
800 do nontemporary accesses and beat inline considerably. */
801 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
802 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
803 {{libcall, {{8, loop}, {24, unrolled_loop},
804 {2048, rep_prefix_4_byte}, {-1, libcall}}},
805 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 4, /* scalar_stmt_cost. */
807 2, /* scalar load_cost. */
808 2, /* scalar_store_cost. */
809 6, /* vec_stmt_cost. */
810 0, /* vec_to_scalar_cost. */
811 2, /* scalar_to_vec_cost. */
812 2, /* vec_align_load_cost. */
813 2, /* vec_unalign_load_cost. */
814 2, /* vec_store_cost. */
815 2, /* cond_taken_branch_cost. */
816 1, /* cond_not_taken_branch_cost. */
820 struct processor_costs pentium4_cost = {
821 COSTS_N_INSNS (1), /* cost of an add instruction */
822 COSTS_N_INSNS (3), /* cost of a lea instruction */
823 COSTS_N_INSNS (4), /* variable shift costs */
824 COSTS_N_INSNS (4), /* constant shift costs */
825 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
826 COSTS_N_INSNS (15), /* HI */
827 COSTS_N_INSNS (15), /* SI */
828 COSTS_N_INSNS (15), /* DI */
829 COSTS_N_INSNS (15)}, /* other */
830 0, /* cost of multiply per each bit set */
831 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
832 COSTS_N_INSNS (56), /* HI */
833 COSTS_N_INSNS (56), /* SI */
834 COSTS_N_INSNS (56), /* DI */
835 COSTS_N_INSNS (56)}, /* other */
836 COSTS_N_INSNS (1), /* cost of movsx */
837 COSTS_N_INSNS (1), /* cost of movzx */
838 16, /* "large" insn */
840 2, /* cost for loading QImode using movzbl */
841 {4, 5, 4}, /* cost of loading integer registers
842 in QImode, HImode and SImode.
843 Relative to reg-reg move (2). */
844 {2, 3, 2}, /* cost of storing integer registers */
845 2, /* cost of reg,reg fld/fst */
846 {2, 2, 6}, /* cost of loading fp registers
847 in SFmode, DFmode and XFmode */
848 {4, 4, 6}, /* cost of storing fp registers
849 in SFmode, DFmode and XFmode */
850 2, /* cost of moving MMX register */
851 {2, 2}, /* cost of loading MMX registers
852 in SImode and DImode */
853 {2, 2}, /* cost of storing MMX registers
854 in SImode and DImode */
855 12, /* cost of moving SSE register */
856 {12, 12, 12}, /* cost of loading SSE registers
857 in SImode, DImode and TImode */
858 {2, 2, 8}, /* cost of storing SSE registers
859 in SImode, DImode and TImode */
860 10, /* MMX or SSE register to integer */
861 8, /* size of l1 cache. */
862 256, /* size of l2 cache. */
863 64, /* size of prefetch block */
864 6, /* number of parallel prefetches */
866 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
867 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
868 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
869 COSTS_N_INSNS (2), /* cost of FABS instruction. */
870 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
871 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
872 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
873 DUMMY_STRINGOP_ALGS},
874 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
876 DUMMY_STRINGOP_ALGS},
877 1, /* scalar_stmt_cost. */
878 1, /* scalar load_cost. */
879 1, /* scalar_store_cost. */
880 1, /* vec_stmt_cost. */
881 1, /* vec_to_scalar_cost. */
882 1, /* scalar_to_vec_cost. */
883 1, /* vec_align_load_cost. */
884 2, /* vec_unalign_load_cost. */
885 1, /* vec_store_cost. */
886 3, /* cond_taken_branch_cost. */
887 1, /* cond_not_taken_branch_cost. */
891 struct processor_costs nocona_cost = {
892 COSTS_N_INSNS (1), /* cost of an add instruction */
893 COSTS_N_INSNS (1), /* cost of a lea instruction */
894 COSTS_N_INSNS (1), /* variable shift costs */
895 COSTS_N_INSNS (1), /* constant shift costs */
896 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
897 COSTS_N_INSNS (10), /* HI */
898 COSTS_N_INSNS (10), /* SI */
899 COSTS_N_INSNS (10), /* DI */
900 COSTS_N_INSNS (10)}, /* other */
901 0, /* cost of multiply per each bit set */
902 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
903 COSTS_N_INSNS (66), /* HI */
904 COSTS_N_INSNS (66), /* SI */
905 COSTS_N_INSNS (66), /* DI */
906 COSTS_N_INSNS (66)}, /* other */
907 COSTS_N_INSNS (1), /* cost of movsx */
908 COSTS_N_INSNS (1), /* cost of movzx */
909 16, /* "large" insn */
911 4, /* cost for loading QImode using movzbl */
912 {4, 4, 4}, /* cost of loading integer registers
913 in QImode, HImode and SImode.
914 Relative to reg-reg move (2). */
915 {4, 4, 4}, /* cost of storing integer registers */
916 3, /* cost of reg,reg fld/fst */
917 {12, 12, 12}, /* cost of loading fp registers
918 in SFmode, DFmode and XFmode */
919 {4, 4, 4}, /* cost of storing fp registers
920 in SFmode, DFmode and XFmode */
921 6, /* cost of moving MMX register */
922 {12, 12}, /* cost of loading MMX registers
923 in SImode and DImode */
924 {12, 12}, /* cost of storing MMX registers
925 in SImode and DImode */
926 6, /* cost of moving SSE register */
927 {12, 12, 12}, /* cost of loading SSE registers
928 in SImode, DImode and TImode */
929 {12, 12, 12}, /* cost of storing SSE registers
930 in SImode, DImode and TImode */
931 8, /* MMX or SSE register to integer */
932 8, /* size of l1 cache. */
933 1024, /* size of l2 cache. */
934 128, /* size of prefetch block */
935 8, /* number of parallel prefetches */
937 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
938 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
939 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
940 COSTS_N_INSNS (3), /* cost of FABS instruction. */
941 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
942 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
943 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
944 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
945 {100000, unrolled_loop}, {-1, libcall}}}},
946 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
948 {libcall, {{24, loop}, {64, unrolled_loop},
949 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
950 1, /* scalar_stmt_cost. */
951 1, /* scalar load_cost. */
952 1, /* scalar_store_cost. */
953 1, /* vec_stmt_cost. */
954 1, /* vec_to_scalar_cost. */
955 1, /* scalar_to_vec_cost. */
956 1, /* vec_align_load_cost. */
957 2, /* vec_unalign_load_cost. */
958 1, /* vec_store_cost. */
959 3, /* cond_taken_branch_cost. */
960 1, /* cond_not_taken_branch_cost. */
964 struct processor_costs core2_cost = {
965 COSTS_N_INSNS (1), /* cost of an add instruction */
966 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
967 COSTS_N_INSNS (1), /* variable shift costs */
968 COSTS_N_INSNS (1), /* constant shift costs */
969 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
970 COSTS_N_INSNS (3), /* HI */
971 COSTS_N_INSNS (3), /* SI */
972 COSTS_N_INSNS (3), /* DI */
973 COSTS_N_INSNS (3)}, /* other */
974 0, /* cost of multiply per each bit set */
975 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
976 COSTS_N_INSNS (22), /* HI */
977 COSTS_N_INSNS (22), /* SI */
978 COSTS_N_INSNS (22), /* DI */
979 COSTS_N_INSNS (22)}, /* other */
980 COSTS_N_INSNS (1), /* cost of movsx */
981 COSTS_N_INSNS (1), /* cost of movzx */
982 8, /* "large" insn */
984 2, /* cost for loading QImode using movzbl */
985 {6, 6, 6}, /* cost of loading integer registers
986 in QImode, HImode and SImode.
987 Relative to reg-reg move (2). */
988 {4, 4, 4}, /* cost of storing integer registers */
989 2, /* cost of reg,reg fld/fst */
990 {6, 6, 6}, /* cost of loading fp registers
991 in SFmode, DFmode and XFmode */
992 {4, 4, 4}, /* cost of loading integer registers */
993 2, /* cost of moving MMX register */
994 {6, 6}, /* cost of loading MMX registers
995 in SImode and DImode */
996 {4, 4}, /* cost of storing MMX registers
997 in SImode and DImode */
998 2, /* cost of moving SSE register */
999 {6, 6, 6}, /* cost of loading SSE registers
1000 in SImode, DImode and TImode */
1001 {4, 4, 4}, /* cost of storing SSE registers
1002 in SImode, DImode and TImode */
1003 2, /* MMX or SSE register to integer */
1004 32, /* size of l1 cache. */
1005 2048, /* size of l2 cache. */
1006 128, /* size of prefetch block */
1007 8, /* number of parallel prefetches */
1008 3, /* Branch cost */
1009 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1010 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1011 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1012 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1013 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1014 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1015 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1016 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1017 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1018 {{libcall, {{8, loop}, {15, unrolled_loop},
1019 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1020 {libcall, {{24, loop}, {32, unrolled_loop},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 1, /* scalar_stmt_cost. */
1023 1, /* scalar load_cost. */
1024 1, /* scalar_store_cost. */
1025 1, /* vec_stmt_cost. */
1026 1, /* vec_to_scalar_cost. */
1027 1, /* scalar_to_vec_cost. */
1028 1, /* vec_align_load_cost. */
1029 2, /* vec_unalign_load_cost. */
1030 1, /* vec_store_cost. */
1031 3, /* cond_taken_branch_cost. */
1032 1, /* cond_not_taken_branch_cost. */
1035 /* Generic64 should produce code tuned for Nocona and K8. */
1037 struct processor_costs generic64_cost = {
1038 COSTS_N_INSNS (1), /* cost of an add instruction */
1039 /* On all chips taken into consideration lea is 2 cycles and more. With
1040 this cost however our current implementation of synth_mult results in
1041 use of unnecessary temporary registers causing regression on several
1042 SPECfp benchmarks. */
1043 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1044 COSTS_N_INSNS (1), /* variable shift costs */
1045 COSTS_N_INSNS (1), /* constant shift costs */
1046 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1047 COSTS_N_INSNS (4), /* HI */
1048 COSTS_N_INSNS (3), /* SI */
1049 COSTS_N_INSNS (4), /* DI */
1050 COSTS_N_INSNS (2)}, /* other */
1051 0, /* cost of multiply per each bit set */
1052 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1053 COSTS_N_INSNS (26), /* HI */
1054 COSTS_N_INSNS (42), /* SI */
1055 COSTS_N_INSNS (74), /* DI */
1056 COSTS_N_INSNS (74)}, /* other */
1057 COSTS_N_INSNS (1), /* cost of movsx */
1058 COSTS_N_INSNS (1), /* cost of movzx */
1059 8, /* "large" insn */
1060 17, /* MOVE_RATIO */
1061 4, /* cost for loading QImode using movzbl */
1062 {4, 4, 4}, /* cost of loading integer registers
1063 in QImode, HImode and SImode.
1064 Relative to reg-reg move (2). */
1065 {4, 4, 4}, /* cost of storing integer registers */
1066 4, /* cost of reg,reg fld/fst */
1067 {12, 12, 12}, /* cost of loading fp registers
1068 in SFmode, DFmode and XFmode */
1069 {6, 6, 8}, /* cost of storing fp registers
1070 in SFmode, DFmode and XFmode */
1071 2, /* cost of moving MMX register */
1072 {8, 8}, /* cost of loading MMX registers
1073 in SImode and DImode */
1074 {8, 8}, /* cost of storing MMX registers
1075 in SImode and DImode */
1076 2, /* cost of moving SSE register */
1077 {8, 8, 8}, /* cost of loading SSE registers
1078 in SImode, DImode and TImode */
1079 {8, 8, 8}, /* cost of storing SSE registers
1080 in SImode, DImode and TImode */
1081 5, /* MMX or SSE register to integer */
1082 32, /* size of l1 cache. */
1083 512, /* size of l2 cache. */
1084 64, /* size of prefetch block */
1085 6, /* number of parallel prefetches */
1086 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1087 is increased to perhaps more appropriate value of 5. */
1088 3, /* Branch cost */
1089 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1090 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1091 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1092 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1093 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1094 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1095 {DUMMY_STRINGOP_ALGS,
1096 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 1, /* scalar_stmt_cost. */
1100 1, /* scalar load_cost. */
1101 1, /* scalar_store_cost. */
1102 1, /* vec_stmt_cost. */
1103 1, /* vec_to_scalar_cost. */
1104 1, /* scalar_to_vec_cost. */
1105 1, /* vec_align_load_cost. */
1106 2, /* vec_unalign_load_cost. */
1107 1, /* vec_store_cost. */
1108 3, /* cond_taken_branch_cost. */
1109 1, /* cond_not_taken_branch_cost. */
1112 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1114 struct processor_costs generic32_cost = {
1115 COSTS_N_INSNS (1), /* cost of an add instruction */
1116 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1117 COSTS_N_INSNS (1), /* variable shift costs */
1118 COSTS_N_INSNS (1), /* constant shift costs */
1119 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1120 COSTS_N_INSNS (4), /* HI */
1121 COSTS_N_INSNS (3), /* SI */
1122 COSTS_N_INSNS (4), /* DI */
1123 COSTS_N_INSNS (2)}, /* other */
1124 0, /* cost of multiply per each bit set */
1125 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1126 COSTS_N_INSNS (26), /* HI */
1127 COSTS_N_INSNS (42), /* SI */
1128 COSTS_N_INSNS (74), /* DI */
1129 COSTS_N_INSNS (74)}, /* other */
1130 COSTS_N_INSNS (1), /* cost of movsx */
1131 COSTS_N_INSNS (1), /* cost of movzx */
1132 8, /* "large" insn */
1133 17, /* MOVE_RATIO */
1134 4, /* cost for loading QImode using movzbl */
1135 {4, 4, 4}, /* cost of loading integer registers
1136 in QImode, HImode and SImode.
1137 Relative to reg-reg move (2). */
1138 {4, 4, 4}, /* cost of storing integer registers */
1139 4, /* cost of reg,reg fld/fst */
1140 {12, 12, 12}, /* cost of loading fp registers
1141 in SFmode, DFmode and XFmode */
1142 {6, 6, 8}, /* cost of storing fp registers
1143 in SFmode, DFmode and XFmode */
1144 2, /* cost of moving MMX register */
1145 {8, 8}, /* cost of loading MMX registers
1146 in SImode and DImode */
1147 {8, 8}, /* cost of storing MMX registers
1148 in SImode and DImode */
1149 2, /* cost of moving SSE register */
1150 {8, 8, 8}, /* cost of loading SSE registers
1151 in SImode, DImode and TImode */
1152 {8, 8, 8}, /* cost of storing SSE registers
1153 in SImode, DImode and TImode */
1154 5, /* MMX or SSE register to integer */
1155 32, /* size of l1 cache. */
1156 256, /* size of l2 cache. */
1157 64, /* size of prefetch block */
1158 6, /* number of parallel prefetches */
1159 3, /* Branch cost */
1160 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1161 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1162 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1163 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1164 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1165 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1166 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1167 DUMMY_STRINGOP_ALGS},
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 1, /* scalar_stmt_cost. */
1171 1, /* scalar load_cost. */
1172 1, /* scalar_store_cost. */
1173 1, /* vec_stmt_cost. */
1174 1, /* vec_to_scalar_cost. */
1175 1, /* scalar_to_vec_cost. */
1176 1, /* vec_align_load_cost. */
1177 2, /* vec_unalign_load_cost. */
1178 1, /* vec_store_cost. */
1179 3, /* cond_taken_branch_cost. */
1180 1, /* cond_not_taken_branch_cost. */
1183 const struct processor_costs *ix86_cost = &pentium_cost;
1185 /* Processor feature/optimization bitmasks. */
1186 #define m_386 (1<<PROCESSOR_I386)
1187 #define m_486 (1<<PROCESSOR_I486)
1188 #define m_PENT (1<<PROCESSOR_PENTIUM)
1189 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1190 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1191 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1192 #define m_CORE2 (1<<PROCESSOR_CORE2)
1194 #define m_GEODE (1<<PROCESSOR_GEODE)
1195 #define m_K6 (1<<PROCESSOR_K6)
1196 #define m_K6_GEODE (m_K6 | m_GEODE)
1197 #define m_K8 (1<<PROCESSOR_K8)
1198 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1199 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1200 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1201 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1203 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1204 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1206 /* Generic instruction choice should be common subset of supported CPUs
1207 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1208 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1210 /* Feature tests against the various tunings. */
1211 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1212 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1213 negatively, so enabling for Generic64 seems like good code size
1214 tradeoff. We can't enable it for 32bit generic because it does not
1215 work well with PPro base chips. */
1216 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1218 /* X86_TUNE_PUSH_MEMORY */
1219 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1220 | m_NOCONA | m_CORE2 | m_GENERIC,
1222 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1225 /* X86_TUNE_USE_BIT_TEST */
1228 /* X86_TUNE_UNROLL_STRLEN */
1229 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1231 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1232 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1234 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1235 on simulation result. But after P4 was made, no performance benefit
1236 was observed with branch hints. It also increases the code size.
1237 As a result, icc never generates branch hints. */
1240 /* X86_TUNE_DOUBLE_WITH_ADD */
1243 /* X86_TUNE_USE_SAHF */
1244 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1245 | m_NOCONA | m_CORE2 | m_GENERIC,
1247 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1248 partial dependencies. */
1249 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1250 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1252 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1253 register stalls on Generic32 compilation setting as well. However
1254 in current implementation the partial register stalls are not eliminated
1255 very well - they can be introduced via subregs synthesized by combine
1256 and can happen in caller/callee saving sequences. Because this option
1257 pays back little on PPro based chips and is in conflict with partial reg
1258 dependencies used by Athlon/P4 based chips, it is better to leave it off
1259 for generic32 for now. */
1262 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1263 m_CORE2 | m_GENERIC,
1265 /* X86_TUNE_USE_HIMODE_FIOP */
1266 m_386 | m_486 | m_K6_GEODE,
1268 /* X86_TUNE_USE_SIMODE_FIOP */
1269 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1271 /* X86_TUNE_USE_MOV0 */
1274 /* X86_TUNE_USE_CLTD */
1275 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1277 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1280 /* X86_TUNE_SPLIT_LONG_MOVES */
1283 /* X86_TUNE_READ_MODIFY_WRITE */
1286 /* X86_TUNE_READ_MODIFY */
1289 /* X86_TUNE_PROMOTE_QIMODE */
1290 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1291 | m_GENERIC /* | m_PENT4 ? */,
1293 /* X86_TUNE_FAST_PREFIX */
1294 ~(m_PENT | m_486 | m_386),
1296 /* X86_TUNE_SINGLE_STRINGOP */
1297 m_386 | m_PENT4 | m_NOCONA,
1299 /* X86_TUNE_QIMODE_MATH */
1302 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1303 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1304 might be considered for Generic32 if our scheme for avoiding partial
1305 stalls was more effective. */
1308 /* X86_TUNE_PROMOTE_QI_REGS */
1311 /* X86_TUNE_PROMOTE_HI_REGS */
1314 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1315 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1317 /* X86_TUNE_ADD_ESP_8 */
1318 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1319 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1321 /* X86_TUNE_SUB_ESP_4 */
1322 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1324 /* X86_TUNE_SUB_ESP_8 */
1325 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1326 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1328 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1329 for DFmode copies */
1330 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1331 | m_GENERIC | m_GEODE),
1333 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1334 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1336 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1337 conflict here in between PPro/Pentium4 based chips that thread 128bit
1338 SSE registers as single units versus K8 based chips that divide SSE
1339 registers to two 64bit halves. This knob promotes all store destinations
1340 to be 128bit to allow register renaming on 128bit SSE units, but usually
1341 results in one extra microop on 64bit SSE units. Experimental results
1342 shows that disabling this option on P4 brings over 20% SPECfp regression,
1343 while enabling it on K8 brings roughly 2.4% regression that can be partly
1344 masked by careful scheduling of moves. */
1345 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1347 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1350 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1351 are resolved on SSE register parts instead of whole registers, so we may
1352 maintain just lower part of scalar values in proper format leaving the
1353 upper part undefined. */
1356 /* X86_TUNE_SSE_TYPELESS_STORES */
1359 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1360 m_PPRO | m_PENT4 | m_NOCONA,
1362 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1363 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1365 /* X86_TUNE_PROLOGUE_USING_MOVE */
1366 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1368 /* X86_TUNE_EPILOGUE_USING_MOVE */
1369 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1371 /* X86_TUNE_SHIFT1 */
1374 /* X86_TUNE_USE_FFREEP */
1377 /* X86_TUNE_INTER_UNIT_MOVES */
1378 ~(m_AMD_MULTIPLE | m_GENERIC),
1380 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1383 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1384 than 4 branch instructions in the 16 byte window. */
1385 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1387 /* X86_TUNE_SCHEDULE */
1388 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1390 /* X86_TUNE_USE_BT */
1393 /* X86_TUNE_USE_INCDEC */
1394 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1396 /* X86_TUNE_PAD_RETURNS */
1397 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1399 /* X86_TUNE_EXT_80387_CONSTANTS */
1400 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1402 /* X86_TUNE_SHORTEN_X87_SSE */
1405 /* X86_TUNE_AVOID_VECTOR_DECODE */
1408 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1409 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1412 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1413 vector path on AMD machines. */
1414 m_K8 | m_GENERIC64 | m_AMDFAM10,
1416 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1418 m_K8 | m_GENERIC64 | m_AMDFAM10,
1420 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1424 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1425 but one byte longer. */
1428 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1429 operand that cannot be represented using a modRM byte. The XOR
1430 replacement is long decoded, so this split helps here as well. */
1433 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1434 from integer to FP. */
1438 /* Feature tests against the various architecture variations. */
1439 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1440 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1441 ~(m_386 | m_486 | m_PENT | m_K6),
1443 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1446 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1449 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1452 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1456 static const unsigned int x86_accumulate_outgoing_args
1457 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1459 static const unsigned int x86_arch_always_fancy_math_387
1460 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1461 | m_NOCONA | m_CORE2 | m_GENERIC;
1463 static enum stringop_alg stringop_alg = no_stringop;
1465 /* In case the average insn count for single function invocation is
1466 lower than this constant, emit fast (but longer) prologue and
1468 #define FAST_PROLOGUE_INSN_COUNT 20
1470 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1471 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1472 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1473 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1475 /* Array of the smallest class containing reg number REGNO, indexed by
1476 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1478 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1480 /* ax, dx, cx, bx */
1481 AREG, DREG, CREG, BREG,
1482 /* si, di, bp, sp */
1483 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1485 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1486 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1489 /* flags, fpsr, fpcr, frame */
1490 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1492 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1495 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1498 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1499 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1500 /* SSE REX registers */
1501 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1505 /* The "default" register map used in 32bit mode. */
1507 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1509 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1510 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1511 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1512 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1513 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1514 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1515 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1518 static int const x86_64_int_parameter_registers[6] =
1520 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1521 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1524 static int const x86_64_ms_abi_int_parameter_registers[4] =
1526 2 /*RCX*/, 1 /*RDX*/,
1527 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1530 static int const x86_64_int_return_registers[4] =
1532 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1535 /* The "default" register map used in 64bit mode. */
1536 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1538 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1539 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1540 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1541 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1542 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1543 8,9,10,11,12,13,14,15, /* extended integer registers */
1544 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1547 /* Define the register numbers to be used in Dwarf debugging information.
1548 The SVR4 reference port C compiler uses the following register numbers
1549 in its Dwarf output code:
1550 0 for %eax (gcc regno = 0)
1551 1 for %ecx (gcc regno = 2)
1552 2 for %edx (gcc regno = 1)
1553 3 for %ebx (gcc regno = 3)
1554 4 for %esp (gcc regno = 7)
1555 5 for %ebp (gcc regno = 6)
1556 6 for %esi (gcc regno = 4)
1557 7 for %edi (gcc regno = 5)
1558 The following three DWARF register numbers are never generated by
1559 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1560 believes these numbers have these meanings.
1561 8 for %eip (no gcc equivalent)
1562 9 for %eflags (gcc regno = 17)
1563 10 for %trapno (no gcc equivalent)
1564 It is not at all clear how we should number the FP stack registers
1565 for the x86 architecture. If the version of SDB on x86/svr4 were
1566 a bit less brain dead with respect to floating-point then we would
1567 have a precedent to follow with respect to DWARF register numbers
1568 for x86 FP registers, but the SDB on x86/svr4 is so completely
1569 broken with respect to FP registers that it is hardly worth thinking
1570 of it as something to strive for compatibility with.
1571 The version of x86/svr4 SDB I have at the moment does (partially)
1572 seem to believe that DWARF register number 11 is associated with
1573 the x86 register %st(0), but that's about all. Higher DWARF
1574 register numbers don't seem to be associated with anything in
1575 particular, and even for DWARF regno 11, SDB only seems to under-
1576 stand that it should say that a variable lives in %st(0) (when
1577 asked via an `=' command) if we said it was in DWARF regno 11,
1578 but SDB still prints garbage when asked for the value of the
1579 variable in question (via a `/' command).
1580 (Also note that the labels SDB prints for various FP stack regs
1581 when doing an `x' command are all wrong.)
1582 Note that these problems generally don't affect the native SVR4
1583 C compiler because it doesn't allow the use of -O with -g and
1584 because when it is *not* optimizing, it allocates a memory
1585 location for each floating-point variable, and the memory
1586 location is what gets described in the DWARF AT_location
1587 attribute for the variable in question.
1588 Regardless of the severe mental illness of the x86/svr4 SDB, we
1589 do something sensible here and we use the following DWARF
1590 register numbers. Note that these are all stack-top-relative
1592 11 for %st(0) (gcc regno = 8)
1593 12 for %st(1) (gcc regno = 9)
1594 13 for %st(2) (gcc regno = 10)
1595 14 for %st(3) (gcc regno = 11)
1596 15 for %st(4) (gcc regno = 12)
1597 16 for %st(5) (gcc regno = 13)
1598 17 for %st(6) (gcc regno = 14)
1599 18 for %st(7) (gcc regno = 15)
1601 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1603 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1604 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1605 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1606 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1607 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1608 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1609 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1612 /* Test and compare insns in i386.md store the information needed to
1613 generate branch and scc insns here. */
1615 rtx ix86_compare_op0 = NULL_RTX;
1616 rtx ix86_compare_op1 = NULL_RTX;
1617 rtx ix86_compare_emitted = NULL_RTX;
1619 /* Size of the register save area. */
1620 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1622 /* Define the structure for the machine field in struct function. */
1624 struct stack_local_entry GTY(())
1626 unsigned short mode;
1629 struct stack_local_entry *next;
1632 /* Structure describing stack frame layout.
1633 Stack grows downward:
1639 saved frame pointer if frame_pointer_needed
1640 <- HARD_FRAME_POINTER
1645 [va_arg registers] (
1646 > to_allocate <- FRAME_POINTER
1656 HOST_WIDE_INT frame;
1658 int outgoing_arguments_size;
1661 HOST_WIDE_INT to_allocate;
1662 /* The offsets relative to ARG_POINTER. */
1663 HOST_WIDE_INT frame_pointer_offset;
1664 HOST_WIDE_INT hard_frame_pointer_offset;
1665 HOST_WIDE_INT stack_pointer_offset;
1667 /* When save_regs_using_mov is set, emit prologue using
1668 move instead of push instructions. */
1669 bool save_regs_using_mov;
1672 /* Code model option. */
1673 enum cmodel ix86_cmodel;
1675 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1677 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1679 /* Which unit we are generating floating point math for. */
1680 enum fpmath_unit ix86_fpmath;
1682 /* Which cpu are we scheduling for. */
1683 enum processor_type ix86_tune;
1685 /* Which instruction set architecture to use. */
1686 enum processor_type ix86_arch;
1688 /* true if sse prefetch instruction is not NOOP. */
1689 int x86_prefetch_sse;
1691 /* ix86_regparm_string as a number */
1692 static int ix86_regparm;
1694 /* -mstackrealign option */
1695 extern int ix86_force_align_arg_pointer;
1696 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1698 /* Preferred alignment for stack boundary in bits. */
1699 unsigned int ix86_preferred_stack_boundary;
1701 /* Values 1-5: see jump.c */
1702 int ix86_branch_cost;
1704 /* Variables which are this size or smaller are put in the data/bss
1705 or ldata/lbss sections. */
1707 int ix86_section_threshold = 65536;
1709 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1710 char internal_label_prefix[16];
1711 int internal_label_prefix_len;
1713 /* Fence to use after loop using movnt. */
1716 /* Register class used for passing given 64bit part of the argument.
1717 These represent classes as documented by the PS ABI, with the exception
1718 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1719 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1721 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1722 whenever possible (upper half does contain padding). */
1723 enum x86_64_reg_class
1726 X86_64_INTEGER_CLASS,
1727 X86_64_INTEGERSI_CLASS,
1734 X86_64_COMPLEX_X87_CLASS,
1737 static const char * const x86_64_reg_class_name[] =
1739 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1740 "sseup", "x87", "x87up", "cplx87", "no"
1743 #define MAX_CLASSES 4
1745 /* Table of constants used by fldpi, fldln2, etc.... */
1746 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1747 static bool ext_80387_constants_init = 0;
1750 static struct machine_function * ix86_init_machine_status (void);
1751 static rtx ix86_function_value (const_tree, const_tree, bool);
1752 static int ix86_function_regparm (const_tree, const_tree);
1753 static void ix86_compute_frame_layout (struct ix86_frame *);
1754 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1758 /* The svr4 ABI for the i386 says that records and unions are returned
1760 #ifndef DEFAULT_PCC_STRUCT_RETURN
1761 #define DEFAULT_PCC_STRUCT_RETURN 1
1764 /* Bit flags that specify the ISA we are compiling for. */
1765 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1767 /* A mask of ix86_isa_flags that includes bit X if X
1768 was set or cleared on the command line. */
1769 static int ix86_isa_flags_explicit;
1771 /* Define a set of ISAs which are available when a given ISA is
1772 enabled. MMX and SSE ISAs are handled separately. */
1774 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1775 #define OPTION_MASK_ISA_3DNOW_SET \
1776 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1778 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1779 #define OPTION_MASK_ISA_SSE2_SET \
1780 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1781 #define OPTION_MASK_ISA_SSE3_SET \
1782 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1783 #define OPTION_MASK_ISA_SSSE3_SET \
1784 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1785 #define OPTION_MASK_ISA_SSE4_1_SET \
1786 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1787 #define OPTION_MASK_ISA_SSE4_2_SET \
1788 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1790 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1792 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1794 #define OPTION_MASK_ISA_SSE4A_SET \
1795 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1796 #define OPTION_MASK_ISA_SSE5_SET \
1797 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1799 /* Define a set of ISAs which aren't available when a given ISA is
1800 disabled. MMX and SSE ISAs are handled separately. */
1802 #define OPTION_MASK_ISA_MMX_UNSET \
1803 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1804 #define OPTION_MASK_ISA_3DNOW_UNSET \
1805 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1806 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1808 #define OPTION_MASK_ISA_SSE_UNSET \
1809 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1810 #define OPTION_MASK_ISA_SSE2_UNSET \
1811 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1812 #define OPTION_MASK_ISA_SSE3_UNSET \
1813 (OPTION_MASK_ISA_SSE3 \
1814 | OPTION_MASK_ISA_SSSE3_UNSET \
1815 | OPTION_MASK_ISA_SSE4A_UNSET )
1816 #define OPTION_MASK_ISA_SSSE3_UNSET \
1817 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1818 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1819 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1820 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1822 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1824 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1826 #define OPTION_MASK_ISA_SSE4A_UNSET \
1827 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1829 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1831 /* Vectorization library interface and handlers. */
1832 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1833 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1834 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1836 /* Implement TARGET_HANDLE_OPTION. */
1839 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1846 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1847 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1851 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1852 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1859 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1860 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1864 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1865 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1875 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1876 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1880 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1881 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1888 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1889 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1893 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1894 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1901 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1902 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1906 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1907 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1914 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1915 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1919 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1920 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1927 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1928 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1932 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1933 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1940 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1941 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1945 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1946 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1951 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1952 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1956 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1957 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1963 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1964 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1968 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1969 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1976 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1977 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1981 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1982 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1991 /* Sometimes certain combinations of command options do not make
1992 sense on a particular target machine. You can define a macro
1993 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1994 defined, is executed once just after all the command options have
1997 Don't use this macro to turn on various extra optimizations for
1998 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2001 override_options (void)
2004 int ix86_tune_defaulted = 0;
2005 int ix86_arch_specified = 0;
2006 unsigned int ix86_arch_mask, ix86_tune_mask;
2008 /* Comes from final.c -- no real reason to change it. */
2009 #define MAX_CODE_ALIGN 16
2013 const struct processor_costs *cost; /* Processor costs */
2014 const int align_loop; /* Default alignments. */
2015 const int align_loop_max_skip;
2016 const int align_jump;
2017 const int align_jump_max_skip;
2018 const int align_func;
2020 const processor_target_table[PROCESSOR_max] =
2022 {&i386_cost, 4, 3, 4, 3, 4},
2023 {&i486_cost, 16, 15, 16, 15, 16},
2024 {&pentium_cost, 16, 7, 16, 7, 16},
2025 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2026 {&geode_cost, 0, 0, 0, 0, 0},
2027 {&k6_cost, 32, 7, 32, 7, 32},
2028 {&athlon_cost, 16, 7, 16, 7, 16},
2029 {&pentium4_cost, 0, 0, 0, 0, 0},
2030 {&k8_cost, 16, 7, 16, 7, 16},
2031 {&nocona_cost, 0, 0, 0, 0, 0},
2032 {&core2_cost, 16, 10, 16, 10, 16},
2033 {&generic32_cost, 16, 7, 16, 7, 16},
2034 {&generic64_cost, 16, 10, 16, 10, 16},
2035 {&amdfam10_cost, 32, 24, 32, 7, 32}
2038 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2069 PTA_PREFETCH_SSE = 1 << 4,
2071 PTA_3DNOW_A = 1 << 6,
2075 PTA_POPCNT = 1 << 10,
2077 PTA_SSE4A = 1 << 12,
2078 PTA_NO_SAHF = 1 << 13,
2079 PTA_SSE4_1 = 1 << 14,
2080 PTA_SSE4_2 = 1 << 15,
2086 const char *const name; /* processor name or nickname. */
2087 const enum processor_type processor;
2088 const unsigned /*enum pta_flags*/ flags;
2090 const processor_alias_table[] =
2092 {"i386", PROCESSOR_I386, 0},
2093 {"i486", PROCESSOR_I486, 0},
2094 {"i586", PROCESSOR_PENTIUM, 0},
2095 {"pentium", PROCESSOR_PENTIUM, 0},
2096 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2097 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2098 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2099 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2100 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2101 {"i686", PROCESSOR_PENTIUMPRO, 0},
2102 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2103 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2104 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2105 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2106 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2107 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2108 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2109 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2110 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2111 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2112 | PTA_CX16 | PTA_NO_SAHF)},
2113 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2114 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2117 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2118 |PTA_PREFETCH_SSE)},
2119 {"k6", PROCESSOR_K6, PTA_MMX},
2120 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2121 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2122 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2123 | PTA_PREFETCH_SSE)},
2124 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2125 | PTA_PREFETCH_SSE)},
2126 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2128 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2130 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2132 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2133 | PTA_MMX | PTA_SSE | PTA_SSE2
2135 {"k8", PROCESSOR_K8, (PTA_64BIT
2136 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2137 | PTA_SSE | PTA_SSE2
2139 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2140 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2141 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2143 {"opteron", PROCESSOR_K8, (PTA_64BIT
2144 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2145 | PTA_SSE | PTA_SSE2
2147 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2148 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2149 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2151 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2152 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2153 | PTA_SSE | PTA_SSE2
2155 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2156 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2157 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2159 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2160 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2161 | PTA_SSE | PTA_SSE2
2163 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2164 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2165 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2167 | PTA_CX16 | PTA_ABM)},
2168 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2169 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2170 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2172 | PTA_CX16 | PTA_ABM)},
2173 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2174 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2177 int const pta_size = ARRAY_SIZE (processor_alias_table);
2179 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2180 SUBTARGET_OVERRIDE_OPTIONS;
2183 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2184 SUBSUBTARGET_OVERRIDE_OPTIONS;
2187 /* -fPIC is the default for x86_64. */
2188 if (TARGET_MACHO && TARGET_64BIT)
2191 /* Set the default values for switches whose default depends on TARGET_64BIT
2192 in case they weren't overwritten by command line options. */
2195 /* Mach-O doesn't support omitting the frame pointer for now. */
2196 if (flag_omit_frame_pointer == 2)
2197 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2198 if (flag_asynchronous_unwind_tables == 2)
2199 flag_asynchronous_unwind_tables = 1;
2200 if (flag_pcc_struct_return == 2)
2201 flag_pcc_struct_return = 0;
2205 if (flag_omit_frame_pointer == 2)
2206 flag_omit_frame_pointer = 0;
2207 if (flag_asynchronous_unwind_tables == 2)
2208 flag_asynchronous_unwind_tables = 0;
2209 if (flag_pcc_struct_return == 2)
2210 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2213 /* Need to check -mtune=generic first. */
2214 if (ix86_tune_string)
2216 if (!strcmp (ix86_tune_string, "generic")
2217 || !strcmp (ix86_tune_string, "i686")
2218 /* As special support for cross compilers we read -mtune=native
2219 as -mtune=generic. With native compilers we won't see the
2220 -mtune=native, as it was changed by the driver. */
2221 || !strcmp (ix86_tune_string, "native"))
2224 ix86_tune_string = "generic64";
2226 ix86_tune_string = "generic32";
2228 else if (!strncmp (ix86_tune_string, "generic", 7))
2229 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2233 if (ix86_arch_string)
2234 ix86_tune_string = ix86_arch_string;
2235 if (!ix86_tune_string)
2237 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2238 ix86_tune_defaulted = 1;
2241 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2242 need to use a sensible tune option. */
2243 if (!strcmp (ix86_tune_string, "generic")
2244 || !strcmp (ix86_tune_string, "x86-64")
2245 || !strcmp (ix86_tune_string, "i686"))
2248 ix86_tune_string = "generic64";
2250 ix86_tune_string = "generic32";
2253 if (ix86_stringop_string)
2255 if (!strcmp (ix86_stringop_string, "rep_byte"))
2256 stringop_alg = rep_prefix_1_byte;
2257 else if (!strcmp (ix86_stringop_string, "libcall"))
2258 stringop_alg = libcall;
2259 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2260 stringop_alg = rep_prefix_4_byte;
2261 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2262 stringop_alg = rep_prefix_8_byte;
2263 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2264 stringop_alg = loop_1_byte;
2265 else if (!strcmp (ix86_stringop_string, "loop"))
2266 stringop_alg = loop;
2267 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2268 stringop_alg = unrolled_loop;
2270 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2272 if (!strcmp (ix86_tune_string, "x86-64"))
2273 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2274 "-mtune=generic instead as appropriate.");
2276 if (!ix86_arch_string)
2277 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2279 ix86_arch_specified = 1;
2281 if (!strcmp (ix86_arch_string, "generic"))
2282 error ("generic CPU can be used only for -mtune= switch");
2283 if (!strncmp (ix86_arch_string, "generic", 7))
2284 error ("bad value (%s) for -march= switch", ix86_arch_string);
2286 if (ix86_cmodel_string != 0)
2288 if (!strcmp (ix86_cmodel_string, "small"))
2289 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2290 else if (!strcmp (ix86_cmodel_string, "medium"))
2291 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2292 else if (!strcmp (ix86_cmodel_string, "large"))
2293 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2295 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2296 else if (!strcmp (ix86_cmodel_string, "32"))
2297 ix86_cmodel = CM_32;
2298 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2299 ix86_cmodel = CM_KERNEL;
2301 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2305 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2306 use of rip-relative addressing. This eliminates fixups that
2307 would otherwise be needed if this object is to be placed in a
2308 DLL, and is essentially just as efficient as direct addressing. */
2309 if (TARGET_64BIT_MS_ABI)
2310 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2311 else if (TARGET_64BIT)
2312 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2314 ix86_cmodel = CM_32;
2316 if (ix86_asm_string != 0)
2319 && !strcmp (ix86_asm_string, "intel"))
2320 ix86_asm_dialect = ASM_INTEL;
2321 else if (!strcmp (ix86_asm_string, "att"))
2322 ix86_asm_dialect = ASM_ATT;
2324 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2326 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2327 error ("code model %qs not supported in the %s bit mode",
2328 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2329 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2330 sorry ("%i-bit mode not compiled in",
2331 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2333 for (i = 0; i < pta_size; i++)
2334 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2336 ix86_arch = processor_alias_table[i].processor;
2337 /* Default cpu tuning to the architecture. */
2338 ix86_tune = ix86_arch;
2340 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2341 error ("CPU you selected does not support x86-64 "
2344 if (processor_alias_table[i].flags & PTA_MMX
2345 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2346 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2347 if (processor_alias_table[i].flags & PTA_3DNOW
2348 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2349 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2350 if (processor_alias_table[i].flags & PTA_3DNOW_A
2351 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2352 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2353 if (processor_alias_table[i].flags & PTA_SSE
2354 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2355 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2356 if (processor_alias_table[i].flags & PTA_SSE2
2357 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2358 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2359 if (processor_alias_table[i].flags & PTA_SSE3
2360 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2361 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2362 if (processor_alias_table[i].flags & PTA_SSSE3
2363 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2364 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2365 if (processor_alias_table[i].flags & PTA_SSE4_1
2366 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2367 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2368 if (processor_alias_table[i].flags & PTA_SSE4_2
2369 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2370 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2371 if (processor_alias_table[i].flags & PTA_SSE4A
2372 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2373 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2374 if (processor_alias_table[i].flags & PTA_SSE5
2375 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2376 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2378 if (processor_alias_table[i].flags & PTA_ABM)
2380 if (processor_alias_table[i].flags & PTA_CX16)
2381 x86_cmpxchg16b = true;
2382 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2384 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2385 x86_prefetch_sse = true;
2386 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2393 error ("bad value (%s) for -march= switch", ix86_arch_string);
2395 ix86_arch_mask = 1u << ix86_arch;
2396 for (i = 0; i < X86_ARCH_LAST; ++i)
2397 ix86_arch_features[i] &= ix86_arch_mask;
2399 for (i = 0; i < pta_size; i++)
2400 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2402 ix86_tune = processor_alias_table[i].processor;
2403 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2405 if (ix86_tune_defaulted)
2407 ix86_tune_string = "x86-64";
2408 for (i = 0; i < pta_size; i++)
2409 if (! strcmp (ix86_tune_string,
2410 processor_alias_table[i].name))
2412 ix86_tune = processor_alias_table[i].processor;
2415 error ("CPU you selected does not support x86-64 "
2418 /* Intel CPUs have always interpreted SSE prefetch instructions as
2419 NOPs; so, we can enable SSE prefetch instructions even when
2420 -mtune (rather than -march) points us to a processor that has them.
2421 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2422 higher processors. */
2424 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2425 x86_prefetch_sse = true;
2429 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2431 ix86_tune_mask = 1u << ix86_tune;
2432 for (i = 0; i < X86_TUNE_LAST; ++i)
2433 ix86_tune_features[i] &= ix86_tune_mask;
2436 ix86_cost = &size_cost;
2438 ix86_cost = processor_target_table[ix86_tune].cost;
2440 /* Arrange to set up i386_stack_locals for all functions. */
2441 init_machine_status = ix86_init_machine_status;
2443 /* Validate -mregparm= value. */
2444 if (ix86_regparm_string)
2447 warning (0, "-mregparm is ignored in 64-bit mode");
2448 i = atoi (ix86_regparm_string);
2449 if (i < 0 || i > REGPARM_MAX)
2450 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2455 ix86_regparm = REGPARM_MAX;
2457 /* If the user has provided any of the -malign-* options,
2458 warn and use that value only if -falign-* is not set.
2459 Remove this code in GCC 3.2 or later. */
2460 if (ix86_align_loops_string)
2462 warning (0, "-malign-loops is obsolete, use -falign-loops");
2463 if (align_loops == 0)
2465 i = atoi (ix86_align_loops_string);
2466 if (i < 0 || i > MAX_CODE_ALIGN)
2467 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2469 align_loops = 1 << i;
2473 if (ix86_align_jumps_string)
2475 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2476 if (align_jumps == 0)
2478 i = atoi (ix86_align_jumps_string);
2479 if (i < 0 || i > MAX_CODE_ALIGN)
2480 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2482 align_jumps = 1 << i;
2486 if (ix86_align_funcs_string)
2488 warning (0, "-malign-functions is obsolete, use -falign-functions");
2489 if (align_functions == 0)
2491 i = atoi (ix86_align_funcs_string);
2492 if (i < 0 || i > MAX_CODE_ALIGN)
2493 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2495 align_functions = 1 << i;
2499 /* Default align_* from the processor table. */
2500 if (align_loops == 0)
2502 align_loops = processor_target_table[ix86_tune].align_loop;
2503 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2505 if (align_jumps == 0)
2507 align_jumps = processor_target_table[ix86_tune].align_jump;
2508 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2510 if (align_functions == 0)
2512 align_functions = processor_target_table[ix86_tune].align_func;
2515 /* Validate -mbranch-cost= value, or provide default. */
2516 ix86_branch_cost = ix86_cost->branch_cost;
2517 if (ix86_branch_cost_string)
2519 i = atoi (ix86_branch_cost_string);
2521 error ("-mbranch-cost=%d is not between 0 and 5", i);
2523 ix86_branch_cost = i;
2525 if (ix86_section_threshold_string)
2527 i = atoi (ix86_section_threshold_string);
2529 error ("-mlarge-data-threshold=%d is negative", i);
2531 ix86_section_threshold = i;
2534 if (ix86_tls_dialect_string)
2536 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2537 ix86_tls_dialect = TLS_DIALECT_GNU;
2538 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2539 ix86_tls_dialect = TLS_DIALECT_GNU2;
2540 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2541 ix86_tls_dialect = TLS_DIALECT_SUN;
2543 error ("bad value (%s) for -mtls-dialect= switch",
2544 ix86_tls_dialect_string);
2547 if (ix87_precision_string)
2549 i = atoi (ix87_precision_string);
2550 if (i != 32 && i != 64 && i != 80)
2551 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2556 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2558 /* Enable by default the SSE and MMX builtins. Do allow the user to
2559 explicitly disable any of these. In particular, disabling SSE and
2560 MMX for kernel code is extremely useful. */
2561 if (!ix86_arch_specified)
2563 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2564 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2567 warning (0, "-mrtd is ignored in 64bit mode");
2571 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2573 if (!ix86_arch_specified)
2575 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2577 /* i386 ABI does not specify red zone. It still makes sense to use it
2578 when programmer takes care to stack from being destroyed. */
2579 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2580 target_flags |= MASK_NO_RED_ZONE;
2583 /* Keep nonleaf frame pointers. */
2584 if (flag_omit_frame_pointer)
2585 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2586 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2587 flag_omit_frame_pointer = 1;
2589 /* If we're doing fast math, we don't care about comparison order
2590 wrt NaNs. This lets us use a shorter comparison sequence. */
2591 if (flag_finite_math_only)
2592 target_flags &= ~MASK_IEEE_FP;
2594 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2595 since the insns won't need emulation. */
2596 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2597 target_flags &= ~MASK_NO_FANCY_MATH_387;
2599 /* Likewise, if the target doesn't have a 387, or we've specified
2600 software floating point, don't use 387 inline intrinsics. */
2602 target_flags |= MASK_NO_FANCY_MATH_387;
2604 /* Turn on MMX builtins for -msse. */
2607 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2608 x86_prefetch_sse = true;
2611 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2612 if (TARGET_SSE4_2 || TARGET_ABM)
2615 /* Validate -mpreferred-stack-boundary= value, or provide default.
2616 The default of 128 bits is for Pentium III's SSE __m128. We can't
2617 change it because of optimize_size. Otherwise, we can't mix object
2618 files compiled with -Os and -On. */
2619 ix86_preferred_stack_boundary = 128;
2620 if (ix86_preferred_stack_boundary_string)
2622 i = atoi (ix86_preferred_stack_boundary_string);
2623 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2624 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2625 TARGET_64BIT ? 4 : 2);
2627 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2630 /* Accept -msseregparm only if at least SSE support is enabled. */
2631 if (TARGET_SSEREGPARM
2633 error ("-msseregparm used without SSE enabled");
2635 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2636 if (ix86_fpmath_string != 0)
2638 if (! strcmp (ix86_fpmath_string, "387"))
2639 ix86_fpmath = FPMATH_387;
2640 else if (! strcmp (ix86_fpmath_string, "sse"))
2644 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2645 ix86_fpmath = FPMATH_387;
2648 ix86_fpmath = FPMATH_SSE;
2650 else if (! strcmp (ix86_fpmath_string, "387,sse")
2651 || ! strcmp (ix86_fpmath_string, "sse,387"))
2655 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2656 ix86_fpmath = FPMATH_387;
2658 else if (!TARGET_80387)
2660 warning (0, "387 instruction set disabled, using SSE arithmetics");
2661 ix86_fpmath = FPMATH_SSE;
2664 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2667 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2670 /* If the i387 is disabled, then do not return values in it. */
2672 target_flags &= ~MASK_FLOAT_RETURNS;
2674 /* Use external vectorized library in vectorizing intrinsics. */
2675 if (ix86_veclibabi_string)
2677 if (strcmp (ix86_veclibabi_string, "svml") == 0)
2678 ix86_veclib_handler = ix86_veclibabi_svml;
2679 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
2680 ix86_veclib_handler = ix86_veclibabi_acml;
2682 error ("unknown vectorization library ABI type (%s) for "
2683 "-mveclibabi= switch", ix86_veclibabi_string);
2686 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2687 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2689 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2691 /* ??? Unwind info is not correct around the CFG unless either a frame
2692 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2693 unwind info generation to be aware of the CFG and propagating states
2695 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2696 || flag_exceptions || flag_non_call_exceptions)
2697 && flag_omit_frame_pointer
2698 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2700 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2701 warning (0, "unwind tables currently require either a frame pointer "
2702 "or -maccumulate-outgoing-args for correctness");
2703 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2706 /* If stack probes are required, the space used for large function
2707 arguments on the stack must also be probed, so enable
2708 -maccumulate-outgoing-args so this happens in the prologue. */
2709 if (TARGET_STACK_PROBE
2710 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2712 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2713 warning (0, "stack probing requires -maccumulate-outgoing-args "
2715 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2718 /* For sane SSE instruction set generation we need fcomi instruction.
2719 It is safe to enable all CMOVE instructions. */
2723 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2726 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2727 p = strchr (internal_label_prefix, 'X');
2728 internal_label_prefix_len = p - internal_label_prefix;
2732 /* When scheduling description is not available, disable scheduler pass
2733 so it won't slow down the compilation and make x87 code slower. */
2734 if (!TARGET_SCHEDULE)
2735 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2737 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2738 set_param_value ("simultaneous-prefetches",
2739 ix86_cost->simultaneous_prefetches);
2740 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2741 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2742 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2743 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2744 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2745 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2747 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2748 can be optimized to ap = __builtin_next_arg (0). */
2749 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
2750 targetm.expand_builtin_va_start = NULL;
2753 /* Return true if this goes in large data/bss. */
2756 ix86_in_large_data_p (tree exp)
2758 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2761 /* Functions are never large data. */
2762 if (TREE_CODE (exp) == FUNCTION_DECL)
2765 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2767 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2768 if (strcmp (section, ".ldata") == 0
2769 || strcmp (section, ".lbss") == 0)
2775 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2777 /* If this is an incomplete type with size 0, then we can't put it
2778 in data because it might be too big when completed. */
2779 if (!size || size > ix86_section_threshold)
2786 /* Switch to the appropriate section for output of DECL.
2787 DECL is either a `VAR_DECL' node or a constant of some sort.
2788 RELOC indicates whether forming the initial value of DECL requires
2789 link-time relocations. */
2791 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2795 x86_64_elf_select_section (tree decl, int reloc,
2796 unsigned HOST_WIDE_INT align)
2798 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2799 && ix86_in_large_data_p (decl))
2801 const char *sname = NULL;
2802 unsigned int flags = SECTION_WRITE;
2803 switch (categorize_decl_for_section (decl, reloc))
2808 case SECCAT_DATA_REL:
2809 sname = ".ldata.rel";
2811 case SECCAT_DATA_REL_LOCAL:
2812 sname = ".ldata.rel.local";
2814 case SECCAT_DATA_REL_RO:
2815 sname = ".ldata.rel.ro";
2817 case SECCAT_DATA_REL_RO_LOCAL:
2818 sname = ".ldata.rel.ro.local";
2822 flags |= SECTION_BSS;
2825 case SECCAT_RODATA_MERGE_STR:
2826 case SECCAT_RODATA_MERGE_STR_INIT:
2827 case SECCAT_RODATA_MERGE_CONST:
2831 case SECCAT_SRODATA:
2838 /* We don't split these for medium model. Place them into
2839 default sections and hope for best. */
2844 /* We might get called with string constants, but get_named_section
2845 doesn't like them as they are not DECLs. Also, we need to set
2846 flags in that case. */
2848 return get_section (sname, flags, NULL);
2849 return get_named_section (decl, sname, reloc);
2852 return default_elf_select_section (decl, reloc, align);
2855 /* Build up a unique section name, expressed as a
2856 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2857 RELOC indicates whether the initial value of EXP requires
2858 link-time relocations. */
2860 static void ATTRIBUTE_UNUSED
2861 x86_64_elf_unique_section (tree decl, int reloc)
2863 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2864 && ix86_in_large_data_p (decl))
2866 const char *prefix = NULL;
2867 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2868 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2870 switch (categorize_decl_for_section (decl, reloc))
2873 case SECCAT_DATA_REL:
2874 case SECCAT_DATA_REL_LOCAL:
2875 case SECCAT_DATA_REL_RO:
2876 case SECCAT_DATA_REL_RO_LOCAL:
2877 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2880 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2883 case SECCAT_RODATA_MERGE_STR:
2884 case SECCAT_RODATA_MERGE_STR_INIT:
2885 case SECCAT_RODATA_MERGE_CONST:
2886 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2888 case SECCAT_SRODATA:
2895 /* We don't split these for medium model. Place them into
2896 default sections and hope for best. */
2904 plen = strlen (prefix);
2906 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2907 name = targetm.strip_name_encoding (name);
2908 nlen = strlen (name);
2910 string = (char *) alloca (nlen + plen + 1);
2911 memcpy (string, prefix, plen);
2912 memcpy (string + plen, name, nlen + 1);
2914 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2918 default_unique_section (decl, reloc);
2921 #ifdef COMMON_ASM_OP
2922 /* This says how to output assembler code to declare an
2923 uninitialized external linkage data object.
2925 For medium model x86-64 we need to use .largecomm opcode for
2928 x86_elf_aligned_common (FILE *file,
2929 const char *name, unsigned HOST_WIDE_INT size,
2932 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2933 && size > (unsigned int)ix86_section_threshold)
2934 fprintf (file, ".largecomm\t");
2936 fprintf (file, "%s", COMMON_ASM_OP);
2937 assemble_name (file, name);
2938 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2939 size, align / BITS_PER_UNIT);
2943 /* Utility function for targets to use in implementing
2944 ASM_OUTPUT_ALIGNED_BSS. */
2947 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2948 const char *name, unsigned HOST_WIDE_INT size,
2951 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2952 && size > (unsigned int)ix86_section_threshold)
2953 switch_to_section (get_named_section (decl, ".lbss", 0));
2955 switch_to_section (bss_section);
2956 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2957 #ifdef ASM_DECLARE_OBJECT_NAME
2958 last_assemble_variable_decl = decl;
2959 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2961 /* Standard thing is just output label for the object. */
2962 ASM_OUTPUT_LABEL (file, name);
2963 #endif /* ASM_DECLARE_OBJECT_NAME */
2964 ASM_OUTPUT_SKIP (file, size ? size : 1);
2968 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2970 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2971 make the problem with not enough registers even worse. */
2972 #ifdef INSN_SCHEDULING
2974 flag_schedule_insns = 0;
2978 /* The Darwin libraries never set errno, so we might as well
2979 avoid calling them when that's the only reason we would. */
2980 flag_errno_math = 0;
2982 /* The default values of these switches depend on the TARGET_64BIT
2983 that is not known at this moment. Mark these values with 2 and
2984 let user the to override these. In case there is no command line option
2985 specifying them, we will set the defaults in override_options. */
2987 flag_omit_frame_pointer = 2;
2988 flag_pcc_struct_return = 2;
2989 flag_asynchronous_unwind_tables = 2;
2990 flag_vect_cost_model = 1;
2991 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2992 SUBTARGET_OPTIMIZATION_OPTIONS;
2996 /* Decide whether we can make a sibling call to a function. DECL is the
2997 declaration of the function being targeted by the call and EXP is the
2998 CALL_EXPR representing the call. */
3001 ix86_function_ok_for_sibcall (tree decl, tree exp)
3006 /* If we are generating position-independent code, we cannot sibcall
3007 optimize any indirect call, or a direct call to a global function,
3008 as the PLT requires %ebx be live. */
3009 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3016 func = TREE_TYPE (CALL_EXPR_FN (exp));
3017 if (POINTER_TYPE_P (func))
3018 func = TREE_TYPE (func);
3021 /* Check that the return value locations are the same. Like
3022 if we are returning floats on the 80387 register stack, we cannot
3023 make a sibcall from a function that doesn't return a float to a
3024 function that does or, conversely, from a function that does return
3025 a float to a function that doesn't; the necessary stack adjustment
3026 would not be executed. This is also the place we notice
3027 differences in the return value ABI. Note that it is ok for one
3028 of the functions to have void return type as long as the return
3029 value of the other is passed in a register. */
3030 a = ix86_function_value (TREE_TYPE (exp), func, false);
3031 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3033 if (STACK_REG_P (a) || STACK_REG_P (b))
3035 if (!rtx_equal_p (a, b))
3038 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3040 else if (!rtx_equal_p (a, b))
3043 /* If this call is indirect, we'll need to be able to use a call-clobbered
3044 register for the address of the target function. Make sure that all
3045 such registers are not used for passing parameters. */
3046 if (!decl && !TARGET_64BIT)
3050 /* We're looking at the CALL_EXPR, we need the type of the function. */
3051 type = CALL_EXPR_FN (exp); /* pointer expression */
3052 type = TREE_TYPE (type); /* pointer type */
3053 type = TREE_TYPE (type); /* function type */
3055 if (ix86_function_regparm (type, NULL) >= 3)
3057 /* ??? Need to count the actual number of registers to be used,
3058 not the possible number of registers. Fix later. */
3063 /* Dllimport'd functions are also called indirectly. */
3064 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3065 && decl && DECL_DLLIMPORT_P (decl)
3066 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3069 /* If we forced aligned the stack, then sibcalling would unalign the
3070 stack, which may break the called function. */
3071 if (cfun->machine->force_align_arg_pointer)
3074 /* Otherwise okay. That also includes certain types of indirect calls. */
3078 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3079 calling convention attributes;
3080 arguments as in struct attribute_spec.handler. */
3083 ix86_handle_cconv_attribute (tree *node, tree name,
3085 int flags ATTRIBUTE_UNUSED,
3088 if (TREE_CODE (*node) != FUNCTION_TYPE
3089 && TREE_CODE (*node) != METHOD_TYPE
3090 && TREE_CODE (*node) != FIELD_DECL
3091 && TREE_CODE (*node) != TYPE_DECL)
3093 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3094 IDENTIFIER_POINTER (name));
3095 *no_add_attrs = true;
3099 /* Can combine regparm with all attributes but fastcall. */
3100 if (is_attribute_p ("regparm", name))
3104 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3106 error ("fastcall and regparm attributes are not compatible");
3109 cst = TREE_VALUE (args);
3110 if (TREE_CODE (cst) != INTEGER_CST)
3112 warning (OPT_Wattributes,
3113 "%qs attribute requires an integer constant argument",
3114 IDENTIFIER_POINTER (name));
3115 *no_add_attrs = true;
3117 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3119 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3120 IDENTIFIER_POINTER (name), REGPARM_MAX);
3121 *no_add_attrs = true;
3125 && lookup_attribute (ix86_force_align_arg_pointer_string,
3126 TYPE_ATTRIBUTES (*node))
3127 && compare_tree_int (cst, REGPARM_MAX-1))
3129 error ("%s functions limited to %d register parameters",
3130 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3138 /* Do not warn when emulating the MS ABI. */
3139 if (!TARGET_64BIT_MS_ABI)
3140 warning (OPT_Wattributes, "%qs attribute ignored",
3141 IDENTIFIER_POINTER (name));
3142 *no_add_attrs = true;
3146 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3147 if (is_attribute_p ("fastcall", name))
3149 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3151 error ("fastcall and cdecl attributes are not compatible");
3153 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3155 error ("fastcall and stdcall attributes are not compatible");
3157 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3159 error ("fastcall and regparm attributes are not compatible");
3163 /* Can combine stdcall with fastcall (redundant), regparm and
3165 else if (is_attribute_p ("stdcall", name))
3167 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3169 error ("stdcall and cdecl attributes are not compatible");
3171 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3173 error ("stdcall and fastcall attributes are not compatible");
3177 /* Can combine cdecl with regparm and sseregparm. */
3178 else if (is_attribute_p ("cdecl", name))
3180 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3182 error ("stdcall and cdecl attributes are not compatible");
3184 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3186 error ("fastcall and cdecl attributes are not compatible");
3190 /* Can combine sseregparm with all attributes. */
3195 /* Return 0 if the attributes for two types are incompatible, 1 if they
3196 are compatible, and 2 if they are nearly compatible (which causes a
3197 warning to be generated). */
3200 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3202 /* Check for mismatch of non-default calling convention. */
3203 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3205 if (TREE_CODE (type1) != FUNCTION_TYPE
3206 && TREE_CODE (type1) != METHOD_TYPE)
3209 /* Check for mismatched fastcall/regparm types. */
3210 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3211 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3212 || (ix86_function_regparm (type1, NULL)
3213 != ix86_function_regparm (type2, NULL)))
3216 /* Check for mismatched sseregparm types. */
3217 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3218 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3221 /* Check for mismatched return types (cdecl vs stdcall). */
3222 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3223 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3229 /* Return the regparm value for a function with the indicated TYPE and DECL.
3230 DECL may be NULL when calling function indirectly
3231 or considering a libcall. */
3234 ix86_function_regparm (const_tree type, const_tree decl)
3237 int regparm = ix86_regparm;
3242 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3244 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3246 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3249 /* Use register calling convention for local functions when possible. */
3250 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3251 && flag_unit_at_a_time && !profile_flag)
3253 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3254 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3257 int local_regparm, globals = 0, regno;
3260 /* Make sure no regparm register is taken by a
3261 fixed register variable. */
3262 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3263 if (fixed_regs[local_regparm])
3266 /* We can't use regparm(3) for nested functions as these use
3267 static chain pointer in third argument. */
3268 if (local_regparm == 3
3269 && (decl_function_context (decl)
3270 || ix86_force_align_arg_pointer)
3271 && !DECL_NO_STATIC_CHAIN (decl))
3274 /* If the function realigns its stackpointer, the prologue will
3275 clobber %ecx. If we've already generated code for the callee,
3276 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3277 scanning the attributes for the self-realigning property. */
3278 f = DECL_STRUCT_FUNCTION (decl);
3279 if (local_regparm == 3
3280 && (f ? !!f->machine->force_align_arg_pointer
3281 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3282 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3285 /* Each fixed register usage increases register pressure,
3286 so less registers should be used for argument passing.
3287 This functionality can be overriden by an explicit
3289 for (regno = 0; regno <= DI_REG; regno++)
3290 if (fixed_regs[regno])
3294 = globals < local_regparm ? local_regparm - globals : 0;
3296 if (local_regparm > regparm)
3297 regparm = local_regparm;
3304 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3305 DFmode (2) arguments in SSE registers for a function with the
3306 indicated TYPE and DECL. DECL may be NULL when calling function
3307 indirectly or considering a libcall. Otherwise return 0. */
3310 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3312 gcc_assert (!TARGET_64BIT);
3314 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3315 by the sseregparm attribute. */
3316 if (TARGET_SSEREGPARM
3317 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3324 error ("Calling %qD with attribute sseregparm without "
3325 "SSE/SSE2 enabled", decl);
3327 error ("Calling %qT with attribute sseregparm without "
3328 "SSE/SSE2 enabled", type);
3336 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3337 (and DFmode for SSE2) arguments in SSE registers. */
3338 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3340 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3341 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3343 return TARGET_SSE2 ? 2 : 1;
3349 /* Return true if EAX is live at the start of the function. Used by
3350 ix86_expand_prologue to determine if we need special help before
3351 calling allocate_stack_worker. */
3354 ix86_eax_live_at_start_p (void)
3356 /* Cheat. Don't bother working forward from ix86_function_regparm
3357 to the function type to whether an actual argument is located in
3358 eax. Instead just look at cfg info, which is still close enough
3359 to correct at this point. This gives false positives for broken
3360 functions that might use uninitialized data that happens to be
3361 allocated in eax, but who cares? */
3362 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3365 /* Value is the number of bytes of arguments automatically
3366 popped when returning from a subroutine call.
3367 FUNDECL is the declaration node of the function (as a tree),
3368 FUNTYPE is the data type of the function (as a tree),
3369 or for a library call it is an identifier node for the subroutine name.
3370 SIZE is the number of bytes of arguments passed on the stack.
3372 On the 80386, the RTD insn may be used to pop them if the number
3373 of args is fixed, but if the number is variable then the caller
3374 must pop them all. RTD can't be used for library calls now
3375 because the library is compiled with the Unix compiler.
3376 Use of RTD is a selectable option, since it is incompatible with
3377 standard Unix calling sequences. If the option is not selected,
3378 the caller must always pop the args.
3380 The attribute stdcall is equivalent to RTD on a per module basis. */
3383 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3387 /* None of the 64-bit ABIs pop arguments. */
3391 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3393 /* Cdecl functions override -mrtd, and never pop the stack. */
3394 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3396 /* Stdcall and fastcall functions will pop the stack if not
3398 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3399 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3402 if (rtd && ! stdarg_p (funtype))
3406 /* Lose any fake structure return argument if it is passed on the stack. */
3407 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3408 && !KEEP_AGGREGATE_RETURN_POINTER)
3410 int nregs = ix86_function_regparm (funtype, fundecl);
3412 return GET_MODE_SIZE (Pmode);
3418 /* Argument support functions. */
3420 /* Return true when register may be used to pass function parameters. */
3422 ix86_function_arg_regno_p (int regno)
3425 const int *parm_regs;
3430 return (regno < REGPARM_MAX
3431 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3433 return (regno < REGPARM_MAX
3434 || (TARGET_MMX && MMX_REGNO_P (regno)
3435 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3436 || (TARGET_SSE && SSE_REGNO_P (regno)
3437 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3442 if (SSE_REGNO_P (regno) && TARGET_SSE)
3447 if (TARGET_SSE && SSE_REGNO_P (regno)
3448 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3452 /* RAX is used as hidden argument to va_arg functions. */
3453 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3456 if (TARGET_64BIT_MS_ABI)
3457 parm_regs = x86_64_ms_abi_int_parameter_registers;
3459 parm_regs = x86_64_int_parameter_registers;
3460 for (i = 0; i < REGPARM_MAX; i++)
3461 if (regno == parm_regs[i])
3466 /* Return if we do not know how to pass TYPE solely in registers. */
3469 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3471 if (must_pass_in_stack_var_size_or_pad (mode, type))
3474 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3475 The layout_type routine is crafty and tries to trick us into passing
3476 currently unsupported vector types on the stack by using TImode. */
3477 return (!TARGET_64BIT && mode == TImode
3478 && type && TREE_CODE (type) != VECTOR_TYPE);
3481 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3482 for a call to a function whose data type is FNTYPE.
3483 For a library call, FNTYPE is 0. */
3486 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3487 tree fntype, /* tree ptr for function decl */
3488 rtx libname, /* SYMBOL_REF of library name or 0 */
3491 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3492 memset (cum, 0, sizeof (*cum));
3494 /* Set up the number of registers to use for passing arguments. */
3495 cum->nregs = ix86_regparm;
3497 cum->sse_nregs = SSE_REGPARM_MAX;
3499 cum->mmx_nregs = MMX_REGPARM_MAX;
3500 cum->warn_sse = true;
3501 cum->warn_mmx = true;
3503 /* Because type might mismatch in between caller and callee, we need to
3504 use actual type of function for local calls.
3505 FIXME: cgraph_analyze can be told to actually record if function uses
3506 va_start so for local functions maybe_vaarg can be made aggressive
3508 FIXME: once typesytem is fixed, we won't need this code anymore. */
3510 fntype = TREE_TYPE (fndecl);
3511 cum->maybe_vaarg = (fntype
3512 ? (!prototype_p (fntype) || stdarg_p (fntype))
3517 /* If there are variable arguments, then we won't pass anything
3518 in registers in 32-bit mode. */
3519 if (cum->maybe_vaarg)
3529 /* Use ecx and edx registers if function has fastcall attribute,
3530 else look for regparm information. */
3533 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3539 cum->nregs = ix86_function_regparm (fntype, fndecl);
3542 /* Set up the number of SSE registers used for passing SFmode
3543 and DFmode arguments. Warn for mismatching ABI. */
3544 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3548 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3549 But in the case of vector types, it is some vector mode.
3551 When we have only some of our vector isa extensions enabled, then there
3552 are some modes for which vector_mode_supported_p is false. For these
3553 modes, the generic vector support in gcc will choose some non-vector mode
3554 in order to implement the type. By computing the natural mode, we'll
3555 select the proper ABI location for the operand and not depend on whatever
3556 the middle-end decides to do with these vector types. */
3558 static enum machine_mode
3559 type_natural_mode (const_tree type)
3561 enum machine_mode mode = TYPE_MODE (type);
3563 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3565 HOST_WIDE_INT size = int_size_in_bytes (type);
3566 if ((size == 8 || size == 16)
3567 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3568 && TYPE_VECTOR_SUBPARTS (type) > 1)
3570 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3572 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3573 mode = MIN_MODE_VECTOR_FLOAT;
3575 mode = MIN_MODE_VECTOR_INT;
3577 /* Get the mode which has this inner mode and number of units. */
3578 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3579 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3580 && GET_MODE_INNER (mode) == innermode)
3590 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3591 this may not agree with the mode that the type system has chosen for the
3592 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3593 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3596 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3601 if (orig_mode != BLKmode)
3602 tmp = gen_rtx_REG (orig_mode, regno);
3605 tmp = gen_rtx_REG (mode, regno);
3606 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3607 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3613 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3614 of this code is to classify each 8bytes of incoming argument by the register
3615 class and assign registers accordingly. */
3617 /* Return the union class of CLASS1 and CLASS2.
3618 See the x86-64 PS ABI for details. */
3620 static enum x86_64_reg_class
3621 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3623 /* Rule #1: If both classes are equal, this is the resulting class. */
3624 if (class1 == class2)
3627 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3629 if (class1 == X86_64_NO_CLASS)
3631 if (class2 == X86_64_NO_CLASS)
3634 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3635 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3636 return X86_64_MEMORY_CLASS;
3638 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3639 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3640 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3641 return X86_64_INTEGERSI_CLASS;
3642 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3643 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3644 return X86_64_INTEGER_CLASS;
3646 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3648 if (class1 == X86_64_X87_CLASS
3649 || class1 == X86_64_X87UP_CLASS
3650 || class1 == X86_64_COMPLEX_X87_CLASS
3651 || class2 == X86_64_X87_CLASS
3652 || class2 == X86_64_X87UP_CLASS
3653 || class2 == X86_64_COMPLEX_X87_CLASS)
3654 return X86_64_MEMORY_CLASS;
3656 /* Rule #6: Otherwise class SSE is used. */
3657 return X86_64_SSE_CLASS;
3660 /* Classify the argument of type TYPE and mode MODE.
3661 CLASSES will be filled by the register class used to pass each word
3662 of the operand. The number of words is returned. In case the parameter
3663 should be passed in memory, 0 is returned. As a special case for zero
3664 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3666 BIT_OFFSET is used internally for handling records and specifies offset
3667 of the offset in bits modulo 256 to avoid overflow cases.
3669 See the x86-64 PS ABI for details.
3673 classify_argument (enum machine_mode mode, const_tree type,
3674 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3676 HOST_WIDE_INT bytes =
3677 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3678 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3680 /* Variable sized entities are always passed/returned in memory. */
3684 if (mode != VOIDmode
3685 && targetm.calls.must_pass_in_stack (mode, type))
3688 if (type && AGGREGATE_TYPE_P (type))
3692 enum x86_64_reg_class subclasses[MAX_CLASSES];
3694 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3698 for (i = 0; i < words; i++)
3699 classes[i] = X86_64_NO_CLASS;
3701 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3702 signalize memory class, so handle it as special case. */
3705 classes[0] = X86_64_NO_CLASS;
3709 /* Classify each field of record and merge classes. */
3710 switch (TREE_CODE (type))
3713 /* And now merge the fields of structure. */
3714 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3716 if (TREE_CODE (field) == FIELD_DECL)
3720 if (TREE_TYPE (field) == error_mark_node)
3723 /* Bitfields are always classified as integer. Handle them
3724 early, since later code would consider them to be
3725 misaligned integers. */
3726 if (DECL_BIT_FIELD (field))
3728 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3729 i < ((int_bit_position (field) + (bit_offset % 64))
3730 + tree_low_cst (DECL_SIZE (field), 0)
3733 merge_classes (X86_64_INTEGER_CLASS,
3738 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3739 TREE_TYPE (field), subclasses,
3740 (int_bit_position (field)
3741 + bit_offset) % 256);
3744 for (i = 0; i < num; i++)
3747 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3749 merge_classes (subclasses[i], classes[i + pos]);
3757 /* Arrays are handled as small records. */
3760 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3761 TREE_TYPE (type), subclasses, bit_offset);
3765 /* The partial classes are now full classes. */
3766 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3767 subclasses[0] = X86_64_SSE_CLASS;
3768 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3769 subclasses[0] = X86_64_INTEGER_CLASS;
3771 for (i = 0; i < words; i++)
3772 classes[i] = subclasses[i % num];
3777 case QUAL_UNION_TYPE:
3778 /* Unions are similar to RECORD_TYPE but offset is always 0.
3780 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3782 if (TREE_CODE (field) == FIELD_DECL)
3786 if (TREE_TYPE (field) == error_mark_node)
3789 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3790 TREE_TYPE (field), subclasses,
3794 for (i = 0; i < num; i++)
3795 classes[i] = merge_classes (subclasses[i], classes[i]);
3804 /* Final merger cleanup. */
3805 for (i = 0; i < words; i++)
3807 /* If one class is MEMORY, everything should be passed in
3809 if (classes[i] == X86_64_MEMORY_CLASS)
3812 /* The X86_64_SSEUP_CLASS should be always preceded by
3813 X86_64_SSE_CLASS. */
3814 if (classes[i] == X86_64_SSEUP_CLASS
3815 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3816 classes[i] = X86_64_SSE_CLASS;
3818 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3819 if (classes[i] == X86_64_X87UP_CLASS
3820 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3821 classes[i] = X86_64_SSE_CLASS;
3826 /* Compute alignment needed. We align all types to natural boundaries with
3827 exception of XFmode that is aligned to 64bits. */
3828 if (mode != VOIDmode && mode != BLKmode)
3830 int mode_alignment = GET_MODE_BITSIZE (mode);
3833 mode_alignment = 128;
3834 else if (mode == XCmode)
3835 mode_alignment = 256;
3836 if (COMPLEX_MODE_P (mode))
3837 mode_alignment /= 2;
3838 /* Misaligned fields are always returned in memory. */
3839 if (bit_offset % mode_alignment)
3843 /* for V1xx modes, just use the base mode */
3844 if (VECTOR_MODE_P (mode) && mode != V1DImode
3845 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3846 mode = GET_MODE_INNER (mode);
3848 /* Classification of atomic types. */
3853 classes[0] = X86_64_SSE_CLASS;
3856 classes[0] = X86_64_SSE_CLASS;
3857 classes[1] = X86_64_SSEUP_CLASS;
3866 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3867 classes[0] = X86_64_INTEGERSI_CLASS;
3869 classes[0] = X86_64_INTEGER_CLASS;
3873 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3878 if (!(bit_offset % 64))
3879 classes[0] = X86_64_SSESF_CLASS;
3881 classes[0] = X86_64_SSE_CLASS;
3884 classes[0] = X86_64_SSEDF_CLASS;
3887 classes[0] = X86_64_X87_CLASS;
3888 classes[1] = X86_64_X87UP_CLASS;
3891 classes[0] = X86_64_SSE_CLASS;
3892 classes[1] = X86_64_SSEUP_CLASS;
3895 classes[0] = X86_64_SSE_CLASS;
3898 classes[0] = X86_64_SSEDF_CLASS;
3899 classes[1] = X86_64_SSEDF_CLASS;
3902 classes[0] = X86_64_COMPLEX_X87_CLASS;
3905 /* This modes is larger than 16 bytes. */
3913 classes[0] = X86_64_SSE_CLASS;
3914 classes[1] = X86_64_SSEUP_CLASS;
3921 classes[0] = X86_64_SSE_CLASS;
3927 gcc_assert (VECTOR_MODE_P (mode));
3932 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3934 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3935 classes[0] = X86_64_INTEGERSI_CLASS;
3937 classes[0] = X86_64_INTEGER_CLASS;
3938 classes[1] = X86_64_INTEGER_CLASS;
3939 return 1 + (bytes > 8);
3943 /* Examine the argument and return set number of register required in each
3944 class. Return 0 iff parameter should be passed in memory. */
3946 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3947 int *int_nregs, int *sse_nregs)
3949 enum x86_64_reg_class regclass[MAX_CLASSES];
3950 int n = classify_argument (mode, type, regclass, 0);
3956 for (n--; n >= 0; n--)
3957 switch (regclass[n])
3959 case X86_64_INTEGER_CLASS:
3960 case X86_64_INTEGERSI_CLASS:
3963 case X86_64_SSE_CLASS:
3964 case X86_64_SSESF_CLASS:
3965 case X86_64_SSEDF_CLASS:
3968 case X86_64_NO_CLASS:
3969 case X86_64_SSEUP_CLASS:
3971 case X86_64_X87_CLASS:
3972 case X86_64_X87UP_CLASS:
3976 case X86_64_COMPLEX_X87_CLASS:
3977 return in_return ? 2 : 0;
3978 case X86_64_MEMORY_CLASS:
3984 /* Construct container for the argument used by GCC interface. See
3985 FUNCTION_ARG for the detailed description. */
3988 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3989 const_tree type, int in_return, int nintregs, int nsseregs,
3990 const int *intreg, int sse_regno)
3992 /* The following variables hold the static issued_error state. */
3993 static bool issued_sse_arg_error;
3994 static bool issued_sse_ret_error;
3995 static bool issued_x87_ret_error;
3997 enum machine_mode tmpmode;
3999 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4000 enum x86_64_reg_class regclass[MAX_CLASSES];
4004 int needed_sseregs, needed_intregs;
4005 rtx exp[MAX_CLASSES];
4008 n = classify_argument (mode, type, regclass, 0);
4011 if (!examine_argument (mode, type, in_return, &needed_intregs,
4014 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4017 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4018 some less clueful developer tries to use floating-point anyway. */
4019 if (needed_sseregs && !TARGET_SSE)
4023 if (!issued_sse_ret_error)
4025 error ("SSE register return with SSE disabled");
4026 issued_sse_ret_error = true;
4029 else if (!issued_sse_arg_error)
4031 error ("SSE register argument with SSE disabled");
4032 issued_sse_arg_error = true;
4037 /* Likewise, error if the ABI requires us to return values in the
4038 x87 registers and the user specified -mno-80387. */
4039 if (!TARGET_80387 && in_return)
4040 for (i = 0; i < n; i++)
4041 if (regclass[i] == X86_64_X87_CLASS
4042 || regclass[i] == X86_64_X87UP_CLASS
4043 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4045 if (!issued_x87_ret_error)
4047 error ("x87 register return with x87 disabled");
4048 issued_x87_ret_error = true;
4053 /* First construct simple cases. Avoid SCmode, since we want to use
4054 single register to pass this type. */
4055 if (n == 1 && mode != SCmode)
4056 switch (regclass[0])
4058 case X86_64_INTEGER_CLASS:
4059 case X86_64_INTEGERSI_CLASS:
4060 return gen_rtx_REG (mode, intreg[0]);
4061 case X86_64_SSE_CLASS:
4062 case X86_64_SSESF_CLASS:
4063 case X86_64_SSEDF_CLASS:
4064 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4065 case X86_64_X87_CLASS:
4066 case X86_64_COMPLEX_X87_CLASS:
4067 return gen_rtx_REG (mode, FIRST_STACK_REG);
4068 case X86_64_NO_CLASS:
4069 /* Zero sized array, struct or class. */
4074 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4075 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4076 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4079 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4080 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4081 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4082 && regclass[1] == X86_64_INTEGER_CLASS
4083 && (mode == CDImode || mode == TImode || mode == TFmode)
4084 && intreg[0] + 1 == intreg[1])
4085 return gen_rtx_REG (mode, intreg[0]);
4087 /* Otherwise figure out the entries of the PARALLEL. */
4088 for (i = 0; i < n; i++)
4090 switch (regclass[i])
4092 case X86_64_NO_CLASS:
4094 case X86_64_INTEGER_CLASS:
4095 case X86_64_INTEGERSI_CLASS:
4096 /* Merge TImodes on aligned occasions here too. */
4097 if (i * 8 + 8 > bytes)
4098 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4099 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4103 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4104 if (tmpmode == BLKmode)
4106 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4107 gen_rtx_REG (tmpmode, *intreg),
4111 case X86_64_SSESF_CLASS:
4112 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4113 gen_rtx_REG (SFmode,
4114 SSE_REGNO (sse_regno)),
4118 case X86_64_SSEDF_CLASS:
4119 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4120 gen_rtx_REG (DFmode,
4121 SSE_REGNO (sse_regno)),
4125 case X86_64_SSE_CLASS:
4126 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4130 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4131 gen_rtx_REG (tmpmode,
4132 SSE_REGNO (sse_regno)),
4134 if (tmpmode == TImode)
4143 /* Empty aligned struct, union or class. */
4147 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4148 for (i = 0; i < nexps; i++)
4149 XVECEXP (ret, 0, i) = exp [i];
4153 /* Update the data in CUM to advance over an argument of mode MODE
4154 and data type TYPE. (TYPE is null for libcalls where that information
4155 may not be available.) */
4158 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4159 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4175 cum->words += words;
4176 cum->nregs -= words;
4177 cum->regno += words;
4179 if (cum->nregs <= 0)
4187 if (cum->float_in_sse < 2)
4190 if (cum->float_in_sse < 1)
4201 if (!type || !AGGREGATE_TYPE_P (type))
4203 cum->sse_words += words;
4204 cum->sse_nregs -= 1;
4205 cum->sse_regno += 1;
4206 if (cum->sse_nregs <= 0)
4219 if (!type || !AGGREGATE_TYPE_P (type))
4221 cum->mmx_words += words;
4222 cum->mmx_nregs -= 1;
4223 cum->mmx_regno += 1;
4224 if (cum->mmx_nregs <= 0)
4235 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4236 tree type, HOST_WIDE_INT words)
4238 int int_nregs, sse_nregs;
4240 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4241 cum->words += words;
4242 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4244 cum->nregs -= int_nregs;
4245 cum->sse_nregs -= sse_nregs;
4246 cum->regno += int_nregs;
4247 cum->sse_regno += sse_nregs;
4250 cum->words += words;
4254 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4255 HOST_WIDE_INT words)
4257 /* Otherwise, this should be passed indirect. */
4258 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4260 cum->words += words;
4269 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4270 tree type, int named ATTRIBUTE_UNUSED)
4272 HOST_WIDE_INT bytes, words;
4274 if (mode == BLKmode)
4275 bytes = int_size_in_bytes (type);
4277 bytes = GET_MODE_SIZE (mode);
4278 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4281 mode = type_natural_mode (type);
4283 if (TARGET_64BIT_MS_ABI)
4284 function_arg_advance_ms_64 (cum, bytes, words);
4285 else if (TARGET_64BIT)
4286 function_arg_advance_64 (cum, mode, type, words);
4288 function_arg_advance_32 (cum, mode, type, bytes, words);
4291 /* Define where to put the arguments to a function.
4292 Value is zero to push the argument on the stack,
4293 or a hard register in which to store the argument.
4295 MODE is the argument's machine mode.
4296 TYPE is the data type of the argument (as a tree).
4297 This is null for libcalls where that information may
4299 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4300 the preceding args and about the function being called.
4301 NAMED is nonzero if this argument is a named parameter
4302 (otherwise it is an extra parameter matching an ellipsis). */
4305 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4306 enum machine_mode orig_mode, tree type,
4307 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4309 static bool warnedsse, warnedmmx;
4311 /* Avoid the AL settings for the Unix64 ABI. */
4312 if (mode == VOIDmode)
4328 if (words <= cum->nregs)
4330 int regno = cum->regno;
4332 /* Fastcall allocates the first two DWORD (SImode) or
4333 smaller arguments to ECX and EDX if it isn't an
4339 || (type && AGGREGATE_TYPE_P (type)))
4342 /* ECX not EAX is the first allocated register. */
4343 if (regno == AX_REG)
4346 return gen_rtx_REG (mode, regno);
4351 if (cum->float_in_sse < 2)
4354 if (cum->float_in_sse < 1)
4364 if (!type || !AGGREGATE_TYPE_P (type))
4366 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4369 warning (0, "SSE vector argument without SSE enabled "
4373 return gen_reg_or_parallel (mode, orig_mode,
4374 cum->sse_regno + FIRST_SSE_REG);
4383 if (!type || !AGGREGATE_TYPE_P (type))
4385 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4388 warning (0, "MMX vector argument without MMX enabled "
4392 return gen_reg_or_parallel (mode, orig_mode,
4393 cum->mmx_regno + FIRST_MMX_REG);
4402 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4403 enum machine_mode orig_mode, tree type)
4405 /* Handle a hidden AL argument containing number of registers
4406 for varargs x86-64 functions. */
4407 if (mode == VOIDmode)
4408 return GEN_INT (cum->maybe_vaarg
4409 ? (cum->sse_nregs < 0
4414 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4416 &x86_64_int_parameter_registers [cum->regno],
4421 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4422 enum machine_mode orig_mode, int named)
4426 /* Avoid the AL settings for the Unix64 ABI. */
4427 if (mode == VOIDmode)
4430 /* If we've run out of registers, it goes on the stack. */
4431 if (cum->nregs == 0)
4434 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4436 /* Only floating point modes are passed in anything but integer regs. */
4437 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4440 regno = cum->regno + FIRST_SSE_REG;
4445 /* Unnamed floating parameters are passed in both the
4446 SSE and integer registers. */
4447 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4448 t2 = gen_rtx_REG (mode, regno);
4449 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4450 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4451 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4455 return gen_reg_or_parallel (mode, orig_mode, regno);
4459 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4460 tree type, int named)
4462 enum machine_mode mode = omode;
4463 HOST_WIDE_INT bytes, words;
4465 if (mode == BLKmode)
4466 bytes = int_size_in_bytes (type);
4468 bytes = GET_MODE_SIZE (mode);
4469 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4471 /* To simplify the code below, represent vector types with a vector mode
4472 even if MMX/SSE are not active. */
4473 if (type && TREE_CODE (type) == VECTOR_TYPE)
4474 mode = type_natural_mode (type);
4476 if (TARGET_64BIT_MS_ABI)
4477 return function_arg_ms_64 (cum, mode, omode, named);
4478 else if (TARGET_64BIT)
4479 return function_arg_64 (cum, mode, omode, type);
4481 return function_arg_32 (cum, mode, omode, type, bytes, words);
4484 /* A C expression that indicates when an argument must be passed by
4485 reference. If nonzero for an argument, a copy of that argument is
4486 made in memory and a pointer to the argument is passed instead of
4487 the argument itself. The pointer is passed in whatever way is
4488 appropriate for passing a pointer to that type. */
4491 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4492 enum machine_mode mode ATTRIBUTE_UNUSED,
4493 const_tree type, bool named ATTRIBUTE_UNUSED)
4495 if (TARGET_64BIT_MS_ABI)
4499 /* Arrays are passed by reference. */
4500 if (TREE_CODE (type) == ARRAY_TYPE)
4503 if (AGGREGATE_TYPE_P (type))
4505 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4506 are passed by reference. */
4507 int el2 = exact_log2 (int_size_in_bytes (type));
4508 return !(el2 >= 0 && el2 <= 3);
4512 /* __m128 is passed by reference. */
4513 /* ??? How to handle complex? For now treat them as structs,
4514 and pass them by reference if they're too large. */
4515 if (GET_MODE_SIZE (mode) > 8)
4518 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4524 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4525 ABI. Only called if TARGET_SSE. */
4527 contains_128bit_aligned_vector_p (tree type)
4529 enum machine_mode mode = TYPE_MODE (type);
4530 if (SSE_REG_MODE_P (mode)
4531 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4533 if (TYPE_ALIGN (type) < 128)
4536 if (AGGREGATE_TYPE_P (type))
4538 /* Walk the aggregates recursively. */
4539 switch (TREE_CODE (type))
4543 case QUAL_UNION_TYPE:
4547 /* Walk all the structure fields. */
4548 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4550 if (TREE_CODE (field) == FIELD_DECL
4551 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4558 /* Just for use if some languages passes arrays by value. */
4559 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4570 /* Gives the alignment boundary, in bits, of an argument with the
4571 specified mode and type. */
4574 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4578 align = TYPE_ALIGN (type);
4580 align = GET_MODE_ALIGNMENT (mode);
4581 if (align < PARM_BOUNDARY)
4582 align = PARM_BOUNDARY;
4583 /* Decimal floating point is aligned to its natural boundary. */
4584 if (!TARGET_64BIT && !VALID_DFP_MODE_P (mode))
4586 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4587 make an exception for SSE modes since these require 128bit
4590 The handling here differs from field_alignment. ICC aligns MMX
4591 arguments to 4 byte boundaries, while structure fields are aligned
4592 to 8 byte boundaries. */
4594 align = PARM_BOUNDARY;
4597 if (!SSE_REG_MODE_P (mode))
4598 align = PARM_BOUNDARY;
4602 if (!contains_128bit_aligned_vector_p (type))
4603 align = PARM_BOUNDARY;
4606 if (align > BIGGEST_ALIGNMENT)
4607 align = BIGGEST_ALIGNMENT;
4611 /* Return true if N is a possible register number of function value. */
4614 ix86_function_value_regno_p (int regno)
4621 case FIRST_FLOAT_REG:
4622 if (TARGET_64BIT_MS_ABI)
4624 return TARGET_FLOAT_RETURNS_IN_80387;
4630 if (TARGET_MACHO || TARGET_64BIT)
4638 /* Define how to find the value returned by a function.
4639 VALTYPE is the data type of the value (as a tree).
4640 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4641 otherwise, FUNC is 0. */
4644 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4645 const_tree fntype, const_tree fn)
4649 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4650 we normally prevent this case when mmx is not available. However
4651 some ABIs may require the result to be returned like DImode. */
4652 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4653 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4655 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4656 we prevent this case when sse is not available. However some ABIs
4657 may require the result to be returned like integer TImode. */
4658 else if (mode == TImode
4659 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4660 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4662 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4663 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4664 regno = FIRST_FLOAT_REG;
4666 /* Most things go in %eax. */
4669 /* Override FP return register with %xmm0 for local functions when
4670 SSE math is enabled or for functions with sseregparm attribute. */
4671 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4673 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4674 if ((sse_level >= 1 && mode == SFmode)
4675 || (sse_level == 2 && mode == DFmode))
4676 regno = FIRST_SSE_REG;
4679 return gen_rtx_REG (orig_mode, regno);
4683 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4688 /* Handle libcalls, which don't provide a type node. */
4689 if (valtype == NULL)
4701 return gen_rtx_REG (mode, FIRST_SSE_REG);
4704 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4708 return gen_rtx_REG (mode, AX_REG);
4712 ret = construct_container (mode, orig_mode, valtype, 1,
4713 REGPARM_MAX, SSE_REGPARM_MAX,
4714 x86_64_int_return_registers, 0);
4716 /* For zero sized structures, construct_container returns NULL, but we
4717 need to keep rest of compiler happy by returning meaningful value. */
4719 ret = gen_rtx_REG (orig_mode, AX_REG);
4725 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4727 unsigned int regno = AX_REG;
4731 if (mode == SFmode || mode == DFmode)
4732 regno = FIRST_SSE_REG;
4733 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4734 regno = FIRST_SSE_REG;
4737 return gen_rtx_REG (orig_mode, regno);
4741 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4742 enum machine_mode orig_mode, enum machine_mode mode)
4744 const_tree fn, fntype;
4747 if (fntype_or_decl && DECL_P (fntype_or_decl))
4748 fn = fntype_or_decl;
4749 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4751 if (TARGET_64BIT_MS_ABI)
4752 return function_value_ms_64 (orig_mode, mode);
4753 else if (TARGET_64BIT)
4754 return function_value_64 (orig_mode, mode, valtype);
4756 return function_value_32 (orig_mode, mode, fntype, fn);
4760 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4761 bool outgoing ATTRIBUTE_UNUSED)
4763 enum machine_mode mode, orig_mode;
4765 orig_mode = TYPE_MODE (valtype);
4766 mode = type_natural_mode (valtype);
4767 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4771 ix86_libcall_value (enum machine_mode mode)
4773 return ix86_function_value_1 (NULL, NULL, mode, mode);
4776 /* Return true iff type is returned in memory. */
4779 return_in_memory_32 (const_tree type, enum machine_mode mode)
4783 if (mode == BLKmode)
4786 size = int_size_in_bytes (type);
4788 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4791 if (VECTOR_MODE_P (mode) || mode == TImode)
4793 /* User-created vectors small enough to fit in EAX. */
4797 /* MMX/3dNow values are returned in MM0,
4798 except when it doesn't exits. */
4800 return (TARGET_MMX ? 0 : 1);
4802 /* SSE values are returned in XMM0, except when it doesn't exist. */
4804 return (TARGET_SSE ? 0 : 1);
4819 return_in_memory_64 (const_tree type, enum machine_mode mode)
4821 int needed_intregs, needed_sseregs;
4822 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4826 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4828 HOST_WIDE_INT size = int_size_in_bytes (type);
4830 /* __m128 and friends are returned in xmm0. */
4831 if (!COMPLEX_MODE_P (mode) && size == 16 && VECTOR_MODE_P (mode))
4834 /* Otherwise, the size must be exactly in [1248]. But not for complex. */
4835 return (size != 1 && size != 2 && size != 4 && size != 8)
4836 || COMPLEX_MODE_P (mode);
4840 ix86_return_in_memory (const_tree type)
4842 const enum machine_mode mode = type_natural_mode (type);
4844 if (TARGET_64BIT_MS_ABI)
4845 return return_in_memory_ms_64 (type, mode);
4846 else if (TARGET_64BIT)
4847 return return_in_memory_64 (type, mode);
4849 return return_in_memory_32 (type, mode);
4852 /* Return false iff TYPE is returned in memory. This version is used
4853 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4854 but differs notably in that when MMX is available, 8-byte vectors
4855 are returned in memory, rather than in MMX registers. */
4858 ix86_sol10_return_in_memory (const_tree type)
4861 enum machine_mode mode = type_natural_mode (type);
4864 return return_in_memory_64 (type, mode);
4866 if (mode == BLKmode)
4869 size = int_size_in_bytes (type);
4871 if (VECTOR_MODE_P (mode))
4873 /* Return in memory only if MMX registers *are* available. This
4874 seems backwards, but it is consistent with the existing
4881 else if (mode == TImode)
4883 else if (mode == XFmode)
4889 /* When returning SSE vector types, we have a choice of either
4890 (1) being abi incompatible with a -march switch, or
4891 (2) generating an error.
4892 Given no good solution, I think the safest thing is one warning.
4893 The user won't be able to use -Werror, but....
4895 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4896 called in response to actually generating a caller or callee that
4897 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4898 via aggregate_value_p for general type probing from tree-ssa. */
4901 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4903 static bool warnedsse, warnedmmx;
4905 if (!TARGET_64BIT && type)
4907 /* Look at the return type of the function, not the function type. */
4908 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4910 if (!TARGET_SSE && !warnedsse)
4913 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4916 warning (0, "SSE vector return without SSE enabled "
4921 if (!TARGET_MMX && !warnedmmx)
4923 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4926 warning (0, "MMX vector return without MMX enabled "
4936 /* Create the va_list data type. */
4939 ix86_build_builtin_va_list (void)
4941 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4943 /* For i386 we use plain pointer to argument area. */
4944 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4945 return build_pointer_type (char_type_node);
4947 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4948 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4950 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4951 unsigned_type_node);
4952 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4953 unsigned_type_node);
4954 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4956 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4959 va_list_gpr_counter_field = f_gpr;
4960 va_list_fpr_counter_field = f_fpr;
4962 DECL_FIELD_CONTEXT (f_gpr) = record;
4963 DECL_FIELD_CONTEXT (f_fpr) = record;
4964 DECL_FIELD_CONTEXT (f_ovf) = record;
4965 DECL_FIELD_CONTEXT (f_sav) = record;
4967 TREE_CHAIN (record) = type_decl;
4968 TYPE_NAME (record) = type_decl;
4969 TYPE_FIELDS (record) = f_gpr;
4970 TREE_CHAIN (f_gpr) = f_fpr;
4971 TREE_CHAIN (f_fpr) = f_ovf;
4972 TREE_CHAIN (f_ovf) = f_sav;
4974 layout_type (record);
4976 /* The correct type is an array type of one element. */
4977 return build_array_type (record, build_index_type (size_zero_node));
4980 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4983 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4993 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4996 /* Indicate to allocate space on the stack for varargs save area. */
4997 ix86_save_varrargs_registers = 1;
4998 /* We need 16-byte stack alignment to save SSE registers. If user
4999 asked for lower preferred_stack_boundary, lets just hope that he knows
5000 what he is doing and won't varargs SSE values.
5002 We also may end up assuming that only 64bit values are stored in SSE
5003 register let some floating point program work. */
5004 if (ix86_preferred_stack_boundary >= BIGGEST_ALIGNMENT)
5005 cfun->stack_alignment_needed = BIGGEST_ALIGNMENT;
5007 save_area = frame_pointer_rtx;
5008 set = get_varargs_alias_set ();
5010 for (i = cum->regno;
5012 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5015 mem = gen_rtx_MEM (Pmode,
5016 plus_constant (save_area, i * UNITS_PER_WORD));
5017 MEM_NOTRAP_P (mem) = 1;
5018 set_mem_alias_set (mem, set);
5019 emit_move_insn (mem, gen_rtx_REG (Pmode,
5020 x86_64_int_parameter_registers[i]));
5023 if (cum->sse_nregs && cfun->va_list_fpr_size)
5025 /* Now emit code to save SSE registers. The AX parameter contains number
5026 of SSE parameter registers used to call this function. We use
5027 sse_prologue_save insn template that produces computed jump across
5028 SSE saves. We need some preparation work to get this working. */
5030 label = gen_label_rtx ();
5031 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5033 /* Compute address to jump to :
5034 label - 5*eax + nnamed_sse_arguments*5 */
5035 tmp_reg = gen_reg_rtx (Pmode);
5036 nsse_reg = gen_reg_rtx (Pmode);
5037 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5038 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5039 gen_rtx_MULT (Pmode, nsse_reg,
5044 gen_rtx_CONST (DImode,
5045 gen_rtx_PLUS (DImode,
5047 GEN_INT (cum->sse_regno * 4))));
5049 emit_move_insn (nsse_reg, label_ref);
5050 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5052 /* Compute address of memory block we save into. We always use pointer
5053 pointing 127 bytes after first byte to store - this is needed to keep
5054 instruction size limited by 4 bytes. */
5055 tmp_reg = gen_reg_rtx (Pmode);
5056 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5057 plus_constant (save_area,
5058 8 * REGPARM_MAX + 127)));
5059 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5060 MEM_NOTRAP_P (mem) = 1;
5061 set_mem_alias_set (mem, set);
5062 set_mem_align (mem, BITS_PER_WORD);
5064 /* And finally do the dirty job! */
5065 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5066 GEN_INT (cum->sse_regno), label));
5071 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5073 alias_set_type set = get_varargs_alias_set ();
5076 for (i = cum->regno; i < REGPARM_MAX; i++)
5080 mem = gen_rtx_MEM (Pmode,
5081 plus_constant (virtual_incoming_args_rtx,
5082 i * UNITS_PER_WORD));
5083 MEM_NOTRAP_P (mem) = 1;
5084 set_mem_alias_set (mem, set);
5086 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5087 emit_move_insn (mem, reg);
5092 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5093 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5096 CUMULATIVE_ARGS next_cum;
5099 /* This argument doesn't appear to be used anymore. Which is good,
5100 because the old code here didn't suppress rtl generation. */
5101 gcc_assert (!no_rtl);
5106 fntype = TREE_TYPE (current_function_decl);
5108 /* For varargs, we do not want to skip the dummy va_dcl argument.
5109 For stdargs, we do want to skip the last named argument. */
5111 if (stdarg_p (fntype))
5112 function_arg_advance (&next_cum, mode, type, 1);
5114 if (TARGET_64BIT_MS_ABI)
5115 setup_incoming_varargs_ms_64 (&next_cum);
5117 setup_incoming_varargs_64 (&next_cum);
5120 /* Implement va_start. */
5123 ix86_va_start (tree valist, rtx nextarg)
5125 HOST_WIDE_INT words, n_gpr, n_fpr;
5126 tree f_gpr, f_fpr, f_ovf, f_sav;
5127 tree gpr, fpr, ovf, sav, t;
5130 /* Only 64bit target needs something special. */
5131 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5133 std_expand_builtin_va_start (valist, nextarg);
5137 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5138 f_fpr = TREE_CHAIN (f_gpr);
5139 f_ovf = TREE_CHAIN (f_fpr);
5140 f_sav = TREE_CHAIN (f_ovf);
5142 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5143 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5144 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5145 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5146 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5148 /* Count number of gp and fp argument registers used. */
5149 words = current_function_args_info.words;
5150 n_gpr = current_function_args_info.regno;
5151 n_fpr = current_function_args_info.sse_regno;
5153 if (cfun->va_list_gpr_size)
5155 type = TREE_TYPE (gpr);
5156 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5157 build_int_cst (type, n_gpr * 8));
5158 TREE_SIDE_EFFECTS (t) = 1;
5159 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5162 if (cfun->va_list_fpr_size)
5164 type = TREE_TYPE (fpr);
5165 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5166 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5167 TREE_SIDE_EFFECTS (t) = 1;
5168 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5171 /* Find the overflow area. */
5172 type = TREE_TYPE (ovf);
5173 t = make_tree (type, virtual_incoming_args_rtx);
5175 t = build2 (POINTER_PLUS_EXPR, type, t,
5176 size_int (words * UNITS_PER_WORD));
5177 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5178 TREE_SIDE_EFFECTS (t) = 1;
5179 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5181 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5183 /* Find the register save area.
5184 Prologue of the function save it right above stack frame. */
5185 type = TREE_TYPE (sav);
5186 t = make_tree (type, frame_pointer_rtx);
5187 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5188 TREE_SIDE_EFFECTS (t) = 1;
5189 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5193 /* Implement va_arg. */
5196 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5198 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5199 tree f_gpr, f_fpr, f_ovf, f_sav;
5200 tree gpr, fpr, ovf, sav, t;
5202 tree lab_false, lab_over = NULL_TREE;
5207 enum machine_mode nat_mode;
5209 /* Only 64bit target needs something special. */
5210 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5211 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5213 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5214 f_fpr = TREE_CHAIN (f_gpr);
5215 f_ovf = TREE_CHAIN (f_fpr);
5216 f_sav = TREE_CHAIN (f_ovf);
5218 valist = build_va_arg_indirect_ref (valist);
5219 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5220 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5221 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5222 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5224 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5226 type = build_pointer_type (type);
5227 size = int_size_in_bytes (type);
5228 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5230 nat_mode = type_natural_mode (type);
5231 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5232 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5234 /* Pull the value out of the saved registers. */
5236 addr = create_tmp_var (ptr_type_node, "addr");
5237 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5241 int needed_intregs, needed_sseregs;
5243 tree int_addr, sse_addr;
5245 lab_false = create_artificial_label ();
5246 lab_over = create_artificial_label ();
5248 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5250 need_temp = (!REG_P (container)
5251 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5252 || TYPE_ALIGN (type) > 128));
5254 /* In case we are passing structure, verify that it is consecutive block
5255 on the register save area. If not we need to do moves. */
5256 if (!need_temp && !REG_P (container))
5258 /* Verify that all registers are strictly consecutive */
5259 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5263 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5265 rtx slot = XVECEXP (container, 0, i);
5266 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5267 || INTVAL (XEXP (slot, 1)) != i * 16)
5275 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5277 rtx slot = XVECEXP (container, 0, i);
5278 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5279 || INTVAL (XEXP (slot, 1)) != i * 8)
5291 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5292 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5293 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5294 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5297 /* First ensure that we fit completely in registers. */
5300 t = build_int_cst (TREE_TYPE (gpr),
5301 (REGPARM_MAX - needed_intregs + 1) * 8);
5302 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5303 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5304 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5305 gimplify_and_add (t, pre_p);
5309 t = build_int_cst (TREE_TYPE (fpr),
5310 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5312 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5313 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5314 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5315 gimplify_and_add (t, pre_p);
5318 /* Compute index to start of area used for integer regs. */
5321 /* int_addr = gpr + sav; */
5322 t = fold_convert (sizetype, gpr);
5323 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5324 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5325 gimplify_and_add (t, pre_p);
5329 /* sse_addr = fpr + sav; */
5330 t = fold_convert (sizetype, fpr);
5331 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5332 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5333 gimplify_and_add (t, pre_p);
5338 tree temp = create_tmp_var (type, "va_arg_tmp");
5341 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5342 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5343 gimplify_and_add (t, pre_p);
5345 for (i = 0; i < XVECLEN (container, 0); i++)
5347 rtx slot = XVECEXP (container, 0, i);
5348 rtx reg = XEXP (slot, 0);
5349 enum machine_mode mode = GET_MODE (reg);
5350 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5351 tree addr_type = build_pointer_type (piece_type);
5354 tree dest_addr, dest;
5356 if (SSE_REGNO_P (REGNO (reg)))
5358 src_addr = sse_addr;
5359 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5363 src_addr = int_addr;
5364 src_offset = REGNO (reg) * 8;
5366 src_addr = fold_convert (addr_type, src_addr);
5367 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5368 size_int (src_offset));
5369 src = build_va_arg_indirect_ref (src_addr);
5371 dest_addr = fold_convert (addr_type, addr);
5372 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5373 size_int (INTVAL (XEXP (slot, 1))));
5374 dest = build_va_arg_indirect_ref (dest_addr);
5376 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5377 gimplify_and_add (t, pre_p);
5383 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5384 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5385 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5386 gimplify_and_add (t, pre_p);
5390 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5391 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5392 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5393 gimplify_and_add (t, pre_p);
5396 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5397 gimplify_and_add (t, pre_p);
5399 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5400 append_to_statement_list (t, pre_p);
5403 /* ... otherwise out of the overflow area. */
5405 /* Care for on-stack alignment if needed. */
5406 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5407 || integer_zerop (TYPE_SIZE (type)))
5411 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5412 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5413 size_int (align - 1));
5414 t = fold_convert (sizetype, t);
5415 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5417 t = fold_convert (TREE_TYPE (ovf), t);
5419 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5421 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5422 gimplify_and_add (t2, pre_p);
5424 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5425 size_int (rsize * UNITS_PER_WORD));
5426 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5427 gimplify_and_add (t, pre_p);
5431 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5432 append_to_statement_list (t, pre_p);
5435 ptrtype = build_pointer_type (type);
5436 addr = fold_convert (ptrtype, addr);
5439 addr = build_va_arg_indirect_ref (addr);
5440 return build_va_arg_indirect_ref (addr);
5443 /* Return nonzero if OPNUM's MEM should be matched
5444 in movabs* patterns. */
5447 ix86_check_movabs (rtx insn, int opnum)
5451 set = PATTERN (insn);
5452 if (GET_CODE (set) == PARALLEL)
5453 set = XVECEXP (set, 0, 0);
5454 gcc_assert (GET_CODE (set) == SET);
5455 mem = XEXP (set, opnum);
5456 while (GET_CODE (mem) == SUBREG)
5457 mem = SUBREG_REG (mem);
5458 gcc_assert (MEM_P (mem));
5459 return (volatile_ok || !MEM_VOLATILE_P (mem));
5462 /* Initialize the table of extra 80387 mathematical constants. */
5465 init_ext_80387_constants (void)
5467 static const char * cst[5] =
5469 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5470 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5471 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5472 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5473 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5477 for (i = 0; i < 5; i++)
5479 real_from_string (&ext_80387_constants_table[i], cst[i]);
5480 /* Ensure each constant is rounded to XFmode precision. */
5481 real_convert (&ext_80387_constants_table[i],
5482 XFmode, &ext_80387_constants_table[i]);
5485 ext_80387_constants_init = 1;
5488 /* Return true if the constant is something that can be loaded with
5489 a special instruction. */
5492 standard_80387_constant_p (rtx x)
5494 enum machine_mode mode = GET_MODE (x);
5498 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5501 if (x == CONST0_RTX (mode))
5503 if (x == CONST1_RTX (mode))
5506 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5508 /* For XFmode constants, try to find a special 80387 instruction when
5509 optimizing for size or on those CPUs that benefit from them. */
5511 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5515 if (! ext_80387_constants_init)
5516 init_ext_80387_constants ();
5518 for (i = 0; i < 5; i++)
5519 if (real_identical (&r, &ext_80387_constants_table[i]))
5523 /* Load of the constant -0.0 or -1.0 will be split as
5524 fldz;fchs or fld1;fchs sequence. */
5525 if (real_isnegzero (&r))
5527 if (real_identical (&r, &dconstm1))
5533 /* Return the opcode of the special instruction to be used to load
5537 standard_80387_constant_opcode (rtx x)
5539 switch (standard_80387_constant_p (x))
5563 /* Return the CONST_DOUBLE representing the 80387 constant that is
5564 loaded by the specified special instruction. The argument IDX
5565 matches the return value from standard_80387_constant_p. */
5568 standard_80387_constant_rtx (int idx)
5572 if (! ext_80387_constants_init)
5573 init_ext_80387_constants ();
5589 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5593 /* Return 1 if mode is a valid mode for sse. */
5595 standard_sse_mode_p (enum machine_mode mode)
5612 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5615 standard_sse_constant_p (rtx x)
5617 enum machine_mode mode = GET_MODE (x);
5619 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5621 if (vector_all_ones_operand (x, mode)
5622 && standard_sse_mode_p (mode))
5623 return TARGET_SSE2 ? 2 : -1;
5628 /* Return the opcode of the special instruction to be used to load
5632 standard_sse_constant_opcode (rtx insn, rtx x)
5634 switch (standard_sse_constant_p (x))
5637 if (get_attr_mode (insn) == MODE_V4SF)
5638 return "xorps\t%0, %0";
5639 else if (get_attr_mode (insn) == MODE_V2DF)
5640 return "xorpd\t%0, %0";
5642 return "pxor\t%0, %0";
5644 return "pcmpeqd\t%0, %0";
5649 /* Returns 1 if OP contains a symbol reference */
5652 symbolic_reference_mentioned_p (rtx op)
5657 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5660 fmt = GET_RTX_FORMAT (GET_CODE (op));
5661 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5667 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5668 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5672 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5679 /* Return 1 if it is appropriate to emit `ret' instructions in the
5680 body of a function. Do this only if the epilogue is simple, needing a
5681 couple of insns. Prior to reloading, we can't tell how many registers
5682 must be saved, so return 0 then. Return 0 if there is no frame
5683 marker to de-allocate. */
5686 ix86_can_use_return_insn_p (void)
5688 struct ix86_frame frame;
5690 if (! reload_completed || frame_pointer_needed)
5693 /* Don't allow more than 32 pop, since that's all we can do
5694 with one instruction. */
5695 if (current_function_pops_args
5696 && current_function_args_size >= 32768)
5699 ix86_compute_frame_layout (&frame);
5700 return frame.to_allocate == 0 && frame.nregs == 0;
5703 /* Value should be nonzero if functions must have frame pointers.
5704 Zero means the frame pointer need not be set up (and parms may
5705 be accessed via the stack pointer) in functions that seem suitable. */
5708 ix86_frame_pointer_required (void)
5710 /* If we accessed previous frames, then the generated code expects
5711 to be able to access the saved ebp value in our frame. */
5712 if (cfun->machine->accesses_prev_frame)
5715 /* Several x86 os'es need a frame pointer for other reasons,
5716 usually pertaining to setjmp. */
5717 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5720 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5721 the frame pointer by default. Turn it back on now if we've not
5722 got a leaf function. */
5723 if (TARGET_OMIT_LEAF_FRAME_POINTER
5724 && (!current_function_is_leaf
5725 || ix86_current_function_calls_tls_descriptor))
5728 if (current_function_profile)
5734 /* Record that the current function accesses previous call frames. */
5737 ix86_setup_frame_addresses (void)
5739 cfun->machine->accesses_prev_frame = 1;
5742 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5743 # define USE_HIDDEN_LINKONCE 1
5745 # define USE_HIDDEN_LINKONCE 0
5748 static int pic_labels_used;
5750 /* Fills in the label name that should be used for a pc thunk for
5751 the given register. */
5754 get_pc_thunk_name (char name[32], unsigned int regno)
5756 gcc_assert (!TARGET_64BIT);
5758 if (USE_HIDDEN_LINKONCE)
5759 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5761 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5765 /* This function generates code for -fpic that loads %ebx with
5766 the return address of the caller and then returns. */
5769 ix86_file_end (void)
5774 for (regno = 0; regno < 8; ++regno)
5778 if (! ((pic_labels_used >> regno) & 1))
5781 get_pc_thunk_name (name, regno);
5786 switch_to_section (darwin_sections[text_coal_section]);
5787 fputs ("\t.weak_definition\t", asm_out_file);
5788 assemble_name (asm_out_file, name);
5789 fputs ("\n\t.private_extern\t", asm_out_file);
5790 assemble_name (asm_out_file, name);
5791 fputs ("\n", asm_out_file);
5792 ASM_OUTPUT_LABEL (asm_out_file, name);
5796 if (USE_HIDDEN_LINKONCE)
5800 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5802 TREE_PUBLIC (decl) = 1;
5803 TREE_STATIC (decl) = 1;
5804 DECL_ONE_ONLY (decl) = 1;
5806 (*targetm.asm_out.unique_section) (decl, 0);
5807 switch_to_section (get_named_section (decl, NULL, 0));
5809 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5810 fputs ("\t.hidden\t", asm_out_file);
5811 assemble_name (asm_out_file, name);
5812 fputc ('\n', asm_out_file);
5813 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5817 switch_to_section (text_section);
5818 ASM_OUTPUT_LABEL (asm_out_file, name);
5821 xops[0] = gen_rtx_REG (SImode, regno);
5822 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5823 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5824 output_asm_insn ("ret", xops);
5827 if (NEED_INDICATE_EXEC_STACK)
5828 file_end_indicate_exec_stack ();
5831 /* Emit code for the SET_GOT patterns. */
5834 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5840 if (TARGET_VXWORKS_RTP && flag_pic)
5842 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5843 xops[2] = gen_rtx_MEM (Pmode,
5844 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5845 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5847 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5848 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5849 an unadorned address. */
5850 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5851 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5852 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5856 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5858 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5860 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5863 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5865 output_asm_insn ("call\t%a2", xops);
5868 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5869 is what will be referenced by the Mach-O PIC subsystem. */
5871 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5874 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5875 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5878 output_asm_insn ("pop{l}\t%0", xops);
5883 get_pc_thunk_name (name, REGNO (dest));
5884 pic_labels_used |= 1 << REGNO (dest);
5886 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5887 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5888 output_asm_insn ("call\t%X2", xops);
5889 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5890 is what will be referenced by the Mach-O PIC subsystem. */
5893 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5895 targetm.asm_out.internal_label (asm_out_file, "L",
5896 CODE_LABEL_NUMBER (label));
5903 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5904 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5906 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5911 /* Generate an "push" pattern for input ARG. */
5916 return gen_rtx_SET (VOIDmode,
5918 gen_rtx_PRE_DEC (Pmode,
5919 stack_pointer_rtx)),
5923 /* Return >= 0 if there is an unused call-clobbered register available
5924 for the entire function. */
5927 ix86_select_alt_pic_regnum (void)
5929 if (current_function_is_leaf && !current_function_profile
5930 && !ix86_current_function_calls_tls_descriptor)
5933 for (i = 2; i >= 0; --i)
5934 if (!df_regs_ever_live_p (i))
5938 return INVALID_REGNUM;
5941 /* Return 1 if we need to save REGNO. */
5943 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5945 if (pic_offset_table_rtx
5946 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5947 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
5948 || current_function_profile
5949 || current_function_calls_eh_return
5950 || current_function_uses_const_pool))
5952 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5957 if (current_function_calls_eh_return && maybe_eh_return)
5962 unsigned test = EH_RETURN_DATA_REGNO (i);
5963 if (test == INVALID_REGNUM)
5970 if (cfun->machine->force_align_arg_pointer
5971 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5974 return (df_regs_ever_live_p (regno)
5975 && !call_used_regs[regno]
5976 && !fixed_regs[regno]
5977 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5980 /* Return number of registers to be saved on the stack. */
5983 ix86_nsaved_regs (void)
5988 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5989 if (ix86_save_reg (regno, true))
5994 /* Return the offset between two registers, one to be eliminated, and the other
5995 its replacement, at the start of a routine. */
5998 ix86_initial_elimination_offset (int from, int to)
6000 struct ix86_frame frame;
6001 ix86_compute_frame_layout (&frame);
6003 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6004 return frame.hard_frame_pointer_offset;
6005 else if (from == FRAME_POINTER_REGNUM
6006 && to == HARD_FRAME_POINTER_REGNUM)
6007 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6010 gcc_assert (to == STACK_POINTER_REGNUM);
6012 if (from == ARG_POINTER_REGNUM)
6013 return frame.stack_pointer_offset;
6015 gcc_assert (from == FRAME_POINTER_REGNUM);
6016 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6020 /* Fill structure ix86_frame about frame of currently computed function. */
6023 ix86_compute_frame_layout (struct ix86_frame *frame)
6025 HOST_WIDE_INT total_size;
6026 unsigned int stack_alignment_needed;
6027 HOST_WIDE_INT offset;
6028 unsigned int preferred_alignment;
6029 HOST_WIDE_INT size = get_frame_size ();
6031 frame->nregs = ix86_nsaved_regs ();
6034 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
6035 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
6037 /* During reload iteration the amount of registers saved can change.
6038 Recompute the value as needed. Do not recompute when amount of registers
6039 didn't change as reload does multiple calls to the function and does not
6040 expect the decision to change within single iteration. */
6042 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6044 int count = frame->nregs;
6046 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6047 /* The fast prologue uses move instead of push to save registers. This
6048 is significantly longer, but also executes faster as modern hardware
6049 can execute the moves in parallel, but can't do that for push/pop.
6051 Be careful about choosing what prologue to emit: When function takes
6052 many instructions to execute we may use slow version as well as in
6053 case function is known to be outside hot spot (this is known with
6054 feedback only). Weight the size of function by number of registers
6055 to save as it is cheap to use one or two push instructions but very
6056 slow to use many of them. */
6058 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6059 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6060 || (flag_branch_probabilities
6061 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6062 cfun->machine->use_fast_prologue_epilogue = false;
6064 cfun->machine->use_fast_prologue_epilogue
6065 = !expensive_function_p (count);
6067 if (TARGET_PROLOGUE_USING_MOVE
6068 && cfun->machine->use_fast_prologue_epilogue)
6069 frame->save_regs_using_mov = true;
6071 frame->save_regs_using_mov = false;
6074 /* Skip return address and saved base pointer. */
6075 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6077 frame->hard_frame_pointer_offset = offset;
6079 /* Do some sanity checking of stack_alignment_needed and
6080 preferred_alignment, since i386 port is the only using those features
6081 that may break easily. */
6083 gcc_assert (!size || stack_alignment_needed);
6084 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6085 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6086 gcc_assert (stack_alignment_needed
6087 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6089 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6090 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6092 /* Register save area */
6093 offset += frame->nregs * UNITS_PER_WORD;
6096 if (ix86_save_varrargs_registers)
6098 offset += X86_64_VARARGS_SIZE;
6099 frame->va_arg_size = X86_64_VARARGS_SIZE;
6102 frame->va_arg_size = 0;
6104 /* Align start of frame for local function. */
6105 frame->padding1 = ((offset + stack_alignment_needed - 1)
6106 & -stack_alignment_needed) - offset;
6108 offset += frame->padding1;
6110 /* Frame pointer points here. */
6111 frame->frame_pointer_offset = offset;
6115 /* Add outgoing arguments area. Can be skipped if we eliminated
6116 all the function calls as dead code.
6117 Skipping is however impossible when function calls alloca. Alloca
6118 expander assumes that last current_function_outgoing_args_size
6119 of stack frame are unused. */
6120 if (ACCUMULATE_OUTGOING_ARGS
6121 && (!current_function_is_leaf || current_function_calls_alloca
6122 || ix86_current_function_calls_tls_descriptor))
6124 offset += current_function_outgoing_args_size;
6125 frame->outgoing_arguments_size = current_function_outgoing_args_size;
6128 frame->outgoing_arguments_size = 0;
6130 /* Align stack boundary. Only needed if we're calling another function
6132 if (!current_function_is_leaf || current_function_calls_alloca
6133 || ix86_current_function_calls_tls_descriptor)
6134 frame->padding2 = ((offset + preferred_alignment - 1)
6135 & -preferred_alignment) - offset;
6137 frame->padding2 = 0;
6139 offset += frame->padding2;
6141 /* We've reached end of stack frame. */
6142 frame->stack_pointer_offset = offset;
6144 /* Size prologue needs to allocate. */
6145 frame->to_allocate =
6146 (size + frame->padding1 + frame->padding2
6147 + frame->outgoing_arguments_size + frame->va_arg_size);
6149 if ((!frame->to_allocate && frame->nregs <= 1)
6150 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6151 frame->save_regs_using_mov = false;
6153 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6154 && current_function_is_leaf
6155 && !ix86_current_function_calls_tls_descriptor)
6157 frame->red_zone_size = frame->to_allocate;
6158 if (frame->save_regs_using_mov)
6159 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6160 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6161 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6164 frame->red_zone_size = 0;
6165 frame->to_allocate -= frame->red_zone_size;
6166 frame->stack_pointer_offset -= frame->red_zone_size;
6168 fprintf (stderr, "\n");
6169 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6170 fprintf (stderr, "size: %ld\n", (long)size);
6171 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6172 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6173 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6174 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6175 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6176 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6177 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6178 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6179 (long)frame->hard_frame_pointer_offset);
6180 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6181 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6182 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
6183 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6187 /* Emit code to save registers in the prologue. */
6190 ix86_emit_save_regs (void)
6195 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6196 if (ix86_save_reg (regno, true))
6198 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6199 RTX_FRAME_RELATED_P (insn) = 1;
6203 /* Emit code to save registers using MOV insns. First register
6204 is restored from POINTER + OFFSET. */
6206 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6211 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6212 if (ix86_save_reg (regno, true))
6214 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6216 gen_rtx_REG (Pmode, regno));
6217 RTX_FRAME_RELATED_P (insn) = 1;
6218 offset += UNITS_PER_WORD;
6222 /* Expand prologue or epilogue stack adjustment.
6223 The pattern exist to put a dependency on all ebp-based memory accesses.
6224 STYLE should be negative if instructions should be marked as frame related,
6225 zero if %r11 register is live and cannot be freely used and positive
6229 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6234 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6235 else if (x86_64_immediate_operand (offset, DImode))
6236 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6240 /* r11 is used by indirect sibcall return as well, set before the
6241 epilogue and used after the epilogue. ATM indirect sibcall
6242 shouldn't be used together with huge frame sizes in one
6243 function because of the frame_size check in sibcall.c. */
6245 r11 = gen_rtx_REG (DImode, R11_REG);
6246 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6248 RTX_FRAME_RELATED_P (insn) = 1;
6249 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6253 RTX_FRAME_RELATED_P (insn) = 1;
6256 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6259 ix86_internal_arg_pointer (void)
6261 bool has_force_align_arg_pointer =
6262 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6263 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6264 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6265 && DECL_NAME (current_function_decl)
6266 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6267 && DECL_FILE_SCOPE_P (current_function_decl))
6268 || ix86_force_align_arg_pointer
6269 || has_force_align_arg_pointer)
6271 /* Nested functions can't realign the stack due to a register
6273 if (DECL_CONTEXT (current_function_decl)
6274 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6276 if (ix86_force_align_arg_pointer)
6277 warning (0, "-mstackrealign ignored for nested functions");
6278 if (has_force_align_arg_pointer)
6279 error ("%s not supported for nested functions",
6280 ix86_force_align_arg_pointer_string);
6281 return virtual_incoming_args_rtx;
6283 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6284 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6287 return virtual_incoming_args_rtx;
6290 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6291 This is called from dwarf2out.c to emit call frame instructions
6292 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6294 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6296 rtx unspec = SET_SRC (pattern);
6297 gcc_assert (GET_CODE (unspec) == UNSPEC);
6301 case UNSPEC_REG_SAVE:
6302 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6303 SET_DEST (pattern));
6305 case UNSPEC_DEF_CFA:
6306 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6307 INTVAL (XVECEXP (unspec, 0, 0)));
6314 /* Expand the prologue into a bunch of separate insns. */
6317 ix86_expand_prologue (void)
6321 struct ix86_frame frame;
6322 HOST_WIDE_INT allocate;
6324 ix86_compute_frame_layout (&frame);
6326 if (cfun->machine->force_align_arg_pointer)
6330 /* Grab the argument pointer. */
6331 x = plus_constant (stack_pointer_rtx, 4);
6332 y = cfun->machine->force_align_arg_pointer;
6333 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6334 RTX_FRAME_RELATED_P (insn) = 1;
6336 /* The unwind info consists of two parts: install the fafp as the cfa,
6337 and record the fafp as the "save register" of the stack pointer.
6338 The later is there in order that the unwinder can see where it
6339 should restore the stack pointer across the and insn. */
6340 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6341 x = gen_rtx_SET (VOIDmode, y, x);
6342 RTX_FRAME_RELATED_P (x) = 1;
6343 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6345 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6346 RTX_FRAME_RELATED_P (y) = 1;
6347 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6348 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6349 REG_NOTES (insn) = x;
6351 /* Align the stack. */
6352 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6355 /* And here we cheat like madmen with the unwind info. We force the
6356 cfa register back to sp+4, which is exactly what it was at the
6357 start of the function. Re-pushing the return address results in
6358 the return at the same spot relative to the cfa, and thus is
6359 correct wrt the unwind info. */
6360 x = cfun->machine->force_align_arg_pointer;
6361 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6362 insn = emit_insn (gen_push (x));
6363 RTX_FRAME_RELATED_P (insn) = 1;
6366 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6367 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6368 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6369 REG_NOTES (insn) = x;
6372 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6373 slower on all targets. Also sdb doesn't like it. */
6375 if (frame_pointer_needed)
6377 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6378 RTX_FRAME_RELATED_P (insn) = 1;
6380 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6381 RTX_FRAME_RELATED_P (insn) = 1;
6384 allocate = frame.to_allocate;
6386 if (!frame.save_regs_using_mov)
6387 ix86_emit_save_regs ();
6389 allocate += frame.nregs * UNITS_PER_WORD;
6391 /* When using red zone we may start register saving before allocating
6392 the stack frame saving one cycle of the prologue. However I will
6393 avoid doing this if I am going to have to probe the stack since
6394 at least on x86_64 the stack probe can turn into a call that clobbers
6395 a red zone location */
6396 if (TARGET_RED_ZONE && frame.save_regs_using_mov
6397 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6398 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6399 : stack_pointer_rtx,
6400 -frame.nregs * UNITS_PER_WORD);
6404 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6405 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6406 GEN_INT (-allocate), -1);
6409 /* Only valid for Win32. */
6410 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6414 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6416 if (TARGET_64BIT_MS_ABI)
6419 eax_live = ix86_eax_live_at_start_p ();
6423 emit_insn (gen_push (eax));
6424 allocate -= UNITS_PER_WORD;
6427 emit_move_insn (eax, GEN_INT (allocate));
6430 insn = gen_allocate_stack_worker_64 (eax);
6432 insn = gen_allocate_stack_worker_32 (eax);
6433 insn = emit_insn (insn);
6434 RTX_FRAME_RELATED_P (insn) = 1;
6435 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6436 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6437 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6438 t, REG_NOTES (insn));
6442 if (frame_pointer_needed)
6443 t = plus_constant (hard_frame_pointer_rtx,
6446 - frame.nregs * UNITS_PER_WORD);
6448 t = plus_constant (stack_pointer_rtx, allocate);
6449 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6453 if (frame.save_regs_using_mov
6454 && !(TARGET_RED_ZONE
6455 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6457 if (!frame_pointer_needed || !frame.to_allocate)
6458 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6460 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6461 -frame.nregs * UNITS_PER_WORD);
6464 pic_reg_used = false;
6465 if (pic_offset_table_rtx
6466 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6467 || current_function_profile))
6469 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6471 if (alt_pic_reg_used != INVALID_REGNUM)
6472 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6474 pic_reg_used = true;
6481 if (ix86_cmodel == CM_LARGE_PIC)
6483 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6484 rtx label = gen_label_rtx ();
6486 LABEL_PRESERVE_P (label) = 1;
6487 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6488 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6489 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6490 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6491 pic_offset_table_rtx, tmp_reg));
6494 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6497 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6500 /* Prevent function calls from being scheduled before the call to mcount.
6501 In the pic_reg_used case, make sure that the got load isn't deleted. */
6502 if (current_function_profile)
6505 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6506 emit_insn (gen_blockage ());
6510 /* Emit code to restore saved registers using MOV insns. First register
6511 is restored from POINTER + OFFSET. */
6513 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6514 int maybe_eh_return)
6517 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6519 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6520 if (ix86_save_reg (regno, maybe_eh_return))
6522 /* Ensure that adjust_address won't be forced to produce pointer
6523 out of range allowed by x86-64 instruction set. */
6524 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6528 r11 = gen_rtx_REG (DImode, R11_REG);
6529 emit_move_insn (r11, GEN_INT (offset));
6530 emit_insn (gen_adddi3 (r11, r11, pointer));
6531 base_address = gen_rtx_MEM (Pmode, r11);
6534 emit_move_insn (gen_rtx_REG (Pmode, regno),
6535 adjust_address (base_address, Pmode, offset));
6536 offset += UNITS_PER_WORD;
6540 /* Restore function stack, frame, and registers. */
6543 ix86_expand_epilogue (int style)
6546 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6547 struct ix86_frame frame;
6548 HOST_WIDE_INT offset;
6550 ix86_compute_frame_layout (&frame);
6552 /* Calculate start of saved registers relative to ebp. Special care
6553 must be taken for the normal return case of a function using
6554 eh_return: the eax and edx registers are marked as saved, but not
6555 restored along this path. */
6556 offset = frame.nregs;
6557 if (current_function_calls_eh_return && style != 2)
6559 offset *= -UNITS_PER_WORD;
6561 /* If we're only restoring one register and sp is not valid then
6562 using a move instruction to restore the register since it's
6563 less work than reloading sp and popping the register.
6565 The default code result in stack adjustment using add/lea instruction,
6566 while this code results in LEAVE instruction (or discrete equivalent),
6567 so it is profitable in some other cases as well. Especially when there
6568 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6569 and there is exactly one register to pop. This heuristic may need some
6570 tuning in future. */
6571 if ((!sp_valid && frame.nregs <= 1)
6572 || (TARGET_EPILOGUE_USING_MOVE
6573 && cfun->machine->use_fast_prologue_epilogue
6574 && (frame.nregs > 1 || frame.to_allocate))
6575 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6576 || (frame_pointer_needed && TARGET_USE_LEAVE
6577 && cfun->machine->use_fast_prologue_epilogue
6578 && frame.nregs == 1)
6579 || current_function_calls_eh_return)
6581 /* Restore registers. We can use ebp or esp to address the memory
6582 locations. If both are available, default to ebp, since offsets
6583 are known to be small. Only exception is esp pointing directly to the
6584 end of block of saved registers, where we may simplify addressing
6587 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6588 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6589 frame.to_allocate, style == 2);
6591 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6592 offset, style == 2);
6594 /* eh_return epilogues need %ecx added to the stack pointer. */
6597 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6599 if (frame_pointer_needed)
6601 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6602 tmp = plus_constant (tmp, UNITS_PER_WORD);
6603 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6605 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6606 emit_move_insn (hard_frame_pointer_rtx, tmp);
6608 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6613 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6614 tmp = plus_constant (tmp, (frame.to_allocate
6615 + frame.nregs * UNITS_PER_WORD));
6616 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6619 else if (!frame_pointer_needed)
6620 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6621 GEN_INT (frame.to_allocate
6622 + frame.nregs * UNITS_PER_WORD),
6624 /* If not an i386, mov & pop is faster than "leave". */
6625 else if (TARGET_USE_LEAVE || optimize_size
6626 || !cfun->machine->use_fast_prologue_epilogue)
6627 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6630 pro_epilogue_adjust_stack (stack_pointer_rtx,
6631 hard_frame_pointer_rtx,
6634 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6636 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6641 /* First step is to deallocate the stack frame so that we can
6642 pop the registers. */
6645 gcc_assert (frame_pointer_needed);
6646 pro_epilogue_adjust_stack (stack_pointer_rtx,
6647 hard_frame_pointer_rtx,
6648 GEN_INT (offset), style);
6650 else if (frame.to_allocate)
6651 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6652 GEN_INT (frame.to_allocate), style);
6654 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6655 if (ix86_save_reg (regno, false))
6658 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6660 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6662 if (frame_pointer_needed)
6664 /* Leave results in shorter dependency chains on CPUs that are
6665 able to grok it fast. */
6666 if (TARGET_USE_LEAVE)
6667 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6668 else if (TARGET_64BIT)
6669 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6671 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6675 if (cfun->machine->force_align_arg_pointer)
6677 emit_insn (gen_addsi3 (stack_pointer_rtx,
6678 cfun->machine->force_align_arg_pointer,
6682 /* Sibcall epilogues don't want a return instruction. */
6686 if (current_function_pops_args && current_function_args_size)
6688 rtx popc = GEN_INT (current_function_pops_args);
6690 /* i386 can only pop 64K bytes. If asked to pop more, pop
6691 return address, do explicit add, and jump indirectly to the
6694 if (current_function_pops_args >= 65536)
6696 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6698 /* There is no "pascal" calling convention in any 64bit ABI. */
6699 gcc_assert (!TARGET_64BIT);
6701 emit_insn (gen_popsi1 (ecx));
6702 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6703 emit_jump_insn (gen_return_indirect_internal (ecx));
6706 emit_jump_insn (gen_return_pop_internal (popc));
6709 emit_jump_insn (gen_return_internal ());
6712 /* Reset from the function's potential modifications. */
6715 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6716 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6718 if (pic_offset_table_rtx)
6719 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6721 /* Mach-O doesn't support labels at the end of objects, so if
6722 it looks like we might want one, insert a NOP. */
6724 rtx insn = get_last_insn ();
6727 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6728 insn = PREV_INSN (insn);
6732 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6733 fputs ("\tnop\n", file);
6739 /* Extract the parts of an RTL expression that is a valid memory address
6740 for an instruction. Return 0 if the structure of the address is
6741 grossly off. Return -1 if the address contains ASHIFT, so it is not
6742 strictly valid, but still used for computing length of lea instruction. */
6745 ix86_decompose_address (rtx addr, struct ix86_address *out)
6747 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6748 rtx base_reg, index_reg;
6749 HOST_WIDE_INT scale = 1;
6750 rtx scale_rtx = NULL_RTX;
6752 enum ix86_address_seg seg = SEG_DEFAULT;
6754 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6756 else if (GET_CODE (addr) == PLUS)
6766 addends[n++] = XEXP (op, 1);
6769 while (GET_CODE (op) == PLUS);
6774 for (i = n; i >= 0; --i)
6777 switch (GET_CODE (op))
6782 index = XEXP (op, 0);
6783 scale_rtx = XEXP (op, 1);
6787 if (XINT (op, 1) == UNSPEC_TP
6788 && TARGET_TLS_DIRECT_SEG_REFS
6789 && seg == SEG_DEFAULT)
6790 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6819 else if (GET_CODE (addr) == MULT)
6821 index = XEXP (addr, 0); /* index*scale */
6822 scale_rtx = XEXP (addr, 1);
6824 else if (GET_CODE (addr) == ASHIFT)
6828 /* We're called for lea too, which implements ashift on occasion. */
6829 index = XEXP (addr, 0);
6830 tmp = XEXP (addr, 1);
6831 if (!CONST_INT_P (tmp))
6833 scale = INTVAL (tmp);
6834 if ((unsigned HOST_WIDE_INT) scale > 3)
6840 disp = addr; /* displacement */
6842 /* Extract the integral value of scale. */
6845 if (!CONST_INT_P (scale_rtx))
6847 scale = INTVAL (scale_rtx);
6850 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6851 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6853 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6854 if (base_reg && index_reg && scale == 1
6855 && (index_reg == arg_pointer_rtx
6856 || index_reg == frame_pointer_rtx
6857 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6860 tmp = base, base = index, index = tmp;
6861 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6864 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6865 if ((base_reg == hard_frame_pointer_rtx
6866 || base_reg == frame_pointer_rtx
6867 || base_reg == arg_pointer_rtx) && !disp)
6870 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6871 Avoid this by transforming to [%esi+0]. */
6872 if (TARGET_K6 && !optimize_size
6873 && base_reg && !index_reg && !disp
6875 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6878 /* Special case: encode reg+reg instead of reg*2. */
6879 if (!base && index && scale && scale == 2)
6880 base = index, base_reg = index_reg, scale = 1;
6882 /* Special case: scaling cannot be encoded without base or displacement. */
6883 if (!base && !disp && index && scale != 1)
6895 /* Return cost of the memory address x.
6896 For i386, it is better to use a complex address than let gcc copy
6897 the address into a reg and make a new pseudo. But not if the address
6898 requires to two regs - that would mean more pseudos with longer
6901 ix86_address_cost (rtx x)
6903 struct ix86_address parts;
6905 int ok = ix86_decompose_address (x, &parts);
6909 if (parts.base && GET_CODE (parts.base) == SUBREG)
6910 parts.base = SUBREG_REG (parts.base);
6911 if (parts.index && GET_CODE (parts.index) == SUBREG)
6912 parts.index = SUBREG_REG (parts.index);
6914 /* Attempt to minimize number of registers in the address. */
6916 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6918 && (!REG_P (parts.index)
6919 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6923 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6925 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6926 && parts.base != parts.index)
6929 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6930 since it's predecode logic can't detect the length of instructions
6931 and it degenerates to vector decoded. Increase cost of such
6932 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6933 to split such addresses or even refuse such addresses at all.
6935 Following addressing modes are affected:
6940 The first and last case may be avoidable by explicitly coding the zero in
6941 memory address, but I don't have AMD-K6 machine handy to check this
6945 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6946 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6947 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6953 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6954 this is used for to form addresses to local data when -fPIC is in
6958 darwin_local_data_pic (rtx disp)
6960 if (GET_CODE (disp) == MINUS)
6962 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6963 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6964 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6966 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6967 if (! strcmp (sym_name, "<pic base>"))
6975 /* Determine if a given RTX is a valid constant. We already know this
6976 satisfies CONSTANT_P. */
6979 legitimate_constant_p (rtx x)
6981 switch (GET_CODE (x))
6986 if (GET_CODE (x) == PLUS)
6988 if (!CONST_INT_P (XEXP (x, 1)))
6993 if (TARGET_MACHO && darwin_local_data_pic (x))
6996 /* Only some unspecs are valid as "constants". */
6997 if (GET_CODE (x) == UNSPEC)
6998 switch (XINT (x, 1))
7003 return TARGET_64BIT;
7006 x = XVECEXP (x, 0, 0);
7007 return (GET_CODE (x) == SYMBOL_REF
7008 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7010 x = XVECEXP (x, 0, 0);
7011 return (GET_CODE (x) == SYMBOL_REF
7012 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7017 /* We must have drilled down to a symbol. */
7018 if (GET_CODE (x) == LABEL_REF)
7020 if (GET_CODE (x) != SYMBOL_REF)
7025 /* TLS symbols are never valid. */
7026 if (SYMBOL_REF_TLS_MODEL (x))
7029 /* DLLIMPORT symbols are never valid. */
7030 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7031 && SYMBOL_REF_DLLIMPORT_P (x))
7036 if (GET_MODE (x) == TImode
7037 && x != CONST0_RTX (TImode)
7043 if (x == CONST0_RTX (GET_MODE (x)))
7051 /* Otherwise we handle everything else in the move patterns. */
7055 /* Determine if it's legal to put X into the constant pool. This
7056 is not possible for the address of thread-local symbols, which
7057 is checked above. */
7060 ix86_cannot_force_const_mem (rtx x)
7062 /* We can always put integral constants and vectors in memory. */
7063 switch (GET_CODE (x))
7073 return !legitimate_constant_p (x);
7076 /* Determine if a given RTX is a valid constant address. */
7079 constant_address_p (rtx x)
7081 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7084 /* Nonzero if the constant value X is a legitimate general operand
7085 when generating PIC code. It is given that flag_pic is on and
7086 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7089 legitimate_pic_operand_p (rtx x)
7093 switch (GET_CODE (x))
7096 inner = XEXP (x, 0);
7097 if (GET_CODE (inner) == PLUS
7098 && CONST_INT_P (XEXP (inner, 1)))
7099 inner = XEXP (inner, 0);
7101 /* Only some unspecs are valid as "constants". */
7102 if (GET_CODE (inner) == UNSPEC)
7103 switch (XINT (inner, 1))
7108 return TARGET_64BIT;
7110 x = XVECEXP (inner, 0, 0);
7111 return (GET_CODE (x) == SYMBOL_REF
7112 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7120 return legitimate_pic_address_disp_p (x);
7127 /* Determine if a given CONST RTX is a valid memory displacement
7131 legitimate_pic_address_disp_p (rtx disp)
7135 /* In 64bit mode we can allow direct addresses of symbols and labels
7136 when they are not dynamic symbols. */
7139 rtx op0 = disp, op1;
7141 switch (GET_CODE (disp))
7147 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7149 op0 = XEXP (XEXP (disp, 0), 0);
7150 op1 = XEXP (XEXP (disp, 0), 1);
7151 if (!CONST_INT_P (op1)
7152 || INTVAL (op1) >= 16*1024*1024
7153 || INTVAL (op1) < -16*1024*1024)
7155 if (GET_CODE (op0) == LABEL_REF)
7157 if (GET_CODE (op0) != SYMBOL_REF)
7162 /* TLS references should always be enclosed in UNSPEC. */
7163 if (SYMBOL_REF_TLS_MODEL (op0))
7165 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7166 && ix86_cmodel != CM_LARGE_PIC)
7174 if (GET_CODE (disp) != CONST)
7176 disp = XEXP (disp, 0);
7180 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7181 of GOT tables. We should not need these anyway. */
7182 if (GET_CODE (disp) != UNSPEC
7183 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7184 && XINT (disp, 1) != UNSPEC_GOTOFF
7185 && XINT (disp, 1) != UNSPEC_PLTOFF))
7188 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7189 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7195 if (GET_CODE (disp) == PLUS)
7197 if (!CONST_INT_P (XEXP (disp, 1)))
7199 disp = XEXP (disp, 0);
7203 if (TARGET_MACHO && darwin_local_data_pic (disp))
7206 if (GET_CODE (disp) != UNSPEC)
7209 switch (XINT (disp, 1))
7214 /* We need to check for both symbols and labels because VxWorks loads
7215 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7217 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7218 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7220 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7221 While ABI specify also 32bit relocation but we don't produce it in
7222 small PIC model at all. */
7223 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7224 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7226 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7228 case UNSPEC_GOTTPOFF:
7229 case UNSPEC_GOTNTPOFF:
7230 case UNSPEC_INDNTPOFF:
7233 disp = XVECEXP (disp, 0, 0);
7234 return (GET_CODE (disp) == SYMBOL_REF
7235 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7237 disp = XVECEXP (disp, 0, 0);
7238 return (GET_CODE (disp) == SYMBOL_REF
7239 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7241 disp = XVECEXP (disp, 0, 0);
7242 return (GET_CODE (disp) == SYMBOL_REF
7243 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7249 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7250 memory address for an instruction. The MODE argument is the machine mode
7251 for the MEM expression that wants to use this address.
7253 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7254 convert common non-canonical forms to canonical form so that they will
7258 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7259 rtx addr, int strict)
7261 struct ix86_address parts;
7262 rtx base, index, disp;
7263 HOST_WIDE_INT scale;
7264 const char *reason = NULL;
7265 rtx reason_rtx = NULL_RTX;
7267 if (ix86_decompose_address (addr, &parts) <= 0)
7269 reason = "decomposition failed";
7274 index = parts.index;
7276 scale = parts.scale;
7278 /* Validate base register.
7280 Don't allow SUBREG's that span more than a word here. It can lead to spill
7281 failures when the base is one word out of a two word structure, which is
7282 represented internally as a DImode int. */
7291 else if (GET_CODE (base) == SUBREG
7292 && REG_P (SUBREG_REG (base))
7293 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7295 reg = SUBREG_REG (base);
7298 reason = "base is not a register";
7302 if (GET_MODE (base) != Pmode)
7304 reason = "base is not in Pmode";
7308 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7309 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7311 reason = "base is not valid";
7316 /* Validate index register.
7318 Don't allow SUBREG's that span more than a word here -- same as above. */
7327 else if (GET_CODE (index) == SUBREG
7328 && REG_P (SUBREG_REG (index))
7329 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7331 reg = SUBREG_REG (index);
7334 reason = "index is not a register";
7338 if (GET_MODE (index) != Pmode)
7340 reason = "index is not in Pmode";
7344 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7345 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7347 reason = "index is not valid";
7352 /* Validate scale factor. */
7355 reason_rtx = GEN_INT (scale);
7358 reason = "scale without index";
7362 if (scale != 2 && scale != 4 && scale != 8)
7364 reason = "scale is not a valid multiplier";
7369 /* Validate displacement. */
7374 if (GET_CODE (disp) == CONST
7375 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7376 switch (XINT (XEXP (disp, 0), 1))
7378 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7379 used. While ABI specify also 32bit relocations, we don't produce
7380 them at all and use IP relative instead. */
7383 gcc_assert (flag_pic);
7385 goto is_legitimate_pic;
7386 reason = "64bit address unspec";
7389 case UNSPEC_GOTPCREL:
7390 gcc_assert (flag_pic);
7391 goto is_legitimate_pic;
7393 case UNSPEC_GOTTPOFF:
7394 case UNSPEC_GOTNTPOFF:
7395 case UNSPEC_INDNTPOFF:
7401 reason = "invalid address unspec";
7405 else if (SYMBOLIC_CONST (disp)
7409 && MACHOPIC_INDIRECT
7410 && !machopic_operand_p (disp)
7416 if (TARGET_64BIT && (index || base))
7418 /* foo@dtpoff(%rX) is ok. */
7419 if (GET_CODE (disp) != CONST
7420 || GET_CODE (XEXP (disp, 0)) != PLUS
7421 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7422 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7423 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7424 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7426 reason = "non-constant pic memory reference";
7430 else if (! legitimate_pic_address_disp_p (disp))
7432 reason = "displacement is an invalid pic construct";
7436 /* This code used to verify that a symbolic pic displacement
7437 includes the pic_offset_table_rtx register.
7439 While this is good idea, unfortunately these constructs may
7440 be created by "adds using lea" optimization for incorrect
7449 This code is nonsensical, but results in addressing
7450 GOT table with pic_offset_table_rtx base. We can't
7451 just refuse it easily, since it gets matched by
7452 "addsi3" pattern, that later gets split to lea in the
7453 case output register differs from input. While this
7454 can be handled by separate addsi pattern for this case
7455 that never results in lea, this seems to be easier and
7456 correct fix for crash to disable this test. */
7458 else if (GET_CODE (disp) != LABEL_REF
7459 && !CONST_INT_P (disp)
7460 && (GET_CODE (disp) != CONST
7461 || !legitimate_constant_p (disp))
7462 && (GET_CODE (disp) != SYMBOL_REF
7463 || !legitimate_constant_p (disp)))
7465 reason = "displacement is not constant";
7468 else if (TARGET_64BIT
7469 && !x86_64_immediate_operand (disp, VOIDmode))
7471 reason = "displacement is out of range";
7476 /* Everything looks valid. */
7483 /* Return a unique alias set for the GOT. */
7485 static alias_set_type
7486 ix86_GOT_alias_set (void)
7488 static alias_set_type set = -1;
7490 set = new_alias_set ();
7494 /* Return a legitimate reference for ORIG (an address) using the
7495 register REG. If REG is 0, a new pseudo is generated.
7497 There are two types of references that must be handled:
7499 1. Global data references must load the address from the GOT, via
7500 the PIC reg. An insn is emitted to do this load, and the reg is
7503 2. Static data references, constant pool addresses, and code labels
7504 compute the address as an offset from the GOT, whose base is in
7505 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7506 differentiate them from global data objects. The returned
7507 address is the PIC reg + an unspec constant.
7509 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7510 reg also appears in the address. */
7513 legitimize_pic_address (rtx orig, rtx reg)
7520 if (TARGET_MACHO && !TARGET_64BIT)
7523 reg = gen_reg_rtx (Pmode);
7524 /* Use the generic Mach-O PIC machinery. */
7525 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7529 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7531 else if (TARGET_64BIT
7532 && ix86_cmodel != CM_SMALL_PIC
7533 && gotoff_operand (addr, Pmode))
7536 /* This symbol may be referenced via a displacement from the PIC
7537 base address (@GOTOFF). */
7539 if (reload_in_progress)
7540 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7541 if (GET_CODE (addr) == CONST)
7542 addr = XEXP (addr, 0);
7543 if (GET_CODE (addr) == PLUS)
7545 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7547 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7550 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7551 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7553 tmpreg = gen_reg_rtx (Pmode);
7556 emit_move_insn (tmpreg, new_rtx);
7560 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7561 tmpreg, 1, OPTAB_DIRECT);
7564 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7566 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7568 /* This symbol may be referenced via a displacement from the PIC
7569 base address (@GOTOFF). */
7571 if (reload_in_progress)
7572 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7573 if (GET_CODE (addr) == CONST)
7574 addr = XEXP (addr, 0);
7575 if (GET_CODE (addr) == PLUS)
7577 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7579 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7582 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7583 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7584 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7588 emit_move_insn (reg, new_rtx);
7592 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7593 /* We can't use @GOTOFF for text labels on VxWorks;
7594 see gotoff_operand. */
7595 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7597 /* Given that we've already handled dllimport variables separately
7598 in legitimize_address, and all other variables should satisfy
7599 legitimate_pic_address_disp_p, we should never arrive here. */
7600 gcc_assert (!TARGET_64BIT_MS_ABI);
7602 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7604 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7605 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7606 new_rtx = gen_const_mem (Pmode, new_rtx);
7607 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7610 reg = gen_reg_rtx (Pmode);
7611 /* Use directly gen_movsi, otherwise the address is loaded
7612 into register for CSE. We don't want to CSE this addresses,
7613 instead we CSE addresses from the GOT table, so skip this. */
7614 emit_insn (gen_movsi (reg, new_rtx));
7619 /* This symbol must be referenced via a load from the
7620 Global Offset Table (@GOT). */
7622 if (reload_in_progress)
7623 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7624 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7625 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7627 new_rtx = force_reg (Pmode, new_rtx);
7628 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7629 new_rtx = gen_const_mem (Pmode, new_rtx);
7630 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7633 reg = gen_reg_rtx (Pmode);
7634 emit_move_insn (reg, new_rtx);
7640 if (CONST_INT_P (addr)
7641 && !x86_64_immediate_operand (addr, VOIDmode))
7645 emit_move_insn (reg, addr);
7649 new_rtx = force_reg (Pmode, addr);
7651 else if (GET_CODE (addr) == CONST)
7653 addr = XEXP (addr, 0);
7655 /* We must match stuff we generate before. Assume the only
7656 unspecs that can get here are ours. Not that we could do
7657 anything with them anyway.... */
7658 if (GET_CODE (addr) == UNSPEC
7659 || (GET_CODE (addr) == PLUS
7660 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7662 gcc_assert (GET_CODE (addr) == PLUS);
7664 if (GET_CODE (addr) == PLUS)
7666 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7668 /* Check first to see if this is a constant offset from a @GOTOFF
7669 symbol reference. */
7670 if (gotoff_operand (op0, Pmode)
7671 && CONST_INT_P (op1))
7675 if (reload_in_progress)
7676 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7677 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7679 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7680 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7681 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7685 emit_move_insn (reg, new_rtx);
7691 if (INTVAL (op1) < -16*1024*1024
7692 || INTVAL (op1) >= 16*1024*1024)
7694 if (!x86_64_immediate_operand (op1, Pmode))
7695 op1 = force_reg (Pmode, op1);
7696 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7702 base = legitimize_pic_address (XEXP (addr, 0), reg);
7703 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7704 base == reg ? NULL_RTX : reg);
7706 if (CONST_INT_P (new_rtx))
7707 new_rtx = plus_constant (base, INTVAL (new_rtx));
7710 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7712 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7713 new_rtx = XEXP (new_rtx, 1);
7715 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7723 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7726 get_thread_pointer (int to_reg)
7730 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7734 reg = gen_reg_rtx (Pmode);
7735 insn = gen_rtx_SET (VOIDmode, reg, tp);
7736 insn = emit_insn (insn);
7741 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7742 false if we expect this to be used for a memory address and true if
7743 we expect to load the address into a register. */
7746 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7748 rtx dest, base, off, pic, tp;
7753 case TLS_MODEL_GLOBAL_DYNAMIC:
7754 dest = gen_reg_rtx (Pmode);
7755 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7757 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7759 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7762 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7763 insns = get_insns ();
7766 CONST_OR_PURE_CALL_P (insns) = 1;
7767 emit_libcall_block (insns, dest, rax, x);
7769 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7770 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7772 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7774 if (TARGET_GNU2_TLS)
7776 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7778 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7782 case TLS_MODEL_LOCAL_DYNAMIC:
7783 base = gen_reg_rtx (Pmode);
7784 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7786 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7788 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7791 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7792 insns = get_insns ();
7795 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7796 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7797 CONST_OR_PURE_CALL_P (insns) = 1;
7798 emit_libcall_block (insns, base, rax, note);
7800 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7801 emit_insn (gen_tls_local_dynamic_base_64 (base));
7803 emit_insn (gen_tls_local_dynamic_base_32 (base));
7805 if (TARGET_GNU2_TLS)
7807 rtx x = ix86_tls_module_base ();
7809 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7810 gen_rtx_MINUS (Pmode, x, tp));
7813 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7814 off = gen_rtx_CONST (Pmode, off);
7816 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7818 if (TARGET_GNU2_TLS)
7820 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7822 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7827 case TLS_MODEL_INITIAL_EXEC:
7831 type = UNSPEC_GOTNTPOFF;
7835 if (reload_in_progress)
7836 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7837 pic = pic_offset_table_rtx;
7838 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7840 else if (!TARGET_ANY_GNU_TLS)
7842 pic = gen_reg_rtx (Pmode);
7843 emit_insn (gen_set_got (pic));
7844 type = UNSPEC_GOTTPOFF;
7849 type = UNSPEC_INDNTPOFF;
7852 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7853 off = gen_rtx_CONST (Pmode, off);
7855 off = gen_rtx_PLUS (Pmode, pic, off);
7856 off = gen_const_mem (Pmode, off);
7857 set_mem_alias_set (off, ix86_GOT_alias_set ());
7859 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7861 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7862 off = force_reg (Pmode, off);
7863 return gen_rtx_PLUS (Pmode, base, off);
7867 base = get_thread_pointer (true);
7868 dest = gen_reg_rtx (Pmode);
7869 emit_insn (gen_subsi3 (dest, base, off));
7873 case TLS_MODEL_LOCAL_EXEC:
7874 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7875 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7876 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7877 off = gen_rtx_CONST (Pmode, off);
7879 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7881 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7882 return gen_rtx_PLUS (Pmode, base, off);
7886 base = get_thread_pointer (true);
7887 dest = gen_reg_rtx (Pmode);
7888 emit_insn (gen_subsi3 (dest, base, off));
7899 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7902 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7903 htab_t dllimport_map;
7906 get_dllimport_decl (tree decl)
7908 struct tree_map *h, in;
7912 size_t namelen, prefixlen;
7918 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7920 in.hash = htab_hash_pointer (decl);
7921 in.base.from = decl;
7922 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7923 h = (struct tree_map *) *loc;
7927 *loc = h = GGC_NEW (struct tree_map);
7929 h->base.from = decl;
7930 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7931 DECL_ARTIFICIAL (to) = 1;
7932 DECL_IGNORED_P (to) = 1;
7933 DECL_EXTERNAL (to) = 1;
7934 TREE_READONLY (to) = 1;
7936 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7937 name = targetm.strip_name_encoding (name);
7938 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
7939 namelen = strlen (name);
7940 prefixlen = strlen (prefix);
7941 imp_name = (char *) alloca (namelen + prefixlen + 1);
7942 memcpy (imp_name, prefix, prefixlen);
7943 memcpy (imp_name + prefixlen, name, namelen + 1);
7945 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7946 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7947 SET_SYMBOL_REF_DECL (rtl, to);
7948 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7950 rtl = gen_const_mem (Pmode, rtl);
7951 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7953 SET_DECL_RTL (to, rtl);
7954 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
7959 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7960 true if we require the result be a register. */
7963 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7968 gcc_assert (SYMBOL_REF_DECL (symbol));
7969 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7971 x = DECL_RTL (imp_decl);
7973 x = force_reg (Pmode, x);
7977 /* Try machine-dependent ways of modifying an illegitimate address
7978 to be legitimate. If we find one, return the new, valid address.
7979 This macro is used in only one place: `memory_address' in explow.c.
7981 OLDX is the address as it was before break_out_memory_refs was called.
7982 In some cases it is useful to look at this to decide what needs to be done.
7984 MODE and WIN are passed so that this macro can use
7985 GO_IF_LEGITIMATE_ADDRESS.
7987 It is always safe for this macro to do nothing. It exists to recognize
7988 opportunities to optimize the output.
7990 For the 80386, we handle X+REG by loading X into a register R and
7991 using R+REG. R will go in a general reg and indexing will be used.
7992 However, if REG is a broken-out memory address or multiplication,
7993 nothing needs to be done because REG can certainly go in a general reg.
7995 When -fpic is used, special handling is needed for symbolic references.
7996 See comments by legitimize_pic_address in i386.c for details. */
7999 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8004 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8006 return legitimize_tls_address (x, (enum tls_model) log, false);
8007 if (GET_CODE (x) == CONST
8008 && GET_CODE (XEXP (x, 0)) == PLUS
8009 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8010 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8012 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8013 (enum tls_model) log, false);
8014 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8017 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8019 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8020 return legitimize_dllimport_symbol (x, true);
8021 if (GET_CODE (x) == CONST
8022 && GET_CODE (XEXP (x, 0)) == PLUS
8023 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8024 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8026 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8027 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8031 if (flag_pic && SYMBOLIC_CONST (x))
8032 return legitimize_pic_address (x, 0);
8034 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8035 if (GET_CODE (x) == ASHIFT
8036 && CONST_INT_P (XEXP (x, 1))
8037 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8040 log = INTVAL (XEXP (x, 1));
8041 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8042 GEN_INT (1 << log));
8045 if (GET_CODE (x) == PLUS)
8047 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8049 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8050 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8051 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8054 log = INTVAL (XEXP (XEXP (x, 0), 1));
8055 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8056 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8057 GEN_INT (1 << log));
8060 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8061 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8062 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8065 log = INTVAL (XEXP (XEXP (x, 1), 1));
8066 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8067 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8068 GEN_INT (1 << log));
8071 /* Put multiply first if it isn't already. */
8072 if (GET_CODE (XEXP (x, 1)) == MULT)
8074 rtx tmp = XEXP (x, 0);
8075 XEXP (x, 0) = XEXP (x, 1);
8080 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8081 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8082 created by virtual register instantiation, register elimination, and
8083 similar optimizations. */
8084 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8087 x = gen_rtx_PLUS (Pmode,
8088 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8089 XEXP (XEXP (x, 1), 0)),
8090 XEXP (XEXP (x, 1), 1));
8094 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8095 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8096 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8097 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8098 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8099 && CONSTANT_P (XEXP (x, 1)))
8102 rtx other = NULL_RTX;
8104 if (CONST_INT_P (XEXP (x, 1)))
8106 constant = XEXP (x, 1);
8107 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8109 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8111 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8112 other = XEXP (x, 1);
8120 x = gen_rtx_PLUS (Pmode,
8121 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8122 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8123 plus_constant (other, INTVAL (constant)));
8127 if (changed && legitimate_address_p (mode, x, FALSE))
8130 if (GET_CODE (XEXP (x, 0)) == MULT)
8133 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8136 if (GET_CODE (XEXP (x, 1)) == MULT)
8139 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8143 && REG_P (XEXP (x, 1))
8144 && REG_P (XEXP (x, 0)))
8147 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8150 x = legitimize_pic_address (x, 0);
8153 if (changed && legitimate_address_p (mode, x, FALSE))
8156 if (REG_P (XEXP (x, 0)))
8158 rtx temp = gen_reg_rtx (Pmode);
8159 rtx val = force_operand (XEXP (x, 1), temp);
8161 emit_move_insn (temp, val);
8167 else if (REG_P (XEXP (x, 1)))
8169 rtx temp = gen_reg_rtx (Pmode);
8170 rtx val = force_operand (XEXP (x, 0), temp);
8172 emit_move_insn (temp, val);
8182 /* Print an integer constant expression in assembler syntax. Addition
8183 and subtraction are the only arithmetic that may appear in these
8184 expressions. FILE is the stdio stream to write to, X is the rtx, and
8185 CODE is the operand print code from the output string. */
8188 output_pic_addr_const (FILE *file, rtx x, int code)
8192 switch (GET_CODE (x))
8195 gcc_assert (flag_pic);
8200 if (! TARGET_MACHO || TARGET_64BIT)
8201 output_addr_const (file, x);
8204 const char *name = XSTR (x, 0);
8206 /* Mark the decl as referenced so that cgraph will
8207 output the function. */
8208 if (SYMBOL_REF_DECL (x))
8209 mark_decl_referenced (SYMBOL_REF_DECL (x));
8212 if (MACHOPIC_INDIRECT
8213 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8214 name = machopic_indirection_name (x, /*stub_p=*/true);
8216 assemble_name (file, name);
8218 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8219 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8220 fputs ("@PLT", file);
8227 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8228 assemble_name (asm_out_file, buf);
8232 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8236 /* This used to output parentheses around the expression,
8237 but that does not work on the 386 (either ATT or BSD assembler). */
8238 output_pic_addr_const (file, XEXP (x, 0), code);
8242 if (GET_MODE (x) == VOIDmode)
8244 /* We can use %d if the number is <32 bits and positive. */
8245 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8246 fprintf (file, "0x%lx%08lx",
8247 (unsigned long) CONST_DOUBLE_HIGH (x),
8248 (unsigned long) CONST_DOUBLE_LOW (x));
8250 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8253 /* We can't handle floating point constants;
8254 PRINT_OPERAND must handle them. */
8255 output_operand_lossage ("floating constant misused");
8259 /* Some assemblers need integer constants to appear first. */
8260 if (CONST_INT_P (XEXP (x, 0)))
8262 output_pic_addr_const (file, XEXP (x, 0), code);
8264 output_pic_addr_const (file, XEXP (x, 1), code);
8268 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8269 output_pic_addr_const (file, XEXP (x, 1), code);
8271 output_pic_addr_const (file, XEXP (x, 0), code);
8277 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8278 output_pic_addr_const (file, XEXP (x, 0), code);
8280 output_pic_addr_const (file, XEXP (x, 1), code);
8282 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8286 gcc_assert (XVECLEN (x, 0) == 1);
8287 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8288 switch (XINT (x, 1))
8291 fputs ("@GOT", file);
8294 fputs ("@GOTOFF", file);
8297 fputs ("@PLTOFF", file);
8299 case UNSPEC_GOTPCREL:
8300 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8301 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8303 case UNSPEC_GOTTPOFF:
8304 /* FIXME: This might be @TPOFF in Sun ld too. */
8305 fputs ("@GOTTPOFF", file);
8308 fputs ("@TPOFF", file);
8312 fputs ("@TPOFF", file);
8314 fputs ("@NTPOFF", file);
8317 fputs ("@DTPOFF", file);
8319 case UNSPEC_GOTNTPOFF:
8321 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8322 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8324 fputs ("@GOTNTPOFF", file);
8326 case UNSPEC_INDNTPOFF:
8327 fputs ("@INDNTPOFF", file);
8330 output_operand_lossage ("invalid UNSPEC as operand");
8336 output_operand_lossage ("invalid expression as operand");
8340 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8341 We need to emit DTP-relative relocations. */
8343 static void ATTRIBUTE_UNUSED
8344 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8346 fputs (ASM_LONG, file);
8347 output_addr_const (file, x);
8348 fputs ("@DTPOFF", file);
8354 fputs (", 0", file);
8361 /* In the name of slightly smaller debug output, and to cater to
8362 general assembler lossage, recognize PIC+GOTOFF and turn it back
8363 into a direct symbol reference.
8365 On Darwin, this is necessary to avoid a crash, because Darwin
8366 has a different PIC label for each routine but the DWARF debugging
8367 information is not associated with any particular routine, so it's
8368 necessary to remove references to the PIC label from RTL stored by
8369 the DWARF output code. */
8372 ix86_delegitimize_address (rtx orig_x)
8375 /* reg_addend is NULL or a multiple of some register. */
8376 rtx reg_addend = NULL_RTX;
8377 /* const_addend is NULL or a const_int. */
8378 rtx const_addend = NULL_RTX;
8379 /* This is the result, or NULL. */
8380 rtx result = NULL_RTX;
8387 if (GET_CODE (x) != CONST
8388 || GET_CODE (XEXP (x, 0)) != UNSPEC
8389 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8392 return XVECEXP (XEXP (x, 0), 0, 0);
8395 if (GET_CODE (x) != PLUS
8396 || GET_CODE (XEXP (x, 1)) != CONST)
8399 if (REG_P (XEXP (x, 0))
8400 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8401 /* %ebx + GOT/GOTOFF */
8403 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8405 /* %ebx + %reg * scale + GOT/GOTOFF */
8406 reg_addend = XEXP (x, 0);
8407 if (REG_P (XEXP (reg_addend, 0))
8408 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8409 reg_addend = XEXP (reg_addend, 1);
8410 else if (REG_P (XEXP (reg_addend, 1))
8411 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8412 reg_addend = XEXP (reg_addend, 0);
8415 if (!REG_P (reg_addend)
8416 && GET_CODE (reg_addend) != MULT
8417 && GET_CODE (reg_addend) != ASHIFT)
8423 x = XEXP (XEXP (x, 1), 0);
8424 if (GET_CODE (x) == PLUS
8425 && CONST_INT_P (XEXP (x, 1)))
8427 const_addend = XEXP (x, 1);
8431 if (GET_CODE (x) == UNSPEC
8432 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8433 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8434 result = XVECEXP (x, 0, 0);
8436 if (TARGET_MACHO && darwin_local_data_pic (x)
8438 result = XEXP (x, 0);
8444 result = gen_rtx_PLUS (Pmode, result, const_addend);
8446 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8450 /* If X is a machine specific address (i.e. a symbol or label being
8451 referenced as a displacement from the GOT implemented using an
8452 UNSPEC), then return the base term. Otherwise return X. */
8455 ix86_find_base_term (rtx x)
8461 if (GET_CODE (x) != CONST)
8464 if (GET_CODE (term) == PLUS
8465 && (CONST_INT_P (XEXP (term, 1))
8466 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8467 term = XEXP (term, 0);
8468 if (GET_CODE (term) != UNSPEC
8469 || XINT (term, 1) != UNSPEC_GOTPCREL)
8472 term = XVECEXP (term, 0, 0);
8474 if (GET_CODE (term) != SYMBOL_REF
8475 && GET_CODE (term) != LABEL_REF)
8481 term = ix86_delegitimize_address (x);
8483 if (GET_CODE (term) != SYMBOL_REF
8484 && GET_CODE (term) != LABEL_REF)
8491 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8496 if (mode == CCFPmode || mode == CCFPUmode)
8498 enum rtx_code second_code, bypass_code;
8499 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8500 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8501 code = ix86_fp_compare_code_to_integer (code);
8505 code = reverse_condition (code);
8556 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8560 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8561 Those same assemblers have the same but opposite lossage on cmov. */
8563 suffix = fp ? "nbe" : "a";
8564 else if (mode == CCCmode)
8587 gcc_assert (mode == CCmode || mode == CCCmode);
8609 gcc_assert (mode == CCmode || mode == CCCmode);
8610 suffix = fp ? "nb" : "ae";
8613 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8620 else if (mode == CCCmode)
8621 suffix = fp ? "nb" : "ae";
8626 suffix = fp ? "u" : "p";
8629 suffix = fp ? "nu" : "np";
8634 fputs (suffix, file);
8637 /* Print the name of register X to FILE based on its machine mode and number.
8638 If CODE is 'w', pretend the mode is HImode.
8639 If CODE is 'b', pretend the mode is QImode.
8640 If CODE is 'k', pretend the mode is SImode.
8641 If CODE is 'q', pretend the mode is DImode.
8642 If CODE is 'h', pretend the reg is the 'high' byte register.
8643 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8646 print_reg (rtx x, int code, FILE *file)
8648 gcc_assert (x == pc_rtx
8649 || (REGNO (x) != ARG_POINTER_REGNUM
8650 && REGNO (x) != FRAME_POINTER_REGNUM
8651 && REGNO (x) != FLAGS_REG
8652 && REGNO (x) != FPSR_REG
8653 && REGNO (x) != FPCR_REG));
8655 if (ASSEMBLER_DIALECT == ASM_ATT)
8660 gcc_assert (TARGET_64BIT);
8661 fputs ("rip", file);
8665 if (code == 'w' || MMX_REG_P (x))
8667 else if (code == 'b')
8669 else if (code == 'k')
8671 else if (code == 'q')
8673 else if (code == 'y')
8675 else if (code == 'h')
8678 code = GET_MODE_SIZE (GET_MODE (x));
8680 /* Irritatingly, AMD extended registers use different naming convention
8681 from the normal registers. */
8682 if (REX_INT_REG_P (x))
8684 gcc_assert (TARGET_64BIT);
8688 error ("extended registers have no high halves");
8691 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8694 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8697 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8700 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8703 error ("unsupported operand size for extended register");
8711 if (STACK_TOP_P (x))
8713 fputs ("st(0)", file);
8720 if (! ANY_FP_REG_P (x))
8721 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8726 fputs (hi_reg_name[REGNO (x)], file);
8729 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8731 fputs (qi_reg_name[REGNO (x)], file);
8734 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8736 fputs (qi_high_reg_name[REGNO (x)], file);
8743 /* Locate some local-dynamic symbol still in use by this function
8744 so that we can print its name in some tls_local_dynamic_base
8748 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8752 if (GET_CODE (x) == SYMBOL_REF
8753 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8755 cfun->machine->some_ld_name = XSTR (x, 0);
8763 get_some_local_dynamic_name (void)
8767 if (cfun->machine->some_ld_name)
8768 return cfun->machine->some_ld_name;
8770 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8772 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8773 return cfun->machine->some_ld_name;
8779 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8780 C -- print opcode suffix for set/cmov insn.
8781 c -- like C, but print reversed condition
8782 F,f -- likewise, but for floating-point.
8783 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8785 R -- print the prefix for register names.
8786 z -- print the opcode suffix for the size of the current operand.
8787 * -- print a star (in certain assembler syntax)
8788 A -- print an absolute memory reference.
8789 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8790 s -- print a shift double count, followed by the assemblers argument
8792 b -- print the QImode name of the register for the indicated operand.
8793 %b0 would print %al if operands[0] is reg 0.
8794 w -- likewise, print the HImode name of the register.
8795 k -- likewise, print the SImode name of the register.
8796 q -- likewise, print the DImode name of the register.
8797 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8798 y -- print "st(0)" instead of "st" as a register.
8799 D -- print condition for SSE cmp instruction.
8800 P -- if PIC, print an @PLT suffix.
8801 X -- don't print any sort of PIC '@' suffix for a symbol.
8802 & -- print some in-use local-dynamic symbol name.
8803 H -- print a memory address offset by 8; used for sse high-parts
8804 Y -- print condition for SSE5 com* instruction.
8805 + -- print a branch hint as 'cs' or 'ds' prefix
8806 ; -- print a semicolon (after prefixes due to bug in older gas).
8810 print_operand (FILE *file, rtx x, int code)
8817 if (ASSEMBLER_DIALECT == ASM_ATT)
8822 assemble_name (file, get_some_local_dynamic_name ());
8826 switch (ASSEMBLER_DIALECT)
8833 /* Intel syntax. For absolute addresses, registers should not
8834 be surrounded by braces. */
8838 PRINT_OPERAND (file, x, 0);
8848 PRINT_OPERAND (file, x, 0);
8853 if (ASSEMBLER_DIALECT == ASM_ATT)
8858 if (ASSEMBLER_DIALECT == ASM_ATT)
8863 if (ASSEMBLER_DIALECT == ASM_ATT)
8868 if (ASSEMBLER_DIALECT == ASM_ATT)
8873 if (ASSEMBLER_DIALECT == ASM_ATT)
8878 if (ASSEMBLER_DIALECT == ASM_ATT)
8883 /* 387 opcodes don't get size suffixes if the operands are
8885 if (STACK_REG_P (x))
8888 /* Likewise if using Intel opcodes. */
8889 if (ASSEMBLER_DIALECT == ASM_INTEL)
8892 /* This is the size of op from size of operand. */
8893 switch (GET_MODE_SIZE (GET_MODE (x)))
8902 #ifdef HAVE_GAS_FILDS_FISTS
8912 if (GET_MODE (x) == SFmode)
8927 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8929 #ifdef GAS_MNEMONICS
8955 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8957 PRINT_OPERAND (file, x, 0);
8963 /* Little bit of braindamage here. The SSE compare instructions
8964 does use completely different names for the comparisons that the
8965 fp conditional moves. */
8966 switch (GET_CODE (x))
8981 fputs ("unord", file);
8985 fputs ("neq", file);
8989 fputs ("nlt", file);
8993 fputs ("nle", file);
8996 fputs ("ord", file);
9003 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9004 if (ASSEMBLER_DIALECT == ASM_ATT)
9006 switch (GET_MODE (x))
9008 case HImode: putc ('w', file); break;
9010 case SFmode: putc ('l', file); break;
9012 case DFmode: putc ('q', file); break;
9013 default: gcc_unreachable ();
9020 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9023 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9024 if (ASSEMBLER_DIALECT == ASM_ATT)
9027 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9030 /* Like above, but reverse condition */
9032 /* Check to see if argument to %c is really a constant
9033 and not a condition code which needs to be reversed. */
9034 if (!COMPARISON_P (x))
9036 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9039 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9042 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9043 if (ASSEMBLER_DIALECT == ASM_ATT)
9046 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9050 /* It doesn't actually matter what mode we use here, as we're
9051 only going to use this for printing. */
9052 x = adjust_address_nv (x, DImode, 8);
9059 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9062 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9065 int pred_val = INTVAL (XEXP (x, 0));
9067 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9068 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9070 int taken = pred_val > REG_BR_PROB_BASE / 2;
9071 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9073 /* Emit hints only in the case default branch prediction
9074 heuristics would fail. */
9075 if (taken != cputaken)
9077 /* We use 3e (DS) prefix for taken branches and
9078 2e (CS) prefix for not taken branches. */
9080 fputs ("ds ; ", file);
9082 fputs ("cs ; ", file);
9090 switch (GET_CODE (x))
9093 fputs ("neq", file);
9100 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9104 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9115 fputs ("unord", file);
9118 fputs ("ord", file);
9121 fputs ("ueq", file);
9124 fputs ("nlt", file);
9127 fputs ("nle", file);
9130 fputs ("ule", file);
9133 fputs ("ult", file);
9136 fputs ("une", file);
9145 fputs (" ; ", file);
9152 output_operand_lossage ("invalid operand code '%c'", code);
9157 print_reg (x, code, file);
9161 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9162 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9163 && GET_MODE (x) != BLKmode)
9166 switch (GET_MODE_SIZE (GET_MODE (x)))
9168 case 1: size = "BYTE"; break;
9169 case 2: size = "WORD"; break;
9170 case 4: size = "DWORD"; break;
9171 case 8: size = "QWORD"; break;
9172 case 12: size = "XWORD"; break;
9174 if (GET_MODE (x) == XFmode)
9183 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9186 else if (code == 'w')
9188 else if (code == 'k')
9192 fputs (" PTR ", file);
9196 /* Avoid (%rip) for call operands. */
9197 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9198 && !CONST_INT_P (x))
9199 output_addr_const (file, x);
9200 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9201 output_operand_lossage ("invalid constraints for operand");
9206 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9211 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9212 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9214 if (ASSEMBLER_DIALECT == ASM_ATT)
9216 fprintf (file, "0x%08lx", l);
9219 /* These float cases don't actually occur as immediate operands. */
9220 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9224 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9225 fprintf (file, "%s", dstr);
9228 else if (GET_CODE (x) == CONST_DOUBLE
9229 && GET_MODE (x) == XFmode)
9233 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9234 fprintf (file, "%s", dstr);
9239 /* We have patterns that allow zero sets of memory, for instance.
9240 In 64-bit mode, we should probably support all 8-byte vectors,
9241 since we can in fact encode that into an immediate. */
9242 if (GET_CODE (x) == CONST_VECTOR)
9244 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9250 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9252 if (ASSEMBLER_DIALECT == ASM_ATT)
9255 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9256 || GET_CODE (x) == LABEL_REF)
9258 if (ASSEMBLER_DIALECT == ASM_ATT)
9261 fputs ("OFFSET FLAT:", file);
9264 if (CONST_INT_P (x))
9265 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9267 output_pic_addr_const (file, x, code);
9269 output_addr_const (file, x);
9273 /* Print a memory operand whose address is ADDR. */
9276 print_operand_address (FILE *file, rtx addr)
9278 struct ix86_address parts;
9279 rtx base, index, disp;
9281 int ok = ix86_decompose_address (addr, &parts);
9286 index = parts.index;
9288 scale = parts.scale;
9296 if (ASSEMBLER_DIALECT == ASM_ATT)
9298 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9304 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9305 if (TARGET_64BIT && !base && !index)
9309 if (GET_CODE (disp) == CONST
9310 && GET_CODE (XEXP (disp, 0)) == PLUS
9311 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9312 symbol = XEXP (XEXP (disp, 0), 0);
9314 if (GET_CODE (symbol) == LABEL_REF
9315 || (GET_CODE (symbol) == SYMBOL_REF
9316 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9319 if (!base && !index)
9321 /* Displacement only requires special attention. */
9323 if (CONST_INT_P (disp))
9325 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9326 fputs ("ds:", file);
9327 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9330 output_pic_addr_const (file, disp, 0);
9332 output_addr_const (file, disp);
9336 if (ASSEMBLER_DIALECT == ASM_ATT)
9341 output_pic_addr_const (file, disp, 0);
9342 else if (GET_CODE (disp) == LABEL_REF)
9343 output_asm_label (disp);
9345 output_addr_const (file, disp);
9350 print_reg (base, 0, file);
9354 print_reg (index, 0, file);
9356 fprintf (file, ",%d", scale);
9362 rtx offset = NULL_RTX;
9366 /* Pull out the offset of a symbol; print any symbol itself. */
9367 if (GET_CODE (disp) == CONST
9368 && GET_CODE (XEXP (disp, 0)) == PLUS
9369 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9371 offset = XEXP (XEXP (disp, 0), 1);
9372 disp = gen_rtx_CONST (VOIDmode,
9373 XEXP (XEXP (disp, 0), 0));
9377 output_pic_addr_const (file, disp, 0);
9378 else if (GET_CODE (disp) == LABEL_REF)
9379 output_asm_label (disp);
9380 else if (CONST_INT_P (disp))
9383 output_addr_const (file, disp);
9389 print_reg (base, 0, file);
9392 if (INTVAL (offset) >= 0)
9394 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9398 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9405 print_reg (index, 0, file);
9407 fprintf (file, "*%d", scale);
9415 output_addr_const_extra (FILE *file, rtx x)
9419 if (GET_CODE (x) != UNSPEC)
9422 op = XVECEXP (x, 0, 0);
9423 switch (XINT (x, 1))
9425 case UNSPEC_GOTTPOFF:
9426 output_addr_const (file, op);
9427 /* FIXME: This might be @TPOFF in Sun ld. */
9428 fputs ("@GOTTPOFF", file);
9431 output_addr_const (file, op);
9432 fputs ("@TPOFF", file);
9435 output_addr_const (file, op);
9437 fputs ("@TPOFF", file);
9439 fputs ("@NTPOFF", file);
9442 output_addr_const (file, op);
9443 fputs ("@DTPOFF", file);
9445 case UNSPEC_GOTNTPOFF:
9446 output_addr_const (file, op);
9448 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9449 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9451 fputs ("@GOTNTPOFF", file);
9453 case UNSPEC_INDNTPOFF:
9454 output_addr_const (file, op);
9455 fputs ("@INDNTPOFF", file);
9465 /* Split one or more DImode RTL references into pairs of SImode
9466 references. The RTL can be REG, offsettable MEM, integer constant, or
9467 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9468 split and "num" is its length. lo_half and hi_half are output arrays
9469 that parallel "operands". */
9472 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9476 rtx op = operands[num];
9478 /* simplify_subreg refuse to split volatile memory addresses,
9479 but we still have to handle it. */
9482 lo_half[num] = adjust_address (op, SImode, 0);
9483 hi_half[num] = adjust_address (op, SImode, 4);
9487 lo_half[num] = simplify_gen_subreg (SImode, op,
9488 GET_MODE (op) == VOIDmode
9489 ? DImode : GET_MODE (op), 0);
9490 hi_half[num] = simplify_gen_subreg (SImode, op,
9491 GET_MODE (op) == VOIDmode
9492 ? DImode : GET_MODE (op), 4);
9496 /* Split one or more TImode RTL references into pairs of DImode
9497 references. The RTL can be REG, offsettable MEM, integer constant, or
9498 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9499 split and "num" is its length. lo_half and hi_half are output arrays
9500 that parallel "operands". */
9503 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9507 rtx op = operands[num];
9509 /* simplify_subreg refuse to split volatile memory addresses, but we
9510 still have to handle it. */
9513 lo_half[num] = adjust_address (op, DImode, 0);
9514 hi_half[num] = adjust_address (op, DImode, 8);
9518 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9519 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9524 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9525 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9526 is the expression of the binary operation. The output may either be
9527 emitted here, or returned to the caller, like all output_* functions.
9529 There is no guarantee that the operands are the same mode, as they
9530 might be within FLOAT or FLOAT_EXTEND expressions. */
9532 #ifndef SYSV386_COMPAT
9533 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9534 wants to fix the assemblers because that causes incompatibility
9535 with gcc. No-one wants to fix gcc because that causes
9536 incompatibility with assemblers... You can use the option of
9537 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9538 #define SYSV386_COMPAT 1
9542 output_387_binary_op (rtx insn, rtx *operands)
9544 static char buf[30];
9547 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9549 #ifdef ENABLE_CHECKING
9550 /* Even if we do not want to check the inputs, this documents input
9551 constraints. Which helps in understanding the following code. */
9552 if (STACK_REG_P (operands[0])
9553 && ((REG_P (operands[1])
9554 && REGNO (operands[0]) == REGNO (operands[1])
9555 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9556 || (REG_P (operands[2])
9557 && REGNO (operands[0]) == REGNO (operands[2])
9558 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9559 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9562 gcc_assert (is_sse);
9565 switch (GET_CODE (operands[3]))
9568 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9569 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9577 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9578 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9586 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9587 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9595 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9596 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9610 if (GET_MODE (operands[0]) == SFmode)
9611 strcat (buf, "ss\t{%2, %0|%0, %2}");
9613 strcat (buf, "sd\t{%2, %0|%0, %2}");
9618 switch (GET_CODE (operands[3]))
9622 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9624 rtx temp = operands[2];
9625 operands[2] = operands[1];
9629 /* know operands[0] == operands[1]. */
9631 if (MEM_P (operands[2]))
9637 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9639 if (STACK_TOP_P (operands[0]))
9640 /* How is it that we are storing to a dead operand[2]?
9641 Well, presumably operands[1] is dead too. We can't
9642 store the result to st(0) as st(0) gets popped on this
9643 instruction. Instead store to operands[2] (which I
9644 think has to be st(1)). st(1) will be popped later.
9645 gcc <= 2.8.1 didn't have this check and generated
9646 assembly code that the Unixware assembler rejected. */
9647 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9649 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9653 if (STACK_TOP_P (operands[0]))
9654 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9656 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9661 if (MEM_P (operands[1]))
9667 if (MEM_P (operands[2]))
9673 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9676 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9677 derived assemblers, confusingly reverse the direction of
9678 the operation for fsub{r} and fdiv{r} when the
9679 destination register is not st(0). The Intel assembler
9680 doesn't have this brain damage. Read !SYSV386_COMPAT to
9681 figure out what the hardware really does. */
9682 if (STACK_TOP_P (operands[0]))
9683 p = "{p\t%0, %2|rp\t%2, %0}";
9685 p = "{rp\t%2, %0|p\t%0, %2}";
9687 if (STACK_TOP_P (operands[0]))
9688 /* As above for fmul/fadd, we can't store to st(0). */
9689 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9691 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9696 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9699 if (STACK_TOP_P (operands[0]))
9700 p = "{rp\t%0, %1|p\t%1, %0}";
9702 p = "{p\t%1, %0|rp\t%0, %1}";
9704 if (STACK_TOP_P (operands[0]))
9705 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9707 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9712 if (STACK_TOP_P (operands[0]))
9714 if (STACK_TOP_P (operands[1]))
9715 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9717 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9720 else if (STACK_TOP_P (operands[1]))
9723 p = "{\t%1, %0|r\t%0, %1}";
9725 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9731 p = "{r\t%2, %0|\t%0, %2}";
9733 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9746 /* Return needed mode for entity in optimize_mode_switching pass. */
9749 ix86_mode_needed (int entity, rtx insn)
9751 enum attr_i387_cw mode;
9753 /* The mode UNINITIALIZED is used to store control word after a
9754 function call or ASM pattern. The mode ANY specify that function
9755 has no requirements on the control word and make no changes in the
9756 bits we are interested in. */
9759 || (NONJUMP_INSN_P (insn)
9760 && (asm_noperands (PATTERN (insn)) >= 0
9761 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9762 return I387_CW_UNINITIALIZED;
9764 if (recog_memoized (insn) < 0)
9767 mode = get_attr_i387_cw (insn);
9772 if (mode == I387_CW_TRUNC)
9777 if (mode == I387_CW_FLOOR)
9782 if (mode == I387_CW_CEIL)
9787 if (mode == I387_CW_MASK_PM)
9798 /* Output code to initialize control word copies used by trunc?f?i and
9799 rounding patterns. CURRENT_MODE is set to current control word,
9800 while NEW_MODE is set to new control word. */
9803 emit_i387_cw_initialization (int mode)
9805 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9808 enum ix86_stack_slot slot;
9810 rtx reg = gen_reg_rtx (HImode);
9812 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9813 emit_move_insn (reg, copy_rtx (stored_mode));
9815 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9820 /* round toward zero (truncate) */
9821 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9822 slot = SLOT_CW_TRUNC;
9826 /* round down toward -oo */
9827 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9828 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9829 slot = SLOT_CW_FLOOR;
9833 /* round up toward +oo */
9834 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9835 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9836 slot = SLOT_CW_CEIL;
9839 case I387_CW_MASK_PM:
9840 /* mask precision exception for nearbyint() */
9841 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9842 slot = SLOT_CW_MASK_PM;
9854 /* round toward zero (truncate) */
9855 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9856 slot = SLOT_CW_TRUNC;
9860 /* round down toward -oo */
9861 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9862 slot = SLOT_CW_FLOOR;
9866 /* round up toward +oo */
9867 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9868 slot = SLOT_CW_CEIL;
9871 case I387_CW_MASK_PM:
9872 /* mask precision exception for nearbyint() */
9873 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9874 slot = SLOT_CW_MASK_PM;
9882 gcc_assert (slot < MAX_386_STACK_LOCALS);
9884 new_mode = assign_386_stack_local (HImode, slot);
9885 emit_move_insn (new_mode, reg);
9888 /* Output code for INSN to convert a float to a signed int. OPERANDS
9889 are the insn operands. The output may be [HSD]Imode and the input
9890 operand may be [SDX]Fmode. */
9893 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9895 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9896 int dimode_p = GET_MODE (operands[0]) == DImode;
9897 int round_mode = get_attr_i387_cw (insn);
9899 /* Jump through a hoop or two for DImode, since the hardware has no
9900 non-popping instruction. We used to do this a different way, but
9901 that was somewhat fragile and broke with post-reload splitters. */
9902 if ((dimode_p || fisttp) && !stack_top_dies)
9903 output_asm_insn ("fld\t%y1", operands);
9905 gcc_assert (STACK_TOP_P (operands[1]));
9906 gcc_assert (MEM_P (operands[0]));
9907 gcc_assert (GET_MODE (operands[1]) != TFmode);
9910 output_asm_insn ("fisttp%z0\t%0", operands);
9913 if (round_mode != I387_CW_ANY)
9914 output_asm_insn ("fldcw\t%3", operands);
9915 if (stack_top_dies || dimode_p)
9916 output_asm_insn ("fistp%z0\t%0", operands);
9918 output_asm_insn ("fist%z0\t%0", operands);
9919 if (round_mode != I387_CW_ANY)
9920 output_asm_insn ("fldcw\t%2", operands);
9926 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9927 have the values zero or one, indicates the ffreep insn's operand
9928 from the OPERANDS array. */
9931 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9933 if (TARGET_USE_FFREEP)
9934 #if HAVE_AS_IX86_FFREEP
9935 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9938 static char retval[] = ".word\t0xc_df";
9939 int regno = REGNO (operands[opno]);
9941 gcc_assert (FP_REGNO_P (regno));
9943 retval[9] = '0' + (regno - FIRST_STACK_REG);
9948 return opno ? "fstp\t%y1" : "fstp\t%y0";
9952 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9953 should be used. UNORDERED_P is true when fucom should be used. */
9956 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9959 rtx cmp_op0, cmp_op1;
9960 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9964 cmp_op0 = operands[0];
9965 cmp_op1 = operands[1];
9969 cmp_op0 = operands[1];
9970 cmp_op1 = operands[2];
9975 if (GET_MODE (operands[0]) == SFmode)
9977 return "ucomiss\t{%1, %0|%0, %1}";
9979 return "comiss\t{%1, %0|%0, %1}";
9982 return "ucomisd\t{%1, %0|%0, %1}";
9984 return "comisd\t{%1, %0|%0, %1}";
9987 gcc_assert (STACK_TOP_P (cmp_op0));
9989 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9991 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9995 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9996 return output_387_ffreep (operands, 1);
9999 return "ftst\n\tfnstsw\t%0";
10002 if (STACK_REG_P (cmp_op1)
10004 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10005 && REGNO (cmp_op1) != FIRST_STACK_REG)
10007 /* If both the top of the 387 stack dies, and the other operand
10008 is also a stack register that dies, then this must be a
10009 `fcompp' float compare */
10013 /* There is no double popping fcomi variant. Fortunately,
10014 eflags is immune from the fstp's cc clobbering. */
10016 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10018 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10019 return output_387_ffreep (operands, 0);
10024 return "fucompp\n\tfnstsw\t%0";
10026 return "fcompp\n\tfnstsw\t%0";
10031 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10033 static const char * const alt[16] =
10035 "fcom%z2\t%y2\n\tfnstsw\t%0",
10036 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10037 "fucom%z2\t%y2\n\tfnstsw\t%0",
10038 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10040 "ficom%z2\t%y2\n\tfnstsw\t%0",
10041 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10045 "fcomi\t{%y1, %0|%0, %y1}",
10046 "fcomip\t{%y1, %0|%0, %y1}",
10047 "fucomi\t{%y1, %0|%0, %y1}",
10048 "fucomip\t{%y1, %0|%0, %y1}",
10059 mask = eflags_p << 3;
10060 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10061 mask |= unordered_p << 1;
10062 mask |= stack_top_dies;
10064 gcc_assert (mask < 16);
10073 ix86_output_addr_vec_elt (FILE *file, int value)
10075 const char *directive = ASM_LONG;
10079 directive = ASM_QUAD;
10081 gcc_assert (!TARGET_64BIT);
10084 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10088 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10090 const char *directive = ASM_LONG;
10093 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10094 directive = ASM_QUAD;
10096 gcc_assert (!TARGET_64BIT);
10098 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10099 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10100 fprintf (file, "%s%s%d-%s%d\n",
10101 directive, LPREFIX, value, LPREFIX, rel);
10102 else if (HAVE_AS_GOTOFF_IN_DATA)
10103 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10105 else if (TARGET_MACHO)
10107 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10108 machopic_output_function_base_name (file);
10109 fprintf(file, "\n");
10113 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10114 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10117 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10121 ix86_expand_clear (rtx dest)
10125 /* We play register width games, which are only valid after reload. */
10126 gcc_assert (reload_completed);
10128 /* Avoid HImode and its attendant prefix byte. */
10129 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10130 dest = gen_rtx_REG (SImode, REGNO (dest));
10131 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10133 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10134 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10136 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10137 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10143 /* X is an unchanging MEM. If it is a constant pool reference, return
10144 the constant pool rtx, else NULL. */
10147 maybe_get_pool_constant (rtx x)
10149 x = ix86_delegitimize_address (XEXP (x, 0));
10151 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10152 return get_pool_constant (x);
10158 ix86_expand_move (enum machine_mode mode, rtx operands[])
10161 enum tls_model model;
10166 if (GET_CODE (op1) == SYMBOL_REF)
10168 model = SYMBOL_REF_TLS_MODEL (op1);
10171 op1 = legitimize_tls_address (op1, model, true);
10172 op1 = force_operand (op1, op0);
10176 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10177 && SYMBOL_REF_DLLIMPORT_P (op1))
10178 op1 = legitimize_dllimport_symbol (op1, false);
10180 else if (GET_CODE (op1) == CONST
10181 && GET_CODE (XEXP (op1, 0)) == PLUS
10182 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10184 rtx addend = XEXP (XEXP (op1, 0), 1);
10185 rtx symbol = XEXP (XEXP (op1, 0), 0);
10188 model = SYMBOL_REF_TLS_MODEL (symbol);
10190 tmp = legitimize_tls_address (symbol, model, true);
10191 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10192 && SYMBOL_REF_DLLIMPORT_P (symbol))
10193 tmp = legitimize_dllimport_symbol (symbol, true);
10197 tmp = force_operand (tmp, NULL);
10198 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10199 op0, 1, OPTAB_DIRECT);
10205 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10207 if (TARGET_MACHO && !TARGET_64BIT)
10212 rtx temp = ((reload_in_progress
10213 || ((op0 && REG_P (op0))
10215 ? op0 : gen_reg_rtx (Pmode));
10216 op1 = machopic_indirect_data_reference (op1, temp);
10217 op1 = machopic_legitimize_pic_address (op1, mode,
10218 temp == op1 ? 0 : temp);
10220 else if (MACHOPIC_INDIRECT)
10221 op1 = machopic_indirect_data_reference (op1, 0);
10229 op1 = force_reg (Pmode, op1);
10230 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10232 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10233 op1 = legitimize_pic_address (op1, reg);
10242 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10243 || !push_operand (op0, mode))
10245 op1 = force_reg (mode, op1);
10247 if (push_operand (op0, mode)
10248 && ! general_no_elim_operand (op1, mode))
10249 op1 = copy_to_mode_reg (mode, op1);
10251 /* Force large constants in 64bit compilation into register
10252 to get them CSEed. */
10253 if (can_create_pseudo_p ()
10254 && (mode == DImode) && TARGET_64BIT
10255 && immediate_operand (op1, mode)
10256 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10257 && !register_operand (op0, mode)
10259 op1 = copy_to_mode_reg (mode, op1);
10261 if (can_create_pseudo_p ()
10262 && FLOAT_MODE_P (mode)
10263 && GET_CODE (op1) == CONST_DOUBLE)
10265 /* If we are loading a floating point constant to a register,
10266 force the value to memory now, since we'll get better code
10267 out the back end. */
10269 op1 = validize_mem (force_const_mem (mode, op1));
10270 if (!register_operand (op0, mode))
10272 rtx temp = gen_reg_rtx (mode);
10273 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10274 emit_move_insn (op0, temp);
10280 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10284 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10286 rtx op0 = operands[0], op1 = operands[1];
10287 unsigned int align = GET_MODE_ALIGNMENT (mode);
10289 /* Force constants other than zero into memory. We do not know how
10290 the instructions used to build constants modify the upper 64 bits
10291 of the register, once we have that information we may be able
10292 to handle some of them more efficiently. */
10293 if (can_create_pseudo_p ()
10294 && register_operand (op0, mode)
10295 && (CONSTANT_P (op1)
10296 || (GET_CODE (op1) == SUBREG
10297 && CONSTANT_P (SUBREG_REG (op1))))
10298 && standard_sse_constant_p (op1) <= 0)
10299 op1 = validize_mem (force_const_mem (mode, op1));
10301 /* TDmode values are passed as TImode on the stack. TImode values
10302 are moved via xmm registers, and moving them to stack can result in
10303 unaligned memory access. Use ix86_expand_vector_move_misalign()
10304 if memory operand is not aligned correctly. */
10305 if (can_create_pseudo_p ()
10306 && (mode == TImode) && !TARGET_64BIT
10307 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10308 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10312 /* ix86_expand_vector_move_misalign() does not like constants ... */
10313 if (CONSTANT_P (op1)
10314 || (GET_CODE (op1) == SUBREG
10315 && CONSTANT_P (SUBREG_REG (op1))))
10316 op1 = validize_mem (force_const_mem (mode, op1));
10318 /* ... nor both arguments in memory. */
10319 if (!register_operand (op0, mode)
10320 && !register_operand (op1, mode))
10321 op1 = force_reg (mode, op1);
10323 tmp[0] = op0; tmp[1] = op1;
10324 ix86_expand_vector_move_misalign (mode, tmp);
10328 /* Make operand1 a register if it isn't already. */
10329 if (can_create_pseudo_p ()
10330 && !register_operand (op0, mode)
10331 && !register_operand (op1, mode))
10333 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10337 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10340 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10341 straight to ix86_expand_vector_move. */
10342 /* Code generation for scalar reg-reg moves of single and double precision data:
10343 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10347 if (x86_sse_partial_reg_dependency == true)
10352 Code generation for scalar loads of double precision data:
10353 if (x86_sse_split_regs == true)
10354 movlpd mem, reg (gas syntax)
10358 Code generation for unaligned packed loads of single precision data
10359 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10360 if (x86_sse_unaligned_move_optimal)
10363 if (x86_sse_partial_reg_dependency == true)
10375 Code generation for unaligned packed loads of double precision data
10376 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10377 if (x86_sse_unaligned_move_optimal)
10380 if (x86_sse_split_regs == true)
10393 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10402 /* If we're optimizing for size, movups is the smallest. */
10405 op0 = gen_lowpart (V4SFmode, op0);
10406 op1 = gen_lowpart (V4SFmode, op1);
10407 emit_insn (gen_sse_movups (op0, op1));
10411 /* ??? If we have typed data, then it would appear that using
10412 movdqu is the only way to get unaligned data loaded with
10414 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10416 op0 = gen_lowpart (V16QImode, op0);
10417 op1 = gen_lowpart (V16QImode, op1);
10418 emit_insn (gen_sse2_movdqu (op0, op1));
10422 if (TARGET_SSE2 && mode == V2DFmode)
10426 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10428 op0 = gen_lowpart (V2DFmode, op0);
10429 op1 = gen_lowpart (V2DFmode, op1);
10430 emit_insn (gen_sse2_movupd (op0, op1));
10434 /* When SSE registers are split into halves, we can avoid
10435 writing to the top half twice. */
10436 if (TARGET_SSE_SPLIT_REGS)
10438 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10443 /* ??? Not sure about the best option for the Intel chips.
10444 The following would seem to satisfy; the register is
10445 entirely cleared, breaking the dependency chain. We
10446 then store to the upper half, with a dependency depth
10447 of one. A rumor has it that Intel recommends two movsd
10448 followed by an unpacklpd, but this is unconfirmed. And
10449 given that the dependency depth of the unpacklpd would
10450 still be one, I'm not sure why this would be better. */
10451 zero = CONST0_RTX (V2DFmode);
10454 m = adjust_address (op1, DFmode, 0);
10455 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10456 m = adjust_address (op1, DFmode, 8);
10457 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10461 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10463 op0 = gen_lowpart (V4SFmode, op0);
10464 op1 = gen_lowpart (V4SFmode, op1);
10465 emit_insn (gen_sse_movups (op0, op1));
10469 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10470 emit_move_insn (op0, CONST0_RTX (mode));
10472 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10474 if (mode != V4SFmode)
10475 op0 = gen_lowpart (V4SFmode, op0);
10476 m = adjust_address (op1, V2SFmode, 0);
10477 emit_insn (gen_sse_loadlps (op0, op0, m));
10478 m = adjust_address (op1, V2SFmode, 8);
10479 emit_insn (gen_sse_loadhps (op0, op0, m));
10482 else if (MEM_P (op0))
10484 /* If we're optimizing for size, movups is the smallest. */
10487 op0 = gen_lowpart (V4SFmode, op0);
10488 op1 = gen_lowpart (V4SFmode, op1);
10489 emit_insn (gen_sse_movups (op0, op1));
10493 /* ??? Similar to above, only less clear because of quote
10494 typeless stores unquote. */
10495 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10496 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10498 op0 = gen_lowpart (V16QImode, op0);
10499 op1 = gen_lowpart (V16QImode, op1);
10500 emit_insn (gen_sse2_movdqu (op0, op1));
10504 if (TARGET_SSE2 && mode == V2DFmode)
10506 m = adjust_address (op0, DFmode, 0);
10507 emit_insn (gen_sse2_storelpd (m, op1));
10508 m = adjust_address (op0, DFmode, 8);
10509 emit_insn (gen_sse2_storehpd (m, op1));
10513 if (mode != V4SFmode)
10514 op1 = gen_lowpart (V4SFmode, op1);
10515 m = adjust_address (op0, V2SFmode, 0);
10516 emit_insn (gen_sse_storelps (m, op1));
10517 m = adjust_address (op0, V2SFmode, 8);
10518 emit_insn (gen_sse_storehps (m, op1));
10522 gcc_unreachable ();
10525 /* Expand a push in MODE. This is some mode for which we do not support
10526 proper push instructions, at least from the registers that we expect
10527 the value to live in. */
10530 ix86_expand_push (enum machine_mode mode, rtx x)
10534 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10535 GEN_INT (-GET_MODE_SIZE (mode)),
10536 stack_pointer_rtx, 1, OPTAB_DIRECT);
10537 if (tmp != stack_pointer_rtx)
10538 emit_move_insn (stack_pointer_rtx, tmp);
10540 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10541 emit_move_insn (tmp, x);
10544 /* Helper function of ix86_fixup_binary_operands to canonicalize
10545 operand order. Returns true if the operands should be swapped. */
10548 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10551 rtx dst = operands[0];
10552 rtx src1 = operands[1];
10553 rtx src2 = operands[2];
10555 /* If the operation is not commutative, we can't do anything. */
10556 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10559 /* Highest priority is that src1 should match dst. */
10560 if (rtx_equal_p (dst, src1))
10562 if (rtx_equal_p (dst, src2))
10565 /* Next highest priority is that immediate constants come second. */
10566 if (immediate_operand (src2, mode))
10568 if (immediate_operand (src1, mode))
10571 /* Lowest priority is that memory references should come second. */
10581 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10582 destination to use for the operation. If different from the true
10583 destination in operands[0], a copy operation will be required. */
10586 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10589 rtx dst = operands[0];
10590 rtx src1 = operands[1];
10591 rtx src2 = operands[2];
10593 /* Canonicalize operand order. */
10594 if (ix86_swap_binary_operands_p (code, mode, operands))
10601 /* Both source operands cannot be in memory. */
10602 if (MEM_P (src1) && MEM_P (src2))
10604 /* Optimization: Only read from memory once. */
10605 if (rtx_equal_p (src1, src2))
10607 src2 = force_reg (mode, src2);
10611 src2 = force_reg (mode, src2);
10614 /* If the destination is memory, and we do not have matching source
10615 operands, do things in registers. */
10616 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10617 dst = gen_reg_rtx (mode);
10619 /* Source 1 cannot be a constant. */
10620 if (CONSTANT_P (src1))
10621 src1 = force_reg (mode, src1);
10623 /* Source 1 cannot be a non-matching memory. */
10624 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10625 src1 = force_reg (mode, src1);
10627 operands[1] = src1;
10628 operands[2] = src2;
10632 /* Similarly, but assume that the destination has already been
10633 set up properly. */
10636 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10637 enum machine_mode mode, rtx operands[])
10639 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10640 gcc_assert (dst == operands[0]);
10643 /* Attempt to expand a binary operator. Make the expansion closer to the
10644 actual machine, then just general_operand, which will allow 3 separate
10645 memory references (one output, two input) in a single insn. */
10648 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10651 rtx src1, src2, dst, op, clob;
10653 dst = ix86_fixup_binary_operands (code, mode, operands);
10654 src1 = operands[1];
10655 src2 = operands[2];
10657 /* Emit the instruction. */
10659 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10660 if (reload_in_progress)
10662 /* Reload doesn't know about the flags register, and doesn't know that
10663 it doesn't want to clobber it. We can only do this with PLUS. */
10664 gcc_assert (code == PLUS);
10669 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10670 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10673 /* Fix up the destination if needed. */
10674 if (dst != operands[0])
10675 emit_move_insn (operands[0], dst);
10678 /* Return TRUE or FALSE depending on whether the binary operator meets the
10679 appropriate constraints. */
10682 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10685 rtx dst = operands[0];
10686 rtx src1 = operands[1];
10687 rtx src2 = operands[2];
10689 /* Both source operands cannot be in memory. */
10690 if (MEM_P (src1) && MEM_P (src2))
10693 /* Canonicalize operand order for commutative operators. */
10694 if (ix86_swap_binary_operands_p (code, mode, operands))
10701 /* If the destination is memory, we must have a matching source operand. */
10702 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10705 /* Source 1 cannot be a constant. */
10706 if (CONSTANT_P (src1))
10709 /* Source 1 cannot be a non-matching memory. */
10710 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10716 /* Attempt to expand a unary operator. Make the expansion closer to the
10717 actual machine, then just general_operand, which will allow 2 separate
10718 memory references (one output, one input) in a single insn. */
10721 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10724 int matching_memory;
10725 rtx src, dst, op, clob;
10730 /* If the destination is memory, and we do not have matching source
10731 operands, do things in registers. */
10732 matching_memory = 0;
10735 if (rtx_equal_p (dst, src))
10736 matching_memory = 1;
10738 dst = gen_reg_rtx (mode);
10741 /* When source operand is memory, destination must match. */
10742 if (MEM_P (src) && !matching_memory)
10743 src = force_reg (mode, src);
10745 /* Emit the instruction. */
10747 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10748 if (reload_in_progress || code == NOT)
10750 /* Reload doesn't know about the flags register, and doesn't know that
10751 it doesn't want to clobber it. */
10752 gcc_assert (code == NOT);
10757 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10758 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10761 /* Fix up the destination if needed. */
10762 if (dst != operands[0])
10763 emit_move_insn (operands[0], dst);
10766 /* Return TRUE or FALSE depending on whether the unary operator meets the
10767 appropriate constraints. */
10770 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10771 enum machine_mode mode ATTRIBUTE_UNUSED,
10772 rtx operands[2] ATTRIBUTE_UNUSED)
10774 /* If one of operands is memory, source and destination must match. */
10775 if ((MEM_P (operands[0])
10776 || MEM_P (operands[1]))
10777 && ! rtx_equal_p (operands[0], operands[1]))
10782 /* Post-reload splitter for converting an SF or DFmode value in an
10783 SSE register into an unsigned SImode. */
10786 ix86_split_convert_uns_si_sse (rtx operands[])
10788 enum machine_mode vecmode;
10789 rtx value, large, zero_or_two31, input, two31, x;
10791 large = operands[1];
10792 zero_or_two31 = operands[2];
10793 input = operands[3];
10794 two31 = operands[4];
10795 vecmode = GET_MODE (large);
10796 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10798 /* Load up the value into the low element. We must ensure that the other
10799 elements are valid floats -- zero is the easiest such value. */
10802 if (vecmode == V4SFmode)
10803 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10805 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10809 input = gen_rtx_REG (vecmode, REGNO (input));
10810 emit_move_insn (value, CONST0_RTX (vecmode));
10811 if (vecmode == V4SFmode)
10812 emit_insn (gen_sse_movss (value, value, input));
10814 emit_insn (gen_sse2_movsd (value, value, input));
10817 emit_move_insn (large, two31);
10818 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10820 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10821 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10823 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10824 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10826 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10827 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10829 large = gen_rtx_REG (V4SImode, REGNO (large));
10830 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10832 x = gen_rtx_REG (V4SImode, REGNO (value));
10833 if (vecmode == V4SFmode)
10834 emit_insn (gen_sse2_cvttps2dq (x, value));
10836 emit_insn (gen_sse2_cvttpd2dq (x, value));
10839 emit_insn (gen_xorv4si3 (value, value, large));
10842 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10843 Expects the 64-bit DImode to be supplied in a pair of integral
10844 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10845 -mfpmath=sse, !optimize_size only. */
10848 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10850 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10851 rtx int_xmm, fp_xmm;
10852 rtx biases, exponents;
10855 int_xmm = gen_reg_rtx (V4SImode);
10856 if (TARGET_INTER_UNIT_MOVES)
10857 emit_insn (gen_movdi_to_sse (int_xmm, input));
10858 else if (TARGET_SSE_SPLIT_REGS)
10860 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10861 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10865 x = gen_reg_rtx (V2DImode);
10866 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10867 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10870 x = gen_rtx_CONST_VECTOR (V4SImode,
10871 gen_rtvec (4, GEN_INT (0x43300000UL),
10872 GEN_INT (0x45300000UL),
10873 const0_rtx, const0_rtx));
10874 exponents = validize_mem (force_const_mem (V4SImode, x));
10876 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10877 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10879 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10880 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10881 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10882 (0x1.0p84 + double(fp_value_hi_xmm)).
10883 Note these exponents differ by 32. */
10885 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10887 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10888 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10889 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10890 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10891 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10892 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10893 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10894 biases = validize_mem (force_const_mem (V2DFmode, biases));
10895 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10897 /* Add the upper and lower DFmode values together. */
10899 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10902 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10903 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10904 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10907 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10910 /* Not used, but eases macroization of patterns. */
10912 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
10913 rtx input ATTRIBUTE_UNUSED)
10915 gcc_unreachable ();
10918 /* Convert an unsigned SImode value into a DFmode. Only currently used
10919 for SSE, but applicable anywhere. */
10922 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10924 REAL_VALUE_TYPE TWO31r;
10927 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10928 NULL, 1, OPTAB_DIRECT);
10930 fp = gen_reg_rtx (DFmode);
10931 emit_insn (gen_floatsidf2 (fp, x));
10933 real_ldexp (&TWO31r, &dconst1, 31);
10934 x = const_double_from_real_value (TWO31r, DFmode);
10936 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10938 emit_move_insn (target, x);
10941 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10942 32-bit mode; otherwise we have a direct convert instruction. */
10945 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10947 REAL_VALUE_TYPE TWO32r;
10948 rtx fp_lo, fp_hi, x;
10950 fp_lo = gen_reg_rtx (DFmode);
10951 fp_hi = gen_reg_rtx (DFmode);
10953 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10955 real_ldexp (&TWO32r, &dconst1, 32);
10956 x = const_double_from_real_value (TWO32r, DFmode);
10957 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10959 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10961 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10964 emit_move_insn (target, x);
10967 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10968 For x86_32, -mfpmath=sse, !optimize_size only. */
10970 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10972 REAL_VALUE_TYPE ONE16r;
10973 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10975 real_ldexp (&ONE16r, &dconst1, 16);
10976 x = const_double_from_real_value (ONE16r, SFmode);
10977 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10978 NULL, 0, OPTAB_DIRECT);
10979 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10980 NULL, 0, OPTAB_DIRECT);
10981 fp_hi = gen_reg_rtx (SFmode);
10982 fp_lo = gen_reg_rtx (SFmode);
10983 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10984 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10985 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10987 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10989 if (!rtx_equal_p (target, fp_hi))
10990 emit_move_insn (target, fp_hi);
10993 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10994 then replicate the value for all elements of the vector
10998 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
11005 v = gen_rtvec (4, value, value, value, value);
11006 return gen_rtx_CONST_VECTOR (V4SImode, v);
11010 v = gen_rtvec (2, value, value);
11011 return gen_rtx_CONST_VECTOR (V2DImode, v);
11015 v = gen_rtvec (4, value, value, value, value);
11017 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11018 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11019 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11023 v = gen_rtvec (2, value, value);
11025 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11026 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11029 gcc_unreachable ();
11033 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11034 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11035 for an SSE register. If VECT is true, then replicate the mask for
11036 all elements of the vector register. If INVERT is true, then create
11037 a mask excluding the sign bit. */
11040 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11042 enum machine_mode vec_mode, imode;
11043 HOST_WIDE_INT hi, lo;
11048 /* Find the sign bit, sign extended to 2*HWI. */
11054 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11055 lo = 0x80000000, hi = lo < 0;
11061 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11062 if (HOST_BITS_PER_WIDE_INT >= 64)
11063 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11065 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11071 vec_mode = VOIDmode;
11072 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11073 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11077 gcc_unreachable ();
11081 lo = ~lo, hi = ~hi;
11083 /* Force this value into the low part of a fp vector constant. */
11084 mask = immed_double_const (lo, hi, imode);
11085 mask = gen_lowpart (mode, mask);
11087 if (vec_mode == VOIDmode)
11088 return force_reg (mode, mask);
11090 v = ix86_build_const_vector (mode, vect, mask);
11091 return force_reg (vec_mode, v);
11094 /* Generate code for floating point ABS or NEG. */
11097 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11100 rtx mask, set, use, clob, dst, src;
11101 bool use_sse = false;
11102 bool vector_mode = VECTOR_MODE_P (mode);
11103 enum machine_mode elt_mode = mode;
11107 elt_mode = GET_MODE_INNER (mode);
11110 else if (mode == TFmode)
11112 else if (TARGET_SSE_MATH)
11113 use_sse = SSE_FLOAT_MODE_P (mode);
11115 /* NEG and ABS performed with SSE use bitwise mask operations.
11116 Create the appropriate mask now. */
11118 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11127 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11128 set = gen_rtx_SET (VOIDmode, dst, set);
11133 set = gen_rtx_fmt_e (code, mode, src);
11134 set = gen_rtx_SET (VOIDmode, dst, set);
11137 use = gen_rtx_USE (VOIDmode, mask);
11138 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11139 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11140 gen_rtvec (3, set, use, clob)));
11147 /* Expand a copysign operation. Special case operand 0 being a constant. */
11150 ix86_expand_copysign (rtx operands[])
11152 enum machine_mode mode, vmode;
11153 rtx dest, op0, op1, mask, nmask;
11155 dest = operands[0];
11159 mode = GET_MODE (dest);
11160 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11162 if (GET_CODE (op0) == CONST_DOUBLE)
11164 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11166 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11167 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11169 if (mode == SFmode || mode == DFmode)
11171 if (op0 == CONST0_RTX (mode))
11172 op0 = CONST0_RTX (vmode);
11177 if (mode == SFmode)
11178 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11179 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11181 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11182 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11186 mask = ix86_build_signbit_mask (mode, 0, 0);
11188 if (mode == SFmode)
11189 copysign_insn = gen_copysignsf3_const;
11190 else if (mode == DFmode)
11191 copysign_insn = gen_copysigndf3_const;
11193 copysign_insn = gen_copysigntf3_const;
11195 emit_insn (copysign_insn (dest, op0, op1, mask));
11199 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11201 nmask = ix86_build_signbit_mask (mode, 0, 1);
11202 mask = ix86_build_signbit_mask (mode, 0, 0);
11204 if (mode == SFmode)
11205 copysign_insn = gen_copysignsf3_var;
11206 else if (mode == DFmode)
11207 copysign_insn = gen_copysigndf3_var;
11209 copysign_insn = gen_copysigntf3_var;
11211 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11215 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11216 be a constant, and so has already been expanded into a vector constant. */
11219 ix86_split_copysign_const (rtx operands[])
11221 enum machine_mode mode, vmode;
11222 rtx dest, op0, op1, mask, x;
11224 dest = operands[0];
11227 mask = operands[3];
11229 mode = GET_MODE (dest);
11230 vmode = GET_MODE (mask);
11232 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11233 x = gen_rtx_AND (vmode, dest, mask);
11234 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11236 if (op0 != CONST0_RTX (vmode))
11238 x = gen_rtx_IOR (vmode, dest, op0);
11239 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11243 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11244 so we have to do two masks. */
11247 ix86_split_copysign_var (rtx operands[])
11249 enum machine_mode mode, vmode;
11250 rtx dest, scratch, op0, op1, mask, nmask, x;
11252 dest = operands[0];
11253 scratch = operands[1];
11256 nmask = operands[4];
11257 mask = operands[5];
11259 mode = GET_MODE (dest);
11260 vmode = GET_MODE (mask);
11262 if (rtx_equal_p (op0, op1))
11264 /* Shouldn't happen often (it's useless, obviously), but when it does
11265 we'd generate incorrect code if we continue below. */
11266 emit_move_insn (dest, op0);
11270 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11272 gcc_assert (REGNO (op1) == REGNO (scratch));
11274 x = gen_rtx_AND (vmode, scratch, mask);
11275 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11278 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11279 x = gen_rtx_NOT (vmode, dest);
11280 x = gen_rtx_AND (vmode, x, op0);
11281 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11285 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11287 x = gen_rtx_AND (vmode, scratch, mask);
11289 else /* alternative 2,4 */
11291 gcc_assert (REGNO (mask) == REGNO (scratch));
11292 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11293 x = gen_rtx_AND (vmode, scratch, op1);
11295 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11297 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11299 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11300 x = gen_rtx_AND (vmode, dest, nmask);
11302 else /* alternative 3,4 */
11304 gcc_assert (REGNO (nmask) == REGNO (dest));
11306 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11307 x = gen_rtx_AND (vmode, dest, op0);
11309 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11312 x = gen_rtx_IOR (vmode, dest, scratch);
11313 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11316 /* Return TRUE or FALSE depending on whether the first SET in INSN
11317 has source and destination with matching CC modes, and that the
11318 CC mode is at least as constrained as REQ_MODE. */
11321 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11324 enum machine_mode set_mode;
11326 set = PATTERN (insn);
11327 if (GET_CODE (set) == PARALLEL)
11328 set = XVECEXP (set, 0, 0);
11329 gcc_assert (GET_CODE (set) == SET);
11330 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11332 set_mode = GET_MODE (SET_DEST (set));
11336 if (req_mode != CCNOmode
11337 && (req_mode != CCmode
11338 || XEXP (SET_SRC (set), 1) != const0_rtx))
11342 if (req_mode == CCGCmode)
11346 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11350 if (req_mode == CCZmode)
11357 gcc_unreachable ();
11360 return (GET_MODE (SET_SRC (set)) == set_mode);
11363 /* Generate insn patterns to do an integer compare of OPERANDS. */
11366 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11368 enum machine_mode cmpmode;
11371 cmpmode = SELECT_CC_MODE (code, op0, op1);
11372 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11374 /* This is very simple, but making the interface the same as in the
11375 FP case makes the rest of the code easier. */
11376 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11377 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11379 /* Return the test that should be put into the flags user, i.e.
11380 the bcc, scc, or cmov instruction. */
11381 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11384 /* Figure out whether to use ordered or unordered fp comparisons.
11385 Return the appropriate mode to use. */
11388 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11390 /* ??? In order to make all comparisons reversible, we do all comparisons
11391 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11392 all forms trapping and nontrapping comparisons, we can make inequality
11393 comparisons trapping again, since it results in better code when using
11394 FCOM based compares. */
11395 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11399 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11401 enum machine_mode mode = GET_MODE (op0);
11403 if (SCALAR_FLOAT_MODE_P (mode))
11405 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11406 return ix86_fp_compare_mode (code);
11411 /* Only zero flag is needed. */
11412 case EQ: /* ZF=0 */
11413 case NE: /* ZF!=0 */
11415 /* Codes needing carry flag. */
11416 case GEU: /* CF=0 */
11417 case LTU: /* CF=1 */
11418 /* Detect overflow checks. They need just the carry flag. */
11419 if (GET_CODE (op0) == PLUS
11420 && rtx_equal_p (op1, XEXP (op0, 0)))
11424 case GTU: /* CF=0 & ZF=0 */
11425 case LEU: /* CF=1 | ZF=1 */
11426 /* Detect overflow checks. They need just the carry flag. */
11427 if (GET_CODE (op0) == MINUS
11428 && rtx_equal_p (op1, XEXP (op0, 0)))
11432 /* Codes possibly doable only with sign flag when
11433 comparing against zero. */
11434 case GE: /* SF=OF or SF=0 */
11435 case LT: /* SF<>OF or SF=1 */
11436 if (op1 == const0_rtx)
11439 /* For other cases Carry flag is not required. */
11441 /* Codes doable only with sign flag when comparing
11442 against zero, but we miss jump instruction for it
11443 so we need to use relational tests against overflow
11444 that thus needs to be zero. */
11445 case GT: /* ZF=0 & SF=OF */
11446 case LE: /* ZF=1 | SF<>OF */
11447 if (op1 == const0_rtx)
11451 /* strcmp pattern do (use flags) and combine may ask us for proper
11456 gcc_unreachable ();
11460 /* Return the fixed registers used for condition codes. */
11463 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11470 /* If two condition code modes are compatible, return a condition code
11471 mode which is compatible with both. Otherwise, return
11474 static enum machine_mode
11475 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11480 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11483 if ((m1 == CCGCmode && m2 == CCGOCmode)
11484 || (m1 == CCGOCmode && m2 == CCGCmode))
11490 gcc_unreachable ();
11520 /* These are only compatible with themselves, which we already
11526 /* Split comparison code CODE into comparisons we can do using branch
11527 instructions. BYPASS_CODE is comparison code for branch that will
11528 branch around FIRST_CODE and SECOND_CODE. If some of branches
11529 is not required, set value to UNKNOWN.
11530 We never require more than two branches. */
11533 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11534 enum rtx_code *first_code,
11535 enum rtx_code *second_code)
11537 *first_code = code;
11538 *bypass_code = UNKNOWN;
11539 *second_code = UNKNOWN;
11541 /* The fcomi comparison sets flags as follows:
11551 case GT: /* GTU - CF=0 & ZF=0 */
11552 case GE: /* GEU - CF=0 */
11553 case ORDERED: /* PF=0 */
11554 case UNORDERED: /* PF=1 */
11555 case UNEQ: /* EQ - ZF=1 */
11556 case UNLT: /* LTU - CF=1 */
11557 case UNLE: /* LEU - CF=1 | ZF=1 */
11558 case LTGT: /* EQ - ZF=0 */
11560 case LT: /* LTU - CF=1 - fails on unordered */
11561 *first_code = UNLT;
11562 *bypass_code = UNORDERED;
11564 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11565 *first_code = UNLE;
11566 *bypass_code = UNORDERED;
11568 case EQ: /* EQ - ZF=1 - fails on unordered */
11569 *first_code = UNEQ;
11570 *bypass_code = UNORDERED;
11572 case NE: /* NE - ZF=0 - fails on unordered */
11573 *first_code = LTGT;
11574 *second_code = UNORDERED;
11576 case UNGE: /* GEU - CF=0 - fails on unordered */
11578 *second_code = UNORDERED;
11580 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11582 *second_code = UNORDERED;
11585 gcc_unreachable ();
11587 if (!TARGET_IEEE_FP)
11589 *second_code = UNKNOWN;
11590 *bypass_code = UNKNOWN;
11594 /* Return cost of comparison done fcom + arithmetics operations on AX.
11595 All following functions do use number of instructions as a cost metrics.
11596 In future this should be tweaked to compute bytes for optimize_size and
11597 take into account performance of various instructions on various CPUs. */
11599 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11601 if (!TARGET_IEEE_FP)
11603 /* The cost of code output by ix86_expand_fp_compare. */
11627 gcc_unreachable ();
11631 /* Return cost of comparison done using fcomi operation.
11632 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11634 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11636 enum rtx_code bypass_code, first_code, second_code;
11637 /* Return arbitrarily high cost when instruction is not supported - this
11638 prevents gcc from using it. */
11641 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11642 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11645 /* Return cost of comparison done using sahf operation.
11646 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11648 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11650 enum rtx_code bypass_code, first_code, second_code;
11651 /* Return arbitrarily high cost when instruction is not preferred - this
11652 avoids gcc from using it. */
11653 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11655 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11656 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11659 /* Compute cost of the comparison done using any method.
11660 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11662 ix86_fp_comparison_cost (enum rtx_code code)
11664 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11667 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11668 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11670 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11671 if (min > sahf_cost)
11673 if (min > fcomi_cost)
11678 /* Return true if we should use an FCOMI instruction for this
11682 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11684 enum rtx_code swapped_code = swap_condition (code);
11686 return ((ix86_fp_comparison_cost (code)
11687 == ix86_fp_comparison_fcomi_cost (code))
11688 || (ix86_fp_comparison_cost (swapped_code)
11689 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11692 /* Swap, force into registers, or otherwise massage the two operands
11693 to a fp comparison. The operands are updated in place; the new
11694 comparison code is returned. */
11696 static enum rtx_code
11697 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11699 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11700 rtx op0 = *pop0, op1 = *pop1;
11701 enum machine_mode op_mode = GET_MODE (op0);
11702 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11704 /* All of the unordered compare instructions only work on registers.
11705 The same is true of the fcomi compare instructions. The XFmode
11706 compare instructions require registers except when comparing
11707 against zero or when converting operand 1 from fixed point to
11711 && (fpcmp_mode == CCFPUmode
11712 || (op_mode == XFmode
11713 && ! (standard_80387_constant_p (op0) == 1
11714 || standard_80387_constant_p (op1) == 1)
11715 && GET_CODE (op1) != FLOAT)
11716 || ix86_use_fcomi_compare (code)))
11718 op0 = force_reg (op_mode, op0);
11719 op1 = force_reg (op_mode, op1);
11723 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11724 things around if they appear profitable, otherwise force op0
11725 into a register. */
11727 if (standard_80387_constant_p (op0) == 0
11729 && ! (standard_80387_constant_p (op1) == 0
11733 tmp = op0, op0 = op1, op1 = tmp;
11734 code = swap_condition (code);
11738 op0 = force_reg (op_mode, op0);
11740 if (CONSTANT_P (op1))
11742 int tmp = standard_80387_constant_p (op1);
11744 op1 = validize_mem (force_const_mem (op_mode, op1));
11748 op1 = force_reg (op_mode, op1);
11751 op1 = force_reg (op_mode, op1);
11755 /* Try to rearrange the comparison to make it cheaper. */
11756 if (ix86_fp_comparison_cost (code)
11757 > ix86_fp_comparison_cost (swap_condition (code))
11758 && (REG_P (op1) || can_create_pseudo_p ()))
11761 tmp = op0, op0 = op1, op1 = tmp;
11762 code = swap_condition (code);
11764 op0 = force_reg (op_mode, op0);
11772 /* Convert comparison codes we use to represent FP comparison to integer
11773 code that will result in proper branch. Return UNKNOWN if no such code
11777 ix86_fp_compare_code_to_integer (enum rtx_code code)
11806 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11809 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11810 rtx *second_test, rtx *bypass_test)
11812 enum machine_mode fpcmp_mode, intcmp_mode;
11814 int cost = ix86_fp_comparison_cost (code);
11815 enum rtx_code bypass_code, first_code, second_code;
11817 fpcmp_mode = ix86_fp_compare_mode (code);
11818 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11821 *second_test = NULL_RTX;
11823 *bypass_test = NULL_RTX;
11825 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11827 /* Do fcomi/sahf based test when profitable. */
11828 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11829 && (bypass_code == UNKNOWN || bypass_test)
11830 && (second_code == UNKNOWN || second_test))
11832 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11833 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11839 gcc_assert (TARGET_SAHF);
11842 scratch = gen_reg_rtx (HImode);
11843 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11845 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11848 /* The FP codes work out to act like unsigned. */
11849 intcmp_mode = fpcmp_mode;
11851 if (bypass_code != UNKNOWN)
11852 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11853 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11855 if (second_code != UNKNOWN)
11856 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11857 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11862 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11863 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11864 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11866 scratch = gen_reg_rtx (HImode);
11867 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11869 /* In the unordered case, we have to check C2 for NaN's, which
11870 doesn't happen to work out to anything nice combination-wise.
11871 So do some bit twiddling on the value we've got in AH to come
11872 up with an appropriate set of condition codes. */
11874 intcmp_mode = CCNOmode;
11879 if (code == GT || !TARGET_IEEE_FP)
11881 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11886 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11887 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11888 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11889 intcmp_mode = CCmode;
11895 if (code == LT && TARGET_IEEE_FP)
11897 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11898 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11899 intcmp_mode = CCmode;
11904 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11910 if (code == GE || !TARGET_IEEE_FP)
11912 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11917 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11918 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11925 if (code == LE && TARGET_IEEE_FP)
11927 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11928 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11929 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11930 intcmp_mode = CCmode;
11935 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11941 if (code == EQ && TARGET_IEEE_FP)
11943 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11944 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11945 intcmp_mode = CCmode;
11950 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11957 if (code == NE && TARGET_IEEE_FP)
11959 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11960 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11966 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11972 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11976 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11981 gcc_unreachable ();
11985 /* Return the test that should be put into the flags user, i.e.
11986 the bcc, scc, or cmov instruction. */
11987 return gen_rtx_fmt_ee (code, VOIDmode,
11988 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11993 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11996 op0 = ix86_compare_op0;
11997 op1 = ix86_compare_op1;
12000 *second_test = NULL_RTX;
12002 *bypass_test = NULL_RTX;
12004 if (ix86_compare_emitted)
12006 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
12007 ix86_compare_emitted = NULL_RTX;
12009 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
12011 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12012 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12013 second_test, bypass_test);
12016 ret = ix86_expand_int_compare (code, op0, op1);
12021 /* Return true if the CODE will result in nontrivial jump sequence. */
12023 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12025 enum rtx_code bypass_code, first_code, second_code;
12028 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12029 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12033 ix86_expand_branch (enum rtx_code code, rtx label)
12037 /* If we have emitted a compare insn, go straight to simple.
12038 ix86_expand_compare won't emit anything if ix86_compare_emitted
12040 if (ix86_compare_emitted)
12043 switch (GET_MODE (ix86_compare_op0))
12049 tmp = ix86_expand_compare (code, NULL, NULL);
12050 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12051 gen_rtx_LABEL_REF (VOIDmode, label),
12053 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12062 enum rtx_code bypass_code, first_code, second_code;
12064 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12065 &ix86_compare_op1);
12067 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12069 /* Check whether we will use the natural sequence with one jump. If
12070 so, we can expand jump early. Otherwise delay expansion by
12071 creating compound insn to not confuse optimizers. */
12072 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12074 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12075 gen_rtx_LABEL_REF (VOIDmode, label),
12076 pc_rtx, NULL_RTX, NULL_RTX);
12080 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12081 ix86_compare_op0, ix86_compare_op1);
12082 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12083 gen_rtx_LABEL_REF (VOIDmode, label),
12085 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12087 use_fcomi = ix86_use_fcomi_compare (code);
12088 vec = rtvec_alloc (3 + !use_fcomi);
12089 RTVEC_ELT (vec, 0) = tmp;
12091 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12093 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12096 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12098 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12107 /* Expand DImode branch into multiple compare+branch. */
12109 rtx lo[2], hi[2], label2;
12110 enum rtx_code code1, code2, code3;
12111 enum machine_mode submode;
12113 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12115 tmp = ix86_compare_op0;
12116 ix86_compare_op0 = ix86_compare_op1;
12117 ix86_compare_op1 = tmp;
12118 code = swap_condition (code);
12120 if (GET_MODE (ix86_compare_op0) == DImode)
12122 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12123 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12128 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12129 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12133 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12134 avoid two branches. This costs one extra insn, so disable when
12135 optimizing for size. */
12137 if ((code == EQ || code == NE)
12139 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12144 if (hi[1] != const0_rtx)
12145 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12146 NULL_RTX, 0, OPTAB_WIDEN);
12149 if (lo[1] != const0_rtx)
12150 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12151 NULL_RTX, 0, OPTAB_WIDEN);
12153 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12154 NULL_RTX, 0, OPTAB_WIDEN);
12156 ix86_compare_op0 = tmp;
12157 ix86_compare_op1 = const0_rtx;
12158 ix86_expand_branch (code, label);
12162 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12163 op1 is a constant and the low word is zero, then we can just
12164 examine the high word. Similarly for low word -1 and
12165 less-or-equal-than or greater-than. */
12167 if (CONST_INT_P (hi[1]))
12170 case LT: case LTU: case GE: case GEU:
12171 if (lo[1] == const0_rtx)
12173 ix86_compare_op0 = hi[0];
12174 ix86_compare_op1 = hi[1];
12175 ix86_expand_branch (code, label);
12179 case LE: case LEU: case GT: case GTU:
12180 if (lo[1] == constm1_rtx)
12182 ix86_compare_op0 = hi[0];
12183 ix86_compare_op1 = hi[1];
12184 ix86_expand_branch (code, label);
12192 /* Otherwise, we need two or three jumps. */
12194 label2 = gen_label_rtx ();
12197 code2 = swap_condition (code);
12198 code3 = unsigned_condition (code);
12202 case LT: case GT: case LTU: case GTU:
12205 case LE: code1 = LT; code2 = GT; break;
12206 case GE: code1 = GT; code2 = LT; break;
12207 case LEU: code1 = LTU; code2 = GTU; break;
12208 case GEU: code1 = GTU; code2 = LTU; break;
12210 case EQ: code1 = UNKNOWN; code2 = NE; break;
12211 case NE: code2 = UNKNOWN; break;
12214 gcc_unreachable ();
12219 * if (hi(a) < hi(b)) goto true;
12220 * if (hi(a) > hi(b)) goto false;
12221 * if (lo(a) < lo(b)) goto true;
12225 ix86_compare_op0 = hi[0];
12226 ix86_compare_op1 = hi[1];
12228 if (code1 != UNKNOWN)
12229 ix86_expand_branch (code1, label);
12230 if (code2 != UNKNOWN)
12231 ix86_expand_branch (code2, label2);
12233 ix86_compare_op0 = lo[0];
12234 ix86_compare_op1 = lo[1];
12235 ix86_expand_branch (code3, label);
12237 if (code2 != UNKNOWN)
12238 emit_label (label2);
12243 gcc_unreachable ();
12247 /* Split branch based on floating point condition. */
12249 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12250 rtx target1, rtx target2, rtx tmp, rtx pushed)
12252 rtx second, bypass;
12253 rtx label = NULL_RTX;
12255 int bypass_probability = -1, second_probability = -1, probability = -1;
12258 if (target2 != pc_rtx)
12261 code = reverse_condition_maybe_unordered (code);
12266 condition = ix86_expand_fp_compare (code, op1, op2,
12267 tmp, &second, &bypass);
12269 /* Remove pushed operand from stack. */
12271 ix86_free_from_memory (GET_MODE (pushed));
12273 if (split_branch_probability >= 0)
12275 /* Distribute the probabilities across the jumps.
12276 Assume the BYPASS and SECOND to be always test
12278 probability = split_branch_probability;
12280 /* Value of 1 is low enough to make no need for probability
12281 to be updated. Later we may run some experiments and see
12282 if unordered values are more frequent in practice. */
12284 bypass_probability = 1;
12286 second_probability = 1;
12288 if (bypass != NULL_RTX)
12290 label = gen_label_rtx ();
12291 i = emit_jump_insn (gen_rtx_SET
12293 gen_rtx_IF_THEN_ELSE (VOIDmode,
12295 gen_rtx_LABEL_REF (VOIDmode,
12298 if (bypass_probability >= 0)
12300 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12301 GEN_INT (bypass_probability),
12304 i = emit_jump_insn (gen_rtx_SET
12306 gen_rtx_IF_THEN_ELSE (VOIDmode,
12307 condition, target1, target2)));
12308 if (probability >= 0)
12310 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12311 GEN_INT (probability),
12313 if (second != NULL_RTX)
12315 i = emit_jump_insn (gen_rtx_SET
12317 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12319 if (second_probability >= 0)
12321 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12322 GEN_INT (second_probability),
12325 if (label != NULL_RTX)
12326 emit_label (label);
12330 ix86_expand_setcc (enum rtx_code code, rtx dest)
12332 rtx ret, tmp, tmpreg, equiv;
12333 rtx second_test, bypass_test;
12335 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12336 return 0; /* FAIL */
12338 gcc_assert (GET_MODE (dest) == QImode);
12340 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12341 PUT_MODE (ret, QImode);
12346 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12347 if (bypass_test || second_test)
12349 rtx test = second_test;
12351 rtx tmp2 = gen_reg_rtx (QImode);
12354 gcc_assert (!second_test);
12355 test = bypass_test;
12357 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12359 PUT_MODE (test, QImode);
12360 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12363 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12365 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12368 /* Attach a REG_EQUAL note describing the comparison result. */
12369 if (ix86_compare_op0 && ix86_compare_op1)
12371 equiv = simplify_gen_relational (code, QImode,
12372 GET_MODE (ix86_compare_op0),
12373 ix86_compare_op0, ix86_compare_op1);
12374 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12377 return 1; /* DONE */
12380 /* Expand comparison setting or clearing carry flag. Return true when
12381 successful and set pop for the operation. */
12383 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12385 enum machine_mode mode =
12386 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12388 /* Do not handle DImode compares that go through special path. */
12389 if (mode == (TARGET_64BIT ? TImode : DImode))
12392 if (SCALAR_FLOAT_MODE_P (mode))
12394 rtx second_test = NULL, bypass_test = NULL;
12395 rtx compare_op, compare_seq;
12397 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12399 /* Shortcut: following common codes never translate
12400 into carry flag compares. */
12401 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12402 || code == ORDERED || code == UNORDERED)
12405 /* These comparisons require zero flag; swap operands so they won't. */
12406 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12407 && !TARGET_IEEE_FP)
12412 code = swap_condition (code);
12415 /* Try to expand the comparison and verify that we end up with
12416 carry flag based comparison. This fails to be true only when
12417 we decide to expand comparison using arithmetic that is not
12418 too common scenario. */
12420 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12421 &second_test, &bypass_test);
12422 compare_seq = get_insns ();
12425 if (second_test || bypass_test)
12428 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12429 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12430 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12432 code = GET_CODE (compare_op);
12434 if (code != LTU && code != GEU)
12437 emit_insn (compare_seq);
12442 if (!INTEGRAL_MODE_P (mode))
12451 /* Convert a==0 into (unsigned)a<1. */
12454 if (op1 != const0_rtx)
12457 code = (code == EQ ? LTU : GEU);
12460 /* Convert a>b into b<a or a>=b-1. */
12463 if (CONST_INT_P (op1))
12465 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12466 /* Bail out on overflow. We still can swap operands but that
12467 would force loading of the constant into register. */
12468 if (op1 == const0_rtx
12469 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12471 code = (code == GTU ? GEU : LTU);
12478 code = (code == GTU ? LTU : GEU);
12482 /* Convert a>=0 into (unsigned)a<0x80000000. */
12485 if (mode == DImode || op1 != const0_rtx)
12487 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12488 code = (code == LT ? GEU : LTU);
12492 if (mode == DImode || op1 != constm1_rtx)
12494 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12495 code = (code == LE ? GEU : LTU);
12501 /* Swapping operands may cause constant to appear as first operand. */
12502 if (!nonimmediate_operand (op0, VOIDmode))
12504 if (!can_create_pseudo_p ())
12506 op0 = force_reg (mode, op0);
12508 ix86_compare_op0 = op0;
12509 ix86_compare_op1 = op1;
12510 *pop = ix86_expand_compare (code, NULL, NULL);
12511 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12516 ix86_expand_int_movcc (rtx operands[])
12518 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12519 rtx compare_seq, compare_op;
12520 rtx second_test, bypass_test;
12521 enum machine_mode mode = GET_MODE (operands[0]);
12522 bool sign_bit_compare_p = false;;
12525 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12526 compare_seq = get_insns ();
12529 compare_code = GET_CODE (compare_op);
12531 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12532 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12533 sign_bit_compare_p = true;
12535 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12536 HImode insns, we'd be swallowed in word prefix ops. */
12538 if ((mode != HImode || TARGET_FAST_PREFIX)
12539 && (mode != (TARGET_64BIT ? TImode : DImode))
12540 && CONST_INT_P (operands[2])
12541 && CONST_INT_P (operands[3]))
12543 rtx out = operands[0];
12544 HOST_WIDE_INT ct = INTVAL (operands[2]);
12545 HOST_WIDE_INT cf = INTVAL (operands[3]);
12546 HOST_WIDE_INT diff;
12549 /* Sign bit compares are better done using shifts than we do by using
12551 if (sign_bit_compare_p
12552 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12553 ix86_compare_op1, &compare_op))
12555 /* Detect overlap between destination and compare sources. */
12558 if (!sign_bit_compare_p)
12560 bool fpcmp = false;
12562 compare_code = GET_CODE (compare_op);
12564 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12565 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12568 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12571 /* To simplify rest of code, restrict to the GEU case. */
12572 if (compare_code == LTU)
12574 HOST_WIDE_INT tmp = ct;
12577 compare_code = reverse_condition (compare_code);
12578 code = reverse_condition (code);
12583 PUT_CODE (compare_op,
12584 reverse_condition_maybe_unordered
12585 (GET_CODE (compare_op)));
12587 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12591 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12592 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12593 tmp = gen_reg_rtx (mode);
12595 if (mode == DImode)
12596 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12598 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12602 if (code == GT || code == GE)
12603 code = reverse_condition (code);
12606 HOST_WIDE_INT tmp = ct;
12611 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12612 ix86_compare_op1, VOIDmode, 0, -1);
12625 tmp = expand_simple_binop (mode, PLUS,
12627 copy_rtx (tmp), 1, OPTAB_DIRECT);
12638 tmp = expand_simple_binop (mode, IOR,
12640 copy_rtx (tmp), 1, OPTAB_DIRECT);
12642 else if (diff == -1 && ct)
12652 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12654 tmp = expand_simple_binop (mode, PLUS,
12655 copy_rtx (tmp), GEN_INT (cf),
12656 copy_rtx (tmp), 1, OPTAB_DIRECT);
12664 * andl cf - ct, dest
12674 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12677 tmp = expand_simple_binop (mode, AND,
12679 gen_int_mode (cf - ct, mode),
12680 copy_rtx (tmp), 1, OPTAB_DIRECT);
12682 tmp = expand_simple_binop (mode, PLUS,
12683 copy_rtx (tmp), GEN_INT (ct),
12684 copy_rtx (tmp), 1, OPTAB_DIRECT);
12687 if (!rtx_equal_p (tmp, out))
12688 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12690 return 1; /* DONE */
12695 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12698 tmp = ct, ct = cf, cf = tmp;
12701 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12703 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12705 /* We may be reversing unordered compare to normal compare, that
12706 is not valid in general (we may convert non-trapping condition
12707 to trapping one), however on i386 we currently emit all
12708 comparisons unordered. */
12709 compare_code = reverse_condition_maybe_unordered (compare_code);
12710 code = reverse_condition_maybe_unordered (code);
12714 compare_code = reverse_condition (compare_code);
12715 code = reverse_condition (code);
12719 compare_code = UNKNOWN;
12720 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12721 && CONST_INT_P (ix86_compare_op1))
12723 if (ix86_compare_op1 == const0_rtx
12724 && (code == LT || code == GE))
12725 compare_code = code;
12726 else if (ix86_compare_op1 == constm1_rtx)
12730 else if (code == GT)
12735 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12736 if (compare_code != UNKNOWN
12737 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12738 && (cf == -1 || ct == -1))
12740 /* If lea code below could be used, only optimize
12741 if it results in a 2 insn sequence. */
12743 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12744 || diff == 3 || diff == 5 || diff == 9)
12745 || (compare_code == LT && ct == -1)
12746 || (compare_code == GE && cf == -1))
12749 * notl op1 (if necessary)
12757 code = reverse_condition (code);
12760 out = emit_store_flag (out, code, ix86_compare_op0,
12761 ix86_compare_op1, VOIDmode, 0, -1);
12763 out = expand_simple_binop (mode, IOR,
12765 out, 1, OPTAB_DIRECT);
12766 if (out != operands[0])
12767 emit_move_insn (operands[0], out);
12769 return 1; /* DONE */
12774 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12775 || diff == 3 || diff == 5 || diff == 9)
12776 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12778 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12784 * lea cf(dest*(ct-cf)),dest
12788 * This also catches the degenerate setcc-only case.
12794 out = emit_store_flag (out, code, ix86_compare_op0,
12795 ix86_compare_op1, VOIDmode, 0, 1);
12798 /* On x86_64 the lea instruction operates on Pmode, so we need
12799 to get arithmetics done in proper mode to match. */
12801 tmp = copy_rtx (out);
12805 out1 = copy_rtx (out);
12806 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12810 tmp = gen_rtx_PLUS (mode, tmp, out1);
12816 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12819 if (!rtx_equal_p (tmp, out))
12822 out = force_operand (tmp, copy_rtx (out));
12824 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12826 if (!rtx_equal_p (out, operands[0]))
12827 emit_move_insn (operands[0], copy_rtx (out));
12829 return 1; /* DONE */
12833 * General case: Jumpful:
12834 * xorl dest,dest cmpl op1, op2
12835 * cmpl op1, op2 movl ct, dest
12836 * setcc dest jcc 1f
12837 * decl dest movl cf, dest
12838 * andl (cf-ct),dest 1:
12841 * Size 20. Size 14.
12843 * This is reasonably steep, but branch mispredict costs are
12844 * high on modern cpus, so consider failing only if optimizing
12848 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12849 && BRANCH_COST >= 2)
12853 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12858 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12860 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12862 /* We may be reversing unordered compare to normal compare,
12863 that is not valid in general (we may convert non-trapping
12864 condition to trapping one), however on i386 we currently
12865 emit all comparisons unordered. */
12866 code = reverse_condition_maybe_unordered (code);
12870 code = reverse_condition (code);
12871 if (compare_code != UNKNOWN)
12872 compare_code = reverse_condition (compare_code);
12876 if (compare_code != UNKNOWN)
12878 /* notl op1 (if needed)
12883 For x < 0 (resp. x <= -1) there will be no notl,
12884 so if possible swap the constants to get rid of the
12886 True/false will be -1/0 while code below (store flag
12887 followed by decrement) is 0/-1, so the constants need
12888 to be exchanged once more. */
12890 if (compare_code == GE || !cf)
12892 code = reverse_condition (code);
12897 HOST_WIDE_INT tmp = cf;
12902 out = emit_store_flag (out, code, ix86_compare_op0,
12903 ix86_compare_op1, VOIDmode, 0, -1);
12907 out = emit_store_flag (out, code, ix86_compare_op0,
12908 ix86_compare_op1, VOIDmode, 0, 1);
12910 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12911 copy_rtx (out), 1, OPTAB_DIRECT);
12914 out = expand_simple_binop (mode, AND, copy_rtx (out),
12915 gen_int_mode (cf - ct, mode),
12916 copy_rtx (out), 1, OPTAB_DIRECT);
12918 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12919 copy_rtx (out), 1, OPTAB_DIRECT);
12920 if (!rtx_equal_p (out, operands[0]))
12921 emit_move_insn (operands[0], copy_rtx (out));
12923 return 1; /* DONE */
12927 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12929 /* Try a few things more with specific constants and a variable. */
12932 rtx var, orig_out, out, tmp;
12934 if (BRANCH_COST <= 2)
12935 return 0; /* FAIL */
12937 /* If one of the two operands is an interesting constant, load a
12938 constant with the above and mask it in with a logical operation. */
12940 if (CONST_INT_P (operands[2]))
12943 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12944 operands[3] = constm1_rtx, op = and_optab;
12945 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12946 operands[3] = const0_rtx, op = ior_optab;
12948 return 0; /* FAIL */
12950 else if (CONST_INT_P (operands[3]))
12953 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12954 operands[2] = constm1_rtx, op = and_optab;
12955 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12956 operands[2] = const0_rtx, op = ior_optab;
12958 return 0; /* FAIL */
12961 return 0; /* FAIL */
12963 orig_out = operands[0];
12964 tmp = gen_reg_rtx (mode);
12967 /* Recurse to get the constant loaded. */
12968 if (ix86_expand_int_movcc (operands) == 0)
12969 return 0; /* FAIL */
12971 /* Mask in the interesting variable. */
12972 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12974 if (!rtx_equal_p (out, orig_out))
12975 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12977 return 1; /* DONE */
12981 * For comparison with above,
12991 if (! nonimmediate_operand (operands[2], mode))
12992 operands[2] = force_reg (mode, operands[2]);
12993 if (! nonimmediate_operand (operands[3], mode))
12994 operands[3] = force_reg (mode, operands[3]);
12996 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12998 rtx tmp = gen_reg_rtx (mode);
12999 emit_move_insn (tmp, operands[3]);
13002 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13004 rtx tmp = gen_reg_rtx (mode);
13005 emit_move_insn (tmp, operands[2]);
13009 if (! register_operand (operands[2], VOIDmode)
13011 || ! register_operand (operands[3], VOIDmode)))
13012 operands[2] = force_reg (mode, operands[2]);
13015 && ! register_operand (operands[3], VOIDmode))
13016 operands[3] = force_reg (mode, operands[3]);
13018 emit_insn (compare_seq);
13019 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13020 gen_rtx_IF_THEN_ELSE (mode,
13021 compare_op, operands[2],
13024 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13025 gen_rtx_IF_THEN_ELSE (mode,
13027 copy_rtx (operands[3]),
13028 copy_rtx (operands[0]))));
13030 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13031 gen_rtx_IF_THEN_ELSE (mode,
13033 copy_rtx (operands[2]),
13034 copy_rtx (operands[0]))));
13036 return 1; /* DONE */
13039 /* Swap, force into registers, or otherwise massage the two operands
13040 to an sse comparison with a mask result. Thus we differ a bit from
13041 ix86_prepare_fp_compare_args which expects to produce a flags result.
13043 The DEST operand exists to help determine whether to commute commutative
13044 operators. The POP0/POP1 operands are updated in place. The new
13045 comparison code is returned, or UNKNOWN if not implementable. */
13047 static enum rtx_code
13048 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13049 rtx *pop0, rtx *pop1)
13057 /* We have no LTGT as an operator. We could implement it with
13058 NE & ORDERED, but this requires an extra temporary. It's
13059 not clear that it's worth it. */
13066 /* These are supported directly. */
13073 /* For commutative operators, try to canonicalize the destination
13074 operand to be first in the comparison - this helps reload to
13075 avoid extra moves. */
13076 if (!dest || !rtx_equal_p (dest, *pop1))
13084 /* These are not supported directly. Swap the comparison operands
13085 to transform into something that is supported. */
13089 code = swap_condition (code);
13093 gcc_unreachable ();
13099 /* Detect conditional moves that exactly match min/max operational
13100 semantics. Note that this is IEEE safe, as long as we don't
13101 interchange the operands.
13103 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13104 and TRUE if the operation is successful and instructions are emitted. */
13107 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13108 rtx cmp_op1, rtx if_true, rtx if_false)
13110 enum machine_mode mode;
13116 else if (code == UNGE)
13119 if_true = if_false;
13125 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13127 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13132 mode = GET_MODE (dest);
13134 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13135 but MODE may be a vector mode and thus not appropriate. */
13136 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13138 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13141 if_true = force_reg (mode, if_true);
13142 v = gen_rtvec (2, if_true, if_false);
13143 tmp = gen_rtx_UNSPEC (mode, v, u);
13147 code = is_min ? SMIN : SMAX;
13148 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13151 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13155 /* Expand an sse vector comparison. Return the register with the result. */
13158 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13159 rtx op_true, rtx op_false)
13161 enum machine_mode mode = GET_MODE (dest);
13164 cmp_op0 = force_reg (mode, cmp_op0);
13165 if (!nonimmediate_operand (cmp_op1, mode))
13166 cmp_op1 = force_reg (mode, cmp_op1);
13169 || reg_overlap_mentioned_p (dest, op_true)
13170 || reg_overlap_mentioned_p (dest, op_false))
13171 dest = gen_reg_rtx (mode);
13173 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13174 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13179 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13180 operations. This is used for both scalar and vector conditional moves. */
13183 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13185 enum machine_mode mode = GET_MODE (dest);
13190 rtx pcmov = gen_rtx_SET (mode, dest,
13191 gen_rtx_IF_THEN_ELSE (mode, cmp,
13196 else if (op_false == CONST0_RTX (mode))
13198 op_true = force_reg (mode, op_true);
13199 x = gen_rtx_AND (mode, cmp, op_true);
13200 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13202 else if (op_true == CONST0_RTX (mode))
13204 op_false = force_reg (mode, op_false);
13205 x = gen_rtx_NOT (mode, cmp);
13206 x = gen_rtx_AND (mode, x, op_false);
13207 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13211 op_true = force_reg (mode, op_true);
13212 op_false = force_reg (mode, op_false);
13214 t2 = gen_reg_rtx (mode);
13216 t3 = gen_reg_rtx (mode);
13220 x = gen_rtx_AND (mode, op_true, cmp);
13221 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13223 x = gen_rtx_NOT (mode, cmp);
13224 x = gen_rtx_AND (mode, x, op_false);
13225 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13227 x = gen_rtx_IOR (mode, t3, t2);
13228 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13232 /* Expand a floating-point conditional move. Return true if successful. */
13235 ix86_expand_fp_movcc (rtx operands[])
13237 enum machine_mode mode = GET_MODE (operands[0]);
13238 enum rtx_code code = GET_CODE (operands[1]);
13239 rtx tmp, compare_op, second_test, bypass_test;
13241 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13243 enum machine_mode cmode;
13245 /* Since we've no cmove for sse registers, don't force bad register
13246 allocation just to gain access to it. Deny movcc when the
13247 comparison mode doesn't match the move mode. */
13248 cmode = GET_MODE (ix86_compare_op0);
13249 if (cmode == VOIDmode)
13250 cmode = GET_MODE (ix86_compare_op1);
13254 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13256 &ix86_compare_op1);
13257 if (code == UNKNOWN)
13260 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13261 ix86_compare_op1, operands[2],
13265 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13266 ix86_compare_op1, operands[2], operands[3]);
13267 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13271 /* The floating point conditional move instructions don't directly
13272 support conditions resulting from a signed integer comparison. */
13274 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13276 /* The floating point conditional move instructions don't directly
13277 support signed integer comparisons. */
13279 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13281 gcc_assert (!second_test && !bypass_test);
13282 tmp = gen_reg_rtx (QImode);
13283 ix86_expand_setcc (code, tmp);
13285 ix86_compare_op0 = tmp;
13286 ix86_compare_op1 = const0_rtx;
13287 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13289 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13291 tmp = gen_reg_rtx (mode);
13292 emit_move_insn (tmp, operands[3]);
13295 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13297 tmp = gen_reg_rtx (mode);
13298 emit_move_insn (tmp, operands[2]);
13302 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13303 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13304 operands[2], operands[3])));
13306 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13307 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13308 operands[3], operands[0])));
13310 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13311 gen_rtx_IF_THEN_ELSE (mode, second_test,
13312 operands[2], operands[0])));
13317 /* Expand a floating-point vector conditional move; a vcond operation
13318 rather than a movcc operation. */
13321 ix86_expand_fp_vcond (rtx operands[])
13323 enum rtx_code code = GET_CODE (operands[3]);
13326 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13327 &operands[4], &operands[5]);
13328 if (code == UNKNOWN)
13331 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13332 operands[5], operands[1], operands[2]))
13335 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13336 operands[1], operands[2]);
13337 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13341 /* Expand a signed/unsigned integral vector conditional move. */
13344 ix86_expand_int_vcond (rtx operands[])
13346 enum machine_mode mode = GET_MODE (operands[0]);
13347 enum rtx_code code = GET_CODE (operands[3]);
13348 bool negate = false;
13351 cop0 = operands[4];
13352 cop1 = operands[5];
13354 /* Canonicalize the comparison to EQ, GT, GTU. */
13365 code = reverse_condition (code);
13371 code = reverse_condition (code);
13377 code = swap_condition (code);
13378 x = cop0, cop0 = cop1, cop1 = x;
13382 gcc_unreachable ();
13385 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13386 if (mode == V2DImode)
13391 /* SSE4.1 supports EQ. */
13392 if (!TARGET_SSE4_1)
13398 /* SSE4.2 supports GT/GTU. */
13399 if (!TARGET_SSE4_2)
13404 gcc_unreachable ();
13408 /* Unsigned parallel compare is not supported by the hardware. Play some
13409 tricks to turn this into a signed comparison against 0. */
13412 cop0 = force_reg (mode, cop0);
13421 /* Perform a parallel modulo subtraction. */
13422 t1 = gen_reg_rtx (mode);
13423 emit_insn ((mode == V4SImode
13425 : gen_subv2di3) (t1, cop0, cop1));
13427 /* Extract the original sign bit of op0. */
13428 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13430 t2 = gen_reg_rtx (mode);
13431 emit_insn ((mode == V4SImode
13433 : gen_andv2di3) (t2, cop0, mask));
13435 /* XOR it back into the result of the subtraction. This results
13436 in the sign bit set iff we saw unsigned underflow. */
13437 x = gen_reg_rtx (mode);
13438 emit_insn ((mode == V4SImode
13440 : gen_xorv2di3) (x, t1, t2));
13448 /* Perform a parallel unsigned saturating subtraction. */
13449 x = gen_reg_rtx (mode);
13450 emit_insn (gen_rtx_SET (VOIDmode, x,
13451 gen_rtx_US_MINUS (mode, cop0, cop1)));
13458 gcc_unreachable ();
13462 cop1 = CONST0_RTX (mode);
13465 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13466 operands[1+negate], operands[2-negate]);
13468 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13469 operands[2-negate]);
13473 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13474 true if we should do zero extension, else sign extension. HIGH_P is
13475 true if we want the N/2 high elements, else the low elements. */
13478 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13480 enum machine_mode imode = GET_MODE (operands[1]);
13481 rtx (*unpack)(rtx, rtx, rtx);
13488 unpack = gen_vec_interleave_highv16qi;
13490 unpack = gen_vec_interleave_lowv16qi;
13494 unpack = gen_vec_interleave_highv8hi;
13496 unpack = gen_vec_interleave_lowv8hi;
13500 unpack = gen_vec_interleave_highv4si;
13502 unpack = gen_vec_interleave_lowv4si;
13505 gcc_unreachable ();
13508 dest = gen_lowpart (imode, operands[0]);
13511 se = force_reg (imode, CONST0_RTX (imode));
13513 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13514 operands[1], pc_rtx, pc_rtx);
13516 emit_insn (unpack (dest, operands[1], se));
13519 /* This function performs the same task as ix86_expand_sse_unpack,
13520 but with SSE4.1 instructions. */
13523 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13525 enum machine_mode imode = GET_MODE (operands[1]);
13526 rtx (*unpack)(rtx, rtx);
13533 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13535 unpack = gen_sse4_1_extendv8qiv8hi2;
13539 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13541 unpack = gen_sse4_1_extendv4hiv4si2;
13545 unpack = gen_sse4_1_zero_extendv2siv2di2;
13547 unpack = gen_sse4_1_extendv2siv2di2;
13550 gcc_unreachable ();
13553 dest = operands[0];
13556 /* Shift higher 8 bytes to lower 8 bytes. */
13557 src = gen_reg_rtx (imode);
13558 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13559 gen_lowpart (TImode, operands[1]),
13565 emit_insn (unpack (dest, src));
13568 /* This function performs the same task as ix86_expand_sse_unpack,
13569 but with amdfam15 instructions. */
13571 #define PPERM_SRC 0x00 /* copy source */
13572 #define PPERM_INVERT 0x20 /* invert source */
13573 #define PPERM_REVERSE 0x40 /* bit reverse source */
13574 #define PPERM_REV_INV 0x60 /* bit reverse & invert src */
13575 #define PPERM_ZERO 0x80 /* all 0's */
13576 #define PPERM_ONES 0xa0 /* all 1's */
13577 #define PPERM_SIGN 0xc0 /* propagate sign bit */
13578 #define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
13580 #define PPERM_SRC1 0x00 /* use first source byte */
13581 #define PPERM_SRC2 0x10 /* use second source byte */
13584 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13586 enum machine_mode imode = GET_MODE (operands[1]);
13587 int pperm_bytes[16];
13589 int h = (high_p) ? 8 : 0;
13592 rtvec v = rtvec_alloc (16);
13595 rtx op0 = operands[0], op1 = operands[1];
13600 vs = rtvec_alloc (8);
13601 h2 = (high_p) ? 8 : 0;
13602 for (i = 0; i < 8; i++)
13604 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13605 pperm_bytes[2*i+1] = ((unsigned_p)
13607 : PPERM_SIGN | PPERM_SRC2 | i | h);
13610 for (i = 0; i < 16; i++)
13611 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13613 for (i = 0; i < 8; i++)
13614 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13616 p = gen_rtx_PARALLEL (VOIDmode, vs);
13617 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13619 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13621 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13625 vs = rtvec_alloc (4);
13626 h2 = (high_p) ? 4 : 0;
13627 for (i = 0; i < 4; i++)
13629 sign_extend = ((unsigned_p)
13631 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13632 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13633 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13634 pperm_bytes[4*i+2] = sign_extend;
13635 pperm_bytes[4*i+3] = sign_extend;
13638 for (i = 0; i < 16; i++)
13639 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13641 for (i = 0; i < 4; i++)
13642 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13644 p = gen_rtx_PARALLEL (VOIDmode, vs);
13645 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13647 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13649 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13653 vs = rtvec_alloc (2);
13654 h2 = (high_p) ? 2 : 0;
13655 for (i = 0; i < 2; i++)
13657 sign_extend = ((unsigned_p)
13659 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13660 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13661 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13662 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13663 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13664 pperm_bytes[8*i+4] = sign_extend;
13665 pperm_bytes[8*i+5] = sign_extend;
13666 pperm_bytes[8*i+6] = sign_extend;
13667 pperm_bytes[8*i+7] = sign_extend;
13670 for (i = 0; i < 16; i++)
13671 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13673 for (i = 0; i < 2; i++)
13674 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13676 p = gen_rtx_PARALLEL (VOIDmode, vs);
13677 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13679 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13681 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13685 gcc_unreachable ();
13691 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13692 next narrower integer vector type */
13694 ix86_expand_sse5_pack (rtx operands[3])
13696 enum machine_mode imode = GET_MODE (operands[0]);
13697 int pperm_bytes[16];
13699 rtvec v = rtvec_alloc (16);
13701 rtx op0 = operands[0];
13702 rtx op1 = operands[1];
13703 rtx op2 = operands[2];
13708 for (i = 0; i < 8; i++)
13710 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13711 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13714 for (i = 0; i < 16; i++)
13715 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13717 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13718 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13722 for (i = 0; i < 4; i++)
13724 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13725 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13726 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13727 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13730 for (i = 0; i < 16; i++)
13731 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13733 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13734 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13738 for (i = 0; i < 2; i++)
13740 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13741 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13742 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13743 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13744 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13745 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13746 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13747 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13750 for (i = 0; i < 16; i++)
13751 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13753 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13754 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13758 gcc_unreachable ();
13764 /* Expand conditional increment or decrement using adb/sbb instructions.
13765 The default case using setcc followed by the conditional move can be
13766 done by generic code. */
13768 ix86_expand_int_addcc (rtx operands[])
13770 enum rtx_code code = GET_CODE (operands[1]);
13772 rtx val = const0_rtx;
13773 bool fpcmp = false;
13774 enum machine_mode mode = GET_MODE (operands[0]);
13776 if (operands[3] != const1_rtx
13777 && operands[3] != constm1_rtx)
13779 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13780 ix86_compare_op1, &compare_op))
13782 code = GET_CODE (compare_op);
13784 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13785 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13788 code = ix86_fp_compare_code_to_integer (code);
13795 PUT_CODE (compare_op,
13796 reverse_condition_maybe_unordered
13797 (GET_CODE (compare_op)));
13799 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13801 PUT_MODE (compare_op, mode);
13803 /* Construct either adc or sbb insn. */
13804 if ((code == LTU) == (operands[3] == constm1_rtx))
13806 switch (GET_MODE (operands[0]))
13809 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13812 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13815 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13818 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13821 gcc_unreachable ();
13826 switch (GET_MODE (operands[0]))
13829 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13832 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13835 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13838 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13841 gcc_unreachable ();
13844 return 1; /* DONE */
13848 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13849 works for floating pointer parameters and nonoffsetable memories.
13850 For pushes, it returns just stack offsets; the values will be saved
13851 in the right order. Maximally three parts are generated. */
13854 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13859 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13861 size = (GET_MODE_SIZE (mode) + 4) / 8;
13863 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13864 gcc_assert (size >= 2 && size <= 3);
13866 /* Optimize constant pool reference to immediates. This is used by fp
13867 moves, that force all constants to memory to allow combining. */
13868 if (MEM_P (operand) && MEM_READONLY_P (operand))
13870 rtx tmp = maybe_get_pool_constant (operand);
13875 if (MEM_P (operand) && !offsettable_memref_p (operand))
13877 /* The only non-offsetable memories we handle are pushes. */
13878 int ok = push_operand (operand, VOIDmode);
13882 operand = copy_rtx (operand);
13883 PUT_MODE (operand, Pmode);
13884 parts[0] = parts[1] = parts[2] = operand;
13888 if (GET_CODE (operand) == CONST_VECTOR)
13890 enum machine_mode imode = int_mode_for_mode (mode);
13891 /* Caution: if we looked through a constant pool memory above,
13892 the operand may actually have a different mode now. That's
13893 ok, since we want to pun this all the way back to an integer. */
13894 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13895 gcc_assert (operand != NULL);
13901 if (mode == DImode)
13902 split_di (&operand, 1, &parts[0], &parts[1]);
13905 if (REG_P (operand))
13907 gcc_assert (reload_completed);
13908 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13909 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13911 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13913 else if (offsettable_memref_p (operand))
13915 operand = adjust_address (operand, SImode, 0);
13916 parts[0] = operand;
13917 parts[1] = adjust_address (operand, SImode, 4);
13919 parts[2] = adjust_address (operand, SImode, 8);
13921 else if (GET_CODE (operand) == CONST_DOUBLE)
13926 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13930 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13931 parts[2] = gen_int_mode (l[2], SImode);
13934 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13937 gcc_unreachable ();
13939 parts[1] = gen_int_mode (l[1], SImode);
13940 parts[0] = gen_int_mode (l[0], SImode);
13943 gcc_unreachable ();
13948 if (mode == TImode)
13949 split_ti (&operand, 1, &parts[0], &parts[1]);
13950 if (mode == XFmode || mode == TFmode)
13952 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13953 if (REG_P (operand))
13955 gcc_assert (reload_completed);
13956 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13957 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13959 else if (offsettable_memref_p (operand))
13961 operand = adjust_address (operand, DImode, 0);
13962 parts[0] = operand;
13963 parts[1] = adjust_address (operand, upper_mode, 8);
13965 else if (GET_CODE (operand) == CONST_DOUBLE)
13970 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13971 real_to_target (l, &r, mode);
13973 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13974 if (HOST_BITS_PER_WIDE_INT >= 64)
13977 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13978 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13981 parts[0] = immed_double_const (l[0], l[1], DImode);
13983 if (upper_mode == SImode)
13984 parts[1] = gen_int_mode (l[2], SImode);
13985 else if (HOST_BITS_PER_WIDE_INT >= 64)
13988 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13989 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13992 parts[1] = immed_double_const (l[2], l[3], DImode);
13995 gcc_unreachable ();
14002 /* Emit insns to perform a move or push of DI, DF, and XF values.
14003 Return false when normal moves are needed; true when all required
14004 insns have been emitted. Operands 2-4 contain the input values
14005 int the correct order; operands 5-7 contain the output values. */
14008 ix86_split_long_move (rtx operands[])
14013 int collisions = 0;
14014 enum machine_mode mode = GET_MODE (operands[0]);
14016 /* The DFmode expanders may ask us to move double.
14017 For 64bit target this is single move. By hiding the fact
14018 here we simplify i386.md splitters. */
14019 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14021 /* Optimize constant pool reference to immediates. This is used by
14022 fp moves, that force all constants to memory to allow combining. */
14024 if (MEM_P (operands[1])
14025 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14026 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14027 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14028 if (push_operand (operands[0], VOIDmode))
14030 operands[0] = copy_rtx (operands[0]);
14031 PUT_MODE (operands[0], Pmode);
14034 operands[0] = gen_lowpart (DImode, operands[0]);
14035 operands[1] = gen_lowpart (DImode, operands[1]);
14036 emit_move_insn (operands[0], operands[1]);
14040 /* The only non-offsettable memory we handle is push. */
14041 if (push_operand (operands[0], VOIDmode))
14044 gcc_assert (!MEM_P (operands[0])
14045 || offsettable_memref_p (operands[0]));
14047 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14048 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14050 /* When emitting push, take care for source operands on the stack. */
14051 if (push && MEM_P (operands[1])
14052 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14055 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14056 XEXP (part[1][2], 0));
14057 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14058 XEXP (part[1][1], 0));
14061 /* We need to do copy in the right order in case an address register
14062 of the source overlaps the destination. */
14063 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14065 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14067 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14070 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14073 /* Collision in the middle part can be handled by reordering. */
14074 if (collisions == 1 && nparts == 3
14075 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14078 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14079 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14082 /* If there are more collisions, we can't handle it by reordering.
14083 Do an lea to the last part and use only one colliding move. */
14084 else if (collisions > 1)
14090 base = part[0][nparts - 1];
14092 /* Handle the case when the last part isn't valid for lea.
14093 Happens in 64-bit mode storing the 12-byte XFmode. */
14094 if (GET_MODE (base) != Pmode)
14095 base = gen_rtx_REG (Pmode, REGNO (base));
14097 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14098 part[1][0] = replace_equiv_address (part[1][0], base);
14099 part[1][1] = replace_equiv_address (part[1][1],
14100 plus_constant (base, UNITS_PER_WORD));
14102 part[1][2] = replace_equiv_address (part[1][2],
14103 plus_constant (base, 8));
14113 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14114 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14115 emit_move_insn (part[0][2], part[1][2]);
14120 /* In 64bit mode we don't have 32bit push available. In case this is
14121 register, it is OK - we will just use larger counterpart. We also
14122 retype memory - these comes from attempt to avoid REX prefix on
14123 moving of second half of TFmode value. */
14124 if (GET_MODE (part[1][1]) == SImode)
14126 switch (GET_CODE (part[1][1]))
14129 part[1][1] = adjust_address (part[1][1], DImode, 0);
14133 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14137 gcc_unreachable ();
14140 if (GET_MODE (part[1][0]) == SImode)
14141 part[1][0] = part[1][1];
14144 emit_move_insn (part[0][1], part[1][1]);
14145 emit_move_insn (part[0][0], part[1][0]);
14149 /* Choose correct order to not overwrite the source before it is copied. */
14150 if ((REG_P (part[0][0])
14151 && REG_P (part[1][1])
14152 && (REGNO (part[0][0]) == REGNO (part[1][1])
14154 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14156 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14160 operands[2] = part[0][2];
14161 operands[3] = part[0][1];
14162 operands[4] = part[0][0];
14163 operands[5] = part[1][2];
14164 operands[6] = part[1][1];
14165 operands[7] = part[1][0];
14169 operands[2] = part[0][1];
14170 operands[3] = part[0][0];
14171 operands[5] = part[1][1];
14172 operands[6] = part[1][0];
14179 operands[2] = part[0][0];
14180 operands[3] = part[0][1];
14181 operands[4] = part[0][2];
14182 operands[5] = part[1][0];
14183 operands[6] = part[1][1];
14184 operands[7] = part[1][2];
14188 operands[2] = part[0][0];
14189 operands[3] = part[0][1];
14190 operands[5] = part[1][0];
14191 operands[6] = part[1][1];
14195 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14198 if (CONST_INT_P (operands[5])
14199 && operands[5] != const0_rtx
14200 && REG_P (operands[2]))
14202 if (CONST_INT_P (operands[6])
14203 && INTVAL (operands[6]) == INTVAL (operands[5]))
14204 operands[6] = operands[2];
14207 && CONST_INT_P (operands[7])
14208 && INTVAL (operands[7]) == INTVAL (operands[5]))
14209 operands[7] = operands[2];
14213 && CONST_INT_P (operands[6])
14214 && operands[6] != const0_rtx
14215 && REG_P (operands[3])
14216 && CONST_INT_P (operands[7])
14217 && INTVAL (operands[7]) == INTVAL (operands[6]))
14218 operands[7] = operands[3];
14221 emit_move_insn (operands[2], operands[5]);
14222 emit_move_insn (operands[3], operands[6]);
14224 emit_move_insn (operands[4], operands[7]);
14229 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14230 left shift by a constant, either using a single shift or
14231 a sequence of add instructions. */
14234 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14238 emit_insn ((mode == DImode
14240 : gen_adddi3) (operand, operand, operand));
14242 else if (!optimize_size
14243 && count * ix86_cost->add <= ix86_cost->shift_const)
14246 for (i=0; i<count; i++)
14248 emit_insn ((mode == DImode
14250 : gen_adddi3) (operand, operand, operand));
14254 emit_insn ((mode == DImode
14256 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14260 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14262 rtx low[2], high[2];
14264 const int single_width = mode == DImode ? 32 : 64;
14266 if (CONST_INT_P (operands[2]))
14268 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14269 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14271 if (count >= single_width)
14273 emit_move_insn (high[0], low[1]);
14274 emit_move_insn (low[0], const0_rtx);
14276 if (count > single_width)
14277 ix86_expand_ashl_const (high[0], count - single_width, mode);
14281 if (!rtx_equal_p (operands[0], operands[1]))
14282 emit_move_insn (operands[0], operands[1]);
14283 emit_insn ((mode == DImode
14285 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14286 ix86_expand_ashl_const (low[0], count, mode);
14291 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14293 if (operands[1] == const1_rtx)
14295 /* Assuming we've chosen a QImode capable registers, then 1 << N
14296 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14297 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14299 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14301 ix86_expand_clear (low[0]);
14302 ix86_expand_clear (high[0]);
14303 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14305 d = gen_lowpart (QImode, low[0]);
14306 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14307 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14308 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14310 d = gen_lowpart (QImode, high[0]);
14311 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14312 s = gen_rtx_NE (QImode, flags, const0_rtx);
14313 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14316 /* Otherwise, we can get the same results by manually performing
14317 a bit extract operation on bit 5/6, and then performing the two
14318 shifts. The two methods of getting 0/1 into low/high are exactly
14319 the same size. Avoiding the shift in the bit extract case helps
14320 pentium4 a bit; no one else seems to care much either way. */
14325 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14326 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14328 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14329 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14331 emit_insn ((mode == DImode
14333 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14334 emit_insn ((mode == DImode
14336 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14337 emit_move_insn (low[0], high[0]);
14338 emit_insn ((mode == DImode
14340 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14343 emit_insn ((mode == DImode
14345 : gen_ashldi3) (low[0], low[0], operands[2]));
14346 emit_insn ((mode == DImode
14348 : gen_ashldi3) (high[0], high[0], operands[2]));
14352 if (operands[1] == constm1_rtx)
14354 /* For -1 << N, we can avoid the shld instruction, because we
14355 know that we're shifting 0...31/63 ones into a -1. */
14356 emit_move_insn (low[0], constm1_rtx);
14358 emit_move_insn (high[0], low[0]);
14360 emit_move_insn (high[0], constm1_rtx);
14364 if (!rtx_equal_p (operands[0], operands[1]))
14365 emit_move_insn (operands[0], operands[1]);
14367 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14368 emit_insn ((mode == DImode
14370 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14373 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14375 if (TARGET_CMOVE && scratch)
14377 ix86_expand_clear (scratch);
14378 emit_insn ((mode == DImode
14379 ? gen_x86_shift_adj_1
14380 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14383 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14387 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14389 rtx low[2], high[2];
14391 const int single_width = mode == DImode ? 32 : 64;
14393 if (CONST_INT_P (operands[2]))
14395 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14396 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14398 if (count == single_width * 2 - 1)
14400 emit_move_insn (high[0], high[1]);
14401 emit_insn ((mode == DImode
14403 : gen_ashrdi3) (high[0], high[0],
14404 GEN_INT (single_width - 1)));
14405 emit_move_insn (low[0], high[0]);
14408 else if (count >= single_width)
14410 emit_move_insn (low[0], high[1]);
14411 emit_move_insn (high[0], low[0]);
14412 emit_insn ((mode == DImode
14414 : gen_ashrdi3) (high[0], high[0],
14415 GEN_INT (single_width - 1)));
14416 if (count > single_width)
14417 emit_insn ((mode == DImode
14419 : gen_ashrdi3) (low[0], low[0],
14420 GEN_INT (count - single_width)));
14424 if (!rtx_equal_p (operands[0], operands[1]))
14425 emit_move_insn (operands[0], operands[1]);
14426 emit_insn ((mode == DImode
14428 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14429 emit_insn ((mode == DImode
14431 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14436 if (!rtx_equal_p (operands[0], operands[1]))
14437 emit_move_insn (operands[0], operands[1]);
14439 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14441 emit_insn ((mode == DImode
14443 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14444 emit_insn ((mode == DImode
14446 : gen_ashrdi3) (high[0], high[0], operands[2]));
14448 if (TARGET_CMOVE && scratch)
14450 emit_move_insn (scratch, high[0]);
14451 emit_insn ((mode == DImode
14453 : gen_ashrdi3) (scratch, scratch,
14454 GEN_INT (single_width - 1)));
14455 emit_insn ((mode == DImode
14456 ? gen_x86_shift_adj_1
14457 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14461 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14466 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14468 rtx low[2], high[2];
14470 const int single_width = mode == DImode ? 32 : 64;
14472 if (CONST_INT_P (operands[2]))
14474 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14475 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14477 if (count >= single_width)
14479 emit_move_insn (low[0], high[1]);
14480 ix86_expand_clear (high[0]);
14482 if (count > single_width)
14483 emit_insn ((mode == DImode
14485 : gen_lshrdi3) (low[0], low[0],
14486 GEN_INT (count - single_width)));
14490 if (!rtx_equal_p (operands[0], operands[1]))
14491 emit_move_insn (operands[0], operands[1]);
14492 emit_insn ((mode == DImode
14494 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14495 emit_insn ((mode == DImode
14497 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14502 if (!rtx_equal_p (operands[0], operands[1]))
14503 emit_move_insn (operands[0], operands[1]);
14505 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14507 emit_insn ((mode == DImode
14509 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14510 emit_insn ((mode == DImode
14512 : gen_lshrdi3) (high[0], high[0], operands[2]));
14514 /* Heh. By reversing the arguments, we can reuse this pattern. */
14515 if (TARGET_CMOVE && scratch)
14517 ix86_expand_clear (scratch);
14518 emit_insn ((mode == DImode
14519 ? gen_x86_shift_adj_1
14520 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14524 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14528 /* Predict just emitted jump instruction to be taken with probability PROB. */
14530 predict_jump (int prob)
14532 rtx insn = get_last_insn ();
14533 gcc_assert (JUMP_P (insn));
14535 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14540 /* Helper function for the string operations below. Dest VARIABLE whether
14541 it is aligned to VALUE bytes. If true, jump to the label. */
14543 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14545 rtx label = gen_label_rtx ();
14546 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14547 if (GET_MODE (variable) == DImode)
14548 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14550 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14551 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14554 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14556 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14560 /* Adjust COUNTER by the VALUE. */
14562 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14564 if (GET_MODE (countreg) == DImode)
14565 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14567 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14570 /* Zero extend possibly SImode EXP to Pmode register. */
14572 ix86_zero_extend_to_Pmode (rtx exp)
14575 if (GET_MODE (exp) == VOIDmode)
14576 return force_reg (Pmode, exp);
14577 if (GET_MODE (exp) == Pmode)
14578 return copy_to_mode_reg (Pmode, exp);
14579 r = gen_reg_rtx (Pmode);
14580 emit_insn (gen_zero_extendsidi2 (r, exp));
14584 /* Divide COUNTREG by SCALE. */
14586 scale_counter (rtx countreg, int scale)
14589 rtx piece_size_mask;
14593 if (CONST_INT_P (countreg))
14594 return GEN_INT (INTVAL (countreg) / scale);
14595 gcc_assert (REG_P (countreg));
14597 piece_size_mask = GEN_INT (scale - 1);
14598 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14599 GEN_INT (exact_log2 (scale)),
14600 NULL, 1, OPTAB_DIRECT);
14604 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14605 DImode for constant loop counts. */
14607 static enum machine_mode
14608 counter_mode (rtx count_exp)
14610 if (GET_MODE (count_exp) != VOIDmode)
14611 return GET_MODE (count_exp);
14612 if (GET_CODE (count_exp) != CONST_INT)
14614 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14619 /* When SRCPTR is non-NULL, output simple loop to move memory
14620 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14621 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14622 equivalent loop to set memory by VALUE (supposed to be in MODE).
14624 The size is rounded down to whole number of chunk size moved at once.
14625 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14629 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14630 rtx destptr, rtx srcptr, rtx value,
14631 rtx count, enum machine_mode mode, int unroll,
14634 rtx out_label, top_label, iter, tmp;
14635 enum machine_mode iter_mode = counter_mode (count);
14636 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14637 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14643 top_label = gen_label_rtx ();
14644 out_label = gen_label_rtx ();
14645 iter = gen_reg_rtx (iter_mode);
14647 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14648 NULL, 1, OPTAB_DIRECT);
14649 /* Those two should combine. */
14650 if (piece_size == const1_rtx)
14652 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14654 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14656 emit_move_insn (iter, const0_rtx);
14658 emit_label (top_label);
14660 tmp = convert_modes (Pmode, iter_mode, iter, true);
14661 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14662 destmem = change_address (destmem, mode, x_addr);
14666 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14667 srcmem = change_address (srcmem, mode, y_addr);
14669 /* When unrolling for chips that reorder memory reads and writes,
14670 we can save registers by using single temporary.
14671 Also using 4 temporaries is overkill in 32bit mode. */
14672 if (!TARGET_64BIT && 0)
14674 for (i = 0; i < unroll; i++)
14679 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14681 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14683 emit_move_insn (destmem, srcmem);
14689 gcc_assert (unroll <= 4);
14690 for (i = 0; i < unroll; i++)
14692 tmpreg[i] = gen_reg_rtx (mode);
14696 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14698 emit_move_insn (tmpreg[i], srcmem);
14700 for (i = 0; i < unroll; i++)
14705 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14707 emit_move_insn (destmem, tmpreg[i]);
14712 for (i = 0; i < unroll; i++)
14716 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14717 emit_move_insn (destmem, value);
14720 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14721 true, OPTAB_LIB_WIDEN);
14723 emit_move_insn (iter, tmp);
14725 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14727 if (expected_size != -1)
14729 expected_size /= GET_MODE_SIZE (mode) * unroll;
14730 if (expected_size == 0)
14732 else if (expected_size > REG_BR_PROB_BASE)
14733 predict_jump (REG_BR_PROB_BASE - 1);
14735 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14738 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14739 iter = ix86_zero_extend_to_Pmode (iter);
14740 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14741 true, OPTAB_LIB_WIDEN);
14742 if (tmp != destptr)
14743 emit_move_insn (destptr, tmp);
14746 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14747 true, OPTAB_LIB_WIDEN);
14749 emit_move_insn (srcptr, tmp);
14751 emit_label (out_label);
14754 /* Output "rep; mov" instruction.
14755 Arguments have same meaning as for previous function */
14757 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14758 rtx destptr, rtx srcptr,
14760 enum machine_mode mode)
14766 /* If the size is known, it is shorter to use rep movs. */
14767 if (mode == QImode && CONST_INT_P (count)
14768 && !(INTVAL (count) & 3))
14771 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14772 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14773 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14774 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14775 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14776 if (mode != QImode)
14778 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14779 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14780 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14781 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14782 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14783 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14787 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14788 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14790 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14794 /* Output "rep; stos" instruction.
14795 Arguments have same meaning as for previous function */
14797 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14799 enum machine_mode mode)
14804 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14805 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14806 value = force_reg (mode, gen_lowpart (mode, value));
14807 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14808 if (mode != QImode)
14810 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14811 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14812 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14815 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14816 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14820 emit_strmov (rtx destmem, rtx srcmem,
14821 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14823 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14824 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14825 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14828 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14830 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14831 rtx destptr, rtx srcptr, rtx count, int max_size)
14834 if (CONST_INT_P (count))
14836 HOST_WIDE_INT countval = INTVAL (count);
14839 if ((countval & 0x10) && max_size > 16)
14843 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14844 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14847 gcc_unreachable ();
14850 if ((countval & 0x08) && max_size > 8)
14853 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14856 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14857 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14861 if ((countval & 0x04) && max_size > 4)
14863 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14866 if ((countval & 0x02) && max_size > 2)
14868 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14871 if ((countval & 0x01) && max_size > 1)
14873 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14880 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14881 count, 1, OPTAB_DIRECT);
14882 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14883 count, QImode, 1, 4);
14887 /* When there are stringops, we can cheaply increase dest and src pointers.
14888 Otherwise we save code size by maintaining offset (zero is readily
14889 available from preceding rep operation) and using x86 addressing modes.
14891 if (TARGET_SINGLE_STRINGOP)
14895 rtx label = ix86_expand_aligntest (count, 4, true);
14896 src = change_address (srcmem, SImode, srcptr);
14897 dest = change_address (destmem, SImode, destptr);
14898 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14899 emit_label (label);
14900 LABEL_NUSES (label) = 1;
14904 rtx label = ix86_expand_aligntest (count, 2, true);
14905 src = change_address (srcmem, HImode, srcptr);
14906 dest = change_address (destmem, HImode, destptr);
14907 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14908 emit_label (label);
14909 LABEL_NUSES (label) = 1;
14913 rtx label = ix86_expand_aligntest (count, 1, true);
14914 src = change_address (srcmem, QImode, srcptr);
14915 dest = change_address (destmem, QImode, destptr);
14916 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14917 emit_label (label);
14918 LABEL_NUSES (label) = 1;
14923 rtx offset = force_reg (Pmode, const0_rtx);
14928 rtx label = ix86_expand_aligntest (count, 4, true);
14929 src = change_address (srcmem, SImode, srcptr);
14930 dest = change_address (destmem, SImode, destptr);
14931 emit_move_insn (dest, src);
14932 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14933 true, OPTAB_LIB_WIDEN);
14935 emit_move_insn (offset, tmp);
14936 emit_label (label);
14937 LABEL_NUSES (label) = 1;
14941 rtx label = ix86_expand_aligntest (count, 2, true);
14942 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14943 src = change_address (srcmem, HImode, tmp);
14944 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14945 dest = change_address (destmem, HImode, tmp);
14946 emit_move_insn (dest, src);
14947 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14948 true, OPTAB_LIB_WIDEN);
14950 emit_move_insn (offset, tmp);
14951 emit_label (label);
14952 LABEL_NUSES (label) = 1;
14956 rtx label = ix86_expand_aligntest (count, 1, true);
14957 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14958 src = change_address (srcmem, QImode, tmp);
14959 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14960 dest = change_address (destmem, QImode, tmp);
14961 emit_move_insn (dest, src);
14962 emit_label (label);
14963 LABEL_NUSES (label) = 1;
14968 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14970 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14971 rtx count, int max_size)
14974 expand_simple_binop (counter_mode (count), AND, count,
14975 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14976 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14977 gen_lowpart (QImode, value), count, QImode,
14981 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14983 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14987 if (CONST_INT_P (count))
14989 HOST_WIDE_INT countval = INTVAL (count);
14992 if ((countval & 0x10) && max_size > 16)
14996 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14997 emit_insn (gen_strset (destptr, dest, value));
14998 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14999 emit_insn (gen_strset (destptr, dest, value));
15002 gcc_unreachable ();
15005 if ((countval & 0x08) && max_size > 8)
15009 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15010 emit_insn (gen_strset (destptr, dest, value));
15014 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15015 emit_insn (gen_strset (destptr, dest, value));
15016 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15017 emit_insn (gen_strset (destptr, dest, value));
15021 if ((countval & 0x04) && max_size > 4)
15023 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15024 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15027 if ((countval & 0x02) && max_size > 2)
15029 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15030 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15033 if ((countval & 0x01) && max_size > 1)
15035 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15036 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15043 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15048 rtx label = ix86_expand_aligntest (count, 16, true);
15051 dest = change_address (destmem, DImode, destptr);
15052 emit_insn (gen_strset (destptr, dest, value));
15053 emit_insn (gen_strset (destptr, dest, value));
15057 dest = change_address (destmem, SImode, destptr);
15058 emit_insn (gen_strset (destptr, dest, value));
15059 emit_insn (gen_strset (destptr, dest, value));
15060 emit_insn (gen_strset (destptr, dest, value));
15061 emit_insn (gen_strset (destptr, dest, value));
15063 emit_label (label);
15064 LABEL_NUSES (label) = 1;
15068 rtx label = ix86_expand_aligntest (count, 8, true);
15071 dest = change_address (destmem, DImode, destptr);
15072 emit_insn (gen_strset (destptr, dest, value));
15076 dest = change_address (destmem, SImode, destptr);
15077 emit_insn (gen_strset (destptr, dest, value));
15078 emit_insn (gen_strset (destptr, dest, value));
15080 emit_label (label);
15081 LABEL_NUSES (label) = 1;
15085 rtx label = ix86_expand_aligntest (count, 4, true);
15086 dest = change_address (destmem, SImode, destptr);
15087 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15088 emit_label (label);
15089 LABEL_NUSES (label) = 1;
15093 rtx label = ix86_expand_aligntest (count, 2, true);
15094 dest = change_address (destmem, HImode, destptr);
15095 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15096 emit_label (label);
15097 LABEL_NUSES (label) = 1;
15101 rtx label = ix86_expand_aligntest (count, 1, true);
15102 dest = change_address (destmem, QImode, destptr);
15103 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15104 emit_label (label);
15105 LABEL_NUSES (label) = 1;
15109 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15110 DESIRED_ALIGNMENT. */
15112 expand_movmem_prologue (rtx destmem, rtx srcmem,
15113 rtx destptr, rtx srcptr, rtx count,
15114 int align, int desired_alignment)
15116 if (align <= 1 && desired_alignment > 1)
15118 rtx label = ix86_expand_aligntest (destptr, 1, false);
15119 srcmem = change_address (srcmem, QImode, srcptr);
15120 destmem = change_address (destmem, QImode, destptr);
15121 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15122 ix86_adjust_counter (count, 1);
15123 emit_label (label);
15124 LABEL_NUSES (label) = 1;
15126 if (align <= 2 && desired_alignment > 2)
15128 rtx label = ix86_expand_aligntest (destptr, 2, false);
15129 srcmem = change_address (srcmem, HImode, srcptr);
15130 destmem = change_address (destmem, HImode, destptr);
15131 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15132 ix86_adjust_counter (count, 2);
15133 emit_label (label);
15134 LABEL_NUSES (label) = 1;
15136 if (align <= 4 && desired_alignment > 4)
15138 rtx label = ix86_expand_aligntest (destptr, 4, false);
15139 srcmem = change_address (srcmem, SImode, srcptr);
15140 destmem = change_address (destmem, SImode, destptr);
15141 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15142 ix86_adjust_counter (count, 4);
15143 emit_label (label);
15144 LABEL_NUSES (label) = 1;
15146 gcc_assert (desired_alignment <= 8);
15149 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15150 DESIRED_ALIGNMENT. */
15152 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15153 int align, int desired_alignment)
15155 if (align <= 1 && desired_alignment > 1)
15157 rtx label = ix86_expand_aligntest (destptr, 1, false);
15158 destmem = change_address (destmem, QImode, destptr);
15159 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15160 ix86_adjust_counter (count, 1);
15161 emit_label (label);
15162 LABEL_NUSES (label) = 1;
15164 if (align <= 2 && desired_alignment > 2)
15166 rtx label = ix86_expand_aligntest (destptr, 2, false);
15167 destmem = change_address (destmem, HImode, destptr);
15168 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15169 ix86_adjust_counter (count, 2);
15170 emit_label (label);
15171 LABEL_NUSES (label) = 1;
15173 if (align <= 4 && desired_alignment > 4)
15175 rtx label = ix86_expand_aligntest (destptr, 4, false);
15176 destmem = change_address (destmem, SImode, destptr);
15177 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15178 ix86_adjust_counter (count, 4);
15179 emit_label (label);
15180 LABEL_NUSES (label) = 1;
15182 gcc_assert (desired_alignment <= 8);
15185 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15186 static enum stringop_alg
15187 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15188 int *dynamic_check)
15190 const struct stringop_algs * algs;
15191 /* Algorithms using the rep prefix want at least edi and ecx;
15192 additionally, memset wants eax and memcpy wants esi. Don't
15193 consider such algorithms if the user has appropriated those
15194 registers for their own purposes. */
15195 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15197 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15199 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15200 || (alg != rep_prefix_1_byte \
15201 && alg != rep_prefix_4_byte \
15202 && alg != rep_prefix_8_byte))
15204 *dynamic_check = -1;
15206 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15208 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15209 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15210 return stringop_alg;
15211 /* rep; movq or rep; movl is the smallest variant. */
15212 else if (optimize_size)
15214 if (!count || (count & 3))
15215 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15217 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15219 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15221 else if (expected_size != -1 && expected_size < 4)
15222 return loop_1_byte;
15223 else if (expected_size != -1)
15226 enum stringop_alg alg = libcall;
15227 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15229 /* We get here if the algorithms that were not libcall-based
15230 were rep-prefix based and we are unable to use rep prefixes
15231 based on global register usage. Break out of the loop and
15232 use the heuristic below. */
15233 if (algs->size[i].max == 0)
15235 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15237 enum stringop_alg candidate = algs->size[i].alg;
15239 if (candidate != libcall && ALG_USABLE_P (candidate))
15241 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15242 last non-libcall inline algorithm. */
15243 if (TARGET_INLINE_ALL_STRINGOPS)
15245 /* When the current size is best to be copied by a libcall,
15246 but we are still forced to inline, run the heuristic below
15247 that will pick code for medium sized blocks. */
15248 if (alg != libcall)
15252 else if (ALG_USABLE_P (candidate))
15256 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15258 /* When asked to inline the call anyway, try to pick meaningful choice.
15259 We look for maximal size of block that is faster to copy by hand and
15260 take blocks of at most of that size guessing that average size will
15261 be roughly half of the block.
15263 If this turns out to be bad, we might simply specify the preferred
15264 choice in ix86_costs. */
15265 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15266 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15269 enum stringop_alg alg;
15271 bool any_alg_usable_p = true;
15273 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15275 enum stringop_alg candidate = algs->size[i].alg;
15276 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15278 if (candidate != libcall && candidate
15279 && ALG_USABLE_P (candidate))
15280 max = algs->size[i].max;
15282 /* If there aren't any usable algorithms, then recursing on
15283 smaller sizes isn't going to find anything. Just return the
15284 simple byte-at-a-time copy loop. */
15285 if (!any_alg_usable_p)
15287 /* Pick something reasonable. */
15288 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15289 *dynamic_check = 128;
15290 return loop_1_byte;
15294 alg = decide_alg (count, max / 2, memset, dynamic_check);
15295 gcc_assert (*dynamic_check == -1);
15296 gcc_assert (alg != libcall);
15297 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15298 *dynamic_check = max;
15301 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15302 #undef ALG_USABLE_P
15305 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15306 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15308 decide_alignment (int align,
15309 enum stringop_alg alg,
15312 int desired_align = 0;
15316 gcc_unreachable ();
15318 case unrolled_loop:
15319 desired_align = GET_MODE_SIZE (Pmode);
15321 case rep_prefix_8_byte:
15324 case rep_prefix_4_byte:
15325 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15326 copying whole cacheline at once. */
15327 if (TARGET_PENTIUMPRO)
15332 case rep_prefix_1_byte:
15333 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15334 copying whole cacheline at once. */
15335 if (TARGET_PENTIUMPRO)
15349 if (desired_align < align)
15350 desired_align = align;
15351 if (expected_size != -1 && expected_size < 4)
15352 desired_align = align;
15353 return desired_align;
15356 /* Return the smallest power of 2 greater than VAL. */
15358 smallest_pow2_greater_than (int val)
15366 /* Expand string move (memcpy) operation. Use i386 string operations when
15367 profitable. expand_setmem contains similar code. The code depends upon
15368 architecture, block size and alignment, but always has the same
15371 1) Prologue guard: Conditional that jumps up to epilogues for small
15372 blocks that can be handled by epilogue alone. This is faster but
15373 also needed for correctness, since prologue assume the block is larger
15374 than the desired alignment.
15376 Optional dynamic check for size and libcall for large
15377 blocks is emitted here too, with -minline-stringops-dynamically.
15379 2) Prologue: copy first few bytes in order to get destination aligned
15380 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15381 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15382 We emit either a jump tree on power of two sized blocks, or a byte loop.
15384 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15385 with specified algorithm.
15387 4) Epilogue: code copying tail of the block that is too small to be
15388 handled by main body (or up to size guarded by prologue guard). */
15391 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15392 rtx expected_align_exp, rtx expected_size_exp)
15398 rtx jump_around_label = NULL;
15399 HOST_WIDE_INT align = 1;
15400 unsigned HOST_WIDE_INT count = 0;
15401 HOST_WIDE_INT expected_size = -1;
15402 int size_needed = 0, epilogue_size_needed;
15403 int desired_align = 0;
15404 enum stringop_alg alg;
15407 if (CONST_INT_P (align_exp))
15408 align = INTVAL (align_exp);
15409 /* i386 can do misaligned access on reasonably increased cost. */
15410 if (CONST_INT_P (expected_align_exp)
15411 && INTVAL (expected_align_exp) > align)
15412 align = INTVAL (expected_align_exp);
15413 if (CONST_INT_P (count_exp))
15414 count = expected_size = INTVAL (count_exp);
15415 if (CONST_INT_P (expected_size_exp) && count == 0)
15416 expected_size = INTVAL (expected_size_exp);
15418 /* Make sure we don't need to care about overflow later on. */
15419 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15422 /* Step 0: Decide on preferred algorithm, desired alignment and
15423 size of chunks to be copied by main loop. */
15425 alg = decide_alg (count, expected_size, false, &dynamic_check);
15426 desired_align = decide_alignment (align, alg, expected_size);
15428 if (!TARGET_ALIGN_STRINGOPS)
15429 align = desired_align;
15431 if (alg == libcall)
15433 gcc_assert (alg != no_stringop);
15435 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15436 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15437 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15442 gcc_unreachable ();
15444 size_needed = GET_MODE_SIZE (Pmode);
15446 case unrolled_loop:
15447 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15449 case rep_prefix_8_byte:
15452 case rep_prefix_4_byte:
15455 case rep_prefix_1_byte:
15461 epilogue_size_needed = size_needed;
15463 /* Step 1: Prologue guard. */
15465 /* Alignment code needs count to be in register. */
15466 if (CONST_INT_P (count_exp) && desired_align > align)
15467 count_exp = force_reg (counter_mode (count_exp), count_exp);
15468 gcc_assert (desired_align >= 1 && align >= 1);
15470 /* Ensure that alignment prologue won't copy past end of block. */
15471 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15473 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15474 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15475 Make sure it is power of 2. */
15476 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15478 if (CONST_INT_P (count_exp))
15480 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15485 label = gen_label_rtx ();
15486 emit_cmp_and_jump_insns (count_exp,
15487 GEN_INT (epilogue_size_needed),
15488 LTU, 0, counter_mode (count_exp), 1, label);
15489 if (expected_size == -1 || expected_size < epilogue_size_needed)
15490 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15492 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15496 /* Emit code to decide on runtime whether library call or inline should be
15498 if (dynamic_check != -1)
15500 if (CONST_INT_P (count_exp))
15502 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15504 emit_block_move_via_libcall (dst, src, count_exp, false);
15505 count_exp = const0_rtx;
15511 rtx hot_label = gen_label_rtx ();
15512 jump_around_label = gen_label_rtx ();
15513 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15514 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15515 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15516 emit_block_move_via_libcall (dst, src, count_exp, false);
15517 emit_jump (jump_around_label);
15518 emit_label (hot_label);
15522 /* Step 2: Alignment prologue. */
15524 if (desired_align > align)
15526 /* Except for the first move in epilogue, we no longer know
15527 constant offset in aliasing info. It don't seems to worth
15528 the pain to maintain it for the first move, so throw away
15530 src = change_address (src, BLKmode, srcreg);
15531 dst = change_address (dst, BLKmode, destreg);
15532 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15535 if (label && size_needed == 1)
15537 emit_label (label);
15538 LABEL_NUSES (label) = 1;
15542 /* Step 3: Main loop. */
15548 gcc_unreachable ();
15550 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15551 count_exp, QImode, 1, expected_size);
15554 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15555 count_exp, Pmode, 1, expected_size);
15557 case unrolled_loop:
15558 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15559 registers for 4 temporaries anyway. */
15560 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15561 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15564 case rep_prefix_8_byte:
15565 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15568 case rep_prefix_4_byte:
15569 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15572 case rep_prefix_1_byte:
15573 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15577 /* Adjust properly the offset of src and dest memory for aliasing. */
15578 if (CONST_INT_P (count_exp))
15580 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15581 (count / size_needed) * size_needed);
15582 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15583 (count / size_needed) * size_needed);
15587 src = change_address (src, BLKmode, srcreg);
15588 dst = change_address (dst, BLKmode, destreg);
15591 /* Step 4: Epilogue to copy the remaining bytes. */
15595 /* When the main loop is done, COUNT_EXP might hold original count,
15596 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15597 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15598 bytes. Compensate if needed. */
15600 if (size_needed < epilogue_size_needed)
15603 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15604 GEN_INT (size_needed - 1), count_exp, 1,
15606 if (tmp != count_exp)
15607 emit_move_insn (count_exp, tmp);
15609 emit_label (label);
15610 LABEL_NUSES (label) = 1;
15613 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15614 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15615 epilogue_size_needed);
15616 if (jump_around_label)
15617 emit_label (jump_around_label);
15621 /* Helper function for memcpy. For QImode value 0xXY produce
15622 0xXYXYXYXY of wide specified by MODE. This is essentially
15623 a * 0x10101010, but we can do slightly better than
15624 synth_mult by unwinding the sequence by hand on CPUs with
15627 promote_duplicated_reg (enum machine_mode mode, rtx val)
15629 enum machine_mode valmode = GET_MODE (val);
15631 int nops = mode == DImode ? 3 : 2;
15633 gcc_assert (mode == SImode || mode == DImode);
15634 if (val == const0_rtx)
15635 return copy_to_mode_reg (mode, const0_rtx);
15636 if (CONST_INT_P (val))
15638 HOST_WIDE_INT v = INTVAL (val) & 255;
15642 if (mode == DImode)
15643 v |= (v << 16) << 16;
15644 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15647 if (valmode == VOIDmode)
15649 if (valmode != QImode)
15650 val = gen_lowpart (QImode, val);
15651 if (mode == QImode)
15653 if (!TARGET_PARTIAL_REG_STALL)
15655 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15656 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15657 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15658 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15660 rtx reg = convert_modes (mode, QImode, val, true);
15661 tmp = promote_duplicated_reg (mode, const1_rtx);
15662 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15667 rtx reg = convert_modes (mode, QImode, val, true);
15669 if (!TARGET_PARTIAL_REG_STALL)
15670 if (mode == SImode)
15671 emit_insn (gen_movsi_insv_1 (reg, reg));
15673 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15676 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15677 NULL, 1, OPTAB_DIRECT);
15679 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15681 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15682 NULL, 1, OPTAB_DIRECT);
15683 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15684 if (mode == SImode)
15686 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15687 NULL, 1, OPTAB_DIRECT);
15688 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15693 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15694 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15695 alignment from ALIGN to DESIRED_ALIGN. */
15697 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15702 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15703 promoted_val = promote_duplicated_reg (DImode, val);
15704 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15705 promoted_val = promote_duplicated_reg (SImode, val);
15706 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15707 promoted_val = promote_duplicated_reg (HImode, val);
15709 promoted_val = val;
15711 return promoted_val;
15714 /* Expand string clear operation (bzero). Use i386 string operations when
15715 profitable. See expand_movmem comment for explanation of individual
15716 steps performed. */
15718 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15719 rtx expected_align_exp, rtx expected_size_exp)
15724 rtx jump_around_label = NULL;
15725 HOST_WIDE_INT align = 1;
15726 unsigned HOST_WIDE_INT count = 0;
15727 HOST_WIDE_INT expected_size = -1;
15728 int size_needed = 0, epilogue_size_needed;
15729 int desired_align = 0;
15730 enum stringop_alg alg;
15731 rtx promoted_val = NULL;
15732 bool force_loopy_epilogue = false;
15735 if (CONST_INT_P (align_exp))
15736 align = INTVAL (align_exp);
15737 /* i386 can do misaligned access on reasonably increased cost. */
15738 if (CONST_INT_P (expected_align_exp)
15739 && INTVAL (expected_align_exp) > align)
15740 align = INTVAL (expected_align_exp);
15741 if (CONST_INT_P (count_exp))
15742 count = expected_size = INTVAL (count_exp);
15743 if (CONST_INT_P (expected_size_exp) && count == 0)
15744 expected_size = INTVAL (expected_size_exp);
15746 /* Make sure we don't need to care about overflow later on. */
15747 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15750 /* Step 0: Decide on preferred algorithm, desired alignment and
15751 size of chunks to be copied by main loop. */
15753 alg = decide_alg (count, expected_size, true, &dynamic_check);
15754 desired_align = decide_alignment (align, alg, expected_size);
15756 if (!TARGET_ALIGN_STRINGOPS)
15757 align = desired_align;
15759 if (alg == libcall)
15761 gcc_assert (alg != no_stringop);
15763 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15764 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15769 gcc_unreachable ();
15771 size_needed = GET_MODE_SIZE (Pmode);
15773 case unrolled_loop:
15774 size_needed = GET_MODE_SIZE (Pmode) * 4;
15776 case rep_prefix_8_byte:
15779 case rep_prefix_4_byte:
15782 case rep_prefix_1_byte:
15787 epilogue_size_needed = size_needed;
15789 /* Step 1: Prologue guard. */
15791 /* Alignment code needs count to be in register. */
15792 if (CONST_INT_P (count_exp) && desired_align > align)
15794 enum machine_mode mode = SImode;
15795 if (TARGET_64BIT && (count & ~0xffffffff))
15797 count_exp = force_reg (mode, count_exp);
15799 /* Do the cheap promotion to allow better CSE across the
15800 main loop and epilogue (ie one load of the big constant in the
15801 front of all code. */
15802 if (CONST_INT_P (val_exp))
15803 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15804 desired_align, align);
15805 /* Ensure that alignment prologue won't copy past end of block. */
15806 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15808 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15809 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15810 Make sure it is power of 2. */
15811 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15813 /* To improve performance of small blocks, we jump around the VAL
15814 promoting mode. This mean that if the promoted VAL is not constant,
15815 we might not use it in the epilogue and have to use byte
15817 if (epilogue_size_needed > 2 && !promoted_val)
15818 force_loopy_epilogue = true;
15819 label = gen_label_rtx ();
15820 emit_cmp_and_jump_insns (count_exp,
15821 GEN_INT (epilogue_size_needed),
15822 LTU, 0, counter_mode (count_exp), 1, label);
15823 if (GET_CODE (count_exp) == CONST_INT)
15825 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15826 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15828 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15830 if (dynamic_check != -1)
15832 rtx hot_label = gen_label_rtx ();
15833 jump_around_label = gen_label_rtx ();
15834 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15835 LEU, 0, counter_mode (count_exp), 1, hot_label);
15836 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15837 set_storage_via_libcall (dst, count_exp, val_exp, false);
15838 emit_jump (jump_around_label);
15839 emit_label (hot_label);
15842 /* Step 2: Alignment prologue. */
15844 /* Do the expensive promotion once we branched off the small blocks. */
15846 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15847 desired_align, align);
15848 gcc_assert (desired_align >= 1 && align >= 1);
15850 if (desired_align > align)
15852 /* Except for the first move in epilogue, we no longer know
15853 constant offset in aliasing info. It don't seems to worth
15854 the pain to maintain it for the first move, so throw away
15856 dst = change_address (dst, BLKmode, destreg);
15857 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15860 if (label && size_needed == 1)
15862 emit_label (label);
15863 LABEL_NUSES (label) = 1;
15867 /* Step 3: Main loop. */
15873 gcc_unreachable ();
15875 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15876 count_exp, QImode, 1, expected_size);
15879 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15880 count_exp, Pmode, 1, expected_size);
15882 case unrolled_loop:
15883 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15884 count_exp, Pmode, 4, expected_size);
15886 case rep_prefix_8_byte:
15887 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15890 case rep_prefix_4_byte:
15891 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15894 case rep_prefix_1_byte:
15895 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15899 /* Adjust properly the offset of src and dest memory for aliasing. */
15900 if (CONST_INT_P (count_exp))
15901 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15902 (count / size_needed) * size_needed);
15904 dst = change_address (dst, BLKmode, destreg);
15906 /* Step 4: Epilogue to copy the remaining bytes. */
15910 /* When the main loop is done, COUNT_EXP might hold original count,
15911 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15912 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15913 bytes. Compensate if needed. */
15915 if (size_needed < desired_align - align)
15918 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15919 GEN_INT (size_needed - 1), count_exp, 1,
15921 size_needed = desired_align - align + 1;
15922 if (tmp != count_exp)
15923 emit_move_insn (count_exp, tmp);
15925 emit_label (label);
15926 LABEL_NUSES (label) = 1;
15928 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15930 if (force_loopy_epilogue)
15931 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15934 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15937 if (jump_around_label)
15938 emit_label (jump_around_label);
15942 /* Expand the appropriate insns for doing strlen if not just doing
15945 out = result, initialized with the start address
15946 align_rtx = alignment of the address.
15947 scratch = scratch register, initialized with the startaddress when
15948 not aligned, otherwise undefined
15950 This is just the body. It needs the initializations mentioned above and
15951 some address computing at the end. These things are done in i386.md. */
15954 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15958 rtx align_2_label = NULL_RTX;
15959 rtx align_3_label = NULL_RTX;
15960 rtx align_4_label = gen_label_rtx ();
15961 rtx end_0_label = gen_label_rtx ();
15963 rtx tmpreg = gen_reg_rtx (SImode);
15964 rtx scratch = gen_reg_rtx (SImode);
15968 if (CONST_INT_P (align_rtx))
15969 align = INTVAL (align_rtx);
15971 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15973 /* Is there a known alignment and is it less than 4? */
15976 rtx scratch1 = gen_reg_rtx (Pmode);
15977 emit_move_insn (scratch1, out);
15978 /* Is there a known alignment and is it not 2? */
15981 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15982 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15984 /* Leave just the 3 lower bits. */
15985 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15986 NULL_RTX, 0, OPTAB_WIDEN);
15988 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15989 Pmode, 1, align_4_label);
15990 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15991 Pmode, 1, align_2_label);
15992 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15993 Pmode, 1, align_3_label);
15997 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15998 check if is aligned to 4 - byte. */
16000 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
16001 NULL_RTX, 0, OPTAB_WIDEN);
16003 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16004 Pmode, 1, align_4_label);
16007 mem = change_address (src, QImode, out);
16009 /* Now compare the bytes. */
16011 /* Compare the first n unaligned byte on a byte per byte basis. */
16012 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16013 QImode, 1, end_0_label);
16015 /* Increment the address. */
16017 emit_insn (gen_adddi3 (out, out, const1_rtx));
16019 emit_insn (gen_addsi3 (out, out, const1_rtx));
16021 /* Not needed with an alignment of 2 */
16024 emit_label (align_2_label);
16026 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16030 emit_insn (gen_adddi3 (out, out, const1_rtx));
16032 emit_insn (gen_addsi3 (out, out, const1_rtx));
16034 emit_label (align_3_label);
16037 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16041 emit_insn (gen_adddi3 (out, out, const1_rtx));
16043 emit_insn (gen_addsi3 (out, out, const1_rtx));
16046 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16047 align this loop. It gives only huge programs, but does not help to
16049 emit_label (align_4_label);
16051 mem = change_address (src, SImode, out);
16052 emit_move_insn (scratch, mem);
16054 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
16056 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
16058 /* This formula yields a nonzero result iff one of the bytes is zero.
16059 This saves three branches inside loop and many cycles. */
16061 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16062 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16063 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16064 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16065 gen_int_mode (0x80808080, SImode)));
16066 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16071 rtx reg = gen_reg_rtx (SImode);
16072 rtx reg2 = gen_reg_rtx (Pmode);
16073 emit_move_insn (reg, tmpreg);
16074 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16076 /* If zero is not in the first two bytes, move two bytes forward. */
16077 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16078 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16079 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16080 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16081 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16084 /* Emit lea manually to avoid clobbering of flags. */
16085 emit_insn (gen_rtx_SET (SImode, reg2,
16086 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16088 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16089 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16090 emit_insn (gen_rtx_SET (VOIDmode, out,
16091 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16098 rtx end_2_label = gen_label_rtx ();
16099 /* Is zero in the first two bytes? */
16101 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16102 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16103 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16104 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16105 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16107 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16108 JUMP_LABEL (tmp) = end_2_label;
16110 /* Not in the first two. Move two bytes forward. */
16111 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16113 emit_insn (gen_adddi3 (out, out, const2_rtx));
16115 emit_insn (gen_addsi3 (out, out, const2_rtx));
16117 emit_label (end_2_label);
16121 /* Avoid branch in fixing the byte. */
16122 tmpreg = gen_lowpart (QImode, tmpreg);
16123 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16124 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16126 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
16128 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
16130 emit_label (end_0_label);
16133 /* Expand strlen. */
16136 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16138 rtx addr, scratch1, scratch2, scratch3, scratch4;
16140 /* The generic case of strlen expander is long. Avoid it's
16141 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16143 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16144 && !TARGET_INLINE_ALL_STRINGOPS
16146 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16149 addr = force_reg (Pmode, XEXP (src, 0));
16150 scratch1 = gen_reg_rtx (Pmode);
16152 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16155 /* Well it seems that some optimizer does not combine a call like
16156 foo(strlen(bar), strlen(bar));
16157 when the move and the subtraction is done here. It does calculate
16158 the length just once when these instructions are done inside of
16159 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16160 often used and I use one fewer register for the lifetime of
16161 output_strlen_unroll() this is better. */
16163 emit_move_insn (out, addr);
16165 ix86_expand_strlensi_unroll_1 (out, src, align);
16167 /* strlensi_unroll_1 returns the address of the zero at the end of
16168 the string, like memchr(), so compute the length by subtracting
16169 the start address. */
16171 emit_insn (gen_subdi3 (out, out, addr));
16173 emit_insn (gen_subsi3 (out, out, addr));
16179 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16180 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16183 scratch2 = gen_reg_rtx (Pmode);
16184 scratch3 = gen_reg_rtx (Pmode);
16185 scratch4 = force_reg (Pmode, constm1_rtx);
16187 emit_move_insn (scratch3, addr);
16188 eoschar = force_reg (QImode, eoschar);
16190 src = replace_equiv_address_nv (src, scratch3);
16192 /* If .md starts supporting :P, this can be done in .md. */
16193 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16194 scratch4), UNSPEC_SCAS);
16195 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16198 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16199 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16203 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16204 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16210 /* For given symbol (function) construct code to compute address of it's PLT
16211 entry in large x86-64 PIC model. */
16213 construct_plt_address (rtx symbol)
16215 rtx tmp = gen_reg_rtx (Pmode);
16216 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16218 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16219 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16221 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16222 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16227 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16228 rtx callarg2 ATTRIBUTE_UNUSED,
16229 rtx pop, int sibcall)
16231 rtx use = NULL, call;
16233 if (pop == const0_rtx)
16235 gcc_assert (!TARGET_64BIT || !pop);
16237 if (TARGET_MACHO && !TARGET_64BIT)
16240 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16241 fnaddr = machopic_indirect_call_target (fnaddr);
16246 /* Static functions and indirect calls don't need the pic register. */
16247 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16248 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16249 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16250 use_reg (&use, pic_offset_table_rtx);
16253 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16255 rtx al = gen_rtx_REG (QImode, AX_REG);
16256 emit_move_insn (al, callarg2);
16257 use_reg (&use, al);
16260 if (ix86_cmodel == CM_LARGE_PIC
16261 && GET_CODE (fnaddr) == MEM
16262 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16263 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16264 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16265 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16267 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16268 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16270 if (sibcall && TARGET_64BIT
16271 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16274 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16275 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16276 emit_move_insn (fnaddr, addr);
16277 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16280 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16282 call = gen_rtx_SET (VOIDmode, retval, call);
16285 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16286 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16287 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16290 call = emit_call_insn (call);
16292 CALL_INSN_FUNCTION_USAGE (call) = use;
16296 /* Clear stack slot assignments remembered from previous functions.
16297 This is called from INIT_EXPANDERS once before RTL is emitted for each
16300 static struct machine_function *
16301 ix86_init_machine_status (void)
16303 struct machine_function *f;
16305 f = GGC_CNEW (struct machine_function);
16306 f->use_fast_prologue_epilogue_nregs = -1;
16307 f->tls_descriptor_call_expanded_p = 0;
16312 /* Return a MEM corresponding to a stack slot with mode MODE.
16313 Allocate a new slot if necessary.
16315 The RTL for a function can have several slots available: N is
16316 which slot to use. */
16319 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16321 struct stack_local_entry *s;
16323 gcc_assert (n < MAX_386_STACK_LOCALS);
16325 /* Virtual slot is valid only before vregs are instantiated. */
16326 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16328 for (s = ix86_stack_locals; s; s = s->next)
16329 if (s->mode == mode && s->n == n)
16330 return copy_rtx (s->rtl);
16332 s = (struct stack_local_entry *)
16333 ggc_alloc (sizeof (struct stack_local_entry));
16336 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16338 s->next = ix86_stack_locals;
16339 ix86_stack_locals = s;
16343 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16345 static GTY(()) rtx ix86_tls_symbol;
16347 ix86_tls_get_addr (void)
16350 if (!ix86_tls_symbol)
16352 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16353 (TARGET_ANY_GNU_TLS
16355 ? "___tls_get_addr"
16356 : "__tls_get_addr");
16359 return ix86_tls_symbol;
16362 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16364 static GTY(()) rtx ix86_tls_module_base_symbol;
16366 ix86_tls_module_base (void)
16369 if (!ix86_tls_module_base_symbol)
16371 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16372 "_TLS_MODULE_BASE_");
16373 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16374 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16377 return ix86_tls_module_base_symbol;
16380 /* Calculate the length of the memory address in the instruction
16381 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16384 memory_address_length (rtx addr)
16386 struct ix86_address parts;
16387 rtx base, index, disp;
16391 if (GET_CODE (addr) == PRE_DEC
16392 || GET_CODE (addr) == POST_INC
16393 || GET_CODE (addr) == PRE_MODIFY
16394 || GET_CODE (addr) == POST_MODIFY)
16397 ok = ix86_decompose_address (addr, &parts);
16400 if (parts.base && GET_CODE (parts.base) == SUBREG)
16401 parts.base = SUBREG_REG (parts.base);
16402 if (parts.index && GET_CODE (parts.index) == SUBREG)
16403 parts.index = SUBREG_REG (parts.index);
16406 index = parts.index;
16411 - esp as the base always wants an index,
16412 - ebp as the base always wants a displacement. */
16414 /* Register Indirect. */
16415 if (base && !index && !disp)
16417 /* esp (for its index) and ebp (for its displacement) need
16418 the two-byte modrm form. */
16419 if (addr == stack_pointer_rtx
16420 || addr == arg_pointer_rtx
16421 || addr == frame_pointer_rtx
16422 || addr == hard_frame_pointer_rtx)
16426 /* Direct Addressing. */
16427 else if (disp && !base && !index)
16432 /* Find the length of the displacement constant. */
16435 if (base && satisfies_constraint_K (disp))
16440 /* ebp always wants a displacement. */
16441 else if (base == hard_frame_pointer_rtx)
16444 /* An index requires the two-byte modrm form.... */
16446 /* ...like esp, which always wants an index. */
16447 || base == stack_pointer_rtx
16448 || base == arg_pointer_rtx
16449 || base == frame_pointer_rtx)
16456 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16457 is set, expect that insn have 8bit immediate alternative. */
16459 ix86_attr_length_immediate_default (rtx insn, int shortform)
16463 extract_insn_cached (insn);
16464 for (i = recog_data.n_operands - 1; i >= 0; --i)
16465 if (CONSTANT_P (recog_data.operand[i]))
16468 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16472 switch (get_attr_mode (insn))
16483 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16488 fatal_insn ("unknown insn mode", insn);
16494 /* Compute default value for "length_address" attribute. */
16496 ix86_attr_length_address_default (rtx insn)
16500 if (get_attr_type (insn) == TYPE_LEA)
16502 rtx set = PATTERN (insn);
16504 if (GET_CODE (set) == PARALLEL)
16505 set = XVECEXP (set, 0, 0);
16507 gcc_assert (GET_CODE (set) == SET);
16509 return memory_address_length (SET_SRC (set));
16512 extract_insn_cached (insn);
16513 for (i = recog_data.n_operands - 1; i >= 0; --i)
16514 if (MEM_P (recog_data.operand[i]))
16516 return memory_address_length (XEXP (recog_data.operand[i], 0));
16522 /* Return the maximum number of instructions a cpu can issue. */
16525 ix86_issue_rate (void)
16529 case PROCESSOR_PENTIUM:
16533 case PROCESSOR_PENTIUMPRO:
16534 case PROCESSOR_PENTIUM4:
16535 case PROCESSOR_ATHLON:
16537 case PROCESSOR_AMDFAM10:
16538 case PROCESSOR_NOCONA:
16539 case PROCESSOR_GENERIC32:
16540 case PROCESSOR_GENERIC64:
16543 case PROCESSOR_CORE2:
16551 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16552 by DEP_INSN and nothing set by DEP_INSN. */
16555 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16559 /* Simplify the test for uninteresting insns. */
16560 if (insn_type != TYPE_SETCC
16561 && insn_type != TYPE_ICMOV
16562 && insn_type != TYPE_FCMOV
16563 && insn_type != TYPE_IBR)
16566 if ((set = single_set (dep_insn)) != 0)
16568 set = SET_DEST (set);
16571 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16572 && XVECLEN (PATTERN (dep_insn), 0) == 2
16573 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16574 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16576 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16577 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16582 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16585 /* This test is true if the dependent insn reads the flags but
16586 not any other potentially set register. */
16587 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16590 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16596 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16597 address with operands set by DEP_INSN. */
16600 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16604 if (insn_type == TYPE_LEA
16607 addr = PATTERN (insn);
16609 if (GET_CODE (addr) == PARALLEL)
16610 addr = XVECEXP (addr, 0, 0);
16612 gcc_assert (GET_CODE (addr) == SET);
16614 addr = SET_SRC (addr);
16619 extract_insn_cached (insn);
16620 for (i = recog_data.n_operands - 1; i >= 0; --i)
16621 if (MEM_P (recog_data.operand[i]))
16623 addr = XEXP (recog_data.operand[i], 0);
16630 return modified_in_p (addr, dep_insn);
16634 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16636 enum attr_type insn_type, dep_insn_type;
16637 enum attr_memory memory;
16639 int dep_insn_code_number;
16641 /* Anti and output dependencies have zero cost on all CPUs. */
16642 if (REG_NOTE_KIND (link) != 0)
16645 dep_insn_code_number = recog_memoized (dep_insn);
16647 /* If we can't recognize the insns, we can't really do anything. */
16648 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16651 insn_type = get_attr_type (insn);
16652 dep_insn_type = get_attr_type (dep_insn);
16656 case PROCESSOR_PENTIUM:
16657 /* Address Generation Interlock adds a cycle of latency. */
16658 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16661 /* ??? Compares pair with jump/setcc. */
16662 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16665 /* Floating point stores require value to be ready one cycle earlier. */
16666 if (insn_type == TYPE_FMOV
16667 && get_attr_memory (insn) == MEMORY_STORE
16668 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16672 case PROCESSOR_PENTIUMPRO:
16673 memory = get_attr_memory (insn);
16675 /* INT->FP conversion is expensive. */
16676 if (get_attr_fp_int_src (dep_insn))
16679 /* There is one cycle extra latency between an FP op and a store. */
16680 if (insn_type == TYPE_FMOV
16681 && (set = single_set (dep_insn)) != NULL_RTX
16682 && (set2 = single_set (insn)) != NULL_RTX
16683 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16684 && MEM_P (SET_DEST (set2)))
16687 /* Show ability of reorder buffer to hide latency of load by executing
16688 in parallel with previous instruction in case
16689 previous instruction is not needed to compute the address. */
16690 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16691 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16693 /* Claim moves to take one cycle, as core can issue one load
16694 at time and the next load can start cycle later. */
16695 if (dep_insn_type == TYPE_IMOV
16696 || dep_insn_type == TYPE_FMOV)
16704 memory = get_attr_memory (insn);
16706 /* The esp dependency is resolved before the instruction is really
16708 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16709 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16712 /* INT->FP conversion is expensive. */
16713 if (get_attr_fp_int_src (dep_insn))
16716 /* Show ability of reorder buffer to hide latency of load by executing
16717 in parallel with previous instruction in case
16718 previous instruction is not needed to compute the address. */
16719 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16720 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16722 /* Claim moves to take one cycle, as core can issue one load
16723 at time and the next load can start cycle later. */
16724 if (dep_insn_type == TYPE_IMOV
16725 || dep_insn_type == TYPE_FMOV)
16734 case PROCESSOR_ATHLON:
16736 case PROCESSOR_AMDFAM10:
16737 case PROCESSOR_GENERIC32:
16738 case PROCESSOR_GENERIC64:
16739 memory = get_attr_memory (insn);
16741 /* Show ability of reorder buffer to hide latency of load by executing
16742 in parallel with previous instruction in case
16743 previous instruction is not needed to compute the address. */
16744 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16745 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16747 enum attr_unit unit = get_attr_unit (insn);
16750 /* Because of the difference between the length of integer and
16751 floating unit pipeline preparation stages, the memory operands
16752 for floating point are cheaper.
16754 ??? For Athlon it the difference is most probably 2. */
16755 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16758 loadcost = TARGET_ATHLON ? 2 : 0;
16760 if (cost >= loadcost)
16773 /* How many alternative schedules to try. This should be as wide as the
16774 scheduling freedom in the DFA, but no wider. Making this value too
16775 large results extra work for the scheduler. */
16778 ia32_multipass_dfa_lookahead (void)
16782 case PROCESSOR_PENTIUM:
16785 case PROCESSOR_PENTIUMPRO:
16795 /* Compute the alignment given to a constant that is being placed in memory.
16796 EXP is the constant and ALIGN is the alignment that the object would
16798 The value of this function is used instead of that alignment to align
16802 ix86_constant_alignment (tree exp, int align)
16804 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
16805 || TREE_CODE (exp) == INTEGER_CST)
16807 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16809 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16812 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16813 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16814 return BITS_PER_WORD;
16819 /* Compute the alignment for a static variable.
16820 TYPE is the data type, and ALIGN is the alignment that
16821 the object would ordinarily have. The value of this function is used
16822 instead of that alignment to align the object. */
16825 ix86_data_alignment (tree type, int align)
16827 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16829 if (AGGREGATE_TYPE_P (type)
16830 && TYPE_SIZE (type)
16831 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16832 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16833 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16834 && align < max_align)
16837 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16838 to 16byte boundary. */
16841 if (AGGREGATE_TYPE_P (type)
16842 && TYPE_SIZE (type)
16843 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16844 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16845 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16849 if (TREE_CODE (type) == ARRAY_TYPE)
16851 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16853 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16856 else if (TREE_CODE (type) == COMPLEX_TYPE)
16859 if (TYPE_MODE (type) == DCmode && align < 64)
16861 if (TYPE_MODE (type) == XCmode && align < 128)
16864 else if ((TREE_CODE (type) == RECORD_TYPE
16865 || TREE_CODE (type) == UNION_TYPE
16866 || TREE_CODE (type) == QUAL_UNION_TYPE)
16867 && TYPE_FIELDS (type))
16869 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16871 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16874 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16875 || TREE_CODE (type) == INTEGER_TYPE)
16877 if (TYPE_MODE (type) == DFmode && align < 64)
16879 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16886 /* Compute the alignment for a local variable.
16887 TYPE is the data type, and ALIGN is the alignment that
16888 the object would ordinarily have. The value of this macro is used
16889 instead of that alignment to align the object. */
16892 ix86_local_alignment (tree type, int align)
16894 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16895 to 16byte boundary. */
16898 if (AGGREGATE_TYPE_P (type)
16899 && TYPE_SIZE (type)
16900 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16901 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16902 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16905 if (TREE_CODE (type) == ARRAY_TYPE)
16907 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16909 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16912 else if (TREE_CODE (type) == COMPLEX_TYPE)
16914 if (TYPE_MODE (type) == DCmode && align < 64)
16916 if (TYPE_MODE (type) == XCmode && align < 128)
16919 else if ((TREE_CODE (type) == RECORD_TYPE
16920 || TREE_CODE (type) == UNION_TYPE
16921 || TREE_CODE (type) == QUAL_UNION_TYPE)
16922 && TYPE_FIELDS (type))
16924 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16926 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16929 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16930 || TREE_CODE (type) == INTEGER_TYPE)
16933 if (TYPE_MODE (type) == DFmode && align < 64)
16935 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16941 /* Emit RTL insns to initialize the variable parts of a trampoline.
16942 FNADDR is an RTX for the address of the function's pure code.
16943 CXT is an RTX for the static chain value for the function. */
16945 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16949 /* Compute offset from the end of the jmp to the target function. */
16950 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16951 plus_constant (tramp, 10),
16952 NULL_RTX, 1, OPTAB_DIRECT);
16953 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16954 gen_int_mode (0xb9, QImode));
16955 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16956 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16957 gen_int_mode (0xe9, QImode));
16958 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16963 /* Try to load address using shorter movl instead of movabs.
16964 We may want to support movq for kernel mode, but kernel does not use
16965 trampolines at the moment. */
16966 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16968 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16969 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16970 gen_int_mode (0xbb41, HImode));
16971 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16972 gen_lowpart (SImode, fnaddr));
16977 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16978 gen_int_mode (0xbb49, HImode));
16979 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16983 /* Load static chain using movabs to r10. */
16984 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16985 gen_int_mode (0xba49, HImode));
16986 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16989 /* Jump to the r11 */
16990 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16991 gen_int_mode (0xff49, HImode));
16992 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16993 gen_int_mode (0xe3, QImode));
16995 gcc_assert (offset <= TRAMPOLINE_SIZE);
16998 #ifdef ENABLE_EXECUTE_STACK
16999 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
17000 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
17004 /* Codes for all the SSE/MMX builtins. */
17007 IX86_BUILTIN_ADDPS,
17008 IX86_BUILTIN_ADDSS,
17009 IX86_BUILTIN_DIVPS,
17010 IX86_BUILTIN_DIVSS,
17011 IX86_BUILTIN_MULPS,
17012 IX86_BUILTIN_MULSS,
17013 IX86_BUILTIN_SUBPS,
17014 IX86_BUILTIN_SUBSS,
17016 IX86_BUILTIN_CMPEQPS,
17017 IX86_BUILTIN_CMPLTPS,
17018 IX86_BUILTIN_CMPLEPS,
17019 IX86_BUILTIN_CMPGTPS,
17020 IX86_BUILTIN_CMPGEPS,
17021 IX86_BUILTIN_CMPNEQPS,
17022 IX86_BUILTIN_CMPNLTPS,
17023 IX86_BUILTIN_CMPNLEPS,
17024 IX86_BUILTIN_CMPNGTPS,
17025 IX86_BUILTIN_CMPNGEPS,
17026 IX86_BUILTIN_CMPORDPS,
17027 IX86_BUILTIN_CMPUNORDPS,
17028 IX86_BUILTIN_CMPEQSS,
17029 IX86_BUILTIN_CMPLTSS,
17030 IX86_BUILTIN_CMPLESS,
17031 IX86_BUILTIN_CMPNEQSS,
17032 IX86_BUILTIN_CMPNLTSS,
17033 IX86_BUILTIN_CMPNLESS,
17034 IX86_BUILTIN_CMPNGTSS,
17035 IX86_BUILTIN_CMPNGESS,
17036 IX86_BUILTIN_CMPORDSS,
17037 IX86_BUILTIN_CMPUNORDSS,
17039 IX86_BUILTIN_COMIEQSS,
17040 IX86_BUILTIN_COMILTSS,
17041 IX86_BUILTIN_COMILESS,
17042 IX86_BUILTIN_COMIGTSS,
17043 IX86_BUILTIN_COMIGESS,
17044 IX86_BUILTIN_COMINEQSS,
17045 IX86_BUILTIN_UCOMIEQSS,
17046 IX86_BUILTIN_UCOMILTSS,
17047 IX86_BUILTIN_UCOMILESS,
17048 IX86_BUILTIN_UCOMIGTSS,
17049 IX86_BUILTIN_UCOMIGESS,
17050 IX86_BUILTIN_UCOMINEQSS,
17052 IX86_BUILTIN_CVTPI2PS,
17053 IX86_BUILTIN_CVTPS2PI,
17054 IX86_BUILTIN_CVTSI2SS,
17055 IX86_BUILTIN_CVTSI642SS,
17056 IX86_BUILTIN_CVTSS2SI,
17057 IX86_BUILTIN_CVTSS2SI64,
17058 IX86_BUILTIN_CVTTPS2PI,
17059 IX86_BUILTIN_CVTTSS2SI,
17060 IX86_BUILTIN_CVTTSS2SI64,
17062 IX86_BUILTIN_MAXPS,
17063 IX86_BUILTIN_MAXSS,
17064 IX86_BUILTIN_MINPS,
17065 IX86_BUILTIN_MINSS,
17067 IX86_BUILTIN_LOADUPS,
17068 IX86_BUILTIN_STOREUPS,
17069 IX86_BUILTIN_MOVSS,
17071 IX86_BUILTIN_MOVHLPS,
17072 IX86_BUILTIN_MOVLHPS,
17073 IX86_BUILTIN_LOADHPS,
17074 IX86_BUILTIN_LOADLPS,
17075 IX86_BUILTIN_STOREHPS,
17076 IX86_BUILTIN_STORELPS,
17078 IX86_BUILTIN_MASKMOVQ,
17079 IX86_BUILTIN_MOVMSKPS,
17080 IX86_BUILTIN_PMOVMSKB,
17082 IX86_BUILTIN_MOVNTPS,
17083 IX86_BUILTIN_MOVNTQ,
17085 IX86_BUILTIN_LOADDQU,
17086 IX86_BUILTIN_STOREDQU,
17088 IX86_BUILTIN_PACKSSWB,
17089 IX86_BUILTIN_PACKSSDW,
17090 IX86_BUILTIN_PACKUSWB,
17092 IX86_BUILTIN_PADDB,
17093 IX86_BUILTIN_PADDW,
17094 IX86_BUILTIN_PADDD,
17095 IX86_BUILTIN_PADDQ,
17096 IX86_BUILTIN_PADDSB,
17097 IX86_BUILTIN_PADDSW,
17098 IX86_BUILTIN_PADDUSB,
17099 IX86_BUILTIN_PADDUSW,
17100 IX86_BUILTIN_PSUBB,
17101 IX86_BUILTIN_PSUBW,
17102 IX86_BUILTIN_PSUBD,
17103 IX86_BUILTIN_PSUBQ,
17104 IX86_BUILTIN_PSUBSB,
17105 IX86_BUILTIN_PSUBSW,
17106 IX86_BUILTIN_PSUBUSB,
17107 IX86_BUILTIN_PSUBUSW,
17110 IX86_BUILTIN_PANDN,
17114 IX86_BUILTIN_PAVGB,
17115 IX86_BUILTIN_PAVGW,
17117 IX86_BUILTIN_PCMPEQB,
17118 IX86_BUILTIN_PCMPEQW,
17119 IX86_BUILTIN_PCMPEQD,
17120 IX86_BUILTIN_PCMPGTB,
17121 IX86_BUILTIN_PCMPGTW,
17122 IX86_BUILTIN_PCMPGTD,
17124 IX86_BUILTIN_PMADDWD,
17126 IX86_BUILTIN_PMAXSW,
17127 IX86_BUILTIN_PMAXUB,
17128 IX86_BUILTIN_PMINSW,
17129 IX86_BUILTIN_PMINUB,
17131 IX86_BUILTIN_PMULHUW,
17132 IX86_BUILTIN_PMULHW,
17133 IX86_BUILTIN_PMULLW,
17135 IX86_BUILTIN_PSADBW,
17136 IX86_BUILTIN_PSHUFW,
17138 IX86_BUILTIN_PSLLW,
17139 IX86_BUILTIN_PSLLD,
17140 IX86_BUILTIN_PSLLQ,
17141 IX86_BUILTIN_PSRAW,
17142 IX86_BUILTIN_PSRAD,
17143 IX86_BUILTIN_PSRLW,
17144 IX86_BUILTIN_PSRLD,
17145 IX86_BUILTIN_PSRLQ,
17146 IX86_BUILTIN_PSLLWI,
17147 IX86_BUILTIN_PSLLDI,
17148 IX86_BUILTIN_PSLLQI,
17149 IX86_BUILTIN_PSRAWI,
17150 IX86_BUILTIN_PSRADI,
17151 IX86_BUILTIN_PSRLWI,
17152 IX86_BUILTIN_PSRLDI,
17153 IX86_BUILTIN_PSRLQI,
17155 IX86_BUILTIN_PUNPCKHBW,
17156 IX86_BUILTIN_PUNPCKHWD,
17157 IX86_BUILTIN_PUNPCKHDQ,
17158 IX86_BUILTIN_PUNPCKLBW,
17159 IX86_BUILTIN_PUNPCKLWD,
17160 IX86_BUILTIN_PUNPCKLDQ,
17162 IX86_BUILTIN_SHUFPS,
17164 IX86_BUILTIN_RCPPS,
17165 IX86_BUILTIN_RCPSS,
17166 IX86_BUILTIN_RSQRTPS,
17167 IX86_BUILTIN_RSQRTPS_NR,
17168 IX86_BUILTIN_RSQRTSS,
17169 IX86_BUILTIN_RSQRTF,
17170 IX86_BUILTIN_SQRTPS,
17171 IX86_BUILTIN_SQRTPS_NR,
17172 IX86_BUILTIN_SQRTSS,
17174 IX86_BUILTIN_UNPCKHPS,
17175 IX86_BUILTIN_UNPCKLPS,
17177 IX86_BUILTIN_ANDPS,
17178 IX86_BUILTIN_ANDNPS,
17180 IX86_BUILTIN_XORPS,
17183 IX86_BUILTIN_LDMXCSR,
17184 IX86_BUILTIN_STMXCSR,
17185 IX86_BUILTIN_SFENCE,
17187 /* 3DNow! Original */
17188 IX86_BUILTIN_FEMMS,
17189 IX86_BUILTIN_PAVGUSB,
17190 IX86_BUILTIN_PF2ID,
17191 IX86_BUILTIN_PFACC,
17192 IX86_BUILTIN_PFADD,
17193 IX86_BUILTIN_PFCMPEQ,
17194 IX86_BUILTIN_PFCMPGE,
17195 IX86_BUILTIN_PFCMPGT,
17196 IX86_BUILTIN_PFMAX,
17197 IX86_BUILTIN_PFMIN,
17198 IX86_BUILTIN_PFMUL,
17199 IX86_BUILTIN_PFRCP,
17200 IX86_BUILTIN_PFRCPIT1,
17201 IX86_BUILTIN_PFRCPIT2,
17202 IX86_BUILTIN_PFRSQIT1,
17203 IX86_BUILTIN_PFRSQRT,
17204 IX86_BUILTIN_PFSUB,
17205 IX86_BUILTIN_PFSUBR,
17206 IX86_BUILTIN_PI2FD,
17207 IX86_BUILTIN_PMULHRW,
17209 /* 3DNow! Athlon Extensions */
17210 IX86_BUILTIN_PF2IW,
17211 IX86_BUILTIN_PFNACC,
17212 IX86_BUILTIN_PFPNACC,
17213 IX86_BUILTIN_PI2FW,
17214 IX86_BUILTIN_PSWAPDSI,
17215 IX86_BUILTIN_PSWAPDSF,
17218 IX86_BUILTIN_ADDPD,
17219 IX86_BUILTIN_ADDSD,
17220 IX86_BUILTIN_DIVPD,
17221 IX86_BUILTIN_DIVSD,
17222 IX86_BUILTIN_MULPD,
17223 IX86_BUILTIN_MULSD,
17224 IX86_BUILTIN_SUBPD,
17225 IX86_BUILTIN_SUBSD,
17227 IX86_BUILTIN_CMPEQPD,
17228 IX86_BUILTIN_CMPLTPD,
17229 IX86_BUILTIN_CMPLEPD,
17230 IX86_BUILTIN_CMPGTPD,
17231 IX86_BUILTIN_CMPGEPD,
17232 IX86_BUILTIN_CMPNEQPD,
17233 IX86_BUILTIN_CMPNLTPD,
17234 IX86_BUILTIN_CMPNLEPD,
17235 IX86_BUILTIN_CMPNGTPD,
17236 IX86_BUILTIN_CMPNGEPD,
17237 IX86_BUILTIN_CMPORDPD,
17238 IX86_BUILTIN_CMPUNORDPD,
17239 IX86_BUILTIN_CMPEQSD,
17240 IX86_BUILTIN_CMPLTSD,
17241 IX86_BUILTIN_CMPLESD,
17242 IX86_BUILTIN_CMPNEQSD,
17243 IX86_BUILTIN_CMPNLTSD,
17244 IX86_BUILTIN_CMPNLESD,
17245 IX86_BUILTIN_CMPORDSD,
17246 IX86_BUILTIN_CMPUNORDSD,
17248 IX86_BUILTIN_COMIEQSD,
17249 IX86_BUILTIN_COMILTSD,
17250 IX86_BUILTIN_COMILESD,
17251 IX86_BUILTIN_COMIGTSD,
17252 IX86_BUILTIN_COMIGESD,
17253 IX86_BUILTIN_COMINEQSD,
17254 IX86_BUILTIN_UCOMIEQSD,
17255 IX86_BUILTIN_UCOMILTSD,
17256 IX86_BUILTIN_UCOMILESD,
17257 IX86_BUILTIN_UCOMIGTSD,
17258 IX86_BUILTIN_UCOMIGESD,
17259 IX86_BUILTIN_UCOMINEQSD,
17261 IX86_BUILTIN_MAXPD,
17262 IX86_BUILTIN_MAXSD,
17263 IX86_BUILTIN_MINPD,
17264 IX86_BUILTIN_MINSD,
17266 IX86_BUILTIN_ANDPD,
17267 IX86_BUILTIN_ANDNPD,
17269 IX86_BUILTIN_XORPD,
17271 IX86_BUILTIN_SQRTPD,
17272 IX86_BUILTIN_SQRTSD,
17274 IX86_BUILTIN_UNPCKHPD,
17275 IX86_BUILTIN_UNPCKLPD,
17277 IX86_BUILTIN_SHUFPD,
17279 IX86_BUILTIN_LOADUPD,
17280 IX86_BUILTIN_STOREUPD,
17281 IX86_BUILTIN_MOVSD,
17283 IX86_BUILTIN_LOADHPD,
17284 IX86_BUILTIN_LOADLPD,
17286 IX86_BUILTIN_CVTDQ2PD,
17287 IX86_BUILTIN_CVTDQ2PS,
17289 IX86_BUILTIN_CVTPD2DQ,
17290 IX86_BUILTIN_CVTPD2PI,
17291 IX86_BUILTIN_CVTPD2PS,
17292 IX86_BUILTIN_CVTTPD2DQ,
17293 IX86_BUILTIN_CVTTPD2PI,
17295 IX86_BUILTIN_CVTPI2PD,
17296 IX86_BUILTIN_CVTSI2SD,
17297 IX86_BUILTIN_CVTSI642SD,
17299 IX86_BUILTIN_CVTSD2SI,
17300 IX86_BUILTIN_CVTSD2SI64,
17301 IX86_BUILTIN_CVTSD2SS,
17302 IX86_BUILTIN_CVTSS2SD,
17303 IX86_BUILTIN_CVTTSD2SI,
17304 IX86_BUILTIN_CVTTSD2SI64,
17306 IX86_BUILTIN_CVTPS2DQ,
17307 IX86_BUILTIN_CVTPS2PD,
17308 IX86_BUILTIN_CVTTPS2DQ,
17310 IX86_BUILTIN_MOVNTI,
17311 IX86_BUILTIN_MOVNTPD,
17312 IX86_BUILTIN_MOVNTDQ,
17315 IX86_BUILTIN_MASKMOVDQU,
17316 IX86_BUILTIN_MOVMSKPD,
17317 IX86_BUILTIN_PMOVMSKB128,
17319 IX86_BUILTIN_PACKSSWB128,
17320 IX86_BUILTIN_PACKSSDW128,
17321 IX86_BUILTIN_PACKUSWB128,
17323 IX86_BUILTIN_PADDB128,
17324 IX86_BUILTIN_PADDW128,
17325 IX86_BUILTIN_PADDD128,
17326 IX86_BUILTIN_PADDQ128,
17327 IX86_BUILTIN_PADDSB128,
17328 IX86_BUILTIN_PADDSW128,
17329 IX86_BUILTIN_PADDUSB128,
17330 IX86_BUILTIN_PADDUSW128,
17331 IX86_BUILTIN_PSUBB128,
17332 IX86_BUILTIN_PSUBW128,
17333 IX86_BUILTIN_PSUBD128,
17334 IX86_BUILTIN_PSUBQ128,
17335 IX86_BUILTIN_PSUBSB128,
17336 IX86_BUILTIN_PSUBSW128,
17337 IX86_BUILTIN_PSUBUSB128,
17338 IX86_BUILTIN_PSUBUSW128,
17340 IX86_BUILTIN_PAND128,
17341 IX86_BUILTIN_PANDN128,
17342 IX86_BUILTIN_POR128,
17343 IX86_BUILTIN_PXOR128,
17345 IX86_BUILTIN_PAVGB128,
17346 IX86_BUILTIN_PAVGW128,
17348 IX86_BUILTIN_PCMPEQB128,
17349 IX86_BUILTIN_PCMPEQW128,
17350 IX86_BUILTIN_PCMPEQD128,
17351 IX86_BUILTIN_PCMPGTB128,
17352 IX86_BUILTIN_PCMPGTW128,
17353 IX86_BUILTIN_PCMPGTD128,
17355 IX86_BUILTIN_PMADDWD128,
17357 IX86_BUILTIN_PMAXSW128,
17358 IX86_BUILTIN_PMAXUB128,
17359 IX86_BUILTIN_PMINSW128,
17360 IX86_BUILTIN_PMINUB128,
17362 IX86_BUILTIN_PMULUDQ,
17363 IX86_BUILTIN_PMULUDQ128,
17364 IX86_BUILTIN_PMULHUW128,
17365 IX86_BUILTIN_PMULHW128,
17366 IX86_BUILTIN_PMULLW128,
17368 IX86_BUILTIN_PSADBW128,
17369 IX86_BUILTIN_PSHUFHW,
17370 IX86_BUILTIN_PSHUFLW,
17371 IX86_BUILTIN_PSHUFD,
17373 IX86_BUILTIN_PSLLDQI128,
17374 IX86_BUILTIN_PSLLWI128,
17375 IX86_BUILTIN_PSLLDI128,
17376 IX86_BUILTIN_PSLLQI128,
17377 IX86_BUILTIN_PSRAWI128,
17378 IX86_BUILTIN_PSRADI128,
17379 IX86_BUILTIN_PSRLDQI128,
17380 IX86_BUILTIN_PSRLWI128,
17381 IX86_BUILTIN_PSRLDI128,
17382 IX86_BUILTIN_PSRLQI128,
17384 IX86_BUILTIN_PSLLDQ128,
17385 IX86_BUILTIN_PSLLW128,
17386 IX86_BUILTIN_PSLLD128,
17387 IX86_BUILTIN_PSLLQ128,
17388 IX86_BUILTIN_PSRAW128,
17389 IX86_BUILTIN_PSRAD128,
17390 IX86_BUILTIN_PSRLW128,
17391 IX86_BUILTIN_PSRLD128,
17392 IX86_BUILTIN_PSRLQ128,
17394 IX86_BUILTIN_PUNPCKHBW128,
17395 IX86_BUILTIN_PUNPCKHWD128,
17396 IX86_BUILTIN_PUNPCKHDQ128,
17397 IX86_BUILTIN_PUNPCKHQDQ128,
17398 IX86_BUILTIN_PUNPCKLBW128,
17399 IX86_BUILTIN_PUNPCKLWD128,
17400 IX86_BUILTIN_PUNPCKLDQ128,
17401 IX86_BUILTIN_PUNPCKLQDQ128,
17403 IX86_BUILTIN_CLFLUSH,
17404 IX86_BUILTIN_MFENCE,
17405 IX86_BUILTIN_LFENCE,
17407 /* Prescott New Instructions. */
17408 IX86_BUILTIN_ADDSUBPS,
17409 IX86_BUILTIN_HADDPS,
17410 IX86_BUILTIN_HSUBPS,
17411 IX86_BUILTIN_MOVSHDUP,
17412 IX86_BUILTIN_MOVSLDUP,
17413 IX86_BUILTIN_ADDSUBPD,
17414 IX86_BUILTIN_HADDPD,
17415 IX86_BUILTIN_HSUBPD,
17416 IX86_BUILTIN_LDDQU,
17418 IX86_BUILTIN_MONITOR,
17419 IX86_BUILTIN_MWAIT,
17422 IX86_BUILTIN_PHADDW,
17423 IX86_BUILTIN_PHADDD,
17424 IX86_BUILTIN_PHADDSW,
17425 IX86_BUILTIN_PHSUBW,
17426 IX86_BUILTIN_PHSUBD,
17427 IX86_BUILTIN_PHSUBSW,
17428 IX86_BUILTIN_PMADDUBSW,
17429 IX86_BUILTIN_PMULHRSW,
17430 IX86_BUILTIN_PSHUFB,
17431 IX86_BUILTIN_PSIGNB,
17432 IX86_BUILTIN_PSIGNW,
17433 IX86_BUILTIN_PSIGND,
17434 IX86_BUILTIN_PALIGNR,
17435 IX86_BUILTIN_PABSB,
17436 IX86_BUILTIN_PABSW,
17437 IX86_BUILTIN_PABSD,
17439 IX86_BUILTIN_PHADDW128,
17440 IX86_BUILTIN_PHADDD128,
17441 IX86_BUILTIN_PHADDSW128,
17442 IX86_BUILTIN_PHSUBW128,
17443 IX86_BUILTIN_PHSUBD128,
17444 IX86_BUILTIN_PHSUBSW128,
17445 IX86_BUILTIN_PMADDUBSW128,
17446 IX86_BUILTIN_PMULHRSW128,
17447 IX86_BUILTIN_PSHUFB128,
17448 IX86_BUILTIN_PSIGNB128,
17449 IX86_BUILTIN_PSIGNW128,
17450 IX86_BUILTIN_PSIGND128,
17451 IX86_BUILTIN_PALIGNR128,
17452 IX86_BUILTIN_PABSB128,
17453 IX86_BUILTIN_PABSW128,
17454 IX86_BUILTIN_PABSD128,
17456 /* AMDFAM10 - SSE4A New Instructions. */
17457 IX86_BUILTIN_MOVNTSD,
17458 IX86_BUILTIN_MOVNTSS,
17459 IX86_BUILTIN_EXTRQI,
17460 IX86_BUILTIN_EXTRQ,
17461 IX86_BUILTIN_INSERTQI,
17462 IX86_BUILTIN_INSERTQ,
17465 IX86_BUILTIN_BLENDPD,
17466 IX86_BUILTIN_BLENDPS,
17467 IX86_BUILTIN_BLENDVPD,
17468 IX86_BUILTIN_BLENDVPS,
17469 IX86_BUILTIN_PBLENDVB128,
17470 IX86_BUILTIN_PBLENDW128,
17475 IX86_BUILTIN_INSERTPS128,
17477 IX86_BUILTIN_MOVNTDQA,
17478 IX86_BUILTIN_MPSADBW128,
17479 IX86_BUILTIN_PACKUSDW128,
17480 IX86_BUILTIN_PCMPEQQ,
17481 IX86_BUILTIN_PHMINPOSUW128,
17483 IX86_BUILTIN_PMAXSB128,
17484 IX86_BUILTIN_PMAXSD128,
17485 IX86_BUILTIN_PMAXUD128,
17486 IX86_BUILTIN_PMAXUW128,
17488 IX86_BUILTIN_PMINSB128,
17489 IX86_BUILTIN_PMINSD128,
17490 IX86_BUILTIN_PMINUD128,
17491 IX86_BUILTIN_PMINUW128,
17493 IX86_BUILTIN_PMOVSXBW128,
17494 IX86_BUILTIN_PMOVSXBD128,
17495 IX86_BUILTIN_PMOVSXBQ128,
17496 IX86_BUILTIN_PMOVSXWD128,
17497 IX86_BUILTIN_PMOVSXWQ128,
17498 IX86_BUILTIN_PMOVSXDQ128,
17500 IX86_BUILTIN_PMOVZXBW128,
17501 IX86_BUILTIN_PMOVZXBD128,
17502 IX86_BUILTIN_PMOVZXBQ128,
17503 IX86_BUILTIN_PMOVZXWD128,
17504 IX86_BUILTIN_PMOVZXWQ128,
17505 IX86_BUILTIN_PMOVZXDQ128,
17507 IX86_BUILTIN_PMULDQ128,
17508 IX86_BUILTIN_PMULLD128,
17510 IX86_BUILTIN_ROUNDPD,
17511 IX86_BUILTIN_ROUNDPS,
17512 IX86_BUILTIN_ROUNDSD,
17513 IX86_BUILTIN_ROUNDSS,
17515 IX86_BUILTIN_PTESTZ,
17516 IX86_BUILTIN_PTESTC,
17517 IX86_BUILTIN_PTESTNZC,
17519 IX86_BUILTIN_VEC_INIT_V2SI,
17520 IX86_BUILTIN_VEC_INIT_V4HI,
17521 IX86_BUILTIN_VEC_INIT_V8QI,
17522 IX86_BUILTIN_VEC_EXT_V2DF,
17523 IX86_BUILTIN_VEC_EXT_V2DI,
17524 IX86_BUILTIN_VEC_EXT_V4SF,
17525 IX86_BUILTIN_VEC_EXT_V4SI,
17526 IX86_BUILTIN_VEC_EXT_V8HI,
17527 IX86_BUILTIN_VEC_EXT_V2SI,
17528 IX86_BUILTIN_VEC_EXT_V4HI,
17529 IX86_BUILTIN_VEC_EXT_V16QI,
17530 IX86_BUILTIN_VEC_SET_V2DI,
17531 IX86_BUILTIN_VEC_SET_V4SF,
17532 IX86_BUILTIN_VEC_SET_V4SI,
17533 IX86_BUILTIN_VEC_SET_V8HI,
17534 IX86_BUILTIN_VEC_SET_V4HI,
17535 IX86_BUILTIN_VEC_SET_V16QI,
17537 IX86_BUILTIN_VEC_PACK_SFIX,
17540 IX86_BUILTIN_CRC32QI,
17541 IX86_BUILTIN_CRC32HI,
17542 IX86_BUILTIN_CRC32SI,
17543 IX86_BUILTIN_CRC32DI,
17545 IX86_BUILTIN_PCMPESTRI128,
17546 IX86_BUILTIN_PCMPESTRM128,
17547 IX86_BUILTIN_PCMPESTRA128,
17548 IX86_BUILTIN_PCMPESTRC128,
17549 IX86_BUILTIN_PCMPESTRO128,
17550 IX86_BUILTIN_PCMPESTRS128,
17551 IX86_BUILTIN_PCMPESTRZ128,
17552 IX86_BUILTIN_PCMPISTRI128,
17553 IX86_BUILTIN_PCMPISTRM128,
17554 IX86_BUILTIN_PCMPISTRA128,
17555 IX86_BUILTIN_PCMPISTRC128,
17556 IX86_BUILTIN_PCMPISTRO128,
17557 IX86_BUILTIN_PCMPISTRS128,
17558 IX86_BUILTIN_PCMPISTRZ128,
17560 IX86_BUILTIN_PCMPGTQ,
17562 /* TFmode support builtins. */
17564 IX86_BUILTIN_FABSQ,
17565 IX86_BUILTIN_COPYSIGNQ,
17567 /* SSE5 instructions */
17568 IX86_BUILTIN_FMADDSS,
17569 IX86_BUILTIN_FMADDSD,
17570 IX86_BUILTIN_FMADDPS,
17571 IX86_BUILTIN_FMADDPD,
17572 IX86_BUILTIN_FMSUBSS,
17573 IX86_BUILTIN_FMSUBSD,
17574 IX86_BUILTIN_FMSUBPS,
17575 IX86_BUILTIN_FMSUBPD,
17576 IX86_BUILTIN_FNMADDSS,
17577 IX86_BUILTIN_FNMADDSD,
17578 IX86_BUILTIN_FNMADDPS,
17579 IX86_BUILTIN_FNMADDPD,
17580 IX86_BUILTIN_FNMSUBSS,
17581 IX86_BUILTIN_FNMSUBSD,
17582 IX86_BUILTIN_FNMSUBPS,
17583 IX86_BUILTIN_FNMSUBPD,
17584 IX86_BUILTIN_PCMOV_V2DI,
17585 IX86_BUILTIN_PCMOV_V4SI,
17586 IX86_BUILTIN_PCMOV_V8HI,
17587 IX86_BUILTIN_PCMOV_V16QI,
17588 IX86_BUILTIN_PCMOV_V4SF,
17589 IX86_BUILTIN_PCMOV_V2DF,
17590 IX86_BUILTIN_PPERM,
17591 IX86_BUILTIN_PERMPS,
17592 IX86_BUILTIN_PERMPD,
17593 IX86_BUILTIN_PMACSSWW,
17594 IX86_BUILTIN_PMACSWW,
17595 IX86_BUILTIN_PMACSSWD,
17596 IX86_BUILTIN_PMACSWD,
17597 IX86_BUILTIN_PMACSSDD,
17598 IX86_BUILTIN_PMACSDD,
17599 IX86_BUILTIN_PMACSSDQL,
17600 IX86_BUILTIN_PMACSSDQH,
17601 IX86_BUILTIN_PMACSDQL,
17602 IX86_BUILTIN_PMACSDQH,
17603 IX86_BUILTIN_PMADCSSWD,
17604 IX86_BUILTIN_PMADCSWD,
17605 IX86_BUILTIN_PHADDBW,
17606 IX86_BUILTIN_PHADDBD,
17607 IX86_BUILTIN_PHADDBQ,
17608 IX86_BUILTIN_PHADDWD,
17609 IX86_BUILTIN_PHADDWQ,
17610 IX86_BUILTIN_PHADDDQ,
17611 IX86_BUILTIN_PHADDUBW,
17612 IX86_BUILTIN_PHADDUBD,
17613 IX86_BUILTIN_PHADDUBQ,
17614 IX86_BUILTIN_PHADDUWD,
17615 IX86_BUILTIN_PHADDUWQ,
17616 IX86_BUILTIN_PHADDUDQ,
17617 IX86_BUILTIN_PHSUBBW,
17618 IX86_BUILTIN_PHSUBWD,
17619 IX86_BUILTIN_PHSUBDQ,
17620 IX86_BUILTIN_PROTB,
17621 IX86_BUILTIN_PROTW,
17622 IX86_BUILTIN_PROTD,
17623 IX86_BUILTIN_PROTQ,
17624 IX86_BUILTIN_PROTB_IMM,
17625 IX86_BUILTIN_PROTW_IMM,
17626 IX86_BUILTIN_PROTD_IMM,
17627 IX86_BUILTIN_PROTQ_IMM,
17628 IX86_BUILTIN_PSHLB,
17629 IX86_BUILTIN_PSHLW,
17630 IX86_BUILTIN_PSHLD,
17631 IX86_BUILTIN_PSHLQ,
17632 IX86_BUILTIN_PSHAB,
17633 IX86_BUILTIN_PSHAW,
17634 IX86_BUILTIN_PSHAD,
17635 IX86_BUILTIN_PSHAQ,
17636 IX86_BUILTIN_FRCZSS,
17637 IX86_BUILTIN_FRCZSD,
17638 IX86_BUILTIN_FRCZPS,
17639 IX86_BUILTIN_FRCZPD,
17640 IX86_BUILTIN_CVTPH2PS,
17641 IX86_BUILTIN_CVTPS2PH,
17643 IX86_BUILTIN_COMEQSS,
17644 IX86_BUILTIN_COMNESS,
17645 IX86_BUILTIN_COMLTSS,
17646 IX86_BUILTIN_COMLESS,
17647 IX86_BUILTIN_COMGTSS,
17648 IX86_BUILTIN_COMGESS,
17649 IX86_BUILTIN_COMUEQSS,
17650 IX86_BUILTIN_COMUNESS,
17651 IX86_BUILTIN_COMULTSS,
17652 IX86_BUILTIN_COMULESS,
17653 IX86_BUILTIN_COMUGTSS,
17654 IX86_BUILTIN_COMUGESS,
17655 IX86_BUILTIN_COMORDSS,
17656 IX86_BUILTIN_COMUNORDSS,
17657 IX86_BUILTIN_COMFALSESS,
17658 IX86_BUILTIN_COMTRUESS,
17660 IX86_BUILTIN_COMEQSD,
17661 IX86_BUILTIN_COMNESD,
17662 IX86_BUILTIN_COMLTSD,
17663 IX86_BUILTIN_COMLESD,
17664 IX86_BUILTIN_COMGTSD,
17665 IX86_BUILTIN_COMGESD,
17666 IX86_BUILTIN_COMUEQSD,
17667 IX86_BUILTIN_COMUNESD,
17668 IX86_BUILTIN_COMULTSD,
17669 IX86_BUILTIN_COMULESD,
17670 IX86_BUILTIN_COMUGTSD,
17671 IX86_BUILTIN_COMUGESD,
17672 IX86_BUILTIN_COMORDSD,
17673 IX86_BUILTIN_COMUNORDSD,
17674 IX86_BUILTIN_COMFALSESD,
17675 IX86_BUILTIN_COMTRUESD,
17677 IX86_BUILTIN_COMEQPS,
17678 IX86_BUILTIN_COMNEPS,
17679 IX86_BUILTIN_COMLTPS,
17680 IX86_BUILTIN_COMLEPS,
17681 IX86_BUILTIN_COMGTPS,
17682 IX86_BUILTIN_COMGEPS,
17683 IX86_BUILTIN_COMUEQPS,
17684 IX86_BUILTIN_COMUNEPS,
17685 IX86_BUILTIN_COMULTPS,
17686 IX86_BUILTIN_COMULEPS,
17687 IX86_BUILTIN_COMUGTPS,
17688 IX86_BUILTIN_COMUGEPS,
17689 IX86_BUILTIN_COMORDPS,
17690 IX86_BUILTIN_COMUNORDPS,
17691 IX86_BUILTIN_COMFALSEPS,
17692 IX86_BUILTIN_COMTRUEPS,
17694 IX86_BUILTIN_COMEQPD,
17695 IX86_BUILTIN_COMNEPD,
17696 IX86_BUILTIN_COMLTPD,
17697 IX86_BUILTIN_COMLEPD,
17698 IX86_BUILTIN_COMGTPD,
17699 IX86_BUILTIN_COMGEPD,
17700 IX86_BUILTIN_COMUEQPD,
17701 IX86_BUILTIN_COMUNEPD,
17702 IX86_BUILTIN_COMULTPD,
17703 IX86_BUILTIN_COMULEPD,
17704 IX86_BUILTIN_COMUGTPD,
17705 IX86_BUILTIN_COMUGEPD,
17706 IX86_BUILTIN_COMORDPD,
17707 IX86_BUILTIN_COMUNORDPD,
17708 IX86_BUILTIN_COMFALSEPD,
17709 IX86_BUILTIN_COMTRUEPD,
17711 IX86_BUILTIN_PCOMEQUB,
17712 IX86_BUILTIN_PCOMNEUB,
17713 IX86_BUILTIN_PCOMLTUB,
17714 IX86_BUILTIN_PCOMLEUB,
17715 IX86_BUILTIN_PCOMGTUB,
17716 IX86_BUILTIN_PCOMGEUB,
17717 IX86_BUILTIN_PCOMFALSEUB,
17718 IX86_BUILTIN_PCOMTRUEUB,
17719 IX86_BUILTIN_PCOMEQUW,
17720 IX86_BUILTIN_PCOMNEUW,
17721 IX86_BUILTIN_PCOMLTUW,
17722 IX86_BUILTIN_PCOMLEUW,
17723 IX86_BUILTIN_PCOMGTUW,
17724 IX86_BUILTIN_PCOMGEUW,
17725 IX86_BUILTIN_PCOMFALSEUW,
17726 IX86_BUILTIN_PCOMTRUEUW,
17727 IX86_BUILTIN_PCOMEQUD,
17728 IX86_BUILTIN_PCOMNEUD,
17729 IX86_BUILTIN_PCOMLTUD,
17730 IX86_BUILTIN_PCOMLEUD,
17731 IX86_BUILTIN_PCOMGTUD,
17732 IX86_BUILTIN_PCOMGEUD,
17733 IX86_BUILTIN_PCOMFALSEUD,
17734 IX86_BUILTIN_PCOMTRUEUD,
17735 IX86_BUILTIN_PCOMEQUQ,
17736 IX86_BUILTIN_PCOMNEUQ,
17737 IX86_BUILTIN_PCOMLTUQ,
17738 IX86_BUILTIN_PCOMLEUQ,
17739 IX86_BUILTIN_PCOMGTUQ,
17740 IX86_BUILTIN_PCOMGEUQ,
17741 IX86_BUILTIN_PCOMFALSEUQ,
17742 IX86_BUILTIN_PCOMTRUEUQ,
17744 IX86_BUILTIN_PCOMEQB,
17745 IX86_BUILTIN_PCOMNEB,
17746 IX86_BUILTIN_PCOMLTB,
17747 IX86_BUILTIN_PCOMLEB,
17748 IX86_BUILTIN_PCOMGTB,
17749 IX86_BUILTIN_PCOMGEB,
17750 IX86_BUILTIN_PCOMFALSEB,
17751 IX86_BUILTIN_PCOMTRUEB,
17752 IX86_BUILTIN_PCOMEQW,
17753 IX86_BUILTIN_PCOMNEW,
17754 IX86_BUILTIN_PCOMLTW,
17755 IX86_BUILTIN_PCOMLEW,
17756 IX86_BUILTIN_PCOMGTW,
17757 IX86_BUILTIN_PCOMGEW,
17758 IX86_BUILTIN_PCOMFALSEW,
17759 IX86_BUILTIN_PCOMTRUEW,
17760 IX86_BUILTIN_PCOMEQD,
17761 IX86_BUILTIN_PCOMNED,
17762 IX86_BUILTIN_PCOMLTD,
17763 IX86_BUILTIN_PCOMLED,
17764 IX86_BUILTIN_PCOMGTD,
17765 IX86_BUILTIN_PCOMGED,
17766 IX86_BUILTIN_PCOMFALSED,
17767 IX86_BUILTIN_PCOMTRUED,
17768 IX86_BUILTIN_PCOMEQQ,
17769 IX86_BUILTIN_PCOMNEQ,
17770 IX86_BUILTIN_PCOMLTQ,
17771 IX86_BUILTIN_PCOMLEQ,
17772 IX86_BUILTIN_PCOMGTQ,
17773 IX86_BUILTIN_PCOMGEQ,
17774 IX86_BUILTIN_PCOMFALSEQ,
17775 IX86_BUILTIN_PCOMTRUEQ,
17780 /* Table for the ix86 builtin decls. */
17781 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17783 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17784 * if the target_flags include one of MASK. Stores the function decl
17785 * in the ix86_builtins array.
17786 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17789 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17791 tree decl = NULL_TREE;
17793 if (mask & ix86_isa_flags
17794 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17796 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17798 ix86_builtins[(int) code] = decl;
17804 /* Like def_builtin, but also marks the function decl "const". */
17807 def_builtin_const (int mask, const char *name, tree type,
17808 enum ix86_builtins code)
17810 tree decl = def_builtin (mask, name, type, code);
17812 TREE_READONLY (decl) = 1;
17816 /* Bits for builtin_description.flag. */
17818 /* Set when we don't support the comparison natively, and should
17819 swap_comparison in order to support it. */
17820 #define BUILTIN_DESC_SWAP_OPERANDS 1
17822 struct builtin_description
17824 const unsigned int mask;
17825 const enum insn_code icode;
17826 const char *const name;
17827 const enum ix86_builtins code;
17828 const enum rtx_code comparison;
17832 static const struct builtin_description bdesc_comi[] =
17834 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17835 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17836 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17837 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17838 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17839 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17840 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17841 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17842 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17843 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17844 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17845 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17860 static const struct builtin_description bdesc_ptest[] =
17863 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
17864 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
17865 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
17868 static const struct builtin_description bdesc_pcmpestr[] =
17871 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
17872 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
17873 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
17874 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
17875 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
17876 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
17877 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
17880 static const struct builtin_description bdesc_pcmpistr[] =
17883 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
17884 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
17885 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
17886 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
17887 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
17888 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
17889 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
17892 static const struct builtin_description bdesc_crc32[] =
17895 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
17896 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
17897 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
17898 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
17901 /* SSE builtins with 3 arguments and the last argument must be an immediate or xmm0. */
17902 static const struct builtin_description bdesc_sse_3arg[] =
17905 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, 0 },
17906 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, 0 },
17907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, 0 },
17908 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, 0 },
17909 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, 0 },
17910 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, 0 },
17911 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, 0 },
17912 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, 0 },
17913 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, 0 },
17914 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, 0 },
17915 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, UNKNOWN, 0 },
17916 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, UNKNOWN, 0 },
17919 static const struct builtin_description bdesc_2arg[] =
17922 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
17923 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
17924 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
17925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
17926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
17927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
17928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
17929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
17931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
17932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
17933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
17934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
17935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
17936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
17937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
17938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
17939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
17940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17942 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
17943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
17944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
17945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
17946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
17947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
17948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
17949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
17950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
17954 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
17955 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
17956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
17957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
17959 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
17960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
17961 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
17962 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
17964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
17965 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
17966 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
17967 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
17968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
17971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
17972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
17973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
17974 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
17975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
17976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
17977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
17978 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
17980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
17981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
17982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
17983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
17984 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
17985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
17986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
17987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
17989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
17990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
17991 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
17993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
17994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
17995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
17996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
17998 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
17999 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
18001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
18002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
18003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
18004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
18005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
18006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
18008 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
18009 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
18010 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
18011 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
18013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
18014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
18015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
18016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
18017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
18018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
18021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
18022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
18023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
18025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
18026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
18027 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
18029 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
18030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
18033 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
18034 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
18035 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
18036 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
18037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
18038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
18039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
18040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
18042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
18043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
18044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
18045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
18046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
18047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
18048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
18049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
18050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
18051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
18054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
18055 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
18056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
18057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
18058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
18059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
18060 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
18061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
18063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
18064 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
18065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
18066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
18068 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
18069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
18070 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
18071 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
18073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
18074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
18075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
18077 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, 0 },
18080 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
18081 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
18082 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
18083 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
18084 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
18085 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
18086 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
18087 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
18089 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
18090 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
18091 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
18092 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
18093 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
18094 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
18095 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
18096 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
18098 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
18099 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
18101 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
18102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
18103 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
18104 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
18106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
18107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
18109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
18110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
18111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
18112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
18113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
18114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
18116 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
18117 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
18118 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
18119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
18121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
18122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
18123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
18124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
18125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
18126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
18127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
18128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
18130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
18131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
18132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
18134 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
18135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
18137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
18138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
18140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
18142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
18143 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
18144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
18145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
18148 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
18149 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
18150 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
18151 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
18152 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
18153 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
18156 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
18157 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
18158 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
18159 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
18160 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
18161 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
18162 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
18163 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
18164 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
18165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
18166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
18167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
18168 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
18169 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
18170 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
18171 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
18172 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
18173 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
18174 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
18175 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
18176 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
18177 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
18178 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
18179 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
18182 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
18183 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
18184 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
18185 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
18186 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
18187 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
18188 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
18189 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
18190 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
18191 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
18192 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
18193 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
18196 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
18199 static const struct builtin_description bdesc_1arg[] =
18202 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
18203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
18205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
18206 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS_NR, UNKNOWN, 0 },
18207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
18208 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, 0 },
18209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
18211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
18212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, UNKNOWN, 0 },
18213 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, UNKNOWN, 0 },
18214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, UNKNOWN, 0 },
18215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, UNKNOWN, 0 },
18216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, 0 },
18219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, UNKNOWN, 0 },
18220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, UNKNOWN, 0 },
18222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, UNKNOWN, 0 },
18224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, UNKNOWN, 0 },
18225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, UNKNOWN, 0 },
18227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, UNKNOWN, 0 },
18228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, UNKNOWN, 0 },
18229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, UNKNOWN, 0 },
18230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, 0 },
18231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, UNKNOWN, 0 },
18233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, UNKNOWN, 0 },
18235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, UNKNOWN, 0 },
18236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, UNKNOWN, 0 },
18237 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, UNKNOWN, 0 },
18238 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, 0 },
18240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, UNKNOWN, 0 },
18241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, UNKNOWN, 0 },
18242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, 0 },
18245 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, 0 },
18246 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, 0 },
18249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, 0 },
18250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, 0 },
18251 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, 0 },
18252 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, 0 },
18253 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, 0 },
18254 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, 0 },
18257 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, UNKNOWN, 0 },
18258 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, UNKNOWN, 0 },
18259 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, 0 },
18260 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, UNKNOWN, 0 },
18261 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, 0 },
18262 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, 0 },
18263 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, UNKNOWN, 0 },
18264 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, UNKNOWN, 0 },
18265 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, 0 },
18266 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, UNKNOWN, 0 },
18267 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, 0 },
18268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, 0 },
18269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, 0 },
18271 /* Fake 1 arg builtins with a constant smaller than 8 bits as the 2nd arg. */
18272 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, UNKNOWN, 0 },
18273 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, UNKNOWN, 0 },
18277 enum multi_arg_type {
18287 MULTI_ARG_3_PERMPS,
18288 MULTI_ARG_3_PERMPD,
18295 MULTI_ARG_2_DI_IMM,
18296 MULTI_ARG_2_SI_IMM,
18297 MULTI_ARG_2_HI_IMM,
18298 MULTI_ARG_2_QI_IMM,
18299 MULTI_ARG_2_SF_CMP,
18300 MULTI_ARG_2_DF_CMP,
18301 MULTI_ARG_2_DI_CMP,
18302 MULTI_ARG_2_SI_CMP,
18303 MULTI_ARG_2_HI_CMP,
18304 MULTI_ARG_2_QI_CMP,
18327 static const struct builtin_description bdesc_multi_arg[] =
18329 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18330 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18331 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18332 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18333 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18334 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18335 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18336 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18337 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18338 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18339 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18340 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18341 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18342 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18343 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18344 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18345 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18346 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18347 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18348 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18349 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18350 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18351 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18352 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18353 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18354 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18355 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18356 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18357 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18358 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18359 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18360 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18361 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18362 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18363 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18364 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18365 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18366 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18367 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18368 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18369 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18370 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18371 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18372 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18373 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18374 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18375 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18376 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18377 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18378 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18379 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18380 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18381 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18382 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18383 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18384 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18385 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18386 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18387 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18388 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18389 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18390 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18391 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18392 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18393 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18394 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18395 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18396 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18397 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18398 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18399 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18400 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18401 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18402 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18403 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18405 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18406 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18407 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18408 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18409 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18410 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18411 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18412 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18413 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18414 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18415 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18416 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18417 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18418 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18419 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18420 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18422 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18423 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18424 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18425 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18426 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18428 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18429 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18430 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18431 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18432 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18433 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18434 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18435 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18436 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18437 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18439 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18440 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18441 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18442 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18443 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18444 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18445 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18446 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18447 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18448 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18449 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18450 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18451 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18452 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18453 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18454 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18456 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18457 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18458 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18459 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18460 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18461 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18462 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18463 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18464 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18465 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18466 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18467 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18468 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18469 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18470 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18471 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18473 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18474 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18475 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18476 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18477 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18478 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18479 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18481 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18482 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18483 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18484 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18491 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18492 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18499 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18500 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18565 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18566 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18569 ix86_init_mmx_sse_builtins (void)
18571 const struct builtin_description * d;
18574 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18575 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18576 tree V1DI_type_node
18577 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
18578 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18579 tree V2DI_type_node
18580 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18581 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18582 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18583 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18584 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
18585 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
18586 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
18588 tree pchar_type_node = build_pointer_type (char_type_node);
18589 tree pcchar_type_node = build_pointer_type (
18590 build_type_variant (char_type_node, 1, 0));
18591 tree pfloat_type_node = build_pointer_type (float_type_node);
18592 tree pcfloat_type_node = build_pointer_type (
18593 build_type_variant (float_type_node, 1, 0));
18594 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
18595 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
18596 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
18599 tree int_ftype_v4sf_v4sf
18600 = build_function_type_list (integer_type_node,
18601 V4SF_type_node, V4SF_type_node, NULL_TREE);
18602 tree v4si_ftype_v4sf_v4sf
18603 = build_function_type_list (V4SI_type_node,
18604 V4SF_type_node, V4SF_type_node, NULL_TREE);
18605 /* MMX/SSE/integer conversions. */
18606 tree int_ftype_v4sf
18607 = build_function_type_list (integer_type_node,
18608 V4SF_type_node, NULL_TREE);
18609 tree int64_ftype_v4sf
18610 = build_function_type_list (long_long_integer_type_node,
18611 V4SF_type_node, NULL_TREE);
18612 tree int_ftype_v8qi
18613 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
18614 tree v4sf_ftype_v4sf_int
18615 = build_function_type_list (V4SF_type_node,
18616 V4SF_type_node, integer_type_node, NULL_TREE);
18617 tree v4sf_ftype_v4sf_int64
18618 = build_function_type_list (V4SF_type_node,
18619 V4SF_type_node, long_long_integer_type_node,
18621 tree v4sf_ftype_v4sf_v2si
18622 = build_function_type_list (V4SF_type_node,
18623 V4SF_type_node, V2SI_type_node, NULL_TREE);
18625 /* Miscellaneous. */
18626 tree v8qi_ftype_v4hi_v4hi
18627 = build_function_type_list (V8QI_type_node,
18628 V4HI_type_node, V4HI_type_node, NULL_TREE);
18629 tree v4hi_ftype_v2si_v2si
18630 = build_function_type_list (V4HI_type_node,
18631 V2SI_type_node, V2SI_type_node, NULL_TREE);
18632 tree v4sf_ftype_v4sf_v4sf_int
18633 = build_function_type_list (V4SF_type_node,
18634 V4SF_type_node, V4SF_type_node,
18635 integer_type_node, NULL_TREE);
18636 tree v2si_ftype_v4hi_v4hi
18637 = build_function_type_list (V2SI_type_node,
18638 V4HI_type_node, V4HI_type_node, NULL_TREE);
18639 tree v4hi_ftype_v4hi_int
18640 = build_function_type_list (V4HI_type_node,
18641 V4HI_type_node, integer_type_node, NULL_TREE);
18642 tree v2si_ftype_v2si_int
18643 = build_function_type_list (V2SI_type_node,
18644 V2SI_type_node, integer_type_node, NULL_TREE);
18645 tree v1di_ftype_v1di_int
18646 = build_function_type_list (V1DI_type_node,
18647 V1DI_type_node, integer_type_node, NULL_TREE);
18649 tree void_ftype_void
18650 = build_function_type (void_type_node, void_list_node);
18651 tree void_ftype_unsigned
18652 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
18653 tree void_ftype_unsigned_unsigned
18654 = build_function_type_list (void_type_node, unsigned_type_node,
18655 unsigned_type_node, NULL_TREE);
18656 tree void_ftype_pcvoid_unsigned_unsigned
18657 = build_function_type_list (void_type_node, const_ptr_type_node,
18658 unsigned_type_node, unsigned_type_node,
18660 tree unsigned_ftype_void
18661 = build_function_type (unsigned_type_node, void_list_node);
18662 tree v2si_ftype_v4sf
18663 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
18664 /* Loads/stores. */
18665 tree void_ftype_v8qi_v8qi_pchar
18666 = build_function_type_list (void_type_node,
18667 V8QI_type_node, V8QI_type_node,
18668 pchar_type_node, NULL_TREE);
18669 tree v4sf_ftype_pcfloat
18670 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
18671 /* @@@ the type is bogus */
18672 tree v4sf_ftype_v4sf_pv2si
18673 = build_function_type_list (V4SF_type_node,
18674 V4SF_type_node, pv2si_type_node, NULL_TREE);
18675 tree void_ftype_pv2si_v4sf
18676 = build_function_type_list (void_type_node,
18677 pv2si_type_node, V4SF_type_node, NULL_TREE);
18678 tree void_ftype_pfloat_v4sf
18679 = build_function_type_list (void_type_node,
18680 pfloat_type_node, V4SF_type_node, NULL_TREE);
18681 tree void_ftype_pdi_di
18682 = build_function_type_list (void_type_node,
18683 pdi_type_node, long_long_unsigned_type_node,
18685 tree void_ftype_pv2di_v2di
18686 = build_function_type_list (void_type_node,
18687 pv2di_type_node, V2DI_type_node, NULL_TREE);
18688 /* Normal vector unops. */
18689 tree v4sf_ftype_v4sf
18690 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
18691 tree v16qi_ftype_v16qi
18692 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
18693 tree v8hi_ftype_v8hi
18694 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
18695 tree v4si_ftype_v4si
18696 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18697 tree v8qi_ftype_v8qi
18698 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
18699 tree v4hi_ftype_v4hi
18700 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
18702 /* Normal vector binops. */
18703 tree v4sf_ftype_v4sf_v4sf
18704 = build_function_type_list (V4SF_type_node,
18705 V4SF_type_node, V4SF_type_node, NULL_TREE);
18706 tree v8qi_ftype_v8qi_v8qi
18707 = build_function_type_list (V8QI_type_node,
18708 V8QI_type_node, V8QI_type_node, NULL_TREE);
18709 tree v4hi_ftype_v4hi_v4hi
18710 = build_function_type_list (V4HI_type_node,
18711 V4HI_type_node, V4HI_type_node, NULL_TREE);
18712 tree v2si_ftype_v2si_v2si
18713 = build_function_type_list (V2SI_type_node,
18714 V2SI_type_node, V2SI_type_node, NULL_TREE);
18715 tree v1di_ftype_v1di_v1di
18716 = build_function_type_list (V1DI_type_node,
18717 V1DI_type_node, V1DI_type_node, NULL_TREE);
18719 tree di_ftype_di_di_int
18720 = build_function_type_list (long_long_unsigned_type_node,
18721 long_long_unsigned_type_node,
18722 long_long_unsigned_type_node,
18723 integer_type_node, NULL_TREE);
18725 tree v2si_ftype_v2sf
18726 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
18727 tree v2sf_ftype_v2si
18728 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
18729 tree v2si_ftype_v2si
18730 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
18731 tree v2sf_ftype_v2sf
18732 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
18733 tree v2sf_ftype_v2sf_v2sf
18734 = build_function_type_list (V2SF_type_node,
18735 V2SF_type_node, V2SF_type_node, NULL_TREE);
18736 tree v2si_ftype_v2sf_v2sf
18737 = build_function_type_list (V2SI_type_node,
18738 V2SF_type_node, V2SF_type_node, NULL_TREE);
18739 tree pint_type_node = build_pointer_type (integer_type_node);
18740 tree pdouble_type_node = build_pointer_type (double_type_node);
18741 tree pcdouble_type_node = build_pointer_type (
18742 build_type_variant (double_type_node, 1, 0));
18743 tree int_ftype_v2df_v2df
18744 = build_function_type_list (integer_type_node,
18745 V2DF_type_node, V2DF_type_node, NULL_TREE);
18747 tree void_ftype_pcvoid
18748 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
18749 tree v4sf_ftype_v4si
18750 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
18751 tree v4si_ftype_v4sf
18752 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
18753 tree v2df_ftype_v4si
18754 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
18755 tree v4si_ftype_v2df
18756 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
18757 tree v4si_ftype_v2df_v2df
18758 = build_function_type_list (V4SI_type_node,
18759 V2DF_type_node, V2DF_type_node, NULL_TREE);
18760 tree v2si_ftype_v2df
18761 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
18762 tree v4sf_ftype_v2df
18763 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
18764 tree v2df_ftype_v2si
18765 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
18766 tree v2df_ftype_v4sf
18767 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
18768 tree int_ftype_v2df
18769 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
18770 tree int64_ftype_v2df
18771 = build_function_type_list (long_long_integer_type_node,
18772 V2DF_type_node, NULL_TREE);
18773 tree v2df_ftype_v2df_int
18774 = build_function_type_list (V2DF_type_node,
18775 V2DF_type_node, integer_type_node, NULL_TREE);
18776 tree v2df_ftype_v2df_int64
18777 = build_function_type_list (V2DF_type_node,
18778 V2DF_type_node, long_long_integer_type_node,
18780 tree v4sf_ftype_v4sf_v2df
18781 = build_function_type_list (V4SF_type_node,
18782 V4SF_type_node, V2DF_type_node, NULL_TREE);
18783 tree v2df_ftype_v2df_v4sf
18784 = build_function_type_list (V2DF_type_node,
18785 V2DF_type_node, V4SF_type_node, NULL_TREE);
18786 tree v2df_ftype_v2df_v2df_int
18787 = build_function_type_list (V2DF_type_node,
18788 V2DF_type_node, V2DF_type_node,
18791 tree v2df_ftype_v2df_pcdouble
18792 = build_function_type_list (V2DF_type_node,
18793 V2DF_type_node, pcdouble_type_node, NULL_TREE);
18794 tree void_ftype_pdouble_v2df
18795 = build_function_type_list (void_type_node,
18796 pdouble_type_node, V2DF_type_node, NULL_TREE);
18797 tree void_ftype_pint_int
18798 = build_function_type_list (void_type_node,
18799 pint_type_node, integer_type_node, NULL_TREE);
18800 tree void_ftype_v16qi_v16qi_pchar
18801 = build_function_type_list (void_type_node,
18802 V16QI_type_node, V16QI_type_node,
18803 pchar_type_node, NULL_TREE);
18804 tree v2df_ftype_pcdouble
18805 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
18806 tree v2df_ftype_v2df_v2df
18807 = build_function_type_list (V2DF_type_node,
18808 V2DF_type_node, V2DF_type_node, NULL_TREE);
18809 tree v16qi_ftype_v16qi_v16qi
18810 = build_function_type_list (V16QI_type_node,
18811 V16QI_type_node, V16QI_type_node, NULL_TREE);
18812 tree v8hi_ftype_v8hi_v8hi
18813 = build_function_type_list (V8HI_type_node,
18814 V8HI_type_node, V8HI_type_node, NULL_TREE);
18815 tree v4si_ftype_v4si_v4si
18816 = build_function_type_list (V4SI_type_node,
18817 V4SI_type_node, V4SI_type_node, NULL_TREE);
18818 tree v2di_ftype_v2di_v2di
18819 = build_function_type_list (V2DI_type_node,
18820 V2DI_type_node, V2DI_type_node, NULL_TREE);
18821 tree v2di_ftype_v2df_v2df
18822 = build_function_type_list (V2DI_type_node,
18823 V2DF_type_node, V2DF_type_node, NULL_TREE);
18824 tree v2df_ftype_v2df
18825 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
18826 tree v2di_ftype_v2di_int
18827 = build_function_type_list (V2DI_type_node,
18828 V2DI_type_node, integer_type_node, NULL_TREE);
18829 tree v2di_ftype_v2di_v2di_int
18830 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18831 V2DI_type_node, integer_type_node, NULL_TREE);
18832 tree v4si_ftype_v4si_int
18833 = build_function_type_list (V4SI_type_node,
18834 V4SI_type_node, integer_type_node, NULL_TREE);
18835 tree v8hi_ftype_v8hi_int
18836 = build_function_type_list (V8HI_type_node,
18837 V8HI_type_node, integer_type_node, NULL_TREE);
18838 tree v4si_ftype_v8hi_v8hi
18839 = build_function_type_list (V4SI_type_node,
18840 V8HI_type_node, V8HI_type_node, NULL_TREE);
18841 tree v1di_ftype_v8qi_v8qi
18842 = build_function_type_list (V1DI_type_node,
18843 V8QI_type_node, V8QI_type_node, NULL_TREE);
18844 tree v1di_ftype_v2si_v2si
18845 = build_function_type_list (V1DI_type_node,
18846 V2SI_type_node, V2SI_type_node, NULL_TREE);
18847 tree v2di_ftype_v16qi_v16qi
18848 = build_function_type_list (V2DI_type_node,
18849 V16QI_type_node, V16QI_type_node, NULL_TREE);
18850 tree v2di_ftype_v4si_v4si
18851 = build_function_type_list (V2DI_type_node,
18852 V4SI_type_node, V4SI_type_node, NULL_TREE);
18853 tree int_ftype_v16qi
18854 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
18855 tree v16qi_ftype_pcchar
18856 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
18857 tree void_ftype_pchar_v16qi
18858 = build_function_type_list (void_type_node,
18859 pchar_type_node, V16QI_type_node, NULL_TREE);
18861 tree v2di_ftype_v2di_unsigned_unsigned
18862 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18863 unsigned_type_node, unsigned_type_node,
18865 tree v2di_ftype_v2di_v2di_unsigned_unsigned
18866 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
18867 unsigned_type_node, unsigned_type_node,
18869 tree v2di_ftype_v2di_v16qi
18870 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
18872 tree v2df_ftype_v2df_v2df_v2df
18873 = build_function_type_list (V2DF_type_node,
18874 V2DF_type_node, V2DF_type_node,
18875 V2DF_type_node, NULL_TREE);
18876 tree v4sf_ftype_v4sf_v4sf_v4sf
18877 = build_function_type_list (V4SF_type_node,
18878 V4SF_type_node, V4SF_type_node,
18879 V4SF_type_node, NULL_TREE);
18880 tree v8hi_ftype_v16qi
18881 = build_function_type_list (V8HI_type_node, V16QI_type_node,
18883 tree v4si_ftype_v16qi
18884 = build_function_type_list (V4SI_type_node, V16QI_type_node,
18886 tree v2di_ftype_v16qi
18887 = build_function_type_list (V2DI_type_node, V16QI_type_node,
18889 tree v4si_ftype_v8hi
18890 = build_function_type_list (V4SI_type_node, V8HI_type_node,
18892 tree v2di_ftype_v8hi
18893 = build_function_type_list (V2DI_type_node, V8HI_type_node,
18895 tree v2di_ftype_v4si
18896 = build_function_type_list (V2DI_type_node, V4SI_type_node,
18898 tree v2di_ftype_pv2di
18899 = build_function_type_list (V2DI_type_node, pv2di_type_node,
18901 tree v16qi_ftype_v16qi_v16qi_int
18902 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18903 V16QI_type_node, integer_type_node,
18905 tree v16qi_ftype_v16qi_v16qi_v16qi
18906 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18907 V16QI_type_node, V16QI_type_node,
18909 tree v8hi_ftype_v8hi_v8hi_int
18910 = build_function_type_list (V8HI_type_node, V8HI_type_node,
18911 V8HI_type_node, integer_type_node,
18913 tree v4si_ftype_v4si_v4si_int
18914 = build_function_type_list (V4SI_type_node, V4SI_type_node,
18915 V4SI_type_node, integer_type_node,
18917 tree int_ftype_v2di_v2di
18918 = build_function_type_list (integer_type_node,
18919 V2DI_type_node, V2DI_type_node,
18921 tree int_ftype_v16qi_int_v16qi_int_int
18922 = build_function_type_list (integer_type_node,
18929 tree v16qi_ftype_v16qi_int_v16qi_int_int
18930 = build_function_type_list (V16QI_type_node,
18937 tree int_ftype_v16qi_v16qi_int
18938 = build_function_type_list (integer_type_node,
18944 /* SSE5 instructions */
18945 tree v2di_ftype_v2di_v2di_v2di
18946 = build_function_type_list (V2DI_type_node,
18952 tree v4si_ftype_v4si_v4si_v4si
18953 = build_function_type_list (V4SI_type_node,
18959 tree v4si_ftype_v4si_v4si_v2di
18960 = build_function_type_list (V4SI_type_node,
18966 tree v8hi_ftype_v8hi_v8hi_v8hi
18967 = build_function_type_list (V8HI_type_node,
18973 tree v8hi_ftype_v8hi_v8hi_v4si
18974 = build_function_type_list (V8HI_type_node,
18980 tree v2df_ftype_v2df_v2df_v16qi
18981 = build_function_type_list (V2DF_type_node,
18987 tree v4sf_ftype_v4sf_v4sf_v16qi
18988 = build_function_type_list (V4SF_type_node,
18994 tree v2di_ftype_v2di_si
18995 = build_function_type_list (V2DI_type_node,
19000 tree v4si_ftype_v4si_si
19001 = build_function_type_list (V4SI_type_node,
19006 tree v8hi_ftype_v8hi_si
19007 = build_function_type_list (V8HI_type_node,
19012 tree v16qi_ftype_v16qi_si
19013 = build_function_type_list (V16QI_type_node,
19017 tree v4sf_ftype_v4hi
19018 = build_function_type_list (V4SF_type_node,
19022 tree v4hi_ftype_v4sf
19023 = build_function_type_list (V4HI_type_node,
19027 tree v2di_ftype_v2di
19028 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19032 /* The __float80 type. */
19033 if (TYPE_MODE (long_double_type_node) == XFmode)
19034 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19038 /* The __float80 type. */
19039 tree float80_type_node = make_node (REAL_TYPE);
19041 TYPE_PRECISION (float80_type_node) = 80;
19042 layout_type (float80_type_node);
19043 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19049 tree float128_type_node = make_node (REAL_TYPE);
19051 TYPE_PRECISION (float128_type_node) = 128;
19052 layout_type (float128_type_node);
19053 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19056 /* TFmode support builtins. */
19057 ftype = build_function_type (float128_type_node,
19059 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19061 ftype = build_function_type_list (float128_type_node,
19062 float128_type_node,
19064 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19066 ftype = build_function_type_list (float128_type_node,
19067 float128_type_node,
19068 float128_type_node,
19070 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19073 /* Add all SSE builtins that are more or less simple operations on
19075 for (i = 0, d = bdesc_sse_3arg;
19076 i < ARRAY_SIZE (bdesc_sse_3arg);
19079 /* Use one of the operands; the target can have a different mode for
19080 mask-generating compares. */
19081 enum machine_mode mode;
19086 mode = insn_data[d->icode].operand[1].mode;
19091 type = v16qi_ftype_v16qi_v16qi_int;
19094 type = v8hi_ftype_v8hi_v8hi_int;
19097 type = v4si_ftype_v4si_v4si_int;
19100 type = v2di_ftype_v2di_v2di_int;
19103 type = v2df_ftype_v2df_v2df_int;
19106 type = v4sf_ftype_v4sf_v4sf_int;
19109 gcc_unreachable ();
19112 /* Override for variable blends. */
19115 case CODE_FOR_sse4_1_blendvpd:
19116 type = v2df_ftype_v2df_v2df_v2df;
19118 case CODE_FOR_sse4_1_blendvps:
19119 type = v4sf_ftype_v4sf_v4sf_v4sf;
19121 case CODE_FOR_sse4_1_pblendvb:
19122 type = v16qi_ftype_v16qi_v16qi_v16qi;
19128 def_builtin_const (d->mask, d->name, type, d->code);
19131 /* Add all builtins that are more or less simple operations on two
19133 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19135 /* Use one of the operands; the target can have a different mode for
19136 mask-generating compares. */
19137 enum machine_mode mode;
19142 mode = insn_data[d->icode].operand[1].mode;
19147 type = v16qi_ftype_v16qi_v16qi;
19150 type = v8hi_ftype_v8hi_v8hi;
19153 type = v4si_ftype_v4si_v4si;
19156 type = v2di_ftype_v2di_v2di;
19159 type = v2df_ftype_v2df_v2df;
19162 type = v4sf_ftype_v4sf_v4sf;
19165 type = v8qi_ftype_v8qi_v8qi;
19168 type = v4hi_ftype_v4hi_v4hi;
19171 type = v2si_ftype_v2si_v2si;
19174 type = v1di_ftype_v1di_v1di;
19178 gcc_unreachable ();
19181 /* Override for comparisons. */
19182 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19183 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
19184 type = v4si_ftype_v4sf_v4sf;
19186 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
19187 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19188 type = v2di_ftype_v2df_v2df;
19190 if (d->icode == CODE_FOR_vec_pack_sfix_v2df)
19191 type = v4si_ftype_v2df_v2df;
19193 def_builtin_const (d->mask, d->name, type, d->code);
19196 /* Add all builtins that are more or less simple operations on 1 operand. */
19197 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19199 enum machine_mode mode;
19204 mode = insn_data[d->icode].operand[1].mode;
19209 type = v16qi_ftype_v16qi;
19212 type = v8hi_ftype_v8hi;
19215 type = v4si_ftype_v4si;
19218 type = v2df_ftype_v2df;
19221 type = v4sf_ftype_v4sf;
19224 type = v8qi_ftype_v8qi;
19227 type = v4hi_ftype_v4hi;
19230 type = v2si_ftype_v2si;
19237 def_builtin_const (d->mask, d->name, type, d->code);
19240 /* pcmpestr[im] insns. */
19241 for (i = 0, d = bdesc_pcmpestr;
19242 i < ARRAY_SIZE (bdesc_pcmpestr);
19245 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19246 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19248 ftype = int_ftype_v16qi_int_v16qi_int_int;
19249 def_builtin_const (d->mask, d->name, ftype, d->code);
19252 /* pcmpistr[im] insns. */
19253 for (i = 0, d = bdesc_pcmpistr;
19254 i < ARRAY_SIZE (bdesc_pcmpistr);
19257 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19258 ftype = v16qi_ftype_v16qi_v16qi_int;
19260 ftype = int_ftype_v16qi_v16qi_int;
19261 def_builtin_const (d->mask, d->name, ftype, d->code);
19264 /* Add the remaining MMX insns with somewhat more complicated types. */
19265 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
19267 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSLLWI);
19268 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSLLDI);
19269 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSLLQI);
19270 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSLLW);
19271 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSLLD);
19272 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSLLQ);
19274 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRLWI);
19275 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRLDI);
19276 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSRLQI);
19277 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRLW);
19278 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRLD);
19279 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSRLQ);
19281 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrawi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRAWI);
19282 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psradi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRADI);
19283 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRAW);
19284 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRAD);
19286 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
19287 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
19289 /* comi/ucomi insns. */
19290 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19291 if (d->mask == OPTION_MASK_ISA_SSE2)
19292 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19294 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19297 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19298 def_builtin_const (d->mask, d->name, int_ftype_v2di_v2di, d->code);
19300 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
19301 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
19302 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
19304 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19305 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19306 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
19307 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
19308 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
19309 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
19310 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
19311 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
19312 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
19313 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
19314 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
19316 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19318 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
19319 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
19321 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
19322 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
19323 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
19324 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
19326 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
19327 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
19328 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
19329 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
19331 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
19333 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", v1di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
19335 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
19336 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
19337 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
19338 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS_NR);
19339 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
19340 ftype = build_function_type_list (float_type_node,
19343 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
19344 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
19345 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS_NR);
19346 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
19348 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
19350 /* Original 3DNow! */
19351 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
19352 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
19353 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
19354 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
19355 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
19356 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
19357 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
19358 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
19359 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
19360 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
19361 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
19362 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
19363 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
19364 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
19365 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
19366 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
19367 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
19368 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
19369 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
19370 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
19372 /* 3DNow! extension as used in the Athlon CPU. */
19373 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
19374 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
19375 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
19376 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
19377 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
19378 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
19381 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19383 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
19384 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
19386 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
19387 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
19389 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
19390 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
19391 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
19392 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
19393 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
19395 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
19396 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
19397 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
19398 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
19400 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
19401 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
19403 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
19405 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
19406 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
19408 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
19409 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
19410 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
19411 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
19412 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
19414 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
19416 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
19417 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
19418 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
19419 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
19421 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
19422 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
19423 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
19425 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
19426 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
19427 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
19428 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
19430 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19431 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
19432 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19434 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
19435 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
19437 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", v1di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
19438 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
19440 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
19441 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
19442 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
19443 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
19444 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
19445 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
19446 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
19448 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
19449 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
19450 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
19451 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
19452 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
19453 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
19454 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
19456 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
19457 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
19458 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
19459 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
19461 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
19463 /* Prescott New Instructions. */
19464 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19465 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19466 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
19469 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
19470 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
19473 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
19474 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
19475 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
19476 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
19477 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
19478 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
19479 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
19480 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
19481 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
19482 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
19483 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
19484 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
19485 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
19486 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
19488 /* SSE4.1 and SSE5 */
19489 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundpd", v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
19490 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundps", v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
19491 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundsd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
19492 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundss", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
19495 ftype = build_function_type_list (unsigned_type_node,
19496 unsigned_type_node,
19497 unsigned_char_type_node,
19499 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
19500 ftype = build_function_type_list (unsigned_type_node,
19501 unsigned_type_node,
19502 short_unsigned_type_node,
19504 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
19505 ftype = build_function_type_list (unsigned_type_node,
19506 unsigned_type_node,
19507 unsigned_type_node,
19509 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
19510 ftype = build_function_type_list (long_long_unsigned_type_node,
19511 long_long_unsigned_type_node,
19512 long_long_unsigned_type_node,
19514 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
19516 /* AMDFAM10 SSE4A New built-ins */
19517 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
19518 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
19519 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
19520 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
19521 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
19522 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
19524 /* Access to the vec_init patterns. */
19525 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19526 integer_type_node, NULL_TREE);
19527 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19529 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19530 short_integer_type_node,
19531 short_integer_type_node,
19532 short_integer_type_node, NULL_TREE);
19533 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19535 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19536 char_type_node, char_type_node,
19537 char_type_node, char_type_node,
19538 char_type_node, char_type_node,
19539 char_type_node, NULL_TREE);
19540 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19542 /* Access to the vec_extract patterns. */
19543 ftype = build_function_type_list (double_type_node, V2DF_type_node,
19544 integer_type_node, NULL_TREE);
19545 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
19547 ftype = build_function_type_list (long_long_integer_type_node,
19548 V2DI_type_node, integer_type_node,
19550 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
19552 ftype = build_function_type_list (float_type_node, V4SF_type_node,
19553 integer_type_node, NULL_TREE);
19554 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
19556 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
19557 integer_type_node, NULL_TREE);
19558 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
19560 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
19561 integer_type_node, NULL_TREE);
19562 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
19564 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
19565 integer_type_node, NULL_TREE);
19566 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
19568 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
19569 integer_type_node, NULL_TREE);
19570 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
19572 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
19573 integer_type_node, NULL_TREE);
19574 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
19576 /* Access to the vec_set patterns. */
19577 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
19579 integer_type_node, NULL_TREE);
19580 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
19582 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
19584 integer_type_node, NULL_TREE);
19585 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
19587 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
19589 integer_type_node, NULL_TREE);
19590 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
19592 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
19594 integer_type_node, NULL_TREE);
19595 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
19597 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
19599 integer_type_node, NULL_TREE);
19600 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
19602 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
19604 integer_type_node, NULL_TREE);
19605 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
19607 /* Add SSE5 multi-arg argument instructions */
19608 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
19610 tree mtype = NULL_TREE;
19615 switch ((enum multi_arg_type)d->flag)
19617 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
19618 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
19619 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
19620 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
19621 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
19622 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
19623 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
19624 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
19625 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
19626 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
19627 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
19628 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
19629 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
19630 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
19631 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
19632 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
19633 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
19634 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
19635 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
19636 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
19637 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
19638 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
19639 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
19640 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
19641 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
19642 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
19643 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
19644 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
19645 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
19646 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
19647 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
19648 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
19649 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
19650 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
19651 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
19652 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
19653 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
19654 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
19655 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
19656 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
19657 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
19658 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
19659 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
19660 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
19661 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
19662 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
19663 case MULTI_ARG_UNKNOWN:
19665 gcc_unreachable ();
19669 def_builtin_const (d->mask, d->name, mtype, d->code);
19674 ix86_init_builtins (void)
19677 ix86_init_mmx_sse_builtins ();
19680 /* Errors in the source file can cause expand_expr to return const0_rtx
19681 where we expect a vector. To avoid crashing, use one of the vector
19682 clear instructions. */
19684 safe_vector_operand (rtx x, enum machine_mode mode)
19686 if (x == const0_rtx)
19687 x = CONST0_RTX (mode);
19691 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
19692 4 operands. The third argument must be a constant smaller than 8
19696 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
19700 tree arg0 = CALL_EXPR_ARG (exp, 0);
19701 tree arg1 = CALL_EXPR_ARG (exp, 1);
19702 tree arg2 = CALL_EXPR_ARG (exp, 2);
19703 rtx op0 = expand_normal (arg0);
19704 rtx op1 = expand_normal (arg1);
19705 rtx op2 = expand_normal (arg2);
19706 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19707 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
19708 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
19709 enum machine_mode mode3 = insn_data[icode].operand[3].mode;
19711 if (VECTOR_MODE_P (mode1))
19712 op0 = safe_vector_operand (op0, mode1);
19713 if (VECTOR_MODE_P (mode2))
19714 op1 = safe_vector_operand (op1, mode2);
19715 if (VECTOR_MODE_P (mode3))
19716 op2 = safe_vector_operand (op2, mode3);
19720 || GET_MODE (target) != tmode
19721 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19722 target = gen_reg_rtx (tmode);
19724 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19725 op0 = copy_to_mode_reg (mode1, op0);
19726 if ((optimize && !register_operand (op1, mode2))
19727 || !(*insn_data[icode].operand[2].predicate) (op1, mode2))
19728 op1 = copy_to_mode_reg (mode2, op1);
19730 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19733 case CODE_FOR_sse4_1_blendvpd:
19734 case CODE_FOR_sse4_1_blendvps:
19735 case CODE_FOR_sse4_1_pblendvb:
19736 op2 = copy_to_mode_reg (mode3, op2);
19739 case CODE_FOR_sse4_1_roundsd:
19740 case CODE_FOR_sse4_1_roundss:
19741 case CODE_FOR_sse4_1_blendps:
19742 error ("the third argument must be a 4-bit immediate");
19745 case CODE_FOR_sse4_1_blendpd:
19746 error ("the third argument must be a 2-bit immediate");
19750 error ("the third argument must be an 8-bit immediate");
19754 pat = GEN_FCN (icode) (target, op0, op1, op2);
19761 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
19764 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
19767 tree arg0 = CALL_EXPR_ARG (exp, 0);
19768 tree arg1 = CALL_EXPR_ARG (exp, 1);
19769 rtx op0 = expand_normal (arg0);
19770 rtx op1 = expand_normal (arg1);
19771 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19772 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19773 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19777 || GET_MODE (target) != tmode
19778 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19779 target = gen_reg_rtx (tmode);
19781 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19782 op0 = copy_to_mode_reg (mode0, op0);
19783 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19785 op1 = copy_to_reg (op1);
19786 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
19789 pat = GEN_FCN (icode) (target, op0, op1);
19796 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
19799 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
19802 tree arg0 = CALL_EXPR_ARG (exp, 0);
19803 tree arg1 = CALL_EXPR_ARG (exp, 1);
19804 rtx op0 = expand_normal (arg0);
19805 rtx op1 = expand_normal (arg1);
19806 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19807 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19808 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19810 if (VECTOR_MODE_P (mode0))
19811 op0 = safe_vector_operand (op0, mode0);
19812 if (VECTOR_MODE_P (mode1))
19813 op1 = safe_vector_operand (op1, mode1);
19815 if (optimize || !target
19816 || GET_MODE (target) != tmode
19817 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19818 target = gen_reg_rtx (tmode);
19820 if (GET_MODE (op1) == SImode && mode1 == TImode)
19822 rtx x = gen_reg_rtx (V4SImode);
19823 emit_insn (gen_sse2_loadd (x, op1));
19824 op1 = gen_lowpart (TImode, x);
19827 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19828 op0 = copy_to_mode_reg (mode0, op0);
19829 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19830 op1 = copy_to_mode_reg (mode1, op1);
19832 /* ??? Using ix86_fixup_binary_operands is problematic when
19833 we've got mismatched modes. Fake it. */
19839 if (tmode == mode0 && tmode == mode1)
19841 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
19845 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
19847 op0 = force_reg (mode0, op0);
19848 op1 = force_reg (mode1, op1);
19849 target = gen_reg_rtx (tmode);
19852 pat = GEN_FCN (icode) (target, op0, op1);
19859 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
19862 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
19863 enum multi_arg_type m_type,
19864 enum insn_code sub_code)
19869 bool comparison_p = false;
19871 bool last_arg_constant = false;
19872 int num_memory = 0;
19875 enum machine_mode mode;
19878 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19882 case MULTI_ARG_3_SF:
19883 case MULTI_ARG_3_DF:
19884 case MULTI_ARG_3_DI:
19885 case MULTI_ARG_3_SI:
19886 case MULTI_ARG_3_SI_DI:
19887 case MULTI_ARG_3_HI:
19888 case MULTI_ARG_3_HI_SI:
19889 case MULTI_ARG_3_QI:
19890 case MULTI_ARG_3_PERMPS:
19891 case MULTI_ARG_3_PERMPD:
19895 case MULTI_ARG_2_SF:
19896 case MULTI_ARG_2_DF:
19897 case MULTI_ARG_2_DI:
19898 case MULTI_ARG_2_SI:
19899 case MULTI_ARG_2_HI:
19900 case MULTI_ARG_2_QI:
19904 case MULTI_ARG_2_DI_IMM:
19905 case MULTI_ARG_2_SI_IMM:
19906 case MULTI_ARG_2_HI_IMM:
19907 case MULTI_ARG_2_QI_IMM:
19909 last_arg_constant = true;
19912 case MULTI_ARG_1_SF:
19913 case MULTI_ARG_1_DF:
19914 case MULTI_ARG_1_DI:
19915 case MULTI_ARG_1_SI:
19916 case MULTI_ARG_1_HI:
19917 case MULTI_ARG_1_QI:
19918 case MULTI_ARG_1_SI_DI:
19919 case MULTI_ARG_1_HI_DI:
19920 case MULTI_ARG_1_HI_SI:
19921 case MULTI_ARG_1_QI_DI:
19922 case MULTI_ARG_1_QI_SI:
19923 case MULTI_ARG_1_QI_HI:
19924 case MULTI_ARG_1_PH2PS:
19925 case MULTI_ARG_1_PS2PH:
19929 case MULTI_ARG_2_SF_CMP:
19930 case MULTI_ARG_2_DF_CMP:
19931 case MULTI_ARG_2_DI_CMP:
19932 case MULTI_ARG_2_SI_CMP:
19933 case MULTI_ARG_2_HI_CMP:
19934 case MULTI_ARG_2_QI_CMP:
19936 comparison_p = true;
19939 case MULTI_ARG_2_SF_TF:
19940 case MULTI_ARG_2_DF_TF:
19941 case MULTI_ARG_2_DI_TF:
19942 case MULTI_ARG_2_SI_TF:
19943 case MULTI_ARG_2_HI_TF:
19944 case MULTI_ARG_2_QI_TF:
19949 case MULTI_ARG_UNKNOWN:
19951 gcc_unreachable ();
19954 if (optimize || !target
19955 || GET_MODE (target) != tmode
19956 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19957 target = gen_reg_rtx (tmode);
19959 gcc_assert (nargs <= 4);
19961 for (i = 0; i < nargs; i++)
19963 tree arg = CALL_EXPR_ARG (exp, i);
19964 rtx op = expand_normal (arg);
19965 int adjust = (comparison_p) ? 1 : 0;
19966 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
19968 if (last_arg_constant && i == nargs-1)
19970 if (GET_CODE (op) != CONST_INT)
19972 error ("last argument must be an immediate");
19973 return gen_reg_rtx (tmode);
19978 if (VECTOR_MODE_P (mode))
19979 op = safe_vector_operand (op, mode);
19981 /* If we aren't optimizing, only allow one memory operand to be
19983 if (memory_operand (op, mode))
19986 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
19989 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
19991 op = force_reg (mode, op);
19995 args[i].mode = mode;
20001 pat = GEN_FCN (icode) (target, args[0].op);
20006 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
20007 GEN_INT ((int)sub_code));
20008 else if (! comparison_p)
20009 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20012 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
20016 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20021 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20025 gcc_unreachable ();
20035 /* Subroutine of ix86_expand_builtin to take care of stores. */
20038 ix86_expand_store_builtin (enum insn_code icode, tree exp)
20041 tree arg0 = CALL_EXPR_ARG (exp, 0);
20042 tree arg1 = CALL_EXPR_ARG (exp, 1);
20043 rtx op0 = expand_normal (arg0);
20044 rtx op1 = expand_normal (arg1);
20045 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
20046 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
20048 if (VECTOR_MODE_P (mode1))
20049 op1 = safe_vector_operand (op1, mode1);
20051 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20052 op1 = copy_to_mode_reg (mode1, op1);
20054 pat = GEN_FCN (icode) (op0, op1);
20060 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
20063 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
20064 rtx target, int do_load)
20067 tree arg0 = CALL_EXPR_ARG (exp, 0);
20068 rtx op0 = expand_normal (arg0);
20069 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20070 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20072 if (optimize || !target
20073 || GET_MODE (target) != tmode
20074 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20075 target = gen_reg_rtx (tmode);
20077 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20080 if (VECTOR_MODE_P (mode0))
20081 op0 = safe_vector_operand (op0, mode0);
20083 if ((optimize && !register_operand (op0, mode0))
20084 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20085 op0 = copy_to_mode_reg (mode0, op0);
20090 case CODE_FOR_sse4_1_roundpd:
20091 case CODE_FOR_sse4_1_roundps:
20093 tree arg1 = CALL_EXPR_ARG (exp, 1);
20094 rtx op1 = expand_normal (arg1);
20095 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20097 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
20099 error ("the second argument must be a 4-bit immediate");
20102 pat = GEN_FCN (icode) (target, op0, op1);
20106 pat = GEN_FCN (icode) (target, op0);
20116 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
20117 sqrtss, rsqrtss, rcpss. */
20120 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
20123 tree arg0 = CALL_EXPR_ARG (exp, 0);
20124 rtx op1, op0 = expand_normal (arg0);
20125 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20126 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20128 if (optimize || !target
20129 || GET_MODE (target) != tmode
20130 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20131 target = gen_reg_rtx (tmode);
20133 if (VECTOR_MODE_P (mode0))
20134 op0 = safe_vector_operand (op0, mode0);
20136 if ((optimize && !register_operand (op0, mode0))
20137 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20138 op0 = copy_to_mode_reg (mode0, op0);
20141 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20142 op1 = copy_to_mode_reg (mode0, op1);
20144 pat = GEN_FCN (icode) (target, op0, op1);
20151 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20154 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
20158 tree arg0 = CALL_EXPR_ARG (exp, 0);
20159 tree arg1 = CALL_EXPR_ARG (exp, 1);
20160 rtx op0 = expand_normal (arg0);
20161 rtx op1 = expand_normal (arg1);
20163 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20164 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20165 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20166 enum rtx_code comparison = d->comparison;
20168 if (VECTOR_MODE_P (mode0))
20169 op0 = safe_vector_operand (op0, mode0);
20170 if (VECTOR_MODE_P (mode1))
20171 op1 = safe_vector_operand (op1, mode1);
20173 /* Swap operands if we have a comparison that isn't available in
20175 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20177 rtx tmp = gen_reg_rtx (mode1);
20178 emit_move_insn (tmp, op1);
20183 if (optimize || !target
20184 || GET_MODE (target) != tmode
20185 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20186 target = gen_reg_rtx (tmode);
20188 if ((optimize && !register_operand (op0, mode0))
20189 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20190 op0 = copy_to_mode_reg (mode0, op0);
20191 if ((optimize && !register_operand (op1, mode1))
20192 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20193 op1 = copy_to_mode_reg (mode1, op1);
20195 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20196 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20203 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20206 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20210 tree arg0 = CALL_EXPR_ARG (exp, 0);
20211 tree arg1 = CALL_EXPR_ARG (exp, 1);
20212 rtx op0 = expand_normal (arg0);
20213 rtx op1 = expand_normal (arg1);
20214 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20215 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20216 enum rtx_code comparison = d->comparison;
20218 if (VECTOR_MODE_P (mode0))
20219 op0 = safe_vector_operand (op0, mode0);
20220 if (VECTOR_MODE_P (mode1))
20221 op1 = safe_vector_operand (op1, mode1);
20223 /* Swap operands if we have a comparison that isn't available in
20225 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20232 target = gen_reg_rtx (SImode);
20233 emit_move_insn (target, const0_rtx);
20234 target = gen_rtx_SUBREG (QImode, target, 0);
20236 if ((optimize && !register_operand (op0, mode0))
20237 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20238 op0 = copy_to_mode_reg (mode0, op0);
20239 if ((optimize && !register_operand (op1, mode1))
20240 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20241 op1 = copy_to_mode_reg (mode1, op1);
20243 pat = GEN_FCN (d->icode) (op0, op1);
20247 emit_insn (gen_rtx_SET (VOIDmode,
20248 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20249 gen_rtx_fmt_ee (comparison, QImode,
20253 return SUBREG_REG (target);
20256 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20259 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20263 tree arg0 = CALL_EXPR_ARG (exp, 0);
20264 tree arg1 = CALL_EXPR_ARG (exp, 1);
20265 rtx op0 = expand_normal (arg0);
20266 rtx op1 = expand_normal (arg1);
20267 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20268 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20269 enum rtx_code comparison = d->comparison;
20271 if (VECTOR_MODE_P (mode0))
20272 op0 = safe_vector_operand (op0, mode0);
20273 if (VECTOR_MODE_P (mode1))
20274 op1 = safe_vector_operand (op1, mode1);
20276 target = gen_reg_rtx (SImode);
20277 emit_move_insn (target, const0_rtx);
20278 target = gen_rtx_SUBREG (QImode, target, 0);
20280 if ((optimize && !register_operand (op0, mode0))
20281 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20282 op0 = copy_to_mode_reg (mode0, op0);
20283 if ((optimize && !register_operand (op1, mode1))
20284 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20285 op1 = copy_to_mode_reg (mode1, op1);
20287 pat = GEN_FCN (d->icode) (op0, op1);
20291 emit_insn (gen_rtx_SET (VOIDmode,
20292 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20293 gen_rtx_fmt_ee (comparison, QImode,
20297 return SUBREG_REG (target);
20300 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20303 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20304 tree exp, rtx target)
20307 tree arg0 = CALL_EXPR_ARG (exp, 0);
20308 tree arg1 = CALL_EXPR_ARG (exp, 1);
20309 tree arg2 = CALL_EXPR_ARG (exp, 2);
20310 tree arg3 = CALL_EXPR_ARG (exp, 3);
20311 tree arg4 = CALL_EXPR_ARG (exp, 4);
20312 rtx scratch0, scratch1;
20313 rtx op0 = expand_normal (arg0);
20314 rtx op1 = expand_normal (arg1);
20315 rtx op2 = expand_normal (arg2);
20316 rtx op3 = expand_normal (arg3);
20317 rtx op4 = expand_normal (arg4);
20318 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20320 tmode0 = insn_data[d->icode].operand[0].mode;
20321 tmode1 = insn_data[d->icode].operand[1].mode;
20322 modev2 = insn_data[d->icode].operand[2].mode;
20323 modei3 = insn_data[d->icode].operand[3].mode;
20324 modev4 = insn_data[d->icode].operand[4].mode;
20325 modei5 = insn_data[d->icode].operand[5].mode;
20326 modeimm = insn_data[d->icode].operand[6].mode;
20328 if (VECTOR_MODE_P (modev2))
20329 op0 = safe_vector_operand (op0, modev2);
20330 if (VECTOR_MODE_P (modev4))
20331 op2 = safe_vector_operand (op2, modev4);
20333 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20334 op0 = copy_to_mode_reg (modev2, op0);
20335 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20336 op1 = copy_to_mode_reg (modei3, op1);
20337 if ((optimize && !register_operand (op2, modev4))
20338 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20339 op2 = copy_to_mode_reg (modev4, op2);
20340 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20341 op3 = copy_to_mode_reg (modei5, op3);
20343 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20345 error ("the fifth argument must be a 8-bit immediate");
20349 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20351 if (optimize || !target
20352 || GET_MODE (target) != tmode0
20353 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20354 target = gen_reg_rtx (tmode0);
20356 scratch1 = gen_reg_rtx (tmode1);
20358 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20360 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20362 if (optimize || !target
20363 || GET_MODE (target) != tmode1
20364 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20365 target = gen_reg_rtx (tmode1);
20367 scratch0 = gen_reg_rtx (tmode0);
20369 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20373 gcc_assert (d->flag);
20375 scratch0 = gen_reg_rtx (tmode0);
20376 scratch1 = gen_reg_rtx (tmode1);
20378 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20388 target = gen_reg_rtx (SImode);
20389 emit_move_insn (target, const0_rtx);
20390 target = gen_rtx_SUBREG (QImode, target, 0);
20393 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20394 gen_rtx_fmt_ee (EQ, QImode,
20395 gen_rtx_REG ((enum machine_mode) d->flag,
20398 return SUBREG_REG (target);
20405 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20408 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20409 tree exp, rtx target)
20412 tree arg0 = CALL_EXPR_ARG (exp, 0);
20413 tree arg1 = CALL_EXPR_ARG (exp, 1);
20414 tree arg2 = CALL_EXPR_ARG (exp, 2);
20415 rtx scratch0, scratch1;
20416 rtx op0 = expand_normal (arg0);
20417 rtx op1 = expand_normal (arg1);
20418 rtx op2 = expand_normal (arg2);
20419 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20421 tmode0 = insn_data[d->icode].operand[0].mode;
20422 tmode1 = insn_data[d->icode].operand[1].mode;
20423 modev2 = insn_data[d->icode].operand[2].mode;
20424 modev3 = insn_data[d->icode].operand[3].mode;
20425 modeimm = insn_data[d->icode].operand[4].mode;
20427 if (VECTOR_MODE_P (modev2))
20428 op0 = safe_vector_operand (op0, modev2);
20429 if (VECTOR_MODE_P (modev3))
20430 op1 = safe_vector_operand (op1, modev3);
20432 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20433 op0 = copy_to_mode_reg (modev2, op0);
20434 if ((optimize && !register_operand (op1, modev3))
20435 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20436 op1 = copy_to_mode_reg (modev3, op1);
20438 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20440 error ("the third argument must be a 8-bit immediate");
20444 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20446 if (optimize || !target
20447 || GET_MODE (target) != tmode0
20448 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20449 target = gen_reg_rtx (tmode0);
20451 scratch1 = gen_reg_rtx (tmode1);
20453 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20455 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20457 if (optimize || !target
20458 || GET_MODE (target) != tmode1
20459 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20460 target = gen_reg_rtx (tmode1);
20462 scratch0 = gen_reg_rtx (tmode0);
20464 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20468 gcc_assert (d->flag);
20470 scratch0 = gen_reg_rtx (tmode0);
20471 scratch1 = gen_reg_rtx (tmode1);
20473 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20483 target = gen_reg_rtx (SImode);
20484 emit_move_insn (target, const0_rtx);
20485 target = gen_rtx_SUBREG (QImode, target, 0);
20488 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20489 gen_rtx_fmt_ee (EQ, QImode,
20490 gen_rtx_REG ((enum machine_mode) d->flag,
20493 return SUBREG_REG (target);
20499 /* Return the integer constant in ARG. Constrain it to be in the range
20500 of the subparts of VEC_TYPE; issue an error if not. */
20503 get_element_number (tree vec_type, tree arg)
20505 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
20507 if (!host_integerp (arg, 1)
20508 || (elt = tree_low_cst (arg, 1), elt > max))
20510 error ("selector must be an integer constant in the range 0..%wi", max);
20517 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20518 ix86_expand_vector_init. We DO have language-level syntax for this, in
20519 the form of (type){ init-list }. Except that since we can't place emms
20520 instructions from inside the compiler, we can't allow the use of MMX
20521 registers unless the user explicitly asks for it. So we do *not* define
20522 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
20523 we have builtins invoked by mmintrin.h that gives us license to emit
20524 these sorts of instructions. */
20527 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
20529 enum machine_mode tmode = TYPE_MODE (type);
20530 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
20531 int i, n_elt = GET_MODE_NUNITS (tmode);
20532 rtvec v = rtvec_alloc (n_elt);
20534 gcc_assert (VECTOR_MODE_P (tmode));
20535 gcc_assert (call_expr_nargs (exp) == n_elt);
20537 for (i = 0; i < n_elt; ++i)
20539 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
20540 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
20543 if (!target || !register_operand (target, tmode))
20544 target = gen_reg_rtx (tmode);
20546 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
20550 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20551 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
20552 had a language-level syntax for referencing vector elements. */
20555 ix86_expand_vec_ext_builtin (tree exp, rtx target)
20557 enum machine_mode tmode, mode0;
20562 arg0 = CALL_EXPR_ARG (exp, 0);
20563 arg1 = CALL_EXPR_ARG (exp, 1);
20565 op0 = expand_normal (arg0);
20566 elt = get_element_number (TREE_TYPE (arg0), arg1);
20568 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20569 mode0 = TYPE_MODE (TREE_TYPE (arg0));
20570 gcc_assert (VECTOR_MODE_P (mode0));
20572 op0 = force_reg (mode0, op0);
20574 if (optimize || !target || !register_operand (target, tmode))
20575 target = gen_reg_rtx (tmode);
20577 ix86_expand_vector_extract (true, target, op0, elt);
20582 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20583 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
20584 a language-level syntax for referencing vector elements. */
20587 ix86_expand_vec_set_builtin (tree exp)
20589 enum machine_mode tmode, mode1;
20590 tree arg0, arg1, arg2;
20592 rtx op0, op1, target;
20594 arg0 = CALL_EXPR_ARG (exp, 0);
20595 arg1 = CALL_EXPR_ARG (exp, 1);
20596 arg2 = CALL_EXPR_ARG (exp, 2);
20598 tmode = TYPE_MODE (TREE_TYPE (arg0));
20599 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20600 gcc_assert (VECTOR_MODE_P (tmode));
20602 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
20603 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
20604 elt = get_element_number (TREE_TYPE (arg0), arg2);
20606 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
20607 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
20609 op0 = force_reg (tmode, op0);
20610 op1 = force_reg (mode1, op1);
20612 /* OP0 is the source of these builtin functions and shouldn't be
20613 modified. Create a copy, use it and return it as target. */
20614 target = gen_reg_rtx (tmode);
20615 emit_move_insn (target, op0);
20616 ix86_expand_vector_set (true, target, op1, elt);
20621 /* Expand an expression EXP that calls a built-in function,
20622 with result going to TARGET if that's convenient
20623 (and in mode MODE if that's convenient).
20624 SUBTARGET may be used as the target for computing one of EXP's operands.
20625 IGNORE is nonzero if the value is to be ignored. */
20628 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
20629 enum machine_mode mode ATTRIBUTE_UNUSED,
20630 int ignore ATTRIBUTE_UNUSED)
20632 const struct builtin_description *d;
20634 enum insn_code icode;
20635 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
20636 tree arg0, arg1, arg2, arg3;
20637 rtx op0, op1, op2, op3, pat;
20638 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
20639 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
20643 case IX86_BUILTIN_EMMS:
20644 emit_insn (gen_mmx_emms ());
20647 case IX86_BUILTIN_SFENCE:
20648 emit_insn (gen_sse_sfence ());
20651 case IX86_BUILTIN_MASKMOVQ:
20652 case IX86_BUILTIN_MASKMOVDQU:
20653 icode = (fcode == IX86_BUILTIN_MASKMOVQ
20654 ? CODE_FOR_mmx_maskmovq
20655 : CODE_FOR_sse2_maskmovdqu);
20656 /* Note the arg order is different from the operand order. */
20657 arg1 = CALL_EXPR_ARG (exp, 0);
20658 arg2 = CALL_EXPR_ARG (exp, 1);
20659 arg0 = CALL_EXPR_ARG (exp, 2);
20660 op0 = expand_normal (arg0);
20661 op1 = expand_normal (arg1);
20662 op2 = expand_normal (arg2);
20663 mode0 = insn_data[icode].operand[0].mode;
20664 mode1 = insn_data[icode].operand[1].mode;
20665 mode2 = insn_data[icode].operand[2].mode;
20667 op0 = force_reg (Pmode, op0);
20668 op0 = gen_rtx_MEM (mode1, op0);
20670 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
20671 op0 = copy_to_mode_reg (mode0, op0);
20672 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
20673 op1 = copy_to_mode_reg (mode1, op1);
20674 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
20675 op2 = copy_to_mode_reg (mode2, op2);
20676 pat = GEN_FCN (icode) (op0, op1, op2);
20682 case IX86_BUILTIN_RSQRTF:
20683 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
20685 case IX86_BUILTIN_SQRTSS:
20686 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
20687 case IX86_BUILTIN_RSQRTSS:
20688 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
20689 case IX86_BUILTIN_RCPSS:
20690 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
20692 case IX86_BUILTIN_LOADUPS:
20693 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
20695 case IX86_BUILTIN_STOREUPS:
20696 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
20698 case IX86_BUILTIN_LOADHPS:
20699 case IX86_BUILTIN_LOADLPS:
20700 case IX86_BUILTIN_LOADHPD:
20701 case IX86_BUILTIN_LOADLPD:
20702 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
20703 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
20704 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
20705 : CODE_FOR_sse2_loadlpd);
20706 arg0 = CALL_EXPR_ARG (exp, 0);
20707 arg1 = CALL_EXPR_ARG (exp, 1);
20708 op0 = expand_normal (arg0);
20709 op1 = expand_normal (arg1);
20710 tmode = insn_data[icode].operand[0].mode;
20711 mode0 = insn_data[icode].operand[1].mode;
20712 mode1 = insn_data[icode].operand[2].mode;
20714 op0 = force_reg (mode0, op0);
20715 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
20716 if (optimize || target == 0
20717 || GET_MODE (target) != tmode
20718 || !register_operand (target, tmode))
20719 target = gen_reg_rtx (tmode);
20720 pat = GEN_FCN (icode) (target, op0, op1);
20726 case IX86_BUILTIN_STOREHPS:
20727 case IX86_BUILTIN_STORELPS:
20728 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
20729 : CODE_FOR_sse_storelps);
20730 arg0 = CALL_EXPR_ARG (exp, 0);
20731 arg1 = CALL_EXPR_ARG (exp, 1);
20732 op0 = expand_normal (arg0);
20733 op1 = expand_normal (arg1);
20734 mode0 = insn_data[icode].operand[0].mode;
20735 mode1 = insn_data[icode].operand[1].mode;
20737 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20738 op1 = force_reg (mode1, op1);
20740 pat = GEN_FCN (icode) (op0, op1);
20746 case IX86_BUILTIN_MOVNTPS:
20747 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
20748 case IX86_BUILTIN_MOVNTQ:
20749 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
20751 case IX86_BUILTIN_LDMXCSR:
20752 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
20753 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20754 emit_move_insn (target, op0);
20755 emit_insn (gen_sse_ldmxcsr (target));
20758 case IX86_BUILTIN_STMXCSR:
20759 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20760 emit_insn (gen_sse_stmxcsr (target));
20761 return copy_to_mode_reg (SImode, target);
20763 case IX86_BUILTIN_SHUFPS:
20764 case IX86_BUILTIN_SHUFPD:
20765 icode = (fcode == IX86_BUILTIN_SHUFPS
20766 ? CODE_FOR_sse_shufps
20767 : CODE_FOR_sse2_shufpd);
20768 arg0 = CALL_EXPR_ARG (exp, 0);
20769 arg1 = CALL_EXPR_ARG (exp, 1);
20770 arg2 = CALL_EXPR_ARG (exp, 2);
20771 op0 = expand_normal (arg0);
20772 op1 = expand_normal (arg1);
20773 op2 = expand_normal (arg2);
20774 tmode = insn_data[icode].operand[0].mode;
20775 mode0 = insn_data[icode].operand[1].mode;
20776 mode1 = insn_data[icode].operand[2].mode;
20777 mode2 = insn_data[icode].operand[3].mode;
20779 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20780 op0 = copy_to_mode_reg (mode0, op0);
20781 if ((optimize && !register_operand (op1, mode1))
20782 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
20783 op1 = copy_to_mode_reg (mode1, op1);
20784 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
20786 /* @@@ better error message */
20787 error ("mask must be an immediate");
20788 return gen_reg_rtx (tmode);
20790 if (optimize || target == 0
20791 || GET_MODE (target) != tmode
20792 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20793 target = gen_reg_rtx (tmode);
20794 pat = GEN_FCN (icode) (target, op0, op1, op2);
20800 case IX86_BUILTIN_PSHUFW:
20801 case IX86_BUILTIN_PSHUFD:
20802 case IX86_BUILTIN_PSHUFHW:
20803 case IX86_BUILTIN_PSHUFLW:
20804 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
20805 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
20806 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
20807 : CODE_FOR_mmx_pshufw);
20808 arg0 = CALL_EXPR_ARG (exp, 0);
20809 arg1 = CALL_EXPR_ARG (exp, 1);
20810 op0 = expand_normal (arg0);
20811 op1 = expand_normal (arg1);
20812 tmode = insn_data[icode].operand[0].mode;
20813 mode1 = insn_data[icode].operand[1].mode;
20814 mode2 = insn_data[icode].operand[2].mode;
20816 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20817 op0 = copy_to_mode_reg (mode1, op0);
20818 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20820 /* @@@ better error message */
20821 error ("mask must be an immediate");
20825 || GET_MODE (target) != tmode
20826 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20827 target = gen_reg_rtx (tmode);
20828 pat = GEN_FCN (icode) (target, op0, op1);
20834 case IX86_BUILTIN_PSLLW:
20835 case IX86_BUILTIN_PSLLWI:
20836 icode = CODE_FOR_mmx_ashlv4hi3;
20838 case IX86_BUILTIN_PSLLD:
20839 case IX86_BUILTIN_PSLLDI:
20840 icode = CODE_FOR_mmx_ashlv2si3;
20842 case IX86_BUILTIN_PSLLQ:
20843 case IX86_BUILTIN_PSLLQI:
20844 icode = CODE_FOR_mmx_ashlv1di3;
20846 case IX86_BUILTIN_PSRAW:
20847 case IX86_BUILTIN_PSRAWI:
20848 icode = CODE_FOR_mmx_ashrv4hi3;
20850 case IX86_BUILTIN_PSRAD:
20851 case IX86_BUILTIN_PSRADI:
20852 icode = CODE_FOR_mmx_ashrv2si3;
20854 case IX86_BUILTIN_PSRLW:
20855 case IX86_BUILTIN_PSRLWI:
20856 icode = CODE_FOR_mmx_lshrv4hi3;
20858 case IX86_BUILTIN_PSRLD:
20859 case IX86_BUILTIN_PSRLDI:
20860 icode = CODE_FOR_mmx_lshrv2si3;
20862 case IX86_BUILTIN_PSRLQ:
20863 case IX86_BUILTIN_PSRLQI:
20864 icode = CODE_FOR_mmx_lshrv1di3;
20867 case IX86_BUILTIN_PSLLW128:
20868 case IX86_BUILTIN_PSLLWI128:
20869 icode = CODE_FOR_ashlv8hi3;
20871 case IX86_BUILTIN_PSLLD128:
20872 case IX86_BUILTIN_PSLLDI128:
20873 icode = CODE_FOR_ashlv4si3;
20875 case IX86_BUILTIN_PSLLQ128:
20876 case IX86_BUILTIN_PSLLQI128:
20877 icode = CODE_FOR_ashlv2di3;
20879 case IX86_BUILTIN_PSRAW128:
20880 case IX86_BUILTIN_PSRAWI128:
20881 icode = CODE_FOR_ashrv8hi3;
20883 case IX86_BUILTIN_PSRAD128:
20884 case IX86_BUILTIN_PSRADI128:
20885 icode = CODE_FOR_ashrv4si3;
20887 case IX86_BUILTIN_PSRLW128:
20888 case IX86_BUILTIN_PSRLWI128:
20889 icode = CODE_FOR_lshrv8hi3;
20891 case IX86_BUILTIN_PSRLD128:
20892 case IX86_BUILTIN_PSRLDI128:
20893 icode = CODE_FOR_lshrv4si3;
20895 case IX86_BUILTIN_PSRLQ128:
20896 case IX86_BUILTIN_PSRLQI128:
20897 icode = CODE_FOR_lshrv2di3;
20900 arg0 = CALL_EXPR_ARG (exp, 0);
20901 arg1 = CALL_EXPR_ARG (exp, 1);
20902 op0 = expand_normal (arg0);
20903 op1 = expand_normal (arg1);
20905 tmode = insn_data[icode].operand[0].mode;
20906 mode1 = insn_data[icode].operand[1].mode;
20908 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20909 op0 = copy_to_reg (op0);
20911 if (!CONST_INT_P (op1))
20912 op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
20914 if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
20915 op1 = copy_to_reg (op1);
20917 target = gen_reg_rtx (tmode);
20918 pat = GEN_FCN (icode) (target, op0, op1);
20924 case IX86_BUILTIN_PSLLDQI128:
20925 case IX86_BUILTIN_PSRLDQI128:
20926 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
20927 : CODE_FOR_sse2_lshrti3);
20928 arg0 = CALL_EXPR_ARG (exp, 0);
20929 arg1 = CALL_EXPR_ARG (exp, 1);
20930 op0 = expand_normal (arg0);
20931 op1 = expand_normal (arg1);
20932 tmode = insn_data[icode].operand[0].mode;
20933 mode1 = insn_data[icode].operand[1].mode;
20934 mode2 = insn_data[icode].operand[2].mode;
20936 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20938 op0 = copy_to_reg (op0);
20939 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
20941 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20943 error ("shift must be an immediate");
20946 target = gen_reg_rtx (V2DImode);
20947 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
20954 case IX86_BUILTIN_FEMMS:
20955 emit_insn (gen_mmx_femms ());
20958 case IX86_BUILTIN_PAVGUSB:
20959 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
20961 case IX86_BUILTIN_PF2ID:
20962 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
20964 case IX86_BUILTIN_PFACC:
20965 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
20967 case IX86_BUILTIN_PFADD:
20968 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
20970 case IX86_BUILTIN_PFCMPEQ:
20971 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
20973 case IX86_BUILTIN_PFCMPGE:
20974 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
20976 case IX86_BUILTIN_PFCMPGT:
20977 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
20979 case IX86_BUILTIN_PFMAX:
20980 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
20982 case IX86_BUILTIN_PFMIN:
20983 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
20985 case IX86_BUILTIN_PFMUL:
20986 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
20988 case IX86_BUILTIN_PFRCP:
20989 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
20991 case IX86_BUILTIN_PFRCPIT1:
20992 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
20994 case IX86_BUILTIN_PFRCPIT2:
20995 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
20997 case IX86_BUILTIN_PFRSQIT1:
20998 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
21000 case IX86_BUILTIN_PFRSQRT:
21001 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
21003 case IX86_BUILTIN_PFSUB:
21004 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
21006 case IX86_BUILTIN_PFSUBR:
21007 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
21009 case IX86_BUILTIN_PI2FD:
21010 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
21012 case IX86_BUILTIN_PMULHRW:
21013 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
21015 case IX86_BUILTIN_PF2IW:
21016 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
21018 case IX86_BUILTIN_PFNACC:
21019 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
21021 case IX86_BUILTIN_PFPNACC:
21022 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
21024 case IX86_BUILTIN_PI2FW:
21025 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
21027 case IX86_BUILTIN_PSWAPDSI:
21028 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
21030 case IX86_BUILTIN_PSWAPDSF:
21031 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
21033 case IX86_BUILTIN_SQRTSD:
21034 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
21035 case IX86_BUILTIN_LOADUPD:
21036 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
21037 case IX86_BUILTIN_STOREUPD:
21038 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
21040 case IX86_BUILTIN_MFENCE:
21041 emit_insn (gen_sse2_mfence ());
21043 case IX86_BUILTIN_LFENCE:
21044 emit_insn (gen_sse2_lfence ());
21047 case IX86_BUILTIN_CLFLUSH:
21048 arg0 = CALL_EXPR_ARG (exp, 0);
21049 op0 = expand_normal (arg0);
21050 icode = CODE_FOR_sse2_clflush;
21051 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21052 op0 = copy_to_mode_reg (Pmode, op0);
21054 emit_insn (gen_sse2_clflush (op0));
21057 case IX86_BUILTIN_MOVNTPD:
21058 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
21059 case IX86_BUILTIN_MOVNTDQ:
21060 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
21061 case IX86_BUILTIN_MOVNTI:
21062 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
21064 case IX86_BUILTIN_LOADDQU:
21065 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
21066 case IX86_BUILTIN_STOREDQU:
21067 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
21069 case IX86_BUILTIN_MONITOR:
21070 arg0 = CALL_EXPR_ARG (exp, 0);
21071 arg1 = CALL_EXPR_ARG (exp, 1);
21072 arg2 = CALL_EXPR_ARG (exp, 2);
21073 op0 = expand_normal (arg0);
21074 op1 = expand_normal (arg1);
21075 op2 = expand_normal (arg2);
21077 op0 = copy_to_mode_reg (Pmode, op0);
21079 op1 = copy_to_mode_reg (SImode, op1);
21081 op2 = copy_to_mode_reg (SImode, op2);
21083 emit_insn (gen_sse3_monitor (op0, op1, op2));
21085 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
21088 case IX86_BUILTIN_MWAIT:
21089 arg0 = CALL_EXPR_ARG (exp, 0);
21090 arg1 = CALL_EXPR_ARG (exp, 1);
21091 op0 = expand_normal (arg0);
21092 op1 = expand_normal (arg1);
21094 op0 = copy_to_mode_reg (SImode, op0);
21096 op1 = copy_to_mode_reg (SImode, op1);
21097 emit_insn (gen_sse3_mwait (op0, op1));
21100 case IX86_BUILTIN_LDDQU:
21101 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
21104 case IX86_BUILTIN_PALIGNR:
21105 case IX86_BUILTIN_PALIGNR128:
21106 if (fcode == IX86_BUILTIN_PALIGNR)
21108 icode = CODE_FOR_ssse3_palignrdi;
21113 icode = CODE_FOR_ssse3_palignrti;
21116 arg0 = CALL_EXPR_ARG (exp, 0);
21117 arg1 = CALL_EXPR_ARG (exp, 1);
21118 arg2 = CALL_EXPR_ARG (exp, 2);
21119 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21120 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21121 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21122 tmode = insn_data[icode].operand[0].mode;
21123 mode1 = insn_data[icode].operand[1].mode;
21124 mode2 = insn_data[icode].operand[2].mode;
21125 mode3 = insn_data[icode].operand[3].mode;
21127 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21129 op0 = copy_to_reg (op0);
21130 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
21132 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21134 op1 = copy_to_reg (op1);
21135 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
21137 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21139 error ("shift must be an immediate");
21142 target = gen_reg_rtx (mode);
21143 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
21150 case IX86_BUILTIN_MOVNTDQA:
21151 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
21154 case IX86_BUILTIN_MOVNTSD:
21155 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
21157 case IX86_BUILTIN_MOVNTSS:
21158 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
21160 case IX86_BUILTIN_INSERTQ:
21161 case IX86_BUILTIN_EXTRQ:
21162 icode = (fcode == IX86_BUILTIN_EXTRQ
21163 ? CODE_FOR_sse4a_extrq
21164 : CODE_FOR_sse4a_insertq);
21165 arg0 = CALL_EXPR_ARG (exp, 0);
21166 arg1 = CALL_EXPR_ARG (exp, 1);
21167 op0 = expand_normal (arg0);
21168 op1 = expand_normal (arg1);
21169 tmode = insn_data[icode].operand[0].mode;
21170 mode1 = insn_data[icode].operand[1].mode;
21171 mode2 = insn_data[icode].operand[2].mode;
21172 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21173 op0 = copy_to_mode_reg (mode1, op0);
21174 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21175 op1 = copy_to_mode_reg (mode2, op1);
21176 if (optimize || target == 0
21177 || GET_MODE (target) != tmode
21178 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21179 target = gen_reg_rtx (tmode);
21180 pat = GEN_FCN (icode) (target, op0, op1);
21186 case IX86_BUILTIN_EXTRQI:
21187 icode = CODE_FOR_sse4a_extrqi;
21188 arg0 = CALL_EXPR_ARG (exp, 0);
21189 arg1 = CALL_EXPR_ARG (exp, 1);
21190 arg2 = CALL_EXPR_ARG (exp, 2);
21191 op0 = expand_normal (arg0);
21192 op1 = expand_normal (arg1);
21193 op2 = expand_normal (arg2);
21194 tmode = insn_data[icode].operand[0].mode;
21195 mode1 = insn_data[icode].operand[1].mode;
21196 mode2 = insn_data[icode].operand[2].mode;
21197 mode3 = insn_data[icode].operand[3].mode;
21198 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21199 op0 = copy_to_mode_reg (mode1, op0);
21200 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21202 error ("index mask must be an immediate");
21203 return gen_reg_rtx (tmode);
21205 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21207 error ("length mask must be an immediate");
21208 return gen_reg_rtx (tmode);
21210 if (optimize || target == 0
21211 || GET_MODE (target) != tmode
21212 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21213 target = gen_reg_rtx (tmode);
21214 pat = GEN_FCN (icode) (target, op0, op1, op2);
21220 case IX86_BUILTIN_INSERTQI:
21221 icode = CODE_FOR_sse4a_insertqi;
21222 arg0 = CALL_EXPR_ARG (exp, 0);
21223 arg1 = CALL_EXPR_ARG (exp, 1);
21224 arg2 = CALL_EXPR_ARG (exp, 2);
21225 arg3 = CALL_EXPR_ARG (exp, 3);
21226 op0 = expand_normal (arg0);
21227 op1 = expand_normal (arg1);
21228 op2 = expand_normal (arg2);
21229 op3 = expand_normal (arg3);
21230 tmode = insn_data[icode].operand[0].mode;
21231 mode1 = insn_data[icode].operand[1].mode;
21232 mode2 = insn_data[icode].operand[2].mode;
21233 mode3 = insn_data[icode].operand[3].mode;
21234 mode4 = insn_data[icode].operand[4].mode;
21236 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21237 op0 = copy_to_mode_reg (mode1, op0);
21239 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21240 op1 = copy_to_mode_reg (mode2, op1);
21242 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21244 error ("index mask must be an immediate");
21245 return gen_reg_rtx (tmode);
21247 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
21249 error ("length mask must be an immediate");
21250 return gen_reg_rtx (tmode);
21252 if (optimize || target == 0
21253 || GET_MODE (target) != tmode
21254 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21255 target = gen_reg_rtx (tmode);
21256 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
21262 case IX86_BUILTIN_VEC_INIT_V2SI:
21263 case IX86_BUILTIN_VEC_INIT_V4HI:
21264 case IX86_BUILTIN_VEC_INIT_V8QI:
21265 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21267 case IX86_BUILTIN_VEC_EXT_V2DF:
21268 case IX86_BUILTIN_VEC_EXT_V2DI:
21269 case IX86_BUILTIN_VEC_EXT_V4SF:
21270 case IX86_BUILTIN_VEC_EXT_V4SI:
21271 case IX86_BUILTIN_VEC_EXT_V8HI:
21272 case IX86_BUILTIN_VEC_EXT_V2SI:
21273 case IX86_BUILTIN_VEC_EXT_V4HI:
21274 case IX86_BUILTIN_VEC_EXT_V16QI:
21275 return ix86_expand_vec_ext_builtin (exp, target);
21277 case IX86_BUILTIN_VEC_SET_V2DI:
21278 case IX86_BUILTIN_VEC_SET_V4SF:
21279 case IX86_BUILTIN_VEC_SET_V4SI:
21280 case IX86_BUILTIN_VEC_SET_V8HI:
21281 case IX86_BUILTIN_VEC_SET_V4HI:
21282 case IX86_BUILTIN_VEC_SET_V16QI:
21283 return ix86_expand_vec_set_builtin (exp);
21285 case IX86_BUILTIN_INFQ:
21287 REAL_VALUE_TYPE inf;
21291 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21293 tmp = validize_mem (force_const_mem (mode, tmp));
21296 target = gen_reg_rtx (mode);
21298 emit_move_insn (target, tmp);
21302 case IX86_BUILTIN_FABSQ:
21303 return ix86_expand_unop_builtin (CODE_FOR_abstf2, exp, target, 0);
21305 case IX86_BUILTIN_COPYSIGNQ:
21306 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
21312 for (i = 0, d = bdesc_sse_3arg;
21313 i < ARRAY_SIZE (bdesc_sse_3arg);
21315 if (d->code == fcode)
21316 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
21319 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21320 if (d->code == fcode)
21322 /* Compares are treated specially. */
21323 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
21324 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
21325 || d->icode == CODE_FOR_sse2_maskcmpv2df3
21326 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
21327 return ix86_expand_sse_compare (d, exp, target);
21329 return ix86_expand_binop_builtin (d->icode, exp, target);
21332 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
21333 if (d->code == fcode)
21334 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
21336 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21337 if (d->code == fcode)
21338 return ix86_expand_sse_comi (d, exp, target);
21340 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
21341 if (d->code == fcode)
21342 return ix86_expand_sse_ptest (d, exp, target);
21344 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
21345 if (d->code == fcode)
21346 return ix86_expand_crc32 (d->icode, exp, target);
21348 for (i = 0, d = bdesc_pcmpestr;
21349 i < ARRAY_SIZE (bdesc_pcmpestr);
21351 if (d->code == fcode)
21352 return ix86_expand_sse_pcmpestr (d, exp, target);
21354 for (i = 0, d = bdesc_pcmpistr;
21355 i < ARRAY_SIZE (bdesc_pcmpistr);
21357 if (d->code == fcode)
21358 return ix86_expand_sse_pcmpistr (d, exp, target);
21360 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21361 if (d->code == fcode)
21362 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21363 (enum multi_arg_type)d->flag,
21366 gcc_unreachable ();
21369 /* Returns a function decl for a vectorized version of the builtin function
21370 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21371 if it is not available. */
21374 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21377 enum machine_mode in_mode, out_mode;
21380 if (TREE_CODE (type_out) != VECTOR_TYPE
21381 || TREE_CODE (type_in) != VECTOR_TYPE)
21384 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21385 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21386 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21387 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21391 case BUILT_IN_SQRT:
21392 if (out_mode == DFmode && out_n == 2
21393 && in_mode == DFmode && in_n == 2)
21394 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21397 case BUILT_IN_SQRTF:
21398 if (out_mode == SFmode && out_n == 4
21399 && in_mode == SFmode && in_n == 4)
21400 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21403 case BUILT_IN_LRINT:
21404 if (out_mode == SImode && out_n == 4
21405 && in_mode == DFmode && in_n == 2)
21406 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21409 case BUILT_IN_LRINTF:
21410 if (out_mode == SImode && out_n == 4
21411 && in_mode == SFmode && in_n == 4)
21412 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21419 /* Dispatch to a handler for a vectorization library. */
21420 if (ix86_veclib_handler)
21421 return (*ix86_veclib_handler)(fn, type_out, type_in);
21426 /* Handler for an SVML-style interface to
21427 a library with vectorized intrinsics. */
21430 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
21433 tree fntype, new_fndecl, args;
21436 enum machine_mode el_mode, in_mode;
21439 /* The SVML is suitable for unsafe math only. */
21440 if (!flag_unsafe_math_optimizations)
21443 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21444 n = TYPE_VECTOR_SUBPARTS (type_out);
21445 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21446 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21447 if (el_mode != in_mode
21455 case BUILT_IN_LOG10:
21457 case BUILT_IN_TANH:
21459 case BUILT_IN_ATAN:
21460 case BUILT_IN_ATAN2:
21461 case BUILT_IN_ATANH:
21462 case BUILT_IN_CBRT:
21463 case BUILT_IN_SINH:
21465 case BUILT_IN_ASINH:
21466 case BUILT_IN_ASIN:
21467 case BUILT_IN_COSH:
21469 case BUILT_IN_ACOSH:
21470 case BUILT_IN_ACOS:
21471 if (el_mode != DFmode || n != 2)
21475 case BUILT_IN_EXPF:
21476 case BUILT_IN_LOGF:
21477 case BUILT_IN_LOG10F:
21478 case BUILT_IN_POWF:
21479 case BUILT_IN_TANHF:
21480 case BUILT_IN_TANF:
21481 case BUILT_IN_ATANF:
21482 case BUILT_IN_ATAN2F:
21483 case BUILT_IN_ATANHF:
21484 case BUILT_IN_CBRTF:
21485 case BUILT_IN_SINHF:
21486 case BUILT_IN_SINF:
21487 case BUILT_IN_ASINHF:
21488 case BUILT_IN_ASINF:
21489 case BUILT_IN_COSHF:
21490 case BUILT_IN_COSF:
21491 case BUILT_IN_ACOSHF:
21492 case BUILT_IN_ACOSF:
21493 if (el_mode != SFmode || n != 4)
21501 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21503 if (fn == BUILT_IN_LOGF)
21504 strcpy (name, "vmlsLn4");
21505 else if (fn == BUILT_IN_LOG)
21506 strcpy (name, "vmldLn2");
21509 sprintf (name, "vmls%s", bname+10);
21510 name[strlen (name)-1] = '4';
21513 sprintf (name, "vmld%s2", bname+10);
21515 /* Convert to uppercase. */
21519 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21520 args = TREE_CHAIN (args))
21524 fntype = build_function_type_list (type_out, type_in, NULL);
21526 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21528 /* Build a function declaration for the vectorized function. */
21529 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21530 TREE_PUBLIC (new_fndecl) = 1;
21531 DECL_EXTERNAL (new_fndecl) = 1;
21532 DECL_IS_NOVOPS (new_fndecl) = 1;
21533 TREE_READONLY (new_fndecl) = 1;
21538 /* Handler for an ACML-style interface to
21539 a library with vectorized intrinsics. */
21542 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21544 char name[20] = "__vr.._";
21545 tree fntype, new_fndecl, args;
21548 enum machine_mode el_mode, in_mode;
21551 /* The ACML is 64bits only and suitable for unsafe math only as
21552 it does not correctly support parts of IEEE with the required
21553 precision such as denormals. */
21555 || !flag_unsafe_math_optimizations)
21558 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21559 n = TYPE_VECTOR_SUBPARTS (type_out);
21560 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21561 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21562 if (el_mode != in_mode
21572 case BUILT_IN_LOG2:
21573 case BUILT_IN_LOG10:
21576 if (el_mode != DFmode
21581 case BUILT_IN_SINF:
21582 case BUILT_IN_COSF:
21583 case BUILT_IN_EXPF:
21584 case BUILT_IN_POWF:
21585 case BUILT_IN_LOGF:
21586 case BUILT_IN_LOG2F:
21587 case BUILT_IN_LOG10F:
21590 if (el_mode != SFmode
21599 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21600 sprintf (name + 7, "%s", bname+10);
21603 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21604 args = TREE_CHAIN (args))
21608 fntype = build_function_type_list (type_out, type_in, NULL);
21610 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21612 /* Build a function declaration for the vectorized function. */
21613 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21614 TREE_PUBLIC (new_fndecl) = 1;
21615 DECL_EXTERNAL (new_fndecl) = 1;
21616 DECL_IS_NOVOPS (new_fndecl) = 1;
21617 TREE_READONLY (new_fndecl) = 1;
21623 /* Returns a decl of a function that implements conversion of the
21624 input vector of type TYPE, or NULL_TREE if it is not available. */
21627 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21629 if (TREE_CODE (type) != VECTOR_TYPE)
21635 switch (TYPE_MODE (type))
21638 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21643 case FIX_TRUNC_EXPR:
21644 switch (TYPE_MODE (type))
21647 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21657 /* Returns a code for a target-specific builtin that implements
21658 reciprocal of the function, or NULL_TREE if not available. */
21661 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21662 bool sqrt ATTRIBUTE_UNUSED)
21664 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21665 && flag_finite_math_only && !flag_trapping_math
21666 && flag_unsafe_math_optimizations))
21670 /* Machine dependent builtins. */
21673 /* Vectorized version of sqrt to rsqrt conversion. */
21674 case IX86_BUILTIN_SQRTPS_NR:
21675 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21681 /* Normal builtins. */
21684 /* Sqrt to rsqrt conversion. */
21685 case BUILT_IN_SQRTF:
21686 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21693 /* Store OPERAND to the memory after reload is completed. This means
21694 that we can't easily use assign_stack_local. */
21696 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21700 gcc_assert (reload_completed);
21701 if (TARGET_RED_ZONE)
21703 result = gen_rtx_MEM (mode,
21704 gen_rtx_PLUS (Pmode,
21706 GEN_INT (-RED_ZONE_SIZE)));
21707 emit_move_insn (result, operand);
21709 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21715 operand = gen_lowpart (DImode, operand);
21719 gen_rtx_SET (VOIDmode,
21720 gen_rtx_MEM (DImode,
21721 gen_rtx_PRE_DEC (DImode,
21722 stack_pointer_rtx)),
21726 gcc_unreachable ();
21728 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21737 split_di (&operand, 1, operands, operands + 1);
21739 gen_rtx_SET (VOIDmode,
21740 gen_rtx_MEM (SImode,
21741 gen_rtx_PRE_DEC (Pmode,
21742 stack_pointer_rtx)),
21745 gen_rtx_SET (VOIDmode,
21746 gen_rtx_MEM (SImode,
21747 gen_rtx_PRE_DEC (Pmode,
21748 stack_pointer_rtx)),
21753 /* Store HImodes as SImodes. */
21754 operand = gen_lowpart (SImode, operand);
21758 gen_rtx_SET (VOIDmode,
21759 gen_rtx_MEM (GET_MODE (operand),
21760 gen_rtx_PRE_DEC (SImode,
21761 stack_pointer_rtx)),
21765 gcc_unreachable ();
21767 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21772 /* Free operand from the memory. */
21774 ix86_free_from_memory (enum machine_mode mode)
21776 if (!TARGET_RED_ZONE)
21780 if (mode == DImode || TARGET_64BIT)
21784 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21785 to pop or add instruction if registers are available. */
21786 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21787 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21792 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21793 QImode must go into class Q_REGS.
21794 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21795 movdf to do mem-to-mem moves through integer regs. */
21797 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
21799 enum machine_mode mode = GET_MODE (x);
21801 /* We're only allowed to return a subclass of CLASS. Many of the
21802 following checks fail for NO_REGS, so eliminate that early. */
21803 if (regclass == NO_REGS)
21806 /* All classes can load zeros. */
21807 if (x == CONST0_RTX (mode))
21810 /* Force constants into memory if we are loading a (nonzero) constant into
21811 an MMX or SSE register. This is because there are no MMX/SSE instructions
21812 to load from a constant. */
21814 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
21817 /* Prefer SSE regs only, if we can use them for math. */
21818 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
21819 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
21821 /* Floating-point constants need more complex checks. */
21822 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
21824 /* General regs can load everything. */
21825 if (reg_class_subset_p (regclass, GENERAL_REGS))
21828 /* Floats can load 0 and 1 plus some others. Note that we eliminated
21829 zero above. We only want to wind up preferring 80387 registers if
21830 we plan on doing computation with them. */
21832 && standard_80387_constant_p (x))
21834 /* Limit class to non-sse. */
21835 if (regclass == FLOAT_SSE_REGS)
21837 if (regclass == FP_TOP_SSE_REGS)
21839 if (regclass == FP_SECOND_SSE_REGS)
21840 return FP_SECOND_REG;
21841 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
21848 /* Generally when we see PLUS here, it's the function invariant
21849 (plus soft-fp const_int). Which can only be computed into general
21851 if (GET_CODE (x) == PLUS)
21852 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
21854 /* QImode constants are easy to load, but non-constant QImode data
21855 must go into Q_REGS. */
21856 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
21858 if (reg_class_subset_p (regclass, Q_REGS))
21860 if (reg_class_subset_p (Q_REGS, regclass))
21868 /* Discourage putting floating-point values in SSE registers unless
21869 SSE math is being used, and likewise for the 387 registers. */
21871 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
21873 enum machine_mode mode = GET_MODE (x);
21875 /* Restrict the output reload class to the register bank that we are doing
21876 math on. If we would like not to return a subset of CLASS, reject this
21877 alternative: if reload cannot do this, it will still use its choice. */
21878 mode = GET_MODE (x);
21879 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
21880 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
21882 if (X87_FLOAT_MODE_P (mode))
21884 if (regclass == FP_TOP_SSE_REGS)
21886 else if (regclass == FP_SECOND_SSE_REGS)
21887 return FP_SECOND_REG;
21889 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
21895 /* If we are copying between general and FP registers, we need a memory
21896 location. The same is true for SSE and MMX registers.
21898 To optimize register_move_cost performance, allow inline variant.
21900 The macro can't work reliably when one of the CLASSES is class containing
21901 registers from multiple units (SSE, MMX, integer). We avoid this by never
21902 combining those units in single alternative in the machine description.
21903 Ensure that this constraint holds to avoid unexpected surprises.
21905 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
21906 enforce these sanity checks. */
21909 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21910 enum machine_mode mode, int strict)
21912 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
21913 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
21914 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
21915 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
21916 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
21917 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
21919 gcc_assert (!strict);
21923 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
21926 /* ??? This is a lie. We do have moves between mmx/general, and for
21927 mmx/sse2. But by saying we need secondary memory we discourage the
21928 register allocator from using the mmx registers unless needed. */
21929 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
21932 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
21934 /* SSE1 doesn't have any direct moves from other classes. */
21938 /* If the target says that inter-unit moves are more expensive
21939 than moving through memory, then don't generate them. */
21940 if (!TARGET_INTER_UNIT_MOVES)
21943 /* Between SSE and general, we have moves no larger than word size. */
21944 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
21952 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21953 enum machine_mode mode, int strict)
21955 return inline_secondary_memory_needed (class1, class2, mode, strict);
21958 /* Return true if the registers in CLASS cannot represent the change from
21959 modes FROM to TO. */
21962 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
21963 enum reg_class regclass)
21968 /* x87 registers can't do subreg at all, as all values are reformatted
21969 to extended precision. */
21970 if (MAYBE_FLOAT_CLASS_P (regclass))
21973 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
21975 /* Vector registers do not support QI or HImode loads. If we don't
21976 disallow a change to these modes, reload will assume it's ok to
21977 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
21978 the vec_dupv4hi pattern. */
21979 if (GET_MODE_SIZE (from) < 4)
21982 /* Vector registers do not support subreg with nonzero offsets, which
21983 are otherwise valid for integer registers. Since we can't see
21984 whether we have a nonzero offset from here, prohibit all
21985 nonparadoxical subregs changing size. */
21986 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
21993 /* Return the cost of moving data of mode M between a
21994 register and memory. A value of 2 is the default; this cost is
21995 relative to those in `REGISTER_MOVE_COST'.
21997 This function is used extensively by register_move_cost that is used to
21998 build tables at startup. Make it inline in this case.
21999 When IN is 2, return maximum of in and out move cost.
22001 If moving between registers and memory is more expensive than
22002 between two registers, you should define this macro to express the
22005 Model also increased moving costs of QImode registers in non
22009 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
22013 if (FLOAT_CLASS_P (regclass))
22031 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
22032 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
22034 if (SSE_CLASS_P (regclass))
22037 switch (GET_MODE_SIZE (mode))
22052 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
22053 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
22055 if (MMX_CLASS_P (regclass))
22058 switch (GET_MODE_SIZE (mode))
22070 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
22071 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
22073 switch (GET_MODE_SIZE (mode))
22076 if (Q_CLASS_P (regclass) || TARGET_64BIT)
22079 return ix86_cost->int_store[0];
22080 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
22081 cost = ix86_cost->movzbl_load;
22083 cost = ix86_cost->int_load[0];
22085 return MAX (cost, ix86_cost->int_store[0]);
22091 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
22093 return ix86_cost->movzbl_load;
22095 return ix86_cost->int_store[0] + 4;
22100 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
22101 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
22103 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
22104 if (mode == TFmode)
22107 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
22109 cost = ix86_cost->int_load[2];
22111 cost = ix86_cost->int_store[2];
22112 return (cost * (((int) GET_MODE_SIZE (mode)
22113 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
22118 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
22120 return inline_memory_move_cost (mode, regclass, in);
22124 /* Return the cost of moving data from a register in class CLASS1 to
22125 one in class CLASS2.
22127 It is not required that the cost always equal 2 when FROM is the same as TO;
22128 on some machines it is expensive to move between registers if they are not
22129 general registers. */
22132 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22133 enum reg_class class2)
22135 /* In case we require secondary memory, compute cost of the store followed
22136 by load. In order to avoid bad register allocation choices, we need
22137 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22139 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22143 cost += inline_memory_move_cost (mode, class1, 2);
22144 cost += inline_memory_move_cost (mode, class2, 2);
22146 /* In case of copying from general_purpose_register we may emit multiple
22147 stores followed by single load causing memory size mismatch stall.
22148 Count this as arbitrarily high cost of 20. */
22149 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22152 /* In the case of FP/MMX moves, the registers actually overlap, and we
22153 have to switch modes in order to treat them differently. */
22154 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22155 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22161 /* Moves between SSE/MMX and integer unit are expensive. */
22162 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22163 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22165 /* ??? By keeping returned value relatively high, we limit the number
22166 of moves between integer and MMX/SSE registers for all targets.
22167 Additionally, high value prevents problem with x86_modes_tieable_p(),
22168 where integer modes in MMX/SSE registers are not tieable
22169 because of missing QImode and HImode moves to, from or between
22170 MMX/SSE registers. */
22171 return MAX (8, ix86_cost->mmxsse_to_integer);
22173 if (MAYBE_FLOAT_CLASS_P (class1))
22174 return ix86_cost->fp_move;
22175 if (MAYBE_SSE_CLASS_P (class1))
22176 return ix86_cost->sse_move;
22177 if (MAYBE_MMX_CLASS_P (class1))
22178 return ix86_cost->mmx_move;
22182 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22185 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22187 /* Flags and only flags can only hold CCmode values. */
22188 if (CC_REGNO_P (regno))
22189 return GET_MODE_CLASS (mode) == MODE_CC;
22190 if (GET_MODE_CLASS (mode) == MODE_CC
22191 || GET_MODE_CLASS (mode) == MODE_RANDOM
22192 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22194 if (FP_REGNO_P (regno))
22195 return VALID_FP_MODE_P (mode);
22196 if (SSE_REGNO_P (regno))
22198 /* We implement the move patterns for all vector modes into and
22199 out of SSE registers, even when no operation instructions
22201 return (VALID_SSE_REG_MODE (mode)
22202 || VALID_SSE2_REG_MODE (mode)
22203 || VALID_MMX_REG_MODE (mode)
22204 || VALID_MMX_REG_MODE_3DNOW (mode));
22206 if (MMX_REGNO_P (regno))
22208 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22209 so if the register is available at all, then we can move data of
22210 the given mode into or out of it. */
22211 return (VALID_MMX_REG_MODE (mode)
22212 || VALID_MMX_REG_MODE_3DNOW (mode));
22215 if (mode == QImode)
22217 /* Take care for QImode values - they can be in non-QI regs,
22218 but then they do cause partial register stalls. */
22219 if (regno < 4 || TARGET_64BIT)
22221 if (!TARGET_PARTIAL_REG_STALL)
22223 return reload_in_progress || reload_completed;
22225 /* We handle both integer and floats in the general purpose registers. */
22226 else if (VALID_INT_MODE_P (mode))
22228 else if (VALID_FP_MODE_P (mode))
22230 else if (VALID_DFP_MODE_P (mode))
22232 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22233 on to use that value in smaller contexts, this can easily force a
22234 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22235 supporting DImode, allow it. */
22236 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22242 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22243 tieable integer mode. */
22246 ix86_tieable_integer_mode_p (enum machine_mode mode)
22255 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22258 return TARGET_64BIT;
22265 /* Return true if MODE1 is accessible in a register that can hold MODE2
22266 without copying. That is, all register classes that can hold MODE2
22267 can also hold MODE1. */
22270 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22272 if (mode1 == mode2)
22275 if (ix86_tieable_integer_mode_p (mode1)
22276 && ix86_tieable_integer_mode_p (mode2))
22279 /* MODE2 being XFmode implies fp stack or general regs, which means we
22280 can tie any smaller floating point modes to it. Note that we do not
22281 tie this with TFmode. */
22282 if (mode2 == XFmode)
22283 return mode1 == SFmode || mode1 == DFmode;
22285 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22286 that we can tie it with SFmode. */
22287 if (mode2 == DFmode)
22288 return mode1 == SFmode;
22290 /* If MODE2 is only appropriate for an SSE register, then tie with
22291 any other mode acceptable to SSE registers. */
22292 if (GET_MODE_SIZE (mode2) == 16
22293 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22294 return (GET_MODE_SIZE (mode1) == 16
22295 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22297 /* If MODE2 is appropriate for an MMX register, then tie
22298 with any other mode acceptable to MMX registers. */
22299 if (GET_MODE_SIZE (mode2) == 8
22300 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22301 return (GET_MODE_SIZE (mode1) == 8
22302 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22307 /* Compute a (partial) cost for rtx X. Return true if the complete
22308 cost has been computed, and false if subexpressions should be
22309 scanned. In either case, *TOTAL contains the cost result. */
22312 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22314 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22315 enum machine_mode mode = GET_MODE (x);
22323 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22325 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22327 else if (flag_pic && SYMBOLIC_CONST (x)
22329 || (!GET_CODE (x) != LABEL_REF
22330 && (GET_CODE (x) != SYMBOL_REF
22331 || !SYMBOL_REF_LOCAL_P (x)))))
22338 if (mode == VOIDmode)
22341 switch (standard_80387_constant_p (x))
22346 default: /* Other constants */
22351 /* Start with (MEM (SYMBOL_REF)), since that's where
22352 it'll probably end up. Add a penalty for size. */
22353 *total = (COSTS_N_INSNS (1)
22354 + (flag_pic != 0 && !TARGET_64BIT)
22355 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22361 /* The zero extensions is often completely free on x86_64, so make
22362 it as cheap as possible. */
22363 if (TARGET_64BIT && mode == DImode
22364 && GET_MODE (XEXP (x, 0)) == SImode)
22366 else if (TARGET_ZERO_EXTEND_WITH_AND)
22367 *total = ix86_cost->add;
22369 *total = ix86_cost->movzx;
22373 *total = ix86_cost->movsx;
22377 if (CONST_INT_P (XEXP (x, 1))
22378 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22380 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22383 *total = ix86_cost->add;
22386 if ((value == 2 || value == 3)
22387 && ix86_cost->lea <= ix86_cost->shift_const)
22389 *total = ix86_cost->lea;
22399 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22401 if (CONST_INT_P (XEXP (x, 1)))
22403 if (INTVAL (XEXP (x, 1)) > 32)
22404 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22406 *total = ix86_cost->shift_const * 2;
22410 if (GET_CODE (XEXP (x, 1)) == AND)
22411 *total = ix86_cost->shift_var * 2;
22413 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22418 if (CONST_INT_P (XEXP (x, 1)))
22419 *total = ix86_cost->shift_const;
22421 *total = ix86_cost->shift_var;
22426 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22428 /* ??? SSE scalar cost should be used here. */
22429 *total = ix86_cost->fmul;
22432 else if (X87_FLOAT_MODE_P (mode))
22434 *total = ix86_cost->fmul;
22437 else if (FLOAT_MODE_P (mode))
22439 /* ??? SSE vector cost should be used here. */
22440 *total = ix86_cost->fmul;
22445 rtx op0 = XEXP (x, 0);
22446 rtx op1 = XEXP (x, 1);
22448 if (CONST_INT_P (XEXP (x, 1)))
22450 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22451 for (nbits = 0; value != 0; value &= value - 1)
22455 /* This is arbitrary. */
22458 /* Compute costs correctly for widening multiplication. */
22459 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22460 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22461 == GET_MODE_SIZE (mode))
22463 int is_mulwiden = 0;
22464 enum machine_mode inner_mode = GET_MODE (op0);
22466 if (GET_CODE (op0) == GET_CODE (op1))
22467 is_mulwiden = 1, op1 = XEXP (op1, 0);
22468 else if (CONST_INT_P (op1))
22470 if (GET_CODE (op0) == SIGN_EXTEND)
22471 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22474 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22478 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22481 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22482 + nbits * ix86_cost->mult_bit
22483 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22492 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22493 /* ??? SSE cost should be used here. */
22494 *total = ix86_cost->fdiv;
22495 else if (X87_FLOAT_MODE_P (mode))
22496 *total = ix86_cost->fdiv;
22497 else if (FLOAT_MODE_P (mode))
22498 /* ??? SSE vector cost should be used here. */
22499 *total = ix86_cost->fdiv;
22501 *total = ix86_cost->divide[MODE_INDEX (mode)];
22505 if (GET_MODE_CLASS (mode) == MODE_INT
22506 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22508 if (GET_CODE (XEXP (x, 0)) == PLUS
22509 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22510 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22511 && CONSTANT_P (XEXP (x, 1)))
22513 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22514 if (val == 2 || val == 4 || val == 8)
22516 *total = ix86_cost->lea;
22517 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22518 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22520 *total += rtx_cost (XEXP (x, 1), outer_code);
22524 else if (GET_CODE (XEXP (x, 0)) == MULT
22525 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22527 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22528 if (val == 2 || val == 4 || val == 8)
22530 *total = ix86_cost->lea;
22531 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22532 *total += rtx_cost (XEXP (x, 1), outer_code);
22536 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22538 *total = ix86_cost->lea;
22539 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22540 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22541 *total += rtx_cost (XEXP (x, 1), outer_code);
22548 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22550 /* ??? SSE cost should be used here. */
22551 *total = ix86_cost->fadd;
22554 else if (X87_FLOAT_MODE_P (mode))
22556 *total = ix86_cost->fadd;
22559 else if (FLOAT_MODE_P (mode))
22561 /* ??? SSE vector cost should be used here. */
22562 *total = ix86_cost->fadd;
22570 if (!TARGET_64BIT && mode == DImode)
22572 *total = (ix86_cost->add * 2
22573 + (rtx_cost (XEXP (x, 0), outer_code)
22574 << (GET_MODE (XEXP (x, 0)) != DImode))
22575 + (rtx_cost (XEXP (x, 1), outer_code)
22576 << (GET_MODE (XEXP (x, 1)) != DImode)));
22582 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22584 /* ??? SSE cost should be used here. */
22585 *total = ix86_cost->fchs;
22588 else if (X87_FLOAT_MODE_P (mode))
22590 *total = ix86_cost->fchs;
22593 else if (FLOAT_MODE_P (mode))
22595 /* ??? SSE vector cost should be used here. */
22596 *total = ix86_cost->fchs;
22602 if (!TARGET_64BIT && mode == DImode)
22603 *total = ix86_cost->add * 2;
22605 *total = ix86_cost->add;
22609 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22610 && XEXP (XEXP (x, 0), 1) == const1_rtx
22611 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22612 && XEXP (x, 1) == const0_rtx)
22614 /* This kind of construct is implemented using test[bwl].
22615 Treat it as if we had an AND. */
22616 *total = (ix86_cost->add
22617 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22618 + rtx_cost (const1_rtx, outer_code));
22624 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22629 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22630 /* ??? SSE cost should be used here. */
22631 *total = ix86_cost->fabs;
22632 else if (X87_FLOAT_MODE_P (mode))
22633 *total = ix86_cost->fabs;
22634 else if (FLOAT_MODE_P (mode))
22635 /* ??? SSE vector cost should be used here. */
22636 *total = ix86_cost->fabs;
22640 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22641 /* ??? SSE cost should be used here. */
22642 *total = ix86_cost->fsqrt;
22643 else if (X87_FLOAT_MODE_P (mode))
22644 *total = ix86_cost->fsqrt;
22645 else if (FLOAT_MODE_P (mode))
22646 /* ??? SSE vector cost should be used here. */
22647 *total = ix86_cost->fsqrt;
22651 if (XINT (x, 1) == UNSPEC_TP)
22662 static int current_machopic_label_num;
22664 /* Given a symbol name and its associated stub, write out the
22665 definition of the stub. */
22668 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22670 unsigned int length;
22671 char *binder_name, *symbol_name, lazy_ptr_name[32];
22672 int label = ++current_machopic_label_num;
22674 /* For 64-bit we shouldn't get here. */
22675 gcc_assert (!TARGET_64BIT);
22677 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22678 symb = (*targetm.strip_name_encoding) (symb);
22680 length = strlen (stub);
22681 binder_name = alloca (length + 32);
22682 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22684 length = strlen (symb);
22685 symbol_name = alloca (length + 32);
22686 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22688 sprintf (lazy_ptr_name, "L%d$lz", label);
22691 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22693 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22695 fprintf (file, "%s:\n", stub);
22696 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22700 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22701 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22702 fprintf (file, "\tjmp\t*%%edx\n");
22705 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22707 fprintf (file, "%s:\n", binder_name);
22711 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22712 fprintf (file, "\tpushl\t%%eax\n");
22715 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22717 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22719 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22720 fprintf (file, "%s:\n", lazy_ptr_name);
22721 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22722 fprintf (file, "\t.long %s\n", binder_name);
22726 darwin_x86_file_end (void)
22728 darwin_file_end ();
22731 #endif /* TARGET_MACHO */
22733 /* Order the registers for register allocator. */
22736 x86_order_regs_for_local_alloc (void)
22741 /* First allocate the local general purpose registers. */
22742 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22743 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22744 reg_alloc_order [pos++] = i;
22746 /* Global general purpose registers. */
22747 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22748 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22749 reg_alloc_order [pos++] = i;
22751 /* x87 registers come first in case we are doing FP math
22753 if (!TARGET_SSE_MATH)
22754 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22755 reg_alloc_order [pos++] = i;
22757 /* SSE registers. */
22758 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22759 reg_alloc_order [pos++] = i;
22760 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22761 reg_alloc_order [pos++] = i;
22763 /* x87 registers. */
22764 if (TARGET_SSE_MATH)
22765 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22766 reg_alloc_order [pos++] = i;
22768 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22769 reg_alloc_order [pos++] = i;
22771 /* Initialize the rest of array as we do not allocate some registers
22773 while (pos < FIRST_PSEUDO_REGISTER)
22774 reg_alloc_order [pos++] = 0;
22777 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22778 struct attribute_spec.handler. */
22780 ix86_handle_struct_attribute (tree *node, tree name,
22781 tree args ATTRIBUTE_UNUSED,
22782 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22785 if (DECL_P (*node))
22787 if (TREE_CODE (*node) == TYPE_DECL)
22788 type = &TREE_TYPE (*node);
22793 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22794 || TREE_CODE (*type) == UNION_TYPE)))
22796 warning (OPT_Wattributes, "%qs attribute ignored",
22797 IDENTIFIER_POINTER (name));
22798 *no_add_attrs = true;
22801 else if ((is_attribute_p ("ms_struct", name)
22802 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
22803 || ((is_attribute_p ("gcc_struct", name)
22804 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
22806 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
22807 IDENTIFIER_POINTER (name));
22808 *no_add_attrs = true;
22815 ix86_ms_bitfield_layout_p (const_tree record_type)
22817 return (TARGET_MS_BITFIELD_LAYOUT &&
22818 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
22819 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
22822 /* Returns an expression indicating where the this parameter is
22823 located on entry to the FUNCTION. */
22826 x86_this_parameter (tree function)
22828 tree type = TREE_TYPE (function);
22829 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
22834 const int *parm_regs;
22836 if (TARGET_64BIT_MS_ABI)
22837 parm_regs = x86_64_ms_abi_int_parameter_registers;
22839 parm_regs = x86_64_int_parameter_registers;
22840 return gen_rtx_REG (DImode, parm_regs[aggr]);
22843 nregs = ix86_function_regparm (type, function);
22845 if (nregs > 0 && !stdarg_p (type))
22849 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
22850 regno = aggr ? DX_REG : CX_REG;
22858 return gen_rtx_MEM (SImode,
22859 plus_constant (stack_pointer_rtx, 4));
22862 return gen_rtx_REG (SImode, regno);
22865 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
22868 /* Determine whether x86_output_mi_thunk can succeed. */
22871 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
22872 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
22873 HOST_WIDE_INT vcall_offset, const_tree function)
22875 /* 64-bit can handle anything. */
22879 /* For 32-bit, everything's fine if we have one free register. */
22880 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
22883 /* Need a free register for vcall_offset. */
22887 /* Need a free register for GOT references. */
22888 if (flag_pic && !(*targetm.binds_local_p) (function))
22891 /* Otherwise ok. */
22895 /* Output the assembler code for a thunk function. THUNK_DECL is the
22896 declaration for the thunk function itself, FUNCTION is the decl for
22897 the target function. DELTA is an immediate constant offset to be
22898 added to THIS. If VCALL_OFFSET is nonzero, the word at
22899 *(*this + vcall_offset) should be added to THIS. */
22902 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
22903 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
22904 HOST_WIDE_INT vcall_offset, tree function)
22907 rtx this_param = x86_this_parameter (function);
22910 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
22911 pull it in now and let DELTA benefit. */
22912 if (REG_P (this_param))
22913 this_reg = this_param;
22914 else if (vcall_offset)
22916 /* Put the this parameter into %eax. */
22917 xops[0] = this_param;
22918 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
22919 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22922 this_reg = NULL_RTX;
22924 /* Adjust the this parameter by a fixed constant. */
22927 xops[0] = GEN_INT (delta);
22928 xops[1] = this_reg ? this_reg : this_param;
22931 if (!x86_64_general_operand (xops[0], DImode))
22933 tmp = gen_rtx_REG (DImode, R10_REG);
22935 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
22937 xops[1] = this_param;
22939 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22942 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22945 /* Adjust the this parameter by a value stored in the vtable. */
22949 tmp = gen_rtx_REG (DImode, R10_REG);
22952 int tmp_regno = CX_REG;
22953 if (lookup_attribute ("fastcall",
22954 TYPE_ATTRIBUTES (TREE_TYPE (function))))
22955 tmp_regno = AX_REG;
22956 tmp = gen_rtx_REG (SImode, tmp_regno);
22959 xops[0] = gen_rtx_MEM (Pmode, this_reg);
22962 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22964 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22966 /* Adjust the this parameter. */
22967 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
22968 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
22970 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
22971 xops[0] = GEN_INT (vcall_offset);
22973 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22974 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
22976 xops[1] = this_reg;
22978 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22980 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22983 /* If necessary, drop THIS back to its stack slot. */
22984 if (this_reg && this_reg != this_param)
22986 xops[0] = this_reg;
22987 xops[1] = this_param;
22988 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22991 xops[0] = XEXP (DECL_RTL (function), 0);
22994 if (!flag_pic || (*targetm.binds_local_p) (function))
22995 output_asm_insn ("jmp\t%P0", xops);
22996 /* All thunks should be in the same object as their target,
22997 and thus binds_local_p should be true. */
22998 else if (TARGET_64BIT_MS_ABI)
22999 gcc_unreachable ();
23002 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
23003 tmp = gen_rtx_CONST (Pmode, tmp);
23004 tmp = gen_rtx_MEM (QImode, tmp);
23006 output_asm_insn ("jmp\t%A0", xops);
23011 if (!flag_pic || (*targetm.binds_local_p) (function))
23012 output_asm_insn ("jmp\t%P0", xops);
23017 rtx sym_ref = XEXP (DECL_RTL (function), 0);
23018 tmp = (gen_rtx_SYMBOL_REF
23020 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
23021 tmp = gen_rtx_MEM (QImode, tmp);
23023 output_asm_insn ("jmp\t%0", xops);
23026 #endif /* TARGET_MACHO */
23028 tmp = gen_rtx_REG (SImode, CX_REG);
23029 output_set_got (tmp, NULL_RTX);
23032 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
23033 output_asm_insn ("jmp\t{*}%1", xops);
23039 x86_file_start (void)
23041 default_file_start ();
23043 darwin_file_start ();
23045 if (X86_FILE_START_VERSION_DIRECTIVE)
23046 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
23047 if (X86_FILE_START_FLTUSED)
23048 fputs ("\t.global\t__fltused\n", asm_out_file);
23049 if (ix86_asm_dialect == ASM_INTEL)
23050 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
23054 x86_field_alignment (tree field, int computed)
23056 enum machine_mode mode;
23057 tree type = TREE_TYPE (field);
23059 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
23061 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
23062 ? get_inner_array_type (type) : type);
23063 if (mode == DFmode || mode == DCmode
23064 || GET_MODE_CLASS (mode) == MODE_INT
23065 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
23066 return MIN (32, computed);
23070 /* Output assembler code to FILE to increment profiler label # LABELNO
23071 for profiling a function entry. */
23073 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
23077 #ifndef NO_PROFILE_COUNTERS
23078 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
23081 if (!TARGET_64BIT_MS_ABI && flag_pic)
23082 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
23084 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23088 #ifndef NO_PROFILE_COUNTERS
23089 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
23090 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
23092 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
23096 #ifndef NO_PROFILE_COUNTERS
23097 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
23098 PROFILE_COUNT_REGISTER);
23100 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23104 /* We don't have exact information about the insn sizes, but we may assume
23105 quite safely that we are informed about all 1 byte insns and memory
23106 address sizes. This is enough to eliminate unnecessary padding in
23110 min_insn_size (rtx insn)
23114 if (!INSN_P (insn) || !active_insn_p (insn))
23117 /* Discard alignments we've emit and jump instructions. */
23118 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
23119 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
23122 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
23123 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
23126 /* Important case - calls are always 5 bytes.
23127 It is common to have many calls in the row. */
23129 && symbolic_reference_mentioned_p (PATTERN (insn))
23130 && !SIBLING_CALL_P (insn))
23132 if (get_attr_length (insn) <= 1)
23135 /* For normal instructions we may rely on the sizes of addresses
23136 and the presence of symbol to require 4 bytes of encoding.
23137 This is not the case for jumps where references are PC relative. */
23138 if (!JUMP_P (insn))
23140 l = get_attr_length_address (insn);
23141 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23150 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23154 ix86_avoid_jump_misspredicts (void)
23156 rtx insn, start = get_insns ();
23157 int nbytes = 0, njumps = 0;
23160 /* Look for all minimal intervals of instructions containing 4 jumps.
23161 The intervals are bounded by START and INSN. NBYTES is the total
23162 size of instructions in the interval including INSN and not including
23163 START. When the NBYTES is smaller than 16 bytes, it is possible
23164 that the end of START and INSN ends up in the same 16byte page.
23166 The smallest offset in the page INSN can start is the case where START
23167 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23168 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23170 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23173 nbytes += min_insn_size (insn);
23175 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23176 INSN_UID (insn), min_insn_size (insn));
23178 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23179 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23187 start = NEXT_INSN (start);
23188 if ((JUMP_P (start)
23189 && GET_CODE (PATTERN (start)) != ADDR_VEC
23190 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23192 njumps--, isjump = 1;
23195 nbytes -= min_insn_size (start);
23197 gcc_assert (njumps >= 0);
23199 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23200 INSN_UID (start), INSN_UID (insn), nbytes);
23202 if (njumps == 3 && isjump && nbytes < 16)
23204 int padsize = 15 - nbytes + min_insn_size (insn);
23207 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23208 INSN_UID (insn), padsize);
23209 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23214 /* AMD Athlon works faster
23215 when RET is not destination of conditional jump or directly preceded
23216 by other jump instruction. We avoid the penalty by inserting NOP just
23217 before the RET instructions in such cases. */
23219 ix86_pad_returns (void)
23224 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23226 basic_block bb = e->src;
23227 rtx ret = BB_END (bb);
23229 bool replace = false;
23231 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23232 || !maybe_hot_bb_p (bb))
23234 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23235 if (active_insn_p (prev) || LABEL_P (prev))
23237 if (prev && LABEL_P (prev))
23242 FOR_EACH_EDGE (e, ei, bb->preds)
23243 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23244 && !(e->flags & EDGE_FALLTHRU))
23249 prev = prev_active_insn (ret);
23251 && ((JUMP_P (prev) && any_condjump_p (prev))
23254 /* Empty functions get branch mispredict even when the jump destination
23255 is not visible to us. */
23256 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23261 emit_insn_before (gen_return_internal_long (), ret);
23267 /* Implement machine specific optimizations. We implement padding of returns
23268 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23272 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23273 ix86_pad_returns ();
23274 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23275 ix86_avoid_jump_misspredicts ();
23278 /* Return nonzero when QImode register that must be represented via REX prefix
23281 x86_extended_QIreg_mentioned_p (rtx insn)
23284 extract_insn_cached (insn);
23285 for (i = 0; i < recog_data.n_operands; i++)
23286 if (REG_P (recog_data.operand[i])
23287 && REGNO (recog_data.operand[i]) >= 4)
23292 /* Return nonzero when P points to register encoded via REX prefix.
23293 Called via for_each_rtx. */
23295 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23297 unsigned int regno;
23300 regno = REGNO (*p);
23301 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23304 /* Return true when INSN mentions register that must be encoded using REX
23307 x86_extended_reg_mentioned_p (rtx insn)
23309 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23312 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23313 optabs would emit if we didn't have TFmode patterns. */
23316 x86_emit_floatuns (rtx operands[2])
23318 rtx neglab, donelab, i0, i1, f0, in, out;
23319 enum machine_mode mode, inmode;
23321 inmode = GET_MODE (operands[1]);
23322 gcc_assert (inmode == SImode || inmode == DImode);
23325 in = force_reg (inmode, operands[1]);
23326 mode = GET_MODE (out);
23327 neglab = gen_label_rtx ();
23328 donelab = gen_label_rtx ();
23329 f0 = gen_reg_rtx (mode);
23331 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23333 expand_float (out, in, 0);
23335 emit_jump_insn (gen_jump (donelab));
23338 emit_label (neglab);
23340 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23342 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23344 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23346 expand_float (f0, i0, 0);
23348 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23350 emit_label (donelab);
23353 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23354 with all elements equal to VAR. Return true if successful. */
23357 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23358 rtx target, rtx val)
23360 enum machine_mode smode, wsmode, wvmode;
23375 val = force_reg (GET_MODE_INNER (mode), val);
23376 x = gen_rtx_VEC_DUPLICATE (mode, val);
23377 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23383 if (TARGET_SSE || TARGET_3DNOW_A)
23385 val = gen_lowpart (SImode, val);
23386 x = gen_rtx_TRUNCATE (HImode, val);
23387 x = gen_rtx_VEC_DUPLICATE (mode, x);
23388 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23410 /* Extend HImode to SImode using a paradoxical SUBREG. */
23411 tmp1 = gen_reg_rtx (SImode);
23412 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23413 /* Insert the SImode value as low element of V4SImode vector. */
23414 tmp2 = gen_reg_rtx (V4SImode);
23415 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23416 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23417 CONST0_RTX (V4SImode),
23419 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23420 /* Cast the V4SImode vector back to a V8HImode vector. */
23421 tmp1 = gen_reg_rtx (V8HImode);
23422 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23423 /* Duplicate the low short through the whole low SImode word. */
23424 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23425 /* Cast the V8HImode vector back to a V4SImode vector. */
23426 tmp2 = gen_reg_rtx (V4SImode);
23427 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23428 /* Replicate the low element of the V4SImode vector. */
23429 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23430 /* Cast the V2SImode back to V8HImode, and store in target. */
23431 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23442 /* Extend QImode to SImode using a paradoxical SUBREG. */
23443 tmp1 = gen_reg_rtx (SImode);
23444 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23445 /* Insert the SImode value as low element of V4SImode vector. */
23446 tmp2 = gen_reg_rtx (V4SImode);
23447 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23448 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23449 CONST0_RTX (V4SImode),
23451 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23452 /* Cast the V4SImode vector back to a V16QImode vector. */
23453 tmp1 = gen_reg_rtx (V16QImode);
23454 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23455 /* Duplicate the low byte through the whole low SImode word. */
23456 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23457 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23458 /* Cast the V16QImode vector back to a V4SImode vector. */
23459 tmp2 = gen_reg_rtx (V4SImode);
23460 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23461 /* Replicate the low element of the V4SImode vector. */
23462 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23463 /* Cast the V2SImode back to V16QImode, and store in target. */
23464 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23472 /* Replicate the value once into the next wider mode and recurse. */
23473 val = convert_modes (wsmode, smode, val, true);
23474 x = expand_simple_binop (wsmode, ASHIFT, val,
23475 GEN_INT (GET_MODE_BITSIZE (smode)),
23476 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23477 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23479 x = gen_reg_rtx (wvmode);
23480 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23481 gcc_unreachable ();
23482 emit_move_insn (target, gen_lowpart (mode, x));
23490 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23491 whose ONE_VAR element is VAR, and other elements are zero. Return true
23495 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23496 rtx target, rtx var, int one_var)
23498 enum machine_mode vsimode;
23514 var = force_reg (GET_MODE_INNER (mode), var);
23515 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23516 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23521 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23522 new_target = gen_reg_rtx (mode);
23524 new_target = target;
23525 var = force_reg (GET_MODE_INNER (mode), var);
23526 x = gen_rtx_VEC_DUPLICATE (mode, var);
23527 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23528 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23531 /* We need to shuffle the value to the correct position, so
23532 create a new pseudo to store the intermediate result. */
23534 /* With SSE2, we can use the integer shuffle insns. */
23535 if (mode != V4SFmode && TARGET_SSE2)
23537 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23539 GEN_INT (one_var == 1 ? 0 : 1),
23540 GEN_INT (one_var == 2 ? 0 : 1),
23541 GEN_INT (one_var == 3 ? 0 : 1)));
23542 if (target != new_target)
23543 emit_move_insn (target, new_target);
23547 /* Otherwise convert the intermediate result to V4SFmode and
23548 use the SSE1 shuffle instructions. */
23549 if (mode != V4SFmode)
23551 tmp = gen_reg_rtx (V4SFmode);
23552 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23557 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23559 GEN_INT (one_var == 1 ? 0 : 1),
23560 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23561 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23563 if (mode != V4SFmode)
23564 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23565 else if (tmp != target)
23566 emit_move_insn (target, tmp);
23568 else if (target != new_target)
23569 emit_move_insn (target, new_target);
23574 vsimode = V4SImode;
23580 vsimode = V2SImode;
23586 /* Zero extend the variable element to SImode and recurse. */
23587 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23589 x = gen_reg_rtx (vsimode);
23590 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23592 gcc_unreachable ();
23594 emit_move_insn (target, gen_lowpart (mode, x));
23602 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23603 consisting of the values in VALS. It is known that all elements
23604 except ONE_VAR are constants. Return true if successful. */
23607 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23608 rtx target, rtx vals, int one_var)
23610 rtx var = XVECEXP (vals, 0, one_var);
23611 enum machine_mode wmode;
23614 const_vec = copy_rtx (vals);
23615 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23616 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23624 /* For the two element vectors, it's just as easy to use
23625 the general case. */
23641 /* There's no way to set one QImode entry easily. Combine
23642 the variable value with its adjacent constant value, and
23643 promote to an HImode set. */
23644 x = XVECEXP (vals, 0, one_var ^ 1);
23647 var = convert_modes (HImode, QImode, var, true);
23648 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23649 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23650 x = GEN_INT (INTVAL (x) & 0xff);
23654 var = convert_modes (HImode, QImode, var, true);
23655 x = gen_int_mode (INTVAL (x) << 8, HImode);
23657 if (x != const0_rtx)
23658 var = expand_simple_binop (HImode, IOR, var, x, var,
23659 1, OPTAB_LIB_WIDEN);
23661 x = gen_reg_rtx (wmode);
23662 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23663 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23665 emit_move_insn (target, gen_lowpart (mode, x));
23672 emit_move_insn (target, const_vec);
23673 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23677 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
23678 all values variable, and none identical. */
23681 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
23682 rtx target, rtx vals)
23684 enum machine_mode half_mode = GET_MODE_INNER (mode);
23685 rtx op0 = NULL, op1 = NULL;
23686 bool use_vec_concat = false;
23692 if (!mmx_ok && !TARGET_SSE)
23698 /* For the two element vectors, we always implement VEC_CONCAT. */
23699 op0 = XVECEXP (vals, 0, 0);
23700 op1 = XVECEXP (vals, 0, 1);
23701 use_vec_concat = true;
23705 half_mode = V2SFmode;
23708 half_mode = V2SImode;
23714 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
23715 Recurse to load the two halves. */
23717 op0 = gen_reg_rtx (half_mode);
23718 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
23719 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
23721 op1 = gen_reg_rtx (half_mode);
23722 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
23723 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
23725 use_vec_concat = true;
23736 gcc_unreachable ();
23739 if (use_vec_concat)
23741 if (!register_operand (op0, half_mode))
23742 op0 = force_reg (half_mode, op0);
23743 if (!register_operand (op1, half_mode))
23744 op1 = force_reg (half_mode, op1);
23746 emit_insn (gen_rtx_SET (VOIDmode, target,
23747 gen_rtx_VEC_CONCAT (mode, op0, op1)));
23751 int i, j, n_elts, n_words, n_elt_per_word;
23752 enum machine_mode inner_mode;
23753 rtx words[4], shift;
23755 inner_mode = GET_MODE_INNER (mode);
23756 n_elts = GET_MODE_NUNITS (mode);
23757 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
23758 n_elt_per_word = n_elts / n_words;
23759 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
23761 for (i = 0; i < n_words; ++i)
23763 rtx word = NULL_RTX;
23765 for (j = 0; j < n_elt_per_word; ++j)
23767 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
23768 elt = convert_modes (word_mode, inner_mode, elt, true);
23774 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
23775 word, 1, OPTAB_LIB_WIDEN);
23776 word = expand_simple_binop (word_mode, IOR, word, elt,
23777 word, 1, OPTAB_LIB_WIDEN);
23785 emit_move_insn (target, gen_lowpart (mode, words[0]));
23786 else if (n_words == 2)
23788 rtx tmp = gen_reg_rtx (mode);
23789 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
23790 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
23791 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
23792 emit_move_insn (target, tmp);
23794 else if (n_words == 4)
23796 rtx tmp = gen_reg_rtx (V4SImode);
23797 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
23798 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
23799 emit_move_insn (target, gen_lowpart (mode, tmp));
23802 gcc_unreachable ();
23806 /* Initialize vector TARGET via VALS. Suppress the use of MMX
23807 instructions unless MMX_OK is true. */
23810 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
23812 enum machine_mode mode = GET_MODE (target);
23813 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23814 int n_elts = GET_MODE_NUNITS (mode);
23815 int n_var = 0, one_var = -1;
23816 bool all_same = true, all_const_zero = true;
23820 for (i = 0; i < n_elts; ++i)
23822 x = XVECEXP (vals, 0, i);
23823 if (!(CONST_INT_P (x)
23824 || GET_CODE (x) == CONST_DOUBLE
23825 || GET_CODE (x) == CONST_FIXED))
23826 n_var++, one_var = i;
23827 else if (x != CONST0_RTX (inner_mode))
23828 all_const_zero = false;
23829 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
23833 /* Constants are best loaded from the constant pool. */
23836 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
23840 /* If all values are identical, broadcast the value. */
23842 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
23843 XVECEXP (vals, 0, 0)))
23846 /* Values where only one field is non-constant are best loaded from
23847 the pool and overwritten via move later. */
23851 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
23852 XVECEXP (vals, 0, one_var),
23856 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
23860 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
23864 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
23866 enum machine_mode mode = GET_MODE (target);
23867 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23868 bool use_vec_merge = false;
23877 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
23878 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
23880 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
23882 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
23883 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23889 use_vec_merge = TARGET_SSE4_1;
23897 /* For the two element vectors, we implement a VEC_CONCAT with
23898 the extraction of the other element. */
23900 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
23901 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
23904 op0 = val, op1 = tmp;
23906 op0 = tmp, op1 = val;
23908 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
23909 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23914 use_vec_merge = TARGET_SSE4_1;
23921 use_vec_merge = true;
23925 /* tmp = target = A B C D */
23926 tmp = copy_to_reg (target);
23927 /* target = A A B B */
23928 emit_insn (gen_sse_unpcklps (target, target, target));
23929 /* target = X A B B */
23930 ix86_expand_vector_set (false, target, val, 0);
23931 /* target = A X C D */
23932 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23933 GEN_INT (1), GEN_INT (0),
23934 GEN_INT (2+4), GEN_INT (3+4)));
23938 /* tmp = target = A B C D */
23939 tmp = copy_to_reg (target);
23940 /* tmp = X B C D */
23941 ix86_expand_vector_set (false, tmp, val, 0);
23942 /* target = A B X D */
23943 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23944 GEN_INT (0), GEN_INT (1),
23945 GEN_INT (0+4), GEN_INT (3+4)));
23949 /* tmp = target = A B C D */
23950 tmp = copy_to_reg (target);
23951 /* tmp = X B C D */
23952 ix86_expand_vector_set (false, tmp, val, 0);
23953 /* target = A B X D */
23954 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23955 GEN_INT (0), GEN_INT (1),
23956 GEN_INT (2+4), GEN_INT (0+4)));
23960 gcc_unreachable ();
23965 use_vec_merge = TARGET_SSE4_1;
23969 /* Element 0 handled by vec_merge below. */
23972 use_vec_merge = true;
23978 /* With SSE2, use integer shuffles to swap element 0 and ELT,
23979 store into element 0, then shuffle them back. */
23983 order[0] = GEN_INT (elt);
23984 order[1] = const1_rtx;
23985 order[2] = const2_rtx;
23986 order[3] = GEN_INT (3);
23987 order[elt] = const0_rtx;
23989 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23990 order[1], order[2], order[3]));
23992 ix86_expand_vector_set (false, target, val, 0);
23994 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23995 order[1], order[2], order[3]));
23999 /* For SSE1, we have to reuse the V4SF code. */
24000 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
24001 gen_lowpart (SFmode, val), elt);
24006 use_vec_merge = TARGET_SSE2;
24009 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24013 use_vec_merge = TARGET_SSE4_1;
24023 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
24024 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
24025 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24029 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24031 emit_move_insn (mem, target);
24033 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24034 emit_move_insn (tmp, val);
24036 emit_move_insn (target, mem);
24041 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
24043 enum machine_mode mode = GET_MODE (vec);
24044 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24045 bool use_vec_extr = false;
24058 use_vec_extr = true;
24062 use_vec_extr = TARGET_SSE4_1;
24074 tmp = gen_reg_rtx (mode);
24075 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
24076 GEN_INT (elt), GEN_INT (elt),
24077 GEN_INT (elt+4), GEN_INT (elt+4)));
24081 tmp = gen_reg_rtx (mode);
24082 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
24086 gcc_unreachable ();
24089 use_vec_extr = true;
24094 use_vec_extr = TARGET_SSE4_1;
24108 tmp = gen_reg_rtx (mode);
24109 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
24110 GEN_INT (elt), GEN_INT (elt),
24111 GEN_INT (elt), GEN_INT (elt)));
24115 tmp = gen_reg_rtx (mode);
24116 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
24120 gcc_unreachable ();
24123 use_vec_extr = true;
24128 /* For SSE1, we have to reuse the V4SF code. */
24129 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24130 gen_lowpart (V4SFmode, vec), elt);
24136 use_vec_extr = TARGET_SSE2;
24139 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24143 use_vec_extr = TARGET_SSE4_1;
24147 /* ??? Could extract the appropriate HImode element and shift. */
24154 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24155 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24157 /* Let the rtl optimizers know about the zero extension performed. */
24158 if (inner_mode == QImode || inner_mode == HImode)
24160 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24161 target = gen_lowpart (SImode, target);
24164 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24168 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24170 emit_move_insn (mem, vec);
24172 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24173 emit_move_insn (target, tmp);
24177 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24178 pattern to reduce; DEST is the destination; IN is the input vector. */
24181 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24183 rtx tmp1, tmp2, tmp3;
24185 tmp1 = gen_reg_rtx (V4SFmode);
24186 tmp2 = gen_reg_rtx (V4SFmode);
24187 tmp3 = gen_reg_rtx (V4SFmode);
24189 emit_insn (gen_sse_movhlps (tmp1, in, in));
24190 emit_insn (fn (tmp2, tmp1, in));
24192 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24193 GEN_INT (1), GEN_INT (1),
24194 GEN_INT (1+4), GEN_INT (1+4)));
24195 emit_insn (fn (dest, tmp2, tmp3));
24198 /* Target hook for scalar_mode_supported_p. */
24200 ix86_scalar_mode_supported_p (enum machine_mode mode)
24202 if (DECIMAL_FLOAT_MODE_P (mode))
24204 else if (mode == TFmode)
24205 return TARGET_64BIT;
24207 return default_scalar_mode_supported_p (mode);
24210 /* Implements target hook vector_mode_supported_p. */
24212 ix86_vector_mode_supported_p (enum machine_mode mode)
24214 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24216 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24218 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24220 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24225 /* Target hook for c_mode_for_suffix. */
24226 static enum machine_mode
24227 ix86_c_mode_for_suffix (char suffix)
24229 if (TARGET_64BIT && suffix == 'q')
24231 if (TARGET_MMX && suffix == 'w')
24237 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24239 We do this in the new i386 backend to maintain source compatibility
24240 with the old cc0-based compiler. */
24243 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24244 tree inputs ATTRIBUTE_UNUSED,
24247 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24249 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24254 /* Implements target vector targetm.asm.encode_section_info. This
24255 is not used by netware. */
24257 static void ATTRIBUTE_UNUSED
24258 ix86_encode_section_info (tree decl, rtx rtl, int first)
24260 default_encode_section_info (decl, rtl, first);
24262 if (TREE_CODE (decl) == VAR_DECL
24263 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24264 && ix86_in_large_data_p (decl))
24265 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24268 /* Worker function for REVERSE_CONDITION. */
24271 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24273 return (mode != CCFPmode && mode != CCFPUmode
24274 ? reverse_condition (code)
24275 : reverse_condition_maybe_unordered (code));
24278 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24282 output_387_reg_move (rtx insn, rtx *operands)
24284 if (REG_P (operands[0]))
24286 if (REG_P (operands[1])
24287 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24289 if (REGNO (operands[0]) == FIRST_STACK_REG)
24290 return output_387_ffreep (operands, 0);
24291 return "fstp\t%y0";
24293 if (STACK_TOP_P (operands[0]))
24294 return "fld%z1\t%y1";
24297 else if (MEM_P (operands[0]))
24299 gcc_assert (REG_P (operands[1]));
24300 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24301 return "fstp%z0\t%y0";
24304 /* There is no non-popping store to memory for XFmode.
24305 So if we need one, follow the store with a load. */
24306 if (GET_MODE (operands[0]) == XFmode)
24307 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24309 return "fst%z0\t%y0";
24316 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24317 FP status register is set. */
24320 ix86_emit_fp_unordered_jump (rtx label)
24322 rtx reg = gen_reg_rtx (HImode);
24325 emit_insn (gen_x86_fnstsw_1 (reg));
24327 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24329 emit_insn (gen_x86_sahf_1 (reg));
24331 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24332 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24336 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24338 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24339 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24342 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24343 gen_rtx_LABEL_REF (VOIDmode, label),
24345 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24347 emit_jump_insn (temp);
24348 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24351 /* Output code to perform a log1p XFmode calculation. */
24353 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24355 rtx label1 = gen_label_rtx ();
24356 rtx label2 = gen_label_rtx ();
24358 rtx tmp = gen_reg_rtx (XFmode);
24359 rtx tmp2 = gen_reg_rtx (XFmode);
24361 emit_insn (gen_absxf2 (tmp, op1));
24362 emit_insn (gen_cmpxf (tmp,
24363 CONST_DOUBLE_FROM_REAL_VALUE (
24364 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24366 emit_jump_insn (gen_bge (label1));
24368 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24369 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24370 emit_jump (label2);
24372 emit_label (label1);
24373 emit_move_insn (tmp, CONST1_RTX (XFmode));
24374 emit_insn (gen_addxf3 (tmp, op1, tmp));
24375 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24376 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24378 emit_label (label2);
24381 /* Output code to perform a Newton-Rhapson approximation of a single precision
24382 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24384 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24386 rtx x0, x1, e0, e1, two;
24388 x0 = gen_reg_rtx (mode);
24389 e0 = gen_reg_rtx (mode);
24390 e1 = gen_reg_rtx (mode);
24391 x1 = gen_reg_rtx (mode);
24393 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24395 if (VECTOR_MODE_P (mode))
24396 two = ix86_build_const_vector (SFmode, true, two);
24398 two = force_reg (mode, two);
24400 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24402 /* x0 = rcp(b) estimate */
24403 emit_insn (gen_rtx_SET (VOIDmode, x0,
24404 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24407 emit_insn (gen_rtx_SET (VOIDmode, e0,
24408 gen_rtx_MULT (mode, x0, b)));
24410 emit_insn (gen_rtx_SET (VOIDmode, e1,
24411 gen_rtx_MINUS (mode, two, e0)));
24413 emit_insn (gen_rtx_SET (VOIDmode, x1,
24414 gen_rtx_MULT (mode, x0, e1)));
24416 emit_insn (gen_rtx_SET (VOIDmode, res,
24417 gen_rtx_MULT (mode, a, x1)));
24420 /* Output code to perform a Newton-Rhapson approximation of a
24421 single precision floating point [reciprocal] square root. */
24423 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24426 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24429 x0 = gen_reg_rtx (mode);
24430 e0 = gen_reg_rtx (mode);
24431 e1 = gen_reg_rtx (mode);
24432 e2 = gen_reg_rtx (mode);
24433 e3 = gen_reg_rtx (mode);
24435 real_from_integer (&r, VOIDmode, -3, -1, 0);
24436 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24438 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24439 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24441 if (VECTOR_MODE_P (mode))
24443 mthree = ix86_build_const_vector (SFmode, true, mthree);
24444 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24447 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24448 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24450 /* x0 = rsqrt(a) estimate */
24451 emit_insn (gen_rtx_SET (VOIDmode, x0,
24452 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24455 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24460 zero = gen_reg_rtx (mode);
24461 mask = gen_reg_rtx (mode);
24463 zero = force_reg (mode, CONST0_RTX(mode));
24464 emit_insn (gen_rtx_SET (VOIDmode, mask,
24465 gen_rtx_NE (mode, zero, a)));
24467 emit_insn (gen_rtx_SET (VOIDmode, x0,
24468 gen_rtx_AND (mode, x0, mask)));
24472 emit_insn (gen_rtx_SET (VOIDmode, e0,
24473 gen_rtx_MULT (mode, x0, a)));
24475 emit_insn (gen_rtx_SET (VOIDmode, e1,
24476 gen_rtx_MULT (mode, e0, x0)));
24479 mthree = force_reg (mode, mthree);
24480 emit_insn (gen_rtx_SET (VOIDmode, e2,
24481 gen_rtx_PLUS (mode, e1, mthree)));
24483 mhalf = force_reg (mode, mhalf);
24485 /* e3 = -.5 * x0 */
24486 emit_insn (gen_rtx_SET (VOIDmode, e3,
24487 gen_rtx_MULT (mode, x0, mhalf)));
24489 /* e3 = -.5 * e0 */
24490 emit_insn (gen_rtx_SET (VOIDmode, e3,
24491 gen_rtx_MULT (mode, e0, mhalf)));
24492 /* ret = e2 * e3 */
24493 emit_insn (gen_rtx_SET (VOIDmode, res,
24494 gen_rtx_MULT (mode, e2, e3)));
24497 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24499 static void ATTRIBUTE_UNUSED
24500 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24503 /* With Binutils 2.15, the "@unwind" marker must be specified on
24504 every occurrence of the ".eh_frame" section, not just the first
24507 && strcmp (name, ".eh_frame") == 0)
24509 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24510 flags & SECTION_WRITE ? "aw" : "a");
24513 default_elf_asm_named_section (name, flags, decl);
24516 /* Return the mangling of TYPE if it is an extended fundamental type. */
24518 static const char *
24519 ix86_mangle_type (const_tree type)
24521 type = TYPE_MAIN_VARIANT (type);
24523 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24524 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24527 switch (TYPE_MODE (type))
24530 /* __float128 is "g". */
24533 /* "long double" or __float80 is "e". */
24540 /* For 32-bit code we can save PIC register setup by using
24541 __stack_chk_fail_local hidden function instead of calling
24542 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24543 register, so it is better to call __stack_chk_fail directly. */
24546 ix86_stack_protect_fail (void)
24548 return TARGET_64BIT
24549 ? default_external_stack_protect_fail ()
24550 : default_hidden_stack_protect_fail ();
24553 /* Select a format to encode pointers in exception handling data. CODE
24554 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24555 true if the symbol may be affected by dynamic relocations.
24557 ??? All x86 object file formats are capable of representing this.
24558 After all, the relocation needed is the same as for the call insn.
24559 Whether or not a particular assembler allows us to enter such, I
24560 guess we'll have to see. */
24562 asm_preferred_eh_data_format (int code, int global)
24566 int type = DW_EH_PE_sdata8;
24568 || ix86_cmodel == CM_SMALL_PIC
24569 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24570 type = DW_EH_PE_sdata4;
24571 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24573 if (ix86_cmodel == CM_SMALL
24574 || (ix86_cmodel == CM_MEDIUM && code))
24575 return DW_EH_PE_udata4;
24576 return DW_EH_PE_absptr;
24579 /* Expand copysign from SIGN to the positive value ABS_VALUE
24580 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24583 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24585 enum machine_mode mode = GET_MODE (sign);
24586 rtx sgn = gen_reg_rtx (mode);
24587 if (mask == NULL_RTX)
24589 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24590 if (!VECTOR_MODE_P (mode))
24592 /* We need to generate a scalar mode mask in this case. */
24593 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24594 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24595 mask = gen_reg_rtx (mode);
24596 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24600 mask = gen_rtx_NOT (mode, mask);
24601 emit_insn (gen_rtx_SET (VOIDmode, sgn,
24602 gen_rtx_AND (mode, mask, sign)));
24603 emit_insn (gen_rtx_SET (VOIDmode, result,
24604 gen_rtx_IOR (mode, abs_value, sgn)));
24607 /* Expand fabs (OP0) and return a new rtx that holds the result. The
24608 mask for masking out the sign-bit is stored in *SMASK, if that is
24611 ix86_expand_sse_fabs (rtx op0, rtx *smask)
24613 enum machine_mode mode = GET_MODE (op0);
24616 xa = gen_reg_rtx (mode);
24617 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
24618 if (!VECTOR_MODE_P (mode))
24620 /* We need to generate a scalar mode mask in this case. */
24621 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24622 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24623 mask = gen_reg_rtx (mode);
24624 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24626 emit_insn (gen_rtx_SET (VOIDmode, xa,
24627 gen_rtx_AND (mode, op0, mask)));
24635 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
24636 swapping the operands if SWAP_OPERANDS is true. The expanded
24637 code is a forward jump to a newly created label in case the
24638 comparison is true. The generated label rtx is returned. */
24640 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
24641 bool swap_operands)
24652 label = gen_label_rtx ();
24653 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
24654 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24655 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
24656 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
24657 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
24658 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
24659 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
24660 JUMP_LABEL (tmp) = label;
24665 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
24666 using comparison code CODE. Operands are swapped for the comparison if
24667 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
24669 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
24670 bool swap_operands)
24672 enum machine_mode mode = GET_MODE (op0);
24673 rtx mask = gen_reg_rtx (mode);
24682 if (mode == DFmode)
24683 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
24684 gen_rtx_fmt_ee (code, mode, op0, op1)));
24686 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
24687 gen_rtx_fmt_ee (code, mode, op0, op1)));
24692 /* Generate and return a rtx of mode MODE for 2**n where n is the number
24693 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
24695 ix86_gen_TWO52 (enum machine_mode mode)
24697 REAL_VALUE_TYPE TWO52r;
24700 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
24701 TWO52 = const_double_from_real_value (TWO52r, mode);
24702 TWO52 = force_reg (mode, TWO52);
24707 /* Expand SSE sequence for computing lround from OP1 storing
24710 ix86_expand_lround (rtx op0, rtx op1)
24712 /* C code for the stuff we're doing below:
24713 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
24716 enum machine_mode mode = GET_MODE (op1);
24717 const struct real_format *fmt;
24718 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24721 /* load nextafter (0.5, 0.0) */
24722 fmt = REAL_MODE_FORMAT (mode);
24723 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24724 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24726 /* adj = copysign (0.5, op1) */
24727 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
24728 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
24730 /* adj = op1 + adj */
24731 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
24733 /* op0 = (imode)adj */
24734 expand_fix (op0, adj, 0);
24737 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
24740 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
24742 /* C code for the stuff we're doing below (for do_floor):
24744 xi -= (double)xi > op1 ? 1 : 0;
24747 enum machine_mode fmode = GET_MODE (op1);
24748 enum machine_mode imode = GET_MODE (op0);
24749 rtx ireg, freg, label, tmp;
24751 /* reg = (long)op1 */
24752 ireg = gen_reg_rtx (imode);
24753 expand_fix (ireg, op1, 0);
24755 /* freg = (double)reg */
24756 freg = gen_reg_rtx (fmode);
24757 expand_float (freg, ireg, 0);
24759 /* ireg = (freg > op1) ? ireg - 1 : ireg */
24760 label = ix86_expand_sse_compare_and_jump (UNLE,
24761 freg, op1, !do_floor);
24762 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
24763 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
24764 emit_move_insn (ireg, tmp);
24766 emit_label (label);
24767 LABEL_NUSES (label) = 1;
24769 emit_move_insn (op0, ireg);
24772 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
24773 result in OPERAND0. */
24775 ix86_expand_rint (rtx operand0, rtx operand1)
24777 /* C code for the stuff we're doing below:
24778 xa = fabs (operand1);
24779 if (!isless (xa, 2**52))
24781 xa = xa + 2**52 - 2**52;
24782 return copysign (xa, operand1);
24784 enum machine_mode mode = GET_MODE (operand0);
24785 rtx res, xa, label, TWO52, mask;
24787 res = gen_reg_rtx (mode);
24788 emit_move_insn (res, operand1);
24790 /* xa = abs (operand1) */
24791 xa = ix86_expand_sse_fabs (res, &mask);
24793 /* if (!isless (xa, TWO52)) goto label; */
24794 TWO52 = ix86_gen_TWO52 (mode);
24795 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24797 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24798 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24800 ix86_sse_copysign_to_positive (res, xa, res, mask);
24802 emit_label (label);
24803 LABEL_NUSES (label) = 1;
24805 emit_move_insn (operand0, res);
24808 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24811 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
24813 /* C code for the stuff we expand below.
24814 double xa = fabs (x), x2;
24815 if (!isless (xa, TWO52))
24817 xa = xa + TWO52 - TWO52;
24818 x2 = copysign (xa, x);
24827 enum machine_mode mode = GET_MODE (operand0);
24828 rtx xa, TWO52, tmp, label, one, res, mask;
24830 TWO52 = ix86_gen_TWO52 (mode);
24832 /* Temporary for holding the result, initialized to the input
24833 operand to ease control flow. */
24834 res = gen_reg_rtx (mode);
24835 emit_move_insn (res, operand1);
24837 /* xa = abs (operand1) */
24838 xa = ix86_expand_sse_fabs (res, &mask);
24840 /* if (!isless (xa, TWO52)) goto label; */
24841 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24843 /* xa = xa + TWO52 - TWO52; */
24844 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24845 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24847 /* xa = copysign (xa, operand1) */
24848 ix86_sse_copysign_to_positive (xa, xa, res, mask);
24850 /* generate 1.0 or -1.0 */
24851 one = force_reg (mode,
24852 const_double_from_real_value (do_floor
24853 ? dconst1 : dconstm1, mode));
24855 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24856 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24857 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24858 gen_rtx_AND (mode, one, tmp)));
24859 /* We always need to subtract here to preserve signed zero. */
24860 tmp = expand_simple_binop (mode, MINUS,
24861 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24862 emit_move_insn (res, tmp);
24864 emit_label (label);
24865 LABEL_NUSES (label) = 1;
24867 emit_move_insn (operand0, res);
24870 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24873 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
24875 /* C code for the stuff we expand below.
24876 double xa = fabs (x), x2;
24877 if (!isless (xa, TWO52))
24879 x2 = (double)(long)x;
24886 if (HONOR_SIGNED_ZEROS (mode))
24887 return copysign (x2, x);
24890 enum machine_mode mode = GET_MODE (operand0);
24891 rtx xa, xi, TWO52, tmp, label, one, res, mask;
24893 TWO52 = ix86_gen_TWO52 (mode);
24895 /* Temporary for holding the result, initialized to the input
24896 operand to ease control flow. */
24897 res = gen_reg_rtx (mode);
24898 emit_move_insn (res, operand1);
24900 /* xa = abs (operand1) */
24901 xa = ix86_expand_sse_fabs (res, &mask);
24903 /* if (!isless (xa, TWO52)) goto label; */
24904 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24906 /* xa = (double)(long)x */
24907 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24908 expand_fix (xi, res, 0);
24909 expand_float (xa, xi, 0);
24912 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24914 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24915 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24916 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24917 gen_rtx_AND (mode, one, tmp)));
24918 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
24919 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24920 emit_move_insn (res, tmp);
24922 if (HONOR_SIGNED_ZEROS (mode))
24923 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24925 emit_label (label);
24926 LABEL_NUSES (label) = 1;
24928 emit_move_insn (operand0, res);
24931 /* Expand SSE sequence for computing round from OPERAND1 storing
24932 into OPERAND0. Sequence that works without relying on DImode truncation
24933 via cvttsd2siq that is only available on 64bit targets. */
24935 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
24937 /* C code for the stuff we expand below.
24938 double xa = fabs (x), xa2, x2;
24939 if (!isless (xa, TWO52))
24941 Using the absolute value and copying back sign makes
24942 -0.0 -> -0.0 correct.
24943 xa2 = xa + TWO52 - TWO52;
24948 else if (dxa > 0.5)
24950 x2 = copysign (xa2, x);
24953 enum machine_mode mode = GET_MODE (operand0);
24954 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
24956 TWO52 = ix86_gen_TWO52 (mode);
24958 /* Temporary for holding the result, initialized to the input
24959 operand to ease control flow. */
24960 res = gen_reg_rtx (mode);
24961 emit_move_insn (res, operand1);
24963 /* xa = abs (operand1) */
24964 xa = ix86_expand_sse_fabs (res, &mask);
24966 /* if (!isless (xa, TWO52)) goto label; */
24967 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24969 /* xa2 = xa + TWO52 - TWO52; */
24970 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24971 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
24973 /* dxa = xa2 - xa; */
24974 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
24976 /* generate 0.5, 1.0 and -0.5 */
24977 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
24978 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
24979 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
24983 tmp = gen_reg_rtx (mode);
24984 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
24985 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
24986 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24987 gen_rtx_AND (mode, one, tmp)));
24988 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24989 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
24990 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
24991 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24992 gen_rtx_AND (mode, one, tmp)));
24993 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24995 /* res = copysign (xa2, operand1) */
24996 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
24998 emit_label (label);
24999 LABEL_NUSES (label) = 1;
25001 emit_move_insn (operand0, res);
25004 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25007 ix86_expand_trunc (rtx operand0, rtx operand1)
25009 /* C code for SSE variant we expand below.
25010 double xa = fabs (x), x2;
25011 if (!isless (xa, TWO52))
25013 x2 = (double)(long)x;
25014 if (HONOR_SIGNED_ZEROS (mode))
25015 return copysign (x2, x);
25018 enum machine_mode mode = GET_MODE (operand0);
25019 rtx xa, xi, TWO52, label, res, mask;
25021 TWO52 = ix86_gen_TWO52 (mode);
25023 /* Temporary for holding the result, initialized to the input
25024 operand to ease control flow. */
25025 res = gen_reg_rtx (mode);
25026 emit_move_insn (res, operand1);
25028 /* xa = abs (operand1) */
25029 xa = ix86_expand_sse_fabs (res, &mask);
25031 /* if (!isless (xa, TWO52)) goto label; */
25032 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25034 /* x = (double)(long)x */
25035 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25036 expand_fix (xi, res, 0);
25037 expand_float (res, xi, 0);
25039 if (HONOR_SIGNED_ZEROS (mode))
25040 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25042 emit_label (label);
25043 LABEL_NUSES (label) = 1;
25045 emit_move_insn (operand0, res);
25048 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25051 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
25053 enum machine_mode mode = GET_MODE (operand0);
25054 rtx xa, mask, TWO52, label, one, res, smask, tmp;
25056 /* C code for SSE variant we expand below.
25057 double xa = fabs (x), x2;
25058 if (!isless (xa, TWO52))
25060 xa2 = xa + TWO52 - TWO52;
25064 x2 = copysign (xa2, x);
25068 TWO52 = ix86_gen_TWO52 (mode);
25070 /* Temporary for holding the result, initialized to the input
25071 operand to ease control flow. */
25072 res = gen_reg_rtx (mode);
25073 emit_move_insn (res, operand1);
25075 /* xa = abs (operand1) */
25076 xa = ix86_expand_sse_fabs (res, &smask);
25078 /* if (!isless (xa, TWO52)) goto label; */
25079 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25081 /* res = xa + TWO52 - TWO52; */
25082 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25083 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
25084 emit_move_insn (res, tmp);
25087 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25089 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
25090 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
25091 emit_insn (gen_rtx_SET (VOIDmode, mask,
25092 gen_rtx_AND (mode, mask, one)));
25093 tmp = expand_simple_binop (mode, MINUS,
25094 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
25095 emit_move_insn (res, tmp);
25097 /* res = copysign (res, operand1) */
25098 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
25100 emit_label (label);
25101 LABEL_NUSES (label) = 1;
25103 emit_move_insn (operand0, res);
25106 /* Expand SSE sequence for computing round from OPERAND1 storing
25109 ix86_expand_round (rtx operand0, rtx operand1)
25111 /* C code for the stuff we're doing below:
25112 double xa = fabs (x);
25113 if (!isless (xa, TWO52))
25115 xa = (double)(long)(xa + nextafter (0.5, 0.0));
25116 return copysign (xa, x);
25118 enum machine_mode mode = GET_MODE (operand0);
25119 rtx res, TWO52, xa, label, xi, half, mask;
25120 const struct real_format *fmt;
25121 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25123 /* Temporary for holding the result, initialized to the input
25124 operand to ease control flow. */
25125 res = gen_reg_rtx (mode);
25126 emit_move_insn (res, operand1);
25128 TWO52 = ix86_gen_TWO52 (mode);
25129 xa = ix86_expand_sse_fabs (res, &mask);
25130 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25132 /* load nextafter (0.5, 0.0) */
25133 fmt = REAL_MODE_FORMAT (mode);
25134 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25135 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25137 /* xa = xa + 0.5 */
25138 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25139 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25141 /* xa = (double)(int64_t)xa */
25142 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25143 expand_fix (xi, xa, 0);
25144 expand_float (xa, xi, 0);
25146 /* res = copysign (xa, operand1) */
25147 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25149 emit_label (label);
25150 LABEL_NUSES (label) = 1;
25152 emit_move_insn (operand0, res);
25156 /* Validate whether a SSE5 instruction is valid or not.
25157 OPERANDS is the array of operands.
25158 NUM is the number of operands.
25159 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25160 NUM_MEMORY is the maximum number of memory operands to accept. */
25162 ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
25168 /* Count the number of memory arguments */
25171 for (i = 0; i < num; i++)
25173 enum machine_mode mode = GET_MODE (operands[i]);
25174 if (register_operand (operands[i], mode))
25177 else if (memory_operand (operands[i], mode))
25179 mem_mask |= (1 << i);
25185 rtx pattern = PATTERN (insn);
25187 /* allow 0 for pcmov */
25188 if (GET_CODE (pattern) != SET
25189 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25191 || operands[i] != CONST0_RTX (mode))
25196 /* If there were no memory operations, allow the insn */
25200 /* Do not allow the destination register to be a memory operand. */
25201 else if (mem_mask & (1 << 0))
25204 /* If there are too many memory operations, disallow the instruction. While
25205 the hardware only allows 1 memory reference, before register allocation
25206 for some insns, we allow two memory operations sometimes in order to allow
25207 code like the following to be optimized:
25209 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25211 or similar cases that are vectorized into using the fmaddss
25213 else if (mem_count > num_memory)
25216 /* Don't allow more than one memory operation if not optimizing. */
25217 else if (mem_count > 1 && !optimize)
25220 else if (num == 4 && mem_count == 1)
25222 /* formats (destination is the first argument), example fmaddss:
25223 xmm1, xmm1, xmm2, xmm3/mem
25224 xmm1, xmm1, xmm2/mem, xmm3
25225 xmm1, xmm2, xmm3/mem, xmm1
25226 xmm1, xmm2/mem, xmm3, xmm1 */
25228 return ((mem_mask == (1 << 1))
25229 || (mem_mask == (1 << 2))
25230 || (mem_mask == (1 << 3)));
25232 /* format, example pmacsdd:
25233 xmm1, xmm2, xmm3/mem, xmm1 */
25235 return (mem_mask == (1 << 2));
25238 else if (num == 4 && num_memory == 2)
25240 /* If there are two memory operations, we can load one of the memory ops
25241 into the destination register. This is for optimizing the
25242 multiply/add ops, which the combiner has optimized both the multiply
25243 and the add insns to have a memory operation. We have to be careful
25244 that the destination doesn't overlap with the inputs. */
25245 rtx op0 = operands[0];
25247 if (reg_mentioned_p (op0, operands[1])
25248 || reg_mentioned_p (op0, operands[2])
25249 || reg_mentioned_p (op0, operands[3]))
25252 /* formats (destination is the first argument), example fmaddss:
25253 xmm1, xmm1, xmm2, xmm3/mem
25254 xmm1, xmm1, xmm2/mem, xmm3
25255 xmm1, xmm2, xmm3/mem, xmm1
25256 xmm1, xmm2/mem, xmm3, xmm1
25258 For the oc0 case, we will load either operands[1] or operands[3] into
25259 operands[0], so any combination of 2 memory operands is ok. */
25263 /* format, example pmacsdd:
25264 xmm1, xmm2, xmm3/mem, xmm1
25266 For the integer multiply/add instructions be more restrictive and
25267 require operands[2] and operands[3] to be the memory operands. */
25269 return (mem_mask == ((1 << 2) | (1 << 3)));
25272 else if (num == 3 && num_memory == 1)
25274 /* formats, example protb:
25275 xmm1, xmm2, xmm3/mem
25276 xmm1, xmm2/mem, xmm3 */
25278 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25280 /* format, example comeq:
25281 xmm1, xmm2, xmm3/mem */
25283 return (mem_mask == (1 << 2));
25287 gcc_unreachable ();
25293 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25294 hardware will allow by using the destination register to load one of the
25295 memory operations. Presently this is used by the multiply/add routines to
25296 allow 2 memory references. */
25299 ix86_expand_sse5_multiple_memory (rtx operands[],
25301 enum machine_mode mode)
25303 rtx op0 = operands[0];
25305 || memory_operand (op0, mode)
25306 || reg_mentioned_p (op0, operands[1])
25307 || reg_mentioned_p (op0, operands[2])
25308 || reg_mentioned_p (op0, operands[3]))
25309 gcc_unreachable ();
25311 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25312 the destination register. */
25313 if (memory_operand (operands[1], mode))
25315 emit_move_insn (op0, operands[1]);
25318 else if (memory_operand (operands[3], mode))
25320 emit_move_insn (op0, operands[3]);
25324 gcc_unreachable ();
25330 /* Table of valid machine attributes. */
25331 static const struct attribute_spec ix86_attribute_table[] =
25333 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25334 /* Stdcall attribute says callee is responsible for popping arguments
25335 if they are not variable. */
25336 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25337 /* Fastcall attribute says callee is responsible for popping arguments
25338 if they are not variable. */
25339 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25340 /* Cdecl attribute says the callee is a normal C declaration */
25341 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25342 /* Regparm attribute specifies how many integer arguments are to be
25343 passed in registers. */
25344 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25345 /* Sseregparm attribute says we are using x86_64 calling conventions
25346 for FP arguments. */
25347 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25348 /* force_align_arg_pointer says this function realigns the stack at entry. */
25349 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25350 false, true, true, ix86_handle_cconv_attribute },
25351 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25352 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25353 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25354 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25356 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25357 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25358 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25359 SUBTARGET_ATTRIBUTE_TABLE,
25361 { NULL, 0, 0, false, false, false, NULL }
25364 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25366 x86_builtin_vectorization_cost (bool runtime_test)
25368 /* If the branch of the runtime test is taken - i.e. - the vectorized
25369 version is skipped - this incurs a misprediction cost (because the
25370 vectorized version is expected to be the fall-through). So we subtract
25371 the latency of a mispredicted branch from the costs that are incured
25372 when the vectorized version is executed.
25374 TODO: The values in individual target tables have to be tuned or new
25375 fields may be needed. For eg. on K8, the default branch path is the
25376 not-taken path. If the taken path is predicted correctly, the minimum
25377 penalty of going down the taken-path is 1 cycle. If the taken-path is
25378 not predicted correctly, then the minimum penalty is 10 cycles. */
25382 return (-(ix86_cost->cond_taken_branch_cost));
25388 /* Initialize the GCC target structure. */
25389 #undef TARGET_ATTRIBUTE_TABLE
25390 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25391 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25392 # undef TARGET_MERGE_DECL_ATTRIBUTES
25393 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25396 #undef TARGET_COMP_TYPE_ATTRIBUTES
25397 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25399 #undef TARGET_INIT_BUILTINS
25400 #define TARGET_INIT_BUILTINS ix86_init_builtins
25401 #undef TARGET_EXPAND_BUILTIN
25402 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25404 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25405 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25406 ix86_builtin_vectorized_function
25408 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25409 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25411 #undef TARGET_BUILTIN_RECIPROCAL
25412 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25414 #undef TARGET_ASM_FUNCTION_EPILOGUE
25415 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25417 #undef TARGET_ENCODE_SECTION_INFO
25418 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25419 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25421 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25424 #undef TARGET_ASM_OPEN_PAREN
25425 #define TARGET_ASM_OPEN_PAREN ""
25426 #undef TARGET_ASM_CLOSE_PAREN
25427 #define TARGET_ASM_CLOSE_PAREN ""
25429 #undef TARGET_ASM_ALIGNED_HI_OP
25430 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25431 #undef TARGET_ASM_ALIGNED_SI_OP
25432 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25434 #undef TARGET_ASM_ALIGNED_DI_OP
25435 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25438 #undef TARGET_ASM_UNALIGNED_HI_OP
25439 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25440 #undef TARGET_ASM_UNALIGNED_SI_OP
25441 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25442 #undef TARGET_ASM_UNALIGNED_DI_OP
25443 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25445 #undef TARGET_SCHED_ADJUST_COST
25446 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25447 #undef TARGET_SCHED_ISSUE_RATE
25448 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25449 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25450 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25451 ia32_multipass_dfa_lookahead
25453 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25454 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25457 #undef TARGET_HAVE_TLS
25458 #define TARGET_HAVE_TLS true
25460 #undef TARGET_CANNOT_FORCE_CONST_MEM
25461 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25462 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25463 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25465 #undef TARGET_DELEGITIMIZE_ADDRESS
25466 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25468 #undef TARGET_MS_BITFIELD_LAYOUT_P
25469 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25472 #undef TARGET_BINDS_LOCAL_P
25473 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25475 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25476 #undef TARGET_BINDS_LOCAL_P
25477 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25480 #undef TARGET_ASM_OUTPUT_MI_THUNK
25481 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25482 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25483 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25485 #undef TARGET_ASM_FILE_START
25486 #define TARGET_ASM_FILE_START x86_file_start
25488 #undef TARGET_DEFAULT_TARGET_FLAGS
25489 #define TARGET_DEFAULT_TARGET_FLAGS \
25491 | TARGET_SUBTARGET_DEFAULT \
25492 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25494 #undef TARGET_HANDLE_OPTION
25495 #define TARGET_HANDLE_OPTION ix86_handle_option
25497 #undef TARGET_RTX_COSTS
25498 #define TARGET_RTX_COSTS ix86_rtx_costs
25499 #undef TARGET_ADDRESS_COST
25500 #define TARGET_ADDRESS_COST ix86_address_cost
25502 #undef TARGET_FIXED_CONDITION_CODE_REGS
25503 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25504 #undef TARGET_CC_MODES_COMPATIBLE
25505 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25507 #undef TARGET_MACHINE_DEPENDENT_REORG
25508 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25510 #undef TARGET_BUILD_BUILTIN_VA_LIST
25511 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25513 #undef TARGET_EXPAND_BUILTIN_VA_START
25514 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
25516 #undef TARGET_MD_ASM_CLOBBERS
25517 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25519 #undef TARGET_PROMOTE_PROTOTYPES
25520 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25521 #undef TARGET_STRUCT_VALUE_RTX
25522 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25523 #undef TARGET_SETUP_INCOMING_VARARGS
25524 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25525 #undef TARGET_MUST_PASS_IN_STACK
25526 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25527 #undef TARGET_PASS_BY_REFERENCE
25528 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25529 #undef TARGET_INTERNAL_ARG_POINTER
25530 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25531 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25532 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25533 #undef TARGET_STRICT_ARGUMENT_NAMING
25534 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25536 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25537 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25539 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25540 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25542 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25543 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25545 #undef TARGET_C_MODE_FOR_SUFFIX
25546 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25549 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25550 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25553 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25554 #undef TARGET_INSERT_ATTRIBUTES
25555 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25558 #undef TARGET_MANGLE_TYPE
25559 #define TARGET_MANGLE_TYPE ix86_mangle_type
25561 #undef TARGET_STACK_PROTECT_FAIL
25562 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25564 #undef TARGET_FUNCTION_VALUE
25565 #define TARGET_FUNCTION_VALUE ix86_function_value
25567 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25568 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25570 struct gcc_target targetm = TARGET_INITIALIZER;
25572 #include "gt-i386.h"