1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
51 #include "tree-gimple.h"
54 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs size_cost = { /* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of loading integer registers */
995 2, /* cost of moving MMX register */
996 {6, 6}, /* cost of loading MMX registers
997 in SImode and DImode */
998 {4, 4}, /* cost of storing MMX registers
999 in SImode and DImode */
1000 2, /* cost of moving SSE register */
1001 {6, 6, 6}, /* cost of loading SSE registers
1002 in SImode, DImode and TImode */
1003 {4, 4, 4}, /* cost of storing SSE registers
1004 in SImode, DImode and TImode */
1005 2, /* MMX or SSE register to integer */
1006 32, /* size of l1 cache. */
1007 2048, /* size of l2 cache. */
1008 128, /* size of prefetch block */
1009 8, /* number of parallel prefetches */
1010 3, /* Branch cost */
1011 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1012 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1013 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1014 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1015 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1016 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1017 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1018 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1019 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1020 {{libcall, {{8, loop}, {15, unrolled_loop},
1021 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1022 {libcall, {{24, loop}, {32, unrolled_loop},
1023 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1024 1, /* scalar_stmt_cost. */
1025 1, /* scalar load_cost. */
1026 1, /* scalar_store_cost. */
1027 1, /* vec_stmt_cost. */
1028 1, /* vec_to_scalar_cost. */
1029 1, /* scalar_to_vec_cost. */
1030 1, /* vec_align_load_cost. */
1031 2, /* vec_unalign_load_cost. */
1032 1, /* vec_store_cost. */
1033 3, /* cond_taken_branch_cost. */
1034 1, /* cond_not_taken_branch_cost. */
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1039 struct processor_costs generic64_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1045 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1046 COSTS_N_INSNS (1), /* variable shift costs */
1047 COSTS_N_INSNS (1), /* constant shift costs */
1048 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1049 COSTS_N_INSNS (4), /* HI */
1050 COSTS_N_INSNS (3), /* SI */
1051 COSTS_N_INSNS (4), /* DI */
1052 COSTS_N_INSNS (2)}, /* other */
1053 0, /* cost of multiply per each bit set */
1054 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1055 COSTS_N_INSNS (26), /* HI */
1056 COSTS_N_INSNS (42), /* SI */
1057 COSTS_N_INSNS (74), /* DI */
1058 COSTS_N_INSNS (74)}, /* other */
1059 COSTS_N_INSNS (1), /* cost of movsx */
1060 COSTS_N_INSNS (1), /* cost of movzx */
1061 8, /* "large" insn */
1062 17, /* MOVE_RATIO */
1063 4, /* cost for loading QImode using movzbl */
1064 {4, 4, 4}, /* cost of loading integer registers
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1067 {4, 4, 4}, /* cost of storing integer registers */
1068 4, /* cost of reg,reg fld/fst */
1069 {12, 12, 12}, /* cost of loading fp registers
1070 in SFmode, DFmode and XFmode */
1071 {6, 6, 8}, /* cost of storing fp registers
1072 in SFmode, DFmode and XFmode */
1073 2, /* cost of moving MMX register */
1074 {8, 8}, /* cost of loading MMX registers
1075 in SImode and DImode */
1076 {8, 8}, /* cost of storing MMX registers
1077 in SImode and DImode */
1078 2, /* cost of moving SSE register */
1079 {8, 8, 8}, /* cost of loading SSE registers
1080 in SImode, DImode and TImode */
1081 {8, 8, 8}, /* cost of storing SSE registers
1082 in SImode, DImode and TImode */
1083 5, /* MMX or SSE register to integer */
1084 32, /* size of l1 cache. */
1085 512, /* size of l2 cache. */
1086 64, /* size of prefetch block */
1087 6, /* number of parallel prefetches */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1090 3, /* Branch cost */
1091 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1092 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1093 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1094 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1095 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1096 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 1, /* scalar_stmt_cost. */
1102 1, /* scalar load_cost. */
1103 1, /* scalar_store_cost. */
1104 1, /* vec_stmt_cost. */
1105 1, /* vec_to_scalar_cost. */
1106 1, /* scalar_to_vec_cost. */
1107 1, /* vec_align_load_cost. */
1108 2, /* vec_unalign_load_cost. */
1109 1, /* vec_store_cost. */
1110 3, /* cond_taken_branch_cost. */
1111 1, /* cond_not_taken_branch_cost. */
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1116 struct processor_costs generic32_cost = {
1117 COSTS_N_INSNS (1), /* cost of an add instruction */
1118 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1119 COSTS_N_INSNS (1), /* variable shift costs */
1120 COSTS_N_INSNS (1), /* constant shift costs */
1121 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1122 COSTS_N_INSNS (4), /* HI */
1123 COSTS_N_INSNS (3), /* SI */
1124 COSTS_N_INSNS (4), /* DI */
1125 COSTS_N_INSNS (2)}, /* other */
1126 0, /* cost of multiply per each bit set */
1127 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1128 COSTS_N_INSNS (26), /* HI */
1129 COSTS_N_INSNS (42), /* SI */
1130 COSTS_N_INSNS (74), /* DI */
1131 COSTS_N_INSNS (74)}, /* other */
1132 COSTS_N_INSNS (1), /* cost of movsx */
1133 COSTS_N_INSNS (1), /* cost of movzx */
1134 8, /* "large" insn */
1135 17, /* MOVE_RATIO */
1136 4, /* cost for loading QImode using movzbl */
1137 {4, 4, 4}, /* cost of loading integer registers
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1140 {4, 4, 4}, /* cost of storing integer registers */
1141 4, /* cost of reg,reg fld/fst */
1142 {12, 12, 12}, /* cost of loading fp registers
1143 in SFmode, DFmode and XFmode */
1144 {6, 6, 8}, /* cost of storing fp registers
1145 in SFmode, DFmode and XFmode */
1146 2, /* cost of moving MMX register */
1147 {8, 8}, /* cost of loading MMX registers
1148 in SImode and DImode */
1149 {8, 8}, /* cost of storing MMX registers
1150 in SImode and DImode */
1151 2, /* cost of moving SSE register */
1152 {8, 8, 8}, /* cost of loading SSE registers
1153 in SImode, DImode and TImode */
1154 {8, 8, 8}, /* cost of storing SSE registers
1155 in SImode, DImode and TImode */
1156 5, /* MMX or SSE register to integer */
1157 32, /* size of l1 cache. */
1158 256, /* size of l2 cache. */
1159 64, /* size of prefetch block */
1160 6, /* number of parallel prefetches */
1161 3, /* Branch cost */
1162 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1163 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1164 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1165 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1166 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1167 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 1, /* scalar_stmt_cost. */
1173 1, /* scalar load_cost. */
1174 1, /* scalar_store_cost. */
1175 1, /* vec_stmt_cost. */
1176 1, /* vec_to_scalar_cost. */
1177 1, /* scalar_to_vec_cost. */
1178 1, /* vec_align_load_cost. */
1179 2, /* vec_unalign_load_cost. */
1180 1, /* vec_store_cost. */
1181 3, /* cond_taken_branch_cost. */
1182 1, /* cond_not_taken_branch_cost. */
1185 const struct processor_costs *ix86_cost = &pentium_cost;
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1213 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1214 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1215 negatively, so enabling for Generic64 seems like good code size
1216 tradeoff. We can't enable it for 32bit generic because it does not
1217 work well with PPro base chips. */
1218 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1220 /* X86_TUNE_PUSH_MEMORY */
1221 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1222 | m_NOCONA | m_CORE2 | m_GENERIC,
1224 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1227 /* X86_TUNE_USE_BIT_TEST */
1230 /* X86_TUNE_UNROLL_STRLEN */
1231 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1233 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1234 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1236 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1237 on simulation result. But after P4 was made, no performance benefit
1238 was observed with branch hints. It also increases the code size.
1239 As a result, icc never generates branch hints. */
1242 /* X86_TUNE_DOUBLE_WITH_ADD */
1245 /* X86_TUNE_USE_SAHF */
1246 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1247 | m_NOCONA | m_CORE2 | m_GENERIC,
1249 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1250 partial dependencies. */
1251 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1252 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1254 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1255 register stalls on Generic32 compilation setting as well. However
1256 in current implementation the partial register stalls are not eliminated
1257 very well - they can be introduced via subregs synthesized by combine
1258 and can happen in caller/callee saving sequences. Because this option
1259 pays back little on PPro based chips and is in conflict with partial reg
1260 dependencies used by Athlon/P4 based chips, it is better to leave it off
1261 for generic32 for now. */
1264 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1265 m_CORE2 | m_GENERIC,
1267 /* X86_TUNE_USE_HIMODE_FIOP */
1268 m_386 | m_486 | m_K6_GEODE,
1270 /* X86_TUNE_USE_SIMODE_FIOP */
1271 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1273 /* X86_TUNE_USE_MOV0 */
1276 /* X86_TUNE_USE_CLTD */
1277 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1279 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1282 /* X86_TUNE_SPLIT_LONG_MOVES */
1285 /* X86_TUNE_READ_MODIFY_WRITE */
1288 /* X86_TUNE_READ_MODIFY */
1291 /* X86_TUNE_PROMOTE_QIMODE */
1292 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1293 | m_GENERIC /* | m_PENT4 ? */,
1295 /* X86_TUNE_FAST_PREFIX */
1296 ~(m_PENT | m_486 | m_386),
1298 /* X86_TUNE_SINGLE_STRINGOP */
1299 m_386 | m_PENT4 | m_NOCONA,
1301 /* X86_TUNE_QIMODE_MATH */
1304 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1305 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1306 might be considered for Generic32 if our scheme for avoiding partial
1307 stalls was more effective. */
1310 /* X86_TUNE_PROMOTE_QI_REGS */
1313 /* X86_TUNE_PROMOTE_HI_REGS */
1316 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1317 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1319 /* X86_TUNE_ADD_ESP_8 */
1320 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1321 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_SUB_ESP_4 */
1324 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_8 */
1327 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1328 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1330 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1331 for DFmode copies */
1332 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1333 | m_GENERIC | m_GEODE),
1335 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1336 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1338 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1339 conflict here in between PPro/Pentium4 based chips that thread 128bit
1340 SSE registers as single units versus K8 based chips that divide SSE
1341 registers to two 64bit halves. This knob promotes all store destinations
1342 to be 128bit to allow register renaming on 128bit SSE units, but usually
1343 results in one extra microop on 64bit SSE units. Experimental results
1344 shows that disabling this option on P4 brings over 20% SPECfp regression,
1345 while enabling it on K8 brings roughly 2.4% regression that can be partly
1346 masked by careful scheduling of moves. */
1347 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1349 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1352 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1353 are resolved on SSE register parts instead of whole registers, so we may
1354 maintain just lower part of scalar values in proper format leaving the
1355 upper part undefined. */
1358 /* X86_TUNE_SSE_TYPELESS_STORES */
1361 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1362 m_PPRO | m_PENT4 | m_NOCONA,
1364 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1365 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1367 /* X86_TUNE_PROLOGUE_USING_MOVE */
1368 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_EPILOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_SHIFT1 */
1376 /* X86_TUNE_USE_FFREEP */
1379 /* X86_TUNE_INTER_UNIT_MOVES */
1380 ~(m_AMD_MULTIPLE | m_GENERIC),
1382 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1385 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1386 than 4 branch instructions in the 16 byte window. */
1387 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1389 /* X86_TUNE_SCHEDULE */
1390 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_USE_BT */
1393 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_INCDEC */
1396 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1398 /* X86_TUNE_PAD_RETURNS */
1399 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_EXT_80387_CONSTANTS */
1402 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_SHORTEN_X87_SSE */
1407 /* X86_TUNE_AVOID_VECTOR_DECODE */
1410 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1411 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1414 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1415 vector path on AMD machines. */
1416 m_K8 | m_GENERIC64 | m_AMDFAM10,
1418 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1420 m_K8 | m_GENERIC64 | m_AMDFAM10,
1422 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1426 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1427 but one byte longer. */
1430 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1431 operand that cannot be represented using a modRM byte. The XOR
1432 replacement is long decoded, so this split helps here as well. */
1435 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1436 from integer to FP. */
1440 /* Feature tests against the various architecture variations. */
1441 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1442 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1443 ~(m_386 | m_486 | m_PENT | m_K6),
1445 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1448 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1451 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1454 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1458 static const unsigned int x86_accumulate_outgoing_args
1459 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1461 static const unsigned int x86_arch_always_fancy_math_387
1462 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1463 | m_NOCONA | m_CORE2 | m_GENERIC;
1465 static enum stringop_alg stringop_alg = no_stringop;
1467 /* In case the average insn count for single function invocation is
1468 lower than this constant, emit fast (but longer) prologue and
1470 #define FAST_PROLOGUE_INSN_COUNT 20
1472 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1473 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1474 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1475 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1477 /* Array of the smallest class containing reg number REGNO, indexed by
1478 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1480 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1482 /* ax, dx, cx, bx */
1483 AREG, DREG, CREG, BREG,
1484 /* si, di, bp, sp */
1485 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1487 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1488 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1491 /* flags, fpsr, fpcr, frame */
1492 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1494 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1497 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1500 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1501 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1502 /* SSE REX registers */
1503 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1507 /* The "default" register map used in 32bit mode. */
1509 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1511 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1512 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1513 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1514 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1515 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1516 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1517 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1520 static int const x86_64_int_parameter_registers[6] =
1522 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1523 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1526 static int const x86_64_ms_abi_int_parameter_registers[4] =
1528 2 /*RCX*/, 1 /*RDX*/,
1529 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1532 static int const x86_64_int_return_registers[4] =
1534 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1537 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Size of the register save area. */
1622 #define X86_64_VARARGS_SIZE (X86_64_REGPARM_MAX * UNITS_PER_WORD + X86_64_SSE_REGPARM_MAX * 16)
1624 /* Define the structure for the machine field in struct function. */
1626 struct stack_local_entry GTY(())
1628 unsigned short mode;
1631 struct stack_local_entry *next;
1634 /* Structure describing stack frame layout.
1635 Stack grows downward:
1641 saved frame pointer if frame_pointer_needed
1642 <- HARD_FRAME_POINTER
1647 [va_arg registers] (
1648 > to_allocate <- FRAME_POINTER
1658 HOST_WIDE_INT frame;
1660 int outgoing_arguments_size;
1663 HOST_WIDE_INT to_allocate;
1664 /* The offsets relative to ARG_POINTER. */
1665 HOST_WIDE_INT frame_pointer_offset;
1666 HOST_WIDE_INT hard_frame_pointer_offset;
1667 HOST_WIDE_INT stack_pointer_offset;
1669 /* When save_regs_using_mov is set, emit prologue using
1670 move instead of push instructions. */
1671 bool save_regs_using_mov;
1674 /* Code model option. */
1675 enum cmodel ix86_cmodel;
1677 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1679 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1681 /* Which unit we are generating floating point math for. */
1682 enum fpmath_unit ix86_fpmath;
1684 /* Which cpu are we scheduling for. */
1685 enum processor_type ix86_tune;
1687 /* Which instruction set architecture to use. */
1688 enum processor_type ix86_arch;
1690 /* true if sse prefetch instruction is not NOOP. */
1691 int x86_prefetch_sse;
1693 /* ix86_regparm_string as a number */
1694 static int ix86_regparm;
1696 /* -mstackrealign option */
1697 extern int ix86_force_align_arg_pointer;
1698 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1700 static rtx (*ix86_gen_leave) (void);
1701 static rtx (*ix86_gen_pop1) (rtx);
1702 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1703 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1704 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1705 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1706 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1708 /* Preferred alignment for stack boundary in bits. */
1709 unsigned int ix86_preferred_stack_boundary;
1711 /* Values 1-5: see jump.c */
1712 int ix86_branch_cost;
1714 /* Variables which are this size or smaller are put in the data/bss
1715 or ldata/lbss sections. */
1717 int ix86_section_threshold = 65536;
1719 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1720 char internal_label_prefix[16];
1721 int internal_label_prefix_len;
1723 /* Fence to use after loop using movnt. */
1726 /* Register class used for passing given 64bit part of the argument.
1727 These represent classes as documented by the PS ABI, with the exception
1728 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1729 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1731 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1732 whenever possible (upper half does contain padding). */
1733 enum x86_64_reg_class
1736 X86_64_INTEGER_CLASS,
1737 X86_64_INTEGERSI_CLASS,
1744 X86_64_COMPLEX_X87_CLASS,
1747 static const char * const x86_64_reg_class_name[] =
1749 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1750 "sseup", "x87", "x87up", "cplx87", "no"
1753 #define MAX_CLASSES 4
1755 /* Table of constants used by fldpi, fldln2, etc.... */
1756 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1757 static bool ext_80387_constants_init = 0;
1760 static struct machine_function * ix86_init_machine_status (void);
1761 static rtx ix86_function_value (const_tree, const_tree, bool);
1762 static int ix86_function_regparm (const_tree, const_tree);
1763 static void ix86_compute_frame_layout (struct ix86_frame *);
1764 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1768 /* The svr4 ABI for the i386 says that records and unions are returned
1770 #ifndef DEFAULT_PCC_STRUCT_RETURN
1771 #define DEFAULT_PCC_STRUCT_RETURN 1
1774 /* Bit flags that specify the ISA we are compiling for. */
1775 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1777 /* A mask of ix86_isa_flags that includes bit X if X
1778 was set or cleared on the command line. */
1779 static int ix86_isa_flags_explicit;
1781 /* Define a set of ISAs which are available when a given ISA is
1782 enabled. MMX and SSE ISAs are handled separately. */
1784 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1785 #define OPTION_MASK_ISA_3DNOW_SET \
1786 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1788 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1789 #define OPTION_MASK_ISA_SSE2_SET \
1790 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1791 #define OPTION_MASK_ISA_SSE3_SET \
1792 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1793 #define OPTION_MASK_ISA_SSSE3_SET \
1794 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1795 #define OPTION_MASK_ISA_SSE4_1_SET \
1796 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1797 #define OPTION_MASK_ISA_SSE4_2_SET \
1798 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1800 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1802 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1804 #define OPTION_MASK_ISA_SSE4A_SET \
1805 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1806 #define OPTION_MASK_ISA_SSE5_SET \
1807 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1809 /* Define a set of ISAs which aren't available when a given ISA is
1810 disabled. MMX and SSE ISAs are handled separately. */
1812 #define OPTION_MASK_ISA_MMX_UNSET \
1813 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1814 #define OPTION_MASK_ISA_3DNOW_UNSET \
1815 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1816 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1818 #define OPTION_MASK_ISA_SSE_UNSET \
1819 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1820 #define OPTION_MASK_ISA_SSE2_UNSET \
1821 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1822 #define OPTION_MASK_ISA_SSE3_UNSET \
1823 (OPTION_MASK_ISA_SSE3 \
1824 | OPTION_MASK_ISA_SSSE3_UNSET \
1825 | OPTION_MASK_ISA_SSE4A_UNSET )
1826 #define OPTION_MASK_ISA_SSSE3_UNSET \
1827 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1828 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1829 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1830 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1832 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1834 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1836 #define OPTION_MASK_ISA_SSE4A_UNSET \
1837 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1839 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1841 /* Vectorization library interface and handlers. */
1842 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1843 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1844 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1846 /* Implement TARGET_HANDLE_OPTION. */
1849 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1856 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1857 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1861 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1862 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1869 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1870 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1874 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1875 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1885 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1886 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1890 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1891 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1898 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1899 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1903 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1904 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1911 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1912 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1916 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1917 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1924 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1925 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1929 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1930 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1937 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1938 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1942 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1943 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1950 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1951 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1955 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1956 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1961 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1962 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1966 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1967 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1973 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1974 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1978 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1979 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1986 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1987 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1991 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1992 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2001 /* Sometimes certain combinations of command options do not make
2002 sense on a particular target machine. You can define a macro
2003 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2004 defined, is executed once just after all the command options have
2007 Don't use this macro to turn on various extra optimizations for
2008 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2011 override_options (void)
2014 int ix86_tune_defaulted = 0;
2015 int ix86_arch_specified = 0;
2016 unsigned int ix86_arch_mask, ix86_tune_mask;
2018 /* Comes from final.c -- no real reason to change it. */
2019 #define MAX_CODE_ALIGN 16
2023 const struct processor_costs *cost; /* Processor costs */
2024 const int align_loop; /* Default alignments. */
2025 const int align_loop_max_skip;
2026 const int align_jump;
2027 const int align_jump_max_skip;
2028 const int align_func;
2030 const processor_target_table[PROCESSOR_max] =
2032 {&i386_cost, 4, 3, 4, 3, 4},
2033 {&i486_cost, 16, 15, 16, 15, 16},
2034 {&pentium_cost, 16, 7, 16, 7, 16},
2035 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2036 {&geode_cost, 0, 0, 0, 0, 0},
2037 {&k6_cost, 32, 7, 32, 7, 32},
2038 {&athlon_cost, 16, 7, 16, 7, 16},
2039 {&pentium4_cost, 0, 0, 0, 0, 0},
2040 {&k8_cost, 16, 7, 16, 7, 16},
2041 {&nocona_cost, 0, 0, 0, 0, 0},
2042 {&core2_cost, 16, 10, 16, 10, 16},
2043 {&generic32_cost, 16, 7, 16, 7, 16},
2044 {&generic64_cost, 16, 10, 16, 10, 16},
2045 {&amdfam10_cost, 32, 24, 32, 7, 32}
2048 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2079 PTA_PREFETCH_SSE = 1 << 4,
2081 PTA_3DNOW_A = 1 << 6,
2085 PTA_POPCNT = 1 << 10,
2087 PTA_SSE4A = 1 << 12,
2088 PTA_NO_SAHF = 1 << 13,
2089 PTA_SSE4_1 = 1 << 14,
2090 PTA_SSE4_2 = 1 << 15,
2093 PTA_PCLMUL = 1 << 18
2098 const char *const name; /* processor name or nickname. */
2099 const enum processor_type processor;
2100 const unsigned /*enum pta_flags*/ flags;
2102 const processor_alias_table[] =
2104 {"i386", PROCESSOR_I386, 0},
2105 {"i486", PROCESSOR_I486, 0},
2106 {"i586", PROCESSOR_PENTIUM, 0},
2107 {"pentium", PROCESSOR_PENTIUM, 0},
2108 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2109 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2110 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2111 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2112 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2113 {"i686", PROCESSOR_PENTIUMPRO, 0},
2114 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2115 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2116 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2117 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2118 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2119 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2120 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2121 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2122 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2123 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2124 | PTA_CX16 | PTA_NO_SAHF)},
2125 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2126 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2129 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2130 |PTA_PREFETCH_SSE)},
2131 {"k6", PROCESSOR_K6, PTA_MMX},
2132 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2133 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2134 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2135 | PTA_PREFETCH_SSE)},
2136 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2137 | PTA_PREFETCH_SSE)},
2138 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2140 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2142 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2144 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2145 | PTA_MMX | PTA_SSE | PTA_SSE2
2147 {"k8", PROCESSOR_K8, (PTA_64BIT
2148 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2149 | PTA_SSE | PTA_SSE2
2151 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2152 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2153 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2155 {"opteron", PROCESSOR_K8, (PTA_64BIT
2156 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2157 | PTA_SSE | PTA_SSE2
2159 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2160 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2161 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2163 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2164 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2165 | PTA_SSE | PTA_SSE2
2167 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2168 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2169 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2171 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2172 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2173 | PTA_SSE | PTA_SSE2
2175 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2176 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2177 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2179 | PTA_CX16 | PTA_ABM)},
2180 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2181 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2182 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2184 | PTA_CX16 | PTA_ABM)},
2185 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2186 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2189 int const pta_size = ARRAY_SIZE (processor_alias_table);
2191 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2192 SUBTARGET_OVERRIDE_OPTIONS;
2195 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2196 SUBSUBTARGET_OVERRIDE_OPTIONS;
2199 /* -fPIC is the default for x86_64. */
2200 if (TARGET_MACHO && TARGET_64BIT)
2203 /* Set the default values for switches whose default depends on TARGET_64BIT
2204 in case they weren't overwritten by command line options. */
2207 /* Mach-O doesn't support omitting the frame pointer for now. */
2208 if (flag_omit_frame_pointer == 2)
2209 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2210 if (flag_asynchronous_unwind_tables == 2)
2211 flag_asynchronous_unwind_tables = 1;
2212 if (flag_pcc_struct_return == 2)
2213 flag_pcc_struct_return = 0;
2217 if (flag_omit_frame_pointer == 2)
2218 flag_omit_frame_pointer = 0;
2219 if (flag_asynchronous_unwind_tables == 2)
2220 flag_asynchronous_unwind_tables = 0;
2221 if (flag_pcc_struct_return == 2)
2222 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2225 /* Need to check -mtune=generic first. */
2226 if (ix86_tune_string)
2228 if (!strcmp (ix86_tune_string, "generic")
2229 || !strcmp (ix86_tune_string, "i686")
2230 /* As special support for cross compilers we read -mtune=native
2231 as -mtune=generic. With native compilers we won't see the
2232 -mtune=native, as it was changed by the driver. */
2233 || !strcmp (ix86_tune_string, "native"))
2236 ix86_tune_string = "generic64";
2238 ix86_tune_string = "generic32";
2240 else if (!strncmp (ix86_tune_string, "generic", 7))
2241 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2245 if (ix86_arch_string)
2246 ix86_tune_string = ix86_arch_string;
2247 if (!ix86_tune_string)
2249 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2250 ix86_tune_defaulted = 1;
2253 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2254 need to use a sensible tune option. */
2255 if (!strcmp (ix86_tune_string, "generic")
2256 || !strcmp (ix86_tune_string, "x86-64")
2257 || !strcmp (ix86_tune_string, "i686"))
2260 ix86_tune_string = "generic64";
2262 ix86_tune_string = "generic32";
2265 if (ix86_stringop_string)
2267 if (!strcmp (ix86_stringop_string, "rep_byte"))
2268 stringop_alg = rep_prefix_1_byte;
2269 else if (!strcmp (ix86_stringop_string, "libcall"))
2270 stringop_alg = libcall;
2271 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2272 stringop_alg = rep_prefix_4_byte;
2273 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2274 stringop_alg = rep_prefix_8_byte;
2275 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2276 stringop_alg = loop_1_byte;
2277 else if (!strcmp (ix86_stringop_string, "loop"))
2278 stringop_alg = loop;
2279 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2280 stringop_alg = unrolled_loop;
2282 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2284 if (!strcmp (ix86_tune_string, "x86-64"))
2285 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2286 "-mtune=generic instead as appropriate.");
2288 if (!ix86_arch_string)
2289 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2291 ix86_arch_specified = 1;
2293 if (!strcmp (ix86_arch_string, "generic"))
2294 error ("generic CPU can be used only for -mtune= switch");
2295 if (!strncmp (ix86_arch_string, "generic", 7))
2296 error ("bad value (%s) for -march= switch", ix86_arch_string);
2298 if (ix86_cmodel_string != 0)
2300 if (!strcmp (ix86_cmodel_string, "small"))
2301 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2302 else if (!strcmp (ix86_cmodel_string, "medium"))
2303 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2304 else if (!strcmp (ix86_cmodel_string, "large"))
2305 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2307 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2308 else if (!strcmp (ix86_cmodel_string, "32"))
2309 ix86_cmodel = CM_32;
2310 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2311 ix86_cmodel = CM_KERNEL;
2313 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2317 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2318 use of rip-relative addressing. This eliminates fixups that
2319 would otherwise be needed if this object is to be placed in a
2320 DLL, and is essentially just as efficient as direct addressing. */
2321 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2322 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2323 else if (TARGET_64BIT)
2324 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2326 ix86_cmodel = CM_32;
2328 if (ix86_asm_string != 0)
2331 && !strcmp (ix86_asm_string, "intel"))
2332 ix86_asm_dialect = ASM_INTEL;
2333 else if (!strcmp (ix86_asm_string, "att"))
2334 ix86_asm_dialect = ASM_ATT;
2336 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2338 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2339 error ("code model %qs not supported in the %s bit mode",
2340 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2341 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2342 sorry ("%i-bit mode not compiled in",
2343 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2345 for (i = 0; i < pta_size; i++)
2346 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2348 ix86_arch = processor_alias_table[i].processor;
2349 /* Default cpu tuning to the architecture. */
2350 ix86_tune = ix86_arch;
2352 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2353 error ("CPU you selected does not support x86-64 "
2356 if (processor_alias_table[i].flags & PTA_MMX
2357 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2358 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2359 if (processor_alias_table[i].flags & PTA_3DNOW
2360 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2361 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2362 if (processor_alias_table[i].flags & PTA_3DNOW_A
2363 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2364 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2365 if (processor_alias_table[i].flags & PTA_SSE
2366 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2367 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2368 if (processor_alias_table[i].flags & PTA_SSE2
2369 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2370 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2371 if (processor_alias_table[i].flags & PTA_SSE3
2372 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2373 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2374 if (processor_alias_table[i].flags & PTA_SSSE3
2375 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2376 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2377 if (processor_alias_table[i].flags & PTA_SSE4_1
2378 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2379 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2380 if (processor_alias_table[i].flags & PTA_SSE4_2
2381 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2382 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2383 if (processor_alias_table[i].flags & PTA_SSE4A
2384 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2385 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2386 if (processor_alias_table[i].flags & PTA_SSE5
2387 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2388 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2390 if (processor_alias_table[i].flags & PTA_ABM)
2392 if (processor_alias_table[i].flags & PTA_CX16)
2393 x86_cmpxchg16b = true;
2394 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2396 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2397 x86_prefetch_sse = true;
2398 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2400 if (processor_alias_table[i].flags & PTA_AES)
2402 if (processor_alias_table[i].flags & PTA_PCLMUL)
2409 error ("bad value (%s) for -march= switch", ix86_arch_string);
2411 ix86_arch_mask = 1u << ix86_arch;
2412 for (i = 0; i < X86_ARCH_LAST; ++i)
2413 ix86_arch_features[i] &= ix86_arch_mask;
2415 for (i = 0; i < pta_size; i++)
2416 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2418 ix86_tune = processor_alias_table[i].processor;
2419 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2421 if (ix86_tune_defaulted)
2423 ix86_tune_string = "x86-64";
2424 for (i = 0; i < pta_size; i++)
2425 if (! strcmp (ix86_tune_string,
2426 processor_alias_table[i].name))
2428 ix86_tune = processor_alias_table[i].processor;
2431 error ("CPU you selected does not support x86-64 "
2434 /* Intel CPUs have always interpreted SSE prefetch instructions as
2435 NOPs; so, we can enable SSE prefetch instructions even when
2436 -mtune (rather than -march) points us to a processor that has them.
2437 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2438 higher processors. */
2440 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2441 x86_prefetch_sse = true;
2445 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2447 /* Enable SSE2 if AES or PCLMUL is enabled. */
2448 if ((x86_aes || x86_pclmul)
2449 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2451 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2452 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2455 ix86_tune_mask = 1u << ix86_tune;
2456 for (i = 0; i < X86_TUNE_LAST; ++i)
2457 ix86_tune_features[i] &= ix86_tune_mask;
2460 ix86_cost = &size_cost;
2462 ix86_cost = processor_target_table[ix86_tune].cost;
2464 /* Arrange to set up i386_stack_locals for all functions. */
2465 init_machine_status = ix86_init_machine_status;
2467 /* Validate -mregparm= value. */
2468 if (ix86_regparm_string)
2471 warning (0, "-mregparm is ignored in 64-bit mode");
2472 i = atoi (ix86_regparm_string);
2473 if (i < 0 || i > REGPARM_MAX)
2474 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2479 ix86_regparm = REGPARM_MAX;
2481 /* If the user has provided any of the -malign-* options,
2482 warn and use that value only if -falign-* is not set.
2483 Remove this code in GCC 3.2 or later. */
2484 if (ix86_align_loops_string)
2486 warning (0, "-malign-loops is obsolete, use -falign-loops");
2487 if (align_loops == 0)
2489 i = atoi (ix86_align_loops_string);
2490 if (i < 0 || i > MAX_CODE_ALIGN)
2491 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2493 align_loops = 1 << i;
2497 if (ix86_align_jumps_string)
2499 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2500 if (align_jumps == 0)
2502 i = atoi (ix86_align_jumps_string);
2503 if (i < 0 || i > MAX_CODE_ALIGN)
2504 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2506 align_jumps = 1 << i;
2510 if (ix86_align_funcs_string)
2512 warning (0, "-malign-functions is obsolete, use -falign-functions");
2513 if (align_functions == 0)
2515 i = atoi (ix86_align_funcs_string);
2516 if (i < 0 || i > MAX_CODE_ALIGN)
2517 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2519 align_functions = 1 << i;
2523 /* Default align_* from the processor table. */
2524 if (align_loops == 0)
2526 align_loops = processor_target_table[ix86_tune].align_loop;
2527 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2529 if (align_jumps == 0)
2531 align_jumps = processor_target_table[ix86_tune].align_jump;
2532 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2534 if (align_functions == 0)
2536 align_functions = processor_target_table[ix86_tune].align_func;
2539 /* Validate -mbranch-cost= value, or provide default. */
2540 ix86_branch_cost = ix86_cost->branch_cost;
2541 if (ix86_branch_cost_string)
2543 i = atoi (ix86_branch_cost_string);
2545 error ("-mbranch-cost=%d is not between 0 and 5", i);
2547 ix86_branch_cost = i;
2549 if (ix86_section_threshold_string)
2551 i = atoi (ix86_section_threshold_string);
2553 error ("-mlarge-data-threshold=%d is negative", i);
2555 ix86_section_threshold = i;
2558 if (ix86_tls_dialect_string)
2560 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2561 ix86_tls_dialect = TLS_DIALECT_GNU;
2562 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2563 ix86_tls_dialect = TLS_DIALECT_GNU2;
2564 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2565 ix86_tls_dialect = TLS_DIALECT_SUN;
2567 error ("bad value (%s) for -mtls-dialect= switch",
2568 ix86_tls_dialect_string);
2571 if (ix87_precision_string)
2573 i = atoi (ix87_precision_string);
2574 if (i != 32 && i != 64 && i != 80)
2575 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2580 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2582 /* Enable by default the SSE and MMX builtins. Do allow the user to
2583 explicitly disable any of these. In particular, disabling SSE and
2584 MMX for kernel code is extremely useful. */
2585 if (!ix86_arch_specified)
2587 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2588 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2591 warning (0, "-mrtd is ignored in 64bit mode");
2595 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2597 if (!ix86_arch_specified)
2599 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2601 /* i386 ABI does not specify red zone. It still makes sense to use it
2602 when programmer takes care to stack from being destroyed. */
2603 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2604 target_flags |= MASK_NO_RED_ZONE;
2607 /* Keep nonleaf frame pointers. */
2608 if (flag_omit_frame_pointer)
2609 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2610 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2611 flag_omit_frame_pointer = 1;
2613 /* If we're doing fast math, we don't care about comparison order
2614 wrt NaNs. This lets us use a shorter comparison sequence. */
2615 if (flag_finite_math_only)
2616 target_flags &= ~MASK_IEEE_FP;
2618 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2619 since the insns won't need emulation. */
2620 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2621 target_flags &= ~MASK_NO_FANCY_MATH_387;
2623 /* Likewise, if the target doesn't have a 387, or we've specified
2624 software floating point, don't use 387 inline intrinsics. */
2626 target_flags |= MASK_NO_FANCY_MATH_387;
2628 /* Turn on MMX builtins for -msse. */
2631 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2632 x86_prefetch_sse = true;
2635 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2636 if (TARGET_SSE4_2 || TARGET_ABM)
2639 /* Validate -mpreferred-stack-boundary= value, or provide default.
2640 The default of 128 bits is for Pentium III's SSE __m128. We can't
2641 change it because of optimize_size. Otherwise, we can't mix object
2642 files compiled with -Os and -On. */
2643 ix86_preferred_stack_boundary = 128;
2644 if (ix86_preferred_stack_boundary_string)
2646 i = atoi (ix86_preferred_stack_boundary_string);
2647 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2648 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2649 TARGET_64BIT ? 4 : 2);
2651 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2654 /* Accept -msseregparm only if at least SSE support is enabled. */
2655 if (TARGET_SSEREGPARM
2657 error ("-msseregparm used without SSE enabled");
2659 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2660 if (ix86_fpmath_string != 0)
2662 if (! strcmp (ix86_fpmath_string, "387"))
2663 ix86_fpmath = FPMATH_387;
2664 else if (! strcmp (ix86_fpmath_string, "sse"))
2668 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2669 ix86_fpmath = FPMATH_387;
2672 ix86_fpmath = FPMATH_SSE;
2674 else if (! strcmp (ix86_fpmath_string, "387,sse")
2675 || ! strcmp (ix86_fpmath_string, "sse,387"))
2679 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2680 ix86_fpmath = FPMATH_387;
2682 else if (!TARGET_80387)
2684 warning (0, "387 instruction set disabled, using SSE arithmetics");
2685 ix86_fpmath = FPMATH_SSE;
2688 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2691 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2694 /* If the i387 is disabled, then do not return values in it. */
2696 target_flags &= ~MASK_FLOAT_RETURNS;
2698 /* Use external vectorized library in vectorizing intrinsics. */
2699 if (ix86_veclibabi_string)
2701 if (strcmp (ix86_veclibabi_string, "svml") == 0)
2702 ix86_veclib_handler = ix86_veclibabi_svml;
2703 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
2704 ix86_veclib_handler = ix86_veclibabi_acml;
2706 error ("unknown vectorization library ABI type (%s) for "
2707 "-mveclibabi= switch", ix86_veclibabi_string);
2710 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2711 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2713 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2715 /* ??? Unwind info is not correct around the CFG unless either a frame
2716 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2717 unwind info generation to be aware of the CFG and propagating states
2719 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2720 || flag_exceptions || flag_non_call_exceptions)
2721 && flag_omit_frame_pointer
2722 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2724 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2725 warning (0, "unwind tables currently require either a frame pointer "
2726 "or -maccumulate-outgoing-args for correctness");
2727 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2730 /* If stack probes are required, the space used for large function
2731 arguments on the stack must also be probed, so enable
2732 -maccumulate-outgoing-args so this happens in the prologue. */
2733 if (TARGET_STACK_PROBE
2734 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2736 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2737 warning (0, "stack probing requires -maccumulate-outgoing-args "
2739 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2742 /* For sane SSE instruction set generation we need fcomi instruction.
2743 It is safe to enable all CMOVE instructions. */
2747 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2750 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2751 p = strchr (internal_label_prefix, 'X');
2752 internal_label_prefix_len = p - internal_label_prefix;
2756 /* When scheduling description is not available, disable scheduler pass
2757 so it won't slow down the compilation and make x87 code slower. */
2758 if (!TARGET_SCHEDULE)
2759 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2761 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2762 set_param_value ("simultaneous-prefetches",
2763 ix86_cost->simultaneous_prefetches);
2764 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2765 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2766 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2767 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2768 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2769 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2771 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2772 can be optimized to ap = __builtin_next_arg (0).
2773 For abi switching it should be corrected. */
2774 if (!TARGET_64BIT || DEFAULT_ABI == MS_ABI)
2775 targetm.expand_builtin_va_start = NULL;
2779 ix86_gen_leave = gen_leave_rex64;
2780 ix86_gen_pop1 = gen_popdi1;
2781 ix86_gen_add3 = gen_adddi3;
2782 ix86_gen_sub3 = gen_subdi3;
2783 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
2784 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
2785 ix86_gen_monitor = gen_sse3_monitor64;
2789 ix86_gen_leave = gen_leave;
2790 ix86_gen_pop1 = gen_popsi1;
2791 ix86_gen_add3 = gen_addsi3;
2792 ix86_gen_sub3 = gen_subsi3;
2793 ix86_gen_sub3_carry = gen_subsi3_carry;
2794 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
2795 ix86_gen_monitor = gen_sse3_monitor;
2799 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
2801 target_flags |= MASK_CLD & ~target_flags_explicit;
2805 /* Return true if this goes in large data/bss. */
2808 ix86_in_large_data_p (tree exp)
2810 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2813 /* Functions are never large data. */
2814 if (TREE_CODE (exp) == FUNCTION_DECL)
2817 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2819 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2820 if (strcmp (section, ".ldata") == 0
2821 || strcmp (section, ".lbss") == 0)
2827 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2829 /* If this is an incomplete type with size 0, then we can't put it
2830 in data because it might be too big when completed. */
2831 if (!size || size > ix86_section_threshold)
2838 /* Switch to the appropriate section for output of DECL.
2839 DECL is either a `VAR_DECL' node or a constant of some sort.
2840 RELOC indicates whether forming the initial value of DECL requires
2841 link-time relocations. */
2843 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2847 x86_64_elf_select_section (tree decl, int reloc,
2848 unsigned HOST_WIDE_INT align)
2850 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2851 && ix86_in_large_data_p (decl))
2853 const char *sname = NULL;
2854 unsigned int flags = SECTION_WRITE;
2855 switch (categorize_decl_for_section (decl, reloc))
2860 case SECCAT_DATA_REL:
2861 sname = ".ldata.rel";
2863 case SECCAT_DATA_REL_LOCAL:
2864 sname = ".ldata.rel.local";
2866 case SECCAT_DATA_REL_RO:
2867 sname = ".ldata.rel.ro";
2869 case SECCAT_DATA_REL_RO_LOCAL:
2870 sname = ".ldata.rel.ro.local";
2874 flags |= SECTION_BSS;
2877 case SECCAT_RODATA_MERGE_STR:
2878 case SECCAT_RODATA_MERGE_STR_INIT:
2879 case SECCAT_RODATA_MERGE_CONST:
2883 case SECCAT_SRODATA:
2890 /* We don't split these for medium model. Place them into
2891 default sections and hope for best. */
2893 case SECCAT_EMUTLS_VAR:
2894 case SECCAT_EMUTLS_TMPL:
2899 /* We might get called with string constants, but get_named_section
2900 doesn't like them as they are not DECLs. Also, we need to set
2901 flags in that case. */
2903 return get_section (sname, flags, NULL);
2904 return get_named_section (decl, sname, reloc);
2907 return default_elf_select_section (decl, reloc, align);
2910 /* Build up a unique section name, expressed as a
2911 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2912 RELOC indicates whether the initial value of EXP requires
2913 link-time relocations. */
2915 static void ATTRIBUTE_UNUSED
2916 x86_64_elf_unique_section (tree decl, int reloc)
2918 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2919 && ix86_in_large_data_p (decl))
2921 const char *prefix = NULL;
2922 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2923 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2925 switch (categorize_decl_for_section (decl, reloc))
2928 case SECCAT_DATA_REL:
2929 case SECCAT_DATA_REL_LOCAL:
2930 case SECCAT_DATA_REL_RO:
2931 case SECCAT_DATA_REL_RO_LOCAL:
2932 prefix = one_only ? ".ld" : ".ldata";
2935 prefix = one_only ? ".lb" : ".lbss";
2938 case SECCAT_RODATA_MERGE_STR:
2939 case SECCAT_RODATA_MERGE_STR_INIT:
2940 case SECCAT_RODATA_MERGE_CONST:
2941 prefix = one_only ? ".lr" : ".lrodata";
2943 case SECCAT_SRODATA:
2950 /* We don't split these for medium model. Place them into
2951 default sections and hope for best. */
2953 case SECCAT_EMUTLS_VAR:
2954 prefix = targetm.emutls.var_section;
2956 case SECCAT_EMUTLS_TMPL:
2957 prefix = targetm.emutls.tmpl_section;
2962 const char *name, *linkonce;
2965 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2966 name = targetm.strip_name_encoding (name);
2968 /* If we're using one_only, then there needs to be a .gnu.linkonce
2969 prefix to the section name. */
2970 linkonce = one_only ? ".gnu.linkonce" : "";
2972 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
2974 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
2978 default_unique_section (decl, reloc);
2981 #ifdef COMMON_ASM_OP
2982 /* This says how to output assembler code to declare an
2983 uninitialized external linkage data object.
2985 For medium model x86-64 we need to use .largecomm opcode for
2988 x86_elf_aligned_common (FILE *file,
2989 const char *name, unsigned HOST_WIDE_INT size,
2992 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2993 && size > (unsigned int)ix86_section_threshold)
2994 fprintf (file, ".largecomm\t");
2996 fprintf (file, "%s", COMMON_ASM_OP);
2997 assemble_name (file, name);
2998 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2999 size, align / BITS_PER_UNIT);
3003 /* Utility function for targets to use in implementing
3004 ASM_OUTPUT_ALIGNED_BSS. */
3007 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3008 const char *name, unsigned HOST_WIDE_INT size,
3011 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3012 && size > (unsigned int)ix86_section_threshold)
3013 switch_to_section (get_named_section (decl, ".lbss", 0));
3015 switch_to_section (bss_section);
3016 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
3017 #ifdef ASM_DECLARE_OBJECT_NAME
3018 last_assemble_variable_decl = decl;
3019 ASM_DECLARE_OBJECT_NAME (file, name, decl);
3021 /* Standard thing is just output label for the object. */
3022 ASM_OUTPUT_LABEL (file, name);
3023 #endif /* ASM_DECLARE_OBJECT_NAME */
3024 ASM_OUTPUT_SKIP (file, size ? size : 1);
3028 optimization_options (int level, int size ATTRIBUTE_UNUSED)
3030 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
3031 make the problem with not enough registers even worse. */
3032 #ifdef INSN_SCHEDULING
3034 flag_schedule_insns = 0;
3038 /* The Darwin libraries never set errno, so we might as well
3039 avoid calling them when that's the only reason we would. */
3040 flag_errno_math = 0;
3042 /* The default values of these switches depend on the TARGET_64BIT
3043 that is not known at this moment. Mark these values with 2 and
3044 let user the to override these. In case there is no command line option
3045 specifying them, we will set the defaults in override_options. */
3047 flag_omit_frame_pointer = 2;
3048 flag_pcc_struct_return = 2;
3049 flag_asynchronous_unwind_tables = 2;
3050 flag_vect_cost_model = 1;
3051 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
3052 SUBTARGET_OPTIMIZATION_OPTIONS;
3056 /* Decide whether we can make a sibling call to a function. DECL is the
3057 declaration of the function being targeted by the call and EXP is the
3058 CALL_EXPR representing the call. */
3061 ix86_function_ok_for_sibcall (tree decl, tree exp)
3066 /* If we are generating position-independent code, we cannot sibcall
3067 optimize any indirect call, or a direct call to a global function,
3068 as the PLT requires %ebx be live. */
3069 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3076 func = TREE_TYPE (CALL_EXPR_FN (exp));
3077 if (POINTER_TYPE_P (func))
3078 func = TREE_TYPE (func);
3081 /* Check that the return value locations are the same. Like
3082 if we are returning floats on the 80387 register stack, we cannot
3083 make a sibcall from a function that doesn't return a float to a
3084 function that does or, conversely, from a function that does return
3085 a float to a function that doesn't; the necessary stack adjustment
3086 would not be executed. This is also the place we notice
3087 differences in the return value ABI. Note that it is ok for one
3088 of the functions to have void return type as long as the return
3089 value of the other is passed in a register. */
3090 a = ix86_function_value (TREE_TYPE (exp), func, false);
3091 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3093 if (STACK_REG_P (a) || STACK_REG_P (b))
3095 if (!rtx_equal_p (a, b))
3098 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3100 else if (!rtx_equal_p (a, b))
3103 /* If this call is indirect, we'll need to be able to use a call-clobbered
3104 register for the address of the target function. Make sure that all
3105 such registers are not used for passing parameters. */
3106 if (!decl && !TARGET_64BIT)
3110 /* We're looking at the CALL_EXPR, we need the type of the function. */
3111 type = CALL_EXPR_FN (exp); /* pointer expression */
3112 type = TREE_TYPE (type); /* pointer type */
3113 type = TREE_TYPE (type); /* function type */
3115 if (ix86_function_regparm (type, NULL) >= 3)
3117 /* ??? Need to count the actual number of registers to be used,
3118 not the possible number of registers. Fix later. */
3123 /* Dllimport'd functions are also called indirectly. */
3124 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3125 && decl && DECL_DLLIMPORT_P (decl)
3126 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3129 /* If we forced aligned the stack, then sibcalling would unalign the
3130 stack, which may break the called function. */
3131 if (cfun->machine->force_align_arg_pointer)
3134 /* Otherwise okay. That also includes certain types of indirect calls. */
3138 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3139 calling convention attributes;
3140 arguments as in struct attribute_spec.handler. */
3143 ix86_handle_cconv_attribute (tree *node, tree name,
3145 int flags ATTRIBUTE_UNUSED,
3148 if (TREE_CODE (*node) != FUNCTION_TYPE
3149 && TREE_CODE (*node) != METHOD_TYPE
3150 && TREE_CODE (*node) != FIELD_DECL
3151 && TREE_CODE (*node) != TYPE_DECL)
3153 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3154 IDENTIFIER_POINTER (name));
3155 *no_add_attrs = true;
3159 /* Can combine regparm with all attributes but fastcall. */
3160 if (is_attribute_p ("regparm", name))
3164 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3166 error ("fastcall and regparm attributes are not compatible");
3169 cst = TREE_VALUE (args);
3170 if (TREE_CODE (cst) != INTEGER_CST)
3172 warning (OPT_Wattributes,
3173 "%qs attribute requires an integer constant argument",
3174 IDENTIFIER_POINTER (name));
3175 *no_add_attrs = true;
3177 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3179 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3180 IDENTIFIER_POINTER (name), REGPARM_MAX);
3181 *no_add_attrs = true;
3185 && lookup_attribute (ix86_force_align_arg_pointer_string,
3186 TYPE_ATTRIBUTES (*node))
3187 && compare_tree_int (cst, REGPARM_MAX-1))
3189 error ("%s functions limited to %d register parameters",
3190 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3198 /* Do not warn when emulating the MS ABI. */
3199 if (TREE_CODE (*node) != FUNCTION_TYPE || !ix86_function_type_abi (*node))
3200 warning (OPT_Wattributes, "%qs attribute ignored",
3201 IDENTIFIER_POINTER (name));
3202 *no_add_attrs = true;
3206 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3207 if (is_attribute_p ("fastcall", name))
3209 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3211 error ("fastcall and cdecl attributes are not compatible");
3213 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3215 error ("fastcall and stdcall attributes are not compatible");
3217 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3219 error ("fastcall and regparm attributes are not compatible");
3223 /* Can combine stdcall with fastcall (redundant), regparm and
3225 else if (is_attribute_p ("stdcall", name))
3227 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3229 error ("stdcall and cdecl attributes are not compatible");
3231 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3233 error ("stdcall and fastcall attributes are not compatible");
3237 /* Can combine cdecl with regparm and sseregparm. */
3238 else if (is_attribute_p ("cdecl", name))
3240 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3242 error ("stdcall and cdecl attributes are not compatible");
3244 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3246 error ("fastcall and cdecl attributes are not compatible");
3250 /* Can combine sseregparm with all attributes. */
3255 /* Return 0 if the attributes for two types are incompatible, 1 if they
3256 are compatible, and 2 if they are nearly compatible (which causes a
3257 warning to be generated). */
3260 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3262 /* Check for mismatch of non-default calling convention. */
3263 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3265 if (TREE_CODE (type1) != FUNCTION_TYPE
3266 && TREE_CODE (type1) != METHOD_TYPE)
3269 /* Check for mismatched fastcall/regparm types. */
3270 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3271 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3272 || (ix86_function_regparm (type1, NULL)
3273 != ix86_function_regparm (type2, NULL)))
3276 /* Check for mismatched sseregparm types. */
3277 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3278 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3281 /* Check for mismatched return types (cdecl vs stdcall). */
3282 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3283 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3289 /* Return the regparm value for a function with the indicated TYPE and DECL.
3290 DECL may be NULL when calling function indirectly
3291 or considering a libcall. */
3294 ix86_function_regparm (const_tree type, const_tree decl)
3297 int regparm = ix86_regparm;
3299 static bool error_issued;
3303 if (ix86_function_type_abi (type) == DEFAULT_ABI)
3305 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
3308 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3312 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3314 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
3316 /* We can't use regparm(3) for nested functions because
3317 these pass static chain pointer in %ecx register. */
3318 if (!error_issued && regparm == 3
3319 && decl_function_context (decl)
3320 && !DECL_NO_STATIC_CHAIN (decl))
3322 error ("nested functions are limited to 2 register parameters");
3323 error_issued = true;
3331 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3334 /* Use register calling convention for local functions when possible. */
3335 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3336 && flag_unit_at_a_time && !profile_flag)
3338 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3339 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3342 int local_regparm, globals = 0, regno;
3345 /* Make sure no regparm register is taken by a
3346 fixed register variable. */
3347 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3348 if (fixed_regs[local_regparm])
3351 /* We can't use regparm(3) for nested functions as these use
3352 static chain pointer in third argument. */
3353 if (local_regparm == 3
3354 && (decl_function_context (decl)
3355 || ix86_force_align_arg_pointer)
3356 && !DECL_NO_STATIC_CHAIN (decl))
3359 /* If the function realigns its stackpointer, the prologue will
3360 clobber %ecx. If we've already generated code for the callee,
3361 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3362 scanning the attributes for the self-realigning property. */
3363 f = DECL_STRUCT_FUNCTION (decl);
3364 if (local_regparm == 3
3365 && (f ? !!f->machine->force_align_arg_pointer
3366 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3367 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3370 /* Each fixed register usage increases register pressure,
3371 so less registers should be used for argument passing.
3372 This functionality can be overriden by an explicit
3374 for (regno = 0; regno <= DI_REG; regno++)
3375 if (fixed_regs[regno])
3379 = globals < local_regparm ? local_regparm - globals : 0;
3381 if (local_regparm > regparm)
3382 regparm = local_regparm;
3389 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3390 DFmode (2) arguments in SSE registers for a function with the
3391 indicated TYPE and DECL. DECL may be NULL when calling function
3392 indirectly or considering a libcall. Otherwise return 0. */
3395 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3397 gcc_assert (!TARGET_64BIT);
3399 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3400 by the sseregparm attribute. */
3401 if (TARGET_SSEREGPARM
3402 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3409 error ("Calling %qD with attribute sseregparm without "
3410 "SSE/SSE2 enabled", decl);
3412 error ("Calling %qT with attribute sseregparm without "
3413 "SSE/SSE2 enabled", type);
3421 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3422 (and DFmode for SSE2) arguments in SSE registers. */
3423 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3425 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3426 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3428 return TARGET_SSE2 ? 2 : 1;
3434 /* Return true if EAX is live at the start of the function. Used by
3435 ix86_expand_prologue to determine if we need special help before
3436 calling allocate_stack_worker. */
3439 ix86_eax_live_at_start_p (void)
3441 /* Cheat. Don't bother working forward from ix86_function_regparm
3442 to the function type to whether an actual argument is located in
3443 eax. Instead just look at cfg info, which is still close enough
3444 to correct at this point. This gives false positives for broken
3445 functions that might use uninitialized data that happens to be
3446 allocated in eax, but who cares? */
3447 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3450 /* Value is the number of bytes of arguments automatically
3451 popped when returning from a subroutine call.
3452 FUNDECL is the declaration node of the function (as a tree),
3453 FUNTYPE is the data type of the function (as a tree),
3454 or for a library call it is an identifier node for the subroutine name.
3455 SIZE is the number of bytes of arguments passed on the stack.
3457 On the 80386, the RTD insn may be used to pop them if the number
3458 of args is fixed, but if the number is variable then the caller
3459 must pop them all. RTD can't be used for library calls now
3460 because the library is compiled with the Unix compiler.
3461 Use of RTD is a selectable option, since it is incompatible with
3462 standard Unix calling sequences. If the option is not selected,
3463 the caller must always pop the args.
3465 The attribute stdcall is equivalent to RTD on a per module basis. */
3468 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3472 /* None of the 64-bit ABIs pop arguments. */
3476 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3478 /* Cdecl functions override -mrtd, and never pop the stack. */
3479 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3481 /* Stdcall and fastcall functions will pop the stack if not
3483 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3484 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3487 if (rtd && ! stdarg_p (funtype))
3491 /* Lose any fake structure return argument if it is passed on the stack. */
3492 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3493 && !KEEP_AGGREGATE_RETURN_POINTER)
3495 int nregs = ix86_function_regparm (funtype, fundecl);
3497 return GET_MODE_SIZE (Pmode);
3503 /* Argument support functions. */
3505 /* Return true when register may be used to pass function parameters. */
3507 ix86_function_arg_regno_p (int regno)
3510 const int *parm_regs;
3515 return (regno < REGPARM_MAX
3516 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3518 return (regno < REGPARM_MAX
3519 || (TARGET_MMX && MMX_REGNO_P (regno)
3520 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3521 || (TARGET_SSE && SSE_REGNO_P (regno)
3522 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3527 if (SSE_REGNO_P (regno) && TARGET_SSE)
3532 if (TARGET_SSE && SSE_REGNO_P (regno)
3533 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3537 /* TODO: The function should depend on current function ABI but
3538 builtins.c would need updating then. Therefore we use the
3541 /* RAX is used as hidden argument to va_arg functions. */
3542 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
3545 if (DEFAULT_ABI == MS_ABI)
3546 parm_regs = x86_64_ms_abi_int_parameter_registers;
3548 parm_regs = x86_64_int_parameter_registers;
3549 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
3550 : X86_64_REGPARM_MAX); i++)
3551 if (regno == parm_regs[i])
3556 /* Return if we do not know how to pass TYPE solely in registers. */
3559 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3561 if (must_pass_in_stack_var_size_or_pad (mode, type))
3564 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3565 The layout_type routine is crafty and tries to trick us into passing
3566 currently unsupported vector types on the stack by using TImode. */
3567 return (!TARGET_64BIT && mode == TImode
3568 && type && TREE_CODE (type) != VECTOR_TYPE);
3571 /* It returns the size, in bytes, of the area reserved for arguments passed
3572 in registers for the function represented by fndecl dependent to the used
3575 ix86_reg_parm_stack_space (const_tree fndecl)
3578 /* For libcalls it is possible that there is no fndecl at hand.
3579 Therefore assume for this case the default abi of the target. */
3581 call_abi = DEFAULT_ABI;
3583 call_abi = ix86_function_abi (fndecl);
3589 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
3592 ix86_function_type_abi (const_tree fntype)
3594 if (TARGET_64BIT && fntype != NULL)
3597 if (DEFAULT_ABI == SYSV_ABI)
3598 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
3600 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
3602 if (DEFAULT_ABI == MS_ABI && abi == SYSV_ABI)
3603 sorry ("using sysv calling convention on target w64 is not supported");
3611 ix86_function_abi (const_tree fndecl)
3615 return ix86_function_type_abi (TREE_TYPE (fndecl));
3618 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
3621 ix86_cfun_abi (void)
3623 if (! cfun || ! TARGET_64BIT)
3625 return cfun->machine->call_abi;
3629 extern void init_regs (void);
3631 /* Implementation of call abi switching target hook. Specific to FNDECL
3632 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
3634 To prevent redudant calls of costy function init_regs (), it checks not to
3635 reset register usage for default abi. */
3637 ix86_call_abi_override (const_tree fndecl)
3639 if (fndecl == NULL_TREE)
3640 cfun->machine->call_abi = DEFAULT_ABI;
3642 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
3643 if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
3645 if (call_used_regs[4 /*RSI*/] != 0 || call_used_regs[5 /*RDI*/] != 0)
3647 call_used_regs[4 /*RSI*/] = 0;
3648 call_used_regs[5 /*RDI*/] = 0;
3652 else if (TARGET_64BIT)
3654 if (call_used_regs[4 /*RSI*/] != 1 || call_used_regs[5 /*RDI*/] != 1)
3656 call_used_regs[4 /*RSI*/] = 1;
3657 call_used_regs[5 /*RDI*/] = 1;
3663 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3664 for a call to a function whose data type is FNTYPE.
3665 For a library call, FNTYPE is 0. */
3668 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3669 tree fntype, /* tree ptr for function decl */
3670 rtx libname, /* SYMBOL_REF of library name or 0 */
3673 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3674 memset (cum, 0, sizeof (*cum));
3676 cum->call_abi = ix86_function_type_abi (fntype);
3677 /* Set up the number of registers to use for passing arguments. */
3678 cum->nregs = ix86_regparm;
3681 if (cum->call_abi != DEFAULT_ABI)
3682 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
3687 cum->sse_nregs = SSE_REGPARM_MAX;
3690 if (cum->call_abi != DEFAULT_ABI)
3691 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
3692 : X64_SSE_REGPARM_MAX;
3696 cum->mmx_nregs = MMX_REGPARM_MAX;
3697 cum->warn_sse = true;
3698 cum->warn_mmx = true;
3700 /* Because type might mismatch in between caller and callee, we need to
3701 use actual type of function for local calls.
3702 FIXME: cgraph_analyze can be told to actually record if function uses
3703 va_start so for local functions maybe_vaarg can be made aggressive
3705 FIXME: once typesytem is fixed, we won't need this code anymore. */
3707 fntype = TREE_TYPE (fndecl);
3708 cum->maybe_vaarg = (fntype
3709 ? (!prototype_p (fntype) || stdarg_p (fntype))
3714 /* If there are variable arguments, then we won't pass anything
3715 in registers in 32-bit mode. */
3716 if (stdarg_p (fntype))
3726 /* Use ecx and edx registers if function has fastcall attribute,
3727 else look for regparm information. */
3730 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3736 cum->nregs = ix86_function_regparm (fntype, fndecl);
3739 /* Set up the number of SSE registers used for passing SFmode
3740 and DFmode arguments. Warn for mismatching ABI. */
3741 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3745 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3746 But in the case of vector types, it is some vector mode.
3748 When we have only some of our vector isa extensions enabled, then there
3749 are some modes for which vector_mode_supported_p is false. For these
3750 modes, the generic vector support in gcc will choose some non-vector mode
3751 in order to implement the type. By computing the natural mode, we'll
3752 select the proper ABI location for the operand and not depend on whatever
3753 the middle-end decides to do with these vector types. */
3755 static enum machine_mode
3756 type_natural_mode (const_tree type)
3758 enum machine_mode mode = TYPE_MODE (type);
3760 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3762 HOST_WIDE_INT size = int_size_in_bytes (type);
3763 if ((size == 8 || size == 16)
3764 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3765 && TYPE_VECTOR_SUBPARTS (type) > 1)
3767 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3769 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3770 mode = MIN_MODE_VECTOR_FLOAT;
3772 mode = MIN_MODE_VECTOR_INT;
3774 /* Get the mode which has this inner mode and number of units. */
3775 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3776 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3777 && GET_MODE_INNER (mode) == innermode)
3787 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3788 this may not agree with the mode that the type system has chosen for the
3789 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3790 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3793 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3798 if (orig_mode != BLKmode)
3799 tmp = gen_rtx_REG (orig_mode, regno);
3802 tmp = gen_rtx_REG (mode, regno);
3803 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3804 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3810 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3811 of this code is to classify each 8bytes of incoming argument by the register
3812 class and assign registers accordingly. */
3814 /* Return the union class of CLASS1 and CLASS2.
3815 See the x86-64 PS ABI for details. */
3817 static enum x86_64_reg_class
3818 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3820 /* Rule #1: If both classes are equal, this is the resulting class. */
3821 if (class1 == class2)
3824 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3826 if (class1 == X86_64_NO_CLASS)
3828 if (class2 == X86_64_NO_CLASS)
3831 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3832 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3833 return X86_64_MEMORY_CLASS;
3835 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3836 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3837 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3838 return X86_64_INTEGERSI_CLASS;
3839 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3840 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3841 return X86_64_INTEGER_CLASS;
3843 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3845 if (class1 == X86_64_X87_CLASS
3846 || class1 == X86_64_X87UP_CLASS
3847 || class1 == X86_64_COMPLEX_X87_CLASS
3848 || class2 == X86_64_X87_CLASS
3849 || class2 == X86_64_X87UP_CLASS
3850 || class2 == X86_64_COMPLEX_X87_CLASS)
3851 return X86_64_MEMORY_CLASS;
3853 /* Rule #6: Otherwise class SSE is used. */
3854 return X86_64_SSE_CLASS;
3857 /* Classify the argument of type TYPE and mode MODE.
3858 CLASSES will be filled by the register class used to pass each word
3859 of the operand. The number of words is returned. In case the parameter
3860 should be passed in memory, 0 is returned. As a special case for zero
3861 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3863 BIT_OFFSET is used internally for handling records and specifies offset
3864 of the offset in bits modulo 256 to avoid overflow cases.
3866 See the x86-64 PS ABI for details.
3870 classify_argument (enum machine_mode mode, const_tree type,
3871 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3873 HOST_WIDE_INT bytes =
3874 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3875 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3877 /* Variable sized entities are always passed/returned in memory. */
3881 if (mode != VOIDmode
3882 && targetm.calls.must_pass_in_stack (mode, type))
3885 if (type && AGGREGATE_TYPE_P (type))
3889 enum x86_64_reg_class subclasses[MAX_CLASSES];
3891 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3895 for (i = 0; i < words; i++)
3896 classes[i] = X86_64_NO_CLASS;
3898 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3899 signalize memory class, so handle it as special case. */
3902 classes[0] = X86_64_NO_CLASS;
3906 /* Classify each field of record and merge classes. */
3907 switch (TREE_CODE (type))
3910 /* And now merge the fields of structure. */
3911 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3913 if (TREE_CODE (field) == FIELD_DECL)
3917 if (TREE_TYPE (field) == error_mark_node)
3920 /* Bitfields are always classified as integer. Handle them
3921 early, since later code would consider them to be
3922 misaligned integers. */
3923 if (DECL_BIT_FIELD (field))
3925 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3926 i < ((int_bit_position (field) + (bit_offset % 64))
3927 + tree_low_cst (DECL_SIZE (field), 0)
3930 merge_classes (X86_64_INTEGER_CLASS,
3935 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3936 TREE_TYPE (field), subclasses,
3937 (int_bit_position (field)
3938 + bit_offset) % 256);
3941 for (i = 0; i < num; i++)
3944 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3946 merge_classes (subclasses[i], classes[i + pos]);
3954 /* Arrays are handled as small records. */
3957 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3958 TREE_TYPE (type), subclasses, bit_offset);
3962 /* The partial classes are now full classes. */
3963 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3964 subclasses[0] = X86_64_SSE_CLASS;
3965 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3966 subclasses[0] = X86_64_INTEGER_CLASS;
3968 for (i = 0; i < words; i++)
3969 classes[i] = subclasses[i % num];
3974 case QUAL_UNION_TYPE:
3975 /* Unions are similar to RECORD_TYPE but offset is always 0.
3977 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3979 if (TREE_CODE (field) == FIELD_DECL)
3983 if (TREE_TYPE (field) == error_mark_node)
3986 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3987 TREE_TYPE (field), subclasses,
3991 for (i = 0; i < num; i++)
3992 classes[i] = merge_classes (subclasses[i], classes[i]);
4001 /* Final merger cleanup. */
4002 for (i = 0; i < words; i++)
4004 /* If one class is MEMORY, everything should be passed in
4006 if (classes[i] == X86_64_MEMORY_CLASS)
4009 /* The X86_64_SSEUP_CLASS should be always preceded by
4010 X86_64_SSE_CLASS. */
4011 if (classes[i] == X86_64_SSEUP_CLASS
4012 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
4013 classes[i] = X86_64_SSE_CLASS;
4015 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4016 if (classes[i] == X86_64_X87UP_CLASS
4017 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
4018 classes[i] = X86_64_SSE_CLASS;
4023 /* Compute alignment needed. We align all types to natural boundaries with
4024 exception of XFmode that is aligned to 64bits. */
4025 if (mode != VOIDmode && mode != BLKmode)
4027 int mode_alignment = GET_MODE_BITSIZE (mode);
4030 mode_alignment = 128;
4031 else if (mode == XCmode)
4032 mode_alignment = 256;
4033 if (COMPLEX_MODE_P (mode))
4034 mode_alignment /= 2;
4035 /* Misaligned fields are always returned in memory. */
4036 if (bit_offset % mode_alignment)
4040 /* for V1xx modes, just use the base mode */
4041 if (VECTOR_MODE_P (mode) && mode != V1DImode
4042 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
4043 mode = GET_MODE_INNER (mode);
4045 /* Classification of atomic types. */
4050 classes[0] = X86_64_SSE_CLASS;
4053 classes[0] = X86_64_SSE_CLASS;
4054 classes[1] = X86_64_SSEUP_CLASS;
4063 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
4064 classes[0] = X86_64_INTEGERSI_CLASS;
4066 classes[0] = X86_64_INTEGER_CLASS;
4070 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
4075 if (!(bit_offset % 64))
4076 classes[0] = X86_64_SSESF_CLASS;
4078 classes[0] = X86_64_SSE_CLASS;
4081 classes[0] = X86_64_SSEDF_CLASS;
4084 classes[0] = X86_64_X87_CLASS;
4085 classes[1] = X86_64_X87UP_CLASS;
4088 classes[0] = X86_64_SSE_CLASS;
4089 classes[1] = X86_64_SSEUP_CLASS;
4092 classes[0] = X86_64_SSE_CLASS;
4095 classes[0] = X86_64_SSEDF_CLASS;
4096 classes[1] = X86_64_SSEDF_CLASS;
4099 classes[0] = X86_64_COMPLEX_X87_CLASS;
4102 /* This modes is larger than 16 bytes. */
4110 classes[0] = X86_64_SSE_CLASS;
4111 classes[1] = X86_64_SSEUP_CLASS;
4118 classes[0] = X86_64_SSE_CLASS;
4124 gcc_assert (VECTOR_MODE_P (mode));
4129 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
4131 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
4132 classes[0] = X86_64_INTEGERSI_CLASS;
4134 classes[0] = X86_64_INTEGER_CLASS;
4135 classes[1] = X86_64_INTEGER_CLASS;
4136 return 1 + (bytes > 8);
4140 /* Examine the argument and return set number of register required in each
4141 class. Return 0 iff parameter should be passed in memory. */
4143 examine_argument (enum machine_mode mode, const_tree type, int in_return,
4144 int *int_nregs, int *sse_nregs)
4146 enum x86_64_reg_class regclass[MAX_CLASSES];
4147 int n = classify_argument (mode, type, regclass, 0);
4153 for (n--; n >= 0; n--)
4154 switch (regclass[n])
4156 case X86_64_INTEGER_CLASS:
4157 case X86_64_INTEGERSI_CLASS:
4160 case X86_64_SSE_CLASS:
4161 case X86_64_SSESF_CLASS:
4162 case X86_64_SSEDF_CLASS:
4165 case X86_64_NO_CLASS:
4166 case X86_64_SSEUP_CLASS:
4168 case X86_64_X87_CLASS:
4169 case X86_64_X87UP_CLASS:
4173 case X86_64_COMPLEX_X87_CLASS:
4174 return in_return ? 2 : 0;
4175 case X86_64_MEMORY_CLASS:
4181 /* Construct container for the argument used by GCC interface. See
4182 FUNCTION_ARG for the detailed description. */
4185 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
4186 const_tree type, int in_return, int nintregs, int nsseregs,
4187 const int *intreg, int sse_regno)
4189 /* The following variables hold the static issued_error state. */
4190 static bool issued_sse_arg_error;
4191 static bool issued_sse_ret_error;
4192 static bool issued_x87_ret_error;
4194 enum machine_mode tmpmode;
4196 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4197 enum x86_64_reg_class regclass[MAX_CLASSES];
4201 int needed_sseregs, needed_intregs;
4202 rtx exp[MAX_CLASSES];
4205 n = classify_argument (mode, type, regclass, 0);
4208 if (!examine_argument (mode, type, in_return, &needed_intregs,
4211 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4214 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4215 some less clueful developer tries to use floating-point anyway. */
4216 if (needed_sseregs && !TARGET_SSE)
4220 if (!issued_sse_ret_error)
4222 error ("SSE register return with SSE disabled");
4223 issued_sse_ret_error = true;
4226 else if (!issued_sse_arg_error)
4228 error ("SSE register argument with SSE disabled");
4229 issued_sse_arg_error = true;
4234 /* Likewise, error if the ABI requires us to return values in the
4235 x87 registers and the user specified -mno-80387. */
4236 if (!TARGET_80387 && in_return)
4237 for (i = 0; i < n; i++)
4238 if (regclass[i] == X86_64_X87_CLASS
4239 || regclass[i] == X86_64_X87UP_CLASS
4240 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4242 if (!issued_x87_ret_error)
4244 error ("x87 register return with x87 disabled");
4245 issued_x87_ret_error = true;
4250 /* First construct simple cases. Avoid SCmode, since we want to use
4251 single register to pass this type. */
4252 if (n == 1 && mode != SCmode)
4253 switch (regclass[0])
4255 case X86_64_INTEGER_CLASS:
4256 case X86_64_INTEGERSI_CLASS:
4257 return gen_rtx_REG (mode, intreg[0]);
4258 case X86_64_SSE_CLASS:
4259 case X86_64_SSESF_CLASS:
4260 case X86_64_SSEDF_CLASS:
4261 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4262 case X86_64_X87_CLASS:
4263 case X86_64_COMPLEX_X87_CLASS:
4264 return gen_rtx_REG (mode, FIRST_STACK_REG);
4265 case X86_64_NO_CLASS:
4266 /* Zero sized array, struct or class. */
4271 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4272 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4273 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4276 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4277 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4278 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4279 && regclass[1] == X86_64_INTEGER_CLASS
4280 && (mode == CDImode || mode == TImode || mode == TFmode)
4281 && intreg[0] + 1 == intreg[1])
4282 return gen_rtx_REG (mode, intreg[0]);
4284 /* Otherwise figure out the entries of the PARALLEL. */
4285 for (i = 0; i < n; i++)
4287 switch (regclass[i])
4289 case X86_64_NO_CLASS:
4291 case X86_64_INTEGER_CLASS:
4292 case X86_64_INTEGERSI_CLASS:
4293 /* Merge TImodes on aligned occasions here too. */
4294 if (i * 8 + 8 > bytes)
4295 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4296 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4300 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4301 if (tmpmode == BLKmode)
4303 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4304 gen_rtx_REG (tmpmode, *intreg),
4308 case X86_64_SSESF_CLASS:
4309 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4310 gen_rtx_REG (SFmode,
4311 SSE_REGNO (sse_regno)),
4315 case X86_64_SSEDF_CLASS:
4316 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4317 gen_rtx_REG (DFmode,
4318 SSE_REGNO (sse_regno)),
4322 case X86_64_SSE_CLASS:
4323 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4327 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4328 gen_rtx_REG (tmpmode,
4329 SSE_REGNO (sse_regno)),
4331 if (tmpmode == TImode)
4340 /* Empty aligned struct, union or class. */
4344 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4345 for (i = 0; i < nexps; i++)
4346 XVECEXP (ret, 0, i) = exp [i];
4350 /* Update the data in CUM to advance over an argument of mode MODE
4351 and data type TYPE. (TYPE is null for libcalls where that information
4352 may not be available.) */
4355 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4356 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4372 cum->words += words;
4373 cum->nregs -= words;
4374 cum->regno += words;
4376 if (cum->nregs <= 0)
4384 if (cum->float_in_sse < 2)
4387 if (cum->float_in_sse < 1)
4398 if (!type || !AGGREGATE_TYPE_P (type))
4400 cum->sse_words += words;
4401 cum->sse_nregs -= 1;
4402 cum->sse_regno += 1;
4403 if (cum->sse_nregs <= 0)
4416 if (!type || !AGGREGATE_TYPE_P (type))
4418 cum->mmx_words += words;
4419 cum->mmx_nregs -= 1;
4420 cum->mmx_regno += 1;
4421 if (cum->mmx_nregs <= 0)
4432 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4433 tree type, HOST_WIDE_INT words)
4435 int int_nregs, sse_nregs;
4437 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4438 cum->words += words;
4439 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4441 cum->nregs -= int_nregs;
4442 cum->sse_nregs -= sse_nregs;
4443 cum->regno += int_nregs;
4444 cum->sse_regno += sse_nregs;
4447 cum->words += words;
4451 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4452 HOST_WIDE_INT words)
4454 /* Otherwise, this should be passed indirect. */
4455 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4457 cum->words += words;
4466 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4467 tree type, int named ATTRIBUTE_UNUSED)
4469 HOST_WIDE_INT bytes, words;
4471 if (mode == BLKmode)
4472 bytes = int_size_in_bytes (type);
4474 bytes = GET_MODE_SIZE (mode);
4475 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4478 mode = type_natural_mode (type);
4480 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
4481 function_arg_advance_ms_64 (cum, bytes, words);
4482 else if (TARGET_64BIT)
4483 function_arg_advance_64 (cum, mode, type, words);
4485 function_arg_advance_32 (cum, mode, type, bytes, words);
4488 /* Define where to put the arguments to a function.
4489 Value is zero to push the argument on the stack,
4490 or a hard register in which to store the argument.
4492 MODE is the argument's machine mode.
4493 TYPE is the data type of the argument (as a tree).
4494 This is null for libcalls where that information may
4496 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4497 the preceding args and about the function being called.
4498 NAMED is nonzero if this argument is a named parameter
4499 (otherwise it is an extra parameter matching an ellipsis). */
4502 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4503 enum machine_mode orig_mode, tree type,
4504 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4506 static bool warnedsse, warnedmmx;
4508 /* Avoid the AL settings for the Unix64 ABI. */
4509 if (mode == VOIDmode)
4525 if (words <= cum->nregs)
4527 int regno = cum->regno;
4529 /* Fastcall allocates the first two DWORD (SImode) or
4530 smaller arguments to ECX and EDX if it isn't an
4536 || (type && AGGREGATE_TYPE_P (type)))
4539 /* ECX not EAX is the first allocated register. */
4540 if (regno == AX_REG)
4543 return gen_rtx_REG (mode, regno);
4548 if (cum->float_in_sse < 2)
4551 if (cum->float_in_sse < 1)
4561 if (!type || !AGGREGATE_TYPE_P (type))
4563 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4566 warning (0, "SSE vector argument without SSE enabled "
4570 return gen_reg_or_parallel (mode, orig_mode,
4571 cum->sse_regno + FIRST_SSE_REG);
4580 if (!type || !AGGREGATE_TYPE_P (type))
4582 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4585 warning (0, "MMX vector argument without MMX enabled "
4589 return gen_reg_or_parallel (mode, orig_mode,
4590 cum->mmx_regno + FIRST_MMX_REG);
4599 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4600 enum machine_mode orig_mode, tree type)
4602 /* Handle a hidden AL argument containing number of registers
4603 for varargs x86-64 functions. */
4604 if (mode == VOIDmode)
4605 return GEN_INT (cum->maybe_vaarg
4606 ? (cum->sse_nregs < 0
4607 ? (cum->call_abi == DEFAULT_ABI
4609 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4610 : X64_SSE_REGPARM_MAX))
4614 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4616 &x86_64_int_parameter_registers [cum->regno],
4621 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4622 enum machine_mode orig_mode, int named,
4623 HOST_WIDE_INT bytes)
4627 /* Avoid the AL settings for the Unix64 ABI. */
4628 if (mode == VOIDmode)
4631 /* If we've run out of registers, it goes on the stack. */
4632 if (cum->nregs == 0)
4635 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4637 /* Only floating point modes are passed in anything but integer regs. */
4638 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4641 regno = cum->regno + FIRST_SSE_REG;
4646 /* Unnamed floating parameters are passed in both the
4647 SSE and integer registers. */
4648 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4649 t2 = gen_rtx_REG (mode, regno);
4650 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4651 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4652 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4655 /* Handle aggregated types passed in register. */
4656 if (orig_mode == BLKmode)
4658 if (bytes > 0 && bytes <= 8)
4659 mode = (bytes > 4 ? DImode : SImode);
4660 if (mode == BLKmode)
4664 return gen_reg_or_parallel (mode, orig_mode, regno);
4668 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4669 tree type, int named)
4671 enum machine_mode mode = omode;
4672 HOST_WIDE_INT bytes, words;
4674 if (mode == BLKmode)
4675 bytes = int_size_in_bytes (type);
4677 bytes = GET_MODE_SIZE (mode);
4678 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4680 /* To simplify the code below, represent vector types with a vector mode
4681 even if MMX/SSE are not active. */
4682 if (type && TREE_CODE (type) == VECTOR_TYPE)
4683 mode = type_natural_mode (type);
4685 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
4686 return function_arg_ms_64 (cum, mode, omode, named, bytes);
4687 else if (TARGET_64BIT)
4688 return function_arg_64 (cum, mode, omode, type);
4690 return function_arg_32 (cum, mode, omode, type, bytes, words);
4693 /* A C expression that indicates when an argument must be passed by
4694 reference. If nonzero for an argument, a copy of that argument is
4695 made in memory and a pointer to the argument is passed instead of
4696 the argument itself. The pointer is passed in whatever way is
4697 appropriate for passing a pointer to that type. */
4700 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4701 enum machine_mode mode ATTRIBUTE_UNUSED,
4702 const_tree type, bool named ATTRIBUTE_UNUSED)
4704 /* See Windows x64 Software Convention. */
4705 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
4707 int msize = (int) GET_MODE_SIZE (mode);
4710 /* Arrays are passed by reference. */
4711 if (TREE_CODE (type) == ARRAY_TYPE)
4714 if (AGGREGATE_TYPE_P (type))
4716 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4717 are passed by reference. */
4718 msize = int_size_in_bytes (type);
4722 /* __m128 is passed by reference. */
4724 case 1: case 2: case 4: case 8:
4730 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4736 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4739 contains_aligned_value_p (tree type)
4741 enum machine_mode mode = TYPE_MODE (type);
4742 if (((TARGET_SSE && SSE_REG_MODE_P (mode)) || mode == TDmode)
4743 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4745 if (TYPE_ALIGN (type) < 128)
4748 if (AGGREGATE_TYPE_P (type))
4750 /* Walk the aggregates recursively. */
4751 switch (TREE_CODE (type))
4755 case QUAL_UNION_TYPE:
4759 /* Walk all the structure fields. */
4760 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4762 if (TREE_CODE (field) == FIELD_DECL
4763 && contains_aligned_value_p (TREE_TYPE (field)))
4770 /* Just for use if some languages passes arrays by value. */
4771 if (contains_aligned_value_p (TREE_TYPE (type)))
4782 /* Gives the alignment boundary, in bits, of an argument with the
4783 specified mode and type. */
4786 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4791 /* Since canonical type is used for call, we convert it to
4792 canonical type if needed. */
4793 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
4794 type = TYPE_CANONICAL (type);
4795 align = TYPE_ALIGN (type);
4798 align = GET_MODE_ALIGNMENT (mode);
4799 if (align < PARM_BOUNDARY)
4800 align = PARM_BOUNDARY;
4801 /* In 32bit, only _Decimal128 is aligned to its natural boundary. */
4802 if (!TARGET_64BIT && mode != TDmode)
4804 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4805 make an exception for SSE modes since these require 128bit
4808 The handling here differs from field_alignment. ICC aligns MMX
4809 arguments to 4 byte boundaries, while structure fields are aligned
4810 to 8 byte boundaries. */
4813 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)) && mode != TDmode)
4814 align = PARM_BOUNDARY;
4818 if (!contains_aligned_value_p (type))
4819 align = PARM_BOUNDARY;
4822 if (align > BIGGEST_ALIGNMENT)
4823 align = BIGGEST_ALIGNMENT;
4827 /* Return true if N is a possible register number of function value. */
4830 ix86_function_value_regno_p (int regno)
4837 case FIRST_FLOAT_REG:
4838 /* TODO: The function should depend on current function ABI but
4839 builtins.c would need updating then. Therefore we use the
4841 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
4843 return TARGET_FLOAT_RETURNS_IN_80387;
4849 if (TARGET_MACHO || TARGET_64BIT)
4857 /* Define how to find the value returned by a function.
4858 VALTYPE is the data type of the value (as a tree).
4859 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4860 otherwise, FUNC is 0. */
4863 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4864 const_tree fntype, const_tree fn)
4868 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4869 we normally prevent this case when mmx is not available. However
4870 some ABIs may require the result to be returned like DImode. */
4871 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4872 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4874 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4875 we prevent this case when sse is not available. However some ABIs
4876 may require the result to be returned like integer TImode. */
4877 else if (mode == TImode
4878 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4879 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4881 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4882 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4883 regno = FIRST_FLOAT_REG;
4885 /* Most things go in %eax. */
4888 /* Override FP return register with %xmm0 for local functions when
4889 SSE math is enabled or for functions with sseregparm attribute. */
4890 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4892 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4893 if ((sse_level >= 1 && mode == SFmode)
4894 || (sse_level == 2 && mode == DFmode))
4895 regno = FIRST_SSE_REG;
4898 return gen_rtx_REG (orig_mode, regno);
4902 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4907 /* Handle libcalls, which don't provide a type node. */
4908 if (valtype == NULL)
4920 return gen_rtx_REG (mode, FIRST_SSE_REG);
4923 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4927 return gen_rtx_REG (mode, AX_REG);
4931 ret = construct_container (mode, orig_mode, valtype, 1,
4932 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
4933 x86_64_int_return_registers, 0);
4935 /* For zero sized structures, construct_container returns NULL, but we
4936 need to keep rest of compiler happy by returning meaningful value. */
4938 ret = gen_rtx_REG (orig_mode, AX_REG);
4944 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4946 unsigned int regno = AX_REG;
4950 switch (GET_MODE_SIZE (mode))
4953 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
4954 && !COMPLEX_MODE_P (mode))
4955 regno = FIRST_SSE_REG;
4959 if (mode == SFmode || mode == DFmode)
4960 regno = FIRST_SSE_REG;
4966 return gen_rtx_REG (orig_mode, regno);
4970 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4971 enum machine_mode orig_mode, enum machine_mode mode)
4973 const_tree fn, fntype;
4976 if (fntype_or_decl && DECL_P (fntype_or_decl))
4977 fn = fntype_or_decl;
4978 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4980 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
4981 return function_value_ms_64 (orig_mode, mode);
4982 else if (TARGET_64BIT)
4983 return function_value_64 (orig_mode, mode, valtype);
4985 return function_value_32 (orig_mode, mode, fntype, fn);
4989 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4990 bool outgoing ATTRIBUTE_UNUSED)
4992 enum machine_mode mode, orig_mode;
4994 orig_mode = TYPE_MODE (valtype);
4995 mode = type_natural_mode (valtype);
4996 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
5000 ix86_libcall_value (enum machine_mode mode)
5002 return ix86_function_value_1 (NULL, NULL, mode, mode);
5005 /* Return true iff type is returned in memory. */
5007 static int ATTRIBUTE_UNUSED
5008 return_in_memory_32 (const_tree type, enum machine_mode mode)
5012 if (mode == BLKmode)
5015 size = int_size_in_bytes (type);
5017 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
5020 if (VECTOR_MODE_P (mode) || mode == TImode)
5022 /* User-created vectors small enough to fit in EAX. */
5026 /* MMX/3dNow values are returned in MM0,
5027 except when it doesn't exits. */
5029 return (TARGET_MMX ? 0 : 1);
5031 /* SSE values are returned in XMM0, except when it doesn't exist. */
5033 return (TARGET_SSE ? 0 : 1);
5047 static int ATTRIBUTE_UNUSED
5048 return_in_memory_64 (const_tree type, enum machine_mode mode)
5050 int needed_intregs, needed_sseregs;
5051 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
5054 static int ATTRIBUTE_UNUSED
5055 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
5057 HOST_WIDE_INT size = int_size_in_bytes (type);
5059 /* __m128 is returned in xmm0. */
5060 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
5061 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
5064 /* Otherwise, the size must be exactly in [1248]. */
5065 return (size != 1 && size != 2 && size != 4 && size != 8);
5069 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5071 #ifdef SUBTARGET_RETURN_IN_MEMORY
5072 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
5074 const enum machine_mode mode = type_natural_mode (type);
5076 if (TARGET_64BIT_MS_ABI)
5077 return return_in_memory_ms_64 (type, mode);
5078 else if (TARGET_64BIT)
5079 return return_in_memory_64 (type, mode);
5081 return return_in_memory_32 (type, mode);
5085 /* Return false iff TYPE is returned in memory. This version is used
5086 on Solaris 10. It is similar to the generic ix86_return_in_memory,
5087 but differs notably in that when MMX is available, 8-byte vectors
5088 are returned in memory, rather than in MMX registers. */
5091 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5094 enum machine_mode mode = type_natural_mode (type);
5097 return return_in_memory_64 (type, mode);
5099 if (mode == BLKmode)
5102 size = int_size_in_bytes (type);
5104 if (VECTOR_MODE_P (mode))
5106 /* Return in memory only if MMX registers *are* available. This
5107 seems backwards, but it is consistent with the existing
5114 else if (mode == TImode)
5116 else if (mode == XFmode)
5122 /* When returning SSE vector types, we have a choice of either
5123 (1) being abi incompatible with a -march switch, or
5124 (2) generating an error.
5125 Given no good solution, I think the safest thing is one warning.
5126 The user won't be able to use -Werror, but....
5128 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
5129 called in response to actually generating a caller or callee that
5130 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
5131 via aggregate_value_p for general type probing from tree-ssa. */
5134 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
5136 static bool warnedsse, warnedmmx;
5138 if (!TARGET_64BIT && type)
5140 /* Look at the return type of the function, not the function type. */
5141 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
5143 if (!TARGET_SSE && !warnedsse)
5146 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
5149 warning (0, "SSE vector return without SSE enabled "
5154 if (!TARGET_MMX && !warnedmmx)
5156 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
5159 warning (0, "MMX vector return without MMX enabled "
5169 /* Create the va_list data type. */
5172 ix86_build_builtin_va_list (void)
5174 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
5176 /* For i386 we use plain pointer to argument area. */
5177 if (!TARGET_64BIT || ix86_cfun_abi () == MS_ABI)
5178 return build_pointer_type (char_type_node);
5180 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5181 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5183 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
5184 unsigned_type_node);
5185 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
5186 unsigned_type_node);
5187 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5189 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5192 va_list_gpr_counter_field = f_gpr;
5193 va_list_fpr_counter_field = f_fpr;
5195 DECL_FIELD_CONTEXT (f_gpr) = record;
5196 DECL_FIELD_CONTEXT (f_fpr) = record;
5197 DECL_FIELD_CONTEXT (f_ovf) = record;
5198 DECL_FIELD_CONTEXT (f_sav) = record;
5200 TREE_CHAIN (record) = type_decl;
5201 TYPE_NAME (record) = type_decl;
5202 TYPE_FIELDS (record) = f_gpr;
5203 TREE_CHAIN (f_gpr) = f_fpr;
5204 TREE_CHAIN (f_fpr) = f_ovf;
5205 TREE_CHAIN (f_ovf) = f_sav;
5207 layout_type (record);
5209 /* The correct type is an array type of one element. */
5210 return build_array_type (record, build_index_type (size_zero_node));
5213 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
5216 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
5225 int regparm = ix86_regparm;
5227 if((cum ? cum->call_abi : ix86_cfun_abi ()) != DEFAULT_ABI)
5228 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
5230 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
5233 /* Indicate to allocate space on the stack for varargs save area. */
5234 ix86_save_varrargs_registers = 1;
5235 /* We need 16-byte stack alignment to save SSE registers. If user
5236 asked for lower preferred_stack_boundary, lets just hope that he knows
5237 what he is doing and won't varargs SSE values.
5239 We also may end up assuming that only 64bit values are stored in SSE
5240 register let some floating point program work. */
5241 if (ix86_preferred_stack_boundary >= BIGGEST_ALIGNMENT)
5242 crtl->stack_alignment_needed = BIGGEST_ALIGNMENT;
5244 save_area = frame_pointer_rtx;
5245 set = get_varargs_alias_set ();
5247 for (i = cum->regno;
5249 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5252 mem = gen_rtx_MEM (Pmode,
5253 plus_constant (save_area, i * UNITS_PER_WORD));
5254 MEM_NOTRAP_P (mem) = 1;
5255 set_mem_alias_set (mem, set);
5256 emit_move_insn (mem, gen_rtx_REG (Pmode,
5257 x86_64_int_parameter_registers[i]));
5260 if (cum->sse_nregs && cfun->va_list_fpr_size)
5262 /* Now emit code to save SSE registers. The AX parameter contains number
5263 of SSE parameter registers used to call this function. We use
5264 sse_prologue_save insn template that produces computed jump across
5265 SSE saves. We need some preparation work to get this working. */
5267 label = gen_label_rtx ();
5268 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5270 /* Compute address to jump to :
5271 label - eax*4 + nnamed_sse_arguments*4 */
5272 tmp_reg = gen_reg_rtx (Pmode);
5273 nsse_reg = gen_reg_rtx (Pmode);
5274 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5275 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5276 gen_rtx_MULT (Pmode, nsse_reg,
5281 gen_rtx_CONST (DImode,
5282 gen_rtx_PLUS (DImode,
5284 GEN_INT (cum->sse_regno * 4))));
5286 emit_move_insn (nsse_reg, label_ref);
5287 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5289 /* Compute address of memory block we save into. We always use pointer
5290 pointing 127 bytes after first byte to store - this is needed to keep
5291 instruction size limited by 4 bytes. */
5292 tmp_reg = gen_reg_rtx (Pmode);
5293 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5294 plus_constant (save_area,
5295 8 * X86_64_REGPARM_MAX + 127)));
5296 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5297 MEM_NOTRAP_P (mem) = 1;
5298 set_mem_alias_set (mem, set);
5299 set_mem_align (mem, BITS_PER_WORD);
5301 /* And finally do the dirty job! */
5302 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5303 GEN_INT (cum->sse_regno), label));
5308 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5310 alias_set_type set = get_varargs_alias_set ();
5313 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
5317 mem = gen_rtx_MEM (Pmode,
5318 plus_constant (virtual_incoming_args_rtx,
5319 i * UNITS_PER_WORD));
5320 MEM_NOTRAP_P (mem) = 1;
5321 set_mem_alias_set (mem, set);
5323 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5324 emit_move_insn (mem, reg);
5329 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5330 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5333 CUMULATIVE_ARGS next_cum;
5336 /* This argument doesn't appear to be used anymore. Which is good,
5337 because the old code here didn't suppress rtl generation. */
5338 gcc_assert (!no_rtl);
5343 fntype = TREE_TYPE (current_function_decl);
5345 /* For varargs, we do not want to skip the dummy va_dcl argument.
5346 For stdargs, we do want to skip the last named argument. */
5348 if (stdarg_p (fntype))
5349 function_arg_advance (&next_cum, mode, type, 1);
5351 if ((cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5352 setup_incoming_varargs_ms_64 (&next_cum);
5354 setup_incoming_varargs_64 (&next_cum);
5357 /* Implement va_start. */
5360 ix86_va_start (tree valist, rtx nextarg)
5362 HOST_WIDE_INT words, n_gpr, n_fpr;
5363 tree f_gpr, f_fpr, f_ovf, f_sav;
5364 tree gpr, fpr, ovf, sav, t;
5367 /* Only 64bit target needs something special. */
5368 if (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI)
5370 std_expand_builtin_va_start (valist, nextarg);
5374 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5375 f_fpr = TREE_CHAIN (f_gpr);
5376 f_ovf = TREE_CHAIN (f_fpr);
5377 f_sav = TREE_CHAIN (f_ovf);
5379 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5380 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5381 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5382 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5383 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5385 /* Count number of gp and fp argument registers used. */
5386 words = crtl->args.info.words;
5387 n_gpr = crtl->args.info.regno;
5388 n_fpr = crtl->args.info.sse_regno;
5390 if (cfun->va_list_gpr_size)
5392 type = TREE_TYPE (gpr);
5393 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5394 build_int_cst (type, n_gpr * 8));
5395 TREE_SIDE_EFFECTS (t) = 1;
5396 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5399 if (cfun->va_list_fpr_size)
5401 type = TREE_TYPE (fpr);
5402 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5403 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
5404 TREE_SIDE_EFFECTS (t) = 1;
5405 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5408 /* Find the overflow area. */
5409 type = TREE_TYPE (ovf);
5410 t = make_tree (type, virtual_incoming_args_rtx);
5412 t = build2 (POINTER_PLUS_EXPR, type, t,
5413 size_int (words * UNITS_PER_WORD));
5414 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5415 TREE_SIDE_EFFECTS (t) = 1;
5416 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5418 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5420 /* Find the register save area.
5421 Prologue of the function save it right above stack frame. */
5422 type = TREE_TYPE (sav);
5423 t = make_tree (type, frame_pointer_rtx);
5424 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5425 TREE_SIDE_EFFECTS (t) = 1;
5426 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5430 /* Implement va_arg. */
5433 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5435 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5436 tree f_gpr, f_fpr, f_ovf, f_sav;
5437 tree gpr, fpr, ovf, sav, t;
5439 tree lab_false, lab_over = NULL_TREE;
5444 enum machine_mode nat_mode;
5446 /* Only 64bit target needs something special. */
5447 if (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI)
5448 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5450 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5451 f_fpr = TREE_CHAIN (f_gpr);
5452 f_ovf = TREE_CHAIN (f_fpr);
5453 f_sav = TREE_CHAIN (f_ovf);
5455 valist = build_va_arg_indirect_ref (valist);
5456 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5457 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5458 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5459 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5461 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5463 type = build_pointer_type (type);
5464 size = int_size_in_bytes (type);
5465 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5467 nat_mode = type_natural_mode (type);
5468 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5469 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
5472 /* Pull the value out of the saved registers. */
5474 addr = create_tmp_var (ptr_type_node, "addr");
5475 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5479 int needed_intregs, needed_sseregs;
5481 tree int_addr, sse_addr;
5483 lab_false = create_artificial_label ();
5484 lab_over = create_artificial_label ();
5486 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5488 need_temp = (!REG_P (container)
5489 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5490 || TYPE_ALIGN (type) > 128));
5492 /* In case we are passing structure, verify that it is consecutive block
5493 on the register save area. If not we need to do moves. */
5494 if (!need_temp && !REG_P (container))
5496 /* Verify that all registers are strictly consecutive */
5497 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5501 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5503 rtx slot = XVECEXP (container, 0, i);
5504 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5505 || INTVAL (XEXP (slot, 1)) != i * 16)
5513 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5515 rtx slot = XVECEXP (container, 0, i);
5516 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5517 || INTVAL (XEXP (slot, 1)) != i * 8)
5529 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5530 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5531 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5532 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5535 /* First ensure that we fit completely in registers. */
5538 t = build_int_cst (TREE_TYPE (gpr),
5539 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
5540 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5541 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5542 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5543 gimplify_and_add (t, pre_p);
5547 t = build_int_cst (TREE_TYPE (fpr),
5548 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5549 + X86_64_REGPARM_MAX * 8);
5550 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5551 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5552 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5553 gimplify_and_add (t, pre_p);
5556 /* Compute index to start of area used for integer regs. */
5559 /* int_addr = gpr + sav; */
5560 t = fold_convert (sizetype, gpr);
5561 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5562 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5563 gimplify_and_add (t, pre_p);
5567 /* sse_addr = fpr + sav; */
5568 t = fold_convert (sizetype, fpr);
5569 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5570 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5571 gimplify_and_add (t, pre_p);
5576 tree temp = create_tmp_var (type, "va_arg_tmp");
5579 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5580 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5581 gimplify_and_add (t, pre_p);
5583 for (i = 0; i < XVECLEN (container, 0); i++)
5585 rtx slot = XVECEXP (container, 0, i);
5586 rtx reg = XEXP (slot, 0);
5587 enum machine_mode mode = GET_MODE (reg);
5588 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5589 tree addr_type = build_pointer_type (piece_type);
5592 tree dest_addr, dest;
5594 if (SSE_REGNO_P (REGNO (reg)))
5596 src_addr = sse_addr;
5597 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5601 src_addr = int_addr;
5602 src_offset = REGNO (reg) * 8;
5604 src_addr = fold_convert (addr_type, src_addr);
5605 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5606 size_int (src_offset));
5607 src = build_va_arg_indirect_ref (src_addr);
5609 dest_addr = fold_convert (addr_type, addr);
5610 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5611 size_int (INTVAL (XEXP (slot, 1))));
5612 dest = build_va_arg_indirect_ref (dest_addr);
5614 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5615 gimplify_and_add (t, pre_p);
5621 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5622 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5623 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5624 gimplify_and_add (t, pre_p);
5628 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5629 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5630 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5631 gimplify_and_add (t, pre_p);
5634 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5635 gimplify_and_add (t, pre_p);
5637 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5638 append_to_statement_list (t, pre_p);
5641 /* ... otherwise out of the overflow area. */
5643 /* Care for on-stack alignment if needed. */
5644 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5645 || integer_zerop (TYPE_SIZE (type)))
5649 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5650 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5651 size_int (align - 1));
5652 t = fold_convert (sizetype, t);
5653 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5655 t = fold_convert (TREE_TYPE (ovf), t);
5657 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5659 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5660 gimplify_and_add (t2, pre_p);
5662 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5663 size_int (rsize * UNITS_PER_WORD));
5664 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5665 gimplify_and_add (t, pre_p);
5669 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5670 append_to_statement_list (t, pre_p);
5673 ptrtype = build_pointer_type (type);
5674 addr = fold_convert (ptrtype, addr);
5677 addr = build_va_arg_indirect_ref (addr);
5678 return build_va_arg_indirect_ref (addr);
5681 /* Return nonzero if OPNUM's MEM should be matched
5682 in movabs* patterns. */
5685 ix86_check_movabs (rtx insn, int opnum)
5689 set = PATTERN (insn);
5690 if (GET_CODE (set) == PARALLEL)
5691 set = XVECEXP (set, 0, 0);
5692 gcc_assert (GET_CODE (set) == SET);
5693 mem = XEXP (set, opnum);
5694 while (GET_CODE (mem) == SUBREG)
5695 mem = SUBREG_REG (mem);
5696 gcc_assert (MEM_P (mem));
5697 return (volatile_ok || !MEM_VOLATILE_P (mem));
5700 /* Initialize the table of extra 80387 mathematical constants. */
5703 init_ext_80387_constants (void)
5705 static const char * cst[5] =
5707 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5708 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5709 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5710 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5711 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5715 for (i = 0; i < 5; i++)
5717 real_from_string (&ext_80387_constants_table[i], cst[i]);
5718 /* Ensure each constant is rounded to XFmode precision. */
5719 real_convert (&ext_80387_constants_table[i],
5720 XFmode, &ext_80387_constants_table[i]);
5723 ext_80387_constants_init = 1;
5726 /* Return true if the constant is something that can be loaded with
5727 a special instruction. */
5730 standard_80387_constant_p (rtx x)
5732 enum machine_mode mode = GET_MODE (x);
5736 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5739 if (x == CONST0_RTX (mode))
5741 if (x == CONST1_RTX (mode))
5744 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5746 /* For XFmode constants, try to find a special 80387 instruction when
5747 optimizing for size or on those CPUs that benefit from them. */
5749 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5753 if (! ext_80387_constants_init)
5754 init_ext_80387_constants ();
5756 for (i = 0; i < 5; i++)
5757 if (real_identical (&r, &ext_80387_constants_table[i]))
5761 /* Load of the constant -0.0 or -1.0 will be split as
5762 fldz;fchs or fld1;fchs sequence. */
5763 if (real_isnegzero (&r))
5765 if (real_identical (&r, &dconstm1))
5771 /* Return the opcode of the special instruction to be used to load
5775 standard_80387_constant_opcode (rtx x)
5777 switch (standard_80387_constant_p (x))
5801 /* Return the CONST_DOUBLE representing the 80387 constant that is
5802 loaded by the specified special instruction. The argument IDX
5803 matches the return value from standard_80387_constant_p. */
5806 standard_80387_constant_rtx (int idx)
5810 if (! ext_80387_constants_init)
5811 init_ext_80387_constants ();
5827 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5831 /* Return 1 if mode is a valid mode for sse. */
5833 standard_sse_mode_p (enum machine_mode mode)
5850 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5853 standard_sse_constant_p (rtx x)
5855 enum machine_mode mode = GET_MODE (x);
5857 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5859 if (vector_all_ones_operand (x, mode)
5860 && standard_sse_mode_p (mode))
5861 return TARGET_SSE2 ? 2 : -1;
5866 /* Return the opcode of the special instruction to be used to load
5870 standard_sse_constant_opcode (rtx insn, rtx x)
5872 switch (standard_sse_constant_p (x))
5875 if (get_attr_mode (insn) == MODE_V4SF)
5876 return "xorps\t%0, %0";
5877 else if (get_attr_mode (insn) == MODE_V2DF)
5878 return "xorpd\t%0, %0";
5880 return "pxor\t%0, %0";
5882 return "pcmpeqd\t%0, %0";
5887 /* Returns 1 if OP contains a symbol reference */
5890 symbolic_reference_mentioned_p (rtx op)
5895 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5898 fmt = GET_RTX_FORMAT (GET_CODE (op));
5899 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5905 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5906 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5910 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5917 /* Return 1 if it is appropriate to emit `ret' instructions in the
5918 body of a function. Do this only if the epilogue is simple, needing a
5919 couple of insns. Prior to reloading, we can't tell how many registers
5920 must be saved, so return 0 then. Return 0 if there is no frame
5921 marker to de-allocate. */
5924 ix86_can_use_return_insn_p (void)
5926 struct ix86_frame frame;
5928 if (! reload_completed || frame_pointer_needed)
5931 /* Don't allow more than 32 pop, since that's all we can do
5932 with one instruction. */
5933 if (crtl->args.pops_args
5934 && crtl->args.size >= 32768)
5937 ix86_compute_frame_layout (&frame);
5938 return frame.to_allocate == 0 && frame.nregs == 0;
5941 /* Value should be nonzero if functions must have frame pointers.
5942 Zero means the frame pointer need not be set up (and parms may
5943 be accessed via the stack pointer) in functions that seem suitable. */
5946 ix86_frame_pointer_required (void)
5948 /* If we accessed previous frames, then the generated code expects
5949 to be able to access the saved ebp value in our frame. */
5950 if (cfun->machine->accesses_prev_frame)
5953 /* Several x86 os'es need a frame pointer for other reasons,
5954 usually pertaining to setjmp. */
5955 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5958 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5959 the frame pointer by default. Turn it back on now if we've not
5960 got a leaf function. */
5961 if (TARGET_OMIT_LEAF_FRAME_POINTER
5962 && (!current_function_is_leaf
5963 || ix86_current_function_calls_tls_descriptor))
5972 /* Record that the current function accesses previous call frames. */
5975 ix86_setup_frame_addresses (void)
5977 cfun->machine->accesses_prev_frame = 1;
5980 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5981 # define USE_HIDDEN_LINKONCE 1
5983 # define USE_HIDDEN_LINKONCE 0
5986 static int pic_labels_used;
5988 /* Fills in the label name that should be used for a pc thunk for
5989 the given register. */
5992 get_pc_thunk_name (char name[32], unsigned int regno)
5994 gcc_assert (!TARGET_64BIT);
5996 if (USE_HIDDEN_LINKONCE)
5997 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5999 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
6003 /* This function generates code for -fpic that loads %ebx with
6004 the return address of the caller and then returns. */
6007 ix86_file_end (void)
6012 for (regno = 0; regno < 8; ++regno)
6016 if (! ((pic_labels_used >> regno) & 1))
6019 get_pc_thunk_name (name, regno);
6024 switch_to_section (darwin_sections[text_coal_section]);
6025 fputs ("\t.weak_definition\t", asm_out_file);
6026 assemble_name (asm_out_file, name);
6027 fputs ("\n\t.private_extern\t", asm_out_file);
6028 assemble_name (asm_out_file, name);
6029 fputs ("\n", asm_out_file);
6030 ASM_OUTPUT_LABEL (asm_out_file, name);
6034 if (USE_HIDDEN_LINKONCE)
6038 decl = build_decl (FUNCTION_DECL, get_identifier (name),
6040 TREE_PUBLIC (decl) = 1;
6041 TREE_STATIC (decl) = 1;
6042 DECL_ONE_ONLY (decl) = 1;
6044 (*targetm.asm_out.unique_section) (decl, 0);
6045 switch_to_section (get_named_section (decl, NULL, 0));
6047 (*targetm.asm_out.globalize_label) (asm_out_file, name);
6048 fputs ("\t.hidden\t", asm_out_file);
6049 assemble_name (asm_out_file, name);
6050 fputc ('\n', asm_out_file);
6051 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
6055 switch_to_section (text_section);
6056 ASM_OUTPUT_LABEL (asm_out_file, name);
6059 xops[0] = gen_rtx_REG (Pmode, regno);
6060 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
6061 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
6062 output_asm_insn ("ret", xops);
6065 if (NEED_INDICATE_EXEC_STACK)
6066 file_end_indicate_exec_stack ();
6069 /* Emit code for the SET_GOT patterns. */
6072 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
6078 if (TARGET_VXWORKS_RTP && flag_pic)
6080 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
6081 xops[2] = gen_rtx_MEM (Pmode,
6082 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
6083 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
6085 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
6086 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
6087 an unadorned address. */
6088 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
6089 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
6090 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
6094 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
6096 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
6098 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
6101 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
6103 output_asm_insn ("call\t%a2", xops);
6106 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
6107 is what will be referenced by the Mach-O PIC subsystem. */
6109 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
6112 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6113 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
6116 output_asm_insn ("pop%z0\t%0", xops);
6121 get_pc_thunk_name (name, REGNO (dest));
6122 pic_labels_used |= 1 << REGNO (dest);
6124 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
6125 xops[2] = gen_rtx_MEM (QImode, xops[2]);
6126 output_asm_insn ("call\t%X2", xops);
6127 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
6128 is what will be referenced by the Mach-O PIC subsystem. */
6131 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
6133 targetm.asm_out.internal_label (asm_out_file, "L",
6134 CODE_LABEL_NUMBER (label));
6141 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
6142 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
6144 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
6149 /* Generate an "push" pattern for input ARG. */
6154 return gen_rtx_SET (VOIDmode,
6156 gen_rtx_PRE_DEC (Pmode,
6157 stack_pointer_rtx)),
6161 /* Return >= 0 if there is an unused call-clobbered register available
6162 for the entire function. */
6165 ix86_select_alt_pic_regnum (void)
6167 if (current_function_is_leaf && !crtl->profile
6168 && !ix86_current_function_calls_tls_descriptor)
6171 for (i = 2; i >= 0; --i)
6172 if (!df_regs_ever_live_p (i))
6176 return INVALID_REGNUM;
6179 /* Return 1 if we need to save REGNO. */
6181 ix86_save_reg (unsigned int regno, int maybe_eh_return)
6183 if (pic_offset_table_rtx
6184 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
6185 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6187 || crtl->calls_eh_return
6188 || crtl->uses_const_pool))
6190 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
6195 if (crtl->calls_eh_return && maybe_eh_return)
6200 unsigned test = EH_RETURN_DATA_REGNO (i);
6201 if (test == INVALID_REGNUM)
6208 if (cfun->machine->force_align_arg_pointer
6209 && regno == REGNO (cfun->machine->force_align_arg_pointer))
6212 return (df_regs_ever_live_p (regno)
6213 && !call_used_regs[regno]
6214 && !fixed_regs[regno]
6215 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
6218 /* Return number of registers to be saved on the stack. */
6221 ix86_nsaved_regs (void)
6226 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
6227 if (ix86_save_reg (regno, true))
6232 /* Return the offset between two registers, one to be eliminated, and the other
6233 its replacement, at the start of a routine. */
6236 ix86_initial_elimination_offset (int from, int to)
6238 struct ix86_frame frame;
6239 ix86_compute_frame_layout (&frame);
6241 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6242 return frame.hard_frame_pointer_offset;
6243 else if (from == FRAME_POINTER_REGNUM
6244 && to == HARD_FRAME_POINTER_REGNUM)
6245 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6248 gcc_assert (to == STACK_POINTER_REGNUM);
6250 if (from == ARG_POINTER_REGNUM)
6251 return frame.stack_pointer_offset;
6253 gcc_assert (from == FRAME_POINTER_REGNUM);
6254 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6258 /* Fill structure ix86_frame about frame of currently computed function. */
6261 ix86_compute_frame_layout (struct ix86_frame *frame)
6263 HOST_WIDE_INT total_size;
6264 unsigned int stack_alignment_needed;
6265 HOST_WIDE_INT offset;
6266 unsigned int preferred_alignment;
6267 HOST_WIDE_INT size = get_frame_size ();
6269 frame->nregs = ix86_nsaved_regs ();
6272 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
6273 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
6275 /* During reload iteration the amount of registers saved can change.
6276 Recompute the value as needed. Do not recompute when amount of registers
6277 didn't change as reload does multiple calls to the function and does not
6278 expect the decision to change within single iteration. */
6280 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6282 int count = frame->nregs;
6284 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6285 /* The fast prologue uses move instead of push to save registers. This
6286 is significantly longer, but also executes faster as modern hardware
6287 can execute the moves in parallel, but can't do that for push/pop.
6289 Be careful about choosing what prologue to emit: When function takes
6290 many instructions to execute we may use slow version as well as in
6291 case function is known to be outside hot spot (this is known with
6292 feedback only). Weight the size of function by number of registers
6293 to save as it is cheap to use one or two push instructions but very
6294 slow to use many of them. */
6296 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6297 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6298 || (flag_branch_probabilities
6299 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6300 cfun->machine->use_fast_prologue_epilogue = false;
6302 cfun->machine->use_fast_prologue_epilogue
6303 = !expensive_function_p (count);
6305 if (TARGET_PROLOGUE_USING_MOVE
6306 && cfun->machine->use_fast_prologue_epilogue)
6307 frame->save_regs_using_mov = true;
6309 frame->save_regs_using_mov = false;
6312 /* Skip return address and saved base pointer. */
6313 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6315 frame->hard_frame_pointer_offset = offset;
6317 /* Do some sanity checking of stack_alignment_needed and
6318 preferred_alignment, since i386 port is the only using those features
6319 that may break easily. */
6321 gcc_assert (!size || stack_alignment_needed);
6322 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6323 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6324 gcc_assert (stack_alignment_needed
6325 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6327 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6328 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6330 /* Register save area */
6331 offset += frame->nregs * UNITS_PER_WORD;
6334 if (ix86_save_varrargs_registers)
6336 offset += X86_64_VARARGS_SIZE;
6337 frame->va_arg_size = X86_64_VARARGS_SIZE;
6340 frame->va_arg_size = 0;
6342 /* Align start of frame for local function. */
6343 frame->padding1 = ((offset + stack_alignment_needed - 1)
6344 & -stack_alignment_needed) - offset;
6346 offset += frame->padding1;
6348 /* Frame pointer points here. */
6349 frame->frame_pointer_offset = offset;
6353 /* Add outgoing arguments area. Can be skipped if we eliminated
6354 all the function calls as dead code.
6355 Skipping is however impossible when function calls alloca. Alloca
6356 expander assumes that last crtl->outgoing_args_size
6357 of stack frame are unused. */
6358 if (ACCUMULATE_OUTGOING_ARGS
6359 && (!current_function_is_leaf || cfun->calls_alloca
6360 || ix86_current_function_calls_tls_descriptor))
6362 offset += crtl->outgoing_args_size;
6363 frame->outgoing_arguments_size = crtl->outgoing_args_size;
6366 frame->outgoing_arguments_size = 0;
6368 /* Align stack boundary. Only needed if we're calling another function
6370 if (!current_function_is_leaf || cfun->calls_alloca
6371 || ix86_current_function_calls_tls_descriptor)
6372 frame->padding2 = ((offset + preferred_alignment - 1)
6373 & -preferred_alignment) - offset;
6375 frame->padding2 = 0;
6377 offset += frame->padding2;
6379 /* We've reached end of stack frame. */
6380 frame->stack_pointer_offset = offset;
6382 /* Size prologue needs to allocate. */
6383 frame->to_allocate =
6384 (size + frame->padding1 + frame->padding2
6385 + frame->outgoing_arguments_size + frame->va_arg_size);
6387 if ((!frame->to_allocate && frame->nregs <= 1)
6388 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6389 frame->save_regs_using_mov = false;
6391 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
6392 && current_function_is_leaf
6393 && !ix86_current_function_calls_tls_descriptor)
6395 frame->red_zone_size = frame->to_allocate;
6396 if (frame->save_regs_using_mov)
6397 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6398 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6399 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6402 frame->red_zone_size = 0;
6403 frame->to_allocate -= frame->red_zone_size;
6404 frame->stack_pointer_offset -= frame->red_zone_size;
6406 fprintf (stderr, "\n");
6407 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6408 fprintf (stderr, "size: %ld\n", (long)size);
6409 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6410 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6411 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6412 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6413 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6414 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6415 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6416 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6417 (long)frame->hard_frame_pointer_offset);
6418 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6419 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6420 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
6421 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6425 /* Emit code to save registers in the prologue. */
6428 ix86_emit_save_regs (void)
6433 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6434 if (ix86_save_reg (regno, true))
6436 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6437 RTX_FRAME_RELATED_P (insn) = 1;
6441 /* Emit code to save registers using MOV insns. First register
6442 is restored from POINTER + OFFSET. */
6444 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6449 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6450 if (ix86_save_reg (regno, true))
6452 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6454 gen_rtx_REG (Pmode, regno));
6455 RTX_FRAME_RELATED_P (insn) = 1;
6456 offset += UNITS_PER_WORD;
6460 /* Expand prologue or epilogue stack adjustment.
6461 The pattern exist to put a dependency on all ebp-based memory accesses.
6462 STYLE should be negative if instructions should be marked as frame related,
6463 zero if %r11 register is live and cannot be freely used and positive
6467 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6472 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6473 else if (x86_64_immediate_operand (offset, DImode))
6474 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6478 /* r11 is used by indirect sibcall return as well, set before the
6479 epilogue and used after the epilogue. ATM indirect sibcall
6480 shouldn't be used together with huge frame sizes in one
6481 function because of the frame_size check in sibcall.c. */
6483 r11 = gen_rtx_REG (DImode, R11_REG);
6484 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6486 RTX_FRAME_RELATED_P (insn) = 1;
6487 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6491 RTX_FRAME_RELATED_P (insn) = 1;
6494 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6497 ix86_internal_arg_pointer (void)
6499 bool has_force_align_arg_pointer =
6500 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6501 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6502 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6503 && DECL_NAME (current_function_decl)
6504 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6505 && DECL_FILE_SCOPE_P (current_function_decl))
6506 || ix86_force_align_arg_pointer
6507 || has_force_align_arg_pointer)
6509 /* Nested functions can't realign the stack due to a register
6511 if (DECL_CONTEXT (current_function_decl)
6512 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6514 if (ix86_force_align_arg_pointer)
6515 warning (0, "-mstackrealign ignored for nested functions");
6516 if (has_force_align_arg_pointer)
6517 error ("%s not supported for nested functions",
6518 ix86_force_align_arg_pointer_string);
6519 return virtual_incoming_args_rtx;
6521 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6522 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6525 return virtual_incoming_args_rtx;
6528 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6529 This is called from dwarf2out.c to emit call frame instructions
6530 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6532 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6534 rtx unspec = SET_SRC (pattern);
6535 gcc_assert (GET_CODE (unspec) == UNSPEC);
6539 case UNSPEC_REG_SAVE:
6540 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6541 SET_DEST (pattern));
6543 case UNSPEC_DEF_CFA:
6544 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6545 INTVAL (XVECEXP (unspec, 0, 0)));
6552 /* Expand the prologue into a bunch of separate insns. */
6555 ix86_expand_prologue (void)
6559 struct ix86_frame frame;
6560 HOST_WIDE_INT allocate;
6562 ix86_compute_frame_layout (&frame);
6564 if (cfun->machine->force_align_arg_pointer)
6568 /* Grab the argument pointer. */
6569 x = plus_constant (stack_pointer_rtx, 4);
6570 y = cfun->machine->force_align_arg_pointer;
6571 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6572 RTX_FRAME_RELATED_P (insn) = 1;
6574 /* The unwind info consists of two parts: install the fafp as the cfa,
6575 and record the fafp as the "save register" of the stack pointer.
6576 The later is there in order that the unwinder can see where it
6577 should restore the stack pointer across the and insn. */
6578 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6579 x = gen_rtx_SET (VOIDmode, y, x);
6580 RTX_FRAME_RELATED_P (x) = 1;
6581 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6583 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6584 RTX_FRAME_RELATED_P (y) = 1;
6585 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6586 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6587 REG_NOTES (insn) = x;
6589 /* Align the stack. */
6590 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6593 /* And here we cheat like madmen with the unwind info. We force the
6594 cfa register back to sp+4, which is exactly what it was at the
6595 start of the function. Re-pushing the return address results in
6596 the return at the same spot relative to the cfa, and thus is
6597 correct wrt the unwind info. */
6598 x = cfun->machine->force_align_arg_pointer;
6599 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6600 insn = emit_insn (gen_push (x));
6601 RTX_FRAME_RELATED_P (insn) = 1;
6604 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6605 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6606 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6607 REG_NOTES (insn) = x;
6610 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6611 slower on all targets. Also sdb doesn't like it. */
6613 if (frame_pointer_needed)
6615 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6616 RTX_FRAME_RELATED_P (insn) = 1;
6618 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6619 RTX_FRAME_RELATED_P (insn) = 1;
6622 allocate = frame.to_allocate;
6624 if (!frame.save_regs_using_mov)
6625 ix86_emit_save_regs ();
6627 allocate += frame.nregs * UNITS_PER_WORD;
6629 /* When using red zone we may start register saving before allocating
6630 the stack frame saving one cycle of the prologue. However I will
6631 avoid doing this if I am going to have to probe the stack since
6632 at least on x86_64 the stack probe can turn into a call that clobbers
6633 a red zone location */
6634 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
6635 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6636 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6637 : stack_pointer_rtx,
6638 -frame.nregs * UNITS_PER_WORD);
6642 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6643 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6644 GEN_INT (-allocate), -1);
6647 /* Only valid for Win32. */
6648 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6652 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
6654 if (cfun->machine->call_abi == MS_ABI)
6657 eax_live = ix86_eax_live_at_start_p ();
6661 emit_insn (gen_push (eax));
6662 allocate -= UNITS_PER_WORD;
6665 emit_move_insn (eax, GEN_INT (allocate));
6668 insn = gen_allocate_stack_worker_64 (eax);
6670 insn = gen_allocate_stack_worker_32 (eax);
6671 insn = emit_insn (insn);
6672 RTX_FRAME_RELATED_P (insn) = 1;
6673 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6674 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6675 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6676 t, REG_NOTES (insn));
6680 if (frame_pointer_needed)
6681 t = plus_constant (hard_frame_pointer_rtx,
6684 - frame.nregs * UNITS_PER_WORD);
6686 t = plus_constant (stack_pointer_rtx, allocate);
6687 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6691 if (frame.save_regs_using_mov
6692 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
6693 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6695 if (!frame_pointer_needed || !frame.to_allocate)
6696 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6698 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6699 -frame.nregs * UNITS_PER_WORD);
6702 pic_reg_used = false;
6703 if (pic_offset_table_rtx
6704 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6707 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6709 if (alt_pic_reg_used != INVALID_REGNUM)
6710 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6712 pic_reg_used = true;
6719 if (ix86_cmodel == CM_LARGE_PIC)
6721 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6722 rtx label = gen_label_rtx ();
6724 LABEL_PRESERVE_P (label) = 1;
6725 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6726 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6727 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6728 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6729 pic_offset_table_rtx, tmp_reg));
6732 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6735 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6738 /* Prevent function calls from being scheduled before the call to mcount.
6739 In the pic_reg_used case, make sure that the got load isn't deleted. */
6743 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6744 emit_insn (gen_blockage ());
6747 /* Emit cld instruction if stringops are used in the function. */
6748 if (TARGET_CLD && ix86_current_function_needs_cld)
6749 emit_insn (gen_cld ());
6752 /* Emit code to restore saved registers using MOV insns. First register
6753 is restored from POINTER + OFFSET. */
6755 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6756 int maybe_eh_return)
6759 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6761 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6762 if (ix86_save_reg (regno, maybe_eh_return))
6764 /* Ensure that adjust_address won't be forced to produce pointer
6765 out of range allowed by x86-64 instruction set. */
6766 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6770 r11 = gen_rtx_REG (DImode, R11_REG);
6771 emit_move_insn (r11, GEN_INT (offset));
6772 emit_insn (gen_adddi3 (r11, r11, pointer));
6773 base_address = gen_rtx_MEM (Pmode, r11);
6776 emit_move_insn (gen_rtx_REG (Pmode, regno),
6777 adjust_address (base_address, Pmode, offset));
6778 offset += UNITS_PER_WORD;
6782 /* Restore function stack, frame, and registers. */
6785 ix86_expand_epilogue (int style)
6788 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6789 struct ix86_frame frame;
6790 HOST_WIDE_INT offset;
6792 ix86_compute_frame_layout (&frame);
6794 /* Calculate start of saved registers relative to ebp. Special care
6795 must be taken for the normal return case of a function using
6796 eh_return: the eax and edx registers are marked as saved, but not
6797 restored along this path. */
6798 offset = frame.nregs;
6799 if (crtl->calls_eh_return && style != 2)
6801 offset *= -UNITS_PER_WORD;
6803 /* If we're only restoring one register and sp is not valid then
6804 using a move instruction to restore the register since it's
6805 less work than reloading sp and popping the register.
6807 The default code result in stack adjustment using add/lea instruction,
6808 while this code results in LEAVE instruction (or discrete equivalent),
6809 so it is profitable in some other cases as well. Especially when there
6810 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6811 and there is exactly one register to pop. This heuristic may need some
6812 tuning in future. */
6813 if ((!sp_valid && frame.nregs <= 1)
6814 || (TARGET_EPILOGUE_USING_MOVE
6815 && cfun->machine->use_fast_prologue_epilogue
6816 && (frame.nregs > 1 || frame.to_allocate))
6817 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6818 || (frame_pointer_needed && TARGET_USE_LEAVE
6819 && cfun->machine->use_fast_prologue_epilogue
6820 && frame.nregs == 1)
6821 || crtl->calls_eh_return)
6823 /* Restore registers. We can use ebp or esp to address the memory
6824 locations. If both are available, default to ebp, since offsets
6825 are known to be small. Only exception is esp pointing directly to the
6826 end of block of saved registers, where we may simplify addressing
6829 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6830 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6831 frame.to_allocate, style == 2);
6833 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6834 offset, style == 2);
6836 /* eh_return epilogues need %ecx added to the stack pointer. */
6839 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6841 if (frame_pointer_needed)
6843 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6844 tmp = plus_constant (tmp, UNITS_PER_WORD);
6845 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6847 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6848 emit_move_insn (hard_frame_pointer_rtx, tmp);
6850 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6855 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6856 tmp = plus_constant (tmp, (frame.to_allocate
6857 + frame.nregs * UNITS_PER_WORD));
6858 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6861 else if (!frame_pointer_needed)
6862 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6863 GEN_INT (frame.to_allocate
6864 + frame.nregs * UNITS_PER_WORD),
6866 /* If not an i386, mov & pop is faster than "leave". */
6867 else if (TARGET_USE_LEAVE || optimize_size
6868 || !cfun->machine->use_fast_prologue_epilogue)
6869 emit_insn ((*ix86_gen_leave) ());
6872 pro_epilogue_adjust_stack (stack_pointer_rtx,
6873 hard_frame_pointer_rtx,
6876 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
6881 /* First step is to deallocate the stack frame so that we can
6882 pop the registers. */
6885 gcc_assert (frame_pointer_needed);
6886 pro_epilogue_adjust_stack (stack_pointer_rtx,
6887 hard_frame_pointer_rtx,
6888 GEN_INT (offset), style);
6890 else if (frame.to_allocate)
6891 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6892 GEN_INT (frame.to_allocate), style);
6894 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6895 if (ix86_save_reg (regno, false))
6896 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
6897 if (frame_pointer_needed)
6899 /* Leave results in shorter dependency chains on CPUs that are
6900 able to grok it fast. */
6901 if (TARGET_USE_LEAVE)
6902 emit_insn ((*ix86_gen_leave) ());
6904 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
6908 if (cfun->machine->force_align_arg_pointer)
6910 emit_insn (gen_addsi3 (stack_pointer_rtx,
6911 cfun->machine->force_align_arg_pointer,
6915 /* Sibcall epilogues don't want a return instruction. */
6919 if (crtl->args.pops_args && crtl->args.size)
6921 rtx popc = GEN_INT (crtl->args.pops_args);
6923 /* i386 can only pop 64K bytes. If asked to pop more, pop
6924 return address, do explicit add, and jump indirectly to the
6927 if (crtl->args.pops_args >= 65536)
6929 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6931 /* There is no "pascal" calling convention in any 64bit ABI. */
6932 gcc_assert (!TARGET_64BIT);
6934 emit_insn (gen_popsi1 (ecx));
6935 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6936 emit_jump_insn (gen_return_indirect_internal (ecx));
6939 emit_jump_insn (gen_return_pop_internal (popc));
6942 emit_jump_insn (gen_return_internal ());
6945 /* Reset from the function's potential modifications. */
6948 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6949 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6951 if (pic_offset_table_rtx)
6952 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6954 /* Mach-O doesn't support labels at the end of objects, so if
6955 it looks like we might want one, insert a NOP. */
6957 rtx insn = get_last_insn ();
6960 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6961 insn = PREV_INSN (insn);
6965 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6966 fputs ("\tnop\n", file);
6972 /* Extract the parts of an RTL expression that is a valid memory address
6973 for an instruction. Return 0 if the structure of the address is
6974 grossly off. Return -1 if the address contains ASHIFT, so it is not
6975 strictly valid, but still used for computing length of lea instruction. */
6978 ix86_decompose_address (rtx addr, struct ix86_address *out)
6980 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6981 rtx base_reg, index_reg;
6982 HOST_WIDE_INT scale = 1;
6983 rtx scale_rtx = NULL_RTX;
6985 enum ix86_address_seg seg = SEG_DEFAULT;
6987 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6989 else if (GET_CODE (addr) == PLUS)
6999 addends[n++] = XEXP (op, 1);
7002 while (GET_CODE (op) == PLUS);
7007 for (i = n; i >= 0; --i)
7010 switch (GET_CODE (op))
7015 index = XEXP (op, 0);
7016 scale_rtx = XEXP (op, 1);
7020 if (XINT (op, 1) == UNSPEC_TP
7021 && TARGET_TLS_DIRECT_SEG_REFS
7022 && seg == SEG_DEFAULT)
7023 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
7052 else if (GET_CODE (addr) == MULT)
7054 index = XEXP (addr, 0); /* index*scale */
7055 scale_rtx = XEXP (addr, 1);
7057 else if (GET_CODE (addr) == ASHIFT)
7061 /* We're called for lea too, which implements ashift on occasion. */
7062 index = XEXP (addr, 0);
7063 tmp = XEXP (addr, 1);
7064 if (!CONST_INT_P (tmp))
7066 scale = INTVAL (tmp);
7067 if ((unsigned HOST_WIDE_INT) scale > 3)
7073 disp = addr; /* displacement */
7075 /* Extract the integral value of scale. */
7078 if (!CONST_INT_P (scale_rtx))
7080 scale = INTVAL (scale_rtx);
7083 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
7084 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
7086 /* Allow arg pointer and stack pointer as index if there is not scaling. */
7087 if (base_reg && index_reg && scale == 1
7088 && (index_reg == arg_pointer_rtx
7089 || index_reg == frame_pointer_rtx
7090 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
7093 tmp = base, base = index, index = tmp;
7094 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
7097 /* Special case: %ebp cannot be encoded as a base without a displacement. */
7098 if ((base_reg == hard_frame_pointer_rtx
7099 || base_reg == frame_pointer_rtx
7100 || base_reg == arg_pointer_rtx) && !disp)
7103 /* Special case: on K6, [%esi] makes the instruction vector decoded.
7104 Avoid this by transforming to [%esi+0]. */
7105 if (TARGET_K6 && !optimize_size
7106 && base_reg && !index_reg && !disp
7108 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
7111 /* Special case: encode reg+reg instead of reg*2. */
7112 if (!base && index && scale && scale == 2)
7113 base = index, base_reg = index_reg, scale = 1;
7115 /* Special case: scaling cannot be encoded without base or displacement. */
7116 if (!base && !disp && index && scale != 1)
7128 /* Return cost of the memory address x.
7129 For i386, it is better to use a complex address than let gcc copy
7130 the address into a reg and make a new pseudo. But not if the address
7131 requires to two regs - that would mean more pseudos with longer
7134 ix86_address_cost (rtx x)
7136 struct ix86_address parts;
7138 int ok = ix86_decompose_address (x, &parts);
7142 if (parts.base && GET_CODE (parts.base) == SUBREG)
7143 parts.base = SUBREG_REG (parts.base);
7144 if (parts.index && GET_CODE (parts.index) == SUBREG)
7145 parts.index = SUBREG_REG (parts.index);
7147 /* Attempt to minimize number of registers in the address. */
7149 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
7151 && (!REG_P (parts.index)
7152 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
7156 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
7158 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
7159 && parts.base != parts.index)
7162 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
7163 since it's predecode logic can't detect the length of instructions
7164 and it degenerates to vector decoded. Increase cost of such
7165 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
7166 to split such addresses or even refuse such addresses at all.
7168 Following addressing modes are affected:
7173 The first and last case may be avoidable by explicitly coding the zero in
7174 memory address, but I don't have AMD-K6 machine handy to check this
7178 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
7179 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
7180 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
7186 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
7187 this is used for to form addresses to local data when -fPIC is in
7191 darwin_local_data_pic (rtx disp)
7193 if (GET_CODE (disp) == MINUS)
7195 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
7196 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
7197 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
7199 const char *sym_name = XSTR (XEXP (disp, 1), 0);
7200 if (! strcmp (sym_name, "<pic base>"))
7208 /* Determine if a given RTX is a valid constant. We already know this
7209 satisfies CONSTANT_P. */
7212 legitimate_constant_p (rtx x)
7214 switch (GET_CODE (x))
7219 if (GET_CODE (x) == PLUS)
7221 if (!CONST_INT_P (XEXP (x, 1)))
7226 if (TARGET_MACHO && darwin_local_data_pic (x))
7229 /* Only some unspecs are valid as "constants". */
7230 if (GET_CODE (x) == UNSPEC)
7231 switch (XINT (x, 1))
7236 return TARGET_64BIT;
7239 x = XVECEXP (x, 0, 0);
7240 return (GET_CODE (x) == SYMBOL_REF
7241 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7243 x = XVECEXP (x, 0, 0);
7244 return (GET_CODE (x) == SYMBOL_REF
7245 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7250 /* We must have drilled down to a symbol. */
7251 if (GET_CODE (x) == LABEL_REF)
7253 if (GET_CODE (x) != SYMBOL_REF)
7258 /* TLS symbols are never valid. */
7259 if (SYMBOL_REF_TLS_MODEL (x))
7262 /* DLLIMPORT symbols are never valid. */
7263 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7264 && SYMBOL_REF_DLLIMPORT_P (x))
7269 if (GET_MODE (x) == TImode
7270 && x != CONST0_RTX (TImode)
7276 if (x == CONST0_RTX (GET_MODE (x)))
7284 /* Otherwise we handle everything else in the move patterns. */
7288 /* Determine if it's legal to put X into the constant pool. This
7289 is not possible for the address of thread-local symbols, which
7290 is checked above. */
7293 ix86_cannot_force_const_mem (rtx x)
7295 /* We can always put integral constants and vectors in memory. */
7296 switch (GET_CODE (x))
7306 return !legitimate_constant_p (x);
7309 /* Determine if a given RTX is a valid constant address. */
7312 constant_address_p (rtx x)
7314 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7317 /* Nonzero if the constant value X is a legitimate general operand
7318 when generating PIC code. It is given that flag_pic is on and
7319 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7322 legitimate_pic_operand_p (rtx x)
7326 switch (GET_CODE (x))
7329 inner = XEXP (x, 0);
7330 if (GET_CODE (inner) == PLUS
7331 && CONST_INT_P (XEXP (inner, 1)))
7332 inner = XEXP (inner, 0);
7334 /* Only some unspecs are valid as "constants". */
7335 if (GET_CODE (inner) == UNSPEC)
7336 switch (XINT (inner, 1))
7341 return TARGET_64BIT;
7343 x = XVECEXP (inner, 0, 0);
7344 return (GET_CODE (x) == SYMBOL_REF
7345 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7353 return legitimate_pic_address_disp_p (x);
7360 /* Determine if a given CONST RTX is a valid memory displacement
7364 legitimate_pic_address_disp_p (rtx disp)
7368 /* In 64bit mode we can allow direct addresses of symbols and labels
7369 when they are not dynamic symbols. */
7372 rtx op0 = disp, op1;
7374 switch (GET_CODE (disp))
7380 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7382 op0 = XEXP (XEXP (disp, 0), 0);
7383 op1 = XEXP (XEXP (disp, 0), 1);
7384 if (!CONST_INT_P (op1)
7385 || INTVAL (op1) >= 16*1024*1024
7386 || INTVAL (op1) < -16*1024*1024)
7388 if (GET_CODE (op0) == LABEL_REF)
7390 if (GET_CODE (op0) != SYMBOL_REF)
7395 /* TLS references should always be enclosed in UNSPEC. */
7396 if (SYMBOL_REF_TLS_MODEL (op0))
7398 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7399 && ix86_cmodel != CM_LARGE_PIC)
7407 if (GET_CODE (disp) != CONST)
7409 disp = XEXP (disp, 0);
7413 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7414 of GOT tables. We should not need these anyway. */
7415 if (GET_CODE (disp) != UNSPEC
7416 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7417 && XINT (disp, 1) != UNSPEC_GOTOFF
7418 && XINT (disp, 1) != UNSPEC_PLTOFF))
7421 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7422 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7428 if (GET_CODE (disp) == PLUS)
7430 if (!CONST_INT_P (XEXP (disp, 1)))
7432 disp = XEXP (disp, 0);
7436 if (TARGET_MACHO && darwin_local_data_pic (disp))
7439 if (GET_CODE (disp) != UNSPEC)
7442 switch (XINT (disp, 1))
7447 /* We need to check for both symbols and labels because VxWorks loads
7448 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7450 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7451 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7453 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7454 While ABI specify also 32bit relocation but we don't produce it in
7455 small PIC model at all. */
7456 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7457 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7459 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7461 case UNSPEC_GOTTPOFF:
7462 case UNSPEC_GOTNTPOFF:
7463 case UNSPEC_INDNTPOFF:
7466 disp = XVECEXP (disp, 0, 0);
7467 return (GET_CODE (disp) == SYMBOL_REF
7468 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7470 disp = XVECEXP (disp, 0, 0);
7471 return (GET_CODE (disp) == SYMBOL_REF
7472 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7474 disp = XVECEXP (disp, 0, 0);
7475 return (GET_CODE (disp) == SYMBOL_REF
7476 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7482 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7483 memory address for an instruction. The MODE argument is the machine mode
7484 for the MEM expression that wants to use this address.
7486 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7487 convert common non-canonical forms to canonical form so that they will
7491 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7492 rtx addr, int strict)
7494 struct ix86_address parts;
7495 rtx base, index, disp;
7496 HOST_WIDE_INT scale;
7497 const char *reason = NULL;
7498 rtx reason_rtx = NULL_RTX;
7500 if (ix86_decompose_address (addr, &parts) <= 0)
7502 reason = "decomposition failed";
7507 index = parts.index;
7509 scale = parts.scale;
7511 /* Validate base register.
7513 Don't allow SUBREG's that span more than a word here. It can lead to spill
7514 failures when the base is one word out of a two word structure, which is
7515 represented internally as a DImode int. */
7524 else if (GET_CODE (base) == SUBREG
7525 && REG_P (SUBREG_REG (base))
7526 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7528 reg = SUBREG_REG (base);
7531 reason = "base is not a register";
7535 if (GET_MODE (base) != Pmode)
7537 reason = "base is not in Pmode";
7541 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7542 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7544 reason = "base is not valid";
7549 /* Validate index register.
7551 Don't allow SUBREG's that span more than a word here -- same as above. */
7560 else if (GET_CODE (index) == SUBREG
7561 && REG_P (SUBREG_REG (index))
7562 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7564 reg = SUBREG_REG (index);
7567 reason = "index is not a register";
7571 if (GET_MODE (index) != Pmode)
7573 reason = "index is not in Pmode";
7577 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7578 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7580 reason = "index is not valid";
7585 /* Validate scale factor. */
7588 reason_rtx = GEN_INT (scale);
7591 reason = "scale without index";
7595 if (scale != 2 && scale != 4 && scale != 8)
7597 reason = "scale is not a valid multiplier";
7602 /* Validate displacement. */
7607 if (GET_CODE (disp) == CONST
7608 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7609 switch (XINT (XEXP (disp, 0), 1))
7611 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7612 used. While ABI specify also 32bit relocations, we don't produce
7613 them at all and use IP relative instead. */
7616 gcc_assert (flag_pic);
7618 goto is_legitimate_pic;
7619 reason = "64bit address unspec";
7622 case UNSPEC_GOTPCREL:
7623 gcc_assert (flag_pic);
7624 goto is_legitimate_pic;
7626 case UNSPEC_GOTTPOFF:
7627 case UNSPEC_GOTNTPOFF:
7628 case UNSPEC_INDNTPOFF:
7634 reason = "invalid address unspec";
7638 else if (SYMBOLIC_CONST (disp)
7642 && MACHOPIC_INDIRECT
7643 && !machopic_operand_p (disp)
7649 if (TARGET_64BIT && (index || base))
7651 /* foo@dtpoff(%rX) is ok. */
7652 if (GET_CODE (disp) != CONST
7653 || GET_CODE (XEXP (disp, 0)) != PLUS
7654 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7655 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7656 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7657 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7659 reason = "non-constant pic memory reference";
7663 else if (! legitimate_pic_address_disp_p (disp))
7665 reason = "displacement is an invalid pic construct";
7669 /* This code used to verify that a symbolic pic displacement
7670 includes the pic_offset_table_rtx register.
7672 While this is good idea, unfortunately these constructs may
7673 be created by "adds using lea" optimization for incorrect
7682 This code is nonsensical, but results in addressing
7683 GOT table with pic_offset_table_rtx base. We can't
7684 just refuse it easily, since it gets matched by
7685 "addsi3" pattern, that later gets split to lea in the
7686 case output register differs from input. While this
7687 can be handled by separate addsi pattern for this case
7688 that never results in lea, this seems to be easier and
7689 correct fix for crash to disable this test. */
7691 else if (GET_CODE (disp) != LABEL_REF
7692 && !CONST_INT_P (disp)
7693 && (GET_CODE (disp) != CONST
7694 || !legitimate_constant_p (disp))
7695 && (GET_CODE (disp) != SYMBOL_REF
7696 || !legitimate_constant_p (disp)))
7698 reason = "displacement is not constant";
7701 else if (TARGET_64BIT
7702 && !x86_64_immediate_operand (disp, VOIDmode))
7704 reason = "displacement is out of range";
7709 /* Everything looks valid. */
7716 /* Return a unique alias set for the GOT. */
7718 static alias_set_type
7719 ix86_GOT_alias_set (void)
7721 static alias_set_type set = -1;
7723 set = new_alias_set ();
7727 /* Return a legitimate reference for ORIG (an address) using the
7728 register REG. If REG is 0, a new pseudo is generated.
7730 There are two types of references that must be handled:
7732 1. Global data references must load the address from the GOT, via
7733 the PIC reg. An insn is emitted to do this load, and the reg is
7736 2. Static data references, constant pool addresses, and code labels
7737 compute the address as an offset from the GOT, whose base is in
7738 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7739 differentiate them from global data objects. The returned
7740 address is the PIC reg + an unspec constant.
7742 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7743 reg also appears in the address. */
7746 legitimize_pic_address (rtx orig, rtx reg)
7753 if (TARGET_MACHO && !TARGET_64BIT)
7756 reg = gen_reg_rtx (Pmode);
7757 /* Use the generic Mach-O PIC machinery. */
7758 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7762 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7764 else if (TARGET_64BIT
7765 && ix86_cmodel != CM_SMALL_PIC
7766 && gotoff_operand (addr, Pmode))
7769 /* This symbol may be referenced via a displacement from the PIC
7770 base address (@GOTOFF). */
7772 if (reload_in_progress)
7773 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7774 if (GET_CODE (addr) == CONST)
7775 addr = XEXP (addr, 0);
7776 if (GET_CODE (addr) == PLUS)
7778 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7780 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7783 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7784 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7786 tmpreg = gen_reg_rtx (Pmode);
7789 emit_move_insn (tmpreg, new_rtx);
7793 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7794 tmpreg, 1, OPTAB_DIRECT);
7797 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7799 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7801 /* This symbol may be referenced via a displacement from the PIC
7802 base address (@GOTOFF). */
7804 if (reload_in_progress)
7805 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7806 if (GET_CODE (addr) == CONST)
7807 addr = XEXP (addr, 0);
7808 if (GET_CODE (addr) == PLUS)
7810 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7812 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7815 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7816 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7817 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7821 emit_move_insn (reg, new_rtx);
7825 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7826 /* We can't use @GOTOFF for text labels on VxWorks;
7827 see gotoff_operand. */
7828 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7830 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7832 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
7833 return legitimize_dllimport_symbol (addr, true);
7834 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
7835 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
7836 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
7838 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
7839 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
7843 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7845 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7846 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7847 new_rtx = gen_const_mem (Pmode, new_rtx);
7848 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7851 reg = gen_reg_rtx (Pmode);
7852 /* Use directly gen_movsi, otherwise the address is loaded
7853 into register for CSE. We don't want to CSE this addresses,
7854 instead we CSE addresses from the GOT table, so skip this. */
7855 emit_insn (gen_movsi (reg, new_rtx));
7860 /* This symbol must be referenced via a load from the
7861 Global Offset Table (@GOT). */
7863 if (reload_in_progress)
7864 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7865 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7866 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7868 new_rtx = force_reg (Pmode, new_rtx);
7869 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7870 new_rtx = gen_const_mem (Pmode, new_rtx);
7871 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7874 reg = gen_reg_rtx (Pmode);
7875 emit_move_insn (reg, new_rtx);
7881 if (CONST_INT_P (addr)
7882 && !x86_64_immediate_operand (addr, VOIDmode))
7886 emit_move_insn (reg, addr);
7890 new_rtx = force_reg (Pmode, addr);
7892 else if (GET_CODE (addr) == CONST)
7894 addr = XEXP (addr, 0);
7896 /* We must match stuff we generate before. Assume the only
7897 unspecs that can get here are ours. Not that we could do
7898 anything with them anyway.... */
7899 if (GET_CODE (addr) == UNSPEC
7900 || (GET_CODE (addr) == PLUS
7901 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7903 gcc_assert (GET_CODE (addr) == PLUS);
7905 if (GET_CODE (addr) == PLUS)
7907 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7909 /* Check first to see if this is a constant offset from a @GOTOFF
7910 symbol reference. */
7911 if (gotoff_operand (op0, Pmode)
7912 && CONST_INT_P (op1))
7916 if (reload_in_progress)
7917 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7918 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7920 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7921 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7922 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7926 emit_move_insn (reg, new_rtx);
7932 if (INTVAL (op1) < -16*1024*1024
7933 || INTVAL (op1) >= 16*1024*1024)
7935 if (!x86_64_immediate_operand (op1, Pmode))
7936 op1 = force_reg (Pmode, op1);
7937 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7943 base = legitimize_pic_address (XEXP (addr, 0), reg);
7944 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7945 base == reg ? NULL_RTX : reg);
7947 if (CONST_INT_P (new_rtx))
7948 new_rtx = plus_constant (base, INTVAL (new_rtx));
7951 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7953 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7954 new_rtx = XEXP (new_rtx, 1);
7956 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7964 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7967 get_thread_pointer (int to_reg)
7971 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7975 reg = gen_reg_rtx (Pmode);
7976 insn = gen_rtx_SET (VOIDmode, reg, tp);
7977 insn = emit_insn (insn);
7982 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7983 false if we expect this to be used for a memory address and true if
7984 we expect to load the address into a register. */
7987 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7989 rtx dest, base, off, pic, tp;
7994 case TLS_MODEL_GLOBAL_DYNAMIC:
7995 dest = gen_reg_rtx (Pmode);
7996 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7998 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
8000 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
8003 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
8004 insns = get_insns ();
8007 RTL_CONST_CALL_P (insns) = 1;
8008 emit_libcall_block (insns, dest, rax, x);
8010 else if (TARGET_64BIT && TARGET_GNU2_TLS)
8011 emit_insn (gen_tls_global_dynamic_64 (dest, x));
8013 emit_insn (gen_tls_global_dynamic_32 (dest, x));
8015 if (TARGET_GNU2_TLS)
8017 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
8019 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
8023 case TLS_MODEL_LOCAL_DYNAMIC:
8024 base = gen_reg_rtx (Pmode);
8025 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
8027 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
8029 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
8032 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
8033 insns = get_insns ();
8036 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
8037 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
8038 RTL_CONST_CALL_P (insns) = 1;
8039 emit_libcall_block (insns, base, rax, note);
8041 else if (TARGET_64BIT && TARGET_GNU2_TLS)
8042 emit_insn (gen_tls_local_dynamic_base_64 (base));
8044 emit_insn (gen_tls_local_dynamic_base_32 (base));
8046 if (TARGET_GNU2_TLS)
8048 rtx x = ix86_tls_module_base ();
8050 set_unique_reg_note (get_last_insn (), REG_EQUIV,
8051 gen_rtx_MINUS (Pmode, x, tp));
8054 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
8055 off = gen_rtx_CONST (Pmode, off);
8057 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
8059 if (TARGET_GNU2_TLS)
8061 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
8063 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
8068 case TLS_MODEL_INITIAL_EXEC:
8072 type = UNSPEC_GOTNTPOFF;
8076 if (reload_in_progress)
8077 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
8078 pic = pic_offset_table_rtx;
8079 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
8081 else if (!TARGET_ANY_GNU_TLS)
8083 pic = gen_reg_rtx (Pmode);
8084 emit_insn (gen_set_got (pic));
8085 type = UNSPEC_GOTTPOFF;
8090 type = UNSPEC_INDNTPOFF;
8093 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
8094 off = gen_rtx_CONST (Pmode, off);
8096 off = gen_rtx_PLUS (Pmode, pic, off);
8097 off = gen_const_mem (Pmode, off);
8098 set_mem_alias_set (off, ix86_GOT_alias_set ());
8100 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
8102 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
8103 off = force_reg (Pmode, off);
8104 return gen_rtx_PLUS (Pmode, base, off);
8108 base = get_thread_pointer (true);
8109 dest = gen_reg_rtx (Pmode);
8110 emit_insn (gen_subsi3 (dest, base, off));
8114 case TLS_MODEL_LOCAL_EXEC:
8115 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
8116 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
8117 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
8118 off = gen_rtx_CONST (Pmode, off);
8120 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
8122 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
8123 return gen_rtx_PLUS (Pmode, base, off);
8127 base = get_thread_pointer (true);
8128 dest = gen_reg_rtx (Pmode);
8129 emit_insn (gen_subsi3 (dest, base, off));
8140 /* Create or return the unique __imp_DECL dllimport symbol corresponding
8143 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
8144 htab_t dllimport_map;
8147 get_dllimport_decl (tree decl)
8149 struct tree_map *h, in;
8153 size_t namelen, prefixlen;
8159 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
8161 in.hash = htab_hash_pointer (decl);
8162 in.base.from = decl;
8163 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
8164 h = (struct tree_map *) *loc;
8168 *loc = h = GGC_NEW (struct tree_map);
8170 h->base.from = decl;
8171 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
8172 DECL_ARTIFICIAL (to) = 1;
8173 DECL_IGNORED_P (to) = 1;
8174 DECL_EXTERNAL (to) = 1;
8175 TREE_READONLY (to) = 1;
8177 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
8178 name = targetm.strip_name_encoding (name);
8179 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
8180 namelen = strlen (name);
8181 prefixlen = strlen (prefix);
8182 imp_name = (char *) alloca (namelen + prefixlen + 1);
8183 memcpy (imp_name, prefix, prefixlen);
8184 memcpy (imp_name + prefixlen, name, namelen + 1);
8186 name = ggc_alloc_string (imp_name, namelen + prefixlen);
8187 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
8188 SET_SYMBOL_REF_DECL (rtl, to);
8189 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
8191 rtl = gen_const_mem (Pmode, rtl);
8192 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
8194 SET_DECL_RTL (to, rtl);
8195 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
8200 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
8201 true if we require the result be a register. */
8204 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
8209 gcc_assert (SYMBOL_REF_DECL (symbol));
8210 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
8212 x = DECL_RTL (imp_decl);
8214 x = force_reg (Pmode, x);
8218 /* Try machine-dependent ways of modifying an illegitimate address
8219 to be legitimate. If we find one, return the new, valid address.
8220 This macro is used in only one place: `memory_address' in explow.c.
8222 OLDX is the address as it was before break_out_memory_refs was called.
8223 In some cases it is useful to look at this to decide what needs to be done.
8225 MODE and WIN are passed so that this macro can use
8226 GO_IF_LEGITIMATE_ADDRESS.
8228 It is always safe for this macro to do nothing. It exists to recognize
8229 opportunities to optimize the output.
8231 For the 80386, we handle X+REG by loading X into a register R and
8232 using R+REG. R will go in a general reg and indexing will be used.
8233 However, if REG is a broken-out memory address or multiplication,
8234 nothing needs to be done because REG can certainly go in a general reg.
8236 When -fpic is used, special handling is needed for symbolic references.
8237 See comments by legitimize_pic_address in i386.c for details. */
8240 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8245 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8247 return legitimize_tls_address (x, (enum tls_model) log, false);
8248 if (GET_CODE (x) == CONST
8249 && GET_CODE (XEXP (x, 0)) == PLUS
8250 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8251 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8253 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8254 (enum tls_model) log, false);
8255 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8258 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8260 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8261 return legitimize_dllimport_symbol (x, true);
8262 if (GET_CODE (x) == CONST
8263 && GET_CODE (XEXP (x, 0)) == PLUS
8264 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8265 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8267 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8268 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8272 if (flag_pic && SYMBOLIC_CONST (x))
8273 return legitimize_pic_address (x, 0);
8275 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8276 if (GET_CODE (x) == ASHIFT
8277 && CONST_INT_P (XEXP (x, 1))
8278 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8281 log = INTVAL (XEXP (x, 1));
8282 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8283 GEN_INT (1 << log));
8286 if (GET_CODE (x) == PLUS)
8288 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8290 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8291 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8292 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8295 log = INTVAL (XEXP (XEXP (x, 0), 1));
8296 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8297 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8298 GEN_INT (1 << log));
8301 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8302 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8303 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8306 log = INTVAL (XEXP (XEXP (x, 1), 1));
8307 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8308 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8309 GEN_INT (1 << log));
8312 /* Put multiply first if it isn't already. */
8313 if (GET_CODE (XEXP (x, 1)) == MULT)
8315 rtx tmp = XEXP (x, 0);
8316 XEXP (x, 0) = XEXP (x, 1);
8321 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8322 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8323 created by virtual register instantiation, register elimination, and
8324 similar optimizations. */
8325 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8328 x = gen_rtx_PLUS (Pmode,
8329 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8330 XEXP (XEXP (x, 1), 0)),
8331 XEXP (XEXP (x, 1), 1));
8335 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8336 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8337 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8338 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8339 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8340 && CONSTANT_P (XEXP (x, 1)))
8343 rtx other = NULL_RTX;
8345 if (CONST_INT_P (XEXP (x, 1)))
8347 constant = XEXP (x, 1);
8348 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8350 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8352 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8353 other = XEXP (x, 1);
8361 x = gen_rtx_PLUS (Pmode,
8362 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8363 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8364 plus_constant (other, INTVAL (constant)));
8368 if (changed && legitimate_address_p (mode, x, FALSE))
8371 if (GET_CODE (XEXP (x, 0)) == MULT)
8374 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8377 if (GET_CODE (XEXP (x, 1)) == MULT)
8380 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8384 && REG_P (XEXP (x, 1))
8385 && REG_P (XEXP (x, 0)))
8388 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8391 x = legitimize_pic_address (x, 0);
8394 if (changed && legitimate_address_p (mode, x, FALSE))
8397 if (REG_P (XEXP (x, 0)))
8399 rtx temp = gen_reg_rtx (Pmode);
8400 rtx val = force_operand (XEXP (x, 1), temp);
8402 emit_move_insn (temp, val);
8408 else if (REG_P (XEXP (x, 1)))
8410 rtx temp = gen_reg_rtx (Pmode);
8411 rtx val = force_operand (XEXP (x, 0), temp);
8413 emit_move_insn (temp, val);
8423 /* Print an integer constant expression in assembler syntax. Addition
8424 and subtraction are the only arithmetic that may appear in these
8425 expressions. FILE is the stdio stream to write to, X is the rtx, and
8426 CODE is the operand print code from the output string. */
8429 output_pic_addr_const (FILE *file, rtx x, int code)
8433 switch (GET_CODE (x))
8436 gcc_assert (flag_pic);
8441 if (! TARGET_MACHO || TARGET_64BIT)
8442 output_addr_const (file, x);
8445 const char *name = XSTR (x, 0);
8447 /* Mark the decl as referenced so that cgraph will
8448 output the function. */
8449 if (SYMBOL_REF_DECL (x))
8450 mark_decl_referenced (SYMBOL_REF_DECL (x));
8453 if (MACHOPIC_INDIRECT
8454 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8455 name = machopic_indirection_name (x, /*stub_p=*/true);
8457 assemble_name (file, name);
8459 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
8460 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8461 fputs ("@PLT", file);
8468 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8469 assemble_name (asm_out_file, buf);
8473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8477 /* This used to output parentheses around the expression,
8478 but that does not work on the 386 (either ATT or BSD assembler). */
8479 output_pic_addr_const (file, XEXP (x, 0), code);
8483 if (GET_MODE (x) == VOIDmode)
8485 /* We can use %d if the number is <32 bits and positive. */
8486 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8487 fprintf (file, "0x%lx%08lx",
8488 (unsigned long) CONST_DOUBLE_HIGH (x),
8489 (unsigned long) CONST_DOUBLE_LOW (x));
8491 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8494 /* We can't handle floating point constants;
8495 PRINT_OPERAND must handle them. */
8496 output_operand_lossage ("floating constant misused");
8500 /* Some assemblers need integer constants to appear first. */
8501 if (CONST_INT_P (XEXP (x, 0)))
8503 output_pic_addr_const (file, XEXP (x, 0), code);
8505 output_pic_addr_const (file, XEXP (x, 1), code);
8509 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8510 output_pic_addr_const (file, XEXP (x, 1), code);
8512 output_pic_addr_const (file, XEXP (x, 0), code);
8518 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8519 output_pic_addr_const (file, XEXP (x, 0), code);
8521 output_pic_addr_const (file, XEXP (x, 1), code);
8523 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8527 gcc_assert (XVECLEN (x, 0) == 1);
8528 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8529 switch (XINT (x, 1))
8532 fputs ("@GOT", file);
8535 fputs ("@GOTOFF", file);
8538 fputs ("@PLTOFF", file);
8540 case UNSPEC_GOTPCREL:
8541 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8542 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8544 case UNSPEC_GOTTPOFF:
8545 /* FIXME: This might be @TPOFF in Sun ld too. */
8546 fputs ("@GOTTPOFF", file);
8549 fputs ("@TPOFF", file);
8553 fputs ("@TPOFF", file);
8555 fputs ("@NTPOFF", file);
8558 fputs ("@DTPOFF", file);
8560 case UNSPEC_GOTNTPOFF:
8562 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8563 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8565 fputs ("@GOTNTPOFF", file);
8567 case UNSPEC_INDNTPOFF:
8568 fputs ("@INDNTPOFF", file);
8571 output_operand_lossage ("invalid UNSPEC as operand");
8577 output_operand_lossage ("invalid expression as operand");
8581 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8582 We need to emit DTP-relative relocations. */
8584 static void ATTRIBUTE_UNUSED
8585 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8587 fputs (ASM_LONG, file);
8588 output_addr_const (file, x);
8589 fputs ("@DTPOFF", file);
8595 fputs (", 0", file);
8602 /* In the name of slightly smaller debug output, and to cater to
8603 general assembler lossage, recognize PIC+GOTOFF and turn it back
8604 into a direct symbol reference.
8606 On Darwin, this is necessary to avoid a crash, because Darwin
8607 has a different PIC label for each routine but the DWARF debugging
8608 information is not associated with any particular routine, so it's
8609 necessary to remove references to the PIC label from RTL stored by
8610 the DWARF output code. */
8613 ix86_delegitimize_address (rtx orig_x)
8616 /* reg_addend is NULL or a multiple of some register. */
8617 rtx reg_addend = NULL_RTX;
8618 /* const_addend is NULL or a const_int. */
8619 rtx const_addend = NULL_RTX;
8620 /* This is the result, or NULL. */
8621 rtx result = NULL_RTX;
8628 if (GET_CODE (x) != CONST
8629 || GET_CODE (XEXP (x, 0)) != UNSPEC
8630 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8633 return XVECEXP (XEXP (x, 0), 0, 0);
8636 if (GET_CODE (x) != PLUS
8637 || GET_CODE (XEXP (x, 1)) != CONST)
8640 if (REG_P (XEXP (x, 0))
8641 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8642 /* %ebx + GOT/GOTOFF */
8644 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8646 /* %ebx + %reg * scale + GOT/GOTOFF */
8647 reg_addend = XEXP (x, 0);
8648 if (REG_P (XEXP (reg_addend, 0))
8649 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8650 reg_addend = XEXP (reg_addend, 1);
8651 else if (REG_P (XEXP (reg_addend, 1))
8652 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8653 reg_addend = XEXP (reg_addend, 0);
8656 if (!REG_P (reg_addend)
8657 && GET_CODE (reg_addend) != MULT
8658 && GET_CODE (reg_addend) != ASHIFT)
8664 x = XEXP (XEXP (x, 1), 0);
8665 if (GET_CODE (x) == PLUS
8666 && CONST_INT_P (XEXP (x, 1)))
8668 const_addend = XEXP (x, 1);
8672 if (GET_CODE (x) == UNSPEC
8673 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8674 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8675 result = XVECEXP (x, 0, 0);
8677 if (TARGET_MACHO && darwin_local_data_pic (x)
8679 result = XEXP (x, 0);
8685 result = gen_rtx_PLUS (Pmode, result, const_addend);
8687 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8691 /* If X is a machine specific address (i.e. a symbol or label being
8692 referenced as a displacement from the GOT implemented using an
8693 UNSPEC), then return the base term. Otherwise return X. */
8696 ix86_find_base_term (rtx x)
8702 if (GET_CODE (x) != CONST)
8705 if (GET_CODE (term) == PLUS
8706 && (CONST_INT_P (XEXP (term, 1))
8707 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8708 term = XEXP (term, 0);
8709 if (GET_CODE (term) != UNSPEC
8710 || XINT (term, 1) != UNSPEC_GOTPCREL)
8713 term = XVECEXP (term, 0, 0);
8715 if (GET_CODE (term) != SYMBOL_REF
8716 && GET_CODE (term) != LABEL_REF)
8722 term = ix86_delegitimize_address (x);
8724 if (GET_CODE (term) != SYMBOL_REF
8725 && GET_CODE (term) != LABEL_REF)
8732 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8737 if (mode == CCFPmode || mode == CCFPUmode)
8739 enum rtx_code second_code, bypass_code;
8740 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8741 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8742 code = ix86_fp_compare_code_to_integer (code);
8746 code = reverse_condition (code);
8797 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8801 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8802 Those same assemblers have the same but opposite lossage on cmov. */
8804 suffix = fp ? "nbe" : "a";
8805 else if (mode == CCCmode)
8828 gcc_assert (mode == CCmode || mode == CCCmode);
8850 gcc_assert (mode == CCmode || mode == CCCmode);
8851 suffix = fp ? "nb" : "ae";
8854 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8861 else if (mode == CCCmode)
8862 suffix = fp ? "nb" : "ae";
8867 suffix = fp ? "u" : "p";
8870 suffix = fp ? "nu" : "np";
8875 fputs (suffix, file);
8878 /* Print the name of register X to FILE based on its machine mode and number.
8879 If CODE is 'w', pretend the mode is HImode.
8880 If CODE is 'b', pretend the mode is QImode.
8881 If CODE is 'k', pretend the mode is SImode.
8882 If CODE is 'q', pretend the mode is DImode.
8883 If CODE is 'h', pretend the reg is the 'high' byte register.
8884 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8887 print_reg (rtx x, int code, FILE *file)
8889 gcc_assert (x == pc_rtx
8890 || (REGNO (x) != ARG_POINTER_REGNUM
8891 && REGNO (x) != FRAME_POINTER_REGNUM
8892 && REGNO (x) != FLAGS_REG
8893 && REGNO (x) != FPSR_REG
8894 && REGNO (x) != FPCR_REG));
8896 if (ASSEMBLER_DIALECT == ASM_ATT)
8901 gcc_assert (TARGET_64BIT);
8902 fputs ("rip", file);
8906 if (code == 'w' || MMX_REG_P (x))
8908 else if (code == 'b')
8910 else if (code == 'k')
8912 else if (code == 'q')
8914 else if (code == 'y')
8916 else if (code == 'h')
8919 code = GET_MODE_SIZE (GET_MODE (x));
8921 /* Irritatingly, AMD extended registers use different naming convention
8922 from the normal registers. */
8923 if (REX_INT_REG_P (x))
8925 gcc_assert (TARGET_64BIT);
8929 error ("extended registers have no high halves");
8932 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8935 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8938 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8941 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8944 error ("unsupported operand size for extended register");
8952 if (STACK_TOP_P (x))
8954 fputs ("st(0)", file);
8961 if (! ANY_FP_REG_P (x))
8962 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8967 fputs (hi_reg_name[REGNO (x)], file);
8970 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8972 fputs (qi_reg_name[REGNO (x)], file);
8975 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8977 fputs (qi_high_reg_name[REGNO (x)], file);
8984 /* Locate some local-dynamic symbol still in use by this function
8985 so that we can print its name in some tls_local_dynamic_base
8989 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8993 if (GET_CODE (x) == SYMBOL_REF
8994 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8996 cfun->machine->some_ld_name = XSTR (x, 0);
9004 get_some_local_dynamic_name (void)
9008 if (cfun->machine->some_ld_name)
9009 return cfun->machine->some_ld_name;
9011 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9013 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9014 return cfun->machine->some_ld_name;
9020 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
9021 C -- print opcode suffix for set/cmov insn.
9022 c -- like C, but print reversed condition
9023 F,f -- likewise, but for floating-point.
9024 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
9026 R -- print the prefix for register names.
9027 z -- print the opcode suffix for the size of the current operand.
9028 * -- print a star (in certain assembler syntax)
9029 A -- print an absolute memory reference.
9030 w -- print the operand as if it's a "word" (HImode) even if it isn't.
9031 s -- print a shift double count, followed by the assemblers argument
9033 b -- print the QImode name of the register for the indicated operand.
9034 %b0 would print %al if operands[0] is reg 0.
9035 w -- likewise, print the HImode name of the register.
9036 k -- likewise, print the SImode name of the register.
9037 q -- likewise, print the DImode name of the register.
9038 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
9039 y -- print "st(0)" instead of "st" as a register.
9040 D -- print condition for SSE cmp instruction.
9041 P -- if PIC, print an @PLT suffix.
9042 X -- don't print any sort of PIC '@' suffix for a symbol.
9043 & -- print some in-use local-dynamic symbol name.
9044 H -- print a memory address offset by 8; used for sse high-parts
9045 Y -- print condition for SSE5 com* instruction.
9046 + -- print a branch hint as 'cs' or 'ds' prefix
9047 ; -- print a semicolon (after prefixes due to bug in older gas).
9051 print_operand (FILE *file, rtx x, int code)
9058 if (ASSEMBLER_DIALECT == ASM_ATT)
9063 assemble_name (file, get_some_local_dynamic_name ());
9067 switch (ASSEMBLER_DIALECT)
9074 /* Intel syntax. For absolute addresses, registers should not
9075 be surrounded by braces. */
9079 PRINT_OPERAND (file, x, 0);
9089 PRINT_OPERAND (file, x, 0);
9094 if (ASSEMBLER_DIALECT == ASM_ATT)
9099 if (ASSEMBLER_DIALECT == ASM_ATT)
9104 if (ASSEMBLER_DIALECT == ASM_ATT)
9109 if (ASSEMBLER_DIALECT == ASM_ATT)
9114 if (ASSEMBLER_DIALECT == ASM_ATT)
9119 if (ASSEMBLER_DIALECT == ASM_ATT)
9124 /* 387 opcodes don't get size suffixes if the operands are
9126 if (STACK_REG_P (x))
9129 /* Likewise if using Intel opcodes. */
9130 if (ASSEMBLER_DIALECT == ASM_INTEL)
9133 /* This is the size of op from size of operand. */
9134 switch (GET_MODE_SIZE (GET_MODE (x)))
9143 #ifdef HAVE_GAS_FILDS_FISTS
9153 if (GET_MODE (x) == SFmode)
9168 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
9172 #ifdef GAS_MNEMONICS
9201 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
9203 PRINT_OPERAND (file, x, 0);
9209 /* Little bit of braindamage here. The SSE compare instructions
9210 does use completely different names for the comparisons that the
9211 fp conditional moves. */
9212 switch (GET_CODE (x))
9227 fputs ("unord", file);
9231 fputs ("neq", file);
9235 fputs ("nlt", file);
9239 fputs ("nle", file);
9242 fputs ("ord", file);
9249 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9250 if (ASSEMBLER_DIALECT == ASM_ATT)
9252 switch (GET_MODE (x))
9254 case HImode: putc ('w', file); break;
9256 case SFmode: putc ('l', file); break;
9258 case DFmode: putc ('q', file); break;
9259 default: gcc_unreachable ();
9266 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9269 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9270 if (ASSEMBLER_DIALECT == ASM_ATT)
9273 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9276 /* Like above, but reverse condition */
9278 /* Check to see if argument to %c is really a constant
9279 and not a condition code which needs to be reversed. */
9280 if (!COMPARISON_P (x))
9282 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9285 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9288 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9289 if (ASSEMBLER_DIALECT == ASM_ATT)
9292 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9296 /* It doesn't actually matter what mode we use here, as we're
9297 only going to use this for printing. */
9298 x = adjust_address_nv (x, DImode, 8);
9305 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9308 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9311 int pred_val = INTVAL (XEXP (x, 0));
9313 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9314 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9316 int taken = pred_val > REG_BR_PROB_BASE / 2;
9317 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9319 /* Emit hints only in the case default branch prediction
9320 heuristics would fail. */
9321 if (taken != cputaken)
9323 /* We use 3e (DS) prefix for taken branches and
9324 2e (CS) prefix for not taken branches. */
9326 fputs ("ds ; ", file);
9328 fputs ("cs ; ", file);
9336 switch (GET_CODE (x))
9339 fputs ("neq", file);
9346 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9350 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9361 fputs ("unord", file);
9364 fputs ("ord", file);
9367 fputs ("ueq", file);
9370 fputs ("nlt", file);
9373 fputs ("nle", file);
9376 fputs ("ule", file);
9379 fputs ("ult", file);
9382 fputs ("une", file);
9391 fputs (" ; ", file);
9398 output_operand_lossage ("invalid operand code '%c'", code);
9403 print_reg (x, code, file);
9407 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9408 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9409 && GET_MODE (x) != BLKmode)
9412 switch (GET_MODE_SIZE (GET_MODE (x)))
9414 case 1: size = "BYTE"; break;
9415 case 2: size = "WORD"; break;
9416 case 4: size = "DWORD"; break;
9417 case 8: size = "QWORD"; break;
9418 case 12: size = "XWORD"; break;
9420 if (GET_MODE (x) == XFmode)
9429 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9432 else if (code == 'w')
9434 else if (code == 'k')
9438 fputs (" PTR ", file);
9442 /* Avoid (%rip) for call operands. */
9443 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9444 && !CONST_INT_P (x))
9445 output_addr_const (file, x);
9446 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9447 output_operand_lossage ("invalid constraints for operand");
9452 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9457 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9458 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9460 if (ASSEMBLER_DIALECT == ASM_ATT)
9462 fprintf (file, "0x%08lx", (long unsigned int) l);
9465 /* These float cases don't actually occur as immediate operands. */
9466 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9470 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9471 fprintf (file, "%s", dstr);
9474 else if (GET_CODE (x) == CONST_DOUBLE
9475 && GET_MODE (x) == XFmode)
9479 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9480 fprintf (file, "%s", dstr);
9485 /* We have patterns that allow zero sets of memory, for instance.
9486 In 64-bit mode, we should probably support all 8-byte vectors,
9487 since we can in fact encode that into an immediate. */
9488 if (GET_CODE (x) == CONST_VECTOR)
9490 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9496 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9498 if (ASSEMBLER_DIALECT == ASM_ATT)
9501 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9502 || GET_CODE (x) == LABEL_REF)
9504 if (ASSEMBLER_DIALECT == ASM_ATT)
9507 fputs ("OFFSET FLAT:", file);
9510 if (CONST_INT_P (x))
9511 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9513 output_pic_addr_const (file, x, code);
9515 output_addr_const (file, x);
9519 /* Print a memory operand whose address is ADDR. */
9522 print_operand_address (FILE *file, rtx addr)
9524 struct ix86_address parts;
9525 rtx base, index, disp;
9527 int ok = ix86_decompose_address (addr, &parts);
9532 index = parts.index;
9534 scale = parts.scale;
9542 if (ASSEMBLER_DIALECT == ASM_ATT)
9544 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9550 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9551 if (TARGET_64BIT && !base && !index)
9555 if (GET_CODE (disp) == CONST
9556 && GET_CODE (XEXP (disp, 0)) == PLUS
9557 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9558 symbol = XEXP (XEXP (disp, 0), 0);
9560 if (GET_CODE (symbol) == LABEL_REF
9561 || (GET_CODE (symbol) == SYMBOL_REF
9562 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9565 if (!base && !index)
9567 /* Displacement only requires special attention. */
9569 if (CONST_INT_P (disp))
9571 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9572 fputs ("ds:", file);
9573 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9576 output_pic_addr_const (file, disp, 0);
9578 output_addr_const (file, disp);
9582 if (ASSEMBLER_DIALECT == ASM_ATT)
9587 output_pic_addr_const (file, disp, 0);
9588 else if (GET_CODE (disp) == LABEL_REF)
9589 output_asm_label (disp);
9591 output_addr_const (file, disp);
9596 print_reg (base, 0, file);
9600 print_reg (index, 0, file);
9602 fprintf (file, ",%d", scale);
9608 rtx offset = NULL_RTX;
9612 /* Pull out the offset of a symbol; print any symbol itself. */
9613 if (GET_CODE (disp) == CONST
9614 && GET_CODE (XEXP (disp, 0)) == PLUS
9615 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9617 offset = XEXP (XEXP (disp, 0), 1);
9618 disp = gen_rtx_CONST (VOIDmode,
9619 XEXP (XEXP (disp, 0), 0));
9623 output_pic_addr_const (file, disp, 0);
9624 else if (GET_CODE (disp) == LABEL_REF)
9625 output_asm_label (disp);
9626 else if (CONST_INT_P (disp))
9629 output_addr_const (file, disp);
9635 print_reg (base, 0, file);
9638 if (INTVAL (offset) >= 0)
9640 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9644 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9651 print_reg (index, 0, file);
9653 fprintf (file, "*%d", scale);
9661 output_addr_const_extra (FILE *file, rtx x)
9665 if (GET_CODE (x) != UNSPEC)
9668 op = XVECEXP (x, 0, 0);
9669 switch (XINT (x, 1))
9671 case UNSPEC_GOTTPOFF:
9672 output_addr_const (file, op);
9673 /* FIXME: This might be @TPOFF in Sun ld. */
9674 fputs ("@GOTTPOFF", file);
9677 output_addr_const (file, op);
9678 fputs ("@TPOFF", file);
9681 output_addr_const (file, op);
9683 fputs ("@TPOFF", file);
9685 fputs ("@NTPOFF", file);
9688 output_addr_const (file, op);
9689 fputs ("@DTPOFF", file);
9691 case UNSPEC_GOTNTPOFF:
9692 output_addr_const (file, op);
9694 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9695 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9697 fputs ("@GOTNTPOFF", file);
9699 case UNSPEC_INDNTPOFF:
9700 output_addr_const (file, op);
9701 fputs ("@INDNTPOFF", file);
9711 /* Split one or more DImode RTL references into pairs of SImode
9712 references. The RTL can be REG, offsettable MEM, integer constant, or
9713 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9714 split and "num" is its length. lo_half and hi_half are output arrays
9715 that parallel "operands". */
9718 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9722 rtx op = operands[num];
9724 /* simplify_subreg refuse to split volatile memory addresses,
9725 but we still have to handle it. */
9728 lo_half[num] = adjust_address (op, SImode, 0);
9729 hi_half[num] = adjust_address (op, SImode, 4);
9733 lo_half[num] = simplify_gen_subreg (SImode, op,
9734 GET_MODE (op) == VOIDmode
9735 ? DImode : GET_MODE (op), 0);
9736 hi_half[num] = simplify_gen_subreg (SImode, op,
9737 GET_MODE (op) == VOIDmode
9738 ? DImode : GET_MODE (op), 4);
9742 /* Split one or more TImode RTL references into pairs of DImode
9743 references. The RTL can be REG, offsettable MEM, integer constant, or
9744 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9745 split and "num" is its length. lo_half and hi_half are output arrays
9746 that parallel "operands". */
9749 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9753 rtx op = operands[num];
9755 /* simplify_subreg refuse to split volatile memory addresses, but we
9756 still have to handle it. */
9759 lo_half[num] = adjust_address (op, DImode, 0);
9760 hi_half[num] = adjust_address (op, DImode, 8);
9764 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9765 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9770 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9771 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9772 is the expression of the binary operation. The output may either be
9773 emitted here, or returned to the caller, like all output_* functions.
9775 There is no guarantee that the operands are the same mode, as they
9776 might be within FLOAT or FLOAT_EXTEND expressions. */
9778 #ifndef SYSV386_COMPAT
9779 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9780 wants to fix the assemblers because that causes incompatibility
9781 with gcc. No-one wants to fix gcc because that causes
9782 incompatibility with assemblers... You can use the option of
9783 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9784 #define SYSV386_COMPAT 1
9788 output_387_binary_op (rtx insn, rtx *operands)
9790 static char buf[30];
9793 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9795 #ifdef ENABLE_CHECKING
9796 /* Even if we do not want to check the inputs, this documents input
9797 constraints. Which helps in understanding the following code. */
9798 if (STACK_REG_P (operands[0])
9799 && ((REG_P (operands[1])
9800 && REGNO (operands[0]) == REGNO (operands[1])
9801 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9802 || (REG_P (operands[2])
9803 && REGNO (operands[0]) == REGNO (operands[2])
9804 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9805 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9808 gcc_assert (is_sse);
9811 switch (GET_CODE (operands[3]))
9814 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9815 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9823 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9824 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9832 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9833 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9841 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9842 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9856 if (GET_MODE (operands[0]) == SFmode)
9857 strcat (buf, "ss\t{%2, %0|%0, %2}");
9859 strcat (buf, "sd\t{%2, %0|%0, %2}");
9864 switch (GET_CODE (operands[3]))
9868 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9870 rtx temp = operands[2];
9871 operands[2] = operands[1];
9875 /* know operands[0] == operands[1]. */
9877 if (MEM_P (operands[2]))
9883 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9885 if (STACK_TOP_P (operands[0]))
9886 /* How is it that we are storing to a dead operand[2]?
9887 Well, presumably operands[1] is dead too. We can't
9888 store the result to st(0) as st(0) gets popped on this
9889 instruction. Instead store to operands[2] (which I
9890 think has to be st(1)). st(1) will be popped later.
9891 gcc <= 2.8.1 didn't have this check and generated
9892 assembly code that the Unixware assembler rejected. */
9893 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9895 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9899 if (STACK_TOP_P (operands[0]))
9900 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9902 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9907 if (MEM_P (operands[1]))
9913 if (MEM_P (operands[2]))
9919 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9922 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9923 derived assemblers, confusingly reverse the direction of
9924 the operation for fsub{r} and fdiv{r} when the
9925 destination register is not st(0). The Intel assembler
9926 doesn't have this brain damage. Read !SYSV386_COMPAT to
9927 figure out what the hardware really does. */
9928 if (STACK_TOP_P (operands[0]))
9929 p = "{p\t%0, %2|rp\t%2, %0}";
9931 p = "{rp\t%2, %0|p\t%0, %2}";
9933 if (STACK_TOP_P (operands[0]))
9934 /* As above for fmul/fadd, we can't store to st(0). */
9935 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9937 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9942 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9945 if (STACK_TOP_P (operands[0]))
9946 p = "{rp\t%0, %1|p\t%1, %0}";
9948 p = "{p\t%1, %0|rp\t%0, %1}";
9950 if (STACK_TOP_P (operands[0]))
9951 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9953 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9958 if (STACK_TOP_P (operands[0]))
9960 if (STACK_TOP_P (operands[1]))
9961 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9963 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9966 else if (STACK_TOP_P (operands[1]))
9969 p = "{\t%1, %0|r\t%0, %1}";
9971 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9977 p = "{r\t%2, %0|\t%0, %2}";
9979 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9992 /* Return needed mode for entity in optimize_mode_switching pass. */
9995 ix86_mode_needed (int entity, rtx insn)
9997 enum attr_i387_cw mode;
9999 /* The mode UNINITIALIZED is used to store control word after a
10000 function call or ASM pattern. The mode ANY specify that function
10001 has no requirements on the control word and make no changes in the
10002 bits we are interested in. */
10005 || (NONJUMP_INSN_P (insn)
10006 && (asm_noperands (PATTERN (insn)) >= 0
10007 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
10008 return I387_CW_UNINITIALIZED;
10010 if (recog_memoized (insn) < 0)
10011 return I387_CW_ANY;
10013 mode = get_attr_i387_cw (insn);
10018 if (mode == I387_CW_TRUNC)
10023 if (mode == I387_CW_FLOOR)
10028 if (mode == I387_CW_CEIL)
10033 if (mode == I387_CW_MASK_PM)
10038 gcc_unreachable ();
10041 return I387_CW_ANY;
10044 /* Output code to initialize control word copies used by trunc?f?i and
10045 rounding patterns. CURRENT_MODE is set to current control word,
10046 while NEW_MODE is set to new control word. */
10049 emit_i387_cw_initialization (int mode)
10051 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
10054 enum ix86_stack_slot slot;
10056 rtx reg = gen_reg_rtx (HImode);
10058 emit_insn (gen_x86_fnstcw_1 (stored_mode));
10059 emit_move_insn (reg, copy_rtx (stored_mode));
10061 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
10065 case I387_CW_TRUNC:
10066 /* round toward zero (truncate) */
10067 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
10068 slot = SLOT_CW_TRUNC;
10071 case I387_CW_FLOOR:
10072 /* round down toward -oo */
10073 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
10074 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
10075 slot = SLOT_CW_FLOOR;
10079 /* round up toward +oo */
10080 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
10081 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
10082 slot = SLOT_CW_CEIL;
10085 case I387_CW_MASK_PM:
10086 /* mask precision exception for nearbyint() */
10087 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
10088 slot = SLOT_CW_MASK_PM;
10092 gcc_unreachable ();
10099 case I387_CW_TRUNC:
10100 /* round toward zero (truncate) */
10101 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
10102 slot = SLOT_CW_TRUNC;
10105 case I387_CW_FLOOR:
10106 /* round down toward -oo */
10107 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
10108 slot = SLOT_CW_FLOOR;
10112 /* round up toward +oo */
10113 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
10114 slot = SLOT_CW_CEIL;
10117 case I387_CW_MASK_PM:
10118 /* mask precision exception for nearbyint() */
10119 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
10120 slot = SLOT_CW_MASK_PM;
10124 gcc_unreachable ();
10128 gcc_assert (slot < MAX_386_STACK_LOCALS);
10130 new_mode = assign_386_stack_local (HImode, slot);
10131 emit_move_insn (new_mode, reg);
10134 /* Output code for INSN to convert a float to a signed int. OPERANDS
10135 are the insn operands. The output may be [HSD]Imode and the input
10136 operand may be [SDX]Fmode. */
10139 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
10141 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
10142 int dimode_p = GET_MODE (operands[0]) == DImode;
10143 int round_mode = get_attr_i387_cw (insn);
10145 /* Jump through a hoop or two for DImode, since the hardware has no
10146 non-popping instruction. We used to do this a different way, but
10147 that was somewhat fragile and broke with post-reload splitters. */
10148 if ((dimode_p || fisttp) && !stack_top_dies)
10149 output_asm_insn ("fld\t%y1", operands);
10151 gcc_assert (STACK_TOP_P (operands[1]));
10152 gcc_assert (MEM_P (operands[0]));
10153 gcc_assert (GET_MODE (operands[1]) != TFmode);
10156 output_asm_insn ("fisttp%z0\t%0", operands);
10159 if (round_mode != I387_CW_ANY)
10160 output_asm_insn ("fldcw\t%3", operands);
10161 if (stack_top_dies || dimode_p)
10162 output_asm_insn ("fistp%z0\t%0", operands);
10164 output_asm_insn ("fist%z0\t%0", operands);
10165 if (round_mode != I387_CW_ANY)
10166 output_asm_insn ("fldcw\t%2", operands);
10172 /* Output code for x87 ffreep insn. The OPNO argument, which may only
10173 have the values zero or one, indicates the ffreep insn's operand
10174 from the OPERANDS array. */
10176 static const char *
10177 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
10179 if (TARGET_USE_FFREEP)
10180 #if HAVE_AS_IX86_FFREEP
10181 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
10184 static char retval[] = ".word\t0xc_df";
10185 int regno = REGNO (operands[opno]);
10187 gcc_assert (FP_REGNO_P (regno));
10189 retval[9] = '0' + (regno - FIRST_STACK_REG);
10194 return opno ? "fstp\t%y1" : "fstp\t%y0";
10198 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
10199 should be used. UNORDERED_P is true when fucom should be used. */
10202 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
10204 int stack_top_dies;
10205 rtx cmp_op0, cmp_op1;
10206 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
10210 cmp_op0 = operands[0];
10211 cmp_op1 = operands[1];
10215 cmp_op0 = operands[1];
10216 cmp_op1 = operands[2];
10221 if (GET_MODE (operands[0]) == SFmode)
10223 return "ucomiss\t{%1, %0|%0, %1}";
10225 return "comiss\t{%1, %0|%0, %1}";
10228 return "ucomisd\t{%1, %0|%0, %1}";
10230 return "comisd\t{%1, %0|%0, %1}";
10233 gcc_assert (STACK_TOP_P (cmp_op0));
10235 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
10237 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
10239 if (stack_top_dies)
10241 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
10242 return output_387_ffreep (operands, 1);
10245 return "ftst\n\tfnstsw\t%0";
10248 if (STACK_REG_P (cmp_op1)
10250 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10251 && REGNO (cmp_op1) != FIRST_STACK_REG)
10253 /* If both the top of the 387 stack dies, and the other operand
10254 is also a stack register that dies, then this must be a
10255 `fcompp' float compare */
10259 /* There is no double popping fcomi variant. Fortunately,
10260 eflags is immune from the fstp's cc clobbering. */
10262 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10264 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10265 return output_387_ffreep (operands, 0);
10270 return "fucompp\n\tfnstsw\t%0";
10272 return "fcompp\n\tfnstsw\t%0";
10277 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10279 static const char * const alt[16] =
10281 "fcom%z2\t%y2\n\tfnstsw\t%0",
10282 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10283 "fucom%z2\t%y2\n\tfnstsw\t%0",
10284 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10286 "ficom%z2\t%y2\n\tfnstsw\t%0",
10287 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10291 "fcomi\t{%y1, %0|%0, %y1}",
10292 "fcomip\t{%y1, %0|%0, %y1}",
10293 "fucomi\t{%y1, %0|%0, %y1}",
10294 "fucomip\t{%y1, %0|%0, %y1}",
10305 mask = eflags_p << 3;
10306 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10307 mask |= unordered_p << 1;
10308 mask |= stack_top_dies;
10310 gcc_assert (mask < 16);
10319 ix86_output_addr_vec_elt (FILE *file, int value)
10321 const char *directive = ASM_LONG;
10325 directive = ASM_QUAD;
10327 gcc_assert (!TARGET_64BIT);
10330 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10334 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10336 const char *directive = ASM_LONG;
10339 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10340 directive = ASM_QUAD;
10342 gcc_assert (!TARGET_64BIT);
10344 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10345 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10346 fprintf (file, "%s%s%d-%s%d\n",
10347 directive, LPREFIX, value, LPREFIX, rel);
10348 else if (HAVE_AS_GOTOFF_IN_DATA)
10349 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10351 else if (TARGET_MACHO)
10353 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10354 machopic_output_function_base_name (file);
10355 fprintf(file, "\n");
10359 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10360 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10363 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10367 ix86_expand_clear (rtx dest)
10371 /* We play register width games, which are only valid after reload. */
10372 gcc_assert (reload_completed);
10374 /* Avoid HImode and its attendant prefix byte. */
10375 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10376 dest = gen_rtx_REG (SImode, REGNO (dest));
10377 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10379 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10380 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10382 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10383 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10389 /* X is an unchanging MEM. If it is a constant pool reference, return
10390 the constant pool rtx, else NULL. */
10393 maybe_get_pool_constant (rtx x)
10395 x = ix86_delegitimize_address (XEXP (x, 0));
10397 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10398 return get_pool_constant (x);
10404 ix86_expand_move (enum machine_mode mode, rtx operands[])
10407 enum tls_model model;
10412 if (GET_CODE (op1) == SYMBOL_REF)
10414 model = SYMBOL_REF_TLS_MODEL (op1);
10417 op1 = legitimize_tls_address (op1, model, true);
10418 op1 = force_operand (op1, op0);
10422 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10423 && SYMBOL_REF_DLLIMPORT_P (op1))
10424 op1 = legitimize_dllimport_symbol (op1, false);
10426 else if (GET_CODE (op1) == CONST
10427 && GET_CODE (XEXP (op1, 0)) == PLUS
10428 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10430 rtx addend = XEXP (XEXP (op1, 0), 1);
10431 rtx symbol = XEXP (XEXP (op1, 0), 0);
10434 model = SYMBOL_REF_TLS_MODEL (symbol);
10436 tmp = legitimize_tls_address (symbol, model, true);
10437 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10438 && SYMBOL_REF_DLLIMPORT_P (symbol))
10439 tmp = legitimize_dllimport_symbol (symbol, true);
10443 tmp = force_operand (tmp, NULL);
10444 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10445 op0, 1, OPTAB_DIRECT);
10451 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10453 if (TARGET_MACHO && !TARGET_64BIT)
10458 rtx temp = ((reload_in_progress
10459 || ((op0 && REG_P (op0))
10461 ? op0 : gen_reg_rtx (Pmode));
10462 op1 = machopic_indirect_data_reference (op1, temp);
10463 op1 = machopic_legitimize_pic_address (op1, mode,
10464 temp == op1 ? 0 : temp);
10466 else if (MACHOPIC_INDIRECT)
10467 op1 = machopic_indirect_data_reference (op1, 0);
10475 op1 = force_reg (Pmode, op1);
10476 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10478 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10479 op1 = legitimize_pic_address (op1, reg);
10488 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10489 || !push_operand (op0, mode))
10491 op1 = force_reg (mode, op1);
10493 if (push_operand (op0, mode)
10494 && ! general_no_elim_operand (op1, mode))
10495 op1 = copy_to_mode_reg (mode, op1);
10497 /* Force large constants in 64bit compilation into register
10498 to get them CSEed. */
10499 if (can_create_pseudo_p ()
10500 && (mode == DImode) && TARGET_64BIT
10501 && immediate_operand (op1, mode)
10502 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10503 && !register_operand (op0, mode)
10505 op1 = copy_to_mode_reg (mode, op1);
10507 if (can_create_pseudo_p ()
10508 && FLOAT_MODE_P (mode)
10509 && GET_CODE (op1) == CONST_DOUBLE)
10511 /* If we are loading a floating point constant to a register,
10512 force the value to memory now, since we'll get better code
10513 out the back end. */
10515 op1 = validize_mem (force_const_mem (mode, op1));
10516 if (!register_operand (op0, mode))
10518 rtx temp = gen_reg_rtx (mode);
10519 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10520 emit_move_insn (op0, temp);
10526 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10530 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10532 rtx op0 = operands[0], op1 = operands[1];
10533 unsigned int align = GET_MODE_ALIGNMENT (mode);
10535 /* Force constants other than zero into memory. We do not know how
10536 the instructions used to build constants modify the upper 64 bits
10537 of the register, once we have that information we may be able
10538 to handle some of them more efficiently. */
10539 if (can_create_pseudo_p ()
10540 && register_operand (op0, mode)
10541 && (CONSTANT_P (op1)
10542 || (GET_CODE (op1) == SUBREG
10543 && CONSTANT_P (SUBREG_REG (op1))))
10544 && standard_sse_constant_p (op1) <= 0)
10545 op1 = validize_mem (force_const_mem (mode, op1));
10547 /* We need to check memory alignment for SSE mode since attribute
10548 can make operands unaligned. */
10549 if (can_create_pseudo_p ()
10550 && SSE_REG_MODE_P (mode)
10551 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10552 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10556 /* ix86_expand_vector_move_misalign() does not like constants ... */
10557 if (CONSTANT_P (op1)
10558 || (GET_CODE (op1) == SUBREG
10559 && CONSTANT_P (SUBREG_REG (op1))))
10560 op1 = validize_mem (force_const_mem (mode, op1));
10562 /* ... nor both arguments in memory. */
10563 if (!register_operand (op0, mode)
10564 && !register_operand (op1, mode))
10565 op1 = force_reg (mode, op1);
10567 tmp[0] = op0; tmp[1] = op1;
10568 ix86_expand_vector_move_misalign (mode, tmp);
10572 /* Make operand1 a register if it isn't already. */
10573 if (can_create_pseudo_p ()
10574 && !register_operand (op0, mode)
10575 && !register_operand (op1, mode))
10577 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10581 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10584 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10585 straight to ix86_expand_vector_move. */
10586 /* Code generation for scalar reg-reg moves of single and double precision data:
10587 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10591 if (x86_sse_partial_reg_dependency == true)
10596 Code generation for scalar loads of double precision data:
10597 if (x86_sse_split_regs == true)
10598 movlpd mem, reg (gas syntax)
10602 Code generation for unaligned packed loads of single precision data
10603 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10604 if (x86_sse_unaligned_move_optimal)
10607 if (x86_sse_partial_reg_dependency == true)
10619 Code generation for unaligned packed loads of double precision data
10620 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10621 if (x86_sse_unaligned_move_optimal)
10624 if (x86_sse_split_regs == true)
10637 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10646 /* If we're optimizing for size, movups is the smallest. */
10649 op0 = gen_lowpart (V4SFmode, op0);
10650 op1 = gen_lowpart (V4SFmode, op1);
10651 emit_insn (gen_sse_movups (op0, op1));
10655 /* ??? If we have typed data, then it would appear that using
10656 movdqu is the only way to get unaligned data loaded with
10658 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10660 op0 = gen_lowpart (V16QImode, op0);
10661 op1 = gen_lowpart (V16QImode, op1);
10662 emit_insn (gen_sse2_movdqu (op0, op1));
10666 if (TARGET_SSE2 && mode == V2DFmode)
10670 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10672 op0 = gen_lowpart (V2DFmode, op0);
10673 op1 = gen_lowpart (V2DFmode, op1);
10674 emit_insn (gen_sse2_movupd (op0, op1));
10678 /* When SSE registers are split into halves, we can avoid
10679 writing to the top half twice. */
10680 if (TARGET_SSE_SPLIT_REGS)
10682 emit_clobber (op0);
10687 /* ??? Not sure about the best option for the Intel chips.
10688 The following would seem to satisfy; the register is
10689 entirely cleared, breaking the dependency chain. We
10690 then store to the upper half, with a dependency depth
10691 of one. A rumor has it that Intel recommends two movsd
10692 followed by an unpacklpd, but this is unconfirmed. And
10693 given that the dependency depth of the unpacklpd would
10694 still be one, I'm not sure why this would be better. */
10695 zero = CONST0_RTX (V2DFmode);
10698 m = adjust_address (op1, DFmode, 0);
10699 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10700 m = adjust_address (op1, DFmode, 8);
10701 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10705 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10707 op0 = gen_lowpart (V4SFmode, op0);
10708 op1 = gen_lowpart (V4SFmode, op1);
10709 emit_insn (gen_sse_movups (op0, op1));
10713 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10714 emit_move_insn (op0, CONST0_RTX (mode));
10716 emit_clobber (op0);
10718 if (mode != V4SFmode)
10719 op0 = gen_lowpart (V4SFmode, op0);
10720 m = adjust_address (op1, V2SFmode, 0);
10721 emit_insn (gen_sse_loadlps (op0, op0, m));
10722 m = adjust_address (op1, V2SFmode, 8);
10723 emit_insn (gen_sse_loadhps (op0, op0, m));
10726 else if (MEM_P (op0))
10728 /* If we're optimizing for size, movups is the smallest. */
10731 op0 = gen_lowpart (V4SFmode, op0);
10732 op1 = gen_lowpart (V4SFmode, op1);
10733 emit_insn (gen_sse_movups (op0, op1));
10737 /* ??? Similar to above, only less clear because of quote
10738 typeless stores unquote. */
10739 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10740 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10742 op0 = gen_lowpart (V16QImode, op0);
10743 op1 = gen_lowpart (V16QImode, op1);
10744 emit_insn (gen_sse2_movdqu (op0, op1));
10748 if (TARGET_SSE2 && mode == V2DFmode)
10750 m = adjust_address (op0, DFmode, 0);
10751 emit_insn (gen_sse2_storelpd (m, op1));
10752 m = adjust_address (op0, DFmode, 8);
10753 emit_insn (gen_sse2_storehpd (m, op1));
10757 if (mode != V4SFmode)
10758 op1 = gen_lowpart (V4SFmode, op1);
10759 m = adjust_address (op0, V2SFmode, 0);
10760 emit_insn (gen_sse_storelps (m, op1));
10761 m = adjust_address (op0, V2SFmode, 8);
10762 emit_insn (gen_sse_storehps (m, op1));
10766 gcc_unreachable ();
10769 /* Expand a push in MODE. This is some mode for which we do not support
10770 proper push instructions, at least from the registers that we expect
10771 the value to live in. */
10774 ix86_expand_push (enum machine_mode mode, rtx x)
10778 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10779 GEN_INT (-GET_MODE_SIZE (mode)),
10780 stack_pointer_rtx, 1, OPTAB_DIRECT);
10781 if (tmp != stack_pointer_rtx)
10782 emit_move_insn (stack_pointer_rtx, tmp);
10784 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10785 emit_move_insn (tmp, x);
10788 /* Helper function of ix86_fixup_binary_operands to canonicalize
10789 operand order. Returns true if the operands should be swapped. */
10792 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10795 rtx dst = operands[0];
10796 rtx src1 = operands[1];
10797 rtx src2 = operands[2];
10799 /* If the operation is not commutative, we can't do anything. */
10800 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10803 /* Highest priority is that src1 should match dst. */
10804 if (rtx_equal_p (dst, src1))
10806 if (rtx_equal_p (dst, src2))
10809 /* Next highest priority is that immediate constants come second. */
10810 if (immediate_operand (src2, mode))
10812 if (immediate_operand (src1, mode))
10815 /* Lowest priority is that memory references should come second. */
10825 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10826 destination to use for the operation. If different from the true
10827 destination in operands[0], a copy operation will be required. */
10830 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10833 rtx dst = operands[0];
10834 rtx src1 = operands[1];
10835 rtx src2 = operands[2];
10837 /* Canonicalize operand order. */
10838 if (ix86_swap_binary_operands_p (code, mode, operands))
10842 /* It is invalid to swap operands of different modes. */
10843 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
10850 /* Both source operands cannot be in memory. */
10851 if (MEM_P (src1) && MEM_P (src2))
10853 /* Optimization: Only read from memory once. */
10854 if (rtx_equal_p (src1, src2))
10856 src2 = force_reg (mode, src2);
10860 src2 = force_reg (mode, src2);
10863 /* If the destination is memory, and we do not have matching source
10864 operands, do things in registers. */
10865 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10866 dst = gen_reg_rtx (mode);
10868 /* Source 1 cannot be a constant. */
10869 if (CONSTANT_P (src1))
10870 src1 = force_reg (mode, src1);
10872 /* Source 1 cannot be a non-matching memory. */
10873 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10874 src1 = force_reg (mode, src1);
10876 operands[1] = src1;
10877 operands[2] = src2;
10881 /* Similarly, but assume that the destination has already been
10882 set up properly. */
10885 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10886 enum machine_mode mode, rtx operands[])
10888 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10889 gcc_assert (dst == operands[0]);
10892 /* Attempt to expand a binary operator. Make the expansion closer to the
10893 actual machine, then just general_operand, which will allow 3 separate
10894 memory references (one output, two input) in a single insn. */
10897 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10900 rtx src1, src2, dst, op, clob;
10902 dst = ix86_fixup_binary_operands (code, mode, operands);
10903 src1 = operands[1];
10904 src2 = operands[2];
10906 /* Emit the instruction. */
10908 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10909 if (reload_in_progress)
10911 /* Reload doesn't know about the flags register, and doesn't know that
10912 it doesn't want to clobber it. We can only do this with PLUS. */
10913 gcc_assert (code == PLUS);
10918 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10919 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10922 /* Fix up the destination if needed. */
10923 if (dst != operands[0])
10924 emit_move_insn (operands[0], dst);
10927 /* Return TRUE or FALSE depending on whether the binary operator meets the
10928 appropriate constraints. */
10931 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10934 rtx dst = operands[0];
10935 rtx src1 = operands[1];
10936 rtx src2 = operands[2];
10938 /* Both source operands cannot be in memory. */
10939 if (MEM_P (src1) && MEM_P (src2))
10942 /* Canonicalize operand order for commutative operators. */
10943 if (ix86_swap_binary_operands_p (code, mode, operands))
10950 /* If the destination is memory, we must have a matching source operand. */
10951 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10954 /* Source 1 cannot be a constant. */
10955 if (CONSTANT_P (src1))
10958 /* Source 1 cannot be a non-matching memory. */
10959 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10965 /* Attempt to expand a unary operator. Make the expansion closer to the
10966 actual machine, then just general_operand, which will allow 2 separate
10967 memory references (one output, one input) in a single insn. */
10970 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10973 int matching_memory;
10974 rtx src, dst, op, clob;
10979 /* If the destination is memory, and we do not have matching source
10980 operands, do things in registers. */
10981 matching_memory = 0;
10984 if (rtx_equal_p (dst, src))
10985 matching_memory = 1;
10987 dst = gen_reg_rtx (mode);
10990 /* When source operand is memory, destination must match. */
10991 if (MEM_P (src) && !matching_memory)
10992 src = force_reg (mode, src);
10994 /* Emit the instruction. */
10996 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10997 if (reload_in_progress || code == NOT)
10999 /* Reload doesn't know about the flags register, and doesn't know that
11000 it doesn't want to clobber it. */
11001 gcc_assert (code == NOT);
11006 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11007 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
11010 /* Fix up the destination if needed. */
11011 if (dst != operands[0])
11012 emit_move_insn (operands[0], dst);
11015 /* Return TRUE or FALSE depending on whether the unary operator meets the
11016 appropriate constraints. */
11019 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
11020 enum machine_mode mode ATTRIBUTE_UNUSED,
11021 rtx operands[2] ATTRIBUTE_UNUSED)
11023 /* If one of operands is memory, source and destination must match. */
11024 if ((MEM_P (operands[0])
11025 || MEM_P (operands[1]))
11026 && ! rtx_equal_p (operands[0], operands[1]))
11031 /* Post-reload splitter for converting an SF or DFmode value in an
11032 SSE register into an unsigned SImode. */
11035 ix86_split_convert_uns_si_sse (rtx operands[])
11037 enum machine_mode vecmode;
11038 rtx value, large, zero_or_two31, input, two31, x;
11040 large = operands[1];
11041 zero_or_two31 = operands[2];
11042 input = operands[3];
11043 two31 = operands[4];
11044 vecmode = GET_MODE (large);
11045 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
11047 /* Load up the value into the low element. We must ensure that the other
11048 elements are valid floats -- zero is the easiest such value. */
11051 if (vecmode == V4SFmode)
11052 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
11054 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
11058 input = gen_rtx_REG (vecmode, REGNO (input));
11059 emit_move_insn (value, CONST0_RTX (vecmode));
11060 if (vecmode == V4SFmode)
11061 emit_insn (gen_sse_movss (value, value, input));
11063 emit_insn (gen_sse2_movsd (value, value, input));
11066 emit_move_insn (large, two31);
11067 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
11069 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
11070 emit_insn (gen_rtx_SET (VOIDmode, large, x));
11072 x = gen_rtx_AND (vecmode, zero_or_two31, large);
11073 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
11075 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
11076 emit_insn (gen_rtx_SET (VOIDmode, value, x));
11078 large = gen_rtx_REG (V4SImode, REGNO (large));
11079 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
11081 x = gen_rtx_REG (V4SImode, REGNO (value));
11082 if (vecmode == V4SFmode)
11083 emit_insn (gen_sse2_cvttps2dq (x, value));
11085 emit_insn (gen_sse2_cvttpd2dq (x, value));
11088 emit_insn (gen_xorv4si3 (value, value, large));
11091 /* Convert an unsigned DImode value into a DFmode, using only SSE.
11092 Expects the 64-bit DImode to be supplied in a pair of integral
11093 registers. Requires SSE2; will use SSE3 if available. For x86_32,
11094 -mfpmath=sse, !optimize_size only. */
11097 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
11099 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
11100 rtx int_xmm, fp_xmm;
11101 rtx biases, exponents;
11104 int_xmm = gen_reg_rtx (V4SImode);
11105 if (TARGET_INTER_UNIT_MOVES)
11106 emit_insn (gen_movdi_to_sse (int_xmm, input));
11107 else if (TARGET_SSE_SPLIT_REGS)
11109 emit_clobber (int_xmm);
11110 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
11114 x = gen_reg_rtx (V2DImode);
11115 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
11116 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
11119 x = gen_rtx_CONST_VECTOR (V4SImode,
11120 gen_rtvec (4, GEN_INT (0x43300000UL),
11121 GEN_INT (0x45300000UL),
11122 const0_rtx, const0_rtx));
11123 exponents = validize_mem (force_const_mem (V4SImode, x));
11125 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
11126 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
11128 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
11129 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
11130 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
11131 (0x1.0p84 + double(fp_value_hi_xmm)).
11132 Note these exponents differ by 32. */
11134 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
11136 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
11137 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
11138 real_ldexp (&bias_lo_rvt, &dconst1, 52);
11139 real_ldexp (&bias_hi_rvt, &dconst1, 84);
11140 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
11141 x = const_double_from_real_value (bias_hi_rvt, DFmode);
11142 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
11143 biases = validize_mem (force_const_mem (V2DFmode, biases));
11144 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
11146 /* Add the upper and lower DFmode values together. */
11148 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
11151 x = copy_to_mode_reg (V2DFmode, fp_xmm);
11152 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
11153 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
11156 ix86_expand_vector_extract (false, target, fp_xmm, 0);
11159 /* Not used, but eases macroization of patterns. */
11161 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
11162 rtx input ATTRIBUTE_UNUSED)
11164 gcc_unreachable ();
11167 /* Convert an unsigned SImode value into a DFmode. Only currently used
11168 for SSE, but applicable anywhere. */
11171 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
11173 REAL_VALUE_TYPE TWO31r;
11176 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
11177 NULL, 1, OPTAB_DIRECT);
11179 fp = gen_reg_rtx (DFmode);
11180 emit_insn (gen_floatsidf2 (fp, x));
11182 real_ldexp (&TWO31r, &dconst1, 31);
11183 x = const_double_from_real_value (TWO31r, DFmode);
11185 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
11187 emit_move_insn (target, x);
11190 /* Convert a signed DImode value into a DFmode. Only used for SSE in
11191 32-bit mode; otherwise we have a direct convert instruction. */
11194 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
11196 REAL_VALUE_TYPE TWO32r;
11197 rtx fp_lo, fp_hi, x;
11199 fp_lo = gen_reg_rtx (DFmode);
11200 fp_hi = gen_reg_rtx (DFmode);
11202 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
11204 real_ldexp (&TWO32r, &dconst1, 32);
11205 x = const_double_from_real_value (TWO32r, DFmode);
11206 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
11208 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
11210 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
11213 emit_move_insn (target, x);
11216 /* Convert an unsigned SImode value into a SFmode, using only SSE.
11217 For x86_32, -mfpmath=sse, !optimize_size only. */
11219 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
11221 REAL_VALUE_TYPE ONE16r;
11222 rtx fp_hi, fp_lo, int_hi, int_lo, x;
11224 real_ldexp (&ONE16r, &dconst1, 16);
11225 x = const_double_from_real_value (ONE16r, SFmode);
11226 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
11227 NULL, 0, OPTAB_DIRECT);
11228 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
11229 NULL, 0, OPTAB_DIRECT);
11230 fp_hi = gen_reg_rtx (SFmode);
11231 fp_lo = gen_reg_rtx (SFmode);
11232 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
11233 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
11234 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
11236 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
11238 if (!rtx_equal_p (target, fp_hi))
11239 emit_move_insn (target, fp_hi);
11242 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
11243 then replicate the value for all elements of the vector
11247 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
11254 v = gen_rtvec (4, value, value, value, value);
11255 return gen_rtx_CONST_VECTOR (V4SImode, v);
11259 v = gen_rtvec (2, value, value);
11260 return gen_rtx_CONST_VECTOR (V2DImode, v);
11264 v = gen_rtvec (4, value, value, value, value);
11266 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11267 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11268 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11272 v = gen_rtvec (2, value, value);
11274 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11275 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11278 gcc_unreachable ();
11282 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11283 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11284 for an SSE register. If VECT is true, then replicate the mask for
11285 all elements of the vector register. If INVERT is true, then create
11286 a mask excluding the sign bit. */
11289 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11291 enum machine_mode vec_mode, imode;
11292 HOST_WIDE_INT hi, lo;
11297 /* Find the sign bit, sign extended to 2*HWI. */
11303 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11304 lo = 0x80000000, hi = lo < 0;
11310 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11311 if (HOST_BITS_PER_WIDE_INT >= 64)
11312 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11314 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11320 vec_mode = VOIDmode;
11321 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11322 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11326 gcc_unreachable ();
11330 lo = ~lo, hi = ~hi;
11332 /* Force this value into the low part of a fp vector constant. */
11333 mask = immed_double_const (lo, hi, imode);
11334 mask = gen_lowpart (mode, mask);
11336 if (vec_mode == VOIDmode)
11337 return force_reg (mode, mask);
11339 v = ix86_build_const_vector (mode, vect, mask);
11340 return force_reg (vec_mode, v);
11343 /* Generate code for floating point ABS or NEG. */
11346 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11349 rtx mask, set, use, clob, dst, src;
11350 bool use_sse = false;
11351 bool vector_mode = VECTOR_MODE_P (mode);
11352 enum machine_mode elt_mode = mode;
11356 elt_mode = GET_MODE_INNER (mode);
11359 else if (mode == TFmode)
11361 else if (TARGET_SSE_MATH)
11362 use_sse = SSE_FLOAT_MODE_P (mode);
11364 /* NEG and ABS performed with SSE use bitwise mask operations.
11365 Create the appropriate mask now. */
11367 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11376 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11377 set = gen_rtx_SET (VOIDmode, dst, set);
11382 set = gen_rtx_fmt_e (code, mode, src);
11383 set = gen_rtx_SET (VOIDmode, dst, set);
11386 use = gen_rtx_USE (VOIDmode, mask);
11387 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11388 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11389 gen_rtvec (3, set, use, clob)));
11396 /* Expand a copysign operation. Special case operand 0 being a constant. */
11399 ix86_expand_copysign (rtx operands[])
11401 enum machine_mode mode;
11402 rtx dest, op0, op1, mask, nmask;
11404 dest = operands[0];
11408 mode = GET_MODE (dest);
11410 if (GET_CODE (op0) == CONST_DOUBLE)
11412 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11414 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11415 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11417 if (mode == SFmode || mode == DFmode)
11419 enum machine_mode vmode;
11421 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11423 if (op0 == CONST0_RTX (mode))
11424 op0 = CONST0_RTX (vmode);
11429 if (mode == SFmode)
11430 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11431 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11433 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11435 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11438 else if (op0 != CONST0_RTX (mode))
11439 op0 = force_reg (mode, op0);
11441 mask = ix86_build_signbit_mask (mode, 0, 0);
11443 if (mode == SFmode)
11444 copysign_insn = gen_copysignsf3_const;
11445 else if (mode == DFmode)
11446 copysign_insn = gen_copysigndf3_const;
11448 copysign_insn = gen_copysigntf3_const;
11450 emit_insn (copysign_insn (dest, op0, op1, mask));
11454 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11456 nmask = ix86_build_signbit_mask (mode, 0, 1);
11457 mask = ix86_build_signbit_mask (mode, 0, 0);
11459 if (mode == SFmode)
11460 copysign_insn = gen_copysignsf3_var;
11461 else if (mode == DFmode)
11462 copysign_insn = gen_copysigndf3_var;
11464 copysign_insn = gen_copysigntf3_var;
11466 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11470 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11471 be a constant, and so has already been expanded into a vector constant. */
11474 ix86_split_copysign_const (rtx operands[])
11476 enum machine_mode mode, vmode;
11477 rtx dest, op0, op1, mask, x;
11479 dest = operands[0];
11482 mask = operands[3];
11484 mode = GET_MODE (dest);
11485 vmode = GET_MODE (mask);
11487 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11488 x = gen_rtx_AND (vmode, dest, mask);
11489 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11491 if (op0 != CONST0_RTX (vmode))
11493 x = gen_rtx_IOR (vmode, dest, op0);
11494 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11498 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11499 so we have to do two masks. */
11502 ix86_split_copysign_var (rtx operands[])
11504 enum machine_mode mode, vmode;
11505 rtx dest, scratch, op0, op1, mask, nmask, x;
11507 dest = operands[0];
11508 scratch = operands[1];
11511 nmask = operands[4];
11512 mask = operands[5];
11514 mode = GET_MODE (dest);
11515 vmode = GET_MODE (mask);
11517 if (rtx_equal_p (op0, op1))
11519 /* Shouldn't happen often (it's useless, obviously), but when it does
11520 we'd generate incorrect code if we continue below. */
11521 emit_move_insn (dest, op0);
11525 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11527 gcc_assert (REGNO (op1) == REGNO (scratch));
11529 x = gen_rtx_AND (vmode, scratch, mask);
11530 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11533 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11534 x = gen_rtx_NOT (vmode, dest);
11535 x = gen_rtx_AND (vmode, x, op0);
11536 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11540 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11542 x = gen_rtx_AND (vmode, scratch, mask);
11544 else /* alternative 2,4 */
11546 gcc_assert (REGNO (mask) == REGNO (scratch));
11547 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11548 x = gen_rtx_AND (vmode, scratch, op1);
11550 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11552 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11554 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11555 x = gen_rtx_AND (vmode, dest, nmask);
11557 else /* alternative 3,4 */
11559 gcc_assert (REGNO (nmask) == REGNO (dest));
11561 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11562 x = gen_rtx_AND (vmode, dest, op0);
11564 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11567 x = gen_rtx_IOR (vmode, dest, scratch);
11568 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11571 /* Return TRUE or FALSE depending on whether the first SET in INSN
11572 has source and destination with matching CC modes, and that the
11573 CC mode is at least as constrained as REQ_MODE. */
11576 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11579 enum machine_mode set_mode;
11581 set = PATTERN (insn);
11582 if (GET_CODE (set) == PARALLEL)
11583 set = XVECEXP (set, 0, 0);
11584 gcc_assert (GET_CODE (set) == SET);
11585 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11587 set_mode = GET_MODE (SET_DEST (set));
11591 if (req_mode != CCNOmode
11592 && (req_mode != CCmode
11593 || XEXP (SET_SRC (set), 1) != const0_rtx))
11597 if (req_mode == CCGCmode)
11601 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11605 if (req_mode == CCZmode)
11612 gcc_unreachable ();
11615 return (GET_MODE (SET_SRC (set)) == set_mode);
11618 /* Generate insn patterns to do an integer compare of OPERANDS. */
11621 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11623 enum machine_mode cmpmode;
11626 cmpmode = SELECT_CC_MODE (code, op0, op1);
11627 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11629 /* This is very simple, but making the interface the same as in the
11630 FP case makes the rest of the code easier. */
11631 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11632 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11634 /* Return the test that should be put into the flags user, i.e.
11635 the bcc, scc, or cmov instruction. */
11636 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11639 /* Figure out whether to use ordered or unordered fp comparisons.
11640 Return the appropriate mode to use. */
11643 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11645 /* ??? In order to make all comparisons reversible, we do all comparisons
11646 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11647 all forms trapping and nontrapping comparisons, we can make inequality
11648 comparisons trapping again, since it results in better code when using
11649 FCOM based compares. */
11650 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11654 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11656 enum machine_mode mode = GET_MODE (op0);
11658 if (SCALAR_FLOAT_MODE_P (mode))
11660 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11661 return ix86_fp_compare_mode (code);
11666 /* Only zero flag is needed. */
11667 case EQ: /* ZF=0 */
11668 case NE: /* ZF!=0 */
11670 /* Codes needing carry flag. */
11671 case GEU: /* CF=0 */
11672 case LTU: /* CF=1 */
11673 /* Detect overflow checks. They need just the carry flag. */
11674 if (GET_CODE (op0) == PLUS
11675 && rtx_equal_p (op1, XEXP (op0, 0)))
11679 case GTU: /* CF=0 & ZF=0 */
11680 case LEU: /* CF=1 | ZF=1 */
11681 /* Detect overflow checks. They need just the carry flag. */
11682 if (GET_CODE (op0) == MINUS
11683 && rtx_equal_p (op1, XEXP (op0, 0)))
11687 /* Codes possibly doable only with sign flag when
11688 comparing against zero. */
11689 case GE: /* SF=OF or SF=0 */
11690 case LT: /* SF<>OF or SF=1 */
11691 if (op1 == const0_rtx)
11694 /* For other cases Carry flag is not required. */
11696 /* Codes doable only with sign flag when comparing
11697 against zero, but we miss jump instruction for it
11698 so we need to use relational tests against overflow
11699 that thus needs to be zero. */
11700 case GT: /* ZF=0 & SF=OF */
11701 case LE: /* ZF=1 | SF<>OF */
11702 if (op1 == const0_rtx)
11706 /* strcmp pattern do (use flags) and combine may ask us for proper
11711 gcc_unreachable ();
11715 /* Return the fixed registers used for condition codes. */
11718 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11725 /* If two condition code modes are compatible, return a condition code
11726 mode which is compatible with both. Otherwise, return
11729 static enum machine_mode
11730 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11735 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11738 if ((m1 == CCGCmode && m2 == CCGOCmode)
11739 || (m1 == CCGOCmode && m2 == CCGCmode))
11745 gcc_unreachable ();
11775 /* These are only compatible with themselves, which we already
11781 /* Split comparison code CODE into comparisons we can do using branch
11782 instructions. BYPASS_CODE is comparison code for branch that will
11783 branch around FIRST_CODE and SECOND_CODE. If some of branches
11784 is not required, set value to UNKNOWN.
11785 We never require more than two branches. */
11788 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11789 enum rtx_code *first_code,
11790 enum rtx_code *second_code)
11792 *first_code = code;
11793 *bypass_code = UNKNOWN;
11794 *second_code = UNKNOWN;
11796 /* The fcomi comparison sets flags as follows:
11806 case GT: /* GTU - CF=0 & ZF=0 */
11807 case GE: /* GEU - CF=0 */
11808 case ORDERED: /* PF=0 */
11809 case UNORDERED: /* PF=1 */
11810 case UNEQ: /* EQ - ZF=1 */
11811 case UNLT: /* LTU - CF=1 */
11812 case UNLE: /* LEU - CF=1 | ZF=1 */
11813 case LTGT: /* EQ - ZF=0 */
11815 case LT: /* LTU - CF=1 - fails on unordered */
11816 *first_code = UNLT;
11817 *bypass_code = UNORDERED;
11819 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11820 *first_code = UNLE;
11821 *bypass_code = UNORDERED;
11823 case EQ: /* EQ - ZF=1 - fails on unordered */
11824 *first_code = UNEQ;
11825 *bypass_code = UNORDERED;
11827 case NE: /* NE - ZF=0 - fails on unordered */
11828 *first_code = LTGT;
11829 *second_code = UNORDERED;
11831 case UNGE: /* GEU - CF=0 - fails on unordered */
11833 *second_code = UNORDERED;
11835 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11837 *second_code = UNORDERED;
11840 gcc_unreachable ();
11842 if (!TARGET_IEEE_FP)
11844 *second_code = UNKNOWN;
11845 *bypass_code = UNKNOWN;
11849 /* Return cost of comparison done fcom + arithmetics operations on AX.
11850 All following functions do use number of instructions as a cost metrics.
11851 In future this should be tweaked to compute bytes for optimize_size and
11852 take into account performance of various instructions on various CPUs. */
11854 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11856 if (!TARGET_IEEE_FP)
11858 /* The cost of code output by ix86_expand_fp_compare. */
11882 gcc_unreachable ();
11886 /* Return cost of comparison done using fcomi operation.
11887 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11889 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11891 enum rtx_code bypass_code, first_code, second_code;
11892 /* Return arbitrarily high cost when instruction is not supported - this
11893 prevents gcc from using it. */
11896 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11897 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11900 /* Return cost of comparison done using sahf operation.
11901 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11903 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11905 enum rtx_code bypass_code, first_code, second_code;
11906 /* Return arbitrarily high cost when instruction is not preferred - this
11907 avoids gcc from using it. */
11908 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11910 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11911 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11914 /* Compute cost of the comparison done using any method.
11915 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11917 ix86_fp_comparison_cost (enum rtx_code code)
11919 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11922 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11923 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11925 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11926 if (min > sahf_cost)
11928 if (min > fcomi_cost)
11933 /* Return true if we should use an FCOMI instruction for this
11937 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11939 enum rtx_code swapped_code = swap_condition (code);
11941 return ((ix86_fp_comparison_cost (code)
11942 == ix86_fp_comparison_fcomi_cost (code))
11943 || (ix86_fp_comparison_cost (swapped_code)
11944 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11947 /* Swap, force into registers, or otherwise massage the two operands
11948 to a fp comparison. The operands are updated in place; the new
11949 comparison code is returned. */
11951 static enum rtx_code
11952 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11954 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11955 rtx op0 = *pop0, op1 = *pop1;
11956 enum machine_mode op_mode = GET_MODE (op0);
11957 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11959 /* All of the unordered compare instructions only work on registers.
11960 The same is true of the fcomi compare instructions. The XFmode
11961 compare instructions require registers except when comparing
11962 against zero or when converting operand 1 from fixed point to
11966 && (fpcmp_mode == CCFPUmode
11967 || (op_mode == XFmode
11968 && ! (standard_80387_constant_p (op0) == 1
11969 || standard_80387_constant_p (op1) == 1)
11970 && GET_CODE (op1) != FLOAT)
11971 || ix86_use_fcomi_compare (code)))
11973 op0 = force_reg (op_mode, op0);
11974 op1 = force_reg (op_mode, op1);
11978 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11979 things around if they appear profitable, otherwise force op0
11980 into a register. */
11982 if (standard_80387_constant_p (op0) == 0
11984 && ! (standard_80387_constant_p (op1) == 0
11988 tmp = op0, op0 = op1, op1 = tmp;
11989 code = swap_condition (code);
11993 op0 = force_reg (op_mode, op0);
11995 if (CONSTANT_P (op1))
11997 int tmp = standard_80387_constant_p (op1);
11999 op1 = validize_mem (force_const_mem (op_mode, op1));
12003 op1 = force_reg (op_mode, op1);
12006 op1 = force_reg (op_mode, op1);
12010 /* Try to rearrange the comparison to make it cheaper. */
12011 if (ix86_fp_comparison_cost (code)
12012 > ix86_fp_comparison_cost (swap_condition (code))
12013 && (REG_P (op1) || can_create_pseudo_p ()))
12016 tmp = op0, op0 = op1, op1 = tmp;
12017 code = swap_condition (code);
12019 op0 = force_reg (op_mode, op0);
12027 /* Convert comparison codes we use to represent FP comparison to integer
12028 code that will result in proper branch. Return UNKNOWN if no such code
12032 ix86_fp_compare_code_to_integer (enum rtx_code code)
12061 /* Generate insn patterns to do a floating point compare of OPERANDS. */
12064 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
12065 rtx *second_test, rtx *bypass_test)
12067 enum machine_mode fpcmp_mode, intcmp_mode;
12069 int cost = ix86_fp_comparison_cost (code);
12070 enum rtx_code bypass_code, first_code, second_code;
12072 fpcmp_mode = ix86_fp_compare_mode (code);
12073 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
12076 *second_test = NULL_RTX;
12078 *bypass_test = NULL_RTX;
12080 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12082 /* Do fcomi/sahf based test when profitable. */
12083 if (ix86_fp_comparison_arithmetics_cost (code) > cost
12084 && (bypass_code == UNKNOWN || bypass_test)
12085 && (second_code == UNKNOWN || second_test))
12087 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
12088 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
12094 gcc_assert (TARGET_SAHF);
12097 scratch = gen_reg_rtx (HImode);
12098 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
12100 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
12103 /* The FP codes work out to act like unsigned. */
12104 intcmp_mode = fpcmp_mode;
12106 if (bypass_code != UNKNOWN)
12107 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
12108 gen_rtx_REG (intcmp_mode, FLAGS_REG),
12110 if (second_code != UNKNOWN)
12111 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
12112 gen_rtx_REG (intcmp_mode, FLAGS_REG),
12117 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
12118 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
12119 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
12121 scratch = gen_reg_rtx (HImode);
12122 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
12124 /* In the unordered case, we have to check C2 for NaN's, which
12125 doesn't happen to work out to anything nice combination-wise.
12126 So do some bit twiddling on the value we've got in AH to come
12127 up with an appropriate set of condition codes. */
12129 intcmp_mode = CCNOmode;
12134 if (code == GT || !TARGET_IEEE_FP)
12136 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
12141 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12142 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
12143 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
12144 intcmp_mode = CCmode;
12150 if (code == LT && TARGET_IEEE_FP)
12152 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12153 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
12154 intcmp_mode = CCmode;
12159 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
12165 if (code == GE || !TARGET_IEEE_FP)
12167 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
12172 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12173 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12180 if (code == LE && TARGET_IEEE_FP)
12182 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12183 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
12184 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12185 intcmp_mode = CCmode;
12190 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
12196 if (code == EQ && TARGET_IEEE_FP)
12198 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12199 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12200 intcmp_mode = CCmode;
12205 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12212 if (code == NE && TARGET_IEEE_FP)
12214 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12215 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12221 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12227 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12231 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12236 gcc_unreachable ();
12240 /* Return the test that should be put into the flags user, i.e.
12241 the bcc, scc, or cmov instruction. */
12242 return gen_rtx_fmt_ee (code, VOIDmode,
12243 gen_rtx_REG (intcmp_mode, FLAGS_REG),
12248 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
12251 op0 = ix86_compare_op0;
12252 op1 = ix86_compare_op1;
12255 *second_test = NULL_RTX;
12257 *bypass_test = NULL_RTX;
12259 if (ix86_compare_emitted)
12261 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
12262 ix86_compare_emitted = NULL_RTX;
12264 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
12266 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12267 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12268 second_test, bypass_test);
12271 ret = ix86_expand_int_compare (code, op0, op1);
12276 /* Return true if the CODE will result in nontrivial jump sequence. */
12278 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12280 enum rtx_code bypass_code, first_code, second_code;
12283 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12284 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12288 ix86_expand_branch (enum rtx_code code, rtx label)
12292 /* If we have emitted a compare insn, go straight to simple.
12293 ix86_expand_compare won't emit anything if ix86_compare_emitted
12295 if (ix86_compare_emitted)
12298 switch (GET_MODE (ix86_compare_op0))
12304 tmp = ix86_expand_compare (code, NULL, NULL);
12305 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12306 gen_rtx_LABEL_REF (VOIDmode, label),
12308 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12317 enum rtx_code bypass_code, first_code, second_code;
12319 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12320 &ix86_compare_op1);
12322 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12324 /* Check whether we will use the natural sequence with one jump. If
12325 so, we can expand jump early. Otherwise delay expansion by
12326 creating compound insn to not confuse optimizers. */
12327 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12329 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12330 gen_rtx_LABEL_REF (VOIDmode, label),
12331 pc_rtx, NULL_RTX, NULL_RTX);
12335 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12336 ix86_compare_op0, ix86_compare_op1);
12337 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12338 gen_rtx_LABEL_REF (VOIDmode, label),
12340 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12342 use_fcomi = ix86_use_fcomi_compare (code);
12343 vec = rtvec_alloc (3 + !use_fcomi);
12344 RTVEC_ELT (vec, 0) = tmp;
12346 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12348 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12351 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12353 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12362 /* Expand DImode branch into multiple compare+branch. */
12364 rtx lo[2], hi[2], label2;
12365 enum rtx_code code1, code2, code3;
12366 enum machine_mode submode;
12368 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12370 tmp = ix86_compare_op0;
12371 ix86_compare_op0 = ix86_compare_op1;
12372 ix86_compare_op1 = tmp;
12373 code = swap_condition (code);
12375 if (GET_MODE (ix86_compare_op0) == DImode)
12377 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12378 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12383 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12384 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12388 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12389 avoid two branches. This costs one extra insn, so disable when
12390 optimizing for size. */
12392 if ((code == EQ || code == NE)
12394 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12399 if (hi[1] != const0_rtx)
12400 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12401 NULL_RTX, 0, OPTAB_WIDEN);
12404 if (lo[1] != const0_rtx)
12405 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12406 NULL_RTX, 0, OPTAB_WIDEN);
12408 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12409 NULL_RTX, 0, OPTAB_WIDEN);
12411 ix86_compare_op0 = tmp;
12412 ix86_compare_op1 = const0_rtx;
12413 ix86_expand_branch (code, label);
12417 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12418 op1 is a constant and the low word is zero, then we can just
12419 examine the high word. Similarly for low word -1 and
12420 less-or-equal-than or greater-than. */
12422 if (CONST_INT_P (hi[1]))
12425 case LT: case LTU: case GE: case GEU:
12426 if (lo[1] == const0_rtx)
12428 ix86_compare_op0 = hi[0];
12429 ix86_compare_op1 = hi[1];
12430 ix86_expand_branch (code, label);
12434 case LE: case LEU: case GT: case GTU:
12435 if (lo[1] == constm1_rtx)
12437 ix86_compare_op0 = hi[0];
12438 ix86_compare_op1 = hi[1];
12439 ix86_expand_branch (code, label);
12447 /* Otherwise, we need two or three jumps. */
12449 label2 = gen_label_rtx ();
12452 code2 = swap_condition (code);
12453 code3 = unsigned_condition (code);
12457 case LT: case GT: case LTU: case GTU:
12460 case LE: code1 = LT; code2 = GT; break;
12461 case GE: code1 = GT; code2 = LT; break;
12462 case LEU: code1 = LTU; code2 = GTU; break;
12463 case GEU: code1 = GTU; code2 = LTU; break;
12465 case EQ: code1 = UNKNOWN; code2 = NE; break;
12466 case NE: code2 = UNKNOWN; break;
12469 gcc_unreachable ();
12474 * if (hi(a) < hi(b)) goto true;
12475 * if (hi(a) > hi(b)) goto false;
12476 * if (lo(a) < lo(b)) goto true;
12480 ix86_compare_op0 = hi[0];
12481 ix86_compare_op1 = hi[1];
12483 if (code1 != UNKNOWN)
12484 ix86_expand_branch (code1, label);
12485 if (code2 != UNKNOWN)
12486 ix86_expand_branch (code2, label2);
12488 ix86_compare_op0 = lo[0];
12489 ix86_compare_op1 = lo[1];
12490 ix86_expand_branch (code3, label);
12492 if (code2 != UNKNOWN)
12493 emit_label (label2);
12498 gcc_unreachable ();
12502 /* Split branch based on floating point condition. */
12504 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12505 rtx target1, rtx target2, rtx tmp, rtx pushed)
12507 rtx second, bypass;
12508 rtx label = NULL_RTX;
12510 int bypass_probability = -1, second_probability = -1, probability = -1;
12513 if (target2 != pc_rtx)
12516 code = reverse_condition_maybe_unordered (code);
12521 condition = ix86_expand_fp_compare (code, op1, op2,
12522 tmp, &second, &bypass);
12524 /* Remove pushed operand from stack. */
12526 ix86_free_from_memory (GET_MODE (pushed));
12528 if (split_branch_probability >= 0)
12530 /* Distribute the probabilities across the jumps.
12531 Assume the BYPASS and SECOND to be always test
12533 probability = split_branch_probability;
12535 /* Value of 1 is low enough to make no need for probability
12536 to be updated. Later we may run some experiments and see
12537 if unordered values are more frequent in practice. */
12539 bypass_probability = 1;
12541 second_probability = 1;
12543 if (bypass != NULL_RTX)
12545 label = gen_label_rtx ();
12546 i = emit_jump_insn (gen_rtx_SET
12548 gen_rtx_IF_THEN_ELSE (VOIDmode,
12550 gen_rtx_LABEL_REF (VOIDmode,
12553 if (bypass_probability >= 0)
12555 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12556 GEN_INT (bypass_probability),
12559 i = emit_jump_insn (gen_rtx_SET
12561 gen_rtx_IF_THEN_ELSE (VOIDmode,
12562 condition, target1, target2)));
12563 if (probability >= 0)
12565 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12566 GEN_INT (probability),
12568 if (second != NULL_RTX)
12570 i = emit_jump_insn (gen_rtx_SET
12572 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12574 if (second_probability >= 0)
12576 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12577 GEN_INT (second_probability),
12580 if (label != NULL_RTX)
12581 emit_label (label);
12585 ix86_expand_setcc (enum rtx_code code, rtx dest)
12587 rtx ret, tmp, tmpreg, equiv;
12588 rtx second_test, bypass_test;
12590 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12591 return 0; /* FAIL */
12593 gcc_assert (GET_MODE (dest) == QImode);
12595 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12596 PUT_MODE (ret, QImode);
12601 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12602 if (bypass_test || second_test)
12604 rtx test = second_test;
12606 rtx tmp2 = gen_reg_rtx (QImode);
12609 gcc_assert (!second_test);
12610 test = bypass_test;
12612 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12614 PUT_MODE (test, QImode);
12615 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12618 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12620 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12623 /* Attach a REG_EQUAL note describing the comparison result. */
12624 if (ix86_compare_op0 && ix86_compare_op1)
12626 equiv = simplify_gen_relational (code, QImode,
12627 GET_MODE (ix86_compare_op0),
12628 ix86_compare_op0, ix86_compare_op1);
12629 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12632 return 1; /* DONE */
12635 /* Expand comparison setting or clearing carry flag. Return true when
12636 successful and set pop for the operation. */
12638 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12640 enum machine_mode mode =
12641 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12643 /* Do not handle DImode compares that go through special path. */
12644 if (mode == (TARGET_64BIT ? TImode : DImode))
12647 if (SCALAR_FLOAT_MODE_P (mode))
12649 rtx second_test = NULL, bypass_test = NULL;
12650 rtx compare_op, compare_seq;
12652 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12654 /* Shortcut: following common codes never translate
12655 into carry flag compares. */
12656 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12657 || code == ORDERED || code == UNORDERED)
12660 /* These comparisons require zero flag; swap operands so they won't. */
12661 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12662 && !TARGET_IEEE_FP)
12667 code = swap_condition (code);
12670 /* Try to expand the comparison and verify that we end up with
12671 carry flag based comparison. This fails to be true only when
12672 we decide to expand comparison using arithmetic that is not
12673 too common scenario. */
12675 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12676 &second_test, &bypass_test);
12677 compare_seq = get_insns ();
12680 if (second_test || bypass_test)
12683 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12684 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12685 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12687 code = GET_CODE (compare_op);
12689 if (code != LTU && code != GEU)
12692 emit_insn (compare_seq);
12697 if (!INTEGRAL_MODE_P (mode))
12706 /* Convert a==0 into (unsigned)a<1. */
12709 if (op1 != const0_rtx)
12712 code = (code == EQ ? LTU : GEU);
12715 /* Convert a>b into b<a or a>=b-1. */
12718 if (CONST_INT_P (op1))
12720 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12721 /* Bail out on overflow. We still can swap operands but that
12722 would force loading of the constant into register. */
12723 if (op1 == const0_rtx
12724 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12726 code = (code == GTU ? GEU : LTU);
12733 code = (code == GTU ? LTU : GEU);
12737 /* Convert a>=0 into (unsigned)a<0x80000000. */
12740 if (mode == DImode || op1 != const0_rtx)
12742 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12743 code = (code == LT ? GEU : LTU);
12747 if (mode == DImode || op1 != constm1_rtx)
12749 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12750 code = (code == LE ? GEU : LTU);
12756 /* Swapping operands may cause constant to appear as first operand. */
12757 if (!nonimmediate_operand (op0, VOIDmode))
12759 if (!can_create_pseudo_p ())
12761 op0 = force_reg (mode, op0);
12763 ix86_compare_op0 = op0;
12764 ix86_compare_op1 = op1;
12765 *pop = ix86_expand_compare (code, NULL, NULL);
12766 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12771 ix86_expand_int_movcc (rtx operands[])
12773 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12774 rtx compare_seq, compare_op;
12775 rtx second_test, bypass_test;
12776 enum machine_mode mode = GET_MODE (operands[0]);
12777 bool sign_bit_compare_p = false;;
12780 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12781 compare_seq = get_insns ();
12784 compare_code = GET_CODE (compare_op);
12786 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12787 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12788 sign_bit_compare_p = true;
12790 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12791 HImode insns, we'd be swallowed in word prefix ops. */
12793 if ((mode != HImode || TARGET_FAST_PREFIX)
12794 && (mode != (TARGET_64BIT ? TImode : DImode))
12795 && CONST_INT_P (operands[2])
12796 && CONST_INT_P (operands[3]))
12798 rtx out = operands[0];
12799 HOST_WIDE_INT ct = INTVAL (operands[2]);
12800 HOST_WIDE_INT cf = INTVAL (operands[3]);
12801 HOST_WIDE_INT diff;
12804 /* Sign bit compares are better done using shifts than we do by using
12806 if (sign_bit_compare_p
12807 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12808 ix86_compare_op1, &compare_op))
12810 /* Detect overlap between destination and compare sources. */
12813 if (!sign_bit_compare_p)
12815 bool fpcmp = false;
12817 compare_code = GET_CODE (compare_op);
12819 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12820 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12823 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12826 /* To simplify rest of code, restrict to the GEU case. */
12827 if (compare_code == LTU)
12829 HOST_WIDE_INT tmp = ct;
12832 compare_code = reverse_condition (compare_code);
12833 code = reverse_condition (code);
12838 PUT_CODE (compare_op,
12839 reverse_condition_maybe_unordered
12840 (GET_CODE (compare_op)));
12842 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12846 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12847 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12848 tmp = gen_reg_rtx (mode);
12850 if (mode == DImode)
12851 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12853 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12857 if (code == GT || code == GE)
12858 code = reverse_condition (code);
12861 HOST_WIDE_INT tmp = ct;
12866 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12867 ix86_compare_op1, VOIDmode, 0, -1);
12880 tmp = expand_simple_binop (mode, PLUS,
12882 copy_rtx (tmp), 1, OPTAB_DIRECT);
12893 tmp = expand_simple_binop (mode, IOR,
12895 copy_rtx (tmp), 1, OPTAB_DIRECT);
12897 else if (diff == -1 && ct)
12907 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12909 tmp = expand_simple_binop (mode, PLUS,
12910 copy_rtx (tmp), GEN_INT (cf),
12911 copy_rtx (tmp), 1, OPTAB_DIRECT);
12919 * andl cf - ct, dest
12929 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12932 tmp = expand_simple_binop (mode, AND,
12934 gen_int_mode (cf - ct, mode),
12935 copy_rtx (tmp), 1, OPTAB_DIRECT);
12937 tmp = expand_simple_binop (mode, PLUS,
12938 copy_rtx (tmp), GEN_INT (ct),
12939 copy_rtx (tmp), 1, OPTAB_DIRECT);
12942 if (!rtx_equal_p (tmp, out))
12943 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12945 return 1; /* DONE */
12950 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12953 tmp = ct, ct = cf, cf = tmp;
12956 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12958 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12960 /* We may be reversing unordered compare to normal compare, that
12961 is not valid in general (we may convert non-trapping condition
12962 to trapping one), however on i386 we currently emit all
12963 comparisons unordered. */
12964 compare_code = reverse_condition_maybe_unordered (compare_code);
12965 code = reverse_condition_maybe_unordered (code);
12969 compare_code = reverse_condition (compare_code);
12970 code = reverse_condition (code);
12974 compare_code = UNKNOWN;
12975 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12976 && CONST_INT_P (ix86_compare_op1))
12978 if (ix86_compare_op1 == const0_rtx
12979 && (code == LT || code == GE))
12980 compare_code = code;
12981 else if (ix86_compare_op1 == constm1_rtx)
12985 else if (code == GT)
12990 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12991 if (compare_code != UNKNOWN
12992 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12993 && (cf == -1 || ct == -1))
12995 /* If lea code below could be used, only optimize
12996 if it results in a 2 insn sequence. */
12998 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12999 || diff == 3 || diff == 5 || diff == 9)
13000 || (compare_code == LT && ct == -1)
13001 || (compare_code == GE && cf == -1))
13004 * notl op1 (if necessary)
13012 code = reverse_condition (code);
13015 out = emit_store_flag (out, code, ix86_compare_op0,
13016 ix86_compare_op1, VOIDmode, 0, -1);
13018 out = expand_simple_binop (mode, IOR,
13020 out, 1, OPTAB_DIRECT);
13021 if (out != operands[0])
13022 emit_move_insn (operands[0], out);
13024 return 1; /* DONE */
13029 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
13030 || diff == 3 || diff == 5 || diff == 9)
13031 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
13033 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
13039 * lea cf(dest*(ct-cf)),dest
13043 * This also catches the degenerate setcc-only case.
13049 out = emit_store_flag (out, code, ix86_compare_op0,
13050 ix86_compare_op1, VOIDmode, 0, 1);
13053 /* On x86_64 the lea instruction operates on Pmode, so we need
13054 to get arithmetics done in proper mode to match. */
13056 tmp = copy_rtx (out);
13060 out1 = copy_rtx (out);
13061 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
13065 tmp = gen_rtx_PLUS (mode, tmp, out1);
13071 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
13074 if (!rtx_equal_p (tmp, out))
13077 out = force_operand (tmp, copy_rtx (out));
13079 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
13081 if (!rtx_equal_p (out, operands[0]))
13082 emit_move_insn (operands[0], copy_rtx (out));
13084 return 1; /* DONE */
13088 * General case: Jumpful:
13089 * xorl dest,dest cmpl op1, op2
13090 * cmpl op1, op2 movl ct, dest
13091 * setcc dest jcc 1f
13092 * decl dest movl cf, dest
13093 * andl (cf-ct),dest 1:
13096 * Size 20. Size 14.
13098 * This is reasonably steep, but branch mispredict costs are
13099 * high on modern cpus, so consider failing only if optimizing
13103 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
13104 && BRANCH_COST >= 2)
13108 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
13113 if (SCALAR_FLOAT_MODE_P (cmp_mode))
13115 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
13117 /* We may be reversing unordered compare to normal compare,
13118 that is not valid in general (we may convert non-trapping
13119 condition to trapping one), however on i386 we currently
13120 emit all comparisons unordered. */
13121 code = reverse_condition_maybe_unordered (code);
13125 code = reverse_condition (code);
13126 if (compare_code != UNKNOWN)
13127 compare_code = reverse_condition (compare_code);
13131 if (compare_code != UNKNOWN)
13133 /* notl op1 (if needed)
13138 For x < 0 (resp. x <= -1) there will be no notl,
13139 so if possible swap the constants to get rid of the
13141 True/false will be -1/0 while code below (store flag
13142 followed by decrement) is 0/-1, so the constants need
13143 to be exchanged once more. */
13145 if (compare_code == GE || !cf)
13147 code = reverse_condition (code);
13152 HOST_WIDE_INT tmp = cf;
13157 out = emit_store_flag (out, code, ix86_compare_op0,
13158 ix86_compare_op1, VOIDmode, 0, -1);
13162 out = emit_store_flag (out, code, ix86_compare_op0,
13163 ix86_compare_op1, VOIDmode, 0, 1);
13165 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
13166 copy_rtx (out), 1, OPTAB_DIRECT);
13169 out = expand_simple_binop (mode, AND, copy_rtx (out),
13170 gen_int_mode (cf - ct, mode),
13171 copy_rtx (out), 1, OPTAB_DIRECT);
13173 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
13174 copy_rtx (out), 1, OPTAB_DIRECT);
13175 if (!rtx_equal_p (out, operands[0]))
13176 emit_move_insn (operands[0], copy_rtx (out));
13178 return 1; /* DONE */
13182 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
13184 /* Try a few things more with specific constants and a variable. */
13187 rtx var, orig_out, out, tmp;
13189 if (BRANCH_COST <= 2)
13190 return 0; /* FAIL */
13192 /* If one of the two operands is an interesting constant, load a
13193 constant with the above and mask it in with a logical operation. */
13195 if (CONST_INT_P (operands[2]))
13198 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
13199 operands[3] = constm1_rtx, op = and_optab;
13200 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
13201 operands[3] = const0_rtx, op = ior_optab;
13203 return 0; /* FAIL */
13205 else if (CONST_INT_P (operands[3]))
13208 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
13209 operands[2] = constm1_rtx, op = and_optab;
13210 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
13211 operands[2] = const0_rtx, op = ior_optab;
13213 return 0; /* FAIL */
13216 return 0; /* FAIL */
13218 orig_out = operands[0];
13219 tmp = gen_reg_rtx (mode);
13222 /* Recurse to get the constant loaded. */
13223 if (ix86_expand_int_movcc (operands) == 0)
13224 return 0; /* FAIL */
13226 /* Mask in the interesting variable. */
13227 out = expand_binop (mode, op, var, tmp, orig_out, 0,
13229 if (!rtx_equal_p (out, orig_out))
13230 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
13232 return 1; /* DONE */
13236 * For comparison with above,
13246 if (! nonimmediate_operand (operands[2], mode))
13247 operands[2] = force_reg (mode, operands[2]);
13248 if (! nonimmediate_operand (operands[3], mode))
13249 operands[3] = force_reg (mode, operands[3]);
13251 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13253 rtx tmp = gen_reg_rtx (mode);
13254 emit_move_insn (tmp, operands[3]);
13257 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13259 rtx tmp = gen_reg_rtx (mode);
13260 emit_move_insn (tmp, operands[2]);
13264 if (! register_operand (operands[2], VOIDmode)
13266 || ! register_operand (operands[3], VOIDmode)))
13267 operands[2] = force_reg (mode, operands[2]);
13270 && ! register_operand (operands[3], VOIDmode))
13271 operands[3] = force_reg (mode, operands[3]);
13273 emit_insn (compare_seq);
13274 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13275 gen_rtx_IF_THEN_ELSE (mode,
13276 compare_op, operands[2],
13279 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13280 gen_rtx_IF_THEN_ELSE (mode,
13282 copy_rtx (operands[3]),
13283 copy_rtx (operands[0]))));
13285 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13286 gen_rtx_IF_THEN_ELSE (mode,
13288 copy_rtx (operands[2]),
13289 copy_rtx (operands[0]))));
13291 return 1; /* DONE */
13294 /* Swap, force into registers, or otherwise massage the two operands
13295 to an sse comparison with a mask result. Thus we differ a bit from
13296 ix86_prepare_fp_compare_args which expects to produce a flags result.
13298 The DEST operand exists to help determine whether to commute commutative
13299 operators. The POP0/POP1 operands are updated in place. The new
13300 comparison code is returned, or UNKNOWN if not implementable. */
13302 static enum rtx_code
13303 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13304 rtx *pop0, rtx *pop1)
13312 /* We have no LTGT as an operator. We could implement it with
13313 NE & ORDERED, but this requires an extra temporary. It's
13314 not clear that it's worth it. */
13321 /* These are supported directly. */
13328 /* For commutative operators, try to canonicalize the destination
13329 operand to be first in the comparison - this helps reload to
13330 avoid extra moves. */
13331 if (!dest || !rtx_equal_p (dest, *pop1))
13339 /* These are not supported directly. Swap the comparison operands
13340 to transform into something that is supported. */
13344 code = swap_condition (code);
13348 gcc_unreachable ();
13354 /* Detect conditional moves that exactly match min/max operational
13355 semantics. Note that this is IEEE safe, as long as we don't
13356 interchange the operands.
13358 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13359 and TRUE if the operation is successful and instructions are emitted. */
13362 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13363 rtx cmp_op1, rtx if_true, rtx if_false)
13365 enum machine_mode mode;
13371 else if (code == UNGE)
13374 if_true = if_false;
13380 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13382 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13387 mode = GET_MODE (dest);
13389 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13390 but MODE may be a vector mode and thus not appropriate. */
13391 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13393 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13396 if_true = force_reg (mode, if_true);
13397 v = gen_rtvec (2, if_true, if_false);
13398 tmp = gen_rtx_UNSPEC (mode, v, u);
13402 code = is_min ? SMIN : SMAX;
13403 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13406 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13410 /* Expand an sse vector comparison. Return the register with the result. */
13413 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13414 rtx op_true, rtx op_false)
13416 enum machine_mode mode = GET_MODE (dest);
13419 cmp_op0 = force_reg (mode, cmp_op0);
13420 if (!nonimmediate_operand (cmp_op1, mode))
13421 cmp_op1 = force_reg (mode, cmp_op1);
13424 || reg_overlap_mentioned_p (dest, op_true)
13425 || reg_overlap_mentioned_p (dest, op_false))
13426 dest = gen_reg_rtx (mode);
13428 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13429 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13434 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13435 operations. This is used for both scalar and vector conditional moves. */
13438 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13440 enum machine_mode mode = GET_MODE (dest);
13443 if (op_false == CONST0_RTX (mode))
13445 op_true = force_reg (mode, op_true);
13446 x = gen_rtx_AND (mode, cmp, op_true);
13447 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13449 else if (op_true == CONST0_RTX (mode))
13451 op_false = force_reg (mode, op_false);
13452 x = gen_rtx_NOT (mode, cmp);
13453 x = gen_rtx_AND (mode, x, op_false);
13454 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13456 else if (TARGET_SSE5)
13458 rtx pcmov = gen_rtx_SET (mode, dest,
13459 gen_rtx_IF_THEN_ELSE (mode, cmp,
13466 op_true = force_reg (mode, op_true);
13467 op_false = force_reg (mode, op_false);
13469 t2 = gen_reg_rtx (mode);
13471 t3 = gen_reg_rtx (mode);
13475 x = gen_rtx_AND (mode, op_true, cmp);
13476 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13478 x = gen_rtx_NOT (mode, cmp);
13479 x = gen_rtx_AND (mode, x, op_false);
13480 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13482 x = gen_rtx_IOR (mode, t3, t2);
13483 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13487 /* Expand a floating-point conditional move. Return true if successful. */
13490 ix86_expand_fp_movcc (rtx operands[])
13492 enum machine_mode mode = GET_MODE (operands[0]);
13493 enum rtx_code code = GET_CODE (operands[1]);
13494 rtx tmp, compare_op, second_test, bypass_test;
13496 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13498 enum machine_mode cmode;
13500 /* Since we've no cmove for sse registers, don't force bad register
13501 allocation just to gain access to it. Deny movcc when the
13502 comparison mode doesn't match the move mode. */
13503 cmode = GET_MODE (ix86_compare_op0);
13504 if (cmode == VOIDmode)
13505 cmode = GET_MODE (ix86_compare_op1);
13509 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13511 &ix86_compare_op1);
13512 if (code == UNKNOWN)
13515 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13516 ix86_compare_op1, operands[2],
13520 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13521 ix86_compare_op1, operands[2], operands[3]);
13522 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13526 /* The floating point conditional move instructions don't directly
13527 support conditions resulting from a signed integer comparison. */
13529 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13531 /* The floating point conditional move instructions don't directly
13532 support signed integer comparisons. */
13534 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13536 gcc_assert (!second_test && !bypass_test);
13537 tmp = gen_reg_rtx (QImode);
13538 ix86_expand_setcc (code, tmp);
13540 ix86_compare_op0 = tmp;
13541 ix86_compare_op1 = const0_rtx;
13542 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13544 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13546 tmp = gen_reg_rtx (mode);
13547 emit_move_insn (tmp, operands[3]);
13550 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13552 tmp = gen_reg_rtx (mode);
13553 emit_move_insn (tmp, operands[2]);
13557 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13558 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13559 operands[2], operands[3])));
13561 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13562 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13563 operands[3], operands[0])));
13565 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13566 gen_rtx_IF_THEN_ELSE (mode, second_test,
13567 operands[2], operands[0])));
13572 /* Expand a floating-point vector conditional move; a vcond operation
13573 rather than a movcc operation. */
13576 ix86_expand_fp_vcond (rtx operands[])
13578 enum rtx_code code = GET_CODE (operands[3]);
13581 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13582 &operands[4], &operands[5]);
13583 if (code == UNKNOWN)
13586 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13587 operands[5], operands[1], operands[2]))
13590 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13591 operands[1], operands[2]);
13592 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13596 /* Expand a signed/unsigned integral vector conditional move. */
13599 ix86_expand_int_vcond (rtx operands[])
13601 enum machine_mode mode = GET_MODE (operands[0]);
13602 enum rtx_code code = GET_CODE (operands[3]);
13603 bool negate = false;
13606 cop0 = operands[4];
13607 cop1 = operands[5];
13609 /* SSE5 supports all of the comparisons on all vector int types. */
13612 /* Canonicalize the comparison to EQ, GT, GTU. */
13623 code = reverse_condition (code);
13629 code = reverse_condition (code);
13635 code = swap_condition (code);
13636 x = cop0, cop0 = cop1, cop1 = x;
13640 gcc_unreachable ();
13643 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13644 if (mode == V2DImode)
13649 /* SSE4.1 supports EQ. */
13650 if (!TARGET_SSE4_1)
13656 /* SSE4.2 supports GT/GTU. */
13657 if (!TARGET_SSE4_2)
13662 gcc_unreachable ();
13666 /* Unsigned parallel compare is not supported by the hardware. Play some
13667 tricks to turn this into a signed comparison against 0. */
13670 cop0 = force_reg (mode, cop0);
13679 /* Perform a parallel modulo subtraction. */
13680 t1 = gen_reg_rtx (mode);
13681 emit_insn ((mode == V4SImode
13683 : gen_subv2di3) (t1, cop0, cop1));
13685 /* Extract the original sign bit of op0. */
13686 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13688 t2 = gen_reg_rtx (mode);
13689 emit_insn ((mode == V4SImode
13691 : gen_andv2di3) (t2, cop0, mask));
13693 /* XOR it back into the result of the subtraction. This results
13694 in the sign bit set iff we saw unsigned underflow. */
13695 x = gen_reg_rtx (mode);
13696 emit_insn ((mode == V4SImode
13698 : gen_xorv2di3) (x, t1, t2));
13706 /* Perform a parallel unsigned saturating subtraction. */
13707 x = gen_reg_rtx (mode);
13708 emit_insn (gen_rtx_SET (VOIDmode, x,
13709 gen_rtx_US_MINUS (mode, cop0, cop1)));
13716 gcc_unreachable ();
13720 cop1 = CONST0_RTX (mode);
13724 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13725 operands[1+negate], operands[2-negate]);
13727 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13728 operands[2-negate]);
13732 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13733 true if we should do zero extension, else sign extension. HIGH_P is
13734 true if we want the N/2 high elements, else the low elements. */
13737 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13739 enum machine_mode imode = GET_MODE (operands[1]);
13740 rtx (*unpack)(rtx, rtx, rtx);
13747 unpack = gen_vec_interleave_highv16qi;
13749 unpack = gen_vec_interleave_lowv16qi;
13753 unpack = gen_vec_interleave_highv8hi;
13755 unpack = gen_vec_interleave_lowv8hi;
13759 unpack = gen_vec_interleave_highv4si;
13761 unpack = gen_vec_interleave_lowv4si;
13764 gcc_unreachable ();
13767 dest = gen_lowpart (imode, operands[0]);
13770 se = force_reg (imode, CONST0_RTX (imode));
13772 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13773 operands[1], pc_rtx, pc_rtx);
13775 emit_insn (unpack (dest, operands[1], se));
13778 /* This function performs the same task as ix86_expand_sse_unpack,
13779 but with SSE4.1 instructions. */
13782 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13784 enum machine_mode imode = GET_MODE (operands[1]);
13785 rtx (*unpack)(rtx, rtx);
13792 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13794 unpack = gen_sse4_1_extendv8qiv8hi2;
13798 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13800 unpack = gen_sse4_1_extendv4hiv4si2;
13804 unpack = gen_sse4_1_zero_extendv2siv2di2;
13806 unpack = gen_sse4_1_extendv2siv2di2;
13809 gcc_unreachable ();
13812 dest = operands[0];
13815 /* Shift higher 8 bytes to lower 8 bytes. */
13816 src = gen_reg_rtx (imode);
13817 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13818 gen_lowpart (TImode, operands[1]),
13824 emit_insn (unpack (dest, src));
13827 /* This function performs the same task as ix86_expand_sse_unpack,
13828 but with sse5 instructions. */
13831 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13833 enum machine_mode imode = GET_MODE (operands[1]);
13834 int pperm_bytes[16];
13836 int h = (high_p) ? 8 : 0;
13839 rtvec v = rtvec_alloc (16);
13842 rtx op0 = operands[0], op1 = operands[1];
13847 vs = rtvec_alloc (8);
13848 h2 = (high_p) ? 8 : 0;
13849 for (i = 0; i < 8; i++)
13851 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13852 pperm_bytes[2*i+1] = ((unsigned_p)
13854 : PPERM_SIGN | PPERM_SRC2 | i | h);
13857 for (i = 0; i < 16; i++)
13858 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13860 for (i = 0; i < 8; i++)
13861 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13863 p = gen_rtx_PARALLEL (VOIDmode, vs);
13864 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13866 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13868 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13872 vs = rtvec_alloc (4);
13873 h2 = (high_p) ? 4 : 0;
13874 for (i = 0; i < 4; i++)
13876 sign_extend = ((unsigned_p)
13878 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13879 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13880 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13881 pperm_bytes[4*i+2] = sign_extend;
13882 pperm_bytes[4*i+3] = sign_extend;
13885 for (i = 0; i < 16; i++)
13886 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13888 for (i = 0; i < 4; i++)
13889 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13891 p = gen_rtx_PARALLEL (VOIDmode, vs);
13892 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13894 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13896 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13900 vs = rtvec_alloc (2);
13901 h2 = (high_p) ? 2 : 0;
13902 for (i = 0; i < 2; i++)
13904 sign_extend = ((unsigned_p)
13906 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13907 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13908 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13909 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13910 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13911 pperm_bytes[8*i+4] = sign_extend;
13912 pperm_bytes[8*i+5] = sign_extend;
13913 pperm_bytes[8*i+6] = sign_extend;
13914 pperm_bytes[8*i+7] = sign_extend;
13917 for (i = 0; i < 16; i++)
13918 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13920 for (i = 0; i < 2; i++)
13921 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13923 p = gen_rtx_PARALLEL (VOIDmode, vs);
13924 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13926 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13928 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13932 gcc_unreachable ();
13938 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13939 next narrower integer vector type */
13941 ix86_expand_sse5_pack (rtx operands[3])
13943 enum machine_mode imode = GET_MODE (operands[0]);
13944 int pperm_bytes[16];
13946 rtvec v = rtvec_alloc (16);
13948 rtx op0 = operands[0];
13949 rtx op1 = operands[1];
13950 rtx op2 = operands[2];
13955 for (i = 0; i < 8; i++)
13957 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13958 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13961 for (i = 0; i < 16; i++)
13962 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13964 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13965 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13969 for (i = 0; i < 4; i++)
13971 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13972 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13973 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13974 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13977 for (i = 0; i < 16; i++)
13978 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13980 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13981 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13985 for (i = 0; i < 2; i++)
13987 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13988 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13989 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13990 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13991 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13992 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13993 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13994 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13997 for (i = 0; i < 16; i++)
13998 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
14000 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
14001 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
14005 gcc_unreachable ();
14011 /* Expand conditional increment or decrement using adb/sbb instructions.
14012 The default case using setcc followed by the conditional move can be
14013 done by generic code. */
14015 ix86_expand_int_addcc (rtx operands[])
14017 enum rtx_code code = GET_CODE (operands[1]);
14019 rtx val = const0_rtx;
14020 bool fpcmp = false;
14021 enum machine_mode mode = GET_MODE (operands[0]);
14023 if (operands[3] != const1_rtx
14024 && operands[3] != constm1_rtx)
14026 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14027 ix86_compare_op1, &compare_op))
14029 code = GET_CODE (compare_op);
14031 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14032 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14035 code = ix86_fp_compare_code_to_integer (code);
14042 PUT_CODE (compare_op,
14043 reverse_condition_maybe_unordered
14044 (GET_CODE (compare_op)));
14046 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14048 PUT_MODE (compare_op, mode);
14050 /* Construct either adc or sbb insn. */
14051 if ((code == LTU) == (operands[3] == constm1_rtx))
14053 switch (GET_MODE (operands[0]))
14056 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
14059 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
14062 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
14065 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
14068 gcc_unreachable ();
14073 switch (GET_MODE (operands[0]))
14076 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
14079 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
14082 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
14085 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
14088 gcc_unreachable ();
14091 return 1; /* DONE */
14095 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
14096 works for floating pointer parameters and nonoffsetable memories.
14097 For pushes, it returns just stack offsets; the values will be saved
14098 in the right order. Maximally three parts are generated. */
14101 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
14106 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
14108 size = (GET_MODE_SIZE (mode) + 4) / 8;
14110 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
14111 gcc_assert (size >= 2 && size <= 3);
14113 /* Optimize constant pool reference to immediates. This is used by fp
14114 moves, that force all constants to memory to allow combining. */
14115 if (MEM_P (operand) && MEM_READONLY_P (operand))
14117 rtx tmp = maybe_get_pool_constant (operand);
14122 if (MEM_P (operand) && !offsettable_memref_p (operand))
14124 /* The only non-offsetable memories we handle are pushes. */
14125 int ok = push_operand (operand, VOIDmode);
14129 operand = copy_rtx (operand);
14130 PUT_MODE (operand, Pmode);
14131 parts[0] = parts[1] = parts[2] = operand;
14135 if (GET_CODE (operand) == CONST_VECTOR)
14137 enum machine_mode imode = int_mode_for_mode (mode);
14138 /* Caution: if we looked through a constant pool memory above,
14139 the operand may actually have a different mode now. That's
14140 ok, since we want to pun this all the way back to an integer. */
14141 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
14142 gcc_assert (operand != NULL);
14148 if (mode == DImode)
14149 split_di (&operand, 1, &parts[0], &parts[1]);
14152 if (REG_P (operand))
14154 gcc_assert (reload_completed);
14155 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
14156 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
14158 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
14160 else if (offsettable_memref_p (operand))
14162 operand = adjust_address (operand, SImode, 0);
14163 parts[0] = operand;
14164 parts[1] = adjust_address (operand, SImode, 4);
14166 parts[2] = adjust_address (operand, SImode, 8);
14168 else if (GET_CODE (operand) == CONST_DOUBLE)
14173 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14177 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
14178 parts[2] = gen_int_mode (l[2], SImode);
14181 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
14184 gcc_unreachable ();
14186 parts[1] = gen_int_mode (l[1], SImode);
14187 parts[0] = gen_int_mode (l[0], SImode);
14190 gcc_unreachable ();
14195 if (mode == TImode)
14196 split_ti (&operand, 1, &parts[0], &parts[1]);
14197 if (mode == XFmode || mode == TFmode)
14199 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
14200 if (REG_P (operand))
14202 gcc_assert (reload_completed);
14203 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
14204 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
14206 else if (offsettable_memref_p (operand))
14208 operand = adjust_address (operand, DImode, 0);
14209 parts[0] = operand;
14210 parts[1] = adjust_address (operand, upper_mode, 8);
14212 else if (GET_CODE (operand) == CONST_DOUBLE)
14217 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14218 real_to_target (l, &r, mode);
14220 /* Do not use shift by 32 to avoid warning on 32bit systems. */
14221 if (HOST_BITS_PER_WIDE_INT >= 64)
14224 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
14225 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
14228 parts[0] = immed_double_const (l[0], l[1], DImode);
14230 if (upper_mode == SImode)
14231 parts[1] = gen_int_mode (l[2], SImode);
14232 else if (HOST_BITS_PER_WIDE_INT >= 64)
14235 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
14236 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
14239 parts[1] = immed_double_const (l[2], l[3], DImode);
14242 gcc_unreachable ();
14249 /* Emit insns to perform a move or push of DI, DF, and XF values.
14250 Return false when normal moves are needed; true when all required
14251 insns have been emitted. Operands 2-4 contain the input values
14252 int the correct order; operands 5-7 contain the output values. */
14255 ix86_split_long_move (rtx operands[])
14260 int collisions = 0;
14261 enum machine_mode mode = GET_MODE (operands[0]);
14263 /* The DFmode expanders may ask us to move double.
14264 For 64bit target this is single move. By hiding the fact
14265 here we simplify i386.md splitters. */
14266 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14268 /* Optimize constant pool reference to immediates. This is used by
14269 fp moves, that force all constants to memory to allow combining. */
14271 if (MEM_P (operands[1])
14272 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14273 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14274 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14275 if (push_operand (operands[0], VOIDmode))
14277 operands[0] = copy_rtx (operands[0]);
14278 PUT_MODE (operands[0], Pmode);
14281 operands[0] = gen_lowpart (DImode, operands[0]);
14282 operands[1] = gen_lowpart (DImode, operands[1]);
14283 emit_move_insn (operands[0], operands[1]);
14287 /* The only non-offsettable memory we handle is push. */
14288 if (push_operand (operands[0], VOIDmode))
14291 gcc_assert (!MEM_P (operands[0])
14292 || offsettable_memref_p (operands[0]));
14294 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14295 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14297 /* When emitting push, take care for source operands on the stack. */
14298 if (push && MEM_P (operands[1])
14299 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14302 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14303 XEXP (part[1][2], 0));
14304 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14305 XEXP (part[1][1], 0));
14308 /* We need to do copy in the right order in case an address register
14309 of the source overlaps the destination. */
14310 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14312 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14314 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14317 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14320 /* Collision in the middle part can be handled by reordering. */
14321 if (collisions == 1 && nparts == 3
14322 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14325 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14326 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14329 /* If there are more collisions, we can't handle it by reordering.
14330 Do an lea to the last part and use only one colliding move. */
14331 else if (collisions > 1)
14337 base = part[0][nparts - 1];
14339 /* Handle the case when the last part isn't valid for lea.
14340 Happens in 64-bit mode storing the 12-byte XFmode. */
14341 if (GET_MODE (base) != Pmode)
14342 base = gen_rtx_REG (Pmode, REGNO (base));
14344 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14345 part[1][0] = replace_equiv_address (part[1][0], base);
14346 part[1][1] = replace_equiv_address (part[1][1],
14347 plus_constant (base, UNITS_PER_WORD));
14349 part[1][2] = replace_equiv_address (part[1][2],
14350 plus_constant (base, 8));
14360 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14361 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14362 emit_move_insn (part[0][2], part[1][2]);
14367 /* In 64bit mode we don't have 32bit push available. In case this is
14368 register, it is OK - we will just use larger counterpart. We also
14369 retype memory - these comes from attempt to avoid REX prefix on
14370 moving of second half of TFmode value. */
14371 if (GET_MODE (part[1][1]) == SImode)
14373 switch (GET_CODE (part[1][1]))
14376 part[1][1] = adjust_address (part[1][1], DImode, 0);
14380 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14384 gcc_unreachable ();
14387 if (GET_MODE (part[1][0]) == SImode)
14388 part[1][0] = part[1][1];
14391 emit_move_insn (part[0][1], part[1][1]);
14392 emit_move_insn (part[0][0], part[1][0]);
14396 /* Choose correct order to not overwrite the source before it is copied. */
14397 if ((REG_P (part[0][0])
14398 && REG_P (part[1][1])
14399 && (REGNO (part[0][0]) == REGNO (part[1][1])
14401 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14403 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14407 operands[2] = part[0][2];
14408 operands[3] = part[0][1];
14409 operands[4] = part[0][0];
14410 operands[5] = part[1][2];
14411 operands[6] = part[1][1];
14412 operands[7] = part[1][0];
14416 operands[2] = part[0][1];
14417 operands[3] = part[0][0];
14418 operands[5] = part[1][1];
14419 operands[6] = part[1][0];
14426 operands[2] = part[0][0];
14427 operands[3] = part[0][1];
14428 operands[4] = part[0][2];
14429 operands[5] = part[1][0];
14430 operands[6] = part[1][1];
14431 operands[7] = part[1][2];
14435 operands[2] = part[0][0];
14436 operands[3] = part[0][1];
14437 operands[5] = part[1][0];
14438 operands[6] = part[1][1];
14442 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14445 if (CONST_INT_P (operands[5])
14446 && operands[5] != const0_rtx
14447 && REG_P (operands[2]))
14449 if (CONST_INT_P (operands[6])
14450 && INTVAL (operands[6]) == INTVAL (operands[5]))
14451 operands[6] = operands[2];
14454 && CONST_INT_P (operands[7])
14455 && INTVAL (operands[7]) == INTVAL (operands[5]))
14456 operands[7] = operands[2];
14460 && CONST_INT_P (operands[6])
14461 && operands[6] != const0_rtx
14462 && REG_P (operands[3])
14463 && CONST_INT_P (operands[7])
14464 && INTVAL (operands[7]) == INTVAL (operands[6]))
14465 operands[7] = operands[3];
14468 emit_move_insn (operands[2], operands[5]);
14469 emit_move_insn (operands[3], operands[6]);
14471 emit_move_insn (operands[4], operands[7]);
14476 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14477 left shift by a constant, either using a single shift or
14478 a sequence of add instructions. */
14481 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14485 emit_insn ((mode == DImode
14487 : gen_adddi3) (operand, operand, operand));
14489 else if (!optimize_size
14490 && count * ix86_cost->add <= ix86_cost->shift_const)
14493 for (i=0; i<count; i++)
14495 emit_insn ((mode == DImode
14497 : gen_adddi3) (operand, operand, operand));
14501 emit_insn ((mode == DImode
14503 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14507 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14509 rtx low[2], high[2];
14511 const int single_width = mode == DImode ? 32 : 64;
14513 if (CONST_INT_P (operands[2]))
14515 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14516 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14518 if (count >= single_width)
14520 emit_move_insn (high[0], low[1]);
14521 emit_move_insn (low[0], const0_rtx);
14523 if (count > single_width)
14524 ix86_expand_ashl_const (high[0], count - single_width, mode);
14528 if (!rtx_equal_p (operands[0], operands[1]))
14529 emit_move_insn (operands[0], operands[1]);
14530 emit_insn ((mode == DImode
14532 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14533 ix86_expand_ashl_const (low[0], count, mode);
14538 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14540 if (operands[1] == const1_rtx)
14542 /* Assuming we've chosen a QImode capable registers, then 1 << N
14543 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14544 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14546 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14548 ix86_expand_clear (low[0]);
14549 ix86_expand_clear (high[0]);
14550 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14552 d = gen_lowpart (QImode, low[0]);
14553 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14554 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14555 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14557 d = gen_lowpart (QImode, high[0]);
14558 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14559 s = gen_rtx_NE (QImode, flags, const0_rtx);
14560 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14563 /* Otherwise, we can get the same results by manually performing
14564 a bit extract operation on bit 5/6, and then performing the two
14565 shifts. The two methods of getting 0/1 into low/high are exactly
14566 the same size. Avoiding the shift in the bit extract case helps
14567 pentium4 a bit; no one else seems to care much either way. */
14572 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14573 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14575 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14576 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14578 emit_insn ((mode == DImode
14580 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14581 emit_insn ((mode == DImode
14583 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14584 emit_move_insn (low[0], high[0]);
14585 emit_insn ((mode == DImode
14587 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14590 emit_insn ((mode == DImode
14592 : gen_ashldi3) (low[0], low[0], operands[2]));
14593 emit_insn ((mode == DImode
14595 : gen_ashldi3) (high[0], high[0], operands[2]));
14599 if (operands[1] == constm1_rtx)
14601 /* For -1 << N, we can avoid the shld instruction, because we
14602 know that we're shifting 0...31/63 ones into a -1. */
14603 emit_move_insn (low[0], constm1_rtx);
14605 emit_move_insn (high[0], low[0]);
14607 emit_move_insn (high[0], constm1_rtx);
14611 if (!rtx_equal_p (operands[0], operands[1]))
14612 emit_move_insn (operands[0], operands[1]);
14614 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14615 emit_insn ((mode == DImode
14617 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14620 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14622 if (TARGET_CMOVE && scratch)
14624 ix86_expand_clear (scratch);
14625 emit_insn ((mode == DImode
14626 ? gen_x86_shift_adj_1
14627 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14630 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14634 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14636 rtx low[2], high[2];
14638 const int single_width = mode == DImode ? 32 : 64;
14640 if (CONST_INT_P (operands[2]))
14642 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14643 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14645 if (count == single_width * 2 - 1)
14647 emit_move_insn (high[0], high[1]);
14648 emit_insn ((mode == DImode
14650 : gen_ashrdi3) (high[0], high[0],
14651 GEN_INT (single_width - 1)));
14652 emit_move_insn (low[0], high[0]);
14655 else if (count >= single_width)
14657 emit_move_insn (low[0], high[1]);
14658 emit_move_insn (high[0], low[0]);
14659 emit_insn ((mode == DImode
14661 : gen_ashrdi3) (high[0], high[0],
14662 GEN_INT (single_width - 1)));
14663 if (count > single_width)
14664 emit_insn ((mode == DImode
14666 : gen_ashrdi3) (low[0], low[0],
14667 GEN_INT (count - single_width)));
14671 if (!rtx_equal_p (operands[0], operands[1]))
14672 emit_move_insn (operands[0], operands[1]);
14673 emit_insn ((mode == DImode
14675 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14676 emit_insn ((mode == DImode
14678 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14683 if (!rtx_equal_p (operands[0], operands[1]))
14684 emit_move_insn (operands[0], operands[1]);
14686 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14688 emit_insn ((mode == DImode
14690 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14691 emit_insn ((mode == DImode
14693 : gen_ashrdi3) (high[0], high[0], operands[2]));
14695 if (TARGET_CMOVE && scratch)
14697 emit_move_insn (scratch, high[0]);
14698 emit_insn ((mode == DImode
14700 : gen_ashrdi3) (scratch, scratch,
14701 GEN_INT (single_width - 1)));
14702 emit_insn ((mode == DImode
14703 ? gen_x86_shift_adj_1
14704 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14708 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14713 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14715 rtx low[2], high[2];
14717 const int single_width = mode == DImode ? 32 : 64;
14719 if (CONST_INT_P (operands[2]))
14721 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14722 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14724 if (count >= single_width)
14726 emit_move_insn (low[0], high[1]);
14727 ix86_expand_clear (high[0]);
14729 if (count > single_width)
14730 emit_insn ((mode == DImode
14732 : gen_lshrdi3) (low[0], low[0],
14733 GEN_INT (count - single_width)));
14737 if (!rtx_equal_p (operands[0], operands[1]))
14738 emit_move_insn (operands[0], operands[1]);
14739 emit_insn ((mode == DImode
14741 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14742 emit_insn ((mode == DImode
14744 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14749 if (!rtx_equal_p (operands[0], operands[1]))
14750 emit_move_insn (operands[0], operands[1]);
14752 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14754 emit_insn ((mode == DImode
14756 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14757 emit_insn ((mode == DImode
14759 : gen_lshrdi3) (high[0], high[0], operands[2]));
14761 /* Heh. By reversing the arguments, we can reuse this pattern. */
14762 if (TARGET_CMOVE && scratch)
14764 ix86_expand_clear (scratch);
14765 emit_insn ((mode == DImode
14766 ? gen_x86_shift_adj_1
14767 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14771 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14775 /* Predict just emitted jump instruction to be taken with probability PROB. */
14777 predict_jump (int prob)
14779 rtx insn = get_last_insn ();
14780 gcc_assert (JUMP_P (insn));
14782 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14787 /* Helper function for the string operations below. Dest VARIABLE whether
14788 it is aligned to VALUE bytes. If true, jump to the label. */
14790 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14792 rtx label = gen_label_rtx ();
14793 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14794 if (GET_MODE (variable) == DImode)
14795 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14797 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14798 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14801 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14803 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14807 /* Adjust COUNTER by the VALUE. */
14809 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14811 if (GET_MODE (countreg) == DImode)
14812 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14814 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14817 /* Zero extend possibly SImode EXP to Pmode register. */
14819 ix86_zero_extend_to_Pmode (rtx exp)
14822 if (GET_MODE (exp) == VOIDmode)
14823 return force_reg (Pmode, exp);
14824 if (GET_MODE (exp) == Pmode)
14825 return copy_to_mode_reg (Pmode, exp);
14826 r = gen_reg_rtx (Pmode);
14827 emit_insn (gen_zero_extendsidi2 (r, exp));
14831 /* Divide COUNTREG by SCALE. */
14833 scale_counter (rtx countreg, int scale)
14836 rtx piece_size_mask;
14840 if (CONST_INT_P (countreg))
14841 return GEN_INT (INTVAL (countreg) / scale);
14842 gcc_assert (REG_P (countreg));
14844 piece_size_mask = GEN_INT (scale - 1);
14845 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14846 GEN_INT (exact_log2 (scale)),
14847 NULL, 1, OPTAB_DIRECT);
14851 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14852 DImode for constant loop counts. */
14854 static enum machine_mode
14855 counter_mode (rtx count_exp)
14857 if (GET_MODE (count_exp) != VOIDmode)
14858 return GET_MODE (count_exp);
14859 if (GET_CODE (count_exp) != CONST_INT)
14861 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14866 /* When SRCPTR is non-NULL, output simple loop to move memory
14867 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14868 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14869 equivalent loop to set memory by VALUE (supposed to be in MODE).
14871 The size is rounded down to whole number of chunk size moved at once.
14872 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14876 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14877 rtx destptr, rtx srcptr, rtx value,
14878 rtx count, enum machine_mode mode, int unroll,
14881 rtx out_label, top_label, iter, tmp;
14882 enum machine_mode iter_mode = counter_mode (count);
14883 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14884 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14890 top_label = gen_label_rtx ();
14891 out_label = gen_label_rtx ();
14892 iter = gen_reg_rtx (iter_mode);
14894 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14895 NULL, 1, OPTAB_DIRECT);
14896 /* Those two should combine. */
14897 if (piece_size == const1_rtx)
14899 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14901 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14903 emit_move_insn (iter, const0_rtx);
14905 emit_label (top_label);
14907 tmp = convert_modes (Pmode, iter_mode, iter, true);
14908 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14909 destmem = change_address (destmem, mode, x_addr);
14913 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14914 srcmem = change_address (srcmem, mode, y_addr);
14916 /* When unrolling for chips that reorder memory reads and writes,
14917 we can save registers by using single temporary.
14918 Also using 4 temporaries is overkill in 32bit mode. */
14919 if (!TARGET_64BIT && 0)
14921 for (i = 0; i < unroll; i++)
14926 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14928 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14930 emit_move_insn (destmem, srcmem);
14936 gcc_assert (unroll <= 4);
14937 for (i = 0; i < unroll; i++)
14939 tmpreg[i] = gen_reg_rtx (mode);
14943 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14945 emit_move_insn (tmpreg[i], srcmem);
14947 for (i = 0; i < unroll; i++)
14952 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14954 emit_move_insn (destmem, tmpreg[i]);
14959 for (i = 0; i < unroll; i++)
14963 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14964 emit_move_insn (destmem, value);
14967 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14968 true, OPTAB_LIB_WIDEN);
14970 emit_move_insn (iter, tmp);
14972 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14974 if (expected_size != -1)
14976 expected_size /= GET_MODE_SIZE (mode) * unroll;
14977 if (expected_size == 0)
14979 else if (expected_size > REG_BR_PROB_BASE)
14980 predict_jump (REG_BR_PROB_BASE - 1);
14982 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14985 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14986 iter = ix86_zero_extend_to_Pmode (iter);
14987 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14988 true, OPTAB_LIB_WIDEN);
14989 if (tmp != destptr)
14990 emit_move_insn (destptr, tmp);
14993 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14994 true, OPTAB_LIB_WIDEN);
14996 emit_move_insn (srcptr, tmp);
14998 emit_label (out_label);
15001 /* Output "rep; mov" instruction.
15002 Arguments have same meaning as for previous function */
15004 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
15005 rtx destptr, rtx srcptr,
15007 enum machine_mode mode)
15013 /* If the size is known, it is shorter to use rep movs. */
15014 if (mode == QImode && CONST_INT_P (count)
15015 && !(INTVAL (count) & 3))
15018 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
15019 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
15020 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
15021 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
15022 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
15023 if (mode != QImode)
15025 destexp = gen_rtx_ASHIFT (Pmode, countreg,
15026 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
15027 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
15028 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
15029 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
15030 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
15034 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
15035 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
15037 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
15041 /* Output "rep; stos" instruction.
15042 Arguments have same meaning as for previous function */
15044 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
15046 enum machine_mode mode)
15051 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
15052 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
15053 value = force_reg (mode, gen_lowpart (mode, value));
15054 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
15055 if (mode != QImode)
15057 destexp = gen_rtx_ASHIFT (Pmode, countreg,
15058 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
15059 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
15062 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
15063 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
15067 emit_strmov (rtx destmem, rtx srcmem,
15068 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
15070 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
15071 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
15072 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15075 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
15077 expand_movmem_epilogue (rtx destmem, rtx srcmem,
15078 rtx destptr, rtx srcptr, rtx count, int max_size)
15081 if (CONST_INT_P (count))
15083 HOST_WIDE_INT countval = INTVAL (count);
15086 if ((countval & 0x10) && max_size > 16)
15090 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
15091 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
15094 gcc_unreachable ();
15097 if ((countval & 0x08) && max_size > 8)
15100 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
15103 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
15104 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
15108 if ((countval & 0x04) && max_size > 4)
15110 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
15113 if ((countval & 0x02) && max_size > 2)
15115 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
15118 if ((countval & 0x01) && max_size > 1)
15120 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
15127 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
15128 count, 1, OPTAB_DIRECT);
15129 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
15130 count, QImode, 1, 4);
15134 /* When there are stringops, we can cheaply increase dest and src pointers.
15135 Otherwise we save code size by maintaining offset (zero is readily
15136 available from preceding rep operation) and using x86 addressing modes.
15138 if (TARGET_SINGLE_STRINGOP)
15142 rtx label = ix86_expand_aligntest (count, 4, true);
15143 src = change_address (srcmem, SImode, srcptr);
15144 dest = change_address (destmem, SImode, destptr);
15145 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15146 emit_label (label);
15147 LABEL_NUSES (label) = 1;
15151 rtx label = ix86_expand_aligntest (count, 2, true);
15152 src = change_address (srcmem, HImode, srcptr);
15153 dest = change_address (destmem, HImode, destptr);
15154 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15155 emit_label (label);
15156 LABEL_NUSES (label) = 1;
15160 rtx label = ix86_expand_aligntest (count, 1, true);
15161 src = change_address (srcmem, QImode, srcptr);
15162 dest = change_address (destmem, QImode, destptr);
15163 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15164 emit_label (label);
15165 LABEL_NUSES (label) = 1;
15170 rtx offset = force_reg (Pmode, const0_rtx);
15175 rtx label = ix86_expand_aligntest (count, 4, true);
15176 src = change_address (srcmem, SImode, srcptr);
15177 dest = change_address (destmem, SImode, destptr);
15178 emit_move_insn (dest, src);
15179 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
15180 true, OPTAB_LIB_WIDEN);
15182 emit_move_insn (offset, tmp);
15183 emit_label (label);
15184 LABEL_NUSES (label) = 1;
15188 rtx label = ix86_expand_aligntest (count, 2, true);
15189 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15190 src = change_address (srcmem, HImode, tmp);
15191 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15192 dest = change_address (destmem, HImode, tmp);
15193 emit_move_insn (dest, src);
15194 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
15195 true, OPTAB_LIB_WIDEN);
15197 emit_move_insn (offset, tmp);
15198 emit_label (label);
15199 LABEL_NUSES (label) = 1;
15203 rtx label = ix86_expand_aligntest (count, 1, true);
15204 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15205 src = change_address (srcmem, QImode, tmp);
15206 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15207 dest = change_address (destmem, QImode, tmp);
15208 emit_move_insn (dest, src);
15209 emit_label (label);
15210 LABEL_NUSES (label) = 1;
15215 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15217 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
15218 rtx count, int max_size)
15221 expand_simple_binop (counter_mode (count), AND, count,
15222 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
15223 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
15224 gen_lowpart (QImode, value), count, QImode,
15228 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15230 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
15234 if (CONST_INT_P (count))
15236 HOST_WIDE_INT countval = INTVAL (count);
15239 if ((countval & 0x10) && max_size > 16)
15243 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15244 emit_insn (gen_strset (destptr, dest, value));
15245 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
15246 emit_insn (gen_strset (destptr, dest, value));
15249 gcc_unreachable ();
15252 if ((countval & 0x08) && max_size > 8)
15256 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15257 emit_insn (gen_strset (destptr, dest, value));
15261 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15262 emit_insn (gen_strset (destptr, dest, value));
15263 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15264 emit_insn (gen_strset (destptr, dest, value));
15268 if ((countval & 0x04) && max_size > 4)
15270 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15271 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15274 if ((countval & 0x02) && max_size > 2)
15276 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15277 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15280 if ((countval & 0x01) && max_size > 1)
15282 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15283 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15290 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15295 rtx label = ix86_expand_aligntest (count, 16, true);
15298 dest = change_address (destmem, DImode, destptr);
15299 emit_insn (gen_strset (destptr, dest, value));
15300 emit_insn (gen_strset (destptr, dest, value));
15304 dest = change_address (destmem, SImode, destptr);
15305 emit_insn (gen_strset (destptr, dest, value));
15306 emit_insn (gen_strset (destptr, dest, value));
15307 emit_insn (gen_strset (destptr, dest, value));
15308 emit_insn (gen_strset (destptr, dest, value));
15310 emit_label (label);
15311 LABEL_NUSES (label) = 1;
15315 rtx label = ix86_expand_aligntest (count, 8, true);
15318 dest = change_address (destmem, DImode, destptr);
15319 emit_insn (gen_strset (destptr, dest, value));
15323 dest = change_address (destmem, SImode, destptr);
15324 emit_insn (gen_strset (destptr, dest, value));
15325 emit_insn (gen_strset (destptr, dest, value));
15327 emit_label (label);
15328 LABEL_NUSES (label) = 1;
15332 rtx label = ix86_expand_aligntest (count, 4, true);
15333 dest = change_address (destmem, SImode, destptr);
15334 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15335 emit_label (label);
15336 LABEL_NUSES (label) = 1;
15340 rtx label = ix86_expand_aligntest (count, 2, true);
15341 dest = change_address (destmem, HImode, destptr);
15342 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15343 emit_label (label);
15344 LABEL_NUSES (label) = 1;
15348 rtx label = ix86_expand_aligntest (count, 1, true);
15349 dest = change_address (destmem, QImode, destptr);
15350 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15351 emit_label (label);
15352 LABEL_NUSES (label) = 1;
15356 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15357 DESIRED_ALIGNMENT. */
15359 expand_movmem_prologue (rtx destmem, rtx srcmem,
15360 rtx destptr, rtx srcptr, rtx count,
15361 int align, int desired_alignment)
15363 if (align <= 1 && desired_alignment > 1)
15365 rtx label = ix86_expand_aligntest (destptr, 1, false);
15366 srcmem = change_address (srcmem, QImode, srcptr);
15367 destmem = change_address (destmem, QImode, destptr);
15368 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15369 ix86_adjust_counter (count, 1);
15370 emit_label (label);
15371 LABEL_NUSES (label) = 1;
15373 if (align <= 2 && desired_alignment > 2)
15375 rtx label = ix86_expand_aligntest (destptr, 2, false);
15376 srcmem = change_address (srcmem, HImode, srcptr);
15377 destmem = change_address (destmem, HImode, destptr);
15378 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15379 ix86_adjust_counter (count, 2);
15380 emit_label (label);
15381 LABEL_NUSES (label) = 1;
15383 if (align <= 4 && desired_alignment > 4)
15385 rtx label = ix86_expand_aligntest (destptr, 4, false);
15386 srcmem = change_address (srcmem, SImode, srcptr);
15387 destmem = change_address (destmem, SImode, destptr);
15388 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15389 ix86_adjust_counter (count, 4);
15390 emit_label (label);
15391 LABEL_NUSES (label) = 1;
15393 gcc_assert (desired_alignment <= 8);
15396 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15397 DESIRED_ALIGNMENT. */
15399 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15400 int align, int desired_alignment)
15402 if (align <= 1 && desired_alignment > 1)
15404 rtx label = ix86_expand_aligntest (destptr, 1, false);
15405 destmem = change_address (destmem, QImode, destptr);
15406 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15407 ix86_adjust_counter (count, 1);
15408 emit_label (label);
15409 LABEL_NUSES (label) = 1;
15411 if (align <= 2 && desired_alignment > 2)
15413 rtx label = ix86_expand_aligntest (destptr, 2, false);
15414 destmem = change_address (destmem, HImode, destptr);
15415 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15416 ix86_adjust_counter (count, 2);
15417 emit_label (label);
15418 LABEL_NUSES (label) = 1;
15420 if (align <= 4 && desired_alignment > 4)
15422 rtx label = ix86_expand_aligntest (destptr, 4, false);
15423 destmem = change_address (destmem, SImode, destptr);
15424 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15425 ix86_adjust_counter (count, 4);
15426 emit_label (label);
15427 LABEL_NUSES (label) = 1;
15429 gcc_assert (desired_alignment <= 8);
15432 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15433 static enum stringop_alg
15434 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15435 int *dynamic_check)
15437 const struct stringop_algs * algs;
15438 /* Algorithms using the rep prefix want at least edi and ecx;
15439 additionally, memset wants eax and memcpy wants esi. Don't
15440 consider such algorithms if the user has appropriated those
15441 registers for their own purposes. */
15442 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15444 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15446 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15447 || (alg != rep_prefix_1_byte \
15448 && alg != rep_prefix_4_byte \
15449 && alg != rep_prefix_8_byte))
15451 *dynamic_check = -1;
15453 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15455 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15456 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15457 return stringop_alg;
15458 /* rep; movq or rep; movl is the smallest variant. */
15459 else if (optimize_size)
15461 if (!count || (count & 3))
15462 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15464 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15466 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15468 else if (expected_size != -1 && expected_size < 4)
15469 return loop_1_byte;
15470 else if (expected_size != -1)
15473 enum stringop_alg alg = libcall;
15474 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15476 /* We get here if the algorithms that were not libcall-based
15477 were rep-prefix based and we are unable to use rep prefixes
15478 based on global register usage. Break out of the loop and
15479 use the heuristic below. */
15480 if (algs->size[i].max == 0)
15482 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15484 enum stringop_alg candidate = algs->size[i].alg;
15486 if (candidate != libcall && ALG_USABLE_P (candidate))
15488 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15489 last non-libcall inline algorithm. */
15490 if (TARGET_INLINE_ALL_STRINGOPS)
15492 /* When the current size is best to be copied by a libcall,
15493 but we are still forced to inline, run the heuristic below
15494 that will pick code for medium sized blocks. */
15495 if (alg != libcall)
15499 else if (ALG_USABLE_P (candidate))
15503 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15505 /* When asked to inline the call anyway, try to pick meaningful choice.
15506 We look for maximal size of block that is faster to copy by hand and
15507 take blocks of at most of that size guessing that average size will
15508 be roughly half of the block.
15510 If this turns out to be bad, we might simply specify the preferred
15511 choice in ix86_costs. */
15512 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15513 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15516 enum stringop_alg alg;
15518 bool any_alg_usable_p = true;
15520 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15522 enum stringop_alg candidate = algs->size[i].alg;
15523 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15525 if (candidate != libcall && candidate
15526 && ALG_USABLE_P (candidate))
15527 max = algs->size[i].max;
15529 /* If there aren't any usable algorithms, then recursing on
15530 smaller sizes isn't going to find anything. Just return the
15531 simple byte-at-a-time copy loop. */
15532 if (!any_alg_usable_p)
15534 /* Pick something reasonable. */
15535 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15536 *dynamic_check = 128;
15537 return loop_1_byte;
15541 alg = decide_alg (count, max / 2, memset, dynamic_check);
15542 gcc_assert (*dynamic_check == -1);
15543 gcc_assert (alg != libcall);
15544 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15545 *dynamic_check = max;
15548 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15549 #undef ALG_USABLE_P
15552 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15553 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15555 decide_alignment (int align,
15556 enum stringop_alg alg,
15559 int desired_align = 0;
15563 gcc_unreachable ();
15565 case unrolled_loop:
15566 desired_align = GET_MODE_SIZE (Pmode);
15568 case rep_prefix_8_byte:
15571 case rep_prefix_4_byte:
15572 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15573 copying whole cacheline at once. */
15574 if (TARGET_PENTIUMPRO)
15579 case rep_prefix_1_byte:
15580 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15581 copying whole cacheline at once. */
15582 if (TARGET_PENTIUMPRO)
15596 if (desired_align < align)
15597 desired_align = align;
15598 if (expected_size != -1 && expected_size < 4)
15599 desired_align = align;
15600 return desired_align;
15603 /* Return the smallest power of 2 greater than VAL. */
15605 smallest_pow2_greater_than (int val)
15613 /* Expand string move (memcpy) operation. Use i386 string operations when
15614 profitable. expand_setmem contains similar code. The code depends upon
15615 architecture, block size and alignment, but always has the same
15618 1) Prologue guard: Conditional that jumps up to epilogues for small
15619 blocks that can be handled by epilogue alone. This is faster but
15620 also needed for correctness, since prologue assume the block is larger
15621 than the desired alignment.
15623 Optional dynamic check for size and libcall for large
15624 blocks is emitted here too, with -minline-stringops-dynamically.
15626 2) Prologue: copy first few bytes in order to get destination aligned
15627 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15628 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15629 We emit either a jump tree on power of two sized blocks, or a byte loop.
15631 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15632 with specified algorithm.
15634 4) Epilogue: code copying tail of the block that is too small to be
15635 handled by main body (or up to size guarded by prologue guard). */
15638 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15639 rtx expected_align_exp, rtx expected_size_exp)
15645 rtx jump_around_label = NULL;
15646 HOST_WIDE_INT align = 1;
15647 unsigned HOST_WIDE_INT count = 0;
15648 HOST_WIDE_INT expected_size = -1;
15649 int size_needed = 0, epilogue_size_needed;
15650 int desired_align = 0;
15651 enum stringop_alg alg;
15654 if (CONST_INT_P (align_exp))
15655 align = INTVAL (align_exp);
15656 /* i386 can do misaligned access on reasonably increased cost. */
15657 if (CONST_INT_P (expected_align_exp)
15658 && INTVAL (expected_align_exp) > align)
15659 align = INTVAL (expected_align_exp);
15660 if (CONST_INT_P (count_exp))
15661 count = expected_size = INTVAL (count_exp);
15662 if (CONST_INT_P (expected_size_exp) && count == 0)
15663 expected_size = INTVAL (expected_size_exp);
15665 /* Make sure we don't need to care about overflow later on. */
15666 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15669 /* Step 0: Decide on preferred algorithm, desired alignment and
15670 size of chunks to be copied by main loop. */
15672 alg = decide_alg (count, expected_size, false, &dynamic_check);
15673 desired_align = decide_alignment (align, alg, expected_size);
15675 if (!TARGET_ALIGN_STRINGOPS)
15676 align = desired_align;
15678 if (alg == libcall)
15680 gcc_assert (alg != no_stringop);
15682 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15683 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15684 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15689 gcc_unreachable ();
15691 size_needed = GET_MODE_SIZE (Pmode);
15693 case unrolled_loop:
15694 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15696 case rep_prefix_8_byte:
15699 case rep_prefix_4_byte:
15702 case rep_prefix_1_byte:
15708 epilogue_size_needed = size_needed;
15710 /* Step 1: Prologue guard. */
15712 /* Alignment code needs count to be in register. */
15713 if (CONST_INT_P (count_exp) && desired_align > align)
15714 count_exp = force_reg (counter_mode (count_exp), count_exp);
15715 gcc_assert (desired_align >= 1 && align >= 1);
15717 /* Ensure that alignment prologue won't copy past end of block. */
15718 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15720 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15721 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15722 Make sure it is power of 2. */
15723 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15725 if (CONST_INT_P (count_exp))
15727 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15732 label = gen_label_rtx ();
15733 emit_cmp_and_jump_insns (count_exp,
15734 GEN_INT (epilogue_size_needed),
15735 LTU, 0, counter_mode (count_exp), 1, label);
15736 if (expected_size == -1 || expected_size < epilogue_size_needed)
15737 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15739 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15743 /* Emit code to decide on runtime whether library call or inline should be
15745 if (dynamic_check != -1)
15747 if (CONST_INT_P (count_exp))
15749 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15751 emit_block_move_via_libcall (dst, src, count_exp, false);
15752 count_exp = const0_rtx;
15758 rtx hot_label = gen_label_rtx ();
15759 jump_around_label = gen_label_rtx ();
15760 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15761 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15762 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15763 emit_block_move_via_libcall (dst, src, count_exp, false);
15764 emit_jump (jump_around_label);
15765 emit_label (hot_label);
15769 /* Step 2: Alignment prologue. */
15771 if (desired_align > align)
15773 /* Except for the first move in epilogue, we no longer know
15774 constant offset in aliasing info. It don't seems to worth
15775 the pain to maintain it for the first move, so throw away
15777 src = change_address (src, BLKmode, srcreg);
15778 dst = change_address (dst, BLKmode, destreg);
15779 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15782 if (label && size_needed == 1)
15784 emit_label (label);
15785 LABEL_NUSES (label) = 1;
15789 /* Step 3: Main loop. */
15795 gcc_unreachable ();
15797 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15798 count_exp, QImode, 1, expected_size);
15801 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15802 count_exp, Pmode, 1, expected_size);
15804 case unrolled_loop:
15805 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15806 registers for 4 temporaries anyway. */
15807 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15808 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15811 case rep_prefix_8_byte:
15812 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15815 case rep_prefix_4_byte:
15816 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15819 case rep_prefix_1_byte:
15820 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15824 /* Adjust properly the offset of src and dest memory for aliasing. */
15825 if (CONST_INT_P (count_exp))
15827 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15828 (count / size_needed) * size_needed);
15829 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15830 (count / size_needed) * size_needed);
15834 src = change_address (src, BLKmode, srcreg);
15835 dst = change_address (dst, BLKmode, destreg);
15838 /* Step 4: Epilogue to copy the remaining bytes. */
15842 /* When the main loop is done, COUNT_EXP might hold original count,
15843 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15844 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15845 bytes. Compensate if needed. */
15847 if (size_needed < epilogue_size_needed)
15850 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15851 GEN_INT (size_needed - 1), count_exp, 1,
15853 if (tmp != count_exp)
15854 emit_move_insn (count_exp, tmp);
15856 emit_label (label);
15857 LABEL_NUSES (label) = 1;
15860 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15861 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15862 epilogue_size_needed);
15863 if (jump_around_label)
15864 emit_label (jump_around_label);
15868 /* Helper function for memcpy. For QImode value 0xXY produce
15869 0xXYXYXYXY of wide specified by MODE. This is essentially
15870 a * 0x10101010, but we can do slightly better than
15871 synth_mult by unwinding the sequence by hand on CPUs with
15874 promote_duplicated_reg (enum machine_mode mode, rtx val)
15876 enum machine_mode valmode = GET_MODE (val);
15878 int nops = mode == DImode ? 3 : 2;
15880 gcc_assert (mode == SImode || mode == DImode);
15881 if (val == const0_rtx)
15882 return copy_to_mode_reg (mode, const0_rtx);
15883 if (CONST_INT_P (val))
15885 HOST_WIDE_INT v = INTVAL (val) & 255;
15889 if (mode == DImode)
15890 v |= (v << 16) << 16;
15891 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15894 if (valmode == VOIDmode)
15896 if (valmode != QImode)
15897 val = gen_lowpart (QImode, val);
15898 if (mode == QImode)
15900 if (!TARGET_PARTIAL_REG_STALL)
15902 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15903 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15904 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15905 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15907 rtx reg = convert_modes (mode, QImode, val, true);
15908 tmp = promote_duplicated_reg (mode, const1_rtx);
15909 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15914 rtx reg = convert_modes (mode, QImode, val, true);
15916 if (!TARGET_PARTIAL_REG_STALL)
15917 if (mode == SImode)
15918 emit_insn (gen_movsi_insv_1 (reg, reg));
15920 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15923 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15924 NULL, 1, OPTAB_DIRECT);
15926 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15928 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15929 NULL, 1, OPTAB_DIRECT);
15930 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15931 if (mode == SImode)
15933 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15934 NULL, 1, OPTAB_DIRECT);
15935 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15940 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15941 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15942 alignment from ALIGN to DESIRED_ALIGN. */
15944 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15949 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15950 promoted_val = promote_duplicated_reg (DImode, val);
15951 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15952 promoted_val = promote_duplicated_reg (SImode, val);
15953 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15954 promoted_val = promote_duplicated_reg (HImode, val);
15956 promoted_val = val;
15958 return promoted_val;
15961 /* Expand string clear operation (bzero). Use i386 string operations when
15962 profitable. See expand_movmem comment for explanation of individual
15963 steps performed. */
15965 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15966 rtx expected_align_exp, rtx expected_size_exp)
15971 rtx jump_around_label = NULL;
15972 HOST_WIDE_INT align = 1;
15973 unsigned HOST_WIDE_INT count = 0;
15974 HOST_WIDE_INT expected_size = -1;
15975 int size_needed = 0, epilogue_size_needed;
15976 int desired_align = 0;
15977 enum stringop_alg alg;
15978 rtx promoted_val = NULL;
15979 bool force_loopy_epilogue = false;
15982 if (CONST_INT_P (align_exp))
15983 align = INTVAL (align_exp);
15984 /* i386 can do misaligned access on reasonably increased cost. */
15985 if (CONST_INT_P (expected_align_exp)
15986 && INTVAL (expected_align_exp) > align)
15987 align = INTVAL (expected_align_exp);
15988 if (CONST_INT_P (count_exp))
15989 count = expected_size = INTVAL (count_exp);
15990 if (CONST_INT_P (expected_size_exp) && count == 0)
15991 expected_size = INTVAL (expected_size_exp);
15993 /* Make sure we don't need to care about overflow later on. */
15994 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15997 /* Step 0: Decide on preferred algorithm, desired alignment and
15998 size of chunks to be copied by main loop. */
16000 alg = decide_alg (count, expected_size, true, &dynamic_check);
16001 desired_align = decide_alignment (align, alg, expected_size);
16003 if (!TARGET_ALIGN_STRINGOPS)
16004 align = desired_align;
16006 if (alg == libcall)
16008 gcc_assert (alg != no_stringop);
16010 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
16011 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
16016 gcc_unreachable ();
16018 size_needed = GET_MODE_SIZE (Pmode);
16020 case unrolled_loop:
16021 size_needed = GET_MODE_SIZE (Pmode) * 4;
16023 case rep_prefix_8_byte:
16026 case rep_prefix_4_byte:
16029 case rep_prefix_1_byte:
16034 epilogue_size_needed = size_needed;
16036 /* Step 1: Prologue guard. */
16038 /* Alignment code needs count to be in register. */
16039 if (CONST_INT_P (count_exp) && desired_align > align)
16041 enum machine_mode mode = SImode;
16042 if (TARGET_64BIT && (count & ~0xffffffff))
16044 count_exp = force_reg (mode, count_exp);
16046 /* Do the cheap promotion to allow better CSE across the
16047 main loop and epilogue (ie one load of the big constant in the
16048 front of all code. */
16049 if (CONST_INT_P (val_exp))
16050 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
16051 desired_align, align);
16052 /* Ensure that alignment prologue won't copy past end of block. */
16053 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
16055 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
16056 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
16057 Make sure it is power of 2. */
16058 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
16060 /* To improve performance of small blocks, we jump around the VAL
16061 promoting mode. This mean that if the promoted VAL is not constant,
16062 we might not use it in the epilogue and have to use byte
16064 if (epilogue_size_needed > 2 && !promoted_val)
16065 force_loopy_epilogue = true;
16066 label = gen_label_rtx ();
16067 emit_cmp_and_jump_insns (count_exp,
16068 GEN_INT (epilogue_size_needed),
16069 LTU, 0, counter_mode (count_exp), 1, label);
16070 if (GET_CODE (count_exp) == CONST_INT)
16072 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
16073 predict_jump (REG_BR_PROB_BASE * 60 / 100);
16075 predict_jump (REG_BR_PROB_BASE * 20 / 100);
16077 if (dynamic_check != -1)
16079 rtx hot_label = gen_label_rtx ();
16080 jump_around_label = gen_label_rtx ();
16081 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
16082 LEU, 0, counter_mode (count_exp), 1, hot_label);
16083 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16084 set_storage_via_libcall (dst, count_exp, val_exp, false);
16085 emit_jump (jump_around_label);
16086 emit_label (hot_label);
16089 /* Step 2: Alignment prologue. */
16091 /* Do the expensive promotion once we branched off the small blocks. */
16093 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
16094 desired_align, align);
16095 gcc_assert (desired_align >= 1 && align >= 1);
16097 if (desired_align > align)
16099 /* Except for the first move in epilogue, we no longer know
16100 constant offset in aliasing info. It don't seems to worth
16101 the pain to maintain it for the first move, so throw away
16103 dst = change_address (dst, BLKmode, destreg);
16104 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
16107 if (label && size_needed == 1)
16109 emit_label (label);
16110 LABEL_NUSES (label) = 1;
16114 /* Step 3: Main loop. */
16120 gcc_unreachable ();
16122 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
16123 count_exp, QImode, 1, expected_size);
16126 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
16127 count_exp, Pmode, 1, expected_size);
16129 case unrolled_loop:
16130 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
16131 count_exp, Pmode, 4, expected_size);
16133 case rep_prefix_8_byte:
16134 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16137 case rep_prefix_4_byte:
16138 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16141 case rep_prefix_1_byte:
16142 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16146 /* Adjust properly the offset of src and dest memory for aliasing. */
16147 if (CONST_INT_P (count_exp))
16148 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
16149 (count / size_needed) * size_needed);
16151 dst = change_address (dst, BLKmode, destreg);
16153 /* Step 4: Epilogue to copy the remaining bytes. */
16157 /* When the main loop is done, COUNT_EXP might hold original count,
16158 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
16159 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
16160 bytes. Compensate if needed. */
16162 if (size_needed < desired_align - align)
16165 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
16166 GEN_INT (size_needed - 1), count_exp, 1,
16168 size_needed = desired_align - align + 1;
16169 if (tmp != count_exp)
16170 emit_move_insn (count_exp, tmp);
16172 emit_label (label);
16173 LABEL_NUSES (label) = 1;
16175 if (count_exp != const0_rtx && epilogue_size_needed > 1)
16177 if (force_loopy_epilogue)
16178 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
16181 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
16184 if (jump_around_label)
16185 emit_label (jump_around_label);
16189 /* Expand the appropriate insns for doing strlen if not just doing
16192 out = result, initialized with the start address
16193 align_rtx = alignment of the address.
16194 scratch = scratch register, initialized with the startaddress when
16195 not aligned, otherwise undefined
16197 This is just the body. It needs the initializations mentioned above and
16198 some address computing at the end. These things are done in i386.md. */
16201 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
16205 rtx align_2_label = NULL_RTX;
16206 rtx align_3_label = NULL_RTX;
16207 rtx align_4_label = gen_label_rtx ();
16208 rtx end_0_label = gen_label_rtx ();
16210 rtx tmpreg = gen_reg_rtx (SImode);
16211 rtx scratch = gen_reg_rtx (SImode);
16215 if (CONST_INT_P (align_rtx))
16216 align = INTVAL (align_rtx);
16218 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
16220 /* Is there a known alignment and is it less than 4? */
16223 rtx scratch1 = gen_reg_rtx (Pmode);
16224 emit_move_insn (scratch1, out);
16225 /* Is there a known alignment and is it not 2? */
16228 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
16229 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
16231 /* Leave just the 3 lower bits. */
16232 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
16233 NULL_RTX, 0, OPTAB_WIDEN);
16235 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16236 Pmode, 1, align_4_label);
16237 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
16238 Pmode, 1, align_2_label);
16239 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
16240 Pmode, 1, align_3_label);
16244 /* Since the alignment is 2, we have to check 2 or 0 bytes;
16245 check if is aligned to 4 - byte. */
16247 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
16248 NULL_RTX, 0, OPTAB_WIDEN);
16250 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16251 Pmode, 1, align_4_label);
16254 mem = change_address (src, QImode, out);
16256 /* Now compare the bytes. */
16258 /* Compare the first n unaligned byte on a byte per byte basis. */
16259 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16260 QImode, 1, end_0_label);
16262 /* Increment the address. */
16263 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
16265 /* Not needed with an alignment of 2 */
16268 emit_label (align_2_label);
16270 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16273 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
16275 emit_label (align_3_label);
16278 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16281 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
16284 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16285 align this loop. It gives only huge programs, but does not help to
16287 emit_label (align_4_label);
16289 mem = change_address (src, SImode, out);
16290 emit_move_insn (scratch, mem);
16291 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
16293 /* This formula yields a nonzero result iff one of the bytes is zero.
16294 This saves three branches inside loop and many cycles. */
16296 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16297 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16298 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16299 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16300 gen_int_mode (0x80808080, SImode)));
16301 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16306 rtx reg = gen_reg_rtx (SImode);
16307 rtx reg2 = gen_reg_rtx (Pmode);
16308 emit_move_insn (reg, tmpreg);
16309 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16311 /* If zero is not in the first two bytes, move two bytes forward. */
16312 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16313 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16314 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16315 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16316 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16319 /* Emit lea manually to avoid clobbering of flags. */
16320 emit_insn (gen_rtx_SET (SImode, reg2,
16321 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16323 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16324 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16325 emit_insn (gen_rtx_SET (VOIDmode, out,
16326 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16333 rtx end_2_label = gen_label_rtx ();
16334 /* Is zero in the first two bytes? */
16336 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16337 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16338 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16339 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16340 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16342 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16343 JUMP_LABEL (tmp) = end_2_label;
16345 /* Not in the first two. Move two bytes forward. */
16346 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16347 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
16349 emit_label (end_2_label);
16353 /* Avoid branch in fixing the byte. */
16354 tmpreg = gen_lowpart (QImode, tmpreg);
16355 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16356 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16357 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
16359 emit_label (end_0_label);
16362 /* Expand strlen. */
16365 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16367 rtx addr, scratch1, scratch2, scratch3, scratch4;
16369 /* The generic case of strlen expander is long. Avoid it's
16370 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16372 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16373 && !TARGET_INLINE_ALL_STRINGOPS
16375 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16378 addr = force_reg (Pmode, XEXP (src, 0));
16379 scratch1 = gen_reg_rtx (Pmode);
16381 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16384 /* Well it seems that some optimizer does not combine a call like
16385 foo(strlen(bar), strlen(bar));
16386 when the move and the subtraction is done here. It does calculate
16387 the length just once when these instructions are done inside of
16388 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16389 often used and I use one fewer register for the lifetime of
16390 output_strlen_unroll() this is better. */
16392 emit_move_insn (out, addr);
16394 ix86_expand_strlensi_unroll_1 (out, src, align);
16396 /* strlensi_unroll_1 returns the address of the zero at the end of
16397 the string, like memchr(), so compute the length by subtracting
16398 the start address. */
16399 emit_insn ((*ix86_gen_sub3) (out, out, addr));
16405 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16406 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16409 scratch2 = gen_reg_rtx (Pmode);
16410 scratch3 = gen_reg_rtx (Pmode);
16411 scratch4 = force_reg (Pmode, constm1_rtx);
16413 emit_move_insn (scratch3, addr);
16414 eoschar = force_reg (QImode, eoschar);
16416 src = replace_equiv_address_nv (src, scratch3);
16418 /* If .md starts supporting :P, this can be done in .md. */
16419 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16420 scratch4), UNSPEC_SCAS);
16421 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16422 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
16423 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
16428 /* For given symbol (function) construct code to compute address of it's PLT
16429 entry in large x86-64 PIC model. */
16431 construct_plt_address (rtx symbol)
16433 rtx tmp = gen_reg_rtx (Pmode);
16434 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16436 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16437 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16439 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16440 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16445 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16446 rtx callarg2 ATTRIBUTE_UNUSED,
16447 rtx pop, int sibcall)
16449 rtx use = NULL, call;
16451 if (pop == const0_rtx)
16453 gcc_assert (!TARGET_64BIT || !pop);
16455 if (TARGET_MACHO && !TARGET_64BIT)
16458 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16459 fnaddr = machopic_indirect_call_target (fnaddr);
16464 /* Static functions and indirect calls don't need the pic register. */
16465 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16466 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16467 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16468 use_reg (&use, pic_offset_table_rtx);
16471 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16473 rtx al = gen_rtx_REG (QImode, AX_REG);
16474 emit_move_insn (al, callarg2);
16475 use_reg (&use, al);
16478 if (ix86_cmodel == CM_LARGE_PIC
16479 && GET_CODE (fnaddr) == MEM
16480 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16481 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16482 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16483 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16485 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16486 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16488 if (sibcall && TARGET_64BIT
16489 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16492 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16493 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16494 emit_move_insn (fnaddr, addr);
16495 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16498 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16500 call = gen_rtx_SET (VOIDmode, retval, call);
16503 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16504 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16505 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16508 call = emit_call_insn (call);
16510 CALL_INSN_FUNCTION_USAGE (call) = use;
16514 /* Clear stack slot assignments remembered from previous functions.
16515 This is called from INIT_EXPANDERS once before RTL is emitted for each
16518 static struct machine_function *
16519 ix86_init_machine_status (void)
16521 struct machine_function *f;
16523 f = GGC_CNEW (struct machine_function);
16524 f->use_fast_prologue_epilogue_nregs = -1;
16525 f->tls_descriptor_call_expanded_p = 0;
16526 f->call_abi = DEFAULT_ABI;
16531 /* Return a MEM corresponding to a stack slot with mode MODE.
16532 Allocate a new slot if necessary.
16534 The RTL for a function can have several slots available: N is
16535 which slot to use. */
16538 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16540 struct stack_local_entry *s;
16542 gcc_assert (n < MAX_386_STACK_LOCALS);
16544 /* Virtual slot is valid only before vregs are instantiated. */
16545 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16547 for (s = ix86_stack_locals; s; s = s->next)
16548 if (s->mode == mode && s->n == n)
16549 return copy_rtx (s->rtl);
16551 s = (struct stack_local_entry *)
16552 ggc_alloc (sizeof (struct stack_local_entry));
16555 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16557 s->next = ix86_stack_locals;
16558 ix86_stack_locals = s;
16562 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16564 static GTY(()) rtx ix86_tls_symbol;
16566 ix86_tls_get_addr (void)
16569 if (!ix86_tls_symbol)
16571 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16572 (TARGET_ANY_GNU_TLS
16574 ? "___tls_get_addr"
16575 : "__tls_get_addr");
16578 return ix86_tls_symbol;
16581 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16583 static GTY(()) rtx ix86_tls_module_base_symbol;
16585 ix86_tls_module_base (void)
16588 if (!ix86_tls_module_base_symbol)
16590 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16591 "_TLS_MODULE_BASE_");
16592 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16593 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16596 return ix86_tls_module_base_symbol;
16599 /* Calculate the length of the memory address in the instruction
16600 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16603 memory_address_length (rtx addr)
16605 struct ix86_address parts;
16606 rtx base, index, disp;
16610 if (GET_CODE (addr) == PRE_DEC
16611 || GET_CODE (addr) == POST_INC
16612 || GET_CODE (addr) == PRE_MODIFY
16613 || GET_CODE (addr) == POST_MODIFY)
16616 ok = ix86_decompose_address (addr, &parts);
16619 if (parts.base && GET_CODE (parts.base) == SUBREG)
16620 parts.base = SUBREG_REG (parts.base);
16621 if (parts.index && GET_CODE (parts.index) == SUBREG)
16622 parts.index = SUBREG_REG (parts.index);
16625 index = parts.index;
16630 - esp as the base always wants an index,
16631 - ebp as the base always wants a displacement. */
16633 /* Register Indirect. */
16634 if (base && !index && !disp)
16636 /* esp (for its index) and ebp (for its displacement) need
16637 the two-byte modrm form. */
16638 if (addr == stack_pointer_rtx
16639 || addr == arg_pointer_rtx
16640 || addr == frame_pointer_rtx
16641 || addr == hard_frame_pointer_rtx)
16645 /* Direct Addressing. */
16646 else if (disp && !base && !index)
16651 /* Find the length of the displacement constant. */
16654 if (base && satisfies_constraint_K (disp))
16659 /* ebp always wants a displacement. */
16660 else if (base == hard_frame_pointer_rtx)
16663 /* An index requires the two-byte modrm form.... */
16665 /* ...like esp, which always wants an index. */
16666 || base == stack_pointer_rtx
16667 || base == arg_pointer_rtx
16668 || base == frame_pointer_rtx)
16675 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16676 is set, expect that insn have 8bit immediate alternative. */
16678 ix86_attr_length_immediate_default (rtx insn, int shortform)
16682 extract_insn_cached (insn);
16683 for (i = recog_data.n_operands - 1; i >= 0; --i)
16684 if (CONSTANT_P (recog_data.operand[i]))
16687 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16691 switch (get_attr_mode (insn))
16702 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16707 fatal_insn ("unknown insn mode", insn);
16713 /* Compute default value for "length_address" attribute. */
16715 ix86_attr_length_address_default (rtx insn)
16719 if (get_attr_type (insn) == TYPE_LEA)
16721 rtx set = PATTERN (insn);
16723 if (GET_CODE (set) == PARALLEL)
16724 set = XVECEXP (set, 0, 0);
16726 gcc_assert (GET_CODE (set) == SET);
16728 return memory_address_length (SET_SRC (set));
16731 extract_insn_cached (insn);
16732 for (i = recog_data.n_operands - 1; i >= 0; --i)
16733 if (MEM_P (recog_data.operand[i]))
16735 return memory_address_length (XEXP (recog_data.operand[i], 0));
16741 /* Return the maximum number of instructions a cpu can issue. */
16744 ix86_issue_rate (void)
16748 case PROCESSOR_PENTIUM:
16752 case PROCESSOR_PENTIUMPRO:
16753 case PROCESSOR_PENTIUM4:
16754 case PROCESSOR_ATHLON:
16756 case PROCESSOR_AMDFAM10:
16757 case PROCESSOR_NOCONA:
16758 case PROCESSOR_GENERIC32:
16759 case PROCESSOR_GENERIC64:
16762 case PROCESSOR_CORE2:
16770 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16771 by DEP_INSN and nothing set by DEP_INSN. */
16774 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16778 /* Simplify the test for uninteresting insns. */
16779 if (insn_type != TYPE_SETCC
16780 && insn_type != TYPE_ICMOV
16781 && insn_type != TYPE_FCMOV
16782 && insn_type != TYPE_IBR)
16785 if ((set = single_set (dep_insn)) != 0)
16787 set = SET_DEST (set);
16790 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16791 && XVECLEN (PATTERN (dep_insn), 0) == 2
16792 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16793 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16795 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16796 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16801 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16804 /* This test is true if the dependent insn reads the flags but
16805 not any other potentially set register. */
16806 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16809 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16815 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16816 address with operands set by DEP_INSN. */
16819 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16823 if (insn_type == TYPE_LEA
16826 addr = PATTERN (insn);
16828 if (GET_CODE (addr) == PARALLEL)
16829 addr = XVECEXP (addr, 0, 0);
16831 gcc_assert (GET_CODE (addr) == SET);
16833 addr = SET_SRC (addr);
16838 extract_insn_cached (insn);
16839 for (i = recog_data.n_operands - 1; i >= 0; --i)
16840 if (MEM_P (recog_data.operand[i]))
16842 addr = XEXP (recog_data.operand[i], 0);
16849 return modified_in_p (addr, dep_insn);
16853 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16855 enum attr_type insn_type, dep_insn_type;
16856 enum attr_memory memory;
16858 int dep_insn_code_number;
16860 /* Anti and output dependencies have zero cost on all CPUs. */
16861 if (REG_NOTE_KIND (link) != 0)
16864 dep_insn_code_number = recog_memoized (dep_insn);
16866 /* If we can't recognize the insns, we can't really do anything. */
16867 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16870 insn_type = get_attr_type (insn);
16871 dep_insn_type = get_attr_type (dep_insn);
16875 case PROCESSOR_PENTIUM:
16876 /* Address Generation Interlock adds a cycle of latency. */
16877 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16880 /* ??? Compares pair with jump/setcc. */
16881 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16884 /* Floating point stores require value to be ready one cycle earlier. */
16885 if (insn_type == TYPE_FMOV
16886 && get_attr_memory (insn) == MEMORY_STORE
16887 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16891 case PROCESSOR_PENTIUMPRO:
16892 memory = get_attr_memory (insn);
16894 /* INT->FP conversion is expensive. */
16895 if (get_attr_fp_int_src (dep_insn))
16898 /* There is one cycle extra latency between an FP op and a store. */
16899 if (insn_type == TYPE_FMOV
16900 && (set = single_set (dep_insn)) != NULL_RTX
16901 && (set2 = single_set (insn)) != NULL_RTX
16902 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16903 && MEM_P (SET_DEST (set2)))
16906 /* Show ability of reorder buffer to hide latency of load by executing
16907 in parallel with previous instruction in case
16908 previous instruction is not needed to compute the address. */
16909 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16910 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16912 /* Claim moves to take one cycle, as core can issue one load
16913 at time and the next load can start cycle later. */
16914 if (dep_insn_type == TYPE_IMOV
16915 || dep_insn_type == TYPE_FMOV)
16923 memory = get_attr_memory (insn);
16925 /* The esp dependency is resolved before the instruction is really
16927 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16928 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16931 /* INT->FP conversion is expensive. */
16932 if (get_attr_fp_int_src (dep_insn))
16935 /* Show ability of reorder buffer to hide latency of load by executing
16936 in parallel with previous instruction in case
16937 previous instruction is not needed to compute the address. */
16938 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16939 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16941 /* Claim moves to take one cycle, as core can issue one load
16942 at time and the next load can start cycle later. */
16943 if (dep_insn_type == TYPE_IMOV
16944 || dep_insn_type == TYPE_FMOV)
16953 case PROCESSOR_ATHLON:
16955 case PROCESSOR_AMDFAM10:
16956 case PROCESSOR_GENERIC32:
16957 case PROCESSOR_GENERIC64:
16958 memory = get_attr_memory (insn);
16960 /* Show ability of reorder buffer to hide latency of load by executing
16961 in parallel with previous instruction in case
16962 previous instruction is not needed to compute the address. */
16963 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16964 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16966 enum attr_unit unit = get_attr_unit (insn);
16969 /* Because of the difference between the length of integer and
16970 floating unit pipeline preparation stages, the memory operands
16971 for floating point are cheaper.
16973 ??? For Athlon it the difference is most probably 2. */
16974 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16977 loadcost = TARGET_ATHLON ? 2 : 0;
16979 if (cost >= loadcost)
16992 /* How many alternative schedules to try. This should be as wide as the
16993 scheduling freedom in the DFA, but no wider. Making this value too
16994 large results extra work for the scheduler. */
16997 ia32_multipass_dfa_lookahead (void)
17001 case PROCESSOR_PENTIUM:
17004 case PROCESSOR_PENTIUMPRO:
17014 /* Compute the alignment given to a constant that is being placed in memory.
17015 EXP is the constant and ALIGN is the alignment that the object would
17017 The value of this function is used instead of that alignment to align
17021 ix86_constant_alignment (tree exp, int align)
17023 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
17024 || TREE_CODE (exp) == INTEGER_CST)
17026 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
17028 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
17031 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
17032 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
17033 return BITS_PER_WORD;
17038 /* Compute the alignment for a static variable.
17039 TYPE is the data type, and ALIGN is the alignment that
17040 the object would ordinarily have. The value of this function is used
17041 instead of that alignment to align the object. */
17044 ix86_data_alignment (tree type, int align)
17046 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
17048 if (AGGREGATE_TYPE_P (type)
17049 && TYPE_SIZE (type)
17050 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
17051 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
17052 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
17053 && align < max_align)
17056 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
17057 to 16byte boundary. */
17060 if (AGGREGATE_TYPE_P (type)
17061 && TYPE_SIZE (type)
17062 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
17063 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
17064 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
17068 if (TREE_CODE (type) == ARRAY_TYPE)
17070 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
17072 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
17075 else if (TREE_CODE (type) == COMPLEX_TYPE)
17078 if (TYPE_MODE (type) == DCmode && align < 64)
17080 if (TYPE_MODE (type) == XCmode && align < 128)
17083 else if ((TREE_CODE (type) == RECORD_TYPE
17084 || TREE_CODE (type) == UNION_TYPE
17085 || TREE_CODE (type) == QUAL_UNION_TYPE)
17086 && TYPE_FIELDS (type))
17088 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
17090 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
17093 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
17094 || TREE_CODE (type) == INTEGER_TYPE)
17096 if (TYPE_MODE (type) == DFmode && align < 64)
17098 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
17105 /* Compute the alignment for a local variable or a stack slot. TYPE is
17106 the data type, MODE is the widest mode available and ALIGN is the
17107 alignment that the object would ordinarily have. The value of this
17108 macro is used instead of that alignment to align the object. */
17111 ix86_local_alignment (tree type, enum machine_mode mode,
17112 unsigned int align)
17114 /* If TYPE is NULL, we are allocating a stack slot for caller-save
17115 register in MODE. We will return the largest alignment of XF
17119 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
17120 align = GET_MODE_ALIGNMENT (DFmode);
17124 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
17125 to 16byte boundary. */
17128 if (AGGREGATE_TYPE_P (type)
17129 && TYPE_SIZE (type)
17130 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
17131 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
17132 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
17135 if (TREE_CODE (type) == ARRAY_TYPE)
17137 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
17139 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
17142 else if (TREE_CODE (type) == COMPLEX_TYPE)
17144 if (TYPE_MODE (type) == DCmode && align < 64)
17146 if (TYPE_MODE (type) == XCmode && align < 128)
17149 else if ((TREE_CODE (type) == RECORD_TYPE
17150 || TREE_CODE (type) == UNION_TYPE
17151 || TREE_CODE (type) == QUAL_UNION_TYPE)
17152 && TYPE_FIELDS (type))
17154 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
17156 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
17159 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
17160 || TREE_CODE (type) == INTEGER_TYPE)
17163 if (TYPE_MODE (type) == DFmode && align < 64)
17165 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
17171 /* Emit RTL insns to initialize the variable parts of a trampoline.
17172 FNADDR is an RTX for the address of the function's pure code.
17173 CXT is an RTX for the static chain value for the function. */
17175 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
17179 /* Compute offset from the end of the jmp to the target function. */
17180 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
17181 plus_constant (tramp, 10),
17182 NULL_RTX, 1, OPTAB_DIRECT);
17183 emit_move_insn (gen_rtx_MEM (QImode, tramp),
17184 gen_int_mode (0xb9, QImode));
17185 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
17186 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
17187 gen_int_mode (0xe9, QImode));
17188 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
17193 /* Try to load address using shorter movl instead of movabs.
17194 We may want to support movq for kernel mode, but kernel does not use
17195 trampolines at the moment. */
17196 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
17198 fnaddr = copy_to_mode_reg (DImode, fnaddr);
17199 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17200 gen_int_mode (0xbb41, HImode));
17201 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
17202 gen_lowpart (SImode, fnaddr));
17207 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17208 gen_int_mode (0xbb49, HImode));
17209 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17213 /* Load static chain using movabs to r10. */
17214 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17215 gen_int_mode (0xba49, HImode));
17216 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17219 /* Jump to the r11 */
17220 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17221 gen_int_mode (0xff49, HImode));
17222 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
17223 gen_int_mode (0xe3, QImode));
17225 gcc_assert (offset <= TRAMPOLINE_SIZE);
17228 #ifdef ENABLE_EXECUTE_STACK
17229 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
17230 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
17234 /* Codes for all the SSE/MMX builtins. */
17237 IX86_BUILTIN_ADDPS,
17238 IX86_BUILTIN_ADDSS,
17239 IX86_BUILTIN_DIVPS,
17240 IX86_BUILTIN_DIVSS,
17241 IX86_BUILTIN_MULPS,
17242 IX86_BUILTIN_MULSS,
17243 IX86_BUILTIN_SUBPS,
17244 IX86_BUILTIN_SUBSS,
17246 IX86_BUILTIN_CMPEQPS,
17247 IX86_BUILTIN_CMPLTPS,
17248 IX86_BUILTIN_CMPLEPS,
17249 IX86_BUILTIN_CMPGTPS,
17250 IX86_BUILTIN_CMPGEPS,
17251 IX86_BUILTIN_CMPNEQPS,
17252 IX86_BUILTIN_CMPNLTPS,
17253 IX86_BUILTIN_CMPNLEPS,
17254 IX86_BUILTIN_CMPNGTPS,
17255 IX86_BUILTIN_CMPNGEPS,
17256 IX86_BUILTIN_CMPORDPS,
17257 IX86_BUILTIN_CMPUNORDPS,
17258 IX86_BUILTIN_CMPEQSS,
17259 IX86_BUILTIN_CMPLTSS,
17260 IX86_BUILTIN_CMPLESS,
17261 IX86_BUILTIN_CMPNEQSS,
17262 IX86_BUILTIN_CMPNLTSS,
17263 IX86_BUILTIN_CMPNLESS,
17264 IX86_BUILTIN_CMPNGTSS,
17265 IX86_BUILTIN_CMPNGESS,
17266 IX86_BUILTIN_CMPORDSS,
17267 IX86_BUILTIN_CMPUNORDSS,
17269 IX86_BUILTIN_COMIEQSS,
17270 IX86_BUILTIN_COMILTSS,
17271 IX86_BUILTIN_COMILESS,
17272 IX86_BUILTIN_COMIGTSS,
17273 IX86_BUILTIN_COMIGESS,
17274 IX86_BUILTIN_COMINEQSS,
17275 IX86_BUILTIN_UCOMIEQSS,
17276 IX86_BUILTIN_UCOMILTSS,
17277 IX86_BUILTIN_UCOMILESS,
17278 IX86_BUILTIN_UCOMIGTSS,
17279 IX86_BUILTIN_UCOMIGESS,
17280 IX86_BUILTIN_UCOMINEQSS,
17282 IX86_BUILTIN_CVTPI2PS,
17283 IX86_BUILTIN_CVTPS2PI,
17284 IX86_BUILTIN_CVTSI2SS,
17285 IX86_BUILTIN_CVTSI642SS,
17286 IX86_BUILTIN_CVTSS2SI,
17287 IX86_BUILTIN_CVTSS2SI64,
17288 IX86_BUILTIN_CVTTPS2PI,
17289 IX86_BUILTIN_CVTTSS2SI,
17290 IX86_BUILTIN_CVTTSS2SI64,
17292 IX86_BUILTIN_MAXPS,
17293 IX86_BUILTIN_MAXSS,
17294 IX86_BUILTIN_MINPS,
17295 IX86_BUILTIN_MINSS,
17297 IX86_BUILTIN_LOADUPS,
17298 IX86_BUILTIN_STOREUPS,
17299 IX86_BUILTIN_MOVSS,
17301 IX86_BUILTIN_MOVHLPS,
17302 IX86_BUILTIN_MOVLHPS,
17303 IX86_BUILTIN_LOADHPS,
17304 IX86_BUILTIN_LOADLPS,
17305 IX86_BUILTIN_STOREHPS,
17306 IX86_BUILTIN_STORELPS,
17308 IX86_BUILTIN_MASKMOVQ,
17309 IX86_BUILTIN_MOVMSKPS,
17310 IX86_BUILTIN_PMOVMSKB,
17312 IX86_BUILTIN_MOVNTPS,
17313 IX86_BUILTIN_MOVNTQ,
17315 IX86_BUILTIN_LOADDQU,
17316 IX86_BUILTIN_STOREDQU,
17318 IX86_BUILTIN_PACKSSWB,
17319 IX86_BUILTIN_PACKSSDW,
17320 IX86_BUILTIN_PACKUSWB,
17322 IX86_BUILTIN_PADDB,
17323 IX86_BUILTIN_PADDW,
17324 IX86_BUILTIN_PADDD,
17325 IX86_BUILTIN_PADDQ,
17326 IX86_BUILTIN_PADDSB,
17327 IX86_BUILTIN_PADDSW,
17328 IX86_BUILTIN_PADDUSB,
17329 IX86_BUILTIN_PADDUSW,
17330 IX86_BUILTIN_PSUBB,
17331 IX86_BUILTIN_PSUBW,
17332 IX86_BUILTIN_PSUBD,
17333 IX86_BUILTIN_PSUBQ,
17334 IX86_BUILTIN_PSUBSB,
17335 IX86_BUILTIN_PSUBSW,
17336 IX86_BUILTIN_PSUBUSB,
17337 IX86_BUILTIN_PSUBUSW,
17340 IX86_BUILTIN_PANDN,
17344 IX86_BUILTIN_PAVGB,
17345 IX86_BUILTIN_PAVGW,
17347 IX86_BUILTIN_PCMPEQB,
17348 IX86_BUILTIN_PCMPEQW,
17349 IX86_BUILTIN_PCMPEQD,
17350 IX86_BUILTIN_PCMPGTB,
17351 IX86_BUILTIN_PCMPGTW,
17352 IX86_BUILTIN_PCMPGTD,
17354 IX86_BUILTIN_PMADDWD,
17356 IX86_BUILTIN_PMAXSW,
17357 IX86_BUILTIN_PMAXUB,
17358 IX86_BUILTIN_PMINSW,
17359 IX86_BUILTIN_PMINUB,
17361 IX86_BUILTIN_PMULHUW,
17362 IX86_BUILTIN_PMULHW,
17363 IX86_BUILTIN_PMULLW,
17365 IX86_BUILTIN_PSADBW,
17366 IX86_BUILTIN_PSHUFW,
17368 IX86_BUILTIN_PSLLW,
17369 IX86_BUILTIN_PSLLD,
17370 IX86_BUILTIN_PSLLQ,
17371 IX86_BUILTIN_PSRAW,
17372 IX86_BUILTIN_PSRAD,
17373 IX86_BUILTIN_PSRLW,
17374 IX86_BUILTIN_PSRLD,
17375 IX86_BUILTIN_PSRLQ,
17376 IX86_BUILTIN_PSLLWI,
17377 IX86_BUILTIN_PSLLDI,
17378 IX86_BUILTIN_PSLLQI,
17379 IX86_BUILTIN_PSRAWI,
17380 IX86_BUILTIN_PSRADI,
17381 IX86_BUILTIN_PSRLWI,
17382 IX86_BUILTIN_PSRLDI,
17383 IX86_BUILTIN_PSRLQI,
17385 IX86_BUILTIN_PUNPCKHBW,
17386 IX86_BUILTIN_PUNPCKHWD,
17387 IX86_BUILTIN_PUNPCKHDQ,
17388 IX86_BUILTIN_PUNPCKLBW,
17389 IX86_BUILTIN_PUNPCKLWD,
17390 IX86_BUILTIN_PUNPCKLDQ,
17392 IX86_BUILTIN_SHUFPS,
17394 IX86_BUILTIN_RCPPS,
17395 IX86_BUILTIN_RCPSS,
17396 IX86_BUILTIN_RSQRTPS,
17397 IX86_BUILTIN_RSQRTPS_NR,
17398 IX86_BUILTIN_RSQRTSS,
17399 IX86_BUILTIN_RSQRTF,
17400 IX86_BUILTIN_SQRTPS,
17401 IX86_BUILTIN_SQRTPS_NR,
17402 IX86_BUILTIN_SQRTSS,
17404 IX86_BUILTIN_UNPCKHPS,
17405 IX86_BUILTIN_UNPCKLPS,
17407 IX86_BUILTIN_ANDPS,
17408 IX86_BUILTIN_ANDNPS,
17410 IX86_BUILTIN_XORPS,
17413 IX86_BUILTIN_LDMXCSR,
17414 IX86_BUILTIN_STMXCSR,
17415 IX86_BUILTIN_SFENCE,
17417 /* 3DNow! Original */
17418 IX86_BUILTIN_FEMMS,
17419 IX86_BUILTIN_PAVGUSB,
17420 IX86_BUILTIN_PF2ID,
17421 IX86_BUILTIN_PFACC,
17422 IX86_BUILTIN_PFADD,
17423 IX86_BUILTIN_PFCMPEQ,
17424 IX86_BUILTIN_PFCMPGE,
17425 IX86_BUILTIN_PFCMPGT,
17426 IX86_BUILTIN_PFMAX,
17427 IX86_BUILTIN_PFMIN,
17428 IX86_BUILTIN_PFMUL,
17429 IX86_BUILTIN_PFRCP,
17430 IX86_BUILTIN_PFRCPIT1,
17431 IX86_BUILTIN_PFRCPIT2,
17432 IX86_BUILTIN_PFRSQIT1,
17433 IX86_BUILTIN_PFRSQRT,
17434 IX86_BUILTIN_PFSUB,
17435 IX86_BUILTIN_PFSUBR,
17436 IX86_BUILTIN_PI2FD,
17437 IX86_BUILTIN_PMULHRW,
17439 /* 3DNow! Athlon Extensions */
17440 IX86_BUILTIN_PF2IW,
17441 IX86_BUILTIN_PFNACC,
17442 IX86_BUILTIN_PFPNACC,
17443 IX86_BUILTIN_PI2FW,
17444 IX86_BUILTIN_PSWAPDSI,
17445 IX86_BUILTIN_PSWAPDSF,
17448 IX86_BUILTIN_ADDPD,
17449 IX86_BUILTIN_ADDSD,
17450 IX86_BUILTIN_DIVPD,
17451 IX86_BUILTIN_DIVSD,
17452 IX86_BUILTIN_MULPD,
17453 IX86_BUILTIN_MULSD,
17454 IX86_BUILTIN_SUBPD,
17455 IX86_BUILTIN_SUBSD,
17457 IX86_BUILTIN_CMPEQPD,
17458 IX86_BUILTIN_CMPLTPD,
17459 IX86_BUILTIN_CMPLEPD,
17460 IX86_BUILTIN_CMPGTPD,
17461 IX86_BUILTIN_CMPGEPD,
17462 IX86_BUILTIN_CMPNEQPD,
17463 IX86_BUILTIN_CMPNLTPD,
17464 IX86_BUILTIN_CMPNLEPD,
17465 IX86_BUILTIN_CMPNGTPD,
17466 IX86_BUILTIN_CMPNGEPD,
17467 IX86_BUILTIN_CMPORDPD,
17468 IX86_BUILTIN_CMPUNORDPD,
17469 IX86_BUILTIN_CMPEQSD,
17470 IX86_BUILTIN_CMPLTSD,
17471 IX86_BUILTIN_CMPLESD,
17472 IX86_BUILTIN_CMPNEQSD,
17473 IX86_BUILTIN_CMPNLTSD,
17474 IX86_BUILTIN_CMPNLESD,
17475 IX86_BUILTIN_CMPORDSD,
17476 IX86_BUILTIN_CMPUNORDSD,
17478 IX86_BUILTIN_COMIEQSD,
17479 IX86_BUILTIN_COMILTSD,
17480 IX86_BUILTIN_COMILESD,
17481 IX86_BUILTIN_COMIGTSD,
17482 IX86_BUILTIN_COMIGESD,
17483 IX86_BUILTIN_COMINEQSD,
17484 IX86_BUILTIN_UCOMIEQSD,
17485 IX86_BUILTIN_UCOMILTSD,
17486 IX86_BUILTIN_UCOMILESD,
17487 IX86_BUILTIN_UCOMIGTSD,
17488 IX86_BUILTIN_UCOMIGESD,
17489 IX86_BUILTIN_UCOMINEQSD,
17491 IX86_BUILTIN_MAXPD,
17492 IX86_BUILTIN_MAXSD,
17493 IX86_BUILTIN_MINPD,
17494 IX86_BUILTIN_MINSD,
17496 IX86_BUILTIN_ANDPD,
17497 IX86_BUILTIN_ANDNPD,
17499 IX86_BUILTIN_XORPD,
17501 IX86_BUILTIN_SQRTPD,
17502 IX86_BUILTIN_SQRTSD,
17504 IX86_BUILTIN_UNPCKHPD,
17505 IX86_BUILTIN_UNPCKLPD,
17507 IX86_BUILTIN_SHUFPD,
17509 IX86_BUILTIN_LOADUPD,
17510 IX86_BUILTIN_STOREUPD,
17511 IX86_BUILTIN_MOVSD,
17513 IX86_BUILTIN_LOADHPD,
17514 IX86_BUILTIN_LOADLPD,
17516 IX86_BUILTIN_CVTDQ2PD,
17517 IX86_BUILTIN_CVTDQ2PS,
17519 IX86_BUILTIN_CVTPD2DQ,
17520 IX86_BUILTIN_CVTPD2PI,
17521 IX86_BUILTIN_CVTPD2PS,
17522 IX86_BUILTIN_CVTTPD2DQ,
17523 IX86_BUILTIN_CVTTPD2PI,
17525 IX86_BUILTIN_CVTPI2PD,
17526 IX86_BUILTIN_CVTSI2SD,
17527 IX86_BUILTIN_CVTSI642SD,
17529 IX86_BUILTIN_CVTSD2SI,
17530 IX86_BUILTIN_CVTSD2SI64,
17531 IX86_BUILTIN_CVTSD2SS,
17532 IX86_BUILTIN_CVTSS2SD,
17533 IX86_BUILTIN_CVTTSD2SI,
17534 IX86_BUILTIN_CVTTSD2SI64,
17536 IX86_BUILTIN_CVTPS2DQ,
17537 IX86_BUILTIN_CVTPS2PD,
17538 IX86_BUILTIN_CVTTPS2DQ,
17540 IX86_BUILTIN_MOVNTI,
17541 IX86_BUILTIN_MOVNTPD,
17542 IX86_BUILTIN_MOVNTDQ,
17545 IX86_BUILTIN_MASKMOVDQU,
17546 IX86_BUILTIN_MOVMSKPD,
17547 IX86_BUILTIN_PMOVMSKB128,
17549 IX86_BUILTIN_PACKSSWB128,
17550 IX86_BUILTIN_PACKSSDW128,
17551 IX86_BUILTIN_PACKUSWB128,
17553 IX86_BUILTIN_PADDB128,
17554 IX86_BUILTIN_PADDW128,
17555 IX86_BUILTIN_PADDD128,
17556 IX86_BUILTIN_PADDQ128,
17557 IX86_BUILTIN_PADDSB128,
17558 IX86_BUILTIN_PADDSW128,
17559 IX86_BUILTIN_PADDUSB128,
17560 IX86_BUILTIN_PADDUSW128,
17561 IX86_BUILTIN_PSUBB128,
17562 IX86_BUILTIN_PSUBW128,
17563 IX86_BUILTIN_PSUBD128,
17564 IX86_BUILTIN_PSUBQ128,
17565 IX86_BUILTIN_PSUBSB128,
17566 IX86_BUILTIN_PSUBSW128,
17567 IX86_BUILTIN_PSUBUSB128,
17568 IX86_BUILTIN_PSUBUSW128,
17570 IX86_BUILTIN_PAND128,
17571 IX86_BUILTIN_PANDN128,
17572 IX86_BUILTIN_POR128,
17573 IX86_BUILTIN_PXOR128,
17575 IX86_BUILTIN_PAVGB128,
17576 IX86_BUILTIN_PAVGW128,
17578 IX86_BUILTIN_PCMPEQB128,
17579 IX86_BUILTIN_PCMPEQW128,
17580 IX86_BUILTIN_PCMPEQD128,
17581 IX86_BUILTIN_PCMPGTB128,
17582 IX86_BUILTIN_PCMPGTW128,
17583 IX86_BUILTIN_PCMPGTD128,
17585 IX86_BUILTIN_PMADDWD128,
17587 IX86_BUILTIN_PMAXSW128,
17588 IX86_BUILTIN_PMAXUB128,
17589 IX86_BUILTIN_PMINSW128,
17590 IX86_BUILTIN_PMINUB128,
17592 IX86_BUILTIN_PMULUDQ,
17593 IX86_BUILTIN_PMULUDQ128,
17594 IX86_BUILTIN_PMULHUW128,
17595 IX86_BUILTIN_PMULHW128,
17596 IX86_BUILTIN_PMULLW128,
17598 IX86_BUILTIN_PSADBW128,
17599 IX86_BUILTIN_PSHUFHW,
17600 IX86_BUILTIN_PSHUFLW,
17601 IX86_BUILTIN_PSHUFD,
17603 IX86_BUILTIN_PSLLDQI128,
17604 IX86_BUILTIN_PSLLWI128,
17605 IX86_BUILTIN_PSLLDI128,
17606 IX86_BUILTIN_PSLLQI128,
17607 IX86_BUILTIN_PSRAWI128,
17608 IX86_BUILTIN_PSRADI128,
17609 IX86_BUILTIN_PSRLDQI128,
17610 IX86_BUILTIN_PSRLWI128,
17611 IX86_BUILTIN_PSRLDI128,
17612 IX86_BUILTIN_PSRLQI128,
17614 IX86_BUILTIN_PSLLDQ128,
17615 IX86_BUILTIN_PSLLW128,
17616 IX86_BUILTIN_PSLLD128,
17617 IX86_BUILTIN_PSLLQ128,
17618 IX86_BUILTIN_PSRAW128,
17619 IX86_BUILTIN_PSRAD128,
17620 IX86_BUILTIN_PSRLW128,
17621 IX86_BUILTIN_PSRLD128,
17622 IX86_BUILTIN_PSRLQ128,
17624 IX86_BUILTIN_PUNPCKHBW128,
17625 IX86_BUILTIN_PUNPCKHWD128,
17626 IX86_BUILTIN_PUNPCKHDQ128,
17627 IX86_BUILTIN_PUNPCKHQDQ128,
17628 IX86_BUILTIN_PUNPCKLBW128,
17629 IX86_BUILTIN_PUNPCKLWD128,
17630 IX86_BUILTIN_PUNPCKLDQ128,
17631 IX86_BUILTIN_PUNPCKLQDQ128,
17633 IX86_BUILTIN_CLFLUSH,
17634 IX86_BUILTIN_MFENCE,
17635 IX86_BUILTIN_LFENCE,
17638 IX86_BUILTIN_ADDSUBPS,
17639 IX86_BUILTIN_HADDPS,
17640 IX86_BUILTIN_HSUBPS,
17641 IX86_BUILTIN_MOVSHDUP,
17642 IX86_BUILTIN_MOVSLDUP,
17643 IX86_BUILTIN_ADDSUBPD,
17644 IX86_BUILTIN_HADDPD,
17645 IX86_BUILTIN_HSUBPD,
17646 IX86_BUILTIN_LDDQU,
17648 IX86_BUILTIN_MONITOR,
17649 IX86_BUILTIN_MWAIT,
17652 IX86_BUILTIN_PHADDW,
17653 IX86_BUILTIN_PHADDD,
17654 IX86_BUILTIN_PHADDSW,
17655 IX86_BUILTIN_PHSUBW,
17656 IX86_BUILTIN_PHSUBD,
17657 IX86_BUILTIN_PHSUBSW,
17658 IX86_BUILTIN_PMADDUBSW,
17659 IX86_BUILTIN_PMULHRSW,
17660 IX86_BUILTIN_PSHUFB,
17661 IX86_BUILTIN_PSIGNB,
17662 IX86_BUILTIN_PSIGNW,
17663 IX86_BUILTIN_PSIGND,
17664 IX86_BUILTIN_PALIGNR,
17665 IX86_BUILTIN_PABSB,
17666 IX86_BUILTIN_PABSW,
17667 IX86_BUILTIN_PABSD,
17669 IX86_BUILTIN_PHADDW128,
17670 IX86_BUILTIN_PHADDD128,
17671 IX86_BUILTIN_PHADDSW128,
17672 IX86_BUILTIN_PHSUBW128,
17673 IX86_BUILTIN_PHSUBD128,
17674 IX86_BUILTIN_PHSUBSW128,
17675 IX86_BUILTIN_PMADDUBSW128,
17676 IX86_BUILTIN_PMULHRSW128,
17677 IX86_BUILTIN_PSHUFB128,
17678 IX86_BUILTIN_PSIGNB128,
17679 IX86_BUILTIN_PSIGNW128,
17680 IX86_BUILTIN_PSIGND128,
17681 IX86_BUILTIN_PALIGNR128,
17682 IX86_BUILTIN_PABSB128,
17683 IX86_BUILTIN_PABSW128,
17684 IX86_BUILTIN_PABSD128,
17686 /* AMDFAM10 - SSE4A New Instructions. */
17687 IX86_BUILTIN_MOVNTSD,
17688 IX86_BUILTIN_MOVNTSS,
17689 IX86_BUILTIN_EXTRQI,
17690 IX86_BUILTIN_EXTRQ,
17691 IX86_BUILTIN_INSERTQI,
17692 IX86_BUILTIN_INSERTQ,
17695 IX86_BUILTIN_BLENDPD,
17696 IX86_BUILTIN_BLENDPS,
17697 IX86_BUILTIN_BLENDVPD,
17698 IX86_BUILTIN_BLENDVPS,
17699 IX86_BUILTIN_PBLENDVB128,
17700 IX86_BUILTIN_PBLENDW128,
17705 IX86_BUILTIN_INSERTPS128,
17707 IX86_BUILTIN_MOVNTDQA,
17708 IX86_BUILTIN_MPSADBW128,
17709 IX86_BUILTIN_PACKUSDW128,
17710 IX86_BUILTIN_PCMPEQQ,
17711 IX86_BUILTIN_PHMINPOSUW128,
17713 IX86_BUILTIN_PMAXSB128,
17714 IX86_BUILTIN_PMAXSD128,
17715 IX86_BUILTIN_PMAXUD128,
17716 IX86_BUILTIN_PMAXUW128,
17718 IX86_BUILTIN_PMINSB128,
17719 IX86_BUILTIN_PMINSD128,
17720 IX86_BUILTIN_PMINUD128,
17721 IX86_BUILTIN_PMINUW128,
17723 IX86_BUILTIN_PMOVSXBW128,
17724 IX86_BUILTIN_PMOVSXBD128,
17725 IX86_BUILTIN_PMOVSXBQ128,
17726 IX86_BUILTIN_PMOVSXWD128,
17727 IX86_BUILTIN_PMOVSXWQ128,
17728 IX86_BUILTIN_PMOVSXDQ128,
17730 IX86_BUILTIN_PMOVZXBW128,
17731 IX86_BUILTIN_PMOVZXBD128,
17732 IX86_BUILTIN_PMOVZXBQ128,
17733 IX86_BUILTIN_PMOVZXWD128,
17734 IX86_BUILTIN_PMOVZXWQ128,
17735 IX86_BUILTIN_PMOVZXDQ128,
17737 IX86_BUILTIN_PMULDQ128,
17738 IX86_BUILTIN_PMULLD128,
17740 IX86_BUILTIN_ROUNDPD,
17741 IX86_BUILTIN_ROUNDPS,
17742 IX86_BUILTIN_ROUNDSD,
17743 IX86_BUILTIN_ROUNDSS,
17745 IX86_BUILTIN_PTESTZ,
17746 IX86_BUILTIN_PTESTC,
17747 IX86_BUILTIN_PTESTNZC,
17749 IX86_BUILTIN_VEC_INIT_V2SI,
17750 IX86_BUILTIN_VEC_INIT_V4HI,
17751 IX86_BUILTIN_VEC_INIT_V8QI,
17752 IX86_BUILTIN_VEC_EXT_V2DF,
17753 IX86_BUILTIN_VEC_EXT_V2DI,
17754 IX86_BUILTIN_VEC_EXT_V4SF,
17755 IX86_BUILTIN_VEC_EXT_V4SI,
17756 IX86_BUILTIN_VEC_EXT_V8HI,
17757 IX86_BUILTIN_VEC_EXT_V2SI,
17758 IX86_BUILTIN_VEC_EXT_V4HI,
17759 IX86_BUILTIN_VEC_EXT_V16QI,
17760 IX86_BUILTIN_VEC_SET_V2DI,
17761 IX86_BUILTIN_VEC_SET_V4SF,
17762 IX86_BUILTIN_VEC_SET_V4SI,
17763 IX86_BUILTIN_VEC_SET_V8HI,
17764 IX86_BUILTIN_VEC_SET_V4HI,
17765 IX86_BUILTIN_VEC_SET_V16QI,
17767 IX86_BUILTIN_VEC_PACK_SFIX,
17770 IX86_BUILTIN_CRC32QI,
17771 IX86_BUILTIN_CRC32HI,
17772 IX86_BUILTIN_CRC32SI,
17773 IX86_BUILTIN_CRC32DI,
17775 IX86_BUILTIN_PCMPESTRI128,
17776 IX86_BUILTIN_PCMPESTRM128,
17777 IX86_BUILTIN_PCMPESTRA128,
17778 IX86_BUILTIN_PCMPESTRC128,
17779 IX86_BUILTIN_PCMPESTRO128,
17780 IX86_BUILTIN_PCMPESTRS128,
17781 IX86_BUILTIN_PCMPESTRZ128,
17782 IX86_BUILTIN_PCMPISTRI128,
17783 IX86_BUILTIN_PCMPISTRM128,
17784 IX86_BUILTIN_PCMPISTRA128,
17785 IX86_BUILTIN_PCMPISTRC128,
17786 IX86_BUILTIN_PCMPISTRO128,
17787 IX86_BUILTIN_PCMPISTRS128,
17788 IX86_BUILTIN_PCMPISTRZ128,
17790 IX86_BUILTIN_PCMPGTQ,
17792 /* AES instructions */
17793 IX86_BUILTIN_AESENC128,
17794 IX86_BUILTIN_AESENCLAST128,
17795 IX86_BUILTIN_AESDEC128,
17796 IX86_BUILTIN_AESDECLAST128,
17797 IX86_BUILTIN_AESIMC128,
17798 IX86_BUILTIN_AESKEYGENASSIST128,
17800 /* PCLMUL instruction */
17801 IX86_BUILTIN_PCLMULQDQ128,
17803 /* TFmode support builtins. */
17805 IX86_BUILTIN_FABSQ,
17806 IX86_BUILTIN_COPYSIGNQ,
17808 /* SSE5 instructions */
17809 IX86_BUILTIN_FMADDSS,
17810 IX86_BUILTIN_FMADDSD,
17811 IX86_BUILTIN_FMADDPS,
17812 IX86_BUILTIN_FMADDPD,
17813 IX86_BUILTIN_FMSUBSS,
17814 IX86_BUILTIN_FMSUBSD,
17815 IX86_BUILTIN_FMSUBPS,
17816 IX86_BUILTIN_FMSUBPD,
17817 IX86_BUILTIN_FNMADDSS,
17818 IX86_BUILTIN_FNMADDSD,
17819 IX86_BUILTIN_FNMADDPS,
17820 IX86_BUILTIN_FNMADDPD,
17821 IX86_BUILTIN_FNMSUBSS,
17822 IX86_BUILTIN_FNMSUBSD,
17823 IX86_BUILTIN_FNMSUBPS,
17824 IX86_BUILTIN_FNMSUBPD,
17825 IX86_BUILTIN_PCMOV_V2DI,
17826 IX86_BUILTIN_PCMOV_V4SI,
17827 IX86_BUILTIN_PCMOV_V8HI,
17828 IX86_BUILTIN_PCMOV_V16QI,
17829 IX86_BUILTIN_PCMOV_V4SF,
17830 IX86_BUILTIN_PCMOV_V2DF,
17831 IX86_BUILTIN_PPERM,
17832 IX86_BUILTIN_PERMPS,
17833 IX86_BUILTIN_PERMPD,
17834 IX86_BUILTIN_PMACSSWW,
17835 IX86_BUILTIN_PMACSWW,
17836 IX86_BUILTIN_PMACSSWD,
17837 IX86_BUILTIN_PMACSWD,
17838 IX86_BUILTIN_PMACSSDD,
17839 IX86_BUILTIN_PMACSDD,
17840 IX86_BUILTIN_PMACSSDQL,
17841 IX86_BUILTIN_PMACSSDQH,
17842 IX86_BUILTIN_PMACSDQL,
17843 IX86_BUILTIN_PMACSDQH,
17844 IX86_BUILTIN_PMADCSSWD,
17845 IX86_BUILTIN_PMADCSWD,
17846 IX86_BUILTIN_PHADDBW,
17847 IX86_BUILTIN_PHADDBD,
17848 IX86_BUILTIN_PHADDBQ,
17849 IX86_BUILTIN_PHADDWD,
17850 IX86_BUILTIN_PHADDWQ,
17851 IX86_BUILTIN_PHADDDQ,
17852 IX86_BUILTIN_PHADDUBW,
17853 IX86_BUILTIN_PHADDUBD,
17854 IX86_BUILTIN_PHADDUBQ,
17855 IX86_BUILTIN_PHADDUWD,
17856 IX86_BUILTIN_PHADDUWQ,
17857 IX86_BUILTIN_PHADDUDQ,
17858 IX86_BUILTIN_PHSUBBW,
17859 IX86_BUILTIN_PHSUBWD,
17860 IX86_BUILTIN_PHSUBDQ,
17861 IX86_BUILTIN_PROTB,
17862 IX86_BUILTIN_PROTW,
17863 IX86_BUILTIN_PROTD,
17864 IX86_BUILTIN_PROTQ,
17865 IX86_BUILTIN_PROTB_IMM,
17866 IX86_BUILTIN_PROTW_IMM,
17867 IX86_BUILTIN_PROTD_IMM,
17868 IX86_BUILTIN_PROTQ_IMM,
17869 IX86_BUILTIN_PSHLB,
17870 IX86_BUILTIN_PSHLW,
17871 IX86_BUILTIN_PSHLD,
17872 IX86_BUILTIN_PSHLQ,
17873 IX86_BUILTIN_PSHAB,
17874 IX86_BUILTIN_PSHAW,
17875 IX86_BUILTIN_PSHAD,
17876 IX86_BUILTIN_PSHAQ,
17877 IX86_BUILTIN_FRCZSS,
17878 IX86_BUILTIN_FRCZSD,
17879 IX86_BUILTIN_FRCZPS,
17880 IX86_BUILTIN_FRCZPD,
17881 IX86_BUILTIN_CVTPH2PS,
17882 IX86_BUILTIN_CVTPS2PH,
17884 IX86_BUILTIN_COMEQSS,
17885 IX86_BUILTIN_COMNESS,
17886 IX86_BUILTIN_COMLTSS,
17887 IX86_BUILTIN_COMLESS,
17888 IX86_BUILTIN_COMGTSS,
17889 IX86_BUILTIN_COMGESS,
17890 IX86_BUILTIN_COMUEQSS,
17891 IX86_BUILTIN_COMUNESS,
17892 IX86_BUILTIN_COMULTSS,
17893 IX86_BUILTIN_COMULESS,
17894 IX86_BUILTIN_COMUGTSS,
17895 IX86_BUILTIN_COMUGESS,
17896 IX86_BUILTIN_COMORDSS,
17897 IX86_BUILTIN_COMUNORDSS,
17898 IX86_BUILTIN_COMFALSESS,
17899 IX86_BUILTIN_COMTRUESS,
17901 IX86_BUILTIN_COMEQSD,
17902 IX86_BUILTIN_COMNESD,
17903 IX86_BUILTIN_COMLTSD,
17904 IX86_BUILTIN_COMLESD,
17905 IX86_BUILTIN_COMGTSD,
17906 IX86_BUILTIN_COMGESD,
17907 IX86_BUILTIN_COMUEQSD,
17908 IX86_BUILTIN_COMUNESD,
17909 IX86_BUILTIN_COMULTSD,
17910 IX86_BUILTIN_COMULESD,
17911 IX86_BUILTIN_COMUGTSD,
17912 IX86_BUILTIN_COMUGESD,
17913 IX86_BUILTIN_COMORDSD,
17914 IX86_BUILTIN_COMUNORDSD,
17915 IX86_BUILTIN_COMFALSESD,
17916 IX86_BUILTIN_COMTRUESD,
17918 IX86_BUILTIN_COMEQPS,
17919 IX86_BUILTIN_COMNEPS,
17920 IX86_BUILTIN_COMLTPS,
17921 IX86_BUILTIN_COMLEPS,
17922 IX86_BUILTIN_COMGTPS,
17923 IX86_BUILTIN_COMGEPS,
17924 IX86_BUILTIN_COMUEQPS,
17925 IX86_BUILTIN_COMUNEPS,
17926 IX86_BUILTIN_COMULTPS,
17927 IX86_BUILTIN_COMULEPS,
17928 IX86_BUILTIN_COMUGTPS,
17929 IX86_BUILTIN_COMUGEPS,
17930 IX86_BUILTIN_COMORDPS,
17931 IX86_BUILTIN_COMUNORDPS,
17932 IX86_BUILTIN_COMFALSEPS,
17933 IX86_BUILTIN_COMTRUEPS,
17935 IX86_BUILTIN_COMEQPD,
17936 IX86_BUILTIN_COMNEPD,
17937 IX86_BUILTIN_COMLTPD,
17938 IX86_BUILTIN_COMLEPD,
17939 IX86_BUILTIN_COMGTPD,
17940 IX86_BUILTIN_COMGEPD,
17941 IX86_BUILTIN_COMUEQPD,
17942 IX86_BUILTIN_COMUNEPD,
17943 IX86_BUILTIN_COMULTPD,
17944 IX86_BUILTIN_COMULEPD,
17945 IX86_BUILTIN_COMUGTPD,
17946 IX86_BUILTIN_COMUGEPD,
17947 IX86_BUILTIN_COMORDPD,
17948 IX86_BUILTIN_COMUNORDPD,
17949 IX86_BUILTIN_COMFALSEPD,
17950 IX86_BUILTIN_COMTRUEPD,
17952 IX86_BUILTIN_PCOMEQUB,
17953 IX86_BUILTIN_PCOMNEUB,
17954 IX86_BUILTIN_PCOMLTUB,
17955 IX86_BUILTIN_PCOMLEUB,
17956 IX86_BUILTIN_PCOMGTUB,
17957 IX86_BUILTIN_PCOMGEUB,
17958 IX86_BUILTIN_PCOMFALSEUB,
17959 IX86_BUILTIN_PCOMTRUEUB,
17960 IX86_BUILTIN_PCOMEQUW,
17961 IX86_BUILTIN_PCOMNEUW,
17962 IX86_BUILTIN_PCOMLTUW,
17963 IX86_BUILTIN_PCOMLEUW,
17964 IX86_BUILTIN_PCOMGTUW,
17965 IX86_BUILTIN_PCOMGEUW,
17966 IX86_BUILTIN_PCOMFALSEUW,
17967 IX86_BUILTIN_PCOMTRUEUW,
17968 IX86_BUILTIN_PCOMEQUD,
17969 IX86_BUILTIN_PCOMNEUD,
17970 IX86_BUILTIN_PCOMLTUD,
17971 IX86_BUILTIN_PCOMLEUD,
17972 IX86_BUILTIN_PCOMGTUD,
17973 IX86_BUILTIN_PCOMGEUD,
17974 IX86_BUILTIN_PCOMFALSEUD,
17975 IX86_BUILTIN_PCOMTRUEUD,
17976 IX86_BUILTIN_PCOMEQUQ,
17977 IX86_BUILTIN_PCOMNEUQ,
17978 IX86_BUILTIN_PCOMLTUQ,
17979 IX86_BUILTIN_PCOMLEUQ,
17980 IX86_BUILTIN_PCOMGTUQ,
17981 IX86_BUILTIN_PCOMGEUQ,
17982 IX86_BUILTIN_PCOMFALSEUQ,
17983 IX86_BUILTIN_PCOMTRUEUQ,
17985 IX86_BUILTIN_PCOMEQB,
17986 IX86_BUILTIN_PCOMNEB,
17987 IX86_BUILTIN_PCOMLTB,
17988 IX86_BUILTIN_PCOMLEB,
17989 IX86_BUILTIN_PCOMGTB,
17990 IX86_BUILTIN_PCOMGEB,
17991 IX86_BUILTIN_PCOMFALSEB,
17992 IX86_BUILTIN_PCOMTRUEB,
17993 IX86_BUILTIN_PCOMEQW,
17994 IX86_BUILTIN_PCOMNEW,
17995 IX86_BUILTIN_PCOMLTW,
17996 IX86_BUILTIN_PCOMLEW,
17997 IX86_BUILTIN_PCOMGTW,
17998 IX86_BUILTIN_PCOMGEW,
17999 IX86_BUILTIN_PCOMFALSEW,
18000 IX86_BUILTIN_PCOMTRUEW,
18001 IX86_BUILTIN_PCOMEQD,
18002 IX86_BUILTIN_PCOMNED,
18003 IX86_BUILTIN_PCOMLTD,
18004 IX86_BUILTIN_PCOMLED,
18005 IX86_BUILTIN_PCOMGTD,
18006 IX86_BUILTIN_PCOMGED,
18007 IX86_BUILTIN_PCOMFALSED,
18008 IX86_BUILTIN_PCOMTRUED,
18009 IX86_BUILTIN_PCOMEQQ,
18010 IX86_BUILTIN_PCOMNEQ,
18011 IX86_BUILTIN_PCOMLTQ,
18012 IX86_BUILTIN_PCOMLEQ,
18013 IX86_BUILTIN_PCOMGTQ,
18014 IX86_BUILTIN_PCOMGEQ,
18015 IX86_BUILTIN_PCOMFALSEQ,
18016 IX86_BUILTIN_PCOMTRUEQ,
18021 /* Table for the ix86 builtin decls. */
18022 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
18024 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
18025 * if the target_flags include one of MASK. Stores the function decl
18026 * in the ix86_builtins array.
18027 * Returns the function decl or NULL_TREE, if the builtin was not added. */
18030 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
18032 tree decl = NULL_TREE;
18034 if (mask & ix86_isa_flags
18035 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
18037 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
18039 ix86_builtins[(int) code] = decl;
18045 /* Like def_builtin, but also marks the function decl "const". */
18048 def_builtin_const (int mask, const char *name, tree type,
18049 enum ix86_builtins code)
18051 tree decl = def_builtin (mask, name, type, code);
18053 TREE_READONLY (decl) = 1;
18057 /* Bits for builtin_description.flag. */
18059 /* Set when we don't support the comparison natively, and should
18060 swap_comparison in order to support it. */
18061 #define BUILTIN_DESC_SWAP_OPERANDS 1
18063 struct builtin_description
18065 const unsigned int mask;
18066 const enum insn_code icode;
18067 const char *const name;
18068 const enum ix86_builtins code;
18069 const enum rtx_code comparison;
18073 static const struct builtin_description bdesc_comi[] =
18075 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
18076 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
18077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
18078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
18079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
18080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
18081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
18082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
18083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
18084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
18085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
18086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
18087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
18088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
18089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
18090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
18091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
18092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
18093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
18094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
18095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
18096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
18097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
18098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
18101 static const struct builtin_description bdesc_pcmpestr[] =
18104 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
18105 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
18106 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
18107 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
18108 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
18109 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
18110 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
18113 static const struct builtin_description bdesc_pcmpistr[] =
18116 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
18117 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
18118 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
18119 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
18120 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
18121 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
18122 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
18125 /* Special builtin types */
18126 enum ix86_special_builtin_type
18128 SPECIAL_FTYPE_UNKNOWN,
18130 V16QI_FTYPE_PCCHAR,
18131 V4SF_FTYPE_PCFLOAT,
18132 V2DF_FTYPE_PCDOUBLE,
18133 V4SF_FTYPE_V4SF_PCV2SF,
18134 V2DF_FTYPE_V2DF_PCDOUBLE,
18136 VOID_FTYPE_PV2SF_V4SF,
18137 VOID_FTYPE_PV2DI_V2DI,
18138 VOID_FTYPE_PCHAR_V16QI,
18139 VOID_FTYPE_PFLOAT_V4SF,
18140 VOID_FTYPE_PDOUBLE_V2DF,
18142 VOID_FTYPE_PINT_INT
18145 /* Builtin types */
18146 enum ix86_builtin_type
18149 FLOAT128_FTYPE_FLOAT128,
18151 FLOAT128_FTYPE_FLOAT128_FLOAT128,
18152 INT_FTYPE_V2DI_V2DI_PTEST,
18170 V4SF_FTYPE_V4SF_VEC_MERGE,
18178 V2DF_FTYPE_V2DF_VEC_MERGE,
18188 V16QI_FTYPE_V16QI_V16QI,
18189 V16QI_FTYPE_V8HI_V8HI,
18190 V8QI_FTYPE_V8QI_V8QI,
18191 V8QI_FTYPE_V4HI_V4HI,
18192 V8HI_FTYPE_V8HI_V8HI,
18193 V8HI_FTYPE_V8HI_V8HI_COUNT,
18194 V8HI_FTYPE_V16QI_V16QI,
18195 V8HI_FTYPE_V4SI_V4SI,
18196 V8HI_FTYPE_V8HI_SI_COUNT,
18197 V4SI_FTYPE_V4SI_V4SI,
18198 V4SI_FTYPE_V4SI_V4SI_COUNT,
18199 V4SI_FTYPE_V8HI_V8HI,
18200 V4SI_FTYPE_V4SF_V4SF,
18201 V4SI_FTYPE_V2DF_V2DF,
18202 V4SI_FTYPE_V4SI_SI_COUNT,
18203 V4HI_FTYPE_V4HI_V4HI,
18204 V4HI_FTYPE_V4HI_V4HI_COUNT,
18205 V4HI_FTYPE_V8QI_V8QI,
18206 V4HI_FTYPE_V2SI_V2SI,
18207 V4HI_FTYPE_V4HI_SI_COUNT,
18208 V4SF_FTYPE_V4SF_V4SF,
18209 V4SF_FTYPE_V4SF_V4SF_SWAP,
18210 V4SF_FTYPE_V4SF_V2SI,
18211 V4SF_FTYPE_V4SF_V2DF,
18212 V4SF_FTYPE_V4SF_DI,
18213 V4SF_FTYPE_V4SF_SI,
18214 V2DI_FTYPE_V2DI_V2DI,
18215 V2DI_FTYPE_V2DI_V2DI_COUNT,
18216 V2DI_FTYPE_V16QI_V16QI,
18217 V2DI_FTYPE_V4SI_V4SI,
18218 V2DI_FTYPE_V2DI_V16QI,
18219 V2DI_FTYPE_V2DF_V2DF,
18220 V2DI_FTYPE_V2DI_SI_COUNT,
18221 V2SI_FTYPE_V2SI_V2SI,
18222 V2SI_FTYPE_V2SI_V2SI_COUNT,
18223 V2SI_FTYPE_V4HI_V4HI,
18224 V2SI_FTYPE_V2SF_V2SF,
18225 V2SI_FTYPE_V2SI_SI_COUNT,
18226 V2DF_FTYPE_V2DF_V2DF,
18227 V2DF_FTYPE_V2DF_V2DF_SWAP,
18228 V2DF_FTYPE_V2DF_V4SF,
18229 V2DF_FTYPE_V2DF_DI,
18230 V2DF_FTYPE_V2DF_SI,
18231 V2SF_FTYPE_V2SF_V2SF,
18232 V1DI_FTYPE_V1DI_V1DI,
18233 V1DI_FTYPE_V1DI_V1DI_COUNT,
18234 V1DI_FTYPE_V8QI_V8QI,
18235 V1DI_FTYPE_V2SI_V2SI,
18236 V1DI_FTYPE_V1DI_SI_COUNT,
18237 UINT64_FTYPE_UINT64_UINT64,
18238 UINT_FTYPE_UINT_UINT,
18239 UINT_FTYPE_UINT_USHORT,
18240 UINT_FTYPE_UINT_UCHAR,
18241 V8HI_FTYPE_V8HI_INT,
18242 V4SI_FTYPE_V4SI_INT,
18243 V4HI_FTYPE_V4HI_INT,
18244 V4SF_FTYPE_V4SF_INT,
18245 V2DI_FTYPE_V2DI_INT,
18246 V2DI2TI_FTYPE_V2DI_INT,
18247 V2DF_FTYPE_V2DF_INT,
18248 V16QI_FTYPE_V16QI_V16QI_V16QI,
18249 V4SF_FTYPE_V4SF_V4SF_V4SF,
18250 V2DF_FTYPE_V2DF_V2DF_V2DF,
18251 V16QI_FTYPE_V16QI_V16QI_INT,
18252 V8HI_FTYPE_V8HI_V8HI_INT,
18253 V4SI_FTYPE_V4SI_V4SI_INT,
18254 V4SF_FTYPE_V4SF_V4SF_INT,
18255 V2DI_FTYPE_V2DI_V2DI_INT,
18256 V2DI2TI_FTYPE_V2DI_V2DI_INT,
18257 V1DI2DI_FTYPE_V1DI_V1DI_INT,
18258 V2DF_FTYPE_V2DF_V2DF_INT,
18259 V2DI_FTYPE_V2DI_UINT_UINT,
18260 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
18263 /* Special builtins with variable number of arguments. */
18264 static const struct builtin_description bdesc_special_args[] =
18267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
18270 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
18273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18275 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
18277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
18278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
18279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
18280 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
18282 /* SSE or 3DNow!A */
18283 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18284 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
18287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
18291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
18293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
18294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
18295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
18297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
18298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
18301 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
18304 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
18307 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18308 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18311 /* Builtins with variable number of arguments. */
18312 static const struct builtin_description bdesc_args[] =
18315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18337 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18342 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18343 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18344 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18346 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18347 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18348 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18349 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18350 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
18351 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
18353 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
18354 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
18355 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
18357 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
18359 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18360 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18361 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
18362 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18363 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18364 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
18366 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18367 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18368 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
18369 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18370 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18371 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
18373 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18374 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18375 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18376 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18379 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18380 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18381 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18382 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18384 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18385 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18386 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18387 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18388 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18389 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18390 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18391 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18392 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18393 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18394 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18395 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18396 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18397 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18398 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18401 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18402 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18403 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18404 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18405 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18406 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
18410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18411 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18413 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18417 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18420 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18424 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18425 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18426 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18430 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
18434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
18435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
18436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
18440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
18441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
18442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
18444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
18446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
18447 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
18448 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18449 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
18450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
18451 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
18452 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18453 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18454 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18456 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18457 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18458 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18459 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18461 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18462 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18463 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18464 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18466 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18467 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18468 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18469 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18470 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18472 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
18473 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
18474 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
18476 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
18478 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18479 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18480 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18482 /* SSE MMX or 3Dnow!A */
18483 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18484 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18485 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18487 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18488 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18489 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18490 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18492 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
18493 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
18495 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
18498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
18501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
18502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
18503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
18504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
18506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
18509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
18514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18516 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18517 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
18521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18523 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18524 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18525 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18526 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
18533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
18534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
18535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
18537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
18539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
18540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
18541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
18545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
18546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
18547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
18549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
18550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
18551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18554 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18558 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18560 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18561 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18563 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18567 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
18569 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18570 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18571 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18572 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18573 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18574 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18575 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18576 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18587 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18588 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
18590 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18592 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18593 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18595 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18598 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18602 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18605 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18606 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18607 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18619 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
18620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
18621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
18623 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
18626 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
18627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
18629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
18631 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
18632 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
18633 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
18634 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
18636 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
18637 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18638 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18639 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
18640 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18641 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18642 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
18644 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
18645 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18646 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18647 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
18648 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18649 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18650 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
18652 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18653 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18654 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18655 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18657 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
18658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
18659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
18661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
18664 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
18665 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
18668 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
18669 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18671 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18672 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18673 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18674 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18675 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18676 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
18680 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
18681 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18682 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
18683 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
18684 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18686 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18687 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18688 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18689 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18690 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18691 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18692 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18693 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18694 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18695 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18696 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18697 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18698 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
18699 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
18700 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18701 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18702 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18703 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18704 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18705 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18706 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18707 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18708 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18709 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18712 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
18713 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
18716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18717 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
18719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
18720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
18724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
18725 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
18727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18728 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18729 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18730 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18731 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18732 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18733 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18734 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18735 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18736 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18737 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18738 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18739 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18741 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
18742 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18743 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18744 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18745 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18746 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18747 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18748 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18749 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18750 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18751 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
18752 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18754 /* SSE4.1 and SSE5 */
18755 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
18756 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
18757 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18758 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18760 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18761 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18762 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18765 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18766 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
18767 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
18768 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
18769 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
18772 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
18773 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
18774 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
18775 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18778 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
18779 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
18781 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18782 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18783 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18784 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18787 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
18790 { OPTION_MASK_ISA_64BIT, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
18791 { OPTION_MASK_ISA_64BIT, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
18795 enum multi_arg_type {
18805 MULTI_ARG_3_PERMPS,
18806 MULTI_ARG_3_PERMPD,
18813 MULTI_ARG_2_DI_IMM,
18814 MULTI_ARG_2_SI_IMM,
18815 MULTI_ARG_2_HI_IMM,
18816 MULTI_ARG_2_QI_IMM,
18817 MULTI_ARG_2_SF_CMP,
18818 MULTI_ARG_2_DF_CMP,
18819 MULTI_ARG_2_DI_CMP,
18820 MULTI_ARG_2_SI_CMP,
18821 MULTI_ARG_2_HI_CMP,
18822 MULTI_ARG_2_QI_CMP,
18845 static const struct builtin_description bdesc_multi_arg[] =
18847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18848 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18850 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18852 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18853 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18858 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18860 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18865 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18866 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18868 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18870 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18873 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18874 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18876 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18881 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18882 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18884 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18887 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18889 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18890 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18892 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18893 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18895 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18897 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18899 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18900 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18903 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18905 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18908 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18909 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18910 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18911 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18913 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18917 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18918 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18919 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18920 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18921 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18927 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18928 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18929 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18930 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18935 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18938 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18943 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18944 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18947 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18951 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18957 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18958 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18959 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18960 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18961 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18962 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18963 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18964 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18965 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18966 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18969 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18977 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18978 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18979 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18980 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18981 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18982 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18983 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18984 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18985 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18986 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18987 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18988 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18989 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18991 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18992 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18993 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18994 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18995 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18996 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18997 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18999 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
19000 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
19001 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
19002 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
19003 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
19004 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
19005 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
19007 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
19008 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
19009 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
19010 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
19011 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
19012 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
19013 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
19015 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
19016 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
19017 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
19018 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
19019 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
19020 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
19021 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
19023 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
19024 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
19025 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
19026 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
19027 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
19028 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
19029 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
19031 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
19032 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
19033 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
19034 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
19035 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
19036 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
19037 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
19039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
19040 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
19041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
19042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
19043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
19044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
19045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
19047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
19048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
19049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
19050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
19051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
19052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
19053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
19055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
19056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
19057 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
19058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
19059 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
19060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
19061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
19062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
19064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
19065 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
19066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
19067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
19068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
19069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
19070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
19071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
19073 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
19074 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
19075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
19076 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
19077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
19078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
19079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
19080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
19083 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
19084 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
19087 ix86_init_mmx_sse_builtins (void)
19089 const struct builtin_description * d;
19092 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
19093 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
19094 tree V1DI_type_node
19095 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
19096 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
19097 tree V2DI_type_node
19098 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
19099 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
19100 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
19101 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
19102 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
19103 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
19104 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
19106 tree pchar_type_node = build_pointer_type (char_type_node);
19107 tree pcchar_type_node
19108 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
19109 tree pfloat_type_node = build_pointer_type (float_type_node);
19110 tree pcfloat_type_node
19111 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
19112 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
19113 tree pcv2sf_type_node
19114 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
19115 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
19116 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
19119 tree int_ftype_v4sf_v4sf
19120 = build_function_type_list (integer_type_node,
19121 V4SF_type_node, V4SF_type_node, NULL_TREE);
19122 tree v4si_ftype_v4sf_v4sf
19123 = build_function_type_list (V4SI_type_node,
19124 V4SF_type_node, V4SF_type_node, NULL_TREE);
19125 /* MMX/SSE/integer conversions. */
19126 tree int_ftype_v4sf
19127 = build_function_type_list (integer_type_node,
19128 V4SF_type_node, NULL_TREE);
19129 tree int64_ftype_v4sf
19130 = build_function_type_list (long_long_integer_type_node,
19131 V4SF_type_node, NULL_TREE);
19132 tree int_ftype_v8qi
19133 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
19134 tree v4sf_ftype_v4sf_int
19135 = build_function_type_list (V4SF_type_node,
19136 V4SF_type_node, integer_type_node, NULL_TREE);
19137 tree v4sf_ftype_v4sf_int64
19138 = build_function_type_list (V4SF_type_node,
19139 V4SF_type_node, long_long_integer_type_node,
19141 tree v4sf_ftype_v4sf_v2si
19142 = build_function_type_list (V4SF_type_node,
19143 V4SF_type_node, V2SI_type_node, NULL_TREE);
19145 /* Miscellaneous. */
19146 tree v8qi_ftype_v4hi_v4hi
19147 = build_function_type_list (V8QI_type_node,
19148 V4HI_type_node, V4HI_type_node, NULL_TREE);
19149 tree v4hi_ftype_v2si_v2si
19150 = build_function_type_list (V4HI_type_node,
19151 V2SI_type_node, V2SI_type_node, NULL_TREE);
19152 tree v4sf_ftype_v4sf_v4sf_int
19153 = build_function_type_list (V4SF_type_node,
19154 V4SF_type_node, V4SF_type_node,
19155 integer_type_node, NULL_TREE);
19156 tree v2si_ftype_v4hi_v4hi
19157 = build_function_type_list (V2SI_type_node,
19158 V4HI_type_node, V4HI_type_node, NULL_TREE);
19159 tree v4hi_ftype_v4hi_int
19160 = build_function_type_list (V4HI_type_node,
19161 V4HI_type_node, integer_type_node, NULL_TREE);
19162 tree v2si_ftype_v2si_int
19163 = build_function_type_list (V2SI_type_node,
19164 V2SI_type_node, integer_type_node, NULL_TREE);
19165 tree v1di_ftype_v1di_int
19166 = build_function_type_list (V1DI_type_node,
19167 V1DI_type_node, integer_type_node, NULL_TREE);
19169 tree void_ftype_void
19170 = build_function_type (void_type_node, void_list_node);
19171 tree void_ftype_unsigned
19172 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
19173 tree void_ftype_unsigned_unsigned
19174 = build_function_type_list (void_type_node, unsigned_type_node,
19175 unsigned_type_node, NULL_TREE);
19176 tree void_ftype_pcvoid_unsigned_unsigned
19177 = build_function_type_list (void_type_node, const_ptr_type_node,
19178 unsigned_type_node, unsigned_type_node,
19180 tree unsigned_ftype_void
19181 = build_function_type (unsigned_type_node, void_list_node);
19182 tree v2si_ftype_v4sf
19183 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
19184 /* Loads/stores. */
19185 tree void_ftype_v8qi_v8qi_pchar
19186 = build_function_type_list (void_type_node,
19187 V8QI_type_node, V8QI_type_node,
19188 pchar_type_node, NULL_TREE);
19189 tree v4sf_ftype_pcfloat
19190 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
19191 tree v4sf_ftype_v4sf_pcv2sf
19192 = build_function_type_list (V4SF_type_node,
19193 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
19194 tree void_ftype_pv2sf_v4sf
19195 = build_function_type_list (void_type_node,
19196 pv2sf_type_node, V4SF_type_node, NULL_TREE);
19197 tree void_ftype_pfloat_v4sf
19198 = build_function_type_list (void_type_node,
19199 pfloat_type_node, V4SF_type_node, NULL_TREE);
19200 tree void_ftype_pdi_di
19201 = build_function_type_list (void_type_node,
19202 pdi_type_node, long_long_unsigned_type_node,
19204 tree void_ftype_pv2di_v2di
19205 = build_function_type_list (void_type_node,
19206 pv2di_type_node, V2DI_type_node, NULL_TREE);
19207 /* Normal vector unops. */
19208 tree v4sf_ftype_v4sf
19209 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
19210 tree v16qi_ftype_v16qi
19211 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
19212 tree v8hi_ftype_v8hi
19213 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
19214 tree v4si_ftype_v4si
19215 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
19216 tree v8qi_ftype_v8qi
19217 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
19218 tree v4hi_ftype_v4hi
19219 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
19221 /* Normal vector binops. */
19222 tree v4sf_ftype_v4sf_v4sf
19223 = build_function_type_list (V4SF_type_node,
19224 V4SF_type_node, V4SF_type_node, NULL_TREE);
19225 tree v8qi_ftype_v8qi_v8qi
19226 = build_function_type_list (V8QI_type_node,
19227 V8QI_type_node, V8QI_type_node, NULL_TREE);
19228 tree v4hi_ftype_v4hi_v4hi
19229 = build_function_type_list (V4HI_type_node,
19230 V4HI_type_node, V4HI_type_node, NULL_TREE);
19231 tree v2si_ftype_v2si_v2si
19232 = build_function_type_list (V2SI_type_node,
19233 V2SI_type_node, V2SI_type_node, NULL_TREE);
19234 tree v1di_ftype_v1di_v1di
19235 = build_function_type_list (V1DI_type_node,
19236 V1DI_type_node, V1DI_type_node, NULL_TREE);
19237 tree v1di_ftype_v1di_v1di_int
19238 = build_function_type_list (V1DI_type_node,
19239 V1DI_type_node, V1DI_type_node,
19240 integer_type_node, NULL_TREE);
19241 tree v2si_ftype_v2sf
19242 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
19243 tree v2sf_ftype_v2si
19244 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
19245 tree v2si_ftype_v2si
19246 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
19247 tree v2sf_ftype_v2sf
19248 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
19249 tree v2sf_ftype_v2sf_v2sf
19250 = build_function_type_list (V2SF_type_node,
19251 V2SF_type_node, V2SF_type_node, NULL_TREE);
19252 tree v2si_ftype_v2sf_v2sf
19253 = build_function_type_list (V2SI_type_node,
19254 V2SF_type_node, V2SF_type_node, NULL_TREE);
19255 tree pint_type_node = build_pointer_type (integer_type_node);
19256 tree pdouble_type_node = build_pointer_type (double_type_node);
19257 tree pcdouble_type_node = build_pointer_type (
19258 build_type_variant (double_type_node, 1, 0));
19259 tree int_ftype_v2df_v2df
19260 = build_function_type_list (integer_type_node,
19261 V2DF_type_node, V2DF_type_node, NULL_TREE);
19263 tree void_ftype_pcvoid
19264 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
19265 tree v4sf_ftype_v4si
19266 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
19267 tree v4si_ftype_v4sf
19268 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
19269 tree v2df_ftype_v4si
19270 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
19271 tree v4si_ftype_v2df
19272 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
19273 tree v4si_ftype_v2df_v2df
19274 = build_function_type_list (V4SI_type_node,
19275 V2DF_type_node, V2DF_type_node, NULL_TREE);
19276 tree v2si_ftype_v2df
19277 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
19278 tree v4sf_ftype_v2df
19279 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
19280 tree v2df_ftype_v2si
19281 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
19282 tree v2df_ftype_v4sf
19283 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
19284 tree int_ftype_v2df
19285 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
19286 tree int64_ftype_v2df
19287 = build_function_type_list (long_long_integer_type_node,
19288 V2DF_type_node, NULL_TREE);
19289 tree v2df_ftype_v2df_int
19290 = build_function_type_list (V2DF_type_node,
19291 V2DF_type_node, integer_type_node, NULL_TREE);
19292 tree v2df_ftype_v2df_int64
19293 = build_function_type_list (V2DF_type_node,
19294 V2DF_type_node, long_long_integer_type_node,
19296 tree v4sf_ftype_v4sf_v2df
19297 = build_function_type_list (V4SF_type_node,
19298 V4SF_type_node, V2DF_type_node, NULL_TREE);
19299 tree v2df_ftype_v2df_v4sf
19300 = build_function_type_list (V2DF_type_node,
19301 V2DF_type_node, V4SF_type_node, NULL_TREE);
19302 tree v2df_ftype_v2df_v2df_int
19303 = build_function_type_list (V2DF_type_node,
19304 V2DF_type_node, V2DF_type_node,
19307 tree v2df_ftype_v2df_pcdouble
19308 = build_function_type_list (V2DF_type_node,
19309 V2DF_type_node, pcdouble_type_node, NULL_TREE);
19310 tree void_ftype_pdouble_v2df
19311 = build_function_type_list (void_type_node,
19312 pdouble_type_node, V2DF_type_node, NULL_TREE);
19313 tree void_ftype_pint_int
19314 = build_function_type_list (void_type_node,
19315 pint_type_node, integer_type_node, NULL_TREE);
19316 tree void_ftype_v16qi_v16qi_pchar
19317 = build_function_type_list (void_type_node,
19318 V16QI_type_node, V16QI_type_node,
19319 pchar_type_node, NULL_TREE);
19320 tree v2df_ftype_pcdouble
19321 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
19322 tree v2df_ftype_v2df_v2df
19323 = build_function_type_list (V2DF_type_node,
19324 V2DF_type_node, V2DF_type_node, NULL_TREE);
19325 tree v16qi_ftype_v16qi_v16qi
19326 = build_function_type_list (V16QI_type_node,
19327 V16QI_type_node, V16QI_type_node, NULL_TREE);
19328 tree v8hi_ftype_v8hi_v8hi
19329 = build_function_type_list (V8HI_type_node,
19330 V8HI_type_node, V8HI_type_node, NULL_TREE);
19331 tree v4si_ftype_v4si_v4si
19332 = build_function_type_list (V4SI_type_node,
19333 V4SI_type_node, V4SI_type_node, NULL_TREE);
19334 tree v2di_ftype_v2di_v2di
19335 = build_function_type_list (V2DI_type_node,
19336 V2DI_type_node, V2DI_type_node, NULL_TREE);
19337 tree v2di_ftype_v2df_v2df
19338 = build_function_type_list (V2DI_type_node,
19339 V2DF_type_node, V2DF_type_node, NULL_TREE);
19340 tree v2df_ftype_v2df
19341 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
19342 tree v2di_ftype_v2di_int
19343 = build_function_type_list (V2DI_type_node,
19344 V2DI_type_node, integer_type_node, NULL_TREE);
19345 tree v2di_ftype_v2di_v2di_int
19346 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19347 V2DI_type_node, integer_type_node, NULL_TREE);
19348 tree v4si_ftype_v4si_int
19349 = build_function_type_list (V4SI_type_node,
19350 V4SI_type_node, integer_type_node, NULL_TREE);
19351 tree v8hi_ftype_v8hi_int
19352 = build_function_type_list (V8HI_type_node,
19353 V8HI_type_node, integer_type_node, NULL_TREE);
19354 tree v4si_ftype_v8hi_v8hi
19355 = build_function_type_list (V4SI_type_node,
19356 V8HI_type_node, V8HI_type_node, NULL_TREE);
19357 tree v1di_ftype_v8qi_v8qi
19358 = build_function_type_list (V1DI_type_node,
19359 V8QI_type_node, V8QI_type_node, NULL_TREE);
19360 tree v1di_ftype_v2si_v2si
19361 = build_function_type_list (V1DI_type_node,
19362 V2SI_type_node, V2SI_type_node, NULL_TREE);
19363 tree v2di_ftype_v16qi_v16qi
19364 = build_function_type_list (V2DI_type_node,
19365 V16QI_type_node, V16QI_type_node, NULL_TREE);
19366 tree v2di_ftype_v4si_v4si
19367 = build_function_type_list (V2DI_type_node,
19368 V4SI_type_node, V4SI_type_node, NULL_TREE);
19369 tree int_ftype_v16qi
19370 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
19371 tree v16qi_ftype_pcchar
19372 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
19373 tree void_ftype_pchar_v16qi
19374 = build_function_type_list (void_type_node,
19375 pchar_type_node, V16QI_type_node, NULL_TREE);
19377 tree v2di_ftype_v2di_unsigned_unsigned
19378 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19379 unsigned_type_node, unsigned_type_node,
19381 tree v2di_ftype_v2di_v2di_unsigned_unsigned
19382 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
19383 unsigned_type_node, unsigned_type_node,
19385 tree v2di_ftype_v2di_v16qi
19386 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
19388 tree v2df_ftype_v2df_v2df_v2df
19389 = build_function_type_list (V2DF_type_node,
19390 V2DF_type_node, V2DF_type_node,
19391 V2DF_type_node, NULL_TREE);
19392 tree v4sf_ftype_v4sf_v4sf_v4sf
19393 = build_function_type_list (V4SF_type_node,
19394 V4SF_type_node, V4SF_type_node,
19395 V4SF_type_node, NULL_TREE);
19396 tree v8hi_ftype_v16qi
19397 = build_function_type_list (V8HI_type_node, V16QI_type_node,
19399 tree v4si_ftype_v16qi
19400 = build_function_type_list (V4SI_type_node, V16QI_type_node,
19402 tree v2di_ftype_v16qi
19403 = build_function_type_list (V2DI_type_node, V16QI_type_node,
19405 tree v4si_ftype_v8hi
19406 = build_function_type_list (V4SI_type_node, V8HI_type_node,
19408 tree v2di_ftype_v8hi
19409 = build_function_type_list (V2DI_type_node, V8HI_type_node,
19411 tree v2di_ftype_v4si
19412 = build_function_type_list (V2DI_type_node, V4SI_type_node,
19414 tree v2di_ftype_pv2di
19415 = build_function_type_list (V2DI_type_node, pv2di_type_node,
19417 tree v16qi_ftype_v16qi_v16qi_int
19418 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19419 V16QI_type_node, integer_type_node,
19421 tree v16qi_ftype_v16qi_v16qi_v16qi
19422 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19423 V16QI_type_node, V16QI_type_node,
19425 tree v8hi_ftype_v8hi_v8hi_int
19426 = build_function_type_list (V8HI_type_node, V8HI_type_node,
19427 V8HI_type_node, integer_type_node,
19429 tree v4si_ftype_v4si_v4si_int
19430 = build_function_type_list (V4SI_type_node, V4SI_type_node,
19431 V4SI_type_node, integer_type_node,
19433 tree int_ftype_v2di_v2di
19434 = build_function_type_list (integer_type_node,
19435 V2DI_type_node, V2DI_type_node,
19437 tree int_ftype_v16qi_int_v16qi_int_int
19438 = build_function_type_list (integer_type_node,
19445 tree v16qi_ftype_v16qi_int_v16qi_int_int
19446 = build_function_type_list (V16QI_type_node,
19453 tree int_ftype_v16qi_v16qi_int
19454 = build_function_type_list (integer_type_node,
19460 /* SSE5 instructions */
19461 tree v2di_ftype_v2di_v2di_v2di
19462 = build_function_type_list (V2DI_type_node,
19468 tree v4si_ftype_v4si_v4si_v4si
19469 = build_function_type_list (V4SI_type_node,
19475 tree v4si_ftype_v4si_v4si_v2di
19476 = build_function_type_list (V4SI_type_node,
19482 tree v8hi_ftype_v8hi_v8hi_v8hi
19483 = build_function_type_list (V8HI_type_node,
19489 tree v8hi_ftype_v8hi_v8hi_v4si
19490 = build_function_type_list (V8HI_type_node,
19496 tree v2df_ftype_v2df_v2df_v16qi
19497 = build_function_type_list (V2DF_type_node,
19503 tree v4sf_ftype_v4sf_v4sf_v16qi
19504 = build_function_type_list (V4SF_type_node,
19510 tree v2di_ftype_v2di_si
19511 = build_function_type_list (V2DI_type_node,
19516 tree v4si_ftype_v4si_si
19517 = build_function_type_list (V4SI_type_node,
19522 tree v8hi_ftype_v8hi_si
19523 = build_function_type_list (V8HI_type_node,
19528 tree v16qi_ftype_v16qi_si
19529 = build_function_type_list (V16QI_type_node,
19533 tree v4sf_ftype_v4hi
19534 = build_function_type_list (V4SF_type_node,
19538 tree v4hi_ftype_v4sf
19539 = build_function_type_list (V4HI_type_node,
19543 tree v2di_ftype_v2di
19544 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19546 tree v16qi_ftype_v8hi_v8hi
19547 = build_function_type_list (V16QI_type_node,
19548 V8HI_type_node, V8HI_type_node,
19550 tree v8hi_ftype_v4si_v4si
19551 = build_function_type_list (V8HI_type_node,
19552 V4SI_type_node, V4SI_type_node,
19554 tree v8hi_ftype_v16qi_v16qi
19555 = build_function_type_list (V8HI_type_node,
19556 V16QI_type_node, V16QI_type_node,
19558 tree v4hi_ftype_v8qi_v8qi
19559 = build_function_type_list (V4HI_type_node,
19560 V8QI_type_node, V8QI_type_node,
19562 tree unsigned_ftype_unsigned_uchar
19563 = build_function_type_list (unsigned_type_node,
19564 unsigned_type_node,
19565 unsigned_char_type_node,
19567 tree unsigned_ftype_unsigned_ushort
19568 = build_function_type_list (unsigned_type_node,
19569 unsigned_type_node,
19570 short_unsigned_type_node,
19572 tree unsigned_ftype_unsigned_unsigned
19573 = build_function_type_list (unsigned_type_node,
19574 unsigned_type_node,
19575 unsigned_type_node,
19577 tree uint64_ftype_uint64_uint64
19578 = build_function_type_list (long_long_unsigned_type_node,
19579 long_long_unsigned_type_node,
19580 long_long_unsigned_type_node,
19582 tree float_ftype_float
19583 = build_function_type_list (float_type_node,
19589 /* The __float80 type. */
19590 if (TYPE_MODE (long_double_type_node) == XFmode)
19591 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19595 /* The __float80 type. */
19596 tree float80_type_node = make_node (REAL_TYPE);
19598 TYPE_PRECISION (float80_type_node) = 80;
19599 layout_type (float80_type_node);
19600 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19606 tree float128_type_node = make_node (REAL_TYPE);
19608 TYPE_PRECISION (float128_type_node) = 128;
19609 layout_type (float128_type_node);
19610 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19613 /* TFmode support builtins. */
19614 ftype = build_function_type (float128_type_node,
19616 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19618 ftype = build_function_type_list (float128_type_node,
19619 float128_type_node,
19621 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19623 ftype = build_function_type_list (float128_type_node,
19624 float128_type_node,
19625 float128_type_node,
19627 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19630 /* Add all special builtins with variable number of operands. */
19631 for (i = 0, d = bdesc_special_args;
19632 i < ARRAY_SIZE (bdesc_special_args);
19640 switch ((enum ix86_special_builtin_type) d->flag)
19642 case VOID_FTYPE_VOID:
19643 type = void_ftype_void;
19645 case V16QI_FTYPE_PCCHAR:
19646 type = v16qi_ftype_pcchar;
19648 case V4SF_FTYPE_PCFLOAT:
19649 type = v4sf_ftype_pcfloat;
19651 case V2DI_FTYPE_PV2DI:
19652 type = v2di_ftype_pv2di;
19654 case V2DF_FTYPE_PCDOUBLE:
19655 type = v2df_ftype_pcdouble;
19657 case V4SF_FTYPE_V4SF_PCV2SF:
19658 type = v4sf_ftype_v4sf_pcv2sf;
19660 case V2DF_FTYPE_V2DF_PCDOUBLE:
19661 type = v2df_ftype_v2df_pcdouble;
19663 case VOID_FTYPE_PV2SF_V4SF:
19664 type = void_ftype_pv2sf_v4sf;
19666 case VOID_FTYPE_PV2DI_V2DI:
19667 type = void_ftype_pv2di_v2di;
19669 case VOID_FTYPE_PCHAR_V16QI:
19670 type = void_ftype_pchar_v16qi;
19672 case VOID_FTYPE_PFLOAT_V4SF:
19673 type = void_ftype_pfloat_v4sf;
19675 case VOID_FTYPE_PDOUBLE_V2DF:
19676 type = void_ftype_pdouble_v2df;
19678 case VOID_FTYPE_PDI_DI:
19679 type = void_ftype_pdi_di;
19681 case VOID_FTYPE_PINT_INT:
19682 type = void_ftype_pint_int;
19685 gcc_unreachable ();
19688 def_builtin (d->mask, d->name, type, d->code);
19691 /* Add all builtins with variable number of operands. */
19692 for (i = 0, d = bdesc_args;
19693 i < ARRAY_SIZE (bdesc_args);
19701 switch ((enum ix86_builtin_type) d->flag)
19703 case FLOAT_FTYPE_FLOAT:
19704 type = float_ftype_float;
19706 case INT_FTYPE_V2DI_V2DI_PTEST:
19707 type = int_ftype_v2di_v2di;
19709 case INT64_FTYPE_V4SF:
19710 type = int64_ftype_v4sf;
19712 case INT64_FTYPE_V2DF:
19713 type = int64_ftype_v2df;
19715 case INT_FTYPE_V16QI:
19716 type = int_ftype_v16qi;
19718 case INT_FTYPE_V8QI:
19719 type = int_ftype_v8qi;
19721 case INT_FTYPE_V4SF:
19722 type = int_ftype_v4sf;
19724 case INT_FTYPE_V2DF:
19725 type = int_ftype_v2df;
19727 case V16QI_FTYPE_V16QI:
19728 type = v16qi_ftype_v16qi;
19730 case V8HI_FTYPE_V8HI:
19731 type = v8hi_ftype_v8hi;
19733 case V8HI_FTYPE_V16QI:
19734 type = v8hi_ftype_v16qi;
19736 case V8QI_FTYPE_V8QI:
19737 type = v8qi_ftype_v8qi;
19739 case V4SI_FTYPE_V4SI:
19740 type = v4si_ftype_v4si;
19742 case V4SI_FTYPE_V16QI:
19743 type = v4si_ftype_v16qi;
19745 case V4SI_FTYPE_V8HI:
19746 type = v4si_ftype_v8hi;
19748 case V4SI_FTYPE_V4SF:
19749 type = v4si_ftype_v4sf;
19751 case V4SI_FTYPE_V2DF:
19752 type = v4si_ftype_v2df;
19754 case V4HI_FTYPE_V4HI:
19755 type = v4hi_ftype_v4hi;
19757 case V4SF_FTYPE_V4SF:
19758 case V4SF_FTYPE_V4SF_VEC_MERGE:
19759 type = v4sf_ftype_v4sf;
19761 case V4SF_FTYPE_V4SI:
19762 type = v4sf_ftype_v4si;
19764 case V4SF_FTYPE_V2DF:
19765 type = v4sf_ftype_v2df;
19767 case V2DI_FTYPE_V2DI:
19768 type = v2di_ftype_v2di;
19770 case V2DI_FTYPE_V16QI:
19771 type = v2di_ftype_v16qi;
19773 case V2DI_FTYPE_V8HI:
19774 type = v2di_ftype_v8hi;
19776 case V2DI_FTYPE_V4SI:
19777 type = v2di_ftype_v4si;
19779 case V2SI_FTYPE_V2SI:
19780 type = v2si_ftype_v2si;
19782 case V2SI_FTYPE_V4SF:
19783 type = v2si_ftype_v4sf;
19785 case V2SI_FTYPE_V2DF:
19786 type = v2si_ftype_v2df;
19788 case V2SI_FTYPE_V2SF:
19789 type = v2si_ftype_v2sf;
19791 case V2DF_FTYPE_V4SF:
19792 type = v2df_ftype_v4sf;
19794 case V2DF_FTYPE_V2DF:
19795 case V2DF_FTYPE_V2DF_VEC_MERGE:
19796 type = v2df_ftype_v2df;
19798 case V2DF_FTYPE_V2SI:
19799 type = v2df_ftype_v2si;
19801 case V2DF_FTYPE_V4SI:
19802 type = v2df_ftype_v4si;
19804 case V2SF_FTYPE_V2SF:
19805 type = v2sf_ftype_v2sf;
19807 case V2SF_FTYPE_V2SI:
19808 type = v2sf_ftype_v2si;
19810 case V16QI_FTYPE_V16QI_V16QI:
19811 type = v16qi_ftype_v16qi_v16qi;
19813 case V16QI_FTYPE_V8HI_V8HI:
19814 type = v16qi_ftype_v8hi_v8hi;
19816 case V8QI_FTYPE_V8QI_V8QI:
19817 type = v8qi_ftype_v8qi_v8qi;
19819 case V8QI_FTYPE_V4HI_V4HI:
19820 type = v8qi_ftype_v4hi_v4hi;
19822 case V8HI_FTYPE_V8HI_V8HI:
19823 case V8HI_FTYPE_V8HI_V8HI_COUNT:
19824 type = v8hi_ftype_v8hi_v8hi;
19826 case V8HI_FTYPE_V16QI_V16QI:
19827 type = v8hi_ftype_v16qi_v16qi;
19829 case V8HI_FTYPE_V4SI_V4SI:
19830 type = v8hi_ftype_v4si_v4si;
19832 case V8HI_FTYPE_V8HI_SI_COUNT:
19833 type = v8hi_ftype_v8hi_int;
19835 case V4SI_FTYPE_V4SI_V4SI:
19836 case V4SI_FTYPE_V4SI_V4SI_COUNT:
19837 type = v4si_ftype_v4si_v4si;
19839 case V4SI_FTYPE_V8HI_V8HI:
19840 type = v4si_ftype_v8hi_v8hi;
19842 case V4SI_FTYPE_V4SF_V4SF:
19843 type = v4si_ftype_v4sf_v4sf;
19845 case V4SI_FTYPE_V2DF_V2DF:
19846 type = v4si_ftype_v2df_v2df;
19848 case V4SI_FTYPE_V4SI_SI_COUNT:
19849 type = v4si_ftype_v4si_int;
19851 case V4HI_FTYPE_V4HI_V4HI:
19852 case V4HI_FTYPE_V4HI_V4HI_COUNT:
19853 type = v4hi_ftype_v4hi_v4hi;
19855 case V4HI_FTYPE_V8QI_V8QI:
19856 type = v4hi_ftype_v8qi_v8qi;
19858 case V4HI_FTYPE_V2SI_V2SI:
19859 type = v4hi_ftype_v2si_v2si;
19861 case V4HI_FTYPE_V4HI_SI_COUNT:
19862 type = v4hi_ftype_v4hi_int;
19864 case V4SF_FTYPE_V4SF_V4SF:
19865 case V4SF_FTYPE_V4SF_V4SF_SWAP:
19866 type = v4sf_ftype_v4sf_v4sf;
19868 case V4SF_FTYPE_V4SF_V2SI:
19869 type = v4sf_ftype_v4sf_v2si;
19871 case V4SF_FTYPE_V4SF_V2DF:
19872 type = v4sf_ftype_v4sf_v2df;
19874 case V4SF_FTYPE_V4SF_DI:
19875 type = v4sf_ftype_v4sf_int64;
19877 case V4SF_FTYPE_V4SF_SI:
19878 type = v4sf_ftype_v4sf_int;
19880 case V2DI_FTYPE_V2DI_V2DI:
19881 case V2DI_FTYPE_V2DI_V2DI_COUNT:
19882 type = v2di_ftype_v2di_v2di;
19884 case V2DI_FTYPE_V16QI_V16QI:
19885 type = v2di_ftype_v16qi_v16qi;
19887 case V2DI_FTYPE_V4SI_V4SI:
19888 type = v2di_ftype_v4si_v4si;
19890 case V2DI_FTYPE_V2DI_V16QI:
19891 type = v2di_ftype_v2di_v16qi;
19893 case V2DI_FTYPE_V2DF_V2DF:
19894 type = v2di_ftype_v2df_v2df;
19896 case V2DI_FTYPE_V2DI_SI_COUNT:
19897 type = v2di_ftype_v2di_int;
19899 case V2SI_FTYPE_V2SI_V2SI:
19900 case V2SI_FTYPE_V2SI_V2SI_COUNT:
19901 type = v2si_ftype_v2si_v2si;
19903 case V2SI_FTYPE_V4HI_V4HI:
19904 type = v2si_ftype_v4hi_v4hi;
19906 case V2SI_FTYPE_V2SF_V2SF:
19907 type = v2si_ftype_v2sf_v2sf;
19909 case V2SI_FTYPE_V2SI_SI_COUNT:
19910 type = v2si_ftype_v2si_int;
19912 case V2DF_FTYPE_V2DF_V2DF:
19913 case V2DF_FTYPE_V2DF_V2DF_SWAP:
19914 type = v2df_ftype_v2df_v2df;
19916 case V2DF_FTYPE_V2DF_V4SF:
19917 type = v2df_ftype_v2df_v4sf;
19919 case V2DF_FTYPE_V2DF_DI:
19920 type = v2df_ftype_v2df_int64;
19922 case V2DF_FTYPE_V2DF_SI:
19923 type = v2df_ftype_v2df_int;
19925 case V2SF_FTYPE_V2SF_V2SF:
19926 type = v2sf_ftype_v2sf_v2sf;
19928 case V1DI_FTYPE_V1DI_V1DI:
19929 case V1DI_FTYPE_V1DI_V1DI_COUNT:
19930 type = v1di_ftype_v1di_v1di;
19932 case V1DI_FTYPE_V8QI_V8QI:
19933 type = v1di_ftype_v8qi_v8qi;
19935 case V1DI_FTYPE_V2SI_V2SI:
19936 type = v1di_ftype_v2si_v2si;
19938 case V1DI_FTYPE_V1DI_SI_COUNT:
19939 type = v1di_ftype_v1di_int;
19941 case UINT64_FTYPE_UINT64_UINT64:
19942 type = uint64_ftype_uint64_uint64;
19944 case UINT_FTYPE_UINT_UINT:
19945 type = unsigned_ftype_unsigned_unsigned;
19947 case UINT_FTYPE_UINT_USHORT:
19948 type = unsigned_ftype_unsigned_ushort;
19950 case UINT_FTYPE_UINT_UCHAR:
19951 type = unsigned_ftype_unsigned_uchar;
19953 case V8HI_FTYPE_V8HI_INT:
19954 type = v8hi_ftype_v8hi_int;
19956 case V4SI_FTYPE_V4SI_INT:
19957 type = v4si_ftype_v4si_int;
19959 case V4HI_FTYPE_V4HI_INT:
19960 type = v4hi_ftype_v4hi_int;
19962 case V4SF_FTYPE_V4SF_INT:
19963 type = v4sf_ftype_v4sf_int;
19965 case V2DI_FTYPE_V2DI_INT:
19966 case V2DI2TI_FTYPE_V2DI_INT:
19967 type = v2di_ftype_v2di_int;
19969 case V2DF_FTYPE_V2DF_INT:
19970 type = v2df_ftype_v2df_int;
19972 case V16QI_FTYPE_V16QI_V16QI_V16QI:
19973 type = v16qi_ftype_v16qi_v16qi_v16qi;
19975 case V4SF_FTYPE_V4SF_V4SF_V4SF:
19976 type = v4sf_ftype_v4sf_v4sf_v4sf;
19978 case V2DF_FTYPE_V2DF_V2DF_V2DF:
19979 type = v2df_ftype_v2df_v2df_v2df;
19981 case V16QI_FTYPE_V16QI_V16QI_INT:
19982 type = v16qi_ftype_v16qi_v16qi_int;
19984 case V8HI_FTYPE_V8HI_V8HI_INT:
19985 type = v8hi_ftype_v8hi_v8hi_int;
19987 case V4SI_FTYPE_V4SI_V4SI_INT:
19988 type = v4si_ftype_v4si_v4si_int;
19990 case V4SF_FTYPE_V4SF_V4SF_INT:
19991 type = v4sf_ftype_v4sf_v4sf_int;
19993 case V2DI_FTYPE_V2DI_V2DI_INT:
19994 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
19995 type = v2di_ftype_v2di_v2di_int;
19997 case V2DF_FTYPE_V2DF_V2DF_INT:
19998 type = v2df_ftype_v2df_v2df_int;
20000 case V2DI_FTYPE_V2DI_UINT_UINT:
20001 type = v2di_ftype_v2di_unsigned_unsigned;
20003 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
20004 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
20006 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
20007 type = v1di_ftype_v1di_v1di_int;
20010 gcc_unreachable ();
20013 def_builtin_const (d->mask, d->name, type, d->code);
20016 /* pcmpestr[im] insns. */
20017 for (i = 0, d = bdesc_pcmpestr;
20018 i < ARRAY_SIZE (bdesc_pcmpestr);
20021 if (d->code == IX86_BUILTIN_PCMPESTRM128)
20022 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
20024 ftype = int_ftype_v16qi_int_v16qi_int_int;
20025 def_builtin_const (d->mask, d->name, ftype, d->code);
20028 /* pcmpistr[im] insns. */
20029 for (i = 0, d = bdesc_pcmpistr;
20030 i < ARRAY_SIZE (bdesc_pcmpistr);
20033 if (d->code == IX86_BUILTIN_PCMPISTRM128)
20034 ftype = v16qi_ftype_v16qi_v16qi_int;
20036 ftype = int_ftype_v16qi_v16qi_int;
20037 def_builtin_const (d->mask, d->name, ftype, d->code);
20040 /* comi/ucomi insns. */
20041 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
20042 if (d->mask == OPTION_MASK_ISA_SSE2)
20043 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
20045 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
20048 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
20049 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
20051 /* SSE or 3DNow!A */
20052 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
20055 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
20057 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
20058 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
20061 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
20062 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
20067 /* Define AES built-in functions only if AES is enabled. */
20068 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
20069 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
20070 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
20071 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
20072 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
20073 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
20079 /* Define PCLMUL built-in function only if PCLMUL is enabled. */
20080 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
20083 /* Access to the vec_init patterns. */
20084 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
20085 integer_type_node, NULL_TREE);
20086 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
20088 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
20089 short_integer_type_node,
20090 short_integer_type_node,
20091 short_integer_type_node, NULL_TREE);
20092 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
20094 ftype = build_function_type_list (V8QI_type_node, char_type_node,
20095 char_type_node, char_type_node,
20096 char_type_node, char_type_node,
20097 char_type_node, char_type_node,
20098 char_type_node, NULL_TREE);
20099 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
20101 /* Access to the vec_extract patterns. */
20102 ftype = build_function_type_list (double_type_node, V2DF_type_node,
20103 integer_type_node, NULL_TREE);
20104 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
20106 ftype = build_function_type_list (long_long_integer_type_node,
20107 V2DI_type_node, integer_type_node,
20109 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
20111 ftype = build_function_type_list (float_type_node, V4SF_type_node,
20112 integer_type_node, NULL_TREE);
20113 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
20115 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
20116 integer_type_node, NULL_TREE);
20117 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
20119 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
20120 integer_type_node, NULL_TREE);
20121 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
20123 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
20124 integer_type_node, NULL_TREE);
20125 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
20127 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
20128 integer_type_node, NULL_TREE);
20129 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
20131 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
20132 integer_type_node, NULL_TREE);
20133 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
20135 /* Access to the vec_set patterns. */
20136 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
20138 integer_type_node, NULL_TREE);
20139 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
20141 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
20143 integer_type_node, NULL_TREE);
20144 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
20146 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
20148 integer_type_node, NULL_TREE);
20149 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
20151 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
20153 integer_type_node, NULL_TREE);
20154 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
20156 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
20158 integer_type_node, NULL_TREE);
20159 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
20161 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
20163 integer_type_node, NULL_TREE);
20164 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
20166 /* Add SSE5 multi-arg argument instructions */
20167 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
20169 tree mtype = NULL_TREE;
20174 switch ((enum multi_arg_type)d->flag)
20176 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
20177 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
20178 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
20179 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
20180 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
20181 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
20182 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
20183 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
20184 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
20185 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
20186 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
20187 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
20188 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
20189 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
20190 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
20191 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
20192 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
20193 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
20194 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
20195 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
20196 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
20197 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
20198 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
20199 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
20200 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
20201 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
20202 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
20203 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
20204 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
20205 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
20206 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
20207 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
20208 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
20209 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
20210 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
20211 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
20212 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
20213 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
20214 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
20215 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
20216 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
20217 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
20218 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
20219 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
20220 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
20221 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
20222 case MULTI_ARG_UNKNOWN:
20224 gcc_unreachable ();
20228 def_builtin_const (d->mask, d->name, mtype, d->code);
20233 ix86_init_builtins (void)
20236 ix86_init_mmx_sse_builtins ();
20239 /* Errors in the source file can cause expand_expr to return const0_rtx
20240 where we expect a vector. To avoid crashing, use one of the vector
20241 clear instructions. */
20243 safe_vector_operand (rtx x, enum machine_mode mode)
20245 if (x == const0_rtx)
20246 x = CONST0_RTX (mode);
20250 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
20253 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
20256 tree arg0 = CALL_EXPR_ARG (exp, 0);
20257 tree arg1 = CALL_EXPR_ARG (exp, 1);
20258 rtx op0 = expand_normal (arg0);
20259 rtx op1 = expand_normal (arg1);
20260 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20261 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20262 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20264 if (VECTOR_MODE_P (mode0))
20265 op0 = safe_vector_operand (op0, mode0);
20266 if (VECTOR_MODE_P (mode1))
20267 op1 = safe_vector_operand (op1, mode1);
20269 if (optimize || !target
20270 || GET_MODE (target) != tmode
20271 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20272 target = gen_reg_rtx (tmode);
20274 if (GET_MODE (op1) == SImode && mode1 == TImode)
20276 rtx x = gen_reg_rtx (V4SImode);
20277 emit_insn (gen_sse2_loadd (x, op1));
20278 op1 = gen_lowpart (TImode, x);
20281 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
20282 op0 = copy_to_mode_reg (mode0, op0);
20283 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
20284 op1 = copy_to_mode_reg (mode1, op1);
20286 pat = GEN_FCN (icode) (target, op0, op1);
20295 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
20298 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
20299 enum multi_arg_type m_type,
20300 enum insn_code sub_code)
20305 bool comparison_p = false;
20307 bool last_arg_constant = false;
20308 int num_memory = 0;
20311 enum machine_mode mode;
20314 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20318 case MULTI_ARG_3_SF:
20319 case MULTI_ARG_3_DF:
20320 case MULTI_ARG_3_DI:
20321 case MULTI_ARG_3_SI:
20322 case MULTI_ARG_3_SI_DI:
20323 case MULTI_ARG_3_HI:
20324 case MULTI_ARG_3_HI_SI:
20325 case MULTI_ARG_3_QI:
20326 case MULTI_ARG_3_PERMPS:
20327 case MULTI_ARG_3_PERMPD:
20331 case MULTI_ARG_2_SF:
20332 case MULTI_ARG_2_DF:
20333 case MULTI_ARG_2_DI:
20334 case MULTI_ARG_2_SI:
20335 case MULTI_ARG_2_HI:
20336 case MULTI_ARG_2_QI:
20340 case MULTI_ARG_2_DI_IMM:
20341 case MULTI_ARG_2_SI_IMM:
20342 case MULTI_ARG_2_HI_IMM:
20343 case MULTI_ARG_2_QI_IMM:
20345 last_arg_constant = true;
20348 case MULTI_ARG_1_SF:
20349 case MULTI_ARG_1_DF:
20350 case MULTI_ARG_1_DI:
20351 case MULTI_ARG_1_SI:
20352 case MULTI_ARG_1_HI:
20353 case MULTI_ARG_1_QI:
20354 case MULTI_ARG_1_SI_DI:
20355 case MULTI_ARG_1_HI_DI:
20356 case MULTI_ARG_1_HI_SI:
20357 case MULTI_ARG_1_QI_DI:
20358 case MULTI_ARG_1_QI_SI:
20359 case MULTI_ARG_1_QI_HI:
20360 case MULTI_ARG_1_PH2PS:
20361 case MULTI_ARG_1_PS2PH:
20365 case MULTI_ARG_2_SF_CMP:
20366 case MULTI_ARG_2_DF_CMP:
20367 case MULTI_ARG_2_DI_CMP:
20368 case MULTI_ARG_2_SI_CMP:
20369 case MULTI_ARG_2_HI_CMP:
20370 case MULTI_ARG_2_QI_CMP:
20372 comparison_p = true;
20375 case MULTI_ARG_2_SF_TF:
20376 case MULTI_ARG_2_DF_TF:
20377 case MULTI_ARG_2_DI_TF:
20378 case MULTI_ARG_2_SI_TF:
20379 case MULTI_ARG_2_HI_TF:
20380 case MULTI_ARG_2_QI_TF:
20385 case MULTI_ARG_UNKNOWN:
20387 gcc_unreachable ();
20390 if (optimize || !target
20391 || GET_MODE (target) != tmode
20392 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20393 target = gen_reg_rtx (tmode);
20395 gcc_assert (nargs <= 4);
20397 for (i = 0; i < nargs; i++)
20399 tree arg = CALL_EXPR_ARG (exp, i);
20400 rtx op = expand_normal (arg);
20401 int adjust = (comparison_p) ? 1 : 0;
20402 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
20404 if (last_arg_constant && i == nargs-1)
20406 if (GET_CODE (op) != CONST_INT)
20408 error ("last argument must be an immediate");
20409 return gen_reg_rtx (tmode);
20414 if (VECTOR_MODE_P (mode))
20415 op = safe_vector_operand (op, mode);
20417 /* If we aren't optimizing, only allow one memory operand to be
20419 if (memory_operand (op, mode))
20422 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
20425 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
20427 op = force_reg (mode, op);
20431 args[i].mode = mode;
20437 pat = GEN_FCN (icode) (target, args[0].op);
20442 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
20443 GEN_INT ((int)sub_code));
20444 else if (! comparison_p)
20445 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20448 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
20452 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20457 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20461 gcc_unreachable ();
20471 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
20472 insns with vec_merge. */
20475 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
20479 tree arg0 = CALL_EXPR_ARG (exp, 0);
20480 rtx op1, op0 = expand_normal (arg0);
20481 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20482 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20484 if (optimize || !target
20485 || GET_MODE (target) != tmode
20486 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20487 target = gen_reg_rtx (tmode);
20489 if (VECTOR_MODE_P (mode0))
20490 op0 = safe_vector_operand (op0, mode0);
20492 if ((optimize && !register_operand (op0, mode0))
20493 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20494 op0 = copy_to_mode_reg (mode0, op0);
20497 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20498 op1 = copy_to_mode_reg (mode0, op1);
20500 pat = GEN_FCN (icode) (target, op0, op1);
20507 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20510 ix86_expand_sse_compare (const struct builtin_description *d,
20511 tree exp, rtx target, bool swap)
20514 tree arg0 = CALL_EXPR_ARG (exp, 0);
20515 tree arg1 = CALL_EXPR_ARG (exp, 1);
20516 rtx op0 = expand_normal (arg0);
20517 rtx op1 = expand_normal (arg1);
20519 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20520 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20521 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20522 enum rtx_code comparison = d->comparison;
20524 if (VECTOR_MODE_P (mode0))
20525 op0 = safe_vector_operand (op0, mode0);
20526 if (VECTOR_MODE_P (mode1))
20527 op1 = safe_vector_operand (op1, mode1);
20529 /* Swap operands if we have a comparison that isn't available in
20533 rtx tmp = gen_reg_rtx (mode1);
20534 emit_move_insn (tmp, op1);
20539 if (optimize || !target
20540 || GET_MODE (target) != tmode
20541 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20542 target = gen_reg_rtx (tmode);
20544 if ((optimize && !register_operand (op0, mode0))
20545 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20546 op0 = copy_to_mode_reg (mode0, op0);
20547 if ((optimize && !register_operand (op1, mode1))
20548 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20549 op1 = copy_to_mode_reg (mode1, op1);
20551 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20552 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20559 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20562 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20566 tree arg0 = CALL_EXPR_ARG (exp, 0);
20567 tree arg1 = CALL_EXPR_ARG (exp, 1);
20568 rtx op0 = expand_normal (arg0);
20569 rtx op1 = expand_normal (arg1);
20570 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20571 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20572 enum rtx_code comparison = d->comparison;
20574 if (VECTOR_MODE_P (mode0))
20575 op0 = safe_vector_operand (op0, mode0);
20576 if (VECTOR_MODE_P (mode1))
20577 op1 = safe_vector_operand (op1, mode1);
20579 /* Swap operands if we have a comparison that isn't available in
20581 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20588 target = gen_reg_rtx (SImode);
20589 emit_move_insn (target, const0_rtx);
20590 target = gen_rtx_SUBREG (QImode, target, 0);
20592 if ((optimize && !register_operand (op0, mode0))
20593 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20594 op0 = copy_to_mode_reg (mode0, op0);
20595 if ((optimize && !register_operand (op1, mode1))
20596 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20597 op1 = copy_to_mode_reg (mode1, op1);
20599 pat = GEN_FCN (d->icode) (op0, op1);
20603 emit_insn (gen_rtx_SET (VOIDmode,
20604 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20605 gen_rtx_fmt_ee (comparison, QImode,
20609 return SUBREG_REG (target);
20612 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20615 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20619 tree arg0 = CALL_EXPR_ARG (exp, 0);
20620 tree arg1 = CALL_EXPR_ARG (exp, 1);
20621 rtx op0 = expand_normal (arg0);
20622 rtx op1 = expand_normal (arg1);
20623 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20624 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20625 enum rtx_code comparison = d->comparison;
20627 if (VECTOR_MODE_P (mode0))
20628 op0 = safe_vector_operand (op0, mode0);
20629 if (VECTOR_MODE_P (mode1))
20630 op1 = safe_vector_operand (op1, mode1);
20632 target = gen_reg_rtx (SImode);
20633 emit_move_insn (target, const0_rtx);
20634 target = gen_rtx_SUBREG (QImode, target, 0);
20636 if ((optimize && !register_operand (op0, mode0))
20637 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20638 op0 = copy_to_mode_reg (mode0, op0);
20639 if ((optimize && !register_operand (op1, mode1))
20640 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20641 op1 = copy_to_mode_reg (mode1, op1);
20643 pat = GEN_FCN (d->icode) (op0, op1);
20647 emit_insn (gen_rtx_SET (VOIDmode,
20648 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20649 gen_rtx_fmt_ee (comparison, QImode,
20653 return SUBREG_REG (target);
20656 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20659 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20660 tree exp, rtx target)
20663 tree arg0 = CALL_EXPR_ARG (exp, 0);
20664 tree arg1 = CALL_EXPR_ARG (exp, 1);
20665 tree arg2 = CALL_EXPR_ARG (exp, 2);
20666 tree arg3 = CALL_EXPR_ARG (exp, 3);
20667 tree arg4 = CALL_EXPR_ARG (exp, 4);
20668 rtx scratch0, scratch1;
20669 rtx op0 = expand_normal (arg0);
20670 rtx op1 = expand_normal (arg1);
20671 rtx op2 = expand_normal (arg2);
20672 rtx op3 = expand_normal (arg3);
20673 rtx op4 = expand_normal (arg4);
20674 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20676 tmode0 = insn_data[d->icode].operand[0].mode;
20677 tmode1 = insn_data[d->icode].operand[1].mode;
20678 modev2 = insn_data[d->icode].operand[2].mode;
20679 modei3 = insn_data[d->icode].operand[3].mode;
20680 modev4 = insn_data[d->icode].operand[4].mode;
20681 modei5 = insn_data[d->icode].operand[5].mode;
20682 modeimm = insn_data[d->icode].operand[6].mode;
20684 if (VECTOR_MODE_P (modev2))
20685 op0 = safe_vector_operand (op0, modev2);
20686 if (VECTOR_MODE_P (modev4))
20687 op2 = safe_vector_operand (op2, modev4);
20689 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20690 op0 = copy_to_mode_reg (modev2, op0);
20691 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20692 op1 = copy_to_mode_reg (modei3, op1);
20693 if ((optimize && !register_operand (op2, modev4))
20694 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20695 op2 = copy_to_mode_reg (modev4, op2);
20696 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20697 op3 = copy_to_mode_reg (modei5, op3);
20699 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20701 error ("the fifth argument must be a 8-bit immediate");
20705 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20707 if (optimize || !target
20708 || GET_MODE (target) != tmode0
20709 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20710 target = gen_reg_rtx (tmode0);
20712 scratch1 = gen_reg_rtx (tmode1);
20714 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20716 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20718 if (optimize || !target
20719 || GET_MODE (target) != tmode1
20720 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20721 target = gen_reg_rtx (tmode1);
20723 scratch0 = gen_reg_rtx (tmode0);
20725 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20729 gcc_assert (d->flag);
20731 scratch0 = gen_reg_rtx (tmode0);
20732 scratch1 = gen_reg_rtx (tmode1);
20734 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20744 target = gen_reg_rtx (SImode);
20745 emit_move_insn (target, const0_rtx);
20746 target = gen_rtx_SUBREG (QImode, target, 0);
20749 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20750 gen_rtx_fmt_ee (EQ, QImode,
20751 gen_rtx_REG ((enum machine_mode) d->flag,
20754 return SUBREG_REG (target);
20761 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20764 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20765 tree exp, rtx target)
20768 tree arg0 = CALL_EXPR_ARG (exp, 0);
20769 tree arg1 = CALL_EXPR_ARG (exp, 1);
20770 tree arg2 = CALL_EXPR_ARG (exp, 2);
20771 rtx scratch0, scratch1;
20772 rtx op0 = expand_normal (arg0);
20773 rtx op1 = expand_normal (arg1);
20774 rtx op2 = expand_normal (arg2);
20775 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20777 tmode0 = insn_data[d->icode].operand[0].mode;
20778 tmode1 = insn_data[d->icode].operand[1].mode;
20779 modev2 = insn_data[d->icode].operand[2].mode;
20780 modev3 = insn_data[d->icode].operand[3].mode;
20781 modeimm = insn_data[d->icode].operand[4].mode;
20783 if (VECTOR_MODE_P (modev2))
20784 op0 = safe_vector_operand (op0, modev2);
20785 if (VECTOR_MODE_P (modev3))
20786 op1 = safe_vector_operand (op1, modev3);
20788 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20789 op0 = copy_to_mode_reg (modev2, op0);
20790 if ((optimize && !register_operand (op1, modev3))
20791 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20792 op1 = copy_to_mode_reg (modev3, op1);
20794 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20796 error ("the third argument must be a 8-bit immediate");
20800 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20802 if (optimize || !target
20803 || GET_MODE (target) != tmode0
20804 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20805 target = gen_reg_rtx (tmode0);
20807 scratch1 = gen_reg_rtx (tmode1);
20809 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20811 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20813 if (optimize || !target
20814 || GET_MODE (target) != tmode1
20815 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20816 target = gen_reg_rtx (tmode1);
20818 scratch0 = gen_reg_rtx (tmode0);
20820 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20824 gcc_assert (d->flag);
20826 scratch0 = gen_reg_rtx (tmode0);
20827 scratch1 = gen_reg_rtx (tmode1);
20829 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20839 target = gen_reg_rtx (SImode);
20840 emit_move_insn (target, const0_rtx);
20841 target = gen_rtx_SUBREG (QImode, target, 0);
20844 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20845 gen_rtx_fmt_ee (EQ, QImode,
20846 gen_rtx_REG ((enum machine_mode) d->flag,
20849 return SUBREG_REG (target);
20855 /* Subroutine of ix86_expand_builtin to take care of insns with
20856 variable number of operands. */
20859 ix86_expand_args_builtin (const struct builtin_description *d,
20860 tree exp, rtx target)
20862 rtx pat, real_target;
20863 unsigned int i, nargs;
20864 unsigned int nargs_constant = 0;
20865 int num_memory = 0;
20869 enum machine_mode mode;
20871 bool last_arg_count = false;
20872 enum insn_code icode = d->icode;
20873 const struct insn_data *insn_p = &insn_data[icode];
20874 enum machine_mode tmode = insn_p->operand[0].mode;
20875 enum machine_mode rmode = VOIDmode;
20877 enum rtx_code comparison = d->comparison;
20879 switch ((enum ix86_builtin_type) d->flag)
20881 case INT_FTYPE_V2DI_V2DI_PTEST:
20882 return ix86_expand_sse_ptest (d, exp, target);
20883 case FLOAT128_FTYPE_FLOAT128:
20884 case FLOAT_FTYPE_FLOAT:
20885 case INT64_FTYPE_V4SF:
20886 case INT64_FTYPE_V2DF:
20887 case INT_FTYPE_V16QI:
20888 case INT_FTYPE_V8QI:
20889 case INT_FTYPE_V4SF:
20890 case INT_FTYPE_V2DF:
20891 case V16QI_FTYPE_V16QI:
20892 case V8HI_FTYPE_V8HI:
20893 case V8HI_FTYPE_V16QI:
20894 case V8QI_FTYPE_V8QI:
20895 case V4SI_FTYPE_V4SI:
20896 case V4SI_FTYPE_V16QI:
20897 case V4SI_FTYPE_V4SF:
20898 case V4SI_FTYPE_V8HI:
20899 case V4SI_FTYPE_V2DF:
20900 case V4HI_FTYPE_V4HI:
20901 case V4SF_FTYPE_V4SF:
20902 case V4SF_FTYPE_V4SI:
20903 case V4SF_FTYPE_V2DF:
20904 case V2DI_FTYPE_V2DI:
20905 case V2DI_FTYPE_V16QI:
20906 case V2DI_FTYPE_V8HI:
20907 case V2DI_FTYPE_V4SI:
20908 case V2DF_FTYPE_V2DF:
20909 case V2DF_FTYPE_V4SI:
20910 case V2DF_FTYPE_V4SF:
20911 case V2DF_FTYPE_V2SI:
20912 case V2SI_FTYPE_V2SI:
20913 case V2SI_FTYPE_V4SF:
20914 case V2SI_FTYPE_V2SF:
20915 case V2SI_FTYPE_V2DF:
20916 case V2SF_FTYPE_V2SF:
20917 case V2SF_FTYPE_V2SI:
20920 case V4SF_FTYPE_V4SF_VEC_MERGE:
20921 case V2DF_FTYPE_V2DF_VEC_MERGE:
20922 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
20923 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
20924 case V16QI_FTYPE_V16QI_V16QI:
20925 case V16QI_FTYPE_V8HI_V8HI:
20926 case V8QI_FTYPE_V8QI_V8QI:
20927 case V8QI_FTYPE_V4HI_V4HI:
20928 case V8HI_FTYPE_V8HI_V8HI:
20929 case V8HI_FTYPE_V16QI_V16QI:
20930 case V8HI_FTYPE_V4SI_V4SI:
20931 case V4SI_FTYPE_V4SI_V4SI:
20932 case V4SI_FTYPE_V8HI_V8HI:
20933 case V4SI_FTYPE_V4SF_V4SF:
20934 case V4SI_FTYPE_V2DF_V2DF:
20935 case V4HI_FTYPE_V4HI_V4HI:
20936 case V4HI_FTYPE_V8QI_V8QI:
20937 case V4HI_FTYPE_V2SI_V2SI:
20938 case V4SF_FTYPE_V4SF_V4SF:
20939 case V4SF_FTYPE_V4SF_V2SI:
20940 case V4SF_FTYPE_V4SF_V2DF:
20941 case V4SF_FTYPE_V4SF_DI:
20942 case V4SF_FTYPE_V4SF_SI:
20943 case V2DI_FTYPE_V2DI_V2DI:
20944 case V2DI_FTYPE_V16QI_V16QI:
20945 case V2DI_FTYPE_V4SI_V4SI:
20946 case V2DI_FTYPE_V2DI_V16QI:
20947 case V2DI_FTYPE_V2DF_V2DF:
20948 case V2SI_FTYPE_V2SI_V2SI:
20949 case V2SI_FTYPE_V4HI_V4HI:
20950 case V2SI_FTYPE_V2SF_V2SF:
20951 case V2DF_FTYPE_V2DF_V2DF:
20952 case V2DF_FTYPE_V2DF_V4SF:
20953 case V2DF_FTYPE_V2DF_DI:
20954 case V2DF_FTYPE_V2DF_SI:
20955 case V2SF_FTYPE_V2SF_V2SF:
20956 case V1DI_FTYPE_V1DI_V1DI:
20957 case V1DI_FTYPE_V8QI_V8QI:
20958 case V1DI_FTYPE_V2SI_V2SI:
20959 if (comparison == UNKNOWN)
20960 return ix86_expand_binop_builtin (icode, exp, target);
20963 case V4SF_FTYPE_V4SF_V4SF_SWAP:
20964 case V2DF_FTYPE_V2DF_V2DF_SWAP:
20965 gcc_assert (comparison != UNKNOWN);
20969 case V8HI_FTYPE_V8HI_V8HI_COUNT:
20970 case V8HI_FTYPE_V8HI_SI_COUNT:
20971 case V4SI_FTYPE_V4SI_V4SI_COUNT:
20972 case V4SI_FTYPE_V4SI_SI_COUNT:
20973 case V4HI_FTYPE_V4HI_V4HI_COUNT:
20974 case V4HI_FTYPE_V4HI_SI_COUNT:
20975 case V2DI_FTYPE_V2DI_V2DI_COUNT:
20976 case V2DI_FTYPE_V2DI_SI_COUNT:
20977 case V2SI_FTYPE_V2SI_V2SI_COUNT:
20978 case V2SI_FTYPE_V2SI_SI_COUNT:
20979 case V1DI_FTYPE_V1DI_V1DI_COUNT:
20980 case V1DI_FTYPE_V1DI_SI_COUNT:
20982 last_arg_count = true;
20984 case UINT64_FTYPE_UINT64_UINT64:
20985 case UINT_FTYPE_UINT_UINT:
20986 case UINT_FTYPE_UINT_USHORT:
20987 case UINT_FTYPE_UINT_UCHAR:
20990 case V2DI2TI_FTYPE_V2DI_INT:
20993 nargs_constant = 1;
20995 case V8HI_FTYPE_V8HI_INT:
20996 case V4SI_FTYPE_V4SI_INT:
20997 case V4HI_FTYPE_V4HI_INT:
20998 case V4SF_FTYPE_V4SF_INT:
20999 case V2DI_FTYPE_V2DI_INT:
21000 case V2DF_FTYPE_V2DF_INT:
21002 nargs_constant = 1;
21004 case V16QI_FTYPE_V16QI_V16QI_V16QI:
21005 case V4SF_FTYPE_V4SF_V4SF_V4SF:
21006 case V2DF_FTYPE_V2DF_V2DF_V2DF:
21009 case V16QI_FTYPE_V16QI_V16QI_INT:
21010 case V8HI_FTYPE_V8HI_V8HI_INT:
21011 case V4SI_FTYPE_V4SI_V4SI_INT:
21012 case V4SF_FTYPE_V4SF_V4SF_INT:
21013 case V2DI_FTYPE_V2DI_V2DI_INT:
21014 case V2DF_FTYPE_V2DF_V2DF_INT:
21016 nargs_constant = 1;
21018 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
21021 nargs_constant = 1;
21023 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
21026 nargs_constant = 1;
21028 case V2DI_FTYPE_V2DI_UINT_UINT:
21030 nargs_constant = 2;
21032 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
21034 nargs_constant = 2;
21037 gcc_unreachable ();
21040 gcc_assert (nargs <= ARRAY_SIZE (args));
21042 if (comparison != UNKNOWN)
21044 gcc_assert (nargs == 2);
21045 return ix86_expand_sse_compare (d, exp, target, swap);
21048 if (rmode == VOIDmode || rmode == tmode)
21052 || GET_MODE (target) != tmode
21053 || ! (*insn_p->operand[0].predicate) (target, tmode))
21054 target = gen_reg_rtx (tmode);
21055 real_target = target;
21059 target = gen_reg_rtx (rmode);
21060 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
21063 for (i = 0; i < nargs; i++)
21065 tree arg = CALL_EXPR_ARG (exp, i);
21066 rtx op = expand_normal (arg);
21067 enum machine_mode mode = insn_p->operand[i + 1].mode;
21068 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
21070 if (last_arg_count && (i + 1) == nargs)
21072 /* SIMD shift insns take either an 8-bit immediate or
21073 register as count. But builtin functions take int as
21074 count. If count doesn't match, we put it in register. */
21077 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
21078 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
21079 op = copy_to_reg (op);
21082 else if ((nargs - i) <= nargs_constant)
21087 case CODE_FOR_sse4_1_roundpd:
21088 case CODE_FOR_sse4_1_roundps:
21089 case CODE_FOR_sse4_1_roundsd:
21090 case CODE_FOR_sse4_1_roundss:
21091 case CODE_FOR_sse4_1_blendps:
21092 error ("the last argument must be a 4-bit immediate");
21095 case CODE_FOR_sse4_1_blendpd:
21096 error ("the last argument must be a 2-bit immediate");
21100 switch (nargs_constant)
21103 if ((nargs - i) == nargs_constant)
21105 error ("the next to last argument must be an 8-bit immediate");
21109 error ("the last argument must be an 8-bit immediate");
21112 gcc_unreachable ();
21119 if (VECTOR_MODE_P (mode))
21120 op = safe_vector_operand (op, mode);
21122 /* If we aren't optimizing, only allow one memory operand to
21124 if (memory_operand (op, mode))
21127 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
21129 if (optimize || !match || num_memory > 1)
21130 op = copy_to_mode_reg (mode, op);
21134 op = copy_to_reg (op);
21135 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
21140 args[i].mode = mode;
21146 pat = GEN_FCN (icode) (real_target, args[0].op);
21149 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
21152 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
21156 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
21157 args[2].op, args[3].op);
21160 gcc_unreachable ();
21170 /* Subroutine of ix86_expand_builtin to take care of special insns
21171 with variable number of operands. */
21174 ix86_expand_special_args_builtin (const struct builtin_description *d,
21175 tree exp, rtx target)
21179 unsigned int i, nargs, arg_adjust, memory;
21183 enum machine_mode mode;
21185 enum insn_code icode = d->icode;
21186 bool last_arg_constant = false;
21187 const struct insn_data *insn_p = &insn_data[icode];
21188 enum machine_mode tmode = insn_p->operand[0].mode;
21189 enum { load, store } class;
21191 switch ((enum ix86_special_builtin_type) d->flag)
21193 case VOID_FTYPE_VOID:
21194 emit_insn (GEN_FCN (icode) (target));
21196 case V2DI_FTYPE_PV2DI:
21197 case V16QI_FTYPE_PCCHAR:
21198 case V4SF_FTYPE_PCFLOAT:
21199 case V2DF_FTYPE_PCDOUBLE:
21204 case VOID_FTYPE_PV2SF_V4SF:
21205 case VOID_FTYPE_PV2DI_V2DI:
21206 case VOID_FTYPE_PCHAR_V16QI:
21207 case VOID_FTYPE_PFLOAT_V4SF:
21208 case VOID_FTYPE_PDOUBLE_V2DF:
21209 case VOID_FTYPE_PDI_DI:
21210 case VOID_FTYPE_PINT_INT:
21213 /* Reserve memory operand for target. */
21214 memory = ARRAY_SIZE (args);
21216 case V4SF_FTYPE_V4SF_PCV2SF:
21217 case V2DF_FTYPE_V2DF_PCDOUBLE:
21223 gcc_unreachable ();
21226 gcc_assert (nargs <= ARRAY_SIZE (args));
21228 if (class == store)
21230 arg = CALL_EXPR_ARG (exp, 0);
21231 op = expand_normal (arg);
21232 gcc_assert (target == 0);
21233 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
21241 || GET_MODE (target) != tmode
21242 || ! (*insn_p->operand[0].predicate) (target, tmode))
21243 target = gen_reg_rtx (tmode);
21246 for (i = 0; i < nargs; i++)
21248 enum machine_mode mode = insn_p->operand[i + 1].mode;
21251 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
21252 op = expand_normal (arg);
21253 match = (*insn_p->operand[i + 1].predicate) (op, mode);
21255 if (last_arg_constant && (i + 1) == nargs)
21261 error ("the last argument must be an 8-bit immediate");
21269 /* This must be the memory operand. */
21270 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
21271 gcc_assert (GET_MODE (op) == mode
21272 || GET_MODE (op) == VOIDmode);
21276 /* This must be register. */
21277 if (VECTOR_MODE_P (mode))
21278 op = safe_vector_operand (op, mode);
21280 gcc_assert (GET_MODE (op) == mode
21281 || GET_MODE (op) == VOIDmode);
21282 op = copy_to_mode_reg (mode, op);
21287 args[i].mode = mode;
21293 pat = GEN_FCN (icode) (target, args[0].op);
21296 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
21299 gcc_unreachable ();
21305 return class == store ? 0 : target;
21308 /* Return the integer constant in ARG. Constrain it to be in the range
21309 of the subparts of VEC_TYPE; issue an error if not. */
21312 get_element_number (tree vec_type, tree arg)
21314 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
21316 if (!host_integerp (arg, 1)
21317 || (elt = tree_low_cst (arg, 1), elt > max))
21319 error ("selector must be an integer constant in the range 0..%wi", max);
21326 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21327 ix86_expand_vector_init. We DO have language-level syntax for this, in
21328 the form of (type){ init-list }. Except that since we can't place emms
21329 instructions from inside the compiler, we can't allow the use of MMX
21330 registers unless the user explicitly asks for it. So we do *not* define
21331 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
21332 we have builtins invoked by mmintrin.h that gives us license to emit
21333 these sorts of instructions. */
21336 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
21338 enum machine_mode tmode = TYPE_MODE (type);
21339 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
21340 int i, n_elt = GET_MODE_NUNITS (tmode);
21341 rtvec v = rtvec_alloc (n_elt);
21343 gcc_assert (VECTOR_MODE_P (tmode));
21344 gcc_assert (call_expr_nargs (exp) == n_elt);
21346 for (i = 0; i < n_elt; ++i)
21348 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
21349 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
21352 if (!target || !register_operand (target, tmode))
21353 target = gen_reg_rtx (tmode);
21355 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
21359 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21360 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
21361 had a language-level syntax for referencing vector elements. */
21364 ix86_expand_vec_ext_builtin (tree exp, rtx target)
21366 enum machine_mode tmode, mode0;
21371 arg0 = CALL_EXPR_ARG (exp, 0);
21372 arg1 = CALL_EXPR_ARG (exp, 1);
21374 op0 = expand_normal (arg0);
21375 elt = get_element_number (TREE_TYPE (arg0), arg1);
21377 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
21378 mode0 = TYPE_MODE (TREE_TYPE (arg0));
21379 gcc_assert (VECTOR_MODE_P (mode0));
21381 op0 = force_reg (mode0, op0);
21383 if (optimize || !target || !register_operand (target, tmode))
21384 target = gen_reg_rtx (tmode);
21386 ix86_expand_vector_extract (true, target, op0, elt);
21391 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21392 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
21393 a language-level syntax for referencing vector elements. */
21396 ix86_expand_vec_set_builtin (tree exp)
21398 enum machine_mode tmode, mode1;
21399 tree arg0, arg1, arg2;
21401 rtx op0, op1, target;
21403 arg0 = CALL_EXPR_ARG (exp, 0);
21404 arg1 = CALL_EXPR_ARG (exp, 1);
21405 arg2 = CALL_EXPR_ARG (exp, 2);
21407 tmode = TYPE_MODE (TREE_TYPE (arg0));
21408 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
21409 gcc_assert (VECTOR_MODE_P (tmode));
21411 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
21412 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
21413 elt = get_element_number (TREE_TYPE (arg0), arg2);
21415 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
21416 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
21418 op0 = force_reg (tmode, op0);
21419 op1 = force_reg (mode1, op1);
21421 /* OP0 is the source of these builtin functions and shouldn't be
21422 modified. Create a copy, use it and return it as target. */
21423 target = gen_reg_rtx (tmode);
21424 emit_move_insn (target, op0);
21425 ix86_expand_vector_set (true, target, op1, elt);
21430 /* Expand an expression EXP that calls a built-in function,
21431 with result going to TARGET if that's convenient
21432 (and in mode MODE if that's convenient).
21433 SUBTARGET may be used as the target for computing one of EXP's operands.
21434 IGNORE is nonzero if the value is to be ignored. */
21437 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
21438 enum machine_mode mode ATTRIBUTE_UNUSED,
21439 int ignore ATTRIBUTE_UNUSED)
21441 const struct builtin_description *d;
21443 enum insn_code icode;
21444 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
21445 tree arg0, arg1, arg2;
21446 rtx op0, op1, op2, pat;
21447 enum machine_mode mode0, mode1, mode2;
21448 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
21452 case IX86_BUILTIN_MASKMOVQ:
21453 case IX86_BUILTIN_MASKMOVDQU:
21454 icode = (fcode == IX86_BUILTIN_MASKMOVQ
21455 ? CODE_FOR_mmx_maskmovq
21456 : CODE_FOR_sse2_maskmovdqu);
21457 /* Note the arg order is different from the operand order. */
21458 arg1 = CALL_EXPR_ARG (exp, 0);
21459 arg2 = CALL_EXPR_ARG (exp, 1);
21460 arg0 = CALL_EXPR_ARG (exp, 2);
21461 op0 = expand_normal (arg0);
21462 op1 = expand_normal (arg1);
21463 op2 = expand_normal (arg2);
21464 mode0 = insn_data[icode].operand[0].mode;
21465 mode1 = insn_data[icode].operand[1].mode;
21466 mode2 = insn_data[icode].operand[2].mode;
21468 op0 = force_reg (Pmode, op0);
21469 op0 = gen_rtx_MEM (mode1, op0);
21471 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
21472 op0 = copy_to_mode_reg (mode0, op0);
21473 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
21474 op1 = copy_to_mode_reg (mode1, op1);
21475 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
21476 op2 = copy_to_mode_reg (mode2, op2);
21477 pat = GEN_FCN (icode) (op0, op1, op2);
21483 case IX86_BUILTIN_LDMXCSR:
21484 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
21485 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21486 emit_move_insn (target, op0);
21487 emit_insn (gen_sse_ldmxcsr (target));
21490 case IX86_BUILTIN_STMXCSR:
21491 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21492 emit_insn (gen_sse_stmxcsr (target));
21493 return copy_to_mode_reg (SImode, target);
21495 case IX86_BUILTIN_CLFLUSH:
21496 arg0 = CALL_EXPR_ARG (exp, 0);
21497 op0 = expand_normal (arg0);
21498 icode = CODE_FOR_sse2_clflush;
21499 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21500 op0 = copy_to_mode_reg (Pmode, op0);
21502 emit_insn (gen_sse2_clflush (op0));
21505 case IX86_BUILTIN_MONITOR:
21506 arg0 = CALL_EXPR_ARG (exp, 0);
21507 arg1 = CALL_EXPR_ARG (exp, 1);
21508 arg2 = CALL_EXPR_ARG (exp, 2);
21509 op0 = expand_normal (arg0);
21510 op1 = expand_normal (arg1);
21511 op2 = expand_normal (arg2);
21513 op0 = copy_to_mode_reg (Pmode, op0);
21515 op1 = copy_to_mode_reg (SImode, op1);
21517 op2 = copy_to_mode_reg (SImode, op2);
21518 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
21521 case IX86_BUILTIN_MWAIT:
21522 arg0 = CALL_EXPR_ARG (exp, 0);
21523 arg1 = CALL_EXPR_ARG (exp, 1);
21524 op0 = expand_normal (arg0);
21525 op1 = expand_normal (arg1);
21527 op0 = copy_to_mode_reg (SImode, op0);
21529 op1 = copy_to_mode_reg (SImode, op1);
21530 emit_insn (gen_sse3_mwait (op0, op1));
21533 case IX86_BUILTIN_VEC_INIT_V2SI:
21534 case IX86_BUILTIN_VEC_INIT_V4HI:
21535 case IX86_BUILTIN_VEC_INIT_V8QI:
21536 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21538 case IX86_BUILTIN_VEC_EXT_V2DF:
21539 case IX86_BUILTIN_VEC_EXT_V2DI:
21540 case IX86_BUILTIN_VEC_EXT_V4SF:
21541 case IX86_BUILTIN_VEC_EXT_V4SI:
21542 case IX86_BUILTIN_VEC_EXT_V8HI:
21543 case IX86_BUILTIN_VEC_EXT_V2SI:
21544 case IX86_BUILTIN_VEC_EXT_V4HI:
21545 case IX86_BUILTIN_VEC_EXT_V16QI:
21546 return ix86_expand_vec_ext_builtin (exp, target);
21548 case IX86_BUILTIN_VEC_SET_V2DI:
21549 case IX86_BUILTIN_VEC_SET_V4SF:
21550 case IX86_BUILTIN_VEC_SET_V4SI:
21551 case IX86_BUILTIN_VEC_SET_V8HI:
21552 case IX86_BUILTIN_VEC_SET_V4HI:
21553 case IX86_BUILTIN_VEC_SET_V16QI:
21554 return ix86_expand_vec_set_builtin (exp);
21556 case IX86_BUILTIN_INFQ:
21558 REAL_VALUE_TYPE inf;
21562 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21564 tmp = validize_mem (force_const_mem (mode, tmp));
21567 target = gen_reg_rtx (mode);
21569 emit_move_insn (target, tmp);
21577 for (i = 0, d = bdesc_special_args;
21578 i < ARRAY_SIZE (bdesc_special_args);
21580 if (d->code == fcode)
21581 return ix86_expand_special_args_builtin (d, exp, target);
21583 for (i = 0, d = bdesc_args;
21584 i < ARRAY_SIZE (bdesc_args);
21586 if (d->code == fcode)
21587 return ix86_expand_args_builtin (d, exp, target);
21589 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21590 if (d->code == fcode)
21591 return ix86_expand_sse_comi (d, exp, target);
21593 for (i = 0, d = bdesc_pcmpestr;
21594 i < ARRAY_SIZE (bdesc_pcmpestr);
21596 if (d->code == fcode)
21597 return ix86_expand_sse_pcmpestr (d, exp, target);
21599 for (i = 0, d = bdesc_pcmpistr;
21600 i < ARRAY_SIZE (bdesc_pcmpistr);
21602 if (d->code == fcode)
21603 return ix86_expand_sse_pcmpistr (d, exp, target);
21605 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21606 if (d->code == fcode)
21607 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21608 (enum multi_arg_type)d->flag,
21611 gcc_unreachable ();
21614 /* Returns a function decl for a vectorized version of the builtin function
21615 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21616 if it is not available. */
21619 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21622 enum machine_mode in_mode, out_mode;
21625 if (TREE_CODE (type_out) != VECTOR_TYPE
21626 || TREE_CODE (type_in) != VECTOR_TYPE)
21629 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21630 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21631 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21632 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21636 case BUILT_IN_SQRT:
21637 if (out_mode == DFmode && out_n == 2
21638 && in_mode == DFmode && in_n == 2)
21639 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21642 case BUILT_IN_SQRTF:
21643 if (out_mode == SFmode && out_n == 4
21644 && in_mode == SFmode && in_n == 4)
21645 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21648 case BUILT_IN_LRINT:
21649 if (out_mode == SImode && out_n == 4
21650 && in_mode == DFmode && in_n == 2)
21651 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21654 case BUILT_IN_LRINTF:
21655 if (out_mode == SImode && out_n == 4
21656 && in_mode == SFmode && in_n == 4)
21657 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21664 /* Dispatch to a handler for a vectorization library. */
21665 if (ix86_veclib_handler)
21666 return (*ix86_veclib_handler)(fn, type_out, type_in);
21671 /* Handler for an SVML-style interface to
21672 a library with vectorized intrinsics. */
21675 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
21678 tree fntype, new_fndecl, args;
21681 enum machine_mode el_mode, in_mode;
21684 /* The SVML is suitable for unsafe math only. */
21685 if (!flag_unsafe_math_optimizations)
21688 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21689 n = TYPE_VECTOR_SUBPARTS (type_out);
21690 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21691 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21692 if (el_mode != in_mode
21700 case BUILT_IN_LOG10:
21702 case BUILT_IN_TANH:
21704 case BUILT_IN_ATAN:
21705 case BUILT_IN_ATAN2:
21706 case BUILT_IN_ATANH:
21707 case BUILT_IN_CBRT:
21708 case BUILT_IN_SINH:
21710 case BUILT_IN_ASINH:
21711 case BUILT_IN_ASIN:
21712 case BUILT_IN_COSH:
21714 case BUILT_IN_ACOSH:
21715 case BUILT_IN_ACOS:
21716 if (el_mode != DFmode || n != 2)
21720 case BUILT_IN_EXPF:
21721 case BUILT_IN_LOGF:
21722 case BUILT_IN_LOG10F:
21723 case BUILT_IN_POWF:
21724 case BUILT_IN_TANHF:
21725 case BUILT_IN_TANF:
21726 case BUILT_IN_ATANF:
21727 case BUILT_IN_ATAN2F:
21728 case BUILT_IN_ATANHF:
21729 case BUILT_IN_CBRTF:
21730 case BUILT_IN_SINHF:
21731 case BUILT_IN_SINF:
21732 case BUILT_IN_ASINHF:
21733 case BUILT_IN_ASINF:
21734 case BUILT_IN_COSHF:
21735 case BUILT_IN_COSF:
21736 case BUILT_IN_ACOSHF:
21737 case BUILT_IN_ACOSF:
21738 if (el_mode != SFmode || n != 4)
21746 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21748 if (fn == BUILT_IN_LOGF)
21749 strcpy (name, "vmlsLn4");
21750 else if (fn == BUILT_IN_LOG)
21751 strcpy (name, "vmldLn2");
21754 sprintf (name, "vmls%s", bname+10);
21755 name[strlen (name)-1] = '4';
21758 sprintf (name, "vmld%s2", bname+10);
21760 /* Convert to uppercase. */
21764 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21765 args = TREE_CHAIN (args))
21769 fntype = build_function_type_list (type_out, type_in, NULL);
21771 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21773 /* Build a function declaration for the vectorized function. */
21774 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21775 TREE_PUBLIC (new_fndecl) = 1;
21776 DECL_EXTERNAL (new_fndecl) = 1;
21777 DECL_IS_NOVOPS (new_fndecl) = 1;
21778 TREE_READONLY (new_fndecl) = 1;
21783 /* Handler for an ACML-style interface to
21784 a library with vectorized intrinsics. */
21787 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21789 char name[20] = "__vr.._";
21790 tree fntype, new_fndecl, args;
21793 enum machine_mode el_mode, in_mode;
21796 /* The ACML is 64bits only and suitable for unsafe math only as
21797 it does not correctly support parts of IEEE with the required
21798 precision such as denormals. */
21800 || !flag_unsafe_math_optimizations)
21803 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21804 n = TYPE_VECTOR_SUBPARTS (type_out);
21805 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21806 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21807 if (el_mode != in_mode
21817 case BUILT_IN_LOG2:
21818 case BUILT_IN_LOG10:
21821 if (el_mode != DFmode
21826 case BUILT_IN_SINF:
21827 case BUILT_IN_COSF:
21828 case BUILT_IN_EXPF:
21829 case BUILT_IN_POWF:
21830 case BUILT_IN_LOGF:
21831 case BUILT_IN_LOG2F:
21832 case BUILT_IN_LOG10F:
21835 if (el_mode != SFmode
21844 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21845 sprintf (name + 7, "%s", bname+10);
21848 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21849 args = TREE_CHAIN (args))
21853 fntype = build_function_type_list (type_out, type_in, NULL);
21855 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21857 /* Build a function declaration for the vectorized function. */
21858 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21859 TREE_PUBLIC (new_fndecl) = 1;
21860 DECL_EXTERNAL (new_fndecl) = 1;
21861 DECL_IS_NOVOPS (new_fndecl) = 1;
21862 TREE_READONLY (new_fndecl) = 1;
21868 /* Returns a decl of a function that implements conversion of the
21869 input vector of type TYPE, or NULL_TREE if it is not available. */
21872 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21874 if (TREE_CODE (type) != VECTOR_TYPE)
21880 switch (TYPE_MODE (type))
21883 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21888 case FIX_TRUNC_EXPR:
21889 switch (TYPE_MODE (type))
21892 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21902 /* Returns a code for a target-specific builtin that implements
21903 reciprocal of the function, or NULL_TREE if not available. */
21906 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21907 bool sqrt ATTRIBUTE_UNUSED)
21909 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21910 && flag_finite_math_only && !flag_trapping_math
21911 && flag_unsafe_math_optimizations))
21915 /* Machine dependent builtins. */
21918 /* Vectorized version of sqrt to rsqrt conversion. */
21919 case IX86_BUILTIN_SQRTPS_NR:
21920 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21926 /* Normal builtins. */
21929 /* Sqrt to rsqrt conversion. */
21930 case BUILT_IN_SQRTF:
21931 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21938 /* Store OPERAND to the memory after reload is completed. This means
21939 that we can't easily use assign_stack_local. */
21941 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21945 gcc_assert (reload_completed);
21946 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
21948 result = gen_rtx_MEM (mode,
21949 gen_rtx_PLUS (Pmode,
21951 GEN_INT (-RED_ZONE_SIZE)));
21952 emit_move_insn (result, operand);
21954 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
21960 operand = gen_lowpart (DImode, operand);
21964 gen_rtx_SET (VOIDmode,
21965 gen_rtx_MEM (DImode,
21966 gen_rtx_PRE_DEC (DImode,
21967 stack_pointer_rtx)),
21971 gcc_unreachable ();
21973 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21982 split_di (&operand, 1, operands, operands + 1);
21984 gen_rtx_SET (VOIDmode,
21985 gen_rtx_MEM (SImode,
21986 gen_rtx_PRE_DEC (Pmode,
21987 stack_pointer_rtx)),
21990 gen_rtx_SET (VOIDmode,
21991 gen_rtx_MEM (SImode,
21992 gen_rtx_PRE_DEC (Pmode,
21993 stack_pointer_rtx)),
21998 /* Store HImodes as SImodes. */
21999 operand = gen_lowpart (SImode, operand);
22003 gen_rtx_SET (VOIDmode,
22004 gen_rtx_MEM (GET_MODE (operand),
22005 gen_rtx_PRE_DEC (SImode,
22006 stack_pointer_rtx)),
22010 gcc_unreachable ();
22012 result = gen_rtx_MEM (mode, stack_pointer_rtx);
22017 /* Free operand from the memory. */
22019 ix86_free_from_memory (enum machine_mode mode)
22021 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
22025 if (mode == DImode || TARGET_64BIT)
22029 /* Use LEA to deallocate stack space. In peephole2 it will be converted
22030 to pop or add instruction if registers are available. */
22031 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
22032 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
22037 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
22038 QImode must go into class Q_REGS.
22039 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
22040 movdf to do mem-to-mem moves through integer regs. */
22042 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
22044 enum machine_mode mode = GET_MODE (x);
22046 /* We're only allowed to return a subclass of CLASS. Many of the
22047 following checks fail for NO_REGS, so eliminate that early. */
22048 if (regclass == NO_REGS)
22051 /* All classes can load zeros. */
22052 if (x == CONST0_RTX (mode))
22055 /* Force constants into memory if we are loading a (nonzero) constant into
22056 an MMX or SSE register. This is because there are no MMX/SSE instructions
22057 to load from a constant. */
22059 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
22062 /* Prefer SSE regs only, if we can use them for math. */
22063 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
22064 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
22066 /* Floating-point constants need more complex checks. */
22067 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
22069 /* General regs can load everything. */
22070 if (reg_class_subset_p (regclass, GENERAL_REGS))
22073 /* Floats can load 0 and 1 plus some others. Note that we eliminated
22074 zero above. We only want to wind up preferring 80387 registers if
22075 we plan on doing computation with them. */
22077 && standard_80387_constant_p (x))
22079 /* Limit class to non-sse. */
22080 if (regclass == FLOAT_SSE_REGS)
22082 if (regclass == FP_TOP_SSE_REGS)
22084 if (regclass == FP_SECOND_SSE_REGS)
22085 return FP_SECOND_REG;
22086 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
22093 /* Generally when we see PLUS here, it's the function invariant
22094 (plus soft-fp const_int). Which can only be computed into general
22096 if (GET_CODE (x) == PLUS)
22097 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
22099 /* QImode constants are easy to load, but non-constant QImode data
22100 must go into Q_REGS. */
22101 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
22103 if (reg_class_subset_p (regclass, Q_REGS))
22105 if (reg_class_subset_p (Q_REGS, regclass))
22113 /* Discourage putting floating-point values in SSE registers unless
22114 SSE math is being used, and likewise for the 387 registers. */
22116 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
22118 enum machine_mode mode = GET_MODE (x);
22120 /* Restrict the output reload class to the register bank that we are doing
22121 math on. If we would like not to return a subset of CLASS, reject this
22122 alternative: if reload cannot do this, it will still use its choice. */
22123 mode = GET_MODE (x);
22124 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
22125 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
22127 if (X87_FLOAT_MODE_P (mode))
22129 if (regclass == FP_TOP_SSE_REGS)
22131 else if (regclass == FP_SECOND_SSE_REGS)
22132 return FP_SECOND_REG;
22134 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
22140 static enum reg_class
22141 ix86_secondary_reload (bool in_p, rtx x, enum reg_class class,
22142 enum machine_mode mode,
22143 secondary_reload_info *sri ATTRIBUTE_UNUSED)
22145 /* QImode spills from non-QI registers require
22146 intermediate register on 32bit targets. */
22147 if (!in_p && mode == QImode && !TARGET_64BIT
22148 && (class == GENERAL_REGS
22149 || class == LEGACY_REGS
22150 || class == INDEX_REGS))
22159 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
22160 regno = true_regnum (x);
22162 /* Return Q_REGS if the operand is in memory. */
22170 /* If we are copying between general and FP registers, we need a memory
22171 location. The same is true for SSE and MMX registers.
22173 To optimize register_move_cost performance, allow inline variant.
22175 The macro can't work reliably when one of the CLASSES is class containing
22176 registers from multiple units (SSE, MMX, integer). We avoid this by never
22177 combining those units in single alternative in the machine description.
22178 Ensure that this constraint holds to avoid unexpected surprises.
22180 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
22181 enforce these sanity checks. */
22184 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22185 enum machine_mode mode, int strict)
22187 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
22188 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
22189 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
22190 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
22191 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
22192 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
22194 gcc_assert (!strict);
22198 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
22201 /* ??? This is a lie. We do have moves between mmx/general, and for
22202 mmx/sse2. But by saying we need secondary memory we discourage the
22203 register allocator from using the mmx registers unless needed. */
22204 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
22207 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22209 /* SSE1 doesn't have any direct moves from other classes. */
22213 /* If the target says that inter-unit moves are more expensive
22214 than moving through memory, then don't generate them. */
22215 if (!TARGET_INTER_UNIT_MOVES)
22218 /* Between SSE and general, we have moves no larger than word size. */
22219 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
22227 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22228 enum machine_mode mode, int strict)
22230 return inline_secondary_memory_needed (class1, class2, mode, strict);
22233 /* Return true if the registers in CLASS cannot represent the change from
22234 modes FROM to TO. */
22237 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
22238 enum reg_class regclass)
22243 /* x87 registers can't do subreg at all, as all values are reformatted
22244 to extended precision. */
22245 if (MAYBE_FLOAT_CLASS_P (regclass))
22248 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
22250 /* Vector registers do not support QI or HImode loads. If we don't
22251 disallow a change to these modes, reload will assume it's ok to
22252 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
22253 the vec_dupv4hi pattern. */
22254 if (GET_MODE_SIZE (from) < 4)
22257 /* Vector registers do not support subreg with nonzero offsets, which
22258 are otherwise valid for integer registers. Since we can't see
22259 whether we have a nonzero offset from here, prohibit all
22260 nonparadoxical subregs changing size. */
22261 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
22268 /* Return the cost of moving data of mode M between a
22269 register and memory. A value of 2 is the default; this cost is
22270 relative to those in `REGISTER_MOVE_COST'.
22272 This function is used extensively by register_move_cost that is used to
22273 build tables at startup. Make it inline in this case.
22274 When IN is 2, return maximum of in and out move cost.
22276 If moving between registers and memory is more expensive than
22277 between two registers, you should define this macro to express the
22280 Model also increased moving costs of QImode registers in non
22284 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
22288 if (FLOAT_CLASS_P (regclass))
22306 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
22307 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
22309 if (SSE_CLASS_P (regclass))
22312 switch (GET_MODE_SIZE (mode))
22327 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
22328 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
22330 if (MMX_CLASS_P (regclass))
22333 switch (GET_MODE_SIZE (mode))
22345 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
22346 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
22348 switch (GET_MODE_SIZE (mode))
22351 if (Q_CLASS_P (regclass) || TARGET_64BIT)
22354 return ix86_cost->int_store[0];
22355 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
22356 cost = ix86_cost->movzbl_load;
22358 cost = ix86_cost->int_load[0];
22360 return MAX (cost, ix86_cost->int_store[0]);
22366 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
22368 return ix86_cost->movzbl_load;
22370 return ix86_cost->int_store[0] + 4;
22375 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
22376 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
22378 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
22379 if (mode == TFmode)
22382 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
22384 cost = ix86_cost->int_load[2];
22386 cost = ix86_cost->int_store[2];
22387 return (cost * (((int) GET_MODE_SIZE (mode)
22388 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
22393 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
22395 return inline_memory_move_cost (mode, regclass, in);
22399 /* Return the cost of moving data from a register in class CLASS1 to
22400 one in class CLASS2.
22402 It is not required that the cost always equal 2 when FROM is the same as TO;
22403 on some machines it is expensive to move between registers if they are not
22404 general registers. */
22407 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22408 enum reg_class class2)
22410 /* In case we require secondary memory, compute cost of the store followed
22411 by load. In order to avoid bad register allocation choices, we need
22412 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22414 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22418 cost += inline_memory_move_cost (mode, class1, 2);
22419 cost += inline_memory_move_cost (mode, class2, 2);
22421 /* In case of copying from general_purpose_register we may emit multiple
22422 stores followed by single load causing memory size mismatch stall.
22423 Count this as arbitrarily high cost of 20. */
22424 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22427 /* In the case of FP/MMX moves, the registers actually overlap, and we
22428 have to switch modes in order to treat them differently. */
22429 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22430 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22436 /* Moves between SSE/MMX and integer unit are expensive. */
22437 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22438 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22440 /* ??? By keeping returned value relatively high, we limit the number
22441 of moves between integer and MMX/SSE registers for all targets.
22442 Additionally, high value prevents problem with x86_modes_tieable_p(),
22443 where integer modes in MMX/SSE registers are not tieable
22444 because of missing QImode and HImode moves to, from or between
22445 MMX/SSE registers. */
22446 return MAX (8, ix86_cost->mmxsse_to_integer);
22448 if (MAYBE_FLOAT_CLASS_P (class1))
22449 return ix86_cost->fp_move;
22450 if (MAYBE_SSE_CLASS_P (class1))
22451 return ix86_cost->sse_move;
22452 if (MAYBE_MMX_CLASS_P (class1))
22453 return ix86_cost->mmx_move;
22457 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22460 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22462 /* Flags and only flags can only hold CCmode values. */
22463 if (CC_REGNO_P (regno))
22464 return GET_MODE_CLASS (mode) == MODE_CC;
22465 if (GET_MODE_CLASS (mode) == MODE_CC
22466 || GET_MODE_CLASS (mode) == MODE_RANDOM
22467 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22469 if (FP_REGNO_P (regno))
22470 return VALID_FP_MODE_P (mode);
22471 if (SSE_REGNO_P (regno))
22473 /* We implement the move patterns for all vector modes into and
22474 out of SSE registers, even when no operation instructions
22476 return (VALID_SSE_REG_MODE (mode)
22477 || VALID_SSE2_REG_MODE (mode)
22478 || VALID_MMX_REG_MODE (mode)
22479 || VALID_MMX_REG_MODE_3DNOW (mode));
22481 if (MMX_REGNO_P (regno))
22483 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22484 so if the register is available at all, then we can move data of
22485 the given mode into or out of it. */
22486 return (VALID_MMX_REG_MODE (mode)
22487 || VALID_MMX_REG_MODE_3DNOW (mode));
22490 if (mode == QImode)
22492 /* Take care for QImode values - they can be in non-QI regs,
22493 but then they do cause partial register stalls. */
22494 if (regno < 4 || TARGET_64BIT)
22496 if (!TARGET_PARTIAL_REG_STALL)
22498 return reload_in_progress || reload_completed;
22500 /* We handle both integer and floats in the general purpose registers. */
22501 else if (VALID_INT_MODE_P (mode))
22503 else if (VALID_FP_MODE_P (mode))
22505 else if (VALID_DFP_MODE_P (mode))
22507 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22508 on to use that value in smaller contexts, this can easily force a
22509 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22510 supporting DImode, allow it. */
22511 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22517 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22518 tieable integer mode. */
22521 ix86_tieable_integer_mode_p (enum machine_mode mode)
22530 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22533 return TARGET_64BIT;
22540 /* Return true if MODE1 is accessible in a register that can hold MODE2
22541 without copying. That is, all register classes that can hold MODE2
22542 can also hold MODE1. */
22545 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22547 if (mode1 == mode2)
22550 if (ix86_tieable_integer_mode_p (mode1)
22551 && ix86_tieable_integer_mode_p (mode2))
22554 /* MODE2 being XFmode implies fp stack or general regs, which means we
22555 can tie any smaller floating point modes to it. Note that we do not
22556 tie this with TFmode. */
22557 if (mode2 == XFmode)
22558 return mode1 == SFmode || mode1 == DFmode;
22560 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22561 that we can tie it with SFmode. */
22562 if (mode2 == DFmode)
22563 return mode1 == SFmode;
22565 /* If MODE2 is only appropriate for an SSE register, then tie with
22566 any other mode acceptable to SSE registers. */
22567 if (GET_MODE_SIZE (mode2) == 16
22568 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22569 return (GET_MODE_SIZE (mode1) == 16
22570 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22572 /* If MODE2 is appropriate for an MMX register, then tie
22573 with any other mode acceptable to MMX registers. */
22574 if (GET_MODE_SIZE (mode2) == 8
22575 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22576 return (GET_MODE_SIZE (mode1) == 8
22577 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22582 /* Compute a (partial) cost for rtx X. Return true if the complete
22583 cost has been computed, and false if subexpressions should be
22584 scanned. In either case, *TOTAL contains the cost result. */
22587 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22589 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22590 enum machine_mode mode = GET_MODE (x);
22598 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22600 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22602 else if (flag_pic && SYMBOLIC_CONST (x)
22604 || (!GET_CODE (x) != LABEL_REF
22605 && (GET_CODE (x) != SYMBOL_REF
22606 || !SYMBOL_REF_LOCAL_P (x)))))
22613 if (mode == VOIDmode)
22616 switch (standard_80387_constant_p (x))
22621 default: /* Other constants */
22626 /* Start with (MEM (SYMBOL_REF)), since that's where
22627 it'll probably end up. Add a penalty for size. */
22628 *total = (COSTS_N_INSNS (1)
22629 + (flag_pic != 0 && !TARGET_64BIT)
22630 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22636 /* The zero extensions is often completely free on x86_64, so make
22637 it as cheap as possible. */
22638 if (TARGET_64BIT && mode == DImode
22639 && GET_MODE (XEXP (x, 0)) == SImode)
22641 else if (TARGET_ZERO_EXTEND_WITH_AND)
22642 *total = ix86_cost->add;
22644 *total = ix86_cost->movzx;
22648 *total = ix86_cost->movsx;
22652 if (CONST_INT_P (XEXP (x, 1))
22653 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22655 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22658 *total = ix86_cost->add;
22661 if ((value == 2 || value == 3)
22662 && ix86_cost->lea <= ix86_cost->shift_const)
22664 *total = ix86_cost->lea;
22674 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22676 if (CONST_INT_P (XEXP (x, 1)))
22678 if (INTVAL (XEXP (x, 1)) > 32)
22679 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22681 *total = ix86_cost->shift_const * 2;
22685 if (GET_CODE (XEXP (x, 1)) == AND)
22686 *total = ix86_cost->shift_var * 2;
22688 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22693 if (CONST_INT_P (XEXP (x, 1)))
22694 *total = ix86_cost->shift_const;
22696 *total = ix86_cost->shift_var;
22701 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22703 /* ??? SSE scalar cost should be used here. */
22704 *total = ix86_cost->fmul;
22707 else if (X87_FLOAT_MODE_P (mode))
22709 *total = ix86_cost->fmul;
22712 else if (FLOAT_MODE_P (mode))
22714 /* ??? SSE vector cost should be used here. */
22715 *total = ix86_cost->fmul;
22720 rtx op0 = XEXP (x, 0);
22721 rtx op1 = XEXP (x, 1);
22723 if (CONST_INT_P (XEXP (x, 1)))
22725 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22726 for (nbits = 0; value != 0; value &= value - 1)
22730 /* This is arbitrary. */
22733 /* Compute costs correctly for widening multiplication. */
22734 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22735 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22736 == GET_MODE_SIZE (mode))
22738 int is_mulwiden = 0;
22739 enum machine_mode inner_mode = GET_MODE (op0);
22741 if (GET_CODE (op0) == GET_CODE (op1))
22742 is_mulwiden = 1, op1 = XEXP (op1, 0);
22743 else if (CONST_INT_P (op1))
22745 if (GET_CODE (op0) == SIGN_EXTEND)
22746 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22749 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22753 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22756 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22757 + nbits * ix86_cost->mult_bit
22758 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22767 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22768 /* ??? SSE cost should be used here. */
22769 *total = ix86_cost->fdiv;
22770 else if (X87_FLOAT_MODE_P (mode))
22771 *total = ix86_cost->fdiv;
22772 else if (FLOAT_MODE_P (mode))
22773 /* ??? SSE vector cost should be used here. */
22774 *total = ix86_cost->fdiv;
22776 *total = ix86_cost->divide[MODE_INDEX (mode)];
22780 if (GET_MODE_CLASS (mode) == MODE_INT
22781 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22783 if (GET_CODE (XEXP (x, 0)) == PLUS
22784 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22785 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22786 && CONSTANT_P (XEXP (x, 1)))
22788 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22789 if (val == 2 || val == 4 || val == 8)
22791 *total = ix86_cost->lea;
22792 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22793 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22795 *total += rtx_cost (XEXP (x, 1), outer_code);
22799 else if (GET_CODE (XEXP (x, 0)) == MULT
22800 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22802 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22803 if (val == 2 || val == 4 || val == 8)
22805 *total = ix86_cost->lea;
22806 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22807 *total += rtx_cost (XEXP (x, 1), outer_code);
22811 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22813 *total = ix86_cost->lea;
22814 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22815 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22816 *total += rtx_cost (XEXP (x, 1), outer_code);
22823 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22825 /* ??? SSE cost should be used here. */
22826 *total = ix86_cost->fadd;
22829 else if (X87_FLOAT_MODE_P (mode))
22831 *total = ix86_cost->fadd;
22834 else if (FLOAT_MODE_P (mode))
22836 /* ??? SSE vector cost should be used here. */
22837 *total = ix86_cost->fadd;
22845 if (!TARGET_64BIT && mode == DImode)
22847 *total = (ix86_cost->add * 2
22848 + (rtx_cost (XEXP (x, 0), outer_code)
22849 << (GET_MODE (XEXP (x, 0)) != DImode))
22850 + (rtx_cost (XEXP (x, 1), outer_code)
22851 << (GET_MODE (XEXP (x, 1)) != DImode)));
22857 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22859 /* ??? SSE cost should be used here. */
22860 *total = ix86_cost->fchs;
22863 else if (X87_FLOAT_MODE_P (mode))
22865 *total = ix86_cost->fchs;
22868 else if (FLOAT_MODE_P (mode))
22870 /* ??? SSE vector cost should be used here. */
22871 *total = ix86_cost->fchs;
22877 if (!TARGET_64BIT && mode == DImode)
22878 *total = ix86_cost->add * 2;
22880 *total = ix86_cost->add;
22884 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22885 && XEXP (XEXP (x, 0), 1) == const1_rtx
22886 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22887 && XEXP (x, 1) == const0_rtx)
22889 /* This kind of construct is implemented using test[bwl].
22890 Treat it as if we had an AND. */
22891 *total = (ix86_cost->add
22892 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22893 + rtx_cost (const1_rtx, outer_code));
22899 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22904 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22905 /* ??? SSE cost should be used here. */
22906 *total = ix86_cost->fabs;
22907 else if (X87_FLOAT_MODE_P (mode))
22908 *total = ix86_cost->fabs;
22909 else if (FLOAT_MODE_P (mode))
22910 /* ??? SSE vector cost should be used here. */
22911 *total = ix86_cost->fabs;
22915 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22916 /* ??? SSE cost should be used here. */
22917 *total = ix86_cost->fsqrt;
22918 else if (X87_FLOAT_MODE_P (mode))
22919 *total = ix86_cost->fsqrt;
22920 else if (FLOAT_MODE_P (mode))
22921 /* ??? SSE vector cost should be used here. */
22922 *total = ix86_cost->fsqrt;
22926 if (XINT (x, 1) == UNSPEC_TP)
22937 static int current_machopic_label_num;
22939 /* Given a symbol name and its associated stub, write out the
22940 definition of the stub. */
22943 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22945 unsigned int length;
22946 char *binder_name, *symbol_name, lazy_ptr_name[32];
22947 int label = ++current_machopic_label_num;
22949 /* For 64-bit we shouldn't get here. */
22950 gcc_assert (!TARGET_64BIT);
22952 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22953 symb = (*targetm.strip_name_encoding) (symb);
22955 length = strlen (stub);
22956 binder_name = alloca (length + 32);
22957 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22959 length = strlen (symb);
22960 symbol_name = alloca (length + 32);
22961 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22963 sprintf (lazy_ptr_name, "L%d$lz", label);
22966 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22968 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22970 fprintf (file, "%s:\n", stub);
22971 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22975 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22976 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22977 fprintf (file, "\tjmp\t*%%edx\n");
22980 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22982 fprintf (file, "%s:\n", binder_name);
22986 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22987 fprintf (file, "\tpushl\t%%eax\n");
22990 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22992 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22994 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22995 fprintf (file, "%s:\n", lazy_ptr_name);
22996 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22997 fprintf (file, "\t.long %s\n", binder_name);
23001 darwin_x86_file_end (void)
23003 darwin_file_end ();
23006 #endif /* TARGET_MACHO */
23008 /* Order the registers for register allocator. */
23011 x86_order_regs_for_local_alloc (void)
23016 /* First allocate the local general purpose registers. */
23017 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
23018 if (GENERAL_REGNO_P (i) && call_used_regs[i])
23019 reg_alloc_order [pos++] = i;
23021 /* Global general purpose registers. */
23022 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
23023 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
23024 reg_alloc_order [pos++] = i;
23026 /* x87 registers come first in case we are doing FP math
23028 if (!TARGET_SSE_MATH)
23029 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
23030 reg_alloc_order [pos++] = i;
23032 /* SSE registers. */
23033 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
23034 reg_alloc_order [pos++] = i;
23035 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
23036 reg_alloc_order [pos++] = i;
23038 /* x87 registers. */
23039 if (TARGET_SSE_MATH)
23040 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
23041 reg_alloc_order [pos++] = i;
23043 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
23044 reg_alloc_order [pos++] = i;
23046 /* Initialize the rest of array as we do not allocate some registers
23048 while (pos < FIRST_PSEUDO_REGISTER)
23049 reg_alloc_order [pos++] = 0;
23052 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
23053 struct attribute_spec.handler. */
23055 ix86_handle_struct_attribute (tree *node, tree name,
23056 tree args ATTRIBUTE_UNUSED,
23057 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
23060 if (DECL_P (*node))
23062 if (TREE_CODE (*node) == TYPE_DECL)
23063 type = &TREE_TYPE (*node);
23068 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
23069 || TREE_CODE (*type) == UNION_TYPE)))
23071 warning (OPT_Wattributes, "%qs attribute ignored",
23072 IDENTIFIER_POINTER (name));
23073 *no_add_attrs = true;
23076 else if ((is_attribute_p ("ms_struct", name)
23077 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
23078 || ((is_attribute_p ("gcc_struct", name)
23079 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
23081 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
23082 IDENTIFIER_POINTER (name));
23083 *no_add_attrs = true;
23090 ix86_ms_bitfield_layout_p (const_tree record_type)
23092 return (TARGET_MS_BITFIELD_LAYOUT &&
23093 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
23094 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
23097 /* Returns an expression indicating where the this parameter is
23098 located on entry to the FUNCTION. */
23101 x86_this_parameter (tree function)
23103 tree type = TREE_TYPE (function);
23104 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
23109 const int *parm_regs;
23111 if (ix86_function_type_abi (type) == MS_ABI)
23112 parm_regs = x86_64_ms_abi_int_parameter_registers;
23114 parm_regs = x86_64_int_parameter_registers;
23115 return gen_rtx_REG (DImode, parm_regs[aggr]);
23118 nregs = ix86_function_regparm (type, function);
23120 if (nregs > 0 && !stdarg_p (type))
23124 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
23125 regno = aggr ? DX_REG : CX_REG;
23133 return gen_rtx_MEM (SImode,
23134 plus_constant (stack_pointer_rtx, 4));
23137 return gen_rtx_REG (SImode, regno);
23140 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
23143 /* Determine whether x86_output_mi_thunk can succeed. */
23146 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
23147 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
23148 HOST_WIDE_INT vcall_offset, const_tree function)
23150 /* 64-bit can handle anything. */
23154 /* For 32-bit, everything's fine if we have one free register. */
23155 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
23158 /* Need a free register for vcall_offset. */
23162 /* Need a free register for GOT references. */
23163 if (flag_pic && !(*targetm.binds_local_p) (function))
23166 /* Otherwise ok. */
23170 /* Output the assembler code for a thunk function. THUNK_DECL is the
23171 declaration for the thunk function itself, FUNCTION is the decl for
23172 the target function. DELTA is an immediate constant offset to be
23173 added to THIS. If VCALL_OFFSET is nonzero, the word at
23174 *(*this + vcall_offset) should be added to THIS. */
23177 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
23178 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
23179 HOST_WIDE_INT vcall_offset, tree function)
23182 rtx this_param = x86_this_parameter (function);
23185 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
23186 pull it in now and let DELTA benefit. */
23187 if (REG_P (this_param))
23188 this_reg = this_param;
23189 else if (vcall_offset)
23191 /* Put the this parameter into %eax. */
23192 xops[0] = this_param;
23193 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
23194 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
23197 this_reg = NULL_RTX;
23199 /* Adjust the this parameter by a fixed constant. */
23202 xops[0] = GEN_INT (delta);
23203 xops[1] = this_reg ? this_reg : this_param;
23206 if (!x86_64_general_operand (xops[0], DImode))
23208 tmp = gen_rtx_REG (DImode, R10_REG);
23210 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
23212 xops[1] = this_param;
23214 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
23217 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
23220 /* Adjust the this parameter by a value stored in the vtable. */
23224 tmp = gen_rtx_REG (DImode, R10_REG);
23227 int tmp_regno = CX_REG;
23228 if (lookup_attribute ("fastcall",
23229 TYPE_ATTRIBUTES (TREE_TYPE (function))))
23230 tmp_regno = AX_REG;
23231 tmp = gen_rtx_REG (SImode, tmp_regno);
23234 xops[0] = gen_rtx_MEM (Pmode, this_reg);
23236 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
23238 /* Adjust the this parameter. */
23239 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
23240 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
23242 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
23243 xops[0] = GEN_INT (vcall_offset);
23245 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23246 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
23248 xops[1] = this_reg;
23249 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
23252 /* If necessary, drop THIS back to its stack slot. */
23253 if (this_reg && this_reg != this_param)
23255 xops[0] = this_reg;
23256 xops[1] = this_param;
23257 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
23260 xops[0] = XEXP (DECL_RTL (function), 0);
23263 if (!flag_pic || (*targetm.binds_local_p) (function))
23264 output_asm_insn ("jmp\t%P0", xops);
23265 /* All thunks should be in the same object as their target,
23266 and thus binds_local_p should be true. */
23267 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
23268 gcc_unreachable ();
23271 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
23272 tmp = gen_rtx_CONST (Pmode, tmp);
23273 tmp = gen_rtx_MEM (QImode, tmp);
23275 output_asm_insn ("jmp\t%A0", xops);
23280 if (!flag_pic || (*targetm.binds_local_p) (function))
23281 output_asm_insn ("jmp\t%P0", xops);
23286 rtx sym_ref = XEXP (DECL_RTL (function), 0);
23287 tmp = (gen_rtx_SYMBOL_REF
23289 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
23290 tmp = gen_rtx_MEM (QImode, tmp);
23292 output_asm_insn ("jmp\t%0", xops);
23295 #endif /* TARGET_MACHO */
23297 tmp = gen_rtx_REG (SImode, CX_REG);
23298 output_set_got (tmp, NULL_RTX);
23301 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
23302 output_asm_insn ("jmp\t{*}%1", xops);
23308 x86_file_start (void)
23310 default_file_start ();
23312 darwin_file_start ();
23314 if (X86_FILE_START_VERSION_DIRECTIVE)
23315 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
23316 if (X86_FILE_START_FLTUSED)
23317 fputs ("\t.global\t__fltused\n", asm_out_file);
23318 if (ix86_asm_dialect == ASM_INTEL)
23319 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
23323 x86_field_alignment (tree field, int computed)
23325 enum machine_mode mode;
23326 tree type = TREE_TYPE (field);
23328 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
23330 mode = TYPE_MODE (strip_array_types (type));
23331 if (mode == DFmode || mode == DCmode
23332 || GET_MODE_CLASS (mode) == MODE_INT
23333 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
23334 return MIN (32, computed);
23338 /* Output assembler code to FILE to increment profiler label # LABELNO
23339 for profiling a function entry. */
23341 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
23345 #ifndef NO_PROFILE_COUNTERS
23346 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
23349 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
23350 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
23352 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23356 #ifndef NO_PROFILE_COUNTERS
23357 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
23358 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
23360 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
23364 #ifndef NO_PROFILE_COUNTERS
23365 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
23366 PROFILE_COUNT_REGISTER);
23368 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23372 /* We don't have exact information about the insn sizes, but we may assume
23373 quite safely that we are informed about all 1 byte insns and memory
23374 address sizes. This is enough to eliminate unnecessary padding in
23378 min_insn_size (rtx insn)
23382 if (!INSN_P (insn) || !active_insn_p (insn))
23385 /* Discard alignments we've emit and jump instructions. */
23386 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
23387 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
23390 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
23391 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
23394 /* Important case - calls are always 5 bytes.
23395 It is common to have many calls in the row. */
23397 && symbolic_reference_mentioned_p (PATTERN (insn))
23398 && !SIBLING_CALL_P (insn))
23400 if (get_attr_length (insn) <= 1)
23403 /* For normal instructions we may rely on the sizes of addresses
23404 and the presence of symbol to require 4 bytes of encoding.
23405 This is not the case for jumps where references are PC relative. */
23406 if (!JUMP_P (insn))
23408 l = get_attr_length_address (insn);
23409 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23418 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23422 ix86_avoid_jump_misspredicts (void)
23424 rtx insn, start = get_insns ();
23425 int nbytes = 0, njumps = 0;
23428 /* Look for all minimal intervals of instructions containing 4 jumps.
23429 The intervals are bounded by START and INSN. NBYTES is the total
23430 size of instructions in the interval including INSN and not including
23431 START. When the NBYTES is smaller than 16 bytes, it is possible
23432 that the end of START and INSN ends up in the same 16byte page.
23434 The smallest offset in the page INSN can start is the case where START
23435 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23436 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23438 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23441 nbytes += min_insn_size (insn);
23443 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23444 INSN_UID (insn), min_insn_size (insn));
23446 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23447 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23455 start = NEXT_INSN (start);
23456 if ((JUMP_P (start)
23457 && GET_CODE (PATTERN (start)) != ADDR_VEC
23458 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23460 njumps--, isjump = 1;
23463 nbytes -= min_insn_size (start);
23465 gcc_assert (njumps >= 0);
23467 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23468 INSN_UID (start), INSN_UID (insn), nbytes);
23470 if (njumps == 3 && isjump && nbytes < 16)
23472 int padsize = 15 - nbytes + min_insn_size (insn);
23475 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23476 INSN_UID (insn), padsize);
23477 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23482 /* AMD Athlon works faster
23483 when RET is not destination of conditional jump or directly preceded
23484 by other jump instruction. We avoid the penalty by inserting NOP just
23485 before the RET instructions in such cases. */
23487 ix86_pad_returns (void)
23492 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23494 basic_block bb = e->src;
23495 rtx ret = BB_END (bb);
23497 bool replace = false;
23499 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23500 || !maybe_hot_bb_p (bb))
23502 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23503 if (active_insn_p (prev) || LABEL_P (prev))
23505 if (prev && LABEL_P (prev))
23510 FOR_EACH_EDGE (e, ei, bb->preds)
23511 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23512 && !(e->flags & EDGE_FALLTHRU))
23517 prev = prev_active_insn (ret);
23519 && ((JUMP_P (prev) && any_condjump_p (prev))
23522 /* Empty functions get branch mispredict even when the jump destination
23523 is not visible to us. */
23524 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23529 emit_insn_before (gen_return_internal_long (), ret);
23535 /* Implement machine specific optimizations. We implement padding of returns
23536 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23540 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23541 ix86_pad_returns ();
23542 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23543 ix86_avoid_jump_misspredicts ();
23546 /* Return nonzero when QImode register that must be represented via REX prefix
23549 x86_extended_QIreg_mentioned_p (rtx insn)
23552 extract_insn_cached (insn);
23553 for (i = 0; i < recog_data.n_operands; i++)
23554 if (REG_P (recog_data.operand[i])
23555 && REGNO (recog_data.operand[i]) >= 4)
23560 /* Return nonzero when P points to register encoded via REX prefix.
23561 Called via for_each_rtx. */
23563 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23565 unsigned int regno;
23568 regno = REGNO (*p);
23569 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23572 /* Return true when INSN mentions register that must be encoded using REX
23575 x86_extended_reg_mentioned_p (rtx insn)
23577 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23580 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23581 optabs would emit if we didn't have TFmode patterns. */
23584 x86_emit_floatuns (rtx operands[2])
23586 rtx neglab, donelab, i0, i1, f0, in, out;
23587 enum machine_mode mode, inmode;
23589 inmode = GET_MODE (operands[1]);
23590 gcc_assert (inmode == SImode || inmode == DImode);
23593 in = force_reg (inmode, operands[1]);
23594 mode = GET_MODE (out);
23595 neglab = gen_label_rtx ();
23596 donelab = gen_label_rtx ();
23597 f0 = gen_reg_rtx (mode);
23599 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23601 expand_float (out, in, 0);
23603 emit_jump_insn (gen_jump (donelab));
23606 emit_label (neglab);
23608 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23610 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23612 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23614 expand_float (f0, i0, 0);
23616 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23618 emit_label (donelab);
23621 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23622 with all elements equal to VAR. Return true if successful. */
23625 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23626 rtx target, rtx val)
23628 enum machine_mode smode, wsmode, wvmode;
23643 val = force_reg (GET_MODE_INNER (mode), val);
23644 x = gen_rtx_VEC_DUPLICATE (mode, val);
23645 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23651 if (TARGET_SSE || TARGET_3DNOW_A)
23653 val = gen_lowpart (SImode, val);
23654 x = gen_rtx_TRUNCATE (HImode, val);
23655 x = gen_rtx_VEC_DUPLICATE (mode, x);
23656 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23678 /* Extend HImode to SImode using a paradoxical SUBREG. */
23679 tmp1 = gen_reg_rtx (SImode);
23680 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23681 /* Insert the SImode value as low element of V4SImode vector. */
23682 tmp2 = gen_reg_rtx (V4SImode);
23683 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23684 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23685 CONST0_RTX (V4SImode),
23687 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23688 /* Cast the V4SImode vector back to a V8HImode vector. */
23689 tmp1 = gen_reg_rtx (V8HImode);
23690 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23691 /* Duplicate the low short through the whole low SImode word. */
23692 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23693 /* Cast the V8HImode vector back to a V4SImode vector. */
23694 tmp2 = gen_reg_rtx (V4SImode);
23695 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23696 /* Replicate the low element of the V4SImode vector. */
23697 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23698 /* Cast the V2SImode back to V8HImode, and store in target. */
23699 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23710 /* Extend QImode to SImode using a paradoxical SUBREG. */
23711 tmp1 = gen_reg_rtx (SImode);
23712 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23713 /* Insert the SImode value as low element of V4SImode vector. */
23714 tmp2 = gen_reg_rtx (V4SImode);
23715 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23716 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23717 CONST0_RTX (V4SImode),
23719 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23720 /* Cast the V4SImode vector back to a V16QImode vector. */
23721 tmp1 = gen_reg_rtx (V16QImode);
23722 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23723 /* Duplicate the low byte through the whole low SImode word. */
23724 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23725 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23726 /* Cast the V16QImode vector back to a V4SImode vector. */
23727 tmp2 = gen_reg_rtx (V4SImode);
23728 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23729 /* Replicate the low element of the V4SImode vector. */
23730 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23731 /* Cast the V2SImode back to V16QImode, and store in target. */
23732 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23740 /* Replicate the value once into the next wider mode and recurse. */
23741 val = convert_modes (wsmode, smode, val, true);
23742 x = expand_simple_binop (wsmode, ASHIFT, val,
23743 GEN_INT (GET_MODE_BITSIZE (smode)),
23744 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23745 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23747 x = gen_reg_rtx (wvmode);
23748 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23749 gcc_unreachable ();
23750 emit_move_insn (target, gen_lowpart (mode, x));
23758 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23759 whose ONE_VAR element is VAR, and other elements are zero. Return true
23763 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23764 rtx target, rtx var, int one_var)
23766 enum machine_mode vsimode;
23769 bool use_vector_set = false;
23774 use_vector_set = TARGET_64BIT && TARGET_SSE4_1;
23779 use_vector_set = TARGET_SSE4_1;
23782 use_vector_set = TARGET_SSE2;
23785 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
23791 if (use_vector_set)
23793 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
23794 var = force_reg (GET_MODE_INNER (mode), var);
23795 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23811 var = force_reg (GET_MODE_INNER (mode), var);
23812 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23813 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23818 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23819 new_target = gen_reg_rtx (mode);
23821 new_target = target;
23822 var = force_reg (GET_MODE_INNER (mode), var);
23823 x = gen_rtx_VEC_DUPLICATE (mode, var);
23824 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23825 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23828 /* We need to shuffle the value to the correct position, so
23829 create a new pseudo to store the intermediate result. */
23831 /* With SSE2, we can use the integer shuffle insns. */
23832 if (mode != V4SFmode && TARGET_SSE2)
23834 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23836 GEN_INT (one_var == 1 ? 0 : 1),
23837 GEN_INT (one_var == 2 ? 0 : 1),
23838 GEN_INT (one_var == 3 ? 0 : 1)));
23839 if (target != new_target)
23840 emit_move_insn (target, new_target);
23844 /* Otherwise convert the intermediate result to V4SFmode and
23845 use the SSE1 shuffle instructions. */
23846 if (mode != V4SFmode)
23848 tmp = gen_reg_rtx (V4SFmode);
23849 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23854 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23856 GEN_INT (one_var == 1 ? 0 : 1),
23857 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23858 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23860 if (mode != V4SFmode)
23861 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23862 else if (tmp != target)
23863 emit_move_insn (target, tmp);
23865 else if (target != new_target)
23866 emit_move_insn (target, new_target);
23871 vsimode = V4SImode;
23877 vsimode = V2SImode;
23883 /* Zero extend the variable element to SImode and recurse. */
23884 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23886 x = gen_reg_rtx (vsimode);
23887 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23889 gcc_unreachable ();
23891 emit_move_insn (target, gen_lowpart (mode, x));
23899 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23900 consisting of the values in VALS. It is known that all elements
23901 except ONE_VAR are constants. Return true if successful. */
23904 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23905 rtx target, rtx vals, int one_var)
23907 rtx var = XVECEXP (vals, 0, one_var);
23908 enum machine_mode wmode;
23911 const_vec = copy_rtx (vals);
23912 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23913 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23921 /* For the two element vectors, it's just as easy to use
23922 the general case. */
23940 /* There's no way to set one QImode entry easily. Combine
23941 the variable value with its adjacent constant value, and
23942 promote to an HImode set. */
23943 x = XVECEXP (vals, 0, one_var ^ 1);
23946 var = convert_modes (HImode, QImode, var, true);
23947 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23948 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23949 x = GEN_INT (INTVAL (x) & 0xff);
23953 var = convert_modes (HImode, QImode, var, true);
23954 x = gen_int_mode (INTVAL (x) << 8, HImode);
23956 if (x != const0_rtx)
23957 var = expand_simple_binop (HImode, IOR, var, x, var,
23958 1, OPTAB_LIB_WIDEN);
23960 x = gen_reg_rtx (wmode);
23961 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23962 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23964 emit_move_insn (target, gen_lowpart (mode, x));
23971 emit_move_insn (target, const_vec);
23972 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23976 /* A subroutine of ix86_expand_vector_init_general. Use vector
23977 concatenate to handle the most general case: all values variable,
23978 and none identical. */
23981 ix86_expand_vector_init_concat (enum machine_mode mode,
23982 rtx target, rtx *ops, int n)
23984 enum machine_mode cmode, hmode = VOIDmode;
23985 rtx first[4], second[2];
24013 gcc_unreachable ();
24016 if (!register_operand (ops[1], cmode))
24017 ops[1] = force_reg (cmode, ops[1]);
24018 if (!register_operand (ops[0], cmode))
24019 ops[0] = force_reg (cmode, ops[0]);
24020 emit_insn (gen_rtx_SET (VOIDmode, target,
24021 gen_rtx_VEC_CONCAT (mode, ops[0],
24035 gcc_unreachable ();
24040 /* FIXME: We process inputs backward to help RA. PR 36222. */
24043 for (; i > 0; i -= 2, j--)
24045 first[j] = gen_reg_rtx (cmode);
24046 v = gen_rtvec (2, ops[i - 1], ops[i]);
24047 ix86_expand_vector_init (false, first[j],
24048 gen_rtx_PARALLEL (cmode, v));
24054 gcc_assert (hmode != VOIDmode);
24055 for (i = j = 0; i < n; i += 2, j++)
24057 second[j] = gen_reg_rtx (hmode);
24058 ix86_expand_vector_init_concat (hmode, second [j],
24062 ix86_expand_vector_init_concat (mode, target, second, n);
24065 ix86_expand_vector_init_concat (mode, target, first, n);
24069 gcc_unreachable ();
24073 /* A subroutine of ix86_expand_vector_init_general. Use vector
24074 interleave to handle the most general case: all values variable,
24075 and none identical. */
24078 ix86_expand_vector_init_interleave (enum machine_mode mode,
24079 rtx target, rtx *ops, int n)
24081 enum machine_mode first_imode, second_imode, third_imode;
24084 rtx (*gen_load_even) (rtx, rtx, rtx);
24085 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
24086 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
24091 gen_load_even = gen_vec_setv8hi;
24092 gen_interleave_first_low = gen_vec_interleave_lowv4si;
24093 gen_interleave_second_low = gen_vec_interleave_lowv2di;
24094 first_imode = V4SImode;
24095 second_imode = V2DImode;
24096 third_imode = VOIDmode;
24099 gen_load_even = gen_vec_setv16qi;
24100 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
24101 gen_interleave_second_low = gen_vec_interleave_lowv4si;
24102 first_imode = V8HImode;
24103 second_imode = V4SImode;
24104 third_imode = V2DImode;
24107 gcc_unreachable ();
24110 for (i = 0; i < n; i++)
24112 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
24113 op0 = gen_reg_rtx (SImode);
24114 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
24116 /* Insert the SImode value as low element of V4SImode vector. */
24117 op1 = gen_reg_rtx (V4SImode);
24118 op0 = gen_rtx_VEC_MERGE (V4SImode,
24119 gen_rtx_VEC_DUPLICATE (V4SImode,
24121 CONST0_RTX (V4SImode),
24123 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
24125 /* Cast the V4SImode vector back to a vector in orignal mode. */
24126 op0 = gen_reg_rtx (mode);
24127 emit_move_insn (op0, gen_lowpart (mode, op1));
24129 /* Load even elements into the second positon. */
24130 emit_insn ((*gen_load_even) (op0, ops [i + i + 1],
24133 /* Cast vector to FIRST_IMODE vector. */
24134 ops[i] = gen_reg_rtx (first_imode);
24135 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
24138 /* Interleave low FIRST_IMODE vectors. */
24139 for (i = j = 0; i < n; i += 2, j++)
24141 op0 = gen_reg_rtx (first_imode);
24142 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
24144 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
24145 ops[j] = gen_reg_rtx (second_imode);
24146 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
24149 /* Interleave low SECOND_IMODE vectors. */
24150 switch (second_imode)
24153 for (i = j = 0; i < n / 2; i += 2, j++)
24155 op0 = gen_reg_rtx (second_imode);
24156 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
24159 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
24161 ops[j] = gen_reg_rtx (third_imode);
24162 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
24164 second_imode = V2DImode;
24165 gen_interleave_second_low = gen_vec_interleave_lowv2di;
24169 op0 = gen_reg_rtx (second_imode);
24170 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
24173 /* Cast the SECOND_IMODE vector back to a vector on original
24175 emit_insn (gen_rtx_SET (VOIDmode, target,
24176 gen_lowpart (mode, op0)));
24180 gcc_unreachable ();
24184 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
24185 all values variable, and none identical. */
24188 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
24189 rtx target, rtx vals)
24198 if (!mmx_ok && !TARGET_SSE)
24206 n = GET_MODE_NUNITS (mode);
24207 for (i = 0; i < n; i++)
24208 ops[i] = XVECEXP (vals, 0, i);
24209 ix86_expand_vector_init_concat (mode, target, ops, n);
24213 if (!TARGET_SSE4_1)
24221 n = GET_MODE_NUNITS (mode);
24222 for (i = 0; i < n; i++)
24223 ops[i] = XVECEXP (vals, 0, i);
24224 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
24232 gcc_unreachable ();
24236 int i, j, n_elts, n_words, n_elt_per_word;
24237 enum machine_mode inner_mode;
24238 rtx words[4], shift;
24240 inner_mode = GET_MODE_INNER (mode);
24241 n_elts = GET_MODE_NUNITS (mode);
24242 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
24243 n_elt_per_word = n_elts / n_words;
24244 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
24246 for (i = 0; i < n_words; ++i)
24248 rtx word = NULL_RTX;
24250 for (j = 0; j < n_elt_per_word; ++j)
24252 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
24253 elt = convert_modes (word_mode, inner_mode, elt, true);
24259 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
24260 word, 1, OPTAB_LIB_WIDEN);
24261 word = expand_simple_binop (word_mode, IOR, word, elt,
24262 word, 1, OPTAB_LIB_WIDEN);
24270 emit_move_insn (target, gen_lowpart (mode, words[0]));
24271 else if (n_words == 2)
24273 rtx tmp = gen_reg_rtx (mode);
24274 emit_clobber (tmp);
24275 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
24276 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
24277 emit_move_insn (target, tmp);
24279 else if (n_words == 4)
24281 rtx tmp = gen_reg_rtx (V4SImode);
24282 gcc_assert (word_mode == SImode);
24283 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
24284 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
24285 emit_move_insn (target, gen_lowpart (mode, tmp));
24288 gcc_unreachable ();
24292 /* Initialize vector TARGET via VALS. Suppress the use of MMX
24293 instructions unless MMX_OK is true. */
24296 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
24298 enum machine_mode mode = GET_MODE (target);
24299 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24300 int n_elts = GET_MODE_NUNITS (mode);
24301 int n_var = 0, one_var = -1;
24302 bool all_same = true, all_const_zero = true;
24306 for (i = 0; i < n_elts; ++i)
24308 x = XVECEXP (vals, 0, i);
24309 if (!(CONST_INT_P (x)
24310 || GET_CODE (x) == CONST_DOUBLE
24311 || GET_CODE (x) == CONST_FIXED))
24312 n_var++, one_var = i;
24313 else if (x != CONST0_RTX (inner_mode))
24314 all_const_zero = false;
24315 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
24319 /* Constants are best loaded from the constant pool. */
24322 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
24326 /* If all values are identical, broadcast the value. */
24328 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
24329 XVECEXP (vals, 0, 0)))
24332 /* Values where only one field is non-constant are best loaded from
24333 the pool and overwritten via move later. */
24337 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
24338 XVECEXP (vals, 0, one_var),
24342 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
24346 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
24350 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
24352 enum machine_mode mode = GET_MODE (target);
24353 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24354 bool use_vec_merge = false;
24363 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
24364 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
24366 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
24368 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
24369 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24375 use_vec_merge = TARGET_SSE4_1;
24383 /* For the two element vectors, we implement a VEC_CONCAT with
24384 the extraction of the other element. */
24386 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
24387 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
24390 op0 = val, op1 = tmp;
24392 op0 = tmp, op1 = val;
24394 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
24395 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24400 use_vec_merge = TARGET_SSE4_1;
24407 use_vec_merge = true;
24411 /* tmp = target = A B C D */
24412 tmp = copy_to_reg (target);
24413 /* target = A A B B */
24414 emit_insn (gen_sse_unpcklps (target, target, target));
24415 /* target = X A B B */
24416 ix86_expand_vector_set (false, target, val, 0);
24417 /* target = A X C D */
24418 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24419 GEN_INT (1), GEN_INT (0),
24420 GEN_INT (2+4), GEN_INT (3+4)));
24424 /* tmp = target = A B C D */
24425 tmp = copy_to_reg (target);
24426 /* tmp = X B C D */
24427 ix86_expand_vector_set (false, tmp, val, 0);
24428 /* target = A B X D */
24429 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24430 GEN_INT (0), GEN_INT (1),
24431 GEN_INT (0+4), GEN_INT (3+4)));
24435 /* tmp = target = A B C D */
24436 tmp = copy_to_reg (target);
24437 /* tmp = X B C D */
24438 ix86_expand_vector_set (false, tmp, val, 0);
24439 /* target = A B X D */
24440 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24441 GEN_INT (0), GEN_INT (1),
24442 GEN_INT (2+4), GEN_INT (0+4)));
24446 gcc_unreachable ();
24451 use_vec_merge = TARGET_SSE4_1;
24455 /* Element 0 handled by vec_merge below. */
24458 use_vec_merge = true;
24464 /* With SSE2, use integer shuffles to swap element 0 and ELT,
24465 store into element 0, then shuffle them back. */
24469 order[0] = GEN_INT (elt);
24470 order[1] = const1_rtx;
24471 order[2] = const2_rtx;
24472 order[3] = GEN_INT (3);
24473 order[elt] = const0_rtx;
24475 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24476 order[1], order[2], order[3]));
24478 ix86_expand_vector_set (false, target, val, 0);
24480 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24481 order[1], order[2], order[3]));
24485 /* For SSE1, we have to reuse the V4SF code. */
24486 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
24487 gen_lowpart (SFmode, val), elt);
24492 use_vec_merge = TARGET_SSE2;
24495 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24499 use_vec_merge = TARGET_SSE4_1;
24509 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
24510 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
24511 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24515 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24517 emit_move_insn (mem, target);
24519 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24520 emit_move_insn (tmp, val);
24522 emit_move_insn (target, mem);
24527 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
24529 enum machine_mode mode = GET_MODE (vec);
24530 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24531 bool use_vec_extr = false;
24544 use_vec_extr = true;
24548 use_vec_extr = TARGET_SSE4_1;
24560 tmp = gen_reg_rtx (mode);
24561 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
24562 GEN_INT (elt), GEN_INT (elt),
24563 GEN_INT (elt+4), GEN_INT (elt+4)));
24567 tmp = gen_reg_rtx (mode);
24568 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
24572 gcc_unreachable ();
24575 use_vec_extr = true;
24580 use_vec_extr = TARGET_SSE4_1;
24594 tmp = gen_reg_rtx (mode);
24595 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
24596 GEN_INT (elt), GEN_INT (elt),
24597 GEN_INT (elt), GEN_INT (elt)));
24601 tmp = gen_reg_rtx (mode);
24602 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
24606 gcc_unreachable ();
24609 use_vec_extr = true;
24614 /* For SSE1, we have to reuse the V4SF code. */
24615 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24616 gen_lowpart (V4SFmode, vec), elt);
24622 use_vec_extr = TARGET_SSE2;
24625 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24629 use_vec_extr = TARGET_SSE4_1;
24633 /* ??? Could extract the appropriate HImode element and shift. */
24640 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24641 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24643 /* Let the rtl optimizers know about the zero extension performed. */
24644 if (inner_mode == QImode || inner_mode == HImode)
24646 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24647 target = gen_lowpart (SImode, target);
24650 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24654 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24656 emit_move_insn (mem, vec);
24658 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24659 emit_move_insn (target, tmp);
24663 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24664 pattern to reduce; DEST is the destination; IN is the input vector. */
24667 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24669 rtx tmp1, tmp2, tmp3;
24671 tmp1 = gen_reg_rtx (V4SFmode);
24672 tmp2 = gen_reg_rtx (V4SFmode);
24673 tmp3 = gen_reg_rtx (V4SFmode);
24675 emit_insn (gen_sse_movhlps (tmp1, in, in));
24676 emit_insn (fn (tmp2, tmp1, in));
24678 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24679 GEN_INT (1), GEN_INT (1),
24680 GEN_INT (1+4), GEN_INT (1+4)));
24681 emit_insn (fn (dest, tmp2, tmp3));
24684 /* Target hook for scalar_mode_supported_p. */
24686 ix86_scalar_mode_supported_p (enum machine_mode mode)
24688 if (DECIMAL_FLOAT_MODE_P (mode))
24690 else if (mode == TFmode)
24691 return TARGET_64BIT;
24693 return default_scalar_mode_supported_p (mode);
24696 /* Implements target hook vector_mode_supported_p. */
24698 ix86_vector_mode_supported_p (enum machine_mode mode)
24700 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24702 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24704 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24706 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24711 /* Target hook for c_mode_for_suffix. */
24712 static enum machine_mode
24713 ix86_c_mode_for_suffix (char suffix)
24715 if (TARGET_64BIT && suffix == 'q')
24717 if (TARGET_MMX && suffix == 'w')
24723 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24725 We do this in the new i386 backend to maintain source compatibility
24726 with the old cc0-based compiler. */
24729 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24730 tree inputs ATTRIBUTE_UNUSED,
24733 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24735 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24740 /* Implements target vector targetm.asm.encode_section_info. This
24741 is not used by netware. */
24743 static void ATTRIBUTE_UNUSED
24744 ix86_encode_section_info (tree decl, rtx rtl, int first)
24746 default_encode_section_info (decl, rtl, first);
24748 if (TREE_CODE (decl) == VAR_DECL
24749 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24750 && ix86_in_large_data_p (decl))
24751 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24754 /* Worker function for REVERSE_CONDITION. */
24757 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24759 return (mode != CCFPmode && mode != CCFPUmode
24760 ? reverse_condition (code)
24761 : reverse_condition_maybe_unordered (code));
24764 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24768 output_387_reg_move (rtx insn, rtx *operands)
24770 if (REG_P (operands[0]))
24772 if (REG_P (operands[1])
24773 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24775 if (REGNO (operands[0]) == FIRST_STACK_REG)
24776 return output_387_ffreep (operands, 0);
24777 return "fstp\t%y0";
24779 if (STACK_TOP_P (operands[0]))
24780 return "fld%z1\t%y1";
24783 else if (MEM_P (operands[0]))
24785 gcc_assert (REG_P (operands[1]));
24786 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24787 return "fstp%z0\t%y0";
24790 /* There is no non-popping store to memory for XFmode.
24791 So if we need one, follow the store with a load. */
24792 if (GET_MODE (operands[0]) == XFmode)
24793 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24795 return "fst%z0\t%y0";
24802 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24803 FP status register is set. */
24806 ix86_emit_fp_unordered_jump (rtx label)
24808 rtx reg = gen_reg_rtx (HImode);
24811 emit_insn (gen_x86_fnstsw_1 (reg));
24813 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24815 emit_insn (gen_x86_sahf_1 (reg));
24817 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24818 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24822 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24824 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24825 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24828 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24829 gen_rtx_LABEL_REF (VOIDmode, label),
24831 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24833 emit_jump_insn (temp);
24834 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24837 /* Output code to perform a log1p XFmode calculation. */
24839 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24841 rtx label1 = gen_label_rtx ();
24842 rtx label2 = gen_label_rtx ();
24844 rtx tmp = gen_reg_rtx (XFmode);
24845 rtx tmp2 = gen_reg_rtx (XFmode);
24847 emit_insn (gen_absxf2 (tmp, op1));
24848 emit_insn (gen_cmpxf (tmp,
24849 CONST_DOUBLE_FROM_REAL_VALUE (
24850 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24852 emit_jump_insn (gen_bge (label1));
24854 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24855 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24856 emit_jump (label2);
24858 emit_label (label1);
24859 emit_move_insn (tmp, CONST1_RTX (XFmode));
24860 emit_insn (gen_addxf3 (tmp, op1, tmp));
24861 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24862 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24864 emit_label (label2);
24867 /* Output code to perform a Newton-Rhapson approximation of a single precision
24868 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24870 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24872 rtx x0, x1, e0, e1, two;
24874 x0 = gen_reg_rtx (mode);
24875 e0 = gen_reg_rtx (mode);
24876 e1 = gen_reg_rtx (mode);
24877 x1 = gen_reg_rtx (mode);
24879 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24881 if (VECTOR_MODE_P (mode))
24882 two = ix86_build_const_vector (SFmode, true, two);
24884 two = force_reg (mode, two);
24886 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24888 /* x0 = rcp(b) estimate */
24889 emit_insn (gen_rtx_SET (VOIDmode, x0,
24890 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24893 emit_insn (gen_rtx_SET (VOIDmode, e0,
24894 gen_rtx_MULT (mode, x0, b)));
24896 emit_insn (gen_rtx_SET (VOIDmode, e1,
24897 gen_rtx_MINUS (mode, two, e0)));
24899 emit_insn (gen_rtx_SET (VOIDmode, x1,
24900 gen_rtx_MULT (mode, x0, e1)));
24902 emit_insn (gen_rtx_SET (VOIDmode, res,
24903 gen_rtx_MULT (mode, a, x1)));
24906 /* Output code to perform a Newton-Rhapson approximation of a
24907 single precision floating point [reciprocal] square root. */
24909 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24912 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24915 x0 = gen_reg_rtx (mode);
24916 e0 = gen_reg_rtx (mode);
24917 e1 = gen_reg_rtx (mode);
24918 e2 = gen_reg_rtx (mode);
24919 e3 = gen_reg_rtx (mode);
24921 real_from_integer (&r, VOIDmode, -3, -1, 0);
24922 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24924 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24925 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24927 if (VECTOR_MODE_P (mode))
24929 mthree = ix86_build_const_vector (SFmode, true, mthree);
24930 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24933 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24934 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24936 /* x0 = rsqrt(a) estimate */
24937 emit_insn (gen_rtx_SET (VOIDmode, x0,
24938 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24941 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24946 zero = gen_reg_rtx (mode);
24947 mask = gen_reg_rtx (mode);
24949 zero = force_reg (mode, CONST0_RTX(mode));
24950 emit_insn (gen_rtx_SET (VOIDmode, mask,
24951 gen_rtx_NE (mode, zero, a)));
24953 emit_insn (gen_rtx_SET (VOIDmode, x0,
24954 gen_rtx_AND (mode, x0, mask)));
24958 emit_insn (gen_rtx_SET (VOIDmode, e0,
24959 gen_rtx_MULT (mode, x0, a)));
24961 emit_insn (gen_rtx_SET (VOIDmode, e1,
24962 gen_rtx_MULT (mode, e0, x0)));
24965 mthree = force_reg (mode, mthree);
24966 emit_insn (gen_rtx_SET (VOIDmode, e2,
24967 gen_rtx_PLUS (mode, e1, mthree)));
24969 mhalf = force_reg (mode, mhalf);
24971 /* e3 = -.5 * x0 */
24972 emit_insn (gen_rtx_SET (VOIDmode, e3,
24973 gen_rtx_MULT (mode, x0, mhalf)));
24975 /* e3 = -.5 * e0 */
24976 emit_insn (gen_rtx_SET (VOIDmode, e3,
24977 gen_rtx_MULT (mode, e0, mhalf)));
24978 /* ret = e2 * e3 */
24979 emit_insn (gen_rtx_SET (VOIDmode, res,
24980 gen_rtx_MULT (mode, e2, e3)));
24983 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24985 static void ATTRIBUTE_UNUSED
24986 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24989 /* With Binutils 2.15, the "@unwind" marker must be specified on
24990 every occurrence of the ".eh_frame" section, not just the first
24993 && strcmp (name, ".eh_frame") == 0)
24995 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24996 flags & SECTION_WRITE ? "aw" : "a");
24999 default_elf_asm_named_section (name, flags, decl);
25002 /* Return the mangling of TYPE if it is an extended fundamental type. */
25004 static const char *
25005 ix86_mangle_type (const_tree type)
25007 type = TYPE_MAIN_VARIANT (type);
25009 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
25010 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
25013 switch (TYPE_MODE (type))
25016 /* __float128 is "g". */
25019 /* "long double" or __float80 is "e". */
25026 /* For 32-bit code we can save PIC register setup by using
25027 __stack_chk_fail_local hidden function instead of calling
25028 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
25029 register, so it is better to call __stack_chk_fail directly. */
25032 ix86_stack_protect_fail (void)
25034 return TARGET_64BIT
25035 ? default_external_stack_protect_fail ()
25036 : default_hidden_stack_protect_fail ();
25039 /* Select a format to encode pointers in exception handling data. CODE
25040 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
25041 true if the symbol may be affected by dynamic relocations.
25043 ??? All x86 object file formats are capable of representing this.
25044 After all, the relocation needed is the same as for the call insn.
25045 Whether or not a particular assembler allows us to enter such, I
25046 guess we'll have to see. */
25048 asm_preferred_eh_data_format (int code, int global)
25052 int type = DW_EH_PE_sdata8;
25054 || ix86_cmodel == CM_SMALL_PIC
25055 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
25056 type = DW_EH_PE_sdata4;
25057 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
25059 if (ix86_cmodel == CM_SMALL
25060 || (ix86_cmodel == CM_MEDIUM && code))
25061 return DW_EH_PE_udata4;
25062 return DW_EH_PE_absptr;
25065 /* Expand copysign from SIGN to the positive value ABS_VALUE
25066 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
25069 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
25071 enum machine_mode mode = GET_MODE (sign);
25072 rtx sgn = gen_reg_rtx (mode);
25073 if (mask == NULL_RTX)
25075 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
25076 if (!VECTOR_MODE_P (mode))
25078 /* We need to generate a scalar mode mask in this case. */
25079 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
25080 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
25081 mask = gen_reg_rtx (mode);
25082 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
25086 mask = gen_rtx_NOT (mode, mask);
25087 emit_insn (gen_rtx_SET (VOIDmode, sgn,
25088 gen_rtx_AND (mode, mask, sign)));
25089 emit_insn (gen_rtx_SET (VOIDmode, result,
25090 gen_rtx_IOR (mode, abs_value, sgn)));
25093 /* Expand fabs (OP0) and return a new rtx that holds the result. The
25094 mask for masking out the sign-bit is stored in *SMASK, if that is
25097 ix86_expand_sse_fabs (rtx op0, rtx *smask)
25099 enum machine_mode mode = GET_MODE (op0);
25102 xa = gen_reg_rtx (mode);
25103 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
25104 if (!VECTOR_MODE_P (mode))
25106 /* We need to generate a scalar mode mask in this case. */
25107 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
25108 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
25109 mask = gen_reg_rtx (mode);
25110 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
25112 emit_insn (gen_rtx_SET (VOIDmode, xa,
25113 gen_rtx_AND (mode, op0, mask)));
25121 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
25122 swapping the operands if SWAP_OPERANDS is true. The expanded
25123 code is a forward jump to a newly created label in case the
25124 comparison is true. The generated label rtx is returned. */
25126 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
25127 bool swap_operands)
25138 label = gen_label_rtx ();
25139 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
25140 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25141 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
25142 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
25143 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
25144 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
25145 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
25146 JUMP_LABEL (tmp) = label;
25151 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
25152 using comparison code CODE. Operands are swapped for the comparison if
25153 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
25155 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
25156 bool swap_operands)
25158 enum machine_mode mode = GET_MODE (op0);
25159 rtx mask = gen_reg_rtx (mode);
25168 if (mode == DFmode)
25169 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
25170 gen_rtx_fmt_ee (code, mode, op0, op1)));
25172 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
25173 gen_rtx_fmt_ee (code, mode, op0, op1)));
25178 /* Generate and return a rtx of mode MODE for 2**n where n is the number
25179 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
25181 ix86_gen_TWO52 (enum machine_mode mode)
25183 REAL_VALUE_TYPE TWO52r;
25186 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
25187 TWO52 = const_double_from_real_value (TWO52r, mode);
25188 TWO52 = force_reg (mode, TWO52);
25193 /* Expand SSE sequence for computing lround from OP1 storing
25196 ix86_expand_lround (rtx op0, rtx op1)
25198 /* C code for the stuff we're doing below:
25199 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
25202 enum machine_mode mode = GET_MODE (op1);
25203 const struct real_format *fmt;
25204 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25207 /* load nextafter (0.5, 0.0) */
25208 fmt = REAL_MODE_FORMAT (mode);
25209 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25210 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25212 /* adj = copysign (0.5, op1) */
25213 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
25214 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
25216 /* adj = op1 + adj */
25217 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
25219 /* op0 = (imode)adj */
25220 expand_fix (op0, adj, 0);
25223 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
25226 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
25228 /* C code for the stuff we're doing below (for do_floor):
25230 xi -= (double)xi > op1 ? 1 : 0;
25233 enum machine_mode fmode = GET_MODE (op1);
25234 enum machine_mode imode = GET_MODE (op0);
25235 rtx ireg, freg, label, tmp;
25237 /* reg = (long)op1 */
25238 ireg = gen_reg_rtx (imode);
25239 expand_fix (ireg, op1, 0);
25241 /* freg = (double)reg */
25242 freg = gen_reg_rtx (fmode);
25243 expand_float (freg, ireg, 0);
25245 /* ireg = (freg > op1) ? ireg - 1 : ireg */
25246 label = ix86_expand_sse_compare_and_jump (UNLE,
25247 freg, op1, !do_floor);
25248 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
25249 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
25250 emit_move_insn (ireg, tmp);
25252 emit_label (label);
25253 LABEL_NUSES (label) = 1;
25255 emit_move_insn (op0, ireg);
25258 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
25259 result in OPERAND0. */
25261 ix86_expand_rint (rtx operand0, rtx operand1)
25263 /* C code for the stuff we're doing below:
25264 xa = fabs (operand1);
25265 if (!isless (xa, 2**52))
25267 xa = xa + 2**52 - 2**52;
25268 return copysign (xa, operand1);
25270 enum machine_mode mode = GET_MODE (operand0);
25271 rtx res, xa, label, TWO52, mask;
25273 res = gen_reg_rtx (mode);
25274 emit_move_insn (res, operand1);
25276 /* xa = abs (operand1) */
25277 xa = ix86_expand_sse_fabs (res, &mask);
25279 /* if (!isless (xa, TWO52)) goto label; */
25280 TWO52 = ix86_gen_TWO52 (mode);
25281 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25283 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25284 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25286 ix86_sse_copysign_to_positive (res, xa, res, mask);
25288 emit_label (label);
25289 LABEL_NUSES (label) = 1;
25291 emit_move_insn (operand0, res);
25294 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25297 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
25299 /* C code for the stuff we expand below.
25300 double xa = fabs (x), x2;
25301 if (!isless (xa, TWO52))
25303 xa = xa + TWO52 - TWO52;
25304 x2 = copysign (xa, x);
25313 enum machine_mode mode = GET_MODE (operand0);
25314 rtx xa, TWO52, tmp, label, one, res, mask;
25316 TWO52 = ix86_gen_TWO52 (mode);
25318 /* Temporary for holding the result, initialized to the input
25319 operand to ease control flow. */
25320 res = gen_reg_rtx (mode);
25321 emit_move_insn (res, operand1);
25323 /* xa = abs (operand1) */
25324 xa = ix86_expand_sse_fabs (res, &mask);
25326 /* if (!isless (xa, TWO52)) goto label; */
25327 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25329 /* xa = xa + TWO52 - TWO52; */
25330 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25331 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25333 /* xa = copysign (xa, operand1) */
25334 ix86_sse_copysign_to_positive (xa, xa, res, mask);
25336 /* generate 1.0 or -1.0 */
25337 one = force_reg (mode,
25338 const_double_from_real_value (do_floor
25339 ? dconst1 : dconstm1, mode));
25341 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25342 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25343 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25344 gen_rtx_AND (mode, one, tmp)));
25345 /* We always need to subtract here to preserve signed zero. */
25346 tmp = expand_simple_binop (mode, MINUS,
25347 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25348 emit_move_insn (res, tmp);
25350 emit_label (label);
25351 LABEL_NUSES (label) = 1;
25353 emit_move_insn (operand0, res);
25356 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25359 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
25361 /* C code for the stuff we expand below.
25362 double xa = fabs (x), x2;
25363 if (!isless (xa, TWO52))
25365 x2 = (double)(long)x;
25372 if (HONOR_SIGNED_ZEROS (mode))
25373 return copysign (x2, x);
25376 enum machine_mode mode = GET_MODE (operand0);
25377 rtx xa, xi, TWO52, tmp, label, one, res, mask;
25379 TWO52 = ix86_gen_TWO52 (mode);
25381 /* Temporary for holding the result, initialized to the input
25382 operand to ease control flow. */
25383 res = gen_reg_rtx (mode);
25384 emit_move_insn (res, operand1);
25386 /* xa = abs (operand1) */
25387 xa = ix86_expand_sse_fabs (res, &mask);
25389 /* if (!isless (xa, TWO52)) goto label; */
25390 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25392 /* xa = (double)(long)x */
25393 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25394 expand_fix (xi, res, 0);
25395 expand_float (xa, xi, 0);
25398 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25400 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25401 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25402 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25403 gen_rtx_AND (mode, one, tmp)));
25404 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
25405 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25406 emit_move_insn (res, tmp);
25408 if (HONOR_SIGNED_ZEROS (mode))
25409 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25411 emit_label (label);
25412 LABEL_NUSES (label) = 1;
25414 emit_move_insn (operand0, res);
25417 /* Expand SSE sequence for computing round from OPERAND1 storing
25418 into OPERAND0. Sequence that works without relying on DImode truncation
25419 via cvttsd2siq that is only available on 64bit targets. */
25421 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
25423 /* C code for the stuff we expand below.
25424 double xa = fabs (x), xa2, x2;
25425 if (!isless (xa, TWO52))
25427 Using the absolute value and copying back sign makes
25428 -0.0 -> -0.0 correct.
25429 xa2 = xa + TWO52 - TWO52;
25434 else if (dxa > 0.5)
25436 x2 = copysign (xa2, x);
25439 enum machine_mode mode = GET_MODE (operand0);
25440 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
25442 TWO52 = ix86_gen_TWO52 (mode);
25444 /* Temporary for holding the result, initialized to the input
25445 operand to ease control flow. */
25446 res = gen_reg_rtx (mode);
25447 emit_move_insn (res, operand1);
25449 /* xa = abs (operand1) */
25450 xa = ix86_expand_sse_fabs (res, &mask);
25452 /* if (!isless (xa, TWO52)) goto label; */
25453 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25455 /* xa2 = xa + TWO52 - TWO52; */
25456 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25457 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
25459 /* dxa = xa2 - xa; */
25460 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
25462 /* generate 0.5, 1.0 and -0.5 */
25463 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
25464 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
25465 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
25469 tmp = gen_reg_rtx (mode);
25470 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
25471 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
25472 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25473 gen_rtx_AND (mode, one, tmp)));
25474 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25475 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
25476 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
25477 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25478 gen_rtx_AND (mode, one, tmp)));
25479 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25481 /* res = copysign (xa2, operand1) */
25482 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
25484 emit_label (label);
25485 LABEL_NUSES (label) = 1;
25487 emit_move_insn (operand0, res);
25490 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25493 ix86_expand_trunc (rtx operand0, rtx operand1)
25495 /* C code for SSE variant we expand below.
25496 double xa = fabs (x), x2;
25497 if (!isless (xa, TWO52))
25499 x2 = (double)(long)x;
25500 if (HONOR_SIGNED_ZEROS (mode))
25501 return copysign (x2, x);
25504 enum machine_mode mode = GET_MODE (operand0);
25505 rtx xa, xi, TWO52, label, res, mask;
25507 TWO52 = ix86_gen_TWO52 (mode);
25509 /* Temporary for holding the result, initialized to the input
25510 operand to ease control flow. */
25511 res = gen_reg_rtx (mode);
25512 emit_move_insn (res, operand1);
25514 /* xa = abs (operand1) */
25515 xa = ix86_expand_sse_fabs (res, &mask);
25517 /* if (!isless (xa, TWO52)) goto label; */
25518 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25520 /* x = (double)(long)x */
25521 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25522 expand_fix (xi, res, 0);
25523 expand_float (res, xi, 0);
25525 if (HONOR_SIGNED_ZEROS (mode))
25526 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25528 emit_label (label);
25529 LABEL_NUSES (label) = 1;
25531 emit_move_insn (operand0, res);
25534 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25537 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
25539 enum machine_mode mode = GET_MODE (operand0);
25540 rtx xa, mask, TWO52, label, one, res, smask, tmp;
25542 /* C code for SSE variant we expand below.
25543 double xa = fabs (x), x2;
25544 if (!isless (xa, TWO52))
25546 xa2 = xa + TWO52 - TWO52;
25550 x2 = copysign (xa2, x);
25554 TWO52 = ix86_gen_TWO52 (mode);
25556 /* Temporary for holding the result, initialized to the input
25557 operand to ease control flow. */
25558 res = gen_reg_rtx (mode);
25559 emit_move_insn (res, operand1);
25561 /* xa = abs (operand1) */
25562 xa = ix86_expand_sse_fabs (res, &smask);
25564 /* if (!isless (xa, TWO52)) goto label; */
25565 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25567 /* res = xa + TWO52 - TWO52; */
25568 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25569 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
25570 emit_move_insn (res, tmp);
25573 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25575 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
25576 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
25577 emit_insn (gen_rtx_SET (VOIDmode, mask,
25578 gen_rtx_AND (mode, mask, one)));
25579 tmp = expand_simple_binop (mode, MINUS,
25580 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
25581 emit_move_insn (res, tmp);
25583 /* res = copysign (res, operand1) */
25584 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
25586 emit_label (label);
25587 LABEL_NUSES (label) = 1;
25589 emit_move_insn (operand0, res);
25592 /* Expand SSE sequence for computing round from OPERAND1 storing
25595 ix86_expand_round (rtx operand0, rtx operand1)
25597 /* C code for the stuff we're doing below:
25598 double xa = fabs (x);
25599 if (!isless (xa, TWO52))
25601 xa = (double)(long)(xa + nextafter (0.5, 0.0));
25602 return copysign (xa, x);
25604 enum machine_mode mode = GET_MODE (operand0);
25605 rtx res, TWO52, xa, label, xi, half, mask;
25606 const struct real_format *fmt;
25607 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25609 /* Temporary for holding the result, initialized to the input
25610 operand to ease control flow. */
25611 res = gen_reg_rtx (mode);
25612 emit_move_insn (res, operand1);
25614 TWO52 = ix86_gen_TWO52 (mode);
25615 xa = ix86_expand_sse_fabs (res, &mask);
25616 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25618 /* load nextafter (0.5, 0.0) */
25619 fmt = REAL_MODE_FORMAT (mode);
25620 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25621 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25623 /* xa = xa + 0.5 */
25624 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25625 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25627 /* xa = (double)(int64_t)xa */
25628 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25629 expand_fix (xi, xa, 0);
25630 expand_float (xa, xi, 0);
25632 /* res = copysign (xa, operand1) */
25633 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25635 emit_label (label);
25636 LABEL_NUSES (label) = 1;
25638 emit_move_insn (operand0, res);
25642 /* Validate whether a SSE5 instruction is valid or not.
25643 OPERANDS is the array of operands.
25644 NUM is the number of operands.
25645 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25646 NUM_MEMORY is the maximum number of memory operands to accept. */
25649 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
25650 bool uses_oc0, int num_memory)
25656 /* Count the number of memory arguments */
25659 for (i = 0; i < num; i++)
25661 enum machine_mode mode = GET_MODE (operands[i]);
25662 if (register_operand (operands[i], mode))
25665 else if (memory_operand (operands[i], mode))
25667 mem_mask |= (1 << i);
25673 rtx pattern = PATTERN (insn);
25675 /* allow 0 for pcmov */
25676 if (GET_CODE (pattern) != SET
25677 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25679 || operands[i] != CONST0_RTX (mode))
25684 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
25685 a memory operation. */
25686 if (num_memory < 0)
25688 num_memory = -num_memory;
25689 if ((mem_mask & (1 << (num-1))) != 0)
25691 mem_mask &= ~(1 << (num-1));
25696 /* If there were no memory operations, allow the insn */
25700 /* Do not allow the destination register to be a memory operand. */
25701 else if (mem_mask & (1 << 0))
25704 /* If there are too many memory operations, disallow the instruction. While
25705 the hardware only allows 1 memory reference, before register allocation
25706 for some insns, we allow two memory operations sometimes in order to allow
25707 code like the following to be optimized:
25709 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25711 or similar cases that are vectorized into using the fmaddss
25713 else if (mem_count > num_memory)
25716 /* Don't allow more than one memory operation if not optimizing. */
25717 else if (mem_count > 1 && !optimize)
25720 else if (num == 4 && mem_count == 1)
25722 /* formats (destination is the first argument), example fmaddss:
25723 xmm1, xmm1, xmm2, xmm3/mem
25724 xmm1, xmm1, xmm2/mem, xmm3
25725 xmm1, xmm2, xmm3/mem, xmm1
25726 xmm1, xmm2/mem, xmm3, xmm1 */
25728 return ((mem_mask == (1 << 1))
25729 || (mem_mask == (1 << 2))
25730 || (mem_mask == (1 << 3)));
25732 /* format, example pmacsdd:
25733 xmm1, xmm2, xmm3/mem, xmm1 */
25735 return (mem_mask == (1 << 2));
25738 else if (num == 4 && num_memory == 2)
25740 /* If there are two memory operations, we can load one of the memory ops
25741 into the destination register. This is for optimizing the
25742 multiply/add ops, which the combiner has optimized both the multiply
25743 and the add insns to have a memory operation. We have to be careful
25744 that the destination doesn't overlap with the inputs. */
25745 rtx op0 = operands[0];
25747 if (reg_mentioned_p (op0, operands[1])
25748 || reg_mentioned_p (op0, operands[2])
25749 || reg_mentioned_p (op0, operands[3]))
25752 /* formats (destination is the first argument), example fmaddss:
25753 xmm1, xmm1, xmm2, xmm3/mem
25754 xmm1, xmm1, xmm2/mem, xmm3
25755 xmm1, xmm2, xmm3/mem, xmm1
25756 xmm1, xmm2/mem, xmm3, xmm1
25758 For the oc0 case, we will load either operands[1] or operands[3] into
25759 operands[0], so any combination of 2 memory operands is ok. */
25763 /* format, example pmacsdd:
25764 xmm1, xmm2, xmm3/mem, xmm1
25766 For the integer multiply/add instructions be more restrictive and
25767 require operands[2] and operands[3] to be the memory operands. */
25769 return (mem_mask == ((1 << 2) | (1 << 3)));
25772 else if (num == 3 && num_memory == 1)
25774 /* formats, example protb:
25775 xmm1, xmm2, xmm3/mem
25776 xmm1, xmm2/mem, xmm3 */
25778 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25780 /* format, example comeq:
25781 xmm1, xmm2, xmm3/mem */
25783 return (mem_mask == (1 << 2));
25787 gcc_unreachable ();
25793 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25794 hardware will allow by using the destination register to load one of the
25795 memory operations. Presently this is used by the multiply/add routines to
25796 allow 2 memory references. */
25799 ix86_expand_sse5_multiple_memory (rtx operands[],
25801 enum machine_mode mode)
25803 rtx op0 = operands[0];
25805 || memory_operand (op0, mode)
25806 || reg_mentioned_p (op0, operands[1])
25807 || reg_mentioned_p (op0, operands[2])
25808 || reg_mentioned_p (op0, operands[3]))
25809 gcc_unreachable ();
25811 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25812 the destination register. */
25813 if (memory_operand (operands[1], mode))
25815 emit_move_insn (op0, operands[1]);
25818 else if (memory_operand (operands[3], mode))
25820 emit_move_insn (op0, operands[3]);
25824 gcc_unreachable ();
25830 /* Table of valid machine attributes. */
25831 static const struct attribute_spec ix86_attribute_table[] =
25833 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25834 /* Stdcall attribute says callee is responsible for popping arguments
25835 if they are not variable. */
25836 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25837 /* Fastcall attribute says callee is responsible for popping arguments
25838 if they are not variable. */
25839 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25840 /* Cdecl attribute says the callee is a normal C declaration */
25841 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25842 /* Regparm attribute specifies how many integer arguments are to be
25843 passed in registers. */
25844 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25845 /* Sseregparm attribute says we are using x86_64 calling conventions
25846 for FP arguments. */
25847 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25848 /* force_align_arg_pointer says this function realigns the stack at entry. */
25849 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25850 false, true, true, ix86_handle_cconv_attribute },
25851 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25852 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25853 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25854 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25856 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25857 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25858 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25859 SUBTARGET_ATTRIBUTE_TABLE,
25861 { NULL, 0, 0, false, false, false, NULL }
25864 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25866 x86_builtin_vectorization_cost (bool runtime_test)
25868 /* If the branch of the runtime test is taken - i.e. - the vectorized
25869 version is skipped - this incurs a misprediction cost (because the
25870 vectorized version is expected to be the fall-through). So we subtract
25871 the latency of a mispredicted branch from the costs that are incured
25872 when the vectorized version is executed.
25874 TODO: The values in individual target tables have to be tuned or new
25875 fields may be needed. For eg. on K8, the default branch path is the
25876 not-taken path. If the taken path is predicted correctly, the minimum
25877 penalty of going down the taken-path is 1 cycle. If the taken-path is
25878 not predicted correctly, then the minimum penalty is 10 cycles. */
25882 return (-(ix86_cost->cond_taken_branch_cost));
25888 /* Initialize the GCC target structure. */
25889 #undef TARGET_RETURN_IN_MEMORY
25890 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
25892 #undef TARGET_ATTRIBUTE_TABLE
25893 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25894 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25895 # undef TARGET_MERGE_DECL_ATTRIBUTES
25896 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25899 #undef TARGET_COMP_TYPE_ATTRIBUTES
25900 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25902 #undef TARGET_INIT_BUILTINS
25903 #define TARGET_INIT_BUILTINS ix86_init_builtins
25904 #undef TARGET_EXPAND_BUILTIN
25905 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25907 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25908 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25909 ix86_builtin_vectorized_function
25911 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25912 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25914 #undef TARGET_BUILTIN_RECIPROCAL
25915 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25917 #undef TARGET_ASM_FUNCTION_EPILOGUE
25918 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25920 #undef TARGET_ENCODE_SECTION_INFO
25921 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25922 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25924 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25927 #undef TARGET_ASM_OPEN_PAREN
25928 #define TARGET_ASM_OPEN_PAREN ""
25929 #undef TARGET_ASM_CLOSE_PAREN
25930 #define TARGET_ASM_CLOSE_PAREN ""
25932 #undef TARGET_ASM_ALIGNED_HI_OP
25933 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25934 #undef TARGET_ASM_ALIGNED_SI_OP
25935 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25937 #undef TARGET_ASM_ALIGNED_DI_OP
25938 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25941 #undef TARGET_ASM_UNALIGNED_HI_OP
25942 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25943 #undef TARGET_ASM_UNALIGNED_SI_OP
25944 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25945 #undef TARGET_ASM_UNALIGNED_DI_OP
25946 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25948 #undef TARGET_SCHED_ADJUST_COST
25949 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25950 #undef TARGET_SCHED_ISSUE_RATE
25951 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25952 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25953 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25954 ia32_multipass_dfa_lookahead
25956 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25957 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25960 #undef TARGET_HAVE_TLS
25961 #define TARGET_HAVE_TLS true
25963 #undef TARGET_CANNOT_FORCE_CONST_MEM
25964 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25965 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25966 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25968 #undef TARGET_DELEGITIMIZE_ADDRESS
25969 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25971 #undef TARGET_MS_BITFIELD_LAYOUT_P
25972 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25975 #undef TARGET_BINDS_LOCAL_P
25976 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25978 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25979 #undef TARGET_BINDS_LOCAL_P
25980 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25983 #undef TARGET_ASM_OUTPUT_MI_THUNK
25984 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25985 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25986 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25988 #undef TARGET_ASM_FILE_START
25989 #define TARGET_ASM_FILE_START x86_file_start
25991 #undef TARGET_DEFAULT_TARGET_FLAGS
25992 #define TARGET_DEFAULT_TARGET_FLAGS \
25994 | TARGET_SUBTARGET_DEFAULT \
25995 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25997 #undef TARGET_HANDLE_OPTION
25998 #define TARGET_HANDLE_OPTION ix86_handle_option
26000 #undef TARGET_RTX_COSTS
26001 #define TARGET_RTX_COSTS ix86_rtx_costs
26002 #undef TARGET_ADDRESS_COST
26003 #define TARGET_ADDRESS_COST ix86_address_cost
26005 #undef TARGET_FIXED_CONDITION_CODE_REGS
26006 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
26007 #undef TARGET_CC_MODES_COMPATIBLE
26008 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
26010 #undef TARGET_MACHINE_DEPENDENT_REORG
26011 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
26013 #undef TARGET_BUILD_BUILTIN_VA_LIST
26014 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
26016 #undef TARGET_EXPAND_BUILTIN_VA_START
26017 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
26019 #undef TARGET_MD_ASM_CLOBBERS
26020 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
26022 #undef TARGET_PROMOTE_PROTOTYPES
26023 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
26024 #undef TARGET_STRUCT_VALUE_RTX
26025 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
26026 #undef TARGET_SETUP_INCOMING_VARARGS
26027 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
26028 #undef TARGET_MUST_PASS_IN_STACK
26029 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
26030 #undef TARGET_PASS_BY_REFERENCE
26031 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
26032 #undef TARGET_INTERNAL_ARG_POINTER
26033 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
26034 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
26035 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
26036 #undef TARGET_STRICT_ARGUMENT_NAMING
26037 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
26039 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
26040 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
26042 #undef TARGET_SCALAR_MODE_SUPPORTED_P
26043 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
26045 #undef TARGET_VECTOR_MODE_SUPPORTED_P
26046 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
26048 #undef TARGET_C_MODE_FOR_SUFFIX
26049 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
26052 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
26053 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
26056 #ifdef SUBTARGET_INSERT_ATTRIBUTES
26057 #undef TARGET_INSERT_ATTRIBUTES
26058 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
26061 #undef TARGET_MANGLE_TYPE
26062 #define TARGET_MANGLE_TYPE ix86_mangle_type
26064 #undef TARGET_STACK_PROTECT_FAIL
26065 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
26067 #undef TARGET_FUNCTION_VALUE
26068 #define TARGET_FUNCTION_VALUE ix86_function_value
26070 #undef TARGET_SECONDARY_RELOAD
26071 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
26073 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
26074 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
26076 struct gcc_target targetm = TARGET_INITIALIZER;
26078 #include "gt-i386.h"
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