1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #ifndef CHECK_STACK_LIMIT
54 #define CHECK_STACK_LIMIT (-1)
57 /* Return index of given mode in mult and division cost tables. */
58 #define MODE_INDEX(mode) \
59 ((mode) == QImode ? 0 \
60 : (mode) == HImode ? 1 \
61 : (mode) == SImode ? 2 \
62 : (mode) == DImode ? 3 \
65 /* Processor costs (relative to an add) */
66 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
67 #define COSTS_N_BYTES(N) ((N) * 2)
70 struct processor_costs size_cost = { /* costs for tunning for size */
71 COSTS_N_BYTES (2), /* cost of an add instruction */
72 COSTS_N_BYTES (3), /* cost of a lea instruction */
73 COSTS_N_BYTES (2), /* variable shift costs */
74 COSTS_N_BYTES (3), /* constant shift costs */
75 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
76 COSTS_N_BYTES (3), /* HI */
77 COSTS_N_BYTES (3), /* SI */
78 COSTS_N_BYTES (3), /* DI */
79 COSTS_N_BYTES (5)}, /* other */
80 0, /* cost of multiply per each bit set */
81 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
82 COSTS_N_BYTES (3), /* HI */
83 COSTS_N_BYTES (3), /* SI */
84 COSTS_N_BYTES (3), /* DI */
85 COSTS_N_BYTES (5)}, /* other */
86 COSTS_N_BYTES (3), /* cost of movsx */
87 COSTS_N_BYTES (3), /* cost of movzx */
90 2, /* cost for loading QImode using movzbl */
91 {2, 2, 2}, /* cost of loading integer registers
92 in QImode, HImode and SImode.
93 Relative to reg-reg move (2). */
94 {2, 2, 2}, /* cost of storing integer registers */
95 2, /* cost of reg,reg fld/fst */
96 {2, 2, 2}, /* cost of loading fp registers
97 in SFmode, DFmode and XFmode */
98 {2, 2, 2}, /* cost of loading integer registers */
99 3, /* cost of moving MMX register */
100 {3, 3}, /* cost of loading MMX registers
101 in SImode and DImode */
102 {3, 3}, /* cost of storing MMX registers
103 in SImode and DImode */
104 3, /* cost of moving SSE register */
105 {3, 3, 3}, /* cost of loading SSE registers
106 in SImode, DImode and TImode */
107 {3, 3, 3}, /* cost of storing SSE registers
108 in SImode, DImode and TImode */
109 3, /* MMX or SSE register to integer */
110 0, /* size of prefetch block */
111 0, /* number of parallel prefetches */
113 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
114 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
115 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
116 COSTS_N_BYTES (2), /* cost of FABS instruction. */
117 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
118 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
121 /* Processor costs (relative to an add) */
123 struct processor_costs i386_cost = { /* 386 specific costs */
124 COSTS_N_INSNS (1), /* cost of an add instruction */
125 COSTS_N_INSNS (1), /* cost of a lea instruction */
126 COSTS_N_INSNS (3), /* variable shift costs */
127 COSTS_N_INSNS (2), /* constant shift costs */
128 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
129 COSTS_N_INSNS (6), /* HI */
130 COSTS_N_INSNS (6), /* SI */
131 COSTS_N_INSNS (6), /* DI */
132 COSTS_N_INSNS (6)}, /* other */
133 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
134 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
135 COSTS_N_INSNS (23), /* HI */
136 COSTS_N_INSNS (23), /* SI */
137 COSTS_N_INSNS (23), /* DI */
138 COSTS_N_INSNS (23)}, /* other */
139 COSTS_N_INSNS (3), /* cost of movsx */
140 COSTS_N_INSNS (2), /* cost of movzx */
141 15, /* "large" insn */
143 4, /* cost for loading QImode using movzbl */
144 {2, 4, 2}, /* cost of loading integer registers
145 in QImode, HImode and SImode.
146 Relative to reg-reg move (2). */
147 {2, 4, 2}, /* cost of storing integer registers */
148 2, /* cost of reg,reg fld/fst */
149 {8, 8, 8}, /* cost of loading fp registers
150 in SFmode, DFmode and XFmode */
151 {8, 8, 8}, /* cost of loading integer registers */
152 2, /* cost of moving MMX register */
153 {4, 8}, /* cost of loading MMX registers
154 in SImode and DImode */
155 {4, 8}, /* cost of storing MMX registers
156 in SImode and DImode */
157 2, /* cost of moving SSE register */
158 {4, 8, 16}, /* cost of loading SSE registers
159 in SImode, DImode and TImode */
160 {4, 8, 16}, /* cost of storing SSE registers
161 in SImode, DImode and TImode */
162 3, /* MMX or SSE register to integer */
163 0, /* size of prefetch block */
164 0, /* number of parallel prefetches */
166 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
167 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
168 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
169 COSTS_N_INSNS (22), /* cost of FABS instruction. */
170 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
171 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
175 struct processor_costs i486_cost = { /* 486 specific costs */
176 COSTS_N_INSNS (1), /* cost of an add instruction */
177 COSTS_N_INSNS (1), /* cost of a lea instruction */
178 COSTS_N_INSNS (3), /* variable shift costs */
179 COSTS_N_INSNS (2), /* constant shift costs */
180 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
181 COSTS_N_INSNS (12), /* HI */
182 COSTS_N_INSNS (12), /* SI */
183 COSTS_N_INSNS (12), /* DI */
184 COSTS_N_INSNS (12)}, /* other */
185 1, /* cost of multiply per each bit set */
186 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
187 COSTS_N_INSNS (40), /* HI */
188 COSTS_N_INSNS (40), /* SI */
189 COSTS_N_INSNS (40), /* DI */
190 COSTS_N_INSNS (40)}, /* other */
191 COSTS_N_INSNS (3), /* cost of movsx */
192 COSTS_N_INSNS (2), /* cost of movzx */
193 15, /* "large" insn */
195 4, /* cost for loading QImode using movzbl */
196 {2, 4, 2}, /* cost of loading integer registers
197 in QImode, HImode and SImode.
198 Relative to reg-reg move (2). */
199 {2, 4, 2}, /* cost of storing integer registers */
200 2, /* cost of reg,reg fld/fst */
201 {8, 8, 8}, /* cost of loading fp registers
202 in SFmode, DFmode and XFmode */
203 {8, 8, 8}, /* cost of loading integer registers */
204 2, /* cost of moving MMX register */
205 {4, 8}, /* cost of loading MMX registers
206 in SImode and DImode */
207 {4, 8}, /* cost of storing MMX registers
208 in SImode and DImode */
209 2, /* cost of moving SSE register */
210 {4, 8, 16}, /* cost of loading SSE registers
211 in SImode, DImode and TImode */
212 {4, 8, 16}, /* cost of storing SSE registers
213 in SImode, DImode and TImode */
214 3, /* MMX or SSE register to integer */
215 0, /* size of prefetch block */
216 0, /* number of parallel prefetches */
218 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
219 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
220 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
221 COSTS_N_INSNS (3), /* cost of FABS instruction. */
222 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
223 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
227 struct processor_costs pentium_cost = {
228 COSTS_N_INSNS (1), /* cost of an add instruction */
229 COSTS_N_INSNS (1), /* cost of a lea instruction */
230 COSTS_N_INSNS (4), /* variable shift costs */
231 COSTS_N_INSNS (1), /* constant shift costs */
232 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
233 COSTS_N_INSNS (11), /* HI */
234 COSTS_N_INSNS (11), /* SI */
235 COSTS_N_INSNS (11), /* DI */
236 COSTS_N_INSNS (11)}, /* other */
237 0, /* cost of multiply per each bit set */
238 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
239 COSTS_N_INSNS (25), /* HI */
240 COSTS_N_INSNS (25), /* SI */
241 COSTS_N_INSNS (25), /* DI */
242 COSTS_N_INSNS (25)}, /* other */
243 COSTS_N_INSNS (3), /* cost of movsx */
244 COSTS_N_INSNS (2), /* cost of movzx */
245 8, /* "large" insn */
247 6, /* cost for loading QImode using movzbl */
248 {2, 4, 2}, /* cost of loading integer registers
249 in QImode, HImode and SImode.
250 Relative to reg-reg move (2). */
251 {2, 4, 2}, /* cost of storing integer registers */
252 2, /* cost of reg,reg fld/fst */
253 {2, 2, 6}, /* cost of loading fp registers
254 in SFmode, DFmode and XFmode */
255 {4, 4, 6}, /* cost of loading integer registers */
256 8, /* cost of moving MMX register */
257 {8, 8}, /* cost of loading MMX registers
258 in SImode and DImode */
259 {8, 8}, /* cost of storing MMX registers
260 in SImode and DImode */
261 2, /* cost of moving SSE register */
262 {4, 8, 16}, /* cost of loading SSE registers
263 in SImode, DImode and TImode */
264 {4, 8, 16}, /* cost of storing SSE registers
265 in SImode, DImode and TImode */
266 3, /* MMX or SSE register to integer */
267 0, /* size of prefetch block */
268 0, /* number of parallel prefetches */
270 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
271 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
272 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
273 COSTS_N_INSNS (1), /* cost of FABS instruction. */
274 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
275 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
279 struct processor_costs pentiumpro_cost = {
280 COSTS_N_INSNS (1), /* cost of an add instruction */
281 COSTS_N_INSNS (1), /* cost of a lea instruction */
282 COSTS_N_INSNS (1), /* variable shift costs */
283 COSTS_N_INSNS (1), /* constant shift costs */
284 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
285 COSTS_N_INSNS (4), /* HI */
286 COSTS_N_INSNS (4), /* SI */
287 COSTS_N_INSNS (4), /* DI */
288 COSTS_N_INSNS (4)}, /* other */
289 0, /* cost of multiply per each bit set */
290 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
291 COSTS_N_INSNS (17), /* HI */
292 COSTS_N_INSNS (17), /* SI */
293 COSTS_N_INSNS (17), /* DI */
294 COSTS_N_INSNS (17)}, /* other */
295 COSTS_N_INSNS (1), /* cost of movsx */
296 COSTS_N_INSNS (1), /* cost of movzx */
297 8, /* "large" insn */
299 2, /* cost for loading QImode using movzbl */
300 {4, 4, 4}, /* cost of loading integer registers
301 in QImode, HImode and SImode.
302 Relative to reg-reg move (2). */
303 {2, 2, 2}, /* cost of storing integer registers */
304 2, /* cost of reg,reg fld/fst */
305 {2, 2, 6}, /* cost of loading fp registers
306 in SFmode, DFmode and XFmode */
307 {4, 4, 6}, /* cost of loading integer registers */
308 2, /* cost of moving MMX register */
309 {2, 2}, /* cost of loading MMX registers
310 in SImode and DImode */
311 {2, 2}, /* cost of storing MMX registers
312 in SImode and DImode */
313 2, /* cost of moving SSE register */
314 {2, 2, 8}, /* cost of loading SSE registers
315 in SImode, DImode and TImode */
316 {2, 2, 8}, /* cost of storing SSE registers
317 in SImode, DImode and TImode */
318 3, /* MMX or SSE register to integer */
319 32, /* size of prefetch block */
320 6, /* number of parallel prefetches */
322 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
323 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
324 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
325 COSTS_N_INSNS (2), /* cost of FABS instruction. */
326 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
327 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
331 struct processor_costs k6_cost = {
332 COSTS_N_INSNS (1), /* cost of an add instruction */
333 COSTS_N_INSNS (2), /* cost of a lea instruction */
334 COSTS_N_INSNS (1), /* variable shift costs */
335 COSTS_N_INSNS (1), /* constant shift costs */
336 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
337 COSTS_N_INSNS (3), /* HI */
338 COSTS_N_INSNS (3), /* SI */
339 COSTS_N_INSNS (3), /* DI */
340 COSTS_N_INSNS (3)}, /* other */
341 0, /* cost of multiply per each bit set */
342 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
343 COSTS_N_INSNS (18), /* HI */
344 COSTS_N_INSNS (18), /* SI */
345 COSTS_N_INSNS (18), /* DI */
346 COSTS_N_INSNS (18)}, /* other */
347 COSTS_N_INSNS (2), /* cost of movsx */
348 COSTS_N_INSNS (2), /* cost of movzx */
349 8, /* "large" insn */
351 3, /* cost for loading QImode using movzbl */
352 {4, 5, 4}, /* cost of loading integer registers
353 in QImode, HImode and SImode.
354 Relative to reg-reg move (2). */
355 {2, 3, 2}, /* cost of storing integer registers */
356 4, /* cost of reg,reg fld/fst */
357 {6, 6, 6}, /* cost of loading fp registers
358 in SFmode, DFmode and XFmode */
359 {4, 4, 4}, /* cost of loading integer registers */
360 2, /* cost of moving MMX register */
361 {2, 2}, /* cost of loading MMX registers
362 in SImode and DImode */
363 {2, 2}, /* cost of storing MMX registers
364 in SImode and DImode */
365 2, /* cost of moving SSE register */
366 {2, 2, 8}, /* cost of loading SSE registers
367 in SImode, DImode and TImode */
368 {2, 2, 8}, /* cost of storing SSE registers
369 in SImode, DImode and TImode */
370 6, /* MMX or SSE register to integer */
371 32, /* size of prefetch block */
372 1, /* number of parallel prefetches */
374 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
375 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
376 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
377 COSTS_N_INSNS (2), /* cost of FABS instruction. */
378 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
379 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
383 struct processor_costs athlon_cost = {
384 COSTS_N_INSNS (1), /* cost of an add instruction */
385 COSTS_N_INSNS (2), /* cost of a lea instruction */
386 COSTS_N_INSNS (1), /* variable shift costs */
387 COSTS_N_INSNS (1), /* constant shift costs */
388 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
389 COSTS_N_INSNS (5), /* HI */
390 COSTS_N_INSNS (5), /* SI */
391 COSTS_N_INSNS (5), /* DI */
392 COSTS_N_INSNS (5)}, /* other */
393 0, /* cost of multiply per each bit set */
394 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
395 COSTS_N_INSNS (26), /* HI */
396 COSTS_N_INSNS (42), /* SI */
397 COSTS_N_INSNS (74), /* DI */
398 COSTS_N_INSNS (74)}, /* other */
399 COSTS_N_INSNS (1), /* cost of movsx */
400 COSTS_N_INSNS (1), /* cost of movzx */
401 8, /* "large" insn */
403 4, /* cost for loading QImode using movzbl */
404 {3, 4, 3}, /* cost of loading integer registers
405 in QImode, HImode and SImode.
406 Relative to reg-reg move (2). */
407 {3, 4, 3}, /* cost of storing integer registers */
408 4, /* cost of reg,reg fld/fst */
409 {4, 4, 12}, /* cost of loading fp registers
410 in SFmode, DFmode and XFmode */
411 {6, 6, 8}, /* cost of loading integer registers */
412 2, /* cost of moving MMX register */
413 {4, 4}, /* cost of loading MMX registers
414 in SImode and DImode */
415 {4, 4}, /* cost of storing MMX registers
416 in SImode and DImode */
417 2, /* cost of moving SSE register */
418 {4, 4, 6}, /* cost of loading SSE registers
419 in SImode, DImode and TImode */
420 {4, 4, 5}, /* cost of storing SSE registers
421 in SImode, DImode and TImode */
422 5, /* MMX or SSE register to integer */
423 64, /* size of prefetch block */
424 6, /* number of parallel prefetches */
426 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
427 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
428 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
429 COSTS_N_INSNS (2), /* cost of FABS instruction. */
430 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
431 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
435 struct processor_costs k8_cost = {
436 COSTS_N_INSNS (1), /* cost of an add instruction */
437 COSTS_N_INSNS (2), /* cost of a lea instruction */
438 COSTS_N_INSNS (1), /* variable shift costs */
439 COSTS_N_INSNS (1), /* constant shift costs */
440 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
441 COSTS_N_INSNS (4), /* HI */
442 COSTS_N_INSNS (3), /* SI */
443 COSTS_N_INSNS (4), /* DI */
444 COSTS_N_INSNS (5)}, /* other */
445 0, /* cost of multiply per each bit set */
446 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
447 COSTS_N_INSNS (26), /* HI */
448 COSTS_N_INSNS (42), /* SI */
449 COSTS_N_INSNS (74), /* DI */
450 COSTS_N_INSNS (74)}, /* other */
451 COSTS_N_INSNS (1), /* cost of movsx */
452 COSTS_N_INSNS (1), /* cost of movzx */
453 8, /* "large" insn */
455 4, /* cost for loading QImode using movzbl */
456 {3, 4, 3}, /* cost of loading integer registers
457 in QImode, HImode and SImode.
458 Relative to reg-reg move (2). */
459 {3, 4, 3}, /* cost of storing integer registers */
460 4, /* cost of reg,reg fld/fst */
461 {4, 4, 12}, /* cost of loading fp registers
462 in SFmode, DFmode and XFmode */
463 {6, 6, 8}, /* cost of loading integer registers */
464 2, /* cost of moving MMX register */
465 {3, 3}, /* cost of loading MMX registers
466 in SImode and DImode */
467 {4, 4}, /* cost of storing MMX registers
468 in SImode and DImode */
469 2, /* cost of moving SSE register */
470 {4, 3, 6}, /* cost of loading SSE registers
471 in SImode, DImode and TImode */
472 {4, 4, 5}, /* cost of storing SSE registers
473 in SImode, DImode and TImode */
474 5, /* MMX or SSE register to integer */
475 64, /* size of prefetch block */
476 6, /* number of parallel prefetches */
478 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
479 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
480 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
481 COSTS_N_INSNS (2), /* cost of FABS instruction. */
482 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
483 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
487 struct processor_costs pentium4_cost = {
488 COSTS_N_INSNS (1), /* cost of an add instruction */
489 COSTS_N_INSNS (3), /* cost of a lea instruction */
490 COSTS_N_INSNS (4), /* variable shift costs */
491 COSTS_N_INSNS (4), /* constant shift costs */
492 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
493 COSTS_N_INSNS (15), /* HI */
494 COSTS_N_INSNS (15), /* SI */
495 COSTS_N_INSNS (15), /* DI */
496 COSTS_N_INSNS (15)}, /* other */
497 0, /* cost of multiply per each bit set */
498 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
499 COSTS_N_INSNS (56), /* HI */
500 COSTS_N_INSNS (56), /* SI */
501 COSTS_N_INSNS (56), /* DI */
502 COSTS_N_INSNS (56)}, /* other */
503 COSTS_N_INSNS (1), /* cost of movsx */
504 COSTS_N_INSNS (1), /* cost of movzx */
505 16, /* "large" insn */
507 2, /* cost for loading QImode using movzbl */
508 {4, 5, 4}, /* cost of loading integer registers
509 in QImode, HImode and SImode.
510 Relative to reg-reg move (2). */
511 {2, 3, 2}, /* cost of storing integer registers */
512 2, /* cost of reg,reg fld/fst */
513 {2, 2, 6}, /* cost of loading fp registers
514 in SFmode, DFmode and XFmode */
515 {4, 4, 6}, /* cost of loading integer registers */
516 2, /* cost of moving MMX register */
517 {2, 2}, /* cost of loading MMX registers
518 in SImode and DImode */
519 {2, 2}, /* cost of storing MMX registers
520 in SImode and DImode */
521 12, /* cost of moving SSE register */
522 {12, 12, 12}, /* cost of loading SSE registers
523 in SImode, DImode and TImode */
524 {2, 2, 8}, /* cost of storing SSE registers
525 in SImode, DImode and TImode */
526 10, /* MMX or SSE register to integer */
527 64, /* size of prefetch block */
528 6, /* number of parallel prefetches */
530 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
531 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
532 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
533 COSTS_N_INSNS (2), /* cost of FABS instruction. */
534 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
535 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
539 struct processor_costs nocona_cost = {
540 COSTS_N_INSNS (1), /* cost of an add instruction */
541 COSTS_N_INSNS (1), /* cost of a lea instruction */
542 COSTS_N_INSNS (1), /* variable shift costs */
543 COSTS_N_INSNS (1), /* constant shift costs */
544 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
545 COSTS_N_INSNS (10), /* HI */
546 COSTS_N_INSNS (10), /* SI */
547 COSTS_N_INSNS (10), /* DI */
548 COSTS_N_INSNS (10)}, /* other */
549 0, /* cost of multiply per each bit set */
550 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
551 COSTS_N_INSNS (66), /* HI */
552 COSTS_N_INSNS (66), /* SI */
553 COSTS_N_INSNS (66), /* DI */
554 COSTS_N_INSNS (66)}, /* other */
555 COSTS_N_INSNS (1), /* cost of movsx */
556 COSTS_N_INSNS (1), /* cost of movzx */
557 16, /* "large" insn */
559 4, /* cost for loading QImode using movzbl */
560 {4, 4, 4}, /* cost of loading integer registers
561 in QImode, HImode and SImode.
562 Relative to reg-reg move (2). */
563 {4, 4, 4}, /* cost of storing integer registers */
564 3, /* cost of reg,reg fld/fst */
565 {12, 12, 12}, /* cost of loading fp registers
566 in SFmode, DFmode and XFmode */
567 {4, 4, 4}, /* cost of loading integer registers */
568 6, /* cost of moving MMX register */
569 {12, 12}, /* cost of loading MMX registers
570 in SImode and DImode */
571 {12, 12}, /* cost of storing MMX registers
572 in SImode and DImode */
573 6, /* cost of moving SSE register */
574 {12, 12, 12}, /* cost of loading SSE registers
575 in SImode, DImode and TImode */
576 {12, 12, 12}, /* cost of storing SSE registers
577 in SImode, DImode and TImode */
578 8, /* MMX or SSE register to integer */
579 128, /* size of prefetch block */
580 8, /* number of parallel prefetches */
582 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
583 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
584 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
585 COSTS_N_INSNS (3), /* cost of FABS instruction. */
586 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
587 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
590 /* Generic64 should produce code tuned for Nocona and K8. */
592 struct processor_costs generic64_cost = {
593 COSTS_N_INSNS (1), /* cost of an add instruction */
594 /* On all chips taken into consideration lea is 2 cycles and more. With
595 this cost however our current implementation of synth_mult results in
596 use of unnecesary temporary registers causing regression on several
597 SPECfp benchmarks. */
598 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
599 COSTS_N_INSNS (1), /* variable shift costs */
600 COSTS_N_INSNS (1), /* constant shift costs */
601 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
602 COSTS_N_INSNS (4), /* HI */
603 COSTS_N_INSNS (3), /* SI */
604 COSTS_N_INSNS (4), /* DI */
605 COSTS_N_INSNS (2)}, /* other */
606 0, /* cost of multiply per each bit set */
607 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
608 COSTS_N_INSNS (26), /* HI */
609 COSTS_N_INSNS (42), /* SI */
610 COSTS_N_INSNS (74), /* DI */
611 COSTS_N_INSNS (74)}, /* other */
612 COSTS_N_INSNS (1), /* cost of movsx */
613 COSTS_N_INSNS (1), /* cost of movzx */
614 8, /* "large" insn */
616 4, /* cost for loading QImode using movzbl */
617 {4, 4, 4}, /* cost of loading integer registers
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
620 {4, 4, 4}, /* cost of storing integer registers */
621 4, /* cost of reg,reg fld/fst */
622 {12, 12, 12}, /* cost of loading fp registers
623 in SFmode, DFmode and XFmode */
624 {6, 6, 8}, /* cost of loading integer registers */
625 2, /* cost of moving MMX register */
626 {8, 8}, /* cost of loading MMX registers
627 in SImode and DImode */
628 {8, 8}, /* cost of storing MMX registers
629 in SImode and DImode */
630 2, /* cost of moving SSE register */
631 {8, 8, 8}, /* cost of loading SSE registers
632 in SImode, DImode and TImode */
633 {8, 8, 8}, /* cost of storing SSE registers
634 in SImode, DImode and TImode */
635 5, /* MMX or SSE register to integer */
636 64, /* size of prefetch block */
637 6, /* number of parallel prefetches */
638 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
639 is increased to perhaps more appropriate value of 5. */
641 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
642 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
643 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
644 COSTS_N_INSNS (8), /* cost of FABS instruction. */
645 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
646 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
649 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
651 struct processor_costs generic32_cost = {
652 COSTS_N_INSNS (1), /* cost of an add instruction */
653 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
654 COSTS_N_INSNS (1), /* variable shift costs */
655 COSTS_N_INSNS (1), /* constant shift costs */
656 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
657 COSTS_N_INSNS (4), /* HI */
658 COSTS_N_INSNS (3), /* SI */
659 COSTS_N_INSNS (4), /* DI */
660 COSTS_N_INSNS (2)}, /* other */
661 0, /* cost of multiply per each bit set */
662 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
663 COSTS_N_INSNS (26), /* HI */
664 COSTS_N_INSNS (42), /* SI */
665 COSTS_N_INSNS (74), /* DI */
666 COSTS_N_INSNS (74)}, /* other */
667 COSTS_N_INSNS (1), /* cost of movsx */
668 COSTS_N_INSNS (1), /* cost of movzx */
669 8, /* "large" insn */
671 4, /* cost for loading QImode using movzbl */
672 {4, 4, 4}, /* cost of loading integer registers
673 in QImode, HImode and SImode.
674 Relative to reg-reg move (2). */
675 {4, 4, 4}, /* cost of storing integer registers */
676 4, /* cost of reg,reg fld/fst */
677 {12, 12, 12}, /* cost of loading fp registers
678 in SFmode, DFmode and XFmode */
679 {6, 6, 8}, /* cost of loading integer registers */
680 2, /* cost of moving MMX register */
681 {8, 8}, /* cost of loading MMX registers
682 in SImode and DImode */
683 {8, 8}, /* cost of storing MMX registers
684 in SImode and DImode */
685 2, /* cost of moving SSE register */
686 {8, 8, 8}, /* cost of loading SSE registers
687 in SImode, DImode and TImode */
688 {8, 8, 8}, /* cost of storing SSE registers
689 in SImode, DImode and TImode */
690 5, /* MMX or SSE register to integer */
691 64, /* size of prefetch block */
692 6, /* number of parallel prefetches */
694 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
695 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
696 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
697 COSTS_N_INSNS (8), /* cost of FABS instruction. */
698 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
699 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
702 const struct processor_costs *ix86_cost = &pentium_cost;
704 /* Processor feature/optimization bitmasks. */
705 #define m_386 (1<<PROCESSOR_I386)
706 #define m_486 (1<<PROCESSOR_I486)
707 #define m_PENT (1<<PROCESSOR_PENTIUM)
708 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
709 #define m_K6 (1<<PROCESSOR_K6)
710 #define m_ATHLON (1<<PROCESSOR_ATHLON)
711 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
712 #define m_K8 (1<<PROCESSOR_K8)
713 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
714 #define m_NOCONA (1<<PROCESSOR_NOCONA)
715 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
716 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
717 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
719 /* Generic instruction choice should be common subset of supported CPUs
720 (PPro/PENT4/NOCONA/Athlon/K8). */
722 /* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
723 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
724 generic because it is not working well with PPro base chips. */
725 const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64;
726 const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
727 const int x86_zero_extend_with_and = m_486 | m_PENT;
728 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */;
729 const int x86_double_with_add = ~m_386;
730 const int x86_use_bit_test = m_386;
731 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
732 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
733 const int x86_fisttp = m_NOCONA;
734 const int x86_3dnow_a = m_ATHLON_K8;
735 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
736 /* Branch hints were put in P4 based on simulation result. But
737 after P4 was made, no performance benefit was observed with
738 branch hints. It also increases the code size. As the result,
739 icc never generates branch hints. */
740 const int x86_branch_hints = 0;
741 const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
742 /* We probably ought to watch for partial register stalls on Generic32
743 compilation setting as well. However in current implementation the
744 partial register stalls are not eliminated very well - they can
745 be introduced via subregs synthesized by combine and can happen
746 in caller/callee saving sequences.
747 Because this option pays back little on PPro based chips and is in conflict
748 with partial reg. dependencies used by Athlon/P4 based chips, it is better
749 to leave it off for generic32 for now. */
750 const int x86_partial_reg_stall = m_PPRO;
751 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
752 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
753 const int x86_use_mov0 = m_K6;
754 const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC);
755 const int x86_read_modify_write = ~m_PENT;
756 const int x86_read_modify = ~(m_PENT | m_PPRO);
757 const int x86_split_long_moves = m_PPRO;
758 const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */
759 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
760 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
761 const int x86_qimode_math = ~(0);
762 const int x86_promote_qi_regs = 0;
763 /* On PPro this flag is meant to avoid partial register stalls. Just like
764 the x86_partial_reg_stall this option might be considered for Generic32
765 if our scheme for avoiding partial stalls was more effective. */
766 const int x86_himode_math = ~(m_PPRO);
767 const int x86_promote_hi_regs = m_PPRO;
768 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC;
769 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
770 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC;
771 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
772 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC);
773 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
774 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
775 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
776 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
777 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
778 const int x86_shift1 = ~m_486;
779 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
780 /* In Generic model we have an conflict here in between PPro/Pentium4 based chips
781 that thread 128bit SSE registers as single units versus K8 based chips that
782 divide SSE registers to two 64bit halves.
783 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
784 to allow register renaming on 128bit SSE units, but usually results in one
785 extra microop on 64bit SSE units. Experimental results shows that disabling
786 this option on P4 brings over 20% SPECfp regression, while enabling it on
787 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
789 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
790 /* Set for machines where the type and dependencies are resolved on SSE
791 register parts instead of whole registers, so we may maintain just
792 lower part of scalar values in proper format leaving the upper part
794 const int x86_sse_split_regs = m_ATHLON_K8;
795 const int x86_sse_typeless_stores = m_ATHLON_K8;
796 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
797 const int x86_use_ffreep = m_ATHLON_K8;
798 const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
799 const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC);
801 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
802 integer data in xmm registers. Which results in pretty abysmal code. */
803 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
805 const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
806 /* Some CPU cores are not able to predict more than 4 branch instructions in
807 the 16 byte window. */
808 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
809 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC;
810 const int x86_use_bt = m_ATHLON_K8;
811 /* Compare and exchange was added for 80486. */
812 const int x86_cmpxchg = ~m_386;
813 /* Compare and exchange 8 bytes was added for pentium. */
814 const int x86_cmpxchg8b = ~(m_386 | m_486);
815 /* Compare and exchange 16 bytes was added for nocona. */
816 const int x86_cmpxchg16b = m_NOCONA;
817 /* Exchange and add was added for 80486. */
818 const int x86_xadd = ~m_386;
819 const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC;
821 /* In case the average insn count for single function invocation is
822 lower than this constant, emit fast (but longer) prologue and
824 #define FAST_PROLOGUE_INSN_COUNT 20
826 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
827 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
828 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
829 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
831 /* Array of the smallest class containing reg number REGNO, indexed by
832 REGNO. Used by REGNO_REG_CLASS in i386.h. */
834 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
837 AREG, DREG, CREG, BREG,
839 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
841 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
842 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
845 /* flags, fpsr, dirflag, frame */
846 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
847 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
849 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
851 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
852 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
853 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
857 /* The "default" register map used in 32bit mode. */
859 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
861 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
862 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
863 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
864 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
865 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
866 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
867 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
870 static int const x86_64_int_parameter_registers[6] =
872 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
873 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
876 static int const x86_64_int_return_registers[4] =
878 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
881 /* The "default" register map used in 64bit mode. */
882 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
884 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
885 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
886 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
887 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
888 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
889 8,9,10,11,12,13,14,15, /* extended integer registers */
890 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
893 /* Define the register numbers to be used in Dwarf debugging information.
894 The SVR4 reference port C compiler uses the following register numbers
895 in its Dwarf output code:
896 0 for %eax (gcc regno = 0)
897 1 for %ecx (gcc regno = 2)
898 2 for %edx (gcc regno = 1)
899 3 for %ebx (gcc regno = 3)
900 4 for %esp (gcc regno = 7)
901 5 for %ebp (gcc regno = 6)
902 6 for %esi (gcc regno = 4)
903 7 for %edi (gcc regno = 5)
904 The following three DWARF register numbers are never generated by
905 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
906 believes these numbers have these meanings.
907 8 for %eip (no gcc equivalent)
908 9 for %eflags (gcc regno = 17)
909 10 for %trapno (no gcc equivalent)
910 It is not at all clear how we should number the FP stack registers
911 for the x86 architecture. If the version of SDB on x86/svr4 were
912 a bit less brain dead with respect to floating-point then we would
913 have a precedent to follow with respect to DWARF register numbers
914 for x86 FP registers, but the SDB on x86/svr4 is so completely
915 broken with respect to FP registers that it is hardly worth thinking
916 of it as something to strive for compatibility with.
917 The version of x86/svr4 SDB I have at the moment does (partially)
918 seem to believe that DWARF register number 11 is associated with
919 the x86 register %st(0), but that's about all. Higher DWARF
920 register numbers don't seem to be associated with anything in
921 particular, and even for DWARF regno 11, SDB only seems to under-
922 stand that it should say that a variable lives in %st(0) (when
923 asked via an `=' command) if we said it was in DWARF regno 11,
924 but SDB still prints garbage when asked for the value of the
925 variable in question (via a `/' command).
926 (Also note that the labels SDB prints for various FP stack regs
927 when doing an `x' command are all wrong.)
928 Note that these problems generally don't affect the native SVR4
929 C compiler because it doesn't allow the use of -O with -g and
930 because when it is *not* optimizing, it allocates a memory
931 location for each floating-point variable, and the memory
932 location is what gets described in the DWARF AT_location
933 attribute for the variable in question.
934 Regardless of the severe mental illness of the x86/svr4 SDB, we
935 do something sensible here and we use the following DWARF
936 register numbers. Note that these are all stack-top-relative
938 11 for %st(0) (gcc regno = 8)
939 12 for %st(1) (gcc regno = 9)
940 13 for %st(2) (gcc regno = 10)
941 14 for %st(3) (gcc regno = 11)
942 15 for %st(4) (gcc regno = 12)
943 16 for %st(5) (gcc regno = 13)
944 17 for %st(6) (gcc regno = 14)
945 18 for %st(7) (gcc regno = 15)
947 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
949 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
950 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
951 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
952 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
953 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
954 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
955 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
958 /* Test and compare insns in i386.md store the information needed to
959 generate branch and scc insns here. */
961 rtx ix86_compare_op0 = NULL_RTX;
962 rtx ix86_compare_op1 = NULL_RTX;
963 rtx ix86_compare_emitted = NULL_RTX;
965 /* Size of the register save area. */
966 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
968 /* Define the structure for the machine field in struct function. */
970 struct stack_local_entry GTY(())
975 struct stack_local_entry *next;
978 /* Structure describing stack frame layout.
979 Stack grows downward:
985 saved frame pointer if frame_pointer_needed
986 <- HARD_FRAME_POINTER
992 > to_allocate <- FRAME_POINTER
1002 HOST_WIDE_INT frame;
1004 int outgoing_arguments_size;
1007 HOST_WIDE_INT to_allocate;
1008 /* The offsets relative to ARG_POINTER. */
1009 HOST_WIDE_INT frame_pointer_offset;
1010 HOST_WIDE_INT hard_frame_pointer_offset;
1011 HOST_WIDE_INT stack_pointer_offset;
1013 /* When save_regs_using_mov is set, emit prologue using
1014 move instead of push instructions. */
1015 bool save_regs_using_mov;
1018 /* Code model option. */
1019 enum cmodel ix86_cmodel;
1021 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1023 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1025 /* Which unit we are generating floating point math for. */
1026 enum fpmath_unit ix86_fpmath;
1028 /* Which cpu are we scheduling for. */
1029 enum processor_type ix86_tune;
1030 /* Which instruction set architecture to use. */
1031 enum processor_type ix86_arch;
1033 /* true if sse prefetch instruction is not NOOP. */
1034 int x86_prefetch_sse;
1036 /* ix86_regparm_string as a number */
1037 static int ix86_regparm;
1039 /* Preferred alignment for stack boundary in bits. */
1040 unsigned int ix86_preferred_stack_boundary;
1042 /* Values 1-5: see jump.c */
1043 int ix86_branch_cost;
1045 /* Variables which are this size or smaller are put in the data/bss
1046 or ldata/lbss sections. */
1048 int ix86_section_threshold = 65536;
1050 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1051 char internal_label_prefix[16];
1052 int internal_label_prefix_len;
1054 /* Table for BUILT_IN_NORMAL to BUILT_IN_MD mapping. */
1055 static GTY(()) tree ix86_builtin_function_variants[(int) END_BUILTINS];
1057 static bool ix86_handle_option (size_t, const char *, int);
1058 static void output_pic_addr_const (FILE *, rtx, int);
1059 static void put_condition_code (enum rtx_code, enum machine_mode,
1061 static const char *get_some_local_dynamic_name (void);
1062 static int get_some_local_dynamic_name_1 (rtx *, void *);
1063 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
1064 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
1066 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
1067 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
1069 static rtx get_thread_pointer (int);
1070 static rtx legitimize_tls_address (rtx, enum tls_model, int);
1071 static void get_pc_thunk_name (char [32], unsigned int);
1072 static rtx gen_push (rtx);
1073 static int ix86_flags_dependant (rtx, rtx, enum attr_type);
1074 static int ix86_agi_dependant (rtx, rtx, enum attr_type);
1075 static struct machine_function * ix86_init_machine_status (void);
1076 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
1077 static int ix86_nsaved_regs (void);
1078 static void ix86_emit_save_regs (void);
1079 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
1080 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
1081 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
1082 static HOST_WIDE_INT ix86_GOT_alias_set (void);
1083 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
1084 static rtx ix86_expand_aligntest (rtx, int);
1085 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
1086 static int ix86_issue_rate (void);
1087 static int ix86_adjust_cost (rtx, rtx, rtx, int);
1088 static int ia32_multipass_dfa_lookahead (void);
1089 static void ix86_init_mmx_sse_builtins (void);
1090 static void ix86_init_sse_abi_builtins (void);
1091 static rtx x86_this_parameter (tree);
1092 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
1093 HOST_WIDE_INT, tree);
1094 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
1095 static void x86_file_start (void);
1096 static void ix86_reorg (void);
1097 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
1098 static tree ix86_build_builtin_va_list (void);
1099 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
1101 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
1102 static bool ix86_scalar_mode_supported_p (enum machine_mode);
1103 static bool ix86_vector_mode_supported_p (enum machine_mode);
1105 static int ix86_address_cost (rtx);
1106 static bool ix86_cannot_force_const_mem (rtx);
1107 static rtx ix86_delegitimize_address (rtx);
1109 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1111 struct builtin_description;
1112 static rtx ix86_expand_sse_comi (const struct builtin_description *,
1114 static rtx ix86_expand_sse_compare (const struct builtin_description *,
1116 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
1117 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
1118 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
1119 static rtx ix86_expand_store_builtin (enum insn_code, tree);
1120 static rtx safe_vector_operand (rtx, enum machine_mode);
1121 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
1122 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
1123 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
1124 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
1125 static int ix86_fp_comparison_cost (enum rtx_code code);
1126 static unsigned int ix86_select_alt_pic_regnum (void);
1127 static int ix86_save_reg (unsigned int, int);
1128 static void ix86_compute_frame_layout (struct ix86_frame *);
1129 static int ix86_comp_type_attributes (tree, tree);
1130 static int ix86_function_regparm (tree, tree);
1131 const struct attribute_spec ix86_attribute_table[];
1132 static bool ix86_function_ok_for_sibcall (tree, tree);
1133 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
1134 static int ix86_value_regno (enum machine_mode, tree, tree);
1135 static bool contains_128bit_aligned_vector_p (tree);
1136 static rtx ix86_struct_value_rtx (tree, int);
1137 static bool ix86_ms_bitfield_layout_p (tree);
1138 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
1139 static int extended_reg_mentioned_1 (rtx *, void *);
1140 static bool ix86_rtx_costs (rtx, int, int, int *);
1141 static int min_insn_size (rtx);
1142 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
1143 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
1144 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
1146 static void ix86_init_builtins (void);
1147 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1148 static rtx ix86_expand_library_builtin (tree, rtx, rtx, enum machine_mode, int);
1149 static const char *ix86_mangle_fundamental_type (tree);
1150 static tree ix86_stack_protect_fail (void);
1151 static rtx ix86_internal_arg_pointer (void);
1152 static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
1154 /* This function is only used on Solaris. */
1155 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
1158 /* Register class used for passing given 64bit part of the argument.
1159 These represent classes as documented by the PS ABI, with the exception
1160 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1161 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1163 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1164 whenever possible (upper half does contain padding).
1166 enum x86_64_reg_class
1169 X86_64_INTEGER_CLASS,
1170 X86_64_INTEGERSI_CLASS,
1177 X86_64_COMPLEX_X87_CLASS,
1180 static const char * const x86_64_reg_class_name[] = {
1181 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1182 "sseup", "x87", "x87up", "cplx87", "no"
1185 #define MAX_CLASSES 4
1187 /* Table of constants used by fldpi, fldln2, etc.... */
1188 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1189 static bool ext_80387_constants_init = 0;
1190 static void init_ext_80387_constants (void);
1191 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
1192 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
1193 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
1194 static section *x86_64_elf_select_section (tree decl, int reloc,
1195 unsigned HOST_WIDE_INT align)
1198 /* Initialize the GCC target structure. */
1199 #undef TARGET_ATTRIBUTE_TABLE
1200 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
1201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1202 # undef TARGET_MERGE_DECL_ATTRIBUTES
1203 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
1206 #undef TARGET_COMP_TYPE_ATTRIBUTES
1207 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
1209 #undef TARGET_INIT_BUILTINS
1210 #define TARGET_INIT_BUILTINS ix86_init_builtins
1211 #undef TARGET_EXPAND_BUILTIN
1212 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
1213 #undef TARGET_EXPAND_LIBRARY_BUILTIN
1214 #define TARGET_EXPAND_LIBRARY_BUILTIN ix86_expand_library_builtin
1216 #undef TARGET_ASM_FUNCTION_EPILOGUE
1217 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
1219 #undef TARGET_ENCODE_SECTION_INFO
1220 #ifndef SUBTARGET_ENCODE_SECTION_INFO
1221 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
1223 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
1226 #undef TARGET_ASM_OPEN_PAREN
1227 #define TARGET_ASM_OPEN_PAREN ""
1228 #undef TARGET_ASM_CLOSE_PAREN
1229 #define TARGET_ASM_CLOSE_PAREN ""
1231 #undef TARGET_ASM_ALIGNED_HI_OP
1232 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
1233 #undef TARGET_ASM_ALIGNED_SI_OP
1234 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1236 #undef TARGET_ASM_ALIGNED_DI_OP
1237 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1240 #undef TARGET_ASM_UNALIGNED_HI_OP
1241 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1242 #undef TARGET_ASM_UNALIGNED_SI_OP
1243 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1244 #undef TARGET_ASM_UNALIGNED_DI_OP
1245 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1247 #undef TARGET_SCHED_ADJUST_COST
1248 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1249 #undef TARGET_SCHED_ISSUE_RATE
1250 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1251 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1252 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1253 ia32_multipass_dfa_lookahead
1255 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1256 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1259 #undef TARGET_HAVE_TLS
1260 #define TARGET_HAVE_TLS true
1262 #undef TARGET_CANNOT_FORCE_CONST_MEM
1263 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1264 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1265 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
1267 #undef TARGET_DELEGITIMIZE_ADDRESS
1268 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1270 #undef TARGET_MS_BITFIELD_LAYOUT_P
1271 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1274 #undef TARGET_BINDS_LOCAL_P
1275 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1278 #undef TARGET_ASM_OUTPUT_MI_THUNK
1279 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1280 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1281 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1283 #undef TARGET_ASM_FILE_START
1284 #define TARGET_ASM_FILE_START x86_file_start
1286 #undef TARGET_DEFAULT_TARGET_FLAGS
1287 #define TARGET_DEFAULT_TARGET_FLAGS \
1289 | TARGET_64BIT_DEFAULT \
1290 | TARGET_SUBTARGET_DEFAULT \
1291 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1293 #undef TARGET_HANDLE_OPTION
1294 #define TARGET_HANDLE_OPTION ix86_handle_option
1296 #undef TARGET_RTX_COSTS
1297 #define TARGET_RTX_COSTS ix86_rtx_costs
1298 #undef TARGET_ADDRESS_COST
1299 #define TARGET_ADDRESS_COST ix86_address_cost
1301 #undef TARGET_FIXED_CONDITION_CODE_REGS
1302 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1303 #undef TARGET_CC_MODES_COMPATIBLE
1304 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1306 #undef TARGET_MACHINE_DEPENDENT_REORG
1307 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1309 #undef TARGET_BUILD_BUILTIN_VA_LIST
1310 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1312 #undef TARGET_MD_ASM_CLOBBERS
1313 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1315 #undef TARGET_PROMOTE_PROTOTYPES
1316 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1317 #undef TARGET_STRUCT_VALUE_RTX
1318 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1319 #undef TARGET_SETUP_INCOMING_VARARGS
1320 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1321 #undef TARGET_MUST_PASS_IN_STACK
1322 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1323 #undef TARGET_PASS_BY_REFERENCE
1324 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1325 #undef TARGET_INTERNAL_ARG_POINTER
1326 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1327 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1328 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1330 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1331 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1333 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1334 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
1336 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1337 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1340 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1341 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1344 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1345 #undef TARGET_INSERT_ATTRIBUTES
1346 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1349 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1350 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1352 #undef TARGET_STACK_PROTECT_FAIL
1353 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1355 #undef TARGET_FUNCTION_VALUE
1356 #define TARGET_FUNCTION_VALUE ix86_function_value
1358 struct gcc_target targetm = TARGET_INITIALIZER;
1361 /* The svr4 ABI for the i386 says that records and unions are returned
1363 #ifndef DEFAULT_PCC_STRUCT_RETURN
1364 #define DEFAULT_PCC_STRUCT_RETURN 1
1367 /* Implement TARGET_HANDLE_OPTION. */
1370 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1377 target_flags &= ~MASK_3DNOW_A;
1378 target_flags_explicit |= MASK_3DNOW_A;
1385 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1386 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1393 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1394 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1401 target_flags &= ~MASK_SSE3;
1402 target_flags_explicit |= MASK_SSE3;
1411 /* Sometimes certain combinations of command options do not make
1412 sense on a particular target machine. You can define a macro
1413 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1414 defined, is executed once just after all the command options have
1417 Don't use this macro to turn on various extra optimizations for
1418 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1421 override_options (void)
1424 int ix86_tune_defaulted = 0;
1426 /* Comes from final.c -- no real reason to change it. */
1427 #define MAX_CODE_ALIGN 16
1431 const struct processor_costs *cost; /* Processor costs */
1432 const int target_enable; /* Target flags to enable. */
1433 const int target_disable; /* Target flags to disable. */
1434 const int align_loop; /* Default alignments. */
1435 const int align_loop_max_skip;
1436 const int align_jump;
1437 const int align_jump_max_skip;
1438 const int align_func;
1440 const processor_target_table[PROCESSOR_max] =
1442 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1443 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1444 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1445 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1446 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1447 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1448 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1449 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1450 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1451 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1452 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1455 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1458 const char *const name; /* processor name or nickname. */
1459 const enum processor_type processor;
1460 const enum pta_flags
1466 PTA_PREFETCH_SSE = 16,
1472 const processor_alias_table[] =
1474 {"i386", PROCESSOR_I386, 0},
1475 {"i486", PROCESSOR_I486, 0},
1476 {"i586", PROCESSOR_PENTIUM, 0},
1477 {"pentium", PROCESSOR_PENTIUM, 0},
1478 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1479 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1480 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1481 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1482 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1483 {"i686", PROCESSOR_PENTIUMPRO, 0},
1484 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1485 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1486 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1487 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1488 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1489 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1490 | PTA_MMX | PTA_PREFETCH_SSE},
1491 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1492 | PTA_MMX | PTA_PREFETCH_SSE},
1493 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1494 | PTA_MMX | PTA_PREFETCH_SSE},
1495 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1496 | PTA_MMX | PTA_PREFETCH_SSE},
1497 {"k6", PROCESSOR_K6, PTA_MMX},
1498 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1499 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1500 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1502 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1503 | PTA_3DNOW | PTA_3DNOW_A},
1504 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1505 | PTA_3DNOW_A | PTA_SSE},
1506 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1507 | PTA_3DNOW_A | PTA_SSE},
1508 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1509 | PTA_3DNOW_A | PTA_SSE},
1510 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1511 | PTA_SSE | PTA_SSE2 },
1512 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1513 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1514 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1515 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1516 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1517 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1518 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1519 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1520 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1521 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1524 int const pta_size = ARRAY_SIZE (processor_alias_table);
1526 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1527 SUBTARGET_OVERRIDE_OPTIONS;
1530 /* Set the default values for switches whose default depends on TARGET_64BIT
1531 in case they weren't overwritten by command line options. */
1534 if (flag_omit_frame_pointer == 2)
1535 flag_omit_frame_pointer = 1;
1536 if (flag_asynchronous_unwind_tables == 2)
1537 flag_asynchronous_unwind_tables = 1;
1538 if (flag_pcc_struct_return == 2)
1539 flag_pcc_struct_return = 0;
1543 if (flag_omit_frame_pointer == 2)
1544 flag_omit_frame_pointer = 0;
1545 if (flag_asynchronous_unwind_tables == 2)
1546 flag_asynchronous_unwind_tables = 0;
1547 if (flag_pcc_struct_return == 2)
1548 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1551 /* Need to check -mtune=generic first. */
1552 if (ix86_tune_string)
1554 if (!strcmp (ix86_tune_string, "generic")
1555 || !strcmp (ix86_tune_string, "i686"))
1558 ix86_tune_string = "generic64";
1560 ix86_tune_string = "generic32";
1562 else if (!strncmp (ix86_tune_string, "generic", 7))
1563 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1567 if (ix86_arch_string)
1568 ix86_tune_string = ix86_arch_string;
1569 if (!ix86_tune_string)
1571 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1572 ix86_tune_defaulted = 1;
1575 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1576 need to use a sensible tune option. */
1577 if (!strcmp (ix86_tune_string, "generic")
1578 || !strcmp (ix86_tune_string, "x86-64")
1579 || !strcmp (ix86_tune_string, "i686"))
1582 ix86_tune_string = "generic64";
1584 ix86_tune_string = "generic32";
1587 if (!strcmp (ix86_tune_string, "x86-64"))
1588 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
1589 "-mtune=generic instead as appropriate.");
1591 if (!ix86_arch_string)
1592 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1593 if (!strcmp (ix86_arch_string, "generic"))
1594 error ("generic CPU can be used only for -mtune= switch");
1595 if (!strncmp (ix86_arch_string, "generic", 7))
1596 error ("bad value (%s) for -march= switch", ix86_arch_string);
1598 if (ix86_cmodel_string != 0)
1600 if (!strcmp (ix86_cmodel_string, "small"))
1601 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1602 else if (!strcmp (ix86_cmodel_string, "medium"))
1603 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1605 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1606 else if (!strcmp (ix86_cmodel_string, "32"))
1607 ix86_cmodel = CM_32;
1608 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1609 ix86_cmodel = CM_KERNEL;
1610 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1611 ix86_cmodel = CM_LARGE;
1613 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1617 ix86_cmodel = CM_32;
1619 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1621 if (ix86_asm_string != 0)
1624 && !strcmp (ix86_asm_string, "intel"))
1625 ix86_asm_dialect = ASM_INTEL;
1626 else if (!strcmp (ix86_asm_string, "att"))
1627 ix86_asm_dialect = ASM_ATT;
1629 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1631 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1632 error ("code model %qs not supported in the %s bit mode",
1633 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1634 if (ix86_cmodel == CM_LARGE)
1635 sorry ("code model %<large%> not supported yet");
1636 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1637 sorry ("%i-bit mode not compiled in",
1638 (target_flags & MASK_64BIT) ? 64 : 32);
1640 for (i = 0; i < pta_size; i++)
1641 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1643 ix86_arch = processor_alias_table[i].processor;
1644 /* Default cpu tuning to the architecture. */
1645 ix86_tune = ix86_arch;
1646 if (processor_alias_table[i].flags & PTA_MMX
1647 && !(target_flags_explicit & MASK_MMX))
1648 target_flags |= MASK_MMX;
1649 if (processor_alias_table[i].flags & PTA_3DNOW
1650 && !(target_flags_explicit & MASK_3DNOW))
1651 target_flags |= MASK_3DNOW;
1652 if (processor_alias_table[i].flags & PTA_3DNOW_A
1653 && !(target_flags_explicit & MASK_3DNOW_A))
1654 target_flags |= MASK_3DNOW_A;
1655 if (processor_alias_table[i].flags & PTA_SSE
1656 && !(target_flags_explicit & MASK_SSE))
1657 target_flags |= MASK_SSE;
1658 if (processor_alias_table[i].flags & PTA_SSE2
1659 && !(target_flags_explicit & MASK_SSE2))
1660 target_flags |= MASK_SSE2;
1661 if (processor_alias_table[i].flags & PTA_SSE3
1662 && !(target_flags_explicit & MASK_SSE3))
1663 target_flags |= MASK_SSE3;
1664 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1665 x86_prefetch_sse = true;
1666 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1667 error ("CPU you selected does not support x86-64 "
1673 error ("bad value (%s) for -march= switch", ix86_arch_string);
1675 for (i = 0; i < pta_size; i++)
1676 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1678 ix86_tune = processor_alias_table[i].processor;
1679 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1681 if (ix86_tune_defaulted)
1683 ix86_tune_string = "x86-64";
1684 for (i = 0; i < pta_size; i++)
1685 if (! strcmp (ix86_tune_string,
1686 processor_alias_table[i].name))
1688 ix86_tune = processor_alias_table[i].processor;
1691 error ("CPU you selected does not support x86-64 "
1694 /* Intel CPUs have always interpreted SSE prefetch instructions as
1695 NOPs; so, we can enable SSE prefetch instructions even when
1696 -mtune (rather than -march) points us to a processor that has them.
1697 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1698 higher processors. */
1699 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1700 x86_prefetch_sse = true;
1704 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1707 ix86_cost = &size_cost;
1709 ix86_cost = processor_target_table[ix86_tune].cost;
1710 target_flags |= processor_target_table[ix86_tune].target_enable;
1711 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1713 /* Arrange to set up i386_stack_locals for all functions. */
1714 init_machine_status = ix86_init_machine_status;
1716 /* Validate -mregparm= value. */
1717 if (ix86_regparm_string)
1719 i = atoi (ix86_regparm_string);
1720 if (i < 0 || i > REGPARM_MAX)
1721 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1727 ix86_regparm = REGPARM_MAX;
1729 /* If the user has provided any of the -malign-* options,
1730 warn and use that value only if -falign-* is not set.
1731 Remove this code in GCC 3.2 or later. */
1732 if (ix86_align_loops_string)
1734 warning (0, "-malign-loops is obsolete, use -falign-loops");
1735 if (align_loops == 0)
1737 i = atoi (ix86_align_loops_string);
1738 if (i < 0 || i > MAX_CODE_ALIGN)
1739 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1741 align_loops = 1 << i;
1745 if (ix86_align_jumps_string)
1747 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1748 if (align_jumps == 0)
1750 i = atoi (ix86_align_jumps_string);
1751 if (i < 0 || i > MAX_CODE_ALIGN)
1752 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1754 align_jumps = 1 << i;
1758 if (ix86_align_funcs_string)
1760 warning (0, "-malign-functions is obsolete, use -falign-functions");
1761 if (align_functions == 0)
1763 i = atoi (ix86_align_funcs_string);
1764 if (i < 0 || i > MAX_CODE_ALIGN)
1765 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1767 align_functions = 1 << i;
1771 /* Default align_* from the processor table. */
1772 if (align_loops == 0)
1774 align_loops = processor_target_table[ix86_tune].align_loop;
1775 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
1777 if (align_jumps == 0)
1779 align_jumps = processor_target_table[ix86_tune].align_jump;
1780 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
1782 if (align_functions == 0)
1784 align_functions = processor_target_table[ix86_tune].align_func;
1787 /* Validate -mpreferred-stack-boundary= value, or provide default.
1788 The default of 128 bits is for Pentium III's SSE __m128, but we
1789 don't want additional code to keep the stack aligned when
1790 optimizing for code size. */
1791 ix86_preferred_stack_boundary = ((TARGET_64BIT || TARGET_MACHO || !optimize_size)
1793 if (ix86_preferred_stack_boundary_string)
1795 i = atoi (ix86_preferred_stack_boundary_string);
1796 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
1797 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
1798 TARGET_64BIT ? 4 : 2);
1800 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
1803 /* Validate -mbranch-cost= value, or provide default. */
1804 ix86_branch_cost = ix86_cost->branch_cost;
1805 if (ix86_branch_cost_string)
1807 i = atoi (ix86_branch_cost_string);
1809 error ("-mbranch-cost=%d is not between 0 and 5", i);
1811 ix86_branch_cost = i;
1813 if (ix86_section_threshold_string)
1815 i = atoi (ix86_section_threshold_string);
1817 error ("-mlarge-data-threshold=%d is negative", i);
1819 ix86_section_threshold = i;
1822 if (ix86_tls_dialect_string)
1824 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
1825 ix86_tls_dialect = TLS_DIALECT_GNU;
1826 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
1827 ix86_tls_dialect = TLS_DIALECT_GNU2;
1828 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
1829 ix86_tls_dialect = TLS_DIALECT_SUN;
1831 error ("bad value (%s) for -mtls-dialect= switch",
1832 ix86_tls_dialect_string);
1835 /* Keep nonleaf frame pointers. */
1836 if (flag_omit_frame_pointer)
1837 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
1838 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
1839 flag_omit_frame_pointer = 1;
1841 /* If we're doing fast math, we don't care about comparison order
1842 wrt NaNs. This lets us use a shorter comparison sequence. */
1843 if (flag_unsafe_math_optimizations)
1844 target_flags &= ~MASK_IEEE_FP;
1846 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1847 since the insns won't need emulation. */
1848 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1849 target_flags &= ~MASK_NO_FANCY_MATH_387;
1851 /* Likewise, if the target doesn't have a 387, or we've specified
1852 software floating point, don't use 387 inline intrinsics. */
1854 target_flags |= MASK_NO_FANCY_MATH_387;
1856 /* Turn on SSE2 builtins for -msse3. */
1858 target_flags |= MASK_SSE2;
1860 /* Turn on SSE builtins for -msse2. */
1862 target_flags |= MASK_SSE;
1864 /* Turn on MMX builtins for -msse. */
1867 target_flags |= MASK_MMX & ~target_flags_explicit;
1868 x86_prefetch_sse = true;
1871 /* Turn on MMX builtins for 3Dnow. */
1873 target_flags |= MASK_MMX;
1877 if (TARGET_ALIGN_DOUBLE)
1878 error ("-malign-double makes no sense in the 64bit mode");
1880 error ("-mrtd calling convention not supported in the 64bit mode");
1882 /* Enable by default the SSE and MMX builtins. Do allow the user to
1883 explicitly disable any of these. In particular, disabling SSE and
1884 MMX for kernel code is extremely useful. */
1886 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
1887 & ~target_flags_explicit);
1891 /* i386 ABI does not specify red zone. It still makes sense to use it
1892 when programmer takes care to stack from being destroyed. */
1893 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
1894 target_flags |= MASK_NO_RED_ZONE;
1897 /* Accept -msseregparm only if at least SSE support is enabled. */
1898 if (TARGET_SSEREGPARM
1900 error ("-msseregparm used without SSE enabled");
1902 /* Accept -msselibm only if at least SSE support is enabled. */
1905 error ("-msselibm used without SSE2 enabled");
1907 /* Ignore -msselibm on 64bit targets. */
1910 error ("-msselibm used on a 64bit target");
1912 ix86_fpmath = TARGET_FPMATH_DEFAULT;
1914 if (ix86_fpmath_string != 0)
1916 if (! strcmp (ix86_fpmath_string, "387"))
1917 ix86_fpmath = FPMATH_387;
1918 else if (! strcmp (ix86_fpmath_string, "sse"))
1922 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1923 ix86_fpmath = FPMATH_387;
1926 ix86_fpmath = FPMATH_SSE;
1928 else if (! strcmp (ix86_fpmath_string, "387,sse")
1929 || ! strcmp (ix86_fpmath_string, "sse,387"))
1933 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1934 ix86_fpmath = FPMATH_387;
1936 else if (!TARGET_80387)
1938 warning (0, "387 instruction set disabled, using SSE arithmetics");
1939 ix86_fpmath = FPMATH_SSE;
1942 ix86_fpmath = FPMATH_SSE | FPMATH_387;
1945 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
1948 /* If the i387 is disabled, then do not return values in it. */
1950 target_flags &= ~MASK_FLOAT_RETURNS;
1952 if ((x86_accumulate_outgoing_args & TUNEMASK)
1953 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1955 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1957 /* ??? Unwind info is not correct around the CFG unless either a frame
1958 pointer is present or M_A_O_A is set. Fixing this requires rewriting
1959 unwind info generation to be aware of the CFG and propagating states
1961 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
1962 || flag_exceptions || flag_non_call_exceptions)
1963 && flag_omit_frame_pointer
1964 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
1966 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1967 warning (0, "unwind tables currently require either a frame pointer "
1968 "or -maccumulate-outgoing-args for correctness");
1969 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1972 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1975 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
1976 p = strchr (internal_label_prefix, 'X');
1977 internal_label_prefix_len = p - internal_label_prefix;
1981 /* When scheduling description is not available, disable scheduler pass
1982 so it won't slow down the compilation and make x87 code slower. */
1983 if (!TARGET_SCHEDULE)
1984 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
1987 /* switch to the appropriate section for output of DECL.
1988 DECL is either a `VAR_DECL' node or a constant of some sort.
1989 RELOC indicates whether forming the initial value of DECL requires
1990 link-time relocations. */
1993 x86_64_elf_select_section (tree decl, int reloc,
1994 unsigned HOST_WIDE_INT align)
1996 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1997 && ix86_in_large_data_p (decl))
1999 const char *sname = NULL;
2000 unsigned int flags = SECTION_WRITE;
2001 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2006 case SECCAT_DATA_REL:
2007 sname = ".ldata.rel";
2009 case SECCAT_DATA_REL_LOCAL:
2010 sname = ".ldata.rel.local";
2012 case SECCAT_DATA_REL_RO:
2013 sname = ".ldata.rel.ro";
2015 case SECCAT_DATA_REL_RO_LOCAL:
2016 sname = ".ldata.rel.ro.local";
2020 flags |= SECTION_BSS;
2023 case SECCAT_RODATA_MERGE_STR:
2024 case SECCAT_RODATA_MERGE_STR_INIT:
2025 case SECCAT_RODATA_MERGE_CONST:
2029 case SECCAT_SRODATA:
2036 /* We don't split these for medium model. Place them into
2037 default sections and hope for best. */
2042 /* We might get called with string constants, but get_named_section
2043 doesn't like them as they are not DECLs. Also, we need to set
2044 flags in that case. */
2046 return get_section (sname, flags, NULL);
2047 return get_named_section (decl, sname, reloc);
2050 return default_elf_select_section (decl, reloc, align);
2053 /* Build up a unique section name, expressed as a
2054 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2055 RELOC indicates whether the initial value of EXP requires
2056 link-time relocations. */
2059 x86_64_elf_unique_section (tree decl, int reloc)
2061 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2062 && ix86_in_large_data_p (decl))
2064 const char *prefix = NULL;
2065 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2066 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2068 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2071 case SECCAT_DATA_REL:
2072 case SECCAT_DATA_REL_LOCAL:
2073 case SECCAT_DATA_REL_RO:
2074 case SECCAT_DATA_REL_RO_LOCAL:
2075 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2078 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2081 case SECCAT_RODATA_MERGE_STR:
2082 case SECCAT_RODATA_MERGE_STR_INIT:
2083 case SECCAT_RODATA_MERGE_CONST:
2084 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2086 case SECCAT_SRODATA:
2093 /* We don't split these for medium model. Place them into
2094 default sections and hope for best. */
2102 plen = strlen (prefix);
2104 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2105 name = targetm.strip_name_encoding (name);
2106 nlen = strlen (name);
2108 string = alloca (nlen + plen + 1);
2109 memcpy (string, prefix, plen);
2110 memcpy (string + plen, name, nlen + 1);
2112 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2116 default_unique_section (decl, reloc);
2119 #ifdef COMMON_ASM_OP
2120 /* This says how to output assembler code to declare an
2121 uninitialized external linkage data object.
2123 For medium model x86-64 we need to use .largecomm opcode for
2126 x86_elf_aligned_common (FILE *file,
2127 const char *name, unsigned HOST_WIDE_INT size,
2130 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2131 && size > (unsigned int)ix86_section_threshold)
2132 fprintf (file, ".largecomm\t");
2134 fprintf (file, "%s", COMMON_ASM_OP);
2135 assemble_name (file, name);
2136 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2137 size, align / BITS_PER_UNIT);
2140 /* Utility function for targets to use in implementing
2141 ASM_OUTPUT_ALIGNED_BSS. */
2144 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2145 const char *name, unsigned HOST_WIDE_INT size,
2148 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2149 && size > (unsigned int)ix86_section_threshold)
2150 switch_to_section (get_named_section (decl, ".lbss", 0));
2152 switch_to_section (bss_section);
2153 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2154 #ifdef ASM_DECLARE_OBJECT_NAME
2155 last_assemble_variable_decl = decl;
2156 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2158 /* Standard thing is just output label for the object. */
2159 ASM_OUTPUT_LABEL (file, name);
2160 #endif /* ASM_DECLARE_OBJECT_NAME */
2161 ASM_OUTPUT_SKIP (file, size ? size : 1);
2166 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2168 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2169 make the problem with not enough registers even worse. */
2170 #ifdef INSN_SCHEDULING
2172 flag_schedule_insns = 0;
2176 /* The Darwin libraries never set errno, so we might as well
2177 avoid calling them when that's the only reason we would. */
2178 flag_errno_math = 0;
2180 /* The default values of these switches depend on the TARGET_64BIT
2181 that is not known at this moment. Mark these values with 2 and
2182 let user the to override these. In case there is no command line option
2183 specifying them, we will set the defaults in override_options. */
2185 flag_omit_frame_pointer = 2;
2186 flag_pcc_struct_return = 2;
2187 flag_asynchronous_unwind_tables = 2;
2188 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2189 SUBTARGET_OPTIMIZATION_OPTIONS;
2193 /* Table of valid machine attributes. */
2194 const struct attribute_spec ix86_attribute_table[] =
2196 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2197 /* Stdcall attribute says callee is responsible for popping arguments
2198 if they are not variable. */
2199 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2200 /* Fastcall attribute says callee is responsible for popping arguments
2201 if they are not variable. */
2202 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2203 /* Cdecl attribute says the callee is a normal C declaration */
2204 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2205 /* Regparm attribute specifies how many integer arguments are to be
2206 passed in registers. */
2207 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
2208 /* Sseregparm attribute says we are using x86_64 calling conventions
2209 for FP arguments. */
2210 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2211 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2212 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2213 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2214 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
2216 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2217 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2218 #ifdef SUBTARGET_ATTRIBUTE_TABLE
2219 SUBTARGET_ATTRIBUTE_TABLE,
2221 { NULL, 0, 0, false, false, false, NULL }
2224 /* Decide whether we can make a sibling call to a function. DECL is the
2225 declaration of the function being targeted by the call and EXP is the
2226 CALL_EXPR representing the call. */
2229 ix86_function_ok_for_sibcall (tree decl, tree exp)
2234 /* If we are generating position-independent code, we cannot sibcall
2235 optimize any indirect call, or a direct call to a global function,
2236 as the PLT requires %ebx be live. */
2237 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2244 func = TREE_TYPE (TREE_OPERAND (exp, 0));
2245 if (POINTER_TYPE_P (func))
2246 func = TREE_TYPE (func);
2249 /* Check that the return value locations are the same. Like
2250 if we are returning floats on the 80387 register stack, we cannot
2251 make a sibcall from a function that doesn't return a float to a
2252 function that does or, conversely, from a function that does return
2253 a float to a function that doesn't; the necessary stack adjustment
2254 would not be executed. This is also the place we notice
2255 differences in the return value ABI. Note that it is ok for one
2256 of the functions to have void return type as long as the return
2257 value of the other is passed in a register. */
2258 a = ix86_function_value (TREE_TYPE (exp), func, false);
2259 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2261 if (STACK_REG_P (a) || STACK_REG_P (b))
2263 if (!rtx_equal_p (a, b))
2266 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2268 else if (!rtx_equal_p (a, b))
2271 /* If this call is indirect, we'll need to be able to use a call-clobbered
2272 register for the address of the target function. Make sure that all
2273 such registers are not used for passing parameters. */
2274 if (!decl && !TARGET_64BIT)
2278 /* We're looking at the CALL_EXPR, we need the type of the function. */
2279 type = TREE_OPERAND (exp, 0); /* pointer expression */
2280 type = TREE_TYPE (type); /* pointer type */
2281 type = TREE_TYPE (type); /* function type */
2283 if (ix86_function_regparm (type, NULL) >= 3)
2285 /* ??? Need to count the actual number of registers to be used,
2286 not the possible number of registers. Fix later. */
2291 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2292 /* Dllimport'd functions are also called indirectly. */
2293 if (decl && DECL_DLLIMPORT_P (decl)
2294 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2298 /* If we forced aligned the stack, then sibcalling would unalign the
2299 stack, which may break the called function. */
2300 if (cfun->machine->force_align_arg_pointer)
2303 /* Otherwise okay. That also includes certain types of indirect calls. */
2307 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2308 calling convention attributes;
2309 arguments as in struct attribute_spec.handler. */
2312 ix86_handle_cconv_attribute (tree *node, tree name,
2314 int flags ATTRIBUTE_UNUSED,
2317 if (TREE_CODE (*node) != FUNCTION_TYPE
2318 && TREE_CODE (*node) != METHOD_TYPE
2319 && TREE_CODE (*node) != FIELD_DECL
2320 && TREE_CODE (*node) != TYPE_DECL)
2322 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2323 IDENTIFIER_POINTER (name));
2324 *no_add_attrs = true;
2328 /* Can combine regparm with all attributes but fastcall. */
2329 if (is_attribute_p ("regparm", name))
2333 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2335 error ("fastcall and regparm attributes are not compatible");
2338 cst = TREE_VALUE (args);
2339 if (TREE_CODE (cst) != INTEGER_CST)
2341 warning (OPT_Wattributes,
2342 "%qs attribute requires an integer constant argument",
2343 IDENTIFIER_POINTER (name));
2344 *no_add_attrs = true;
2346 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2348 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2349 IDENTIFIER_POINTER (name), REGPARM_MAX);
2350 *no_add_attrs = true;
2358 warning (OPT_Wattributes, "%qs attribute ignored",
2359 IDENTIFIER_POINTER (name));
2360 *no_add_attrs = true;
2364 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2365 if (is_attribute_p ("fastcall", name))
2367 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2369 error ("fastcall and cdecl attributes are not compatible");
2371 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2373 error ("fastcall and stdcall attributes are not compatible");
2375 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2377 error ("fastcall and regparm attributes are not compatible");
2381 /* Can combine stdcall with fastcall (redundant), regparm and
2383 else if (is_attribute_p ("stdcall", name))
2385 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2387 error ("stdcall and cdecl attributes are not compatible");
2389 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2391 error ("stdcall and fastcall attributes are not compatible");
2395 /* Can combine cdecl with regparm and sseregparm. */
2396 else if (is_attribute_p ("cdecl", name))
2398 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2400 error ("stdcall and cdecl attributes are not compatible");
2402 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2404 error ("fastcall and cdecl attributes are not compatible");
2408 /* Can combine sseregparm with all attributes. */
2413 /* Return 0 if the attributes for two types are incompatible, 1 if they
2414 are compatible, and 2 if they are nearly compatible (which causes a
2415 warning to be generated). */
2418 ix86_comp_type_attributes (tree type1, tree type2)
2420 /* Check for mismatch of non-default calling convention. */
2421 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2423 if (TREE_CODE (type1) != FUNCTION_TYPE)
2426 /* Check for mismatched fastcall/regparm types. */
2427 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2428 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2429 || (ix86_function_regparm (type1, NULL)
2430 != ix86_function_regparm (type2, NULL)))
2433 /* Check for mismatched sseregparm types. */
2434 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2435 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2438 /* Check for mismatched return types (cdecl vs stdcall). */
2439 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2440 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2446 /* Return the regparm value for a function with the indicated TYPE and DECL.
2447 DECL may be NULL when calling function indirectly
2448 or considering a libcall. */
2451 ix86_function_regparm (tree type, tree decl)
2454 int regparm = ix86_regparm;
2455 bool user_convention = false;
2459 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2462 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2463 user_convention = true;
2466 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2469 user_convention = true;
2472 /* Use register calling convention for local functions when possible. */
2473 if (!TARGET_64BIT && !user_convention && decl
2474 && flag_unit_at_a_time && !profile_flag)
2476 struct cgraph_local_info *i = cgraph_local_info (decl);
2479 int local_regparm, globals = 0, regno;
2481 /* Make sure no regparm register is taken by a global register
2483 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2484 if (global_regs[local_regparm])
2486 /* We can't use regparm(3) for nested functions as these use
2487 static chain pointer in third argument. */
2488 if (local_regparm == 3
2489 && decl_function_context (decl)
2490 && !DECL_NO_STATIC_CHAIN (decl))
2492 /* Each global register variable increases register preassure,
2493 so the more global reg vars there are, the smaller regparm
2494 optimization use, unless requested by the user explicitly. */
2495 for (regno = 0; regno < 6; regno++)
2496 if (global_regs[regno])
2499 = globals < local_regparm ? local_regparm - globals : 0;
2501 if (local_regparm > regparm)
2502 regparm = local_regparm;
2509 /* Return 1 or 2, if we can pass up to 8 SFmode (1) and DFmode (2) arguments
2510 in SSE registers for a function with the indicated TYPE and DECL.
2511 DECL may be NULL when calling function indirectly
2512 or considering a libcall. Otherwise return 0. */
2515 ix86_function_sseregparm (tree type, tree decl)
2517 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2518 by the sseregparm attribute. */
2519 if (TARGET_SSEREGPARM
2521 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2526 error ("Calling %qD with attribute sseregparm without "
2527 "SSE/SSE2 enabled", decl);
2529 error ("Calling %qT with attribute sseregparm without "
2530 "SSE/SSE2 enabled", type);
2537 /* For local functions, pass SFmode (and DFmode for SSE2) arguments
2538 in SSE registers even for 32-bit mode and not just 3, but up to
2539 8 SSE arguments in registers. */
2540 if (!TARGET_64BIT && decl
2541 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2543 struct cgraph_local_info *i = cgraph_local_info (decl);
2545 return TARGET_SSE2 ? 2 : 1;
2551 /* Return true if EAX is live at the start of the function. Used by
2552 ix86_expand_prologue to determine if we need special help before
2553 calling allocate_stack_worker. */
2556 ix86_eax_live_at_start_p (void)
2558 /* Cheat. Don't bother working forward from ix86_function_regparm
2559 to the function type to whether an actual argument is located in
2560 eax. Instead just look at cfg info, which is still close enough
2561 to correct at this point. This gives false positives for broken
2562 functions that might use uninitialized data that happens to be
2563 allocated in eax, but who cares? */
2564 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2567 /* Value is the number of bytes of arguments automatically
2568 popped when returning from a subroutine call.
2569 FUNDECL is the declaration node of the function (as a tree),
2570 FUNTYPE is the data type of the function (as a tree),
2571 or for a library call it is an identifier node for the subroutine name.
2572 SIZE is the number of bytes of arguments passed on the stack.
2574 On the 80386, the RTD insn may be used to pop them if the number
2575 of args is fixed, but if the number is variable then the caller
2576 must pop them all. RTD can't be used for library calls now
2577 because the library is compiled with the Unix compiler.
2578 Use of RTD is a selectable option, since it is incompatible with
2579 standard Unix calling sequences. If the option is not selected,
2580 the caller must always pop the args.
2582 The attribute stdcall is equivalent to RTD on a per module basis. */
2585 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2587 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2589 /* Cdecl functions override -mrtd, and never pop the stack. */
2590 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2592 /* Stdcall and fastcall functions will pop the stack if not
2594 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2595 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2599 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2600 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2601 == void_type_node)))
2605 /* Lose any fake structure return argument if it is passed on the stack. */
2606 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2608 && !KEEP_AGGREGATE_RETURN_POINTER)
2610 int nregs = ix86_function_regparm (funtype, fundecl);
2613 return GET_MODE_SIZE (Pmode);
2619 /* Argument support functions. */
2621 /* Return true when register may be used to pass function parameters. */
2623 ix86_function_arg_regno_p (int regno)
2627 return (regno < REGPARM_MAX
2628 || (TARGET_MMX && MMX_REGNO_P (regno)
2629 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2630 || (TARGET_SSE && SSE_REGNO_P (regno)
2631 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2633 if (TARGET_SSE && SSE_REGNO_P (regno)
2634 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2636 /* RAX is used as hidden argument to va_arg functions. */
2639 for (i = 0; i < REGPARM_MAX; i++)
2640 if (regno == x86_64_int_parameter_registers[i])
2645 /* Return if we do not know how to pass TYPE solely in registers. */
2648 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2650 if (must_pass_in_stack_var_size_or_pad (mode, type))
2653 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2654 The layout_type routine is crafty and tries to trick us into passing
2655 currently unsupported vector types on the stack by using TImode. */
2656 return (!TARGET_64BIT && mode == TImode
2657 && type && TREE_CODE (type) != VECTOR_TYPE);
2660 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2661 for a call to a function whose data type is FNTYPE.
2662 For a library call, FNTYPE is 0. */
2665 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2666 tree fntype, /* tree ptr for function decl */
2667 rtx libname, /* SYMBOL_REF of library name or 0 */
2670 static CUMULATIVE_ARGS zero_cum;
2671 tree param, next_param;
2673 if (TARGET_DEBUG_ARG)
2675 fprintf (stderr, "\ninit_cumulative_args (");
2677 fprintf (stderr, "fntype code = %s, ret code = %s",
2678 tree_code_name[(int) TREE_CODE (fntype)],
2679 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
2681 fprintf (stderr, "no fntype");
2684 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
2689 /* Set up the number of registers to use for passing arguments. */
2690 cum->nregs = ix86_regparm;
2692 cum->sse_nregs = SSE_REGPARM_MAX;
2694 cum->mmx_nregs = MMX_REGPARM_MAX;
2695 cum->warn_sse = true;
2696 cum->warn_mmx = true;
2697 cum->maybe_vaarg = false;
2699 /* Use ecx and edx registers if function has fastcall attribute,
2700 else look for regparm information. */
2701 if (fntype && !TARGET_64BIT)
2703 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
2709 cum->nregs = ix86_function_regparm (fntype, fndecl);
2712 /* Set up the number of SSE registers used for passing SFmode
2713 and DFmode arguments. Warn for mismatching ABI. */
2714 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
2716 /* Determine if this function has variable arguments. This is
2717 indicated by the last argument being 'void_type_mode' if there
2718 are no variable arguments. If there are variable arguments, then
2719 we won't pass anything in registers in 32-bit mode. */
2721 if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
2723 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2724 param != 0; param = next_param)
2726 next_param = TREE_CHAIN (param);
2727 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
2737 cum->float_in_sse = 0;
2739 cum->maybe_vaarg = true;
2743 if ((!fntype && !libname)
2744 || (fntype && !TYPE_ARG_TYPES (fntype)))
2745 cum->maybe_vaarg = true;
2747 if (TARGET_DEBUG_ARG)
2748 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
2753 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
2754 But in the case of vector types, it is some vector mode.
2756 When we have only some of our vector isa extensions enabled, then there
2757 are some modes for which vector_mode_supported_p is false. For these
2758 modes, the generic vector support in gcc will choose some non-vector mode
2759 in order to implement the type. By computing the natural mode, we'll
2760 select the proper ABI location for the operand and not depend on whatever
2761 the middle-end decides to do with these vector types. */
2763 static enum machine_mode
2764 type_natural_mode (tree type)
2766 enum machine_mode mode = TYPE_MODE (type);
2768 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
2770 HOST_WIDE_INT size = int_size_in_bytes (type);
2771 if ((size == 8 || size == 16)
2772 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
2773 && TYPE_VECTOR_SUBPARTS (type) > 1)
2775 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
2777 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
2778 mode = MIN_MODE_VECTOR_FLOAT;
2780 mode = MIN_MODE_VECTOR_INT;
2782 /* Get the mode which has this inner mode and number of units. */
2783 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
2784 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
2785 && GET_MODE_INNER (mode) == innermode)
2795 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
2796 this may not agree with the mode that the type system has chosen for the
2797 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
2798 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
2801 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
2806 if (orig_mode != BLKmode)
2807 tmp = gen_rtx_REG (orig_mode, regno);
2810 tmp = gen_rtx_REG (mode, regno);
2811 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
2812 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
2818 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2819 of this code is to classify each 8bytes of incoming argument by the register
2820 class and assign registers accordingly. */
2822 /* Return the union class of CLASS1 and CLASS2.
2823 See the x86-64 PS ABI for details. */
2825 static enum x86_64_reg_class
2826 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
2828 /* Rule #1: If both classes are equal, this is the resulting class. */
2829 if (class1 == class2)
2832 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2834 if (class1 == X86_64_NO_CLASS)
2836 if (class2 == X86_64_NO_CLASS)
2839 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2840 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
2841 return X86_64_MEMORY_CLASS;
2843 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2844 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
2845 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
2846 return X86_64_INTEGERSI_CLASS;
2847 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
2848 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
2849 return X86_64_INTEGER_CLASS;
2851 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
2853 if (class1 == X86_64_X87_CLASS
2854 || class1 == X86_64_X87UP_CLASS
2855 || class1 == X86_64_COMPLEX_X87_CLASS
2856 || class2 == X86_64_X87_CLASS
2857 || class2 == X86_64_X87UP_CLASS
2858 || class2 == X86_64_COMPLEX_X87_CLASS)
2859 return X86_64_MEMORY_CLASS;
2861 /* Rule #6: Otherwise class SSE is used. */
2862 return X86_64_SSE_CLASS;
2865 /* Classify the argument of type TYPE and mode MODE.
2866 CLASSES will be filled by the register class used to pass each word
2867 of the operand. The number of words is returned. In case the parameter
2868 should be passed in memory, 0 is returned. As a special case for zero
2869 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2871 BIT_OFFSET is used internally for handling records and specifies offset
2872 of the offset in bits modulo 256 to avoid overflow cases.
2874 See the x86-64 PS ABI for details.
2878 classify_argument (enum machine_mode mode, tree type,
2879 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
2881 HOST_WIDE_INT bytes =
2882 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2883 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2885 /* Variable sized entities are always passed/returned in memory. */
2889 if (mode != VOIDmode
2890 && targetm.calls.must_pass_in_stack (mode, type))
2893 if (type && AGGREGATE_TYPE_P (type))
2897 enum x86_64_reg_class subclasses[MAX_CLASSES];
2899 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2903 for (i = 0; i < words; i++)
2904 classes[i] = X86_64_NO_CLASS;
2906 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2907 signalize memory class, so handle it as special case. */
2910 classes[0] = X86_64_NO_CLASS;
2914 /* Classify each field of record and merge classes. */
2915 switch (TREE_CODE (type))
2918 /* For classes first merge in the field of the subclasses. */
2919 if (TYPE_BINFO (type))
2921 tree binfo, base_binfo;
2924 for (binfo = TYPE_BINFO (type), basenum = 0;
2925 BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
2928 int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
2929 tree type = BINFO_TYPE (base_binfo);
2931 num = classify_argument (TYPE_MODE (type),
2933 (offset + bit_offset) % 256);
2936 for (i = 0; i < num; i++)
2938 int pos = (offset + (bit_offset % 64)) / 8 / 8;
2940 merge_classes (subclasses[i], classes[i + pos]);
2944 /* And now merge the fields of structure. */
2945 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2947 if (TREE_CODE (field) == FIELD_DECL)
2951 /* Bitfields are always classified as integer. Handle them
2952 early, since later code would consider them to be
2953 misaligned integers. */
2954 if (DECL_BIT_FIELD (field))
2956 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2957 i < ((int_bit_position (field) + (bit_offset % 64))
2958 + tree_low_cst (DECL_SIZE (field), 0)
2961 merge_classes (X86_64_INTEGER_CLASS,
2966 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2967 TREE_TYPE (field), subclasses,
2968 (int_bit_position (field)
2969 + bit_offset) % 256);
2972 for (i = 0; i < num; i++)
2975 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2977 merge_classes (subclasses[i], classes[i + pos]);
2985 /* Arrays are handled as small records. */
2988 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
2989 TREE_TYPE (type), subclasses, bit_offset);
2993 /* The partial classes are now full classes. */
2994 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
2995 subclasses[0] = X86_64_SSE_CLASS;
2996 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
2997 subclasses[0] = X86_64_INTEGER_CLASS;
2999 for (i = 0; i < words; i++)
3000 classes[i] = subclasses[i % num];
3005 case QUAL_UNION_TYPE:
3006 /* Unions are similar to RECORD_TYPE but offset is always 0.
3009 /* Unions are not derived. */
3010 gcc_assert (!TYPE_BINFO (type)
3011 || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type)));
3012 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3014 if (TREE_CODE (field) == FIELD_DECL)
3017 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3018 TREE_TYPE (field), subclasses,
3022 for (i = 0; i < num; i++)
3023 classes[i] = merge_classes (subclasses[i], classes[i]);
3032 /* Final merger cleanup. */
3033 for (i = 0; i < words; i++)
3035 /* If one class is MEMORY, everything should be passed in
3037 if (classes[i] == X86_64_MEMORY_CLASS)
3040 /* The X86_64_SSEUP_CLASS should be always preceded by
3041 X86_64_SSE_CLASS. */
3042 if (classes[i] == X86_64_SSEUP_CLASS
3043 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3044 classes[i] = X86_64_SSE_CLASS;
3046 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3047 if (classes[i] == X86_64_X87UP_CLASS
3048 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3049 classes[i] = X86_64_SSE_CLASS;
3054 /* Compute alignment needed. We align all types to natural boundaries with
3055 exception of XFmode that is aligned to 64bits. */
3056 if (mode != VOIDmode && mode != BLKmode)
3058 int mode_alignment = GET_MODE_BITSIZE (mode);
3061 mode_alignment = 128;
3062 else if (mode == XCmode)
3063 mode_alignment = 256;
3064 if (COMPLEX_MODE_P (mode))
3065 mode_alignment /= 2;
3066 /* Misaligned fields are always returned in memory. */
3067 if (bit_offset % mode_alignment)
3071 /* for V1xx modes, just use the base mode */
3072 if (VECTOR_MODE_P (mode)
3073 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3074 mode = GET_MODE_INNER (mode);
3076 /* Classification of atomic types. */
3081 classes[0] = X86_64_SSE_CLASS;
3084 classes[0] = X86_64_SSE_CLASS;
3085 classes[1] = X86_64_SSEUP_CLASS;
3094 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3095 classes[0] = X86_64_INTEGERSI_CLASS;
3097 classes[0] = X86_64_INTEGER_CLASS;
3101 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3106 if (!(bit_offset % 64))
3107 classes[0] = X86_64_SSESF_CLASS;
3109 classes[0] = X86_64_SSE_CLASS;
3112 classes[0] = X86_64_SSEDF_CLASS;
3115 classes[0] = X86_64_X87_CLASS;
3116 classes[1] = X86_64_X87UP_CLASS;
3119 classes[0] = X86_64_SSE_CLASS;
3120 classes[1] = X86_64_SSEUP_CLASS;
3123 classes[0] = X86_64_SSE_CLASS;
3126 classes[0] = X86_64_SSEDF_CLASS;
3127 classes[1] = X86_64_SSEDF_CLASS;
3130 classes[0] = X86_64_COMPLEX_X87_CLASS;
3133 /* This modes is larger than 16 bytes. */
3141 classes[0] = X86_64_SSE_CLASS;
3142 classes[1] = X86_64_SSEUP_CLASS;
3148 classes[0] = X86_64_SSE_CLASS;
3154 gcc_assert (VECTOR_MODE_P (mode));
3159 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3161 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3162 classes[0] = X86_64_INTEGERSI_CLASS;
3164 classes[0] = X86_64_INTEGER_CLASS;
3165 classes[1] = X86_64_INTEGER_CLASS;
3166 return 1 + (bytes > 8);
3170 /* Examine the argument and return set number of register required in each
3171 class. Return 0 iff parameter should be passed in memory. */
3173 examine_argument (enum machine_mode mode, tree type, int in_return,
3174 int *int_nregs, int *sse_nregs)
3176 enum x86_64_reg_class class[MAX_CLASSES];
3177 int n = classify_argument (mode, type, class, 0);
3183 for (n--; n >= 0; n--)
3186 case X86_64_INTEGER_CLASS:
3187 case X86_64_INTEGERSI_CLASS:
3190 case X86_64_SSE_CLASS:
3191 case X86_64_SSESF_CLASS:
3192 case X86_64_SSEDF_CLASS:
3195 case X86_64_NO_CLASS:
3196 case X86_64_SSEUP_CLASS:
3198 case X86_64_X87_CLASS:
3199 case X86_64_X87UP_CLASS:
3203 case X86_64_COMPLEX_X87_CLASS:
3204 return in_return ? 2 : 0;
3205 case X86_64_MEMORY_CLASS:
3211 /* Construct container for the argument used by GCC interface. See
3212 FUNCTION_ARG for the detailed description. */
3215 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3216 tree type, int in_return, int nintregs, int nsseregs,
3217 const int *intreg, int sse_regno)
3219 enum machine_mode tmpmode;
3221 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3222 enum x86_64_reg_class class[MAX_CLASSES];
3226 int needed_sseregs, needed_intregs;
3227 rtx exp[MAX_CLASSES];
3230 n = classify_argument (mode, type, class, 0);
3231 if (TARGET_DEBUG_ARG)
3234 fprintf (stderr, "Memory class\n");
3237 fprintf (stderr, "Classes:");
3238 for (i = 0; i < n; i++)
3240 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
3242 fprintf (stderr, "\n");
3247 if (!examine_argument (mode, type, in_return, &needed_intregs,
3250 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3253 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3254 some less clueful developer tries to use floating-point anyway. */
3255 if (needed_sseregs && !TARGET_SSE)
3257 static bool issued_error;
3260 issued_error = true;
3262 error ("SSE register return with SSE disabled");
3264 error ("SSE register argument with SSE disabled");
3269 /* First construct simple cases. Avoid SCmode, since we want to use
3270 single register to pass this type. */
3271 if (n == 1 && mode != SCmode)
3274 case X86_64_INTEGER_CLASS:
3275 case X86_64_INTEGERSI_CLASS:
3276 return gen_rtx_REG (mode, intreg[0]);
3277 case X86_64_SSE_CLASS:
3278 case X86_64_SSESF_CLASS:
3279 case X86_64_SSEDF_CLASS:
3280 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3281 case X86_64_X87_CLASS:
3282 case X86_64_COMPLEX_X87_CLASS:
3283 return gen_rtx_REG (mode, FIRST_STACK_REG);
3284 case X86_64_NO_CLASS:
3285 /* Zero sized array, struct or class. */
3290 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
3292 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3294 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
3295 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3296 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
3297 && class[1] == X86_64_INTEGER_CLASS
3298 && (mode == CDImode || mode == TImode || mode == TFmode)
3299 && intreg[0] + 1 == intreg[1])
3300 return gen_rtx_REG (mode, intreg[0]);
3302 /* Otherwise figure out the entries of the PARALLEL. */
3303 for (i = 0; i < n; i++)
3307 case X86_64_NO_CLASS:
3309 case X86_64_INTEGER_CLASS:
3310 case X86_64_INTEGERSI_CLASS:
3311 /* Merge TImodes on aligned occasions here too. */
3312 if (i * 8 + 8 > bytes)
3313 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3314 else if (class[i] == X86_64_INTEGERSI_CLASS)
3318 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3319 if (tmpmode == BLKmode)
3321 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3322 gen_rtx_REG (tmpmode, *intreg),
3326 case X86_64_SSESF_CLASS:
3327 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3328 gen_rtx_REG (SFmode,
3329 SSE_REGNO (sse_regno)),
3333 case X86_64_SSEDF_CLASS:
3334 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3335 gen_rtx_REG (DFmode,
3336 SSE_REGNO (sse_regno)),
3340 case X86_64_SSE_CLASS:
3341 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3345 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3346 gen_rtx_REG (tmpmode,
3347 SSE_REGNO (sse_regno)),
3349 if (tmpmode == TImode)
3358 /* Empty aligned struct, union or class. */
3362 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3363 for (i = 0; i < nexps; i++)
3364 XVECEXP (ret, 0, i) = exp [i];
3368 /* Update the data in CUM to advance over an argument
3369 of mode MODE and data type TYPE.
3370 (TYPE is null for libcalls where that information may not be available.) */
3373 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3374 tree type, int named)
3377 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3378 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3381 mode = type_natural_mode (type);
3383 if (TARGET_DEBUG_ARG)
3384 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3385 "mode=%s, named=%d)\n\n",
3386 words, cum->words, cum->nregs, cum->sse_nregs,
3387 GET_MODE_NAME (mode), named);
3391 int int_nregs, sse_nregs;
3392 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3393 cum->words += words;
3394 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3396 cum->nregs -= int_nregs;
3397 cum->sse_nregs -= sse_nregs;
3398 cum->regno += int_nregs;
3399 cum->sse_regno += sse_nregs;
3402 cum->words += words;
3420 cum->words += words;
3421 cum->nregs -= words;
3422 cum->regno += words;
3424 if (cum->nregs <= 0)
3432 if (cum->float_in_sse < 2)
3435 if (cum->float_in_sse < 1)
3446 if (!type || !AGGREGATE_TYPE_P (type))
3448 cum->sse_words += words;
3449 cum->sse_nregs -= 1;
3450 cum->sse_regno += 1;
3451 if (cum->sse_nregs <= 0)
3463 if (!type || !AGGREGATE_TYPE_P (type))
3465 cum->mmx_words += words;
3466 cum->mmx_nregs -= 1;
3467 cum->mmx_regno += 1;
3468 if (cum->mmx_nregs <= 0)
3479 /* Define where to put the arguments to a function.
3480 Value is zero to push the argument on the stack,
3481 or a hard register in which to store the argument.
3483 MODE is the argument's machine mode.
3484 TYPE is the data type of the argument (as a tree).
3485 This is null for libcalls where that information may
3487 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3488 the preceding args and about the function being called.
3489 NAMED is nonzero if this argument is a named parameter
3490 (otherwise it is an extra parameter matching an ellipsis). */
3493 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3494 tree type, int named)
3496 enum machine_mode mode = orig_mode;
3499 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3500 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3501 static bool warnedsse, warnedmmx;
3503 /* To simplify the code below, represent vector types with a vector mode
3504 even if MMX/SSE are not active. */
3505 if (type && TREE_CODE (type) == VECTOR_TYPE)
3506 mode = type_natural_mode (type);
3508 /* Handle a hidden AL argument containing number of registers for varargs
3509 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3511 if (mode == VOIDmode)
3514 return GEN_INT (cum->maybe_vaarg
3515 ? (cum->sse_nregs < 0
3523 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3525 &x86_64_int_parameter_registers [cum->regno],
3530 /* For now, pass fp/complex values on the stack. */
3542 if (words <= cum->nregs)
3544 int regno = cum->regno;
3546 /* Fastcall allocates the first two DWORD (SImode) or
3547 smaller arguments to ECX and EDX. */
3550 if (mode == BLKmode || mode == DImode)
3553 /* ECX not EAX is the first allocated register. */
3557 ret = gen_rtx_REG (mode, regno);
3561 if (cum->float_in_sse < 2)
3564 if (cum->float_in_sse < 1)
3574 if (!type || !AGGREGATE_TYPE_P (type))
3576 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3579 warning (0, "SSE vector argument without SSE enabled "
3583 ret = gen_reg_or_parallel (mode, orig_mode,
3584 cum->sse_regno + FIRST_SSE_REG);
3591 if (!type || !AGGREGATE_TYPE_P (type))
3593 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3596 warning (0, "MMX vector argument without MMX enabled "
3600 ret = gen_reg_or_parallel (mode, orig_mode,
3601 cum->mmx_regno + FIRST_MMX_REG);
3606 if (TARGET_DEBUG_ARG)
3609 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3610 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
3613 print_simple_rtl (stderr, ret);
3615 fprintf (stderr, ", stack");
3617 fprintf (stderr, " )\n");
3623 /* A C expression that indicates when an argument must be passed by
3624 reference. If nonzero for an argument, a copy of that argument is
3625 made in memory and a pointer to the argument is passed instead of
3626 the argument itself. The pointer is passed in whatever way is
3627 appropriate for passing a pointer to that type. */
3630 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3631 enum machine_mode mode ATTRIBUTE_UNUSED,
3632 tree type, bool named ATTRIBUTE_UNUSED)
3637 if (type && int_size_in_bytes (type) == -1)
3639 if (TARGET_DEBUG_ARG)
3640 fprintf (stderr, "function_arg_pass_by_reference\n");
3647 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
3648 ABI. Only called if TARGET_SSE. */
3650 contains_128bit_aligned_vector_p (tree type)
3652 enum machine_mode mode = TYPE_MODE (type);
3653 if (SSE_REG_MODE_P (mode)
3654 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
3656 if (TYPE_ALIGN (type) < 128)
3659 if (AGGREGATE_TYPE_P (type))
3661 /* Walk the aggregates recursively. */
3662 switch (TREE_CODE (type))
3666 case QUAL_UNION_TYPE:
3670 if (TYPE_BINFO (type))
3672 tree binfo, base_binfo;
3675 for (binfo = TYPE_BINFO (type), i = 0;
3676 BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
3677 if (contains_128bit_aligned_vector_p
3678 (BINFO_TYPE (base_binfo)))
3681 /* And now merge the fields of structure. */
3682 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3684 if (TREE_CODE (field) == FIELD_DECL
3685 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
3692 /* Just for use if some languages passes arrays by value. */
3693 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
3704 /* Gives the alignment boundary, in bits, of an argument with the
3705 specified mode and type. */
3708 ix86_function_arg_boundary (enum machine_mode mode, tree type)
3712 align = TYPE_ALIGN (type);
3714 align = GET_MODE_ALIGNMENT (mode);
3715 if (align < PARM_BOUNDARY)
3716 align = PARM_BOUNDARY;
3719 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
3720 make an exception for SSE modes since these require 128bit
3723 The handling here differs from field_alignment. ICC aligns MMX
3724 arguments to 4 byte boundaries, while structure fields are aligned
3725 to 8 byte boundaries. */
3727 align = PARM_BOUNDARY;
3730 if (!SSE_REG_MODE_P (mode))
3731 align = PARM_BOUNDARY;
3735 if (!contains_128bit_aligned_vector_p (type))
3736 align = PARM_BOUNDARY;
3744 /* Return true if N is a possible register number of function value. */
3746 ix86_function_value_regno_p (int regno)
3749 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
3750 || (regno == FIRST_SSE_REG && TARGET_SSE))
3754 && (regno == FIRST_MMX_REG && TARGET_MMX))
3760 /* Define how to find the value returned by a function.
3761 VALTYPE is the data type of the value (as a tree).
3762 If the precise function being called is known, FUNC is its FUNCTION_DECL;
3763 otherwise, FUNC is 0. */
3765 ix86_function_value (tree valtype, tree fntype_or_decl,
3766 bool outgoing ATTRIBUTE_UNUSED)
3768 enum machine_mode natmode = type_natural_mode (valtype);
3772 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
3773 1, REGPARM_MAX, SSE_REGPARM_MAX,
3774 x86_64_int_return_registers, 0);
3775 /* For zero sized structures, construct_container return NULL, but we
3776 need to keep rest of compiler happy by returning meaningful value. */
3778 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
3783 tree fn = NULL_TREE, fntype;
3785 && DECL_P (fntype_or_decl))
3786 fn = fntype_or_decl;
3787 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
3788 return gen_rtx_REG (TYPE_MODE (valtype),
3789 ix86_value_regno (natmode, fn, fntype));
3793 /* Return true iff type is returned in memory. */
3795 ix86_return_in_memory (tree type)
3797 int needed_intregs, needed_sseregs, size;
3798 enum machine_mode mode = type_natural_mode (type);
3801 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
3803 if (mode == BLKmode)
3806 size = int_size_in_bytes (type);
3808 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
3811 if (VECTOR_MODE_P (mode) || mode == TImode)
3813 /* User-created vectors small enough to fit in EAX. */
3817 /* MMX/3dNow values are returned in MM0,
3818 except when it doesn't exits. */
3820 return (TARGET_MMX ? 0 : 1);
3822 /* SSE values are returned in XMM0, except when it doesn't exist. */
3824 return (TARGET_SSE ? 0 : 1);
3838 /* When returning SSE vector types, we have a choice of either
3839 (1) being abi incompatible with a -march switch, or
3840 (2) generating an error.
3841 Given no good solution, I think the safest thing is one warning.
3842 The user won't be able to use -Werror, but....
3844 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3845 called in response to actually generating a caller or callee that
3846 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3847 via aggregate_value_p for general type probing from tree-ssa. */
3850 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
3852 static bool warnedsse, warnedmmx;
3856 /* Look at the return type of the function, not the function type. */
3857 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
3859 if (!TARGET_SSE && !warnedsse)
3862 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3865 warning (0, "SSE vector return without SSE enabled "
3870 if (!TARGET_MMX && !warnedmmx)
3872 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
3875 warning (0, "MMX vector return without MMX enabled "
3884 /* Define how to find the value returned by a library function
3885 assuming the value has mode MODE. */
3887 ix86_libcall_value (enum machine_mode mode)
3901 return gen_rtx_REG (mode, FIRST_SSE_REG);
3904 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
3908 return gen_rtx_REG (mode, 0);
3912 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
3915 /* Given a mode, return the register to use for a return value. */
3918 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
3920 gcc_assert (!TARGET_64BIT);
3922 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
3923 we prevent this case when mmx is not available. */
3924 if ((VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8))
3925 return FIRST_MMX_REG;
3927 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3928 we prevent this case when sse is not available. */
3929 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3930 return FIRST_SSE_REG;
3932 /* Decimal floating point values can go in %eax, unlike other float modes. */
3933 if (DECIMAL_FLOAT_MODE_P (mode))
3936 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
3937 if (!SCALAR_FLOAT_MODE_P (mode) || !TARGET_FLOAT_RETURNS_IN_80387)
3940 /* Floating point return values in %st(0), except for local functions when
3941 SSE math is enabled or for functions with sseregparm attribute. */
3942 if ((func || fntype)
3943 && (mode == SFmode || mode == DFmode))
3945 int sse_level = ix86_function_sseregparm (fntype, func);
3946 if ((sse_level >= 1 && mode == SFmode)
3947 || (sse_level == 2 && mode == DFmode))
3948 return FIRST_SSE_REG;
3951 return FIRST_FLOAT_REG;
3954 /* Create the va_list data type. */
3957 ix86_build_builtin_va_list (void)
3959 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3961 /* For i386 we use plain pointer to argument area. */
3963 return build_pointer_type (char_type_node);
3965 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3966 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3968 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
3969 unsigned_type_node);
3970 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
3971 unsigned_type_node);
3972 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3974 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3977 va_list_gpr_counter_field = f_gpr;
3978 va_list_fpr_counter_field = f_fpr;
3980 DECL_FIELD_CONTEXT (f_gpr) = record;
3981 DECL_FIELD_CONTEXT (f_fpr) = record;
3982 DECL_FIELD_CONTEXT (f_ovf) = record;
3983 DECL_FIELD_CONTEXT (f_sav) = record;
3985 TREE_CHAIN (record) = type_decl;
3986 TYPE_NAME (record) = type_decl;
3987 TYPE_FIELDS (record) = f_gpr;
3988 TREE_CHAIN (f_gpr) = f_fpr;
3989 TREE_CHAIN (f_fpr) = f_ovf;
3990 TREE_CHAIN (f_ovf) = f_sav;
3992 layout_type (record);
3994 /* The correct type is an array type of one element. */
3995 return build_array_type (record, build_index_type (size_zero_node));
3998 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4001 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4002 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4005 CUMULATIVE_ARGS next_cum;
4006 rtx save_area = NULL_RTX, mem;
4019 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4022 /* Indicate to allocate space on the stack for varargs save area. */
4023 ix86_save_varrargs_registers = 1;
4025 cfun->stack_alignment_needed = 128;
4027 fntype = TREE_TYPE (current_function_decl);
4028 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
4029 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4030 != void_type_node));
4032 /* For varargs, we do not want to skip the dummy va_dcl argument.
4033 For stdargs, we do want to skip the last named argument. */
4036 function_arg_advance (&next_cum, mode, type, 1);
4039 save_area = frame_pointer_rtx;
4041 set = get_varargs_alias_set ();
4043 for (i = next_cum.regno;
4045 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4048 mem = gen_rtx_MEM (Pmode,
4049 plus_constant (save_area, i * UNITS_PER_WORD));
4050 MEM_NOTRAP_P (mem) = 1;
4051 set_mem_alias_set (mem, set);
4052 emit_move_insn (mem, gen_rtx_REG (Pmode,
4053 x86_64_int_parameter_registers[i]));
4056 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
4058 /* Now emit code to save SSE registers. The AX parameter contains number
4059 of SSE parameter registers used to call this function. We use
4060 sse_prologue_save insn template that produces computed jump across
4061 SSE saves. We need some preparation work to get this working. */
4063 label = gen_label_rtx ();
4064 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4066 /* Compute address to jump to :
4067 label - 5*eax + nnamed_sse_arguments*5 */
4068 tmp_reg = gen_reg_rtx (Pmode);
4069 nsse_reg = gen_reg_rtx (Pmode);
4070 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
4071 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4072 gen_rtx_MULT (Pmode, nsse_reg,
4074 if (next_cum.sse_regno)
4077 gen_rtx_CONST (DImode,
4078 gen_rtx_PLUS (DImode,
4080 GEN_INT (next_cum.sse_regno * 4))));
4082 emit_move_insn (nsse_reg, label_ref);
4083 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4085 /* Compute address of memory block we save into. We always use pointer
4086 pointing 127 bytes after first byte to store - this is needed to keep
4087 instruction size limited by 4 bytes. */
4088 tmp_reg = gen_reg_rtx (Pmode);
4089 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4090 plus_constant (save_area,
4091 8 * REGPARM_MAX + 127)));
4092 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4093 MEM_NOTRAP_P (mem) = 1;
4094 set_mem_alias_set (mem, set);
4095 set_mem_align (mem, BITS_PER_WORD);
4097 /* And finally do the dirty job! */
4098 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4099 GEN_INT (next_cum.sse_regno), label));
4104 /* Implement va_start. */
4107 ix86_va_start (tree valist, rtx nextarg)
4109 HOST_WIDE_INT words, n_gpr, n_fpr;
4110 tree f_gpr, f_fpr, f_ovf, f_sav;
4111 tree gpr, fpr, ovf, sav, t;
4113 /* Only 64bit target needs something special. */
4116 std_expand_builtin_va_start (valist, nextarg);
4120 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4121 f_fpr = TREE_CHAIN (f_gpr);
4122 f_ovf = TREE_CHAIN (f_fpr);
4123 f_sav = TREE_CHAIN (f_ovf);
4125 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4126 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4127 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4128 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4129 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4131 /* Count number of gp and fp argument registers used. */
4132 words = current_function_args_info.words;
4133 n_gpr = current_function_args_info.regno;
4134 n_fpr = current_function_args_info.sse_regno;
4136 if (TARGET_DEBUG_ARG)
4137 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
4138 (int) words, (int) n_gpr, (int) n_fpr);
4140 if (cfun->va_list_gpr_size)
4142 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
4143 build_int_cst (NULL_TREE, n_gpr * 8));
4144 TREE_SIDE_EFFECTS (t) = 1;
4145 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4148 if (cfun->va_list_fpr_size)
4150 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
4151 build_int_cst (NULL_TREE, n_fpr * 16 + 8*REGPARM_MAX));
4152 TREE_SIDE_EFFECTS (t) = 1;
4153 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4156 /* Find the overflow area. */
4157 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4159 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
4160 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
4161 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4162 TREE_SIDE_EFFECTS (t) = 1;
4163 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4165 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
4167 /* Find the register save area.
4168 Prologue of the function save it right above stack frame. */
4169 t = make_tree (TREE_TYPE (sav), frame_pointer_rtx);
4170 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4171 TREE_SIDE_EFFECTS (t) = 1;
4172 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4176 /* Implement va_arg. */
4179 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4181 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
4182 tree f_gpr, f_fpr, f_ovf, f_sav;
4183 tree gpr, fpr, ovf, sav, t;
4185 tree lab_false, lab_over = NULL_TREE;
4190 enum machine_mode nat_mode;
4192 /* Only 64bit target needs something special. */
4194 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4196 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4197 f_fpr = TREE_CHAIN (f_gpr);
4198 f_ovf = TREE_CHAIN (f_fpr);
4199 f_sav = TREE_CHAIN (f_ovf);
4201 valist = build_va_arg_indirect_ref (valist);
4202 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4203 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4204 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4205 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4207 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
4209 type = build_pointer_type (type);
4210 size = int_size_in_bytes (type);
4211 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4213 nat_mode = type_natural_mode (type);
4214 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
4215 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
4217 /* Pull the value out of the saved registers. */
4219 addr = create_tmp_var (ptr_type_node, "addr");
4220 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
4224 int needed_intregs, needed_sseregs;
4226 tree int_addr, sse_addr;
4228 lab_false = create_artificial_label ();
4229 lab_over = create_artificial_label ();
4231 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
4233 need_temp = (!REG_P (container)
4234 && ((needed_intregs && TYPE_ALIGN (type) > 64)
4235 || TYPE_ALIGN (type) > 128));
4237 /* In case we are passing structure, verify that it is consecutive block
4238 on the register save area. If not we need to do moves. */
4239 if (!need_temp && !REG_P (container))
4241 /* Verify that all registers are strictly consecutive */
4242 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
4246 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4248 rtx slot = XVECEXP (container, 0, i);
4249 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
4250 || INTVAL (XEXP (slot, 1)) != i * 16)
4258 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4260 rtx slot = XVECEXP (container, 0, i);
4261 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
4262 || INTVAL (XEXP (slot, 1)) != i * 8)
4274 int_addr = create_tmp_var (ptr_type_node, "int_addr");
4275 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
4276 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
4277 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
4280 /* First ensure that we fit completely in registers. */
4283 t = build_int_cst (TREE_TYPE (gpr),
4284 (REGPARM_MAX - needed_intregs + 1) * 8);
4285 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
4286 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4287 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4288 gimplify_and_add (t, pre_p);
4292 t = build_int_cst (TREE_TYPE (fpr),
4293 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
4295 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
4296 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4297 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4298 gimplify_and_add (t, pre_p);
4301 /* Compute index to start of area used for integer regs. */
4304 /* int_addr = gpr + sav; */
4305 t = fold_convert (ptr_type_node, gpr);
4306 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4307 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
4308 gimplify_and_add (t, pre_p);
4312 /* sse_addr = fpr + sav; */
4313 t = fold_convert (ptr_type_node, fpr);
4314 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4315 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
4316 gimplify_and_add (t, pre_p);
4321 tree temp = create_tmp_var (type, "va_arg_tmp");
4324 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
4325 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
4326 gimplify_and_add (t, pre_p);
4328 for (i = 0; i < XVECLEN (container, 0); i++)
4330 rtx slot = XVECEXP (container, 0, i);
4331 rtx reg = XEXP (slot, 0);
4332 enum machine_mode mode = GET_MODE (reg);
4333 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
4334 tree addr_type = build_pointer_type (piece_type);
4337 tree dest_addr, dest;
4339 if (SSE_REGNO_P (REGNO (reg)))
4341 src_addr = sse_addr;
4342 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4346 src_addr = int_addr;
4347 src_offset = REGNO (reg) * 8;
4349 src_addr = fold_convert (addr_type, src_addr);
4350 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
4351 size_int (src_offset)));
4352 src = build_va_arg_indirect_ref (src_addr);
4354 dest_addr = fold_convert (addr_type, addr);
4355 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
4356 size_int (INTVAL (XEXP (slot, 1)))));
4357 dest = build_va_arg_indirect_ref (dest_addr);
4359 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
4360 gimplify_and_add (t, pre_p);
4366 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4367 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4368 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4369 gimplify_and_add (t, pre_p);
4373 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4374 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4375 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4376 gimplify_and_add (t, pre_p);
4379 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4380 gimplify_and_add (t, pre_p);
4382 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4383 append_to_statement_list (t, pre_p);
4386 /* ... otherwise out of the overflow area. */
4388 /* Care for on-stack alignment if needed. */
4389 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
4390 || integer_zerop (TYPE_SIZE (type)))
4394 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4395 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4396 build_int_cst (TREE_TYPE (ovf), align - 1));
4397 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4398 build_int_cst (TREE_TYPE (t), -align));
4400 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4402 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4403 gimplify_and_add (t2, pre_p);
4405 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4406 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4407 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4408 gimplify_and_add (t, pre_p);
4412 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4413 append_to_statement_list (t, pre_p);
4416 ptrtype = build_pointer_type (type);
4417 addr = fold_convert (ptrtype, addr);
4420 addr = build_va_arg_indirect_ref (addr);
4421 return build_va_arg_indirect_ref (addr);
4424 /* Return nonzero if OPNUM's MEM should be matched
4425 in movabs* patterns. */
4428 ix86_check_movabs (rtx insn, int opnum)
4432 set = PATTERN (insn);
4433 if (GET_CODE (set) == PARALLEL)
4434 set = XVECEXP (set, 0, 0);
4435 gcc_assert (GET_CODE (set) == SET);
4436 mem = XEXP (set, opnum);
4437 while (GET_CODE (mem) == SUBREG)
4438 mem = SUBREG_REG (mem);
4439 gcc_assert (GET_CODE (mem) == MEM);
4440 return (volatile_ok || !MEM_VOLATILE_P (mem));
4443 /* Initialize the table of extra 80387 mathematical constants. */
4446 init_ext_80387_constants (void)
4448 static const char * cst[5] =
4450 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4451 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4452 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4453 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4454 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4458 for (i = 0; i < 5; i++)
4460 real_from_string (&ext_80387_constants_table[i], cst[i]);
4461 /* Ensure each constant is rounded to XFmode precision. */
4462 real_convert (&ext_80387_constants_table[i],
4463 XFmode, &ext_80387_constants_table[i]);
4466 ext_80387_constants_init = 1;
4469 /* Return true if the constant is something that can be loaded with
4470 a special instruction. */
4473 standard_80387_constant_p (rtx x)
4475 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4478 if (x == CONST0_RTX (GET_MODE (x)))
4480 if (x == CONST1_RTX (GET_MODE (x)))
4483 /* For XFmode constants, try to find a special 80387 instruction when
4484 optimizing for size or on those CPUs that benefit from them. */
4485 if (GET_MODE (x) == XFmode
4486 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4491 if (! ext_80387_constants_init)
4492 init_ext_80387_constants ();
4494 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4495 for (i = 0; i < 5; i++)
4496 if (real_identical (&r, &ext_80387_constants_table[i]))
4503 /* Return the opcode of the special instruction to be used to load
4507 standard_80387_constant_opcode (rtx x)
4509 switch (standard_80387_constant_p (x))
4530 /* Return the CONST_DOUBLE representing the 80387 constant that is
4531 loaded by the specified special instruction. The argument IDX
4532 matches the return value from standard_80387_constant_p. */
4535 standard_80387_constant_rtx (int idx)
4539 if (! ext_80387_constants_init)
4540 init_ext_80387_constants ();
4556 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4560 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4563 standard_sse_constant_p (rtx x)
4565 if (x == const0_rtx)
4567 return (x == CONST0_RTX (GET_MODE (x)));
4570 /* Returns 1 if OP contains a symbol reference */
4573 symbolic_reference_mentioned_p (rtx op)
4578 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
4581 fmt = GET_RTX_FORMAT (GET_CODE (op));
4582 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
4588 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
4589 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
4593 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
4600 /* Return 1 if it is appropriate to emit `ret' instructions in the
4601 body of a function. Do this only if the epilogue is simple, needing a
4602 couple of insns. Prior to reloading, we can't tell how many registers
4603 must be saved, so return 0 then. Return 0 if there is no frame
4604 marker to de-allocate. */
4607 ix86_can_use_return_insn_p (void)
4609 struct ix86_frame frame;
4611 if (! reload_completed || frame_pointer_needed)
4614 /* Don't allow more than 32 pop, since that's all we can do
4615 with one instruction. */
4616 if (current_function_pops_args
4617 && current_function_args_size >= 32768)
4620 ix86_compute_frame_layout (&frame);
4621 return frame.to_allocate == 0 && frame.nregs == 0;
4624 /* Value should be nonzero if functions must have frame pointers.
4625 Zero means the frame pointer need not be set up (and parms may
4626 be accessed via the stack pointer) in functions that seem suitable. */
4629 ix86_frame_pointer_required (void)
4631 /* If we accessed previous frames, then the generated code expects
4632 to be able to access the saved ebp value in our frame. */
4633 if (cfun->machine->accesses_prev_frame)
4636 /* Several x86 os'es need a frame pointer for other reasons,
4637 usually pertaining to setjmp. */
4638 if (SUBTARGET_FRAME_POINTER_REQUIRED)
4641 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
4642 the frame pointer by default. Turn it back on now if we've not
4643 got a leaf function. */
4644 if (TARGET_OMIT_LEAF_FRAME_POINTER
4645 && (!current_function_is_leaf
4646 || ix86_current_function_calls_tls_descriptor))
4649 if (current_function_profile)
4655 /* Record that the current function accesses previous call frames. */
4658 ix86_setup_frame_addresses (void)
4660 cfun->machine->accesses_prev_frame = 1;
4663 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
4664 # define USE_HIDDEN_LINKONCE 1
4666 # define USE_HIDDEN_LINKONCE 0
4669 static int pic_labels_used;
4671 /* Fills in the label name that should be used for a pc thunk for
4672 the given register. */
4675 get_pc_thunk_name (char name[32], unsigned int regno)
4677 if (USE_HIDDEN_LINKONCE)
4678 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
4680 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
4684 /* This function generates code for -fpic that loads %ebx with
4685 the return address of the caller and then returns. */
4688 ix86_file_end (void)
4693 for (regno = 0; regno < 8; ++regno)
4697 if (! ((pic_labels_used >> regno) & 1))
4700 get_pc_thunk_name (name, regno);
4705 switch_to_section (darwin_sections[text_coal_section]);
4706 fputs ("\t.weak_definition\t", asm_out_file);
4707 assemble_name (asm_out_file, name);
4708 fputs ("\n\t.private_extern\t", asm_out_file);
4709 assemble_name (asm_out_file, name);
4710 fputs ("\n", asm_out_file);
4711 ASM_OUTPUT_LABEL (asm_out_file, name);
4715 if (USE_HIDDEN_LINKONCE)
4719 decl = build_decl (FUNCTION_DECL, get_identifier (name),
4721 TREE_PUBLIC (decl) = 1;
4722 TREE_STATIC (decl) = 1;
4723 DECL_ONE_ONLY (decl) = 1;
4725 (*targetm.asm_out.unique_section) (decl, 0);
4726 switch_to_section (get_named_section (decl, NULL, 0));
4728 (*targetm.asm_out.globalize_label) (asm_out_file, name);
4729 fputs ("\t.hidden\t", asm_out_file);
4730 assemble_name (asm_out_file, name);
4731 fputc ('\n', asm_out_file);
4732 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
4736 switch_to_section (text_section);
4737 ASM_OUTPUT_LABEL (asm_out_file, name);
4740 xops[0] = gen_rtx_REG (SImode, regno);
4741 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
4742 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
4743 output_asm_insn ("ret", xops);
4746 if (NEED_INDICATE_EXEC_STACK)
4747 file_end_indicate_exec_stack ();
4750 /* Emit code for the SET_GOT patterns. */
4753 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
4758 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
4760 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
4762 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
4765 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
4767 output_asm_insn ("call\t%a2", xops);
4770 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
4771 is what will be referenced by the Mach-O PIC subsystem. */
4773 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4776 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4777 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
4780 output_asm_insn ("pop{l}\t%0", xops);
4785 get_pc_thunk_name (name, REGNO (dest));
4786 pic_labels_used |= 1 << REGNO (dest);
4788 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4789 xops[2] = gen_rtx_MEM (QImode, xops[2]);
4790 output_asm_insn ("call\t%X2", xops);
4791 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
4792 is what will be referenced by the Mach-O PIC subsystem. */
4795 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4797 targetm.asm_out.internal_label (asm_out_file, "L",
4798 CODE_LABEL_NUMBER (label));
4805 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
4806 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
4808 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
4813 /* Generate an "push" pattern for input ARG. */
4818 return gen_rtx_SET (VOIDmode,
4820 gen_rtx_PRE_DEC (Pmode,
4821 stack_pointer_rtx)),
4825 /* Return >= 0 if there is an unused call-clobbered register available
4826 for the entire function. */
4829 ix86_select_alt_pic_regnum (void)
4831 if (current_function_is_leaf && !current_function_profile
4832 && !ix86_current_function_calls_tls_descriptor)
4835 for (i = 2; i >= 0; --i)
4836 if (!regs_ever_live[i])
4840 return INVALID_REGNUM;
4843 /* Return 1 if we need to save REGNO. */
4845 ix86_save_reg (unsigned int regno, int maybe_eh_return)
4847 if (pic_offset_table_rtx
4848 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
4849 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4850 || current_function_profile
4851 || current_function_calls_eh_return
4852 || current_function_uses_const_pool))
4854 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
4859 if (current_function_calls_eh_return && maybe_eh_return)
4864 unsigned test = EH_RETURN_DATA_REGNO (i);
4865 if (test == INVALID_REGNUM)
4872 if (cfun->machine->force_align_arg_pointer
4873 && regno == REGNO (cfun->machine->force_align_arg_pointer))
4876 return (regs_ever_live[regno]
4877 && !call_used_regs[regno]
4878 && !fixed_regs[regno]
4879 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
4882 /* Return number of registers to be saved on the stack. */
4885 ix86_nsaved_regs (void)
4890 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4891 if (ix86_save_reg (regno, true))
4896 /* Return the offset between two registers, one to be eliminated, and the other
4897 its replacement, at the start of a routine. */
4900 ix86_initial_elimination_offset (int from, int to)
4902 struct ix86_frame frame;
4903 ix86_compute_frame_layout (&frame);
4905 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
4906 return frame.hard_frame_pointer_offset;
4907 else if (from == FRAME_POINTER_REGNUM
4908 && to == HARD_FRAME_POINTER_REGNUM)
4909 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
4912 gcc_assert (to == STACK_POINTER_REGNUM);
4914 if (from == ARG_POINTER_REGNUM)
4915 return frame.stack_pointer_offset;
4917 gcc_assert (from == FRAME_POINTER_REGNUM);
4918 return frame.stack_pointer_offset - frame.frame_pointer_offset;
4922 /* Fill structure ix86_frame about frame of currently computed function. */
4925 ix86_compute_frame_layout (struct ix86_frame *frame)
4927 HOST_WIDE_INT total_size;
4928 unsigned int stack_alignment_needed;
4929 HOST_WIDE_INT offset;
4930 unsigned int preferred_alignment;
4931 HOST_WIDE_INT size = get_frame_size ();
4933 frame->nregs = ix86_nsaved_regs ();
4936 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
4937 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
4939 /* During reload iteration the amount of registers saved can change.
4940 Recompute the value as needed. Do not recompute when amount of registers
4941 didn't change as reload does multiple calls to the function and does not
4942 expect the decision to change within single iteration. */
4944 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
4946 int count = frame->nregs;
4948 cfun->machine->use_fast_prologue_epilogue_nregs = count;
4949 /* The fast prologue uses move instead of push to save registers. This
4950 is significantly longer, but also executes faster as modern hardware
4951 can execute the moves in parallel, but can't do that for push/pop.
4953 Be careful about choosing what prologue to emit: When function takes
4954 many instructions to execute we may use slow version as well as in
4955 case function is known to be outside hot spot (this is known with
4956 feedback only). Weight the size of function by number of registers
4957 to save as it is cheap to use one or two push instructions but very
4958 slow to use many of them. */
4960 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
4961 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
4962 || (flag_branch_probabilities
4963 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
4964 cfun->machine->use_fast_prologue_epilogue = false;
4966 cfun->machine->use_fast_prologue_epilogue
4967 = !expensive_function_p (count);
4969 if (TARGET_PROLOGUE_USING_MOVE
4970 && cfun->machine->use_fast_prologue_epilogue)
4971 frame->save_regs_using_mov = true;
4973 frame->save_regs_using_mov = false;
4976 /* Skip return address and saved base pointer. */
4977 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
4979 frame->hard_frame_pointer_offset = offset;
4981 /* Do some sanity checking of stack_alignment_needed and
4982 preferred_alignment, since i386 port is the only using those features
4983 that may break easily. */
4985 gcc_assert (!size || stack_alignment_needed);
4986 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
4987 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4988 gcc_assert (stack_alignment_needed
4989 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4991 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
4992 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
4994 /* Register save area */
4995 offset += frame->nregs * UNITS_PER_WORD;
4998 if (ix86_save_varrargs_registers)
5000 offset += X86_64_VARARGS_SIZE;
5001 frame->va_arg_size = X86_64_VARARGS_SIZE;
5004 frame->va_arg_size = 0;
5006 /* Align start of frame for local function. */
5007 frame->padding1 = ((offset + stack_alignment_needed - 1)
5008 & -stack_alignment_needed) - offset;
5010 offset += frame->padding1;
5012 /* Frame pointer points here. */
5013 frame->frame_pointer_offset = offset;
5017 /* Add outgoing arguments area. Can be skipped if we eliminated
5018 all the function calls as dead code.
5019 Skipping is however impossible when function calls alloca. Alloca
5020 expander assumes that last current_function_outgoing_args_size
5021 of stack frame are unused. */
5022 if (ACCUMULATE_OUTGOING_ARGS
5023 && (!current_function_is_leaf || current_function_calls_alloca
5024 || ix86_current_function_calls_tls_descriptor))
5026 offset += current_function_outgoing_args_size;
5027 frame->outgoing_arguments_size = current_function_outgoing_args_size;
5030 frame->outgoing_arguments_size = 0;
5032 /* Align stack boundary. Only needed if we're calling another function
5034 if (!current_function_is_leaf || current_function_calls_alloca
5035 || ix86_current_function_calls_tls_descriptor)
5036 frame->padding2 = ((offset + preferred_alignment - 1)
5037 & -preferred_alignment) - offset;
5039 frame->padding2 = 0;
5041 offset += frame->padding2;
5043 /* We've reached end of stack frame. */
5044 frame->stack_pointer_offset = offset;
5046 /* Size prologue needs to allocate. */
5047 frame->to_allocate =
5048 (size + frame->padding1 + frame->padding2
5049 + frame->outgoing_arguments_size + frame->va_arg_size);
5051 if ((!frame->to_allocate && frame->nregs <= 1)
5052 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
5053 frame->save_regs_using_mov = false;
5055 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
5056 && current_function_is_leaf
5057 && !ix86_current_function_calls_tls_descriptor)
5059 frame->red_zone_size = frame->to_allocate;
5060 if (frame->save_regs_using_mov)
5061 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
5062 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
5063 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
5066 frame->red_zone_size = 0;
5067 frame->to_allocate -= frame->red_zone_size;
5068 frame->stack_pointer_offset -= frame->red_zone_size;
5070 fprintf (stderr, "nregs: %i\n", frame->nregs);
5071 fprintf (stderr, "size: %i\n", size);
5072 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
5073 fprintf (stderr, "padding1: %i\n", frame->padding1);
5074 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
5075 fprintf (stderr, "padding2: %i\n", frame->padding2);
5076 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
5077 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
5078 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
5079 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
5080 frame->hard_frame_pointer_offset);
5081 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
5085 /* Emit code to save registers in the prologue. */
5088 ix86_emit_save_regs (void)
5093 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
5094 if (ix86_save_reg (regno, true))
5096 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
5097 RTX_FRAME_RELATED_P (insn) = 1;
5101 /* Emit code to save registers using MOV insns. First register
5102 is restored from POINTER + OFFSET. */
5104 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
5109 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5110 if (ix86_save_reg (regno, true))
5112 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
5114 gen_rtx_REG (Pmode, regno));
5115 RTX_FRAME_RELATED_P (insn) = 1;
5116 offset += UNITS_PER_WORD;
5120 /* Expand prologue or epilogue stack adjustment.
5121 The pattern exist to put a dependency on all ebp-based memory accesses.
5122 STYLE should be negative if instructions should be marked as frame related,
5123 zero if %r11 register is live and cannot be freely used and positive
5127 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
5132 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
5133 else if (x86_64_immediate_operand (offset, DImode))
5134 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
5138 /* r11 is used by indirect sibcall return as well, set before the
5139 epilogue and used after the epilogue. ATM indirect sibcall
5140 shouldn't be used together with huge frame sizes in one
5141 function because of the frame_size check in sibcall.c. */
5143 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
5144 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
5146 RTX_FRAME_RELATED_P (insn) = 1;
5147 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
5151 RTX_FRAME_RELATED_P (insn) = 1;
5154 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5157 ix86_internal_arg_pointer (void)
5159 if (FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
5160 && DECL_NAME (current_function_decl)
5161 && MAIN_NAME_P (DECL_NAME (current_function_decl))
5162 && DECL_FILE_SCOPE_P (current_function_decl))
5164 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
5165 return copy_to_reg (cfun->machine->force_align_arg_pointer);
5168 return virtual_incoming_args_rtx;
5171 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5172 This is called from dwarf2out.c to emit call frame instructions
5173 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5175 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
5177 rtx unspec = SET_SRC (pattern);
5178 gcc_assert (GET_CODE (unspec) == UNSPEC);
5182 case UNSPEC_REG_SAVE:
5183 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
5184 SET_DEST (pattern));
5186 case UNSPEC_DEF_CFA:
5187 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
5188 INTVAL (XVECEXP (unspec, 0, 0)));
5195 /* Expand the prologue into a bunch of separate insns. */
5198 ix86_expand_prologue (void)
5202 struct ix86_frame frame;
5203 HOST_WIDE_INT allocate;
5205 ix86_compute_frame_layout (&frame);
5207 if (cfun->machine->force_align_arg_pointer)
5211 /* Grab the argument pointer. */
5212 x = plus_constant (stack_pointer_rtx, 4);
5213 y = cfun->machine->force_align_arg_pointer;
5214 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
5215 RTX_FRAME_RELATED_P (insn) = 1;
5217 /* The unwind info consists of two parts: install the fafp as the cfa,
5218 and record the fafp as the "save register" of the stack pointer.
5219 The later is there in order that the unwinder can see where it
5220 should restore the stack pointer across the and insn. */
5221 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
5222 x = gen_rtx_SET (VOIDmode, y, x);
5223 RTX_FRAME_RELATED_P (x) = 1;
5224 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
5226 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
5227 RTX_FRAME_RELATED_P (y) = 1;
5228 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
5229 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5230 REG_NOTES (insn) = x;
5232 /* Align the stack. */
5233 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
5236 /* And here we cheat like madmen with the unwind info. We force the
5237 cfa register back to sp+4, which is exactly what it was at the
5238 start of the function. Re-pushing the return address results in
5239 the return at the same spot relative to the cfa, and thus is
5240 correct wrt the unwind info. */
5241 x = cfun->machine->force_align_arg_pointer;
5242 x = gen_frame_mem (Pmode, plus_constant (x, -4));
5243 insn = emit_insn (gen_push (x));
5244 RTX_FRAME_RELATED_P (insn) = 1;
5247 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
5248 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
5249 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5250 REG_NOTES (insn) = x;
5253 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5254 slower on all targets. Also sdb doesn't like it. */
5256 if (frame_pointer_needed)
5258 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
5259 RTX_FRAME_RELATED_P (insn) = 1;
5261 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
5262 RTX_FRAME_RELATED_P (insn) = 1;
5265 allocate = frame.to_allocate;
5267 if (!frame.save_regs_using_mov)
5268 ix86_emit_save_regs ();
5270 allocate += frame.nregs * UNITS_PER_WORD;
5272 /* When using red zone we may start register saving before allocating
5273 the stack frame saving one cycle of the prologue. */
5274 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
5275 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
5276 : stack_pointer_rtx,
5277 -frame.nregs * UNITS_PER_WORD);
5281 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
5282 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5283 GEN_INT (-allocate), -1);
5286 /* Only valid for Win32. */
5287 rtx eax = gen_rtx_REG (SImode, 0);
5288 bool eax_live = ix86_eax_live_at_start_p ();
5291 gcc_assert (!TARGET_64BIT);
5295 emit_insn (gen_push (eax));
5299 emit_move_insn (eax, GEN_INT (allocate));
5301 insn = emit_insn (gen_allocate_stack_worker (eax));
5302 RTX_FRAME_RELATED_P (insn) = 1;
5303 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
5304 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
5305 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
5306 t, REG_NOTES (insn));
5310 if (frame_pointer_needed)
5311 t = plus_constant (hard_frame_pointer_rtx,
5314 - frame.nregs * UNITS_PER_WORD);
5316 t = plus_constant (stack_pointer_rtx, allocate);
5317 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
5321 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
5323 if (!frame_pointer_needed || !frame.to_allocate)
5324 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
5326 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
5327 -frame.nregs * UNITS_PER_WORD);
5330 pic_reg_used = false;
5331 if (pic_offset_table_rtx
5332 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
5333 || current_function_profile))
5335 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
5337 if (alt_pic_reg_used != INVALID_REGNUM)
5338 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
5340 pic_reg_used = true;
5346 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
5348 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
5350 /* Even with accurate pre-reload life analysis, we can wind up
5351 deleting all references to the pic register after reload.
5352 Consider if cross-jumping unifies two sides of a branch
5353 controlled by a comparison vs the only read from a global.
5354 In which case, allow the set_got to be deleted, though we're
5355 too late to do anything about the ebx save in the prologue. */
5356 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
5359 /* Prevent function calls from be scheduled before the call to mcount.
5360 In the pic_reg_used case, make sure that the got load isn't deleted. */
5361 if (current_function_profile)
5362 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
5365 /* Emit code to restore saved registers using MOV insns. First register
5366 is restored from POINTER + OFFSET. */
5368 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
5369 int maybe_eh_return)
5372 rtx base_address = gen_rtx_MEM (Pmode, pointer);
5374 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5375 if (ix86_save_reg (regno, maybe_eh_return))
5377 /* Ensure that adjust_address won't be forced to produce pointer
5378 out of range allowed by x86-64 instruction set. */
5379 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
5383 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
5384 emit_move_insn (r11, GEN_INT (offset));
5385 emit_insn (gen_adddi3 (r11, r11, pointer));
5386 base_address = gen_rtx_MEM (Pmode, r11);
5389 emit_move_insn (gen_rtx_REG (Pmode, regno),
5390 adjust_address (base_address, Pmode, offset));
5391 offset += UNITS_PER_WORD;
5395 /* Restore function stack, frame, and registers. */
5398 ix86_expand_epilogue (int style)
5401 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
5402 struct ix86_frame frame;
5403 HOST_WIDE_INT offset;
5405 ix86_compute_frame_layout (&frame);
5407 /* Calculate start of saved registers relative to ebp. Special care
5408 must be taken for the normal return case of a function using
5409 eh_return: the eax and edx registers are marked as saved, but not
5410 restored along this path. */
5411 offset = frame.nregs;
5412 if (current_function_calls_eh_return && style != 2)
5414 offset *= -UNITS_PER_WORD;
5416 /* If we're only restoring one register and sp is not valid then
5417 using a move instruction to restore the register since it's
5418 less work than reloading sp and popping the register.
5420 The default code result in stack adjustment using add/lea instruction,
5421 while this code results in LEAVE instruction (or discrete equivalent),
5422 so it is profitable in some other cases as well. Especially when there
5423 are no registers to restore. We also use this code when TARGET_USE_LEAVE
5424 and there is exactly one register to pop. This heuristic may need some
5425 tuning in future. */
5426 if ((!sp_valid && frame.nregs <= 1)
5427 || (TARGET_EPILOGUE_USING_MOVE
5428 && cfun->machine->use_fast_prologue_epilogue
5429 && (frame.nregs > 1 || frame.to_allocate))
5430 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
5431 || (frame_pointer_needed && TARGET_USE_LEAVE
5432 && cfun->machine->use_fast_prologue_epilogue
5433 && frame.nregs == 1)
5434 || current_function_calls_eh_return)
5436 /* Restore registers. We can use ebp or esp to address the memory
5437 locations. If both are available, default to ebp, since offsets
5438 are known to be small. Only exception is esp pointing directly to the
5439 end of block of saved registers, where we may simplify addressing
5442 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
5443 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
5444 frame.to_allocate, style == 2);
5446 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
5447 offset, style == 2);
5449 /* eh_return epilogues need %ecx added to the stack pointer. */
5452 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
5454 if (frame_pointer_needed)
5456 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
5457 tmp = plus_constant (tmp, UNITS_PER_WORD);
5458 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
5460 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5461 emit_move_insn (hard_frame_pointer_rtx, tmp);
5463 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
5468 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
5469 tmp = plus_constant (tmp, (frame.to_allocate
5470 + frame.nregs * UNITS_PER_WORD));
5471 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
5474 else if (!frame_pointer_needed)
5475 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5476 GEN_INT (frame.to_allocate
5477 + frame.nregs * UNITS_PER_WORD),
5479 /* If not an i386, mov & pop is faster than "leave". */
5480 else if (TARGET_USE_LEAVE || optimize_size
5481 || !cfun->machine->use_fast_prologue_epilogue)
5482 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5485 pro_epilogue_adjust_stack (stack_pointer_rtx,
5486 hard_frame_pointer_rtx,
5489 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5491 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5496 /* First step is to deallocate the stack frame so that we can
5497 pop the registers. */
5500 gcc_assert (frame_pointer_needed);
5501 pro_epilogue_adjust_stack (stack_pointer_rtx,
5502 hard_frame_pointer_rtx,
5503 GEN_INT (offset), style);
5505 else if (frame.to_allocate)
5506 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5507 GEN_INT (frame.to_allocate), style);
5509 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5510 if (ix86_save_reg (regno, false))
5513 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5515 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5517 if (frame_pointer_needed)
5519 /* Leave results in shorter dependency chains on CPUs that are
5520 able to grok it fast. */
5521 if (TARGET_USE_LEAVE)
5522 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5523 else if (TARGET_64BIT)
5524 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5526 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5530 if (cfun->machine->force_align_arg_pointer)
5532 emit_insn (gen_addsi3 (stack_pointer_rtx,
5533 cfun->machine->force_align_arg_pointer,
5537 /* Sibcall epilogues don't want a return instruction. */
5541 if (current_function_pops_args && current_function_args_size)
5543 rtx popc = GEN_INT (current_function_pops_args);
5545 /* i386 can only pop 64K bytes. If asked to pop more, pop
5546 return address, do explicit add, and jump indirectly to the
5549 if (current_function_pops_args >= 65536)
5551 rtx ecx = gen_rtx_REG (SImode, 2);
5553 /* There is no "pascal" calling convention in 64bit ABI. */
5554 gcc_assert (!TARGET_64BIT);
5556 emit_insn (gen_popsi1 (ecx));
5557 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
5558 emit_jump_insn (gen_return_indirect_internal (ecx));
5561 emit_jump_insn (gen_return_pop_internal (popc));
5564 emit_jump_insn (gen_return_internal ());
5567 /* Reset from the function's potential modifications. */
5570 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5571 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5573 if (pic_offset_table_rtx)
5574 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
5577 /* Extract the parts of an RTL expression that is a valid memory address
5578 for an instruction. Return 0 if the structure of the address is
5579 grossly off. Return -1 if the address contains ASHIFT, so it is not
5580 strictly valid, but still used for computing length of lea instruction. */
5583 ix86_decompose_address (rtx addr, struct ix86_address *out)
5585 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
5586 rtx base_reg, index_reg;
5587 HOST_WIDE_INT scale = 1;
5588 rtx scale_rtx = NULL_RTX;
5590 enum ix86_address_seg seg = SEG_DEFAULT;
5592 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
5594 else if (GET_CODE (addr) == PLUS)
5604 addends[n++] = XEXP (op, 1);
5607 while (GET_CODE (op) == PLUS);
5612 for (i = n; i >= 0; --i)
5615 switch (GET_CODE (op))
5620 index = XEXP (op, 0);
5621 scale_rtx = XEXP (op, 1);
5625 if (XINT (op, 1) == UNSPEC_TP
5626 && TARGET_TLS_DIRECT_SEG_REFS
5627 && seg == SEG_DEFAULT)
5628 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
5657 else if (GET_CODE (addr) == MULT)
5659 index = XEXP (addr, 0); /* index*scale */
5660 scale_rtx = XEXP (addr, 1);
5662 else if (GET_CODE (addr) == ASHIFT)
5666 /* We're called for lea too, which implements ashift on occasion. */
5667 index = XEXP (addr, 0);
5668 tmp = XEXP (addr, 1);
5669 if (GET_CODE (tmp) != CONST_INT)
5671 scale = INTVAL (tmp);
5672 if ((unsigned HOST_WIDE_INT) scale > 3)
5678 disp = addr; /* displacement */
5680 /* Extract the integral value of scale. */
5683 if (GET_CODE (scale_rtx) != CONST_INT)
5685 scale = INTVAL (scale_rtx);
5688 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
5689 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
5691 /* Allow arg pointer and stack pointer as index if there is not scaling. */
5692 if (base_reg && index_reg && scale == 1
5693 && (index_reg == arg_pointer_rtx
5694 || index_reg == frame_pointer_rtx
5695 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
5698 tmp = base, base = index, index = tmp;
5699 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
5702 /* Special case: %ebp cannot be encoded as a base without a displacement. */
5703 if ((base_reg == hard_frame_pointer_rtx
5704 || base_reg == frame_pointer_rtx
5705 || base_reg == arg_pointer_rtx) && !disp)
5708 /* Special case: on K6, [%esi] makes the instruction vector decoded.
5709 Avoid this by transforming to [%esi+0]. */
5710 if (ix86_tune == PROCESSOR_K6 && !optimize_size
5711 && base_reg && !index_reg && !disp
5713 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
5716 /* Special case: encode reg+reg instead of reg*2. */
5717 if (!base && index && scale && scale == 2)
5718 base = index, base_reg = index_reg, scale = 1;
5720 /* Special case: scaling cannot be encoded without base or displacement. */
5721 if (!base && !disp && index && scale != 1)
5733 /* Return cost of the memory address x.
5734 For i386, it is better to use a complex address than let gcc copy
5735 the address into a reg and make a new pseudo. But not if the address
5736 requires to two regs - that would mean more pseudos with longer
5739 ix86_address_cost (rtx x)
5741 struct ix86_address parts;
5743 int ok = ix86_decompose_address (x, &parts);
5747 if (parts.base && GET_CODE (parts.base) == SUBREG)
5748 parts.base = SUBREG_REG (parts.base);
5749 if (parts.index && GET_CODE (parts.index) == SUBREG)
5750 parts.index = SUBREG_REG (parts.index);
5752 /* More complex memory references are better. */
5753 if (parts.disp && parts.disp != const0_rtx)
5755 if (parts.seg != SEG_DEFAULT)
5758 /* Attempt to minimize number of registers in the address. */
5760 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
5762 && (!REG_P (parts.index)
5763 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
5767 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
5769 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
5770 && parts.base != parts.index)
5773 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
5774 since it's predecode logic can't detect the length of instructions
5775 and it degenerates to vector decoded. Increase cost of such
5776 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
5777 to split such addresses or even refuse such addresses at all.
5779 Following addressing modes are affected:
5784 The first and last case may be avoidable by explicitly coding the zero in
5785 memory address, but I don't have AMD-K6 machine handy to check this
5789 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
5790 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
5791 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
5797 /* If X is a machine specific address (i.e. a symbol or label being
5798 referenced as a displacement from the GOT implemented using an
5799 UNSPEC), then return the base term. Otherwise return X. */
5802 ix86_find_base_term (rtx x)
5808 if (GET_CODE (x) != CONST)
5811 if (GET_CODE (term) == PLUS
5812 && (GET_CODE (XEXP (term, 1)) == CONST_INT
5813 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
5814 term = XEXP (term, 0);
5815 if (GET_CODE (term) != UNSPEC
5816 || XINT (term, 1) != UNSPEC_GOTPCREL)
5819 term = XVECEXP (term, 0, 0);
5821 if (GET_CODE (term) != SYMBOL_REF
5822 && GET_CODE (term) != LABEL_REF)
5828 term = ix86_delegitimize_address (x);
5830 if (GET_CODE (term) != SYMBOL_REF
5831 && GET_CODE (term) != LABEL_REF)
5837 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
5838 this is used for to form addresses to local data when -fPIC is in
5842 darwin_local_data_pic (rtx disp)
5844 if (GET_CODE (disp) == MINUS)
5846 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
5847 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
5848 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
5850 const char *sym_name = XSTR (XEXP (disp, 1), 0);
5851 if (! strcmp (sym_name, "<pic base>"))
5859 /* Determine if a given RTX is a valid constant. We already know this
5860 satisfies CONSTANT_P. */
5863 legitimate_constant_p (rtx x)
5865 switch (GET_CODE (x))
5870 if (GET_CODE (x) == PLUS)
5872 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5877 if (TARGET_MACHO && darwin_local_data_pic (x))
5880 /* Only some unspecs are valid as "constants". */
5881 if (GET_CODE (x) == UNSPEC)
5882 switch (XINT (x, 1))
5885 return TARGET_64BIT;
5888 x = XVECEXP (x, 0, 0);
5889 return (GET_CODE (x) == SYMBOL_REF
5890 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
5892 x = XVECEXP (x, 0, 0);
5893 return (GET_CODE (x) == SYMBOL_REF
5894 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
5899 /* We must have drilled down to a symbol. */
5900 if (GET_CODE (x) == LABEL_REF)
5902 if (GET_CODE (x) != SYMBOL_REF)
5907 /* TLS symbols are never valid. */
5908 if (SYMBOL_REF_TLS_MODEL (x))
5916 /* Otherwise we handle everything else in the move patterns. */
5920 /* Determine if it's legal to put X into the constant pool. This
5921 is not possible for the address of thread-local symbols, which
5922 is checked above. */
5925 ix86_cannot_force_const_mem (rtx x)
5927 return !legitimate_constant_p (x);
5930 /* Determine if a given RTX is a valid constant address. */
5933 constant_address_p (rtx x)
5935 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
5938 /* Nonzero if the constant value X is a legitimate general operand
5939 when generating PIC code. It is given that flag_pic is on and
5940 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
5943 legitimate_pic_operand_p (rtx x)
5947 switch (GET_CODE (x))
5950 inner = XEXP (x, 0);
5951 if (GET_CODE (inner) == PLUS
5952 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
5953 inner = XEXP (inner, 0);
5955 /* Only some unspecs are valid as "constants". */
5956 if (GET_CODE (inner) == UNSPEC)
5957 switch (XINT (inner, 1))
5960 return TARGET_64BIT;
5962 x = XVECEXP (inner, 0, 0);
5963 return (GET_CODE (x) == SYMBOL_REF
5964 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
5972 return legitimate_pic_address_disp_p (x);
5979 /* Determine if a given CONST RTX is a valid memory displacement
5983 legitimate_pic_address_disp_p (rtx disp)
5987 /* In 64bit mode we can allow direct addresses of symbols and labels
5988 when they are not dynamic symbols. */
5991 rtx op0 = disp, op1;
5993 switch (GET_CODE (disp))
5999 if (GET_CODE (XEXP (disp, 0)) != PLUS)
6001 op0 = XEXP (XEXP (disp, 0), 0);
6002 op1 = XEXP (XEXP (disp, 0), 1);
6003 if (GET_CODE (op1) != CONST_INT
6004 || INTVAL (op1) >= 16*1024*1024
6005 || INTVAL (op1) < -16*1024*1024)
6007 if (GET_CODE (op0) == LABEL_REF)
6009 if (GET_CODE (op0) != SYMBOL_REF)
6014 /* TLS references should always be enclosed in UNSPEC. */
6015 if (SYMBOL_REF_TLS_MODEL (op0))
6017 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0))
6025 if (GET_CODE (disp) != CONST)
6027 disp = XEXP (disp, 0);
6031 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6032 of GOT tables. We should not need these anyway. */
6033 if (GET_CODE (disp) != UNSPEC
6034 || (XINT (disp, 1) != UNSPEC_GOTPCREL
6035 && XINT (disp, 1) != UNSPEC_GOTOFF))
6038 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
6039 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
6045 if (GET_CODE (disp) == PLUS)
6047 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
6049 disp = XEXP (disp, 0);
6053 if (TARGET_MACHO && darwin_local_data_pic (disp))
6056 if (GET_CODE (disp) != UNSPEC)
6059 switch (XINT (disp, 1))
6064 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
6066 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6067 While ABI specify also 32bit relocation but we don't produce it in
6068 small PIC model at all. */
6069 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6070 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
6072 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
6074 case UNSPEC_GOTTPOFF:
6075 case UNSPEC_GOTNTPOFF:
6076 case UNSPEC_INDNTPOFF:
6079 disp = XVECEXP (disp, 0, 0);
6080 return (GET_CODE (disp) == SYMBOL_REF
6081 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
6083 disp = XVECEXP (disp, 0, 0);
6084 return (GET_CODE (disp) == SYMBOL_REF
6085 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
6087 disp = XVECEXP (disp, 0, 0);
6088 return (GET_CODE (disp) == SYMBOL_REF
6089 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
6095 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6096 memory address for an instruction. The MODE argument is the machine mode
6097 for the MEM expression that wants to use this address.
6099 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6100 convert common non-canonical forms to canonical form so that they will
6104 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
6106 struct ix86_address parts;
6107 rtx base, index, disp;
6108 HOST_WIDE_INT scale;
6109 const char *reason = NULL;
6110 rtx reason_rtx = NULL_RTX;
6112 if (TARGET_DEBUG_ADDR)
6115 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
6116 GET_MODE_NAME (mode), strict);
6120 if (ix86_decompose_address (addr, &parts) <= 0)
6122 reason = "decomposition failed";
6127 index = parts.index;
6129 scale = parts.scale;
6131 /* Validate base register.
6133 Don't allow SUBREG's that span more than a word here. It can lead to spill
6134 failures when the base is one word out of a two word structure, which is
6135 represented internally as a DImode int. */
6144 else if (GET_CODE (base) == SUBREG
6145 && REG_P (SUBREG_REG (base))
6146 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
6148 reg = SUBREG_REG (base);
6151 reason = "base is not a register";
6155 if (GET_MODE (base) != Pmode)
6157 reason = "base is not in Pmode";
6161 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
6162 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
6164 reason = "base is not valid";
6169 /* Validate index register.
6171 Don't allow SUBREG's that span more than a word here -- same as above. */
6180 else if (GET_CODE (index) == SUBREG
6181 && REG_P (SUBREG_REG (index))
6182 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
6184 reg = SUBREG_REG (index);
6187 reason = "index is not a register";
6191 if (GET_MODE (index) != Pmode)
6193 reason = "index is not in Pmode";
6197 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
6198 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
6200 reason = "index is not valid";
6205 /* Validate scale factor. */
6208 reason_rtx = GEN_INT (scale);
6211 reason = "scale without index";
6215 if (scale != 2 && scale != 4 && scale != 8)
6217 reason = "scale is not a valid multiplier";
6222 /* Validate displacement. */
6227 if (GET_CODE (disp) == CONST
6228 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
6229 switch (XINT (XEXP (disp, 0), 1))
6231 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6232 used. While ABI specify also 32bit relocations, we don't produce
6233 them at all and use IP relative instead. */
6236 gcc_assert (flag_pic);
6238 goto is_legitimate_pic;
6239 reason = "64bit address unspec";
6242 case UNSPEC_GOTPCREL:
6243 gcc_assert (flag_pic);
6244 goto is_legitimate_pic;
6246 case UNSPEC_GOTTPOFF:
6247 case UNSPEC_GOTNTPOFF:
6248 case UNSPEC_INDNTPOFF:
6254 reason = "invalid address unspec";
6258 else if (flag_pic && (SYMBOLIC_CONST (disp)
6260 && !machopic_operand_p (disp)
6265 if (TARGET_64BIT && (index || base))
6267 /* foo@dtpoff(%rX) is ok. */
6268 if (GET_CODE (disp) != CONST
6269 || GET_CODE (XEXP (disp, 0)) != PLUS
6270 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
6271 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
6272 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
6273 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
6275 reason = "non-constant pic memory reference";
6279 else if (! legitimate_pic_address_disp_p (disp))
6281 reason = "displacement is an invalid pic construct";
6285 /* This code used to verify that a symbolic pic displacement
6286 includes the pic_offset_table_rtx register.
6288 While this is good idea, unfortunately these constructs may
6289 be created by "adds using lea" optimization for incorrect
6298 This code is nonsensical, but results in addressing
6299 GOT table with pic_offset_table_rtx base. We can't
6300 just refuse it easily, since it gets matched by
6301 "addsi3" pattern, that later gets split to lea in the
6302 case output register differs from input. While this
6303 can be handled by separate addsi pattern for this case
6304 that never results in lea, this seems to be easier and
6305 correct fix for crash to disable this test. */
6307 else if (GET_CODE (disp) != LABEL_REF
6308 && GET_CODE (disp) != CONST_INT
6309 && (GET_CODE (disp) != CONST
6310 || !legitimate_constant_p (disp))
6311 && (GET_CODE (disp) != SYMBOL_REF
6312 || !legitimate_constant_p (disp)))
6314 reason = "displacement is not constant";
6317 else if (TARGET_64BIT
6318 && !x86_64_immediate_operand (disp, VOIDmode))
6320 reason = "displacement is out of range";
6325 /* Everything looks valid. */
6326 if (TARGET_DEBUG_ADDR)
6327 fprintf (stderr, "Success.\n");
6331 if (TARGET_DEBUG_ADDR)
6333 fprintf (stderr, "Error: %s\n", reason);
6334 debug_rtx (reason_rtx);
6339 /* Return a unique alias set for the GOT. */
6341 static HOST_WIDE_INT
6342 ix86_GOT_alias_set (void)
6344 static HOST_WIDE_INT set = -1;
6346 set = new_alias_set ();
6350 /* Return a legitimate reference for ORIG (an address) using the
6351 register REG. If REG is 0, a new pseudo is generated.
6353 There are two types of references that must be handled:
6355 1. Global data references must load the address from the GOT, via
6356 the PIC reg. An insn is emitted to do this load, and the reg is
6359 2. Static data references, constant pool addresses, and code labels
6360 compute the address as an offset from the GOT, whose base is in
6361 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
6362 differentiate them from global data objects. The returned
6363 address is the PIC reg + an unspec constant.
6365 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
6366 reg also appears in the address. */
6369 legitimize_pic_address (rtx orig, rtx reg)
6377 reg = gen_reg_rtx (Pmode);
6378 /* Use the generic Mach-O PIC machinery. */
6379 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
6382 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
6384 else if (TARGET_64BIT
6385 && ix86_cmodel != CM_SMALL_PIC
6386 && local_symbolic_operand (addr, Pmode))
6389 /* This symbol may be referenced via a displacement from the PIC
6390 base address (@GOTOFF). */
6392 if (reload_in_progress)
6393 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6394 if (GET_CODE (addr) == CONST)
6395 addr = XEXP (addr, 0);
6396 if (GET_CODE (addr) == PLUS)
6398 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6399 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6402 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6403 new = gen_rtx_CONST (Pmode, new);
6405 tmpreg = gen_reg_rtx (Pmode);
6408 emit_move_insn (tmpreg, new);
6412 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
6413 tmpreg, 1, OPTAB_DIRECT);
6416 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
6418 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
6420 /* This symbol may be referenced via a displacement from the PIC
6421 base address (@GOTOFF). */
6423 if (reload_in_progress)
6424 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6425 if (GET_CODE (addr) == CONST)
6426 addr = XEXP (addr, 0);
6427 if (GET_CODE (addr) == PLUS)
6429 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6430 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6433 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6434 new = gen_rtx_CONST (Pmode, new);
6435 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6439 emit_move_insn (reg, new);
6443 else if (GET_CODE (addr) == SYMBOL_REF)
6447 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
6448 new = gen_rtx_CONST (Pmode, new);
6449 new = gen_const_mem (Pmode, new);
6450 set_mem_alias_set (new, ix86_GOT_alias_set ());
6453 reg = gen_reg_rtx (Pmode);
6454 /* Use directly gen_movsi, otherwise the address is loaded
6455 into register for CSE. We don't want to CSE this addresses,
6456 instead we CSE addresses from the GOT table, so skip this. */
6457 emit_insn (gen_movsi (reg, new));
6462 /* This symbol must be referenced via a load from the
6463 Global Offset Table (@GOT). */
6465 if (reload_in_progress)
6466 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6467 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
6468 new = gen_rtx_CONST (Pmode, new);
6469 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6470 new = gen_const_mem (Pmode, new);
6471 set_mem_alias_set (new, ix86_GOT_alias_set ());
6474 reg = gen_reg_rtx (Pmode);
6475 emit_move_insn (reg, new);
6481 if (GET_CODE (addr) == CONST_INT
6482 && !x86_64_immediate_operand (addr, VOIDmode))
6486 emit_move_insn (reg, addr);
6490 new = force_reg (Pmode, addr);
6492 else if (GET_CODE (addr) == CONST)
6494 addr = XEXP (addr, 0);
6496 /* We must match stuff we generate before. Assume the only
6497 unspecs that can get here are ours. Not that we could do
6498 anything with them anyway.... */
6499 if (GET_CODE (addr) == UNSPEC
6500 || (GET_CODE (addr) == PLUS
6501 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
6503 gcc_assert (GET_CODE (addr) == PLUS);
6505 if (GET_CODE (addr) == PLUS)
6507 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
6509 /* Check first to see if this is a constant offset from a @GOTOFF
6510 symbol reference. */
6511 if (local_symbolic_operand (op0, Pmode)
6512 && GET_CODE (op1) == CONST_INT)
6516 if (reload_in_progress)
6517 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6518 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
6520 new = gen_rtx_PLUS (Pmode, new, op1);
6521 new = gen_rtx_CONST (Pmode, new);
6522 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6526 emit_move_insn (reg, new);
6532 if (INTVAL (op1) < -16*1024*1024
6533 || INTVAL (op1) >= 16*1024*1024)
6535 if (!x86_64_immediate_operand (op1, Pmode))
6536 op1 = force_reg (Pmode, op1);
6537 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
6543 base = legitimize_pic_address (XEXP (addr, 0), reg);
6544 new = legitimize_pic_address (XEXP (addr, 1),
6545 base == reg ? NULL_RTX : reg);
6547 if (GET_CODE (new) == CONST_INT)
6548 new = plus_constant (base, INTVAL (new));
6551 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
6553 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
6554 new = XEXP (new, 1);
6556 new = gen_rtx_PLUS (Pmode, base, new);
6564 /* Load the thread pointer. If TO_REG is true, force it into a register. */
6567 get_thread_pointer (int to_reg)
6571 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
6575 reg = gen_reg_rtx (Pmode);
6576 insn = gen_rtx_SET (VOIDmode, reg, tp);
6577 insn = emit_insn (insn);
6582 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
6583 false if we expect this to be used for a memory address and true if
6584 we expect to load the address into a register. */
6587 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
6589 rtx dest, base, off, pic, tp;
6594 case TLS_MODEL_GLOBAL_DYNAMIC:
6595 dest = gen_reg_rtx (Pmode);
6596 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
6598 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
6600 rtx rax = gen_rtx_REG (Pmode, 0), insns;
6603 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
6604 insns = get_insns ();
6607 emit_libcall_block (insns, dest, rax, x);
6609 else if (TARGET_64BIT && TARGET_GNU2_TLS)
6610 emit_insn (gen_tls_global_dynamic_64 (dest, x));
6612 emit_insn (gen_tls_global_dynamic_32 (dest, x));
6614 if (TARGET_GNU2_TLS)
6616 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
6618 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
6622 case TLS_MODEL_LOCAL_DYNAMIC:
6623 base = gen_reg_rtx (Pmode);
6624 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
6626 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
6628 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
6631 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
6632 insns = get_insns ();
6635 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
6636 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
6637 emit_libcall_block (insns, base, rax, note);
6639 else if (TARGET_64BIT && TARGET_GNU2_TLS)
6640 emit_insn (gen_tls_local_dynamic_base_64 (base));
6642 emit_insn (gen_tls_local_dynamic_base_32 (base));
6644 if (TARGET_GNU2_TLS)
6646 rtx x = ix86_tls_module_base ();
6648 base = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, base));
6650 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
6653 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
6654 off = gen_rtx_CONST (Pmode, off);
6656 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
6659 case TLS_MODEL_INITIAL_EXEC:
6663 type = UNSPEC_GOTNTPOFF;
6667 if (reload_in_progress)
6668 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6669 pic = pic_offset_table_rtx;
6670 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
6672 else if (!TARGET_ANY_GNU_TLS)
6674 pic = gen_reg_rtx (Pmode);
6675 emit_insn (gen_set_got (pic));
6676 type = UNSPEC_GOTTPOFF;
6681 type = UNSPEC_INDNTPOFF;
6684 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
6685 off = gen_rtx_CONST (Pmode, off);
6687 off = gen_rtx_PLUS (Pmode, pic, off);
6688 off = gen_const_mem (Pmode, off);
6689 set_mem_alias_set (off, ix86_GOT_alias_set ());
6691 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6693 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6694 off = force_reg (Pmode, off);
6695 return gen_rtx_PLUS (Pmode, base, off);
6699 base = get_thread_pointer (true);
6700 dest = gen_reg_rtx (Pmode);
6701 emit_insn (gen_subsi3 (dest, base, off));
6705 case TLS_MODEL_LOCAL_EXEC:
6706 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
6707 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6708 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
6709 off = gen_rtx_CONST (Pmode, off);
6711 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6713 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6714 return gen_rtx_PLUS (Pmode, base, off);
6718 base = get_thread_pointer (true);
6719 dest = gen_reg_rtx (Pmode);
6720 emit_insn (gen_subsi3 (dest, base, off));
6731 /* Try machine-dependent ways of modifying an illegitimate address
6732 to be legitimate. If we find one, return the new, valid address.
6733 This macro is used in only one place: `memory_address' in explow.c.
6735 OLDX is the address as it was before break_out_memory_refs was called.
6736 In some cases it is useful to look at this to decide what needs to be done.
6738 MODE and WIN are passed so that this macro can use
6739 GO_IF_LEGITIMATE_ADDRESS.
6741 It is always safe for this macro to do nothing. It exists to recognize
6742 opportunities to optimize the output.
6744 For the 80386, we handle X+REG by loading X into a register R and
6745 using R+REG. R will go in a general reg and indexing will be used.
6746 However, if REG is a broken-out memory address or multiplication,
6747 nothing needs to be done because REG can certainly go in a general reg.
6749 When -fpic is used, special handling is needed for symbolic references.
6750 See comments by legitimize_pic_address in i386.c for details. */
6753 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
6758 if (TARGET_DEBUG_ADDR)
6760 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
6761 GET_MODE_NAME (mode));
6765 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
6767 return legitimize_tls_address (x, log, false);
6768 if (GET_CODE (x) == CONST
6769 && GET_CODE (XEXP (x, 0)) == PLUS
6770 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6771 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
6773 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
6774 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
6777 if (flag_pic && SYMBOLIC_CONST (x))
6778 return legitimize_pic_address (x, 0);
6780 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
6781 if (GET_CODE (x) == ASHIFT
6782 && GET_CODE (XEXP (x, 1)) == CONST_INT
6783 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
6786 log = INTVAL (XEXP (x, 1));
6787 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
6788 GEN_INT (1 << log));
6791 if (GET_CODE (x) == PLUS)
6793 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
6795 if (GET_CODE (XEXP (x, 0)) == ASHIFT
6796 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6797 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
6800 log = INTVAL (XEXP (XEXP (x, 0), 1));
6801 XEXP (x, 0) = gen_rtx_MULT (Pmode,
6802 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
6803 GEN_INT (1 << log));
6806 if (GET_CODE (XEXP (x, 1)) == ASHIFT
6807 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
6808 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
6811 log = INTVAL (XEXP (XEXP (x, 1), 1));
6812 XEXP (x, 1) = gen_rtx_MULT (Pmode,
6813 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
6814 GEN_INT (1 << log));
6817 /* Put multiply first if it isn't already. */
6818 if (GET_CODE (XEXP (x, 1)) == MULT)
6820 rtx tmp = XEXP (x, 0);
6821 XEXP (x, 0) = XEXP (x, 1);
6826 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
6827 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
6828 created by virtual register instantiation, register elimination, and
6829 similar optimizations. */
6830 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
6833 x = gen_rtx_PLUS (Pmode,
6834 gen_rtx_PLUS (Pmode, XEXP (x, 0),
6835 XEXP (XEXP (x, 1), 0)),
6836 XEXP (XEXP (x, 1), 1));
6840 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
6841 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
6842 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
6843 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
6844 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
6845 && CONSTANT_P (XEXP (x, 1)))
6848 rtx other = NULL_RTX;
6850 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6852 constant = XEXP (x, 1);
6853 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
6855 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
6857 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
6858 other = XEXP (x, 1);
6866 x = gen_rtx_PLUS (Pmode,
6867 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
6868 XEXP (XEXP (XEXP (x, 0), 1), 0)),
6869 plus_constant (other, INTVAL (constant)));
6873 if (changed && legitimate_address_p (mode, x, FALSE))
6876 if (GET_CODE (XEXP (x, 0)) == MULT)
6879 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
6882 if (GET_CODE (XEXP (x, 1)) == MULT)
6885 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
6889 && GET_CODE (XEXP (x, 1)) == REG
6890 && GET_CODE (XEXP (x, 0)) == REG)
6893 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
6896 x = legitimize_pic_address (x, 0);
6899 if (changed && legitimate_address_p (mode, x, FALSE))
6902 if (GET_CODE (XEXP (x, 0)) == REG)
6904 rtx temp = gen_reg_rtx (Pmode);
6905 rtx val = force_operand (XEXP (x, 1), temp);
6907 emit_move_insn (temp, val);
6913 else if (GET_CODE (XEXP (x, 1)) == REG)
6915 rtx temp = gen_reg_rtx (Pmode);
6916 rtx val = force_operand (XEXP (x, 0), temp);
6918 emit_move_insn (temp, val);
6928 /* Print an integer constant expression in assembler syntax. Addition
6929 and subtraction are the only arithmetic that may appear in these
6930 expressions. FILE is the stdio stream to write to, X is the rtx, and
6931 CODE is the operand print code from the output string. */
6934 output_pic_addr_const (FILE *file, rtx x, int code)
6938 switch (GET_CODE (x))
6941 gcc_assert (flag_pic);
6946 output_addr_const (file, x);
6947 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
6948 fputs ("@PLT", file);
6955 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
6956 assemble_name (asm_out_file, buf);
6960 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
6964 /* This used to output parentheses around the expression,
6965 but that does not work on the 386 (either ATT or BSD assembler). */
6966 output_pic_addr_const (file, XEXP (x, 0), code);
6970 if (GET_MODE (x) == VOIDmode)
6972 /* We can use %d if the number is <32 bits and positive. */
6973 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
6974 fprintf (file, "0x%lx%08lx",
6975 (unsigned long) CONST_DOUBLE_HIGH (x),
6976 (unsigned long) CONST_DOUBLE_LOW (x));
6978 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
6981 /* We can't handle floating point constants;
6982 PRINT_OPERAND must handle them. */
6983 output_operand_lossage ("floating constant misused");
6987 /* Some assemblers need integer constants to appear first. */
6988 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6990 output_pic_addr_const (file, XEXP (x, 0), code);
6992 output_pic_addr_const (file, XEXP (x, 1), code);
6996 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
6997 output_pic_addr_const (file, XEXP (x, 1), code);
6999 output_pic_addr_const (file, XEXP (x, 0), code);
7005 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
7006 output_pic_addr_const (file, XEXP (x, 0), code);
7008 output_pic_addr_const (file, XEXP (x, 1), code);
7010 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
7014 gcc_assert (XVECLEN (x, 0) == 1);
7015 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
7016 switch (XINT (x, 1))
7019 fputs ("@GOT", file);
7022 fputs ("@GOTOFF", file);
7024 case UNSPEC_GOTPCREL:
7025 fputs ("@GOTPCREL(%rip)", file);
7027 case UNSPEC_GOTTPOFF:
7028 /* FIXME: This might be @TPOFF in Sun ld too. */
7029 fputs ("@GOTTPOFF", file);
7032 fputs ("@TPOFF", file);
7036 fputs ("@TPOFF", file);
7038 fputs ("@NTPOFF", file);
7041 fputs ("@DTPOFF", file);
7043 case UNSPEC_GOTNTPOFF:
7045 fputs ("@GOTTPOFF(%rip)", file);
7047 fputs ("@GOTNTPOFF", file);
7049 case UNSPEC_INDNTPOFF:
7050 fputs ("@INDNTPOFF", file);
7053 output_operand_lossage ("invalid UNSPEC as operand");
7059 output_operand_lossage ("invalid expression as operand");
7063 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7064 We need to emit DTP-relative relocations. */
7067 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
7069 fputs (ASM_LONG, file);
7070 output_addr_const (file, x);
7071 fputs ("@DTPOFF", file);
7077 fputs (", 0", file);
7084 /* In the name of slightly smaller debug output, and to cater to
7085 general assembler lossage, recognize PIC+GOTOFF and turn it back
7086 into a direct symbol reference. */
7089 ix86_delegitimize_address (rtx orig_x)
7093 if (GET_CODE (x) == MEM)
7098 if (GET_CODE (x) != CONST
7099 || GET_CODE (XEXP (x, 0)) != UNSPEC
7100 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
7101 || GET_CODE (orig_x) != MEM)
7103 return XVECEXP (XEXP (x, 0), 0, 0);
7106 if (GET_CODE (x) != PLUS
7107 || GET_CODE (XEXP (x, 1)) != CONST)
7110 if (GET_CODE (XEXP (x, 0)) == REG
7111 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
7112 /* %ebx + GOT/GOTOFF */
7114 else if (GET_CODE (XEXP (x, 0)) == PLUS)
7116 /* %ebx + %reg * scale + GOT/GOTOFF */
7118 if (GET_CODE (XEXP (y, 0)) == REG
7119 && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
7121 else if (GET_CODE (XEXP (y, 1)) == REG
7122 && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
7126 if (GET_CODE (y) != REG
7127 && GET_CODE (y) != MULT
7128 && GET_CODE (y) != ASHIFT)
7134 x = XEXP (XEXP (x, 1), 0);
7135 if (GET_CODE (x) == UNSPEC
7136 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
7137 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
7140 return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
7141 return XVECEXP (x, 0, 0);
7144 if (GET_CODE (x) == PLUS
7145 && GET_CODE (XEXP (x, 0)) == UNSPEC
7146 && GET_CODE (XEXP (x, 1)) == CONST_INT
7147 && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
7148 || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
7149 && GET_CODE (orig_x) != MEM)))
7151 x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
7153 return gen_rtx_PLUS (Pmode, y, x);
7157 if (TARGET_MACHO && darwin_local_data_pic (x)
7158 && GET_CODE (orig_x) != MEM)
7162 return gen_rtx_PLUS (Pmode, y, x);
7169 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
7174 if (mode == CCFPmode || mode == CCFPUmode)
7176 enum rtx_code second_code, bypass_code;
7177 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
7178 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
7179 code = ix86_fp_compare_code_to_integer (code);
7183 code = reverse_condition (code);
7194 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
7198 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
7199 Those same assemblers have the same but opposite lossage on cmov. */
7200 gcc_assert (mode == CCmode);
7201 suffix = fp ? "nbe" : "a";
7221 gcc_assert (mode == CCmode);
7243 gcc_assert (mode == CCmode);
7244 suffix = fp ? "nb" : "ae";
7247 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
7251 gcc_assert (mode == CCmode);
7255 suffix = fp ? "u" : "p";
7258 suffix = fp ? "nu" : "np";
7263 fputs (suffix, file);
7266 /* Print the name of register X to FILE based on its machine mode and number.
7267 If CODE is 'w', pretend the mode is HImode.
7268 If CODE is 'b', pretend the mode is QImode.
7269 If CODE is 'k', pretend the mode is SImode.
7270 If CODE is 'q', pretend the mode is DImode.
7271 If CODE is 'h', pretend the reg is the 'high' byte register.
7272 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
7275 print_reg (rtx x, int code, FILE *file)
7277 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
7278 && REGNO (x) != FRAME_POINTER_REGNUM
7279 && REGNO (x) != FLAGS_REG
7280 && REGNO (x) != FPSR_REG);
7282 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
7285 if (code == 'w' || MMX_REG_P (x))
7287 else if (code == 'b')
7289 else if (code == 'k')
7291 else if (code == 'q')
7293 else if (code == 'y')
7295 else if (code == 'h')
7298 code = GET_MODE_SIZE (GET_MODE (x));
7300 /* Irritatingly, AMD extended registers use different naming convention
7301 from the normal registers. */
7302 if (REX_INT_REG_P (x))
7304 gcc_assert (TARGET_64BIT);
7308 error ("extended registers have no high halves");
7311 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
7314 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
7317 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
7320 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
7323 error ("unsupported operand size for extended register");
7331 if (STACK_TOP_P (x))
7333 fputs ("st(0)", file);
7340 if (! ANY_FP_REG_P (x))
7341 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
7346 fputs (hi_reg_name[REGNO (x)], file);
7349 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
7351 fputs (qi_reg_name[REGNO (x)], file);
7354 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
7356 fputs (qi_high_reg_name[REGNO (x)], file);
7363 /* Locate some local-dynamic symbol still in use by this function
7364 so that we can print its name in some tls_local_dynamic_base
7368 get_some_local_dynamic_name (void)
7372 if (cfun->machine->some_ld_name)
7373 return cfun->machine->some_ld_name;
7375 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
7377 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
7378 return cfun->machine->some_ld_name;
7384 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
7388 if (GET_CODE (x) == SYMBOL_REF
7389 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
7391 cfun->machine->some_ld_name = XSTR (x, 0);
7399 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
7400 C -- print opcode suffix for set/cmov insn.
7401 c -- like C, but print reversed condition
7402 F,f -- likewise, but for floating-point.
7403 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
7405 R -- print the prefix for register names.
7406 z -- print the opcode suffix for the size of the current operand.
7407 * -- print a star (in certain assembler syntax)
7408 A -- print an absolute memory reference.
7409 w -- print the operand as if it's a "word" (HImode) even if it isn't.
7410 s -- print a shift double count, followed by the assemblers argument
7412 b -- print the QImode name of the register for the indicated operand.
7413 %b0 would print %al if operands[0] is reg 0.
7414 w -- likewise, print the HImode name of the register.
7415 k -- likewise, print the SImode name of the register.
7416 q -- likewise, print the DImode name of the register.
7417 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
7418 y -- print "st(0)" instead of "st" as a register.
7419 D -- print condition for SSE cmp instruction.
7420 P -- if PIC, print an @PLT suffix.
7421 X -- don't print any sort of PIC '@' suffix for a symbol.
7422 & -- print some in-use local-dynamic symbol name.
7423 H -- print a memory address offset by 8; used for sse high-parts
7427 print_operand (FILE *file, rtx x, int code)
7434 if (ASSEMBLER_DIALECT == ASM_ATT)
7439 assemble_name (file, get_some_local_dynamic_name ());
7443 switch (ASSEMBLER_DIALECT)
7450 /* Intel syntax. For absolute addresses, registers should not
7451 be surrounded by braces. */
7452 if (GET_CODE (x) != REG)
7455 PRINT_OPERAND (file, x, 0);
7465 PRINT_OPERAND (file, x, 0);
7470 if (ASSEMBLER_DIALECT == ASM_ATT)
7475 if (ASSEMBLER_DIALECT == ASM_ATT)
7480 if (ASSEMBLER_DIALECT == ASM_ATT)
7485 if (ASSEMBLER_DIALECT == ASM_ATT)
7490 if (ASSEMBLER_DIALECT == ASM_ATT)
7495 if (ASSEMBLER_DIALECT == ASM_ATT)
7500 /* 387 opcodes don't get size suffixes if the operands are
7502 if (STACK_REG_P (x))
7505 /* Likewise if using Intel opcodes. */
7506 if (ASSEMBLER_DIALECT == ASM_INTEL)
7509 /* This is the size of op from size of operand. */
7510 switch (GET_MODE_SIZE (GET_MODE (x)))
7513 #ifdef HAVE_GAS_FILDS_FISTS
7519 if (GET_MODE (x) == SFmode)
7534 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
7536 #ifdef GAS_MNEMONICS
7562 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
7564 PRINT_OPERAND (file, x, 0);
7570 /* Little bit of braindamage here. The SSE compare instructions
7571 does use completely different names for the comparisons that the
7572 fp conditional moves. */
7573 switch (GET_CODE (x))
7588 fputs ("unord", file);
7592 fputs ("neq", file);
7596 fputs ("nlt", file);
7600 fputs ("nle", file);
7603 fputs ("ord", file);
7610 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7611 if (ASSEMBLER_DIALECT == ASM_ATT)
7613 switch (GET_MODE (x))
7615 case HImode: putc ('w', file); break;
7617 case SFmode: putc ('l', file); break;
7619 case DFmode: putc ('q', file); break;
7620 default: gcc_unreachable ();
7627 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
7630 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7631 if (ASSEMBLER_DIALECT == ASM_ATT)
7634 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
7637 /* Like above, but reverse condition */
7639 /* Check to see if argument to %c is really a constant
7640 and not a condition code which needs to be reversed. */
7641 if (!COMPARISON_P (x))
7643 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
7646 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
7649 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7650 if (ASSEMBLER_DIALECT == ASM_ATT)
7653 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
7657 /* It doesn't actually matter what mode we use here, as we're
7658 only going to use this for printing. */
7659 x = adjust_address_nv (x, DImode, 8);
7666 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
7669 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
7672 int pred_val = INTVAL (XEXP (x, 0));
7674 if (pred_val < REG_BR_PROB_BASE * 45 / 100
7675 || pred_val > REG_BR_PROB_BASE * 55 / 100)
7677 int taken = pred_val > REG_BR_PROB_BASE / 2;
7678 int cputaken = final_forward_branch_p (current_output_insn) == 0;
7680 /* Emit hints only in the case default branch prediction
7681 heuristics would fail. */
7682 if (taken != cputaken)
7684 /* We use 3e (DS) prefix for taken branches and
7685 2e (CS) prefix for not taken branches. */
7687 fputs ("ds ; ", file);
7689 fputs ("cs ; ", file);
7696 output_operand_lossage ("invalid operand code '%c'", code);
7700 if (GET_CODE (x) == REG)
7701 print_reg (x, code, file);
7703 else if (GET_CODE (x) == MEM)
7705 /* No `byte ptr' prefix for call instructions. */
7706 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
7709 switch (GET_MODE_SIZE (GET_MODE (x)))
7711 case 1: size = "BYTE"; break;
7712 case 2: size = "WORD"; break;
7713 case 4: size = "DWORD"; break;
7714 case 8: size = "QWORD"; break;
7715 case 12: size = "XWORD"; break;
7716 case 16: size = "XMMWORD"; break;
7721 /* Check for explicit size override (codes 'b', 'w' and 'k') */
7724 else if (code == 'w')
7726 else if (code == 'k')
7730 fputs (" PTR ", file);
7734 /* Avoid (%rip) for call operands. */
7735 if (CONSTANT_ADDRESS_P (x) && code == 'P'
7736 && GET_CODE (x) != CONST_INT)
7737 output_addr_const (file, x);
7738 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
7739 output_operand_lossage ("invalid constraints for operand");
7744 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7749 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7750 REAL_VALUE_TO_TARGET_SINGLE (r, l);
7752 if (ASSEMBLER_DIALECT == ASM_ATT)
7754 fprintf (file, "0x%08lx", l);
7757 /* These float cases don't actually occur as immediate operands. */
7758 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7762 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7763 fprintf (file, "%s", dstr);
7766 else if (GET_CODE (x) == CONST_DOUBLE
7767 && GET_MODE (x) == XFmode)
7771 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7772 fprintf (file, "%s", dstr);
7777 /* We have patterns that allow zero sets of memory, for instance.
7778 In 64-bit mode, we should probably support all 8-byte vectors,
7779 since we can in fact encode that into an immediate. */
7780 if (GET_CODE (x) == CONST_VECTOR)
7782 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
7788 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
7790 if (ASSEMBLER_DIALECT == ASM_ATT)
7793 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
7794 || GET_CODE (x) == LABEL_REF)
7796 if (ASSEMBLER_DIALECT == ASM_ATT)
7799 fputs ("OFFSET FLAT:", file);
7802 if (GET_CODE (x) == CONST_INT)
7803 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7805 output_pic_addr_const (file, x, code);
7807 output_addr_const (file, x);
7811 /* Print a memory operand whose address is ADDR. */
7814 print_operand_address (FILE *file, rtx addr)
7816 struct ix86_address parts;
7817 rtx base, index, disp;
7819 int ok = ix86_decompose_address (addr, &parts);
7824 index = parts.index;
7826 scale = parts.scale;
7834 if (USER_LABEL_PREFIX[0] == 0)
7836 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
7842 if (!base && !index)
7844 /* Displacement only requires special attention. */
7846 if (GET_CODE (disp) == CONST_INT)
7848 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
7850 if (USER_LABEL_PREFIX[0] == 0)
7852 fputs ("ds:", file);
7854 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
7857 output_pic_addr_const (file, disp, 0);
7859 output_addr_const (file, disp);
7861 /* Use one byte shorter RIP relative addressing for 64bit mode. */
7864 if (GET_CODE (disp) == CONST
7865 && GET_CODE (XEXP (disp, 0)) == PLUS
7866 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7867 disp = XEXP (XEXP (disp, 0), 0);
7868 if (GET_CODE (disp) == LABEL_REF
7869 || (GET_CODE (disp) == SYMBOL_REF
7870 && SYMBOL_REF_TLS_MODEL (disp) == 0))
7871 fputs ("(%rip)", file);
7876 if (ASSEMBLER_DIALECT == ASM_ATT)
7881 output_pic_addr_const (file, disp, 0);
7882 else if (GET_CODE (disp) == LABEL_REF)
7883 output_asm_label (disp);
7885 output_addr_const (file, disp);
7890 print_reg (base, 0, file);
7894 print_reg (index, 0, file);
7896 fprintf (file, ",%d", scale);
7902 rtx offset = NULL_RTX;
7906 /* Pull out the offset of a symbol; print any symbol itself. */
7907 if (GET_CODE (disp) == CONST
7908 && GET_CODE (XEXP (disp, 0)) == PLUS
7909 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7911 offset = XEXP (XEXP (disp, 0), 1);
7912 disp = gen_rtx_CONST (VOIDmode,
7913 XEXP (XEXP (disp, 0), 0));
7917 output_pic_addr_const (file, disp, 0);
7918 else if (GET_CODE (disp) == LABEL_REF)
7919 output_asm_label (disp);
7920 else if (GET_CODE (disp) == CONST_INT)
7923 output_addr_const (file, disp);
7929 print_reg (base, 0, file);
7932 if (INTVAL (offset) >= 0)
7934 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7938 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7945 print_reg (index, 0, file);
7947 fprintf (file, "*%d", scale);
7955 output_addr_const_extra (FILE *file, rtx x)
7959 if (GET_CODE (x) != UNSPEC)
7962 op = XVECEXP (x, 0, 0);
7963 switch (XINT (x, 1))
7965 case UNSPEC_GOTTPOFF:
7966 output_addr_const (file, op);
7967 /* FIXME: This might be @TPOFF in Sun ld. */
7968 fputs ("@GOTTPOFF", file);
7971 output_addr_const (file, op);
7972 fputs ("@TPOFF", file);
7975 output_addr_const (file, op);
7977 fputs ("@TPOFF", file);
7979 fputs ("@NTPOFF", file);
7982 output_addr_const (file, op);
7983 fputs ("@DTPOFF", file);
7985 case UNSPEC_GOTNTPOFF:
7986 output_addr_const (file, op);
7988 fputs ("@GOTTPOFF(%rip)", file);
7990 fputs ("@GOTNTPOFF", file);
7992 case UNSPEC_INDNTPOFF:
7993 output_addr_const (file, op);
7994 fputs ("@INDNTPOFF", file);
8004 /* Split one or more DImode RTL references into pairs of SImode
8005 references. The RTL can be REG, offsettable MEM, integer constant, or
8006 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8007 split and "num" is its length. lo_half and hi_half are output arrays
8008 that parallel "operands". */
8011 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8015 rtx op = operands[num];
8017 /* simplify_subreg refuse to split volatile memory addresses,
8018 but we still have to handle it. */
8019 if (GET_CODE (op) == MEM)
8021 lo_half[num] = adjust_address (op, SImode, 0);
8022 hi_half[num] = adjust_address (op, SImode, 4);
8026 lo_half[num] = simplify_gen_subreg (SImode, op,
8027 GET_MODE (op) == VOIDmode
8028 ? DImode : GET_MODE (op), 0);
8029 hi_half[num] = simplify_gen_subreg (SImode, op,
8030 GET_MODE (op) == VOIDmode
8031 ? DImode : GET_MODE (op), 4);
8035 /* Split one or more TImode RTL references into pairs of DImode
8036 references. The RTL can be REG, offsettable MEM, integer constant, or
8037 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8038 split and "num" is its length. lo_half and hi_half are output arrays
8039 that parallel "operands". */
8042 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8046 rtx op = operands[num];
8048 /* simplify_subreg refuse to split volatile memory addresses, but we
8049 still have to handle it. */
8050 if (GET_CODE (op) == MEM)
8052 lo_half[num] = adjust_address (op, DImode, 0);
8053 hi_half[num] = adjust_address (op, DImode, 8);
8057 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
8058 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
8063 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8064 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8065 is the expression of the binary operation. The output may either be
8066 emitted here, or returned to the caller, like all output_* functions.
8068 There is no guarantee that the operands are the same mode, as they
8069 might be within FLOAT or FLOAT_EXTEND expressions. */
8071 #ifndef SYSV386_COMPAT
8072 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8073 wants to fix the assemblers because that causes incompatibility
8074 with gcc. No-one wants to fix gcc because that causes
8075 incompatibility with assemblers... You can use the option of
8076 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8077 #define SYSV386_COMPAT 1
8081 output_387_binary_op (rtx insn, rtx *operands)
8083 static char buf[30];
8086 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
8088 #ifdef ENABLE_CHECKING
8089 /* Even if we do not want to check the inputs, this documents input
8090 constraints. Which helps in understanding the following code. */
8091 if (STACK_REG_P (operands[0])
8092 && ((REG_P (operands[1])
8093 && REGNO (operands[0]) == REGNO (operands[1])
8094 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
8095 || (REG_P (operands[2])
8096 && REGNO (operands[0]) == REGNO (operands[2])
8097 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
8098 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
8101 gcc_assert (is_sse);
8104 switch (GET_CODE (operands[3]))
8107 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8108 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8116 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8117 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8125 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8126 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8134 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8135 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8149 if (GET_MODE (operands[0]) == SFmode)
8150 strcat (buf, "ss\t{%2, %0|%0, %2}");
8152 strcat (buf, "sd\t{%2, %0|%0, %2}");
8157 switch (GET_CODE (operands[3]))
8161 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
8163 rtx temp = operands[2];
8164 operands[2] = operands[1];
8168 /* know operands[0] == operands[1]. */
8170 if (GET_CODE (operands[2]) == MEM)
8176 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8178 if (STACK_TOP_P (operands[0]))
8179 /* How is it that we are storing to a dead operand[2]?
8180 Well, presumably operands[1] is dead too. We can't
8181 store the result to st(0) as st(0) gets popped on this
8182 instruction. Instead store to operands[2] (which I
8183 think has to be st(1)). st(1) will be popped later.
8184 gcc <= 2.8.1 didn't have this check and generated
8185 assembly code that the Unixware assembler rejected. */
8186 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8188 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8192 if (STACK_TOP_P (operands[0]))
8193 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8195 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8200 if (GET_CODE (operands[1]) == MEM)
8206 if (GET_CODE (operands[2]) == MEM)
8212 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8215 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
8216 derived assemblers, confusingly reverse the direction of
8217 the operation for fsub{r} and fdiv{r} when the
8218 destination register is not st(0). The Intel assembler
8219 doesn't have this brain damage. Read !SYSV386_COMPAT to
8220 figure out what the hardware really does. */
8221 if (STACK_TOP_P (operands[0]))
8222 p = "{p\t%0, %2|rp\t%2, %0}";
8224 p = "{rp\t%2, %0|p\t%0, %2}";
8226 if (STACK_TOP_P (operands[0]))
8227 /* As above for fmul/fadd, we can't store to st(0). */
8228 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8230 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8235 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
8238 if (STACK_TOP_P (operands[0]))
8239 p = "{rp\t%0, %1|p\t%1, %0}";
8241 p = "{p\t%1, %0|rp\t%0, %1}";
8243 if (STACK_TOP_P (operands[0]))
8244 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
8246 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
8251 if (STACK_TOP_P (operands[0]))
8253 if (STACK_TOP_P (operands[1]))
8254 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8256 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
8259 else if (STACK_TOP_P (operands[1]))
8262 p = "{\t%1, %0|r\t%0, %1}";
8264 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
8270 p = "{r\t%2, %0|\t%0, %2}";
8272 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8285 /* Return needed mode for entity in optimize_mode_switching pass. */
8288 ix86_mode_needed (int entity, rtx insn)
8290 enum attr_i387_cw mode;
8292 /* The mode UNINITIALIZED is used to store control word after a
8293 function call or ASM pattern. The mode ANY specify that function
8294 has no requirements on the control word and make no changes in the
8295 bits we are interested in. */
8298 || (NONJUMP_INSN_P (insn)
8299 && (asm_noperands (PATTERN (insn)) >= 0
8300 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
8301 return I387_CW_UNINITIALIZED;
8303 if (recog_memoized (insn) < 0)
8306 mode = get_attr_i387_cw (insn);
8311 if (mode == I387_CW_TRUNC)
8316 if (mode == I387_CW_FLOOR)
8321 if (mode == I387_CW_CEIL)
8326 if (mode == I387_CW_MASK_PM)
8337 /* Output code to initialize control word copies used by trunc?f?i and
8338 rounding patterns. CURRENT_MODE is set to current control word,
8339 while NEW_MODE is set to new control word. */
8342 emit_i387_cw_initialization (int mode)
8344 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
8349 rtx reg = gen_reg_rtx (HImode);
8351 emit_insn (gen_x86_fnstcw_1 (stored_mode));
8352 emit_move_insn (reg, stored_mode);
8354 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
8359 /* round toward zero (truncate) */
8360 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
8361 slot = SLOT_CW_TRUNC;
8365 /* round down toward -oo */
8366 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8367 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
8368 slot = SLOT_CW_FLOOR;
8372 /* round up toward +oo */
8373 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8374 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
8375 slot = SLOT_CW_CEIL;
8378 case I387_CW_MASK_PM:
8379 /* mask precision exception for nearbyint() */
8380 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8381 slot = SLOT_CW_MASK_PM;
8393 /* round toward zero (truncate) */
8394 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
8395 slot = SLOT_CW_TRUNC;
8399 /* round down toward -oo */
8400 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
8401 slot = SLOT_CW_FLOOR;
8405 /* round up toward +oo */
8406 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
8407 slot = SLOT_CW_CEIL;
8410 case I387_CW_MASK_PM:
8411 /* mask precision exception for nearbyint() */
8412 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8413 slot = SLOT_CW_MASK_PM;
8421 gcc_assert (slot < MAX_386_STACK_LOCALS);
8423 new_mode = assign_386_stack_local (HImode, slot);
8424 emit_move_insn (new_mode, reg);
8427 /* Output code for INSN to convert a float to a signed int. OPERANDS
8428 are the insn operands. The output may be [HSD]Imode and the input
8429 operand may be [SDX]Fmode. */
8432 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
8434 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8435 int dimode_p = GET_MODE (operands[0]) == DImode;
8436 int round_mode = get_attr_i387_cw (insn);
8438 /* Jump through a hoop or two for DImode, since the hardware has no
8439 non-popping instruction. We used to do this a different way, but
8440 that was somewhat fragile and broke with post-reload splitters. */
8441 if ((dimode_p || fisttp) && !stack_top_dies)
8442 output_asm_insn ("fld\t%y1", operands);
8444 gcc_assert (STACK_TOP_P (operands[1]));
8445 gcc_assert (GET_CODE (operands[0]) == MEM);
8448 output_asm_insn ("fisttp%z0\t%0", operands);
8451 if (round_mode != I387_CW_ANY)
8452 output_asm_insn ("fldcw\t%3", operands);
8453 if (stack_top_dies || dimode_p)
8454 output_asm_insn ("fistp%z0\t%0", operands);
8456 output_asm_insn ("fist%z0\t%0", operands);
8457 if (round_mode != I387_CW_ANY)
8458 output_asm_insn ("fldcw\t%2", operands);
8464 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
8465 should be used. UNORDERED_P is true when fucom should be used. */
8468 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
8471 rtx cmp_op0, cmp_op1;
8472 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
8476 cmp_op0 = operands[0];
8477 cmp_op1 = operands[1];
8481 cmp_op0 = operands[1];
8482 cmp_op1 = operands[2];
8487 if (GET_MODE (operands[0]) == SFmode)
8489 return "ucomiss\t{%1, %0|%0, %1}";
8491 return "comiss\t{%1, %0|%0, %1}";
8494 return "ucomisd\t{%1, %0|%0, %1}";
8496 return "comisd\t{%1, %0|%0, %1}";
8499 gcc_assert (STACK_TOP_P (cmp_op0));
8501 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8503 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
8507 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
8508 return TARGET_USE_FFREEP ? "ffreep\t%y1" : "fstp\t%y1";
8511 return "ftst\n\tfnstsw\t%0";
8514 if (STACK_REG_P (cmp_op1)
8516 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
8517 && REGNO (cmp_op1) != FIRST_STACK_REG)
8519 /* If both the top of the 387 stack dies, and the other operand
8520 is also a stack register that dies, then this must be a
8521 `fcompp' float compare */
8525 /* There is no double popping fcomi variant. Fortunately,
8526 eflags is immune from the fstp's cc clobbering. */
8528 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
8530 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
8531 return TARGET_USE_FFREEP ? "ffreep\t%y0" : "fstp\t%y0";
8536 return "fucompp\n\tfnstsw\t%0";
8538 return "fcompp\n\tfnstsw\t%0";
8543 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
8545 static const char * const alt[16] =
8547 "fcom%z2\t%y2\n\tfnstsw\t%0",
8548 "fcomp%z2\t%y2\n\tfnstsw\t%0",
8549 "fucom%z2\t%y2\n\tfnstsw\t%0",
8550 "fucomp%z2\t%y2\n\tfnstsw\t%0",
8552 "ficom%z2\t%y2\n\tfnstsw\t%0",
8553 "ficomp%z2\t%y2\n\tfnstsw\t%0",
8557 "fcomi\t{%y1, %0|%0, %y1}",
8558 "fcomip\t{%y1, %0|%0, %y1}",
8559 "fucomi\t{%y1, %0|%0, %y1}",
8560 "fucomip\t{%y1, %0|%0, %y1}",
8571 mask = eflags_p << 3;
8572 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
8573 mask |= unordered_p << 1;
8574 mask |= stack_top_dies;
8576 gcc_assert (mask < 16);
8585 ix86_output_addr_vec_elt (FILE *file, int value)
8587 const char *directive = ASM_LONG;
8591 directive = ASM_QUAD;
8593 gcc_assert (!TARGET_64BIT);
8596 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
8600 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
8603 fprintf (file, "%s%s%d-%s%d\n",
8604 ASM_LONG, LPREFIX, value, LPREFIX, rel);
8605 else if (HAVE_AS_GOTOFF_IN_DATA)
8606 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
8608 else if (TARGET_MACHO)
8610 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
8611 machopic_output_function_base_name (file);
8612 fprintf(file, "\n");
8616 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
8617 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
8620 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
8624 ix86_expand_clear (rtx dest)
8628 /* We play register width games, which are only valid after reload. */
8629 gcc_assert (reload_completed);
8631 /* Avoid HImode and its attendant prefix byte. */
8632 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
8633 dest = gen_rtx_REG (SImode, REGNO (dest));
8635 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
8637 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
8638 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
8640 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
8641 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
8647 /* X is an unchanging MEM. If it is a constant pool reference, return
8648 the constant pool rtx, else NULL. */
8651 maybe_get_pool_constant (rtx x)
8653 x = ix86_delegitimize_address (XEXP (x, 0));
8655 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
8656 return get_pool_constant (x);
8662 ix86_expand_move (enum machine_mode mode, rtx operands[])
8664 int strict = (reload_in_progress || reload_completed);
8666 enum tls_model model;
8671 if (GET_CODE (op1) == SYMBOL_REF)
8673 model = SYMBOL_REF_TLS_MODEL (op1);
8676 op1 = legitimize_tls_address (op1, model, true);
8677 op1 = force_operand (op1, op0);
8682 else if (GET_CODE (op1) == CONST
8683 && GET_CODE (XEXP (op1, 0)) == PLUS
8684 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
8686 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
8689 rtx addend = XEXP (XEXP (op1, 0), 1);
8690 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
8691 op1 = force_operand (op1, NULL);
8692 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
8693 op0, 1, OPTAB_DIRECT);
8699 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
8704 rtx temp = ((reload_in_progress
8705 || ((op0 && GET_CODE (op0) == REG)
8707 ? op0 : gen_reg_rtx (Pmode));
8708 op1 = machopic_indirect_data_reference (op1, temp);
8709 op1 = machopic_legitimize_pic_address (op1, mode,
8710 temp == op1 ? 0 : temp);
8712 else if (MACHOPIC_INDIRECT)
8713 op1 = machopic_indirect_data_reference (op1, 0);
8717 if (GET_CODE (op0) == MEM)
8718 op1 = force_reg (Pmode, op1);
8720 op1 = legitimize_address (op1, op1, Pmode);
8721 #endif /* TARGET_MACHO */
8725 if (GET_CODE (op0) == MEM
8726 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
8727 || !push_operand (op0, mode))
8728 && GET_CODE (op1) == MEM)
8729 op1 = force_reg (mode, op1);
8731 if (push_operand (op0, mode)
8732 && ! general_no_elim_operand (op1, mode))
8733 op1 = copy_to_mode_reg (mode, op1);
8735 /* Force large constants in 64bit compilation into register
8736 to get them CSEed. */
8737 if (TARGET_64BIT && mode == DImode
8738 && immediate_operand (op1, mode)
8739 && !x86_64_zext_immediate_operand (op1, VOIDmode)
8740 && !register_operand (op0, mode)
8741 && optimize && !reload_completed && !reload_in_progress)
8742 op1 = copy_to_mode_reg (mode, op1);
8744 if (FLOAT_MODE_P (mode))
8746 /* If we are loading a floating point constant to a register,
8747 force the value to memory now, since we'll get better code
8748 out the back end. */
8752 else if (GET_CODE (op1) == CONST_DOUBLE)
8754 op1 = validize_mem (force_const_mem (mode, op1));
8755 if (!register_operand (op0, mode))
8757 rtx temp = gen_reg_rtx (mode);
8758 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
8759 emit_move_insn (op0, temp);
8766 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8770 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
8772 rtx op0 = operands[0], op1 = operands[1];
8774 /* Force constants other than zero into memory. We do not know how
8775 the instructions used to build constants modify the upper 64 bits
8776 of the register, once we have that information we may be able
8777 to handle some of them more efficiently. */
8778 if ((reload_in_progress | reload_completed) == 0
8779 && register_operand (op0, mode)
8780 && CONSTANT_P (op1) && op1 != CONST0_RTX (mode))
8781 op1 = validize_mem (force_const_mem (mode, op1));
8783 /* Make operand1 a register if it isn't already. */
8785 && !register_operand (op0, mode)
8786 && !register_operand (op1, mode))
8788 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
8792 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8795 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
8796 straight to ix86_expand_vector_move. */
8799 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
8808 /* If we're optimizing for size, movups is the smallest. */
8811 op0 = gen_lowpart (V4SFmode, op0);
8812 op1 = gen_lowpart (V4SFmode, op1);
8813 emit_insn (gen_sse_movups (op0, op1));
8817 /* ??? If we have typed data, then it would appear that using
8818 movdqu is the only way to get unaligned data loaded with
8820 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8822 op0 = gen_lowpart (V16QImode, op0);
8823 op1 = gen_lowpart (V16QImode, op1);
8824 emit_insn (gen_sse2_movdqu (op0, op1));
8828 if (TARGET_SSE2 && mode == V2DFmode)
8832 /* When SSE registers are split into halves, we can avoid
8833 writing to the top half twice. */
8834 if (TARGET_SSE_SPLIT_REGS)
8836 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8841 /* ??? Not sure about the best option for the Intel chips.
8842 The following would seem to satisfy; the register is
8843 entirely cleared, breaking the dependency chain. We
8844 then store to the upper half, with a dependency depth
8845 of one. A rumor has it that Intel recommends two movsd
8846 followed by an unpacklpd, but this is unconfirmed. And
8847 given that the dependency depth of the unpacklpd would
8848 still be one, I'm not sure why this would be better. */
8849 zero = CONST0_RTX (V2DFmode);
8852 m = adjust_address (op1, DFmode, 0);
8853 emit_insn (gen_sse2_loadlpd (op0, zero, m));
8854 m = adjust_address (op1, DFmode, 8);
8855 emit_insn (gen_sse2_loadhpd (op0, op0, m));
8859 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
8860 emit_move_insn (op0, CONST0_RTX (mode));
8862 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8864 if (mode != V4SFmode)
8865 op0 = gen_lowpart (V4SFmode, op0);
8866 m = adjust_address (op1, V2SFmode, 0);
8867 emit_insn (gen_sse_loadlps (op0, op0, m));
8868 m = adjust_address (op1, V2SFmode, 8);
8869 emit_insn (gen_sse_loadhps (op0, op0, m));
8872 else if (MEM_P (op0))
8874 /* If we're optimizing for size, movups is the smallest. */
8877 op0 = gen_lowpart (V4SFmode, op0);
8878 op1 = gen_lowpart (V4SFmode, op1);
8879 emit_insn (gen_sse_movups (op0, op1));
8883 /* ??? Similar to above, only less clear because of quote
8884 typeless stores unquote. */
8885 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
8886 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8888 op0 = gen_lowpart (V16QImode, op0);
8889 op1 = gen_lowpart (V16QImode, op1);
8890 emit_insn (gen_sse2_movdqu (op0, op1));
8894 if (TARGET_SSE2 && mode == V2DFmode)
8896 m = adjust_address (op0, DFmode, 0);
8897 emit_insn (gen_sse2_storelpd (m, op1));
8898 m = adjust_address (op0, DFmode, 8);
8899 emit_insn (gen_sse2_storehpd (m, op1));
8903 if (mode != V4SFmode)
8904 op1 = gen_lowpart (V4SFmode, op1);
8905 m = adjust_address (op0, V2SFmode, 0);
8906 emit_insn (gen_sse_storelps (m, op1));
8907 m = adjust_address (op0, V2SFmode, 8);
8908 emit_insn (gen_sse_storehps (m, op1));
8915 /* Expand a push in MODE. This is some mode for which we do not support
8916 proper push instructions, at least from the registers that we expect
8917 the value to live in. */
8920 ix86_expand_push (enum machine_mode mode, rtx x)
8924 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
8925 GEN_INT (-GET_MODE_SIZE (mode)),
8926 stack_pointer_rtx, 1, OPTAB_DIRECT);
8927 if (tmp != stack_pointer_rtx)
8928 emit_move_insn (stack_pointer_rtx, tmp);
8930 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
8931 emit_move_insn (tmp, x);
8934 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
8935 destination to use for the operation. If different from the true
8936 destination in operands[0], a copy operation will be required. */
8939 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
8942 int matching_memory;
8943 rtx src1, src2, dst;
8949 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
8950 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8951 && (rtx_equal_p (dst, src2)
8952 || immediate_operand (src1, mode)))
8959 /* If the destination is memory, and we do not have matching source
8960 operands, do things in registers. */
8961 matching_memory = 0;
8962 if (GET_CODE (dst) == MEM)
8964 if (rtx_equal_p (dst, src1))
8965 matching_memory = 1;
8966 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8967 && rtx_equal_p (dst, src2))
8968 matching_memory = 2;
8970 dst = gen_reg_rtx (mode);
8973 /* Both source operands cannot be in memory. */
8974 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
8976 if (matching_memory != 2)
8977 src2 = force_reg (mode, src2);
8979 src1 = force_reg (mode, src1);
8982 /* If the operation is not commutable, source 1 cannot be a constant
8983 or non-matching memory. */
8984 if ((CONSTANT_P (src1)
8985 || (!matching_memory && GET_CODE (src1) == MEM))
8986 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8987 src1 = force_reg (mode, src1);
8989 src1 = operands[1] = src1;
8990 src2 = operands[2] = src2;
8994 /* Similarly, but assume that the destination has already been
8998 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
8999 enum machine_mode mode, rtx operands[])
9001 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
9002 gcc_assert (dst == operands[0]);
9005 /* Attempt to expand a binary operator. Make the expansion closer to the
9006 actual machine, then just general_operand, which will allow 3 separate
9007 memory references (one output, two input) in a single insn. */
9010 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
9013 rtx src1, src2, dst, op, clob;
9015 dst = ix86_fixup_binary_operands (code, mode, operands);
9019 /* Emit the instruction. */
9021 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
9022 if (reload_in_progress)
9024 /* Reload doesn't know about the flags register, and doesn't know that
9025 it doesn't want to clobber it. We can only do this with PLUS. */
9026 gcc_assert (code == PLUS);
9031 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9032 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9035 /* Fix up the destination if needed. */
9036 if (dst != operands[0])
9037 emit_move_insn (operands[0], dst);
9040 /* Return TRUE or FALSE depending on whether the binary operator meets the
9041 appropriate constraints. */
9044 ix86_binary_operator_ok (enum rtx_code code,
9045 enum machine_mode mode ATTRIBUTE_UNUSED,
9048 /* Both source operands cannot be in memory. */
9049 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
9051 /* If the operation is not commutable, source 1 cannot be a constant. */
9052 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
9054 /* If the destination is memory, we must have a matching source operand. */
9055 if (GET_CODE (operands[0]) == MEM
9056 && ! (rtx_equal_p (operands[0], operands[1])
9057 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9058 && rtx_equal_p (operands[0], operands[2]))))
9060 /* If the operation is not commutable and the source 1 is memory, we must
9061 have a matching destination. */
9062 if (GET_CODE (operands[1]) == MEM
9063 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
9064 && ! rtx_equal_p (operands[0], operands[1]))
9069 /* Attempt to expand a unary operator. Make the expansion closer to the
9070 actual machine, then just general_operand, which will allow 2 separate
9071 memory references (one output, one input) in a single insn. */
9074 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
9077 int matching_memory;
9078 rtx src, dst, op, clob;
9083 /* If the destination is memory, and we do not have matching source
9084 operands, do things in registers. */
9085 matching_memory = 0;
9088 if (rtx_equal_p (dst, src))
9089 matching_memory = 1;
9091 dst = gen_reg_rtx (mode);
9094 /* When source operand is memory, destination must match. */
9095 if (MEM_P (src) && !matching_memory)
9096 src = force_reg (mode, src);
9098 /* Emit the instruction. */
9100 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
9101 if (reload_in_progress || code == NOT)
9103 /* Reload doesn't know about the flags register, and doesn't know that
9104 it doesn't want to clobber it. */
9105 gcc_assert (code == NOT);
9110 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9111 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9114 /* Fix up the destination if needed. */
9115 if (dst != operands[0])
9116 emit_move_insn (operands[0], dst);
9119 /* Return TRUE or FALSE depending on whether the unary operator meets the
9120 appropriate constraints. */
9123 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
9124 enum machine_mode mode ATTRIBUTE_UNUSED,
9125 rtx operands[2] ATTRIBUTE_UNUSED)
9127 /* If one of operands is memory, source and destination must match. */
9128 if ((GET_CODE (operands[0]) == MEM
9129 || GET_CODE (operands[1]) == MEM)
9130 && ! rtx_equal_p (operands[0], operands[1]))
9135 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
9136 Create a mask for the sign bit in MODE for an SSE register. If VECT is
9137 true, then replicate the mask for all elements of the vector register.
9138 If INVERT is true, then create a mask excluding the sign bit. */
9141 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
9143 enum machine_mode vec_mode;
9144 HOST_WIDE_INT hi, lo;
9149 /* Find the sign bit, sign extended to 2*HWI. */
9151 lo = 0x80000000, hi = lo < 0;
9152 else if (HOST_BITS_PER_WIDE_INT >= 64)
9153 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
9155 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
9160 /* Force this value into the low part of a fp vector constant. */
9161 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
9162 mask = gen_lowpart (mode, mask);
9167 v = gen_rtvec (4, mask, mask, mask, mask);
9169 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
9170 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9171 vec_mode = V4SFmode;
9176 v = gen_rtvec (2, mask, mask);
9178 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
9179 vec_mode = V2DFmode;
9182 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
9185 /* Generate code for floating point ABS or NEG. */
9188 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
9191 rtx mask, set, use, clob, dst, src;
9192 bool matching_memory;
9193 bool use_sse = false;
9194 bool vector_mode = VECTOR_MODE_P (mode);
9195 enum machine_mode elt_mode = mode;
9199 elt_mode = GET_MODE_INNER (mode);
9202 else if (TARGET_SSE_MATH)
9203 use_sse = SSE_FLOAT_MODE_P (mode);
9205 /* NEG and ABS performed with SSE use bitwise mask operations.
9206 Create the appropriate mask now. */
9208 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
9211 /* When not using SSE, we don't use the mask, but prefer to keep the
9212 same general form of the insn pattern to reduce duplication when
9213 it comes time to split. */
9220 /* If the destination is memory, and we don't have matching source
9221 operands, do things in registers. */
9222 matching_memory = false;
9225 if (rtx_equal_p (dst, src))
9226 matching_memory = true;
9228 dst = gen_reg_rtx (mode);
9230 if (MEM_P (src) && !matching_memory)
9231 src = force_reg (mode, src);
9235 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
9236 set = gen_rtx_SET (VOIDmode, dst, set);
9241 set = gen_rtx_fmt_e (code, mode, src);
9242 set = gen_rtx_SET (VOIDmode, dst, set);
9243 use = gen_rtx_USE (VOIDmode, mask);
9244 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9245 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, set, use, clob)));
9248 if (dst != operands[0])
9249 emit_move_insn (operands[0], dst);
9252 /* Expand a copysign operation. Special case operand 0 being a constant. */
9255 ix86_expand_copysign (rtx operands[])
9257 enum machine_mode mode, vmode;
9258 rtx dest, op0, op1, mask, nmask;
9264 mode = GET_MODE (dest);
9265 vmode = mode == SFmode ? V4SFmode : V2DFmode;
9267 if (GET_CODE (op0) == CONST_DOUBLE)
9271 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
9272 op0 = simplify_unary_operation (ABS, mode, op0, mode);
9274 if (op0 == CONST0_RTX (mode))
9275 op0 = CONST0_RTX (vmode);
9279 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
9280 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9282 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
9283 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
9286 mask = ix86_build_signbit_mask (mode, 0, 0);
9289 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
9291 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
9295 nmask = ix86_build_signbit_mask (mode, 0, 1);
9296 mask = ix86_build_signbit_mask (mode, 0, 0);
9299 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
9301 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
9305 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
9306 be a constant, and so has already been expanded into a vector constant. */
9309 ix86_split_copysign_const (rtx operands[])
9311 enum machine_mode mode, vmode;
9312 rtx dest, op0, op1, mask, x;
9319 mode = GET_MODE (dest);
9320 vmode = GET_MODE (mask);
9322 dest = simplify_gen_subreg (vmode, dest, mode, 0);
9323 x = gen_rtx_AND (vmode, dest, mask);
9324 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9326 if (op0 != CONST0_RTX (vmode))
9328 x = gen_rtx_IOR (vmode, dest, op0);
9329 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9333 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
9334 so we have to do two masks. */
9337 ix86_split_copysign_var (rtx operands[])
9339 enum machine_mode mode, vmode;
9340 rtx dest, scratch, op0, op1, mask, nmask, x;
9343 scratch = operands[1];
9346 nmask = operands[4];
9349 mode = GET_MODE (dest);
9350 vmode = GET_MODE (mask);
9352 if (rtx_equal_p (op0, op1))
9354 /* Shouldn't happen often (it's useless, obviously), but when it does
9355 we'd generate incorrect code if we continue below. */
9356 emit_move_insn (dest, op0);
9360 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
9362 gcc_assert (REGNO (op1) == REGNO (scratch));
9364 x = gen_rtx_AND (vmode, scratch, mask);
9365 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9368 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9369 x = gen_rtx_NOT (vmode, dest);
9370 x = gen_rtx_AND (vmode, x, op0);
9371 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9375 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
9377 x = gen_rtx_AND (vmode, scratch, mask);
9379 else /* alternative 2,4 */
9381 gcc_assert (REGNO (mask) == REGNO (scratch));
9382 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
9383 x = gen_rtx_AND (vmode, scratch, op1);
9385 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9387 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
9389 dest = simplify_gen_subreg (vmode, op0, mode, 0);
9390 x = gen_rtx_AND (vmode, dest, nmask);
9392 else /* alternative 3,4 */
9394 gcc_assert (REGNO (nmask) == REGNO (dest));
9396 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9397 x = gen_rtx_AND (vmode, dest, op0);
9399 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9402 x = gen_rtx_IOR (vmode, dest, scratch);
9403 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9406 /* Return TRUE or FALSE depending on whether the first SET in INSN
9407 has source and destination with matching CC modes, and that the
9408 CC mode is at least as constrained as REQ_MODE. */
9411 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
9414 enum machine_mode set_mode;
9416 set = PATTERN (insn);
9417 if (GET_CODE (set) == PARALLEL)
9418 set = XVECEXP (set, 0, 0);
9419 gcc_assert (GET_CODE (set) == SET);
9420 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
9422 set_mode = GET_MODE (SET_DEST (set));
9426 if (req_mode != CCNOmode
9427 && (req_mode != CCmode
9428 || XEXP (SET_SRC (set), 1) != const0_rtx))
9432 if (req_mode == CCGCmode)
9436 if (req_mode == CCGOCmode || req_mode == CCNOmode)
9440 if (req_mode == CCZmode)
9450 return (GET_MODE (SET_SRC (set)) == set_mode);
9453 /* Generate insn patterns to do an integer compare of OPERANDS. */
9456 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
9458 enum machine_mode cmpmode;
9461 cmpmode = SELECT_CC_MODE (code, op0, op1);
9462 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
9464 /* This is very simple, but making the interface the same as in the
9465 FP case makes the rest of the code easier. */
9466 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
9467 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
9469 /* Return the test that should be put into the flags user, i.e.
9470 the bcc, scc, or cmov instruction. */
9471 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
9474 /* Figure out whether to use ordered or unordered fp comparisons.
9475 Return the appropriate mode to use. */
9478 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
9480 /* ??? In order to make all comparisons reversible, we do all comparisons
9481 non-trapping when compiling for IEEE. Once gcc is able to distinguish
9482 all forms trapping and nontrapping comparisons, we can make inequality
9483 comparisons trapping again, since it results in better code when using
9484 FCOM based compares. */
9485 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
9489 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
9491 if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
9492 return ix86_fp_compare_mode (code);
9495 /* Only zero flag is needed. */
9497 case NE: /* ZF!=0 */
9499 /* Codes needing carry flag. */
9500 case GEU: /* CF=0 */
9501 case GTU: /* CF=0 & ZF=0 */
9502 case LTU: /* CF=1 */
9503 case LEU: /* CF=1 | ZF=1 */
9505 /* Codes possibly doable only with sign flag when
9506 comparing against zero. */
9507 case GE: /* SF=OF or SF=0 */
9508 case LT: /* SF<>OF or SF=1 */
9509 if (op1 == const0_rtx)
9512 /* For other cases Carry flag is not required. */
9514 /* Codes doable only with sign flag when comparing
9515 against zero, but we miss jump instruction for it
9516 so we need to use relational tests against overflow
9517 that thus needs to be zero. */
9518 case GT: /* ZF=0 & SF=OF */
9519 case LE: /* ZF=1 | SF<>OF */
9520 if (op1 == const0_rtx)
9524 /* strcmp pattern do (use flags) and combine may ask us for proper
9533 /* Return the fixed registers used for condition codes. */
9536 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9543 /* If two condition code modes are compatible, return a condition code
9544 mode which is compatible with both. Otherwise, return
9547 static enum machine_mode
9548 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
9553 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
9556 if ((m1 == CCGCmode && m2 == CCGOCmode)
9557 || (m1 == CCGOCmode && m2 == CCGCmode))
9585 /* These are only compatible with themselves, which we already
9591 /* Return true if we should use an FCOMI instruction for this fp comparison. */
9594 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
9596 enum rtx_code swapped_code = swap_condition (code);
9597 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
9598 || (ix86_fp_comparison_cost (swapped_code)
9599 == ix86_fp_comparison_fcomi_cost (swapped_code)));
9602 /* Swap, force into registers, or otherwise massage the two operands
9603 to a fp comparison. The operands are updated in place; the new
9604 comparison code is returned. */
9606 static enum rtx_code
9607 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
9609 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
9610 rtx op0 = *pop0, op1 = *pop1;
9611 enum machine_mode op_mode = GET_MODE (op0);
9612 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
9614 /* All of the unordered compare instructions only work on registers.
9615 The same is true of the fcomi compare instructions. The XFmode
9616 compare instructions require registers except when comparing
9617 against zero or when converting operand 1 from fixed point to
9621 && (fpcmp_mode == CCFPUmode
9622 || (op_mode == XFmode
9623 && ! (standard_80387_constant_p (op0) == 1
9624 || standard_80387_constant_p (op1) == 1)
9625 && GET_CODE (op1) != FLOAT)
9626 || ix86_use_fcomi_compare (code)))
9628 op0 = force_reg (op_mode, op0);
9629 op1 = force_reg (op_mode, op1);
9633 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
9634 things around if they appear profitable, otherwise force op0
9637 if (standard_80387_constant_p (op0) == 0
9638 || (GET_CODE (op0) == MEM
9639 && ! (standard_80387_constant_p (op1) == 0
9640 || GET_CODE (op1) == MEM)))
9643 tmp = op0, op0 = op1, op1 = tmp;
9644 code = swap_condition (code);
9647 if (GET_CODE (op0) != REG)
9648 op0 = force_reg (op_mode, op0);
9650 if (CONSTANT_P (op1))
9652 int tmp = standard_80387_constant_p (op1);
9654 op1 = validize_mem (force_const_mem (op_mode, op1));
9658 op1 = force_reg (op_mode, op1);
9661 op1 = force_reg (op_mode, op1);
9665 /* Try to rearrange the comparison to make it cheaper. */
9666 if (ix86_fp_comparison_cost (code)
9667 > ix86_fp_comparison_cost (swap_condition (code))
9668 && (GET_CODE (op1) == REG || !no_new_pseudos))
9671 tmp = op0, op0 = op1, op1 = tmp;
9672 code = swap_condition (code);
9673 if (GET_CODE (op0) != REG)
9674 op0 = force_reg (op_mode, op0);
9682 /* Convert comparison codes we use to represent FP comparison to integer
9683 code that will result in proper branch. Return UNKNOWN if no such code
9687 ix86_fp_compare_code_to_integer (enum rtx_code code)
9716 /* Split comparison code CODE into comparisons we can do using branch
9717 instructions. BYPASS_CODE is comparison code for branch that will
9718 branch around FIRST_CODE and SECOND_CODE. If some of branches
9719 is not required, set value to UNKNOWN.
9720 We never require more than two branches. */
9723 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
9724 enum rtx_code *first_code,
9725 enum rtx_code *second_code)
9728 *bypass_code = UNKNOWN;
9729 *second_code = UNKNOWN;
9731 /* The fcomi comparison sets flags as follows:
9741 case GT: /* GTU - CF=0 & ZF=0 */
9742 case GE: /* GEU - CF=0 */
9743 case ORDERED: /* PF=0 */
9744 case UNORDERED: /* PF=1 */
9745 case UNEQ: /* EQ - ZF=1 */
9746 case UNLT: /* LTU - CF=1 */
9747 case UNLE: /* LEU - CF=1 | ZF=1 */
9748 case LTGT: /* EQ - ZF=0 */
9750 case LT: /* LTU - CF=1 - fails on unordered */
9752 *bypass_code = UNORDERED;
9754 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
9756 *bypass_code = UNORDERED;
9758 case EQ: /* EQ - ZF=1 - fails on unordered */
9760 *bypass_code = UNORDERED;
9762 case NE: /* NE - ZF=0 - fails on unordered */
9764 *second_code = UNORDERED;
9766 case UNGE: /* GEU - CF=0 - fails on unordered */
9768 *second_code = UNORDERED;
9770 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
9772 *second_code = UNORDERED;
9777 if (!TARGET_IEEE_FP)
9779 *second_code = UNKNOWN;
9780 *bypass_code = UNKNOWN;
9784 /* Return cost of comparison done fcom + arithmetics operations on AX.
9785 All following functions do use number of instructions as a cost metrics.
9786 In future this should be tweaked to compute bytes for optimize_size and
9787 take into account performance of various instructions on various CPUs. */
9789 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
9791 if (!TARGET_IEEE_FP)
9793 /* The cost of code output by ix86_expand_fp_compare. */
9821 /* Return cost of comparison done using fcomi operation.
9822 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9824 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
9826 enum rtx_code bypass_code, first_code, second_code;
9827 /* Return arbitrarily high cost when instruction is not supported - this
9828 prevents gcc from using it. */
9831 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9832 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
9835 /* Return cost of comparison done using sahf operation.
9836 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9838 ix86_fp_comparison_sahf_cost (enum rtx_code code)
9840 enum rtx_code bypass_code, first_code, second_code;
9841 /* Return arbitrarily high cost when instruction is not preferred - this
9842 avoids gcc from using it. */
9843 if (!TARGET_USE_SAHF && !optimize_size)
9845 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9846 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
9849 /* Compute cost of the comparison done using any method.
9850 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9852 ix86_fp_comparison_cost (enum rtx_code code)
9854 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
9857 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
9858 sahf_cost = ix86_fp_comparison_sahf_cost (code);
9860 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
9861 if (min > sahf_cost)
9863 if (min > fcomi_cost)
9868 /* Generate insn patterns to do a floating point compare of OPERANDS. */
9871 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
9872 rtx *second_test, rtx *bypass_test)
9874 enum machine_mode fpcmp_mode, intcmp_mode;
9876 int cost = ix86_fp_comparison_cost (code);
9877 enum rtx_code bypass_code, first_code, second_code;
9879 fpcmp_mode = ix86_fp_compare_mode (code);
9880 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
9883 *second_test = NULL_RTX;
9885 *bypass_test = NULL_RTX;
9887 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9889 /* Do fcomi/sahf based test when profitable. */
9890 if ((bypass_code == UNKNOWN || bypass_test)
9891 && (second_code == UNKNOWN || second_test)
9892 && ix86_fp_comparison_arithmetics_cost (code) > cost)
9896 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9897 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
9903 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9904 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9906 scratch = gen_reg_rtx (HImode);
9907 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9908 emit_insn (gen_x86_sahf_1 (scratch));
9911 /* The FP codes work out to act like unsigned. */
9912 intcmp_mode = fpcmp_mode;
9914 if (bypass_code != UNKNOWN)
9915 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
9916 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9918 if (second_code != UNKNOWN)
9919 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
9920 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9925 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
9926 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9927 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9929 scratch = gen_reg_rtx (HImode);
9930 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9932 /* In the unordered case, we have to check C2 for NaN's, which
9933 doesn't happen to work out to anything nice combination-wise.
9934 So do some bit twiddling on the value we've got in AH to come
9935 up with an appropriate set of condition codes. */
9937 intcmp_mode = CCNOmode;
9942 if (code == GT || !TARGET_IEEE_FP)
9944 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9949 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9950 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9951 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
9952 intcmp_mode = CCmode;
9958 if (code == LT && TARGET_IEEE_FP)
9960 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9961 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
9962 intcmp_mode = CCmode;
9967 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
9973 if (code == GE || !TARGET_IEEE_FP)
9975 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
9980 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9981 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9988 if (code == LE && TARGET_IEEE_FP)
9990 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9991 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9992 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9993 intcmp_mode = CCmode;
9998 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
10004 if (code == EQ && TARGET_IEEE_FP)
10006 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10007 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
10008 intcmp_mode = CCmode;
10013 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10020 if (code == NE && TARGET_IEEE_FP)
10022 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10023 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
10029 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10035 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10039 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10044 gcc_unreachable ();
10048 /* Return the test that should be put into the flags user, i.e.
10049 the bcc, scc, or cmov instruction. */
10050 return gen_rtx_fmt_ee (code, VOIDmode,
10051 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10056 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
10059 op0 = ix86_compare_op0;
10060 op1 = ix86_compare_op1;
10063 *second_test = NULL_RTX;
10065 *bypass_test = NULL_RTX;
10067 if (ix86_compare_emitted)
10069 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
10070 ix86_compare_emitted = NULL_RTX;
10072 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
10073 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10074 second_test, bypass_test);
10076 ret = ix86_expand_int_compare (code, op0, op1);
10081 /* Return true if the CODE will result in nontrivial jump sequence. */
10083 ix86_fp_jump_nontrivial_p (enum rtx_code code)
10085 enum rtx_code bypass_code, first_code, second_code;
10088 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10089 return bypass_code != UNKNOWN || second_code != UNKNOWN;
10093 ix86_expand_branch (enum rtx_code code, rtx label)
10097 switch (GET_MODE (ix86_compare_op0))
10103 tmp = ix86_expand_compare (code, NULL, NULL);
10104 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10105 gen_rtx_LABEL_REF (VOIDmode, label),
10107 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10116 enum rtx_code bypass_code, first_code, second_code;
10118 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
10119 &ix86_compare_op1);
10121 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10123 /* Check whether we will use the natural sequence with one jump. If
10124 so, we can expand jump early. Otherwise delay expansion by
10125 creating compound insn to not confuse optimizers. */
10126 if (bypass_code == UNKNOWN && second_code == UNKNOWN
10129 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
10130 gen_rtx_LABEL_REF (VOIDmode, label),
10131 pc_rtx, NULL_RTX, NULL_RTX);
10135 tmp = gen_rtx_fmt_ee (code, VOIDmode,
10136 ix86_compare_op0, ix86_compare_op1);
10137 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10138 gen_rtx_LABEL_REF (VOIDmode, label),
10140 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
10142 use_fcomi = ix86_use_fcomi_compare (code);
10143 vec = rtvec_alloc (3 + !use_fcomi);
10144 RTVEC_ELT (vec, 0) = tmp;
10146 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
10148 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
10151 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
10153 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
10162 /* Expand DImode branch into multiple compare+branch. */
10164 rtx lo[2], hi[2], label2;
10165 enum rtx_code code1, code2, code3;
10166 enum machine_mode submode;
10168 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
10170 tmp = ix86_compare_op0;
10171 ix86_compare_op0 = ix86_compare_op1;
10172 ix86_compare_op1 = tmp;
10173 code = swap_condition (code);
10175 if (GET_MODE (ix86_compare_op0) == DImode)
10177 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
10178 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
10183 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
10184 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
10188 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
10189 avoid two branches. This costs one extra insn, so disable when
10190 optimizing for size. */
10192 if ((code == EQ || code == NE)
10194 || hi[1] == const0_rtx || lo[1] == const0_rtx))
10199 if (hi[1] != const0_rtx)
10200 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
10201 NULL_RTX, 0, OPTAB_WIDEN);
10204 if (lo[1] != const0_rtx)
10205 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
10206 NULL_RTX, 0, OPTAB_WIDEN);
10208 tmp = expand_binop (submode, ior_optab, xor1, xor0,
10209 NULL_RTX, 0, OPTAB_WIDEN);
10211 ix86_compare_op0 = tmp;
10212 ix86_compare_op1 = const0_rtx;
10213 ix86_expand_branch (code, label);
10217 /* Otherwise, if we are doing less-than or greater-or-equal-than,
10218 op1 is a constant and the low word is zero, then we can just
10219 examine the high word. */
10221 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
10224 case LT: case LTU: case GE: case GEU:
10225 ix86_compare_op0 = hi[0];
10226 ix86_compare_op1 = hi[1];
10227 ix86_expand_branch (code, label);
10233 /* Otherwise, we need two or three jumps. */
10235 label2 = gen_label_rtx ();
10238 code2 = swap_condition (code);
10239 code3 = unsigned_condition (code);
10243 case LT: case GT: case LTU: case GTU:
10246 case LE: code1 = LT; code2 = GT; break;
10247 case GE: code1 = GT; code2 = LT; break;
10248 case LEU: code1 = LTU; code2 = GTU; break;
10249 case GEU: code1 = GTU; code2 = LTU; break;
10251 case EQ: code1 = UNKNOWN; code2 = NE; break;
10252 case NE: code2 = UNKNOWN; break;
10255 gcc_unreachable ();
10260 * if (hi(a) < hi(b)) goto true;
10261 * if (hi(a) > hi(b)) goto false;
10262 * if (lo(a) < lo(b)) goto true;
10266 ix86_compare_op0 = hi[0];
10267 ix86_compare_op1 = hi[1];
10269 if (code1 != UNKNOWN)
10270 ix86_expand_branch (code1, label);
10271 if (code2 != UNKNOWN)
10272 ix86_expand_branch (code2, label2);
10274 ix86_compare_op0 = lo[0];
10275 ix86_compare_op1 = lo[1];
10276 ix86_expand_branch (code3, label);
10278 if (code2 != UNKNOWN)
10279 emit_label (label2);
10284 gcc_unreachable ();
10288 /* Split branch based on floating point condition. */
10290 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
10291 rtx target1, rtx target2, rtx tmp, rtx pushed)
10293 rtx second, bypass;
10294 rtx label = NULL_RTX;
10296 int bypass_probability = -1, second_probability = -1, probability = -1;
10299 if (target2 != pc_rtx)
10302 code = reverse_condition_maybe_unordered (code);
10307 condition = ix86_expand_fp_compare (code, op1, op2,
10308 tmp, &second, &bypass);
10310 /* Remove pushed operand from stack. */
10312 ix86_free_from_memory (GET_MODE (pushed));
10314 if (split_branch_probability >= 0)
10316 /* Distribute the probabilities across the jumps.
10317 Assume the BYPASS and SECOND to be always test
10319 probability = split_branch_probability;
10321 /* Value of 1 is low enough to make no need for probability
10322 to be updated. Later we may run some experiments and see
10323 if unordered values are more frequent in practice. */
10325 bypass_probability = 1;
10327 second_probability = 1;
10329 if (bypass != NULL_RTX)
10331 label = gen_label_rtx ();
10332 i = emit_jump_insn (gen_rtx_SET
10334 gen_rtx_IF_THEN_ELSE (VOIDmode,
10336 gen_rtx_LABEL_REF (VOIDmode,
10339 if (bypass_probability >= 0)
10341 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10342 GEN_INT (bypass_probability),
10345 i = emit_jump_insn (gen_rtx_SET
10347 gen_rtx_IF_THEN_ELSE (VOIDmode,
10348 condition, target1, target2)));
10349 if (probability >= 0)
10351 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10352 GEN_INT (probability),
10354 if (second != NULL_RTX)
10356 i = emit_jump_insn (gen_rtx_SET
10358 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
10360 if (second_probability >= 0)
10362 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10363 GEN_INT (second_probability),
10366 if (label != NULL_RTX)
10367 emit_label (label);
10371 ix86_expand_setcc (enum rtx_code code, rtx dest)
10373 rtx ret, tmp, tmpreg, equiv;
10374 rtx second_test, bypass_test;
10376 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
10377 return 0; /* FAIL */
10379 gcc_assert (GET_MODE (dest) == QImode);
10381 ret = ix86_expand_compare (code, &second_test, &bypass_test);
10382 PUT_MODE (ret, QImode);
10387 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
10388 if (bypass_test || second_test)
10390 rtx test = second_test;
10392 rtx tmp2 = gen_reg_rtx (QImode);
10395 gcc_assert (!second_test);
10396 test = bypass_test;
10398 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
10400 PUT_MODE (test, QImode);
10401 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
10404 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
10406 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
10409 /* Attach a REG_EQUAL note describing the comparison result. */
10410 if (ix86_compare_op0 && ix86_compare_op1)
10412 equiv = simplify_gen_relational (code, QImode,
10413 GET_MODE (ix86_compare_op0),
10414 ix86_compare_op0, ix86_compare_op1);
10415 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
10418 return 1; /* DONE */
10421 /* Expand comparison setting or clearing carry flag. Return true when
10422 successful and set pop for the operation. */
10424 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
10426 enum machine_mode mode =
10427 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
10429 /* Do not handle DImode compares that go trought special path. Also we can't
10430 deal with FP compares yet. This is possible to add. */
10431 if (mode == (TARGET_64BIT ? TImode : DImode))
10433 if (FLOAT_MODE_P (mode))
10435 rtx second_test = NULL, bypass_test = NULL;
10436 rtx compare_op, compare_seq;
10438 /* Shortcut: following common codes never translate into carry flag compares. */
10439 if (code == EQ || code == NE || code == UNEQ || code == LTGT
10440 || code == ORDERED || code == UNORDERED)
10443 /* These comparisons require zero flag; swap operands so they won't. */
10444 if ((code == GT || code == UNLE || code == LE || code == UNGT)
10445 && !TARGET_IEEE_FP)
10450 code = swap_condition (code);
10453 /* Try to expand the comparison and verify that we end up with carry flag
10454 based comparison. This is fails to be true only when we decide to expand
10455 comparison using arithmetic that is not too common scenario. */
10457 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10458 &second_test, &bypass_test);
10459 compare_seq = get_insns ();
10462 if (second_test || bypass_test)
10464 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10465 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10466 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
10468 code = GET_CODE (compare_op);
10469 if (code != LTU && code != GEU)
10471 emit_insn (compare_seq);
10475 if (!INTEGRAL_MODE_P (mode))
10483 /* Convert a==0 into (unsigned)a<1. */
10486 if (op1 != const0_rtx)
10489 code = (code == EQ ? LTU : GEU);
10492 /* Convert a>b into b<a or a>=b-1. */
10495 if (GET_CODE (op1) == CONST_INT)
10497 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
10498 /* Bail out on overflow. We still can swap operands but that
10499 would force loading of the constant into register. */
10500 if (op1 == const0_rtx
10501 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
10503 code = (code == GTU ? GEU : LTU);
10510 code = (code == GTU ? LTU : GEU);
10514 /* Convert a>=0 into (unsigned)a<0x80000000. */
10517 if (mode == DImode || op1 != const0_rtx)
10519 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10520 code = (code == LT ? GEU : LTU);
10524 if (mode == DImode || op1 != constm1_rtx)
10526 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10527 code = (code == LE ? GEU : LTU);
10533 /* Swapping operands may cause constant to appear as first operand. */
10534 if (!nonimmediate_operand (op0, VOIDmode))
10536 if (no_new_pseudos)
10538 op0 = force_reg (mode, op0);
10540 ix86_compare_op0 = op0;
10541 ix86_compare_op1 = op1;
10542 *pop = ix86_expand_compare (code, NULL, NULL);
10543 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
10548 ix86_expand_int_movcc (rtx operands[])
10550 enum rtx_code code = GET_CODE (operands[1]), compare_code;
10551 rtx compare_seq, compare_op;
10552 rtx second_test, bypass_test;
10553 enum machine_mode mode = GET_MODE (operands[0]);
10554 bool sign_bit_compare_p = false;;
10557 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10558 compare_seq = get_insns ();
10561 compare_code = GET_CODE (compare_op);
10563 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
10564 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
10565 sign_bit_compare_p = true;
10567 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
10568 HImode insns, we'd be swallowed in word prefix ops. */
10570 if ((mode != HImode || TARGET_FAST_PREFIX)
10571 && (mode != (TARGET_64BIT ? TImode : DImode))
10572 && GET_CODE (operands[2]) == CONST_INT
10573 && GET_CODE (operands[3]) == CONST_INT)
10575 rtx out = operands[0];
10576 HOST_WIDE_INT ct = INTVAL (operands[2]);
10577 HOST_WIDE_INT cf = INTVAL (operands[3]);
10578 HOST_WIDE_INT diff;
10581 /* Sign bit compares are better done using shifts than we do by using
10583 if (sign_bit_compare_p
10584 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10585 ix86_compare_op1, &compare_op))
10587 /* Detect overlap between destination and compare sources. */
10590 if (!sign_bit_compare_p)
10592 bool fpcmp = false;
10594 compare_code = GET_CODE (compare_op);
10596 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10597 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10600 compare_code = ix86_fp_compare_code_to_integer (compare_code);
10603 /* To simplify rest of code, restrict to the GEU case. */
10604 if (compare_code == LTU)
10606 HOST_WIDE_INT tmp = ct;
10609 compare_code = reverse_condition (compare_code);
10610 code = reverse_condition (code);
10615 PUT_CODE (compare_op,
10616 reverse_condition_maybe_unordered
10617 (GET_CODE (compare_op)));
10619 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10623 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
10624 || reg_overlap_mentioned_p (out, ix86_compare_op1))
10625 tmp = gen_reg_rtx (mode);
10627 if (mode == DImode)
10628 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
10630 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
10634 if (code == GT || code == GE)
10635 code = reverse_condition (code);
10638 HOST_WIDE_INT tmp = ct;
10643 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
10644 ix86_compare_op1, VOIDmode, 0, -1);
10657 tmp = expand_simple_binop (mode, PLUS,
10659 copy_rtx (tmp), 1, OPTAB_DIRECT);
10670 tmp = expand_simple_binop (mode, IOR,
10672 copy_rtx (tmp), 1, OPTAB_DIRECT);
10674 else if (diff == -1 && ct)
10684 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10686 tmp = expand_simple_binop (mode, PLUS,
10687 copy_rtx (tmp), GEN_INT (cf),
10688 copy_rtx (tmp), 1, OPTAB_DIRECT);
10696 * andl cf - ct, dest
10706 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10709 tmp = expand_simple_binop (mode, AND,
10711 gen_int_mode (cf - ct, mode),
10712 copy_rtx (tmp), 1, OPTAB_DIRECT);
10714 tmp = expand_simple_binop (mode, PLUS,
10715 copy_rtx (tmp), GEN_INT (ct),
10716 copy_rtx (tmp), 1, OPTAB_DIRECT);
10719 if (!rtx_equal_p (tmp, out))
10720 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
10722 return 1; /* DONE */
10728 tmp = ct, ct = cf, cf = tmp;
10730 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10732 /* We may be reversing unordered compare to normal compare, that
10733 is not valid in general (we may convert non-trapping condition
10734 to trapping one), however on i386 we currently emit all
10735 comparisons unordered. */
10736 compare_code = reverse_condition_maybe_unordered (compare_code);
10737 code = reverse_condition_maybe_unordered (code);
10741 compare_code = reverse_condition (compare_code);
10742 code = reverse_condition (code);
10746 compare_code = UNKNOWN;
10747 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
10748 && GET_CODE (ix86_compare_op1) == CONST_INT)
10750 if (ix86_compare_op1 == const0_rtx
10751 && (code == LT || code == GE))
10752 compare_code = code;
10753 else if (ix86_compare_op1 == constm1_rtx)
10757 else if (code == GT)
10762 /* Optimize dest = (op0 < 0) ? -1 : cf. */
10763 if (compare_code != UNKNOWN
10764 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
10765 && (cf == -1 || ct == -1))
10767 /* If lea code below could be used, only optimize
10768 if it results in a 2 insn sequence. */
10770 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
10771 || diff == 3 || diff == 5 || diff == 9)
10772 || (compare_code == LT && ct == -1)
10773 || (compare_code == GE && cf == -1))
10776 * notl op1 (if necessary)
10784 code = reverse_condition (code);
10787 out = emit_store_flag (out, code, ix86_compare_op0,
10788 ix86_compare_op1, VOIDmode, 0, -1);
10790 out = expand_simple_binop (mode, IOR,
10792 out, 1, OPTAB_DIRECT);
10793 if (out != operands[0])
10794 emit_move_insn (operands[0], out);
10796 return 1; /* DONE */
10801 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
10802 || diff == 3 || diff == 5 || diff == 9)
10803 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
10805 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
10811 * lea cf(dest*(ct-cf)),dest
10815 * This also catches the degenerate setcc-only case.
10821 out = emit_store_flag (out, code, ix86_compare_op0,
10822 ix86_compare_op1, VOIDmode, 0, 1);
10825 /* On x86_64 the lea instruction operates on Pmode, so we need
10826 to get arithmetics done in proper mode to match. */
10828 tmp = copy_rtx (out);
10832 out1 = copy_rtx (out);
10833 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
10837 tmp = gen_rtx_PLUS (mode, tmp, out1);
10843 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
10846 if (!rtx_equal_p (tmp, out))
10849 out = force_operand (tmp, copy_rtx (out));
10851 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
10853 if (!rtx_equal_p (out, operands[0]))
10854 emit_move_insn (operands[0], copy_rtx (out));
10856 return 1; /* DONE */
10860 * General case: Jumpful:
10861 * xorl dest,dest cmpl op1, op2
10862 * cmpl op1, op2 movl ct, dest
10863 * setcc dest jcc 1f
10864 * decl dest movl cf, dest
10865 * andl (cf-ct),dest 1:
10868 * Size 20. Size 14.
10870 * This is reasonably steep, but branch mispredict costs are
10871 * high on modern cpus, so consider failing only if optimizing
10875 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10876 && BRANCH_COST >= 2)
10882 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10883 /* We may be reversing unordered compare to normal compare,
10884 that is not valid in general (we may convert non-trapping
10885 condition to trapping one), however on i386 we currently
10886 emit all comparisons unordered. */
10887 code = reverse_condition_maybe_unordered (code);
10890 code = reverse_condition (code);
10891 if (compare_code != UNKNOWN)
10892 compare_code = reverse_condition (compare_code);
10896 if (compare_code != UNKNOWN)
10898 /* notl op1 (if needed)
10903 For x < 0 (resp. x <= -1) there will be no notl,
10904 so if possible swap the constants to get rid of the
10906 True/false will be -1/0 while code below (store flag
10907 followed by decrement) is 0/-1, so the constants need
10908 to be exchanged once more. */
10910 if (compare_code == GE || !cf)
10912 code = reverse_condition (code);
10917 HOST_WIDE_INT tmp = cf;
10922 out = emit_store_flag (out, code, ix86_compare_op0,
10923 ix86_compare_op1, VOIDmode, 0, -1);
10927 out = emit_store_flag (out, code, ix86_compare_op0,
10928 ix86_compare_op1, VOIDmode, 0, 1);
10930 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
10931 copy_rtx (out), 1, OPTAB_DIRECT);
10934 out = expand_simple_binop (mode, AND, copy_rtx (out),
10935 gen_int_mode (cf - ct, mode),
10936 copy_rtx (out), 1, OPTAB_DIRECT);
10938 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
10939 copy_rtx (out), 1, OPTAB_DIRECT);
10940 if (!rtx_equal_p (out, operands[0]))
10941 emit_move_insn (operands[0], copy_rtx (out));
10943 return 1; /* DONE */
10947 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10949 /* Try a few things more with specific constants and a variable. */
10952 rtx var, orig_out, out, tmp;
10954 if (BRANCH_COST <= 2)
10955 return 0; /* FAIL */
10957 /* If one of the two operands is an interesting constant, load a
10958 constant with the above and mask it in with a logical operation. */
10960 if (GET_CODE (operands[2]) == CONST_INT)
10963 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
10964 operands[3] = constm1_rtx, op = and_optab;
10965 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
10966 operands[3] = const0_rtx, op = ior_optab;
10968 return 0; /* FAIL */
10970 else if (GET_CODE (operands[3]) == CONST_INT)
10973 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
10974 operands[2] = constm1_rtx, op = and_optab;
10975 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
10976 operands[2] = const0_rtx, op = ior_optab;
10978 return 0; /* FAIL */
10981 return 0; /* FAIL */
10983 orig_out = operands[0];
10984 tmp = gen_reg_rtx (mode);
10987 /* Recurse to get the constant loaded. */
10988 if (ix86_expand_int_movcc (operands) == 0)
10989 return 0; /* FAIL */
10991 /* Mask in the interesting variable. */
10992 out = expand_binop (mode, op, var, tmp, orig_out, 0,
10994 if (!rtx_equal_p (out, orig_out))
10995 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
10997 return 1; /* DONE */
11001 * For comparison with above,
11011 if (! nonimmediate_operand (operands[2], mode))
11012 operands[2] = force_reg (mode, operands[2]);
11013 if (! nonimmediate_operand (operands[3], mode))
11014 operands[3] = force_reg (mode, operands[3]);
11016 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11018 rtx tmp = gen_reg_rtx (mode);
11019 emit_move_insn (tmp, operands[3]);
11022 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11024 rtx tmp = gen_reg_rtx (mode);
11025 emit_move_insn (tmp, operands[2]);
11029 if (! register_operand (operands[2], VOIDmode)
11031 || ! register_operand (operands[3], VOIDmode)))
11032 operands[2] = force_reg (mode, operands[2]);
11035 && ! register_operand (operands[3], VOIDmode))
11036 operands[3] = force_reg (mode, operands[3]);
11038 emit_insn (compare_seq);
11039 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11040 gen_rtx_IF_THEN_ELSE (mode,
11041 compare_op, operands[2],
11044 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11045 gen_rtx_IF_THEN_ELSE (mode,
11047 copy_rtx (operands[3]),
11048 copy_rtx (operands[0]))));
11050 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11051 gen_rtx_IF_THEN_ELSE (mode,
11053 copy_rtx (operands[2]),
11054 copy_rtx (operands[0]))));
11056 return 1; /* DONE */
11059 /* Swap, force into registers, or otherwise massage the two operands
11060 to an sse comparison with a mask result. Thus we differ a bit from
11061 ix86_prepare_fp_compare_args which expects to produce a flags result.
11063 The DEST operand exists to help determine whether to commute commutative
11064 operators. The POP0/POP1 operands are updated in place. The new
11065 comparison code is returned, or UNKNOWN if not implementable. */
11067 static enum rtx_code
11068 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
11069 rtx *pop0, rtx *pop1)
11077 /* We have no LTGT as an operator. We could implement it with
11078 NE & ORDERED, but this requires an extra temporary. It's
11079 not clear that it's worth it. */
11086 /* These are supported directly. */
11093 /* For commutative operators, try to canonicalize the destination
11094 operand to be first in the comparison - this helps reload to
11095 avoid extra moves. */
11096 if (!dest || !rtx_equal_p (dest, *pop1))
11104 /* These are not supported directly. Swap the comparison operands
11105 to transform into something that is supported. */
11109 code = swap_condition (code);
11113 gcc_unreachable ();
11119 /* Detect conditional moves that exactly match min/max operational
11120 semantics. Note that this is IEEE safe, as long as we don't
11121 interchange the operands.
11123 Returns FALSE if this conditional move doesn't match a MIN/MAX,
11124 and TRUE if the operation is successful and instructions are emitted. */
11127 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
11128 rtx cmp_op1, rtx if_true, rtx if_false)
11130 enum machine_mode mode;
11136 else if (code == UNGE)
11139 if_true = if_false;
11145 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
11147 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
11152 mode = GET_MODE (dest);
11154 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
11155 but MODE may be a vector mode and thus not appropriate. */
11156 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
11158 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
11161 if_true = force_reg (mode, if_true);
11162 v = gen_rtvec (2, if_true, if_false);
11163 tmp = gen_rtx_UNSPEC (mode, v, u);
11167 code = is_min ? SMIN : SMAX;
11168 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
11171 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
11175 /* Expand an sse vector comparison. Return the register with the result. */
11178 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
11179 rtx op_true, rtx op_false)
11181 enum machine_mode mode = GET_MODE (dest);
11184 cmp_op0 = force_reg (mode, cmp_op0);
11185 if (!nonimmediate_operand (cmp_op1, mode))
11186 cmp_op1 = force_reg (mode, cmp_op1);
11189 || reg_overlap_mentioned_p (dest, op_true)
11190 || reg_overlap_mentioned_p (dest, op_false))
11191 dest = gen_reg_rtx (mode);
11193 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
11194 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11199 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
11200 operations. This is used for both scalar and vector conditional moves. */
11203 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
11205 enum machine_mode mode = GET_MODE (dest);
11208 if (op_false == CONST0_RTX (mode))
11210 op_true = force_reg (mode, op_true);
11211 x = gen_rtx_AND (mode, cmp, op_true);
11212 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11214 else if (op_true == CONST0_RTX (mode))
11216 op_false = force_reg (mode, op_false);
11217 x = gen_rtx_NOT (mode, cmp);
11218 x = gen_rtx_AND (mode, x, op_false);
11219 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11223 op_true = force_reg (mode, op_true);
11224 op_false = force_reg (mode, op_false);
11226 t2 = gen_reg_rtx (mode);
11228 t3 = gen_reg_rtx (mode);
11232 x = gen_rtx_AND (mode, op_true, cmp);
11233 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
11235 x = gen_rtx_NOT (mode, cmp);
11236 x = gen_rtx_AND (mode, x, op_false);
11237 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
11239 x = gen_rtx_IOR (mode, t3, t2);
11240 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11244 /* Expand a floating-point conditional move. Return true if successful. */
11247 ix86_expand_fp_movcc (rtx operands[])
11249 enum machine_mode mode = GET_MODE (operands[0]);
11250 enum rtx_code code = GET_CODE (operands[1]);
11251 rtx tmp, compare_op, second_test, bypass_test;
11253 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
11255 enum machine_mode cmode;
11257 /* Since we've no cmove for sse registers, don't force bad register
11258 allocation just to gain access to it. Deny movcc when the
11259 comparison mode doesn't match the move mode. */
11260 cmode = GET_MODE (ix86_compare_op0);
11261 if (cmode == VOIDmode)
11262 cmode = GET_MODE (ix86_compare_op1);
11266 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11268 &ix86_compare_op1);
11269 if (code == UNKNOWN)
11272 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
11273 ix86_compare_op1, operands[2],
11277 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
11278 ix86_compare_op1, operands[2], operands[3]);
11279 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
11283 /* The floating point conditional move instructions don't directly
11284 support conditions resulting from a signed integer comparison. */
11286 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11288 /* The floating point conditional move instructions don't directly
11289 support signed integer comparisons. */
11291 if (!fcmov_comparison_operator (compare_op, VOIDmode))
11293 gcc_assert (!second_test && !bypass_test);
11294 tmp = gen_reg_rtx (QImode);
11295 ix86_expand_setcc (code, tmp);
11297 ix86_compare_op0 = tmp;
11298 ix86_compare_op1 = const0_rtx;
11299 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11301 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11303 tmp = gen_reg_rtx (mode);
11304 emit_move_insn (tmp, operands[3]);
11307 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11309 tmp = gen_reg_rtx (mode);
11310 emit_move_insn (tmp, operands[2]);
11314 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11315 gen_rtx_IF_THEN_ELSE (mode, compare_op,
11316 operands[2], operands[3])));
11318 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11319 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
11320 operands[3], operands[0])));
11322 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11323 gen_rtx_IF_THEN_ELSE (mode, second_test,
11324 operands[2], operands[0])));
11329 /* Expand a floating-point vector conditional move; a vcond operation
11330 rather than a movcc operation. */
11333 ix86_expand_fp_vcond (rtx operands[])
11335 enum rtx_code code = GET_CODE (operands[3]);
11338 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11339 &operands[4], &operands[5]);
11340 if (code == UNKNOWN)
11343 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
11344 operands[5], operands[1], operands[2]))
11347 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
11348 operands[1], operands[2]);
11349 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
11353 /* Expand a signed integral vector conditional move. */
11356 ix86_expand_int_vcond (rtx operands[])
11358 enum machine_mode mode = GET_MODE (operands[0]);
11359 enum rtx_code code = GET_CODE (operands[3]);
11360 bool negate = false;
11363 cop0 = operands[4];
11364 cop1 = operands[5];
11366 /* Canonicalize the comparison to EQ, GT, GTU. */
11377 code = reverse_condition (code);
11383 code = reverse_condition (code);
11389 code = swap_condition (code);
11390 x = cop0, cop0 = cop1, cop1 = x;
11394 gcc_unreachable ();
11397 /* Unsigned parallel compare is not supported by the hardware. Play some
11398 tricks to turn this into a signed comparison against 0. */
11407 /* Perform a parallel modulo subtraction. */
11408 t1 = gen_reg_rtx (mode);
11409 emit_insn (gen_subv4si3 (t1, cop0, cop1));
11411 /* Extract the original sign bit of op0. */
11412 mask = GEN_INT (-0x80000000);
11413 mask = gen_rtx_CONST_VECTOR (mode,
11414 gen_rtvec (4, mask, mask, mask, mask));
11415 mask = force_reg (mode, mask);
11416 t2 = gen_reg_rtx (mode);
11417 emit_insn (gen_andv4si3 (t2, cop0, mask));
11419 /* XOR it back into the result of the subtraction. This results
11420 in the sign bit set iff we saw unsigned underflow. */
11421 x = gen_reg_rtx (mode);
11422 emit_insn (gen_xorv4si3 (x, t1, t2));
11430 /* Perform a parallel unsigned saturating subtraction. */
11431 x = gen_reg_rtx (mode);
11432 emit_insn (gen_rtx_SET (VOIDmode, x,
11433 gen_rtx_US_MINUS (mode, cop0, cop1)));
11440 gcc_unreachable ();
11444 cop1 = CONST0_RTX (mode);
11447 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
11448 operands[1+negate], operands[2-negate]);
11450 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
11451 operands[2-negate]);
11455 /* Expand conditional increment or decrement using adb/sbb instructions.
11456 The default case using setcc followed by the conditional move can be
11457 done by generic code. */
11459 ix86_expand_int_addcc (rtx operands[])
11461 enum rtx_code code = GET_CODE (operands[1]);
11463 rtx val = const0_rtx;
11464 bool fpcmp = false;
11465 enum machine_mode mode = GET_MODE (operands[0]);
11467 if (operands[3] != const1_rtx
11468 && operands[3] != constm1_rtx)
11470 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
11471 ix86_compare_op1, &compare_op))
11473 code = GET_CODE (compare_op);
11475 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11476 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11479 code = ix86_fp_compare_code_to_integer (code);
11486 PUT_CODE (compare_op,
11487 reverse_condition_maybe_unordered
11488 (GET_CODE (compare_op)));
11490 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
11492 PUT_MODE (compare_op, mode);
11494 /* Construct either adc or sbb insn. */
11495 if ((code == LTU) == (operands[3] == constm1_rtx))
11497 switch (GET_MODE (operands[0]))
11500 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
11503 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
11506 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
11509 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11512 gcc_unreachable ();
11517 switch (GET_MODE (operands[0]))
11520 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
11523 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
11526 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
11529 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11532 gcc_unreachable ();
11535 return 1; /* DONE */
11539 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
11540 works for floating pointer parameters and nonoffsetable memories.
11541 For pushes, it returns just stack offsets; the values will be saved
11542 in the right order. Maximally three parts are generated. */
11545 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
11550 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
11552 size = (GET_MODE_SIZE (mode) + 4) / 8;
11554 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
11555 gcc_assert (size >= 2 && size <= 3);
11557 /* Optimize constant pool reference to immediates. This is used by fp
11558 moves, that force all constants to memory to allow combining. */
11559 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
11561 rtx tmp = maybe_get_pool_constant (operand);
11566 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
11568 /* The only non-offsetable memories we handle are pushes. */
11569 int ok = push_operand (operand, VOIDmode);
11573 operand = copy_rtx (operand);
11574 PUT_MODE (operand, Pmode);
11575 parts[0] = parts[1] = parts[2] = operand;
11579 if (GET_CODE (operand) == CONST_VECTOR)
11581 enum machine_mode imode = int_mode_for_mode (mode);
11582 /* Caution: if we looked through a constant pool memory above,
11583 the operand may actually have a different mode now. That's
11584 ok, since we want to pun this all the way back to an integer. */
11585 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
11586 gcc_assert (operand != NULL);
11592 if (mode == DImode)
11593 split_di (&operand, 1, &parts[0], &parts[1]);
11596 if (REG_P (operand))
11598 gcc_assert (reload_completed);
11599 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
11600 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
11602 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
11604 else if (offsettable_memref_p (operand))
11606 operand = adjust_address (operand, SImode, 0);
11607 parts[0] = operand;
11608 parts[1] = adjust_address (operand, SImode, 4);
11610 parts[2] = adjust_address (operand, SImode, 8);
11612 else if (GET_CODE (operand) == CONST_DOUBLE)
11617 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11621 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
11622 parts[2] = gen_int_mode (l[2], SImode);
11625 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
11628 gcc_unreachable ();
11630 parts[1] = gen_int_mode (l[1], SImode);
11631 parts[0] = gen_int_mode (l[0], SImode);
11634 gcc_unreachable ();
11639 if (mode == TImode)
11640 split_ti (&operand, 1, &parts[0], &parts[1]);
11641 if (mode == XFmode || mode == TFmode)
11643 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
11644 if (REG_P (operand))
11646 gcc_assert (reload_completed);
11647 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
11648 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
11650 else if (offsettable_memref_p (operand))
11652 operand = adjust_address (operand, DImode, 0);
11653 parts[0] = operand;
11654 parts[1] = adjust_address (operand, upper_mode, 8);
11656 else if (GET_CODE (operand) == CONST_DOUBLE)
11661 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11662 real_to_target (l, &r, mode);
11664 /* Do not use shift by 32 to avoid warning on 32bit systems. */
11665 if (HOST_BITS_PER_WIDE_INT >= 64)
11668 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
11669 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
11672 parts[0] = immed_double_const (l[0], l[1], DImode);
11674 if (upper_mode == SImode)
11675 parts[1] = gen_int_mode (l[2], SImode);
11676 else if (HOST_BITS_PER_WIDE_INT >= 64)
11679 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
11680 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
11683 parts[1] = immed_double_const (l[2], l[3], DImode);
11686 gcc_unreachable ();
11693 /* Emit insns to perform a move or push of DI, DF, and XF values.
11694 Return false when normal moves are needed; true when all required
11695 insns have been emitted. Operands 2-4 contain the input values
11696 int the correct order; operands 5-7 contain the output values. */
11699 ix86_split_long_move (rtx operands[])
11704 int collisions = 0;
11705 enum machine_mode mode = GET_MODE (operands[0]);
11707 /* The DFmode expanders may ask us to move double.
11708 For 64bit target this is single move. By hiding the fact
11709 here we simplify i386.md splitters. */
11710 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
11712 /* Optimize constant pool reference to immediates. This is used by
11713 fp moves, that force all constants to memory to allow combining. */
11715 if (GET_CODE (operands[1]) == MEM
11716 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
11717 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
11718 operands[1] = get_pool_constant (XEXP (operands[1], 0));
11719 if (push_operand (operands[0], VOIDmode))
11721 operands[0] = copy_rtx (operands[0]);
11722 PUT_MODE (operands[0], Pmode);
11725 operands[0] = gen_lowpart (DImode, operands[0]);
11726 operands[1] = gen_lowpart (DImode, operands[1]);
11727 emit_move_insn (operands[0], operands[1]);
11731 /* The only non-offsettable memory we handle is push. */
11732 if (push_operand (operands[0], VOIDmode))
11735 gcc_assert (GET_CODE (operands[0]) != MEM
11736 || offsettable_memref_p (operands[0]));
11738 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
11739 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
11741 /* When emitting push, take care for source operands on the stack. */
11742 if (push && GET_CODE (operands[1]) == MEM
11743 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
11746 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
11747 XEXP (part[1][2], 0));
11748 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
11749 XEXP (part[1][1], 0));
11752 /* We need to do copy in the right order in case an address register
11753 of the source overlaps the destination. */
11754 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
11756 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
11758 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11761 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
11764 /* Collision in the middle part can be handled by reordering. */
11765 if (collisions == 1 && nparts == 3
11766 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11769 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
11770 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
11773 /* If there are more collisions, we can't handle it by reordering.
11774 Do an lea to the last part and use only one colliding move. */
11775 else if (collisions > 1)
11781 base = part[0][nparts - 1];
11783 /* Handle the case when the last part isn't valid for lea.
11784 Happens in 64-bit mode storing the 12-byte XFmode. */
11785 if (GET_MODE (base) != Pmode)
11786 base = gen_rtx_REG (Pmode, REGNO (base));
11788 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
11789 part[1][0] = replace_equiv_address (part[1][0], base);
11790 part[1][1] = replace_equiv_address (part[1][1],
11791 plus_constant (base, UNITS_PER_WORD));
11793 part[1][2] = replace_equiv_address (part[1][2],
11794 plus_constant (base, 8));
11804 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
11805 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
11806 emit_move_insn (part[0][2], part[1][2]);
11811 /* In 64bit mode we don't have 32bit push available. In case this is
11812 register, it is OK - we will just use larger counterpart. We also
11813 retype memory - these comes from attempt to avoid REX prefix on
11814 moving of second half of TFmode value. */
11815 if (GET_MODE (part[1][1]) == SImode)
11817 switch (GET_CODE (part[1][1]))
11820 part[1][1] = adjust_address (part[1][1], DImode, 0);
11824 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
11828 gcc_unreachable ();
11831 if (GET_MODE (part[1][0]) == SImode)
11832 part[1][0] = part[1][1];
11835 emit_move_insn (part[0][1], part[1][1]);
11836 emit_move_insn (part[0][0], part[1][0]);
11840 /* Choose correct order to not overwrite the source before it is copied. */
11841 if ((REG_P (part[0][0])
11842 && REG_P (part[1][1])
11843 && (REGNO (part[0][0]) == REGNO (part[1][1])
11845 && REGNO (part[0][0]) == REGNO (part[1][2]))))
11847 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
11851 operands[2] = part[0][2];
11852 operands[3] = part[0][1];
11853 operands[4] = part[0][0];
11854 operands[5] = part[1][2];
11855 operands[6] = part[1][1];
11856 operands[7] = part[1][0];
11860 operands[2] = part[0][1];
11861 operands[3] = part[0][0];
11862 operands[5] = part[1][1];
11863 operands[6] = part[1][0];
11870 operands[2] = part[0][0];
11871 operands[3] = part[0][1];
11872 operands[4] = part[0][2];
11873 operands[5] = part[1][0];
11874 operands[6] = part[1][1];
11875 operands[7] = part[1][2];
11879 operands[2] = part[0][0];
11880 operands[3] = part[0][1];
11881 operands[5] = part[1][0];
11882 operands[6] = part[1][1];
11886 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
11889 if (GET_CODE (operands[5]) == CONST_INT
11890 && operands[5] != const0_rtx
11891 && REG_P (operands[2]))
11893 if (GET_CODE (operands[6]) == CONST_INT
11894 && INTVAL (operands[6]) == INTVAL (operands[5]))
11895 operands[6] = operands[2];
11898 && GET_CODE (operands[7]) == CONST_INT
11899 && INTVAL (operands[7]) == INTVAL (operands[5]))
11900 operands[7] = operands[2];
11904 && GET_CODE (operands[6]) == CONST_INT
11905 && operands[6] != const0_rtx
11906 && REG_P (operands[3])
11907 && GET_CODE (operands[7]) == CONST_INT
11908 && INTVAL (operands[7]) == INTVAL (operands[6]))
11909 operands[7] = operands[3];
11912 emit_move_insn (operands[2], operands[5]);
11913 emit_move_insn (operands[3], operands[6]);
11915 emit_move_insn (operands[4], operands[7]);
11920 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
11921 left shift by a constant, either using a single shift or
11922 a sequence of add instructions. */
11925 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
11929 emit_insn ((mode == DImode
11931 : gen_adddi3) (operand, operand, operand));
11933 else if (!optimize_size
11934 && count * ix86_cost->add <= ix86_cost->shift_const)
11937 for (i=0; i<count; i++)
11939 emit_insn ((mode == DImode
11941 : gen_adddi3) (operand, operand, operand));
11945 emit_insn ((mode == DImode
11947 : gen_ashldi3) (operand, operand, GEN_INT (count)));
11951 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
11953 rtx low[2], high[2];
11955 const int single_width = mode == DImode ? 32 : 64;
11957 if (GET_CODE (operands[2]) == CONST_INT)
11959 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11960 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11962 if (count >= single_width)
11964 emit_move_insn (high[0], low[1]);
11965 emit_move_insn (low[0], const0_rtx);
11967 if (count > single_width)
11968 ix86_expand_ashl_const (high[0], count - single_width, mode);
11972 if (!rtx_equal_p (operands[0], operands[1]))
11973 emit_move_insn (operands[0], operands[1]);
11974 emit_insn ((mode == DImode
11976 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
11977 ix86_expand_ashl_const (low[0], count, mode);
11982 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11984 if (operands[1] == const1_rtx)
11986 /* Assuming we've chosen a QImode capable registers, then 1 << N
11987 can be done with two 32/64-bit shifts, no branches, no cmoves. */
11988 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
11990 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
11992 ix86_expand_clear (low[0]);
11993 ix86_expand_clear (high[0]);
11994 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
11996 d = gen_lowpart (QImode, low[0]);
11997 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11998 s = gen_rtx_EQ (QImode, flags, const0_rtx);
11999 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12001 d = gen_lowpart (QImode, high[0]);
12002 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
12003 s = gen_rtx_NE (QImode, flags, const0_rtx);
12004 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12007 /* Otherwise, we can get the same results by manually performing
12008 a bit extract operation on bit 5/6, and then performing the two
12009 shifts. The two methods of getting 0/1 into low/high are exactly
12010 the same size. Avoiding the shift in the bit extract case helps
12011 pentium4 a bit; no one else seems to care much either way. */
12016 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
12017 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
12019 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
12020 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
12022 emit_insn ((mode == DImode
12024 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
12025 emit_insn ((mode == DImode
12027 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
12028 emit_move_insn (low[0], high[0]);
12029 emit_insn ((mode == DImode
12031 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
12034 emit_insn ((mode == DImode
12036 : gen_ashldi3) (low[0], low[0], operands[2]));
12037 emit_insn ((mode == DImode
12039 : gen_ashldi3) (high[0], high[0], operands[2]));
12043 if (operands[1] == constm1_rtx)
12045 /* For -1 << N, we can avoid the shld instruction, because we
12046 know that we're shifting 0...31/63 ones into a -1. */
12047 emit_move_insn (low[0], constm1_rtx);
12049 emit_move_insn (high[0], low[0]);
12051 emit_move_insn (high[0], constm1_rtx);
12055 if (!rtx_equal_p (operands[0], operands[1]))
12056 emit_move_insn (operands[0], operands[1]);
12058 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12059 emit_insn ((mode == DImode
12061 : gen_x86_64_shld) (high[0], low[0], operands[2]));
12064 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
12066 if (TARGET_CMOVE && scratch)
12068 ix86_expand_clear (scratch);
12069 emit_insn ((mode == DImode
12070 ? gen_x86_shift_adj_1
12071 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
12074 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
12078 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
12080 rtx low[2], high[2];
12082 const int single_width = mode == DImode ? 32 : 64;
12084 if (GET_CODE (operands[2]) == CONST_INT)
12086 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12087 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12089 if (count == single_width * 2 - 1)
12091 emit_move_insn (high[0], high[1]);
12092 emit_insn ((mode == DImode
12094 : gen_ashrdi3) (high[0], high[0],
12095 GEN_INT (single_width - 1)));
12096 emit_move_insn (low[0], high[0]);
12099 else if (count >= single_width)
12101 emit_move_insn (low[0], high[1]);
12102 emit_move_insn (high[0], low[0]);
12103 emit_insn ((mode == DImode
12105 : gen_ashrdi3) (high[0], high[0],
12106 GEN_INT (single_width - 1)));
12107 if (count > single_width)
12108 emit_insn ((mode == DImode
12110 : gen_ashrdi3) (low[0], low[0],
12111 GEN_INT (count - single_width)));
12115 if (!rtx_equal_p (operands[0], operands[1]))
12116 emit_move_insn (operands[0], operands[1]);
12117 emit_insn ((mode == DImode
12119 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12120 emit_insn ((mode == DImode
12122 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
12127 if (!rtx_equal_p (operands[0], operands[1]))
12128 emit_move_insn (operands[0], operands[1]);
12130 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12132 emit_insn ((mode == DImode
12134 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12135 emit_insn ((mode == DImode
12137 : gen_ashrdi3) (high[0], high[0], operands[2]));
12139 if (TARGET_CMOVE && scratch)
12141 emit_move_insn (scratch, high[0]);
12142 emit_insn ((mode == DImode
12144 : gen_ashrdi3) (scratch, scratch,
12145 GEN_INT (single_width - 1)));
12146 emit_insn ((mode == DImode
12147 ? gen_x86_shift_adj_1
12148 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12152 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
12157 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
12159 rtx low[2], high[2];
12161 const int single_width = mode == DImode ? 32 : 64;
12163 if (GET_CODE (operands[2]) == CONST_INT)
12165 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12166 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12168 if (count >= single_width)
12170 emit_move_insn (low[0], high[1]);
12171 ix86_expand_clear (high[0]);
12173 if (count > single_width)
12174 emit_insn ((mode == DImode
12176 : gen_lshrdi3) (low[0], low[0],
12177 GEN_INT (count - single_width)));
12181 if (!rtx_equal_p (operands[0], operands[1]))
12182 emit_move_insn (operands[0], operands[1]);
12183 emit_insn ((mode == DImode
12185 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12186 emit_insn ((mode == DImode
12188 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
12193 if (!rtx_equal_p (operands[0], operands[1]))
12194 emit_move_insn (operands[0], operands[1]);
12196 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12198 emit_insn ((mode == DImode
12200 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12201 emit_insn ((mode == DImode
12203 : gen_lshrdi3) (high[0], high[0], operands[2]));
12205 /* Heh. By reversing the arguments, we can reuse this pattern. */
12206 if (TARGET_CMOVE && scratch)
12208 ix86_expand_clear (scratch);
12209 emit_insn ((mode == DImode
12210 ? gen_x86_shift_adj_1
12211 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12215 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
12219 /* Helper function for the string operations below. Dest VARIABLE whether
12220 it is aligned to VALUE bytes. If true, jump to the label. */
12222 ix86_expand_aligntest (rtx variable, int value)
12224 rtx label = gen_label_rtx ();
12225 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
12226 if (GET_MODE (variable) == DImode)
12227 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
12229 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
12230 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
12235 /* Adjust COUNTER by the VALUE. */
12237 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
12239 if (GET_MODE (countreg) == DImode)
12240 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
12242 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
12245 /* Zero extend possibly SImode EXP to Pmode register. */
12247 ix86_zero_extend_to_Pmode (rtx exp)
12250 if (GET_MODE (exp) == VOIDmode)
12251 return force_reg (Pmode, exp);
12252 if (GET_MODE (exp) == Pmode)
12253 return copy_to_mode_reg (Pmode, exp);
12254 r = gen_reg_rtx (Pmode);
12255 emit_insn (gen_zero_extendsidi2 (r, exp));
12259 /* Expand string move (memcpy) operation. Use i386 string operations when
12260 profitable. expand_clrmem contains similar code. */
12262 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
12264 rtx srcreg, destreg, countreg, srcexp, destexp;
12265 enum machine_mode counter_mode;
12266 HOST_WIDE_INT align = 0;
12267 unsigned HOST_WIDE_INT count = 0;
12269 if (GET_CODE (align_exp) == CONST_INT)
12270 align = INTVAL (align_exp);
12272 /* Can't use any of this if the user has appropriated esi or edi. */
12273 if (global_regs[4] || global_regs[5])
12276 /* This simple hack avoids all inlining code and simplifies code below. */
12277 if (!TARGET_ALIGN_STRINGOPS)
12280 if (GET_CODE (count_exp) == CONST_INT)
12282 count = INTVAL (count_exp);
12283 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12287 /* Figure out proper mode for counter. For 32bits it is always SImode,
12288 for 64bits use SImode when possible, otherwise DImode.
12289 Set count to number of bytes copied when known at compile time. */
12291 || GET_MODE (count_exp) == SImode
12292 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12293 counter_mode = SImode;
12295 counter_mode = DImode;
12297 gcc_assert (counter_mode == SImode || counter_mode == DImode);
12299 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12300 if (destreg != XEXP (dst, 0))
12301 dst = replace_equiv_address_nv (dst, destreg);
12302 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
12303 if (srcreg != XEXP (src, 0))
12304 src = replace_equiv_address_nv (src, srcreg);
12306 /* When optimizing for size emit simple rep ; movsb instruction for
12307 counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)?
12308 sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb.
12309 Sice of (movsl;)*(movsw;)?(movsb;)? sequence is
12310 count / 4 + (count & 3), the other sequence is either 4 or 7 bytes,
12311 but we don't know whether upper 24 (resp. 56) bits of %ecx will be
12312 known to be zero or not. The rep; movsb sequence causes higher
12313 register pressure though, so take that into account. */
12315 if ((!optimize || optimize_size)
12320 || (count & 3) + count / 4 > 6))))
12322 emit_insn (gen_cld ());
12323 countreg = ix86_zero_extend_to_Pmode (count_exp);
12324 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12325 srcexp = gen_rtx_PLUS (Pmode, srcreg, countreg);
12326 emit_insn (gen_rep_mov (destreg, dst, srcreg, src, countreg,
12330 /* For constant aligned (or small unaligned) copies use rep movsl
12331 followed by code copying the rest. For PentiumPro ensure 8 byte
12332 alignment to allow rep movsl acceleration. */
12334 else if (count != 0
12336 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12337 || optimize_size || count < (unsigned int) 64))
12339 unsigned HOST_WIDE_INT offset = 0;
12340 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12341 rtx srcmem, dstmem;
12343 emit_insn (gen_cld ());
12344 if (count & ~(size - 1))
12346 if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4)
12348 enum machine_mode movs_mode = size == 4 ? SImode : DImode;
12350 while (offset < (count & ~(size - 1)))
12352 srcmem = adjust_automodify_address_nv (src, movs_mode,
12354 dstmem = adjust_automodify_address_nv (dst, movs_mode,
12356 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12362 countreg = GEN_INT ((count >> (size == 4 ? 2 : 3))
12363 & (TARGET_64BIT ? -1 : 0x3fffffff));
12364 countreg = copy_to_mode_reg (counter_mode, countreg);
12365 countreg = ix86_zero_extend_to_Pmode (countreg);
12367 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12368 GEN_INT (size == 4 ? 2 : 3));
12369 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
12370 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12372 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
12373 countreg, destexp, srcexp));
12374 offset = count & ~(size - 1);
12377 if (size == 8 && (count & 0x04))
12379 srcmem = adjust_automodify_address_nv (src, SImode, srcreg,
12381 dstmem = adjust_automodify_address_nv (dst, SImode, destreg,
12383 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12388 srcmem = adjust_automodify_address_nv (src, HImode, srcreg,
12390 dstmem = adjust_automodify_address_nv (dst, HImode, destreg,
12392 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12397 srcmem = adjust_automodify_address_nv (src, QImode, srcreg,
12399 dstmem = adjust_automodify_address_nv (dst, QImode, destreg,
12401 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12404 /* The generic code based on the glibc implementation:
12405 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
12406 allowing accelerated copying there)
12407 - copy the data using rep movsl
12408 - copy the rest. */
12413 rtx srcmem, dstmem;
12414 int desired_alignment = (TARGET_PENTIUMPRO
12415 && (count == 0 || count >= (unsigned int) 260)
12416 ? 8 : UNITS_PER_WORD);
12417 /* Get rid of MEM_OFFSETs, they won't be accurate. */
12418 dst = change_address (dst, BLKmode, destreg);
12419 src = change_address (src, BLKmode, srcreg);
12421 /* In case we don't know anything about the alignment, default to
12422 library version, since it is usually equally fast and result in
12425 Also emit call when we know that the count is large and call overhead
12426 will not be important. */
12427 if (!TARGET_INLINE_ALL_STRINGOPS
12428 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12431 if (TARGET_SINGLE_STRINGOP)
12432 emit_insn (gen_cld ());
12434 countreg2 = gen_reg_rtx (Pmode);
12435 countreg = copy_to_mode_reg (counter_mode, count_exp);
12437 /* We don't use loops to align destination and to copy parts smaller
12438 than 4 bytes, because gcc is able to optimize such code better (in
12439 the case the destination or the count really is aligned, gcc is often
12440 able to predict the branches) and also it is friendlier to the
12441 hardware branch prediction.
12443 Using loops is beneficial for generic case, because we can
12444 handle small counts using the loops. Many CPUs (such as Athlon)
12445 have large REP prefix setup costs.
12447 This is quite costly. Maybe we can revisit this decision later or
12448 add some customizability to this code. */
12450 if (count == 0 && align < desired_alignment)
12452 label = gen_label_rtx ();
12453 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12454 LEU, 0, counter_mode, 1, label);
12458 rtx label = ix86_expand_aligntest (destreg, 1);
12459 srcmem = change_address (src, QImode, srcreg);
12460 dstmem = change_address (dst, QImode, destreg);
12461 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12462 ix86_adjust_counter (countreg, 1);
12463 emit_label (label);
12464 LABEL_NUSES (label) = 1;
12468 rtx label = ix86_expand_aligntest (destreg, 2);
12469 srcmem = change_address (src, HImode, srcreg);
12470 dstmem = change_address (dst, HImode, destreg);
12471 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12472 ix86_adjust_counter (countreg, 2);
12473 emit_label (label);
12474 LABEL_NUSES (label) = 1;
12476 if (align <= 4 && desired_alignment > 4)
12478 rtx label = ix86_expand_aligntest (destreg, 4);
12479 srcmem = change_address (src, SImode, srcreg);
12480 dstmem = change_address (dst, SImode, destreg);
12481 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12482 ix86_adjust_counter (countreg, 4);
12483 emit_label (label);
12484 LABEL_NUSES (label) = 1;
12487 if (label && desired_alignment > 4 && !TARGET_64BIT)
12489 emit_label (label);
12490 LABEL_NUSES (label) = 1;
12493 if (!TARGET_SINGLE_STRINGOP)
12494 emit_insn (gen_cld ());
12497 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12499 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12503 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12504 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12506 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
12507 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12508 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
12509 countreg2, destexp, srcexp));
12513 emit_label (label);
12514 LABEL_NUSES (label) = 1;
12516 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12518 srcmem = change_address (src, SImode, srcreg);
12519 dstmem = change_address (dst, SImode, destreg);
12520 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12522 if ((align <= 4 || count == 0) && TARGET_64BIT)
12524 rtx label = ix86_expand_aligntest (countreg, 4);
12525 srcmem = change_address (src, SImode, srcreg);
12526 dstmem = change_address (dst, SImode, destreg);
12527 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12528 emit_label (label);
12529 LABEL_NUSES (label) = 1;
12531 if (align > 2 && count != 0 && (count & 2))
12533 srcmem = change_address (src, HImode, srcreg);
12534 dstmem = change_address (dst, HImode, destreg);
12535 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12537 if (align <= 2 || count == 0)
12539 rtx label = ix86_expand_aligntest (countreg, 2);
12540 srcmem = change_address (src, HImode, srcreg);
12541 dstmem = change_address (dst, HImode, destreg);
12542 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12543 emit_label (label);
12544 LABEL_NUSES (label) = 1;
12546 if (align > 1 && count != 0 && (count & 1))
12548 srcmem = change_address (src, QImode, srcreg);
12549 dstmem = change_address (dst, QImode, destreg);
12550 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12552 if (align <= 1 || count == 0)
12554 rtx label = ix86_expand_aligntest (countreg, 1);
12555 srcmem = change_address (src, QImode, srcreg);
12556 dstmem = change_address (dst, QImode, destreg);
12557 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12558 emit_label (label);
12559 LABEL_NUSES (label) = 1;
12566 /* Expand string clear operation (bzero). Use i386 string operations when
12567 profitable. expand_movmem contains similar code. */
12569 ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
12571 rtx destreg, zeroreg, countreg, destexp;
12572 enum machine_mode counter_mode;
12573 HOST_WIDE_INT align = 0;
12574 unsigned HOST_WIDE_INT count = 0;
12576 if (GET_CODE (align_exp) == CONST_INT)
12577 align = INTVAL (align_exp);
12579 /* Can't use any of this if the user has appropriated esi. */
12580 if (global_regs[4])
12583 /* This simple hack avoids all inlining code and simplifies code below. */
12584 if (!TARGET_ALIGN_STRINGOPS)
12587 if (GET_CODE (count_exp) == CONST_INT)
12589 count = INTVAL (count_exp);
12590 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12593 /* Figure out proper mode for counter. For 32bits it is always SImode,
12594 for 64bits use SImode when possible, otherwise DImode.
12595 Set count to number of bytes copied when known at compile time. */
12597 || GET_MODE (count_exp) == SImode
12598 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12599 counter_mode = SImode;
12601 counter_mode = DImode;
12603 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12604 if (destreg != XEXP (dst, 0))
12605 dst = replace_equiv_address_nv (dst, destreg);
12608 /* When optimizing for size emit simple rep ; movsb instruction for
12609 counts not divisible by 4. The movl $N, %ecx; rep; stosb
12610 sequence is 7 bytes long, so if optimizing for size and count is
12611 small enough that some stosl, stosw and stosb instructions without
12612 rep are shorter, fall back into the next if. */
12614 if ((!optimize || optimize_size)
12617 && (!optimize_size || (count & 0x03) + (count >> 2) > 7))))
12619 emit_insn (gen_cld ());
12621 countreg = ix86_zero_extend_to_Pmode (count_exp);
12622 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12623 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12624 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp));
12626 else if (count != 0
12628 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12629 || optimize_size || count < (unsigned int) 64))
12631 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12632 unsigned HOST_WIDE_INT offset = 0;
12634 emit_insn (gen_cld ());
12636 zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx);
12637 if (count & ~(size - 1))
12639 unsigned HOST_WIDE_INT repcount;
12640 unsigned int max_nonrep;
12642 repcount = count >> (size == 4 ? 2 : 3);
12644 repcount &= 0x3fffffff;
12646 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
12647 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
12648 bytes. In both cases the latter seems to be faster for small
12650 max_nonrep = size == 4 ? 7 : 4;
12651 if (!optimize_size)
12654 case PROCESSOR_PENTIUM4:
12655 case PROCESSOR_NOCONA:
12662 if (repcount <= max_nonrep)
12663 while (repcount-- > 0)
12665 rtx mem = adjust_automodify_address_nv (dst,
12666 GET_MODE (zeroreg),
12668 emit_insn (gen_strset (destreg, mem, zeroreg));
12673 countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount));
12674 countreg = ix86_zero_extend_to_Pmode (countreg);
12675 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12676 GEN_INT (size == 4 ? 2 : 3));
12677 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12678 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg,
12680 offset = count & ~(size - 1);
12683 if (size == 8 && (count & 0x04))
12685 rtx mem = adjust_automodify_address_nv (dst, SImode, destreg,
12687 emit_insn (gen_strset (destreg, mem,
12688 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12693 rtx mem = adjust_automodify_address_nv (dst, HImode, destreg,
12695 emit_insn (gen_strset (destreg, mem,
12696 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12701 rtx mem = adjust_automodify_address_nv (dst, QImode, destreg,
12703 emit_insn (gen_strset (destreg, mem,
12704 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12711 /* Compute desired alignment of the string operation. */
12712 int desired_alignment = (TARGET_PENTIUMPRO
12713 && (count == 0 || count >= (unsigned int) 260)
12714 ? 8 : UNITS_PER_WORD);
12716 /* In case we don't know anything about the alignment, default to
12717 library version, since it is usually equally fast and result in
12720 Also emit call when we know that the count is large and call overhead
12721 will not be important. */
12722 if (!TARGET_INLINE_ALL_STRINGOPS
12723 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12726 if (TARGET_SINGLE_STRINGOP)
12727 emit_insn (gen_cld ());
12729 countreg2 = gen_reg_rtx (Pmode);
12730 countreg = copy_to_mode_reg (counter_mode, count_exp);
12731 zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
12732 /* Get rid of MEM_OFFSET, it won't be accurate. */
12733 dst = change_address (dst, BLKmode, destreg);
12735 if (count == 0 && align < desired_alignment)
12737 label = gen_label_rtx ();
12738 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12739 LEU, 0, counter_mode, 1, label);
12743 rtx label = ix86_expand_aligntest (destreg, 1);
12744 emit_insn (gen_strset (destreg, dst,
12745 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12746 ix86_adjust_counter (countreg, 1);
12747 emit_label (label);
12748 LABEL_NUSES (label) = 1;
12752 rtx label = ix86_expand_aligntest (destreg, 2);
12753 emit_insn (gen_strset (destreg, dst,
12754 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12755 ix86_adjust_counter (countreg, 2);
12756 emit_label (label);
12757 LABEL_NUSES (label) = 1;
12759 if (align <= 4 && desired_alignment > 4)
12761 rtx label = ix86_expand_aligntest (destreg, 4);
12762 emit_insn (gen_strset (destreg, dst,
12764 ? gen_rtx_SUBREG (SImode, zeroreg, 0)
12766 ix86_adjust_counter (countreg, 4);
12767 emit_label (label);
12768 LABEL_NUSES (label) = 1;
12771 if (label && desired_alignment > 4 && !TARGET_64BIT)
12773 emit_label (label);
12774 LABEL_NUSES (label) = 1;
12778 if (!TARGET_SINGLE_STRINGOP)
12779 emit_insn (gen_cld ());
12782 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12784 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12788 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12789 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12791 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12792 emit_insn (gen_rep_stos (destreg, countreg2, dst, zeroreg, destexp));
12796 emit_label (label);
12797 LABEL_NUSES (label) = 1;
12800 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12801 emit_insn (gen_strset (destreg, dst,
12802 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12803 if (TARGET_64BIT && (align <= 4 || count == 0))
12805 rtx label = ix86_expand_aligntest (countreg, 4);
12806 emit_insn (gen_strset (destreg, dst,
12807 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12808 emit_label (label);
12809 LABEL_NUSES (label) = 1;
12811 if (align > 2 && count != 0 && (count & 2))
12812 emit_insn (gen_strset (destreg, dst,
12813 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12814 if (align <= 2 || count == 0)
12816 rtx label = ix86_expand_aligntest (countreg, 2);
12817 emit_insn (gen_strset (destreg, dst,
12818 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12819 emit_label (label);
12820 LABEL_NUSES (label) = 1;
12822 if (align > 1 && count != 0 && (count & 1))
12823 emit_insn (gen_strset (destreg, dst,
12824 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12825 if (align <= 1 || count == 0)
12827 rtx label = ix86_expand_aligntest (countreg, 1);
12828 emit_insn (gen_strset (destreg, dst,
12829 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12830 emit_label (label);
12831 LABEL_NUSES (label) = 1;
12837 /* Expand strlen. */
12839 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
12841 rtx addr, scratch1, scratch2, scratch3, scratch4;
12843 /* The generic case of strlen expander is long. Avoid it's
12844 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12846 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12847 && !TARGET_INLINE_ALL_STRINGOPS
12849 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12852 addr = force_reg (Pmode, XEXP (src, 0));
12853 scratch1 = gen_reg_rtx (Pmode);
12855 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12858 /* Well it seems that some optimizer does not combine a call like
12859 foo(strlen(bar), strlen(bar));
12860 when the move and the subtraction is done here. It does calculate
12861 the length just once when these instructions are done inside of
12862 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12863 often used and I use one fewer register for the lifetime of
12864 output_strlen_unroll() this is better. */
12866 emit_move_insn (out, addr);
12868 ix86_expand_strlensi_unroll_1 (out, src, align);
12870 /* strlensi_unroll_1 returns the address of the zero at the end of
12871 the string, like memchr(), so compute the length by subtracting
12872 the start address. */
12874 emit_insn (gen_subdi3 (out, out, addr));
12876 emit_insn (gen_subsi3 (out, out, addr));
12881 scratch2 = gen_reg_rtx (Pmode);
12882 scratch3 = gen_reg_rtx (Pmode);
12883 scratch4 = force_reg (Pmode, constm1_rtx);
12885 emit_move_insn (scratch3, addr);
12886 eoschar = force_reg (QImode, eoschar);
12888 emit_insn (gen_cld ());
12889 src = replace_equiv_address_nv (src, scratch3);
12891 /* If .md starts supporting :P, this can be done in .md. */
12892 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
12893 scratch4), UNSPEC_SCAS);
12894 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
12897 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
12898 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
12902 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12903 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12909 /* Expand the appropriate insns for doing strlen if not just doing
12912 out = result, initialized with the start address
12913 align_rtx = alignment of the address.
12914 scratch = scratch register, initialized with the startaddress when
12915 not aligned, otherwise undefined
12917 This is just the body. It needs the initializations mentioned above and
12918 some address computing at the end. These things are done in i386.md. */
12921 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
12925 rtx align_2_label = NULL_RTX;
12926 rtx align_3_label = NULL_RTX;
12927 rtx align_4_label = gen_label_rtx ();
12928 rtx end_0_label = gen_label_rtx ();
12930 rtx tmpreg = gen_reg_rtx (SImode);
12931 rtx scratch = gen_reg_rtx (SImode);
12935 if (GET_CODE (align_rtx) == CONST_INT)
12936 align = INTVAL (align_rtx);
12938 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
12940 /* Is there a known alignment and is it less than 4? */
12943 rtx scratch1 = gen_reg_rtx (Pmode);
12944 emit_move_insn (scratch1, out);
12945 /* Is there a known alignment and is it not 2? */
12948 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
12949 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
12951 /* Leave just the 3 lower bits. */
12952 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
12953 NULL_RTX, 0, OPTAB_WIDEN);
12955 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12956 Pmode, 1, align_4_label);
12957 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
12958 Pmode, 1, align_2_label);
12959 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
12960 Pmode, 1, align_3_label);
12964 /* Since the alignment is 2, we have to check 2 or 0 bytes;
12965 check if is aligned to 4 - byte. */
12967 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
12968 NULL_RTX, 0, OPTAB_WIDEN);
12970 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12971 Pmode, 1, align_4_label);
12974 mem = change_address (src, QImode, out);
12976 /* Now compare the bytes. */
12978 /* Compare the first n unaligned byte on a byte per byte basis. */
12979 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
12980 QImode, 1, end_0_label);
12982 /* Increment the address. */
12984 emit_insn (gen_adddi3 (out, out, const1_rtx));
12986 emit_insn (gen_addsi3 (out, out, const1_rtx));
12988 /* Not needed with an alignment of 2 */
12991 emit_label (align_2_label);
12993 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12997 emit_insn (gen_adddi3 (out, out, const1_rtx));
12999 emit_insn (gen_addsi3 (out, out, const1_rtx));
13001 emit_label (align_3_label);
13004 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
13008 emit_insn (gen_adddi3 (out, out, const1_rtx));
13010 emit_insn (gen_addsi3 (out, out, const1_rtx));
13013 /* Generate loop to check 4 bytes at a time. It is not a good idea to
13014 align this loop. It gives only huge programs, but does not help to
13016 emit_label (align_4_label);
13018 mem = change_address (src, SImode, out);
13019 emit_move_insn (scratch, mem);
13021 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
13023 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
13025 /* This formula yields a nonzero result iff one of the bytes is zero.
13026 This saves three branches inside loop and many cycles. */
13028 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
13029 emit_insn (gen_one_cmplsi2 (scratch, scratch));
13030 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
13031 emit_insn (gen_andsi3 (tmpreg, tmpreg,
13032 gen_int_mode (0x80808080, SImode)));
13033 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
13038 rtx reg = gen_reg_rtx (SImode);
13039 rtx reg2 = gen_reg_rtx (Pmode);
13040 emit_move_insn (reg, tmpreg);
13041 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
13043 /* If zero is not in the first two bytes, move two bytes forward. */
13044 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
13045 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13046 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
13047 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
13048 gen_rtx_IF_THEN_ELSE (SImode, tmp,
13051 /* Emit lea manually to avoid clobbering of flags. */
13052 emit_insn (gen_rtx_SET (SImode, reg2,
13053 gen_rtx_PLUS (Pmode, out, const2_rtx)));
13055 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13056 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
13057 emit_insn (gen_rtx_SET (VOIDmode, out,
13058 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
13065 rtx end_2_label = gen_label_rtx ();
13066 /* Is zero in the first two bytes? */
13068 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
13069 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13070 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
13071 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13072 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
13074 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
13075 JUMP_LABEL (tmp) = end_2_label;
13077 /* Not in the first two. Move two bytes forward. */
13078 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
13080 emit_insn (gen_adddi3 (out, out, const2_rtx));
13082 emit_insn (gen_addsi3 (out, out, const2_rtx));
13084 emit_label (end_2_label);
13088 /* Avoid branch in fixing the byte. */
13089 tmpreg = gen_lowpart (QImode, tmpreg);
13090 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
13091 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
13093 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
13095 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
13097 emit_label (end_0_label);
13101 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
13102 rtx callarg2 ATTRIBUTE_UNUSED,
13103 rtx pop, int sibcall)
13105 rtx use = NULL, call;
13107 if (pop == const0_rtx)
13109 gcc_assert (!TARGET_64BIT || !pop);
13112 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
13113 fnaddr = machopic_indirect_call_target (fnaddr);
13115 /* Static functions and indirect calls don't need the pic register. */
13116 if (! TARGET_64BIT && flag_pic
13117 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
13118 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
13119 use_reg (&use, pic_offset_table_rtx);
13121 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
13123 rtx al = gen_rtx_REG (QImode, 0);
13124 emit_move_insn (al, callarg2);
13125 use_reg (&use, al);
13127 #endif /* TARGET_MACHO */
13129 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
13131 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
13132 fnaddr = gen_rtx_MEM (QImode, fnaddr);
13134 if (sibcall && TARGET_64BIT
13135 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
13138 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
13139 fnaddr = gen_rtx_REG (Pmode, FIRST_REX_INT_REG + 3 /* R11 */);
13140 emit_move_insn (fnaddr, addr);
13141 fnaddr = gen_rtx_MEM (QImode, fnaddr);
13144 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
13146 call = gen_rtx_SET (VOIDmode, retval, call);
13149 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
13150 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
13151 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
13154 call = emit_call_insn (call);
13156 CALL_INSN_FUNCTION_USAGE (call) = use;
13160 /* Clear stack slot assignments remembered from previous functions.
13161 This is called from INIT_EXPANDERS once before RTL is emitted for each
13164 static struct machine_function *
13165 ix86_init_machine_status (void)
13167 struct machine_function *f;
13169 f = ggc_alloc_cleared (sizeof (struct machine_function));
13170 f->use_fast_prologue_epilogue_nregs = -1;
13171 f->tls_descriptor_call_expanded_p = 0;
13176 /* Return a MEM corresponding to a stack slot with mode MODE.
13177 Allocate a new slot if necessary.
13179 The RTL for a function can have several slots available: N is
13180 which slot to use. */
13183 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
13185 struct stack_local_entry *s;
13187 gcc_assert (n < MAX_386_STACK_LOCALS);
13189 for (s = ix86_stack_locals; s; s = s->next)
13190 if (s->mode == mode && s->n == n)
13193 s = (struct stack_local_entry *)
13194 ggc_alloc (sizeof (struct stack_local_entry));
13197 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13199 s->next = ix86_stack_locals;
13200 ix86_stack_locals = s;
13204 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13206 static GTY(()) rtx ix86_tls_symbol;
13208 ix86_tls_get_addr (void)
13211 if (!ix86_tls_symbol)
13213 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
13214 (TARGET_ANY_GNU_TLS
13216 ? "___tls_get_addr"
13217 : "__tls_get_addr");
13220 return ix86_tls_symbol;
13223 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13225 static GTY(()) rtx ix86_tls_module_base_symbol;
13227 ix86_tls_module_base (void)
13230 if (!ix86_tls_module_base_symbol)
13232 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
13233 "_TLS_MODULE_BASE_");
13234 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
13235 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
13238 return ix86_tls_module_base_symbol;
13241 /* Calculate the length of the memory address in the instruction
13242 encoding. Does not include the one-byte modrm, opcode, or prefix. */
13245 memory_address_length (rtx addr)
13247 struct ix86_address parts;
13248 rtx base, index, disp;
13252 if (GET_CODE (addr) == PRE_DEC
13253 || GET_CODE (addr) == POST_INC
13254 || GET_CODE (addr) == PRE_MODIFY
13255 || GET_CODE (addr) == POST_MODIFY)
13258 ok = ix86_decompose_address (addr, &parts);
13261 if (parts.base && GET_CODE (parts.base) == SUBREG)
13262 parts.base = SUBREG_REG (parts.base);
13263 if (parts.index && GET_CODE (parts.index) == SUBREG)
13264 parts.index = SUBREG_REG (parts.index);
13267 index = parts.index;
13272 - esp as the base always wants an index,
13273 - ebp as the base always wants a displacement. */
13275 /* Register Indirect. */
13276 if (base && !index && !disp)
13278 /* esp (for its index) and ebp (for its displacement) need
13279 the two-byte modrm form. */
13280 if (addr == stack_pointer_rtx
13281 || addr == arg_pointer_rtx
13282 || addr == frame_pointer_rtx
13283 || addr == hard_frame_pointer_rtx)
13287 /* Direct Addressing. */
13288 else if (disp && !base && !index)
13293 /* Find the length of the displacement constant. */
13296 if (base && satisfies_constraint_K (disp))
13301 /* ebp always wants a displacement. */
13302 else if (base == hard_frame_pointer_rtx)
13305 /* An index requires the two-byte modrm form.... */
13307 /* ...like esp, which always wants an index. */
13308 || base == stack_pointer_rtx
13309 || base == arg_pointer_rtx
13310 || base == frame_pointer_rtx)
13317 /* Compute default value for "length_immediate" attribute. When SHORTFORM
13318 is set, expect that insn have 8bit immediate alternative. */
13320 ix86_attr_length_immediate_default (rtx insn, int shortform)
13324 extract_insn_cached (insn);
13325 for (i = recog_data.n_operands - 1; i >= 0; --i)
13326 if (CONSTANT_P (recog_data.operand[i]))
13329 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
13333 switch (get_attr_mode (insn))
13344 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
13349 fatal_insn ("unknown insn mode", insn);
13355 /* Compute default value for "length_address" attribute. */
13357 ix86_attr_length_address_default (rtx insn)
13361 if (get_attr_type (insn) == TYPE_LEA)
13363 rtx set = PATTERN (insn);
13365 if (GET_CODE (set) == PARALLEL)
13366 set = XVECEXP (set, 0, 0);
13368 gcc_assert (GET_CODE (set) == SET);
13370 return memory_address_length (SET_SRC (set));
13373 extract_insn_cached (insn);
13374 for (i = recog_data.n_operands - 1; i >= 0; --i)
13375 if (GET_CODE (recog_data.operand[i]) == MEM)
13377 return memory_address_length (XEXP (recog_data.operand[i], 0));
13383 /* Return the maximum number of instructions a cpu can issue. */
13386 ix86_issue_rate (void)
13390 case PROCESSOR_PENTIUM:
13394 case PROCESSOR_PENTIUMPRO:
13395 case PROCESSOR_PENTIUM4:
13396 case PROCESSOR_ATHLON:
13398 case PROCESSOR_NOCONA:
13399 case PROCESSOR_GENERIC32:
13400 case PROCESSOR_GENERIC64:
13408 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
13409 by DEP_INSN and nothing set by DEP_INSN. */
13412 ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
13416 /* Simplify the test for uninteresting insns. */
13417 if (insn_type != TYPE_SETCC
13418 && insn_type != TYPE_ICMOV
13419 && insn_type != TYPE_FCMOV
13420 && insn_type != TYPE_IBR)
13423 if ((set = single_set (dep_insn)) != 0)
13425 set = SET_DEST (set);
13428 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
13429 && XVECLEN (PATTERN (dep_insn), 0) == 2
13430 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
13431 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
13433 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13434 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13439 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
13442 /* This test is true if the dependent insn reads the flags but
13443 not any other potentially set register. */
13444 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
13447 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
13453 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
13454 address with operands set by DEP_INSN. */
13457 ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
13461 if (insn_type == TYPE_LEA
13464 addr = PATTERN (insn);
13466 if (GET_CODE (addr) == PARALLEL)
13467 addr = XVECEXP (addr, 0, 0);
13469 gcc_assert (GET_CODE (addr) == SET);
13471 addr = SET_SRC (addr);
13476 extract_insn_cached (insn);
13477 for (i = recog_data.n_operands - 1; i >= 0; --i)
13478 if (GET_CODE (recog_data.operand[i]) == MEM)
13480 addr = XEXP (recog_data.operand[i], 0);
13487 return modified_in_p (addr, dep_insn);
13491 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
13493 enum attr_type insn_type, dep_insn_type;
13494 enum attr_memory memory;
13496 int dep_insn_code_number;
13498 /* Anti and output dependencies have zero cost on all CPUs. */
13499 if (REG_NOTE_KIND (link) != 0)
13502 dep_insn_code_number = recog_memoized (dep_insn);
13504 /* If we can't recognize the insns, we can't really do anything. */
13505 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
13508 insn_type = get_attr_type (insn);
13509 dep_insn_type = get_attr_type (dep_insn);
13513 case PROCESSOR_PENTIUM:
13514 /* Address Generation Interlock adds a cycle of latency. */
13515 if (ix86_agi_dependant (insn, dep_insn, insn_type))
13518 /* ??? Compares pair with jump/setcc. */
13519 if (ix86_flags_dependant (insn, dep_insn, insn_type))
13522 /* Floating point stores require value to be ready one cycle earlier. */
13523 if (insn_type == TYPE_FMOV
13524 && get_attr_memory (insn) == MEMORY_STORE
13525 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13529 case PROCESSOR_PENTIUMPRO:
13530 memory = get_attr_memory (insn);
13532 /* INT->FP conversion is expensive. */
13533 if (get_attr_fp_int_src (dep_insn))
13536 /* There is one cycle extra latency between an FP op and a store. */
13537 if (insn_type == TYPE_FMOV
13538 && (set = single_set (dep_insn)) != NULL_RTX
13539 && (set2 = single_set (insn)) != NULL_RTX
13540 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
13541 && GET_CODE (SET_DEST (set2)) == MEM)
13544 /* Show ability of reorder buffer to hide latency of load by executing
13545 in parallel with previous instruction in case
13546 previous instruction is not needed to compute the address. */
13547 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13548 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13550 /* Claim moves to take one cycle, as core can issue one load
13551 at time and the next load can start cycle later. */
13552 if (dep_insn_type == TYPE_IMOV
13553 || dep_insn_type == TYPE_FMOV)
13561 memory = get_attr_memory (insn);
13563 /* The esp dependency is resolved before the instruction is really
13565 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
13566 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
13569 /* INT->FP conversion is expensive. */
13570 if (get_attr_fp_int_src (dep_insn))
13573 /* Show ability of reorder buffer to hide latency of load by executing
13574 in parallel with previous instruction in case
13575 previous instruction is not needed to compute the address. */
13576 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13577 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13579 /* Claim moves to take one cycle, as core can issue one load
13580 at time and the next load can start cycle later. */
13581 if (dep_insn_type == TYPE_IMOV
13582 || dep_insn_type == TYPE_FMOV)
13591 case PROCESSOR_ATHLON:
13593 case PROCESSOR_GENERIC32:
13594 case PROCESSOR_GENERIC64:
13595 memory = get_attr_memory (insn);
13597 /* Show ability of reorder buffer to hide latency of load by executing
13598 in parallel with previous instruction in case
13599 previous instruction is not needed to compute the address. */
13600 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13601 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13603 enum attr_unit unit = get_attr_unit (insn);
13606 /* Because of the difference between the length of integer and
13607 floating unit pipeline preparation stages, the memory operands
13608 for floating point are cheaper.
13610 ??? For Athlon it the difference is most probably 2. */
13611 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
13614 loadcost = TARGET_ATHLON ? 2 : 0;
13616 if (cost >= loadcost)
13629 /* How many alternative schedules to try. This should be as wide as the
13630 scheduling freedom in the DFA, but no wider. Making this value too
13631 large results extra work for the scheduler. */
13634 ia32_multipass_dfa_lookahead (void)
13636 if (ix86_tune == PROCESSOR_PENTIUM)
13639 if (ix86_tune == PROCESSOR_PENTIUMPRO
13640 || ix86_tune == PROCESSOR_K6)
13648 /* Compute the alignment given to a constant that is being placed in memory.
13649 EXP is the constant and ALIGN is the alignment that the object would
13651 The value of this function is used instead of that alignment to align
13655 ix86_constant_alignment (tree exp, int align)
13657 if (TREE_CODE (exp) == REAL_CST)
13659 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
13661 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
13664 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
13665 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
13666 return BITS_PER_WORD;
13671 /* Compute the alignment for a static variable.
13672 TYPE is the data type, and ALIGN is the alignment that
13673 the object would ordinarily have. The value of this function is used
13674 instead of that alignment to align the object. */
13677 ix86_data_alignment (tree type, int align)
13679 int max_align = optimize_size ? BITS_PER_WORD : 256;
13681 if (AGGREGATE_TYPE_P (type)
13682 && TYPE_SIZE (type)
13683 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13684 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
13685 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
13686 && align < max_align)
13689 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13690 to 16byte boundary. */
13693 if (AGGREGATE_TYPE_P (type)
13694 && TYPE_SIZE (type)
13695 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13696 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
13697 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13701 if (TREE_CODE (type) == ARRAY_TYPE)
13703 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13705 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13708 else if (TREE_CODE (type) == COMPLEX_TYPE)
13711 if (TYPE_MODE (type) == DCmode && align < 64)
13713 if (TYPE_MODE (type) == XCmode && align < 128)
13716 else if ((TREE_CODE (type) == RECORD_TYPE
13717 || TREE_CODE (type) == UNION_TYPE
13718 || TREE_CODE (type) == QUAL_UNION_TYPE)
13719 && TYPE_FIELDS (type))
13721 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13723 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13726 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13727 || TREE_CODE (type) == INTEGER_TYPE)
13729 if (TYPE_MODE (type) == DFmode && align < 64)
13731 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13738 /* Compute the alignment for a local variable.
13739 TYPE is the data type, and ALIGN is the alignment that
13740 the object would ordinarily have. The value of this macro is used
13741 instead of that alignment to align the object. */
13744 ix86_local_alignment (tree type, int align)
13746 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13747 to 16byte boundary. */
13750 if (AGGREGATE_TYPE_P (type)
13751 && TYPE_SIZE (type)
13752 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13753 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
13754 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13757 if (TREE_CODE (type) == ARRAY_TYPE)
13759 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13761 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13764 else if (TREE_CODE (type) == COMPLEX_TYPE)
13766 if (TYPE_MODE (type) == DCmode && align < 64)
13768 if (TYPE_MODE (type) == XCmode && align < 128)
13771 else if ((TREE_CODE (type) == RECORD_TYPE
13772 || TREE_CODE (type) == UNION_TYPE
13773 || TREE_CODE (type) == QUAL_UNION_TYPE)
13774 && TYPE_FIELDS (type))
13776 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13778 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13781 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13782 || TREE_CODE (type) == INTEGER_TYPE)
13785 if (TYPE_MODE (type) == DFmode && align < 64)
13787 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13793 /* Emit RTL insns to initialize the variable parts of a trampoline.
13794 FNADDR is an RTX for the address of the function's pure code.
13795 CXT is an RTX for the static chain value for the function. */
13797 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
13801 /* Compute offset from the end of the jmp to the target function. */
13802 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
13803 plus_constant (tramp, 10),
13804 NULL_RTX, 1, OPTAB_DIRECT);
13805 emit_move_insn (gen_rtx_MEM (QImode, tramp),
13806 gen_int_mode (0xb9, QImode));
13807 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
13808 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
13809 gen_int_mode (0xe9, QImode));
13810 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
13815 /* Try to load address using shorter movl instead of movabs.
13816 We may want to support movq for kernel mode, but kernel does not use
13817 trampolines at the moment. */
13818 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
13820 fnaddr = copy_to_mode_reg (DImode, fnaddr);
13821 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13822 gen_int_mode (0xbb41, HImode));
13823 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
13824 gen_lowpart (SImode, fnaddr));
13829 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13830 gen_int_mode (0xbb49, HImode));
13831 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13835 /* Load static chain using movabs to r10. */
13836 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13837 gen_int_mode (0xba49, HImode));
13838 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13841 /* Jump to the r11 */
13842 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13843 gen_int_mode (0xff49, HImode));
13844 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
13845 gen_int_mode (0xe3, QImode));
13847 gcc_assert (offset <= TRAMPOLINE_SIZE);
13850 #ifdef ENABLE_EXECUTE_STACK
13851 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
13852 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
13856 /* Codes for all the SSE/MMX builtins. */
13859 IX86_BUILTIN_ADDPS,
13860 IX86_BUILTIN_ADDSS,
13861 IX86_BUILTIN_DIVPS,
13862 IX86_BUILTIN_DIVSS,
13863 IX86_BUILTIN_MULPS,
13864 IX86_BUILTIN_MULSS,
13865 IX86_BUILTIN_SUBPS,
13866 IX86_BUILTIN_SUBSS,
13868 IX86_BUILTIN_CMPEQPS,
13869 IX86_BUILTIN_CMPLTPS,
13870 IX86_BUILTIN_CMPLEPS,
13871 IX86_BUILTIN_CMPGTPS,
13872 IX86_BUILTIN_CMPGEPS,
13873 IX86_BUILTIN_CMPNEQPS,
13874 IX86_BUILTIN_CMPNLTPS,
13875 IX86_BUILTIN_CMPNLEPS,
13876 IX86_BUILTIN_CMPNGTPS,
13877 IX86_BUILTIN_CMPNGEPS,
13878 IX86_BUILTIN_CMPORDPS,
13879 IX86_BUILTIN_CMPUNORDPS,
13880 IX86_BUILTIN_CMPEQSS,
13881 IX86_BUILTIN_CMPLTSS,
13882 IX86_BUILTIN_CMPLESS,
13883 IX86_BUILTIN_CMPNEQSS,
13884 IX86_BUILTIN_CMPNLTSS,
13885 IX86_BUILTIN_CMPNLESS,
13886 IX86_BUILTIN_CMPNGTSS,
13887 IX86_BUILTIN_CMPNGESS,
13888 IX86_BUILTIN_CMPORDSS,
13889 IX86_BUILTIN_CMPUNORDSS,
13891 IX86_BUILTIN_COMIEQSS,
13892 IX86_BUILTIN_COMILTSS,
13893 IX86_BUILTIN_COMILESS,
13894 IX86_BUILTIN_COMIGTSS,
13895 IX86_BUILTIN_COMIGESS,
13896 IX86_BUILTIN_COMINEQSS,
13897 IX86_BUILTIN_UCOMIEQSS,
13898 IX86_BUILTIN_UCOMILTSS,
13899 IX86_BUILTIN_UCOMILESS,
13900 IX86_BUILTIN_UCOMIGTSS,
13901 IX86_BUILTIN_UCOMIGESS,
13902 IX86_BUILTIN_UCOMINEQSS,
13904 IX86_BUILTIN_CVTPI2PS,
13905 IX86_BUILTIN_CVTPS2PI,
13906 IX86_BUILTIN_CVTSI2SS,
13907 IX86_BUILTIN_CVTSI642SS,
13908 IX86_BUILTIN_CVTSS2SI,
13909 IX86_BUILTIN_CVTSS2SI64,
13910 IX86_BUILTIN_CVTTPS2PI,
13911 IX86_BUILTIN_CVTTSS2SI,
13912 IX86_BUILTIN_CVTTSS2SI64,
13914 IX86_BUILTIN_MAXPS,
13915 IX86_BUILTIN_MAXSS,
13916 IX86_BUILTIN_MINPS,
13917 IX86_BUILTIN_MINSS,
13919 IX86_BUILTIN_LOADUPS,
13920 IX86_BUILTIN_STOREUPS,
13921 IX86_BUILTIN_MOVSS,
13923 IX86_BUILTIN_MOVHLPS,
13924 IX86_BUILTIN_MOVLHPS,
13925 IX86_BUILTIN_LOADHPS,
13926 IX86_BUILTIN_LOADLPS,
13927 IX86_BUILTIN_STOREHPS,
13928 IX86_BUILTIN_STORELPS,
13930 IX86_BUILTIN_MASKMOVQ,
13931 IX86_BUILTIN_MOVMSKPS,
13932 IX86_BUILTIN_PMOVMSKB,
13934 IX86_BUILTIN_MOVNTPS,
13935 IX86_BUILTIN_MOVNTQ,
13937 IX86_BUILTIN_LOADDQU,
13938 IX86_BUILTIN_STOREDQU,
13940 IX86_BUILTIN_PACKSSWB,
13941 IX86_BUILTIN_PACKSSDW,
13942 IX86_BUILTIN_PACKUSWB,
13944 IX86_BUILTIN_PADDB,
13945 IX86_BUILTIN_PADDW,
13946 IX86_BUILTIN_PADDD,
13947 IX86_BUILTIN_PADDQ,
13948 IX86_BUILTIN_PADDSB,
13949 IX86_BUILTIN_PADDSW,
13950 IX86_BUILTIN_PADDUSB,
13951 IX86_BUILTIN_PADDUSW,
13952 IX86_BUILTIN_PSUBB,
13953 IX86_BUILTIN_PSUBW,
13954 IX86_BUILTIN_PSUBD,
13955 IX86_BUILTIN_PSUBQ,
13956 IX86_BUILTIN_PSUBSB,
13957 IX86_BUILTIN_PSUBSW,
13958 IX86_BUILTIN_PSUBUSB,
13959 IX86_BUILTIN_PSUBUSW,
13962 IX86_BUILTIN_PANDN,
13966 IX86_BUILTIN_PAVGB,
13967 IX86_BUILTIN_PAVGW,
13969 IX86_BUILTIN_PCMPEQB,
13970 IX86_BUILTIN_PCMPEQW,
13971 IX86_BUILTIN_PCMPEQD,
13972 IX86_BUILTIN_PCMPGTB,
13973 IX86_BUILTIN_PCMPGTW,
13974 IX86_BUILTIN_PCMPGTD,
13976 IX86_BUILTIN_PMADDWD,
13978 IX86_BUILTIN_PMAXSW,
13979 IX86_BUILTIN_PMAXUB,
13980 IX86_BUILTIN_PMINSW,
13981 IX86_BUILTIN_PMINUB,
13983 IX86_BUILTIN_PMULHUW,
13984 IX86_BUILTIN_PMULHW,
13985 IX86_BUILTIN_PMULLW,
13987 IX86_BUILTIN_PSADBW,
13988 IX86_BUILTIN_PSHUFW,
13990 IX86_BUILTIN_PSLLW,
13991 IX86_BUILTIN_PSLLD,
13992 IX86_BUILTIN_PSLLQ,
13993 IX86_BUILTIN_PSRAW,
13994 IX86_BUILTIN_PSRAD,
13995 IX86_BUILTIN_PSRLW,
13996 IX86_BUILTIN_PSRLD,
13997 IX86_BUILTIN_PSRLQ,
13998 IX86_BUILTIN_PSLLWI,
13999 IX86_BUILTIN_PSLLDI,
14000 IX86_BUILTIN_PSLLQI,
14001 IX86_BUILTIN_PSRAWI,
14002 IX86_BUILTIN_PSRADI,
14003 IX86_BUILTIN_PSRLWI,
14004 IX86_BUILTIN_PSRLDI,
14005 IX86_BUILTIN_PSRLQI,
14007 IX86_BUILTIN_PUNPCKHBW,
14008 IX86_BUILTIN_PUNPCKHWD,
14009 IX86_BUILTIN_PUNPCKHDQ,
14010 IX86_BUILTIN_PUNPCKLBW,
14011 IX86_BUILTIN_PUNPCKLWD,
14012 IX86_BUILTIN_PUNPCKLDQ,
14014 IX86_BUILTIN_SHUFPS,
14016 IX86_BUILTIN_RCPPS,
14017 IX86_BUILTIN_RCPSS,
14018 IX86_BUILTIN_RSQRTPS,
14019 IX86_BUILTIN_RSQRTSS,
14020 IX86_BUILTIN_SQRTPS,
14021 IX86_BUILTIN_SQRTSS,
14023 IX86_BUILTIN_UNPCKHPS,
14024 IX86_BUILTIN_UNPCKLPS,
14026 IX86_BUILTIN_ANDPS,
14027 IX86_BUILTIN_ANDNPS,
14029 IX86_BUILTIN_XORPS,
14032 IX86_BUILTIN_LDMXCSR,
14033 IX86_BUILTIN_STMXCSR,
14034 IX86_BUILTIN_SFENCE,
14036 /* 3DNow! Original */
14037 IX86_BUILTIN_FEMMS,
14038 IX86_BUILTIN_PAVGUSB,
14039 IX86_BUILTIN_PF2ID,
14040 IX86_BUILTIN_PFACC,
14041 IX86_BUILTIN_PFADD,
14042 IX86_BUILTIN_PFCMPEQ,
14043 IX86_BUILTIN_PFCMPGE,
14044 IX86_BUILTIN_PFCMPGT,
14045 IX86_BUILTIN_PFMAX,
14046 IX86_BUILTIN_PFMIN,
14047 IX86_BUILTIN_PFMUL,
14048 IX86_BUILTIN_PFRCP,
14049 IX86_BUILTIN_PFRCPIT1,
14050 IX86_BUILTIN_PFRCPIT2,
14051 IX86_BUILTIN_PFRSQIT1,
14052 IX86_BUILTIN_PFRSQRT,
14053 IX86_BUILTIN_PFSUB,
14054 IX86_BUILTIN_PFSUBR,
14055 IX86_BUILTIN_PI2FD,
14056 IX86_BUILTIN_PMULHRW,
14058 /* 3DNow! Athlon Extensions */
14059 IX86_BUILTIN_PF2IW,
14060 IX86_BUILTIN_PFNACC,
14061 IX86_BUILTIN_PFPNACC,
14062 IX86_BUILTIN_PI2FW,
14063 IX86_BUILTIN_PSWAPDSI,
14064 IX86_BUILTIN_PSWAPDSF,
14067 IX86_BUILTIN_ADDPD,
14068 IX86_BUILTIN_ADDSD,
14069 IX86_BUILTIN_DIVPD,
14070 IX86_BUILTIN_DIVSD,
14071 IX86_BUILTIN_MULPD,
14072 IX86_BUILTIN_MULSD,
14073 IX86_BUILTIN_SUBPD,
14074 IX86_BUILTIN_SUBSD,
14076 IX86_BUILTIN_CMPEQPD,
14077 IX86_BUILTIN_CMPLTPD,
14078 IX86_BUILTIN_CMPLEPD,
14079 IX86_BUILTIN_CMPGTPD,
14080 IX86_BUILTIN_CMPGEPD,
14081 IX86_BUILTIN_CMPNEQPD,
14082 IX86_BUILTIN_CMPNLTPD,
14083 IX86_BUILTIN_CMPNLEPD,
14084 IX86_BUILTIN_CMPNGTPD,
14085 IX86_BUILTIN_CMPNGEPD,
14086 IX86_BUILTIN_CMPORDPD,
14087 IX86_BUILTIN_CMPUNORDPD,
14088 IX86_BUILTIN_CMPNEPD,
14089 IX86_BUILTIN_CMPEQSD,
14090 IX86_BUILTIN_CMPLTSD,
14091 IX86_BUILTIN_CMPLESD,
14092 IX86_BUILTIN_CMPNEQSD,
14093 IX86_BUILTIN_CMPNLTSD,
14094 IX86_BUILTIN_CMPNLESD,
14095 IX86_BUILTIN_CMPORDSD,
14096 IX86_BUILTIN_CMPUNORDSD,
14097 IX86_BUILTIN_CMPNESD,
14099 IX86_BUILTIN_COMIEQSD,
14100 IX86_BUILTIN_COMILTSD,
14101 IX86_BUILTIN_COMILESD,
14102 IX86_BUILTIN_COMIGTSD,
14103 IX86_BUILTIN_COMIGESD,
14104 IX86_BUILTIN_COMINEQSD,
14105 IX86_BUILTIN_UCOMIEQSD,
14106 IX86_BUILTIN_UCOMILTSD,
14107 IX86_BUILTIN_UCOMILESD,
14108 IX86_BUILTIN_UCOMIGTSD,
14109 IX86_BUILTIN_UCOMIGESD,
14110 IX86_BUILTIN_UCOMINEQSD,
14112 IX86_BUILTIN_MAXPD,
14113 IX86_BUILTIN_MAXSD,
14114 IX86_BUILTIN_MINPD,
14115 IX86_BUILTIN_MINSD,
14117 IX86_BUILTIN_ANDPD,
14118 IX86_BUILTIN_ANDNPD,
14120 IX86_BUILTIN_XORPD,
14122 IX86_BUILTIN_SQRTPD,
14123 IX86_BUILTIN_SQRTSD,
14125 IX86_BUILTIN_UNPCKHPD,
14126 IX86_BUILTIN_UNPCKLPD,
14128 IX86_BUILTIN_SHUFPD,
14130 IX86_BUILTIN_LOADUPD,
14131 IX86_BUILTIN_STOREUPD,
14132 IX86_BUILTIN_MOVSD,
14134 IX86_BUILTIN_LOADHPD,
14135 IX86_BUILTIN_LOADLPD,
14137 IX86_BUILTIN_CVTDQ2PD,
14138 IX86_BUILTIN_CVTDQ2PS,
14140 IX86_BUILTIN_CVTPD2DQ,
14141 IX86_BUILTIN_CVTPD2PI,
14142 IX86_BUILTIN_CVTPD2PS,
14143 IX86_BUILTIN_CVTTPD2DQ,
14144 IX86_BUILTIN_CVTTPD2PI,
14146 IX86_BUILTIN_CVTPI2PD,
14147 IX86_BUILTIN_CVTSI2SD,
14148 IX86_BUILTIN_CVTSI642SD,
14150 IX86_BUILTIN_CVTSD2SI,
14151 IX86_BUILTIN_CVTSD2SI64,
14152 IX86_BUILTIN_CVTSD2SS,
14153 IX86_BUILTIN_CVTSS2SD,
14154 IX86_BUILTIN_CVTTSD2SI,
14155 IX86_BUILTIN_CVTTSD2SI64,
14157 IX86_BUILTIN_CVTPS2DQ,
14158 IX86_BUILTIN_CVTPS2PD,
14159 IX86_BUILTIN_CVTTPS2DQ,
14161 IX86_BUILTIN_MOVNTI,
14162 IX86_BUILTIN_MOVNTPD,
14163 IX86_BUILTIN_MOVNTDQ,
14166 IX86_BUILTIN_MASKMOVDQU,
14167 IX86_BUILTIN_MOVMSKPD,
14168 IX86_BUILTIN_PMOVMSKB128,
14170 IX86_BUILTIN_PACKSSWB128,
14171 IX86_BUILTIN_PACKSSDW128,
14172 IX86_BUILTIN_PACKUSWB128,
14174 IX86_BUILTIN_PADDB128,
14175 IX86_BUILTIN_PADDW128,
14176 IX86_BUILTIN_PADDD128,
14177 IX86_BUILTIN_PADDQ128,
14178 IX86_BUILTIN_PADDSB128,
14179 IX86_BUILTIN_PADDSW128,
14180 IX86_BUILTIN_PADDUSB128,
14181 IX86_BUILTIN_PADDUSW128,
14182 IX86_BUILTIN_PSUBB128,
14183 IX86_BUILTIN_PSUBW128,
14184 IX86_BUILTIN_PSUBD128,
14185 IX86_BUILTIN_PSUBQ128,
14186 IX86_BUILTIN_PSUBSB128,
14187 IX86_BUILTIN_PSUBSW128,
14188 IX86_BUILTIN_PSUBUSB128,
14189 IX86_BUILTIN_PSUBUSW128,
14191 IX86_BUILTIN_PAND128,
14192 IX86_BUILTIN_PANDN128,
14193 IX86_BUILTIN_POR128,
14194 IX86_BUILTIN_PXOR128,
14196 IX86_BUILTIN_PAVGB128,
14197 IX86_BUILTIN_PAVGW128,
14199 IX86_BUILTIN_PCMPEQB128,
14200 IX86_BUILTIN_PCMPEQW128,
14201 IX86_BUILTIN_PCMPEQD128,
14202 IX86_BUILTIN_PCMPGTB128,
14203 IX86_BUILTIN_PCMPGTW128,
14204 IX86_BUILTIN_PCMPGTD128,
14206 IX86_BUILTIN_PMADDWD128,
14208 IX86_BUILTIN_PMAXSW128,
14209 IX86_BUILTIN_PMAXUB128,
14210 IX86_BUILTIN_PMINSW128,
14211 IX86_BUILTIN_PMINUB128,
14213 IX86_BUILTIN_PMULUDQ,
14214 IX86_BUILTIN_PMULUDQ128,
14215 IX86_BUILTIN_PMULHUW128,
14216 IX86_BUILTIN_PMULHW128,
14217 IX86_BUILTIN_PMULLW128,
14219 IX86_BUILTIN_PSADBW128,
14220 IX86_BUILTIN_PSHUFHW,
14221 IX86_BUILTIN_PSHUFLW,
14222 IX86_BUILTIN_PSHUFD,
14224 IX86_BUILTIN_PSLLW128,
14225 IX86_BUILTIN_PSLLD128,
14226 IX86_BUILTIN_PSLLQ128,
14227 IX86_BUILTIN_PSRAW128,
14228 IX86_BUILTIN_PSRAD128,
14229 IX86_BUILTIN_PSRLW128,
14230 IX86_BUILTIN_PSRLD128,
14231 IX86_BUILTIN_PSRLQ128,
14232 IX86_BUILTIN_PSLLDQI128,
14233 IX86_BUILTIN_PSLLWI128,
14234 IX86_BUILTIN_PSLLDI128,
14235 IX86_BUILTIN_PSLLQI128,
14236 IX86_BUILTIN_PSRAWI128,
14237 IX86_BUILTIN_PSRADI128,
14238 IX86_BUILTIN_PSRLDQI128,
14239 IX86_BUILTIN_PSRLWI128,
14240 IX86_BUILTIN_PSRLDI128,
14241 IX86_BUILTIN_PSRLQI128,
14243 IX86_BUILTIN_PUNPCKHBW128,
14244 IX86_BUILTIN_PUNPCKHWD128,
14245 IX86_BUILTIN_PUNPCKHDQ128,
14246 IX86_BUILTIN_PUNPCKHQDQ128,
14247 IX86_BUILTIN_PUNPCKLBW128,
14248 IX86_BUILTIN_PUNPCKLWD128,
14249 IX86_BUILTIN_PUNPCKLDQ128,
14250 IX86_BUILTIN_PUNPCKLQDQ128,
14252 IX86_BUILTIN_CLFLUSH,
14253 IX86_BUILTIN_MFENCE,
14254 IX86_BUILTIN_LFENCE,
14256 /* Prescott New Instructions. */
14257 IX86_BUILTIN_ADDSUBPS,
14258 IX86_BUILTIN_HADDPS,
14259 IX86_BUILTIN_HSUBPS,
14260 IX86_BUILTIN_MOVSHDUP,
14261 IX86_BUILTIN_MOVSLDUP,
14262 IX86_BUILTIN_ADDSUBPD,
14263 IX86_BUILTIN_HADDPD,
14264 IX86_BUILTIN_HSUBPD,
14265 IX86_BUILTIN_LDDQU,
14267 IX86_BUILTIN_MONITOR,
14268 IX86_BUILTIN_MWAIT,
14270 IX86_BUILTIN_VEC_INIT_V2SI,
14271 IX86_BUILTIN_VEC_INIT_V4HI,
14272 IX86_BUILTIN_VEC_INIT_V8QI,
14273 IX86_BUILTIN_VEC_EXT_V2DF,
14274 IX86_BUILTIN_VEC_EXT_V2DI,
14275 IX86_BUILTIN_VEC_EXT_V4SF,
14276 IX86_BUILTIN_VEC_EXT_V4SI,
14277 IX86_BUILTIN_VEC_EXT_V8HI,
14278 IX86_BUILTIN_VEC_EXT_V2SI,
14279 IX86_BUILTIN_VEC_EXT_V4HI,
14280 IX86_BUILTIN_VEC_SET_V8HI,
14281 IX86_BUILTIN_VEC_SET_V4HI,
14283 /* SSE2 ABI functions. */
14284 IX86_BUILTIN_SSE2_ACOS,
14285 IX86_BUILTIN_SSE2_ACOSF,
14286 IX86_BUILTIN_SSE2_ASIN,
14287 IX86_BUILTIN_SSE2_ASINF,
14288 IX86_BUILTIN_SSE2_ATAN,
14289 IX86_BUILTIN_SSE2_ATANF,
14290 IX86_BUILTIN_SSE2_ATAN2,
14291 IX86_BUILTIN_SSE2_ATAN2F,
14292 IX86_BUILTIN_SSE2_COS,
14293 IX86_BUILTIN_SSE2_COSF,
14294 IX86_BUILTIN_SSE2_EXP,
14295 IX86_BUILTIN_SSE2_EXPF,
14296 IX86_BUILTIN_SSE2_LOG10,
14297 IX86_BUILTIN_SSE2_LOG10F,
14298 IX86_BUILTIN_SSE2_LOG,
14299 IX86_BUILTIN_SSE2_LOGF,
14300 IX86_BUILTIN_SSE2_SIN,
14301 IX86_BUILTIN_SSE2_SINF,
14302 IX86_BUILTIN_SSE2_TAN,
14303 IX86_BUILTIN_SSE2_TANF,
14308 #define def_builtin(MASK, NAME, TYPE, CODE) \
14310 if ((MASK) & target_flags \
14311 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
14312 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
14313 NULL, NULL_TREE); \
14316 /* Bits for builtin_description.flag. */
14318 /* Set when we don't support the comparison natively, and should
14319 swap_comparison in order to support it. */
14320 #define BUILTIN_DESC_SWAP_OPERANDS 1
14322 struct builtin_description
14324 const unsigned int mask;
14325 const enum insn_code icode;
14326 const char *const name;
14327 const enum ix86_builtins code;
14328 const enum rtx_code comparison;
14329 const unsigned int flag;
14332 static const struct builtin_description bdesc_comi[] =
14334 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
14335 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
14336 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
14337 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
14338 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
14339 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
14340 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
14341 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
14342 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
14343 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
14344 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
14345 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
14346 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
14347 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
14348 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
14349 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
14350 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
14351 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
14352 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
14353 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
14354 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
14355 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
14356 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
14357 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
14360 static const struct builtin_description bdesc_2arg[] =
14363 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
14364 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
14365 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
14366 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
14367 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
14368 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
14369 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
14370 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
14372 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
14373 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
14374 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
14375 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
14376 BUILTIN_DESC_SWAP_OPERANDS },
14377 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
14378 BUILTIN_DESC_SWAP_OPERANDS },
14379 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
14380 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
14381 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
14382 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
14383 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
14384 BUILTIN_DESC_SWAP_OPERANDS },
14385 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
14386 BUILTIN_DESC_SWAP_OPERANDS },
14387 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
14388 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
14389 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
14390 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
14391 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
14392 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
14393 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
14394 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
14395 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
14396 BUILTIN_DESC_SWAP_OPERANDS },
14397 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
14398 BUILTIN_DESC_SWAP_OPERANDS },
14399 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
14401 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
14402 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
14403 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
14404 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
14406 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
14407 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
14408 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
14409 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
14411 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
14412 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
14413 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
14414 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
14415 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
14418 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
14419 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
14420 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
14421 { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
14422 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
14423 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
14424 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
14425 { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
14427 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
14428 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
14429 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
14430 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
14431 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
14432 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
14433 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
14434 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
14436 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
14437 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
14438 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
14440 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
14441 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
14442 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
14443 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
14445 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
14446 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
14448 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
14449 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
14450 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
14451 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
14452 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
14453 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
14455 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
14456 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
14457 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
14458 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
14460 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
14461 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
14462 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
14463 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
14464 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
14465 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
14468 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
14469 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
14470 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
14472 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
14473 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
14474 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
14476 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
14477 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
14478 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
14479 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
14480 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
14481 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
14483 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
14484 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
14485 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
14486 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
14487 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
14488 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
14490 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
14491 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
14492 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
14493 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
14495 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
14496 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
14499 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
14500 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
14501 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
14502 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
14503 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
14504 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
14505 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
14506 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
14508 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
14509 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
14510 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
14511 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
14512 BUILTIN_DESC_SWAP_OPERANDS },
14513 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
14514 BUILTIN_DESC_SWAP_OPERANDS },
14515 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
14516 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
14517 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
14518 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
14519 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
14520 BUILTIN_DESC_SWAP_OPERANDS },
14521 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
14522 BUILTIN_DESC_SWAP_OPERANDS },
14523 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
14524 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
14525 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
14526 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
14527 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
14528 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
14529 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
14530 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
14531 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
14533 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
14534 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
14535 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
14536 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
14538 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
14539 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
14540 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
14541 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
14543 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
14544 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
14545 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
14548 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
14549 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
14550 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
14551 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
14552 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
14553 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
14554 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
14555 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
14557 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
14558 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
14559 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
14560 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
14561 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
14562 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
14563 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
14564 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
14566 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
14567 { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
14569 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
14570 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
14571 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
14572 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
14574 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
14575 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
14577 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
14578 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
14579 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
14580 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
14581 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
14582 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
14584 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
14585 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
14586 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
14587 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
14589 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
14590 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
14591 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
14592 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
14593 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
14594 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
14595 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
14596 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
14598 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
14599 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
14600 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
14602 { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
14603 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
14605 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
14606 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
14608 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
14609 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
14610 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
14612 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
14613 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
14614 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
14616 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
14617 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
14619 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
14621 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
14622 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
14623 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
14624 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
14627 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
14628 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
14629 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
14630 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
14631 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
14632 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
14635 static const struct builtin_description bdesc_1arg[] =
14637 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
14638 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
14640 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
14641 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
14642 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
14644 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
14645 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
14646 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
14647 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
14648 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
14649 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
14651 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
14652 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
14654 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
14656 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
14657 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
14659 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
14660 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
14661 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
14662 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
14663 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
14665 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
14667 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
14668 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
14669 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
14670 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
14672 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
14673 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
14674 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
14677 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
14678 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
14682 ix86_init_builtins (void)
14685 ix86_init_mmx_sse_builtins ();
14687 ix86_init_sse_abi_builtins ();
14690 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
14691 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
14694 ix86_init_mmx_sse_builtins (void)
14696 const struct builtin_description * d;
14699 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
14700 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14701 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
14702 tree V2DI_type_node
14703 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
14704 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
14705 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
14706 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
14707 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14708 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14709 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
14711 tree pchar_type_node = build_pointer_type (char_type_node);
14712 tree pcchar_type_node = build_pointer_type (
14713 build_type_variant (char_type_node, 1, 0));
14714 tree pfloat_type_node = build_pointer_type (float_type_node);
14715 tree pcfloat_type_node = build_pointer_type (
14716 build_type_variant (float_type_node, 1, 0));
14717 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
14718 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
14719 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
14722 tree int_ftype_v4sf_v4sf
14723 = build_function_type_list (integer_type_node,
14724 V4SF_type_node, V4SF_type_node, NULL_TREE);
14725 tree v4si_ftype_v4sf_v4sf
14726 = build_function_type_list (V4SI_type_node,
14727 V4SF_type_node, V4SF_type_node, NULL_TREE);
14728 /* MMX/SSE/integer conversions. */
14729 tree int_ftype_v4sf
14730 = build_function_type_list (integer_type_node,
14731 V4SF_type_node, NULL_TREE);
14732 tree int64_ftype_v4sf
14733 = build_function_type_list (long_long_integer_type_node,
14734 V4SF_type_node, NULL_TREE);
14735 tree int_ftype_v8qi
14736 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
14737 tree v4sf_ftype_v4sf_int
14738 = build_function_type_list (V4SF_type_node,
14739 V4SF_type_node, integer_type_node, NULL_TREE);
14740 tree v4sf_ftype_v4sf_int64
14741 = build_function_type_list (V4SF_type_node,
14742 V4SF_type_node, long_long_integer_type_node,
14744 tree v4sf_ftype_v4sf_v2si
14745 = build_function_type_list (V4SF_type_node,
14746 V4SF_type_node, V2SI_type_node, NULL_TREE);
14748 /* Miscellaneous. */
14749 tree v8qi_ftype_v4hi_v4hi
14750 = build_function_type_list (V8QI_type_node,
14751 V4HI_type_node, V4HI_type_node, NULL_TREE);
14752 tree v4hi_ftype_v2si_v2si
14753 = build_function_type_list (V4HI_type_node,
14754 V2SI_type_node, V2SI_type_node, NULL_TREE);
14755 tree v4sf_ftype_v4sf_v4sf_int
14756 = build_function_type_list (V4SF_type_node,
14757 V4SF_type_node, V4SF_type_node,
14758 integer_type_node, NULL_TREE);
14759 tree v2si_ftype_v4hi_v4hi
14760 = build_function_type_list (V2SI_type_node,
14761 V4HI_type_node, V4HI_type_node, NULL_TREE);
14762 tree v4hi_ftype_v4hi_int
14763 = build_function_type_list (V4HI_type_node,
14764 V4HI_type_node, integer_type_node, NULL_TREE);
14765 tree v4hi_ftype_v4hi_di
14766 = build_function_type_list (V4HI_type_node,
14767 V4HI_type_node, long_long_unsigned_type_node,
14769 tree v2si_ftype_v2si_di
14770 = build_function_type_list (V2SI_type_node,
14771 V2SI_type_node, long_long_unsigned_type_node,
14773 tree void_ftype_void
14774 = build_function_type (void_type_node, void_list_node);
14775 tree void_ftype_unsigned
14776 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
14777 tree void_ftype_unsigned_unsigned
14778 = build_function_type_list (void_type_node, unsigned_type_node,
14779 unsigned_type_node, NULL_TREE);
14780 tree void_ftype_pcvoid_unsigned_unsigned
14781 = build_function_type_list (void_type_node, const_ptr_type_node,
14782 unsigned_type_node, unsigned_type_node,
14784 tree unsigned_ftype_void
14785 = build_function_type (unsigned_type_node, void_list_node);
14786 tree v2si_ftype_v4sf
14787 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
14788 /* Loads/stores. */
14789 tree void_ftype_v8qi_v8qi_pchar
14790 = build_function_type_list (void_type_node,
14791 V8QI_type_node, V8QI_type_node,
14792 pchar_type_node, NULL_TREE);
14793 tree v4sf_ftype_pcfloat
14794 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
14795 /* @@@ the type is bogus */
14796 tree v4sf_ftype_v4sf_pv2si
14797 = build_function_type_list (V4SF_type_node,
14798 V4SF_type_node, pv2si_type_node, NULL_TREE);
14799 tree void_ftype_pv2si_v4sf
14800 = build_function_type_list (void_type_node,
14801 pv2si_type_node, V4SF_type_node, NULL_TREE);
14802 tree void_ftype_pfloat_v4sf
14803 = build_function_type_list (void_type_node,
14804 pfloat_type_node, V4SF_type_node, NULL_TREE);
14805 tree void_ftype_pdi_di
14806 = build_function_type_list (void_type_node,
14807 pdi_type_node, long_long_unsigned_type_node,
14809 tree void_ftype_pv2di_v2di
14810 = build_function_type_list (void_type_node,
14811 pv2di_type_node, V2DI_type_node, NULL_TREE);
14812 /* Normal vector unops. */
14813 tree v4sf_ftype_v4sf
14814 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14816 /* Normal vector binops. */
14817 tree v4sf_ftype_v4sf_v4sf
14818 = build_function_type_list (V4SF_type_node,
14819 V4SF_type_node, V4SF_type_node, NULL_TREE);
14820 tree v8qi_ftype_v8qi_v8qi
14821 = build_function_type_list (V8QI_type_node,
14822 V8QI_type_node, V8QI_type_node, NULL_TREE);
14823 tree v4hi_ftype_v4hi_v4hi
14824 = build_function_type_list (V4HI_type_node,
14825 V4HI_type_node, V4HI_type_node, NULL_TREE);
14826 tree v2si_ftype_v2si_v2si
14827 = build_function_type_list (V2SI_type_node,
14828 V2SI_type_node, V2SI_type_node, NULL_TREE);
14829 tree di_ftype_di_di
14830 = build_function_type_list (long_long_unsigned_type_node,
14831 long_long_unsigned_type_node,
14832 long_long_unsigned_type_node, NULL_TREE);
14834 tree v2si_ftype_v2sf
14835 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
14836 tree v2sf_ftype_v2si
14837 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
14838 tree v2si_ftype_v2si
14839 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
14840 tree v2sf_ftype_v2sf
14841 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
14842 tree v2sf_ftype_v2sf_v2sf
14843 = build_function_type_list (V2SF_type_node,
14844 V2SF_type_node, V2SF_type_node, NULL_TREE);
14845 tree v2si_ftype_v2sf_v2sf
14846 = build_function_type_list (V2SI_type_node,
14847 V2SF_type_node, V2SF_type_node, NULL_TREE);
14848 tree pint_type_node = build_pointer_type (integer_type_node);
14849 tree pdouble_type_node = build_pointer_type (double_type_node);
14850 tree pcdouble_type_node = build_pointer_type (
14851 build_type_variant (double_type_node, 1, 0));
14852 tree int_ftype_v2df_v2df
14853 = build_function_type_list (integer_type_node,
14854 V2DF_type_node, V2DF_type_node, NULL_TREE);
14856 tree void_ftype_pcvoid
14857 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
14858 tree v4sf_ftype_v4si
14859 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
14860 tree v4si_ftype_v4sf
14861 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
14862 tree v2df_ftype_v4si
14863 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
14864 tree v4si_ftype_v2df
14865 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
14866 tree v2si_ftype_v2df
14867 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
14868 tree v4sf_ftype_v2df
14869 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
14870 tree v2df_ftype_v2si
14871 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
14872 tree v2df_ftype_v4sf
14873 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
14874 tree int_ftype_v2df
14875 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
14876 tree int64_ftype_v2df
14877 = build_function_type_list (long_long_integer_type_node,
14878 V2DF_type_node, NULL_TREE);
14879 tree v2df_ftype_v2df_int
14880 = build_function_type_list (V2DF_type_node,
14881 V2DF_type_node, integer_type_node, NULL_TREE);
14882 tree v2df_ftype_v2df_int64
14883 = build_function_type_list (V2DF_type_node,
14884 V2DF_type_node, long_long_integer_type_node,
14886 tree v4sf_ftype_v4sf_v2df
14887 = build_function_type_list (V4SF_type_node,
14888 V4SF_type_node, V2DF_type_node, NULL_TREE);
14889 tree v2df_ftype_v2df_v4sf
14890 = build_function_type_list (V2DF_type_node,
14891 V2DF_type_node, V4SF_type_node, NULL_TREE);
14892 tree v2df_ftype_v2df_v2df_int
14893 = build_function_type_list (V2DF_type_node,
14894 V2DF_type_node, V2DF_type_node,
14897 tree v2df_ftype_v2df_pcdouble
14898 = build_function_type_list (V2DF_type_node,
14899 V2DF_type_node, pcdouble_type_node, NULL_TREE);
14900 tree void_ftype_pdouble_v2df
14901 = build_function_type_list (void_type_node,
14902 pdouble_type_node, V2DF_type_node, NULL_TREE);
14903 tree void_ftype_pint_int
14904 = build_function_type_list (void_type_node,
14905 pint_type_node, integer_type_node, NULL_TREE);
14906 tree void_ftype_v16qi_v16qi_pchar
14907 = build_function_type_list (void_type_node,
14908 V16QI_type_node, V16QI_type_node,
14909 pchar_type_node, NULL_TREE);
14910 tree v2df_ftype_pcdouble
14911 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
14912 tree v2df_ftype_v2df_v2df
14913 = build_function_type_list (V2DF_type_node,
14914 V2DF_type_node, V2DF_type_node, NULL_TREE);
14915 tree v16qi_ftype_v16qi_v16qi
14916 = build_function_type_list (V16QI_type_node,
14917 V16QI_type_node, V16QI_type_node, NULL_TREE);
14918 tree v8hi_ftype_v8hi_v8hi
14919 = build_function_type_list (V8HI_type_node,
14920 V8HI_type_node, V8HI_type_node, NULL_TREE);
14921 tree v4si_ftype_v4si_v4si
14922 = build_function_type_list (V4SI_type_node,
14923 V4SI_type_node, V4SI_type_node, NULL_TREE);
14924 tree v2di_ftype_v2di_v2di
14925 = build_function_type_list (V2DI_type_node,
14926 V2DI_type_node, V2DI_type_node, NULL_TREE);
14927 tree v2di_ftype_v2df_v2df
14928 = build_function_type_list (V2DI_type_node,
14929 V2DF_type_node, V2DF_type_node, NULL_TREE);
14930 tree v2df_ftype_v2df
14931 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14932 tree v2di_ftype_v2di_int
14933 = build_function_type_list (V2DI_type_node,
14934 V2DI_type_node, integer_type_node, NULL_TREE);
14935 tree v4si_ftype_v4si_int
14936 = build_function_type_list (V4SI_type_node,
14937 V4SI_type_node, integer_type_node, NULL_TREE);
14938 tree v8hi_ftype_v8hi_int
14939 = build_function_type_list (V8HI_type_node,
14940 V8HI_type_node, integer_type_node, NULL_TREE);
14941 tree v8hi_ftype_v8hi_v2di
14942 = build_function_type_list (V8HI_type_node,
14943 V8HI_type_node, V2DI_type_node, NULL_TREE);
14944 tree v4si_ftype_v4si_v2di
14945 = build_function_type_list (V4SI_type_node,
14946 V4SI_type_node, V2DI_type_node, NULL_TREE);
14947 tree v4si_ftype_v8hi_v8hi
14948 = build_function_type_list (V4SI_type_node,
14949 V8HI_type_node, V8HI_type_node, NULL_TREE);
14950 tree di_ftype_v8qi_v8qi
14951 = build_function_type_list (long_long_unsigned_type_node,
14952 V8QI_type_node, V8QI_type_node, NULL_TREE);
14953 tree di_ftype_v2si_v2si
14954 = build_function_type_list (long_long_unsigned_type_node,
14955 V2SI_type_node, V2SI_type_node, NULL_TREE);
14956 tree v2di_ftype_v16qi_v16qi
14957 = build_function_type_list (V2DI_type_node,
14958 V16QI_type_node, V16QI_type_node, NULL_TREE);
14959 tree v2di_ftype_v4si_v4si
14960 = build_function_type_list (V2DI_type_node,
14961 V4SI_type_node, V4SI_type_node, NULL_TREE);
14962 tree int_ftype_v16qi
14963 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
14964 tree v16qi_ftype_pcchar
14965 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
14966 tree void_ftype_pchar_v16qi
14967 = build_function_type_list (void_type_node,
14968 pchar_type_node, V16QI_type_node, NULL_TREE);
14971 tree float128_type;
14974 /* The __float80 type. */
14975 if (TYPE_MODE (long_double_type_node) == XFmode)
14976 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
14980 /* The __float80 type. */
14981 float80_type = make_node (REAL_TYPE);
14982 TYPE_PRECISION (float80_type) = 80;
14983 layout_type (float80_type);
14984 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
14989 float128_type = make_node (REAL_TYPE);
14990 TYPE_PRECISION (float128_type) = 128;
14991 layout_type (float128_type);
14992 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
14995 /* Add all builtins that are more or less simple operations on two
14997 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14999 /* Use one of the operands; the target can have a different mode for
15000 mask-generating compares. */
15001 enum machine_mode mode;
15006 mode = insn_data[d->icode].operand[1].mode;
15011 type = v16qi_ftype_v16qi_v16qi;
15014 type = v8hi_ftype_v8hi_v8hi;
15017 type = v4si_ftype_v4si_v4si;
15020 type = v2di_ftype_v2di_v2di;
15023 type = v2df_ftype_v2df_v2df;
15026 type = v4sf_ftype_v4sf_v4sf;
15029 type = v8qi_ftype_v8qi_v8qi;
15032 type = v4hi_ftype_v4hi_v4hi;
15035 type = v2si_ftype_v2si_v2si;
15038 type = di_ftype_di_di;
15042 gcc_unreachable ();
15045 /* Override for comparisons. */
15046 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
15047 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
15048 type = v4si_ftype_v4sf_v4sf;
15050 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
15051 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15052 type = v2di_ftype_v2df_v2df;
15054 def_builtin (d->mask, d->name, type, d->code);
15057 /* Add the remaining MMX insns with somewhat more complicated types. */
15058 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
15059 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
15060 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
15061 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
15063 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
15064 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
15065 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
15067 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
15068 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
15070 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
15071 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
15073 /* comi/ucomi insns. */
15074 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
15075 if (d->mask == MASK_SSE2)
15076 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
15078 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
15080 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
15081 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
15082 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
15084 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
15085 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
15086 def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
15087 def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
15088 def_builtin (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
15089 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
15090 def_builtin (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
15091 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
15092 def_builtin (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
15093 def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
15094 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
15096 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
15098 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
15099 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
15101 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
15102 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
15103 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
15104 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
15106 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
15107 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
15108 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
15109 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
15111 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
15113 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
15115 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
15116 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
15117 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
15118 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
15119 def_builtin (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
15120 def_builtin (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
15122 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
15124 /* Original 3DNow! */
15125 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
15126 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
15127 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
15128 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
15129 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
15130 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
15131 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
15132 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
15133 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
15134 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
15135 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
15136 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
15137 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
15138 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
15139 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
15140 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
15141 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
15142 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
15143 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
15144 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
15146 /* 3DNow! extension as used in the Athlon CPU. */
15147 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
15148 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
15149 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
15150 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
15151 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
15152 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
15155 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
15157 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
15158 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
15160 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
15161 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
15163 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
15164 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
15165 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
15166 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
15167 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
15169 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
15170 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
15171 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
15172 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
15174 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
15175 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
15177 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
15179 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
15180 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
15182 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
15183 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
15184 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
15185 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
15186 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
15188 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
15190 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
15191 def_builtin (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
15192 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
15193 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
15195 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
15196 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
15197 def_builtin (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
15199 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
15200 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
15201 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
15202 def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
15204 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
15205 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
15206 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
15208 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
15209 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
15211 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
15212 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
15214 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
15215 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
15216 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
15218 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
15219 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
15220 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
15222 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
15223 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
15225 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
15226 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
15227 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
15228 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
15230 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
15231 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
15232 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
15233 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
15235 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
15236 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
15238 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
15240 /* Prescott New Instructions. */
15241 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
15242 void_ftype_pcvoid_unsigned_unsigned,
15243 IX86_BUILTIN_MONITOR);
15244 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
15245 void_ftype_unsigned_unsigned,
15246 IX86_BUILTIN_MWAIT);
15247 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
15249 IX86_BUILTIN_MOVSHDUP);
15250 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
15252 IX86_BUILTIN_MOVSLDUP);
15253 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
15254 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15256 /* Access to the vec_init patterns. */
15257 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15258 integer_type_node, NULL_TREE);
15259 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15260 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15262 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15263 short_integer_type_node,
15264 short_integer_type_node,
15265 short_integer_type_node, NULL_TREE);
15266 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
15267 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
15269 ftype = build_function_type_list (V8QI_type_node, char_type_node,
15270 char_type_node, char_type_node,
15271 char_type_node, char_type_node,
15272 char_type_node, char_type_node,
15273 char_type_node, NULL_TREE);
15274 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
15275 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
15277 /* Access to the vec_extract patterns. */
15278 ftype = build_function_type_list (double_type_node, V2DF_type_node,
15279 integer_type_node, NULL_TREE);
15280 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
15281 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
15283 ftype = build_function_type_list (long_long_integer_type_node,
15284 V2DI_type_node, integer_type_node,
15286 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
15287 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
15289 ftype = build_function_type_list (float_type_node, V4SF_type_node,
15290 integer_type_node, NULL_TREE);
15291 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
15292 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
15294 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
15295 integer_type_node, NULL_TREE);
15296 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
15297 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
15299 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
15300 integer_type_node, NULL_TREE);
15301 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
15302 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
15304 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
15305 integer_type_node, NULL_TREE);
15306 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
15307 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
15309 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
15310 integer_type_node, NULL_TREE);
15311 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
15312 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
15314 /* Access to the vec_set patterns. */
15315 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
15317 integer_type_node, NULL_TREE);
15318 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
15319 ftype, IX86_BUILTIN_VEC_SET_V8HI);
15321 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
15323 integer_type_node, NULL_TREE);
15324 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
15325 ftype, IX86_BUILTIN_VEC_SET_V4HI);
15329 /* Set up all the SSE ABI builtins that we may use to override
15330 the normal builtins. */
15332 ix86_init_sse_abi_builtins (void)
15334 tree dbl, flt, dbl2, flt2;
15336 /* Bail out in case the template definitions are not available. */
15337 if (! built_in_decls [BUILT_IN_SIN]
15338 || ! built_in_decls [BUILT_IN_SINF]
15339 || ! built_in_decls [BUILT_IN_ATAN2]
15340 || ! built_in_decls [BUILT_IN_ATAN2F])
15343 /* Build the function types as variants of the existing ones. */
15344 dbl = build_variant_type_copy (TREE_TYPE (built_in_decls [BUILT_IN_SIN]));
15345 TYPE_ATTRIBUTES (dbl)
15346 = tree_cons (get_identifier ("sseregparm"),
15347 NULL_TREE, TYPE_ATTRIBUTES (dbl));
15348 flt = build_variant_type_copy (TREE_TYPE (built_in_decls [BUILT_IN_SINF]));
15349 TYPE_ATTRIBUTES (flt)
15350 = tree_cons (get_identifier ("sseregparm"),
15351 NULL_TREE, TYPE_ATTRIBUTES (flt));
15352 dbl2 = build_variant_type_copy (TREE_TYPE (built_in_decls [BUILT_IN_ATAN2]));
15353 TYPE_ATTRIBUTES (dbl2)
15354 = tree_cons (get_identifier ("sseregparm"),
15355 NULL_TREE, TYPE_ATTRIBUTES (dbl2));
15356 flt2 = build_variant_type_copy (TREE_TYPE (built_in_decls [BUILT_IN_ATAN2F]));
15357 TYPE_ATTRIBUTES (flt2)
15358 = tree_cons (get_identifier ("sseregparm"),
15359 NULL_TREE, TYPE_ATTRIBUTES (flt2));
15361 #define def_builtin(capname, name, type) \
15362 ix86_builtin_function_variants [BUILT_IN_ ## capname] \
15363 = lang_hooks.builtin_function ("__builtin_sse2_" # name, type, \
15364 IX86_BUILTIN_SSE2_ ## capname, \
15366 "__libm_sse2_" # name, NULL_TREE)
15368 def_builtin (ACOS, acos, dbl);
15369 def_builtin (ACOSF, acosf, flt);
15370 def_builtin (ASIN, asin, dbl);
15371 def_builtin (ASINF, asinf, flt);
15372 def_builtin (ATAN, atan, dbl);
15373 def_builtin (ATANF, atanf, flt);
15374 def_builtin (ATAN2, atan2, dbl2);
15375 def_builtin (ATAN2F, atan2f, flt2);
15376 def_builtin (COS, cos, dbl);
15377 def_builtin (COSF, cosf, flt);
15378 def_builtin (EXP, exp, dbl);
15379 def_builtin (EXPF, expf, flt);
15380 def_builtin (LOG10, log10, dbl);
15381 def_builtin (LOG10F, log10f, flt);
15382 def_builtin (LOG, log, dbl);
15383 def_builtin (LOGF, logf, flt);
15384 def_builtin (SIN, sin, dbl);
15385 def_builtin (SINF, sinf, flt);
15386 def_builtin (TAN, tan, dbl);
15387 def_builtin (TANF, tanf, flt);
15392 /* Errors in the source file can cause expand_expr to return const0_rtx
15393 where we expect a vector. To avoid crashing, use one of the vector
15394 clear instructions. */
15396 safe_vector_operand (rtx x, enum machine_mode mode)
15398 if (x == const0_rtx)
15399 x = CONST0_RTX (mode);
15403 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
15406 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
15409 tree arg0 = TREE_VALUE (arglist);
15410 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15411 rtx op0 = expand_normal (arg0);
15412 rtx op1 = expand_normal (arg1);
15413 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15414 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15415 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
15417 if (VECTOR_MODE_P (mode0))
15418 op0 = safe_vector_operand (op0, mode0);
15419 if (VECTOR_MODE_P (mode1))
15420 op1 = safe_vector_operand (op1, mode1);
15422 if (optimize || !target
15423 || GET_MODE (target) != tmode
15424 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15425 target = gen_reg_rtx (tmode);
15427 if (GET_MODE (op1) == SImode && mode1 == TImode)
15429 rtx x = gen_reg_rtx (V4SImode);
15430 emit_insn (gen_sse2_loadd (x, op1));
15431 op1 = gen_lowpart (TImode, x);
15434 /* The insn must want input operands in the same modes as the
15436 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
15437 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
15439 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15440 op0 = copy_to_mode_reg (mode0, op0);
15441 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
15442 op1 = copy_to_mode_reg (mode1, op1);
15444 /* ??? Using ix86_fixup_binary_operands is problematic when
15445 we've got mismatched modes. Fake it. */
15451 if (tmode == mode0 && tmode == mode1)
15453 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
15457 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
15459 op0 = force_reg (mode0, op0);
15460 op1 = force_reg (mode1, op1);
15461 target = gen_reg_rtx (tmode);
15464 pat = GEN_FCN (icode) (target, op0, op1);
15471 /* Subroutine of ix86_expand_builtin to take care of stores. */
15474 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
15477 tree arg0 = TREE_VALUE (arglist);
15478 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15479 rtx op0 = expand_normal (arg0);
15480 rtx op1 = expand_normal (arg1);
15481 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
15482 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
15484 if (VECTOR_MODE_P (mode1))
15485 op1 = safe_vector_operand (op1, mode1);
15487 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15488 op1 = copy_to_mode_reg (mode1, op1);
15490 pat = GEN_FCN (icode) (op0, op1);
15496 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
15499 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
15500 rtx target, int do_load)
15503 tree arg0 = TREE_VALUE (arglist);
15504 rtx op0 = expand_normal (arg0);
15505 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15506 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15508 if (optimize || !target
15509 || GET_MODE (target) != tmode
15510 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15511 target = gen_reg_rtx (tmode);
15513 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15516 if (VECTOR_MODE_P (mode0))
15517 op0 = safe_vector_operand (op0, mode0);
15519 if ((optimize && !register_operand (op0, mode0))
15520 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15521 op0 = copy_to_mode_reg (mode0, op0);
15524 pat = GEN_FCN (icode) (target, op0);
15531 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
15532 sqrtss, rsqrtss, rcpss. */
15535 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
15538 tree arg0 = TREE_VALUE (arglist);
15539 rtx op1, op0 = expand_normal (arg0);
15540 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15541 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15543 if (optimize || !target
15544 || GET_MODE (target) != tmode
15545 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15546 target = gen_reg_rtx (tmode);
15548 if (VECTOR_MODE_P (mode0))
15549 op0 = safe_vector_operand (op0, mode0);
15551 if ((optimize && !register_operand (op0, mode0))
15552 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15553 op0 = copy_to_mode_reg (mode0, op0);
15556 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
15557 op1 = copy_to_mode_reg (mode0, op1);
15559 pat = GEN_FCN (icode) (target, op0, op1);
15566 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
15569 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
15573 tree arg0 = TREE_VALUE (arglist);
15574 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15575 rtx op0 = expand_normal (arg0);
15576 rtx op1 = expand_normal (arg1);
15578 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
15579 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
15580 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
15581 enum rtx_code comparison = d->comparison;
15583 if (VECTOR_MODE_P (mode0))
15584 op0 = safe_vector_operand (op0, mode0);
15585 if (VECTOR_MODE_P (mode1))
15586 op1 = safe_vector_operand (op1, mode1);
15588 /* Swap operands if we have a comparison that isn't available in
15590 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15592 rtx tmp = gen_reg_rtx (mode1);
15593 emit_move_insn (tmp, op1);
15598 if (optimize || !target
15599 || GET_MODE (target) != tmode
15600 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
15601 target = gen_reg_rtx (tmode);
15603 if ((optimize && !register_operand (op0, mode0))
15604 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
15605 op0 = copy_to_mode_reg (mode0, op0);
15606 if ((optimize && !register_operand (op1, mode1))
15607 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
15608 op1 = copy_to_mode_reg (mode1, op1);
15610 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15611 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
15618 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
15621 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
15625 tree arg0 = TREE_VALUE (arglist);
15626 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15627 rtx op0 = expand_normal (arg0);
15628 rtx op1 = expand_normal (arg1);
15630 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
15631 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
15632 enum rtx_code comparison = d->comparison;
15634 if (VECTOR_MODE_P (mode0))
15635 op0 = safe_vector_operand (op0, mode0);
15636 if (VECTOR_MODE_P (mode1))
15637 op1 = safe_vector_operand (op1, mode1);
15639 /* Swap operands if we have a comparison that isn't available in
15641 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15648 target = gen_reg_rtx (SImode);
15649 emit_move_insn (target, const0_rtx);
15650 target = gen_rtx_SUBREG (QImode, target, 0);
15652 if ((optimize && !register_operand (op0, mode0))
15653 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15654 op0 = copy_to_mode_reg (mode0, op0);
15655 if ((optimize && !register_operand (op1, mode1))
15656 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15657 op1 = copy_to_mode_reg (mode1, op1);
15659 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15660 pat = GEN_FCN (d->icode) (op0, op1);
15664 emit_insn (gen_rtx_SET (VOIDmode,
15665 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
15666 gen_rtx_fmt_ee (comparison, QImode,
15670 return SUBREG_REG (target);
15673 /* Return the integer constant in ARG. Constrain it to be in the range
15674 of the subparts of VEC_TYPE; issue an error if not. */
15677 get_element_number (tree vec_type, tree arg)
15679 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15681 if (!host_integerp (arg, 1)
15682 || (elt = tree_low_cst (arg, 1), elt > max))
15684 error ("selector must be an integer constant in the range 0..%wi", max);
15691 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15692 ix86_expand_vector_init. We DO have language-level syntax for this, in
15693 the form of (type){ init-list }. Except that since we can't place emms
15694 instructions from inside the compiler, we can't allow the use of MMX
15695 registers unless the user explicitly asks for it. So we do *not* define
15696 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
15697 we have builtins invoked by mmintrin.h that gives us license to emit
15698 these sorts of instructions. */
15701 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
15703 enum machine_mode tmode = TYPE_MODE (type);
15704 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
15705 int i, n_elt = GET_MODE_NUNITS (tmode);
15706 rtvec v = rtvec_alloc (n_elt);
15708 gcc_assert (VECTOR_MODE_P (tmode));
15710 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
15712 rtx x = expand_normal (TREE_VALUE (arglist));
15713 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15716 gcc_assert (arglist == NULL);
15718 if (!target || !register_operand (target, tmode))
15719 target = gen_reg_rtx (tmode);
15721 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
15725 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15726 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
15727 had a language-level syntax for referencing vector elements. */
15730 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
15732 enum machine_mode tmode, mode0;
15737 arg0 = TREE_VALUE (arglist);
15738 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15740 op0 = expand_normal (arg0);
15741 elt = get_element_number (TREE_TYPE (arg0), arg1);
15743 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15744 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15745 gcc_assert (VECTOR_MODE_P (mode0));
15747 op0 = force_reg (mode0, op0);
15749 if (optimize || !target || !register_operand (target, tmode))
15750 target = gen_reg_rtx (tmode);
15752 ix86_expand_vector_extract (true, target, op0, elt);
15757 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15758 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
15759 a language-level syntax for referencing vector elements. */
15762 ix86_expand_vec_set_builtin (tree arglist)
15764 enum machine_mode tmode, mode1;
15765 tree arg0, arg1, arg2;
15769 arg0 = TREE_VALUE (arglist);
15770 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15771 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15773 tmode = TYPE_MODE (TREE_TYPE (arg0));
15774 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15775 gcc_assert (VECTOR_MODE_P (tmode));
15777 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
15778 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
15779 elt = get_element_number (TREE_TYPE (arg0), arg2);
15781 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15782 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15784 op0 = force_reg (tmode, op0);
15785 op1 = force_reg (mode1, op1);
15787 ix86_expand_vector_set (true, op0, op1, elt);
15792 /* Expand an expression EXP that calls a built-in function,
15793 with result going to TARGET if that's convenient
15794 (and in mode MODE if that's convenient).
15795 SUBTARGET may be used as the target for computing one of EXP's operands.
15796 IGNORE is nonzero if the value is to be ignored. */
15799 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15800 enum machine_mode mode ATTRIBUTE_UNUSED,
15801 int ignore ATTRIBUTE_UNUSED)
15803 const struct builtin_description *d;
15805 enum insn_code icode;
15806 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
15807 tree arglist = TREE_OPERAND (exp, 1);
15808 tree arg0, arg1, arg2;
15809 rtx op0, op1, op2, pat;
15810 enum machine_mode tmode, mode0, mode1, mode2;
15811 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15815 case IX86_BUILTIN_EMMS:
15816 emit_insn (gen_mmx_emms ());
15819 case IX86_BUILTIN_SFENCE:
15820 emit_insn (gen_sse_sfence ());
15823 case IX86_BUILTIN_MASKMOVQ:
15824 case IX86_BUILTIN_MASKMOVDQU:
15825 icode = (fcode == IX86_BUILTIN_MASKMOVQ
15826 ? CODE_FOR_mmx_maskmovq
15827 : CODE_FOR_sse2_maskmovdqu);
15828 /* Note the arg order is different from the operand order. */
15829 arg1 = TREE_VALUE (arglist);
15830 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
15831 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15832 op0 = expand_normal (arg0);
15833 op1 = expand_normal (arg1);
15834 op2 = expand_normal (arg2);
15835 mode0 = insn_data[icode].operand[0].mode;
15836 mode1 = insn_data[icode].operand[1].mode;
15837 mode2 = insn_data[icode].operand[2].mode;
15839 op0 = force_reg (Pmode, op0);
15840 op0 = gen_rtx_MEM (mode1, op0);
15842 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15843 op0 = copy_to_mode_reg (mode0, op0);
15844 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15845 op1 = copy_to_mode_reg (mode1, op1);
15846 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
15847 op2 = copy_to_mode_reg (mode2, op2);
15848 pat = GEN_FCN (icode) (op0, op1, op2);
15854 case IX86_BUILTIN_SQRTSS:
15855 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
15856 case IX86_BUILTIN_RSQRTSS:
15857 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
15858 case IX86_BUILTIN_RCPSS:
15859 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
15861 case IX86_BUILTIN_LOADUPS:
15862 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
15864 case IX86_BUILTIN_STOREUPS:
15865 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
15867 case IX86_BUILTIN_LOADHPS:
15868 case IX86_BUILTIN_LOADLPS:
15869 case IX86_BUILTIN_LOADHPD:
15870 case IX86_BUILTIN_LOADLPD:
15871 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
15872 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
15873 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
15874 : CODE_FOR_sse2_loadlpd);
15875 arg0 = TREE_VALUE (arglist);
15876 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15877 op0 = expand_normal (arg0);
15878 op1 = expand_normal (arg1);
15879 tmode = insn_data[icode].operand[0].mode;
15880 mode0 = insn_data[icode].operand[1].mode;
15881 mode1 = insn_data[icode].operand[2].mode;
15883 op0 = force_reg (mode0, op0);
15884 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
15885 if (optimize || target == 0
15886 || GET_MODE (target) != tmode
15887 || !register_operand (target, tmode))
15888 target = gen_reg_rtx (tmode);
15889 pat = GEN_FCN (icode) (target, op0, op1);
15895 case IX86_BUILTIN_STOREHPS:
15896 case IX86_BUILTIN_STORELPS:
15897 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
15898 : CODE_FOR_sse_storelps);
15899 arg0 = TREE_VALUE (arglist);
15900 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15901 op0 = expand_normal (arg0);
15902 op1 = expand_normal (arg1);
15903 mode0 = insn_data[icode].operand[0].mode;
15904 mode1 = insn_data[icode].operand[1].mode;
15906 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15907 op1 = force_reg (mode1, op1);
15909 pat = GEN_FCN (icode) (op0, op1);
15915 case IX86_BUILTIN_MOVNTPS:
15916 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
15917 case IX86_BUILTIN_MOVNTQ:
15918 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
15920 case IX86_BUILTIN_LDMXCSR:
15921 op0 = expand_normal (TREE_VALUE (arglist));
15922 target = assign_386_stack_local (SImode, SLOT_TEMP);
15923 emit_move_insn (target, op0);
15924 emit_insn (gen_sse_ldmxcsr (target));
15927 case IX86_BUILTIN_STMXCSR:
15928 target = assign_386_stack_local (SImode, SLOT_TEMP);
15929 emit_insn (gen_sse_stmxcsr (target));
15930 return copy_to_mode_reg (SImode, target);
15932 case IX86_BUILTIN_SHUFPS:
15933 case IX86_BUILTIN_SHUFPD:
15934 icode = (fcode == IX86_BUILTIN_SHUFPS
15935 ? CODE_FOR_sse_shufps
15936 : CODE_FOR_sse2_shufpd);
15937 arg0 = TREE_VALUE (arglist);
15938 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15939 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15940 op0 = expand_normal (arg0);
15941 op1 = expand_normal (arg1);
15942 op2 = expand_normal (arg2);
15943 tmode = insn_data[icode].operand[0].mode;
15944 mode0 = insn_data[icode].operand[1].mode;
15945 mode1 = insn_data[icode].operand[2].mode;
15946 mode2 = insn_data[icode].operand[3].mode;
15948 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15949 op0 = copy_to_mode_reg (mode0, op0);
15950 if ((optimize && !register_operand (op1, mode1))
15951 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
15952 op1 = copy_to_mode_reg (mode1, op1);
15953 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15955 /* @@@ better error message */
15956 error ("mask must be an immediate");
15957 return gen_reg_rtx (tmode);
15959 if (optimize || target == 0
15960 || GET_MODE (target) != tmode
15961 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15962 target = gen_reg_rtx (tmode);
15963 pat = GEN_FCN (icode) (target, op0, op1, op2);
15969 case IX86_BUILTIN_PSHUFW:
15970 case IX86_BUILTIN_PSHUFD:
15971 case IX86_BUILTIN_PSHUFHW:
15972 case IX86_BUILTIN_PSHUFLW:
15973 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
15974 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
15975 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
15976 : CODE_FOR_mmx_pshufw);
15977 arg0 = TREE_VALUE (arglist);
15978 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15979 op0 = expand_normal (arg0);
15980 op1 = expand_normal (arg1);
15981 tmode = insn_data[icode].operand[0].mode;
15982 mode1 = insn_data[icode].operand[1].mode;
15983 mode2 = insn_data[icode].operand[2].mode;
15985 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15986 op0 = copy_to_mode_reg (mode1, op0);
15987 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15989 /* @@@ better error message */
15990 error ("mask must be an immediate");
15994 || GET_MODE (target) != tmode
15995 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15996 target = gen_reg_rtx (tmode);
15997 pat = GEN_FCN (icode) (target, op0, op1);
16003 case IX86_BUILTIN_PSLLDQI128:
16004 case IX86_BUILTIN_PSRLDQI128:
16005 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
16006 : CODE_FOR_sse2_lshrti3);
16007 arg0 = TREE_VALUE (arglist);
16008 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16009 op0 = expand_normal (arg0);
16010 op1 = expand_normal (arg1);
16011 tmode = insn_data[icode].operand[0].mode;
16012 mode1 = insn_data[icode].operand[1].mode;
16013 mode2 = insn_data[icode].operand[2].mode;
16015 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
16017 op0 = copy_to_reg (op0);
16018 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
16020 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
16022 error ("shift must be an immediate");
16025 target = gen_reg_rtx (V2DImode);
16026 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
16032 case IX86_BUILTIN_FEMMS:
16033 emit_insn (gen_mmx_femms ());
16036 case IX86_BUILTIN_PAVGUSB:
16037 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
16039 case IX86_BUILTIN_PF2ID:
16040 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
16042 case IX86_BUILTIN_PFACC:
16043 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
16045 case IX86_BUILTIN_PFADD:
16046 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
16048 case IX86_BUILTIN_PFCMPEQ:
16049 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
16051 case IX86_BUILTIN_PFCMPGE:
16052 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
16054 case IX86_BUILTIN_PFCMPGT:
16055 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
16057 case IX86_BUILTIN_PFMAX:
16058 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
16060 case IX86_BUILTIN_PFMIN:
16061 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
16063 case IX86_BUILTIN_PFMUL:
16064 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
16066 case IX86_BUILTIN_PFRCP:
16067 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
16069 case IX86_BUILTIN_PFRCPIT1:
16070 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
16072 case IX86_BUILTIN_PFRCPIT2:
16073 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
16075 case IX86_BUILTIN_PFRSQIT1:
16076 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
16078 case IX86_BUILTIN_PFRSQRT:
16079 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
16081 case IX86_BUILTIN_PFSUB:
16082 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
16084 case IX86_BUILTIN_PFSUBR:
16085 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
16087 case IX86_BUILTIN_PI2FD:
16088 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
16090 case IX86_BUILTIN_PMULHRW:
16091 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
16093 case IX86_BUILTIN_PF2IW:
16094 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
16096 case IX86_BUILTIN_PFNACC:
16097 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
16099 case IX86_BUILTIN_PFPNACC:
16100 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
16102 case IX86_BUILTIN_PI2FW:
16103 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
16105 case IX86_BUILTIN_PSWAPDSI:
16106 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
16108 case IX86_BUILTIN_PSWAPDSF:
16109 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
16111 case IX86_BUILTIN_SQRTSD:
16112 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
16113 case IX86_BUILTIN_LOADUPD:
16114 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
16115 case IX86_BUILTIN_STOREUPD:
16116 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
16118 case IX86_BUILTIN_MFENCE:
16119 emit_insn (gen_sse2_mfence ());
16121 case IX86_BUILTIN_LFENCE:
16122 emit_insn (gen_sse2_lfence ());
16125 case IX86_BUILTIN_CLFLUSH:
16126 arg0 = TREE_VALUE (arglist);
16127 op0 = expand_normal (arg0);
16128 icode = CODE_FOR_sse2_clflush;
16129 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
16130 op0 = copy_to_mode_reg (Pmode, op0);
16132 emit_insn (gen_sse2_clflush (op0));
16135 case IX86_BUILTIN_MOVNTPD:
16136 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
16137 case IX86_BUILTIN_MOVNTDQ:
16138 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
16139 case IX86_BUILTIN_MOVNTI:
16140 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
16142 case IX86_BUILTIN_LOADDQU:
16143 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
16144 case IX86_BUILTIN_STOREDQU:
16145 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
16147 case IX86_BUILTIN_MONITOR:
16148 arg0 = TREE_VALUE (arglist);
16149 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16150 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
16151 op0 = expand_normal (arg0);
16152 op1 = expand_normal (arg1);
16153 op2 = expand_normal (arg2);
16155 op0 = copy_to_mode_reg (SImode, op0);
16157 op1 = copy_to_mode_reg (SImode, op1);
16159 op2 = copy_to_mode_reg (SImode, op2);
16160 emit_insn (gen_sse3_monitor (op0, op1, op2));
16163 case IX86_BUILTIN_MWAIT:
16164 arg0 = TREE_VALUE (arglist);
16165 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16166 op0 = expand_normal (arg0);
16167 op1 = expand_normal (arg1);
16169 op0 = copy_to_mode_reg (SImode, op0);
16171 op1 = copy_to_mode_reg (SImode, op1);
16172 emit_insn (gen_sse3_mwait (op0, op1));
16175 case IX86_BUILTIN_LDDQU:
16176 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
16179 case IX86_BUILTIN_VEC_INIT_V2SI:
16180 case IX86_BUILTIN_VEC_INIT_V4HI:
16181 case IX86_BUILTIN_VEC_INIT_V8QI:
16182 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16184 case IX86_BUILTIN_VEC_EXT_V2DF:
16185 case IX86_BUILTIN_VEC_EXT_V2DI:
16186 case IX86_BUILTIN_VEC_EXT_V4SF:
16187 case IX86_BUILTIN_VEC_EXT_V4SI:
16188 case IX86_BUILTIN_VEC_EXT_V8HI:
16189 case IX86_BUILTIN_VEC_EXT_V2SI:
16190 case IX86_BUILTIN_VEC_EXT_V4HI:
16191 return ix86_expand_vec_ext_builtin (arglist, target);
16193 case IX86_BUILTIN_VEC_SET_V8HI:
16194 case IX86_BUILTIN_VEC_SET_V4HI:
16195 return ix86_expand_vec_set_builtin (arglist);
16201 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16202 if (d->code == fcode)
16204 /* Compares are treated specially. */
16205 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
16206 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
16207 || d->icode == CODE_FOR_sse2_maskcmpv2df3
16208 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
16209 return ix86_expand_sse_compare (d, arglist, target);
16211 return ix86_expand_binop_builtin (d->icode, arglist, target);
16214 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16215 if (d->code == fcode)
16216 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
16218 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
16219 if (d->code == fcode)
16220 return ix86_expand_sse_comi (d, arglist, target);
16222 gcc_unreachable ();
16225 /* Expand an expression EXP that calls a built-in library function,
16226 with result going to TARGET if that's convenient
16227 (and in mode MODE if that's convenient).
16228 SUBTARGET may be used as the target for computing one of EXP's operands.
16229 IGNORE is nonzero if the value is to be ignored. */
16232 ix86_expand_library_builtin (tree exp, rtx target,
16233 rtx subtarget ATTRIBUTE_UNUSED,
16234 enum machine_mode mode ATTRIBUTE_UNUSED,
16237 enum built_in_function fncode;
16238 tree fndecl, newfn, call;
16240 /* Try expanding builtin math functions to the SSE2 ABI variants. */
16241 if (!TARGET_SSELIBM)
16244 fncode = builtin_mathfn_code (exp);
16245 if (!ix86_builtin_function_variants [(int)fncode])
16248 fndecl = get_callee_fndecl (exp);
16249 if (DECL_RTL_SET_P (fndecl))
16252 /* Build the redirected call and expand it. */
16253 newfn = ix86_builtin_function_variants [(int)fncode];
16254 call = build_function_call_expr (newfn, TREE_OPERAND (exp, 1));
16255 return expand_call (call, target, ignore);
16258 /* Store OPERAND to the memory after reload is completed. This means
16259 that we can't easily use assign_stack_local. */
16261 ix86_force_to_memory (enum machine_mode mode, rtx operand)
16265 gcc_assert (reload_completed);
16266 if (TARGET_RED_ZONE)
16268 result = gen_rtx_MEM (mode,
16269 gen_rtx_PLUS (Pmode,
16271 GEN_INT (-RED_ZONE_SIZE)));
16272 emit_move_insn (result, operand);
16274 else if (!TARGET_RED_ZONE && TARGET_64BIT)
16280 operand = gen_lowpart (DImode, operand);
16284 gen_rtx_SET (VOIDmode,
16285 gen_rtx_MEM (DImode,
16286 gen_rtx_PRE_DEC (DImode,
16287 stack_pointer_rtx)),
16291 gcc_unreachable ();
16293 result = gen_rtx_MEM (mode, stack_pointer_rtx);
16302 split_di (&operand, 1, operands, operands + 1);
16304 gen_rtx_SET (VOIDmode,
16305 gen_rtx_MEM (SImode,
16306 gen_rtx_PRE_DEC (Pmode,
16307 stack_pointer_rtx)),
16310 gen_rtx_SET (VOIDmode,
16311 gen_rtx_MEM (SImode,
16312 gen_rtx_PRE_DEC (Pmode,
16313 stack_pointer_rtx)),
16318 /* Store HImodes as SImodes. */
16319 operand = gen_lowpart (SImode, operand);
16323 gen_rtx_SET (VOIDmode,
16324 gen_rtx_MEM (GET_MODE (operand),
16325 gen_rtx_PRE_DEC (SImode,
16326 stack_pointer_rtx)),
16330 gcc_unreachable ();
16332 result = gen_rtx_MEM (mode, stack_pointer_rtx);
16337 /* Free operand from the memory. */
16339 ix86_free_from_memory (enum machine_mode mode)
16341 if (!TARGET_RED_ZONE)
16345 if (mode == DImode || TARGET_64BIT)
16349 /* Use LEA to deallocate stack space. In peephole2 it will be converted
16350 to pop or add instruction if registers are available. */
16351 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
16352 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
16357 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
16358 QImode must go into class Q_REGS.
16359 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
16360 movdf to do mem-to-mem moves through integer regs. */
16362 ix86_preferred_reload_class (rtx x, enum reg_class class)
16364 /* We're only allowed to return a subclass of CLASS. Many of the
16365 following checks fail for NO_REGS, so eliminate that early. */
16366 if (class == NO_REGS)
16369 /* All classes can load zeros. */
16370 if (x == CONST0_RTX (GET_MODE (x)))
16373 /* Floating-point constants need more complex checks. */
16374 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
16376 /* General regs can load everything. */
16377 if (reg_class_subset_p (class, GENERAL_REGS))
16380 /* Floats can load 0 and 1 plus some others. Note that we eliminated
16381 zero above. We only want to wind up preferring 80387 registers if
16382 we plan on doing computation with them. */
16384 && (TARGET_MIX_SSE_I387
16385 || !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
16386 && standard_80387_constant_p (x))
16388 /* Limit class to non-sse. */
16389 if (class == FLOAT_SSE_REGS)
16391 if (class == FP_TOP_SSE_REGS)
16393 if (class == FP_SECOND_SSE_REGS)
16394 return FP_SECOND_REG;
16395 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
16401 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
16403 if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
16406 /* Generally when we see PLUS here, it's the function invariant
16407 (plus soft-fp const_int). Which can only be computed into general
16409 if (GET_CODE (x) == PLUS)
16410 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
16412 /* QImode constants are easy to load, but non-constant QImode data
16413 must go into Q_REGS. */
16414 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
16416 if (reg_class_subset_p (class, Q_REGS))
16418 if (reg_class_subset_p (Q_REGS, class))
16426 /* If we are copying between general and FP registers, we need a memory
16427 location. The same is true for SSE and MMX registers.
16429 The macro can't work reliably when one of the CLASSES is class containing
16430 registers from multiple units (SSE, MMX, integer). We avoid this by never
16431 combining those units in single alternative in the machine description.
16432 Ensure that this constraint holds to avoid unexpected surprises.
16434 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
16435 enforce these sanity checks. */
16438 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
16439 enum machine_mode mode, int strict)
16441 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
16442 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
16443 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
16444 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
16445 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
16446 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
16448 gcc_assert (!strict);
16452 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
16455 /* ??? This is a lie. We do have moves between mmx/general, and for
16456 mmx/sse2. But by saying we need secondary memory we discourage the
16457 register allocator from using the mmx registers unless needed. */
16458 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
16461 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
16463 /* SSE1 doesn't have any direct moves from other classes. */
16467 /* If the target says that inter-unit moves are more expensive
16468 than moving through memory, then don't generate them. */
16469 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
16472 /* Between SSE and general, we have moves no larger than word size. */
16473 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
16476 /* ??? For the cost of one register reformat penalty, we could use
16477 the same instructions to move SFmode and DFmode data, but the
16478 relevant move patterns don't support those alternatives. */
16479 if (mode == SFmode || mode == DFmode)
16486 /* Return true if the registers in CLASS cannot represent the change from
16487 modes FROM to TO. */
16490 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
16491 enum reg_class class)
16496 /* x87 registers can't do subreg at all, as all values are reformatted
16497 to extended precision. */
16498 if (MAYBE_FLOAT_CLASS_P (class))
16501 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
16503 /* Vector registers do not support QI or HImode loads. If we don't
16504 disallow a change to these modes, reload will assume it's ok to
16505 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
16506 the vec_dupv4hi pattern. */
16507 if (GET_MODE_SIZE (from) < 4)
16510 /* Vector registers do not support subreg with nonzero offsets, which
16511 are otherwise valid for integer registers. Since we can't see
16512 whether we have a nonzero offset from here, prohibit all
16513 nonparadoxical subregs changing size. */
16514 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
16521 /* Return the cost of moving data from a register in class CLASS1 to
16522 one in class CLASS2.
16524 It is not required that the cost always equal 2 when FROM is the same as TO;
16525 on some machines it is expensive to move between registers if they are not
16526 general registers. */
16529 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
16530 enum reg_class class2)
16532 /* In case we require secondary memory, compute cost of the store followed
16533 by load. In order to avoid bad register allocation choices, we need
16534 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
16536 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
16540 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
16541 MEMORY_MOVE_COST (mode, class1, 1));
16542 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
16543 MEMORY_MOVE_COST (mode, class2, 1));
16545 /* In case of copying from general_purpose_register we may emit multiple
16546 stores followed by single load causing memory size mismatch stall.
16547 Count this as arbitrarily high cost of 20. */
16548 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
16551 /* In the case of FP/MMX moves, the registers actually overlap, and we
16552 have to switch modes in order to treat them differently. */
16553 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
16554 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
16560 /* Moves between SSE/MMX and integer unit are expensive. */
16561 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
16562 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
16563 return ix86_cost->mmxsse_to_integer;
16564 if (MAYBE_FLOAT_CLASS_P (class1))
16565 return ix86_cost->fp_move;
16566 if (MAYBE_SSE_CLASS_P (class1))
16567 return ix86_cost->sse_move;
16568 if (MAYBE_MMX_CLASS_P (class1))
16569 return ix86_cost->mmx_move;
16573 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
16576 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
16578 /* Flags and only flags can only hold CCmode values. */
16579 if (CC_REGNO_P (regno))
16580 return GET_MODE_CLASS (mode) == MODE_CC;
16581 if (GET_MODE_CLASS (mode) == MODE_CC
16582 || GET_MODE_CLASS (mode) == MODE_RANDOM
16583 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
16585 if (FP_REGNO_P (regno))
16586 return VALID_FP_MODE_P (mode);
16587 if (SSE_REGNO_P (regno))
16589 /* We implement the move patterns for all vector modes into and
16590 out of SSE registers, even when no operation instructions
16592 return (VALID_SSE_REG_MODE (mode)
16593 || VALID_SSE2_REG_MODE (mode)
16594 || VALID_MMX_REG_MODE (mode)
16595 || VALID_MMX_REG_MODE_3DNOW (mode));
16597 if (MMX_REGNO_P (regno))
16599 /* We implement the move patterns for 3DNOW modes even in MMX mode,
16600 so if the register is available at all, then we can move data of
16601 the given mode into or out of it. */
16602 return (VALID_MMX_REG_MODE (mode)
16603 || VALID_MMX_REG_MODE_3DNOW (mode));
16606 if (mode == QImode)
16608 /* Take care for QImode values - they can be in non-QI regs,
16609 but then they do cause partial register stalls. */
16610 if (regno < 4 || TARGET_64BIT)
16612 if (!TARGET_PARTIAL_REG_STALL)
16614 return reload_in_progress || reload_completed;
16616 /* We handle both integer and floats in the general purpose registers. */
16617 else if (VALID_INT_MODE_P (mode))
16619 else if (VALID_FP_MODE_P (mode))
16621 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
16622 on to use that value in smaller contexts, this can easily force a
16623 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
16624 supporting DImode, allow it. */
16625 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
16631 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
16632 tieable integer mode. */
16635 ix86_tieable_integer_mode_p (enum machine_mode mode)
16644 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
16647 return TARGET_64BIT;
16654 /* Return true if MODE1 is accessible in a register that can hold MODE2
16655 without copying. That is, all register classes that can hold MODE2
16656 can also hold MODE1. */
16659 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
16661 if (mode1 == mode2)
16664 if (ix86_tieable_integer_mode_p (mode1)
16665 && ix86_tieable_integer_mode_p (mode2))
16668 /* MODE2 being XFmode implies fp stack or general regs, which means we
16669 can tie any smaller floating point modes to it. Note that we do not
16670 tie this with TFmode. */
16671 if (mode2 == XFmode)
16672 return mode1 == SFmode || mode1 == DFmode;
16674 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
16675 that we can tie it with SFmode. */
16676 if (mode2 == DFmode)
16677 return mode1 == SFmode;
16679 /* If MODE2 is only appropriate for an SSE register, then tie with
16680 any other mode acceptable to SSE registers. */
16681 if (GET_MODE_SIZE (mode2) >= 8
16682 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
16683 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
16685 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
16686 with any other mode acceptable to MMX registers. */
16687 if (GET_MODE_SIZE (mode2) == 8
16688 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
16689 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
16694 /* Return the cost of moving data of mode M between a
16695 register and memory. A value of 2 is the default; this cost is
16696 relative to those in `REGISTER_MOVE_COST'.
16698 If moving between registers and memory is more expensive than
16699 between two registers, you should define this macro to express the
16702 Model also increased moving costs of QImode registers in non
16706 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
16708 if (FLOAT_CLASS_P (class))
16725 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
16727 if (SSE_CLASS_P (class))
16730 switch (GET_MODE_SIZE (mode))
16744 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
16746 if (MMX_CLASS_P (class))
16749 switch (GET_MODE_SIZE (mode))
16760 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
16762 switch (GET_MODE_SIZE (mode))
16766 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
16767 : ix86_cost->movzbl_load);
16769 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
16770 : ix86_cost->int_store[0] + 4);
16773 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
16775 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
16776 if (mode == TFmode)
16778 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
16779 * (((int) GET_MODE_SIZE (mode)
16780 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
16784 /* Compute a (partial) cost for rtx X. Return true if the complete
16785 cost has been computed, and false if subexpressions should be
16786 scanned. In either case, *TOTAL contains the cost result. */
16789 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
16791 enum machine_mode mode = GET_MODE (x);
16799 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
16801 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
16803 else if (flag_pic && SYMBOLIC_CONST (x)
16805 || (!GET_CODE (x) != LABEL_REF
16806 && (GET_CODE (x) != SYMBOL_REF
16807 || !SYMBOL_REF_LOCAL_P (x)))))
16814 if (mode == VOIDmode)
16817 switch (standard_80387_constant_p (x))
16822 default: /* Other constants */
16827 /* Start with (MEM (SYMBOL_REF)), since that's where
16828 it'll probably end up. Add a penalty for size. */
16829 *total = (COSTS_N_INSNS (1)
16830 + (flag_pic != 0 && !TARGET_64BIT)
16831 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
16837 /* The zero extensions is often completely free on x86_64, so make
16838 it as cheap as possible. */
16839 if (TARGET_64BIT && mode == DImode
16840 && GET_MODE (XEXP (x, 0)) == SImode)
16842 else if (TARGET_ZERO_EXTEND_WITH_AND)
16843 *total = ix86_cost->add;
16845 *total = ix86_cost->movzx;
16849 *total = ix86_cost->movsx;
16853 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16854 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
16856 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16859 *total = ix86_cost->add;
16862 if ((value == 2 || value == 3)
16863 && ix86_cost->lea <= ix86_cost->shift_const)
16865 *total = ix86_cost->lea;
16875 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
16877 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16879 if (INTVAL (XEXP (x, 1)) > 32)
16880 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
16882 *total = ix86_cost->shift_const * 2;
16886 if (GET_CODE (XEXP (x, 1)) == AND)
16887 *total = ix86_cost->shift_var * 2;
16889 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
16894 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16895 *total = ix86_cost->shift_const;
16897 *total = ix86_cost->shift_var;
16902 if (FLOAT_MODE_P (mode))
16904 *total = ix86_cost->fmul;
16909 rtx op0 = XEXP (x, 0);
16910 rtx op1 = XEXP (x, 1);
16912 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16914 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16915 for (nbits = 0; value != 0; value &= value - 1)
16919 /* This is arbitrary. */
16922 /* Compute costs correctly for widening multiplication. */
16923 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
16924 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
16925 == GET_MODE_SIZE (mode))
16927 int is_mulwiden = 0;
16928 enum machine_mode inner_mode = GET_MODE (op0);
16930 if (GET_CODE (op0) == GET_CODE (op1))
16931 is_mulwiden = 1, op1 = XEXP (op1, 0);
16932 else if (GET_CODE (op1) == CONST_INT)
16934 if (GET_CODE (op0) == SIGN_EXTEND)
16935 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
16938 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
16942 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
16945 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
16946 + nbits * ix86_cost->mult_bit
16947 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
16956 if (FLOAT_MODE_P (mode))
16957 *total = ix86_cost->fdiv;
16959 *total = ix86_cost->divide[MODE_INDEX (mode)];
16963 if (FLOAT_MODE_P (mode))
16964 *total = ix86_cost->fadd;
16965 else if (GET_MODE_CLASS (mode) == MODE_INT
16966 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
16968 if (GET_CODE (XEXP (x, 0)) == PLUS
16969 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
16970 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
16971 && CONSTANT_P (XEXP (x, 1)))
16973 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
16974 if (val == 2 || val == 4 || val == 8)
16976 *total = ix86_cost->lea;
16977 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16978 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
16980 *total += rtx_cost (XEXP (x, 1), outer_code);
16984 else if (GET_CODE (XEXP (x, 0)) == MULT
16985 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
16987 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
16988 if (val == 2 || val == 4 || val == 8)
16990 *total = ix86_cost->lea;
16991 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16992 *total += rtx_cost (XEXP (x, 1), outer_code);
16996 else if (GET_CODE (XEXP (x, 0)) == PLUS)
16998 *total = ix86_cost->lea;
16999 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
17000 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
17001 *total += rtx_cost (XEXP (x, 1), outer_code);
17008 if (FLOAT_MODE_P (mode))
17010 *total = ix86_cost->fadd;
17018 if (!TARGET_64BIT && mode == DImode)
17020 *total = (ix86_cost->add * 2
17021 + (rtx_cost (XEXP (x, 0), outer_code)
17022 << (GET_MODE (XEXP (x, 0)) != DImode))
17023 + (rtx_cost (XEXP (x, 1), outer_code)
17024 << (GET_MODE (XEXP (x, 1)) != DImode)));
17030 if (FLOAT_MODE_P (mode))
17032 *total = ix86_cost->fchs;
17038 if (!TARGET_64BIT && mode == DImode)
17039 *total = ix86_cost->add * 2;
17041 *total = ix86_cost->add;
17045 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
17046 && XEXP (XEXP (x, 0), 1) == const1_rtx
17047 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
17048 && XEXP (x, 1) == const0_rtx)
17050 /* This kind of construct is implemented using test[bwl].
17051 Treat it as if we had an AND. */
17052 *total = (ix86_cost->add
17053 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
17054 + rtx_cost (const1_rtx, outer_code));
17060 if (!TARGET_SSE_MATH
17062 || (mode == DFmode && !TARGET_SSE2))
17067 if (FLOAT_MODE_P (mode))
17068 *total = ix86_cost->fabs;
17072 if (FLOAT_MODE_P (mode))
17073 *total = ix86_cost->fsqrt;
17077 if (XINT (x, 1) == UNSPEC_TP)
17088 static int current_machopic_label_num;
17090 /* Given a symbol name and its associated stub, write out the
17091 definition of the stub. */
17094 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17096 unsigned int length;
17097 char *binder_name, *symbol_name, lazy_ptr_name[32];
17098 int label = ++current_machopic_label_num;
17100 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17101 symb = (*targetm.strip_name_encoding) (symb);
17103 length = strlen (stub);
17104 binder_name = alloca (length + 32);
17105 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
17107 length = strlen (symb);
17108 symbol_name = alloca (length + 32);
17109 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17111 sprintf (lazy_ptr_name, "L%d$lz", label);
17114 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
17116 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
17118 fprintf (file, "%s:\n", stub);
17119 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17123 fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label, label);
17124 fprintf (file, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
17125 fprintf (file, "\tjmp *%%edx\n");
17128 fprintf (file, "\tjmp *%s\n", lazy_ptr_name);
17130 fprintf (file, "%s:\n", binder_name);
17134 fprintf (file, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
17135 fprintf (file, "\tpushl %%eax\n");
17138 fprintf (file, "\t pushl $%s\n", lazy_ptr_name);
17140 fprintf (file, "\tjmp dyld_stub_binding_helper\n");
17142 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17143 fprintf (file, "%s:\n", lazy_ptr_name);
17144 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17145 fprintf (file, "\t.long %s\n", binder_name);
17149 darwin_x86_file_end (void)
17151 darwin_file_end ();
17154 #endif /* TARGET_MACHO */
17156 /* Order the registers for register allocator. */
17159 x86_order_regs_for_local_alloc (void)
17164 /* First allocate the local general purpose registers. */
17165 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17166 if (GENERAL_REGNO_P (i) && call_used_regs[i])
17167 reg_alloc_order [pos++] = i;
17169 /* Global general purpose registers. */
17170 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17171 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
17172 reg_alloc_order [pos++] = i;
17174 /* x87 registers come first in case we are doing FP math
17176 if (!TARGET_SSE_MATH)
17177 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
17178 reg_alloc_order [pos++] = i;
17180 /* SSE registers. */
17181 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
17182 reg_alloc_order [pos++] = i;
17183 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
17184 reg_alloc_order [pos++] = i;
17186 /* x87 registers. */
17187 if (TARGET_SSE_MATH)
17188 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
17189 reg_alloc_order [pos++] = i;
17191 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
17192 reg_alloc_order [pos++] = i;
17194 /* Initialize the rest of array as we do not allocate some registers
17196 while (pos < FIRST_PSEUDO_REGISTER)
17197 reg_alloc_order [pos++] = 0;
17200 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
17201 struct attribute_spec.handler. */
17203 ix86_handle_struct_attribute (tree *node, tree name,
17204 tree args ATTRIBUTE_UNUSED,
17205 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
17208 if (DECL_P (*node))
17210 if (TREE_CODE (*node) == TYPE_DECL)
17211 type = &TREE_TYPE (*node);
17216 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
17217 || TREE_CODE (*type) == UNION_TYPE)))
17219 warning (OPT_Wattributes, "%qs attribute ignored",
17220 IDENTIFIER_POINTER (name));
17221 *no_add_attrs = true;
17224 else if ((is_attribute_p ("ms_struct", name)
17225 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
17226 || ((is_attribute_p ("gcc_struct", name)
17227 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
17229 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
17230 IDENTIFIER_POINTER (name));
17231 *no_add_attrs = true;
17238 ix86_ms_bitfield_layout_p (tree record_type)
17240 return (TARGET_MS_BITFIELD_LAYOUT &&
17241 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
17242 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
17245 /* Returns an expression indicating where the this parameter is
17246 located on entry to the FUNCTION. */
17249 x86_this_parameter (tree function)
17251 tree type = TREE_TYPE (function);
17255 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
17256 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
17259 if (ix86_function_regparm (type, function) > 0)
17263 parm = TYPE_ARG_TYPES (type);
17264 /* Figure out whether or not the function has a variable number of
17266 for (; parm; parm = TREE_CHAIN (parm))
17267 if (TREE_VALUE (parm) == void_type_node)
17269 /* If not, the this parameter is in the first argument. */
17273 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
17275 return gen_rtx_REG (SImode, regno);
17279 if (aggregate_value_p (TREE_TYPE (type), type))
17280 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
17282 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
17285 /* Determine whether x86_output_mi_thunk can succeed. */
17288 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
17289 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
17290 HOST_WIDE_INT vcall_offset, tree function)
17292 /* 64-bit can handle anything. */
17296 /* For 32-bit, everything's fine if we have one free register. */
17297 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
17300 /* Need a free register for vcall_offset. */
17304 /* Need a free register for GOT references. */
17305 if (flag_pic && !(*targetm.binds_local_p) (function))
17308 /* Otherwise ok. */
17312 /* Output the assembler code for a thunk function. THUNK_DECL is the
17313 declaration for the thunk function itself, FUNCTION is the decl for
17314 the target function. DELTA is an immediate constant offset to be
17315 added to THIS. If VCALL_OFFSET is nonzero, the word at
17316 *(*this + vcall_offset) should be added to THIS. */
17319 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
17320 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
17321 HOST_WIDE_INT vcall_offset, tree function)
17324 rtx this = x86_this_parameter (function);
17327 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
17328 pull it in now and let DELTA benefit. */
17331 else if (vcall_offset)
17333 /* Put the this parameter into %eax. */
17335 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
17336 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17339 this_reg = NULL_RTX;
17341 /* Adjust the this parameter by a fixed constant. */
17344 xops[0] = GEN_INT (delta);
17345 xops[1] = this_reg ? this_reg : this;
17348 if (!x86_64_general_operand (xops[0], DImode))
17350 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
17352 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
17356 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
17359 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
17362 /* Adjust the this parameter by a value stored in the vtable. */
17366 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
17369 int tmp_regno = 2 /* ECX */;
17370 if (lookup_attribute ("fastcall",
17371 TYPE_ATTRIBUTES (TREE_TYPE (function))))
17372 tmp_regno = 0 /* EAX */;
17373 tmp = gen_rtx_REG (SImode, tmp_regno);
17376 xops[0] = gen_rtx_MEM (Pmode, this_reg);
17379 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
17381 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17383 /* Adjust the this parameter. */
17384 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
17385 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
17387 rtx tmp2 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
17388 xops[0] = GEN_INT (vcall_offset);
17390 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
17391 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
17393 xops[1] = this_reg;
17395 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
17397 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
17400 /* If necessary, drop THIS back to its stack slot. */
17401 if (this_reg && this_reg != this)
17403 xops[0] = this_reg;
17405 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17408 xops[0] = XEXP (DECL_RTL (function), 0);
17411 if (!flag_pic || (*targetm.binds_local_p) (function))
17412 output_asm_insn ("jmp\t%P0", xops);
17415 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
17416 tmp = gen_rtx_CONST (Pmode, tmp);
17417 tmp = gen_rtx_MEM (QImode, tmp);
17419 output_asm_insn ("jmp\t%A0", xops);
17424 if (!flag_pic || (*targetm.binds_local_p) (function))
17425 output_asm_insn ("jmp\t%P0", xops);
17430 rtx sym_ref = XEXP (DECL_RTL (function), 0);
17431 tmp = (gen_rtx_SYMBOL_REF
17433 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
17434 tmp = gen_rtx_MEM (QImode, tmp);
17436 output_asm_insn ("jmp\t%0", xops);
17439 #endif /* TARGET_MACHO */
17441 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
17442 output_set_got (tmp, NULL_RTX);
17445 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
17446 output_asm_insn ("jmp\t{*}%1", xops);
17452 x86_file_start (void)
17454 default_file_start ();
17455 if (X86_FILE_START_VERSION_DIRECTIVE)
17456 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
17457 if (X86_FILE_START_FLTUSED)
17458 fputs ("\t.global\t__fltused\n", asm_out_file);
17459 if (ix86_asm_dialect == ASM_INTEL)
17460 fputs ("\t.intel_syntax\n", asm_out_file);
17464 x86_field_alignment (tree field, int computed)
17466 enum machine_mode mode;
17467 tree type = TREE_TYPE (field);
17469 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
17471 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
17472 ? get_inner_array_type (type) : type);
17473 if (mode == DFmode || mode == DCmode
17474 || GET_MODE_CLASS (mode) == MODE_INT
17475 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
17476 return MIN (32, computed);
17480 /* Output assembler code to FILE to increment profiler label # LABELNO
17481 for profiling a function entry. */
17483 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
17488 #ifndef NO_PROFILE_COUNTERS
17489 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
17491 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
17495 #ifndef NO_PROFILE_COUNTERS
17496 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
17498 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
17502 #ifndef NO_PROFILE_COUNTERS
17503 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
17504 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
17506 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
17510 #ifndef NO_PROFILE_COUNTERS
17511 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
17512 PROFILE_COUNT_REGISTER);
17514 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
17518 /* We don't have exact information about the insn sizes, but we may assume
17519 quite safely that we are informed about all 1 byte insns and memory
17520 address sizes. This is enough to eliminate unnecessary padding in
17524 min_insn_size (rtx insn)
17528 if (!INSN_P (insn) || !active_insn_p (insn))
17531 /* Discard alignments we've emit and jump instructions. */
17532 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
17533 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
17535 if (GET_CODE (insn) == JUMP_INSN
17536 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
17537 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
17540 /* Important case - calls are always 5 bytes.
17541 It is common to have many calls in the row. */
17542 if (GET_CODE (insn) == CALL_INSN
17543 && symbolic_reference_mentioned_p (PATTERN (insn))
17544 && !SIBLING_CALL_P (insn))
17546 if (get_attr_length (insn) <= 1)
17549 /* For normal instructions we may rely on the sizes of addresses
17550 and the presence of symbol to require 4 bytes of encoding.
17551 This is not the case for jumps where references are PC relative. */
17552 if (GET_CODE (insn) != JUMP_INSN)
17554 l = get_attr_length_address (insn);
17555 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
17564 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
17568 ix86_avoid_jump_misspredicts (void)
17570 rtx insn, start = get_insns ();
17571 int nbytes = 0, njumps = 0;
17574 /* Look for all minimal intervals of instructions containing 4 jumps.
17575 The intervals are bounded by START and INSN. NBYTES is the total
17576 size of instructions in the interval including INSN and not including
17577 START. When the NBYTES is smaller than 16 bytes, it is possible
17578 that the end of START and INSN ends up in the same 16byte page.
17580 The smallest offset in the page INSN can start is the case where START
17581 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
17582 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
17584 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17587 nbytes += min_insn_size (insn);
17589 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
17590 INSN_UID (insn), min_insn_size (insn));
17591 if ((GET_CODE (insn) == JUMP_INSN
17592 && GET_CODE (PATTERN (insn)) != ADDR_VEC
17593 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
17594 || GET_CODE (insn) == CALL_INSN)
17601 start = NEXT_INSN (start);
17602 if ((GET_CODE (start) == JUMP_INSN
17603 && GET_CODE (PATTERN (start)) != ADDR_VEC
17604 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
17605 || GET_CODE (start) == CALL_INSN)
17606 njumps--, isjump = 1;
17609 nbytes -= min_insn_size (start);
17611 gcc_assert (njumps >= 0);
17613 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
17614 INSN_UID (start), INSN_UID (insn), nbytes);
17616 if (njumps == 3 && isjump && nbytes < 16)
17618 int padsize = 15 - nbytes + min_insn_size (insn);
17621 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
17622 INSN_UID (insn), padsize);
17623 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
17628 /* AMD Athlon works faster
17629 when RET is not destination of conditional jump or directly preceded
17630 by other jump instruction. We avoid the penalty by inserting NOP just
17631 before the RET instructions in such cases. */
17633 ix86_pad_returns (void)
17638 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
17640 basic_block bb = e->src;
17641 rtx ret = BB_END (bb);
17643 bool replace = false;
17645 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
17646 || !maybe_hot_bb_p (bb))
17648 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
17649 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
17651 if (prev && GET_CODE (prev) == CODE_LABEL)
17656 FOR_EACH_EDGE (e, ei, bb->preds)
17657 if (EDGE_FREQUENCY (e) && e->src->index >= 0
17658 && !(e->flags & EDGE_FALLTHRU))
17663 prev = prev_active_insn (ret);
17665 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
17666 || GET_CODE (prev) == CALL_INSN))
17668 /* Empty functions get branch mispredict even when the jump destination
17669 is not visible to us. */
17670 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
17675 emit_insn_before (gen_return_internal_long (), ret);
17681 /* Implement machine specific optimizations. We implement padding of returns
17682 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
17686 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
17687 ix86_pad_returns ();
17688 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
17689 ix86_avoid_jump_misspredicts ();
17692 /* Return nonzero when QImode register that must be represented via REX prefix
17695 x86_extended_QIreg_mentioned_p (rtx insn)
17698 extract_insn_cached (insn);
17699 for (i = 0; i < recog_data.n_operands; i++)
17700 if (REG_P (recog_data.operand[i])
17701 && REGNO (recog_data.operand[i]) >= 4)
17706 /* Return nonzero when P points to register encoded via REX prefix.
17707 Called via for_each_rtx. */
17709 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
17711 unsigned int regno;
17714 regno = REGNO (*p);
17715 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
17718 /* Return true when INSN mentions register that must be encoded using REX
17721 x86_extended_reg_mentioned_p (rtx insn)
17723 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
17726 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
17727 optabs would emit if we didn't have TFmode patterns. */
17730 x86_emit_floatuns (rtx operands[2])
17732 rtx neglab, donelab, i0, i1, f0, in, out;
17733 enum machine_mode mode, inmode;
17735 inmode = GET_MODE (operands[1]);
17736 gcc_assert (inmode == SImode || inmode == DImode);
17739 in = force_reg (inmode, operands[1]);
17740 mode = GET_MODE (out);
17741 neglab = gen_label_rtx ();
17742 donelab = gen_label_rtx ();
17743 i1 = gen_reg_rtx (Pmode);
17744 f0 = gen_reg_rtx (mode);
17746 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
17748 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
17749 emit_jump_insn (gen_jump (donelab));
17752 emit_label (neglab);
17754 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17755 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17756 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
17757 expand_float (f0, i0, 0);
17758 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
17760 emit_label (donelab);
17763 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17764 with all elements equal to VAR. Return true if successful. */
17767 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
17768 rtx target, rtx val)
17770 enum machine_mode smode, wsmode, wvmode;
17777 if (!mmx_ok && !TARGET_SSE)
17785 val = force_reg (GET_MODE_INNER (mode), val);
17786 x = gen_rtx_VEC_DUPLICATE (mode, val);
17787 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17793 if (TARGET_SSE || TARGET_3DNOW_A)
17795 val = gen_lowpart (SImode, val);
17796 x = gen_rtx_TRUNCATE (HImode, val);
17797 x = gen_rtx_VEC_DUPLICATE (mode, x);
17798 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17827 /* Replicate the value once into the next wider mode and recurse. */
17828 val = convert_modes (wsmode, smode, val, true);
17829 x = expand_simple_binop (wsmode, ASHIFT, val,
17830 GEN_INT (GET_MODE_BITSIZE (smode)),
17831 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17832 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
17834 x = gen_reg_rtx (wvmode);
17835 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
17836 gcc_unreachable ();
17837 emit_move_insn (target, gen_lowpart (mode, x));
17845 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17846 whose low element is VAR, and other elements are zero. Return true
17850 ix86_expand_vector_init_low_nonzero (bool mmx_ok, enum machine_mode mode,
17851 rtx target, rtx var)
17853 enum machine_mode vsimode;
17860 if (!mmx_ok && !TARGET_SSE)
17866 var = force_reg (GET_MODE_INNER (mode), var);
17867 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
17868 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17873 var = force_reg (GET_MODE_INNER (mode), var);
17874 x = gen_rtx_VEC_DUPLICATE (mode, var);
17875 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
17876 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17881 vsimode = V4SImode;
17887 vsimode = V2SImode;
17890 /* Zero extend the variable element to SImode and recurse. */
17891 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
17893 x = gen_reg_rtx (vsimode);
17894 if (!ix86_expand_vector_init_low_nonzero (mmx_ok, vsimode, x, var))
17895 gcc_unreachable ();
17897 emit_move_insn (target, gen_lowpart (mode, x));
17905 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17906 consisting of the values in VALS. It is known that all elements
17907 except ONE_VAR are constants. Return true if successful. */
17910 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
17911 rtx target, rtx vals, int one_var)
17913 rtx var = XVECEXP (vals, 0, one_var);
17914 enum machine_mode wmode;
17917 const_vec = copy_rtx (vals);
17918 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
17919 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
17927 /* For the two element vectors, it's just as easy to use
17928 the general case. */
17944 /* There's no way to set one QImode entry easily. Combine
17945 the variable value with its adjacent constant value, and
17946 promote to an HImode set. */
17947 x = XVECEXP (vals, 0, one_var ^ 1);
17950 var = convert_modes (HImode, QImode, var, true);
17951 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
17952 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17953 x = GEN_INT (INTVAL (x) & 0xff);
17957 var = convert_modes (HImode, QImode, var, true);
17958 x = gen_int_mode (INTVAL (x) << 8, HImode);
17960 if (x != const0_rtx)
17961 var = expand_simple_binop (HImode, IOR, var, x, var,
17962 1, OPTAB_LIB_WIDEN);
17964 x = gen_reg_rtx (wmode);
17965 emit_move_insn (x, gen_lowpart (wmode, const_vec));
17966 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
17968 emit_move_insn (target, gen_lowpart (mode, x));
17975 emit_move_insn (target, const_vec);
17976 ix86_expand_vector_set (mmx_ok, target, var, one_var);
17980 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
17981 all values variable, and none identical. */
17984 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
17985 rtx target, rtx vals)
17987 enum machine_mode half_mode = GET_MODE_INNER (mode);
17988 rtx op0 = NULL, op1 = NULL;
17989 bool use_vec_concat = false;
17995 if (!mmx_ok && !TARGET_SSE)
18001 /* For the two element vectors, we always implement VEC_CONCAT. */
18002 op0 = XVECEXP (vals, 0, 0);
18003 op1 = XVECEXP (vals, 0, 1);
18004 use_vec_concat = true;
18008 half_mode = V2SFmode;
18011 half_mode = V2SImode;
18017 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
18018 Recurse to load the two halves. */
18020 op0 = gen_reg_rtx (half_mode);
18021 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
18022 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
18024 op1 = gen_reg_rtx (half_mode);
18025 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
18026 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
18028 use_vec_concat = true;
18039 gcc_unreachable ();
18042 if (use_vec_concat)
18044 if (!register_operand (op0, half_mode))
18045 op0 = force_reg (half_mode, op0);
18046 if (!register_operand (op1, half_mode))
18047 op1 = force_reg (half_mode, op1);
18049 emit_insn (gen_rtx_SET (VOIDmode, target,
18050 gen_rtx_VEC_CONCAT (mode, op0, op1)));
18054 int i, j, n_elts, n_words, n_elt_per_word;
18055 enum machine_mode inner_mode;
18056 rtx words[4], shift;
18058 inner_mode = GET_MODE_INNER (mode);
18059 n_elts = GET_MODE_NUNITS (mode);
18060 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
18061 n_elt_per_word = n_elts / n_words;
18062 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
18064 for (i = 0; i < n_words; ++i)
18066 rtx word = NULL_RTX;
18068 for (j = 0; j < n_elt_per_word; ++j)
18070 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
18071 elt = convert_modes (word_mode, inner_mode, elt, true);
18077 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
18078 word, 1, OPTAB_LIB_WIDEN);
18079 word = expand_simple_binop (word_mode, IOR, word, elt,
18080 word, 1, OPTAB_LIB_WIDEN);
18088 emit_move_insn (target, gen_lowpart (mode, words[0]));
18089 else if (n_words == 2)
18091 rtx tmp = gen_reg_rtx (mode);
18092 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
18093 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
18094 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
18095 emit_move_insn (target, tmp);
18097 else if (n_words == 4)
18099 rtx tmp = gen_reg_rtx (V4SImode);
18100 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
18101 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
18102 emit_move_insn (target, gen_lowpart (mode, tmp));
18105 gcc_unreachable ();
18109 /* Initialize vector TARGET via VALS. Suppress the use of MMX
18110 instructions unless MMX_OK is true. */
18113 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
18115 enum machine_mode mode = GET_MODE (target);
18116 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18117 int n_elts = GET_MODE_NUNITS (mode);
18118 int n_var = 0, one_var = -1;
18119 bool all_same = true, all_const_zero = true;
18123 for (i = 0; i < n_elts; ++i)
18125 x = XVECEXP (vals, 0, i);
18126 if (!CONSTANT_P (x))
18127 n_var++, one_var = i;
18128 else if (x != CONST0_RTX (inner_mode))
18129 all_const_zero = false;
18130 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18134 /* Constants are best loaded from the constant pool. */
18137 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
18141 /* If all values are identical, broadcast the value. */
18143 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
18144 XVECEXP (vals, 0, 0)))
18147 /* Values where only one field is non-constant are best loaded from
18148 the pool and overwritten via move later. */
18151 if (all_const_zero && one_var == 0
18152 && ix86_expand_vector_init_low_nonzero (mmx_ok, mode, target,
18153 XVECEXP (vals, 0, 0)))
18156 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
18160 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
18164 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
18166 enum machine_mode mode = GET_MODE (target);
18167 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18168 bool use_vec_merge = false;
18177 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
18178 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
18180 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
18182 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
18183 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18193 /* For the two element vectors, we implement a VEC_CONCAT with
18194 the extraction of the other element. */
18196 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
18197 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
18200 op0 = val, op1 = tmp;
18202 op0 = tmp, op1 = val;
18204 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
18205 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18213 use_vec_merge = true;
18217 /* tmp = target = A B C D */
18218 tmp = copy_to_reg (target);
18219 /* target = A A B B */
18220 emit_insn (gen_sse_unpcklps (target, target, target));
18221 /* target = X A B B */
18222 ix86_expand_vector_set (false, target, val, 0);
18223 /* target = A X C D */
18224 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18225 GEN_INT (1), GEN_INT (0),
18226 GEN_INT (2+4), GEN_INT (3+4)));
18230 /* tmp = target = A B C D */
18231 tmp = copy_to_reg (target);
18232 /* tmp = X B C D */
18233 ix86_expand_vector_set (false, tmp, val, 0);
18234 /* target = A B X D */
18235 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18236 GEN_INT (0), GEN_INT (1),
18237 GEN_INT (0+4), GEN_INT (3+4)));
18241 /* tmp = target = A B C D */
18242 tmp = copy_to_reg (target);
18243 /* tmp = X B C D */
18244 ix86_expand_vector_set (false, tmp, val, 0);
18245 /* target = A B X D */
18246 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18247 GEN_INT (0), GEN_INT (1),
18248 GEN_INT (2+4), GEN_INT (0+4)));
18252 gcc_unreachable ();
18257 /* Element 0 handled by vec_merge below. */
18260 use_vec_merge = true;
18266 /* With SSE2, use integer shuffles to swap element 0 and ELT,
18267 store into element 0, then shuffle them back. */
18271 order[0] = GEN_INT (elt);
18272 order[1] = const1_rtx;
18273 order[2] = const2_rtx;
18274 order[3] = GEN_INT (3);
18275 order[elt] = const0_rtx;
18277 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
18278 order[1], order[2], order[3]));
18280 ix86_expand_vector_set (false, target, val, 0);
18282 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
18283 order[1], order[2], order[3]));
18287 /* For SSE1, we have to reuse the V4SF code. */
18288 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
18289 gen_lowpart (SFmode, val), elt);
18294 use_vec_merge = TARGET_SSE2;
18297 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
18308 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
18309 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
18310 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18314 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
18316 emit_move_insn (mem, target);
18318 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
18319 emit_move_insn (tmp, val);
18321 emit_move_insn (target, mem);
18326 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
18328 enum machine_mode mode = GET_MODE (vec);
18329 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18330 bool use_vec_extr = false;
18343 use_vec_extr = true;
18355 tmp = gen_reg_rtx (mode);
18356 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
18357 GEN_INT (elt), GEN_INT (elt),
18358 GEN_INT (elt+4), GEN_INT (elt+4)));
18362 tmp = gen_reg_rtx (mode);
18363 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
18367 gcc_unreachable ();
18370 use_vec_extr = true;
18385 tmp = gen_reg_rtx (mode);
18386 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
18387 GEN_INT (elt), GEN_INT (elt),
18388 GEN_INT (elt), GEN_INT (elt)));
18392 tmp = gen_reg_rtx (mode);
18393 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
18397 gcc_unreachable ();
18400 use_vec_extr = true;
18405 /* For SSE1, we have to reuse the V4SF code. */
18406 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
18407 gen_lowpart (V4SFmode, vec), elt);
18413 use_vec_extr = TARGET_SSE2;
18416 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
18421 /* ??? Could extract the appropriate HImode element and shift. */
18428 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
18429 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
18431 /* Let the rtl optimizers know about the zero extension performed. */
18432 if (inner_mode == HImode)
18434 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
18435 target = gen_lowpart (SImode, target);
18438 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18442 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
18444 emit_move_insn (mem, vec);
18446 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
18447 emit_move_insn (target, tmp);
18451 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
18452 pattern to reduce; DEST is the destination; IN is the input vector. */
18455 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
18457 rtx tmp1, tmp2, tmp3;
18459 tmp1 = gen_reg_rtx (V4SFmode);
18460 tmp2 = gen_reg_rtx (V4SFmode);
18461 tmp3 = gen_reg_rtx (V4SFmode);
18463 emit_insn (gen_sse_movhlps (tmp1, in, in));
18464 emit_insn (fn (tmp2, tmp1, in));
18466 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
18467 GEN_INT (1), GEN_INT (1),
18468 GEN_INT (1+4), GEN_INT (1+4)));
18469 emit_insn (fn (dest, tmp2, tmp3));
18472 /* Target hook for scalar_mode_supported_p. */
18474 ix86_scalar_mode_supported_p (enum machine_mode mode)
18476 if (DECIMAL_FLOAT_MODE_P (mode))
18479 return default_scalar_mode_supported_p (mode);
18482 /* Implements target hook vector_mode_supported_p. */
18484 ix86_vector_mode_supported_p (enum machine_mode mode)
18486 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
18488 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
18490 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
18492 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
18497 /* Worker function for TARGET_MD_ASM_CLOBBERS.
18499 We do this in the new i386 backend to maintain source compatibility
18500 with the old cc0-based compiler. */
18503 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
18504 tree inputs ATTRIBUTE_UNUSED,
18507 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
18509 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
18511 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
18516 /* Return true if this goes in small data/bss. */
18519 ix86_in_large_data_p (tree exp)
18521 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
18524 /* Functions are never large data. */
18525 if (TREE_CODE (exp) == FUNCTION_DECL)
18528 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
18530 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
18531 if (strcmp (section, ".ldata") == 0
18532 || strcmp (section, ".lbss") == 0)
18538 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
18540 /* If this is an incomplete type with size 0, then we can't put it
18541 in data because it might be too big when completed. */
18542 if (!size || size > ix86_section_threshold)
18549 ix86_encode_section_info (tree decl, rtx rtl, int first)
18551 default_encode_section_info (decl, rtl, first);
18553 if (TREE_CODE (decl) == VAR_DECL
18554 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
18555 && ix86_in_large_data_p (decl))
18556 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
18559 /* Worker function for REVERSE_CONDITION. */
18562 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
18564 return (mode != CCFPmode && mode != CCFPUmode
18565 ? reverse_condition (code)
18566 : reverse_condition_maybe_unordered (code));
18569 /* Output code to perform an x87 FP register move, from OPERANDS[1]
18573 output_387_reg_move (rtx insn, rtx *operands)
18575 if (REG_P (operands[1])
18576 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
18578 if (REGNO (operands[0]) == FIRST_STACK_REG
18579 && TARGET_USE_FFREEP)
18580 return "ffreep\t%y0";
18581 return "fstp\t%y0";
18583 if (STACK_TOP_P (operands[0]))
18584 return "fld%z1\t%y1";
18588 /* Output code to perform a conditional jump to LABEL, if C2 flag in
18589 FP status register is set. */
18592 ix86_emit_fp_unordered_jump (rtx label)
18594 rtx reg = gen_reg_rtx (HImode);
18597 emit_insn (gen_x86_fnstsw_1 (reg));
18599 if (TARGET_USE_SAHF)
18601 emit_insn (gen_x86_sahf_1 (reg));
18603 temp = gen_rtx_REG (CCmode, FLAGS_REG);
18604 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
18608 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
18610 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18611 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
18614 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
18615 gen_rtx_LABEL_REF (VOIDmode, label),
18617 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
18618 emit_jump_insn (temp);
18621 /* Output code to perform a log1p XFmode calculation. */
18623 void ix86_emit_i387_log1p (rtx op0, rtx op1)
18625 rtx label1 = gen_label_rtx ();
18626 rtx label2 = gen_label_rtx ();
18628 rtx tmp = gen_reg_rtx (XFmode);
18629 rtx tmp2 = gen_reg_rtx (XFmode);
18631 emit_insn (gen_absxf2 (tmp, op1));
18632 emit_insn (gen_cmpxf (tmp,
18633 CONST_DOUBLE_FROM_REAL_VALUE (
18634 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
18636 emit_jump_insn (gen_bge (label1));
18638 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18639 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
18640 emit_jump (label2);
18642 emit_label (label1);
18643 emit_move_insn (tmp, CONST1_RTX (XFmode));
18644 emit_insn (gen_addxf3 (tmp, op1, tmp));
18645 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18646 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
18648 emit_label (label2);
18651 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
18654 i386_solaris_elf_named_section (const char *name, unsigned int flags,
18657 /* With Binutils 2.15, the "@unwind" marker must be specified on
18658 every occurrence of the ".eh_frame" section, not just the first
18661 && strcmp (name, ".eh_frame") == 0)
18663 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
18664 flags & SECTION_WRITE ? "aw" : "a");
18667 default_elf_asm_named_section (name, flags, decl);
18670 /* Return the mangling of TYPE if it is an extended fundamental type. */
18672 static const char *
18673 ix86_mangle_fundamental_type (tree type)
18675 switch (TYPE_MODE (type))
18678 /* __float128 is "g". */
18681 /* "long double" or __float80 is "e". */
18688 /* For 32-bit code we can save PIC register setup by using
18689 __stack_chk_fail_local hidden function instead of calling
18690 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
18691 register, so it is better to call __stack_chk_fail directly. */
18694 ix86_stack_protect_fail (void)
18696 return TARGET_64BIT
18697 ? default_external_stack_protect_fail ()
18698 : default_hidden_stack_protect_fail ();
18701 /* Select a format to encode pointers in exception handling data. CODE
18702 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
18703 true if the symbol may be affected by dynamic relocations.
18705 ??? All x86 object file formats are capable of representing this.
18706 After all, the relocation needed is the same as for the call insn.
18707 Whether or not a particular assembler allows us to enter such, I
18708 guess we'll have to see. */
18710 asm_preferred_eh_data_format (int code, int global)
18714 int type = DW_EH_PE_sdata8;
18716 || ix86_cmodel == CM_SMALL_PIC
18717 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
18718 type = DW_EH_PE_sdata4;
18719 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
18721 if (ix86_cmodel == CM_SMALL
18722 || (ix86_cmodel == CM_MEDIUM && code))
18723 return DW_EH_PE_udata4;
18724 return DW_EH_PE_absptr;
18727 #include "gt-i386.h"