1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #include "tm-constrs.h"
55 #ifndef CHECK_STACK_LIMIT
56 #define CHECK_STACK_LIMIT (-1)
59 /* Return index of given mode in mult and division cost tables. */
60 #define MODE_INDEX(mode) \
61 ((mode) == QImode ? 0 \
62 : (mode) == HImode ? 1 \
63 : (mode) == SImode ? 2 \
64 : (mode) == DImode ? 3 \
67 /* Processor costs (relative to an add) */
68 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
69 #define COSTS_N_BYTES(N) ((N) * 2)
71 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
74 struct processor_costs size_cost = { /* costs for tuning for size */
75 COSTS_N_BYTES (2), /* cost of an add instruction */
76 COSTS_N_BYTES (3), /* cost of a lea instruction */
77 COSTS_N_BYTES (2), /* variable shift costs */
78 COSTS_N_BYTES (3), /* constant shift costs */
79 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
80 COSTS_N_BYTES (3), /* HI */
81 COSTS_N_BYTES (3), /* SI */
82 COSTS_N_BYTES (3), /* DI */
83 COSTS_N_BYTES (5)}, /* other */
84 0, /* cost of multiply per each bit set */
85 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 COSTS_N_BYTES (3), /* cost of movsx */
91 COSTS_N_BYTES (3), /* cost of movzx */
94 2, /* cost for loading QImode using movzbl */
95 {2, 2, 2}, /* cost of loading integer registers
96 in QImode, HImode and SImode.
97 Relative to reg-reg move (2). */
98 {2, 2, 2}, /* cost of storing integer registers */
99 2, /* cost of reg,reg fld/fst */
100 {2, 2, 2}, /* cost of loading fp registers
101 in SFmode, DFmode and XFmode */
102 {2, 2, 2}, /* cost of storing fp registers
103 in SFmode, DFmode and XFmode */
104 3, /* cost of moving MMX register */
105 {3, 3}, /* cost of loading MMX registers
106 in SImode and DImode */
107 {3, 3}, /* cost of storing MMX registers
108 in SImode and DImode */
109 3, /* cost of moving SSE register */
110 {3, 3, 3}, /* cost of loading SSE registers
111 in SImode, DImode and TImode */
112 {3, 3, 3}, /* cost of storing SSE registers
113 in SImode, DImode and TImode */
114 3, /* MMX or SSE register to integer */
115 0, /* size of prefetch block */
116 0, /* number of parallel prefetches */
118 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
119 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
120 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
121 COSTS_N_BYTES (2), /* cost of FABS instruction. */
122 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
123 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
124 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
125 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
126 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
127 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}}
130 /* Processor costs (relative to an add) */
132 struct processor_costs i386_cost = { /* 386 specific costs */
133 COSTS_N_INSNS (1), /* cost of an add instruction */
134 COSTS_N_INSNS (1), /* cost of a lea instruction */
135 COSTS_N_INSNS (3), /* variable shift costs */
136 COSTS_N_INSNS (2), /* constant shift costs */
137 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
138 COSTS_N_INSNS (6), /* HI */
139 COSTS_N_INSNS (6), /* SI */
140 COSTS_N_INSNS (6), /* DI */
141 COSTS_N_INSNS (6)}, /* other */
142 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
143 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
144 COSTS_N_INSNS (23), /* HI */
145 COSTS_N_INSNS (23), /* SI */
146 COSTS_N_INSNS (23), /* DI */
147 COSTS_N_INSNS (23)}, /* other */
148 COSTS_N_INSNS (3), /* cost of movsx */
149 COSTS_N_INSNS (2), /* cost of movzx */
150 15, /* "large" insn */
152 4, /* cost for loading QImode using movzbl */
153 {2, 4, 2}, /* cost of loading integer registers
154 in QImode, HImode and SImode.
155 Relative to reg-reg move (2). */
156 {2, 4, 2}, /* cost of storing integer registers */
157 2, /* cost of reg,reg fld/fst */
158 {8, 8, 8}, /* cost of loading fp registers
159 in SFmode, DFmode and XFmode */
160 {8, 8, 8}, /* cost of storing fp registers
161 in SFmode, DFmode and XFmode */
162 2, /* cost of moving MMX register */
163 {4, 8}, /* cost of loading MMX registers
164 in SImode and DImode */
165 {4, 8}, /* cost of storing MMX registers
166 in SImode and DImode */
167 2, /* cost of moving SSE register */
168 {4, 8, 16}, /* cost of loading SSE registers
169 in SImode, DImode and TImode */
170 {4, 8, 16}, /* cost of storing SSE registers
171 in SImode, DImode and TImode */
172 3, /* MMX or SSE register to integer */
173 0, /* size of prefetch block */
174 0, /* number of parallel prefetches */
176 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
177 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
178 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
179 COSTS_N_INSNS (22), /* cost of FABS instruction. */
180 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
181 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
182 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
183 DUMMY_STRINGOP_ALGS},
184 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
185 DUMMY_STRINGOP_ALGS},
189 struct processor_costs i486_cost = { /* 486 specific costs */
190 COSTS_N_INSNS (1), /* cost of an add instruction */
191 COSTS_N_INSNS (1), /* cost of a lea instruction */
192 COSTS_N_INSNS (3), /* variable shift costs */
193 COSTS_N_INSNS (2), /* constant shift costs */
194 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
195 COSTS_N_INSNS (12), /* HI */
196 COSTS_N_INSNS (12), /* SI */
197 COSTS_N_INSNS (12), /* DI */
198 COSTS_N_INSNS (12)}, /* other */
199 1, /* cost of multiply per each bit set */
200 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
201 COSTS_N_INSNS (40), /* HI */
202 COSTS_N_INSNS (40), /* SI */
203 COSTS_N_INSNS (40), /* DI */
204 COSTS_N_INSNS (40)}, /* other */
205 COSTS_N_INSNS (3), /* cost of movsx */
206 COSTS_N_INSNS (2), /* cost of movzx */
207 15, /* "large" insn */
209 4, /* cost for loading QImode using movzbl */
210 {2, 4, 2}, /* cost of loading integer registers
211 in QImode, HImode and SImode.
212 Relative to reg-reg move (2). */
213 {2, 4, 2}, /* cost of storing integer registers */
214 2, /* cost of reg,reg fld/fst */
215 {8, 8, 8}, /* cost of loading fp registers
216 in SFmode, DFmode and XFmode */
217 {8, 8, 8}, /* cost of storing fp registers
218 in SFmode, DFmode and XFmode */
219 2, /* cost of moving MMX register */
220 {4, 8}, /* cost of loading MMX registers
221 in SImode and DImode */
222 {4, 8}, /* cost of storing MMX registers
223 in SImode and DImode */
224 2, /* cost of moving SSE register */
225 {4, 8, 16}, /* cost of loading SSE registers
226 in SImode, DImode and TImode */
227 {4, 8, 16}, /* cost of storing SSE registers
228 in SImode, DImode and TImode */
229 3, /* MMX or SSE register to integer */
230 0, /* size of prefetch block */
231 0, /* number of parallel prefetches */
233 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
234 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
235 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
236 COSTS_N_INSNS (3), /* cost of FABS instruction. */
237 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
238 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
239 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
240 DUMMY_STRINGOP_ALGS},
241 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
246 struct processor_costs pentium_cost = {
247 COSTS_N_INSNS (1), /* cost of an add instruction */
248 COSTS_N_INSNS (1), /* cost of a lea instruction */
249 COSTS_N_INSNS (4), /* variable shift costs */
250 COSTS_N_INSNS (1), /* constant shift costs */
251 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
252 COSTS_N_INSNS (11), /* HI */
253 COSTS_N_INSNS (11), /* SI */
254 COSTS_N_INSNS (11), /* DI */
255 COSTS_N_INSNS (11)}, /* other */
256 0, /* cost of multiply per each bit set */
257 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
258 COSTS_N_INSNS (25), /* HI */
259 COSTS_N_INSNS (25), /* SI */
260 COSTS_N_INSNS (25), /* DI */
261 COSTS_N_INSNS (25)}, /* other */
262 COSTS_N_INSNS (3), /* cost of movsx */
263 COSTS_N_INSNS (2), /* cost of movzx */
264 8, /* "large" insn */
266 6, /* cost for loading QImode using movzbl */
267 {2, 4, 2}, /* cost of loading integer registers
268 in QImode, HImode and SImode.
269 Relative to reg-reg move (2). */
270 {2, 4, 2}, /* cost of storing integer registers */
271 2, /* cost of reg,reg fld/fst */
272 {2, 2, 6}, /* cost of loading fp registers
273 in SFmode, DFmode and XFmode */
274 {4, 4, 6}, /* cost of storing fp registers
275 in SFmode, DFmode and XFmode */
276 8, /* cost of moving MMX register */
277 {8, 8}, /* cost of loading MMX registers
278 in SImode and DImode */
279 {8, 8}, /* cost of storing MMX registers
280 in SImode and DImode */
281 2, /* cost of moving SSE register */
282 {4, 8, 16}, /* cost of loading SSE registers
283 in SImode, DImode and TImode */
284 {4, 8, 16}, /* cost of storing SSE registers
285 in SImode, DImode and TImode */
286 3, /* MMX or SSE register to integer */
287 0, /* size of prefetch block */
288 0, /* number of parallel prefetches */
290 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
291 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
292 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
293 COSTS_N_INSNS (1), /* cost of FABS instruction. */
294 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
295 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
296 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
297 DUMMY_STRINGOP_ALGS},
298 {{libcall, {{-1, rep_prefix_4_byte}}},
303 struct processor_costs pentiumpro_cost = {
304 COSTS_N_INSNS (1), /* cost of an add instruction */
305 COSTS_N_INSNS (1), /* cost of a lea instruction */
306 COSTS_N_INSNS (1), /* variable shift costs */
307 COSTS_N_INSNS (1), /* constant shift costs */
308 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
309 COSTS_N_INSNS (4), /* HI */
310 COSTS_N_INSNS (4), /* SI */
311 COSTS_N_INSNS (4), /* DI */
312 COSTS_N_INSNS (4)}, /* other */
313 0, /* cost of multiply per each bit set */
314 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
315 COSTS_N_INSNS (17), /* HI */
316 COSTS_N_INSNS (17), /* SI */
317 COSTS_N_INSNS (17), /* DI */
318 COSTS_N_INSNS (17)}, /* other */
319 COSTS_N_INSNS (1), /* cost of movsx */
320 COSTS_N_INSNS (1), /* cost of movzx */
321 8, /* "large" insn */
323 2, /* cost for loading QImode using movzbl */
324 {4, 4, 4}, /* cost of loading integer registers
325 in QImode, HImode and SImode.
326 Relative to reg-reg move (2). */
327 {2, 2, 2}, /* cost of storing integer registers */
328 2, /* cost of reg,reg fld/fst */
329 {2, 2, 6}, /* cost of loading fp registers
330 in SFmode, DFmode and XFmode */
331 {4, 4, 6}, /* cost of storing fp registers
332 in SFmode, DFmode and XFmode */
333 2, /* cost of moving MMX register */
334 {2, 2}, /* cost of loading MMX registers
335 in SImode and DImode */
336 {2, 2}, /* cost of storing MMX registers
337 in SImode and DImode */
338 2, /* cost of moving SSE register */
339 {2, 2, 8}, /* cost of loading SSE registers
340 in SImode, DImode and TImode */
341 {2, 2, 8}, /* cost of storing SSE registers
342 in SImode, DImode and TImode */
343 3, /* MMX or SSE register to integer */
344 32, /* size of prefetch block */
345 6, /* number of parallel prefetches */
347 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
348 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
349 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
350 COSTS_N_INSNS (2), /* cost of FABS instruction. */
351 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
352 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
353 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
354 the alignment). For small blocks inline loop is still a noticeable win, for bigger
355 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
356 more expensive startup time in CPU, but after 4K the difference is down in the noise.
358 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
359 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
360 DUMMY_STRINGOP_ALGS},
361 {{rep_prefix_4_byte, {{1024, unrolled_loop},
362 {8192, rep_prefix_4_byte}, {-1, libcall}}},
367 struct processor_costs geode_cost = {
368 COSTS_N_INSNS (1), /* cost of an add instruction */
369 COSTS_N_INSNS (1), /* cost of a lea instruction */
370 COSTS_N_INSNS (2), /* variable shift costs */
371 COSTS_N_INSNS (1), /* constant shift costs */
372 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
373 COSTS_N_INSNS (4), /* HI */
374 COSTS_N_INSNS (7), /* SI */
375 COSTS_N_INSNS (7), /* DI */
376 COSTS_N_INSNS (7)}, /* other */
377 0, /* cost of multiply per each bit set */
378 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
379 COSTS_N_INSNS (23), /* HI */
380 COSTS_N_INSNS (39), /* SI */
381 COSTS_N_INSNS (39), /* DI */
382 COSTS_N_INSNS (39)}, /* other */
383 COSTS_N_INSNS (1), /* cost of movsx */
384 COSTS_N_INSNS (1), /* cost of movzx */
385 8, /* "large" insn */
387 1, /* cost for loading QImode using movzbl */
388 {1, 1, 1}, /* cost of loading integer registers
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
391 {1, 1, 1}, /* cost of storing integer registers */
392 1, /* cost of reg,reg fld/fst */
393 {1, 1, 1}, /* cost of loading fp registers
394 in SFmode, DFmode and XFmode */
395 {4, 6, 6}, /* cost of storing fp registers
396 in SFmode, DFmode and XFmode */
398 1, /* cost of moving MMX register */
399 {1, 1}, /* cost of loading MMX registers
400 in SImode and DImode */
401 {1, 1}, /* cost of storing MMX registers
402 in SImode and DImode */
403 1, /* cost of moving SSE register */
404 {1, 1, 1}, /* cost of loading SSE registers
405 in SImode, DImode and TImode */
406 {1, 1, 1}, /* cost of storing SSE registers
407 in SImode, DImode and TImode */
408 1, /* MMX or SSE register to integer */
409 32, /* size of prefetch block */
410 1, /* number of parallel prefetches */
412 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
413 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
414 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
415 COSTS_N_INSNS (1), /* cost of FABS instruction. */
416 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
417 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
418 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
419 DUMMY_STRINGOP_ALGS},
420 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
425 struct processor_costs k6_cost = {
426 COSTS_N_INSNS (1), /* cost of an add instruction */
427 COSTS_N_INSNS (2), /* cost of a lea instruction */
428 COSTS_N_INSNS (1), /* variable shift costs */
429 COSTS_N_INSNS (1), /* constant shift costs */
430 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
431 COSTS_N_INSNS (3), /* HI */
432 COSTS_N_INSNS (3), /* SI */
433 COSTS_N_INSNS (3), /* DI */
434 COSTS_N_INSNS (3)}, /* other */
435 0, /* cost of multiply per each bit set */
436 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
437 COSTS_N_INSNS (18), /* HI */
438 COSTS_N_INSNS (18), /* SI */
439 COSTS_N_INSNS (18), /* DI */
440 COSTS_N_INSNS (18)}, /* other */
441 COSTS_N_INSNS (2), /* cost of movsx */
442 COSTS_N_INSNS (2), /* cost of movzx */
443 8, /* "large" insn */
445 3, /* cost for loading QImode using movzbl */
446 {4, 5, 4}, /* cost of loading integer registers
447 in QImode, HImode and SImode.
448 Relative to reg-reg move (2). */
449 {2, 3, 2}, /* cost of storing integer registers */
450 4, /* cost of reg,reg fld/fst */
451 {6, 6, 6}, /* cost of loading fp registers
452 in SFmode, DFmode and XFmode */
453 {4, 4, 4}, /* cost of storing fp registers
454 in SFmode, DFmode and XFmode */
455 2, /* cost of moving MMX register */
456 {2, 2}, /* cost of loading MMX registers
457 in SImode and DImode */
458 {2, 2}, /* cost of storing MMX registers
459 in SImode and DImode */
460 2, /* cost of moving SSE register */
461 {2, 2, 8}, /* cost of loading SSE registers
462 in SImode, DImode and TImode */
463 {2, 2, 8}, /* cost of storing SSE registers
464 in SImode, DImode and TImode */
465 6, /* MMX or SSE register to integer */
466 32, /* size of prefetch block */
467 1, /* number of parallel prefetches */
469 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
470 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
471 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
472 COSTS_N_INSNS (2), /* cost of FABS instruction. */
473 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
474 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
475 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
476 DUMMY_STRINGOP_ALGS},
477 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
482 struct processor_costs athlon_cost = {
483 COSTS_N_INSNS (1), /* cost of an add instruction */
484 COSTS_N_INSNS (2), /* cost of a lea instruction */
485 COSTS_N_INSNS (1), /* variable shift costs */
486 COSTS_N_INSNS (1), /* constant shift costs */
487 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
488 COSTS_N_INSNS (5), /* HI */
489 COSTS_N_INSNS (5), /* SI */
490 COSTS_N_INSNS (5), /* DI */
491 COSTS_N_INSNS (5)}, /* other */
492 0, /* cost of multiply per each bit set */
493 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
494 COSTS_N_INSNS (26), /* HI */
495 COSTS_N_INSNS (42), /* SI */
496 COSTS_N_INSNS (74), /* DI */
497 COSTS_N_INSNS (74)}, /* other */
498 COSTS_N_INSNS (1), /* cost of movsx */
499 COSTS_N_INSNS (1), /* cost of movzx */
500 8, /* "large" insn */
502 4, /* cost for loading QImode using movzbl */
503 {3, 4, 3}, /* cost of loading integer registers
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
506 {3, 4, 3}, /* cost of storing integer registers */
507 4, /* cost of reg,reg fld/fst */
508 {4, 4, 12}, /* cost of loading fp registers
509 in SFmode, DFmode and XFmode */
510 {6, 6, 8}, /* cost of storing fp registers
511 in SFmode, DFmode and XFmode */
512 2, /* cost of moving MMX register */
513 {4, 4}, /* cost of loading MMX registers
514 in SImode and DImode */
515 {4, 4}, /* cost of storing MMX registers
516 in SImode and DImode */
517 2, /* cost of moving SSE register */
518 {4, 4, 6}, /* cost of loading SSE registers
519 in SImode, DImode and TImode */
520 {4, 4, 5}, /* cost of storing SSE registers
521 in SImode, DImode and TImode */
522 5, /* MMX or SSE register to integer */
523 64, /* size of prefetch block */
524 6, /* number of parallel prefetches */
526 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
527 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
528 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
529 COSTS_N_INSNS (2), /* cost of FABS instruction. */
530 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
531 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
532 /* For some reason, Athlon deals better with REP prefix (relative to loops)
533 compared to K8. Alignment becomes important after 8 bytes for memcpy and
534 128 bytes for memset. */
535 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
536 DUMMY_STRINGOP_ALGS},
537 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
542 struct processor_costs k8_cost = {
543 COSTS_N_INSNS (1), /* cost of an add instruction */
544 COSTS_N_INSNS (2), /* cost of a lea instruction */
545 COSTS_N_INSNS (1), /* variable shift costs */
546 COSTS_N_INSNS (1), /* constant shift costs */
547 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
548 COSTS_N_INSNS (4), /* HI */
549 COSTS_N_INSNS (3), /* SI */
550 COSTS_N_INSNS (4), /* DI */
551 COSTS_N_INSNS (5)}, /* other */
552 0, /* cost of multiply per each bit set */
553 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
554 COSTS_N_INSNS (26), /* HI */
555 COSTS_N_INSNS (42), /* SI */
556 COSTS_N_INSNS (74), /* DI */
557 COSTS_N_INSNS (74)}, /* other */
558 COSTS_N_INSNS (1), /* cost of movsx */
559 COSTS_N_INSNS (1), /* cost of movzx */
560 8, /* "large" insn */
562 4, /* cost for loading QImode using movzbl */
563 {3, 4, 3}, /* cost of loading integer registers
564 in QImode, HImode and SImode.
565 Relative to reg-reg move (2). */
566 {3, 4, 3}, /* cost of storing integer registers */
567 4, /* cost of reg,reg fld/fst */
568 {4, 4, 12}, /* cost of loading fp registers
569 in SFmode, DFmode and XFmode */
570 {6, 6, 8}, /* cost of storing fp registers
571 in SFmode, DFmode and XFmode */
572 2, /* cost of moving MMX register */
573 {3, 3}, /* cost of loading MMX registers
574 in SImode and DImode */
575 {4, 4}, /* cost of storing MMX registers
576 in SImode and DImode */
577 2, /* cost of moving SSE register */
578 {4, 3, 6}, /* cost of loading SSE registers
579 in SImode, DImode and TImode */
580 {4, 4, 5}, /* cost of storing SSE registers
581 in SImode, DImode and TImode */
582 5, /* MMX or SSE register to integer */
583 64, /* size of prefetch block */
584 /* New AMD processors never drop prefetches; if they cannot be performed
585 immediately, they are queued. We set number of simultaneous prefetches
586 to a large constant to reflect this (it probably is not a good idea not
587 to limit number of prefetches at all, as their execution also takes some
589 100, /* number of parallel prefetches */
591 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
592 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
593 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
594 COSTS_N_INSNS (2), /* cost of FABS instruction. */
595 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
596 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
597 /* K8 has optimized REP instruction for medium sized blocks, but for very small
598 blocks it is better to use loop. For large blocks, libcall can do
599 nontemporary accesses and beat inline considerably. */
600 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
601 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
602 {{libcall, {{8, loop}, {24, unrolled_loop},
603 {2048, rep_prefix_4_byte}, {-1, libcall}}},
604 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
607 struct processor_costs amdfam10_cost = {
608 COSTS_N_INSNS (1), /* cost of an add instruction */
609 COSTS_N_INSNS (2), /* cost of a lea instruction */
610 COSTS_N_INSNS (1), /* variable shift costs */
611 COSTS_N_INSNS (1), /* constant shift costs */
612 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
613 COSTS_N_INSNS (4), /* HI */
614 COSTS_N_INSNS (3), /* SI */
615 COSTS_N_INSNS (4), /* DI */
616 COSTS_N_INSNS (5)}, /* other */
617 0, /* cost of multiply per each bit set */
618 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
619 COSTS_N_INSNS (35), /* HI */
620 COSTS_N_INSNS (51), /* SI */
621 COSTS_N_INSNS (83), /* DI */
622 COSTS_N_INSNS (83)}, /* other */
623 COSTS_N_INSNS (1), /* cost of movsx */
624 COSTS_N_INSNS (1), /* cost of movzx */
625 8, /* "large" insn */
627 4, /* cost for loading QImode using movzbl */
628 {3, 4, 3}, /* cost of loading integer registers
629 in QImode, HImode and SImode.
630 Relative to reg-reg move (2). */
631 {3, 4, 3}, /* cost of storing integer registers */
632 4, /* cost of reg,reg fld/fst */
633 {4, 4, 12}, /* cost of loading fp registers
634 in SFmode, DFmode and XFmode */
635 {6, 6, 8}, /* cost of storing fp registers
636 in SFmode, DFmode and XFmode */
637 2, /* cost of moving MMX register */
638 {3, 3}, /* cost of loading MMX registers
639 in SImode and DImode */
640 {4, 4}, /* cost of storing MMX registers
641 in SImode and DImode */
642 2, /* cost of moving SSE register */
643 {4, 4, 3}, /* cost of loading SSE registers
644 in SImode, DImode and TImode */
645 {4, 4, 5}, /* cost of storing SSE registers
646 in SImode, DImode and TImode */
647 3, /* MMX or SSE register to integer */
649 MOVD reg64, xmmreg Double FSTORE 4
650 MOVD reg32, xmmreg Double FSTORE 4
652 MOVD reg64, xmmreg Double FADD 3
654 MOVD reg32, xmmreg Double FADD 3
656 64, /* size of prefetch block */
657 /* New AMD processors never drop prefetches; if they cannot be performed
658 immediately, they are queued. We set number of simultaneous prefetches
659 to a large constant to reflect this (it probably is not a good idea not
660 to limit number of prefetches at all, as their execution also takes some
662 100, /* number of parallel prefetches */
664 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
665 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
666 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
667 COSTS_N_INSNS (2), /* cost of FABS instruction. */
668 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
669 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
671 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
672 very small blocks it is better to use loop. For large blocks, libcall can
673 do nontemporary accesses and beat inline considerably. */
674 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
675 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
676 {{libcall, {{8, loop}, {24, unrolled_loop},
677 {2048, rep_prefix_4_byte}, {-1, libcall}}},
678 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
682 struct processor_costs pentium4_cost = {
683 COSTS_N_INSNS (1), /* cost of an add instruction */
684 COSTS_N_INSNS (3), /* cost of a lea instruction */
685 COSTS_N_INSNS (4), /* variable shift costs */
686 COSTS_N_INSNS (4), /* constant shift costs */
687 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
688 COSTS_N_INSNS (15), /* HI */
689 COSTS_N_INSNS (15), /* SI */
690 COSTS_N_INSNS (15), /* DI */
691 COSTS_N_INSNS (15)}, /* other */
692 0, /* cost of multiply per each bit set */
693 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
694 COSTS_N_INSNS (56), /* HI */
695 COSTS_N_INSNS (56), /* SI */
696 COSTS_N_INSNS (56), /* DI */
697 COSTS_N_INSNS (56)}, /* other */
698 COSTS_N_INSNS (1), /* cost of movsx */
699 COSTS_N_INSNS (1), /* cost of movzx */
700 16, /* "large" insn */
702 2, /* cost for loading QImode using movzbl */
703 {4, 5, 4}, /* cost of loading integer registers
704 in QImode, HImode and SImode.
705 Relative to reg-reg move (2). */
706 {2, 3, 2}, /* cost of storing integer registers */
707 2, /* cost of reg,reg fld/fst */
708 {2, 2, 6}, /* cost of loading fp registers
709 in SFmode, DFmode and XFmode */
710 {4, 4, 6}, /* cost of storing fp registers
711 in SFmode, DFmode and XFmode */
712 2, /* cost of moving MMX register */
713 {2, 2}, /* cost of loading MMX registers
714 in SImode and DImode */
715 {2, 2}, /* cost of storing MMX registers
716 in SImode and DImode */
717 12, /* cost of moving SSE register */
718 {12, 12, 12}, /* cost of loading SSE registers
719 in SImode, DImode and TImode */
720 {2, 2, 8}, /* cost of storing SSE registers
721 in SImode, DImode and TImode */
722 10, /* MMX or SSE register to integer */
723 64, /* size of prefetch block */
724 6, /* number of parallel prefetches */
726 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
727 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
728 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
729 COSTS_N_INSNS (2), /* cost of FABS instruction. */
730 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
731 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
732 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
733 DUMMY_STRINGOP_ALGS},
734 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
736 DUMMY_STRINGOP_ALGS},
740 struct processor_costs nocona_cost = {
741 COSTS_N_INSNS (1), /* cost of an add instruction */
742 COSTS_N_INSNS (1), /* cost of a lea instruction */
743 COSTS_N_INSNS (1), /* variable shift costs */
744 COSTS_N_INSNS (1), /* constant shift costs */
745 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
746 COSTS_N_INSNS (10), /* HI */
747 COSTS_N_INSNS (10), /* SI */
748 COSTS_N_INSNS (10), /* DI */
749 COSTS_N_INSNS (10)}, /* other */
750 0, /* cost of multiply per each bit set */
751 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
752 COSTS_N_INSNS (66), /* HI */
753 COSTS_N_INSNS (66), /* SI */
754 COSTS_N_INSNS (66), /* DI */
755 COSTS_N_INSNS (66)}, /* other */
756 COSTS_N_INSNS (1), /* cost of movsx */
757 COSTS_N_INSNS (1), /* cost of movzx */
758 16, /* "large" insn */
760 4, /* cost for loading QImode using movzbl */
761 {4, 4, 4}, /* cost of loading integer registers
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
764 {4, 4, 4}, /* cost of storing integer registers */
765 3, /* cost of reg,reg fld/fst */
766 {12, 12, 12}, /* cost of loading fp registers
767 in SFmode, DFmode and XFmode */
768 {4, 4, 4}, /* cost of storing fp registers
769 in SFmode, DFmode and XFmode */
770 6, /* cost of moving MMX register */
771 {12, 12}, /* cost of loading MMX registers
772 in SImode and DImode */
773 {12, 12}, /* cost of storing MMX registers
774 in SImode and DImode */
775 6, /* cost of moving SSE register */
776 {12, 12, 12}, /* cost of loading SSE registers
777 in SImode, DImode and TImode */
778 {12, 12, 12}, /* cost of storing SSE registers
779 in SImode, DImode and TImode */
780 8, /* MMX or SSE register to integer */
781 128, /* size of prefetch block */
782 8, /* number of parallel prefetches */
784 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
785 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
786 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
787 COSTS_N_INSNS (3), /* cost of FABS instruction. */
788 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
789 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
790 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
791 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
792 {100000, unrolled_loop}, {-1, libcall}}}},
793 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
795 {libcall, {{24, loop}, {64, unrolled_loop},
796 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
800 struct processor_costs core2_cost = {
801 COSTS_N_INSNS (1), /* cost of an add instruction */
802 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
803 COSTS_N_INSNS (1), /* variable shift costs */
804 COSTS_N_INSNS (1), /* constant shift costs */
805 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
806 COSTS_N_INSNS (3), /* HI */
807 COSTS_N_INSNS (3), /* SI */
808 COSTS_N_INSNS (3), /* DI */
809 COSTS_N_INSNS (3)}, /* other */
810 0, /* cost of multiply per each bit set */
811 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
812 COSTS_N_INSNS (22), /* HI */
813 COSTS_N_INSNS (22), /* SI */
814 COSTS_N_INSNS (22), /* DI */
815 COSTS_N_INSNS (22)}, /* other */
816 COSTS_N_INSNS (1), /* cost of movsx */
817 COSTS_N_INSNS (1), /* cost of movzx */
818 8, /* "large" insn */
820 2, /* cost for loading QImode using movzbl */
821 {6, 6, 6}, /* cost of loading integer registers
822 in QImode, HImode and SImode.
823 Relative to reg-reg move (2). */
824 {4, 4, 4}, /* cost of storing integer registers */
825 2, /* cost of reg,reg fld/fst */
826 {6, 6, 6}, /* cost of loading fp registers
827 in SFmode, DFmode and XFmode */
828 {4, 4, 4}, /* cost of loading integer registers */
829 2, /* cost of moving MMX register */
830 {6, 6}, /* cost of loading MMX registers
831 in SImode and DImode */
832 {4, 4}, /* cost of storing MMX registers
833 in SImode and DImode */
834 2, /* cost of moving SSE register */
835 {6, 6, 6}, /* cost of loading SSE registers
836 in SImode, DImode and TImode */
837 {4, 4, 4}, /* cost of storing SSE registers
838 in SImode, DImode and TImode */
839 2, /* MMX or SSE register to integer */
840 128, /* size of prefetch block */
841 8, /* number of parallel prefetches */
843 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
844 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
845 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
846 COSTS_N_INSNS (1), /* cost of FABS instruction. */
847 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
848 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
849 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
850 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
851 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
852 {{libcall, {{8, loop}, {15, unrolled_loop},
853 {2048, rep_prefix_4_byte}, {-1, libcall}}},
854 {libcall, {{24, loop}, {32, unrolled_loop},
855 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
858 /* Generic64 should produce code tuned for Nocona and K8. */
860 struct processor_costs generic64_cost = {
861 COSTS_N_INSNS (1), /* cost of an add instruction */
862 /* On all chips taken into consideration lea is 2 cycles and more. With
863 this cost however our current implementation of synth_mult results in
864 use of unnecessary temporary registers causing regression on several
865 SPECfp benchmarks. */
866 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
867 COSTS_N_INSNS (1), /* variable shift costs */
868 COSTS_N_INSNS (1), /* constant shift costs */
869 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
870 COSTS_N_INSNS (4), /* HI */
871 COSTS_N_INSNS (3), /* SI */
872 COSTS_N_INSNS (4), /* DI */
873 COSTS_N_INSNS (2)}, /* other */
874 0, /* cost of multiply per each bit set */
875 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
876 COSTS_N_INSNS (26), /* HI */
877 COSTS_N_INSNS (42), /* SI */
878 COSTS_N_INSNS (74), /* DI */
879 COSTS_N_INSNS (74)}, /* other */
880 COSTS_N_INSNS (1), /* cost of movsx */
881 COSTS_N_INSNS (1), /* cost of movzx */
882 8, /* "large" insn */
884 4, /* cost for loading QImode using movzbl */
885 {4, 4, 4}, /* cost of loading integer registers
886 in QImode, HImode and SImode.
887 Relative to reg-reg move (2). */
888 {4, 4, 4}, /* cost of storing integer registers */
889 4, /* cost of reg,reg fld/fst */
890 {12, 12, 12}, /* cost of loading fp registers
891 in SFmode, DFmode and XFmode */
892 {6, 6, 8}, /* cost of storing fp registers
893 in SFmode, DFmode and XFmode */
894 2, /* cost of moving MMX register */
895 {8, 8}, /* cost of loading MMX registers
896 in SImode and DImode */
897 {8, 8}, /* cost of storing MMX registers
898 in SImode and DImode */
899 2, /* cost of moving SSE register */
900 {8, 8, 8}, /* cost of loading SSE registers
901 in SImode, DImode and TImode */
902 {8, 8, 8}, /* cost of storing SSE registers
903 in SImode, DImode and TImode */
904 5, /* MMX or SSE register to integer */
905 64, /* size of prefetch block */
906 6, /* number of parallel prefetches */
907 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
908 is increased to perhaps more appropriate value of 5. */
910 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
911 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
912 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
913 COSTS_N_INSNS (8), /* cost of FABS instruction. */
914 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
915 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
916 {DUMMY_STRINGOP_ALGS,
917 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
918 {DUMMY_STRINGOP_ALGS,
919 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
922 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
924 struct processor_costs generic32_cost = {
925 COSTS_N_INSNS (1), /* cost of an add instruction */
926 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
927 COSTS_N_INSNS (1), /* variable shift costs */
928 COSTS_N_INSNS (1), /* constant shift costs */
929 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
930 COSTS_N_INSNS (4), /* HI */
931 COSTS_N_INSNS (3), /* SI */
932 COSTS_N_INSNS (4), /* DI */
933 COSTS_N_INSNS (2)}, /* other */
934 0, /* cost of multiply per each bit set */
935 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
936 COSTS_N_INSNS (26), /* HI */
937 COSTS_N_INSNS (42), /* SI */
938 COSTS_N_INSNS (74), /* DI */
939 COSTS_N_INSNS (74)}, /* other */
940 COSTS_N_INSNS (1), /* cost of movsx */
941 COSTS_N_INSNS (1), /* cost of movzx */
942 8, /* "large" insn */
944 4, /* cost for loading QImode using movzbl */
945 {4, 4, 4}, /* cost of loading integer registers
946 in QImode, HImode and SImode.
947 Relative to reg-reg move (2). */
948 {4, 4, 4}, /* cost of storing integer registers */
949 4, /* cost of reg,reg fld/fst */
950 {12, 12, 12}, /* cost of loading fp registers
951 in SFmode, DFmode and XFmode */
952 {6, 6, 8}, /* cost of storing fp registers
953 in SFmode, DFmode and XFmode */
954 2, /* cost of moving MMX register */
955 {8, 8}, /* cost of loading MMX registers
956 in SImode and DImode */
957 {8, 8}, /* cost of storing MMX registers
958 in SImode and DImode */
959 2, /* cost of moving SSE register */
960 {8, 8, 8}, /* cost of loading SSE registers
961 in SImode, DImode and TImode */
962 {8, 8, 8}, /* cost of storing SSE registers
963 in SImode, DImode and TImode */
964 5, /* MMX or SSE register to integer */
965 64, /* size of prefetch block */
966 6, /* number of parallel prefetches */
968 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
969 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
970 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
971 COSTS_N_INSNS (8), /* cost of FABS instruction. */
972 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
973 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
974 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
975 DUMMY_STRINGOP_ALGS},
976 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
977 DUMMY_STRINGOP_ALGS},
980 const struct processor_costs *ix86_cost = &pentium_cost;
982 /* Processor feature/optimization bitmasks. */
983 #define m_386 (1<<PROCESSOR_I386)
984 #define m_486 (1<<PROCESSOR_I486)
985 #define m_PENT (1<<PROCESSOR_PENTIUM)
986 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
987 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
988 #define m_NOCONA (1<<PROCESSOR_NOCONA)
989 #define m_CORE2 (1<<PROCESSOR_CORE2)
991 #define m_GEODE (1<<PROCESSOR_GEODE)
992 #define m_K6 (1<<PROCESSOR_K6)
993 #define m_K6_GEODE (m_K6 | m_GEODE)
994 #define m_K8 (1<<PROCESSOR_K8)
995 #define m_ATHLON (1<<PROCESSOR_ATHLON)
996 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
997 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
998 #define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
1000 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1001 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1003 /* Generic instruction choice should be common subset of supported CPUs
1004 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1005 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1007 /* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
1008 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
1009 generic because it is not working well with PPro base chips. */
1010 const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_CORE2
1012 const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4
1013 | m_NOCONA | m_CORE2 | m_GENERIC;
1014 const int x86_zero_extend_with_and = m_486 | m_PENT;
1015 /* Enable to zero extend integer registers to avoid partial dependencies */
1016 const int x86_movx = m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA
1017 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
1018 const int x86_double_with_add = ~m_386;
1019 const int x86_use_bit_test = m_386;
1020 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8_AMDFAM10
1021 | m_K6 | m_CORE2 | m_GENERIC;
1022 const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4
1024 const int x86_3dnow_a = m_ATHLON_K8_AMDFAM10;
1025 const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8_AMDFAM10
1026 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
1027 /* Branch hints were put in P4 based on simulation result. But
1028 after P4 was made, no performance benefit was observed with
1029 branch hints. It also increases the code size. As the result,
1030 icc never generates branch hints. */
1031 const int x86_branch_hints = 0;
1032 const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32;
1033 /*m_GENERIC | m_ATHLON_K8 ? */
1034 /* We probably ought to watch for partial register stalls on Generic32
1035 compilation setting as well. However in current implementation the
1036 partial register stalls are not eliminated very well - they can
1037 be introduced via subregs synthesized by combine and can happen
1038 in caller/callee saving sequences.
1039 Because this option pays back little on PPro based chips and is in conflict
1040 with partial reg. dependencies used by Athlon/P4 based chips, it is better
1041 to leave it off for generic32 for now. */
1042 const int x86_partial_reg_stall = m_PPRO;
1043 const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
1044 const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
1045 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT
1046 | m_CORE2 | m_GENERIC);
1047 const int x86_use_mov0 = m_K6;
1048 const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
1049 /* Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1050 const int x86_use_xchgb = m_PENT4;
1051 const int x86_read_modify_write = ~m_PENT;
1052 const int x86_read_modify = ~(m_PENT | m_PPRO);
1053 const int x86_split_long_moves = m_PPRO;
1054 const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486
1055 | m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC;
1057 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
1058 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
1059 const int x86_qimode_math = ~(0);
1060 const int x86_promote_qi_regs = 0;
1061 /* On PPro this flag is meant to avoid partial register stalls. Just like
1062 the x86_partial_reg_stall this option might be considered for Generic32
1063 if our scheme for avoiding partial stalls was more effective. */
1064 const int x86_himode_math = ~(m_PPRO);
1065 const int x86_promote_hi_regs = m_PPRO;
1066 /* Enable if add/sub rsp is preferred over 1 or 2 push/pop */
1067 const int x86_sub_esp_4 = m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA
1068 | m_CORE2 | m_GENERIC;
1069 const int x86_sub_esp_8 = m_ATHLON_K8_AMDFAM10 | m_PPRO | m_386 | m_486
1070 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
1071 const int x86_add_esp_4 = m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT4 | m_NOCONA
1072 | m_CORE2 | m_GENERIC;
1073 const int x86_add_esp_8 = m_ATHLON_K8_AMDFAM10 | m_PPRO | m_K6_GEODE | m_386
1074 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
1075 /* Enable if integer moves are preferred for DFmode copies */
1076 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA
1077 | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
1078 const int x86_partial_reg_dependency = m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA
1079 | m_CORE2 | m_GENERIC;
1080 const int x86_memory_mismatch_stall = m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA
1081 | m_CORE2 | m_GENERIC;
1082 /* If ACCUMULATE_OUTGOING_ARGS is enabled, the maximum amount of space required
1083 for outgoing arguments will be computed and placed into the variable
1084 `current_function_outgoing_args_size'. No space will be pushed onto the stack
1085 for each call; instead, the function prologue should increase the stack frame
1086 size by this amount. Setting both PUSH_ARGS and ACCUMULATE_OUTGOING_ARGS is
1088 const int x86_accumulate_outgoing_args = m_ATHLON_K8_AMDFAM10 | m_PENT4
1089 | m_NOCONA | m_PPRO | m_CORE2
1091 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
1092 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
1093 const int x86_shift1 = ~m_486;
1094 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO
1095 | m_ATHLON_K8_AMDFAM10 | m_PENT4
1096 | m_NOCONA | m_CORE2 | m_GENERIC;
1097 /* In Generic model we have an conflict here in between PPro/Pentium4 based chips
1098 that thread 128bit SSE registers as single units versus K8 based chips that
1099 divide SSE registers to two 64bit halves.
1100 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
1101 to allow register renaming on 128bit SSE units, but usually results in one
1102 extra microop on 64bit SSE units. Experimental results shows that disabling
1103 this option on P4 brings over 20% SPECfp regression, while enabling it on
1104 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
1106 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1107 | m_GENERIC | m_AMDFAM10;
1108 /* Set for machines where the type and dependencies are resolved on SSE
1109 register parts instead of whole registers, so we may maintain just
1110 lower part of scalar values in proper format leaving the upper part
1112 const int x86_sse_split_regs = m_ATHLON_K8;
1113 /* Code generation for scalar reg-reg moves of single and double precision data:
1114 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
1118 if (x86_sse_partial_reg_dependency == true)
1123 Code generation for scalar loads of double precision data:
1124 if (x86_sse_split_regs == true)
1125 movlpd mem, reg (gas syntax)
1129 Code generation for unaligned packed loads of single precision data
1130 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
1131 if (x86_sse_unaligned_move_optimal)
1134 if (x86_sse_partial_reg_dependency == true)
1146 Code generation for unaligned packed loads of double precision data
1147 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
1148 if (x86_sse_unaligned_move_optimal)
1151 if (x86_sse_split_regs == true)
1162 const int x86_sse_unaligned_move_optimal = m_AMDFAM10;
1163 const int x86_sse_typeless_stores = m_ATHLON_K8_AMDFAM10;
1164 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
1165 const int x86_use_ffreep = m_ATHLON_K8_AMDFAM10;
1166 const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
1168 const int x86_inter_unit_moves = ~(m_ATHLON_K8_AMDFAM10 | m_GENERIC);
1170 const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON_K8 | m_PENT4
1171 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1172 /* Some CPU cores are not able to predict more than 4 branch instructions in
1173 the 16 byte window. */
1174 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT4
1175 | m_NOCONA | m_CORE2 | m_GENERIC;
1176 const int x86_schedule = m_PPRO | m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT
1177 | m_CORE2 | m_GENERIC;
1178 const int x86_use_bt = m_ATHLON_K8_AMDFAM10;
1179 /* Compare and exchange was added for 80486. */
1180 const int x86_cmpxchg = ~m_386;
1181 /* Compare and exchange 8 bytes was added for pentium. */
1182 const int x86_cmpxchg8b = ~(m_386 | m_486);
1183 /* Exchange and add was added for 80486. */
1184 const int x86_xadd = ~m_386;
1185 /* Byteswap was added for 80486. */
1186 const int x86_bswap = ~m_386;
1187 const int x86_pad_returns = m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC;
1189 static enum stringop_alg stringop_alg = no_stringop;
1191 /* In case the average insn count for single function invocation is
1192 lower than this constant, emit fast (but longer) prologue and
1194 #define FAST_PROLOGUE_INSN_COUNT 20
1196 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1197 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1198 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1199 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1201 /* Array of the smallest class containing reg number REGNO, indexed by
1202 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1204 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1206 /* ax, dx, cx, bx */
1207 AREG, DREG, CREG, BREG,
1208 /* si, di, bp, sp */
1209 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1211 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1212 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1215 /* flags, fpsr, fpcr, frame */
1216 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1217 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1219 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1221 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1222 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1223 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1227 /* The "default" register map used in 32bit mode. */
1229 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1231 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1232 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1233 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1234 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1235 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1236 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1237 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1240 static int const x86_64_int_parameter_registers[6] =
1242 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1243 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1246 static int const x86_64_int_return_registers[4] =
1248 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
1251 /* The "default" register map used in 64bit mode. */
1252 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1254 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1255 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1256 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1257 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1258 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1259 8,9,10,11,12,13,14,15, /* extended integer registers */
1260 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1263 /* Define the register numbers to be used in Dwarf debugging information.
1264 The SVR4 reference port C compiler uses the following register numbers
1265 in its Dwarf output code:
1266 0 for %eax (gcc regno = 0)
1267 1 for %ecx (gcc regno = 2)
1268 2 for %edx (gcc regno = 1)
1269 3 for %ebx (gcc regno = 3)
1270 4 for %esp (gcc regno = 7)
1271 5 for %ebp (gcc regno = 6)
1272 6 for %esi (gcc regno = 4)
1273 7 for %edi (gcc regno = 5)
1274 The following three DWARF register numbers are never generated by
1275 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1276 believes these numbers have these meanings.
1277 8 for %eip (no gcc equivalent)
1278 9 for %eflags (gcc regno = 17)
1279 10 for %trapno (no gcc equivalent)
1280 It is not at all clear how we should number the FP stack registers
1281 for the x86 architecture. If the version of SDB on x86/svr4 were
1282 a bit less brain dead with respect to floating-point then we would
1283 have a precedent to follow with respect to DWARF register numbers
1284 for x86 FP registers, but the SDB on x86/svr4 is so completely
1285 broken with respect to FP registers that it is hardly worth thinking
1286 of it as something to strive for compatibility with.
1287 The version of x86/svr4 SDB I have at the moment does (partially)
1288 seem to believe that DWARF register number 11 is associated with
1289 the x86 register %st(0), but that's about all. Higher DWARF
1290 register numbers don't seem to be associated with anything in
1291 particular, and even for DWARF regno 11, SDB only seems to under-
1292 stand that it should say that a variable lives in %st(0) (when
1293 asked via an `=' command) if we said it was in DWARF regno 11,
1294 but SDB still prints garbage when asked for the value of the
1295 variable in question (via a `/' command).
1296 (Also note that the labels SDB prints for various FP stack regs
1297 when doing an `x' command are all wrong.)
1298 Note that these problems generally don't affect the native SVR4
1299 C compiler because it doesn't allow the use of -O with -g and
1300 because when it is *not* optimizing, it allocates a memory
1301 location for each floating-point variable, and the memory
1302 location is what gets described in the DWARF AT_location
1303 attribute for the variable in question.
1304 Regardless of the severe mental illness of the x86/svr4 SDB, we
1305 do something sensible here and we use the following DWARF
1306 register numbers. Note that these are all stack-top-relative
1308 11 for %st(0) (gcc regno = 8)
1309 12 for %st(1) (gcc regno = 9)
1310 13 for %st(2) (gcc regno = 10)
1311 14 for %st(3) (gcc regno = 11)
1312 15 for %st(4) (gcc regno = 12)
1313 16 for %st(5) (gcc regno = 13)
1314 17 for %st(6) (gcc regno = 14)
1315 18 for %st(7) (gcc regno = 15)
1317 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1319 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1320 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1321 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1322 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1323 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1324 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1325 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1328 /* Test and compare insns in i386.md store the information needed to
1329 generate branch and scc insns here. */
1331 rtx ix86_compare_op0 = NULL_RTX;
1332 rtx ix86_compare_op1 = NULL_RTX;
1333 rtx ix86_compare_emitted = NULL_RTX;
1335 /* Size of the register save area. */
1336 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1338 /* Define the structure for the machine field in struct function. */
1340 struct stack_local_entry GTY(())
1342 unsigned short mode;
1345 struct stack_local_entry *next;
1348 /* Structure describing stack frame layout.
1349 Stack grows downward:
1355 saved frame pointer if frame_pointer_needed
1356 <- HARD_FRAME_POINTER
1361 [va_arg registers] (
1362 > to_allocate <- FRAME_POINTER
1372 HOST_WIDE_INT frame;
1374 int outgoing_arguments_size;
1377 HOST_WIDE_INT to_allocate;
1378 /* The offsets relative to ARG_POINTER. */
1379 HOST_WIDE_INT frame_pointer_offset;
1380 HOST_WIDE_INT hard_frame_pointer_offset;
1381 HOST_WIDE_INT stack_pointer_offset;
1383 /* When save_regs_using_mov is set, emit prologue using
1384 move instead of push instructions. */
1385 bool save_regs_using_mov;
1388 /* Code model option. */
1389 enum cmodel ix86_cmodel;
1391 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1393 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1395 /* Which unit we are generating floating point math for. */
1396 enum fpmath_unit ix86_fpmath;
1398 /* Which cpu are we scheduling for. */
1399 enum processor_type ix86_tune;
1402 /* Which instruction set architecture to use. */
1403 enum processor_type ix86_arch;
1406 /* true if sse prefetch instruction is not NOOP. */
1407 int x86_prefetch_sse;
1409 /* true if cmpxchg16b is supported. */
1412 /* ix86_regparm_string as a number */
1413 static int ix86_regparm;
1415 /* -mstackrealign option */
1416 extern int ix86_force_align_arg_pointer;
1417 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1419 /* Preferred alignment for stack boundary in bits. */
1420 unsigned int ix86_preferred_stack_boundary;
1422 /* Values 1-5: see jump.c */
1423 int ix86_branch_cost;
1425 /* Variables which are this size or smaller are put in the data/bss
1426 or ldata/lbss sections. */
1428 int ix86_section_threshold = 65536;
1430 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1431 char internal_label_prefix[16];
1432 int internal_label_prefix_len;
1434 static bool ix86_handle_option (size_t, const char *, int);
1435 static void output_pic_addr_const (FILE *, rtx, int);
1436 static void put_condition_code (enum rtx_code, enum machine_mode,
1438 static const char *get_some_local_dynamic_name (void);
1439 static int get_some_local_dynamic_name_1 (rtx *, void *);
1440 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
1441 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
1443 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
1444 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
1446 static rtx get_thread_pointer (int);
1447 static rtx legitimize_tls_address (rtx, enum tls_model, int);
1448 static void get_pc_thunk_name (char [32], unsigned int);
1449 static rtx gen_push (rtx);
1450 static int ix86_flags_dependent (rtx, rtx, enum attr_type);
1451 static int ix86_agi_dependent (rtx, rtx, enum attr_type);
1452 static struct machine_function * ix86_init_machine_status (void);
1453 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
1454 static int ix86_nsaved_regs (void);
1455 static void ix86_emit_save_regs (void);
1456 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
1457 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
1458 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
1459 static HOST_WIDE_INT ix86_GOT_alias_set (void);
1460 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
1461 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
1462 static int ix86_issue_rate (void);
1463 static int ix86_adjust_cost (rtx, rtx, rtx, int);
1464 static int ia32_multipass_dfa_lookahead (void);
1465 static void ix86_init_mmx_sse_builtins (void);
1466 static rtx x86_this_parameter (tree);
1467 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
1468 HOST_WIDE_INT, tree);
1469 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
1470 static void x86_file_start (void);
1471 static void ix86_reorg (void);
1472 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
1473 static tree ix86_build_builtin_va_list (void);
1474 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
1476 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
1477 static bool ix86_scalar_mode_supported_p (enum machine_mode);
1478 static bool ix86_vector_mode_supported_p (enum machine_mode);
1480 static int ix86_address_cost (rtx);
1481 static bool ix86_cannot_force_const_mem (rtx);
1482 static rtx ix86_delegitimize_address (rtx);
1484 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1486 struct builtin_description;
1487 static rtx ix86_expand_sse_comi (const struct builtin_description *,
1489 static rtx ix86_expand_sse_compare (const struct builtin_description *,
1491 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
1492 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
1493 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
1494 static rtx ix86_expand_store_builtin (enum insn_code, tree);
1495 static rtx safe_vector_operand (rtx, enum machine_mode);
1496 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
1497 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
1498 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
1499 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
1500 static int ix86_fp_comparison_cost (enum rtx_code code);
1501 static unsigned int ix86_select_alt_pic_regnum (void);
1502 static int ix86_save_reg (unsigned int, int);
1503 static void ix86_compute_frame_layout (struct ix86_frame *);
1504 static int ix86_comp_type_attributes (tree, tree);
1505 static int ix86_function_regparm (tree, tree);
1506 const struct attribute_spec ix86_attribute_table[];
1507 static bool ix86_function_ok_for_sibcall (tree, tree);
1508 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
1509 static int ix86_value_regno (enum machine_mode, tree, tree);
1510 static bool contains_128bit_aligned_vector_p (tree);
1511 static rtx ix86_struct_value_rtx (tree, int);
1512 static bool ix86_ms_bitfield_layout_p (tree);
1513 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
1514 static int extended_reg_mentioned_1 (rtx *, void *);
1515 static bool ix86_rtx_costs (rtx, int, int, int *);
1516 static int min_insn_size (rtx);
1517 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
1518 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
1519 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
1521 static void ix86_init_builtins (void);
1522 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1523 static tree ix86_builtin_vectorized_function (enum built_in_function, tree, tree);
1524 static tree ix86_builtin_conversion (enum tree_code, tree);
1525 static const char *ix86_mangle_fundamental_type (tree);
1526 static tree ix86_stack_protect_fail (void);
1527 static rtx ix86_internal_arg_pointer (void);
1528 static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
1529 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1532 /* This function is only used on Solaris. */
1533 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
1536 /* Register class used for passing given 64bit part of the argument.
1537 These represent classes as documented by the PS ABI, with the exception
1538 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1539 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1541 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1542 whenever possible (upper half does contain padding).
1544 enum x86_64_reg_class
1547 X86_64_INTEGER_CLASS,
1548 X86_64_INTEGERSI_CLASS,
1555 X86_64_COMPLEX_X87_CLASS,
1558 static const char * const x86_64_reg_class_name[] = {
1559 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1560 "sseup", "x87", "x87up", "cplx87", "no"
1563 #define MAX_CLASSES 4
1565 /* Table of constants used by fldpi, fldln2, etc.... */
1566 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1567 static bool ext_80387_constants_init = 0;
1568 static void init_ext_80387_constants (void);
1569 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
1570 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
1571 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
1572 static section *x86_64_elf_select_section (tree decl, int reloc,
1573 unsigned HOST_WIDE_INT align)
1576 /* Initialize the GCC target structure. */
1577 #undef TARGET_ATTRIBUTE_TABLE
1578 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
1579 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1580 # undef TARGET_MERGE_DECL_ATTRIBUTES
1581 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
1584 #undef TARGET_COMP_TYPE_ATTRIBUTES
1585 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
1587 #undef TARGET_INIT_BUILTINS
1588 #define TARGET_INIT_BUILTINS ix86_init_builtins
1589 #undef TARGET_EXPAND_BUILTIN
1590 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
1592 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1593 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION ix86_builtin_vectorized_function
1594 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1595 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_builtin_conversion
1597 #undef TARGET_ASM_FUNCTION_EPILOGUE
1598 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
1600 #undef TARGET_ENCODE_SECTION_INFO
1601 #ifndef SUBTARGET_ENCODE_SECTION_INFO
1602 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
1604 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
1607 #undef TARGET_ASM_OPEN_PAREN
1608 #define TARGET_ASM_OPEN_PAREN ""
1609 #undef TARGET_ASM_CLOSE_PAREN
1610 #define TARGET_ASM_CLOSE_PAREN ""
1612 #undef TARGET_ASM_ALIGNED_HI_OP
1613 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
1614 #undef TARGET_ASM_ALIGNED_SI_OP
1615 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1617 #undef TARGET_ASM_ALIGNED_DI_OP
1618 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1621 #undef TARGET_ASM_UNALIGNED_HI_OP
1622 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1623 #undef TARGET_ASM_UNALIGNED_SI_OP
1624 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1625 #undef TARGET_ASM_UNALIGNED_DI_OP
1626 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1628 #undef TARGET_SCHED_ADJUST_COST
1629 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1630 #undef TARGET_SCHED_ISSUE_RATE
1631 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1632 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1633 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1634 ia32_multipass_dfa_lookahead
1636 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1637 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1640 #undef TARGET_HAVE_TLS
1641 #define TARGET_HAVE_TLS true
1643 #undef TARGET_CANNOT_FORCE_CONST_MEM
1644 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1645 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1646 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
1648 #undef TARGET_DELEGITIMIZE_ADDRESS
1649 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1651 #undef TARGET_MS_BITFIELD_LAYOUT_P
1652 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1655 #undef TARGET_BINDS_LOCAL_P
1656 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1659 #undef TARGET_ASM_OUTPUT_MI_THUNK
1660 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1661 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1662 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1664 #undef TARGET_ASM_FILE_START
1665 #define TARGET_ASM_FILE_START x86_file_start
1667 #undef TARGET_DEFAULT_TARGET_FLAGS
1668 #define TARGET_DEFAULT_TARGET_FLAGS \
1670 | TARGET_64BIT_DEFAULT \
1671 | TARGET_SUBTARGET_DEFAULT \
1672 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1674 #undef TARGET_HANDLE_OPTION
1675 #define TARGET_HANDLE_OPTION ix86_handle_option
1677 #undef TARGET_RTX_COSTS
1678 #define TARGET_RTX_COSTS ix86_rtx_costs
1679 #undef TARGET_ADDRESS_COST
1680 #define TARGET_ADDRESS_COST ix86_address_cost
1682 #undef TARGET_FIXED_CONDITION_CODE_REGS
1683 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1684 #undef TARGET_CC_MODES_COMPATIBLE
1685 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1687 #undef TARGET_MACHINE_DEPENDENT_REORG
1688 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1690 #undef TARGET_BUILD_BUILTIN_VA_LIST
1691 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1693 #undef TARGET_MD_ASM_CLOBBERS
1694 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1696 #undef TARGET_PROMOTE_PROTOTYPES
1697 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1698 #undef TARGET_STRUCT_VALUE_RTX
1699 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1700 #undef TARGET_SETUP_INCOMING_VARARGS
1701 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1702 #undef TARGET_MUST_PASS_IN_STACK
1703 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1704 #undef TARGET_PASS_BY_REFERENCE
1705 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1706 #undef TARGET_INTERNAL_ARG_POINTER
1707 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1708 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1709 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1711 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1712 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1714 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1715 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
1717 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1718 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1721 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1722 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1725 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1726 #undef TARGET_INSERT_ATTRIBUTES
1727 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1730 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1731 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1733 #undef TARGET_STACK_PROTECT_FAIL
1734 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1736 #undef TARGET_FUNCTION_VALUE
1737 #define TARGET_FUNCTION_VALUE ix86_function_value
1739 struct gcc_target targetm = TARGET_INITIALIZER;
1742 /* The svr4 ABI for the i386 says that records and unions are returned
1744 #ifndef DEFAULT_PCC_STRUCT_RETURN
1745 #define DEFAULT_PCC_STRUCT_RETURN 1
1748 /* Implement TARGET_HANDLE_OPTION. */
1751 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1758 target_flags &= ~MASK_3DNOW_A;
1759 target_flags_explicit |= MASK_3DNOW_A;
1766 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1767 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1774 target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSE4A);
1775 target_flags_explicit |= MASK_SSE2 | MASK_SSE3 | MASK_SSE4A;
1782 target_flags &= ~(MASK_SSE3 | MASK_SSE4A);
1783 target_flags_explicit |= MASK_SSE3 | MASK_SSE4A;
1790 target_flags &= ~MASK_SSE4A;
1791 target_flags_explicit |= MASK_SSE4A;
1800 /* Sometimes certain combinations of command options do not make
1801 sense on a particular target machine. You can define a macro
1802 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1803 defined, is executed once just after all the command options have
1806 Don't use this macro to turn on various extra optimizations for
1807 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1810 override_options (void)
1813 int ix86_tune_defaulted = 0;
1815 /* Comes from final.c -- no real reason to change it. */
1816 #define MAX_CODE_ALIGN 16
1820 const struct processor_costs *cost; /* Processor costs */
1821 const int target_enable; /* Target flags to enable. */
1822 const int target_disable; /* Target flags to disable. */
1823 const int align_loop; /* Default alignments. */
1824 const int align_loop_max_skip;
1825 const int align_jump;
1826 const int align_jump_max_skip;
1827 const int align_func;
1829 const processor_target_table[PROCESSOR_max] =
1831 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1832 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1833 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1834 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1835 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1836 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1837 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1838 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1839 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1840 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1841 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1842 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1843 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16},
1844 {&amdfam10_cost, 0, 0, 32, 7, 32, 7, 32}
1847 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1850 const char *const name; /* processor name or nickname. */
1851 const enum processor_type processor;
1852 const enum pta_flags
1858 PTA_PREFETCH_SSE = 16,
1869 const processor_alias_table[] =
1871 {"i386", PROCESSOR_I386, 0},
1872 {"i486", PROCESSOR_I486, 0},
1873 {"i586", PROCESSOR_PENTIUM, 0},
1874 {"pentium", PROCESSOR_PENTIUM, 0},
1875 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1876 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1877 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1878 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1879 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1880 {"i686", PROCESSOR_PENTIUMPRO, 0},
1881 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1882 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1883 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1884 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1885 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1886 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1887 | PTA_MMX | PTA_PREFETCH_SSE},
1888 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1889 | PTA_MMX | PTA_PREFETCH_SSE},
1890 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1891 | PTA_MMX | PTA_PREFETCH_SSE},
1892 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1893 | PTA_MMX | PTA_PREFETCH_SSE | PTA_CX16},
1894 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
1895 | PTA_64BIT | PTA_MMX
1896 | PTA_PREFETCH_SSE | PTA_CX16},
1897 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1899 {"k6", PROCESSOR_K6, PTA_MMX},
1900 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1901 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1902 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1904 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1905 | PTA_3DNOW | PTA_3DNOW_A},
1906 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1907 | PTA_3DNOW_A | PTA_SSE},
1908 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1909 | PTA_3DNOW_A | PTA_SSE},
1910 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1911 | PTA_3DNOW_A | PTA_SSE},
1912 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1913 | PTA_SSE | PTA_SSE2 },
1914 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1915 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1916 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1917 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1918 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1919 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1920 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1921 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1922 {"amdfam10", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1923 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1924 | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
1925 | PTA_ABM | PTA_SSE4A | PTA_CX16},
1926 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1927 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1930 int const pta_size = ARRAY_SIZE (processor_alias_table);
1932 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1933 SUBTARGET_OVERRIDE_OPTIONS;
1936 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1937 SUBSUBTARGET_OVERRIDE_OPTIONS;
1940 /* -fPIC is the default for x86_64. */
1941 if (TARGET_MACHO && TARGET_64BIT)
1944 /* Set the default values for switches whose default depends on TARGET_64BIT
1945 in case they weren't overwritten by command line options. */
1948 /* Mach-O doesn't support omitting the frame pointer for now. */
1949 if (flag_omit_frame_pointer == 2)
1950 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
1951 if (flag_asynchronous_unwind_tables == 2)
1952 flag_asynchronous_unwind_tables = 1;
1953 if (flag_pcc_struct_return == 2)
1954 flag_pcc_struct_return = 0;
1958 if (flag_omit_frame_pointer == 2)
1959 flag_omit_frame_pointer = 0;
1960 if (flag_asynchronous_unwind_tables == 2)
1961 flag_asynchronous_unwind_tables = 0;
1962 if (flag_pcc_struct_return == 2)
1963 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1966 /* Need to check -mtune=generic first. */
1967 if (ix86_tune_string)
1969 if (!strcmp (ix86_tune_string, "generic")
1970 || !strcmp (ix86_tune_string, "i686")
1971 /* As special support for cross compilers we read -mtune=native
1972 as -mtune=generic. With native compilers we won't see the
1973 -mtune=native, as it was changed by the driver. */
1974 || !strcmp (ix86_tune_string, "native"))
1977 ix86_tune_string = "generic64";
1979 ix86_tune_string = "generic32";
1981 else if (!strncmp (ix86_tune_string, "generic", 7))
1982 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1986 if (ix86_arch_string)
1987 ix86_tune_string = ix86_arch_string;
1988 if (!ix86_tune_string)
1990 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1991 ix86_tune_defaulted = 1;
1994 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1995 need to use a sensible tune option. */
1996 if (!strcmp (ix86_tune_string, "generic")
1997 || !strcmp (ix86_tune_string, "x86-64")
1998 || !strcmp (ix86_tune_string, "i686"))
2001 ix86_tune_string = "generic64";
2003 ix86_tune_string = "generic32";
2006 if (ix86_stringop_string)
2008 if (!strcmp (ix86_stringop_string, "rep_byte"))
2009 stringop_alg = rep_prefix_1_byte;
2010 else if (!strcmp (ix86_stringop_string, "libcall"))
2011 stringop_alg = libcall;
2012 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2013 stringop_alg = rep_prefix_4_byte;
2014 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2015 stringop_alg = rep_prefix_8_byte;
2016 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2017 stringop_alg = loop_1_byte;
2018 else if (!strcmp (ix86_stringop_string, "loop"))
2019 stringop_alg = loop;
2020 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2021 stringop_alg = unrolled_loop;
2023 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2025 if (!strcmp (ix86_tune_string, "x86-64"))
2026 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2027 "-mtune=generic instead as appropriate.");
2029 if (!ix86_arch_string)
2030 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2031 if (!strcmp (ix86_arch_string, "generic"))
2032 error ("generic CPU can be used only for -mtune= switch");
2033 if (!strncmp (ix86_arch_string, "generic", 7))
2034 error ("bad value (%s) for -march= switch", ix86_arch_string);
2036 if (ix86_cmodel_string != 0)
2038 if (!strcmp (ix86_cmodel_string, "small"))
2039 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2040 else if (!strcmp (ix86_cmodel_string, "medium"))
2041 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2043 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
2044 else if (!strcmp (ix86_cmodel_string, "32"))
2045 ix86_cmodel = CM_32;
2046 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2047 ix86_cmodel = CM_KERNEL;
2048 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
2049 ix86_cmodel = CM_LARGE;
2051 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2055 ix86_cmodel = CM_32;
2057 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2059 if (ix86_asm_string != 0)
2062 && !strcmp (ix86_asm_string, "intel"))
2063 ix86_asm_dialect = ASM_INTEL;
2064 else if (!strcmp (ix86_asm_string, "att"))
2065 ix86_asm_dialect = ASM_ATT;
2067 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2069 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2070 error ("code model %qs not supported in the %s bit mode",
2071 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2072 if (ix86_cmodel == CM_LARGE)
2073 sorry ("code model %<large%> not supported yet");
2074 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
2075 sorry ("%i-bit mode not compiled in",
2076 (target_flags & MASK_64BIT) ? 64 : 32);
2078 for (i = 0; i < pta_size; i++)
2079 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2081 ix86_arch = processor_alias_table[i].processor;
2082 /* Default cpu tuning to the architecture. */
2083 ix86_tune = ix86_arch;
2084 if (processor_alias_table[i].flags & PTA_MMX
2085 && !(target_flags_explicit & MASK_MMX))
2086 target_flags |= MASK_MMX;
2087 if (processor_alias_table[i].flags & PTA_3DNOW
2088 && !(target_flags_explicit & MASK_3DNOW))
2089 target_flags |= MASK_3DNOW;
2090 if (processor_alias_table[i].flags & PTA_3DNOW_A
2091 && !(target_flags_explicit & MASK_3DNOW_A))
2092 target_flags |= MASK_3DNOW_A;
2093 if (processor_alias_table[i].flags & PTA_SSE
2094 && !(target_flags_explicit & MASK_SSE))
2095 target_flags |= MASK_SSE;
2096 if (processor_alias_table[i].flags & PTA_SSE2
2097 && !(target_flags_explicit & MASK_SSE2))
2098 target_flags |= MASK_SSE2;
2099 if (processor_alias_table[i].flags & PTA_SSE3
2100 && !(target_flags_explicit & MASK_SSE3))
2101 target_flags |= MASK_SSE3;
2102 if (processor_alias_table[i].flags & PTA_SSSE3
2103 && !(target_flags_explicit & MASK_SSSE3))
2104 target_flags |= MASK_SSSE3;
2105 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
2106 x86_prefetch_sse = true;
2107 if (processor_alias_table[i].flags & PTA_CX16)
2108 x86_cmpxchg16b = true;
2109 if (processor_alias_table[i].flags & PTA_POPCNT
2110 && !(target_flags_explicit & MASK_POPCNT))
2111 target_flags |= MASK_POPCNT;
2112 if (processor_alias_table[i].flags & PTA_ABM
2113 && !(target_flags_explicit & MASK_ABM))
2114 target_flags |= MASK_ABM;
2115 if (processor_alias_table[i].flags & PTA_SSE4A
2116 && !(target_flags_explicit & MASK_SSE4A))
2117 target_flags |= MASK_SSE4A;
2118 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2119 error ("CPU you selected does not support x86-64 "
2125 error ("bad value (%s) for -march= switch", ix86_arch_string);
2127 for (i = 0; i < pta_size; i++)
2128 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2130 ix86_tune = processor_alias_table[i].processor;
2131 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2133 if (ix86_tune_defaulted)
2135 ix86_tune_string = "x86-64";
2136 for (i = 0; i < pta_size; i++)
2137 if (! strcmp (ix86_tune_string,
2138 processor_alias_table[i].name))
2140 ix86_tune = processor_alias_table[i].processor;
2143 error ("CPU you selected does not support x86-64 "
2146 /* Intel CPUs have always interpreted SSE prefetch instructions as
2147 NOPs; so, we can enable SSE prefetch instructions even when
2148 -mtune (rather than -march) points us to a processor that has them.
2149 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2150 higher processors. */
2151 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
2152 x86_prefetch_sse = true;
2156 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2158 ix86_arch_mask = 1 << ix86_arch;
2159 ix86_tune_mask = 1 << ix86_tune;
2162 ix86_cost = &size_cost;
2164 ix86_cost = processor_target_table[ix86_tune].cost;
2165 target_flags |= processor_target_table[ix86_tune].target_enable;
2166 target_flags &= ~processor_target_table[ix86_tune].target_disable;
2168 /* Arrange to set up i386_stack_locals for all functions. */
2169 init_machine_status = ix86_init_machine_status;
2171 /* Validate -mregparm= value. */
2172 if (ix86_regparm_string)
2174 i = atoi (ix86_regparm_string);
2175 if (i < 0 || i > REGPARM_MAX)
2176 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2182 ix86_regparm = REGPARM_MAX;
2184 /* If the user has provided any of the -malign-* options,
2185 warn and use that value only if -falign-* is not set.
2186 Remove this code in GCC 3.2 or later. */
2187 if (ix86_align_loops_string)
2189 warning (0, "-malign-loops is obsolete, use -falign-loops");
2190 if (align_loops == 0)
2192 i = atoi (ix86_align_loops_string);
2193 if (i < 0 || i > MAX_CODE_ALIGN)
2194 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2196 align_loops = 1 << i;
2200 if (ix86_align_jumps_string)
2202 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2203 if (align_jumps == 0)
2205 i = atoi (ix86_align_jumps_string);
2206 if (i < 0 || i > MAX_CODE_ALIGN)
2207 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2209 align_jumps = 1 << i;
2213 if (ix86_align_funcs_string)
2215 warning (0, "-malign-functions is obsolete, use -falign-functions");
2216 if (align_functions == 0)
2218 i = atoi (ix86_align_funcs_string);
2219 if (i < 0 || i > MAX_CODE_ALIGN)
2220 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2222 align_functions = 1 << i;
2226 /* Default align_* from the processor table. */
2227 if (align_loops == 0)
2229 align_loops = processor_target_table[ix86_tune].align_loop;
2230 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2232 if (align_jumps == 0)
2234 align_jumps = processor_target_table[ix86_tune].align_jump;
2235 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2237 if (align_functions == 0)
2239 align_functions = processor_target_table[ix86_tune].align_func;
2242 /* Validate -mbranch-cost= value, or provide default. */
2243 ix86_branch_cost = ix86_cost->branch_cost;
2244 if (ix86_branch_cost_string)
2246 i = atoi (ix86_branch_cost_string);
2248 error ("-mbranch-cost=%d is not between 0 and 5", i);
2250 ix86_branch_cost = i;
2252 if (ix86_section_threshold_string)
2254 i = atoi (ix86_section_threshold_string);
2256 error ("-mlarge-data-threshold=%d is negative", i);
2258 ix86_section_threshold = i;
2261 if (ix86_tls_dialect_string)
2263 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2264 ix86_tls_dialect = TLS_DIALECT_GNU;
2265 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2266 ix86_tls_dialect = TLS_DIALECT_GNU2;
2267 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2268 ix86_tls_dialect = TLS_DIALECT_SUN;
2270 error ("bad value (%s) for -mtls-dialect= switch",
2271 ix86_tls_dialect_string);
2274 /* Keep nonleaf frame pointers. */
2275 if (flag_omit_frame_pointer)
2276 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2277 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2278 flag_omit_frame_pointer = 1;
2280 /* If we're doing fast math, we don't care about comparison order
2281 wrt NaNs. This lets us use a shorter comparison sequence. */
2282 if (flag_finite_math_only)
2283 target_flags &= ~MASK_IEEE_FP;
2285 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2286 since the insns won't need emulation. */
2287 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2288 target_flags &= ~MASK_NO_FANCY_MATH_387;
2290 /* Likewise, if the target doesn't have a 387, or we've specified
2291 software floating point, don't use 387 inline intrinsics. */
2293 target_flags |= MASK_NO_FANCY_MATH_387;
2295 /* Turn on SSE3 builtins for -mssse3. */
2297 target_flags |= MASK_SSE3;
2299 /* Turn on SSE3 builtins for -msse4a. */
2301 target_flags |= MASK_SSE3;
2303 /* Turn on SSE2 builtins for -msse3. */
2305 target_flags |= MASK_SSE2;
2307 /* Turn on SSE builtins for -msse2. */
2309 target_flags |= MASK_SSE;
2311 /* Turn on MMX builtins for -msse. */
2314 target_flags |= MASK_MMX & ~target_flags_explicit;
2315 x86_prefetch_sse = true;
2318 /* Turn on MMX builtins for 3Dnow. */
2320 target_flags |= MASK_MMX;
2322 /* Turn on POPCNT builtins for -mabm. */
2324 target_flags |= MASK_POPCNT;
2328 if (TARGET_ALIGN_DOUBLE)
2329 error ("-malign-double makes no sense in the 64bit mode");
2331 error ("-mrtd calling convention not supported in the 64bit mode");
2333 /* Enable by default the SSE and MMX builtins. Do allow the user to
2334 explicitly disable any of these. In particular, disabling SSE and
2335 MMX for kernel code is extremely useful. */
2337 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
2338 & ~target_flags_explicit);
2342 /* i386 ABI does not specify red zone. It still makes sense to use it
2343 when programmer takes care to stack from being destroyed. */
2344 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2345 target_flags |= MASK_NO_RED_ZONE;
2348 /* Validate -mpreferred-stack-boundary= value, or provide default.
2349 The default of 128 bits is for Pentium III's SSE __m128. We can't
2350 change it because of optimize_size. Otherwise, we can't mix object
2351 files compiled with -Os and -On. */
2352 ix86_preferred_stack_boundary = 128;
2353 if (ix86_preferred_stack_boundary_string)
2355 i = atoi (ix86_preferred_stack_boundary_string);
2356 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2357 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2358 TARGET_64BIT ? 4 : 2);
2360 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2363 /* Accept -msseregparm only if at least SSE support is enabled. */
2364 if (TARGET_SSEREGPARM
2366 error ("-msseregparm used without SSE enabled");
2368 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2370 if (ix86_fpmath_string != 0)
2372 if (! strcmp (ix86_fpmath_string, "387"))
2373 ix86_fpmath = FPMATH_387;
2374 else if (! strcmp (ix86_fpmath_string, "sse"))
2378 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2379 ix86_fpmath = FPMATH_387;
2382 ix86_fpmath = FPMATH_SSE;
2384 else if (! strcmp (ix86_fpmath_string, "387,sse")
2385 || ! strcmp (ix86_fpmath_string, "sse,387"))
2389 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2390 ix86_fpmath = FPMATH_387;
2392 else if (!TARGET_80387)
2394 warning (0, "387 instruction set disabled, using SSE arithmetics");
2395 ix86_fpmath = FPMATH_SSE;
2398 ix86_fpmath = FPMATH_SSE | FPMATH_387;
2401 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2404 /* If the i387 is disabled, then do not return values in it. */
2406 target_flags &= ~MASK_FLOAT_RETURNS;
2408 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2409 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2411 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2413 /* ??? Unwind info is not correct around the CFG unless either a frame
2414 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2415 unwind info generation to be aware of the CFG and propagating states
2417 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2418 || flag_exceptions || flag_non_call_exceptions)
2419 && flag_omit_frame_pointer
2420 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2422 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2423 warning (0, "unwind tables currently require either a frame pointer "
2424 "or -maccumulate-outgoing-args for correctness");
2425 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2428 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2431 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2432 p = strchr (internal_label_prefix, 'X');
2433 internal_label_prefix_len = p - internal_label_prefix;
2437 /* When scheduling description is not available, disable scheduler pass
2438 so it won't slow down the compilation and make x87 code slower. */
2439 if (!TARGET_SCHEDULE)
2440 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2442 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2443 set_param_value ("simultaneous-prefetches",
2444 ix86_cost->simultaneous_prefetches);
2445 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2446 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2449 /* switch to the appropriate section for output of DECL.
2450 DECL is either a `VAR_DECL' node or a constant of some sort.
2451 RELOC indicates whether forming the initial value of DECL requires
2452 link-time relocations. */
2455 x86_64_elf_select_section (tree decl, int reloc,
2456 unsigned HOST_WIDE_INT align)
2458 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2459 && ix86_in_large_data_p (decl))
2461 const char *sname = NULL;
2462 unsigned int flags = SECTION_WRITE;
2463 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2468 case SECCAT_DATA_REL:
2469 sname = ".ldata.rel";
2471 case SECCAT_DATA_REL_LOCAL:
2472 sname = ".ldata.rel.local";
2474 case SECCAT_DATA_REL_RO:
2475 sname = ".ldata.rel.ro";
2477 case SECCAT_DATA_REL_RO_LOCAL:
2478 sname = ".ldata.rel.ro.local";
2482 flags |= SECTION_BSS;
2485 case SECCAT_RODATA_MERGE_STR:
2486 case SECCAT_RODATA_MERGE_STR_INIT:
2487 case SECCAT_RODATA_MERGE_CONST:
2491 case SECCAT_SRODATA:
2498 /* We don't split these for medium model. Place them into
2499 default sections and hope for best. */
2504 /* We might get called with string constants, but get_named_section
2505 doesn't like them as they are not DECLs. Also, we need to set
2506 flags in that case. */
2508 return get_section (sname, flags, NULL);
2509 return get_named_section (decl, sname, reloc);
2512 return default_elf_select_section (decl, reloc, align);
2515 /* Build up a unique section name, expressed as a
2516 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2517 RELOC indicates whether the initial value of EXP requires
2518 link-time relocations. */
2521 x86_64_elf_unique_section (tree decl, int reloc)
2523 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2524 && ix86_in_large_data_p (decl))
2526 const char *prefix = NULL;
2527 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2528 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2530 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2533 case SECCAT_DATA_REL:
2534 case SECCAT_DATA_REL_LOCAL:
2535 case SECCAT_DATA_REL_RO:
2536 case SECCAT_DATA_REL_RO_LOCAL:
2537 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2540 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2543 case SECCAT_RODATA_MERGE_STR:
2544 case SECCAT_RODATA_MERGE_STR_INIT:
2545 case SECCAT_RODATA_MERGE_CONST:
2546 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2548 case SECCAT_SRODATA:
2555 /* We don't split these for medium model. Place them into
2556 default sections and hope for best. */
2564 plen = strlen (prefix);
2566 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2567 name = targetm.strip_name_encoding (name);
2568 nlen = strlen (name);
2570 string = alloca (nlen + plen + 1);
2571 memcpy (string, prefix, plen);
2572 memcpy (string + plen, name, nlen + 1);
2574 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2578 default_unique_section (decl, reloc);
2581 #ifdef COMMON_ASM_OP
2582 /* This says how to output assembler code to declare an
2583 uninitialized external linkage data object.
2585 For medium model x86-64 we need to use .largecomm opcode for
2588 x86_elf_aligned_common (FILE *file,
2589 const char *name, unsigned HOST_WIDE_INT size,
2592 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2593 && size > (unsigned int)ix86_section_threshold)
2594 fprintf (file, ".largecomm\t");
2596 fprintf (file, "%s", COMMON_ASM_OP);
2597 assemble_name (file, name);
2598 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2599 size, align / BITS_PER_UNIT);
2602 /* Utility function for targets to use in implementing
2603 ASM_OUTPUT_ALIGNED_BSS. */
2606 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2607 const char *name, unsigned HOST_WIDE_INT size,
2610 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2611 && size > (unsigned int)ix86_section_threshold)
2612 switch_to_section (get_named_section (decl, ".lbss", 0));
2614 switch_to_section (bss_section);
2615 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2616 #ifdef ASM_DECLARE_OBJECT_NAME
2617 last_assemble_variable_decl = decl;
2618 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2620 /* Standard thing is just output label for the object. */
2621 ASM_OUTPUT_LABEL (file, name);
2622 #endif /* ASM_DECLARE_OBJECT_NAME */
2623 ASM_OUTPUT_SKIP (file, size ? size : 1);
2627 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2629 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2630 make the problem with not enough registers even worse. */
2631 #ifdef INSN_SCHEDULING
2633 flag_schedule_insns = 0;
2637 /* The Darwin libraries never set errno, so we might as well
2638 avoid calling them when that's the only reason we would. */
2639 flag_errno_math = 0;
2641 /* The default values of these switches depend on the TARGET_64BIT
2642 that is not known at this moment. Mark these values with 2 and
2643 let user the to override these. In case there is no command line option
2644 specifying them, we will set the defaults in override_options. */
2646 flag_omit_frame_pointer = 2;
2647 flag_pcc_struct_return = 2;
2648 flag_asynchronous_unwind_tables = 2;
2649 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2650 SUBTARGET_OPTIMIZATION_OPTIONS;
2654 /* Table of valid machine attributes. */
2655 const struct attribute_spec ix86_attribute_table[] =
2657 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2658 /* Stdcall attribute says callee is responsible for popping arguments
2659 if they are not variable. */
2660 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2661 /* Fastcall attribute says callee is responsible for popping arguments
2662 if they are not variable. */
2663 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2664 /* Cdecl attribute says the callee is a normal C declaration */
2665 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2666 /* Regparm attribute specifies how many integer arguments are to be
2667 passed in registers. */
2668 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
2669 /* Sseregparm attribute says we are using x86_64 calling conventions
2670 for FP arguments. */
2671 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2672 /* force_align_arg_pointer says this function realigns the stack at entry. */
2673 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
2674 false, true, true, ix86_handle_cconv_attribute },
2675 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2676 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2677 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2678 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
2680 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2681 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2682 #ifdef SUBTARGET_ATTRIBUTE_TABLE
2683 SUBTARGET_ATTRIBUTE_TABLE,
2685 { NULL, 0, 0, false, false, false, NULL }
2688 /* Decide whether we can make a sibling call to a function. DECL is the
2689 declaration of the function being targeted by the call and EXP is the
2690 CALL_EXPR representing the call. */
2693 ix86_function_ok_for_sibcall (tree decl, tree exp)
2698 /* If we are generating position-independent code, we cannot sibcall
2699 optimize any indirect call, or a direct call to a global function,
2700 as the PLT requires %ebx be live. */
2701 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2708 func = TREE_TYPE (CALL_EXPR_FN (exp));
2709 if (POINTER_TYPE_P (func))
2710 func = TREE_TYPE (func);
2713 /* Check that the return value locations are the same. Like
2714 if we are returning floats on the 80387 register stack, we cannot
2715 make a sibcall from a function that doesn't return a float to a
2716 function that does or, conversely, from a function that does return
2717 a float to a function that doesn't; the necessary stack adjustment
2718 would not be executed. This is also the place we notice
2719 differences in the return value ABI. Note that it is ok for one
2720 of the functions to have void return type as long as the return
2721 value of the other is passed in a register. */
2722 a = ix86_function_value (TREE_TYPE (exp), func, false);
2723 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2725 if (STACK_REG_P (a) || STACK_REG_P (b))
2727 if (!rtx_equal_p (a, b))
2730 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2732 else if (!rtx_equal_p (a, b))
2735 /* If this call is indirect, we'll need to be able to use a call-clobbered
2736 register for the address of the target function. Make sure that all
2737 such registers are not used for passing parameters. */
2738 if (!decl && !TARGET_64BIT)
2742 /* We're looking at the CALL_EXPR, we need the type of the function. */
2743 type = CALL_EXPR_FN (exp); /* pointer expression */
2744 type = TREE_TYPE (type); /* pointer type */
2745 type = TREE_TYPE (type); /* function type */
2747 if (ix86_function_regparm (type, NULL) >= 3)
2749 /* ??? Need to count the actual number of registers to be used,
2750 not the possible number of registers. Fix later. */
2755 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2756 /* Dllimport'd functions are also called indirectly. */
2757 if (decl && DECL_DLLIMPORT_P (decl)
2758 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2762 /* If we forced aligned the stack, then sibcalling would unalign the
2763 stack, which may break the called function. */
2764 if (cfun->machine->force_align_arg_pointer)
2767 /* Otherwise okay. That also includes certain types of indirect calls. */
2771 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2772 calling convention attributes;
2773 arguments as in struct attribute_spec.handler. */
2776 ix86_handle_cconv_attribute (tree *node, tree name,
2778 int flags ATTRIBUTE_UNUSED,
2781 if (TREE_CODE (*node) != FUNCTION_TYPE
2782 && TREE_CODE (*node) != METHOD_TYPE
2783 && TREE_CODE (*node) != FIELD_DECL
2784 && TREE_CODE (*node) != TYPE_DECL)
2786 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2787 IDENTIFIER_POINTER (name));
2788 *no_add_attrs = true;
2792 /* Can combine regparm with all attributes but fastcall. */
2793 if (is_attribute_p ("regparm", name))
2797 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2799 error ("fastcall and regparm attributes are not compatible");
2802 cst = TREE_VALUE (args);
2803 if (TREE_CODE (cst) != INTEGER_CST)
2805 warning (OPT_Wattributes,
2806 "%qs attribute requires an integer constant argument",
2807 IDENTIFIER_POINTER (name));
2808 *no_add_attrs = true;
2810 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2812 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2813 IDENTIFIER_POINTER (name), REGPARM_MAX);
2814 *no_add_attrs = true;
2818 && lookup_attribute (ix86_force_align_arg_pointer_string,
2819 TYPE_ATTRIBUTES (*node))
2820 && compare_tree_int (cst, REGPARM_MAX-1))
2822 error ("%s functions limited to %d register parameters",
2823 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
2831 warning (OPT_Wattributes, "%qs attribute ignored",
2832 IDENTIFIER_POINTER (name));
2833 *no_add_attrs = true;
2837 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2838 if (is_attribute_p ("fastcall", name))
2840 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2842 error ("fastcall and cdecl attributes are not compatible");
2844 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2846 error ("fastcall and stdcall attributes are not compatible");
2848 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2850 error ("fastcall and regparm attributes are not compatible");
2854 /* Can combine stdcall with fastcall (redundant), regparm and
2856 else if (is_attribute_p ("stdcall", name))
2858 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2860 error ("stdcall and cdecl attributes are not compatible");
2862 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2864 error ("stdcall and fastcall attributes are not compatible");
2868 /* Can combine cdecl with regparm and sseregparm. */
2869 else if (is_attribute_p ("cdecl", name))
2871 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2873 error ("stdcall and cdecl attributes are not compatible");
2875 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2877 error ("fastcall and cdecl attributes are not compatible");
2881 /* Can combine sseregparm with all attributes. */
2886 /* Return 0 if the attributes for two types are incompatible, 1 if they
2887 are compatible, and 2 if they are nearly compatible (which causes a
2888 warning to be generated). */
2891 ix86_comp_type_attributes (tree type1, tree type2)
2893 /* Check for mismatch of non-default calling convention. */
2894 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2896 if (TREE_CODE (type1) != FUNCTION_TYPE)
2899 /* Check for mismatched fastcall/regparm types. */
2900 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2901 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2902 || (ix86_function_regparm (type1, NULL)
2903 != ix86_function_regparm (type2, NULL)))
2906 /* Check for mismatched sseregparm types. */
2907 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2908 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2911 /* Check for mismatched return types (cdecl vs stdcall). */
2912 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2913 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2919 /* Return the regparm value for a function with the indicated TYPE and DECL.
2920 DECL may be NULL when calling function indirectly
2921 or considering a libcall. */
2924 ix86_function_regparm (tree type, tree decl)
2927 int regparm = ix86_regparm;
2928 bool user_convention = false;
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