1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static rtx ix86_static_chain (const_tree, bool);
1883 static int ix86_function_regparm (const_tree, const_tree);
1884 static void ix86_compute_frame_layout (struct ix86_frame *);
1885 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1887 static void ix86_add_new_builtins (int);
1889 enum ix86_function_specific_strings
1891 IX86_FUNCTION_SPECIFIC_ARCH,
1892 IX86_FUNCTION_SPECIFIC_TUNE,
1893 IX86_FUNCTION_SPECIFIC_FPMATH,
1894 IX86_FUNCTION_SPECIFIC_MAX
1897 static char *ix86_target_string (int, int, const char *, const char *,
1898 const char *, bool);
1899 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1900 static void ix86_function_specific_save (struct cl_target_option *);
1901 static void ix86_function_specific_restore (struct cl_target_option *);
1902 static void ix86_function_specific_print (FILE *, int,
1903 struct cl_target_option *);
1904 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1905 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1906 static bool ix86_can_inline_p (tree, tree);
1907 static void ix86_set_current_function (tree);
1909 static enum calling_abi ix86_function_abi (const_tree);
1912 /* The svr4 ABI for the i386 says that records and unions are returned
1914 #ifndef DEFAULT_PCC_STRUCT_RETURN
1915 #define DEFAULT_PCC_STRUCT_RETURN 1
1918 /* Whether -mtune= or -march= were specified */
1919 static int ix86_tune_defaulted;
1920 static int ix86_arch_specified;
1922 /* Bit flags that specify the ISA we are compiling for. */
1923 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1925 /* A mask of ix86_isa_flags that includes bit X if X
1926 was set or cleared on the command line. */
1927 static int ix86_isa_flags_explicit;
1929 /* Define a set of ISAs which are available when a given ISA is
1930 enabled. MMX and SSE ISAs are handled separately. */
1932 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1933 #define OPTION_MASK_ISA_3DNOW_SET \
1934 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1936 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1937 #define OPTION_MASK_ISA_SSE2_SET \
1938 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1939 #define OPTION_MASK_ISA_SSE3_SET \
1940 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1941 #define OPTION_MASK_ISA_SSSE3_SET \
1942 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1943 #define OPTION_MASK_ISA_SSE4_1_SET \
1944 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1945 #define OPTION_MASK_ISA_SSE4_2_SET \
1946 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1947 #define OPTION_MASK_ISA_AVX_SET \
1948 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1949 #define OPTION_MASK_ISA_FMA_SET \
1950 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1952 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1954 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1956 #define OPTION_MASK_ISA_SSE4A_SET \
1957 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1958 #define OPTION_MASK_ISA_FMA4_SET \
1959 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1960 | OPTION_MASK_ISA_AVX_SET)
1962 /* AES and PCLMUL need SSE2 because they use xmm registers */
1963 #define OPTION_MASK_ISA_AES_SET \
1964 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1965 #define OPTION_MASK_ISA_PCLMUL_SET \
1966 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1968 #define OPTION_MASK_ISA_ABM_SET \
1969 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1971 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1972 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1973 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1974 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1975 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1977 /* Define a set of ISAs which aren't available when a given ISA is
1978 disabled. MMX and SSE ISAs are handled separately. */
1980 #define OPTION_MASK_ISA_MMX_UNSET \
1981 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1982 #define OPTION_MASK_ISA_3DNOW_UNSET \
1983 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1984 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1986 #define OPTION_MASK_ISA_SSE_UNSET \
1987 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1988 #define OPTION_MASK_ISA_SSE2_UNSET \
1989 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1990 #define OPTION_MASK_ISA_SSE3_UNSET \
1991 (OPTION_MASK_ISA_SSE3 \
1992 | OPTION_MASK_ISA_SSSE3_UNSET \
1993 | OPTION_MASK_ISA_SSE4A_UNSET )
1994 #define OPTION_MASK_ISA_SSSE3_UNSET \
1995 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1996 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1997 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1998 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1999 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2000 #define OPTION_MASK_ISA_AVX_UNSET \
2001 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2002 | OPTION_MASK_ISA_FMA4_UNSET)
2003 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2005 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2007 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2009 #define OPTION_MASK_ISA_SSE4A_UNSET \
2010 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2012 #define OPTION_MASK_ISA_FMA4_UNSET OPTION_MASK_ISA_FMA4
2014 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2015 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2016 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2017 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2018 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2019 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2020 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2021 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2023 /* Vectorization library interface and handlers. */
2024 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2025 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2026 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2028 /* Processor target table, indexed by processor number */
2031 const struct processor_costs *cost; /* Processor costs */
2032 const int align_loop; /* Default alignments. */
2033 const int align_loop_max_skip;
2034 const int align_jump;
2035 const int align_jump_max_skip;
2036 const int align_func;
2039 static const struct ptt processor_target_table[PROCESSOR_max] =
2041 {&i386_cost, 4, 3, 4, 3, 4},
2042 {&i486_cost, 16, 15, 16, 15, 16},
2043 {&pentium_cost, 16, 7, 16, 7, 16},
2044 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2045 {&geode_cost, 0, 0, 0, 0, 0},
2046 {&k6_cost, 32, 7, 32, 7, 32},
2047 {&athlon_cost, 16, 7, 16, 7, 16},
2048 {&pentium4_cost, 0, 0, 0, 0, 0},
2049 {&k8_cost, 16, 7, 16, 7, 16},
2050 {&nocona_cost, 0, 0, 0, 0, 0},
2051 {&core2_cost, 16, 10, 16, 10, 16},
2052 {&generic32_cost, 16, 7, 16, 7, 16},
2053 {&generic64_cost, 16, 10, 16, 10, 16},
2054 {&amdfam10_cost, 32, 24, 32, 7, 32},
2055 {&atom_cost, 16, 7, 16, 7, 16}
2058 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2084 /* Implement TARGET_HANDLE_OPTION. */
2087 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2094 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2095 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2099 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2100 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2107 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2112 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2113 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2123 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2124 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2128 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2201 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2206 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2214 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2219 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2220 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2225 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2226 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2230 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2231 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2237 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2238 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2242 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2243 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2250 ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
2255 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
2263 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2268 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2276 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2281 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2289 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2294 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2302 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2307 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2315 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2320 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2328 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2333 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2341 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2346 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2347 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2354 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2359 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2360 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2369 /* Return a string the documents the current -m options. The caller is
2370 responsible for freeing the string. */
2373 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2374 const char *fpmath, bool add_nl_p)
2376 struct ix86_target_opts
2378 const char *option; /* option string */
2379 int mask; /* isa mask options */
2382 /* This table is ordered so that options like -msse4.2 that imply
2383 preceding options while match those first. */
2384 static struct ix86_target_opts isa_opts[] =
2386 { "-m64", OPTION_MASK_ISA_64BIT },
2387 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2388 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2389 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2390 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2391 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2392 { "-msse3", OPTION_MASK_ISA_SSE3 },
2393 { "-msse2", OPTION_MASK_ISA_SSE2 },
2394 { "-msse", OPTION_MASK_ISA_SSE },
2395 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2396 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2397 { "-mmmx", OPTION_MASK_ISA_MMX },
2398 { "-mabm", OPTION_MASK_ISA_ABM },
2399 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2400 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2401 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2402 { "-maes", OPTION_MASK_ISA_AES },
2403 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2407 static struct ix86_target_opts flag_opts[] =
2409 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2410 { "-m80387", MASK_80387 },
2411 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2412 { "-malign-double", MASK_ALIGN_DOUBLE },
2413 { "-mcld", MASK_CLD },
2414 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2415 { "-mieee-fp", MASK_IEEE_FP },
2416 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2417 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2418 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2419 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2420 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2421 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2422 { "-mno-red-zone", MASK_NO_RED_ZONE },
2423 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2424 { "-mrecip", MASK_RECIP },
2425 { "-mrtd", MASK_RTD },
2426 { "-msseregparm", MASK_SSEREGPARM },
2427 { "-mstack-arg-probe", MASK_STACK_PROBE },
2428 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2431 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2434 char target_other[40];
2443 memset (opts, '\0', sizeof (opts));
2445 /* Add -march= option. */
2448 opts[num][0] = "-march=";
2449 opts[num++][1] = arch;
2452 /* Add -mtune= option. */
2455 opts[num][0] = "-mtune=";
2456 opts[num++][1] = tune;
2459 /* Pick out the options in isa options. */
2460 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2462 if ((isa & isa_opts[i].mask) != 0)
2464 opts[num++][0] = isa_opts[i].option;
2465 isa &= ~ isa_opts[i].mask;
2469 if (isa && add_nl_p)
2471 opts[num++][0] = isa_other;
2472 sprintf (isa_other, "(other isa: 0x%x)", isa);
2475 /* Add flag options. */
2476 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2478 if ((flags & flag_opts[i].mask) != 0)
2480 opts[num++][0] = flag_opts[i].option;
2481 flags &= ~ flag_opts[i].mask;
2485 if (flags && add_nl_p)
2487 opts[num++][0] = target_other;
2488 sprintf (target_other, "(other flags: 0x%x)", isa);
2491 /* Add -fpmath= option. */
2494 opts[num][0] = "-mfpmath=";
2495 opts[num++][1] = fpmath;
2502 gcc_assert (num < ARRAY_SIZE (opts));
2504 /* Size the string. */
2506 sep_len = (add_nl_p) ? 3 : 1;
2507 for (i = 0; i < num; i++)
2510 for (j = 0; j < 2; j++)
2512 len += strlen (opts[i][j]);
2515 /* Build the string. */
2516 ret = ptr = (char *) xmalloc (len);
2519 for (i = 0; i < num; i++)
2523 for (j = 0; j < 2; j++)
2524 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2531 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2539 for (j = 0; j < 2; j++)
2542 memcpy (ptr, opts[i][j], len2[j]);
2544 line_len += len2[j];
2549 gcc_assert (ret + len >= ptr);
2554 /* Function that is callable from the debugger to print the current
2557 ix86_debug_options (void)
2559 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2560 ix86_arch_string, ix86_tune_string,
2561 ix86_fpmath_string, true);
2565 fprintf (stderr, "%s\n\n", opts);
2569 fputs ("<no options>\n\n", stderr);
2574 /* Sometimes certain combinations of command options do not make
2575 sense on a particular target machine. You can define a macro
2576 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2577 defined, is executed once just after all the command options have
2580 Don't use this macro to turn on various extra optimizations for
2581 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2584 override_options (bool main_args_p)
2587 unsigned int ix86_arch_mask, ix86_tune_mask;
2592 /* Comes from final.c -- no real reason to change it. */
2593 #define MAX_CODE_ALIGN 16
2601 PTA_PREFETCH_SSE = 1 << 4,
2603 PTA_3DNOW_A = 1 << 6,
2607 PTA_POPCNT = 1 << 10,
2609 PTA_SSE4A = 1 << 12,
2610 PTA_NO_SAHF = 1 << 13,
2611 PTA_SSE4_1 = 1 << 14,
2612 PTA_SSE4_2 = 1 << 15,
2614 PTA_PCLMUL = 1 << 17,
2617 PTA_MOVBE = 1 << 20,
2623 const char *const name; /* processor name or nickname. */
2624 const enum processor_type processor;
2625 const enum attr_cpu schedule;
2626 const unsigned /*enum pta_flags*/ flags;
2628 const processor_alias_table[] =
2630 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2631 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2632 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2633 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2634 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2635 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2636 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2637 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2638 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2639 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2640 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2641 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2642 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2644 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2646 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2647 PTA_MMX | PTA_SSE | PTA_SSE2},
2648 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2649 PTA_MMX |PTA_SSE | PTA_SSE2},
2650 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2651 PTA_MMX | PTA_SSE | PTA_SSE2},
2652 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2653 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2654 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2655 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2656 | PTA_CX16 | PTA_NO_SAHF},
2657 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2658 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2659 | PTA_SSSE3 | PTA_CX16},
2660 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2661 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2662 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2663 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2664 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2665 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2666 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2667 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2668 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2669 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2670 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2671 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2672 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2673 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2674 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2675 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2676 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2677 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2678 {"x86-64", PROCESSOR_K8, CPU_K8,
2679 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2680 {"k8", PROCESSOR_K8, CPU_K8,
2681 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2682 | PTA_SSE2 | PTA_NO_SAHF},
2683 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2684 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2685 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2686 {"opteron", PROCESSOR_K8, CPU_K8,
2687 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2688 | PTA_SSE2 | PTA_NO_SAHF},
2689 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2690 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2691 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2692 {"athlon64", PROCESSOR_K8, CPU_K8,
2693 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2694 | PTA_SSE2 | PTA_NO_SAHF},
2695 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2696 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2697 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2698 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2699 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2700 | PTA_SSE2 | PTA_NO_SAHF},
2701 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2702 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2703 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2704 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2705 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2706 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2707 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2708 0 /* flags are only used for -march switch. */ },
2709 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2710 PTA_64BIT /* flags are only used for -march switch. */ },
2713 int const pta_size = ARRAY_SIZE (processor_alias_table);
2715 /* Set up prefix/suffix so the error messages refer to either the command
2716 line argument, or the attribute(target). */
2725 prefix = "option(\"";
2730 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2731 SUBTARGET_OVERRIDE_OPTIONS;
2734 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2735 SUBSUBTARGET_OVERRIDE_OPTIONS;
2738 /* -fPIC is the default for x86_64. */
2739 if (TARGET_MACHO && TARGET_64BIT)
2742 /* Set the default values for switches whose default depends on TARGET_64BIT
2743 in case they weren't overwritten by command line options. */
2746 /* Mach-O doesn't support omitting the frame pointer for now. */
2747 if (flag_omit_frame_pointer == 2)
2748 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2749 if (flag_asynchronous_unwind_tables == 2)
2750 flag_asynchronous_unwind_tables = 1;
2751 if (flag_pcc_struct_return == 2)
2752 flag_pcc_struct_return = 0;
2756 if (flag_omit_frame_pointer == 2)
2757 flag_omit_frame_pointer = 0;
2758 if (flag_asynchronous_unwind_tables == 2)
2759 flag_asynchronous_unwind_tables = 0;
2760 if (flag_pcc_struct_return == 2)
2761 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2764 /* Need to check -mtune=generic first. */
2765 if (ix86_tune_string)
2767 if (!strcmp (ix86_tune_string, "generic")
2768 || !strcmp (ix86_tune_string, "i686")
2769 /* As special support for cross compilers we read -mtune=native
2770 as -mtune=generic. With native compilers we won't see the
2771 -mtune=native, as it was changed by the driver. */
2772 || !strcmp (ix86_tune_string, "native"))
2775 ix86_tune_string = "generic64";
2777 ix86_tune_string = "generic32";
2779 /* If this call is for setting the option attribute, allow the
2780 generic32/generic64 that was previously set. */
2781 else if (!main_args_p
2782 && (!strcmp (ix86_tune_string, "generic32")
2783 || !strcmp (ix86_tune_string, "generic64")))
2785 else if (!strncmp (ix86_tune_string, "generic", 7))
2786 error ("bad value (%s) for %stune=%s %s",
2787 ix86_tune_string, prefix, suffix, sw);
2791 if (ix86_arch_string)
2792 ix86_tune_string = ix86_arch_string;
2793 if (!ix86_tune_string)
2795 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2796 ix86_tune_defaulted = 1;
2799 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2800 need to use a sensible tune option. */
2801 if (!strcmp (ix86_tune_string, "generic")
2802 || !strcmp (ix86_tune_string, "x86-64")
2803 || !strcmp (ix86_tune_string, "i686"))
2806 ix86_tune_string = "generic64";
2808 ix86_tune_string = "generic32";
2811 if (ix86_stringop_string)
2813 if (!strcmp (ix86_stringop_string, "rep_byte"))
2814 stringop_alg = rep_prefix_1_byte;
2815 else if (!strcmp (ix86_stringop_string, "libcall"))
2816 stringop_alg = libcall;
2817 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2818 stringop_alg = rep_prefix_4_byte;
2819 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2821 /* rep; movq isn't available in 32-bit code. */
2822 stringop_alg = rep_prefix_8_byte;
2823 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2824 stringop_alg = loop_1_byte;
2825 else if (!strcmp (ix86_stringop_string, "loop"))
2826 stringop_alg = loop;
2827 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2828 stringop_alg = unrolled_loop;
2830 error ("bad value (%s) for %sstringop-strategy=%s %s",
2831 ix86_stringop_string, prefix, suffix, sw);
2833 if (!strcmp (ix86_tune_string, "x86-64"))
2834 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2835 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2836 prefix, suffix, prefix, suffix, prefix, suffix);
2838 if (!ix86_arch_string)
2839 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2841 ix86_arch_specified = 1;
2843 if (!strcmp (ix86_arch_string, "generic"))
2844 error ("generic CPU can be used only for %stune=%s %s",
2845 prefix, suffix, sw);
2846 if (!strncmp (ix86_arch_string, "generic", 7))
2847 error ("bad value (%s) for %sarch=%s %s",
2848 ix86_arch_string, prefix, suffix, sw);
2850 /* Validate -mabi= value. */
2851 if (ix86_abi_string)
2853 if (strcmp (ix86_abi_string, "sysv") == 0)
2854 ix86_abi = SYSV_ABI;
2855 else if (strcmp (ix86_abi_string, "ms") == 0)
2858 error ("unknown ABI (%s) for %sabi=%s %s",
2859 ix86_abi_string, prefix, suffix, sw);
2862 ix86_abi = DEFAULT_ABI;
2864 if (ix86_cmodel_string != 0)
2866 if (!strcmp (ix86_cmodel_string, "small"))
2867 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2868 else if (!strcmp (ix86_cmodel_string, "medium"))
2869 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2870 else if (!strcmp (ix86_cmodel_string, "large"))
2871 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2873 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2874 else if (!strcmp (ix86_cmodel_string, "32"))
2875 ix86_cmodel = CM_32;
2876 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2877 ix86_cmodel = CM_KERNEL;
2879 error ("bad value (%s) for %scmodel=%s %s",
2880 ix86_cmodel_string, prefix, suffix, sw);
2884 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2885 use of rip-relative addressing. This eliminates fixups that
2886 would otherwise be needed if this object is to be placed in a
2887 DLL, and is essentially just as efficient as direct addressing. */
2888 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2889 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2890 else if (TARGET_64BIT)
2891 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2893 ix86_cmodel = CM_32;
2895 if (ix86_asm_string != 0)
2898 && !strcmp (ix86_asm_string, "intel"))
2899 ix86_asm_dialect = ASM_INTEL;
2900 else if (!strcmp (ix86_asm_string, "att"))
2901 ix86_asm_dialect = ASM_ATT;
2903 error ("bad value (%s) for %sasm=%s %s",
2904 ix86_asm_string, prefix, suffix, sw);
2906 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2907 error ("code model %qs not supported in the %s bit mode",
2908 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2909 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2910 sorry ("%i-bit mode not compiled in",
2911 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2913 for (i = 0; i < pta_size; i++)
2914 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2916 ix86_schedule = processor_alias_table[i].schedule;
2917 ix86_arch = processor_alias_table[i].processor;
2918 /* Default cpu tuning to the architecture. */
2919 ix86_tune = ix86_arch;
2921 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2922 error ("CPU you selected does not support x86-64 "
2925 if (processor_alias_table[i].flags & PTA_MMX
2926 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2927 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2928 if (processor_alias_table[i].flags & PTA_3DNOW
2929 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2930 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2931 if (processor_alias_table[i].flags & PTA_3DNOW_A
2932 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2933 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2934 if (processor_alias_table[i].flags & PTA_SSE
2935 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2936 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2937 if (processor_alias_table[i].flags & PTA_SSE2
2938 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2939 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2940 if (processor_alias_table[i].flags & PTA_SSE3
2941 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2942 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2943 if (processor_alias_table[i].flags & PTA_SSSE3
2944 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2945 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2946 if (processor_alias_table[i].flags & PTA_SSE4_1
2947 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2948 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2949 if (processor_alias_table[i].flags & PTA_SSE4_2
2950 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2951 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2952 if (processor_alias_table[i].flags & PTA_AVX
2953 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2954 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2955 if (processor_alias_table[i].flags & PTA_FMA
2956 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2957 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2958 if (processor_alias_table[i].flags & PTA_SSE4A
2959 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2960 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2961 if (processor_alias_table[i].flags & PTA_FMA4
2962 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
2963 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
2964 if (processor_alias_table[i].flags & PTA_ABM
2965 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2966 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2967 if (processor_alias_table[i].flags & PTA_CX16
2968 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2969 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2970 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2971 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2972 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2973 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2974 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2975 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2976 if (processor_alias_table[i].flags & PTA_MOVBE
2977 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2978 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2979 if (processor_alias_table[i].flags & PTA_AES
2980 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2981 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2982 if (processor_alias_table[i].flags & PTA_PCLMUL
2983 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2984 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2985 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2986 x86_prefetch_sse = true;
2992 error ("bad value (%s) for %sarch=%s %s",
2993 ix86_arch_string, prefix, suffix, sw);
2995 ix86_arch_mask = 1u << ix86_arch;
2996 for (i = 0; i < X86_ARCH_LAST; ++i)
2997 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2999 for (i = 0; i < pta_size; i++)
3000 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3002 ix86_schedule = processor_alias_table[i].schedule;
3003 ix86_tune = processor_alias_table[i].processor;
3004 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3006 if (ix86_tune_defaulted)
3008 ix86_tune_string = "x86-64";
3009 for (i = 0; i < pta_size; i++)
3010 if (! strcmp (ix86_tune_string,
3011 processor_alias_table[i].name))
3013 ix86_schedule = processor_alias_table[i].schedule;
3014 ix86_tune = processor_alias_table[i].processor;
3017 error ("CPU you selected does not support x86-64 "
3020 /* Intel CPUs have always interpreted SSE prefetch instructions as
3021 NOPs; so, we can enable SSE prefetch instructions even when
3022 -mtune (rather than -march) points us to a processor that has them.
3023 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3024 higher processors. */
3026 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3027 x86_prefetch_sse = true;
3031 error ("bad value (%s) for %stune=%s %s",
3032 ix86_tune_string, prefix, suffix, sw);
3034 ix86_tune_mask = 1u << ix86_tune;
3035 for (i = 0; i < X86_TUNE_LAST; ++i)
3036 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3039 ix86_cost = &ix86_size_cost;
3041 ix86_cost = processor_target_table[ix86_tune].cost;
3043 /* Arrange to set up i386_stack_locals for all functions. */
3044 init_machine_status = ix86_init_machine_status;
3046 /* Validate -mregparm= value. */
3047 if (ix86_regparm_string)
3050 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3051 i = atoi (ix86_regparm_string);
3052 if (i < 0 || i > REGPARM_MAX)
3053 error ("%sregparm=%d%s is not between 0 and %d",
3054 prefix, i, suffix, REGPARM_MAX);
3059 ix86_regparm = REGPARM_MAX;
3061 /* If the user has provided any of the -malign-* options,
3062 warn and use that value only if -falign-* is not set.
3063 Remove this code in GCC 3.2 or later. */
3064 if (ix86_align_loops_string)
3066 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3067 prefix, suffix, suffix);
3068 if (align_loops == 0)
3070 i = atoi (ix86_align_loops_string);
3071 if (i < 0 || i > MAX_CODE_ALIGN)
3072 error ("%salign-loops=%d%s is not between 0 and %d",
3073 prefix, i, suffix, MAX_CODE_ALIGN);
3075 align_loops = 1 << i;
3079 if (ix86_align_jumps_string)
3081 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3082 prefix, suffix, suffix);
3083 if (align_jumps == 0)
3085 i = atoi (ix86_align_jumps_string);
3086 if (i < 0 || i > MAX_CODE_ALIGN)
3087 error ("%salign-loops=%d%s is not between 0 and %d",
3088 prefix, i, suffix, MAX_CODE_ALIGN);
3090 align_jumps = 1 << i;
3094 if (ix86_align_funcs_string)
3096 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3097 prefix, suffix, suffix);
3098 if (align_functions == 0)
3100 i = atoi (ix86_align_funcs_string);
3101 if (i < 0 || i > MAX_CODE_ALIGN)
3102 error ("%salign-loops=%d%s is not between 0 and %d",
3103 prefix, i, suffix, MAX_CODE_ALIGN);
3105 align_functions = 1 << i;
3109 /* Default align_* from the processor table. */
3110 if (align_loops == 0)
3112 align_loops = processor_target_table[ix86_tune].align_loop;
3113 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3115 if (align_jumps == 0)
3117 align_jumps = processor_target_table[ix86_tune].align_jump;
3118 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3120 if (align_functions == 0)
3122 align_functions = processor_target_table[ix86_tune].align_func;
3125 /* Validate -mbranch-cost= value, or provide default. */
3126 ix86_branch_cost = ix86_cost->branch_cost;
3127 if (ix86_branch_cost_string)
3129 i = atoi (ix86_branch_cost_string);
3131 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3133 ix86_branch_cost = i;
3135 if (ix86_section_threshold_string)
3137 i = atoi (ix86_section_threshold_string);
3139 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3141 ix86_section_threshold = i;
3144 if (ix86_tls_dialect_string)
3146 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3147 ix86_tls_dialect = TLS_DIALECT_GNU;
3148 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3149 ix86_tls_dialect = TLS_DIALECT_GNU2;
3150 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3151 ix86_tls_dialect = TLS_DIALECT_SUN;
3153 error ("bad value (%s) for %stls-dialect=%s %s",
3154 ix86_tls_dialect_string, prefix, suffix, sw);
3157 if (ix87_precision_string)
3159 i = atoi (ix87_precision_string);
3160 if (i != 32 && i != 64 && i != 80)
3161 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3166 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3168 /* Enable by default the SSE and MMX builtins. Do allow the user to
3169 explicitly disable any of these. In particular, disabling SSE and
3170 MMX for kernel code is extremely useful. */
3171 if (!ix86_arch_specified)
3173 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3174 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3177 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3181 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3183 if (!ix86_arch_specified)
3185 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3187 /* i386 ABI does not specify red zone. It still makes sense to use it
3188 when programmer takes care to stack from being destroyed. */
3189 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3190 target_flags |= MASK_NO_RED_ZONE;
3193 /* Keep nonleaf frame pointers. */
3194 if (flag_omit_frame_pointer)
3195 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3196 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3197 flag_omit_frame_pointer = 1;
3199 /* If we're doing fast math, we don't care about comparison order
3200 wrt NaNs. This lets us use a shorter comparison sequence. */
3201 if (flag_finite_math_only)
3202 target_flags &= ~MASK_IEEE_FP;
3204 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3205 since the insns won't need emulation. */
3206 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3207 target_flags &= ~MASK_NO_FANCY_MATH_387;
3209 /* Likewise, if the target doesn't have a 387, or we've specified
3210 software floating point, don't use 387 inline intrinsics. */
3212 target_flags |= MASK_NO_FANCY_MATH_387;
3214 /* Turn on MMX builtins for -msse. */
3217 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3218 x86_prefetch_sse = true;
3221 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3222 if (TARGET_SSE4_2 || TARGET_ABM)
3223 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3225 /* Validate -mpreferred-stack-boundary= value or default it to
3226 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3227 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3228 if (ix86_preferred_stack_boundary_string)
3230 i = atoi (ix86_preferred_stack_boundary_string);
3231 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3232 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3233 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3235 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3238 /* Set the default value for -mstackrealign. */
3239 if (ix86_force_align_arg_pointer == -1)
3240 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3242 /* Validate -mincoming-stack-boundary= value or default it to
3243 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3244 if (ix86_force_align_arg_pointer)
3245 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3247 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3248 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3249 if (ix86_incoming_stack_boundary_string)
3251 i = atoi (ix86_incoming_stack_boundary_string);
3252 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3253 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3254 i, TARGET_64BIT ? 4 : 2);
3257 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3258 ix86_incoming_stack_boundary
3259 = ix86_user_incoming_stack_boundary;
3263 /* Accept -msseregparm only if at least SSE support is enabled. */
3264 if (TARGET_SSEREGPARM
3266 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3268 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3269 if (ix86_fpmath_string != 0)
3271 if (! strcmp (ix86_fpmath_string, "387"))
3272 ix86_fpmath = FPMATH_387;
3273 else if (! strcmp (ix86_fpmath_string, "sse"))
3277 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3278 ix86_fpmath = FPMATH_387;
3281 ix86_fpmath = FPMATH_SSE;
3283 else if (! strcmp (ix86_fpmath_string, "387,sse")
3284 || ! strcmp (ix86_fpmath_string, "387+sse")
3285 || ! strcmp (ix86_fpmath_string, "sse,387")
3286 || ! strcmp (ix86_fpmath_string, "sse+387")
3287 || ! strcmp (ix86_fpmath_string, "both"))
3291 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3292 ix86_fpmath = FPMATH_387;
3294 else if (!TARGET_80387)
3296 warning (0, "387 instruction set disabled, using SSE arithmetics");
3297 ix86_fpmath = FPMATH_SSE;
3300 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3303 error ("bad value (%s) for %sfpmath=%s %s",
3304 ix86_fpmath_string, prefix, suffix, sw);
3307 /* If the i387 is disabled, then do not return values in it. */
3309 target_flags &= ~MASK_FLOAT_RETURNS;
3311 /* Use external vectorized library in vectorizing intrinsics. */
3312 if (ix86_veclibabi_string)
3314 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3315 ix86_veclib_handler = ix86_veclibabi_svml;
3316 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3317 ix86_veclib_handler = ix86_veclibabi_acml;
3319 error ("unknown vectorization library ABI type (%s) for "
3320 "%sveclibabi=%s %s", ix86_veclibabi_string,
3321 prefix, suffix, sw);
3324 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3325 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3327 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3329 /* ??? Unwind info is not correct around the CFG unless either a frame
3330 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3331 unwind info generation to be aware of the CFG and propagating states
3333 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3334 || flag_exceptions || flag_non_call_exceptions)
3335 && flag_omit_frame_pointer
3336 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3338 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3339 warning (0, "unwind tables currently require either a frame pointer "
3340 "or %saccumulate-outgoing-args%s for correctness",
3342 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3345 /* If stack probes are required, the space used for large function
3346 arguments on the stack must also be probed, so enable
3347 -maccumulate-outgoing-args so this happens in the prologue. */
3348 if (TARGET_STACK_PROBE
3349 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3351 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3352 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3353 "for correctness", prefix, suffix);
3354 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3357 /* For sane SSE instruction set generation we need fcomi instruction.
3358 It is safe to enable all CMOVE instructions. */
3362 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3365 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3366 p = strchr (internal_label_prefix, 'X');
3367 internal_label_prefix_len = p - internal_label_prefix;
3371 /* When scheduling description is not available, disable scheduler pass
3372 so it won't slow down the compilation and make x87 code slower. */
3373 if (!TARGET_SCHEDULE)
3374 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3376 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3377 set_param_value ("simultaneous-prefetches",
3378 ix86_cost->simultaneous_prefetches);
3379 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3380 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3381 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3382 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3383 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3384 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3386 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3387 can be optimized to ap = __builtin_next_arg (0). */
3389 targetm.expand_builtin_va_start = NULL;
3393 ix86_gen_leave = gen_leave_rex64;
3394 ix86_gen_pop1 = gen_popdi1;
3395 ix86_gen_add3 = gen_adddi3;
3396 ix86_gen_sub3 = gen_subdi3;
3397 ix86_gen_sub3_carry = gen_subdi3_carry;
3398 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3399 ix86_gen_monitor = gen_sse3_monitor64;
3400 ix86_gen_andsp = gen_anddi3;
3404 ix86_gen_leave = gen_leave;
3405 ix86_gen_pop1 = gen_popsi1;
3406 ix86_gen_add3 = gen_addsi3;
3407 ix86_gen_sub3 = gen_subsi3;
3408 ix86_gen_sub3_carry = gen_subsi3_carry;
3409 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3410 ix86_gen_monitor = gen_sse3_monitor;
3411 ix86_gen_andsp = gen_andsi3;
3415 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3417 target_flags |= MASK_CLD & ~target_flags_explicit;
3420 /* Save the initial options in case the user does function specific options */
3422 target_option_default_node = target_option_current_node
3423 = build_target_option_node ();
3426 /* Update register usage after having seen the compiler flags. */
3429 ix86_conditional_register_usage (void)
3434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3436 if (fixed_regs[i] > 1)
3437 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3438 if (call_used_regs[i] > 1)
3439 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3442 /* The PIC register, if it exists, is fixed. */
3443 j = PIC_OFFSET_TABLE_REGNUM;
3444 if (j != INVALID_REGNUM)
3445 fixed_regs[j] = call_used_regs[j] = 1;
3447 /* The MS_ABI changes the set of call-used registers. */
3448 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3450 call_used_regs[SI_REG] = 0;
3451 call_used_regs[DI_REG] = 0;
3452 call_used_regs[XMM6_REG] = 0;
3453 call_used_regs[XMM7_REG] = 0;
3454 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3455 call_used_regs[i] = 0;
3458 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3459 other call-clobbered regs for 64-bit. */
3462 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3465 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3466 && call_used_regs[i])
3467 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3470 /* If MMX is disabled, squash the registers. */
3472 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3473 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3474 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3476 /* If SSE is disabled, squash the registers. */
3478 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3479 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3480 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3482 /* If the FPU is disabled, squash the registers. */
3483 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3485 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3486 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3488 /* If 32-bit, squash the 64-bit registers. */
3491 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3493 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3499 /* Save the current options */
3502 ix86_function_specific_save (struct cl_target_option *ptr)
3504 ptr->arch = ix86_arch;
3505 ptr->schedule = ix86_schedule;
3506 ptr->tune = ix86_tune;
3507 ptr->fpmath = ix86_fpmath;
3508 ptr->branch_cost = ix86_branch_cost;
3509 ptr->tune_defaulted = ix86_tune_defaulted;
3510 ptr->arch_specified = ix86_arch_specified;
3511 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3512 ptr->target_flags_explicit = target_flags_explicit;
3514 /* The fields are char but the variables are not; make sure the
3515 values fit in the fields. */
3516 gcc_assert (ptr->arch == ix86_arch);
3517 gcc_assert (ptr->schedule == ix86_schedule);
3518 gcc_assert (ptr->tune == ix86_tune);
3519 gcc_assert (ptr->fpmath == ix86_fpmath);
3520 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3523 /* Restore the current options */
3526 ix86_function_specific_restore (struct cl_target_option *ptr)
3528 enum processor_type old_tune = ix86_tune;
3529 enum processor_type old_arch = ix86_arch;
3530 unsigned int ix86_arch_mask, ix86_tune_mask;
3533 ix86_arch = (enum processor_type) ptr->arch;
3534 ix86_schedule = (enum attr_cpu) ptr->schedule;
3535 ix86_tune = (enum processor_type) ptr->tune;
3536 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3537 ix86_branch_cost = ptr->branch_cost;
3538 ix86_tune_defaulted = ptr->tune_defaulted;
3539 ix86_arch_specified = ptr->arch_specified;
3540 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3541 target_flags_explicit = ptr->target_flags_explicit;
3543 /* Recreate the arch feature tests if the arch changed */
3544 if (old_arch != ix86_arch)
3546 ix86_arch_mask = 1u << ix86_arch;
3547 for (i = 0; i < X86_ARCH_LAST; ++i)
3548 ix86_arch_features[i]
3549 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3552 /* Recreate the tune optimization tests */
3553 if (old_tune != ix86_tune)
3555 ix86_tune_mask = 1u << ix86_tune;
3556 for (i = 0; i < X86_TUNE_LAST; ++i)
3557 ix86_tune_features[i]
3558 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3562 /* Print the current options */
3565 ix86_function_specific_print (FILE *file, int indent,
3566 struct cl_target_option *ptr)
3569 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3570 NULL, NULL, NULL, false);
3572 fprintf (file, "%*sarch = %d (%s)\n",
3575 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3576 ? cpu_names[ptr->arch]
3579 fprintf (file, "%*stune = %d (%s)\n",
3582 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3583 ? cpu_names[ptr->tune]
3586 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3587 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3588 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3589 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3593 fprintf (file, "%*s%s\n", indent, "", target_string);
3594 free (target_string);
3599 /* Inner function to process the attribute((target(...))), take an argument and
3600 set the current options from the argument. If we have a list, recursively go
3604 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3609 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3610 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3611 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3612 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3627 enum ix86_opt_type type;
3632 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3633 IX86_ATTR_ISA ("abm", OPT_mabm),
3634 IX86_ATTR_ISA ("aes", OPT_maes),
3635 IX86_ATTR_ISA ("avx", OPT_mavx),
3636 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3637 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3638 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3639 IX86_ATTR_ISA ("sse", OPT_msse),
3640 IX86_ATTR_ISA ("sse2", OPT_msse2),
3641 IX86_ATTR_ISA ("sse3", OPT_msse3),
3642 IX86_ATTR_ISA ("sse4", OPT_msse4),
3643 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3644 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3645 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3646 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3647 IX86_ATTR_ISA ("fma4", OPT_mfma4),
3649 /* string options */
3650 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3651 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3652 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3655 IX86_ATTR_YES ("cld",
3659 IX86_ATTR_NO ("fancy-math-387",
3660 OPT_mfancy_math_387,
3661 MASK_NO_FANCY_MATH_387),
3663 IX86_ATTR_YES ("ieee-fp",
3667 IX86_ATTR_YES ("inline-all-stringops",
3668 OPT_minline_all_stringops,
3669 MASK_INLINE_ALL_STRINGOPS),
3671 IX86_ATTR_YES ("inline-stringops-dynamically",
3672 OPT_minline_stringops_dynamically,
3673 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3675 IX86_ATTR_NO ("align-stringops",
3676 OPT_mno_align_stringops,
3677 MASK_NO_ALIGN_STRINGOPS),
3679 IX86_ATTR_YES ("recip",
3685 /* If this is a list, recurse to get the options. */
3686 if (TREE_CODE (args) == TREE_LIST)
3690 for (; args; args = TREE_CHAIN (args))
3691 if (TREE_VALUE (args)
3692 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3698 else if (TREE_CODE (args) != STRING_CST)
3701 /* Handle multiple arguments separated by commas. */
3702 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3704 while (next_optstr && *next_optstr != '\0')
3706 char *p = next_optstr;
3708 char *comma = strchr (next_optstr, ',');
3709 const char *opt_string;
3710 size_t len, opt_len;
3715 enum ix86_opt_type type = ix86_opt_unknown;
3721 len = comma - next_optstr;
3722 next_optstr = comma + 1;
3730 /* Recognize no-xxx. */
3731 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3740 /* Find the option. */
3743 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3745 type = attrs[i].type;
3746 opt_len = attrs[i].len;
3747 if (ch == attrs[i].string[0]
3748 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3749 && memcmp (p, attrs[i].string, opt_len) == 0)
3752 mask = attrs[i].mask;
3753 opt_string = attrs[i].string;
3758 /* Process the option. */
3761 error ("attribute(target(\"%s\")) is unknown", orig_p);
3765 else if (type == ix86_opt_isa)
3766 ix86_handle_option (opt, p, opt_set_p);
3768 else if (type == ix86_opt_yes || type == ix86_opt_no)
3770 if (type == ix86_opt_no)
3771 opt_set_p = !opt_set_p;
3774 target_flags |= mask;
3776 target_flags &= ~mask;
3779 else if (type == ix86_opt_str)
3783 error ("option(\"%s\") was already specified", opt_string);
3787 p_strings[opt] = xstrdup (p + opt_len);
3797 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3800 ix86_valid_target_attribute_tree (tree args)
3802 const char *orig_arch_string = ix86_arch_string;
3803 const char *orig_tune_string = ix86_tune_string;
3804 const char *orig_fpmath_string = ix86_fpmath_string;
3805 int orig_tune_defaulted = ix86_tune_defaulted;
3806 int orig_arch_specified = ix86_arch_specified;
3807 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3810 struct cl_target_option *def
3811 = TREE_TARGET_OPTION (target_option_default_node);
3813 /* Process each of the options on the chain. */
3814 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3817 /* If the changed options are different from the default, rerun override_options,
3818 and then save the options away. The string options are are attribute options,
3819 and will be undone when we copy the save structure. */
3820 if (ix86_isa_flags != def->ix86_isa_flags
3821 || target_flags != def->target_flags
3822 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3823 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3824 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3826 /* If we are using the default tune= or arch=, undo the string assigned,
3827 and use the default. */
3828 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3829 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3830 else if (!orig_arch_specified)
3831 ix86_arch_string = NULL;
3833 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3834 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3835 else if (orig_tune_defaulted)
3836 ix86_tune_string = NULL;
3838 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3839 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3840 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3841 else if (!TARGET_64BIT && TARGET_SSE)
3842 ix86_fpmath_string = "sse,387";
3844 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3845 override_options (false);
3847 /* Add any builtin functions with the new isa if any. */
3848 ix86_add_new_builtins (ix86_isa_flags);
3850 /* Save the current options unless we are validating options for
3852 t = build_target_option_node ();
3854 ix86_arch_string = orig_arch_string;
3855 ix86_tune_string = orig_tune_string;
3856 ix86_fpmath_string = orig_fpmath_string;
3858 /* Free up memory allocated to hold the strings */
3859 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3860 if (option_strings[i])
3861 free (option_strings[i]);
3867 /* Hook to validate attribute((target("string"))). */
3870 ix86_valid_target_attribute_p (tree fndecl,
3871 tree ARG_UNUSED (name),
3873 int ARG_UNUSED (flags))
3875 struct cl_target_option cur_target;
3877 tree old_optimize = build_optimization_node ();
3878 tree new_target, new_optimize;
3879 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3881 /* If the function changed the optimization levels as well as setting target
3882 options, start with the optimizations specified. */
3883 if (func_optimize && func_optimize != old_optimize)
3884 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3886 /* The target attributes may also change some optimization flags, so update
3887 the optimization options if necessary. */
3888 cl_target_option_save (&cur_target);
3889 new_target = ix86_valid_target_attribute_tree (args);
3890 new_optimize = build_optimization_node ();
3897 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3899 if (old_optimize != new_optimize)
3900 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3903 cl_target_option_restore (&cur_target);
3905 if (old_optimize != new_optimize)
3906 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3912 /* Hook to determine if one function can safely inline another. */
3915 ix86_can_inline_p (tree caller, tree callee)
3918 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3919 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3921 /* If callee has no option attributes, then it is ok to inline. */
3925 /* If caller has no option attributes, but callee does then it is not ok to
3927 else if (!caller_tree)
3932 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3933 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3935 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3936 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3938 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3939 != callee_opts->ix86_isa_flags)
3942 /* See if we have the same non-isa options. */
3943 else if (caller_opts->target_flags != callee_opts->target_flags)
3946 /* See if arch, tune, etc. are the same. */
3947 else if (caller_opts->arch != callee_opts->arch)
3950 else if (caller_opts->tune != callee_opts->tune)
3953 else if (caller_opts->fpmath != callee_opts->fpmath)
3956 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3967 /* Remember the last target of ix86_set_current_function. */
3968 static GTY(()) tree ix86_previous_fndecl;
3970 /* Establish appropriate back-end context for processing the function
3971 FNDECL. The argument might be NULL to indicate processing at top
3972 level, outside of any function scope. */
3974 ix86_set_current_function (tree fndecl)
3976 /* Only change the context if the function changes. This hook is called
3977 several times in the course of compiling a function, and we don't want to
3978 slow things down too much or call target_reinit when it isn't safe. */
3979 if (fndecl && fndecl != ix86_previous_fndecl)
3981 tree old_tree = (ix86_previous_fndecl
3982 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3985 tree new_tree = (fndecl
3986 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3989 ix86_previous_fndecl = fndecl;
3990 if (old_tree == new_tree)
3995 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
4001 struct cl_target_option *def
4002 = TREE_TARGET_OPTION (target_option_current_node);
4004 cl_target_option_restore (def);
4011 /* Return true if this goes in large data/bss. */
4014 ix86_in_large_data_p (tree exp)
4016 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4019 /* Functions are never large data. */
4020 if (TREE_CODE (exp) == FUNCTION_DECL)
4023 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4025 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4026 if (strcmp (section, ".ldata") == 0
4027 || strcmp (section, ".lbss") == 0)
4033 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4035 /* If this is an incomplete type with size 0, then we can't put it
4036 in data because it might be too big when completed. */
4037 if (!size || size > ix86_section_threshold)
4044 /* Switch to the appropriate section for output of DECL.
4045 DECL is either a `VAR_DECL' node or a constant of some sort.
4046 RELOC indicates whether forming the initial value of DECL requires
4047 link-time relocations. */
4049 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4053 x86_64_elf_select_section (tree decl, int reloc,
4054 unsigned HOST_WIDE_INT align)
4056 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4057 && ix86_in_large_data_p (decl))
4059 const char *sname = NULL;
4060 unsigned int flags = SECTION_WRITE;
4061 switch (categorize_decl_for_section (decl, reloc))
4066 case SECCAT_DATA_REL:
4067 sname = ".ldata.rel";
4069 case SECCAT_DATA_REL_LOCAL:
4070 sname = ".ldata.rel.local";
4072 case SECCAT_DATA_REL_RO:
4073 sname = ".ldata.rel.ro";
4075 case SECCAT_DATA_REL_RO_LOCAL:
4076 sname = ".ldata.rel.ro.local";
4080 flags |= SECTION_BSS;
4083 case SECCAT_RODATA_MERGE_STR:
4084 case SECCAT_RODATA_MERGE_STR_INIT:
4085 case SECCAT_RODATA_MERGE_CONST:
4089 case SECCAT_SRODATA:
4096 /* We don't split these for medium model. Place them into
4097 default sections and hope for best. */
4099 case SECCAT_EMUTLS_VAR:
4100 case SECCAT_EMUTLS_TMPL:
4105 /* We might get called with string constants, but get_named_section
4106 doesn't like them as they are not DECLs. Also, we need to set
4107 flags in that case. */
4109 return get_section (sname, flags, NULL);
4110 return get_named_section (decl, sname, reloc);
4113 return default_elf_select_section (decl, reloc, align);
4116 /* Build up a unique section name, expressed as a
4117 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4118 RELOC indicates whether the initial value of EXP requires
4119 link-time relocations. */
4121 static void ATTRIBUTE_UNUSED
4122 x86_64_elf_unique_section (tree decl, int reloc)
4124 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4125 && ix86_in_large_data_p (decl))
4127 const char *prefix = NULL;
4128 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4129 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4131 switch (categorize_decl_for_section (decl, reloc))
4134 case SECCAT_DATA_REL:
4135 case SECCAT_DATA_REL_LOCAL:
4136 case SECCAT_DATA_REL_RO:
4137 case SECCAT_DATA_REL_RO_LOCAL:
4138 prefix = one_only ? ".ld" : ".ldata";
4141 prefix = one_only ? ".lb" : ".lbss";
4144 case SECCAT_RODATA_MERGE_STR:
4145 case SECCAT_RODATA_MERGE_STR_INIT:
4146 case SECCAT_RODATA_MERGE_CONST:
4147 prefix = one_only ? ".lr" : ".lrodata";
4149 case SECCAT_SRODATA:
4156 /* We don't split these for medium model. Place them into
4157 default sections and hope for best. */
4159 case SECCAT_EMUTLS_VAR:
4160 prefix = targetm.emutls.var_section;
4162 case SECCAT_EMUTLS_TMPL:
4163 prefix = targetm.emutls.tmpl_section;
4168 const char *name, *linkonce;
4171 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4172 name = targetm.strip_name_encoding (name);
4174 /* If we're using one_only, then there needs to be a .gnu.linkonce
4175 prefix to the section name. */
4176 linkonce = one_only ? ".gnu.linkonce" : "";
4178 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4180 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4184 default_unique_section (decl, reloc);
4187 #ifdef COMMON_ASM_OP
4188 /* This says how to output assembler code to declare an
4189 uninitialized external linkage data object.
4191 For medium model x86-64 we need to use .largecomm opcode for
4194 x86_elf_aligned_common (FILE *file,
4195 const char *name, unsigned HOST_WIDE_INT size,
4198 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4199 && size > (unsigned int)ix86_section_threshold)
4200 fputs (".largecomm\t", file);
4202 fputs (COMMON_ASM_OP, file);
4203 assemble_name (file, name);
4204 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4205 size, align / BITS_PER_UNIT);
4209 /* Utility function for targets to use in implementing
4210 ASM_OUTPUT_ALIGNED_BSS. */
4213 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4214 const char *name, unsigned HOST_WIDE_INT size,
4217 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4218 && size > (unsigned int)ix86_section_threshold)
4219 switch_to_section (get_named_section (decl, ".lbss", 0));
4221 switch_to_section (bss_section);
4222 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4223 #ifdef ASM_DECLARE_OBJECT_NAME
4224 last_assemble_variable_decl = decl;
4225 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4227 /* Standard thing is just output label for the object. */
4228 ASM_OUTPUT_LABEL (file, name);
4229 #endif /* ASM_DECLARE_OBJECT_NAME */
4230 ASM_OUTPUT_SKIP (file, size ? size : 1);
4234 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4236 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4237 make the problem with not enough registers even worse. */
4238 #ifdef INSN_SCHEDULING
4240 flag_schedule_insns = 0;
4244 /* The Darwin libraries never set errno, so we might as well
4245 avoid calling them when that's the only reason we would. */
4246 flag_errno_math = 0;
4248 /* The default values of these switches depend on the TARGET_64BIT
4249 that is not known at this moment. Mark these values with 2 and
4250 let user the to override these. In case there is no command line option
4251 specifying them, we will set the defaults in override_options. */
4253 flag_omit_frame_pointer = 2;
4254 flag_pcc_struct_return = 2;
4255 flag_asynchronous_unwind_tables = 2;
4256 flag_vect_cost_model = 1;
4257 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4258 SUBTARGET_OPTIMIZATION_OPTIONS;
4262 /* Decide whether we can make a sibling call to a function. DECL is the
4263 declaration of the function being targeted by the call and EXP is the
4264 CALL_EXPR representing the call. */
4267 ix86_function_ok_for_sibcall (tree decl, tree exp)
4269 tree type, decl_or_type;
4272 /* If we are generating position-independent code, we cannot sibcall
4273 optimize any indirect call, or a direct call to a global function,
4274 as the PLT requires %ebx be live. */
4275 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4278 /* If we need to align the outgoing stack, then sibcalling would
4279 unalign the stack, which may break the called function. */
4280 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4285 decl_or_type = decl;
4286 type = TREE_TYPE (decl);
4290 /* We're looking at the CALL_EXPR, we need the type of the function. */
4291 type = CALL_EXPR_FN (exp); /* pointer expression */
4292 type = TREE_TYPE (type); /* pointer type */
4293 type = TREE_TYPE (type); /* function type */
4294 decl_or_type = type;
4297 /* Check that the return value locations are the same. Like
4298 if we are returning floats on the 80387 register stack, we cannot
4299 make a sibcall from a function that doesn't return a float to a
4300 function that does or, conversely, from a function that does return
4301 a float to a function that doesn't; the necessary stack adjustment
4302 would not be executed. This is also the place we notice
4303 differences in the return value ABI. Note that it is ok for one
4304 of the functions to have void return type as long as the return
4305 value of the other is passed in a register. */
4306 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4307 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4309 if (STACK_REG_P (a) || STACK_REG_P (b))
4311 if (!rtx_equal_p (a, b))
4314 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4316 else if (!rtx_equal_p (a, b))
4321 /* The SYSV ABI has more call-clobbered registers;
4322 disallow sibcalls from MS to SYSV. */
4323 if (cfun->machine->call_abi == MS_ABI
4324 && ix86_function_type_abi (type) == SYSV_ABI)
4329 /* If this call is indirect, we'll need to be able to use a
4330 call-clobbered register for the address of the target function.
4331 Make sure that all such registers are not used for passing
4332 parameters. Note that DLLIMPORT functions are indirect. */
4334 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4336 if (ix86_function_regparm (type, NULL) >= 3)
4338 /* ??? Need to count the actual number of registers to be used,
4339 not the possible number of registers. Fix later. */
4345 /* Otherwise okay. That also includes certain types of indirect calls. */
4349 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4350 calling convention attributes;
4351 arguments as in struct attribute_spec.handler. */
4354 ix86_handle_cconv_attribute (tree *node, tree name,
4356 int flags ATTRIBUTE_UNUSED,
4359 if (TREE_CODE (*node) != FUNCTION_TYPE
4360 && TREE_CODE (*node) != METHOD_TYPE
4361 && TREE_CODE (*node) != FIELD_DECL
4362 && TREE_CODE (*node) != TYPE_DECL)
4364 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4366 *no_add_attrs = true;
4370 /* Can combine regparm with all attributes but fastcall. */
4371 if (is_attribute_p ("regparm", name))
4375 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4377 error ("fastcall and regparm attributes are not compatible");
4380 cst = TREE_VALUE (args);
4381 if (TREE_CODE (cst) != INTEGER_CST)
4383 warning (OPT_Wattributes,
4384 "%qE attribute requires an integer constant argument",
4386 *no_add_attrs = true;
4388 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4390 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4392 *no_add_attrs = true;
4400 /* Do not warn when emulating the MS ABI. */
4401 if (TREE_CODE (*node) != FUNCTION_TYPE
4402 || ix86_function_type_abi (*node) != MS_ABI)
4403 warning (OPT_Wattributes, "%qE attribute ignored",
4405 *no_add_attrs = true;
4409 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4410 if (is_attribute_p ("fastcall", name))
4412 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4414 error ("fastcall and cdecl attributes are not compatible");
4416 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4418 error ("fastcall and stdcall attributes are not compatible");
4420 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4422 error ("fastcall and regparm attributes are not compatible");
4426 /* Can combine stdcall with fastcall (redundant), regparm and
4428 else if (is_attribute_p ("stdcall", name))
4430 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4432 error ("stdcall and cdecl attributes are not compatible");
4434 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4436 error ("stdcall and fastcall attributes are not compatible");
4440 /* Can combine cdecl with regparm and sseregparm. */
4441 else if (is_attribute_p ("cdecl", name))
4443 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4445 error ("stdcall and cdecl attributes are not compatible");
4447 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4449 error ("fastcall and cdecl attributes are not compatible");
4453 /* Can combine sseregparm with all attributes. */
4458 /* Return 0 if the attributes for two types are incompatible, 1 if they
4459 are compatible, and 2 if they are nearly compatible (which causes a
4460 warning to be generated). */
4463 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4465 /* Check for mismatch of non-default calling convention. */
4466 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4468 if (TREE_CODE (type1) != FUNCTION_TYPE
4469 && TREE_CODE (type1) != METHOD_TYPE)
4472 /* Check for mismatched fastcall/regparm types. */
4473 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4474 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4475 || (ix86_function_regparm (type1, NULL)
4476 != ix86_function_regparm (type2, NULL)))
4479 /* Check for mismatched sseregparm types. */
4480 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4481 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4484 /* Check for mismatched return types (cdecl vs stdcall). */
4485 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4486 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4492 /* Return the regparm value for a function with the indicated TYPE and DECL.
4493 DECL may be NULL when calling function indirectly
4494 or considering a libcall. */
4497 ix86_function_regparm (const_tree type, const_tree decl)
4503 return (ix86_function_type_abi (type) == SYSV_ABI
4504 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4506 regparm = ix86_regparm;
4507 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4510 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4514 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4517 /* Use register calling convention for local functions when possible. */
4519 && TREE_CODE (decl) == FUNCTION_DECL
4523 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4524 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4527 int local_regparm, globals = 0, regno;
4529 /* Make sure no regparm register is taken by a
4530 fixed register variable. */
4531 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4532 if (fixed_regs[local_regparm])
4535 /* We don't want to use regparm(3) for nested functions as
4536 these use a static chain pointer in the third argument. */
4537 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
4540 /* Each fixed register usage increases register pressure,
4541 so less registers should be used for argument passing.
4542 This functionality can be overriden by an explicit
4544 for (regno = 0; regno <= DI_REG; regno++)
4545 if (fixed_regs[regno])
4549 = globals < local_regparm ? local_regparm - globals : 0;
4551 if (local_regparm > regparm)
4552 regparm = local_regparm;
4559 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4560 DFmode (2) arguments in SSE registers for a function with the
4561 indicated TYPE and DECL. DECL may be NULL when calling function
4562 indirectly or considering a libcall. Otherwise return 0. */
4565 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4567 gcc_assert (!TARGET_64BIT);
4569 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4570 by the sseregparm attribute. */
4571 if (TARGET_SSEREGPARM
4572 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4579 error ("Calling %qD with attribute sseregparm without "
4580 "SSE/SSE2 enabled", decl);
4582 error ("Calling %qT with attribute sseregparm without "
4583 "SSE/SSE2 enabled", type);
4591 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4592 (and DFmode for SSE2) arguments in SSE registers. */
4593 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4595 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4596 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4598 return TARGET_SSE2 ? 2 : 1;
4604 /* Return true if EAX is live at the start of the function. Used by
4605 ix86_expand_prologue to determine if we need special help before
4606 calling allocate_stack_worker. */
4609 ix86_eax_live_at_start_p (void)
4611 /* Cheat. Don't bother working forward from ix86_function_regparm
4612 to the function type to whether an actual argument is located in
4613 eax. Instead just look at cfg info, which is still close enough
4614 to correct at this point. This gives false positives for broken
4615 functions that might use uninitialized data that happens to be
4616 allocated in eax, but who cares? */
4617 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4620 /* Value is the number of bytes of arguments automatically
4621 popped when returning from a subroutine call.
4622 FUNDECL is the declaration node of the function (as a tree),
4623 FUNTYPE is the data type of the function (as a tree),
4624 or for a library call it is an identifier node for the subroutine name.
4625 SIZE is the number of bytes of arguments passed on the stack.
4627 On the 80386, the RTD insn may be used to pop them if the number
4628 of args is fixed, but if the number is variable then the caller
4629 must pop them all. RTD can't be used for library calls now
4630 because the library is compiled with the Unix compiler.
4631 Use of RTD is a selectable option, since it is incompatible with
4632 standard Unix calling sequences. If the option is not selected,
4633 the caller must always pop the args.
4635 The attribute stdcall is equivalent to RTD on a per module basis. */
4638 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4642 /* None of the 64-bit ABIs pop arguments. */
4646 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4648 /* Cdecl functions override -mrtd, and never pop the stack. */
4649 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4651 /* Stdcall and fastcall functions will pop the stack if not
4653 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4654 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4657 if (rtd && ! stdarg_p (funtype))
4661 /* Lose any fake structure return argument if it is passed on the stack. */
4662 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4663 && !KEEP_AGGREGATE_RETURN_POINTER)
4665 int nregs = ix86_function_regparm (funtype, fundecl);
4667 return GET_MODE_SIZE (Pmode);
4673 /* Argument support functions. */
4675 /* Return true when register may be used to pass function parameters. */
4677 ix86_function_arg_regno_p (int regno)
4680 const int *parm_regs;
4685 return (regno < REGPARM_MAX
4686 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4688 return (regno < REGPARM_MAX
4689 || (TARGET_MMX && MMX_REGNO_P (regno)
4690 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4691 || (TARGET_SSE && SSE_REGNO_P (regno)
4692 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4697 if (SSE_REGNO_P (regno) && TARGET_SSE)
4702 if (TARGET_SSE && SSE_REGNO_P (regno)
4703 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4707 /* TODO: The function should depend on current function ABI but
4708 builtins.c would need updating then. Therefore we use the
4711 /* RAX is used as hidden argument to va_arg functions. */
4712 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4715 if (ix86_abi == MS_ABI)
4716 parm_regs = x86_64_ms_abi_int_parameter_registers;
4718 parm_regs = x86_64_int_parameter_registers;
4719 for (i = 0; i < (ix86_abi == MS_ABI
4720 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4721 if (regno == parm_regs[i])
4726 /* Return if we do not know how to pass TYPE solely in registers. */
4729 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4731 if (must_pass_in_stack_var_size_or_pad (mode, type))
4734 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4735 The layout_type routine is crafty and tries to trick us into passing
4736 currently unsupported vector types on the stack by using TImode. */
4737 return (!TARGET_64BIT && mode == TImode
4738 && type && TREE_CODE (type) != VECTOR_TYPE);
4741 /* It returns the size, in bytes, of the area reserved for arguments passed
4742 in registers for the function represented by fndecl dependent to the used
4745 ix86_reg_parm_stack_space (const_tree fndecl)
4747 enum calling_abi call_abi = SYSV_ABI;
4748 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4749 call_abi = ix86_function_abi (fndecl);
4751 call_abi = ix86_function_type_abi (fndecl);
4752 if (call_abi == MS_ABI)
4757 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4760 ix86_function_type_abi (const_tree fntype)
4762 if (TARGET_64BIT && fntype != NULL)
4764 enum calling_abi abi = ix86_abi;
4765 if (abi == SYSV_ABI)
4767 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4770 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4777 static enum calling_abi
4778 ix86_function_abi (const_tree fndecl)
4782 return ix86_function_type_abi (TREE_TYPE (fndecl));
4785 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4788 ix86_cfun_abi (void)
4790 if (! cfun || ! TARGET_64BIT)
4792 return cfun->machine->call_abi;
4796 extern void init_regs (void);
4798 /* Implementation of call abi switching target hook. Specific to FNDECL
4799 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4800 for more details. */
4802 ix86_call_abi_override (const_tree fndecl)
4804 if (fndecl == NULL_TREE)
4805 cfun->machine->call_abi = ix86_abi;
4807 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4810 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4811 re-initialization of init_regs each time we switch function context since
4812 this is needed only during RTL expansion. */
4814 ix86_maybe_switch_abi (void)
4817 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4821 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4822 for a call to a function whose data type is FNTYPE.
4823 For a library call, FNTYPE is 0. */
4826 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4827 tree fntype, /* tree ptr for function decl */
4828 rtx libname, /* SYMBOL_REF of library name or 0 */
4831 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4832 memset (cum, 0, sizeof (*cum));
4835 cum->call_abi = ix86_function_abi (fndecl);
4837 cum->call_abi = ix86_function_type_abi (fntype);
4838 /* Set up the number of registers to use for passing arguments. */
4840 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4841 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4842 "or subtarget optimization implying it");
4843 cum->nregs = ix86_regparm;
4846 if (cum->call_abi != ix86_abi)
4847 cum->nregs = (ix86_abi != SYSV_ABI
4848 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4852 cum->sse_nregs = SSE_REGPARM_MAX;
4855 if (cum->call_abi != ix86_abi)
4856 cum->sse_nregs = (ix86_abi != SYSV_ABI
4857 ? X86_64_SSE_REGPARM_MAX
4858 : X86_64_MS_SSE_REGPARM_MAX);
4862 cum->mmx_nregs = MMX_REGPARM_MAX;
4863 cum->warn_avx = true;
4864 cum->warn_sse = true;
4865 cum->warn_mmx = true;
4867 /* Because type might mismatch in between caller and callee, we need to
4868 use actual type of function for local calls.
4869 FIXME: cgraph_analyze can be told to actually record if function uses
4870 va_start so for local functions maybe_vaarg can be made aggressive
4872 FIXME: once typesytem is fixed, we won't need this code anymore. */
4874 fntype = TREE_TYPE (fndecl);
4875 cum->maybe_vaarg = (fntype
4876 ? (!prototype_p (fntype) || stdarg_p (fntype))
4881 /* If there are variable arguments, then we won't pass anything
4882 in registers in 32-bit mode. */
4883 if (stdarg_p (fntype))
4894 /* Use ecx and edx registers if function has fastcall attribute,
4895 else look for regparm information. */
4898 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4904 cum->nregs = ix86_function_regparm (fntype, fndecl);
4907 /* Set up the number of SSE registers used for passing SFmode
4908 and DFmode arguments. Warn for mismatching ABI. */
4909 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4913 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4914 But in the case of vector types, it is some vector mode.
4916 When we have only some of our vector isa extensions enabled, then there
4917 are some modes for which vector_mode_supported_p is false. For these
4918 modes, the generic vector support in gcc will choose some non-vector mode
4919 in order to implement the type. By computing the natural mode, we'll
4920 select the proper ABI location for the operand and not depend on whatever
4921 the middle-end decides to do with these vector types.
4923 The midde-end can't deal with the vector types > 16 bytes. In this
4924 case, we return the original mode and warn ABI change if CUM isn't
4927 static enum machine_mode
4928 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4930 enum machine_mode mode = TYPE_MODE (type);
4932 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4934 HOST_WIDE_INT size = int_size_in_bytes (type);
4935 if ((size == 8 || size == 16 || size == 32)
4936 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4937 && TYPE_VECTOR_SUBPARTS (type) > 1)
4939 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4941 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4942 mode = MIN_MODE_VECTOR_FLOAT;
4944 mode = MIN_MODE_VECTOR_INT;
4946 /* Get the mode which has this inner mode and number of units. */
4947 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4948 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4949 && GET_MODE_INNER (mode) == innermode)
4951 if (size == 32 && !TARGET_AVX)
4953 static bool warnedavx;
4960 warning (0, "AVX vector argument without AVX "
4961 "enabled changes the ABI");
4963 return TYPE_MODE (type);
4976 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4977 this may not agree with the mode that the type system has chosen for the
4978 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4979 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4982 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4987 if (orig_mode != BLKmode)
4988 tmp = gen_rtx_REG (orig_mode, regno);
4991 tmp = gen_rtx_REG (mode, regno);
4992 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4993 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4999 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5000 of this code is to classify each 8bytes of incoming argument by the register
5001 class and assign registers accordingly. */
5003 /* Return the union class of CLASS1 and CLASS2.
5004 See the x86-64 PS ABI for details. */
5006 static enum x86_64_reg_class
5007 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5009 /* Rule #1: If both classes are equal, this is the resulting class. */
5010 if (class1 == class2)
5013 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5015 if (class1 == X86_64_NO_CLASS)
5017 if (class2 == X86_64_NO_CLASS)
5020 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5021 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5022 return X86_64_MEMORY_CLASS;
5024 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5025 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5026 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5027 return X86_64_INTEGERSI_CLASS;
5028 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5029 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5030 return X86_64_INTEGER_CLASS;
5032 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5034 if (class1 == X86_64_X87_CLASS
5035 || class1 == X86_64_X87UP_CLASS
5036 || class1 == X86_64_COMPLEX_X87_CLASS
5037 || class2 == X86_64_X87_CLASS
5038 || class2 == X86_64_X87UP_CLASS
5039 || class2 == X86_64_COMPLEX_X87_CLASS)
5040 return X86_64_MEMORY_CLASS;
5042 /* Rule #6: Otherwise class SSE is used. */
5043 return X86_64_SSE_CLASS;
5046 /* Classify the argument of type TYPE and mode MODE.
5047 CLASSES will be filled by the register class used to pass each word
5048 of the operand. The number of words is returned. In case the parameter
5049 should be passed in memory, 0 is returned. As a special case for zero
5050 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5052 BIT_OFFSET is used internally for handling records and specifies offset
5053 of the offset in bits modulo 256 to avoid overflow cases.
5055 See the x86-64 PS ABI for details.
5059 classify_argument (enum machine_mode mode, const_tree type,
5060 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5062 HOST_WIDE_INT bytes =
5063 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5064 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5066 /* Variable sized entities are always passed/returned in memory. */
5070 if (mode != VOIDmode
5071 && targetm.calls.must_pass_in_stack (mode, type))
5074 if (type && AGGREGATE_TYPE_P (type))
5078 enum x86_64_reg_class subclasses[MAX_CLASSES];
5080 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5084 for (i = 0; i < words; i++)
5085 classes[i] = X86_64_NO_CLASS;
5087 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5088 signalize memory class, so handle it as special case. */
5091 classes[0] = X86_64_NO_CLASS;
5095 /* Classify each field of record and merge classes. */
5096 switch (TREE_CODE (type))
5099 /* And now merge the fields of structure. */
5100 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5102 if (TREE_CODE (field) == FIELD_DECL)
5106 if (TREE_TYPE (field) == error_mark_node)
5109 /* Bitfields are always classified as integer. Handle them
5110 early, since later code would consider them to be
5111 misaligned integers. */
5112 if (DECL_BIT_FIELD (field))
5114 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5115 i < ((int_bit_position (field) + (bit_offset % 64))
5116 + tree_low_cst (DECL_SIZE (field), 0)
5119 merge_classes (X86_64_INTEGER_CLASS,
5126 type = TREE_TYPE (field);
5128 /* Flexible array member is ignored. */
5129 if (TYPE_MODE (type) == BLKmode
5130 && TREE_CODE (type) == ARRAY_TYPE
5131 && TYPE_SIZE (type) == NULL_TREE
5132 && TYPE_DOMAIN (type) != NULL_TREE
5133 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5138 if (!warned && warn_psabi)
5141 inform (input_location,
5142 "The ABI of passing struct with"
5143 " a flexible array member has"
5144 " changed in GCC 4.4");
5148 num = classify_argument (TYPE_MODE (type), type,
5150 (int_bit_position (field)
5151 + bit_offset) % 256);
5154 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5155 for (i = 0; i < num && (i + pos) < words; i++)
5157 merge_classes (subclasses[i], classes[i + pos]);
5164 /* Arrays are handled as small records. */
5167 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5168 TREE_TYPE (type), subclasses, bit_offset);
5172 /* The partial classes are now full classes. */
5173 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5174 subclasses[0] = X86_64_SSE_CLASS;
5175 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5176 && !((bit_offset % 64) == 0 && bytes == 4))
5177 subclasses[0] = X86_64_INTEGER_CLASS;
5179 for (i = 0; i < words; i++)
5180 classes[i] = subclasses[i % num];
5185 case QUAL_UNION_TYPE:
5186 /* Unions are similar to RECORD_TYPE but offset is always 0.
5188 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5190 if (TREE_CODE (field) == FIELD_DECL)
5194 if (TREE_TYPE (field) == error_mark_node)
5197 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5198 TREE_TYPE (field), subclasses,
5202 for (i = 0; i < num; i++)
5203 classes[i] = merge_classes (subclasses[i], classes[i]);
5214 /* When size > 16 bytes, if the first one isn't
5215 X86_64_SSE_CLASS or any other ones aren't
5216 X86_64_SSEUP_CLASS, everything should be passed in
5218 if (classes[0] != X86_64_SSE_CLASS)
5221 for (i = 1; i < words; i++)
5222 if (classes[i] != X86_64_SSEUP_CLASS)
5226 /* Final merger cleanup. */
5227 for (i = 0; i < words; i++)
5229 /* If one class is MEMORY, everything should be passed in
5231 if (classes[i] == X86_64_MEMORY_CLASS)
5234 /* The X86_64_SSEUP_CLASS should be always preceded by
5235 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5236 if (classes[i] == X86_64_SSEUP_CLASS
5237 && classes[i - 1] != X86_64_SSE_CLASS
5238 && classes[i - 1] != X86_64_SSEUP_CLASS)
5240 /* The first one should never be X86_64_SSEUP_CLASS. */
5241 gcc_assert (i != 0);
5242 classes[i] = X86_64_SSE_CLASS;
5245 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5246 everything should be passed in memory. */
5247 if (classes[i] == X86_64_X87UP_CLASS
5248 && (classes[i - 1] != X86_64_X87_CLASS))
5252 /* The first one should never be X86_64_X87UP_CLASS. */
5253 gcc_assert (i != 0);
5254 if (!warned && warn_psabi)
5257 inform (input_location,
5258 "The ABI of passing union with long double"
5259 " has changed in GCC 4.4");
5267 /* Compute alignment needed. We align all types to natural boundaries with
5268 exception of XFmode that is aligned to 64bits. */
5269 if (mode != VOIDmode && mode != BLKmode)
5271 int mode_alignment = GET_MODE_BITSIZE (mode);
5274 mode_alignment = 128;
5275 else if (mode == XCmode)
5276 mode_alignment = 256;
5277 if (COMPLEX_MODE_P (mode))
5278 mode_alignment /= 2;
5279 /* Misaligned fields are always returned in memory. */
5280 if (bit_offset % mode_alignment)
5284 /* for V1xx modes, just use the base mode */
5285 if (VECTOR_MODE_P (mode) && mode != V1DImode
5286 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5287 mode = GET_MODE_INNER (mode);
5289 /* Classification of atomic types. */
5294 classes[0] = X86_64_SSE_CLASS;
5297 classes[0] = X86_64_SSE_CLASS;
5298 classes[1] = X86_64_SSEUP_CLASS;
5308 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5312 classes[0] = X86_64_INTEGERSI_CLASS;
5315 else if (size <= 64)
5317 classes[0] = X86_64_INTEGER_CLASS;
5320 else if (size <= 64+32)
5322 classes[0] = X86_64_INTEGER_CLASS;
5323 classes[1] = X86_64_INTEGERSI_CLASS;
5326 else if (size <= 64+64)
5328 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5336 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5340 /* OImode shouldn't be used directly. */
5345 if (!(bit_offset % 64))
5346 classes[0] = X86_64_SSESF_CLASS;
5348 classes[0] = X86_64_SSE_CLASS;
5351 classes[0] = X86_64_SSEDF_CLASS;
5354 classes[0] = X86_64_X87_CLASS;
5355 classes[1] = X86_64_X87UP_CLASS;
5358 classes[0] = X86_64_SSE_CLASS;
5359 classes[1] = X86_64_SSEUP_CLASS;
5362 classes[0] = X86_64_SSE_CLASS;
5363 if (!(bit_offset % 64))
5369 if (!warned && warn_psabi)
5372 inform (input_location,
5373 "The ABI of passing structure with complex float"
5374 " member has changed in GCC 4.4");
5376 classes[1] = X86_64_SSESF_CLASS;
5380 classes[0] = X86_64_SSEDF_CLASS;
5381 classes[1] = X86_64_SSEDF_CLASS;
5384 classes[0] = X86_64_COMPLEX_X87_CLASS;
5387 /* This modes is larger than 16 bytes. */
5395 classes[0] = X86_64_SSE_CLASS;
5396 classes[1] = X86_64_SSEUP_CLASS;
5397 classes[2] = X86_64_SSEUP_CLASS;
5398 classes[3] = X86_64_SSEUP_CLASS;
5406 classes[0] = X86_64_SSE_CLASS;
5407 classes[1] = X86_64_SSEUP_CLASS;
5414 classes[0] = X86_64_SSE_CLASS;
5420 gcc_assert (VECTOR_MODE_P (mode));
5425 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5427 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5428 classes[0] = X86_64_INTEGERSI_CLASS;
5430 classes[0] = X86_64_INTEGER_CLASS;
5431 classes[1] = X86_64_INTEGER_CLASS;
5432 return 1 + (bytes > 8);
5436 /* Examine the argument and return set number of register required in each
5437 class. Return 0 iff parameter should be passed in memory. */
5439 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5440 int *int_nregs, int *sse_nregs)
5442 enum x86_64_reg_class regclass[MAX_CLASSES];
5443 int n = classify_argument (mode, type, regclass, 0);
5449 for (n--; n >= 0; n--)
5450 switch (regclass[n])
5452 case X86_64_INTEGER_CLASS:
5453 case X86_64_INTEGERSI_CLASS:
5456 case X86_64_SSE_CLASS:
5457 case X86_64_SSESF_CLASS:
5458 case X86_64_SSEDF_CLASS:
5461 case X86_64_NO_CLASS:
5462 case X86_64_SSEUP_CLASS:
5464 case X86_64_X87_CLASS:
5465 case X86_64_X87UP_CLASS:
5469 case X86_64_COMPLEX_X87_CLASS:
5470 return in_return ? 2 : 0;
5471 case X86_64_MEMORY_CLASS:
5477 /* Construct container for the argument used by GCC interface. See
5478 FUNCTION_ARG for the detailed description. */
5481 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5482 const_tree type, int in_return, int nintregs, int nsseregs,
5483 const int *intreg, int sse_regno)
5485 /* The following variables hold the static issued_error state. */
5486 static bool issued_sse_arg_error;
5487 static bool issued_sse_ret_error;
5488 static bool issued_x87_ret_error;
5490 enum machine_mode tmpmode;
5492 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5493 enum x86_64_reg_class regclass[MAX_CLASSES];
5497 int needed_sseregs, needed_intregs;
5498 rtx exp[MAX_CLASSES];
5501 n = classify_argument (mode, type, regclass, 0);
5504 if (!examine_argument (mode, type, in_return, &needed_intregs,
5507 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5510 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5511 some less clueful developer tries to use floating-point anyway. */
5512 if (needed_sseregs && !TARGET_SSE)
5516 if (!issued_sse_ret_error)
5518 error ("SSE register return with SSE disabled");
5519 issued_sse_ret_error = true;
5522 else if (!issued_sse_arg_error)
5524 error ("SSE register argument with SSE disabled");
5525 issued_sse_arg_error = true;
5530 /* Likewise, error if the ABI requires us to return values in the
5531 x87 registers and the user specified -mno-80387. */
5532 if (!TARGET_80387 && in_return)
5533 for (i = 0; i < n; i++)
5534 if (regclass[i] == X86_64_X87_CLASS
5535 || regclass[i] == X86_64_X87UP_CLASS
5536 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5538 if (!issued_x87_ret_error)
5540 error ("x87 register return with x87 disabled");
5541 issued_x87_ret_error = true;
5546 /* First construct simple cases. Avoid SCmode, since we want to use
5547 single register to pass this type. */
5548 if (n == 1 && mode != SCmode)
5549 switch (regclass[0])
5551 case X86_64_INTEGER_CLASS:
5552 case X86_64_INTEGERSI_CLASS:
5553 return gen_rtx_REG (mode, intreg[0]);
5554 case X86_64_SSE_CLASS:
5555 case X86_64_SSESF_CLASS:
5556 case X86_64_SSEDF_CLASS:
5557 if (mode != BLKmode)
5558 return gen_reg_or_parallel (mode, orig_mode,
5559 SSE_REGNO (sse_regno));
5561 case X86_64_X87_CLASS:
5562 case X86_64_COMPLEX_X87_CLASS:
5563 return gen_rtx_REG (mode, FIRST_STACK_REG);
5564 case X86_64_NO_CLASS:
5565 /* Zero sized array, struct or class. */
5570 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5571 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5572 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5574 && regclass[0] == X86_64_SSE_CLASS
5575 && regclass[1] == X86_64_SSEUP_CLASS
5576 && regclass[2] == X86_64_SSEUP_CLASS
5577 && regclass[3] == X86_64_SSEUP_CLASS
5579 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5582 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5583 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5584 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5585 && regclass[1] == X86_64_INTEGER_CLASS
5586 && (mode == CDImode || mode == TImode || mode == TFmode)
5587 && intreg[0] + 1 == intreg[1])
5588 return gen_rtx_REG (mode, intreg[0]);
5590 /* Otherwise figure out the entries of the PARALLEL. */
5591 for (i = 0; i < n; i++)
5595 switch (regclass[i])
5597 case X86_64_NO_CLASS:
5599 case X86_64_INTEGER_CLASS:
5600 case X86_64_INTEGERSI_CLASS:
5601 /* Merge TImodes on aligned occasions here too. */
5602 if (i * 8 + 8 > bytes)
5603 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5604 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5608 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5609 if (tmpmode == BLKmode)
5611 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5612 gen_rtx_REG (tmpmode, *intreg),
5616 case X86_64_SSESF_CLASS:
5617 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5618 gen_rtx_REG (SFmode,
5619 SSE_REGNO (sse_regno)),
5623 case X86_64_SSEDF_CLASS:
5624 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5625 gen_rtx_REG (DFmode,
5626 SSE_REGNO (sse_regno)),
5630 case X86_64_SSE_CLASS:
5638 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5648 && regclass[1] == X86_64_SSEUP_CLASS
5649 && regclass[2] == X86_64_SSEUP_CLASS
5650 && regclass[3] == X86_64_SSEUP_CLASS);
5657 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5658 gen_rtx_REG (tmpmode,
5659 SSE_REGNO (sse_regno)),
5668 /* Empty aligned struct, union or class. */
5672 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5673 for (i = 0; i < nexps; i++)
5674 XVECEXP (ret, 0, i) = exp [i];
5678 /* Update the data in CUM to advance over an argument of mode MODE
5679 and data type TYPE. (TYPE is null for libcalls where that information
5680 may not be available.) */
5683 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5684 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5700 cum->words += words;
5701 cum->nregs -= words;
5702 cum->regno += words;
5704 if (cum->nregs <= 0)
5712 /* OImode shouldn't be used directly. */
5716 if (cum->float_in_sse < 2)
5719 if (cum->float_in_sse < 1)
5736 if (!type || !AGGREGATE_TYPE_P (type))
5738 cum->sse_words += words;
5739 cum->sse_nregs -= 1;
5740 cum->sse_regno += 1;
5741 if (cum->sse_nregs <= 0)
5754 if (!type || !AGGREGATE_TYPE_P (type))
5756 cum->mmx_words += words;
5757 cum->mmx_nregs -= 1;
5758 cum->mmx_regno += 1;
5759 if (cum->mmx_nregs <= 0)
5770 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5771 tree type, HOST_WIDE_INT words, int named)
5773 int int_nregs, sse_nregs;
5775 /* Unnamed 256bit vector mode parameters are passed on stack. */
5776 if (!named && VALID_AVX256_REG_MODE (mode))
5779 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5780 cum->words += words;
5781 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5783 cum->nregs -= int_nregs;
5784 cum->sse_nregs -= sse_nregs;
5785 cum->regno += int_nregs;
5786 cum->sse_regno += sse_nregs;
5789 cum->words += words;
5793 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5794 HOST_WIDE_INT words)
5796 /* Otherwise, this should be passed indirect. */
5797 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5799 cum->words += words;
5808 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5809 tree type, int named)
5811 HOST_WIDE_INT bytes, words;
5813 if (mode == BLKmode)
5814 bytes = int_size_in_bytes (type);
5816 bytes = GET_MODE_SIZE (mode);
5817 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5820 mode = type_natural_mode (type, NULL);
5822 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5823 function_arg_advance_ms_64 (cum, bytes, words);
5824 else if (TARGET_64BIT)
5825 function_arg_advance_64 (cum, mode, type, words, named);
5827 function_arg_advance_32 (cum, mode, type, bytes, words);
5830 /* Define where to put the arguments to a function.
5831 Value is zero to push the argument on the stack,
5832 or a hard register in which to store the argument.
5834 MODE is the argument's machine mode.
5835 TYPE is the data type of the argument (as a tree).
5836 This is null for libcalls where that information may
5838 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5839 the preceding args and about the function being called.
5840 NAMED is nonzero if this argument is a named parameter
5841 (otherwise it is an extra parameter matching an ellipsis). */
5844 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5845 enum machine_mode orig_mode, tree type,
5846 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5848 static bool warnedsse, warnedmmx;
5850 /* Avoid the AL settings for the Unix64 ABI. */
5851 if (mode == VOIDmode)
5867 if (words <= cum->nregs)
5869 int regno = cum->regno;
5871 /* Fastcall allocates the first two DWORD (SImode) or
5872 smaller arguments to ECX and EDX if it isn't an
5878 || (type && AGGREGATE_TYPE_P (type)))
5881 /* ECX not EAX is the first allocated register. */
5882 if (regno == AX_REG)
5885 return gen_rtx_REG (mode, regno);
5890 if (cum->float_in_sse < 2)
5893 if (cum->float_in_sse < 1)
5897 /* In 32bit, we pass TImode in xmm registers. */
5904 if (!type || !AGGREGATE_TYPE_P (type))
5906 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5909 warning (0, "SSE vector argument without SSE enabled "
5913 return gen_reg_or_parallel (mode, orig_mode,
5914 cum->sse_regno + FIRST_SSE_REG);
5919 /* OImode shouldn't be used directly. */
5928 if (!type || !AGGREGATE_TYPE_P (type))
5931 return gen_reg_or_parallel (mode, orig_mode,
5932 cum->sse_regno + FIRST_SSE_REG);
5941 if (!type || !AGGREGATE_TYPE_P (type))
5943 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5946 warning (0, "MMX vector argument without MMX enabled "
5950 return gen_reg_or_parallel (mode, orig_mode,
5951 cum->mmx_regno + FIRST_MMX_REG);
5960 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5961 enum machine_mode orig_mode, tree type, int named)
5963 /* Handle a hidden AL argument containing number of registers
5964 for varargs x86-64 functions. */
5965 if (mode == VOIDmode)
5966 return GEN_INT (cum->maybe_vaarg
5967 ? (cum->sse_nregs < 0
5968 ? (cum->call_abi == ix86_abi
5970 : (ix86_abi != SYSV_ABI
5971 ? X86_64_SSE_REGPARM_MAX
5972 : X86_64_MS_SSE_REGPARM_MAX))
5987 /* Unnamed 256bit vector mode parameters are passed on stack. */
5993 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5995 &x86_64_int_parameter_registers [cum->regno],
6000 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6001 enum machine_mode orig_mode, int named,
6002 HOST_WIDE_INT bytes)
6006 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6007 We use value of -2 to specify that current function call is MSABI. */
6008 if (mode == VOIDmode)
6009 return GEN_INT (-2);
6011 /* If we've run out of registers, it goes on the stack. */
6012 if (cum->nregs == 0)
6015 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6017 /* Only floating point modes are passed in anything but integer regs. */
6018 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6021 regno = cum->regno + FIRST_SSE_REG;
6026 /* Unnamed floating parameters are passed in both the
6027 SSE and integer registers. */
6028 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6029 t2 = gen_rtx_REG (mode, regno);
6030 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6031 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6032 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6035 /* Handle aggregated types passed in register. */
6036 if (orig_mode == BLKmode)
6038 if (bytes > 0 && bytes <= 8)
6039 mode = (bytes > 4 ? DImode : SImode);
6040 if (mode == BLKmode)
6044 return gen_reg_or_parallel (mode, orig_mode, regno);
6048 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6049 tree type, int named)
6051 enum machine_mode mode = omode;
6052 HOST_WIDE_INT bytes, words;
6054 if (mode == BLKmode)
6055 bytes = int_size_in_bytes (type);
6057 bytes = GET_MODE_SIZE (mode);
6058 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6060 /* To simplify the code below, represent vector types with a vector mode
6061 even if MMX/SSE are not active. */
6062 if (type && TREE_CODE (type) == VECTOR_TYPE)
6063 mode = type_natural_mode (type, cum);
6065 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6066 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6067 else if (TARGET_64BIT)
6068 return function_arg_64 (cum, mode, omode, type, named);
6070 return function_arg_32 (cum, mode, omode, type, bytes, words);
6073 /* A C expression that indicates when an argument must be passed by
6074 reference. If nonzero for an argument, a copy of that argument is
6075 made in memory and a pointer to the argument is passed instead of
6076 the argument itself. The pointer is passed in whatever way is
6077 appropriate for passing a pointer to that type. */
6080 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6081 enum machine_mode mode ATTRIBUTE_UNUSED,
6082 const_tree type, bool named ATTRIBUTE_UNUSED)
6084 /* See Windows x64 Software Convention. */
6085 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6087 int msize = (int) GET_MODE_SIZE (mode);
6090 /* Arrays are passed by reference. */
6091 if (TREE_CODE (type) == ARRAY_TYPE)
6094 if (AGGREGATE_TYPE_P (type))
6096 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6097 are passed by reference. */
6098 msize = int_size_in_bytes (type);
6102 /* __m128 is passed by reference. */
6104 case 1: case 2: case 4: case 8:
6110 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6116 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6119 contains_aligned_value_p (tree type)
6121 enum machine_mode mode = TYPE_MODE (type);
6122 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6126 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6128 if (TYPE_ALIGN (type) < 128)
6131 if (AGGREGATE_TYPE_P (type))
6133 /* Walk the aggregates recursively. */
6134 switch (TREE_CODE (type))
6138 case QUAL_UNION_TYPE:
6142 /* Walk all the structure fields. */
6143 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6145 if (TREE_CODE (field) == FIELD_DECL
6146 && contains_aligned_value_p (TREE_TYPE (field)))
6153 /* Just for use if some languages passes arrays by value. */
6154 if (contains_aligned_value_p (TREE_TYPE (type)))
6165 /* Gives the alignment boundary, in bits, of an argument with the
6166 specified mode and type. */
6169 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6174 /* Since canonical type is used for call, we convert it to
6175 canonical type if needed. */
6176 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6177 type = TYPE_CANONICAL (type);
6178 align = TYPE_ALIGN (type);
6181 align = GET_MODE_ALIGNMENT (mode);
6182 if (align < PARM_BOUNDARY)
6183 align = PARM_BOUNDARY;
6184 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6185 natural boundaries. */
6186 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6188 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6189 make an exception for SSE modes since these require 128bit
6192 The handling here differs from field_alignment. ICC aligns MMX
6193 arguments to 4 byte boundaries, while structure fields are aligned
6194 to 8 byte boundaries. */
6197 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6198 align = PARM_BOUNDARY;
6202 if (!contains_aligned_value_p (type))
6203 align = PARM_BOUNDARY;
6206 if (align > BIGGEST_ALIGNMENT)
6207 align = BIGGEST_ALIGNMENT;
6211 /* Return true if N is a possible register number of function value. */
6214 ix86_function_value_regno_p (int regno)
6221 case FIRST_FLOAT_REG:
6222 /* TODO: The function should depend on current function ABI but
6223 builtins.c would need updating then. Therefore we use the
6225 if (TARGET_64BIT && ix86_abi == MS_ABI)
6227 return TARGET_FLOAT_RETURNS_IN_80387;
6233 if (TARGET_MACHO || TARGET_64BIT)
6241 /* Define how to find the value returned by a function.
6242 VALTYPE is the data type of the value (as a tree).
6243 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6244 otherwise, FUNC is 0. */
6247 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6248 const_tree fntype, const_tree fn)
6252 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6253 we normally prevent this case when mmx is not available. However
6254 some ABIs may require the result to be returned like DImode. */
6255 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6256 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6258 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6259 we prevent this case when sse is not available. However some ABIs
6260 may require the result to be returned like integer TImode. */
6261 else if (mode == TImode
6262 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6263 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6265 /* 32-byte vector modes in %ymm0. */
6266 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6267 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6269 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6270 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6271 regno = FIRST_FLOAT_REG;
6273 /* Most things go in %eax. */
6276 /* Override FP return register with %xmm0 for local functions when
6277 SSE math is enabled or for functions with sseregparm attribute. */
6278 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6280 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6281 if ((sse_level >= 1 && mode == SFmode)
6282 || (sse_level == 2 && mode == DFmode))
6283 regno = FIRST_SSE_REG;
6286 /* OImode shouldn't be used directly. */
6287 gcc_assert (mode != OImode);
6289 return gen_rtx_REG (orig_mode, regno);
6293 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6298 /* Handle libcalls, which don't provide a type node. */
6299 if (valtype == NULL)
6311 return gen_rtx_REG (mode, FIRST_SSE_REG);
6314 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6318 return gen_rtx_REG (mode, AX_REG);
6322 ret = construct_container (mode, orig_mode, valtype, 1,
6323 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6324 x86_64_int_return_registers, 0);
6326 /* For zero sized structures, construct_container returns NULL, but we
6327 need to keep rest of compiler happy by returning meaningful value. */
6329 ret = gen_rtx_REG (orig_mode, AX_REG);
6335 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6337 unsigned int regno = AX_REG;
6341 switch (GET_MODE_SIZE (mode))
6344 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6345 && !COMPLEX_MODE_P (mode))
6346 regno = FIRST_SSE_REG;
6350 if (mode == SFmode || mode == DFmode)
6351 regno = FIRST_SSE_REG;
6357 return gen_rtx_REG (orig_mode, regno);
6361 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6362 enum machine_mode orig_mode, enum machine_mode mode)
6364 const_tree fn, fntype;
6367 if (fntype_or_decl && DECL_P (fntype_or_decl))
6368 fn = fntype_or_decl;
6369 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6371 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6372 return function_value_ms_64 (orig_mode, mode);
6373 else if (TARGET_64BIT)
6374 return function_value_64 (orig_mode, mode, valtype);
6376 return function_value_32 (orig_mode, mode, fntype, fn);
6380 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6381 bool outgoing ATTRIBUTE_UNUSED)
6383 enum machine_mode mode, orig_mode;
6385 orig_mode = TYPE_MODE (valtype);
6386 mode = type_natural_mode (valtype, NULL);
6387 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6391 ix86_libcall_value (enum machine_mode mode)
6393 return ix86_function_value_1 (NULL, NULL, mode, mode);
6396 /* Return true iff type is returned in memory. */
6398 static int ATTRIBUTE_UNUSED
6399 return_in_memory_32 (const_tree type, enum machine_mode mode)
6403 if (mode == BLKmode)
6406 size = int_size_in_bytes (type);
6408 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6411 if (VECTOR_MODE_P (mode) || mode == TImode)
6413 /* User-created vectors small enough to fit in EAX. */
6417 /* MMX/3dNow values are returned in MM0,
6418 except when it doesn't exits. */
6420 return (TARGET_MMX ? 0 : 1);
6422 /* SSE values are returned in XMM0, except when it doesn't exist. */
6424 return (TARGET_SSE ? 0 : 1);
6426 /* AVX values are returned in YMM0, except when it doesn't exist. */
6428 return TARGET_AVX ? 0 : 1;
6437 /* OImode shouldn't be used directly. */
6438 gcc_assert (mode != OImode);
6443 static int ATTRIBUTE_UNUSED
6444 return_in_memory_64 (const_tree type, enum machine_mode mode)
6446 int needed_intregs, needed_sseregs;
6447 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6450 static int ATTRIBUTE_UNUSED
6451 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6453 HOST_WIDE_INT size = int_size_in_bytes (type);
6455 /* __m128 is returned in xmm0. */
6456 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6457 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6460 /* Otherwise, the size must be exactly in [1248]. */
6461 return (size != 1 && size != 2 && size != 4 && size != 8);
6465 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6467 #ifdef SUBTARGET_RETURN_IN_MEMORY
6468 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6470 const enum machine_mode mode = type_natural_mode (type, NULL);
6474 if (ix86_function_type_abi (fntype) == MS_ABI)
6475 return return_in_memory_ms_64 (type, mode);
6477 return return_in_memory_64 (type, mode);
6480 return return_in_memory_32 (type, mode);
6484 /* Return false iff TYPE is returned in memory. This version is used
6485 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6486 but differs notably in that when MMX is available, 8-byte vectors
6487 are returned in memory, rather than in MMX registers. */
6490 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6493 enum machine_mode mode = type_natural_mode (type, NULL);
6496 return return_in_memory_64 (type, mode);
6498 if (mode == BLKmode)
6501 size = int_size_in_bytes (type);
6503 if (VECTOR_MODE_P (mode))
6505 /* Return in memory only if MMX registers *are* available. This
6506 seems backwards, but it is consistent with the existing
6513 else if (mode == TImode)
6515 else if (mode == XFmode)
6521 /* When returning SSE vector types, we have a choice of either
6522 (1) being abi incompatible with a -march switch, or
6523 (2) generating an error.
6524 Given no good solution, I think the safest thing is one warning.
6525 The user won't be able to use -Werror, but....
6527 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6528 called in response to actually generating a caller or callee that
6529 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6530 via aggregate_value_p for general type probing from tree-ssa. */
6533 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6535 static bool warnedsse, warnedmmx;
6537 if (!TARGET_64BIT && type)
6539 /* Look at the return type of the function, not the function type. */
6540 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6542 if (!TARGET_SSE && !warnedsse)
6545 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6548 warning (0, "SSE vector return without SSE enabled "
6553 if (!TARGET_MMX && !warnedmmx)
6555 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6558 warning (0, "MMX vector return without MMX enabled "
6568 /* Create the va_list data type. */
6570 /* Returns the calling convention specific va_list date type.
6571 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6574 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6576 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6578 /* For i386 we use plain pointer to argument area. */
6579 if (!TARGET_64BIT || abi == MS_ABI)
6580 return build_pointer_type (char_type_node);
6582 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6583 type_decl = build_decl (BUILTINS_LOCATION,
6584 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6586 f_gpr = build_decl (BUILTINS_LOCATION,
6587 FIELD_DECL, get_identifier ("gp_offset"),
6588 unsigned_type_node);
6589 f_fpr = build_decl (BUILTINS_LOCATION,
6590 FIELD_DECL, get_identifier ("fp_offset"),
6591 unsigned_type_node);
6592 f_ovf = build_decl (BUILTINS_LOCATION,
6593 FIELD_DECL, get_identifier ("overflow_arg_area"),
6595 f_sav = build_decl (BUILTINS_LOCATION,
6596 FIELD_DECL, get_identifier ("reg_save_area"),
6599 va_list_gpr_counter_field = f_gpr;
6600 va_list_fpr_counter_field = f_fpr;
6602 DECL_FIELD_CONTEXT (f_gpr) = record;
6603 DECL_FIELD_CONTEXT (f_fpr) = record;
6604 DECL_FIELD_CONTEXT (f_ovf) = record;
6605 DECL_FIELD_CONTEXT (f_sav) = record;
6607 TREE_CHAIN (record) = type_decl;
6608 TYPE_NAME (record) = type_decl;
6609 TYPE_FIELDS (record) = f_gpr;
6610 TREE_CHAIN (f_gpr) = f_fpr;
6611 TREE_CHAIN (f_fpr) = f_ovf;
6612 TREE_CHAIN (f_ovf) = f_sav;
6614 layout_type (record);
6616 /* The correct type is an array type of one element. */
6617 return build_array_type (record, build_index_type (size_zero_node));
6620 /* Setup the builtin va_list data type and for 64-bit the additional
6621 calling convention specific va_list data types. */
6624 ix86_build_builtin_va_list (void)
6626 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6628 /* Initialize abi specific va_list builtin types. */
6632 if (ix86_abi == MS_ABI)
6634 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6635 if (TREE_CODE (t) != RECORD_TYPE)
6636 t = build_variant_type_copy (t);
6637 sysv_va_list_type_node = t;
6642 if (TREE_CODE (t) != RECORD_TYPE)
6643 t = build_variant_type_copy (t);
6644 sysv_va_list_type_node = t;
6646 if (ix86_abi != MS_ABI)
6648 t = ix86_build_builtin_va_list_abi (MS_ABI);
6649 if (TREE_CODE (t) != RECORD_TYPE)
6650 t = build_variant_type_copy (t);
6651 ms_va_list_type_node = t;
6656 if (TREE_CODE (t) != RECORD_TYPE)
6657 t = build_variant_type_copy (t);
6658 ms_va_list_type_node = t;
6665 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6668 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6677 int regparm = ix86_regparm;
6679 if (cum->call_abi != ix86_abi)
6680 regparm = (ix86_abi != SYSV_ABI
6681 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6683 /* GPR size of varargs save area. */
6684 if (cfun->va_list_gpr_size)
6685 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6687 ix86_varargs_gpr_size = 0;
6689 /* FPR size of varargs save area. We don't need it if we don't pass
6690 anything in SSE registers. */
6691 if (cum->sse_nregs && cfun->va_list_fpr_size)
6692 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6694 ix86_varargs_fpr_size = 0;
6696 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6699 save_area = frame_pointer_rtx;
6700 set = get_varargs_alias_set ();
6702 for (i = cum->regno;
6704 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6707 mem = gen_rtx_MEM (Pmode,
6708 plus_constant (save_area, i * UNITS_PER_WORD));
6709 MEM_NOTRAP_P (mem) = 1;
6710 set_mem_alias_set (mem, set);
6711 emit_move_insn (mem, gen_rtx_REG (Pmode,
6712 x86_64_int_parameter_registers[i]));
6715 if (ix86_varargs_fpr_size)
6717 /* Now emit code to save SSE registers. The AX parameter contains number
6718 of SSE parameter registers used to call this function. We use
6719 sse_prologue_save insn template that produces computed jump across
6720 SSE saves. We need some preparation work to get this working. */
6722 label = gen_label_rtx ();
6723 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6725 /* Compute address to jump to :
6726 label - eax*4 + nnamed_sse_arguments*4 Or
6727 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6728 tmp_reg = gen_reg_rtx (Pmode);
6729 nsse_reg = gen_reg_rtx (Pmode);
6730 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6731 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6732 gen_rtx_MULT (Pmode, nsse_reg,
6735 /* vmovaps is one byte longer than movaps. */
6737 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6738 gen_rtx_PLUS (Pmode, tmp_reg,
6744 gen_rtx_CONST (DImode,
6745 gen_rtx_PLUS (DImode,
6747 GEN_INT (cum->sse_regno
6748 * (TARGET_AVX ? 5 : 4)))));
6750 emit_move_insn (nsse_reg, label_ref);
6751 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6753 /* Compute address of memory block we save into. We always use pointer
6754 pointing 127 bytes after first byte to store - this is needed to keep
6755 instruction size limited by 4 bytes (5 bytes for AVX) with one
6756 byte displacement. */
6757 tmp_reg = gen_reg_rtx (Pmode);
6758 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6759 plus_constant (save_area,
6760 ix86_varargs_gpr_size + 127)));
6761 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6762 MEM_NOTRAP_P (mem) = 1;
6763 set_mem_alias_set (mem, set);
6764 set_mem_align (mem, BITS_PER_WORD);
6766 /* And finally do the dirty job! */
6767 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6768 GEN_INT (cum->sse_regno), label));
6773 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6775 alias_set_type set = get_varargs_alias_set ();
6778 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6782 mem = gen_rtx_MEM (Pmode,
6783 plus_constant (virtual_incoming_args_rtx,
6784 i * UNITS_PER_WORD));
6785 MEM_NOTRAP_P (mem) = 1;
6786 set_mem_alias_set (mem, set);
6788 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6789 emit_move_insn (mem, reg);
6794 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6795 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6798 CUMULATIVE_ARGS next_cum;
6801 /* This argument doesn't appear to be used anymore. Which is good,
6802 because the old code here didn't suppress rtl generation. */
6803 gcc_assert (!no_rtl);
6808 fntype = TREE_TYPE (current_function_decl);
6810 /* For varargs, we do not want to skip the dummy va_dcl argument.
6811 For stdargs, we do want to skip the last named argument. */
6813 if (stdarg_p (fntype))
6814 function_arg_advance (&next_cum, mode, type, 1);
6816 if (cum->call_abi == MS_ABI)
6817 setup_incoming_varargs_ms_64 (&next_cum);
6819 setup_incoming_varargs_64 (&next_cum);
6822 /* Checks if TYPE is of kind va_list char *. */
6825 is_va_list_char_pointer (tree type)
6829 /* For 32-bit it is always true. */
6832 canonic = ix86_canonical_va_list_type (type);
6833 return (canonic == ms_va_list_type_node
6834 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6837 /* Implement va_start. */
6840 ix86_va_start (tree valist, rtx nextarg)
6842 HOST_WIDE_INT words, n_gpr, n_fpr;
6843 tree f_gpr, f_fpr, f_ovf, f_sav;
6844 tree gpr, fpr, ovf, sav, t;
6847 /* Only 64bit target needs something special. */
6848 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6850 std_expand_builtin_va_start (valist, nextarg);
6854 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6855 f_fpr = TREE_CHAIN (f_gpr);
6856 f_ovf = TREE_CHAIN (f_fpr);
6857 f_sav = TREE_CHAIN (f_ovf);
6859 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6860 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6861 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6862 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6863 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6865 /* Count number of gp and fp argument registers used. */
6866 words = crtl->args.info.words;
6867 n_gpr = crtl->args.info.regno;
6868 n_fpr = crtl->args.info.sse_regno;
6870 if (cfun->va_list_gpr_size)
6872 type = TREE_TYPE (gpr);
6873 t = build2 (MODIFY_EXPR, type,
6874 gpr, build_int_cst (type, n_gpr * 8));
6875 TREE_SIDE_EFFECTS (t) = 1;
6876 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6879 if (TARGET_SSE && cfun->va_list_fpr_size)
6881 type = TREE_TYPE (fpr);
6882 t = build2 (MODIFY_EXPR, type, fpr,
6883 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6884 TREE_SIDE_EFFECTS (t) = 1;
6885 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6888 /* Find the overflow area. */
6889 type = TREE_TYPE (ovf);
6890 t = make_tree (type, crtl->args.internal_arg_pointer);
6892 t = build2 (POINTER_PLUS_EXPR, type, t,
6893 size_int (words * UNITS_PER_WORD));
6894 t = build2 (MODIFY_EXPR, type, ovf, t);
6895 TREE_SIDE_EFFECTS (t) = 1;
6896 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6898 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6900 /* Find the register save area.
6901 Prologue of the function save it right above stack frame. */
6902 type = TREE_TYPE (sav);
6903 t = make_tree (type, frame_pointer_rtx);
6904 if (!ix86_varargs_gpr_size)
6905 t = build2 (POINTER_PLUS_EXPR, type, t,
6906 size_int (-8 * X86_64_REGPARM_MAX));
6907 t = build2 (MODIFY_EXPR, type, sav, t);
6908 TREE_SIDE_EFFECTS (t) = 1;
6909 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6913 /* Implement va_arg. */
6916 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6919 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6920 tree f_gpr, f_fpr, f_ovf, f_sav;
6921 tree gpr, fpr, ovf, sav, t;
6923 tree lab_false, lab_over = NULL_TREE;
6928 enum machine_mode nat_mode;
6931 /* Only 64bit target needs something special. */
6932 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6933 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6935 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6936 f_fpr = TREE_CHAIN (f_gpr);
6937 f_ovf = TREE_CHAIN (f_fpr);
6938 f_sav = TREE_CHAIN (f_ovf);
6940 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6941 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6942 valist = build_va_arg_indirect_ref (valist);
6943 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6944 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6945 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6947 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6949 type = build_pointer_type (type);
6950 size = int_size_in_bytes (type);
6951 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6953 nat_mode = type_natural_mode (type, NULL);
6962 /* Unnamed 256bit vector mode parameters are passed on stack. */
6963 if (ix86_cfun_abi () == SYSV_ABI)
6970 container = construct_container (nat_mode, TYPE_MODE (type),
6971 type, 0, X86_64_REGPARM_MAX,
6972 X86_64_SSE_REGPARM_MAX, intreg,
6977 /* Pull the value out of the saved registers. */
6979 addr = create_tmp_var (ptr_type_node, "addr");
6983 int needed_intregs, needed_sseregs;
6985 tree int_addr, sse_addr;
6987 lab_false = create_artificial_label (UNKNOWN_LOCATION);
6988 lab_over = create_artificial_label (UNKNOWN_LOCATION);
6990 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6992 need_temp = (!REG_P (container)
6993 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6994 || TYPE_ALIGN (type) > 128));
6996 /* In case we are passing structure, verify that it is consecutive block
6997 on the register save area. If not we need to do moves. */
6998 if (!need_temp && !REG_P (container))
7000 /* Verify that all registers are strictly consecutive */
7001 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7005 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7007 rtx slot = XVECEXP (container, 0, i);
7008 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7009 || INTVAL (XEXP (slot, 1)) != i * 16)
7017 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7019 rtx slot = XVECEXP (container, 0, i);
7020 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7021 || INTVAL (XEXP (slot, 1)) != i * 8)
7033 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7034 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7037 /* First ensure that we fit completely in registers. */
7040 t = build_int_cst (TREE_TYPE (gpr),
7041 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7042 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7043 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7044 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7045 gimplify_and_add (t, pre_p);
7049 t = build_int_cst (TREE_TYPE (fpr),
7050 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7051 + X86_64_REGPARM_MAX * 8);
7052 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7053 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7054 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7055 gimplify_and_add (t, pre_p);
7058 /* Compute index to start of area used for integer regs. */
7061 /* int_addr = gpr + sav; */
7062 t = fold_convert (sizetype, gpr);
7063 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7064 gimplify_assign (int_addr, t, pre_p);
7068 /* sse_addr = fpr + sav; */
7069 t = fold_convert (sizetype, fpr);
7070 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7071 gimplify_assign (sse_addr, t, pre_p);
7076 tree temp = create_tmp_var (type, "va_arg_tmp");
7079 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7080 gimplify_assign (addr, t, pre_p);
7082 for (i = 0; i < XVECLEN (container, 0); i++)
7084 rtx slot = XVECEXP (container, 0, i);
7085 rtx reg = XEXP (slot, 0);
7086 enum machine_mode mode = GET_MODE (reg);
7087 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7088 tree addr_type = build_pointer_type (piece_type);
7089 tree daddr_type = build_pointer_type_for_mode (piece_type,
7093 tree dest_addr, dest;
7095 if (SSE_REGNO_P (REGNO (reg)))
7097 src_addr = sse_addr;
7098 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7102 src_addr = int_addr;
7103 src_offset = REGNO (reg) * 8;
7105 src_addr = fold_convert (addr_type, src_addr);
7106 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7107 size_int (src_offset));
7108 src = build_va_arg_indirect_ref (src_addr);
7110 dest_addr = fold_convert (daddr_type, addr);
7111 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7112 size_int (INTVAL (XEXP (slot, 1))));
7113 dest = build_va_arg_indirect_ref (dest_addr);
7115 gimplify_assign (dest, src, pre_p);
7121 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7122 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7123 gimplify_assign (gpr, t, pre_p);
7128 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7129 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7130 gimplify_assign (fpr, t, pre_p);
7133 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7135 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7138 /* ... otherwise out of the overflow area. */
7140 /* When we align parameter on stack for caller, if the parameter
7141 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7142 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7143 here with caller. */
7144 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7145 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7146 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7148 /* Care for on-stack alignment if needed. */
7149 if (arg_boundary <= 64
7150 || integer_zerop (TYPE_SIZE (type)))
7154 HOST_WIDE_INT align = arg_boundary / 8;
7155 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7156 size_int (align - 1));
7157 t = fold_convert (sizetype, t);
7158 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7160 t = fold_convert (TREE_TYPE (ovf), t);
7162 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7163 gimplify_assign (addr, t, pre_p);
7165 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7166 size_int (rsize * UNITS_PER_WORD));
7167 gimplify_assign (unshare_expr (ovf), t, pre_p);
7170 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7172 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7173 addr = fold_convert (ptrtype, addr);
7176 addr = build_va_arg_indirect_ref (addr);
7177 return build_va_arg_indirect_ref (addr);
7180 /* Return nonzero if OPNUM's MEM should be matched
7181 in movabs* patterns. */
7184 ix86_check_movabs (rtx insn, int opnum)
7188 set = PATTERN (insn);
7189 if (GET_CODE (set) == PARALLEL)
7190 set = XVECEXP (set, 0, 0);
7191 gcc_assert (GET_CODE (set) == SET);
7192 mem = XEXP (set, opnum);
7193 while (GET_CODE (mem) == SUBREG)
7194 mem = SUBREG_REG (mem);
7195 gcc_assert (MEM_P (mem));
7196 return (volatile_ok || !MEM_VOLATILE_P (mem));
7199 /* Initialize the table of extra 80387 mathematical constants. */
7202 init_ext_80387_constants (void)
7204 static const char * cst[5] =
7206 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7207 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7208 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7209 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7210 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7214 for (i = 0; i < 5; i++)
7216 real_from_string (&ext_80387_constants_table[i], cst[i]);
7217 /* Ensure each constant is rounded to XFmode precision. */
7218 real_convert (&ext_80387_constants_table[i],
7219 XFmode, &ext_80387_constants_table[i]);
7222 ext_80387_constants_init = 1;
7225 /* Return true if the constant is something that can be loaded with
7226 a special instruction. */
7229 standard_80387_constant_p (rtx x)
7231 enum machine_mode mode = GET_MODE (x);
7235 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7238 if (x == CONST0_RTX (mode))
7240 if (x == CONST1_RTX (mode))
7243 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7245 /* For XFmode constants, try to find a special 80387 instruction when
7246 optimizing for size or on those CPUs that benefit from them. */
7248 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7252 if (! ext_80387_constants_init)
7253 init_ext_80387_constants ();
7255 for (i = 0; i < 5; i++)
7256 if (real_identical (&r, &ext_80387_constants_table[i]))
7260 /* Load of the constant -0.0 or -1.0 will be split as
7261 fldz;fchs or fld1;fchs sequence. */
7262 if (real_isnegzero (&r))
7264 if (real_identical (&r, &dconstm1))
7270 /* Return the opcode of the special instruction to be used to load
7274 standard_80387_constant_opcode (rtx x)
7276 switch (standard_80387_constant_p (x))
7300 /* Return the CONST_DOUBLE representing the 80387 constant that is
7301 loaded by the specified special instruction. The argument IDX
7302 matches the return value from standard_80387_constant_p. */
7305 standard_80387_constant_rtx (int idx)
7309 if (! ext_80387_constants_init)
7310 init_ext_80387_constants ();
7326 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7330 /* Return 1 if X is all 0s and 2 if x is all 1s
7331 in supported SSE vector mode. */
7334 standard_sse_constant_p (rtx x)
7336 enum machine_mode mode = GET_MODE (x);
7338 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7340 if (vector_all_ones_operand (x, mode))
7356 /* Return the opcode of the special instruction to be used to load
7360 standard_sse_constant_opcode (rtx insn, rtx x)
7362 switch (standard_sse_constant_p (x))
7365 switch (get_attr_mode (insn))
7368 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7370 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7372 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7374 return "vxorps\t%x0, %x0, %x0";
7376 return "vxorpd\t%x0, %x0, %x0";
7378 return "vpxor\t%x0, %x0, %x0";
7383 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7390 /* Returns 1 if OP contains a symbol reference */
7393 symbolic_reference_mentioned_p (rtx op)
7398 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7401 fmt = GET_RTX_FORMAT (GET_CODE (op));
7402 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7408 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7409 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7413 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7420 /* Return 1 if it is appropriate to emit `ret' instructions in the
7421 body of a function. Do this only if the epilogue is simple, needing a
7422 couple of insns. Prior to reloading, we can't tell how many registers
7423 must be saved, so return 0 then. Return 0 if there is no frame
7424 marker to de-allocate. */
7427 ix86_can_use_return_insn_p (void)
7429 struct ix86_frame frame;
7431 if (! reload_completed || frame_pointer_needed)
7434 /* Don't allow more than 32 pop, since that's all we can do
7435 with one instruction. */
7436 if (crtl->args.pops_args
7437 && crtl->args.size >= 32768)
7440 ix86_compute_frame_layout (&frame);
7441 return frame.to_allocate == 0 && frame.padding0 == 0
7442 && (frame.nregs + frame.nsseregs) == 0;
7445 /* Value should be nonzero if functions must have frame pointers.
7446 Zero means the frame pointer need not be set up (and parms may
7447 be accessed via the stack pointer) in functions that seem suitable. */
7450 ix86_frame_pointer_required (void)
7452 /* If we accessed previous frames, then the generated code expects
7453 to be able to access the saved ebp value in our frame. */
7454 if (cfun->machine->accesses_prev_frame)
7457 /* Several x86 os'es need a frame pointer for other reasons,
7458 usually pertaining to setjmp. */
7459 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7462 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7463 the frame pointer by default. Turn it back on now if we've not
7464 got a leaf function. */
7465 if (TARGET_OMIT_LEAF_FRAME_POINTER
7466 && (!current_function_is_leaf
7467 || ix86_current_function_calls_tls_descriptor))
7476 /* Record that the current function accesses previous call frames. */
7479 ix86_setup_frame_addresses (void)
7481 cfun->machine->accesses_prev_frame = 1;
7484 #ifndef USE_HIDDEN_LINKONCE
7485 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7486 # define USE_HIDDEN_LINKONCE 1
7488 # define USE_HIDDEN_LINKONCE 0
7492 static int pic_labels_used;
7494 /* Fills in the label name that should be used for a pc thunk for
7495 the given register. */
7498 get_pc_thunk_name (char name[32], unsigned int regno)
7500 gcc_assert (!TARGET_64BIT);
7502 if (USE_HIDDEN_LINKONCE)
7503 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7505 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7509 /* This function generates code for -fpic that loads %ebx with
7510 the return address of the caller and then returns. */
7513 ix86_file_end (void)
7518 for (regno = 0; regno < 8; ++regno)
7522 if (! ((pic_labels_used >> regno) & 1))
7525 get_pc_thunk_name (name, regno);
7530 switch_to_section (darwin_sections[text_coal_section]);
7531 fputs ("\t.weak_definition\t", asm_out_file);
7532 assemble_name (asm_out_file, name);
7533 fputs ("\n\t.private_extern\t", asm_out_file);
7534 assemble_name (asm_out_file, name);
7535 fputs ("\n", asm_out_file);
7536 ASM_OUTPUT_LABEL (asm_out_file, name);
7540 if (USE_HIDDEN_LINKONCE)
7544 decl = build_decl (BUILTINS_LOCATION,
7545 FUNCTION_DECL, get_identifier (name),
7547 TREE_PUBLIC (decl) = 1;
7548 TREE_STATIC (decl) = 1;
7549 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7551 (*targetm.asm_out.unique_section) (decl, 0);
7552 switch_to_section (get_named_section (decl, NULL, 0));
7554 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7555 fputs ("\t.hidden\t", asm_out_file);
7556 assemble_name (asm_out_file, name);
7557 putc ('\n', asm_out_file);
7558 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7562 switch_to_section (text_section);
7563 ASM_OUTPUT_LABEL (asm_out_file, name);
7566 xops[0] = gen_rtx_REG (Pmode, regno);
7567 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7568 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7569 output_asm_insn ("ret", xops);
7572 if (NEED_INDICATE_EXEC_STACK)
7573 file_end_indicate_exec_stack ();
7576 /* Emit code for the SET_GOT patterns. */
7579 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7585 if (TARGET_VXWORKS_RTP && flag_pic)
7587 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7588 xops[2] = gen_rtx_MEM (Pmode,
7589 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7590 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7592 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7593 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7594 an unadorned address. */
7595 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7596 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7597 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7601 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7603 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7605 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7608 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7610 output_asm_insn ("call\t%a2", xops);
7613 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7614 is what will be referenced by the Mach-O PIC subsystem. */
7616 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7619 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7620 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7623 output_asm_insn ("pop%z0\t%0", xops);
7628 get_pc_thunk_name (name, REGNO (dest));
7629 pic_labels_used |= 1 << REGNO (dest);
7631 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7632 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7633 output_asm_insn ("call\t%X2", xops);
7634 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7635 is what will be referenced by the Mach-O PIC subsystem. */
7638 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7640 targetm.asm_out.internal_label (asm_out_file, "L",
7641 CODE_LABEL_NUMBER (label));
7648 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7649 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7651 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7656 /* Generate an "push" pattern for input ARG. */
7661 if (ix86_cfa_state->reg == stack_pointer_rtx)
7662 ix86_cfa_state->offset += UNITS_PER_WORD;
7664 return gen_rtx_SET (VOIDmode,
7666 gen_rtx_PRE_DEC (Pmode,
7667 stack_pointer_rtx)),
7671 /* Return >= 0 if there is an unused call-clobbered register available
7672 for the entire function. */
7675 ix86_select_alt_pic_regnum (void)
7677 if (current_function_is_leaf && !crtl->profile
7678 && !ix86_current_function_calls_tls_descriptor)
7681 /* Can't use the same register for both PIC and DRAP. */
7683 drap = REGNO (crtl->drap_reg);
7686 for (i = 2; i >= 0; --i)
7687 if (i != drap && !df_regs_ever_live_p (i))
7691 return INVALID_REGNUM;
7694 /* Return 1 if we need to save REGNO. */
7696 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7698 if (pic_offset_table_rtx
7699 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7700 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7702 || crtl->calls_eh_return
7703 || crtl->uses_const_pool))
7705 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7710 if (crtl->calls_eh_return && maybe_eh_return)
7715 unsigned test = EH_RETURN_DATA_REGNO (i);
7716 if (test == INVALID_REGNUM)
7723 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7726 return (df_regs_ever_live_p (regno)
7727 && !call_used_regs[regno]
7728 && !fixed_regs[regno]
7729 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7732 /* Return number of saved general prupose registers. */
7735 ix86_nsaved_regs (void)
7740 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7741 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7746 /* Return number of saved SSE registrers. */
7749 ix86_nsaved_sseregs (void)
7754 if (ix86_cfun_abi () != MS_ABI)
7756 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7757 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7762 /* Given FROM and TO register numbers, say whether this elimination is
7763 allowed. If stack alignment is needed, we can only replace argument
7764 pointer with hard frame pointer, or replace frame pointer with stack
7765 pointer. Otherwise, frame pointer elimination is automatically
7766 handled and all other eliminations are valid. */
7769 ix86_can_eliminate (const int from, const int to)
7771 if (stack_realign_fp)
7772 return ((from == ARG_POINTER_REGNUM
7773 && to == HARD_FRAME_POINTER_REGNUM)
7774 || (from == FRAME_POINTER_REGNUM
7775 && to == STACK_POINTER_REGNUM));
7777 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7780 /* Return the offset between two registers, one to be eliminated, and the other
7781 its replacement, at the start of a routine. */
7784 ix86_initial_elimination_offset (int from, int to)
7786 struct ix86_frame frame;
7787 ix86_compute_frame_layout (&frame);
7789 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7790 return frame.hard_frame_pointer_offset;
7791 else if (from == FRAME_POINTER_REGNUM
7792 && to == HARD_FRAME_POINTER_REGNUM)
7793 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7796 gcc_assert (to == STACK_POINTER_REGNUM);
7798 if (from == ARG_POINTER_REGNUM)
7799 return frame.stack_pointer_offset;
7801 gcc_assert (from == FRAME_POINTER_REGNUM);
7802 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7806 /* In a dynamically-aligned function, we can't know the offset from
7807 stack pointer to frame pointer, so we must ensure that setjmp
7808 eliminates fp against the hard fp (%ebp) rather than trying to
7809 index from %esp up to the top of the frame across a gap that is
7810 of unknown (at compile-time) size. */
7812 ix86_builtin_setjmp_frame_value (void)
7814 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7817 /* Fill structure ix86_frame about frame of currently computed function. */
7820 ix86_compute_frame_layout (struct ix86_frame *frame)
7822 unsigned int stack_alignment_needed;
7823 HOST_WIDE_INT offset;
7824 unsigned int preferred_alignment;
7825 HOST_WIDE_INT size = get_frame_size ();
7827 frame->nregs = ix86_nsaved_regs ();
7828 frame->nsseregs = ix86_nsaved_sseregs ();
7830 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7831 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7833 /* MS ABI seem to require stack alignment to be always 16 except for function
7835 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7837 preferred_alignment = 16;
7838 stack_alignment_needed = 16;
7839 crtl->preferred_stack_boundary = 128;
7840 crtl->stack_alignment_needed = 128;
7843 gcc_assert (!size || stack_alignment_needed);
7844 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7845 gcc_assert (preferred_alignment <= stack_alignment_needed);
7847 /* During reload iteration the amount of registers saved can change.
7848 Recompute the value as needed. Do not recompute when amount of registers
7849 didn't change as reload does multiple calls to the function and does not
7850 expect the decision to change within single iteration. */
7851 if (!optimize_function_for_size_p (cfun)
7852 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7854 int count = frame->nregs;
7856 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7857 /* The fast prologue uses move instead of push to save registers. This
7858 is significantly longer, but also executes faster as modern hardware
7859 can execute the moves in parallel, but can't do that for push/pop.
7861 Be careful about choosing what prologue to emit: When function takes
7862 many instructions to execute we may use slow version as well as in
7863 case function is known to be outside hot spot (this is known with
7864 feedback only). Weight the size of function by number of registers
7865 to save as it is cheap to use one or two push instructions but very
7866 slow to use many of them. */
7868 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7869 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7870 || (flag_branch_probabilities
7871 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7872 cfun->machine->use_fast_prologue_epilogue = false;
7874 cfun->machine->use_fast_prologue_epilogue
7875 = !expensive_function_p (count);
7877 if (TARGET_PROLOGUE_USING_MOVE
7878 && cfun->machine->use_fast_prologue_epilogue)
7879 frame->save_regs_using_mov = true;
7881 frame->save_regs_using_mov = false;
7883 /* Skip return address. */
7884 offset = UNITS_PER_WORD;
7886 /* Skip pushed static chain. */
7887 if (ix86_static_chain_on_stack)
7888 offset += UNITS_PER_WORD;
7890 /* Skip saved base pointer. */
7891 if (frame_pointer_needed)
7892 offset += UNITS_PER_WORD;
7894 frame->hard_frame_pointer_offset = offset;
7896 /* Set offset to aligned because the realigned frame starts from
7898 if (stack_realign_fp)
7899 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7901 /* Register save area */
7902 offset += frame->nregs * UNITS_PER_WORD;
7904 /* Align SSE reg save area. */
7905 if (frame->nsseregs)
7906 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7908 frame->padding0 = 0;
7910 /* SSE register save area. */
7911 offset += frame->padding0 + frame->nsseregs * 16;
7914 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7915 offset += frame->va_arg_size;
7917 /* Align start of frame for local function. */
7918 frame->padding1 = ((offset + stack_alignment_needed - 1)
7919 & -stack_alignment_needed) - offset;
7921 offset += frame->padding1;
7923 /* Frame pointer points here. */
7924 frame->frame_pointer_offset = offset;
7928 /* Add outgoing arguments area. Can be skipped if we eliminated
7929 all the function calls as dead code.
7930 Skipping is however impossible when function calls alloca. Alloca
7931 expander assumes that last crtl->outgoing_args_size
7932 of stack frame are unused. */
7933 if (ACCUMULATE_OUTGOING_ARGS
7934 && (!current_function_is_leaf || cfun->calls_alloca
7935 || ix86_current_function_calls_tls_descriptor))
7937 offset += crtl->outgoing_args_size;
7938 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7941 frame->outgoing_arguments_size = 0;
7943 /* Align stack boundary. Only needed if we're calling another function
7945 if (!current_function_is_leaf || cfun->calls_alloca
7946 || ix86_current_function_calls_tls_descriptor)
7947 frame->padding2 = ((offset + preferred_alignment - 1)
7948 & -preferred_alignment) - offset;
7950 frame->padding2 = 0;
7952 offset += frame->padding2;
7954 /* We've reached end of stack frame. */
7955 frame->stack_pointer_offset = offset;
7957 /* Size prologue needs to allocate. */
7958 frame->to_allocate =
7959 (size + frame->padding1 + frame->padding2
7960 + frame->outgoing_arguments_size + frame->va_arg_size);
7962 if ((!frame->to_allocate && frame->nregs <= 1)
7963 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7964 frame->save_regs_using_mov = false;
7966 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7967 && current_function_sp_is_unchanging
7968 && current_function_is_leaf
7969 && !ix86_current_function_calls_tls_descriptor)
7971 frame->red_zone_size = frame->to_allocate;
7972 if (frame->save_regs_using_mov)
7973 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7974 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7975 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7978 frame->red_zone_size = 0;
7979 frame->to_allocate -= frame->red_zone_size;
7980 frame->stack_pointer_offset -= frame->red_zone_size;
7983 /* Emit code to save registers in the prologue. */
7986 ix86_emit_save_regs (void)
7991 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7992 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7994 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7995 RTX_FRAME_RELATED_P (insn) = 1;
7999 /* Emit code to save registers using MOV insns. First register
8000 is restored from POINTER + OFFSET. */
8002 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8007 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8008 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8010 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8012 gen_rtx_REG (Pmode, regno));
8013 RTX_FRAME_RELATED_P (insn) = 1;
8014 offset += UNITS_PER_WORD;
8018 /* Emit code to save registers using MOV insns. First register
8019 is restored from POINTER + OFFSET. */
8021 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8027 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8028 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8030 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8031 set_mem_align (mem, 128);
8032 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8033 RTX_FRAME_RELATED_P (insn) = 1;
8038 static GTY(()) rtx queued_cfa_restores;
8040 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8041 manipulation insn. Don't add it if the previously
8042 saved value will be left untouched within stack red-zone till return,
8043 as unwinders can find the same value in the register and
8047 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8050 && !TARGET_64BIT_MS_ABI
8051 && red_offset + RED_ZONE_SIZE >= 0
8052 && crtl->args.pops_args < 65536)
8057 add_reg_note (insn, REG_CFA_RESTORE, reg);
8058 RTX_FRAME_RELATED_P (insn) = 1;
8062 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8065 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8068 ix86_add_queued_cfa_restore_notes (rtx insn)
8071 if (!queued_cfa_restores)
8073 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8075 XEXP (last, 1) = REG_NOTES (insn);
8076 REG_NOTES (insn) = queued_cfa_restores;
8077 queued_cfa_restores = NULL_RTX;
8078 RTX_FRAME_RELATED_P (insn) = 1;
8081 /* Expand prologue or epilogue stack adjustment.
8082 The pattern exist to put a dependency on all ebp-based memory accesses.
8083 STYLE should be negative if instructions should be marked as frame related,
8084 zero if %r11 register is live and cannot be freely used and positive
8088 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8089 int style, bool set_cfa)
8094 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8095 else if (x86_64_immediate_operand (offset, DImode))
8096 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8100 /* r11 is used by indirect sibcall return as well, set before the
8101 epilogue and used after the epilogue. ATM indirect sibcall
8102 shouldn't be used together with huge frame sizes in one
8103 function because of the frame_size check in sibcall.c. */
8105 r11 = gen_rtx_REG (DImode, R11_REG);
8106 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8108 RTX_FRAME_RELATED_P (insn) = 1;
8109 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8114 ix86_add_queued_cfa_restore_notes (insn);
8120 gcc_assert (ix86_cfa_state->reg == src);
8121 ix86_cfa_state->offset += INTVAL (offset);
8122 ix86_cfa_state->reg = dest;
8124 r = gen_rtx_PLUS (Pmode, src, offset);
8125 r = gen_rtx_SET (VOIDmode, dest, r);
8126 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8127 RTX_FRAME_RELATED_P (insn) = 1;
8130 RTX_FRAME_RELATED_P (insn) = 1;
8133 /* Find an available register to be used as dynamic realign argument
8134 pointer regsiter. Such a register will be written in prologue and
8135 used in begin of body, so it must not be
8136 1. parameter passing register.
8138 We reuse static-chain register if it is available. Otherwise, we
8139 use DI for i386 and R13 for x86-64. We chose R13 since it has
8142 Return: the regno of chosen register. */
8145 find_drap_reg (void)
8147 tree decl = cfun->decl;
8151 /* Use R13 for nested function or function need static chain.
8152 Since function with tail call may use any caller-saved
8153 registers in epilogue, DRAP must not use caller-saved
8154 register in such case. */
8155 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8162 /* Use DI for nested function or function need static chain.
8163 Since function with tail call may use any caller-saved
8164 registers in epilogue, DRAP must not use caller-saved
8165 register in such case. */
8166 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8169 /* Reuse static chain register if it isn't used for parameter
8171 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8172 && !lookup_attribute ("fastcall",
8173 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8180 /* Update incoming stack boundary and estimated stack alignment. */
8183 ix86_update_stack_boundary (void)
8185 /* Prefer the one specified at command line. */
8186 ix86_incoming_stack_boundary
8187 = (ix86_user_incoming_stack_boundary
8188 ? ix86_user_incoming_stack_boundary
8189 : ix86_default_incoming_stack_boundary);
8191 /* Incoming stack alignment can be changed on individual functions
8192 via force_align_arg_pointer attribute. We use the smallest
8193 incoming stack boundary. */
8194 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8195 && lookup_attribute (ix86_force_align_arg_pointer_string,
8196 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8197 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8199 /* The incoming stack frame has to be aligned at least at
8200 parm_stack_boundary. */
8201 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8202 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8204 /* Stack at entrance of main is aligned by runtime. We use the
8205 smallest incoming stack boundary. */
8206 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8207 && DECL_NAME (current_function_decl)
8208 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8209 && DECL_FILE_SCOPE_P (current_function_decl))
8210 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8212 /* x86_64 vararg needs 16byte stack alignment for register save
8216 && crtl->stack_alignment_estimated < 128)
8217 crtl->stack_alignment_estimated = 128;
8220 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8221 needed or an rtx for DRAP otherwise. */
8224 ix86_get_drap_rtx (void)
8226 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8227 crtl->need_drap = true;
8229 if (stack_realign_drap)
8231 /* Assign DRAP to vDRAP and returns vDRAP */
8232 unsigned int regno = find_drap_reg ();
8237 arg_ptr = gen_rtx_REG (Pmode, regno);
8238 crtl->drap_reg = arg_ptr;
8241 drap_vreg = copy_to_reg (arg_ptr);
8245 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8246 RTX_FRAME_RELATED_P (insn) = 1;
8253 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8256 ix86_internal_arg_pointer (void)
8258 return virtual_incoming_args_rtx;
8261 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8262 to be generated in correct form. */
8264 ix86_finalize_stack_realign_flags (void)
8266 /* Check if stack realign is really needed after reload, and
8267 stores result in cfun */
8268 unsigned int incoming_stack_boundary
8269 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8270 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8271 unsigned int stack_realign = (incoming_stack_boundary
8272 < (current_function_is_leaf
8273 ? crtl->max_used_stack_slot_alignment
8274 : crtl->stack_alignment_needed));
8276 if (crtl->stack_realign_finalized)
8278 /* After stack_realign_needed is finalized, we can't no longer
8280 gcc_assert (crtl->stack_realign_needed == stack_realign);
8284 crtl->stack_realign_needed = stack_realign;
8285 crtl->stack_realign_finalized = true;
8289 /* Expand the prologue into a bunch of separate insns. */
8292 ix86_expand_prologue (void)
8296 struct ix86_frame frame;
8297 HOST_WIDE_INT allocate;
8299 ix86_finalize_stack_realign_flags ();
8301 /* DRAP should not coexist with stack_realign_fp */
8302 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8304 /* Initialize CFA state for before the prologue. */
8305 ix86_cfa_state->reg = stack_pointer_rtx;
8306 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8308 ix86_compute_frame_layout (&frame);
8310 /* The first insn of a function that accepts its static chain on the
8311 stack is to push the register that would be filled in by a direct
8312 call. This insn will be skipped by the trampoline. */
8313 if (ix86_static_chain_on_stack)
8317 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8318 emit_insn (gen_blockage ());
8320 /* We don't want to interpret this push insn as a register save,
8321 only as a stack adjustment. The real copy of the register as
8322 a save will be done later, if needed. */
8323 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8324 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8325 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8326 RTX_FRAME_RELATED_P (insn) = 1;
8329 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8330 of DRAP is needed and stack realignment is really needed after reload */
8331 if (crtl->drap_reg && crtl->stack_realign_needed)
8334 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8335 int param_ptr_offset = UNITS_PER_WORD;
8337 if (ix86_static_chain_on_stack)
8338 param_ptr_offset += UNITS_PER_WORD;
8339 if (!call_used_regs[REGNO (crtl->drap_reg)])
8340 param_ptr_offset += UNITS_PER_WORD;
8342 gcc_assert (stack_realign_drap);
8344 /* Grab the argument pointer. */
8345 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8348 /* Only need to push parameter pointer reg if it is caller
8350 if (!call_used_regs[REGNO (crtl->drap_reg)])
8352 /* Push arg pointer reg */
8353 insn = emit_insn (gen_push (y));
8354 RTX_FRAME_RELATED_P (insn) = 1;
8357 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8358 RTX_FRAME_RELATED_P (insn) = 1;
8359 ix86_cfa_state->reg = crtl->drap_reg;
8361 /* Align the stack. */
8362 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8364 GEN_INT (-align_bytes)));
8365 RTX_FRAME_RELATED_P (insn) = 1;
8367 /* Replicate the return address on the stack so that return
8368 address can be reached via (argp - 1) slot. This is needed
8369 to implement macro RETURN_ADDR_RTX and intrinsic function
8370 expand_builtin_return_addr etc. */
8372 x = gen_frame_mem (Pmode,
8373 plus_constant (x, -UNITS_PER_WORD));
8374 insn = emit_insn (gen_push (x));
8375 RTX_FRAME_RELATED_P (insn) = 1;
8378 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8379 slower on all targets. Also sdb doesn't like it. */
8381 if (frame_pointer_needed)
8383 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8384 RTX_FRAME_RELATED_P (insn) = 1;
8386 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8387 RTX_FRAME_RELATED_P (insn) = 1;
8389 if (ix86_cfa_state->reg == stack_pointer_rtx)
8390 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8393 if (stack_realign_fp)
8395 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8396 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8398 /* Align the stack. */
8399 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8401 GEN_INT (-align_bytes)));
8402 RTX_FRAME_RELATED_P (insn) = 1;
8405 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8407 if (!frame.save_regs_using_mov)
8408 ix86_emit_save_regs ();
8410 allocate += frame.nregs * UNITS_PER_WORD;
8412 /* When using red zone we may start register saving before allocating
8413 the stack frame saving one cycle of the prologue. However I will
8414 avoid doing this if I am going to have to probe the stack since
8415 at least on x86_64 the stack probe can turn into a call that clobbers
8416 a red zone location */
8417 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8418 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8419 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8420 && !crtl->stack_realign_needed)
8421 ? hard_frame_pointer_rtx
8422 : stack_pointer_rtx,
8423 -frame.nregs * UNITS_PER_WORD);
8427 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8428 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8429 GEN_INT (-allocate), -1,
8430 ix86_cfa_state->reg == stack_pointer_rtx);
8433 /* Only valid for Win32. */
8434 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8438 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8440 if (cfun->machine->call_abi == MS_ABI)
8443 eax_live = ix86_eax_live_at_start_p ();
8447 emit_insn (gen_push (eax));
8448 allocate -= UNITS_PER_WORD;
8451 emit_move_insn (eax, GEN_INT (allocate));
8454 insn = gen_allocate_stack_worker_64 (eax, eax);
8456 insn = gen_allocate_stack_worker_32 (eax, eax);
8457 insn = emit_insn (insn);
8459 if (ix86_cfa_state->reg == stack_pointer_rtx)
8461 ix86_cfa_state->offset += allocate;
8462 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8463 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8464 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8465 RTX_FRAME_RELATED_P (insn) = 1;
8470 if (frame_pointer_needed)
8471 t = plus_constant (hard_frame_pointer_rtx,
8474 - frame.nregs * UNITS_PER_WORD);
8476 t = plus_constant (stack_pointer_rtx, allocate);
8477 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8481 if (frame.save_regs_using_mov
8482 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8483 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8485 if (!frame_pointer_needed
8486 || !(frame.to_allocate + frame.padding0)
8487 || crtl->stack_realign_needed)
8488 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8490 + frame.nsseregs * 16 + frame.padding0);
8492 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8493 -frame.nregs * UNITS_PER_WORD);
8495 if (!frame_pointer_needed
8496 || !(frame.to_allocate + frame.padding0)
8497 || crtl->stack_realign_needed)
8498 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8501 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8502 - frame.nregs * UNITS_PER_WORD
8503 - frame.nsseregs * 16
8506 pic_reg_used = false;
8507 if (pic_offset_table_rtx
8508 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8511 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8513 if (alt_pic_reg_used != INVALID_REGNUM)
8514 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8516 pic_reg_used = true;
8523 if (ix86_cmodel == CM_LARGE_PIC)
8525 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8526 rtx label = gen_label_rtx ();
8528 LABEL_PRESERVE_P (label) = 1;
8529 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8530 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8531 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8532 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8533 pic_offset_table_rtx, tmp_reg));
8536 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8539 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8542 /* In the pic_reg_used case, make sure that the got load isn't deleted
8543 when mcount needs it. Blockage to avoid call movement across mcount
8544 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8546 if (crtl->profile && pic_reg_used)
8547 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8549 if (crtl->drap_reg && !crtl->stack_realign_needed)
8551 /* vDRAP is setup but after reload it turns out stack realign
8552 isn't necessary, here we will emit prologue to setup DRAP
8553 without stack realign adjustment */
8555 int drap_bp_offset = UNITS_PER_WORD * 2;
8557 if (ix86_static_chain_on_stack)
8558 drap_bp_offset += UNITS_PER_WORD;
8559 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8560 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8563 /* Prevent instructions from being scheduled into register save push
8564 sequence when access to the redzone area is done through frame pointer.
8565 The offset between the frame pointer and the stack pointer is calculated
8566 relative to the value of the stack pointer at the end of the function
8567 prologue, and moving instructions that access redzone area via frame
8568 pointer inside push sequence violates this assumption. */
8569 if (frame_pointer_needed && frame.red_zone_size)
8570 emit_insn (gen_memory_blockage ());
8572 /* Emit cld instruction if stringops are used in the function. */
8573 if (TARGET_CLD && ix86_current_function_needs_cld)
8574 emit_insn (gen_cld ());
8577 /* Emit code to restore REG using a POP insn. */
8580 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8582 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8584 if (ix86_cfa_state->reg == crtl->drap_reg
8585 && REGNO (reg) == REGNO (crtl->drap_reg))
8587 /* Previously we'd represented the CFA as an expression
8588 like *(%ebp - 8). We've just popped that value from
8589 the stack, which means we need to reset the CFA to
8590 the drap register. This will remain until we restore
8591 the stack pointer. */
8592 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8593 RTX_FRAME_RELATED_P (insn) = 1;
8597 if (ix86_cfa_state->reg == stack_pointer_rtx)
8599 ix86_cfa_state->offset -= UNITS_PER_WORD;
8600 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8601 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8602 RTX_FRAME_RELATED_P (insn) = 1;
8605 /* When the frame pointer is the CFA, and we pop it, we are
8606 swapping back to the stack pointer as the CFA. This happens
8607 for stack frames that don't allocate other data, so we assume
8608 the stack pointer is now pointing at the return address, i.e.
8609 the function entry state, which makes the offset be 1 word. */
8610 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8611 && reg == hard_frame_pointer_rtx)
8613 ix86_cfa_state->reg = stack_pointer_rtx;
8614 ix86_cfa_state->offset -= UNITS_PER_WORD;
8616 add_reg_note (insn, REG_CFA_DEF_CFA,
8617 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8618 GEN_INT (ix86_cfa_state->offset)));
8619 RTX_FRAME_RELATED_P (insn) = 1;
8622 ix86_add_cfa_restore_note (insn, reg, red_offset);
8625 /* Emit code to restore saved registers using POP insns. */
8628 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8632 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8633 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8635 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8637 red_offset += UNITS_PER_WORD;
8641 /* Emit code and notes for the LEAVE instruction. */
8644 ix86_emit_leave (HOST_WIDE_INT red_offset)
8646 rtx insn = emit_insn (ix86_gen_leave ());
8648 ix86_add_queued_cfa_restore_notes (insn);
8650 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8652 ix86_cfa_state->reg = stack_pointer_rtx;
8653 ix86_cfa_state->offset -= UNITS_PER_WORD;
8655 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8656 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8657 RTX_FRAME_RELATED_P (insn) = 1;
8658 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8662 /* Emit code to restore saved registers using MOV insns. First register
8663 is restored from POINTER + OFFSET. */
8665 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8666 HOST_WIDE_INT red_offset,
8667 int maybe_eh_return)
8670 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8673 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8674 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8676 rtx reg = gen_rtx_REG (Pmode, regno);
8678 /* Ensure that adjust_address won't be forced to produce pointer
8679 out of range allowed by x86-64 instruction set. */
8680 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8684 r11 = gen_rtx_REG (DImode, R11_REG);
8685 emit_move_insn (r11, GEN_INT (offset));
8686 emit_insn (gen_adddi3 (r11, r11, pointer));
8687 base_address = gen_rtx_MEM (Pmode, r11);
8690 insn = emit_move_insn (reg,
8691 adjust_address (base_address, Pmode, offset));
8692 offset += UNITS_PER_WORD;
8694 if (ix86_cfa_state->reg == crtl->drap_reg
8695 && regno == REGNO (crtl->drap_reg))
8697 /* Previously we'd represented the CFA as an expression
8698 like *(%ebp - 8). We've just popped that value from
8699 the stack, which means we need to reset the CFA to
8700 the drap register. This will remain until we restore
8701 the stack pointer. */
8702 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8703 RTX_FRAME_RELATED_P (insn) = 1;
8706 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8708 red_offset += UNITS_PER_WORD;
8712 /* Emit code to restore saved registers using MOV insns. First register
8713 is restored from POINTER + OFFSET. */
8715 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8716 HOST_WIDE_INT red_offset,
8717 int maybe_eh_return)
8720 rtx base_address = gen_rtx_MEM (TImode, pointer);
8723 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8724 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8726 rtx reg = gen_rtx_REG (TImode, regno);
8728 /* Ensure that adjust_address won't be forced to produce pointer
8729 out of range allowed by x86-64 instruction set. */
8730 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8734 r11 = gen_rtx_REG (DImode, R11_REG);
8735 emit_move_insn (r11, GEN_INT (offset));
8736 emit_insn (gen_adddi3 (r11, r11, pointer));
8737 base_address = gen_rtx_MEM (TImode, r11);
8740 mem = adjust_address (base_address, TImode, offset);
8741 set_mem_align (mem, 128);
8742 insn = emit_move_insn (reg, mem);
8745 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8751 /* Restore function stack, frame, and registers. */
8754 ix86_expand_epilogue (int style)
8757 struct ix86_frame frame;
8758 HOST_WIDE_INT offset, red_offset;
8759 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8762 ix86_finalize_stack_realign_flags ();
8764 /* When stack is realigned, SP must be valid. */
8765 sp_valid = (!frame_pointer_needed
8766 || current_function_sp_is_unchanging
8767 || stack_realign_fp);
8769 ix86_compute_frame_layout (&frame);
8771 /* See the comment about red zone and frame
8772 pointer usage in ix86_expand_prologue. */
8773 if (frame_pointer_needed && frame.red_zone_size)
8774 emit_insn (gen_memory_blockage ());
8776 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8777 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8779 /* Calculate start of saved registers relative to ebp. Special care
8780 must be taken for the normal return case of a function using
8781 eh_return: the eax and edx registers are marked as saved, but not
8782 restored along this path. */
8783 offset = frame.nregs;
8784 if (crtl->calls_eh_return && style != 2)
8786 offset *= -UNITS_PER_WORD;
8787 offset -= frame.nsseregs * 16 + frame.padding0;
8789 /* Calculate start of saved registers relative to esp on entry of the
8790 function. When realigning stack, this needs to be the most negative
8791 value possible at runtime. */
8792 red_offset = offset;
8794 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8796 else if (stack_realign_fp)
8797 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8799 if (ix86_static_chain_on_stack)
8800 red_offset -= UNITS_PER_WORD;
8801 if (frame_pointer_needed)
8802 red_offset -= UNITS_PER_WORD;
8804 /* If we're only restoring one register and sp is not valid then
8805 using a move instruction to restore the register since it's
8806 less work than reloading sp and popping the register.
8808 The default code result in stack adjustment using add/lea instruction,
8809 while this code results in LEAVE instruction (or discrete equivalent),
8810 so it is profitable in some other cases as well. Especially when there
8811 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8812 and there is exactly one register to pop. This heuristic may need some
8813 tuning in future. */
8814 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8815 || (TARGET_EPILOGUE_USING_MOVE
8816 && cfun->machine->use_fast_prologue_epilogue
8817 && ((frame.nregs + frame.nsseregs) > 1
8818 || (frame.to_allocate + frame.padding0) != 0))
8819 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8820 && (frame.to_allocate + frame.padding0) != 0)
8821 || (frame_pointer_needed && TARGET_USE_LEAVE
8822 && cfun->machine->use_fast_prologue_epilogue
8823 && (frame.nregs + frame.nsseregs) == 1)
8824 || crtl->calls_eh_return)
8826 /* Restore registers. We can use ebp or esp to address the memory
8827 locations. If both are available, default to ebp, since offsets
8828 are known to be small. Only exception is esp pointing directly
8829 to the end of block of saved registers, where we may simplify
8832 If we are realigning stack with bp and sp, regs restore can't
8833 be addressed by bp. sp must be used instead. */
8835 if (!frame_pointer_needed
8836 || (sp_valid && !(frame.to_allocate + frame.padding0))
8837 || stack_realign_fp)
8839 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8840 frame.to_allocate, red_offset,
8842 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8844 + frame.nsseregs * 16
8847 + frame.nsseregs * 16
8848 + frame.padding0, style == 2);
8852 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8855 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8857 + frame.nsseregs * 16
8860 + frame.nsseregs * 16
8861 + frame.padding0, style == 2);
8864 red_offset -= offset;
8866 /* eh_return epilogues need %ecx added to the stack pointer. */
8869 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8871 /* Stack align doesn't work with eh_return. */
8872 gcc_assert (!crtl->stack_realign_needed);
8873 /* Neither does regparm nested functions. */
8874 gcc_assert (!ix86_static_chain_on_stack);
8876 if (frame_pointer_needed)
8878 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8879 tmp = plus_constant (tmp, UNITS_PER_WORD);
8880 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8882 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8883 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8885 /* Note that we use SA as a temporary CFA, as the return
8886 address is at the proper place relative to it. We
8887 pretend this happens at the FP restore insn because
8888 prior to this insn the FP would be stored at the wrong
8889 offset relative to SA, and after this insn we have no
8890 other reasonable register to use for the CFA. We don't
8891 bother resetting the CFA to the SP for the duration of
8893 add_reg_note (tmp, REG_CFA_DEF_CFA,
8894 plus_constant (sa, UNITS_PER_WORD));
8895 ix86_add_queued_cfa_restore_notes (tmp);
8896 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8897 RTX_FRAME_RELATED_P (tmp) = 1;
8898 ix86_cfa_state->reg = sa;
8899 ix86_cfa_state->offset = UNITS_PER_WORD;
8901 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8902 const0_rtx, style, false);
8906 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8907 tmp = plus_constant (tmp, (frame.to_allocate
8908 + frame.nregs * UNITS_PER_WORD
8909 + frame.nsseregs * 16
8911 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8912 ix86_add_queued_cfa_restore_notes (tmp);
8914 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8915 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8917 ix86_cfa_state->offset = UNITS_PER_WORD;
8918 add_reg_note (tmp, REG_CFA_DEF_CFA,
8919 plus_constant (stack_pointer_rtx,
8921 RTX_FRAME_RELATED_P (tmp) = 1;
8925 else if (!frame_pointer_needed)
8926 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8927 GEN_INT (frame.to_allocate
8928 + frame.nregs * UNITS_PER_WORD
8929 + frame.nsseregs * 16
8931 style, !using_drap);
8932 /* If not an i386, mov & pop is faster than "leave". */
8933 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8934 || !cfun->machine->use_fast_prologue_epilogue)
8935 ix86_emit_leave (red_offset);
8938 pro_epilogue_adjust_stack (stack_pointer_rtx,
8939 hard_frame_pointer_rtx,
8940 const0_rtx, style, !using_drap);
8942 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
8947 /* First step is to deallocate the stack frame so that we can
8950 If we realign stack with frame pointer, then stack pointer
8951 won't be able to recover via lea $offset(%bp), %sp, because
8952 there is a padding area between bp and sp for realign.
8953 "add $to_allocate, %sp" must be used instead. */
8956 gcc_assert (frame_pointer_needed);
8957 gcc_assert (!stack_realign_fp);
8958 pro_epilogue_adjust_stack (stack_pointer_rtx,
8959 hard_frame_pointer_rtx,
8960 GEN_INT (offset), style, false);
8961 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8964 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8965 GEN_INT (frame.nsseregs * 16 + frame.padding0),
8968 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8970 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8971 frame.to_allocate, red_offset,
8973 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8974 GEN_INT (frame.to_allocate
8975 + frame.nsseregs * 16
8976 + frame.padding0), style,
8977 !using_drap && !frame_pointer_needed);
8980 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
8982 red_offset -= offset;
8984 if (frame_pointer_needed)
8986 /* Leave results in shorter dependency chains on CPUs that are
8987 able to grok it fast. */
8988 if (TARGET_USE_LEAVE)
8989 ix86_emit_leave (red_offset);
8992 /* For stack realigned really happens, recover stack
8993 pointer to hard frame pointer is a must, if not using
8995 if (stack_realign_fp)
8996 pro_epilogue_adjust_stack (stack_pointer_rtx,
8997 hard_frame_pointer_rtx,
8998 const0_rtx, style, !using_drap);
8999 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
9007 int param_ptr_offset = UNITS_PER_WORD;
9010 gcc_assert (stack_realign_drap);
9012 if (ix86_static_chain_on_stack)
9013 param_ptr_offset += UNITS_PER_WORD;
9014 if (!call_used_regs[REGNO (crtl->drap_reg)])
9015 param_ptr_offset += UNITS_PER_WORD;
9017 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9019 GEN_INT (-param_ptr_offset)));
9021 ix86_cfa_state->reg = stack_pointer_rtx;
9022 ix86_cfa_state->offset = param_ptr_offset;
9024 add_reg_note (insn, REG_CFA_DEF_CFA,
9025 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9026 GEN_INT (ix86_cfa_state->offset)));
9027 RTX_FRAME_RELATED_P (insn) = 1;
9029 if (!call_used_regs[REGNO (crtl->drap_reg)])
9030 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9033 /* Remove the saved static chain from the stack. The use of ECX is
9034 merely as a scratch register, not as the actual static chain. */
9035 if (ix86_static_chain_on_stack)
9039 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9040 ix86_cfa_state->offset += UNITS_PER_WORD;
9042 r = gen_rtx_REG (Pmode, CX_REG);
9043 insn = emit_insn (ix86_gen_pop1 (r));
9045 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9046 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9047 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9048 RTX_FRAME_RELATED_P (insn) = 1;
9051 /* Sibcall epilogues don't want a return instruction. */
9054 *ix86_cfa_state = cfa_state_save;
9058 if (crtl->args.pops_args && crtl->args.size)
9060 rtx popc = GEN_INT (crtl->args.pops_args);
9062 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9063 address, do explicit add, and jump indirectly to the caller. */
9065 if (crtl->args.pops_args >= 65536)
9067 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9070 /* There is no "pascal" calling convention in any 64bit ABI. */
9071 gcc_assert (!TARGET_64BIT);
9073 insn = emit_insn (gen_popsi1 (ecx));
9074 ix86_cfa_state->offset -= UNITS_PER_WORD;
9076 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9077 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9078 add_reg_note (insn, REG_CFA_REGISTER,
9079 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9080 RTX_FRAME_RELATED_P (insn) = 1;
9082 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9084 emit_jump_insn (gen_return_indirect_internal (ecx));
9087 emit_jump_insn (gen_return_pop_internal (popc));
9090 emit_jump_insn (gen_return_internal ());
9092 /* Restore the state back to the state from the prologue,
9093 so that it's correct for the next epilogue. */
9094 *ix86_cfa_state = cfa_state_save;
9097 /* Reset from the function's potential modifications. */
9100 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9101 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9103 if (pic_offset_table_rtx)
9104 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9106 /* Mach-O doesn't support labels at the end of objects, so if
9107 it looks like we might want one, insert a NOP. */
9109 rtx insn = get_last_insn ();
9112 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9113 insn = PREV_INSN (insn);
9117 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9118 fputs ("\tnop\n", file);
9124 /* Extract the parts of an RTL expression that is a valid memory address
9125 for an instruction. Return 0 if the structure of the address is
9126 grossly off. Return -1 if the address contains ASHIFT, so it is not
9127 strictly valid, but still used for computing length of lea instruction. */
9130 ix86_decompose_address (rtx addr, struct ix86_address *out)
9132 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9133 rtx base_reg, index_reg;
9134 HOST_WIDE_INT scale = 1;
9135 rtx scale_rtx = NULL_RTX;
9137 enum ix86_address_seg seg = SEG_DEFAULT;
9139 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9141 else if (GET_CODE (addr) == PLUS)
9151 addends[n++] = XEXP (op, 1);
9154 while (GET_CODE (op) == PLUS);
9159 for (i = n; i >= 0; --i)
9162 switch (GET_CODE (op))
9167 index = XEXP (op, 0);
9168 scale_rtx = XEXP (op, 1);
9172 if (XINT (op, 1) == UNSPEC_TP
9173 && TARGET_TLS_DIRECT_SEG_REFS
9174 && seg == SEG_DEFAULT)
9175 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9204 else if (GET_CODE (addr) == MULT)
9206 index = XEXP (addr, 0); /* index*scale */
9207 scale_rtx = XEXP (addr, 1);
9209 else if (GET_CODE (addr) == ASHIFT)
9213 /* We're called for lea too, which implements ashift on occasion. */
9214 index = XEXP (addr, 0);
9215 tmp = XEXP (addr, 1);
9216 if (!CONST_INT_P (tmp))
9218 scale = INTVAL (tmp);
9219 if ((unsigned HOST_WIDE_INT) scale > 3)
9225 disp = addr; /* displacement */
9227 /* Extract the integral value of scale. */
9230 if (!CONST_INT_P (scale_rtx))
9232 scale = INTVAL (scale_rtx);
9235 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9236 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9238 /* Avoid useless 0 displacement. */
9239 if (disp == const0_rtx && (base || index))
9242 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9243 if (base_reg && index_reg && scale == 1
9244 && (index_reg == arg_pointer_rtx
9245 || index_reg == frame_pointer_rtx
9246 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9249 tmp = base, base = index, index = tmp;
9250 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9253 /* Special case: %ebp cannot be encoded as a base without a displacement.
9257 && (base_reg == hard_frame_pointer_rtx
9258 || base_reg == frame_pointer_rtx
9259 || base_reg == arg_pointer_rtx
9260 || (REG_P (base_reg)
9261 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9262 || REGNO (base_reg) == R13_REG))))
9265 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9266 Avoid this by transforming to [%esi+0].
9267 Reload calls address legitimization without cfun defined, so we need
9268 to test cfun for being non-NULL. */
9269 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9270 && base_reg && !index_reg && !disp
9272 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9275 /* Special case: encode reg+reg instead of reg*2. */
9276 if (!base && index && scale == 2)
9277 base = index, base_reg = index_reg, scale = 1;
9279 /* Special case: scaling cannot be encoded without base or displacement. */
9280 if (!base && !disp && index && scale != 1)
9292 /* Return cost of the memory address x.
9293 For i386, it is better to use a complex address than let gcc copy
9294 the address into a reg and make a new pseudo. But not if the address
9295 requires to two regs - that would mean more pseudos with longer
9298 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9300 struct ix86_address parts;
9302 int ok = ix86_decompose_address (x, &parts);
9306 if (parts.base && GET_CODE (parts.base) == SUBREG)
9307 parts.base = SUBREG_REG (parts.base);
9308 if (parts.index && GET_CODE (parts.index) == SUBREG)
9309 parts.index = SUBREG_REG (parts.index);
9311 /* Attempt to minimize number of registers in the address. */
9313 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9315 && (!REG_P (parts.index)
9316 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9320 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9322 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9323 && parts.base != parts.index)
9326 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9327 since it's predecode logic can't detect the length of instructions
9328 and it degenerates to vector decoded. Increase cost of such
9329 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9330 to split such addresses or even refuse such addresses at all.
9332 Following addressing modes are affected:
9337 The first and last case may be avoidable by explicitly coding the zero in
9338 memory address, but I don't have AMD-K6 machine handy to check this
9342 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9343 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9344 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9350 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9351 this is used for to form addresses to local data when -fPIC is in
9355 darwin_local_data_pic (rtx disp)
9357 return (GET_CODE (disp) == UNSPEC
9358 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9361 /* Determine if a given RTX is a valid constant. We already know this
9362 satisfies CONSTANT_P. */
9365 legitimate_constant_p (rtx x)
9367 switch (GET_CODE (x))
9372 if (GET_CODE (x) == PLUS)
9374 if (!CONST_INT_P (XEXP (x, 1)))
9379 if (TARGET_MACHO && darwin_local_data_pic (x))
9382 /* Only some unspecs are valid as "constants". */
9383 if (GET_CODE (x) == UNSPEC)
9384 switch (XINT (x, 1))
9389 return TARGET_64BIT;
9392 x = XVECEXP (x, 0, 0);
9393 return (GET_CODE (x) == SYMBOL_REF
9394 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9396 x = XVECEXP (x, 0, 0);
9397 return (GET_CODE (x) == SYMBOL_REF
9398 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9403 /* We must have drilled down to a symbol. */
9404 if (GET_CODE (x) == LABEL_REF)
9406 if (GET_CODE (x) != SYMBOL_REF)
9411 /* TLS symbols are never valid. */
9412 if (SYMBOL_REF_TLS_MODEL (x))
9415 /* DLLIMPORT symbols are never valid. */
9416 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9417 && SYMBOL_REF_DLLIMPORT_P (x))
9422 if (GET_MODE (x) == TImode
9423 && x != CONST0_RTX (TImode)
9429 if (!standard_sse_constant_p (x))
9436 /* Otherwise we handle everything else in the move patterns. */
9440 /* Determine if it's legal to put X into the constant pool. This
9441 is not possible for the address of thread-local symbols, which
9442 is checked above. */
9445 ix86_cannot_force_const_mem (rtx x)
9447 /* We can always put integral constants and vectors in memory. */
9448 switch (GET_CODE (x))
9458 return !legitimate_constant_p (x);
9462 /* Nonzero if the constant value X is a legitimate general operand
9463 when generating PIC code. It is given that flag_pic is on and
9464 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9467 legitimate_pic_operand_p (rtx x)
9471 switch (GET_CODE (x))
9474 inner = XEXP (x, 0);
9475 if (GET_CODE (inner) == PLUS
9476 && CONST_INT_P (XEXP (inner, 1)))
9477 inner = XEXP (inner, 0);
9479 /* Only some unspecs are valid as "constants". */
9480 if (GET_CODE (inner) == UNSPEC)
9481 switch (XINT (inner, 1))
9486 return TARGET_64BIT;
9488 x = XVECEXP (inner, 0, 0);
9489 return (GET_CODE (x) == SYMBOL_REF
9490 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9491 case UNSPEC_MACHOPIC_OFFSET:
9492 return legitimate_pic_address_disp_p (x);
9500 return legitimate_pic_address_disp_p (x);
9507 /* Determine if a given CONST RTX is a valid memory displacement
9511 legitimate_pic_address_disp_p (rtx disp)
9515 /* In 64bit mode we can allow direct addresses of symbols and labels
9516 when they are not dynamic symbols. */
9519 rtx op0 = disp, op1;
9521 switch (GET_CODE (disp))
9527 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9529 op0 = XEXP (XEXP (disp, 0), 0);
9530 op1 = XEXP (XEXP (disp, 0), 1);
9531 if (!CONST_INT_P (op1)
9532 || INTVAL (op1) >= 16*1024*1024
9533 || INTVAL (op1) < -16*1024*1024)
9535 if (GET_CODE (op0) == LABEL_REF)
9537 if (GET_CODE (op0) != SYMBOL_REF)
9542 /* TLS references should always be enclosed in UNSPEC. */
9543 if (SYMBOL_REF_TLS_MODEL (op0))
9545 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9546 && ix86_cmodel != CM_LARGE_PIC)
9554 if (GET_CODE (disp) != CONST)
9556 disp = XEXP (disp, 0);
9560 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9561 of GOT tables. We should not need these anyway. */
9562 if (GET_CODE (disp) != UNSPEC
9563 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9564 && XINT (disp, 1) != UNSPEC_GOTOFF
9565 && XINT (disp, 1) != UNSPEC_PLTOFF))
9568 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9569 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9575 if (GET_CODE (disp) == PLUS)
9577 if (!CONST_INT_P (XEXP (disp, 1)))
9579 disp = XEXP (disp, 0);
9583 if (TARGET_MACHO && darwin_local_data_pic (disp))
9586 if (GET_CODE (disp) != UNSPEC)
9589 switch (XINT (disp, 1))
9594 /* We need to check for both symbols and labels because VxWorks loads
9595 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9597 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9598 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9600 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9601 While ABI specify also 32bit relocation but we don't produce it in
9602 small PIC model at all. */
9603 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9604 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9606 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9608 case UNSPEC_GOTTPOFF:
9609 case UNSPEC_GOTNTPOFF:
9610 case UNSPEC_INDNTPOFF:
9613 disp = XVECEXP (disp, 0, 0);
9614 return (GET_CODE (disp) == SYMBOL_REF
9615 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9617 disp = XVECEXP (disp, 0, 0);
9618 return (GET_CODE (disp) == SYMBOL_REF
9619 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9621 disp = XVECEXP (disp, 0, 0);
9622 return (GET_CODE (disp) == SYMBOL_REF
9623 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9629 /* Recognizes RTL expressions that are valid memory addresses for an
9630 instruction. The MODE argument is the machine mode for the MEM
9631 expression that wants to use this address.
9633 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9634 convert common non-canonical forms to canonical form so that they will
9638 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9639 rtx addr, bool strict)
9641 struct ix86_address parts;
9642 rtx base, index, disp;
9643 HOST_WIDE_INT scale;
9645 if (ix86_decompose_address (addr, &parts) <= 0)
9646 /* Decomposition failed. */
9650 index = parts.index;
9652 scale = parts.scale;
9654 /* Validate base register.
9656 Don't allow SUBREG's that span more than a word here. It can lead to spill
9657 failures when the base is one word out of a two word structure, which is
9658 represented internally as a DImode int. */
9666 else if (GET_CODE (base) == SUBREG
9667 && REG_P (SUBREG_REG (base))
9668 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9670 reg = SUBREG_REG (base);
9672 /* Base is not a register. */
9675 if (GET_MODE (base) != Pmode)
9676 /* Base is not in Pmode. */
9679 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9680 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9681 /* Base is not valid. */
9685 /* Validate index register.
9687 Don't allow SUBREG's that span more than a word here -- same as above. */
9695 else if (GET_CODE (index) == SUBREG
9696 && REG_P (SUBREG_REG (index))
9697 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9699 reg = SUBREG_REG (index);
9701 /* Index is not a register. */
9704 if (GET_MODE (index) != Pmode)
9705 /* Index is not in Pmode. */
9708 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9709 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9710 /* Index is not valid. */
9714 /* Validate scale factor. */
9718 /* Scale without index. */
9721 if (scale != 2 && scale != 4 && scale != 8)
9722 /* Scale is not a valid multiplier. */
9726 /* Validate displacement. */
9729 if (GET_CODE (disp) == CONST
9730 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9731 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9732 switch (XINT (XEXP (disp, 0), 1))
9734 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9735 used. While ABI specify also 32bit relocations, we don't produce
9736 them at all and use IP relative instead. */
9739 gcc_assert (flag_pic);
9741 goto is_legitimate_pic;
9743 /* 64bit address unspec. */
9746 case UNSPEC_GOTPCREL:
9747 gcc_assert (flag_pic);
9748 goto is_legitimate_pic;
9750 case UNSPEC_GOTTPOFF:
9751 case UNSPEC_GOTNTPOFF:
9752 case UNSPEC_INDNTPOFF:
9758 /* Invalid address unspec. */
9762 else if (SYMBOLIC_CONST (disp)
9766 && MACHOPIC_INDIRECT
9767 && !machopic_operand_p (disp)
9773 if (TARGET_64BIT && (index || base))
9775 /* foo@dtpoff(%rX) is ok. */
9776 if (GET_CODE (disp) != CONST
9777 || GET_CODE (XEXP (disp, 0)) != PLUS
9778 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9779 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9780 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9781 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9782 /* Non-constant pic memory reference. */
9785 else if (! legitimate_pic_address_disp_p (disp))
9786 /* Displacement is an invalid pic construct. */
9789 /* This code used to verify that a symbolic pic displacement
9790 includes the pic_offset_table_rtx register.
9792 While this is good idea, unfortunately these constructs may
9793 be created by "adds using lea" optimization for incorrect
9802 This code is nonsensical, but results in addressing
9803 GOT table with pic_offset_table_rtx base. We can't
9804 just refuse it easily, since it gets matched by
9805 "addsi3" pattern, that later gets split to lea in the
9806 case output register differs from input. While this
9807 can be handled by separate addsi pattern for this case
9808 that never results in lea, this seems to be easier and
9809 correct fix for crash to disable this test. */
9811 else if (GET_CODE (disp) != LABEL_REF
9812 && !CONST_INT_P (disp)
9813 && (GET_CODE (disp) != CONST
9814 || !legitimate_constant_p (disp))
9815 && (GET_CODE (disp) != SYMBOL_REF
9816 || !legitimate_constant_p (disp)))
9817 /* Displacement is not constant. */
9819 else if (TARGET_64BIT
9820 && !x86_64_immediate_operand (disp, VOIDmode))
9821 /* Displacement is out of range. */
9825 /* Everything looks valid. */
9829 /* Determine if a given RTX is a valid constant address. */
9832 constant_address_p (rtx x)
9834 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9837 /* Return a unique alias set for the GOT. */
9839 static alias_set_type
9840 ix86_GOT_alias_set (void)
9842 static alias_set_type set = -1;
9844 set = new_alias_set ();
9848 /* Return a legitimate reference for ORIG (an address) using the
9849 register REG. If REG is 0, a new pseudo is generated.
9851 There are two types of references that must be handled:
9853 1. Global data references must load the address from the GOT, via
9854 the PIC reg. An insn is emitted to do this load, and the reg is
9857 2. Static data references, constant pool addresses, and code labels
9858 compute the address as an offset from the GOT, whose base is in
9859 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9860 differentiate them from global data objects. The returned
9861 address is the PIC reg + an unspec constant.
9863 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9864 reg also appears in the address. */
9867 legitimize_pic_address (rtx orig, rtx reg)
9874 if (TARGET_MACHO && !TARGET_64BIT)
9877 reg = gen_reg_rtx (Pmode);
9878 /* Use the generic Mach-O PIC machinery. */
9879 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9883 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9885 else if (TARGET_64BIT
9886 && ix86_cmodel != CM_SMALL_PIC
9887 && gotoff_operand (addr, Pmode))
9890 /* This symbol may be referenced via a displacement from the PIC
9891 base address (@GOTOFF). */
9893 if (reload_in_progress)
9894 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9895 if (GET_CODE (addr) == CONST)
9896 addr = XEXP (addr, 0);
9897 if (GET_CODE (addr) == PLUS)
9899 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9901 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9904 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9905 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9907 tmpreg = gen_reg_rtx (Pmode);
9910 emit_move_insn (tmpreg, new_rtx);
9914 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9915 tmpreg, 1, OPTAB_DIRECT);
9918 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9920 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9922 /* This symbol may be referenced via a displacement from the PIC
9923 base address (@GOTOFF). */
9925 if (reload_in_progress)
9926 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9927 if (GET_CODE (addr) == CONST)
9928 addr = XEXP (addr, 0);
9929 if (GET_CODE (addr) == PLUS)
9931 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9933 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9936 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9937 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9938 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9942 emit_move_insn (reg, new_rtx);
9946 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9947 /* We can't use @GOTOFF for text labels on VxWorks;
9948 see gotoff_operand. */
9949 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9951 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9953 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9954 return legitimize_dllimport_symbol (addr, true);
9955 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9956 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9957 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9959 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9960 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9964 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9966 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9967 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9968 new_rtx = gen_const_mem (Pmode, new_rtx);
9969 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9972 reg = gen_reg_rtx (Pmode);
9973 /* Use directly gen_movsi, otherwise the address is loaded
9974 into register for CSE. We don't want to CSE this addresses,
9975 instead we CSE addresses from the GOT table, so skip this. */
9976 emit_insn (gen_movsi (reg, new_rtx));
9981 /* This symbol must be referenced via a load from the
9982 Global Offset Table (@GOT). */
9984 if (reload_in_progress)
9985 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9986 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9987 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9989 new_rtx = force_reg (Pmode, new_rtx);
9990 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9991 new_rtx = gen_const_mem (Pmode, new_rtx);
9992 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9995 reg = gen_reg_rtx (Pmode);
9996 emit_move_insn (reg, new_rtx);
10002 if (CONST_INT_P (addr)
10003 && !x86_64_immediate_operand (addr, VOIDmode))
10007 emit_move_insn (reg, addr);
10011 new_rtx = force_reg (Pmode, addr);
10013 else if (GET_CODE (addr) == CONST)
10015 addr = XEXP (addr, 0);
10017 /* We must match stuff we generate before. Assume the only
10018 unspecs that can get here are ours. Not that we could do
10019 anything with them anyway.... */
10020 if (GET_CODE (addr) == UNSPEC
10021 || (GET_CODE (addr) == PLUS
10022 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10024 gcc_assert (GET_CODE (addr) == PLUS);
10026 if (GET_CODE (addr) == PLUS)
10028 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10030 /* Check first to see if this is a constant offset from a @GOTOFF
10031 symbol reference. */
10032 if (gotoff_operand (op0, Pmode)
10033 && CONST_INT_P (op1))
10037 if (reload_in_progress)
10038 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10039 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10041 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10042 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10043 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10047 emit_move_insn (reg, new_rtx);
10053 if (INTVAL (op1) < -16*1024*1024
10054 || INTVAL (op1) >= 16*1024*1024)
10056 if (!x86_64_immediate_operand (op1, Pmode))
10057 op1 = force_reg (Pmode, op1);
10058 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10064 base = legitimize_pic_address (XEXP (addr, 0), reg);
10065 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10066 base == reg ? NULL_RTX : reg);
10068 if (CONST_INT_P (new_rtx))
10069 new_rtx = plus_constant (base, INTVAL (new_rtx));
10072 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10074 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10075 new_rtx = XEXP (new_rtx, 1);
10077 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10085 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10088 get_thread_pointer (int to_reg)
10092 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10096 reg = gen_reg_rtx (Pmode);
10097 insn = gen_rtx_SET (VOIDmode, reg, tp);
10098 insn = emit_insn (insn);
10103 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10104 false if we expect this to be used for a memory address and true if
10105 we expect to load the address into a register. */
10108 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10110 rtx dest, base, off, pic, tp;
10115 case TLS_MODEL_GLOBAL_DYNAMIC:
10116 dest = gen_reg_rtx (Pmode);
10117 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10119 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10121 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10124 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10125 insns = get_insns ();
10128 RTL_CONST_CALL_P (insns) = 1;
10129 emit_libcall_block (insns, dest, rax, x);
10131 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10132 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10134 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10136 if (TARGET_GNU2_TLS)
10138 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10140 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10144 case TLS_MODEL_LOCAL_DYNAMIC:
10145 base = gen_reg_rtx (Pmode);
10146 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10148 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10150 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10153 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10154 insns = get_insns ();
10157 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10158 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10159 RTL_CONST_CALL_P (insns) = 1;
10160 emit_libcall_block (insns, base, rax, note);
10162 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10163 emit_insn (gen_tls_local_dynamic_base_64 (base));
10165 emit_insn (gen_tls_local_dynamic_base_32 (base));
10167 if (TARGET_GNU2_TLS)
10169 rtx x = ix86_tls_module_base ();
10171 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10172 gen_rtx_MINUS (Pmode, x, tp));
10175 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10176 off = gen_rtx_CONST (Pmode, off);
10178 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10180 if (TARGET_GNU2_TLS)
10182 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10184 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10189 case TLS_MODEL_INITIAL_EXEC:
10193 type = UNSPEC_GOTNTPOFF;
10197 if (reload_in_progress)
10198 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10199 pic = pic_offset_table_rtx;
10200 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10202 else if (!TARGET_ANY_GNU_TLS)
10204 pic = gen_reg_rtx (Pmode);
10205 emit_insn (gen_set_got (pic));
10206 type = UNSPEC_GOTTPOFF;
10211 type = UNSPEC_INDNTPOFF;
10214 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10215 off = gen_rtx_CONST (Pmode, off);
10217 off = gen_rtx_PLUS (Pmode, pic, off);
10218 off = gen_const_mem (Pmode, off);
10219 set_mem_alias_set (off, ix86_GOT_alias_set ());
10221 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10223 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10224 off = force_reg (Pmode, off);
10225 return gen_rtx_PLUS (Pmode, base, off);
10229 base = get_thread_pointer (true);
10230 dest = gen_reg_rtx (Pmode);
10231 emit_insn (gen_subsi3 (dest, base, off));
10235 case TLS_MODEL_LOCAL_EXEC:
10236 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10237 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10238 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10239 off = gen_rtx_CONST (Pmode, off);
10241 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10243 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10244 return gen_rtx_PLUS (Pmode, base, off);
10248 base = get_thread_pointer (true);
10249 dest = gen_reg_rtx (Pmode);
10250 emit_insn (gen_subsi3 (dest, base, off));
10255 gcc_unreachable ();
10261 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10264 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10265 htab_t dllimport_map;
10268 get_dllimport_decl (tree decl)
10270 struct tree_map *h, in;
10273 const char *prefix;
10274 size_t namelen, prefixlen;
10279 if (!dllimport_map)
10280 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10282 in.hash = htab_hash_pointer (decl);
10283 in.base.from = decl;
10284 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10285 h = (struct tree_map *) *loc;
10289 *loc = h = GGC_NEW (struct tree_map);
10291 h->base.from = decl;
10292 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10293 VAR_DECL, NULL, ptr_type_node);
10294 DECL_ARTIFICIAL (to) = 1;
10295 DECL_IGNORED_P (to) = 1;
10296 DECL_EXTERNAL (to) = 1;
10297 TREE_READONLY (to) = 1;
10299 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10300 name = targetm.strip_name_encoding (name);
10301 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10302 ? "*__imp_" : "*__imp__";
10303 namelen = strlen (name);
10304 prefixlen = strlen (prefix);
10305 imp_name = (char *) alloca (namelen + prefixlen + 1);
10306 memcpy (imp_name, prefix, prefixlen);
10307 memcpy (imp_name + prefixlen, name, namelen + 1);
10309 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10310 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10311 SET_SYMBOL_REF_DECL (rtl, to);
10312 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10314 rtl = gen_const_mem (Pmode, rtl);
10315 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10317 SET_DECL_RTL (to, rtl);
10318 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10323 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10324 true if we require the result be a register. */
10327 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10332 gcc_assert (SYMBOL_REF_DECL (symbol));
10333 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10335 x = DECL_RTL (imp_decl);
10337 x = force_reg (Pmode, x);
10341 /* Try machine-dependent ways of modifying an illegitimate address
10342 to be legitimate. If we find one, return the new, valid address.
10343 This macro is used in only one place: `memory_address' in explow.c.
10345 OLDX is the address as it was before break_out_memory_refs was called.
10346 In some cases it is useful to look at this to decide what needs to be done.
10348 It is always safe for this macro to do nothing. It exists to recognize
10349 opportunities to optimize the output.
10351 For the 80386, we handle X+REG by loading X into a register R and
10352 using R+REG. R will go in a general reg and indexing will be used.
10353 However, if REG is a broken-out memory address or multiplication,
10354 nothing needs to be done because REG can certainly go in a general reg.
10356 When -fpic is used, special handling is needed for symbolic references.
10357 See comments by legitimize_pic_address in i386.c for details. */
10360 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10361 enum machine_mode mode)
10366 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10368 return legitimize_tls_address (x, (enum tls_model) log, false);
10369 if (GET_CODE (x) == CONST
10370 && GET_CODE (XEXP (x, 0)) == PLUS
10371 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10372 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10374 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10375 (enum tls_model) log, false);
10376 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10379 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10381 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10382 return legitimize_dllimport_symbol (x, true);
10383 if (GET_CODE (x) == CONST
10384 && GET_CODE (XEXP (x, 0)) == PLUS
10385 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10386 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10388 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10389 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10393 if (flag_pic && SYMBOLIC_CONST (x))
10394 return legitimize_pic_address (x, 0);
10396 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10397 if (GET_CODE (x) == ASHIFT
10398 && CONST_INT_P (XEXP (x, 1))
10399 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10402 log = INTVAL (XEXP (x, 1));
10403 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10404 GEN_INT (1 << log));
10407 if (GET_CODE (x) == PLUS)
10409 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10411 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10412 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10413 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10416 log = INTVAL (XEXP (XEXP (x, 0), 1));
10417 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10418 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10419 GEN_INT (1 << log));
10422 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10423 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10424 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10427 log = INTVAL (XEXP (XEXP (x, 1), 1));
10428 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10429 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10430 GEN_INT (1 << log));
10433 /* Put multiply first if it isn't already. */
10434 if (GET_CODE (XEXP (x, 1)) == MULT)
10436 rtx tmp = XEXP (x, 0);
10437 XEXP (x, 0) = XEXP (x, 1);
10442 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10443 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10444 created by virtual register instantiation, register elimination, and
10445 similar optimizations. */
10446 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10449 x = gen_rtx_PLUS (Pmode,
10450 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10451 XEXP (XEXP (x, 1), 0)),
10452 XEXP (XEXP (x, 1), 1));
10456 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10457 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10458 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10459 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10460 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10461 && CONSTANT_P (XEXP (x, 1)))
10464 rtx other = NULL_RTX;
10466 if (CONST_INT_P (XEXP (x, 1)))
10468 constant = XEXP (x, 1);
10469 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10471 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10473 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10474 other = XEXP (x, 1);
10482 x = gen_rtx_PLUS (Pmode,
10483 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10484 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10485 plus_constant (other, INTVAL (constant)));
10489 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10492 if (GET_CODE (XEXP (x, 0)) == MULT)
10495 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10498 if (GET_CODE (XEXP (x, 1)) == MULT)
10501 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10505 && REG_P (XEXP (x, 1))
10506 && REG_P (XEXP (x, 0)))
10509 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10512 x = legitimize_pic_address (x, 0);
10515 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10518 if (REG_P (XEXP (x, 0)))
10520 rtx temp = gen_reg_rtx (Pmode);
10521 rtx val = force_operand (XEXP (x, 1), temp);
10523 emit_move_insn (temp, val);
10525 XEXP (x, 1) = temp;
10529 else if (REG_P (XEXP (x, 1)))
10531 rtx temp = gen_reg_rtx (Pmode);
10532 rtx val = force_operand (XEXP (x, 0), temp);
10534 emit_move_insn (temp, val);
10536 XEXP (x, 0) = temp;
10544 /* Print an integer constant expression in assembler syntax. Addition
10545 and subtraction are the only arithmetic that may appear in these
10546 expressions. FILE is the stdio stream to write to, X is the rtx, and
10547 CODE is the operand print code from the output string. */
10550 output_pic_addr_const (FILE *file, rtx x, int code)
10554 switch (GET_CODE (x))
10557 gcc_assert (flag_pic);
10562 if (! TARGET_MACHO || TARGET_64BIT)
10563 output_addr_const (file, x);
10566 const char *name = XSTR (x, 0);
10568 /* Mark the decl as referenced so that cgraph will
10569 output the function. */
10570 if (SYMBOL_REF_DECL (x))
10571 mark_decl_referenced (SYMBOL_REF_DECL (x));
10574 if (MACHOPIC_INDIRECT
10575 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10576 name = machopic_indirection_name (x, /*stub_p=*/true);
10578 assemble_name (file, name);
10580 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10581 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10582 fputs ("@PLT", file);
10589 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10590 assemble_name (asm_out_file, buf);
10594 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10598 /* This used to output parentheses around the expression,
10599 but that does not work on the 386 (either ATT or BSD assembler). */
10600 output_pic_addr_const (file, XEXP (x, 0), code);
10604 if (GET_MODE (x) == VOIDmode)
10606 /* We can use %d if the number is <32 bits and positive. */
10607 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10608 fprintf (file, "0x%lx%08lx",
10609 (unsigned long) CONST_DOUBLE_HIGH (x),
10610 (unsigned long) CONST_DOUBLE_LOW (x));
10612 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10615 /* We can't handle floating point constants;
10616 PRINT_OPERAND must handle them. */
10617 output_operand_lossage ("floating constant misused");
10621 /* Some assemblers need integer constants to appear first. */
10622 if (CONST_INT_P (XEXP (x, 0)))
10624 output_pic_addr_const (file, XEXP (x, 0), code);
10626 output_pic_addr_const (file, XEXP (x, 1), code);
10630 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10631 output_pic_addr_const (file, XEXP (x, 1), code);
10633 output_pic_addr_const (file, XEXP (x, 0), code);
10639 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10640 output_pic_addr_const (file, XEXP (x, 0), code);
10642 output_pic_addr_const (file, XEXP (x, 1), code);
10644 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10648 gcc_assert (XVECLEN (x, 0) == 1);
10649 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10650 switch (XINT (x, 1))
10653 fputs ("@GOT", file);
10655 case UNSPEC_GOTOFF:
10656 fputs ("@GOTOFF", file);
10658 case UNSPEC_PLTOFF:
10659 fputs ("@PLTOFF", file);
10661 case UNSPEC_GOTPCREL:
10662 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10663 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10665 case UNSPEC_GOTTPOFF:
10666 /* FIXME: This might be @TPOFF in Sun ld too. */
10667 fputs ("@GOTTPOFF", file);
10670 fputs ("@TPOFF", file);
10672 case UNSPEC_NTPOFF:
10674 fputs ("@TPOFF", file);
10676 fputs ("@NTPOFF", file);
10678 case UNSPEC_DTPOFF:
10679 fputs ("@DTPOFF", file);
10681 case UNSPEC_GOTNTPOFF:
10683 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10684 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10686 fputs ("@GOTNTPOFF", file);
10688 case UNSPEC_INDNTPOFF:
10689 fputs ("@INDNTPOFF", file);
10692 case UNSPEC_MACHOPIC_OFFSET:
10694 machopic_output_function_base_name (file);
10698 output_operand_lossage ("invalid UNSPEC as operand");
10704 output_operand_lossage ("invalid expression as operand");
10708 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10709 We need to emit DTP-relative relocations. */
10711 static void ATTRIBUTE_UNUSED
10712 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10714 fputs (ASM_LONG, file);
10715 output_addr_const (file, x);
10716 fputs ("@DTPOFF", file);
10722 fputs (", 0", file);
10725 gcc_unreachable ();
10729 /* Return true if X is a representation of the PIC register. This copes
10730 with calls from ix86_find_base_term, where the register might have
10731 been replaced by a cselib value. */
10734 ix86_pic_register_p (rtx x)
10736 if (GET_CODE (x) == VALUE)
10737 return (pic_offset_table_rtx
10738 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10740 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10743 /* In the name of slightly smaller debug output, and to cater to
10744 general assembler lossage, recognize PIC+GOTOFF and turn it back
10745 into a direct symbol reference.
10747 On Darwin, this is necessary to avoid a crash, because Darwin
10748 has a different PIC label for each routine but the DWARF debugging
10749 information is not associated with any particular routine, so it's
10750 necessary to remove references to the PIC label from RTL stored by
10751 the DWARF output code. */
10754 ix86_delegitimize_address (rtx x)
10756 rtx orig_x = delegitimize_mem_from_attrs (x);
10757 /* reg_addend is NULL or a multiple of some register. */
10758 rtx reg_addend = NULL_RTX;
10759 /* const_addend is NULL or a const_int. */
10760 rtx const_addend = NULL_RTX;
10761 /* This is the result, or NULL. */
10762 rtx result = NULL_RTX;
10771 if (GET_CODE (x) != CONST
10772 || GET_CODE (XEXP (x, 0)) != UNSPEC
10773 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10774 || !MEM_P (orig_x))
10776 return XVECEXP (XEXP (x, 0), 0, 0);
10779 if (GET_CODE (x) != PLUS
10780 || GET_CODE (XEXP (x, 1)) != CONST)
10783 if (ix86_pic_register_p (XEXP (x, 0)))
10784 /* %ebx + GOT/GOTOFF */
10786 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10788 /* %ebx + %reg * scale + GOT/GOTOFF */
10789 reg_addend = XEXP (x, 0);
10790 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10791 reg_addend = XEXP (reg_addend, 1);
10792 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10793 reg_addend = XEXP (reg_addend, 0);
10796 if (!REG_P (reg_addend)
10797 && GET_CODE (reg_addend) != MULT
10798 && GET_CODE (reg_addend) != ASHIFT)
10804 x = XEXP (XEXP (x, 1), 0);
10805 if (GET_CODE (x) == PLUS
10806 && CONST_INT_P (XEXP (x, 1)))
10808 const_addend = XEXP (x, 1);
10812 if (GET_CODE (x) == UNSPEC
10813 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10814 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10815 result = XVECEXP (x, 0, 0);
10817 if (TARGET_MACHO && darwin_local_data_pic (x)
10818 && !MEM_P (orig_x))
10819 result = XVECEXP (x, 0, 0);
10825 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10827 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10831 /* If X is a machine specific address (i.e. a symbol or label being
10832 referenced as a displacement from the GOT implemented using an
10833 UNSPEC), then return the base term. Otherwise return X. */
10836 ix86_find_base_term (rtx x)
10842 if (GET_CODE (x) != CONST)
10844 term = XEXP (x, 0);
10845 if (GET_CODE (term) == PLUS
10846 && (CONST_INT_P (XEXP (term, 1))
10847 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10848 term = XEXP (term, 0);
10849 if (GET_CODE (term) != UNSPEC
10850 || XINT (term, 1) != UNSPEC_GOTPCREL)
10853 return XVECEXP (term, 0, 0);
10856 return ix86_delegitimize_address (x);
10860 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10861 int fp, FILE *file)
10863 const char *suffix;
10865 if (mode == CCFPmode || mode == CCFPUmode)
10867 code = ix86_fp_compare_code_to_integer (code);
10871 code = reverse_condition (code);
10922 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10926 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10927 Those same assemblers have the same but opposite lossage on cmov. */
10928 if (mode == CCmode)
10929 suffix = fp ? "nbe" : "a";
10930 else if (mode == CCCmode)
10933 gcc_unreachable ();
10949 gcc_unreachable ();
10953 gcc_assert (mode == CCmode || mode == CCCmode);
10970 gcc_unreachable ();
10974 /* ??? As above. */
10975 gcc_assert (mode == CCmode || mode == CCCmode);
10976 suffix = fp ? "nb" : "ae";
10979 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10983 /* ??? As above. */
10984 if (mode == CCmode)
10986 else if (mode == CCCmode)
10987 suffix = fp ? "nb" : "ae";
10989 gcc_unreachable ();
10992 suffix = fp ? "u" : "p";
10995 suffix = fp ? "nu" : "np";
10998 gcc_unreachable ();
11000 fputs (suffix, file);
11003 /* Print the name of register X to FILE based on its machine mode and number.
11004 If CODE is 'w', pretend the mode is HImode.
11005 If CODE is 'b', pretend the mode is QImode.
11006 If CODE is 'k', pretend the mode is SImode.
11007 If CODE is 'q', pretend the mode is DImode.
11008 If CODE is 'x', pretend the mode is V4SFmode.
11009 If CODE is 't', pretend the mode is V8SFmode.
11010 If CODE is 'h', pretend the reg is the 'high' byte register.
11011 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11012 If CODE is 'd', duplicate the operand for AVX instruction.
11016 print_reg (rtx x, int code, FILE *file)
11019 bool duplicated = code == 'd' && TARGET_AVX;
11021 gcc_assert (x == pc_rtx
11022 || (REGNO (x) != ARG_POINTER_REGNUM
11023 && REGNO (x) != FRAME_POINTER_REGNUM
11024 && REGNO (x) != FLAGS_REG
11025 && REGNO (x) != FPSR_REG
11026 && REGNO (x) != FPCR_REG));
11028 if (ASSEMBLER_DIALECT == ASM_ATT)
11033 gcc_assert (TARGET_64BIT);
11034 fputs ("rip", file);
11038 if (code == 'w' || MMX_REG_P (x))
11040 else if (code == 'b')
11042 else if (code == 'k')
11044 else if (code == 'q')
11046 else if (code == 'y')
11048 else if (code == 'h')
11050 else if (code == 'x')
11052 else if (code == 't')
11055 code = GET_MODE_SIZE (GET_MODE (x));
11057 /* Irritatingly, AMD extended registers use different naming convention
11058 from the normal registers. */
11059 if (REX_INT_REG_P (x))
11061 gcc_assert (TARGET_64BIT);
11065 error ("extended registers have no high halves");
11068 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11071 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11074 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11077 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11080 error ("unsupported operand size for extended register");
11090 if (STACK_TOP_P (x))
11099 if (! ANY_FP_REG_P (x))
11100 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11105 reg = hi_reg_name[REGNO (x)];
11108 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11110 reg = qi_reg_name[REGNO (x)];
11113 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11115 reg = qi_high_reg_name[REGNO (x)];
11120 gcc_assert (!duplicated);
11122 fputs (hi_reg_name[REGNO (x)] + 1, file);
11127 gcc_unreachable ();
11133 if (ASSEMBLER_DIALECT == ASM_ATT)
11134 fprintf (file, ", %%%s", reg);
11136 fprintf (file, ", %s", reg);
11140 /* Locate some local-dynamic symbol still in use by this function
11141 so that we can print its name in some tls_local_dynamic_base
11145 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11149 if (GET_CODE (x) == SYMBOL_REF
11150 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11152 cfun->machine->some_ld_name = XSTR (x, 0);
11159 static const char *
11160 get_some_local_dynamic_name (void)
11164 if (cfun->machine->some_ld_name)
11165 return cfun->machine->some_ld_name;
11167 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11169 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11170 return cfun->machine->some_ld_name;
11172 gcc_unreachable ();
11175 /* Meaning of CODE:
11176 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11177 C -- print opcode suffix for set/cmov insn.
11178 c -- like C, but print reversed condition
11179 E,e -- likewise, but for compare-and-branch fused insn.
11180 F,f -- likewise, but for floating-point.
11181 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11183 R -- print the prefix for register names.
11184 z -- print the opcode suffix for the size of the current operand.
11185 Z -- likewise, with special suffixes for x87 instructions.
11186 * -- print a star (in certain assembler syntax)
11187 A -- print an absolute memory reference.
11188 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11189 s -- print a shift double count, followed by the assemblers argument
11191 b -- print the QImode name of the register for the indicated operand.
11192 %b0 would print %al if operands[0] is reg 0.
11193 w -- likewise, print the HImode name of the register.
11194 k -- likewise, print the SImode name of the register.
11195 q -- likewise, print the DImode name of the register.
11196 x -- likewise, print the V4SFmode name of the register.
11197 t -- likewise, print the V8SFmode name of the register.
11198 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11199 y -- print "st(0)" instead of "st" as a register.
11200 d -- print duplicated register operand for AVX instruction.
11201 D -- print condition for SSE cmp instruction.
11202 P -- if PIC, print an @PLT suffix.
11203 X -- don't print any sort of PIC '@' suffix for a symbol.
11204 & -- print some in-use local-dynamic symbol name.
11205 H -- print a memory address offset by 8; used for sse high-parts
11206 + -- print a branch hint as 'cs' or 'ds' prefix
11207 ; -- print a semicolon (after prefixes due to bug in older gas).
11211 print_operand (FILE *file, rtx x, int code)
11218 if (ASSEMBLER_DIALECT == ASM_ATT)
11223 assemble_name (file, get_some_local_dynamic_name ());
11227 switch (ASSEMBLER_DIALECT)
11234 /* Intel syntax. For absolute addresses, registers should not
11235 be surrounded by braces. */
11239 PRINT_OPERAND (file, x, 0);
11246 gcc_unreachable ();
11249 PRINT_OPERAND (file, x, 0);
11254 if (ASSEMBLER_DIALECT == ASM_ATT)
11259 if (ASSEMBLER_DIALECT == ASM_ATT)
11264 if (ASSEMBLER_DIALECT == ASM_ATT)
11269 if (ASSEMBLER_DIALECT == ASM_ATT)
11274 if (ASSEMBLER_DIALECT == ASM_ATT)
11279 if (ASSEMBLER_DIALECT == ASM_ATT)
11284 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11286 /* Opcodes don't get size suffixes if using Intel opcodes. */
11287 if (ASSEMBLER_DIALECT == ASM_INTEL)
11290 switch (GET_MODE_SIZE (GET_MODE (x)))
11309 output_operand_lossage
11310 ("invalid operand size for operand code '%c'", code);
11315 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11317 (0, "non-integer operand used with operand code '%c'", code);
11321 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11322 if (ASSEMBLER_DIALECT == ASM_INTEL)
11325 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11327 switch (GET_MODE_SIZE (GET_MODE (x)))
11330 #ifdef HAVE_AS_IX86_FILDS
11340 #ifdef HAVE_AS_IX86_FILDQ
11343 fputs ("ll", file);
11351 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11353 /* 387 opcodes don't get size suffixes
11354 if the operands are registers. */
11355 if (STACK_REG_P (x))
11358 switch (GET_MODE_SIZE (GET_MODE (x)))
11379 output_operand_lossage
11380 ("invalid operand type used with operand code '%c'", code);
11384 output_operand_lossage
11385 ("invalid operand size for operand code '%c'", code);
11402 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11404 PRINT_OPERAND (file, x, 0);
11405 fputs (", ", file);
11410 /* Little bit of braindamage here. The SSE compare instructions
11411 does use completely different names for the comparisons that the
11412 fp conditional moves. */
11415 switch (GET_CODE (x))
11418 fputs ("eq", file);
11421 fputs ("eq_us", file);
11424 fputs ("lt", file);
11427 fputs ("nge", file);
11430 fputs ("le", file);
11433 fputs ("ngt", file);
11436 fputs ("unord", file);
11439 fputs ("neq", file);
11442 fputs ("neq_oq", file);
11445 fputs ("ge", file);
11448 fputs ("nlt", file);
11451 fputs ("gt", file);
11454 fputs ("nle", file);
11457 fputs ("ord", file);
11460 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11466 switch (GET_CODE (x))
11470 fputs ("eq", file);
11474 fputs ("lt", file);
11478 fputs ("le", file);
11481 fputs ("unord", file);
11485 fputs ("neq", file);
11489 fputs ("nlt", file);
11493 fputs ("nle", file);
11496 fputs ("ord", file);
11499 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11505 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11506 if (ASSEMBLER_DIALECT == ASM_ATT)
11508 switch (GET_MODE (x))
11510 case HImode: putc ('w', file); break;
11512 case SFmode: putc ('l', file); break;
11514 case DFmode: putc ('q', file); break;
11515 default: gcc_unreachable ();
11522 if (!COMPARISON_P (x))
11524 output_operand_lossage ("operand is neither a constant nor a "
11525 "condition code, invalid operand code "
11529 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11532 if (!COMPARISON_P (x))
11534 output_operand_lossage ("operand is neither a constant nor a "
11535 "condition code, invalid operand code "
11539 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11540 if (ASSEMBLER_DIALECT == ASM_ATT)
11543 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11546 /* Like above, but reverse condition */
11548 /* Check to see if argument to %c is really a constant
11549 and not a condition code which needs to be reversed. */
11550 if (!COMPARISON_P (x))
11552 output_operand_lossage ("operand is neither a constant nor a "
11553 "condition code, invalid operand "
11557 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11560 if (!COMPARISON_P (x))
11562 output_operand_lossage ("operand is neither a constant nor a "
11563 "condition code, invalid operand "
11567 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11568 if (ASSEMBLER_DIALECT == ASM_ATT)
11571 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11575 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11579 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11583 /* It doesn't actually matter what mode we use here, as we're
11584 only going to use this for printing. */
11585 x = adjust_address_nv (x, DImode, 8);
11593 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11596 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11599 int pred_val = INTVAL (XEXP (x, 0));
11601 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11602 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11604 int taken = pred_val > REG_BR_PROB_BASE / 2;
11605 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11607 /* Emit hints only in the case default branch prediction
11608 heuristics would fail. */
11609 if (taken != cputaken)
11611 /* We use 3e (DS) prefix for taken branches and
11612 2e (CS) prefix for not taken branches. */
11614 fputs ("ds ; ", file);
11616 fputs ("cs ; ", file);
11625 fputs (" ; ", file);
11632 output_operand_lossage ("invalid operand code '%c'", code);
11637 print_reg (x, code, file);
11639 else if (MEM_P (x))
11641 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11642 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11643 && GET_MODE (x) != BLKmode)
11646 switch (GET_MODE_SIZE (GET_MODE (x)))
11648 case 1: size = "BYTE"; break;
11649 case 2: size = "WORD"; break;
11650 case 4: size = "DWORD"; break;
11651 case 8: size = "QWORD"; break;
11652 case 12: size = "XWORD"; break;
11654 if (GET_MODE (x) == XFmode)
11660 gcc_unreachable ();
11663 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11666 else if (code == 'w')
11668 else if (code == 'k')
11671 fputs (size, file);
11672 fputs (" PTR ", file);
11676 /* Avoid (%rip) for call operands. */
11677 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11678 && !CONST_INT_P (x))
11679 output_addr_const (file, x);
11680 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11681 output_operand_lossage ("invalid constraints for operand");
11683 output_address (x);
11686 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11691 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11692 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11694 if (ASSEMBLER_DIALECT == ASM_ATT)
11696 fprintf (file, "0x%08lx", (long unsigned int) l);
11699 /* These float cases don't actually occur as immediate operands. */
11700 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11704 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11705 fputs (dstr, file);
11708 else if (GET_CODE (x) == CONST_DOUBLE
11709 && GET_MODE (x) == XFmode)
11713 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11714 fputs (dstr, file);
11719 /* We have patterns that allow zero sets of memory, for instance.
11720 In 64-bit mode, we should probably support all 8-byte vectors,
11721 since we can in fact encode that into an immediate. */
11722 if (GET_CODE (x) == CONST_VECTOR)
11724 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11730 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11732 if (ASSEMBLER_DIALECT == ASM_ATT)
11735 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11736 || GET_CODE (x) == LABEL_REF)
11738 if (ASSEMBLER_DIALECT == ASM_ATT)
11741 fputs ("OFFSET FLAT:", file);
11744 if (CONST_INT_P (x))
11745 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11747 output_pic_addr_const (file, x, code);
11749 output_addr_const (file, x);
11753 /* Print a memory operand whose address is ADDR. */
11756 print_operand_address (FILE *file, rtx addr)
11758 struct ix86_address parts;
11759 rtx base, index, disp;
11761 int ok = ix86_decompose_address (addr, &parts);
11766 index = parts.index;
11768 scale = parts.scale;
11776 if (ASSEMBLER_DIALECT == ASM_ATT)
11778 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11781 gcc_unreachable ();
11784 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11785 if (TARGET_64BIT && !base && !index)
11789 if (GET_CODE (disp) == CONST
11790 && GET_CODE (XEXP (disp, 0)) == PLUS
11791 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11792 symbol = XEXP (XEXP (disp, 0), 0);
11794 if (GET_CODE (symbol) == LABEL_REF
11795 || (GET_CODE (symbol) == SYMBOL_REF
11796 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11799 if (!base && !index)
11801 /* Displacement only requires special attention. */
11803 if (CONST_INT_P (disp))
11805 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11806 fputs ("ds:", file);
11807 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11810 output_pic_addr_const (file, disp, 0);
11812 output_addr_const (file, disp);
11816 if (ASSEMBLER_DIALECT == ASM_ATT)
11821 output_pic_addr_const (file, disp, 0);
11822 else if (GET_CODE (disp) == LABEL_REF)
11823 output_asm_label (disp);
11825 output_addr_const (file, disp);
11830 print_reg (base, 0, file);
11834 print_reg (index, 0, file);
11836 fprintf (file, ",%d", scale);
11842 rtx offset = NULL_RTX;
11846 /* Pull out the offset of a symbol; print any symbol itself. */
11847 if (GET_CODE (disp) == CONST
11848 && GET_CODE (XEXP (disp, 0)) == PLUS
11849 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11851 offset = XEXP (XEXP (disp, 0), 1);
11852 disp = gen_rtx_CONST (VOIDmode,
11853 XEXP (XEXP (disp, 0), 0));
11857 output_pic_addr_const (file, disp, 0);
11858 else if (GET_CODE (disp) == LABEL_REF)
11859 output_asm_label (disp);
11860 else if (CONST_INT_P (disp))
11863 output_addr_const (file, disp);
11869 print_reg (base, 0, file);
11872 if (INTVAL (offset) >= 0)
11874 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11878 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11885 print_reg (index, 0, file);
11887 fprintf (file, "*%d", scale);
11895 output_addr_const_extra (FILE *file, rtx x)
11899 if (GET_CODE (x) != UNSPEC)
11902 op = XVECEXP (x, 0, 0);
11903 switch (XINT (x, 1))
11905 case UNSPEC_GOTTPOFF:
11906 output_addr_const (file, op);
11907 /* FIXME: This might be @TPOFF in Sun ld. */
11908 fputs ("@GOTTPOFF", file);
11911 output_addr_const (file, op);
11912 fputs ("@TPOFF", file);
11914 case UNSPEC_NTPOFF:
11915 output_addr_const (file, op);
11917 fputs ("@TPOFF", file);
11919 fputs ("@NTPOFF", file);
11921 case UNSPEC_DTPOFF:
11922 output_addr_const (file, op);
11923 fputs ("@DTPOFF", file);
11925 case UNSPEC_GOTNTPOFF:
11926 output_addr_const (file, op);
11928 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11929 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11931 fputs ("@GOTNTPOFF", file);
11933 case UNSPEC_INDNTPOFF:
11934 output_addr_const (file, op);
11935 fputs ("@INDNTPOFF", file);
11938 case UNSPEC_MACHOPIC_OFFSET:
11939 output_addr_const (file, op);
11941 machopic_output_function_base_name (file);
11952 /* Split one or more DImode RTL references into pairs of SImode
11953 references. The RTL can be REG, offsettable MEM, integer constant, or
11954 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11955 split and "num" is its length. lo_half and hi_half are output arrays
11956 that parallel "operands". */
11959 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11963 rtx op = operands[num];
11965 /* simplify_subreg refuse to split volatile memory addresses,
11966 but we still have to handle it. */
11969 lo_half[num] = adjust_address (op, SImode, 0);
11970 hi_half[num] = adjust_address (op, SImode, 4);
11974 lo_half[num] = simplify_gen_subreg (SImode, op,
11975 GET_MODE (op) == VOIDmode
11976 ? DImode : GET_MODE (op), 0);
11977 hi_half[num] = simplify_gen_subreg (SImode, op,
11978 GET_MODE (op) == VOIDmode
11979 ? DImode : GET_MODE (op), 4);
11983 /* Split one or more TImode RTL references into pairs of DImode
11984 references. The RTL can be REG, offsettable MEM, integer constant, or
11985 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11986 split and "num" is its length. lo_half and hi_half are output arrays
11987 that parallel "operands". */
11990 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11994 rtx op = operands[num];
11996 /* simplify_subreg refuse to split volatile memory addresses, but we
11997 still have to handle it. */
12000 lo_half[num] = adjust_address (op, DImode, 0);
12001 hi_half[num] = adjust_address (op, DImode, 8);
12005 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12006 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12011 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12012 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12013 is the expression of the binary operation. The output may either be
12014 emitted here, or returned to the caller, like all output_* functions.
12016 There is no guarantee that the operands are the same mode, as they
12017 might be within FLOAT or FLOAT_EXTEND expressions. */
12019 #ifndef SYSV386_COMPAT
12020 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12021 wants to fix the assemblers because that causes incompatibility
12022 with gcc. No-one wants to fix gcc because that causes
12023 incompatibility with assemblers... You can use the option of
12024 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12025 #define SYSV386_COMPAT 1
12029 output_387_binary_op (rtx insn, rtx *operands)
12031 static char buf[40];
12034 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12036 #ifdef ENABLE_CHECKING
12037 /* Even if we do not want to check the inputs, this documents input
12038 constraints. Which helps in understanding the following code. */
12039 if (STACK_REG_P (operands[0])
12040 && ((REG_P (operands[1])
12041 && REGNO (operands[0]) == REGNO (operands[1])
12042 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12043 || (REG_P (operands[2])
12044 && REGNO (operands[0]) == REGNO (operands[2])
12045 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12046 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12049 gcc_assert (is_sse);
12052 switch (GET_CODE (operands[3]))
12055 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12056 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12064 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12065 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12073 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12074 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12082 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12083 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12091 gcc_unreachable ();
12098 strcpy (buf, ssep);
12099 if (GET_MODE (operands[0]) == SFmode)
12100 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12102 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12106 strcpy (buf, ssep + 1);
12107 if (GET_MODE (operands[0]) == SFmode)
12108 strcat (buf, "ss\t{%2, %0|%0, %2}");
12110 strcat (buf, "sd\t{%2, %0|%0, %2}");
12116 switch (GET_CODE (operands[3]))
12120 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12122 rtx temp = operands[2];
12123 operands[2] = operands[1];
12124 operands[1] = temp;
12127 /* know operands[0] == operands[1]. */
12129 if (MEM_P (operands[2]))
12135 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12137 if (STACK_TOP_P (operands[0]))
12138 /* How is it that we are storing to a dead operand[2]?
12139 Well, presumably operands[1] is dead too. We can't
12140 store the result to st(0) as st(0) gets popped on this
12141 instruction. Instead store to operands[2] (which I
12142 think has to be st(1)). st(1) will be popped later.
12143 gcc <= 2.8.1 didn't have this check and generated
12144 assembly code that the Unixware assembler rejected. */
12145 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12147 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12151 if (STACK_TOP_P (operands[0]))
12152 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12154 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12159 if (MEM_P (operands[1]))
12165 if (MEM_P (operands[2]))
12171 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12174 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12175 derived assemblers, confusingly reverse the direction of
12176 the operation for fsub{r} and fdiv{r} when the
12177 destination register is not st(0). The Intel assembler
12178 doesn't have this brain damage. Read !SYSV386_COMPAT to
12179 figure out what the hardware really does. */
12180 if (STACK_TOP_P (operands[0]))
12181 p = "{p\t%0, %2|rp\t%2, %0}";
12183 p = "{rp\t%2, %0|p\t%0, %2}";
12185 if (STACK_TOP_P (operands[0]))
12186 /* As above for fmul/fadd, we can't store to st(0). */
12187 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12189 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12194 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12197 if (STACK_TOP_P (operands[0]))
12198 p = "{rp\t%0, %1|p\t%1, %0}";
12200 p = "{p\t%1, %0|rp\t%0, %1}";
12202 if (STACK_TOP_P (operands[0]))
12203 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12205 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12210 if (STACK_TOP_P (operands[0]))
12212 if (STACK_TOP_P (operands[1]))
12213 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12215 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12218 else if (STACK_TOP_P (operands[1]))
12221 p = "{\t%1, %0|r\t%0, %1}";
12223 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12229 p = "{r\t%2, %0|\t%0, %2}";
12231 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12237 gcc_unreachable ();
12244 /* Return needed mode for entity in optimize_mode_switching pass. */
12247 ix86_mode_needed (int entity, rtx insn)
12249 enum attr_i387_cw mode;
12251 /* The mode UNINITIALIZED is used to store control word after a
12252 function call or ASM pattern. The mode ANY specify that function
12253 has no requirements on the control word and make no changes in the
12254 bits we are interested in. */
12257 || (NONJUMP_INSN_P (insn)
12258 && (asm_noperands (PATTERN (insn)) >= 0
12259 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12260 return I387_CW_UNINITIALIZED;
12262 if (recog_memoized (insn) < 0)
12263 return I387_CW_ANY;
12265 mode = get_attr_i387_cw (insn);
12270 if (mode == I387_CW_TRUNC)
12275 if (mode == I387_CW_FLOOR)
12280 if (mode == I387_CW_CEIL)
12285 if (mode == I387_CW_MASK_PM)
12290 gcc_unreachable ();
12293 return I387_CW_ANY;
12296 /* Output code to initialize control word copies used by trunc?f?i and
12297 rounding patterns. CURRENT_MODE is set to current control word,
12298 while NEW_MODE is set to new control word. */
12301 emit_i387_cw_initialization (int mode)
12303 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12306 enum ix86_stack_slot slot;
12308 rtx reg = gen_reg_rtx (HImode);
12310 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12311 emit_move_insn (reg, copy_rtx (stored_mode));
12313 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12314 || optimize_function_for_size_p (cfun))
12318 case I387_CW_TRUNC:
12319 /* round toward zero (truncate) */
12320 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12321 slot = SLOT_CW_TRUNC;
12324 case I387_CW_FLOOR:
12325 /* round down toward -oo */
12326 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12327 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12328 slot = SLOT_CW_FLOOR;
12332 /* round up toward +oo */
12333 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12334 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12335 slot = SLOT_CW_CEIL;
12338 case I387_CW_MASK_PM:
12339 /* mask precision exception for nearbyint() */
12340 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12341 slot = SLOT_CW_MASK_PM;
12345 gcc_unreachable ();
12352 case I387_CW_TRUNC:
12353 /* round toward zero (truncate) */
12354 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12355 slot = SLOT_CW_TRUNC;
12358 case I387_CW_FLOOR:
12359 /* round down toward -oo */
12360 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12361 slot = SLOT_CW_FLOOR;
12365 /* round up toward +oo */
12366 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12367 slot = SLOT_CW_CEIL;
12370 case I387_CW_MASK_PM:
12371 /* mask precision exception for nearbyint() */
12372 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12373 slot = SLOT_CW_MASK_PM;
12377 gcc_unreachable ();
12381 gcc_assert (slot < MAX_386_STACK_LOCALS);
12383 new_mode = assign_386_stack_local (HImode, slot);
12384 emit_move_insn (new_mode, reg);
12387 /* Output code for INSN to convert a float to a signed int. OPERANDS
12388 are the insn operands. The output may be [HSD]Imode and the input
12389 operand may be [SDX]Fmode. */
12392 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12394 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12395 int dimode_p = GET_MODE (operands[0]) == DImode;
12396 int round_mode = get_attr_i387_cw (insn);
12398 /* Jump through a hoop or two for DImode, since the hardware has no
12399 non-popping instruction. We used to do this a different way, but
12400 that was somewhat fragile and broke with post-reload splitters. */
12401 if ((dimode_p || fisttp) && !stack_top_dies)
12402 output_asm_insn ("fld\t%y1", operands);
12404 gcc_assert (STACK_TOP_P (operands[1]));
12405 gcc_assert (MEM_P (operands[0]));
12406 gcc_assert (GET_MODE (operands[1]) != TFmode);
12409 output_asm_insn ("fisttp%Z0\t%0", operands);
12412 if (round_mode != I387_CW_ANY)
12413 output_asm_insn ("fldcw\t%3", operands);
12414 if (stack_top_dies || dimode_p)
12415 output_asm_insn ("fistp%Z0\t%0", operands);
12417 output_asm_insn ("fist%Z0\t%0", operands);
12418 if (round_mode != I387_CW_ANY)
12419 output_asm_insn ("fldcw\t%2", operands);
12425 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12426 have the values zero or one, indicates the ffreep insn's operand
12427 from the OPERANDS array. */
12429 static const char *
12430 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12432 if (TARGET_USE_FFREEP)
12433 #ifdef HAVE_AS_IX86_FFREEP
12434 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12437 static char retval[32];
12438 int regno = REGNO (operands[opno]);
12440 gcc_assert (FP_REGNO_P (regno));
12442 regno -= FIRST_STACK_REG;
12444 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12449 return opno ? "fstp\t%y1" : "fstp\t%y0";
12453 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12454 should be used. UNORDERED_P is true when fucom should be used. */
12457 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12459 int stack_top_dies;
12460 rtx cmp_op0, cmp_op1;
12461 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12465 cmp_op0 = operands[0];
12466 cmp_op1 = operands[1];
12470 cmp_op0 = operands[1];
12471 cmp_op1 = operands[2];
12476 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12477 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12478 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12479 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12481 if (GET_MODE (operands[0]) == SFmode)
12483 return &ucomiss[TARGET_AVX ? 0 : 1];
12485 return &comiss[TARGET_AVX ? 0 : 1];
12488 return &ucomisd[TARGET_AVX ? 0 : 1];
12490 return &comisd[TARGET_AVX ? 0 : 1];
12493 gcc_assert (STACK_TOP_P (cmp_op0));
12495 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12497 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12499 if (stack_top_dies)
12501 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12502 return output_387_ffreep (operands, 1);
12505 return "ftst\n\tfnstsw\t%0";
12508 if (STACK_REG_P (cmp_op1)
12510 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12511 && REGNO (cmp_op1) != FIRST_STACK_REG)
12513 /* If both the top of the 387 stack dies, and the other operand
12514 is also a stack register that dies, then this must be a
12515 `fcompp' float compare */
12519 /* There is no double popping fcomi variant. Fortunately,
12520 eflags is immune from the fstp's cc clobbering. */
12522 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12524 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12525 return output_387_ffreep (operands, 0);
12530 return "fucompp\n\tfnstsw\t%0";
12532 return "fcompp\n\tfnstsw\t%0";
12537 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12539 static const char * const alt[16] =
12541 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12542 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12543 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12544 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12546 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12547 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12551 "fcomi\t{%y1, %0|%0, %y1}",
12552 "fcomip\t{%y1, %0|%0, %y1}",
12553 "fucomi\t{%y1, %0|%0, %y1}",
12554 "fucomip\t{%y1, %0|%0, %y1}",
12565 mask = eflags_p << 3;
12566 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12567 mask |= unordered_p << 1;
12568 mask |= stack_top_dies;
12570 gcc_assert (mask < 16);
12579 ix86_output_addr_vec_elt (FILE *file, int value)
12581 const char *directive = ASM_LONG;
12585 directive = ASM_QUAD;
12587 gcc_assert (!TARGET_64BIT);
12590 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12594 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12596 const char *directive = ASM_LONG;
12599 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12600 directive = ASM_QUAD;
12602 gcc_assert (!TARGET_64BIT);
12604 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12605 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12606 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12607 directive, value, rel);
12608 else if (HAVE_AS_GOTOFF_IN_DATA)
12609 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12611 else if (TARGET_MACHO)
12613 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12614 machopic_output_function_base_name (file);
12619 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12620 GOT_SYMBOL_NAME, value);
12623 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12627 ix86_expand_clear (rtx dest)
12631 /* We play register width games, which are only valid after reload. */
12632 gcc_assert (reload_completed);
12634 /* Avoid HImode and its attendant prefix byte. */
12635 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12636 dest = gen_rtx_REG (SImode, REGNO (dest));
12637 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12639 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12640 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12642 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12643 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12649 /* X is an unchanging MEM. If it is a constant pool reference, return
12650 the constant pool rtx, else NULL. */
12653 maybe_get_pool_constant (rtx x)
12655 x = ix86_delegitimize_address (XEXP (x, 0));
12657 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12658 return get_pool_constant (x);
12664 ix86_expand_move (enum machine_mode mode, rtx operands[])
12667 enum tls_model model;
12672 if (GET_CODE (op1) == SYMBOL_REF)
12674 model = SYMBOL_REF_TLS_MODEL (op1);
12677 op1 = legitimize_tls_address (op1, model, true);
12678 op1 = force_operand (op1, op0);
12682 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12683 && SYMBOL_REF_DLLIMPORT_P (op1))
12684 op1 = legitimize_dllimport_symbol (op1, false);
12686 else if (GET_CODE (op1) == CONST
12687 && GET_CODE (XEXP (op1, 0)) == PLUS
12688 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12690 rtx addend = XEXP (XEXP (op1, 0), 1);
12691 rtx symbol = XEXP (XEXP (op1, 0), 0);
12694 model = SYMBOL_REF_TLS_MODEL (symbol);
12696 tmp = legitimize_tls_address (symbol, model, true);
12697 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12698 && SYMBOL_REF_DLLIMPORT_P (symbol))
12699 tmp = legitimize_dllimport_symbol (symbol, true);
12703 tmp = force_operand (tmp, NULL);
12704 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12705 op0, 1, OPTAB_DIRECT);
12711 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12713 if (TARGET_MACHO && !TARGET_64BIT)
12718 rtx temp = ((reload_in_progress
12719 || ((op0 && REG_P (op0))
12721 ? op0 : gen_reg_rtx (Pmode));
12722 op1 = machopic_indirect_data_reference (op1, temp);
12723 op1 = machopic_legitimize_pic_address (op1, mode,
12724 temp == op1 ? 0 : temp);
12726 else if (MACHOPIC_INDIRECT)
12727 op1 = machopic_indirect_data_reference (op1, 0);
12735 op1 = force_reg (Pmode, op1);
12736 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12738 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12739 op1 = legitimize_pic_address (op1, reg);
12748 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12749 || !push_operand (op0, mode))
12751 op1 = force_reg (mode, op1);
12753 if (push_operand (op0, mode)
12754 && ! general_no_elim_operand (op1, mode))
12755 op1 = copy_to_mode_reg (mode, op1);
12757 /* Force large constants in 64bit compilation into register
12758 to get them CSEed. */
12759 if (can_create_pseudo_p ()
12760 && (mode == DImode) && TARGET_64BIT
12761 && immediate_operand (op1, mode)
12762 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12763 && !register_operand (op0, mode)
12765 op1 = copy_to_mode_reg (mode, op1);
12767 if (can_create_pseudo_p ()
12768 && FLOAT_MODE_P (mode)
12769 && GET_CODE (op1) == CONST_DOUBLE)
12771 /* If we are loading a floating point constant to a register,
12772 force the value to memory now, since we'll get better code
12773 out the back end. */
12775 op1 = validize_mem (force_const_mem (mode, op1));
12776 if (!register_operand (op0, mode))
12778 rtx temp = gen_reg_rtx (mode);
12779 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12780 emit_move_insn (op0, temp);
12786 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12790 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12792 rtx op0 = operands[0], op1 = operands[1];
12793 unsigned int align = GET_MODE_ALIGNMENT (mode);
12795 /* Force constants other than zero into memory. We do not know how
12796 the instructions used to build constants modify the upper 64 bits
12797 of the register, once we have that information we may be able
12798 to handle some of them more efficiently. */
12799 if (can_create_pseudo_p ()
12800 && register_operand (op0, mode)
12801 && (CONSTANT_P (op1)
12802 || (GET_CODE (op1) == SUBREG
12803 && CONSTANT_P (SUBREG_REG (op1))))
12804 && !standard_sse_constant_p (op1))
12805 op1 = validize_mem (force_const_mem (mode, op1));
12807 /* We need to check memory alignment for SSE mode since attribute
12808 can make operands unaligned. */
12809 if (can_create_pseudo_p ()
12810 && SSE_REG_MODE_P (mode)
12811 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12812 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12816 /* ix86_expand_vector_move_misalign() does not like constants ... */
12817 if (CONSTANT_P (op1)
12818 || (GET_CODE (op1) == SUBREG
12819 && CONSTANT_P (SUBREG_REG (op1))))
12820 op1 = validize_mem (force_const_mem (mode, op1));
12822 /* ... nor both arguments in memory. */
12823 if (!register_operand (op0, mode)
12824 && !register_operand (op1, mode))
12825 op1 = force_reg (mode, op1);
12827 tmp[0] = op0; tmp[1] = op1;
12828 ix86_expand_vector_move_misalign (mode, tmp);
12832 /* Make operand1 a register if it isn't already. */
12833 if (can_create_pseudo_p ()
12834 && !register_operand (op0, mode)
12835 && !register_operand (op1, mode))
12837 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12841 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12844 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12845 straight to ix86_expand_vector_move. */
12846 /* Code generation for scalar reg-reg moves of single and double precision data:
12847 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12851 if (x86_sse_partial_reg_dependency == true)
12856 Code generation for scalar loads of double precision data:
12857 if (x86_sse_split_regs == true)
12858 movlpd mem, reg (gas syntax)
12862 Code generation for unaligned packed loads of single precision data
12863 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12864 if (x86_sse_unaligned_move_optimal)
12867 if (x86_sse_partial_reg_dependency == true)
12879 Code generation for unaligned packed loads of double precision data
12880 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12881 if (x86_sse_unaligned_move_optimal)
12884 if (x86_sse_split_regs == true)
12897 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12906 switch (GET_MODE_CLASS (mode))
12908 case MODE_VECTOR_INT:
12910 switch (GET_MODE_SIZE (mode))
12913 op0 = gen_lowpart (V16QImode, op0);
12914 op1 = gen_lowpart (V16QImode, op1);
12915 emit_insn (gen_avx_movdqu (op0, op1));
12918 op0 = gen_lowpart (V32QImode, op0);
12919 op1 = gen_lowpart (V32QImode, op1);
12920 emit_insn (gen_avx_movdqu256 (op0, op1));
12923 gcc_unreachable ();
12926 case MODE_VECTOR_FLOAT:
12927 op0 = gen_lowpart (mode, op0);
12928 op1 = gen_lowpart (mode, op1);
12933 emit_insn (gen_avx_movups (op0, op1));
12936 emit_insn (gen_avx_movups256 (op0, op1));
12939 emit_insn (gen_avx_movupd (op0, op1));
12942 emit_insn (gen_avx_movupd256 (op0, op1));
12945 gcc_unreachable ();
12950 gcc_unreachable ();
12958 /* If we're optimizing for size, movups is the smallest. */
12959 if (optimize_insn_for_size_p ())
12961 op0 = gen_lowpart (V4SFmode, op0);
12962 op1 = gen_lowpart (V4SFmode, op1);
12963 emit_insn (gen_sse_movups (op0, op1));
12967 /* ??? If we have typed data, then it would appear that using
12968 movdqu is the only way to get unaligned data loaded with
12970 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12972 op0 = gen_lowpart (V16QImode, op0);
12973 op1 = gen_lowpart (V16QImode, op1);
12974 emit_insn (gen_sse2_movdqu (op0, op1));
12978 if (TARGET_SSE2 && mode == V2DFmode)
12982 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12984 op0 = gen_lowpart (V2DFmode, op0);
12985 op1 = gen_lowpart (V2DFmode, op1);
12986 emit_insn (gen_sse2_movupd (op0, op1));
12990 /* When SSE registers are split into halves, we can avoid
12991 writing to the top half twice. */
12992 if (TARGET_SSE_SPLIT_REGS)
12994 emit_clobber (op0);
12999 /* ??? Not sure about the best option for the Intel chips.
13000 The following would seem to satisfy; the register is
13001 entirely cleared, breaking the dependency chain. We
13002 then store to the upper half, with a dependency depth
13003 of one. A rumor has it that Intel recommends two movsd
13004 followed by an unpacklpd, but this is unconfirmed. And
13005 given that the dependency depth of the unpacklpd would
13006 still be one, I'm not sure why this would be better. */
13007 zero = CONST0_RTX (V2DFmode);
13010 m = adjust_address (op1, DFmode, 0);
13011 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13012 m = adjust_address (op1, DFmode, 8);
13013 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13017 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13019 op0 = gen_lowpart (V4SFmode, op0);
13020 op1 = gen_lowpart (V4SFmode, op1);
13021 emit_insn (gen_sse_movups (op0, op1));
13025 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13026 emit_move_insn (op0, CONST0_RTX (mode));
13028 emit_clobber (op0);
13030 if (mode != V4SFmode)
13031 op0 = gen_lowpart (V4SFmode, op0);
13032 m = adjust_address (op1, V2SFmode, 0);
13033 emit_insn (gen_sse_loadlps (op0, op0, m));
13034 m = adjust_address (op1, V2SFmode, 8);
13035 emit_insn (gen_sse_loadhps (op0, op0, m));
13038 else if (MEM_P (op0))
13040 /* If we're optimizing for size, movups is the smallest. */
13041 if (optimize_insn_for_size_p ())
13043 op0 = gen_lowpart (V4SFmode, op0);
13044 op1 = gen_lowpart (V4SFmode, op1);
13045 emit_insn (gen_sse_movups (op0, op1));
13049 /* ??? Similar to above, only less clear because of quote
13050 typeless stores unquote. */
13051 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13052 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13054 op0 = gen_lowpart (V16QImode, op0);
13055 op1 = gen_lowpart (V16QImode, op1);
13056 emit_insn (gen_sse2_movdqu (op0, op1));
13060 if (TARGET_SSE2 && mode == V2DFmode)
13062 m = adjust_address (op0, DFmode, 0);
13063 emit_insn (gen_sse2_storelpd (m, op1));
13064 m = adjust_address (op0, DFmode, 8);
13065 emit_insn (gen_sse2_storehpd (m, op1));
13069 if (mode != V4SFmode)
13070 op1 = gen_lowpart (V4SFmode, op1);
13071 m = adjust_address (op0, V2SFmode, 0);
13072 emit_insn (gen_sse_storelps (m, op1));
13073 m = adjust_address (op0, V2SFmode, 8);
13074 emit_insn (gen_sse_storehps (m, op1));
13078 gcc_unreachable ();
13081 /* Expand a push in MODE. This is some mode for which we do not support
13082 proper push instructions, at least from the registers that we expect
13083 the value to live in. */
13086 ix86_expand_push (enum machine_mode mode, rtx x)
13090 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13091 GEN_INT (-GET_MODE_SIZE (mode)),
13092 stack_pointer_rtx, 1, OPTAB_DIRECT);
13093 if (tmp != stack_pointer_rtx)
13094 emit_move_insn (stack_pointer_rtx, tmp);
13096 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13098 /* When we push an operand onto stack, it has to be aligned at least
13099 at the function argument boundary. However since we don't have
13100 the argument type, we can't determine the actual argument
13102 emit_move_insn (tmp, x);
13105 /* Helper function of ix86_fixup_binary_operands to canonicalize
13106 operand order. Returns true if the operands should be swapped. */
13109 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13112 rtx dst = operands[0];
13113 rtx src1 = operands[1];
13114 rtx src2 = operands[2];
13116 /* If the operation is not commutative, we can't do anything. */
13117 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13120 /* Highest priority is that src1 should match dst. */
13121 if (rtx_equal_p (dst, src1))
13123 if (rtx_equal_p (dst, src2))
13126 /* Next highest priority is that immediate constants come second. */
13127 if (immediate_operand (src2, mode))
13129 if (immediate_operand (src1, mode))
13132 /* Lowest priority is that memory references should come second. */
13142 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13143 destination to use for the operation. If different from the true
13144 destination in operands[0], a copy operation will be required. */
13147 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13150 rtx dst = operands[0];
13151 rtx src1 = operands[1];
13152 rtx src2 = operands[2];
13154 /* Canonicalize operand order. */
13155 if (ix86_swap_binary_operands_p (code, mode, operands))
13159 /* It is invalid to swap operands of different modes. */
13160 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13167 /* Both source operands cannot be in memory. */
13168 if (MEM_P (src1) && MEM_P (src2))
13170 /* Optimization: Only read from memory once. */
13171 if (rtx_equal_p (src1, src2))
13173 src2 = force_reg (mode, src2);
13177 src2 = force_reg (mode, src2);
13180 /* If the destination is memory, and we do not have matching source
13181 operands, do things in registers. */
13182 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13183 dst = gen_reg_rtx (mode);
13185 /* Source 1 cannot be a constant. */
13186 if (CONSTANT_P (src1))
13187 src1 = force_reg (mode, src1);
13189 /* Source 1 cannot be a non-matching memory. */
13190 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13191 src1 = force_reg (mode, src1);
13193 operands[1] = src1;
13194 operands[2] = src2;
13198 /* Similarly, but assume that the destination has already been
13199 set up properly. */
13202 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13203 enum machine_mode mode, rtx operands[])
13205 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13206 gcc_assert (dst == operands[0]);
13209 /* Attempt to expand a binary operator. Make the expansion closer to the
13210 actual machine, then just general_operand, which will allow 3 separate
13211 memory references (one output, two input) in a single insn. */
13214 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13217 rtx src1, src2, dst, op, clob;
13219 dst = ix86_fixup_binary_operands (code, mode, operands);
13220 src1 = operands[1];
13221 src2 = operands[2];
13223 /* Emit the instruction. */
13225 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13226 if (reload_in_progress)
13228 /* Reload doesn't know about the flags register, and doesn't know that
13229 it doesn't want to clobber it. We can only do this with PLUS. */
13230 gcc_assert (code == PLUS);
13235 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13236 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13239 /* Fix up the destination if needed. */
13240 if (dst != operands[0])
13241 emit_move_insn (operands[0], dst);
13244 /* Return TRUE or FALSE depending on whether the binary operator meets the
13245 appropriate constraints. */
13248 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13251 rtx dst = operands[0];
13252 rtx src1 = operands[1];
13253 rtx src2 = operands[2];
13255 /* Both source operands cannot be in memory. */
13256 if (MEM_P (src1) && MEM_P (src2))
13259 /* Canonicalize operand order for commutative operators. */
13260 if (ix86_swap_binary_operands_p (code, mode, operands))
13267 /* If the destination is memory, we must have a matching source operand. */
13268 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13271 /* Source 1 cannot be a constant. */
13272 if (CONSTANT_P (src1))
13275 /* Source 1 cannot be a non-matching memory. */
13276 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13282 /* Attempt to expand a unary operator. Make the expansion closer to the
13283 actual machine, then just general_operand, which will allow 2 separate
13284 memory references (one output, one input) in a single insn. */
13287 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13290 int matching_memory;
13291 rtx src, dst, op, clob;
13296 /* If the destination is memory, and we do not have matching source
13297 operands, do things in registers. */
13298 matching_memory = 0;
13301 if (rtx_equal_p (dst, src))
13302 matching_memory = 1;
13304 dst = gen_reg_rtx (mode);
13307 /* When source operand is memory, destination must match. */
13308 if (MEM_P (src) && !matching_memory)
13309 src = force_reg (mode, src);
13311 /* Emit the instruction. */
13313 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13314 if (reload_in_progress || code == NOT)
13316 /* Reload doesn't know about the flags register, and doesn't know that
13317 it doesn't want to clobber it. */
13318 gcc_assert (code == NOT);
13323 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13324 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13327 /* Fix up the destination if needed. */
13328 if (dst != operands[0])
13329 emit_move_insn (operands[0], dst);
13332 #define LEA_SEARCH_THRESHOLD 12
13334 /* Search backward for non-agu definition of register number REGNO1
13335 or register number REGNO2 in INSN's basic block until
13336 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13337 2. Reach BB boundary, or
13338 3. Reach agu definition.
13339 Returns the distance between the non-agu definition point and INSN.
13340 If no definition point, returns -1. */
13343 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13346 basic_block bb = BLOCK_FOR_INSN (insn);
13349 enum attr_type insn_type;
13351 if (insn != BB_HEAD (bb))
13353 rtx prev = PREV_INSN (insn);
13354 while (prev && distance < LEA_SEARCH_THRESHOLD)
13359 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13360 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13361 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13362 && (regno1 == DF_REF_REGNO (*def_rec)
13363 || regno2 == DF_REF_REGNO (*def_rec)))
13365 insn_type = get_attr_type (prev);
13366 if (insn_type != TYPE_LEA)
13370 if (prev == BB_HEAD (bb))
13372 prev = PREV_INSN (prev);
13376 if (distance < LEA_SEARCH_THRESHOLD)
13380 bool simple_loop = false;
13382 FOR_EACH_EDGE (e, ei, bb->preds)
13385 simple_loop = true;
13391 rtx prev = BB_END (bb);
13394 && distance < LEA_SEARCH_THRESHOLD)
13399 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13400 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13401 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13402 && (regno1 == DF_REF_REGNO (*def_rec)
13403 || regno2 == DF_REF_REGNO (*def_rec)))
13405 insn_type = get_attr_type (prev);
13406 if (insn_type != TYPE_LEA)
13410 prev = PREV_INSN (prev);
13418 /* get_attr_type may modify recog data. We want to make sure
13419 that recog data is valid for instruction INSN, on which
13420 distance_non_agu_define is called. INSN is unchanged here. */
13421 extract_insn_cached (insn);
13425 /* Return the distance between INSN and the next insn that uses
13426 register number REGNO0 in memory address. Return -1 if no such
13427 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13430 distance_agu_use (unsigned int regno0, rtx insn)
13432 basic_block bb = BLOCK_FOR_INSN (insn);
13437 if (insn != BB_END (bb))
13439 rtx next = NEXT_INSN (insn);
13440 while (next && distance < LEA_SEARCH_THRESHOLD)
13446 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13447 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13448 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13449 && regno0 == DF_REF_REGNO (*use_rec))
13451 /* Return DISTANCE if OP0 is used in memory
13452 address in NEXT. */
13456 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13457 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13458 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13459 && regno0 == DF_REF_REGNO (*def_rec))
13461 /* Return -1 if OP0 is set in NEXT. */
13465 if (next == BB_END (bb))
13467 next = NEXT_INSN (next);
13471 if (distance < LEA_SEARCH_THRESHOLD)
13475 bool simple_loop = false;
13477 FOR_EACH_EDGE (e, ei, bb->succs)
13480 simple_loop = true;
13486 rtx next = BB_HEAD (bb);
13489 && distance < LEA_SEARCH_THRESHOLD)
13495 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13496 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13497 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13498 && regno0 == DF_REF_REGNO (*use_rec))
13500 /* Return DISTANCE if OP0 is used in memory
13501 address in NEXT. */
13505 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13506 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13507 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13508 && regno0 == DF_REF_REGNO (*def_rec))
13510 /* Return -1 if OP0 is set in NEXT. */
13515 next = NEXT_INSN (next);
13523 /* Define this macro to tune LEA priority vs ADD, it take effect when
13524 there is a dilemma of choicing LEA or ADD
13525 Negative value: ADD is more preferred than LEA
13527 Positive value: LEA is more preferred than ADD*/
13528 #define IX86_LEA_PRIORITY 2
13530 /* Return true if it is ok to optimize an ADD operation to LEA
13531 operation to avoid flag register consumation. For the processors
13532 like ATOM, if the destination register of LEA holds an actual
13533 address which will be used soon, LEA is better and otherwise ADD
13537 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13538 rtx insn, rtx operands[])
13540 unsigned int regno0 = true_regnum (operands[0]);
13541 unsigned int regno1 = true_regnum (operands[1]);
13542 unsigned int regno2;
13544 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13545 return regno0 != regno1;
13547 regno2 = true_regnum (operands[2]);
13549 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13550 if (regno0 != regno1 && regno0 != regno2)
13554 int dist_define, dist_use;
13555 dist_define = distance_non_agu_define (regno1, regno2, insn);
13556 if (dist_define <= 0)
13559 /* If this insn has both backward non-agu dependence and forward
13560 agu dependence, the one with short distance take effect. */
13561 dist_use = distance_agu_use (regno0, insn);
13563 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13570 /* Return true if destination reg of SET_BODY is shift count of
13574 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13580 /* Retrieve destination of SET_BODY. */
13581 switch (GET_CODE (set_body))
13584 set_dest = SET_DEST (set_body);
13585 if (!set_dest || !REG_P (set_dest))
13589 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13590 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13598 /* Retrieve shift count of USE_BODY. */
13599 switch (GET_CODE (use_body))
13602 shift_rtx = XEXP (use_body, 1);
13605 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13606 if (ix86_dep_by_shift_count_body (set_body,
13607 XVECEXP (use_body, 0, i)))
13615 && (GET_CODE (shift_rtx) == ASHIFT
13616 || GET_CODE (shift_rtx) == LSHIFTRT
13617 || GET_CODE (shift_rtx) == ASHIFTRT
13618 || GET_CODE (shift_rtx) == ROTATE
13619 || GET_CODE (shift_rtx) == ROTATERT))
13621 rtx shift_count = XEXP (shift_rtx, 1);
13623 /* Return true if shift count is dest of SET_BODY. */
13624 if (REG_P (shift_count)
13625 && true_regnum (set_dest) == true_regnum (shift_count))
13632 /* Return true if destination reg of SET_INSN is shift count of
13636 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13638 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13639 PATTERN (use_insn));
13642 /* Return TRUE or FALSE depending on whether the unary operator meets the
13643 appropriate constraints. */
13646 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13647 enum machine_mode mode ATTRIBUTE_UNUSED,
13648 rtx operands[2] ATTRIBUTE_UNUSED)
13650 /* If one of operands is memory, source and destination must match. */
13651 if ((MEM_P (operands[0])
13652 || MEM_P (operands[1]))
13653 && ! rtx_equal_p (operands[0], operands[1]))
13658 /* Post-reload splitter for converting an SF or DFmode value in an
13659 SSE register into an unsigned SImode. */
13662 ix86_split_convert_uns_si_sse (rtx operands[])
13664 enum machine_mode vecmode;
13665 rtx value, large, zero_or_two31, input, two31, x;
13667 large = operands[1];
13668 zero_or_two31 = operands[2];
13669 input = operands[3];
13670 two31 = operands[4];
13671 vecmode = GET_MODE (large);
13672 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13674 /* Load up the value into the low element. We must ensure that the other
13675 elements are valid floats -- zero is the easiest such value. */
13678 if (vecmode == V4SFmode)
13679 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13681 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13685 input = gen_rtx_REG (vecmode, REGNO (input));
13686 emit_move_insn (value, CONST0_RTX (vecmode));
13687 if (vecmode == V4SFmode)
13688 emit_insn (gen_sse_movss (value, value, input));
13690 emit_insn (gen_sse2_movsd (value, value, input));
13693 emit_move_insn (large, two31);
13694 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13696 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13697 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13699 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13700 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13702 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13703 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13705 large = gen_rtx_REG (V4SImode, REGNO (large));
13706 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13708 x = gen_rtx_REG (V4SImode, REGNO (value));
13709 if (vecmode == V4SFmode)
13710 emit_insn (gen_sse2_cvttps2dq (x, value));
13712 emit_insn (gen_sse2_cvttpd2dq (x, value));
13715 emit_insn (gen_xorv4si3 (value, value, large));
13718 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13719 Expects the 64-bit DImode to be supplied in a pair of integral
13720 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13721 -mfpmath=sse, !optimize_size only. */
13724 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13726 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13727 rtx int_xmm, fp_xmm;
13728 rtx biases, exponents;
13731 int_xmm = gen_reg_rtx (V4SImode);
13732 if (TARGET_INTER_UNIT_MOVES)
13733 emit_insn (gen_movdi_to_sse (int_xmm, input));
13734 else if (TARGET_SSE_SPLIT_REGS)
13736 emit_clobber (int_xmm);
13737 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13741 x = gen_reg_rtx (V2DImode);
13742 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13743 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13746 x = gen_rtx_CONST_VECTOR (V4SImode,
13747 gen_rtvec (4, GEN_INT (0x43300000UL),
13748 GEN_INT (0x45300000UL),
13749 const0_rtx, const0_rtx));
13750 exponents = validize_mem (force_const_mem (V4SImode, x));
13752 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13753 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13755 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13756 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13757 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13758 (0x1.0p84 + double(fp_value_hi_xmm)).
13759 Note these exponents differ by 32. */
13761 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13763 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13764 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13765 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13766 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13767 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13768 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13769 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13770 biases = validize_mem (force_const_mem (V2DFmode, biases));
13771 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13773 /* Add the upper and lower DFmode values together. */
13775 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13778 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13779 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13780 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13783 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13786 /* Not used, but eases macroization of patterns. */
13788 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13789 rtx input ATTRIBUTE_UNUSED)
13791 gcc_unreachable ();
13794 /* Convert an unsigned SImode value into a DFmode. Only currently used
13795 for SSE, but applicable anywhere. */
13798 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13800 REAL_VALUE_TYPE TWO31r;
13803 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13804 NULL, 1, OPTAB_DIRECT);
13806 fp = gen_reg_rtx (DFmode);
13807 emit_insn (gen_floatsidf2 (fp, x));
13809 real_ldexp (&TWO31r, &dconst1, 31);
13810 x = const_double_from_real_value (TWO31r, DFmode);
13812 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13814 emit_move_insn (target, x);
13817 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13818 32-bit mode; otherwise we have a direct convert instruction. */
13821 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13823 REAL_VALUE_TYPE TWO32r;
13824 rtx fp_lo, fp_hi, x;
13826 fp_lo = gen_reg_rtx (DFmode);
13827 fp_hi = gen_reg_rtx (DFmode);
13829 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13831 real_ldexp (&TWO32r, &dconst1, 32);
13832 x = const_double_from_real_value (TWO32r, DFmode);
13833 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13835 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13837 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13840 emit_move_insn (target, x);
13843 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13844 For x86_32, -mfpmath=sse, !optimize_size only. */
13846 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13848 REAL_VALUE_TYPE ONE16r;
13849 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13851 real_ldexp (&ONE16r, &dconst1, 16);
13852 x = const_double_from_real_value (ONE16r, SFmode);
13853 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13854 NULL, 0, OPTAB_DIRECT);
13855 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13856 NULL, 0, OPTAB_DIRECT);
13857 fp_hi = gen_reg_rtx (SFmode);
13858 fp_lo = gen_reg_rtx (SFmode);
13859 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13860 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13861 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13863 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13865 if (!rtx_equal_p (target, fp_hi))
13866 emit_move_insn (target, fp_hi);
13869 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13870 then replicate the value for all elements of the vector
13874 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13881 v = gen_rtvec (4, value, value, value, value);
13882 return gen_rtx_CONST_VECTOR (V4SImode, v);
13886 v = gen_rtvec (2, value, value);
13887 return gen_rtx_CONST_VECTOR (V2DImode, v);
13891 v = gen_rtvec (4, value, value, value, value);
13893 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13894 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13895 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13899 v = gen_rtvec (2, value, value);
13901 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13902 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13905 gcc_unreachable ();
13909 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13910 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13911 for an SSE register. If VECT is true, then replicate the mask for
13912 all elements of the vector register. If INVERT is true, then create
13913 a mask excluding the sign bit. */
13916 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13918 enum machine_mode vec_mode, imode;
13919 HOST_WIDE_INT hi, lo;
13924 /* Find the sign bit, sign extended to 2*HWI. */
13930 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13931 lo = 0x80000000, hi = lo < 0;
13937 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13938 if (HOST_BITS_PER_WIDE_INT >= 64)
13939 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13941 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13946 vec_mode = VOIDmode;
13947 if (HOST_BITS_PER_WIDE_INT >= 64)
13950 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13957 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13961 lo = ~lo, hi = ~hi;
13967 mask = immed_double_const (lo, hi, imode);
13969 vec = gen_rtvec (2, v, mask);
13970 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13971 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13978 gcc_unreachable ();
13982 lo = ~lo, hi = ~hi;
13984 /* Force this value into the low part of a fp vector constant. */
13985 mask = immed_double_const (lo, hi, imode);
13986 mask = gen_lowpart (mode, mask);
13988 if (vec_mode == VOIDmode)
13989 return force_reg (mode, mask);
13991 v = ix86_build_const_vector (mode, vect, mask);
13992 return force_reg (vec_mode, v);
13995 /* Generate code for floating point ABS or NEG. */
13998 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14001 rtx mask, set, use, clob, dst, src;
14002 bool use_sse = false;
14003 bool vector_mode = VECTOR_MODE_P (mode);
14004 enum machine_mode elt_mode = mode;
14008 elt_mode = GET_MODE_INNER (mode);
14011 else if (mode == TFmode)
14013 else if (TARGET_SSE_MATH)
14014 use_sse = SSE_FLOAT_MODE_P (mode);
14016 /* NEG and ABS performed with SSE use bitwise mask operations.
14017 Create the appropriate mask now. */
14019 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14028 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14029 set = gen_rtx_SET (VOIDmode, dst, set);
14034 set = gen_rtx_fmt_e (code, mode, src);
14035 set = gen_rtx_SET (VOIDmode, dst, set);
14038 use = gen_rtx_USE (VOIDmode, mask);
14039 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14040 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14041 gen_rtvec (3, set, use, clob)));
14048 /* Expand a copysign operation. Special case operand 0 being a constant. */
14051 ix86_expand_copysign (rtx operands[])
14053 enum machine_mode mode;
14054 rtx dest, op0, op1, mask, nmask;
14056 dest = operands[0];
14060 mode = GET_MODE (dest);
14062 if (GET_CODE (op0) == CONST_DOUBLE)
14064 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14066 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14067 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14069 if (mode == SFmode || mode == DFmode)
14071 enum machine_mode vmode;
14073 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14075 if (op0 == CONST0_RTX (mode))
14076 op0 = CONST0_RTX (vmode);
14079 rtx v = ix86_build_const_vector (mode, false, op0);
14081 op0 = force_reg (vmode, v);
14084 else if (op0 != CONST0_RTX (mode))
14085 op0 = force_reg (mode, op0);
14087 mask = ix86_build_signbit_mask (mode, 0, 0);
14089 if (mode == SFmode)
14090 copysign_insn = gen_copysignsf3_const;
14091 else if (mode == DFmode)
14092 copysign_insn = gen_copysigndf3_const;
14094 copysign_insn = gen_copysigntf3_const;
14096 emit_insn (copysign_insn (dest, op0, op1, mask));
14100 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14102 nmask = ix86_build_signbit_mask (mode, 0, 1);
14103 mask = ix86_build_signbit_mask (mode, 0, 0);
14105 if (mode == SFmode)
14106 copysign_insn = gen_copysignsf3_var;
14107 else if (mode == DFmode)
14108 copysign_insn = gen_copysigndf3_var;
14110 copysign_insn = gen_copysigntf3_var;
14112 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14116 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14117 be a constant, and so has already been expanded into a vector constant. */
14120 ix86_split_copysign_const (rtx operands[])
14122 enum machine_mode mode, vmode;
14123 rtx dest, op0, mask, x;
14125 dest = operands[0];
14127 mask = operands[3];
14129 mode = GET_MODE (dest);
14130 vmode = GET_MODE (mask);
14132 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14133 x = gen_rtx_AND (vmode, dest, mask);
14134 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14136 if (op0 != CONST0_RTX (vmode))
14138 x = gen_rtx_IOR (vmode, dest, op0);
14139 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14143 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14144 so we have to do two masks. */
14147 ix86_split_copysign_var (rtx operands[])
14149 enum machine_mode mode, vmode;
14150 rtx dest, scratch, op0, op1, mask, nmask, x;
14152 dest = operands[0];
14153 scratch = operands[1];
14156 nmask = operands[4];
14157 mask = operands[5];
14159 mode = GET_MODE (dest);
14160 vmode = GET_MODE (mask);
14162 if (rtx_equal_p (op0, op1))
14164 /* Shouldn't happen often (it's useless, obviously), but when it does
14165 we'd generate incorrect code if we continue below. */
14166 emit_move_insn (dest, op0);
14170 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14172 gcc_assert (REGNO (op1) == REGNO (scratch));
14174 x = gen_rtx_AND (vmode, scratch, mask);
14175 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14178 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14179 x = gen_rtx_NOT (vmode, dest);
14180 x = gen_rtx_AND (vmode, x, op0);
14181 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14185 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14187 x = gen_rtx_AND (vmode, scratch, mask);
14189 else /* alternative 2,4 */
14191 gcc_assert (REGNO (mask) == REGNO (scratch));
14192 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14193 x = gen_rtx_AND (vmode, scratch, op1);
14195 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14197 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14199 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14200 x = gen_rtx_AND (vmode, dest, nmask);
14202 else /* alternative 3,4 */
14204 gcc_assert (REGNO (nmask) == REGNO (dest));
14206 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14207 x = gen_rtx_AND (vmode, dest, op0);
14209 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14212 x = gen_rtx_IOR (vmode, dest, scratch);
14213 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14216 /* Return TRUE or FALSE depending on whether the first SET in INSN
14217 has source and destination with matching CC modes, and that the
14218 CC mode is at least as constrained as REQ_MODE. */
14221 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14224 enum machine_mode set_mode;
14226 set = PATTERN (insn);
14227 if (GET_CODE (set) == PARALLEL)
14228 set = XVECEXP (set, 0, 0);
14229 gcc_assert (GET_CODE (set) == SET);
14230 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14232 set_mode = GET_MODE (SET_DEST (set));
14236 if (req_mode != CCNOmode
14237 && (req_mode != CCmode
14238 || XEXP (SET_SRC (set), 1) != const0_rtx))
14242 if (req_mode == CCGCmode)
14246 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14250 if (req_mode == CCZmode)
14261 gcc_unreachable ();
14264 return (GET_MODE (SET_SRC (set)) == set_mode);
14267 /* Generate insn patterns to do an integer compare of OPERANDS. */
14270 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14272 enum machine_mode cmpmode;
14275 cmpmode = SELECT_CC_MODE (code, op0, op1);
14276 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14278 /* This is very simple, but making the interface the same as in the
14279 FP case makes the rest of the code easier. */
14280 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14281 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14283 /* Return the test that should be put into the flags user, i.e.
14284 the bcc, scc, or cmov instruction. */
14285 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14288 /* Figure out whether to use ordered or unordered fp comparisons.
14289 Return the appropriate mode to use. */
14292 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14294 /* ??? In order to make all comparisons reversible, we do all comparisons
14295 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14296 all forms trapping and nontrapping comparisons, we can make inequality
14297 comparisons trapping again, since it results in better code when using
14298 FCOM based compares. */
14299 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14303 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14305 enum machine_mode mode = GET_MODE (op0);
14307 if (SCALAR_FLOAT_MODE_P (mode))
14309 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14310 return ix86_fp_compare_mode (code);
14315 /* Only zero flag is needed. */
14316 case EQ: /* ZF=0 */
14317 case NE: /* ZF!=0 */
14319 /* Codes needing carry flag. */
14320 case GEU: /* CF=0 */
14321 case LTU: /* CF=1 */
14322 /* Detect overflow checks. They need just the carry flag. */
14323 if (GET_CODE (op0) == PLUS
14324 && rtx_equal_p (op1, XEXP (op0, 0)))
14328 case GTU: /* CF=0 & ZF=0 */
14329 case LEU: /* CF=1 | ZF=1 */
14330 /* Detect overflow checks. They need just the carry flag. */
14331 if (GET_CODE (op0) == MINUS
14332 && rtx_equal_p (op1, XEXP (op0, 0)))
14336 /* Codes possibly doable only with sign flag when
14337 comparing against zero. */
14338 case GE: /* SF=OF or SF=0 */
14339 case LT: /* SF<>OF or SF=1 */
14340 if (op1 == const0_rtx)
14343 /* For other cases Carry flag is not required. */
14345 /* Codes doable only with sign flag when comparing
14346 against zero, but we miss jump instruction for it
14347 so we need to use relational tests against overflow
14348 that thus needs to be zero. */
14349 case GT: /* ZF=0 & SF=OF */
14350 case LE: /* ZF=1 | SF<>OF */
14351 if (op1 == const0_rtx)
14355 /* strcmp pattern do (use flags) and combine may ask us for proper
14360 gcc_unreachable ();
14364 /* Return the fixed registers used for condition codes. */
14367 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14374 /* If two condition code modes are compatible, return a condition code
14375 mode which is compatible with both. Otherwise, return
14378 static enum machine_mode
14379 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14384 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14387 if ((m1 == CCGCmode && m2 == CCGOCmode)
14388 || (m1 == CCGOCmode && m2 == CCGCmode))
14394 gcc_unreachable ();
14424 /* These are only compatible with themselves, which we already
14431 /* Return a comparison we can do and that it is equivalent to
14432 swap_condition (code) apart possibly from orderedness.
14433 But, never change orderedness if TARGET_IEEE_FP, returning
14434 UNKNOWN in that case if necessary. */
14436 static enum rtx_code
14437 ix86_fp_swap_condition (enum rtx_code code)
14441 case GT: /* GTU - CF=0 & ZF=0 */
14442 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14443 case GE: /* GEU - CF=0 */
14444 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14445 case UNLT: /* LTU - CF=1 */
14446 return TARGET_IEEE_FP ? UNKNOWN : GT;
14447 case UNLE: /* LEU - CF=1 | ZF=1 */
14448 return TARGET_IEEE_FP ? UNKNOWN : GE;
14450 return swap_condition (code);
14454 /* Return cost of comparison CODE using the best strategy for performance.
14455 All following functions do use number of instructions as a cost metrics.
14456 In future this should be tweaked to compute bytes for optimize_size and
14457 take into account performance of various instructions on various CPUs. */
14460 ix86_fp_comparison_cost (enum rtx_code code)
14464 /* The cost of code using bit-twiddling on %ah. */
14481 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14485 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14488 gcc_unreachable ();
14491 switch (ix86_fp_comparison_strategy (code))
14493 case IX86_FPCMP_COMI:
14494 return arith_cost > 4 ? 3 : 2;
14495 case IX86_FPCMP_SAHF:
14496 return arith_cost > 4 ? 4 : 3;
14502 /* Return strategy to use for floating-point. We assume that fcomi is always
14503 preferrable where available, since that is also true when looking at size
14504 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14506 enum ix86_fpcmp_strategy
14507 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14509 /* Do fcomi/sahf based test when profitable. */
14512 return IX86_FPCMP_COMI;
14514 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14515 return IX86_FPCMP_SAHF;
14517 return IX86_FPCMP_ARITH;
14520 /* Swap, force into registers, or otherwise massage the two operands
14521 to a fp comparison. The operands are updated in place; the new
14522 comparison code is returned. */
14524 static enum rtx_code
14525 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14527 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14528 rtx op0 = *pop0, op1 = *pop1;
14529 enum machine_mode op_mode = GET_MODE (op0);
14530 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14532 /* All of the unordered compare instructions only work on registers.
14533 The same is true of the fcomi compare instructions. The XFmode
14534 compare instructions require registers except when comparing
14535 against zero or when converting operand 1 from fixed point to
14539 && (fpcmp_mode == CCFPUmode
14540 || (op_mode == XFmode
14541 && ! (standard_80387_constant_p (op0) == 1
14542 || standard_80387_constant_p (op1) == 1)
14543 && GET_CODE (op1) != FLOAT)
14544 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14546 op0 = force_reg (op_mode, op0);
14547 op1 = force_reg (op_mode, op1);
14551 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14552 things around if they appear profitable, otherwise force op0
14553 into a register. */
14555 if (standard_80387_constant_p (op0) == 0
14557 && ! (standard_80387_constant_p (op1) == 0
14560 enum rtx_code new_code = ix86_fp_swap_condition (code);
14561 if (new_code != UNKNOWN)
14564 tmp = op0, op0 = op1, op1 = tmp;
14570 op0 = force_reg (op_mode, op0);
14572 if (CONSTANT_P (op1))
14574 int tmp = standard_80387_constant_p (op1);
14576 op1 = validize_mem (force_const_mem (op_mode, op1));
14580 op1 = force_reg (op_mode, op1);
14583 op1 = force_reg (op_mode, op1);
14587 /* Try to rearrange the comparison to make it cheaper. */
14588 if (ix86_fp_comparison_cost (code)
14589 > ix86_fp_comparison_cost (swap_condition (code))
14590 && (REG_P (op1) || can_create_pseudo_p ()))
14593 tmp = op0, op0 = op1, op1 = tmp;
14594 code = swap_condition (code);
14596 op0 = force_reg (op_mode, op0);
14604 /* Convert comparison codes we use to represent FP comparison to integer
14605 code that will result in proper branch. Return UNKNOWN if no such code
14609 ix86_fp_compare_code_to_integer (enum rtx_code code)
14638 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14641 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14643 enum machine_mode fpcmp_mode, intcmp_mode;
14646 fpcmp_mode = ix86_fp_compare_mode (code);
14647 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14649 /* Do fcomi/sahf based test when profitable. */
14650 switch (ix86_fp_comparison_strategy (code))
14652 case IX86_FPCMP_COMI:
14653 intcmp_mode = fpcmp_mode;
14654 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14655 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14660 case IX86_FPCMP_SAHF:
14661 intcmp_mode = fpcmp_mode;
14662 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14663 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14667 scratch = gen_reg_rtx (HImode);
14668 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14669 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14672 case IX86_FPCMP_ARITH:
14673 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14674 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14675 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14677 scratch = gen_reg_rtx (HImode);
14678 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14680 /* In the unordered case, we have to check C2 for NaN's, which
14681 doesn't happen to work out to anything nice combination-wise.
14682 So do some bit twiddling on the value we've got in AH to come
14683 up with an appropriate set of condition codes. */
14685 intcmp_mode = CCNOmode;
14690 if (code == GT || !TARGET_IEEE_FP)
14692 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14697 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14698 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14699 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14700 intcmp_mode = CCmode;
14706 if (code == LT && TARGET_IEEE_FP)
14708 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14709 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14710 intcmp_mode = CCmode;
14715 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14721 if (code == GE || !TARGET_IEEE_FP)
14723 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14728 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14729 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14735 if (code == LE && TARGET_IEEE_FP)
14737 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14738 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14739 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14740 intcmp_mode = CCmode;
14745 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14751 if (code == EQ && TARGET_IEEE_FP)
14753 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14754 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14755 intcmp_mode = CCmode;
14760 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14766 if (code == NE && TARGET_IEEE_FP)
14768 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14769 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14775 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14781 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14785 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14790 gcc_unreachable ();
14798 /* Return the test that should be put into the flags user, i.e.
14799 the bcc, scc, or cmov instruction. */
14800 return gen_rtx_fmt_ee (code, VOIDmode,
14801 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14806 ix86_expand_compare (enum rtx_code code)
14809 op0 = ix86_compare_op0;
14810 op1 = ix86_compare_op1;
14812 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14813 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14815 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14817 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14818 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
14821 ret = ix86_expand_int_compare (code, op0, op1);
14827 ix86_expand_branch (enum rtx_code code, rtx label)
14831 switch (GET_MODE (ix86_compare_op0))
14840 tmp = ix86_expand_compare (code);
14841 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14842 gen_rtx_LABEL_REF (VOIDmode, label),
14844 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14851 /* Expand DImode branch into multiple compare+branch. */
14853 rtx lo[2], hi[2], label2;
14854 enum rtx_code code1, code2, code3;
14855 enum machine_mode submode;
14857 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14859 tmp = ix86_compare_op0;
14860 ix86_compare_op0 = ix86_compare_op1;
14861 ix86_compare_op1 = tmp;
14862 code = swap_condition (code);
14864 if (GET_MODE (ix86_compare_op0) == DImode)
14866 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14867 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14872 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14873 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14877 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14878 avoid two branches. This costs one extra insn, so disable when
14879 optimizing for size. */
14881 if ((code == EQ || code == NE)
14882 && (!optimize_insn_for_size_p ()
14883 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14888 if (hi[1] != const0_rtx)
14889 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14890 NULL_RTX, 0, OPTAB_WIDEN);
14893 if (lo[1] != const0_rtx)
14894 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14895 NULL_RTX, 0, OPTAB_WIDEN);
14897 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14898 NULL_RTX, 0, OPTAB_WIDEN);
14900 ix86_compare_op0 = tmp;
14901 ix86_compare_op1 = const0_rtx;
14902 ix86_expand_branch (code, label);
14906 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14907 op1 is a constant and the low word is zero, then we can just
14908 examine the high word. Similarly for low word -1 and
14909 less-or-equal-than or greater-than. */
14911 if (CONST_INT_P (hi[1]))
14914 case LT: case LTU: case GE: case GEU:
14915 if (lo[1] == const0_rtx)
14917 ix86_compare_op0 = hi[0];
14918 ix86_compare_op1 = hi[1];
14919 ix86_expand_branch (code, label);
14923 case LE: case LEU: case GT: case GTU:
14924 if (lo[1] == constm1_rtx)
14926 ix86_compare_op0 = hi[0];
14927 ix86_compare_op1 = hi[1];
14928 ix86_expand_branch (code, label);
14936 /* Otherwise, we need two or three jumps. */
14938 label2 = gen_label_rtx ();
14941 code2 = swap_condition (code);
14942 code3 = unsigned_condition (code);
14946 case LT: case GT: case LTU: case GTU:
14949 case LE: code1 = LT; code2 = GT; break;
14950 case GE: code1 = GT; code2 = LT; break;
14951 case LEU: code1 = LTU; code2 = GTU; break;
14952 case GEU: code1 = GTU; code2 = LTU; break;
14954 case EQ: code1 = UNKNOWN; code2 = NE; break;
14955 case NE: code2 = UNKNOWN; break;
14958 gcc_unreachable ();
14963 * if (hi(a) < hi(b)) goto true;
14964 * if (hi(a) > hi(b)) goto false;
14965 * if (lo(a) < lo(b)) goto true;
14969 ix86_compare_op0 = hi[0];
14970 ix86_compare_op1 = hi[1];
14972 if (code1 != UNKNOWN)
14973 ix86_expand_branch (code1, label);
14974 if (code2 != UNKNOWN)
14975 ix86_expand_branch (code2, label2);
14977 ix86_compare_op0 = lo[0];
14978 ix86_compare_op1 = lo[1];
14979 ix86_expand_branch (code3, label);
14981 if (code2 != UNKNOWN)
14982 emit_label (label2);
14987 /* If we have already emitted a compare insn, go straight to simple.
14988 ix86_expand_compare won't emit anything if ix86_compare_emitted
14990 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
14995 /* Split branch based on floating point condition. */
14997 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14998 rtx target1, rtx target2, rtx tmp, rtx pushed)
15003 if (target2 != pc_rtx)
15006 code = reverse_condition_maybe_unordered (code);
15011 condition = ix86_expand_fp_compare (code, op1, op2,
15014 /* Remove pushed operand from stack. */
15016 ix86_free_from_memory (GET_MODE (pushed));
15018 i = emit_jump_insn (gen_rtx_SET
15020 gen_rtx_IF_THEN_ELSE (VOIDmode,
15021 condition, target1, target2)));
15022 if (split_branch_probability >= 0)
15023 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15027 ix86_expand_setcc (enum rtx_code code, rtx dest)
15031 gcc_assert (GET_MODE (dest) == QImode);
15033 ret = ix86_expand_compare (code);
15034 PUT_MODE (ret, QImode);
15035 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15038 /* Expand comparison setting or clearing carry flag. Return true when
15039 successful and set pop for the operation. */
15041 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15043 enum machine_mode mode =
15044 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15046 /* Do not handle DImode compares that go through special path. */
15047 if (mode == (TARGET_64BIT ? TImode : DImode))
15050 if (SCALAR_FLOAT_MODE_P (mode))
15052 rtx compare_op, compare_seq;
15054 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15056 /* Shortcut: following common codes never translate
15057 into carry flag compares. */
15058 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15059 || code == ORDERED || code == UNORDERED)
15062 /* These comparisons require zero flag; swap operands so they won't. */
15063 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15064 && !TARGET_IEEE_FP)
15069 code = swap_condition (code);
15072 /* Try to expand the comparison and verify that we end up with
15073 carry flag based comparison. This fails to be true only when
15074 we decide to expand comparison using arithmetic that is not
15075 too common scenario. */
15077 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15078 compare_seq = get_insns ();
15081 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15082 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15083 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15085 code = GET_CODE (compare_op);
15087 if (code != LTU && code != GEU)
15090 emit_insn (compare_seq);
15095 if (!INTEGRAL_MODE_P (mode))
15104 /* Convert a==0 into (unsigned)a<1. */
15107 if (op1 != const0_rtx)
15110 code = (code == EQ ? LTU : GEU);
15113 /* Convert a>b into b<a or a>=b-1. */
15116 if (CONST_INT_P (op1))
15118 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15119 /* Bail out on overflow. We still can swap operands but that
15120 would force loading of the constant into register. */
15121 if (op1 == const0_rtx
15122 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15124 code = (code == GTU ? GEU : LTU);
15131 code = (code == GTU ? LTU : GEU);
15135 /* Convert a>=0 into (unsigned)a<0x80000000. */
15138 if (mode == DImode || op1 != const0_rtx)
15140 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15141 code = (code == LT ? GEU : LTU);
15145 if (mode == DImode || op1 != constm1_rtx)
15147 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15148 code = (code == LE ? GEU : LTU);
15154 /* Swapping operands may cause constant to appear as first operand. */
15155 if (!nonimmediate_operand (op0, VOIDmode))
15157 if (!can_create_pseudo_p ())
15159 op0 = force_reg (mode, op0);
15161 ix86_compare_op0 = op0;
15162 ix86_compare_op1 = op1;
15163 *pop = ix86_expand_compare (code);
15164 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15169 ix86_expand_int_movcc (rtx operands[])
15171 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15172 rtx compare_seq, compare_op;
15173 enum machine_mode mode = GET_MODE (operands[0]);
15174 bool sign_bit_compare_p = false;;
15177 ix86_compare_op0 = XEXP (operands[1], 0);
15178 ix86_compare_op1 = XEXP (operands[1], 1);
15179 compare_op = ix86_expand_compare (code);
15180 compare_seq = get_insns ();
15183 compare_code = GET_CODE (compare_op);
15185 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15186 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15187 sign_bit_compare_p = true;
15189 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15190 HImode insns, we'd be swallowed in word prefix ops. */
15192 if ((mode != HImode || TARGET_FAST_PREFIX)
15193 && (mode != (TARGET_64BIT ? TImode : DImode))
15194 && CONST_INT_P (operands[2])
15195 && CONST_INT_P (operands[3]))
15197 rtx out = operands[0];
15198 HOST_WIDE_INT ct = INTVAL (operands[2]);
15199 HOST_WIDE_INT cf = INTVAL (operands[3]);
15200 HOST_WIDE_INT diff;
15203 /* Sign bit compares are better done using shifts than we do by using
15205 if (sign_bit_compare_p
15206 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15207 ix86_compare_op1, &compare_op))
15209 /* Detect overlap between destination and compare sources. */
15212 if (!sign_bit_compare_p)
15214 bool fpcmp = false;
15216 compare_code = GET_CODE (compare_op);
15218 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15219 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15222 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15225 /* To simplify rest of code, restrict to the GEU case. */
15226 if (compare_code == LTU)
15228 HOST_WIDE_INT tmp = ct;
15231 compare_code = reverse_condition (compare_code);
15232 code = reverse_condition (code);
15237 PUT_CODE (compare_op,
15238 reverse_condition_maybe_unordered
15239 (GET_CODE (compare_op)));
15241 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15245 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15246 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15247 tmp = gen_reg_rtx (mode);
15249 if (mode == DImode)
15250 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15252 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15256 if (code == GT || code == GE)
15257 code = reverse_condition (code);
15260 HOST_WIDE_INT tmp = ct;
15265 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15266 ix86_compare_op1, VOIDmode, 0, -1);
15279 tmp = expand_simple_binop (mode, PLUS,
15281 copy_rtx (tmp), 1, OPTAB_DIRECT);
15292 tmp = expand_simple_binop (mode, IOR,
15294 copy_rtx (tmp), 1, OPTAB_DIRECT);
15296 else if (diff == -1 && ct)
15306 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15308 tmp = expand_simple_binop (mode, PLUS,
15309 copy_rtx (tmp), GEN_INT (cf),
15310 copy_rtx (tmp), 1, OPTAB_DIRECT);
15318 * andl cf - ct, dest
15328 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15331 tmp = expand_simple_binop (mode, AND,
15333 gen_int_mode (cf - ct, mode),
15334 copy_rtx (tmp), 1, OPTAB_DIRECT);
15336 tmp = expand_simple_binop (mode, PLUS,
15337 copy_rtx (tmp), GEN_INT (ct),
15338 copy_rtx (tmp), 1, OPTAB_DIRECT);
15341 if (!rtx_equal_p (tmp, out))
15342 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15344 return 1; /* DONE */
15349 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15352 tmp = ct, ct = cf, cf = tmp;
15355 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15357 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15359 /* We may be reversing unordered compare to normal compare, that
15360 is not valid in general (we may convert non-trapping condition
15361 to trapping one), however on i386 we currently emit all
15362 comparisons unordered. */
15363 compare_code = reverse_condition_maybe_unordered (compare_code);
15364 code = reverse_condition_maybe_unordered (code);
15368 compare_code = reverse_condition (compare_code);
15369 code = reverse_condition (code);
15373 compare_code = UNKNOWN;
15374 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15375 && CONST_INT_P (ix86_compare_op1))
15377 if (ix86_compare_op1 == const0_rtx
15378 && (code == LT || code == GE))
15379 compare_code = code;
15380 else if (ix86_compare_op1 == constm1_rtx)
15384 else if (code == GT)
15389 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15390 if (compare_code != UNKNOWN
15391 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15392 && (cf == -1 || ct == -1))
15394 /* If lea code below could be used, only optimize
15395 if it results in a 2 insn sequence. */
15397 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15398 || diff == 3 || diff == 5 || diff == 9)
15399 || (compare_code == LT && ct == -1)
15400 || (compare_code == GE && cf == -1))
15403 * notl op1 (if necessary)
15411 code = reverse_condition (code);
15414 out = emit_store_flag (out, code, ix86_compare_op0,
15415 ix86_compare_op1, VOIDmode, 0, -1);
15417 out = expand_simple_binop (mode, IOR,
15419 out, 1, OPTAB_DIRECT);
15420 if (out != operands[0])
15421 emit_move_insn (operands[0], out);
15423 return 1; /* DONE */
15428 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15429 || diff == 3 || diff == 5 || diff == 9)
15430 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15432 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15438 * lea cf(dest*(ct-cf)),dest
15442 * This also catches the degenerate setcc-only case.
15448 out = emit_store_flag (out, code, ix86_compare_op0,
15449 ix86_compare_op1, VOIDmode, 0, 1);
15452 /* On x86_64 the lea instruction operates on Pmode, so we need
15453 to get arithmetics done in proper mode to match. */
15455 tmp = copy_rtx (out);
15459 out1 = copy_rtx (out);
15460 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15464 tmp = gen_rtx_PLUS (mode, tmp, out1);
15470 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15473 if (!rtx_equal_p (tmp, out))
15476 out = force_operand (tmp, copy_rtx (out));
15478 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15480 if (!rtx_equal_p (out, operands[0]))
15481 emit_move_insn (operands[0], copy_rtx (out));
15483 return 1; /* DONE */
15487 * General case: Jumpful:
15488 * xorl dest,dest cmpl op1, op2
15489 * cmpl op1, op2 movl ct, dest
15490 * setcc dest jcc 1f
15491 * decl dest movl cf, dest
15492 * andl (cf-ct),dest 1:
15495 * Size 20. Size 14.
15497 * This is reasonably steep, but branch mispredict costs are
15498 * high on modern cpus, so consider failing only if optimizing
15502 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15503 && BRANCH_COST (optimize_insn_for_speed_p (),
15508 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15513 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15515 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15517 /* We may be reversing unordered compare to normal compare,
15518 that is not valid in general (we may convert non-trapping
15519 condition to trapping one), however on i386 we currently
15520 emit all comparisons unordered. */
15521 code = reverse_condition_maybe_unordered (code);
15525 code = reverse_condition (code);
15526 if (compare_code != UNKNOWN)
15527 compare_code = reverse_condition (compare_code);
15531 if (compare_code != UNKNOWN)
15533 /* notl op1 (if needed)
15538 For x < 0 (resp. x <= -1) there will be no notl,
15539 so if possible swap the constants to get rid of the
15541 True/false will be -1/0 while code below (store flag
15542 followed by decrement) is 0/-1, so the constants need
15543 to be exchanged once more. */
15545 if (compare_code == GE || !cf)
15547 code = reverse_condition (code);
15552 HOST_WIDE_INT tmp = cf;
15557 out = emit_store_flag (out, code, ix86_compare_op0,
15558 ix86_compare_op1, VOIDmode, 0, -1);
15562 out = emit_store_flag (out, code, ix86_compare_op0,
15563 ix86_compare_op1, VOIDmode, 0, 1);
15565 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15566 copy_rtx (out), 1, OPTAB_DIRECT);
15569 out = expand_simple_binop (mode, AND, copy_rtx (out),
15570 gen_int_mode (cf - ct, mode),
15571 copy_rtx (out), 1, OPTAB_DIRECT);
15573 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15574 copy_rtx (out), 1, OPTAB_DIRECT);
15575 if (!rtx_equal_p (out, operands[0]))
15576 emit_move_insn (operands[0], copy_rtx (out));
15578 return 1; /* DONE */
15582 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15584 /* Try a few things more with specific constants and a variable. */
15587 rtx var, orig_out, out, tmp;
15589 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15590 return 0; /* FAIL */
15592 /* If one of the two operands is an interesting constant, load a
15593 constant with the above and mask it in with a logical operation. */
15595 if (CONST_INT_P (operands[2]))
15598 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15599 operands[3] = constm1_rtx, op = and_optab;
15600 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15601 operands[3] = const0_rtx, op = ior_optab;
15603 return 0; /* FAIL */
15605 else if (CONST_INT_P (operands[3]))
15608 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15609 operands[2] = constm1_rtx, op = and_optab;
15610 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15611 operands[2] = const0_rtx, op = ior_optab;
15613 return 0; /* FAIL */
15616 return 0; /* FAIL */
15618 orig_out = operands[0];
15619 tmp = gen_reg_rtx (mode);
15622 /* Recurse to get the constant loaded. */
15623 if (ix86_expand_int_movcc (operands) == 0)
15624 return 0; /* FAIL */
15626 /* Mask in the interesting variable. */
15627 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15629 if (!rtx_equal_p (out, orig_out))
15630 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15632 return 1; /* DONE */
15636 * For comparison with above,
15646 if (! nonimmediate_operand (operands[2], mode))
15647 operands[2] = force_reg (mode, operands[2]);
15648 if (! nonimmediate_operand (operands[3], mode))
15649 operands[3] = force_reg (mode, operands[3]);
15651 if (! register_operand (operands[2], VOIDmode)
15653 || ! register_operand (operands[3], VOIDmode)))
15654 operands[2] = force_reg (mode, operands[2]);
15657 && ! register_operand (operands[3], VOIDmode))
15658 operands[3] = force_reg (mode, operands[3]);
15660 emit_insn (compare_seq);
15661 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15662 gen_rtx_IF_THEN_ELSE (mode,
15663 compare_op, operands[2],
15666 return 1; /* DONE */
15669 /* Swap, force into registers, or otherwise massage the two operands
15670 to an sse comparison with a mask result. Thus we differ a bit from
15671 ix86_prepare_fp_compare_args which expects to produce a flags result.
15673 The DEST operand exists to help determine whether to commute commutative
15674 operators. The POP0/POP1 operands are updated in place. The new
15675 comparison code is returned, or UNKNOWN if not implementable. */
15677 static enum rtx_code
15678 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15679 rtx *pop0, rtx *pop1)
15687 /* We have no LTGT as an operator. We could implement it with
15688 NE & ORDERED, but this requires an extra temporary. It's
15689 not clear that it's worth it. */
15696 /* These are supported directly. */
15703 /* For commutative operators, try to canonicalize the destination
15704 operand to be first in the comparison - this helps reload to
15705 avoid extra moves. */
15706 if (!dest || !rtx_equal_p (dest, *pop1))
15714 /* These are not supported directly. Swap the comparison operands
15715 to transform into something that is supported. */
15719 code = swap_condition (code);
15723 gcc_unreachable ();
15729 /* Detect conditional moves that exactly match min/max operational
15730 semantics. Note that this is IEEE safe, as long as we don't
15731 interchange the operands.
15733 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15734 and TRUE if the operation is successful and instructions are emitted. */
15737 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15738 rtx cmp_op1, rtx if_true, rtx if_false)
15740 enum machine_mode mode;
15746 else if (code == UNGE)
15749 if_true = if_false;
15755 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15757 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15762 mode = GET_MODE (dest);
15764 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15765 but MODE may be a vector mode and thus not appropriate. */
15766 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15768 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15771 if_true = force_reg (mode, if_true);
15772 v = gen_rtvec (2, if_true, if_false);
15773 tmp = gen_rtx_UNSPEC (mode, v, u);
15777 code = is_min ? SMIN : SMAX;
15778 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15781 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15785 /* Expand an sse vector comparison. Return the register with the result. */
15788 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15789 rtx op_true, rtx op_false)
15791 enum machine_mode mode = GET_MODE (dest);
15794 cmp_op0 = force_reg (mode, cmp_op0);
15795 if (!nonimmediate_operand (cmp_op1, mode))
15796 cmp_op1 = force_reg (mode, cmp_op1);
15799 || reg_overlap_mentioned_p (dest, op_true)
15800 || reg_overlap_mentioned_p (dest, op_false))
15801 dest = gen_reg_rtx (mode);
15803 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15804 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15809 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15810 operations. This is used for both scalar and vector conditional moves. */
15813 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15815 enum machine_mode mode = GET_MODE (dest);
15818 if (op_false == CONST0_RTX (mode))
15820 op_true = force_reg (mode, op_true);
15821 x = gen_rtx_AND (mode, cmp, op_true);
15822 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15824 else if (op_true == CONST0_RTX (mode))
15826 op_false = force_reg (mode, op_false);
15827 x = gen_rtx_NOT (mode, cmp);
15828 x = gen_rtx_AND (mode, x, op_false);
15829 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15833 op_true = force_reg (mode, op_true);
15834 op_false = force_reg (mode, op_false);
15836 t2 = gen_reg_rtx (mode);
15838 t3 = gen_reg_rtx (mode);
15842 x = gen_rtx_AND (mode, op_true, cmp);
15843 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15845 x = gen_rtx_NOT (mode, cmp);
15846 x = gen_rtx_AND (mode, x, op_false);
15847 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15849 x = gen_rtx_IOR (mode, t3, t2);
15850 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15854 /* Expand a floating-point conditional move. Return true if successful. */
15857 ix86_expand_fp_movcc (rtx operands[])
15859 enum machine_mode mode = GET_MODE (operands[0]);
15860 enum rtx_code code = GET_CODE (operands[1]);
15861 rtx tmp, compare_op;
15863 ix86_compare_op0 = XEXP (operands[1], 0);
15864 ix86_compare_op1 = XEXP (operands[1], 1);
15865 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15867 enum machine_mode cmode;
15869 /* Since we've no cmove for sse registers, don't force bad register
15870 allocation just to gain access to it. Deny movcc when the
15871 comparison mode doesn't match the move mode. */
15872 cmode = GET_MODE (ix86_compare_op0);
15873 if (cmode == VOIDmode)
15874 cmode = GET_MODE (ix86_compare_op1);
15878 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15880 &ix86_compare_op1);
15881 if (code == UNKNOWN)
15884 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15885 ix86_compare_op1, operands[2],
15889 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15890 ix86_compare_op1, operands[2], operands[3]);
15891 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15895 /* The floating point conditional move instructions don't directly
15896 support conditions resulting from a signed integer comparison. */
15898 compare_op = ix86_expand_compare (code);
15899 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15901 tmp = gen_reg_rtx (QImode);
15902 ix86_expand_setcc (code, tmp);
15904 ix86_compare_op0 = tmp;
15905 ix86_compare_op1 = const0_rtx;
15906 compare_op = ix86_expand_compare (code);
15909 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15910 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15911 operands[2], operands[3])));
15916 /* Expand a floating-point vector conditional move; a vcond operation
15917 rather than a movcc operation. */
15920 ix86_expand_fp_vcond (rtx operands[])
15922 enum rtx_code code = GET_CODE (operands[3]);
15925 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15926 &operands[4], &operands[5]);
15927 if (code == UNKNOWN)
15930 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15931 operands[5], operands[1], operands[2]))
15934 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15935 operands[1], operands[2]);
15936 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15940 /* Expand a signed/unsigned integral vector conditional move. */
15943 ix86_expand_int_vcond (rtx operands[])
15945 enum machine_mode mode = GET_MODE (operands[0]);
15946 enum rtx_code code = GET_CODE (operands[3]);
15947 bool negate = false;
15950 cop0 = operands[4];
15951 cop1 = operands[5];
15953 /* Canonicalize the comparison to EQ, GT, GTU. */
15964 code = reverse_condition (code);
15970 code = reverse_condition (code);
15976 code = swap_condition (code);
15977 x = cop0, cop0 = cop1, cop1 = x;
15981 gcc_unreachable ();
15984 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15985 if (mode == V2DImode)
15990 /* SSE4.1 supports EQ. */
15991 if (!TARGET_SSE4_1)
15997 /* SSE4.2 supports GT/GTU. */
15998 if (!TARGET_SSE4_2)
16003 gcc_unreachable ();
16007 /* Unsigned parallel compare is not supported by the hardware. Play some
16008 tricks to turn this into a signed comparison against 0. */
16011 cop0 = force_reg (mode, cop0);
16020 /* Perform a parallel modulo subtraction. */
16021 t1 = gen_reg_rtx (mode);
16022 emit_insn ((mode == V4SImode
16024 : gen_subv2di3) (t1, cop0, cop1));
16026 /* Extract the original sign bit of op0. */
16027 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16029 t2 = gen_reg_rtx (mode);
16030 emit_insn ((mode == V4SImode
16032 : gen_andv2di3) (t2, cop0, mask));
16034 /* XOR it back into the result of the subtraction. This results
16035 in the sign bit set iff we saw unsigned underflow. */
16036 x = gen_reg_rtx (mode);
16037 emit_insn ((mode == V4SImode
16039 : gen_xorv2di3) (x, t1, t2));
16047 /* Perform a parallel unsigned saturating subtraction. */
16048 x = gen_reg_rtx (mode);
16049 emit_insn (gen_rtx_SET (VOIDmode, x,
16050 gen_rtx_US_MINUS (mode, cop0, cop1)));
16057 gcc_unreachable ();
16061 cop1 = CONST0_RTX (mode);
16064 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16065 operands[1+negate], operands[2-negate]);
16067 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16068 operands[2-negate]);
16072 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16073 true if we should do zero extension, else sign extension. HIGH_P is
16074 true if we want the N/2 high elements, else the low elements. */
16077 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16079 enum machine_mode imode = GET_MODE (operands[1]);
16080 rtx (*unpack)(rtx, rtx, rtx);
16087 unpack = gen_vec_interleave_highv16qi;
16089 unpack = gen_vec_interleave_lowv16qi;
16093 unpack = gen_vec_interleave_highv8hi;
16095 unpack = gen_vec_interleave_lowv8hi;
16099 unpack = gen_vec_interleave_highv4si;
16101 unpack = gen_vec_interleave_lowv4si;
16104 gcc_unreachable ();
16107 dest = gen_lowpart (imode, operands[0]);
16110 se = force_reg (imode, CONST0_RTX (imode));
16112 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16113 operands[1], pc_rtx, pc_rtx);
16115 emit_insn (unpack (dest, operands[1], se));
16118 /* This function performs the same task as ix86_expand_sse_unpack,
16119 but with SSE4.1 instructions. */
16122 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16124 enum machine_mode imode = GET_MODE (operands[1]);
16125 rtx (*unpack)(rtx, rtx);
16132 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16134 unpack = gen_sse4_1_extendv8qiv8hi2;
16138 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16140 unpack = gen_sse4_1_extendv4hiv4si2;
16144 unpack = gen_sse4_1_zero_extendv2siv2di2;
16146 unpack = gen_sse4_1_extendv2siv2di2;
16149 gcc_unreachable ();
16152 dest = operands[0];
16155 /* Shift higher 8 bytes to lower 8 bytes. */
16156 src = gen_reg_rtx (imode);
16157 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16158 gen_lowpart (TImode, operands[1]),
16164 emit_insn (unpack (dest, src));
16167 /* Expand conditional increment or decrement using adb/sbb instructions.
16168 The default case using setcc followed by the conditional move can be
16169 done by generic code. */
16171 ix86_expand_int_addcc (rtx operands[])
16173 enum rtx_code code = GET_CODE (operands[1]);
16174 rtx (*insn)(rtx, rtx, rtx, rtx);
16176 rtx val = const0_rtx;
16177 bool fpcmp = false;
16178 enum machine_mode mode = GET_MODE (operands[0]);
16180 ix86_compare_op0 = XEXP (operands[1], 0);
16181 ix86_compare_op1 = XEXP (operands[1], 1);
16182 if (operands[3] != const1_rtx
16183 && operands[3] != constm1_rtx)
16185 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16186 ix86_compare_op1, &compare_op))
16188 code = GET_CODE (compare_op);
16190 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16191 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16194 code = ix86_fp_compare_code_to_integer (code);
16201 PUT_CODE (compare_op,
16202 reverse_condition_maybe_unordered
16203 (GET_CODE (compare_op)));
16205 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16207 PUT_MODE (compare_op, mode);
16209 /* Construct either adc or sbb insn. */
16210 if ((code == LTU) == (operands[3] == constm1_rtx))
16212 switch (GET_MODE (operands[0]))
16215 insn = gen_subqi3_carry;
16218 insn = gen_subhi3_carry;
16221 insn = gen_subsi3_carry;
16224 insn = gen_subdi3_carry;
16227 gcc_unreachable ();
16232 switch (GET_MODE (operands[0]))
16235 insn = gen_addqi3_carry;
16238 insn = gen_addhi3_carry;
16241 insn = gen_addsi3_carry;
16244 insn = gen_adddi3_carry;
16247 gcc_unreachable ();
16250 emit_insn (insn (operands[0], operands[2], val, compare_op));
16252 return 1; /* DONE */
16256 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16257 works for floating pointer parameters and nonoffsetable memories.
16258 For pushes, it returns just stack offsets; the values will be saved
16259 in the right order. Maximally three parts are generated. */
16262 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16267 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16269 size = (GET_MODE_SIZE (mode) + 4) / 8;
16271 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16272 gcc_assert (size >= 2 && size <= 4);
16274 /* Optimize constant pool reference to immediates. This is used by fp
16275 moves, that force all constants to memory to allow combining. */
16276 if (MEM_P (operand) && MEM_READONLY_P (operand))
16278 rtx tmp = maybe_get_pool_constant (operand);
16283 if (MEM_P (operand) && !offsettable_memref_p (operand))
16285 /* The only non-offsetable memories we handle are pushes. */
16286 int ok = push_operand (operand, VOIDmode);
16290 operand = copy_rtx (operand);
16291 PUT_MODE (operand, Pmode);
16292 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16296 if (GET_CODE (operand) == CONST_VECTOR)
16298 enum machine_mode imode = int_mode_for_mode (mode);
16299 /* Caution: if we looked through a constant pool memory above,
16300 the operand may actually have a different mode now. That's
16301 ok, since we want to pun this all the way back to an integer. */
16302 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16303 gcc_assert (operand != NULL);
16309 if (mode == DImode)
16310 split_di (&operand, 1, &parts[0], &parts[1]);
16315 if (REG_P (operand))
16317 gcc_assert (reload_completed);
16318 for (i = 0; i < size; i++)
16319 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16321 else if (offsettable_memref_p (operand))
16323 operand = adjust_address (operand, SImode, 0);
16324 parts[0] = operand;
16325 for (i = 1; i < size; i++)
16326 parts[i] = adjust_address (operand, SImode, 4 * i);
16328 else if (GET_CODE (operand) == CONST_DOUBLE)
16333 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16337 real_to_target (l, &r, mode);
16338 parts[3] = gen_int_mode (l[3], SImode);
16339 parts[2] = gen_int_mode (l[2], SImode);
16342 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16343 parts[2] = gen_int_mode (l[2], SImode);
16346 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16349 gcc_unreachable ();
16351 parts[1] = gen_int_mode (l[1], SImode);
16352 parts[0] = gen_int_mode (l[0], SImode);
16355 gcc_unreachable ();
16360 if (mode == TImode)
16361 split_ti (&operand, 1, &parts[0], &parts[1]);
16362 if (mode == XFmode || mode == TFmode)
16364 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16365 if (REG_P (operand))
16367 gcc_assert (reload_completed);
16368 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16369 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16371 else if (offsettable_memref_p (operand))
16373 operand = adjust_address (operand, DImode, 0);
16374 parts[0] = operand;
16375 parts[1] = adjust_address (operand, upper_mode, 8);
16377 else if (GET_CODE (operand) == CONST_DOUBLE)
16382 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16383 real_to_target (l, &r, mode);
16385 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16386 if (HOST_BITS_PER_WIDE_INT >= 64)
16389 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16390 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16393 parts[0] = immed_double_const (l[0], l[1], DImode);
16395 if (upper_mode == SImode)
16396 parts[1] = gen_int_mode (l[2], SImode);
16397 else if (HOST_BITS_PER_WIDE_INT >= 64)
16400 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16401 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16404 parts[1] = immed_double_const (l[2], l[3], DImode);
16407 gcc_unreachable ();
16414 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16415 Return false when normal moves are needed; true when all required
16416 insns have been emitted. Operands 2-4 contain the input values
16417 int the correct order; operands 5-7 contain the output values. */
16420 ix86_split_long_move (rtx operands[])
16425 int collisions = 0;
16426 enum machine_mode mode = GET_MODE (operands[0]);
16427 bool collisionparts[4];
16429 /* The DFmode expanders may ask us to move double.
16430 For 64bit target this is single move. By hiding the fact
16431 here we simplify i386.md splitters. */
16432 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16434 /* Optimize constant pool reference to immediates. This is used by
16435 fp moves, that force all constants to memory to allow combining. */
16437 if (MEM_P (operands[1])
16438 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16439 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16440 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16441 if (push_operand (operands[0], VOIDmode))
16443 operands[0] = copy_rtx (operands[0]);
16444 PUT_MODE (operands[0], Pmode);
16447 operands[0] = gen_lowpart (DImode, operands[0]);
16448 operands[1] = gen_lowpart (DImode, operands[1]);
16449 emit_move_insn (operands[0], operands[1]);
16453 /* The only non-offsettable memory we handle is push. */
16454 if (push_operand (operands[0], VOIDmode))
16457 gcc_assert (!MEM_P (operands[0])
16458 || offsettable_memref_p (operands[0]));
16460 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16461 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16463 /* When emitting push, take care for source operands on the stack. */
16464 if (push && MEM_P (operands[1])
16465 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16467 rtx src_base = XEXP (part[1][nparts - 1], 0);
16469 /* Compensate for the stack decrement by 4. */
16470 if (!TARGET_64BIT && nparts == 3
16471 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16472 src_base = plus_constant (src_base, 4);
16474 /* src_base refers to the stack pointer and is
16475 automatically decreased by emitted push. */
16476 for (i = 0; i < nparts; i++)
16477 part[1][i] = change_address (part[1][i],
16478 GET_MODE (part[1][i]), src_base);
16481 /* We need to do copy in the right order in case an address register
16482 of the source overlaps the destination. */
16483 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16487 for (i = 0; i < nparts; i++)
16490 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16491 if (collisionparts[i])
16495 /* Collision in the middle part can be handled by reordering. */
16496 if (collisions == 1 && nparts == 3 && collisionparts [1])
16498 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16499 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16501 else if (collisions == 1
16503 && (collisionparts [1] || collisionparts [2]))
16505 if (collisionparts [1])
16507 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16508 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16512 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16513 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16517 /* If there are more collisions, we can't handle it by reordering.
16518 Do an lea to the last part and use only one colliding move. */
16519 else if (collisions > 1)
16525 base = part[0][nparts - 1];
16527 /* Handle the case when the last part isn't valid for lea.
16528 Happens in 64-bit mode storing the 12-byte XFmode. */
16529 if (GET_MODE (base) != Pmode)
16530 base = gen_rtx_REG (Pmode, REGNO (base));
16532 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16533 part[1][0] = replace_equiv_address (part[1][0], base);
16534 for (i = 1; i < nparts; i++)
16536 tmp = plus_constant (base, UNITS_PER_WORD * i);
16537 part[1][i] = replace_equiv_address (part[1][i], tmp);
16548 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16549 emit_insn (gen_addsi3 (stack_pointer_rtx,
16550 stack_pointer_rtx, GEN_INT (-4)));
16551 emit_move_insn (part[0][2], part[1][2]);
16553 else if (nparts == 4)
16555 emit_move_insn (part[0][3], part[1][3]);
16556 emit_move_insn (part[0][2], part[1][2]);
16561 /* In 64bit mode we don't have 32bit push available. In case this is
16562 register, it is OK - we will just use larger counterpart. We also
16563 retype memory - these comes from attempt to avoid REX prefix on
16564 moving of second half of TFmode value. */
16565 if (GET_MODE (part[1][1]) == SImode)
16567 switch (GET_CODE (part[1][1]))
16570 part[1][1] = adjust_address (part[1][1], DImode, 0);
16574 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16578 gcc_unreachable ();
16581 if (GET_MODE (part[1][0]) == SImode)
16582 part[1][0] = part[1][1];
16585 emit_move_insn (part[0][1], part[1][1]);
16586 emit_move_insn (part[0][0], part[1][0]);
16590 /* Choose correct order to not overwrite the source before it is copied. */
16591 if ((REG_P (part[0][0])
16592 && REG_P (part[1][1])
16593 && (REGNO (part[0][0]) == REGNO (part[1][1])
16595 && REGNO (part[0][0]) == REGNO (part[1][2]))
16597 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16599 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16601 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16603 operands[2 + i] = part[0][j];
16604 operands[6 + i] = part[1][j];
16609 for (i = 0; i < nparts; i++)
16611 operands[2 + i] = part[0][i];
16612 operands[6 + i] = part[1][i];
16616 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16617 if (optimize_insn_for_size_p ())
16619 for (j = 0; j < nparts - 1; j++)
16620 if (CONST_INT_P (operands[6 + j])
16621 && operands[6 + j] != const0_rtx
16622 && REG_P (operands[2 + j]))
16623 for (i = j; i < nparts - 1; i++)
16624 if (CONST_INT_P (operands[7 + i])
16625 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16626 operands[7 + i] = operands[2 + j];
16629 for (i = 0; i < nparts; i++)
16630 emit_move_insn (operands[2 + i], operands[6 + i]);
16635 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16636 left shift by a constant, either using a single shift or
16637 a sequence of add instructions. */
16640 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16644 emit_insn ((mode == DImode
16646 : gen_adddi3) (operand, operand, operand));
16648 else if (!optimize_insn_for_size_p ()
16649 && count * ix86_cost->add <= ix86_cost->shift_const)
16652 for (i=0; i<count; i++)
16654 emit_insn ((mode == DImode
16656 : gen_adddi3) (operand, operand, operand));
16660 emit_insn ((mode == DImode
16662 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16666 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16668 rtx low[2], high[2];
16670 const int single_width = mode == DImode ? 32 : 64;
16672 if (CONST_INT_P (operands[2]))
16674 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16675 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16677 if (count >= single_width)
16679 emit_move_insn (high[0], low[1]);
16680 emit_move_insn (low[0], const0_rtx);
16682 if (count > single_width)
16683 ix86_expand_ashl_const (high[0], count - single_width, mode);
16687 if (!rtx_equal_p (operands[0], operands[1]))
16688 emit_move_insn (operands[0], operands[1]);
16689 emit_insn ((mode == DImode
16691 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16692 ix86_expand_ashl_const (low[0], count, mode);
16697 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16699 if (operands[1] == const1_rtx)
16701 /* Assuming we've chosen a QImode capable registers, then 1 << N
16702 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16703 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16705 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16707 ix86_expand_clear (low[0]);
16708 ix86_expand_clear (high[0]);
16709 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16711 d = gen_lowpart (QImode, low[0]);
16712 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16713 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16714 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16716 d = gen_lowpart (QImode, high[0]);
16717 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16718 s = gen_rtx_NE (QImode, flags, const0_rtx);
16719 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16722 /* Otherwise, we can get the same results by manually performing
16723 a bit extract operation on bit 5/6, and then performing the two
16724 shifts. The two methods of getting 0/1 into low/high are exactly
16725 the same size. Avoiding the shift in the bit extract case helps
16726 pentium4 a bit; no one else seems to care much either way. */
16731 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16732 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16734 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16735 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16737 emit_insn ((mode == DImode
16739 : gen_lshrdi3) (high[0], high[0],
16740 GEN_INT (mode == DImode ? 5 : 6)));
16741 emit_insn ((mode == DImode
16743 : gen_anddi3) (high[0], high[0], const1_rtx));
16744 emit_move_insn (low[0], high[0]);
16745 emit_insn ((mode == DImode
16747 : gen_xordi3) (low[0], low[0], const1_rtx));
16750 emit_insn ((mode == DImode
16752 : gen_ashldi3) (low[0], low[0], operands[2]));
16753 emit_insn ((mode == DImode
16755 : gen_ashldi3) (high[0], high[0], operands[2]));
16759 if (operands[1] == constm1_rtx)
16761 /* For -1 << N, we can avoid the shld instruction, because we
16762 know that we're shifting 0...31/63 ones into a -1. */
16763 emit_move_insn (low[0], constm1_rtx);
16764 if (optimize_insn_for_size_p ())
16765 emit_move_insn (high[0], low[0]);
16767 emit_move_insn (high[0], constm1_rtx);
16771 if (!rtx_equal_p (operands[0], operands[1]))
16772 emit_move_insn (operands[0], operands[1]);
16774 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16775 emit_insn ((mode == DImode
16777 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16780 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16782 if (TARGET_CMOVE && scratch)
16784 ix86_expand_clear (scratch);
16785 emit_insn ((mode == DImode
16786 ? gen_x86_shift_adj_1
16787 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16791 emit_insn ((mode == DImode
16792 ? gen_x86_shift_adj_2
16793 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16797 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16799 rtx low[2], high[2];
16801 const int single_width = mode == DImode ? 32 : 64;
16803 if (CONST_INT_P (operands[2]))
16805 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16806 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16808 if (count == single_width * 2 - 1)
16810 emit_move_insn (high[0], high[1]);
16811 emit_insn ((mode == DImode
16813 : gen_ashrdi3) (high[0], high[0],
16814 GEN_INT (single_width - 1)));
16815 emit_move_insn (low[0], high[0]);
16818 else if (count >= single_width)
16820 emit_move_insn (low[0], high[1]);
16821 emit_move_insn (high[0], low[0]);
16822 emit_insn ((mode == DImode
16824 : gen_ashrdi3) (high[0], high[0],
16825 GEN_INT (single_width - 1)));
16826 if (count > single_width)
16827 emit_insn ((mode == DImode
16829 : gen_ashrdi3) (low[0], low[0],
16830 GEN_INT (count - single_width)));
16834 if (!rtx_equal_p (operands[0], operands[1]))
16835 emit_move_insn (operands[0], operands[1]);
16836 emit_insn ((mode == DImode
16838 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16839 emit_insn ((mode == DImode
16841 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16846 if (!rtx_equal_p (operands[0], operands[1]))
16847 emit_move_insn (operands[0], operands[1]);
16849 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16851 emit_insn ((mode == DImode
16853 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16854 emit_insn ((mode == DImode
16856 : gen_ashrdi3) (high[0], high[0], operands[2]));
16858 if (TARGET_CMOVE && scratch)
16860 emit_move_insn (scratch, high[0]);
16861 emit_insn ((mode == DImode
16863 : gen_ashrdi3) (scratch, scratch,
16864 GEN_INT (single_width - 1)));
16865 emit_insn ((mode == DImode
16866 ? gen_x86_shift_adj_1
16867 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16871 emit_insn ((mode == DImode
16872 ? gen_x86_shift_adj_3
16873 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16878 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16880 rtx low[2], high[2];
16882 const int single_width = mode == DImode ? 32 : 64;
16884 if (CONST_INT_P (operands[2]))
16886 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16887 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16889 if (count >= single_width)
16891 emit_move_insn (low[0], high[1]);
16892 ix86_expand_clear (high[0]);
16894 if (count > single_width)
16895 emit_insn ((mode == DImode
16897 : gen_lshrdi3) (low[0], low[0],
16898 GEN_INT (count - single_width)));
16902 if (!rtx_equal_p (operands[0], operands[1]))
16903 emit_move_insn (operands[0], operands[1]);
16904 emit_insn ((mode == DImode
16906 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16907 emit_insn ((mode == DImode
16909 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16914 if (!rtx_equal_p (operands[0], operands[1]))
16915 emit_move_insn (operands[0], operands[1]);
16917 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16919 emit_insn ((mode == DImode
16921 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16922 emit_insn ((mode == DImode
16924 : gen_lshrdi3) (high[0], high[0], operands[2]));
16926 /* Heh. By reversing the arguments, we can reuse this pattern. */
16927 if (TARGET_CMOVE && scratch)
16929 ix86_expand_clear (scratch);
16930 emit_insn ((mode == DImode
16931 ? gen_x86_shift_adj_1
16932 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16936 emit_insn ((mode == DImode
16937 ? gen_x86_shift_adj_2
16938 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16942 /* Predict just emitted jump instruction to be taken with probability PROB. */
16944 predict_jump (int prob)
16946 rtx insn = get_last_insn ();
16947 gcc_assert (JUMP_P (insn));
16948 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
16951 /* Helper function for the string operations below. Dest VARIABLE whether
16952 it is aligned to VALUE bytes. If true, jump to the label. */
16954 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16956 rtx label = gen_label_rtx ();
16957 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16958 if (GET_MODE (variable) == DImode)
16959 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16961 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16962 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16965 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16967 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16971 /* Adjust COUNTER by the VALUE. */
16973 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16975 if (GET_MODE (countreg) == DImode)
16976 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16978 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16981 /* Zero extend possibly SImode EXP to Pmode register. */
16983 ix86_zero_extend_to_Pmode (rtx exp)
16986 if (GET_MODE (exp) == VOIDmode)
16987 return force_reg (Pmode, exp);
16988 if (GET_MODE (exp) == Pmode)
16989 return copy_to_mode_reg (Pmode, exp);
16990 r = gen_reg_rtx (Pmode);
16991 emit_insn (gen_zero_extendsidi2 (r, exp));
16995 /* Divide COUNTREG by SCALE. */
16997 scale_counter (rtx countreg, int scale)
17003 if (CONST_INT_P (countreg))
17004 return GEN_INT (INTVAL (countreg) / scale);
17005 gcc_assert (REG_P (countreg));
17007 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17008 GEN_INT (exact_log2 (scale)),
17009 NULL, 1, OPTAB_DIRECT);
17013 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17014 DImode for constant loop counts. */
17016 static enum machine_mode
17017 counter_mode (rtx count_exp)
17019 if (GET_MODE (count_exp) != VOIDmode)
17020 return GET_MODE (count_exp);
17021 if (!CONST_INT_P (count_exp))
17023 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17028 /* When SRCPTR is non-NULL, output simple loop to move memory
17029 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17030 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17031 equivalent loop to set memory by VALUE (supposed to be in MODE).
17033 The size is rounded down to whole number of chunk size moved at once.
17034 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17038 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17039 rtx destptr, rtx srcptr, rtx value,
17040 rtx count, enum machine_mode mode, int unroll,
17043 rtx out_label, top_label, iter, tmp;
17044 enum machine_mode iter_mode = counter_mode (count);
17045 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17046 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17052 top_label = gen_label_rtx ();
17053 out_label = gen_label_rtx ();
17054 iter = gen_reg_rtx (iter_mode);
17056 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17057 NULL, 1, OPTAB_DIRECT);
17058 /* Those two should combine. */
17059 if (piece_size == const1_rtx)
17061 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17063 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17065 emit_move_insn (iter, const0_rtx);
17067 emit_label (top_label);
17069 tmp = convert_modes (Pmode, iter_mode, iter, true);
17070 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17071 destmem = change_address (destmem, mode, x_addr);
17075 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17076 srcmem = change_address (srcmem, mode, y_addr);
17078 /* When unrolling for chips that reorder memory reads and writes,
17079 we can save registers by using single temporary.
17080 Also using 4 temporaries is overkill in 32bit mode. */
17081 if (!TARGET_64BIT && 0)
17083 for (i = 0; i < unroll; i++)
17088 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17090 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17092 emit_move_insn (destmem, srcmem);
17098 gcc_assert (unroll <= 4);
17099 for (i = 0; i < unroll; i++)
17101 tmpreg[i] = gen_reg_rtx (mode);
17105 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17107 emit_move_insn (tmpreg[i], srcmem);
17109 for (i = 0; i < unroll; i++)
17114 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17116 emit_move_insn (destmem, tmpreg[i]);
17121 for (i = 0; i < unroll; i++)
17125 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17126 emit_move_insn (destmem, value);
17129 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17130 true, OPTAB_LIB_WIDEN);
17132 emit_move_insn (iter, tmp);
17134 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17136 if (expected_size != -1)
17138 expected_size /= GET_MODE_SIZE (mode) * unroll;
17139 if (expected_size == 0)
17141 else if (expected_size > REG_BR_PROB_BASE)
17142 predict_jump (REG_BR_PROB_BASE - 1);
17144 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17147 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17148 iter = ix86_zero_extend_to_Pmode (iter);
17149 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17150 true, OPTAB_LIB_WIDEN);
17151 if (tmp != destptr)
17152 emit_move_insn (destptr, tmp);
17155 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17156 true, OPTAB_LIB_WIDEN);
17158 emit_move_insn (srcptr, tmp);
17160 emit_label (out_label);
17163 /* Output "rep; mov" instruction.
17164 Arguments have same meaning as for previous function */
17166 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17167 rtx destptr, rtx srcptr,
17169 enum machine_mode mode)
17175 /* If the size is known, it is shorter to use rep movs. */
17176 if (mode == QImode && CONST_INT_P (count)
17177 && !(INTVAL (count) & 3))
17180 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17181 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17182 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17183 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17184 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17185 if (mode != QImode)
17187 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17188 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17189 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17190 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17191 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17192 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17196 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17197 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17199 if (CONST_INT_P (count))
17201 count = GEN_INT (INTVAL (count)
17202 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17203 destmem = shallow_copy_rtx (destmem);
17204 srcmem = shallow_copy_rtx (srcmem);
17205 set_mem_size (destmem, count);
17206 set_mem_size (srcmem, count);
17210 if (MEM_SIZE (destmem))
17211 set_mem_size (destmem, NULL_RTX);
17212 if (MEM_SIZE (srcmem))
17213 set_mem_size (srcmem, NULL_RTX);
17215 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17219 /* Output "rep; stos" instruction.
17220 Arguments have same meaning as for previous function */
17222 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17223 rtx count, enum machine_mode mode,
17229 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17230 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17231 value = force_reg (mode, gen_lowpart (mode, value));
17232 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17233 if (mode != QImode)
17235 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17236 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17237 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17240 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17241 if (orig_value == const0_rtx && CONST_INT_P (count))
17243 count = GEN_INT (INTVAL (count)
17244 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17245 destmem = shallow_copy_rtx (destmem);
17246 set_mem_size (destmem, count);
17248 else if (MEM_SIZE (destmem))
17249 set_mem_size (destmem, NULL_RTX);
17250 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17254 emit_strmov (rtx destmem, rtx srcmem,
17255 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17257 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17258 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17259 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17262 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17264 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17265 rtx destptr, rtx srcptr, rtx count, int max_size)
17268 if (CONST_INT_P (count))
17270 HOST_WIDE_INT countval = INTVAL (count);
17273 if ((countval & 0x10) && max_size > 16)
17277 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17278 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17281 gcc_unreachable ();
17284 if ((countval & 0x08) && max_size > 8)
17287 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17290 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17291 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17295 if ((countval & 0x04) && max_size > 4)
17297 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17300 if ((countval & 0x02) && max_size > 2)
17302 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17305 if ((countval & 0x01) && max_size > 1)
17307 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17314 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17315 count, 1, OPTAB_DIRECT);
17316 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17317 count, QImode, 1, 4);
17321 /* When there are stringops, we can cheaply increase dest and src pointers.
17322 Otherwise we save code size by maintaining offset (zero is readily
17323 available from preceding rep operation) and using x86 addressing modes.
17325 if (TARGET_SINGLE_STRINGOP)
17329 rtx label = ix86_expand_aligntest (count, 4, true);
17330 src = change_address (srcmem, SImode, srcptr);
17331 dest = change_address (destmem, SImode, destptr);
17332 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17333 emit_label (label);
17334 LABEL_NUSES (label) = 1;
17338 rtx label = ix86_expand_aligntest (count, 2, true);
17339 src = change_address (srcmem, HImode, srcptr);
17340 dest = change_address (destmem, HImode, destptr);
17341 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17342 emit_label (label);
17343 LABEL_NUSES (label) = 1;
17347 rtx label = ix86_expand_aligntest (count, 1, true);
17348 src = change_address (srcmem, QImode, srcptr);
17349 dest = change_address (destmem, QImode, destptr);
17350 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17351 emit_label (label);
17352 LABEL_NUSES (label) = 1;
17357 rtx offset = force_reg (Pmode, const0_rtx);
17362 rtx label = ix86_expand_aligntest (count, 4, true);
17363 src = change_address (srcmem, SImode, srcptr);
17364 dest = change_address (destmem, SImode, destptr);
17365 emit_move_insn (dest, src);
17366 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17367 true, OPTAB_LIB_WIDEN);
17369 emit_move_insn (offset, tmp);
17370 emit_label (label);
17371 LABEL_NUSES (label) = 1;
17375 rtx label = ix86_expand_aligntest (count, 2, true);
17376 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17377 src = change_address (srcmem, HImode, tmp);
17378 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17379 dest = change_address (destmem, HImode, tmp);
17380 emit_move_insn (dest, src);
17381 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17382 true, OPTAB_LIB_WIDEN);
17384 emit_move_insn (offset, tmp);
17385 emit_label (label);
17386 LABEL_NUSES (label) = 1;
17390 rtx label = ix86_expand_aligntest (count, 1, true);
17391 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17392 src = change_address (srcmem, QImode, tmp);
17393 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17394 dest = change_address (destmem, QImode, tmp);
17395 emit_move_insn (dest, src);
17396 emit_label (label);
17397 LABEL_NUSES (label) = 1;
17402 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17404 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17405 rtx count, int max_size)
17408 expand_simple_binop (counter_mode (count), AND, count,
17409 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17410 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17411 gen_lowpart (QImode, value), count, QImode,
17415 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17417 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17421 if (CONST_INT_P (count))
17423 HOST_WIDE_INT countval = INTVAL (count);
17426 if ((countval & 0x10) && max_size > 16)
17430 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17431 emit_insn (gen_strset (destptr, dest, value));
17432 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17433 emit_insn (gen_strset (destptr, dest, value));
17436 gcc_unreachable ();
17439 if ((countval & 0x08) && max_size > 8)
17443 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17444 emit_insn (gen_strset (destptr, dest, value));
17448 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17449 emit_insn (gen_strset (destptr, dest, value));
17450 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17451 emit_insn (gen_strset (destptr, dest, value));
17455 if ((countval & 0x04) && max_size > 4)
17457 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17458 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17461 if ((countval & 0x02) && max_size > 2)
17463 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17464 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17467 if ((countval & 0x01) && max_size > 1)
17469 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17470 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17477 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17482 rtx label = ix86_expand_aligntest (count, 16, true);
17485 dest = change_address (destmem, DImode, destptr);
17486 emit_insn (gen_strset (destptr, dest, value));
17487 emit_insn (gen_strset (destptr, dest, value));
17491 dest = change_address (destmem, SImode, destptr);
17492 emit_insn (gen_strset (destptr, dest, value));
17493 emit_insn (gen_strset (destptr, dest, value));
17494 emit_insn (gen_strset (destptr, dest, value));
17495 emit_insn (gen_strset (destptr, dest, value));
17497 emit_label (label);
17498 LABEL_NUSES (label) = 1;
17502 rtx label = ix86_expand_aligntest (count, 8, true);
17505 dest = change_address (destmem, DImode, destptr);
17506 emit_insn (gen_strset (destptr, dest, value));
17510 dest = change_address (destmem, SImode, destptr);
17511 emit_insn (gen_strset (destptr, dest, value));
17512 emit_insn (gen_strset (destptr, dest, value));
17514 emit_label (label);
17515 LABEL_NUSES (label) = 1;
17519 rtx label = ix86_expand_aligntest (count, 4, true);
17520 dest = change_address (destmem, SImode, destptr);
17521 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17522 emit_label (label);
17523 LABEL_NUSES (label) = 1;
17527 rtx label = ix86_expand_aligntest (count, 2, true);
17528 dest = change_address (destmem, HImode, destptr);
17529 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17530 emit_label (label);
17531 LABEL_NUSES (label) = 1;
17535 rtx label = ix86_expand_aligntest (count, 1, true);
17536 dest = change_address (destmem, QImode, destptr);
17537 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17538 emit_label (label);
17539 LABEL_NUSES (label) = 1;
17543 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17544 DESIRED_ALIGNMENT. */
17546 expand_movmem_prologue (rtx destmem, rtx srcmem,
17547 rtx destptr, rtx srcptr, rtx count,
17548 int align, int desired_alignment)
17550 if (align <= 1 && desired_alignment > 1)
17552 rtx label = ix86_expand_aligntest (destptr, 1, false);
17553 srcmem = change_address (srcmem, QImode, srcptr);
17554 destmem = change_address (destmem, QImode, destptr);
17555 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17556 ix86_adjust_counter (count, 1);
17557 emit_label (label);
17558 LABEL_NUSES (label) = 1;
17560 if (align <= 2 && desired_alignment > 2)
17562 rtx label = ix86_expand_aligntest (destptr, 2, false);
17563 srcmem = change_address (srcmem, HImode, srcptr);
17564 destmem = change_address (destmem, HImode, destptr);
17565 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17566 ix86_adjust_counter (count, 2);
17567 emit_label (label);
17568 LABEL_NUSES (label) = 1;
17570 if (align <= 4 && desired_alignment > 4)
17572 rtx label = ix86_expand_aligntest (destptr, 4, false);
17573 srcmem = change_address (srcmem, SImode, srcptr);
17574 destmem = change_address (destmem, SImode, destptr);
17575 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17576 ix86_adjust_counter (count, 4);
17577 emit_label (label);
17578 LABEL_NUSES (label) = 1;
17580 gcc_assert (desired_alignment <= 8);
17583 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17584 ALIGN_BYTES is how many bytes need to be copied. */
17586 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17587 int desired_align, int align_bytes)
17590 rtx src_size, dst_size;
17592 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17593 if (src_align_bytes >= 0)
17594 src_align_bytes = desired_align - src_align_bytes;
17595 src_size = MEM_SIZE (src);
17596 dst_size = MEM_SIZE (dst);
17597 if (align_bytes & 1)
17599 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17600 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17602 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17604 if (align_bytes & 2)
17606 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17607 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17608 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17609 set_mem_align (dst, 2 * BITS_PER_UNIT);
17610 if (src_align_bytes >= 0
17611 && (src_align_bytes & 1) == (align_bytes & 1)
17612 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17613 set_mem_align (src, 2 * BITS_PER_UNIT);
17615 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17617 if (align_bytes & 4)
17619 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17620 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17621 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17622 set_mem_align (dst, 4 * BITS_PER_UNIT);
17623 if (src_align_bytes >= 0)
17625 unsigned int src_align = 0;
17626 if ((src_align_bytes & 3) == (align_bytes & 3))
17628 else if ((src_align_bytes & 1) == (align_bytes & 1))
17630 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17631 set_mem_align (src, src_align * BITS_PER_UNIT);
17634 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17636 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17637 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17638 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17639 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17640 if (src_align_bytes >= 0)
17642 unsigned int src_align = 0;
17643 if ((src_align_bytes & 7) == (align_bytes & 7))
17645 else if ((src_align_bytes & 3) == (align_bytes & 3))
17647 else if ((src_align_bytes & 1) == (align_bytes & 1))
17649 if (src_align > (unsigned int) desired_align)
17650 src_align = desired_align;
17651 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17652 set_mem_align (src, src_align * BITS_PER_UNIT);
17655 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17657 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17662 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17663 DESIRED_ALIGNMENT. */
17665 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17666 int align, int desired_alignment)
17668 if (align <= 1 && desired_alignment > 1)
17670 rtx label = ix86_expand_aligntest (destptr, 1, false);
17671 destmem = change_address (destmem, QImode, destptr);
17672 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17673 ix86_adjust_counter (count, 1);
17674 emit_label (label);
17675 LABEL_NUSES (label) = 1;
17677 if (align <= 2 && desired_alignment > 2)
17679 rtx label = ix86_expand_aligntest (destptr, 2, false);
17680 destmem = change_address (destmem, HImode, destptr);
17681 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17682 ix86_adjust_counter (count, 2);
17683 emit_label (label);
17684 LABEL_NUSES (label) = 1;
17686 if (align <= 4 && desired_alignment > 4)
17688 rtx label = ix86_expand_aligntest (destptr, 4, false);
17689 destmem = change_address (destmem, SImode, destptr);
17690 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17691 ix86_adjust_counter (count, 4);
17692 emit_label (label);
17693 LABEL_NUSES (label) = 1;
17695 gcc_assert (desired_alignment <= 8);
17698 /* Set enough from DST to align DST known to by aligned by ALIGN to
17699 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17701 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17702 int desired_align, int align_bytes)
17705 rtx dst_size = MEM_SIZE (dst);
17706 if (align_bytes & 1)
17708 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17710 emit_insn (gen_strset (destreg, dst,
17711 gen_lowpart (QImode, value)));
17713 if (align_bytes & 2)
17715 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17716 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17717 set_mem_align (dst, 2 * BITS_PER_UNIT);
17719 emit_insn (gen_strset (destreg, dst,
17720 gen_lowpart (HImode, value)));
17722 if (align_bytes & 4)
17724 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17725 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17726 set_mem_align (dst, 4 * BITS_PER_UNIT);
17728 emit_insn (gen_strset (destreg, dst,
17729 gen_lowpart (SImode, value)));
17731 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17732 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17733 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17735 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17739 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17740 static enum stringop_alg
17741 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17742 int *dynamic_check)
17744 const struct stringop_algs * algs;
17745 bool optimize_for_speed;
17746 /* Algorithms using the rep prefix want at least edi and ecx;
17747 additionally, memset wants eax and memcpy wants esi. Don't
17748 consider such algorithms if the user has appropriated those
17749 registers for their own purposes. */
17750 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17752 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17754 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17755 || (alg != rep_prefix_1_byte \
17756 && alg != rep_prefix_4_byte \
17757 && alg != rep_prefix_8_byte))
17758 const struct processor_costs *cost;
17760 /* Even if the string operation call is cold, we still might spend a lot
17761 of time processing large blocks. */
17762 if (optimize_function_for_size_p (cfun)
17763 || (optimize_insn_for_size_p ()
17764 && expected_size != -1 && expected_size < 256))
17765 optimize_for_speed = false;
17767 optimize_for_speed = true;
17769 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17771 *dynamic_check = -1;
17773 algs = &cost->memset[TARGET_64BIT != 0];
17775 algs = &cost->memcpy[TARGET_64BIT != 0];
17776 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17777 return stringop_alg;
17778 /* rep; movq or rep; movl is the smallest variant. */
17779 else if (!optimize_for_speed)
17781 if (!count || (count & 3))
17782 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17784 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17786 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17788 else if (expected_size != -1 && expected_size < 4)
17789 return loop_1_byte;
17790 else if (expected_size != -1)
17793 enum stringop_alg alg = libcall;
17794 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17796 /* We get here if the algorithms that were not libcall-based
17797 were rep-prefix based and we are unable to use rep prefixes
17798 based on global register usage. Break out of the loop and
17799 use the heuristic below. */
17800 if (algs->size[i].max == 0)
17802 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17804 enum stringop_alg candidate = algs->size[i].alg;
17806 if (candidate != libcall && ALG_USABLE_P (candidate))
17808 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17809 last non-libcall inline algorithm. */
17810 if (TARGET_INLINE_ALL_STRINGOPS)
17812 /* When the current size is best to be copied by a libcall,
17813 but we are still forced to inline, run the heuristic below
17814 that will pick code for medium sized blocks. */
17815 if (alg != libcall)
17819 else if (ALG_USABLE_P (candidate))
17823 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17825 /* When asked to inline the call anyway, try to pick meaningful choice.
17826 We look for maximal size of block that is faster to copy by hand and
17827 take blocks of at most of that size guessing that average size will
17828 be roughly half of the block.
17830 If this turns out to be bad, we might simply specify the preferred
17831 choice in ix86_costs. */
17832 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17833 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17836 enum stringop_alg alg;
17838 bool any_alg_usable_p = true;
17840 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17842 enum stringop_alg candidate = algs->size[i].alg;
17843 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17845 if (candidate != libcall && candidate
17846 && ALG_USABLE_P (candidate))
17847 max = algs->size[i].max;
17849 /* If there aren't any usable algorithms, then recursing on
17850 smaller sizes isn't going to find anything. Just return the
17851 simple byte-at-a-time copy loop. */
17852 if (!any_alg_usable_p)
17854 /* Pick something reasonable. */
17855 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17856 *dynamic_check = 128;
17857 return loop_1_byte;
17861 alg = decide_alg (count, max / 2, memset, dynamic_check);
17862 gcc_assert (*dynamic_check == -1);
17863 gcc_assert (alg != libcall);
17864 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17865 *dynamic_check = max;
17868 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17869 #undef ALG_USABLE_P
17872 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17873 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17875 decide_alignment (int align,
17876 enum stringop_alg alg,
17879 int desired_align = 0;
17883 gcc_unreachable ();
17885 case unrolled_loop:
17886 desired_align = GET_MODE_SIZE (Pmode);
17888 case rep_prefix_8_byte:
17891 case rep_prefix_4_byte:
17892 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17893 copying whole cacheline at once. */
17894 if (TARGET_PENTIUMPRO)
17899 case rep_prefix_1_byte:
17900 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17901 copying whole cacheline at once. */
17902 if (TARGET_PENTIUMPRO)
17916 if (desired_align < align)
17917 desired_align = align;
17918 if (expected_size != -1 && expected_size < 4)
17919 desired_align = align;
17920 return desired_align;
17923 /* Return the smallest power of 2 greater than VAL. */
17925 smallest_pow2_greater_than (int val)
17933 /* Expand string move (memcpy) operation. Use i386 string operations when
17934 profitable. expand_setmem contains similar code. The code depends upon
17935 architecture, block size and alignment, but always has the same
17938 1) Prologue guard: Conditional that jumps up to epilogues for small
17939 blocks that can be handled by epilogue alone. This is faster but
17940 also needed for correctness, since prologue assume the block is larger
17941 than the desired alignment.
17943 Optional dynamic check for size and libcall for large
17944 blocks is emitted here too, with -minline-stringops-dynamically.
17946 2) Prologue: copy first few bytes in order to get destination aligned
17947 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17948 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17949 We emit either a jump tree on power of two sized blocks, or a byte loop.
17951 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17952 with specified algorithm.
17954 4) Epilogue: code copying tail of the block that is too small to be
17955 handled by main body (or up to size guarded by prologue guard). */
17958 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17959 rtx expected_align_exp, rtx expected_size_exp)
17965 rtx jump_around_label = NULL;
17966 HOST_WIDE_INT align = 1;
17967 unsigned HOST_WIDE_INT count = 0;
17968 HOST_WIDE_INT expected_size = -1;
17969 int size_needed = 0, epilogue_size_needed;
17970 int desired_align = 0, align_bytes = 0;
17971 enum stringop_alg alg;
17973 bool need_zero_guard = false;
17975 if (CONST_INT_P (align_exp))
17976 align = INTVAL (align_exp);
17977 /* i386 can do misaligned access on reasonably increased cost. */
17978 if (CONST_INT_P (expected_align_exp)
17979 && INTVAL (expected_align_exp) > align)
17980 align = INTVAL (expected_align_exp);
17981 /* ALIGN is the minimum of destination and source alignment, but we care here
17982 just about destination alignment. */
17983 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17984 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17986 if (CONST_INT_P (count_exp))
17987 count = expected_size = INTVAL (count_exp);
17988 if (CONST_INT_P (expected_size_exp) && count == 0)
17989 expected_size = INTVAL (expected_size_exp);
17991 /* Make sure we don't need to care about overflow later on. */
17992 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17995 /* Step 0: Decide on preferred algorithm, desired alignment and
17996 size of chunks to be copied by main loop. */
17998 alg = decide_alg (count, expected_size, false, &dynamic_check);
17999 desired_align = decide_alignment (align, alg, expected_size);
18001 if (!TARGET_ALIGN_STRINGOPS)
18002 align = desired_align;
18004 if (alg == libcall)
18006 gcc_assert (alg != no_stringop);
18008 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18009 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18010 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18015 gcc_unreachable ();
18017 need_zero_guard = true;
18018 size_needed = GET_MODE_SIZE (Pmode);
18020 case unrolled_loop:
18021 need_zero_guard = true;
18022 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18024 case rep_prefix_8_byte:
18027 case rep_prefix_4_byte:
18030 case rep_prefix_1_byte:
18034 need_zero_guard = true;
18039 epilogue_size_needed = size_needed;
18041 /* Step 1: Prologue guard. */
18043 /* Alignment code needs count to be in register. */
18044 if (CONST_INT_P (count_exp) && desired_align > align)
18046 if (INTVAL (count_exp) > desired_align
18047 && INTVAL (count_exp) > size_needed)
18050 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18051 if (align_bytes <= 0)
18054 align_bytes = desired_align - align_bytes;
18056 if (align_bytes == 0)
18057 count_exp = force_reg (counter_mode (count_exp), count_exp);
18059 gcc_assert (desired_align >= 1 && align >= 1);
18061 /* Ensure that alignment prologue won't copy past end of block. */
18062 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18064 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18065 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18066 Make sure it is power of 2. */
18067 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18071 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18073 /* If main algorithm works on QImode, no epilogue is needed.
18074 For small sizes just don't align anything. */
18075 if (size_needed == 1)
18076 desired_align = align;
18083 label = gen_label_rtx ();
18084 emit_cmp_and_jump_insns (count_exp,
18085 GEN_INT (epilogue_size_needed),
18086 LTU, 0, counter_mode (count_exp), 1, label);
18087 if (expected_size == -1 || expected_size < epilogue_size_needed)
18088 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18090 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18094 /* Emit code to decide on runtime whether library call or inline should be
18096 if (dynamic_check != -1)
18098 if (CONST_INT_P (count_exp))
18100 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18102 emit_block_move_via_libcall (dst, src, count_exp, false);
18103 count_exp = const0_rtx;
18109 rtx hot_label = gen_label_rtx ();
18110 jump_around_label = gen_label_rtx ();
18111 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18112 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18113 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18114 emit_block_move_via_libcall (dst, src, count_exp, false);
18115 emit_jump (jump_around_label);
18116 emit_label (hot_label);
18120 /* Step 2: Alignment prologue. */
18122 if (desired_align > align)
18124 if (align_bytes == 0)
18126 /* Except for the first move in epilogue, we no longer know
18127 constant offset in aliasing info. It don't seems to worth
18128 the pain to maintain it for the first move, so throw away
18130 src = change_address (src, BLKmode, srcreg);
18131 dst = change_address (dst, BLKmode, destreg);
18132 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18137 /* If we know how many bytes need to be stored before dst is
18138 sufficiently aligned, maintain aliasing info accurately. */
18139 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18140 desired_align, align_bytes);
18141 count_exp = plus_constant (count_exp, -align_bytes);
18142 count -= align_bytes;
18144 if (need_zero_guard
18145 && (count < (unsigned HOST_WIDE_INT) size_needed
18146 || (align_bytes == 0
18147 && count < ((unsigned HOST_WIDE_INT) size_needed
18148 + desired_align - align))))
18150 /* It is possible that we copied enough so the main loop will not
18152 gcc_assert (size_needed > 1);
18153 if (label == NULL_RTX)
18154 label = gen_label_rtx ();
18155 emit_cmp_and_jump_insns (count_exp,
18156 GEN_INT (size_needed),
18157 LTU, 0, counter_mode (count_exp), 1, label);
18158 if (expected_size == -1
18159 || expected_size < (desired_align - align) / 2 + size_needed)
18160 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18162 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18165 if (label && size_needed == 1)
18167 emit_label (label);
18168 LABEL_NUSES (label) = 1;
18170 epilogue_size_needed = 1;
18172 else if (label == NULL_RTX)
18173 epilogue_size_needed = size_needed;
18175 /* Step 3: Main loop. */
18181 gcc_unreachable ();
18183 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18184 count_exp, QImode, 1, expected_size);
18187 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18188 count_exp, Pmode, 1, expected_size);
18190 case unrolled_loop:
18191 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18192 registers for 4 temporaries anyway. */
18193 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18194 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18197 case rep_prefix_8_byte:
18198 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18201 case rep_prefix_4_byte:
18202 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18205 case rep_prefix_1_byte:
18206 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18210 /* Adjust properly the offset of src and dest memory for aliasing. */
18211 if (CONST_INT_P (count_exp))
18213 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18214 (count / size_needed) * size_needed);
18215 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18216 (count / size_needed) * size_needed);
18220 src = change_address (src, BLKmode, srcreg);
18221 dst = change_address (dst, BLKmode, destreg);
18224 /* Step 4: Epilogue to copy the remaining bytes. */
18228 /* When the main loop is done, COUNT_EXP might hold original count,
18229 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18230 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18231 bytes. Compensate if needed. */
18233 if (size_needed < epilogue_size_needed)
18236 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18237 GEN_INT (size_needed - 1), count_exp, 1,
18239 if (tmp != count_exp)
18240 emit_move_insn (count_exp, tmp);
18242 emit_label (label);
18243 LABEL_NUSES (label) = 1;
18246 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18247 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18248 epilogue_size_needed);
18249 if (jump_around_label)
18250 emit_label (jump_around_label);
18254 /* Helper function for memcpy. For QImode value 0xXY produce
18255 0xXYXYXYXY of wide specified by MODE. This is essentially
18256 a * 0x10101010, but we can do slightly better than
18257 synth_mult by unwinding the sequence by hand on CPUs with
18260 promote_duplicated_reg (enum machine_mode mode, rtx val)
18262 enum machine_mode valmode = GET_MODE (val);
18264 int nops = mode == DImode ? 3 : 2;
18266 gcc_assert (mode == SImode || mode == DImode);
18267 if (val == const0_rtx)
18268 return copy_to_mode_reg (mode, const0_rtx);
18269 if (CONST_INT_P (val))
18271 HOST_WIDE_INT v = INTVAL (val) & 255;
18275 if (mode == DImode)
18276 v |= (v << 16) << 16;
18277 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18280 if (valmode == VOIDmode)
18282 if (valmode != QImode)
18283 val = gen_lowpart (QImode, val);
18284 if (mode == QImode)
18286 if (!TARGET_PARTIAL_REG_STALL)
18288 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18289 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18290 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18291 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18293 rtx reg = convert_modes (mode, QImode, val, true);
18294 tmp = promote_duplicated_reg (mode, const1_rtx);
18295 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18300 rtx reg = convert_modes (mode, QImode, val, true);
18302 if (!TARGET_PARTIAL_REG_STALL)
18303 if (mode == SImode)
18304 emit_insn (gen_movsi_insv_1 (reg, reg));
18306 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18309 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18310 NULL, 1, OPTAB_DIRECT);
18312 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18314 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18315 NULL, 1, OPTAB_DIRECT);
18316 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18317 if (mode == SImode)
18319 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18320 NULL, 1, OPTAB_DIRECT);
18321 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18326 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18327 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18328 alignment from ALIGN to DESIRED_ALIGN. */
18330 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18335 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18336 promoted_val = promote_duplicated_reg (DImode, val);
18337 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18338 promoted_val = promote_duplicated_reg (SImode, val);
18339 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18340 promoted_val = promote_duplicated_reg (HImode, val);
18342 promoted_val = val;
18344 return promoted_val;
18347 /* Expand string clear operation (bzero). Use i386 string operations when
18348 profitable. See expand_movmem comment for explanation of individual
18349 steps performed. */
18351 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18352 rtx expected_align_exp, rtx expected_size_exp)
18357 rtx jump_around_label = NULL;
18358 HOST_WIDE_INT align = 1;
18359 unsigned HOST_WIDE_INT count = 0;
18360 HOST_WIDE_INT expected_size = -1;
18361 int size_needed = 0, epilogue_size_needed;
18362 int desired_align = 0, align_bytes = 0;
18363 enum stringop_alg alg;
18364 rtx promoted_val = NULL;
18365 bool force_loopy_epilogue = false;
18367 bool need_zero_guard = false;
18369 if (CONST_INT_P (align_exp))
18370 align = INTVAL (align_exp);
18371 /* i386 can do misaligned access on reasonably increased cost. */
18372 if (CONST_INT_P (expected_align_exp)
18373 && INTVAL (expected_align_exp) > align)
18374 align = INTVAL (expected_align_exp);
18375 if (CONST_INT_P (count_exp))
18376 count = expected_size = INTVAL (count_exp);
18377 if (CONST_INT_P (expected_size_exp) && count == 0)
18378 expected_size = INTVAL (expected_size_exp);
18380 /* Make sure we don't need to care about overflow later on. */
18381 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18384 /* Step 0: Decide on preferred algorithm, desired alignment and
18385 size of chunks to be copied by main loop. */
18387 alg = decide_alg (count, expected_size, true, &dynamic_check);
18388 desired_align = decide_alignment (align, alg, expected_size);
18390 if (!TARGET_ALIGN_STRINGOPS)
18391 align = desired_align;
18393 if (alg == libcall)
18395 gcc_assert (alg != no_stringop);
18397 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18398 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18403 gcc_unreachable ();
18405 need_zero_guard = true;
18406 size_needed = GET_MODE_SIZE (Pmode);
18408 case unrolled_loop:
18409 need_zero_guard = true;
18410 size_needed = GET_MODE_SIZE (Pmode) * 4;
18412 case rep_prefix_8_byte:
18415 case rep_prefix_4_byte:
18418 case rep_prefix_1_byte:
18422 need_zero_guard = true;
18426 epilogue_size_needed = size_needed;
18428 /* Step 1: Prologue guard. */
18430 /* Alignment code needs count to be in register. */
18431 if (CONST_INT_P (count_exp) && desired_align > align)
18433 if (INTVAL (count_exp) > desired_align
18434 && INTVAL (count_exp) > size_needed)
18437 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18438 if (align_bytes <= 0)
18441 align_bytes = desired_align - align_bytes;
18443 if (align_bytes == 0)
18445 enum machine_mode mode = SImode;
18446 if (TARGET_64BIT && (count & ~0xffffffff))
18448 count_exp = force_reg (mode, count_exp);
18451 /* Do the cheap promotion to allow better CSE across the
18452 main loop and epilogue (ie one load of the big constant in the
18453 front of all code. */
18454 if (CONST_INT_P (val_exp))
18455 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18456 desired_align, align);
18457 /* Ensure that alignment prologue won't copy past end of block. */
18458 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18460 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18461 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18462 Make sure it is power of 2. */
18463 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18465 /* To improve performance of small blocks, we jump around the VAL
18466 promoting mode. This mean that if the promoted VAL is not constant,
18467 we might not use it in the epilogue and have to use byte
18469 if (epilogue_size_needed > 2 && !promoted_val)
18470 force_loopy_epilogue = true;
18473 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18475 /* If main algorithm works on QImode, no epilogue is needed.
18476 For small sizes just don't align anything. */
18477 if (size_needed == 1)
18478 desired_align = align;
18485 label = gen_label_rtx ();
18486 emit_cmp_and_jump_insns (count_exp,
18487 GEN_INT (epilogue_size_needed),
18488 LTU, 0, counter_mode (count_exp), 1, label);
18489 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18490 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18492 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18495 if (dynamic_check != -1)
18497 rtx hot_label = gen_label_rtx ();
18498 jump_around_label = gen_label_rtx ();
18499 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18500 LEU, 0, counter_mode (count_exp), 1, hot_label);
18501 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18502 set_storage_via_libcall (dst, count_exp, val_exp, false);
18503 emit_jump (jump_around_label);
18504 emit_label (hot_label);
18507 /* Step 2: Alignment prologue. */
18509 /* Do the expensive promotion once we branched off the small blocks. */
18511 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18512 desired_align, align);
18513 gcc_assert (desired_align >= 1 && align >= 1);
18515 if (desired_align > align)
18517 if (align_bytes == 0)
18519 /* Except for the first move in epilogue, we no longer know
18520 constant offset in aliasing info. It don't seems to worth
18521 the pain to maintain it for the first move, so throw away
18523 dst = change_address (dst, BLKmode, destreg);
18524 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18529 /* If we know how many bytes need to be stored before dst is
18530 sufficiently aligned, maintain aliasing info accurately. */
18531 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18532 desired_align, align_bytes);
18533 count_exp = plus_constant (count_exp, -align_bytes);
18534 count -= align_bytes;
18536 if (need_zero_guard
18537 && (count < (unsigned HOST_WIDE_INT) size_needed
18538 || (align_bytes == 0
18539 && count < ((unsigned HOST_WIDE_INT) size_needed
18540 + desired_align - align))))
18542 /* It is possible that we copied enough so the main loop will not
18544 gcc_assert (size_needed > 1);
18545 if (label == NULL_RTX)
18546 label = gen_label_rtx ();
18547 emit_cmp_and_jump_insns (count_exp,
18548 GEN_INT (size_needed),
18549 LTU, 0, counter_mode (count_exp), 1, label);
18550 if (expected_size == -1
18551 || expected_size < (desired_align - align) / 2 + size_needed)
18552 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18554 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18557 if (label && size_needed == 1)
18559 emit_label (label);
18560 LABEL_NUSES (label) = 1;
18562 promoted_val = val_exp;
18563 epilogue_size_needed = 1;
18565 else if (label == NULL_RTX)
18566 epilogue_size_needed = size_needed;
18568 /* Step 3: Main loop. */
18574 gcc_unreachable ();
18576 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18577 count_exp, QImode, 1, expected_size);
18580 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18581 count_exp, Pmode, 1, expected_size);
18583 case unrolled_loop:
18584 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18585 count_exp, Pmode, 4, expected_size);
18587 case rep_prefix_8_byte:
18588 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18591 case rep_prefix_4_byte:
18592 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18595 case rep_prefix_1_byte:
18596 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18600 /* Adjust properly the offset of src and dest memory for aliasing. */
18601 if (CONST_INT_P (count_exp))
18602 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18603 (count / size_needed) * size_needed);
18605 dst = change_address (dst, BLKmode, destreg);
18607 /* Step 4: Epilogue to copy the remaining bytes. */
18611 /* When the main loop is done, COUNT_EXP might hold original count,
18612 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18613 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18614 bytes. Compensate if needed. */
18616 if (size_needed < epilogue_size_needed)
18619 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18620 GEN_INT (size_needed - 1), count_exp, 1,
18622 if (tmp != count_exp)
18623 emit_move_insn (count_exp, tmp);
18625 emit_label (label);
18626 LABEL_NUSES (label) = 1;
18629 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18631 if (force_loopy_epilogue)
18632 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18633 epilogue_size_needed);
18635 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18636 epilogue_size_needed);
18638 if (jump_around_label)
18639 emit_label (jump_around_label);
18643 /* Expand the appropriate insns for doing strlen if not just doing
18646 out = result, initialized with the start address
18647 align_rtx = alignment of the address.
18648 scratch = scratch register, initialized with the startaddress when
18649 not aligned, otherwise undefined
18651 This is just the body. It needs the initializations mentioned above and
18652 some address computing at the end. These things are done in i386.md. */
18655 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18659 rtx align_2_label = NULL_RTX;
18660 rtx align_3_label = NULL_RTX;
18661 rtx align_4_label = gen_label_rtx ();
18662 rtx end_0_label = gen_label_rtx ();
18664 rtx tmpreg = gen_reg_rtx (SImode);
18665 rtx scratch = gen_reg_rtx (SImode);
18669 if (CONST_INT_P (align_rtx))
18670 align = INTVAL (align_rtx);
18672 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18674 /* Is there a known alignment and is it less than 4? */
18677 rtx scratch1 = gen_reg_rtx (Pmode);
18678 emit_move_insn (scratch1, out);
18679 /* Is there a known alignment and is it not 2? */
18682 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18683 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18685 /* Leave just the 3 lower bits. */
18686 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18687 NULL_RTX, 0, OPTAB_WIDEN);
18689 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18690 Pmode, 1, align_4_label);
18691 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18692 Pmode, 1, align_2_label);
18693 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18694 Pmode, 1, align_3_label);
18698 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18699 check if is aligned to 4 - byte. */
18701 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18702 NULL_RTX, 0, OPTAB_WIDEN);
18704 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18705 Pmode, 1, align_4_label);
18708 mem = change_address (src, QImode, out);
18710 /* Now compare the bytes. */
18712 /* Compare the first n unaligned byte on a byte per byte basis. */
18713 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18714 QImode, 1, end_0_label);
18716 /* Increment the address. */
18717 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18719 /* Not needed with an alignment of 2 */
18722 emit_label (align_2_label);
18724 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18727 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18729 emit_label (align_3_label);
18732 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18735 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18738 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18739 align this loop. It gives only huge programs, but does not help to
18741 emit_label (align_4_label);
18743 mem = change_address (src, SImode, out);
18744 emit_move_insn (scratch, mem);
18745 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18747 /* This formula yields a nonzero result iff one of the bytes is zero.
18748 This saves three branches inside loop and many cycles. */
18750 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18751 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18752 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18753 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18754 gen_int_mode (0x80808080, SImode)));
18755 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18760 rtx reg = gen_reg_rtx (SImode);
18761 rtx reg2 = gen_reg_rtx (Pmode);
18762 emit_move_insn (reg, tmpreg);
18763 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18765 /* If zero is not in the first two bytes, move two bytes forward. */
18766 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18767 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18768 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18769 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18770 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18773 /* Emit lea manually to avoid clobbering of flags. */
18774 emit_insn (gen_rtx_SET (SImode, reg2,
18775 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18777 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18778 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18779 emit_insn (gen_rtx_SET (VOIDmode, out,
18780 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18787 rtx end_2_label = gen_label_rtx ();
18788 /* Is zero in the first two bytes? */
18790 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18791 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18792 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18793 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18794 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18796 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18797 JUMP_LABEL (tmp) = end_2_label;
18799 /* Not in the first two. Move two bytes forward. */
18800 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18801 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18803 emit_label (end_2_label);
18807 /* Avoid branch in fixing the byte. */
18808 tmpreg = gen_lowpart (QImode, tmpreg);
18809 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18810 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18811 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18813 emit_label (end_0_label);
18816 /* Expand strlen. */
18819 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18821 rtx addr, scratch1, scratch2, scratch3, scratch4;
18823 /* The generic case of strlen expander is long. Avoid it's
18824 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18826 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18827 && !TARGET_INLINE_ALL_STRINGOPS
18828 && !optimize_insn_for_size_p ()
18829 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18832 addr = force_reg (Pmode, XEXP (src, 0));
18833 scratch1 = gen_reg_rtx (Pmode);
18835 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18836 && !optimize_insn_for_size_p ())
18838 /* Well it seems that some optimizer does not combine a call like
18839 foo(strlen(bar), strlen(bar));
18840 when the move and the subtraction is done here. It does calculate
18841 the length just once when these instructions are done inside of
18842 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18843 often used and I use one fewer register for the lifetime of
18844 output_strlen_unroll() this is better. */
18846 emit_move_insn (out, addr);
18848 ix86_expand_strlensi_unroll_1 (out, src, align);
18850 /* strlensi_unroll_1 returns the address of the zero at the end of
18851 the string, like memchr(), so compute the length by subtracting
18852 the start address. */
18853 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18859 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18860 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18863 scratch2 = gen_reg_rtx (Pmode);
18864 scratch3 = gen_reg_rtx (Pmode);
18865 scratch4 = force_reg (Pmode, constm1_rtx);
18867 emit_move_insn (scratch3, addr);
18868 eoschar = force_reg (QImode, eoschar);
18870 src = replace_equiv_address_nv (src, scratch3);
18872 /* If .md starts supporting :P, this can be done in .md. */
18873 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18874 scratch4), UNSPEC_SCAS);
18875 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18876 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18877 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18882 /* For given symbol (function) construct code to compute address of it's PLT
18883 entry in large x86-64 PIC model. */
18885 construct_plt_address (rtx symbol)
18887 rtx tmp = gen_reg_rtx (Pmode);
18888 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18890 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18891 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18893 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18894 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18899 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18901 rtx pop, int sibcall)
18903 rtx use = NULL, call;
18905 if (pop == const0_rtx)
18907 gcc_assert (!TARGET_64BIT || !pop);
18909 if (TARGET_MACHO && !TARGET_64BIT)
18912 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18913 fnaddr = machopic_indirect_call_target (fnaddr);
18918 /* Static functions and indirect calls don't need the pic register. */
18919 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18920 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18921 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18922 use_reg (&use, pic_offset_table_rtx);
18925 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18927 rtx al = gen_rtx_REG (QImode, AX_REG);
18928 emit_move_insn (al, callarg2);
18929 use_reg (&use, al);
18932 if (ix86_cmodel == CM_LARGE_PIC
18934 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18935 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18936 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18938 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18939 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18941 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18942 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18945 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18947 call = gen_rtx_SET (VOIDmode, retval, call);
18950 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18951 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18952 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18955 && ix86_cfun_abi () == MS_ABI
18956 && (!callarg2 || INTVAL (callarg2) != -2))
18958 /* We need to represent that SI and DI registers are clobbered
18960 static int clobbered_registers[] = {
18961 XMM6_REG, XMM7_REG, XMM8_REG,
18962 XMM9_REG, XMM10_REG, XMM11_REG,
18963 XMM12_REG, XMM13_REG, XMM14_REG,
18964 XMM15_REG, SI_REG, DI_REG
18967 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18968 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18969 UNSPEC_MS_TO_SYSV_CALL);
18973 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18974 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18977 (SSE_REGNO_P (clobbered_registers[i])
18979 clobbered_registers[i]));
18981 call = gen_rtx_PARALLEL (VOIDmode,
18982 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18986 call = emit_call_insn (call);
18988 CALL_INSN_FUNCTION_USAGE (call) = use;
18992 /* Clear stack slot assignments remembered from previous functions.
18993 This is called from INIT_EXPANDERS once before RTL is emitted for each
18996 static struct machine_function *
18997 ix86_init_machine_status (void)
18999 struct machine_function *f;
19001 f = GGC_CNEW (struct machine_function);
19002 f->use_fast_prologue_epilogue_nregs = -1;
19003 f->tls_descriptor_call_expanded_p = 0;
19004 f->call_abi = ix86_abi;
19009 /* Return a MEM corresponding to a stack slot with mode MODE.
19010 Allocate a new slot if necessary.
19012 The RTL for a function can have several slots available: N is
19013 which slot to use. */
19016 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19018 struct stack_local_entry *s;
19020 gcc_assert (n < MAX_386_STACK_LOCALS);
19022 /* Virtual slot is valid only before vregs are instantiated. */
19023 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19025 for (s = ix86_stack_locals; s; s = s->next)
19026 if (s->mode == mode && s->n == n)
19027 return copy_rtx (s->rtl);
19029 s = (struct stack_local_entry *)
19030 ggc_alloc (sizeof (struct stack_local_entry));
19033 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19035 s->next = ix86_stack_locals;
19036 ix86_stack_locals = s;
19040 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19042 static GTY(()) rtx ix86_tls_symbol;
19044 ix86_tls_get_addr (void)
19047 if (!ix86_tls_symbol)
19049 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19050 (TARGET_ANY_GNU_TLS
19052 ? "___tls_get_addr"
19053 : "__tls_get_addr");
19056 return ix86_tls_symbol;
19059 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19061 static GTY(()) rtx ix86_tls_module_base_symbol;
19063 ix86_tls_module_base (void)
19066 if (!ix86_tls_module_base_symbol)
19068 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19069 "_TLS_MODULE_BASE_");
19070 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19071 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19074 return ix86_tls_module_base_symbol;
19077 /* Calculate the length of the memory address in the instruction
19078 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19081 memory_address_length (rtx addr)
19083 struct ix86_address parts;
19084 rtx base, index, disp;
19088 if (GET_CODE (addr) == PRE_DEC
19089 || GET_CODE (addr) == POST_INC
19090 || GET_CODE (addr) == PRE_MODIFY
19091 || GET_CODE (addr) == POST_MODIFY)
19094 ok = ix86_decompose_address (addr, &parts);
19097 if (parts.base && GET_CODE (parts.base) == SUBREG)
19098 parts.base = SUBREG_REG (parts.base);
19099 if (parts.index && GET_CODE (parts.index) == SUBREG)
19100 parts.index = SUBREG_REG (parts.index);
19103 index = parts.index;
19108 - esp as the base always wants an index,
19109 - ebp as the base always wants a displacement,
19110 - r12 as the base always wants an index,
19111 - r13 as the base always wants a displacement. */
19113 /* Register Indirect. */
19114 if (base && !index && !disp)
19116 /* esp (for its index) and ebp (for its displacement) need
19117 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19120 && (addr == arg_pointer_rtx
19121 || addr == frame_pointer_rtx
19122 || REGNO (addr) == SP_REG
19123 || REGNO (addr) == BP_REG
19124 || REGNO (addr) == R12_REG
19125 || REGNO (addr) == R13_REG))
19129 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19130 is not disp32, but disp32(%rip), so for disp32
19131 SIB byte is needed, unless print_operand_address
19132 optimizes it into disp32(%rip) or (%rip) is implied
19134 else if (disp && !base && !index)
19141 if (GET_CODE (disp) == CONST)
19142 symbol = XEXP (disp, 0);
19143 if (GET_CODE (symbol) == PLUS
19144 && CONST_INT_P (XEXP (symbol, 1)))
19145 symbol = XEXP (symbol, 0);
19147 if (GET_CODE (symbol) != LABEL_REF
19148 && (GET_CODE (symbol) != SYMBOL_REF
19149 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19150 && (GET_CODE (symbol) != UNSPEC
19151 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19152 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19159 /* Find the length of the displacement constant. */
19162 if (base && satisfies_constraint_K (disp))
19167 /* ebp always wants a displacement. Similarly r13. */
19168 else if (base && REG_P (base)
19169 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19172 /* An index requires the two-byte modrm form.... */
19174 /* ...like esp (or r12), which always wants an index. */
19175 || base == arg_pointer_rtx
19176 || base == frame_pointer_rtx
19177 || (base && REG_P (base)
19178 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19195 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19196 is set, expect that insn have 8bit immediate alternative. */
19198 ix86_attr_length_immediate_default (rtx insn, int shortform)
19202 extract_insn_cached (insn);
19203 for (i = recog_data.n_operands - 1; i >= 0; --i)
19204 if (CONSTANT_P (recog_data.operand[i]))
19206 enum attr_mode mode = get_attr_mode (insn);
19209 if (shortform && CONST_INT_P (recog_data.operand[i]))
19211 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19218 ival = trunc_int_for_mode (ival, HImode);
19221 ival = trunc_int_for_mode (ival, SImode);
19226 if (IN_RANGE (ival, -128, 127))
19243 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19248 fatal_insn ("unknown insn mode", insn);
19253 /* Compute default value for "length_address" attribute. */
19255 ix86_attr_length_address_default (rtx insn)
19259 if (get_attr_type (insn) == TYPE_LEA)
19261 rtx set = PATTERN (insn), addr;
19263 if (GET_CODE (set) == PARALLEL)
19264 set = XVECEXP (set, 0, 0);
19266 gcc_assert (GET_CODE (set) == SET);
19268 addr = SET_SRC (set);
19269 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19271 if (GET_CODE (addr) == ZERO_EXTEND)
19272 addr = XEXP (addr, 0);
19273 if (GET_CODE (addr) == SUBREG)
19274 addr = SUBREG_REG (addr);
19277 return memory_address_length (addr);
19280 extract_insn_cached (insn);
19281 for (i = recog_data.n_operands - 1; i >= 0; --i)
19282 if (MEM_P (recog_data.operand[i]))
19284 constrain_operands_cached (reload_completed);
19285 if (which_alternative != -1)
19287 const char *constraints = recog_data.constraints[i];
19288 int alt = which_alternative;
19290 while (*constraints == '=' || *constraints == '+')
19293 while (*constraints++ != ',')
19295 /* Skip ignored operands. */
19296 if (*constraints == 'X')
19299 return memory_address_length (XEXP (recog_data.operand[i], 0));
19304 /* Compute default value for "length_vex" attribute. It includes
19305 2 or 3 byte VEX prefix and 1 opcode byte. */
19308 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19313 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19314 byte VEX prefix. */
19315 if (!has_0f_opcode || has_vex_w)
19318 /* We can always use 2 byte VEX prefix in 32bit. */
19322 extract_insn_cached (insn);
19324 for (i = recog_data.n_operands - 1; i >= 0; --i)
19325 if (REG_P (recog_data.operand[i]))
19327 /* REX.W bit uses 3 byte VEX prefix. */
19328 if (GET_MODE (recog_data.operand[i]) == DImode
19329 && GENERAL_REG_P (recog_data.operand[i]))
19334 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19335 if (MEM_P (recog_data.operand[i])
19336 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19343 /* Return the maximum number of instructions a cpu can issue. */
19346 ix86_issue_rate (void)
19350 case PROCESSOR_PENTIUM:
19351 case PROCESSOR_ATOM:
19355 case PROCESSOR_PENTIUMPRO:
19356 case PROCESSOR_PENTIUM4:
19357 case PROCESSOR_ATHLON:
19359 case PROCESSOR_AMDFAM10:
19360 case PROCESSOR_NOCONA:
19361 case PROCESSOR_GENERIC32:
19362 case PROCESSOR_GENERIC64:
19365 case PROCESSOR_CORE2:
19373 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19374 by DEP_INSN and nothing set by DEP_INSN. */
19377 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19381 /* Simplify the test for uninteresting insns. */
19382 if (insn_type != TYPE_SETCC
19383 && insn_type != TYPE_ICMOV
19384 && insn_type != TYPE_FCMOV
19385 && insn_type != TYPE_IBR)
19388 if ((set = single_set (dep_insn)) != 0)
19390 set = SET_DEST (set);
19393 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19394 && XVECLEN (PATTERN (dep_insn), 0) == 2
19395 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19396 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19398 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19399 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19404 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19407 /* This test is true if the dependent insn reads the flags but
19408 not any other potentially set register. */
19409 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19412 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19418 /* Return true iff USE_INSN has a memory address with operands set by
19422 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19425 extract_insn_cached (use_insn);
19426 for (i = recog_data.n_operands - 1; i >= 0; --i)
19427 if (MEM_P (recog_data.operand[i]))
19429 rtx addr = XEXP (recog_data.operand[i], 0);
19430 return modified_in_p (addr, set_insn) != 0;
19436 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19438 enum attr_type insn_type, dep_insn_type;
19439 enum attr_memory memory;
19441 int dep_insn_code_number;
19443 /* Anti and output dependencies have zero cost on all CPUs. */
19444 if (REG_NOTE_KIND (link) != 0)
19447 dep_insn_code_number = recog_memoized (dep_insn);
19449 /* If we can't recognize the insns, we can't really do anything. */
19450 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19453 insn_type = get_attr_type (insn);
19454 dep_insn_type = get_attr_type (dep_insn);
19458 case PROCESSOR_PENTIUM:
19459 /* Address Generation Interlock adds a cycle of latency. */
19460 if (insn_type == TYPE_LEA)
19462 rtx addr = PATTERN (insn);
19464 if (GET_CODE (addr) == PARALLEL)
19465 addr = XVECEXP (addr, 0, 0);
19467 gcc_assert (GET_CODE (addr) == SET);
19469 addr = SET_SRC (addr);
19470 if (modified_in_p (addr, dep_insn))
19473 else if (ix86_agi_dependent (dep_insn, insn))
19476 /* ??? Compares pair with jump/setcc. */
19477 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19480 /* Floating point stores require value to be ready one cycle earlier. */
19481 if (insn_type == TYPE_FMOV
19482 && get_attr_memory (insn) == MEMORY_STORE
19483 && !ix86_agi_dependent (dep_insn, insn))
19487 case PROCESSOR_PENTIUMPRO:
19488 memory = get_attr_memory (insn);
19490 /* INT->FP conversion is expensive. */
19491 if (get_attr_fp_int_src (dep_insn))
19494 /* There is one cycle extra latency between an FP op and a store. */
19495 if (insn_type == TYPE_FMOV
19496 && (set = single_set (dep_insn)) != NULL_RTX
19497 && (set2 = single_set (insn)) != NULL_RTX
19498 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19499 && MEM_P (SET_DEST (set2)))
19502 /* Show ability of reorder buffer to hide latency of load by executing
19503 in parallel with previous instruction in case
19504 previous instruction is not needed to compute the address. */
19505 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19506 && !ix86_agi_dependent (dep_insn, insn))
19508 /* Claim moves to take one cycle, as core can issue one load
19509 at time and the next load can start cycle later. */
19510 if (dep_insn_type == TYPE_IMOV
19511 || dep_insn_type == TYPE_FMOV)
19519 memory = get_attr_memory (insn);
19521 /* The esp dependency is resolved before the instruction is really
19523 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19524 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19527 /* INT->FP conversion is expensive. */
19528 if (get_attr_fp_int_src (dep_insn))
19531 /* Show ability of reorder buffer to hide latency of load by executing
19532 in parallel with previous instruction in case
19533 previous instruction is not needed to compute the address. */
19534 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19535 && !ix86_agi_dependent (dep_insn, insn))
19537 /* Claim moves to take one cycle, as core can issue one load
19538 at time and the next load can start cycle later. */
19539 if (dep_insn_type == TYPE_IMOV
19540 || dep_insn_type == TYPE_FMOV)
19549 case PROCESSOR_ATHLON:
19551 case PROCESSOR_AMDFAM10:
19552 case PROCESSOR_ATOM:
19553 case PROCESSOR_GENERIC32:
19554 case PROCESSOR_GENERIC64:
19555 memory = get_attr_memory (insn);
19557 /* Show ability of reorder buffer to hide latency of load by executing
19558 in parallel with previous instruction in case
19559 previous instruction is not needed to compute the address. */
19560 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19561 && !ix86_agi_dependent (dep_insn, insn))
19563 enum attr_unit unit = get_attr_unit (insn);
19566 /* Because of the difference between the length of integer and
19567 floating unit pipeline preparation stages, the memory operands
19568 for floating point are cheaper.
19570 ??? For Athlon it the difference is most probably 2. */
19571 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19574 loadcost = TARGET_ATHLON ? 2 : 0;
19576 if (cost >= loadcost)
19589 /* How many alternative schedules to try. This should be as wide as the
19590 scheduling freedom in the DFA, but no wider. Making this value too
19591 large results extra work for the scheduler. */
19594 ia32_multipass_dfa_lookahead (void)
19598 case PROCESSOR_PENTIUM:
19601 case PROCESSOR_PENTIUMPRO:
19611 /* Compute the alignment given to a constant that is being placed in memory.
19612 EXP is the constant and ALIGN is the alignment that the object would
19614 The value of this function is used instead of that alignment to align
19618 ix86_constant_alignment (tree exp, int align)
19620 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19621 || TREE_CODE (exp) == INTEGER_CST)
19623 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19625 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19628 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19629 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19630 return BITS_PER_WORD;
19635 /* Compute the alignment for a static variable.
19636 TYPE is the data type, and ALIGN is the alignment that
19637 the object would ordinarily have. The value of this function is used
19638 instead of that alignment to align the object. */
19641 ix86_data_alignment (tree type, int align)
19643 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19645 if (AGGREGATE_TYPE_P (type)
19646 && TYPE_SIZE (type)
19647 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19648 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19649 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19650 && align < max_align)
19653 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19654 to 16byte boundary. */
19657 if (AGGREGATE_TYPE_P (type)
19658 && TYPE_SIZE (type)
19659 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19660 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19661 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19665 if (TREE_CODE (type) == ARRAY_TYPE)
19667 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19669 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19672 else if (TREE_CODE (type) == COMPLEX_TYPE)
19675 if (TYPE_MODE (type) == DCmode && align < 64)
19677 if ((TYPE_MODE (type) == XCmode
19678 || TYPE_MODE (type) == TCmode) && align < 128)
19681 else if ((TREE_CODE (type) == RECORD_TYPE
19682 || TREE_CODE (type) == UNION_TYPE
19683 || TREE_CODE (type) == QUAL_UNION_TYPE)
19684 && TYPE_FIELDS (type))
19686 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19688 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19691 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19692 || TREE_CODE (type) == INTEGER_TYPE)
19694 if (TYPE_MODE (type) == DFmode && align < 64)
19696 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19703 /* Compute the alignment for a local variable or a stack slot. EXP is
19704 the data type or decl itself, MODE is the widest mode available and
19705 ALIGN is the alignment that the object would ordinarily have. The
19706 value of this macro is used instead of that alignment to align the
19710 ix86_local_alignment (tree exp, enum machine_mode mode,
19711 unsigned int align)
19715 if (exp && DECL_P (exp))
19717 type = TREE_TYPE (exp);
19726 /* Don't do dynamic stack realignment for long long objects with
19727 -mpreferred-stack-boundary=2. */
19730 && ix86_preferred_stack_boundary < 64
19731 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19732 && (!type || !TYPE_USER_ALIGN (type))
19733 && (!decl || !DECL_USER_ALIGN (decl)))
19736 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19737 register in MODE. We will return the largest alignment of XF
19741 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19742 align = GET_MODE_ALIGNMENT (DFmode);
19746 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19747 to 16byte boundary. */
19750 if (AGGREGATE_TYPE_P (type)
19751 && TYPE_SIZE (type)
19752 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19753 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19754 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19757 if (TREE_CODE (type) == ARRAY_TYPE)
19759 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19761 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19764 else if (TREE_CODE (type) == COMPLEX_TYPE)
19766 if (TYPE_MODE (type) == DCmode && align < 64)
19768 if ((TYPE_MODE (type) == XCmode
19769 || TYPE_MODE (type) == TCmode) && align < 128)
19772 else if ((TREE_CODE (type) == RECORD_TYPE
19773 || TREE_CODE (type) == UNION_TYPE
19774 || TREE_CODE (type) == QUAL_UNION_TYPE)
19775 && TYPE_FIELDS (type))
19777 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19779 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19782 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19783 || TREE_CODE (type) == INTEGER_TYPE)
19786 if (TYPE_MODE (type) == DFmode && align < 64)
19788 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19794 /* Compute the minimum required alignment for dynamic stack realignment
19795 purposes for a local variable, parameter or a stack slot. EXP is
19796 the data type or decl itself, MODE is its mode and ALIGN is the
19797 alignment that the object would ordinarily have. */
19800 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19801 unsigned int align)
19805 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19808 if (exp && DECL_P (exp))
19810 type = TREE_TYPE (exp);
19819 /* Don't do dynamic stack realignment for long long objects with
19820 -mpreferred-stack-boundary=2. */
19821 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19822 && (!type || !TYPE_USER_ALIGN (type))
19823 && (!decl || !DECL_USER_ALIGN (decl)))
19829 /* Find a location for the static chain incoming to a nested function.
19830 This is a register, unless all free registers are used by arguments. */
19833 ix86_static_chain (const_tree fndecl, bool incoming_p)
19837 if (!DECL_STATIC_CHAIN (fndecl))
19842 /* We always use R10 in 64-bit mode. */
19848 /* By default in 32-bit mode we use ECX to pass the static chain. */
19851 fntype = TREE_TYPE (fndecl);
19852 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
19854 /* Fastcall functions use ecx/edx for arguments, which leaves
19855 us with EAX for the static chain. */
19858 else if (ix86_function_regparm (fntype, fndecl) == 3)
19860 /* For regparm 3, we have no free call-clobbered registers in
19861 which to store the static chain. In order to implement this,
19862 we have the trampoline push the static chain to the stack.
19863 However, we can't push a value below the return address when
19864 we call the nested function directly, so we have to use an
19865 alternate entry point. For this we use ESI, and have the
19866 alternate entry point push ESI, so that things appear the
19867 same once we're executing the nested function. */
19870 if (fndecl == current_function_decl)
19871 ix86_static_chain_on_stack = true;
19872 return gen_frame_mem (SImode,
19873 plus_constant (arg_pointer_rtx, -8));
19879 return gen_rtx_REG (Pmode, regno);
19882 /* Emit RTL insns to initialize the variable parts of a trampoline.
19883 FNDECL is the decl of the target address; M_TRAMP is a MEM for
19884 the trampoline, and CHAIN_VALUE is an RTX for the static chain
19885 to be passed to the target function. */
19888 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
19892 fnaddr = XEXP (DECL_RTL (fndecl), 0);
19899 /* Depending on the static chain location, either load a register
19900 with a constant, or push the constant to the stack. All of the
19901 instructions are the same size. */
19902 chain = ix86_static_chain (fndecl, true);
19905 if (REGNO (chain) == CX_REG)
19907 else if (REGNO (chain) == AX_REG)
19910 gcc_unreachable ();
19915 mem = adjust_address (m_tramp, QImode, 0);
19916 emit_move_insn (mem, gen_int_mode (opcode, QImode));
19918 mem = adjust_address (m_tramp, SImode, 1);
19919 emit_move_insn (mem, chain_value);
19921 /* Compute offset from the end of the jmp to the target function.
19922 In the case in which the trampoline stores the static chain on
19923 the stack, we need to skip the first insn which pushes the
19924 (call-saved) register static chain; this push is 1 byte. */
19925 disp = expand_binop (SImode, sub_optab, fnaddr,
19926 plus_constant (XEXP (m_tramp, 0),
19927 MEM_P (chain) ? 9 : 10),
19928 NULL_RTX, 1, OPTAB_DIRECT);
19930 mem = adjust_address (m_tramp, QImode, 5);
19931 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
19933 mem = adjust_address (m_tramp, SImode, 6);
19934 emit_move_insn (mem, disp);
19940 /* Load the function address to r11. Try to load address using
19941 the shorter movl instead of movabs. We may want to support
19942 movq for kernel mode, but kernel does not use trampolines at
19944 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19946 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19948 mem = adjust_address (m_tramp, HImode, offset);
19949 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
19951 mem = adjust_address (m_tramp, SImode, offset + 2);
19952 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
19957 mem = adjust_address (m_tramp, HImode, offset);
19958 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
19960 mem = adjust_address (m_tramp, DImode, offset + 2);
19961 emit_move_insn (mem, fnaddr);
19965 /* Load static chain using movabs to r10. */
19966 mem = adjust_address (m_tramp, HImode, offset);
19967 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
19969 mem = adjust_address (m_tramp, DImode, offset + 2);
19970 emit_move_insn (mem, chain_value);
19973 /* Jump to r11; the last (unused) byte is a nop, only there to
19974 pad the write out to a single 32-bit store. */
19975 mem = adjust_address (m_tramp, SImode, offset);
19976 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
19979 gcc_assert (offset <= TRAMPOLINE_SIZE);
19982 #ifdef ENABLE_EXECUTE_STACK
19983 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19984 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
19988 /* Codes for all the SSE/MMX builtins. */
19991 IX86_BUILTIN_ADDPS,
19992 IX86_BUILTIN_ADDSS,
19993 IX86_BUILTIN_DIVPS,
19994 IX86_BUILTIN_DIVSS,
19995 IX86_BUILTIN_MULPS,
19996 IX86_BUILTIN_MULSS,
19997 IX86_BUILTIN_SUBPS,
19998 IX86_BUILTIN_SUBSS,
20000 IX86_BUILTIN_CMPEQPS,
20001 IX86_BUILTIN_CMPLTPS,
20002 IX86_BUILTIN_CMPLEPS,
20003 IX86_BUILTIN_CMPGTPS,
20004 IX86_BUILTIN_CMPGEPS,
20005 IX86_BUILTIN_CMPNEQPS,
20006 IX86_BUILTIN_CMPNLTPS,
20007 IX86_BUILTIN_CMPNLEPS,
20008 IX86_BUILTIN_CMPNGTPS,
20009 IX86_BUILTIN_CMPNGEPS,
20010 IX86_BUILTIN_CMPORDPS,
20011 IX86_BUILTIN_CMPUNORDPS,
20012 IX86_BUILTIN_CMPEQSS,
20013 IX86_BUILTIN_CMPLTSS,
20014 IX86_BUILTIN_CMPLESS,
20015 IX86_BUILTIN_CMPNEQSS,
20016 IX86_BUILTIN_CMPNLTSS,
20017 IX86_BUILTIN_CMPNLESS,
20018 IX86_BUILTIN_CMPNGTSS,
20019 IX86_BUILTIN_CMPNGESS,
20020 IX86_BUILTIN_CMPORDSS,
20021 IX86_BUILTIN_CMPUNORDSS,
20023 IX86_BUILTIN_COMIEQSS,
20024 IX86_BUILTIN_COMILTSS,
20025 IX86_BUILTIN_COMILESS,
20026 IX86_BUILTIN_COMIGTSS,
20027 IX86_BUILTIN_COMIGESS,
20028 IX86_BUILTIN_COMINEQSS,
20029 IX86_BUILTIN_UCOMIEQSS,
20030 IX86_BUILTIN_UCOMILTSS,
20031 IX86_BUILTIN_UCOMILESS,
20032 IX86_BUILTIN_UCOMIGTSS,
20033 IX86_BUILTIN_UCOMIGESS,
20034 IX86_BUILTIN_UCOMINEQSS,
20036 IX86_BUILTIN_CVTPI2PS,
20037 IX86_BUILTIN_CVTPS2PI,
20038 IX86_BUILTIN_CVTSI2SS,
20039 IX86_BUILTIN_CVTSI642SS,
20040 IX86_BUILTIN_CVTSS2SI,
20041 IX86_BUILTIN_CVTSS2SI64,
20042 IX86_BUILTIN_CVTTPS2PI,
20043 IX86_BUILTIN_CVTTSS2SI,
20044 IX86_BUILTIN_CVTTSS2SI64,
20046 IX86_BUILTIN_MAXPS,
20047 IX86_BUILTIN_MAXSS,
20048 IX86_BUILTIN_MINPS,
20049 IX86_BUILTIN_MINSS,
20051 IX86_BUILTIN_LOADUPS,
20052 IX86_BUILTIN_STOREUPS,
20053 IX86_BUILTIN_MOVSS,
20055 IX86_BUILTIN_MOVHLPS,
20056 IX86_BUILTIN_MOVLHPS,
20057 IX86_BUILTIN_LOADHPS,
20058 IX86_BUILTIN_LOADLPS,
20059 IX86_BUILTIN_STOREHPS,
20060 IX86_BUILTIN_STORELPS,
20062 IX86_BUILTIN_MASKMOVQ,
20063 IX86_BUILTIN_MOVMSKPS,
20064 IX86_BUILTIN_PMOVMSKB,
20066 IX86_BUILTIN_MOVNTPS,
20067 IX86_BUILTIN_MOVNTQ,
20069 IX86_BUILTIN_LOADDQU,
20070 IX86_BUILTIN_STOREDQU,
20072 IX86_BUILTIN_PACKSSWB,
20073 IX86_BUILTIN_PACKSSDW,
20074 IX86_BUILTIN_PACKUSWB,
20076 IX86_BUILTIN_PADDB,
20077 IX86_BUILTIN_PADDW,
20078 IX86_BUILTIN_PADDD,
20079 IX86_BUILTIN_PADDQ,
20080 IX86_BUILTIN_PADDSB,
20081 IX86_BUILTIN_PADDSW,
20082 IX86_BUILTIN_PADDUSB,
20083 IX86_BUILTIN_PADDUSW,
20084 IX86_BUILTIN_PSUBB,
20085 IX86_BUILTIN_PSUBW,
20086 IX86_BUILTIN_PSUBD,
20087 IX86_BUILTIN_PSUBQ,
20088 IX86_BUILTIN_PSUBSB,
20089 IX86_BUILTIN_PSUBSW,
20090 IX86_BUILTIN_PSUBUSB,
20091 IX86_BUILTIN_PSUBUSW,
20094 IX86_BUILTIN_PANDN,
20098 IX86_BUILTIN_PAVGB,
20099 IX86_BUILTIN_PAVGW,
20101 IX86_BUILTIN_PCMPEQB,
20102 IX86_BUILTIN_PCMPEQW,
20103 IX86_BUILTIN_PCMPEQD,
20104 IX86_BUILTIN_PCMPGTB,
20105 IX86_BUILTIN_PCMPGTW,
20106 IX86_BUILTIN_PCMPGTD,
20108 IX86_BUILTIN_PMADDWD,
20110 IX86_BUILTIN_PMAXSW,
20111 IX86_BUILTIN_PMAXUB,
20112 IX86_BUILTIN_PMINSW,
20113 IX86_BUILTIN_PMINUB,
20115 IX86_BUILTIN_PMULHUW,
20116 IX86_BUILTIN_PMULHW,
20117 IX86_BUILTIN_PMULLW,
20119 IX86_BUILTIN_PSADBW,
20120 IX86_BUILTIN_PSHUFW,
20122 IX86_BUILTIN_PSLLW,
20123 IX86_BUILTIN_PSLLD,
20124 IX86_BUILTIN_PSLLQ,
20125 IX86_BUILTIN_PSRAW,
20126 IX86_BUILTIN_PSRAD,
20127 IX86_BUILTIN_PSRLW,
20128 IX86_BUILTIN_PSRLD,
20129 IX86_BUILTIN_PSRLQ,
20130 IX86_BUILTIN_PSLLWI,
20131 IX86_BUILTIN_PSLLDI,
20132 IX86_BUILTIN_PSLLQI,
20133 IX86_BUILTIN_PSRAWI,
20134 IX86_BUILTIN_PSRADI,
20135 IX86_BUILTIN_PSRLWI,
20136 IX86_BUILTIN_PSRLDI,
20137 IX86_BUILTIN_PSRLQI,
20139 IX86_BUILTIN_PUNPCKHBW,
20140 IX86_BUILTIN_PUNPCKHWD,
20141 IX86_BUILTIN_PUNPCKHDQ,
20142 IX86_BUILTIN_PUNPCKLBW,
20143 IX86_BUILTIN_PUNPCKLWD,
20144 IX86_BUILTIN_PUNPCKLDQ,
20146 IX86_BUILTIN_SHUFPS,
20148 IX86_BUILTIN_RCPPS,
20149 IX86_BUILTIN_RCPSS,
20150 IX86_BUILTIN_RSQRTPS,
20151 IX86_BUILTIN_RSQRTPS_NR,
20152 IX86_BUILTIN_RSQRTSS,
20153 IX86_BUILTIN_RSQRTF,
20154 IX86_BUILTIN_SQRTPS,
20155 IX86_BUILTIN_SQRTPS_NR,
20156 IX86_BUILTIN_SQRTSS,
20158 IX86_BUILTIN_UNPCKHPS,
20159 IX86_BUILTIN_UNPCKLPS,
20161 IX86_BUILTIN_ANDPS,
20162 IX86_BUILTIN_ANDNPS,
20164 IX86_BUILTIN_XORPS,
20167 IX86_BUILTIN_LDMXCSR,
20168 IX86_BUILTIN_STMXCSR,
20169 IX86_BUILTIN_SFENCE,
20171 /* 3DNow! Original */
20172 IX86_BUILTIN_FEMMS,
20173 IX86_BUILTIN_PAVGUSB,
20174 IX86_BUILTIN_PF2ID,
20175 IX86_BUILTIN_PFACC,
20176 IX86_BUILTIN_PFADD,
20177 IX86_BUILTIN_PFCMPEQ,
20178 IX86_BUILTIN_PFCMPGE,
20179 IX86_BUILTIN_PFCMPGT,
20180 IX86_BUILTIN_PFMAX,
20181 IX86_BUILTIN_PFMIN,
20182 IX86_BUILTIN_PFMUL,
20183 IX86_BUILTIN_PFRCP,
20184 IX86_BUILTIN_PFRCPIT1,
20185 IX86_BUILTIN_PFRCPIT2,
20186 IX86_BUILTIN_PFRSQIT1,
20187 IX86_BUILTIN_PFRSQRT,
20188 IX86_BUILTIN_PFSUB,
20189 IX86_BUILTIN_PFSUBR,
20190 IX86_BUILTIN_PI2FD,
20191 IX86_BUILTIN_PMULHRW,
20193 /* 3DNow! Athlon Extensions */
20194 IX86_BUILTIN_PF2IW,
20195 IX86_BUILTIN_PFNACC,
20196 IX86_BUILTIN_PFPNACC,
20197 IX86_BUILTIN_PI2FW,
20198 IX86_BUILTIN_PSWAPDSI,
20199 IX86_BUILTIN_PSWAPDSF,
20202 IX86_BUILTIN_ADDPD,
20203 IX86_BUILTIN_ADDSD,
20204 IX86_BUILTIN_DIVPD,
20205 IX86_BUILTIN_DIVSD,
20206 IX86_BUILTIN_MULPD,
20207 IX86_BUILTIN_MULSD,
20208 IX86_BUILTIN_SUBPD,
20209 IX86_BUILTIN_SUBSD,
20211 IX86_BUILTIN_CMPEQPD,
20212 IX86_BUILTIN_CMPLTPD,
20213 IX86_BUILTIN_CMPLEPD,
20214 IX86_BUILTIN_CMPGTPD,
20215 IX86_BUILTIN_CMPGEPD,
20216 IX86_BUILTIN_CMPNEQPD,
20217 IX86_BUILTIN_CMPNLTPD,
20218 IX86_BUILTIN_CMPNLEPD,
20219 IX86_BUILTIN_CMPNGTPD,
20220 IX86_BUILTIN_CMPNGEPD,
20221 IX86_BUILTIN_CMPORDPD,
20222 IX86_BUILTIN_CMPUNORDPD,
20223 IX86_BUILTIN_CMPEQSD,
20224 IX86_BUILTIN_CMPLTSD,
20225 IX86_BUILTIN_CMPLESD,
20226 IX86_BUILTIN_CMPNEQSD,
20227 IX86_BUILTIN_CMPNLTSD,
20228 IX86_BUILTIN_CMPNLESD,
20229 IX86_BUILTIN_CMPORDSD,
20230 IX86_BUILTIN_CMPUNORDSD,
20232 IX86_BUILTIN_COMIEQSD,
20233 IX86_BUILTIN_COMILTSD,
20234 IX86_BUILTIN_COMILESD,
20235 IX86_BUILTIN_COMIGTSD,
20236 IX86_BUILTIN_COMIGESD,
20237 IX86_BUILTIN_COMINEQSD,
20238 IX86_BUILTIN_UCOMIEQSD,
20239 IX86_BUILTIN_UCOMILTSD,
20240 IX86_BUILTIN_UCOMILESD,
20241 IX86_BUILTIN_UCOMIGTSD,
20242 IX86_BUILTIN_UCOMIGESD,
20243 IX86_BUILTIN_UCOMINEQSD,
20245 IX86_BUILTIN_MAXPD,
20246 IX86_BUILTIN_MAXSD,
20247 IX86_BUILTIN_MINPD,
20248 IX86_BUILTIN_MINSD,
20250 IX86_BUILTIN_ANDPD,
20251 IX86_BUILTIN_ANDNPD,
20253 IX86_BUILTIN_XORPD,
20255 IX86_BUILTIN_SQRTPD,
20256 IX86_BUILTIN_SQRTSD,
20258 IX86_BUILTIN_UNPCKHPD,
20259 IX86_BUILTIN_UNPCKLPD,
20261 IX86_BUILTIN_SHUFPD,
20263 IX86_BUILTIN_LOADUPD,
20264 IX86_BUILTIN_STOREUPD,
20265 IX86_BUILTIN_MOVSD,
20267 IX86_BUILTIN_LOADHPD,
20268 IX86_BUILTIN_LOADLPD,
20270 IX86_BUILTIN_CVTDQ2PD,
20271 IX86_BUILTIN_CVTDQ2PS,
20273 IX86_BUILTIN_CVTPD2DQ,
20274 IX86_BUILTIN_CVTPD2PI,
20275 IX86_BUILTIN_CVTPD2PS,
20276 IX86_BUILTIN_CVTTPD2DQ,
20277 IX86_BUILTIN_CVTTPD2PI,
20279 IX86_BUILTIN_CVTPI2PD,
20280 IX86_BUILTIN_CVTSI2SD,
20281 IX86_BUILTIN_CVTSI642SD,
20283 IX86_BUILTIN_CVTSD2SI,
20284 IX86_BUILTIN_CVTSD2SI64,
20285 IX86_BUILTIN_CVTSD2SS,
20286 IX86_BUILTIN_CVTSS2SD,
20287 IX86_BUILTIN_CVTTSD2SI,
20288 IX86_BUILTIN_CVTTSD2SI64,
20290 IX86_BUILTIN_CVTPS2DQ,
20291 IX86_BUILTIN_CVTPS2PD,
20292 IX86_BUILTIN_CVTTPS2DQ,
20294 IX86_BUILTIN_MOVNTI,
20295 IX86_BUILTIN_MOVNTPD,
20296 IX86_BUILTIN_MOVNTDQ,
20298 IX86_BUILTIN_MOVQ128,
20301 IX86_BUILTIN_MASKMOVDQU,
20302 IX86_BUILTIN_MOVMSKPD,
20303 IX86_BUILTIN_PMOVMSKB128,
20305 IX86_BUILTIN_PACKSSWB128,
20306 IX86_BUILTIN_PACKSSDW128,
20307 IX86_BUILTIN_PACKUSWB128,
20309 IX86_BUILTIN_PADDB128,
20310 IX86_BUILTIN_PADDW128,
20311 IX86_BUILTIN_PADDD128,
20312 IX86_BUILTIN_PADDQ128,
20313 IX86_BUILTIN_PADDSB128,
20314 IX86_BUILTIN_PADDSW128,
20315 IX86_BUILTIN_PADDUSB128,
20316 IX86_BUILTIN_PADDUSW128,
20317 IX86_BUILTIN_PSUBB128,
20318 IX86_BUILTIN_PSUBW128,
20319 IX86_BUILTIN_PSUBD128,
20320 IX86_BUILTIN_PSUBQ128,
20321 IX86_BUILTIN_PSUBSB128,
20322 IX86_BUILTIN_PSUBSW128,
20323 IX86_BUILTIN_PSUBUSB128,
20324 IX86_BUILTIN_PSUBUSW128,
20326 IX86_BUILTIN_PAND128,
20327 IX86_BUILTIN_PANDN128,
20328 IX86_BUILTIN_POR128,
20329 IX86_BUILTIN_PXOR128,
20331 IX86_BUILTIN_PAVGB128,
20332 IX86_BUILTIN_PAVGW128,
20334 IX86_BUILTIN_PCMPEQB128,
20335 IX86_BUILTIN_PCMPEQW128,
20336 IX86_BUILTIN_PCMPEQD128,
20337 IX86_BUILTIN_PCMPGTB128,
20338 IX86_BUILTIN_PCMPGTW128,
20339 IX86_BUILTIN_PCMPGTD128,
20341 IX86_BUILTIN_PMADDWD128,
20343 IX86_BUILTIN_PMAXSW128,
20344 IX86_BUILTIN_PMAXUB128,
20345 IX86_BUILTIN_PMINSW128,
20346 IX86_BUILTIN_PMINUB128,
20348 IX86_BUILTIN_PMULUDQ,
20349 IX86_BUILTIN_PMULUDQ128,
20350 IX86_BUILTIN_PMULHUW128,
20351 IX86_BUILTIN_PMULHW128,
20352 IX86_BUILTIN_PMULLW128,
20354 IX86_BUILTIN_PSADBW128,
20355 IX86_BUILTIN_PSHUFHW,
20356 IX86_BUILTIN_PSHUFLW,
20357 IX86_BUILTIN_PSHUFD,
20359 IX86_BUILTIN_PSLLDQI128,
20360 IX86_BUILTIN_PSLLWI128,
20361 IX86_BUILTIN_PSLLDI128,
20362 IX86_BUILTIN_PSLLQI128,
20363 IX86_BUILTIN_PSRAWI128,
20364 IX86_BUILTIN_PSRADI128,
20365 IX86_BUILTIN_PSRLDQI128,
20366 IX86_BUILTIN_PSRLWI128,
20367 IX86_BUILTIN_PSRLDI128,
20368 IX86_BUILTIN_PSRLQI128,
20370 IX86_BUILTIN_PSLLDQ128,
20371 IX86_BUILTIN_PSLLW128,
20372 IX86_BUILTIN_PSLLD128,
20373 IX86_BUILTIN_PSLLQ128,
20374 IX86_BUILTIN_PSRAW128,
20375 IX86_BUILTIN_PSRAD128,
20376 IX86_BUILTIN_PSRLW128,
20377 IX86_BUILTIN_PSRLD128,
20378 IX86_BUILTIN_PSRLQ128,
20380 IX86_BUILTIN_PUNPCKHBW128,
20381 IX86_BUILTIN_PUNPCKHWD128,
20382 IX86_BUILTIN_PUNPCKHDQ128,
20383 IX86_BUILTIN_PUNPCKHQDQ128,
20384 IX86_BUILTIN_PUNPCKLBW128,
20385 IX86_BUILTIN_PUNPCKLWD128,
20386 IX86_BUILTIN_PUNPCKLDQ128,
20387 IX86_BUILTIN_PUNPCKLQDQ128,
20389 IX86_BUILTIN_CLFLUSH,
20390 IX86_BUILTIN_MFENCE,
20391 IX86_BUILTIN_LFENCE,
20393 IX86_BUILTIN_BSRSI,
20394 IX86_BUILTIN_BSRDI,
20395 IX86_BUILTIN_RDPMC,
20396 IX86_BUILTIN_RDTSC,
20397 IX86_BUILTIN_RDTSCP,
20398 IX86_BUILTIN_ROLQI,
20399 IX86_BUILTIN_ROLHI,
20400 IX86_BUILTIN_RORQI,
20401 IX86_BUILTIN_RORHI,
20404 IX86_BUILTIN_ADDSUBPS,
20405 IX86_BUILTIN_HADDPS,
20406 IX86_BUILTIN_HSUBPS,
20407 IX86_BUILTIN_MOVSHDUP,
20408 IX86_BUILTIN_MOVSLDUP,
20409 IX86_BUILTIN_ADDSUBPD,
20410 IX86_BUILTIN_HADDPD,
20411 IX86_BUILTIN_HSUBPD,
20412 IX86_BUILTIN_LDDQU,
20414 IX86_BUILTIN_MONITOR,
20415 IX86_BUILTIN_MWAIT,
20418 IX86_BUILTIN_PHADDW,
20419 IX86_BUILTIN_PHADDD,
20420 IX86_BUILTIN_PHADDSW,
20421 IX86_BUILTIN_PHSUBW,
20422 IX86_BUILTIN_PHSUBD,
20423 IX86_BUILTIN_PHSUBSW,
20424 IX86_BUILTIN_PMADDUBSW,
20425 IX86_BUILTIN_PMULHRSW,
20426 IX86_BUILTIN_PSHUFB,
20427 IX86_BUILTIN_PSIGNB,
20428 IX86_BUILTIN_PSIGNW,
20429 IX86_BUILTIN_PSIGND,
20430 IX86_BUILTIN_PALIGNR,
20431 IX86_BUILTIN_PABSB,
20432 IX86_BUILTIN_PABSW,
20433 IX86_BUILTIN_PABSD,
20435 IX86_BUILTIN_PHADDW128,
20436 IX86_BUILTIN_PHADDD128,
20437 IX86_BUILTIN_PHADDSW128,
20438 IX86_BUILTIN_PHSUBW128,
20439 IX86_BUILTIN_PHSUBD128,
20440 IX86_BUILTIN_PHSUBSW128,
20441 IX86_BUILTIN_PMADDUBSW128,
20442 IX86_BUILTIN_PMULHRSW128,
20443 IX86_BUILTIN_PSHUFB128,
20444 IX86_BUILTIN_PSIGNB128,
20445 IX86_BUILTIN_PSIGNW128,
20446 IX86_BUILTIN_PSIGND128,
20447 IX86_BUILTIN_PALIGNR128,
20448 IX86_BUILTIN_PABSB128,
20449 IX86_BUILTIN_PABSW128,
20450 IX86_BUILTIN_PABSD128,
20452 /* AMDFAM10 - SSE4A New Instructions. */
20453 IX86_BUILTIN_MOVNTSD,
20454 IX86_BUILTIN_MOVNTSS,
20455 IX86_BUILTIN_EXTRQI,
20456 IX86_BUILTIN_EXTRQ,
20457 IX86_BUILTIN_INSERTQI,
20458 IX86_BUILTIN_INSERTQ,
20461 IX86_BUILTIN_BLENDPD,
20462 IX86_BUILTIN_BLENDPS,
20463 IX86_BUILTIN_BLENDVPD,
20464 IX86_BUILTIN_BLENDVPS,
20465 IX86_BUILTIN_PBLENDVB128,
20466 IX86_BUILTIN_PBLENDW128,
20471 IX86_BUILTIN_INSERTPS128,
20473 IX86_BUILTIN_MOVNTDQA,
20474 IX86_BUILTIN_MPSADBW128,
20475 IX86_BUILTIN_PACKUSDW128,
20476 IX86_BUILTIN_PCMPEQQ,
20477 IX86_BUILTIN_PHMINPOSUW128,
20479 IX86_BUILTIN_PMAXSB128,
20480 IX86_BUILTIN_PMAXSD128,
20481 IX86_BUILTIN_PMAXUD128,
20482 IX86_BUILTIN_PMAXUW128,
20484 IX86_BUILTIN_PMINSB128,
20485 IX86_BUILTIN_PMINSD128,
20486 IX86_BUILTIN_PMINUD128,
20487 IX86_BUILTIN_PMINUW128,
20489 IX86_BUILTIN_PMOVSXBW128,
20490 IX86_BUILTIN_PMOVSXBD128,
20491 IX86_BUILTIN_PMOVSXBQ128,
20492 IX86_BUILTIN_PMOVSXWD128,
20493 IX86_BUILTIN_PMOVSXWQ128,
20494 IX86_BUILTIN_PMOVSXDQ128,
20496 IX86_BUILTIN_PMOVZXBW128,
20497 IX86_BUILTIN_PMOVZXBD128,
20498 IX86_BUILTIN_PMOVZXBQ128,
20499 IX86_BUILTIN_PMOVZXWD128,
20500 IX86_BUILTIN_PMOVZXWQ128,
20501 IX86_BUILTIN_PMOVZXDQ128,
20503 IX86_BUILTIN_PMULDQ128,
20504 IX86_BUILTIN_PMULLD128,
20506 IX86_BUILTIN_ROUNDPD,
20507 IX86_BUILTIN_ROUNDPS,
20508 IX86_BUILTIN_ROUNDSD,
20509 IX86_BUILTIN_ROUNDSS,
20511 IX86_BUILTIN_PTESTZ,
20512 IX86_BUILTIN_PTESTC,
20513 IX86_BUILTIN_PTESTNZC,
20515 IX86_BUILTIN_VEC_INIT_V2SI,
20516 IX86_BUILTIN_VEC_INIT_V4HI,
20517 IX86_BUILTIN_VEC_INIT_V8QI,
20518 IX86_BUILTIN_VEC_EXT_V2DF,
20519 IX86_BUILTIN_VEC_EXT_V2DI,
20520 IX86_BUILTIN_VEC_EXT_V4SF,
20521 IX86_BUILTIN_VEC_EXT_V4SI,
20522 IX86_BUILTIN_VEC_EXT_V8HI,
20523 IX86_BUILTIN_VEC_EXT_V2SI,
20524 IX86_BUILTIN_VEC_EXT_V4HI,
20525 IX86_BUILTIN_VEC_EXT_V16QI,
20526 IX86_BUILTIN_VEC_SET_V2DI,
20527 IX86_BUILTIN_VEC_SET_V4SF,
20528 IX86_BUILTIN_VEC_SET_V4SI,
20529 IX86_BUILTIN_VEC_SET_V8HI,
20530 IX86_BUILTIN_VEC_SET_V4HI,
20531 IX86_BUILTIN_VEC_SET_V16QI,
20533 IX86_BUILTIN_VEC_PACK_SFIX,
20536 IX86_BUILTIN_CRC32QI,
20537 IX86_BUILTIN_CRC32HI,
20538 IX86_BUILTIN_CRC32SI,
20539 IX86_BUILTIN_CRC32DI,
20541 IX86_BUILTIN_PCMPESTRI128,
20542 IX86_BUILTIN_PCMPESTRM128,
20543 IX86_BUILTIN_PCMPESTRA128,
20544 IX86_BUILTIN_PCMPESTRC128,
20545 IX86_BUILTIN_PCMPESTRO128,
20546 IX86_BUILTIN_PCMPESTRS128,
20547 IX86_BUILTIN_PCMPESTRZ128,
20548 IX86_BUILTIN_PCMPISTRI128,
20549 IX86_BUILTIN_PCMPISTRM128,
20550 IX86_BUILTIN_PCMPISTRA128,
20551 IX86_BUILTIN_PCMPISTRC128,
20552 IX86_BUILTIN_PCMPISTRO128,
20553 IX86_BUILTIN_PCMPISTRS128,
20554 IX86_BUILTIN_PCMPISTRZ128,
20556 IX86_BUILTIN_PCMPGTQ,
20558 /* AES instructions */
20559 IX86_BUILTIN_AESENC128,
20560 IX86_BUILTIN_AESENCLAST128,
20561 IX86_BUILTIN_AESDEC128,
20562 IX86_BUILTIN_AESDECLAST128,
20563 IX86_BUILTIN_AESIMC128,
20564 IX86_BUILTIN_AESKEYGENASSIST128,
20566 /* PCLMUL instruction */
20567 IX86_BUILTIN_PCLMULQDQ128,
20570 IX86_BUILTIN_ADDPD256,
20571 IX86_BUILTIN_ADDPS256,
20572 IX86_BUILTIN_ADDSUBPD256,
20573 IX86_BUILTIN_ADDSUBPS256,
20574 IX86_BUILTIN_ANDPD256,
20575 IX86_BUILTIN_ANDPS256,
20576 IX86_BUILTIN_ANDNPD256,
20577 IX86_BUILTIN_ANDNPS256,
20578 IX86_BUILTIN_BLENDPD256,
20579 IX86_BUILTIN_BLENDPS256,
20580 IX86_BUILTIN_BLENDVPD256,
20581 IX86_BUILTIN_BLENDVPS256,
20582 IX86_BUILTIN_DIVPD256,
20583 IX86_BUILTIN_DIVPS256,
20584 IX86_BUILTIN_DPPS256,
20585 IX86_BUILTIN_HADDPD256,
20586 IX86_BUILTIN_HADDPS256,
20587 IX86_BUILTIN_HSUBPD256,
20588 IX86_BUILTIN_HSUBPS256,
20589 IX86_BUILTIN_MAXPD256,
20590 IX86_BUILTIN_MAXPS256,
20591 IX86_BUILTIN_MINPD256,
20592 IX86_BUILTIN_MINPS256,
20593 IX86_BUILTIN_MULPD256,
20594 IX86_BUILTIN_MULPS256,
20595 IX86_BUILTIN_ORPD256,
20596 IX86_BUILTIN_ORPS256,
20597 IX86_BUILTIN_SHUFPD256,
20598 IX86_BUILTIN_SHUFPS256,
20599 IX86_BUILTIN_SUBPD256,
20600 IX86_BUILTIN_SUBPS256,
20601 IX86_BUILTIN_XORPD256,
20602 IX86_BUILTIN_XORPS256,
20603 IX86_BUILTIN_CMPSD,
20604 IX86_BUILTIN_CMPSS,
20605 IX86_BUILTIN_CMPPD,
20606 IX86_BUILTIN_CMPPS,
20607 IX86_BUILTIN_CMPPD256,
20608 IX86_BUILTIN_CMPPS256,
20609 IX86_BUILTIN_CVTDQ2PD256,
20610 IX86_BUILTIN_CVTDQ2PS256,
20611 IX86_BUILTIN_CVTPD2PS256,
20612 IX86_BUILTIN_CVTPS2DQ256,
20613 IX86_BUILTIN_CVTPS2PD256,
20614 IX86_BUILTIN_CVTTPD2DQ256,
20615 IX86_BUILTIN_CVTPD2DQ256,
20616 IX86_BUILTIN_CVTTPS2DQ256,
20617 IX86_BUILTIN_EXTRACTF128PD256,
20618 IX86_BUILTIN_EXTRACTF128PS256,
20619 IX86_BUILTIN_EXTRACTF128SI256,
20620 IX86_BUILTIN_VZEROALL,
20621 IX86_BUILTIN_VZEROUPPER,
20622 IX86_BUILTIN_VZEROUPPER_REX64,
20623 IX86_BUILTIN_VPERMILVARPD,
20624 IX86_BUILTIN_VPERMILVARPS,
20625 IX86_BUILTIN_VPERMILVARPD256,
20626 IX86_BUILTIN_VPERMILVARPS256,
20627 IX86_BUILTIN_VPERMILPD,
20628 IX86_BUILTIN_VPERMILPS,
20629 IX86_BUILTIN_VPERMILPD256,
20630 IX86_BUILTIN_VPERMILPS256,
20631 IX86_BUILTIN_VPERM2F128PD256,
20632 IX86_BUILTIN_VPERM2F128PS256,
20633 IX86_BUILTIN_VPERM2F128SI256,
20634 IX86_BUILTIN_VBROADCASTSS,
20635 IX86_BUILTIN_VBROADCASTSD256,
20636 IX86_BUILTIN_VBROADCASTSS256,
20637 IX86_BUILTIN_VBROADCASTPD256,
20638 IX86_BUILTIN_VBROADCASTPS256,
20639 IX86_BUILTIN_VINSERTF128PD256,
20640 IX86_BUILTIN_VINSERTF128PS256,
20641 IX86_BUILTIN_VINSERTF128SI256,
20642 IX86_BUILTIN_LOADUPD256,
20643 IX86_BUILTIN_LOADUPS256,
20644 IX86_BUILTIN_STOREUPD256,
20645 IX86_BUILTIN_STOREUPS256,
20646 IX86_BUILTIN_LDDQU256,
20647 IX86_BUILTIN_MOVNTDQ256,
20648 IX86_BUILTIN_MOVNTPD256,
20649 IX86_BUILTIN_MOVNTPS256,
20650 IX86_BUILTIN_LOADDQU256,
20651 IX86_BUILTIN_STOREDQU256,
20652 IX86_BUILTIN_MASKLOADPD,
20653 IX86_BUILTIN_MASKLOADPS,
20654 IX86_BUILTIN_MASKSTOREPD,
20655 IX86_BUILTIN_MASKSTOREPS,
20656 IX86_BUILTIN_MASKLOADPD256,
20657 IX86_BUILTIN_MASKLOADPS256,
20658 IX86_BUILTIN_MASKSTOREPD256,
20659 IX86_BUILTIN_MASKSTOREPS256,
20660 IX86_BUILTIN_MOVSHDUP256,
20661 IX86_BUILTIN_MOVSLDUP256,
20662 IX86_BUILTIN_MOVDDUP256,
20664 IX86_BUILTIN_SQRTPD256,
20665 IX86_BUILTIN_SQRTPS256,
20666 IX86_BUILTIN_SQRTPS_NR256,
20667 IX86_BUILTIN_RSQRTPS256,
20668 IX86_BUILTIN_RSQRTPS_NR256,
20670 IX86_BUILTIN_RCPPS256,
20672 IX86_BUILTIN_ROUNDPD256,
20673 IX86_BUILTIN_ROUNDPS256,
20675 IX86_BUILTIN_UNPCKHPD256,
20676 IX86_BUILTIN_UNPCKLPD256,
20677 IX86_BUILTIN_UNPCKHPS256,
20678 IX86_BUILTIN_UNPCKLPS256,
20680 IX86_BUILTIN_SI256_SI,
20681 IX86_BUILTIN_PS256_PS,
20682 IX86_BUILTIN_PD256_PD,
20683 IX86_BUILTIN_SI_SI256,
20684 IX86_BUILTIN_PS_PS256,
20685 IX86_BUILTIN_PD_PD256,
20687 IX86_BUILTIN_VTESTZPD,
20688 IX86_BUILTIN_VTESTCPD,
20689 IX86_BUILTIN_VTESTNZCPD,
20690 IX86_BUILTIN_VTESTZPS,
20691 IX86_BUILTIN_VTESTCPS,
20692 IX86_BUILTIN_VTESTNZCPS,
20693 IX86_BUILTIN_VTESTZPD256,
20694 IX86_BUILTIN_VTESTCPD256,
20695 IX86_BUILTIN_VTESTNZCPD256,
20696 IX86_BUILTIN_VTESTZPS256,
20697 IX86_BUILTIN_VTESTCPS256,
20698 IX86_BUILTIN_VTESTNZCPS256,
20699 IX86_BUILTIN_PTESTZ256,
20700 IX86_BUILTIN_PTESTC256,
20701 IX86_BUILTIN_PTESTNZC256,
20703 IX86_BUILTIN_MOVMSKPD256,
20704 IX86_BUILTIN_MOVMSKPS256,
20706 /* TFmode support builtins. */
20708 IX86_BUILTIN_HUGE_VALQ,
20709 IX86_BUILTIN_FABSQ,
20710 IX86_BUILTIN_COPYSIGNQ,
20712 /* Vectorizer support builtins. */
20713 IX86_BUILTIN_CPYSGNPS,
20714 IX86_BUILTIN_CPYSGNPD,
20716 IX86_BUILTIN_CVTUDQ2PS,
20718 /* FMA4 instructions. */
20719 IX86_BUILTIN_VFMADDSS,
20720 IX86_BUILTIN_VFMADDSD,
20721 IX86_BUILTIN_VFMADDPS,
20722 IX86_BUILTIN_VFMADDPD,
20723 IX86_BUILTIN_VFMSUBSS,
20724 IX86_BUILTIN_VFMSUBSD,
20725 IX86_BUILTIN_VFMSUBPS,
20726 IX86_BUILTIN_VFMSUBPD,
20727 IX86_BUILTIN_VFMADDSUBPS,
20728 IX86_BUILTIN_VFMADDSUBPD,
20729 IX86_BUILTIN_VFMSUBADDPS,
20730 IX86_BUILTIN_VFMSUBADDPD,
20731 IX86_BUILTIN_VFNMADDSS,
20732 IX86_BUILTIN_VFNMADDSD,
20733 IX86_BUILTIN_VFNMADDPS,
20734 IX86_BUILTIN_VFNMADDPD,
20735 IX86_BUILTIN_VFNMSUBSS,
20736 IX86_BUILTIN_VFNMSUBSD,
20737 IX86_BUILTIN_VFNMSUBPS,
20738 IX86_BUILTIN_VFNMSUBPD,
20739 IX86_BUILTIN_VFMADDPS256,
20740 IX86_BUILTIN_VFMADDPD256,
20741 IX86_BUILTIN_VFMSUBPS256,
20742 IX86_BUILTIN_VFMSUBPD256,
20743 IX86_BUILTIN_VFMADDSUBPS256,
20744 IX86_BUILTIN_VFMADDSUBPD256,
20745 IX86_BUILTIN_VFMSUBADDPS256,
20746 IX86_BUILTIN_VFMSUBADDPD256,
20747 IX86_BUILTIN_VFNMADDPS256,
20748 IX86_BUILTIN_VFNMADDPD256,
20749 IX86_BUILTIN_VFNMSUBPS256,
20750 IX86_BUILTIN_VFNMSUBPD256,
20754 /* Table for the ix86 builtin decls. */
20755 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20757 /* Table of all of the builtin functions that are possible with different ISA's
20758 but are waiting to be built until a function is declared to use that
20760 struct GTY(()) builtin_isa {
20761 tree type; /* builtin type to use in the declaration */
20762 const char *name; /* function name */
20763 int isa; /* isa_flags this builtin is defined for */
20764 bool const_p; /* true if the declaration is constant */
20767 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20770 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20771 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20772 * function decl in the ix86_builtins array. Returns the function decl or
20773 * NULL_TREE, if the builtin was not added.
20775 * If the front end has a special hook for builtin functions, delay adding
20776 * builtin functions that aren't in the current ISA until the ISA is changed
20777 * with function specific optimization. Doing so, can save about 300K for the
20778 * default compiler. When the builtin is expanded, check at that time whether
20781 * If the front end doesn't have a special hook, record all builtins, even if
20782 * it isn't an instruction set in the current ISA in case the user uses
20783 * function specific options for a different ISA, so that we don't get scope
20784 * errors if a builtin is added in the middle of a function scope. */
20787 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20789 tree decl = NULL_TREE;
20791 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20793 ix86_builtins_isa[(int) code].isa = mask;
20795 if ((mask & ix86_isa_flags) != 0
20796 || (lang_hooks.builtin_function
20797 == lang_hooks.builtin_function_ext_scope))
20800 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20802 ix86_builtins[(int) code] = decl;
20803 ix86_builtins_isa[(int) code].type = NULL_TREE;
20807 ix86_builtins[(int) code] = NULL_TREE;
20808 ix86_builtins_isa[(int) code].const_p = false;
20809 ix86_builtins_isa[(int) code].type = type;
20810 ix86_builtins_isa[(int) code].name = name;
20817 /* Like def_builtin, but also marks the function decl "const". */
20820 def_builtin_const (int mask, const char *name, tree type,
20821 enum ix86_builtins code)
20823 tree decl = def_builtin (mask, name, type, code);
20825 TREE_READONLY (decl) = 1;
20827 ix86_builtins_isa[(int) code].const_p = true;
20832 /* Add any new builtin functions for a given ISA that may not have been
20833 declared. This saves a bit of space compared to adding all of the
20834 declarations to the tree, even if we didn't use them. */
20837 ix86_add_new_builtins (int isa)
20842 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20844 if ((ix86_builtins_isa[i].isa & isa) != 0
20845 && ix86_builtins_isa[i].type != NULL_TREE)
20847 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20848 ix86_builtins_isa[i].type,
20849 i, BUILT_IN_MD, NULL,
20852 ix86_builtins[i] = decl;
20853 ix86_builtins_isa[i].type = NULL_TREE;
20854 if (ix86_builtins_isa[i].const_p)
20855 TREE_READONLY (decl) = 1;
20860 /* Bits for builtin_description.flag. */
20862 /* Set when we don't support the comparison natively, and should
20863 swap_comparison in order to support it. */
20864 #define BUILTIN_DESC_SWAP_OPERANDS 1
20866 struct builtin_description
20868 const unsigned int mask;
20869 const enum insn_code icode;
20870 const char *const name;
20871 const enum ix86_builtins code;
20872 const enum rtx_code comparison;
20876 static const struct builtin_description bdesc_comi[] =
20878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20880 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20881 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20882 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20883 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20884 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20885 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20886 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20887 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20888 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20889 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20904 static const struct builtin_description bdesc_pcmpestr[] =
20907 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20908 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20909 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20910 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20911 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20912 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20913 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20916 static const struct builtin_description bdesc_pcmpistr[] =
20919 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20920 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20921 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20922 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20923 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20924 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20925 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20928 /* Special builtin types */
20929 enum ix86_special_builtin_type
20931 SPECIAL_FTYPE_UNKNOWN,
20934 UINT64_FTYPE_PUNSIGNED,
20935 V32QI_FTYPE_PCCHAR,
20936 V16QI_FTYPE_PCCHAR,
20938 V8SF_FTYPE_PCFLOAT,
20940 V4DF_FTYPE_PCDOUBLE,
20941 V4SF_FTYPE_PCFLOAT,
20942 V2DF_FTYPE_PCDOUBLE,
20943 V8SF_FTYPE_PCV8SF_V8SF,
20944 V4DF_FTYPE_PCV4DF_V4DF,
20945 V4SF_FTYPE_V4SF_PCV2SF,
20946 V4SF_FTYPE_PCV4SF_V4SF,
20947 V2DF_FTYPE_V2DF_PCDOUBLE,
20948 V2DF_FTYPE_PCV2DF_V2DF,
20950 VOID_FTYPE_PV2SF_V4SF,
20951 VOID_FTYPE_PV4DI_V4DI,
20952 VOID_FTYPE_PV2DI_V2DI,
20953 VOID_FTYPE_PCHAR_V32QI,
20954 VOID_FTYPE_PCHAR_V16QI,
20955 VOID_FTYPE_PFLOAT_V8SF,
20956 VOID_FTYPE_PFLOAT_V4SF,
20957 VOID_FTYPE_PDOUBLE_V4DF,
20958 VOID_FTYPE_PDOUBLE_V2DF,
20960 VOID_FTYPE_PINT_INT,
20961 VOID_FTYPE_PV8SF_V8SF_V8SF,
20962 VOID_FTYPE_PV4DF_V4DF_V4DF,
20963 VOID_FTYPE_PV4SF_V4SF_V4SF,
20964 VOID_FTYPE_PV2DF_V2DF_V2DF
20967 /* Builtin types */
20968 enum ix86_builtin_type
20971 FLOAT128_FTYPE_FLOAT128,
20973 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20974 INT_FTYPE_V8SF_V8SF_PTEST,
20975 INT_FTYPE_V4DI_V4DI_PTEST,
20976 INT_FTYPE_V4DF_V4DF_PTEST,
20977 INT_FTYPE_V4SF_V4SF_PTEST,
20978 INT_FTYPE_V2DI_V2DI_PTEST,
20979 INT_FTYPE_V2DF_V2DF_PTEST,
21014 V4SF_FTYPE_V4SF_VEC_MERGE,
21023 V2DF_FTYPE_V2DF_VEC_MERGE,
21034 V16QI_FTYPE_V16QI_V16QI,
21035 V16QI_FTYPE_V8HI_V8HI,
21036 V8QI_FTYPE_V8QI_V8QI,
21037 V8QI_FTYPE_V4HI_V4HI,
21038 V8HI_FTYPE_V8HI_V8HI,
21039 V8HI_FTYPE_V8HI_V8HI_COUNT,
21040 V8HI_FTYPE_V16QI_V16QI,
21041 V8HI_FTYPE_V4SI_V4SI,
21042 V8HI_FTYPE_V8HI_SI_COUNT,
21043 V8SF_FTYPE_V8SF_V8SF,
21044 V8SF_FTYPE_V8SF_V8SI,
21045 V4SI_FTYPE_V4SI_V4SI,
21046 V4SI_FTYPE_V4SI_V4SI_COUNT,
21047 V4SI_FTYPE_V8HI_V8HI,
21048 V4SI_FTYPE_V4SF_V4SF,
21049 V4SI_FTYPE_V2DF_V2DF,
21050 V4SI_FTYPE_V4SI_SI_COUNT,
21051 V4HI_FTYPE_V4HI_V4HI,
21052 V4HI_FTYPE_V4HI_V4HI_COUNT,
21053 V4HI_FTYPE_V8QI_V8QI,
21054 V4HI_FTYPE_V2SI_V2SI,
21055 V4HI_FTYPE_V4HI_SI_COUNT,
21056 V4DF_FTYPE_V4DF_V4DF,
21057 V4DF_FTYPE_V4DF_V4DI,
21058 V4SF_FTYPE_V4SF_V4SF,
21059 V4SF_FTYPE_V4SF_V4SF_SWAP,
21060 V4SF_FTYPE_V4SF_V4SI,
21061 V4SF_FTYPE_V4SF_V2SI,
21062 V4SF_FTYPE_V4SF_V2DF,
21063 V4SF_FTYPE_V4SF_DI,
21064 V4SF_FTYPE_V4SF_SI,
21065 V2DI_FTYPE_V2DI_V2DI,
21066 V2DI_FTYPE_V2DI_V2DI_COUNT,
21067 V2DI_FTYPE_V16QI_V16QI,
21068 V2DI_FTYPE_V4SI_V4SI,
21069 V2DI_FTYPE_V2DI_V16QI,
21070 V2DI_FTYPE_V2DF_V2DF,
21071 V2DI_FTYPE_V2DI_SI_COUNT,
21072 V2SI_FTYPE_V2SI_V2SI,
21073 V2SI_FTYPE_V2SI_V2SI_COUNT,
21074 V2SI_FTYPE_V4HI_V4HI,
21075 V2SI_FTYPE_V2SF_V2SF,
21076 V2SI_FTYPE_V2SI_SI_COUNT,
21077 V2DF_FTYPE_V2DF_V2DF,
21078 V2DF_FTYPE_V2DF_V2DF_SWAP,
21079 V2DF_FTYPE_V2DF_V4SF,
21080 V2DF_FTYPE_V2DF_V2DI,
21081 V2DF_FTYPE_V2DF_DI,
21082 V2DF_FTYPE_V2DF_SI,
21083 V2SF_FTYPE_V2SF_V2SF,
21084 V1DI_FTYPE_V1DI_V1DI,
21085 V1DI_FTYPE_V1DI_V1DI_COUNT,
21086 V1DI_FTYPE_V8QI_V8QI,
21087 V1DI_FTYPE_V2SI_V2SI,
21088 V1DI_FTYPE_V1DI_SI_COUNT,
21089 UINT64_FTYPE_UINT64_UINT64,
21090 UINT_FTYPE_UINT_UINT,
21091 UINT_FTYPE_UINT_USHORT,
21092 UINT_FTYPE_UINT_UCHAR,
21093 UINT16_FTYPE_UINT16_INT,
21094 UINT8_FTYPE_UINT8_INT,
21095 V8HI_FTYPE_V8HI_INT,
21096 V4SI_FTYPE_V4SI_INT,
21097 V4HI_FTYPE_V4HI_INT,
21098 V8SF_FTYPE_V8SF_INT,
21099 V4SI_FTYPE_V8SI_INT,
21100 V4SF_FTYPE_V8SF_INT,
21101 V2DF_FTYPE_V4DF_INT,
21102 V4DF_FTYPE_V4DF_INT,
21103 V4SF_FTYPE_V4SF_INT,
21104 V2DI_FTYPE_V2DI_INT,
21105 V2DI2TI_FTYPE_V2DI_INT,
21106 V2DF_FTYPE_V2DF_INT,
21107 V16QI_FTYPE_V16QI_V16QI_V16QI,
21108 V8SF_FTYPE_V8SF_V8SF_V8SF,
21109 V4DF_FTYPE_V4DF_V4DF_V4DF,
21110 V4SF_FTYPE_V4SF_V4SF_V4SF,
21111 V2DF_FTYPE_V2DF_V2DF_V2DF,
21112 V16QI_FTYPE_V16QI_V16QI_INT,
21113 V8SI_FTYPE_V8SI_V8SI_INT,
21114 V8SI_FTYPE_V8SI_V4SI_INT,
21115 V8HI_FTYPE_V8HI_V8HI_INT,
21116 V8SF_FTYPE_V8SF_V8SF_INT,
21117 V8SF_FTYPE_V8SF_V4SF_INT,
21118 V4SI_FTYPE_V4SI_V4SI_INT,
21119 V4DF_FTYPE_V4DF_V4DF_INT,
21120 V4DF_FTYPE_V4DF_V2DF_INT,
21121 V4SF_FTYPE_V4SF_V4SF_INT,
21122 V2DI_FTYPE_V2DI_V2DI_INT,
21123 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21124 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21125 V2DF_FTYPE_V2DF_V2DF_INT,
21126 V2DI_FTYPE_V2DI_UINT_UINT,
21127 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21130 /* Special builtins with variable number of arguments. */
21131 static const struct builtin_description bdesc_special_args[] =
21133 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21134 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21140 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21145 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21152 /* SSE or 3DNow!A */
21153 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21154 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21171 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21174 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21177 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21178 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21183 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21210 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21213 /* Builtins with variable number of arguments. */
21214 static const struct builtin_description bdesc_args[] =
21216 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21217 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21218 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21219 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21220 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21221 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21222 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21235 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21242 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21249 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21250 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21251 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21252 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21253 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21254 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21256 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21258 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21260 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21263 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21276 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21277 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21278 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21279 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21289 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21290 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21291 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21292 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21294 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21295 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21296 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21297 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21298 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21299 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21300 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21301 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21302 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21303 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21304 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21305 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21306 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21307 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21308 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21311 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21312 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21313 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21314 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21315 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21316 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21321 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21323 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21326 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21327 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21330 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21334 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21335 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21336 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21337 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21343 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21352 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21353 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21354 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21356 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21357 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21358 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21359 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21360 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21361 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21362 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21366 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21367 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21369 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21371 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21372 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21373 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21374 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21376 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21378 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21379 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21386 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21388 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21394 /* SSE MMX or 3Dnow!A */
21395 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21396 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21397 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21399 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21400 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21401 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21402 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21404 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21405 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21407 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21428 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21429 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21430 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21436 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21437 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21438 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21439 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21467 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21471 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21473 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21474 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21476 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21482 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21484 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21485 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21486 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21487 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21488 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21489 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21490 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21491 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21502 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21503 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21505 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21507 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21508 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21520 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21521 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21522 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21547 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21552 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21553 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21554 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21555 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21556 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21557 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21560 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21561 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21562 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21563 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21564 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21565 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21567 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21568 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21569 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21570 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21578 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21579 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21581 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21584 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21585 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21588 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21589 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21591 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21592 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21593 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21594 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21595 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21596 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21599 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21600 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21601 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21602 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21603 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21604 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21606 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21607 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21608 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21609 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21610 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21611 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21612 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21613 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21614 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21615 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21616 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21617 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21618 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21619 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21620 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21621 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21622 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21623 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21624 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21625 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21626 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21627 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21628 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21629 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21632 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21633 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21636 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21637 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21638 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21639 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21640 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21641 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21642 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21643 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21645 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21647 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21648 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21649 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21650 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21651 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21652 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21653 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21654 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21655 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21656 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21657 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21658 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21659 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21661 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21662 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21663 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21664 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21665 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21666 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21667 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21668 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21669 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21670 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21671 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21672 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21675 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21676 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21677 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21678 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21680 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21681 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21682 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21685 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21686 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21687 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21688 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21689 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21692 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21693 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21694 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21695 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21698 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21699 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21701 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21702 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21703 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21704 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21707 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21710 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21711 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21714 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21715 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21718 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21724 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21725 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21726 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21727 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21728 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21729 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21730 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21731 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21732 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21733 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21734 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21735 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21768 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21781 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21783 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21785 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21825 enum multi_arg_type {
21833 static const struct builtin_description bdesc_multi_arg[] =
21835 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21836 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21837 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21838 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21839 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21840 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21841 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21842 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21844 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21845 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21846 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21847 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21848 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21849 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21850 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21851 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21853 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21854 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21855 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21856 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21858 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21859 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21860 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21861 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21863 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21864 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21865 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21866 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21868 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21869 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21870 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21871 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 }
21875 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21876 in the current target ISA to allow the user to compile particular modules
21877 with different target specific options that differ from the command line
21880 ix86_init_mmx_sse_builtins (void)
21882 const struct builtin_description * d;
21885 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21886 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21887 tree V1DI_type_node
21888 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21889 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21890 tree V2DI_type_node
21891 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21892 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21893 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21894 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21895 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21896 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21897 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21899 tree pchar_type_node = build_pointer_type (char_type_node);
21900 tree pcchar_type_node
21901 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21902 tree pfloat_type_node = build_pointer_type (float_type_node);
21903 tree pcfloat_type_node
21904 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21905 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21906 tree pcv2sf_type_node
21907 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21908 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21909 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21912 tree int_ftype_v4sf_v4sf
21913 = build_function_type_list (integer_type_node,
21914 V4SF_type_node, V4SF_type_node, NULL_TREE);
21915 tree v4si_ftype_v4sf_v4sf
21916 = build_function_type_list (V4SI_type_node,
21917 V4SF_type_node, V4SF_type_node, NULL_TREE);
21918 /* MMX/SSE/integer conversions. */
21919 tree int_ftype_v4sf
21920 = build_function_type_list (integer_type_node,
21921 V4SF_type_node, NULL_TREE);
21922 tree int64_ftype_v4sf
21923 = build_function_type_list (long_long_integer_type_node,
21924 V4SF_type_node, NULL_TREE);
21925 tree int_ftype_v8qi
21926 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21927 tree v4sf_ftype_v4sf_int
21928 = build_function_type_list (V4SF_type_node,
21929 V4SF_type_node, integer_type_node, NULL_TREE);
21930 tree v4sf_ftype_v4sf_int64
21931 = build_function_type_list (V4SF_type_node,
21932 V4SF_type_node, long_long_integer_type_node,
21934 tree v4sf_ftype_v4sf_v2si
21935 = build_function_type_list (V4SF_type_node,
21936 V4SF_type_node, V2SI_type_node, NULL_TREE);
21938 /* Miscellaneous. */
21939 tree v8qi_ftype_v4hi_v4hi
21940 = build_function_type_list (V8QI_type_node,
21941 V4HI_type_node, V4HI_type_node, NULL_TREE);
21942 tree v4hi_ftype_v2si_v2si
21943 = build_function_type_list (V4HI_type_node,
21944 V2SI_type_node, V2SI_type_node, NULL_TREE);
21945 tree v4sf_ftype_v4sf_v4sf_int
21946 = build_function_type_list (V4SF_type_node,
21947 V4SF_type_node, V4SF_type_node,
21948 integer_type_node, NULL_TREE);
21949 tree v2si_ftype_v4hi_v4hi
21950 = build_function_type_list (V2SI_type_node,
21951 V4HI_type_node, V4HI_type_node, NULL_TREE);
21952 tree v4hi_ftype_v4hi_int
21953 = build_function_type_list (V4HI_type_node,
21954 V4HI_type_node, integer_type_node, NULL_TREE);
21955 tree v2si_ftype_v2si_int
21956 = build_function_type_list (V2SI_type_node,
21957 V2SI_type_node, integer_type_node, NULL_TREE);
21958 tree v1di_ftype_v1di_int
21959 = build_function_type_list (V1DI_type_node,
21960 V1DI_type_node, integer_type_node, NULL_TREE);
21962 tree void_ftype_void
21963 = build_function_type (void_type_node, void_list_node);
21964 tree void_ftype_unsigned
21965 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21966 tree void_ftype_unsigned_unsigned
21967 = build_function_type_list (void_type_node, unsigned_type_node,
21968 unsigned_type_node, NULL_TREE);
21969 tree void_ftype_pcvoid_unsigned_unsigned
21970 = build_function_type_list (void_type_node, const_ptr_type_node,
21971 unsigned_type_node, unsigned_type_node,
21973 tree unsigned_ftype_void
21974 = build_function_type (unsigned_type_node, void_list_node);
21975 tree v2si_ftype_v4sf
21976 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21977 /* Loads/stores. */
21978 tree void_ftype_v8qi_v8qi_pchar
21979 = build_function_type_list (void_type_node,
21980 V8QI_type_node, V8QI_type_node,
21981 pchar_type_node, NULL_TREE);
21982 tree v4sf_ftype_pcfloat
21983 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21984 tree v4sf_ftype_v4sf_pcv2sf
21985 = build_function_type_list (V4SF_type_node,
21986 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21987 tree void_ftype_pv2sf_v4sf
21988 = build_function_type_list (void_type_node,
21989 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21990 tree void_ftype_pfloat_v4sf
21991 = build_function_type_list (void_type_node,
21992 pfloat_type_node, V4SF_type_node, NULL_TREE);
21993 tree void_ftype_pdi_di
21994 = build_function_type_list (void_type_node,
21995 pdi_type_node, long_long_unsigned_type_node,
21997 tree void_ftype_pv2di_v2di
21998 = build_function_type_list (void_type_node,
21999 pv2di_type_node, V2DI_type_node, NULL_TREE);
22000 /* Normal vector unops. */
22001 tree v4sf_ftype_v4sf
22002 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22003 tree v16qi_ftype_v16qi
22004 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22005 tree v8hi_ftype_v8hi
22006 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22007 tree v4si_ftype_v4si
22008 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22009 tree v8qi_ftype_v8qi
22010 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22011 tree v4hi_ftype_v4hi
22012 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22014 /* Normal vector binops. */
22015 tree v4sf_ftype_v4sf_v4sf
22016 = build_function_type_list (V4SF_type_node,
22017 V4SF_type_node, V4SF_type_node, NULL_TREE);
22018 tree v8qi_ftype_v8qi_v8qi
22019 = build_function_type_list (V8QI_type_node,
22020 V8QI_type_node, V8QI_type_node, NULL_TREE);
22021 tree v4hi_ftype_v4hi_v4hi
22022 = build_function_type_list (V4HI_type_node,
22023 V4HI_type_node, V4HI_type_node, NULL_TREE);
22024 tree v2si_ftype_v2si_v2si
22025 = build_function_type_list (V2SI_type_node,
22026 V2SI_type_node, V2SI_type_node, NULL_TREE);
22027 tree v1di_ftype_v1di_v1di
22028 = build_function_type_list (V1DI_type_node,
22029 V1DI_type_node, V1DI_type_node, NULL_TREE);
22030 tree v1di_ftype_v1di_v1di_int
22031 = build_function_type_list (V1DI_type_node,
22032 V1DI_type_node, V1DI_type_node,
22033 integer_type_node, NULL_TREE);
22034 tree v2si_ftype_v2sf
22035 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22036 tree v2sf_ftype_v2si
22037 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22038 tree v2si_ftype_v2si
22039 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22040 tree v2sf_ftype_v2sf
22041 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22042 tree v2sf_ftype_v2sf_v2sf
22043 = build_function_type_list (V2SF_type_node,
22044 V2SF_type_node, V2SF_type_node, NULL_TREE);
22045 tree v2si_ftype_v2sf_v2sf
22046 = build_function_type_list (V2SI_type_node,
22047 V2SF_type_node, V2SF_type_node, NULL_TREE);
22048 tree pint_type_node = build_pointer_type (integer_type_node);
22049 tree pdouble_type_node = build_pointer_type (double_type_node);
22050 tree pcdouble_type_node = build_pointer_type (
22051 build_type_variant (double_type_node, 1, 0));
22052 tree int_ftype_v2df_v2df
22053 = build_function_type_list (integer_type_node,
22054 V2DF_type_node, V2DF_type_node, NULL_TREE);
22056 tree void_ftype_pcvoid
22057 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22058 tree v4sf_ftype_v4si
22059 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22060 tree v4si_ftype_v4sf
22061 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22062 tree v2df_ftype_v4si
22063 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22064 tree v4si_ftype_v2df
22065 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22066 tree v4si_ftype_v2df_v2df
22067 = build_function_type_list (V4SI_type_node,
22068 V2DF_type_node, V2DF_type_node, NULL_TREE);
22069 tree v2si_ftype_v2df
22070 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22071 tree v4sf_ftype_v2df
22072 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22073 tree v2df_ftype_v2si
22074 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22075 tree v2df_ftype_v4sf
22076 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22077 tree int_ftype_v2df
22078 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22079 tree int64_ftype_v2df
22080 = build_function_type_list (long_long_integer_type_node,
22081 V2DF_type_node, NULL_TREE);
22082 tree v2df_ftype_v2df_int
22083 = build_function_type_list (V2DF_type_node,
22084 V2DF_type_node, integer_type_node, NULL_TREE);
22085 tree v2df_ftype_v2df_int64
22086 = build_function_type_list (V2DF_type_node,
22087 V2DF_type_node, long_long_integer_type_node,
22089 tree v4sf_ftype_v4sf_v2df
22090 = build_function_type_list (V4SF_type_node,
22091 V4SF_type_node, V2DF_type_node, NULL_TREE);
22092 tree v2df_ftype_v2df_v4sf
22093 = build_function_type_list (V2DF_type_node,
22094 V2DF_type_node, V4SF_type_node, NULL_TREE);
22095 tree v2df_ftype_v2df_v2df_int
22096 = build_function_type_list (V2DF_type_node,
22097 V2DF_type_node, V2DF_type_node,
22100 tree v2df_ftype_v2df_pcdouble
22101 = build_function_type_list (V2DF_type_node,
22102 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22103 tree void_ftype_pdouble_v2df
22104 = build_function_type_list (void_type_node,
22105 pdouble_type_node, V2DF_type_node, NULL_TREE);
22106 tree void_ftype_pint_int
22107 = build_function_type_list (void_type_node,
22108 pint_type_node, integer_type_node, NULL_TREE);
22109 tree void_ftype_v16qi_v16qi_pchar
22110 = build_function_type_list (void_type_node,
22111 V16QI_type_node, V16QI_type_node,
22112 pchar_type_node, NULL_TREE);
22113 tree v2df_ftype_pcdouble
22114 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22115 tree v2df_ftype_v2df_v2df
22116 = build_function_type_list (V2DF_type_node,
22117 V2DF_type_node, V2DF_type_node, NULL_TREE);
22118 tree v16qi_ftype_v16qi_v16qi
22119 = build_function_type_list (V16QI_type_node,
22120 V16QI_type_node, V16QI_type_node, NULL_TREE);
22121 tree v8hi_ftype_v8hi_v8hi
22122 = build_function_type_list (V8HI_type_node,
22123 V8HI_type_node, V8HI_type_node, NULL_TREE);
22124 tree v4si_ftype_v4si_v4si
22125 = build_function_type_list (V4SI_type_node,
22126 V4SI_type_node, V4SI_type_node, NULL_TREE);
22127 tree v2di_ftype_v2di_v2di
22128 = build_function_type_list (V2DI_type_node,
22129 V2DI_type_node, V2DI_type_node, NULL_TREE);
22130 tree v2di_ftype_v2df_v2df
22131 = build_function_type_list (V2DI_type_node,
22132 V2DF_type_node, V2DF_type_node, NULL_TREE);
22133 tree v2df_ftype_v2df
22134 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22135 tree v2di_ftype_v2di_int
22136 = build_function_type_list (V2DI_type_node,
22137 V2DI_type_node, integer_type_node, NULL_TREE);
22138 tree v2di_ftype_v2di_v2di_int
22139 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22140 V2DI_type_node, integer_type_node, NULL_TREE);
22141 tree v4si_ftype_v4si_int
22142 = build_function_type_list (V4SI_type_node,
22143 V4SI_type_node, integer_type_node, NULL_TREE);
22144 tree v8hi_ftype_v8hi_int
22145 = build_function_type_list (V8HI_type_node,
22146 V8HI_type_node, integer_type_node, NULL_TREE);
22147 tree v4si_ftype_v8hi_v8hi
22148 = build_function_type_list (V4SI_type_node,
22149 V8HI_type_node, V8HI_type_node, NULL_TREE);
22150 tree v1di_ftype_v8qi_v8qi
22151 = build_function_type_list (V1DI_type_node,
22152 V8QI_type_node, V8QI_type_node, NULL_TREE);
22153 tree v1di_ftype_v2si_v2si
22154 = build_function_type_list (V1DI_type_node,
22155 V2SI_type_node, V2SI_type_node, NULL_TREE);
22156 tree v2di_ftype_v16qi_v16qi
22157 = build_function_type_list (V2DI_type_node,
22158 V16QI_type_node, V16QI_type_node, NULL_TREE);
22159 tree v2di_ftype_v4si_v4si
22160 = build_function_type_list (V2DI_type_node,
22161 V4SI_type_node, V4SI_type_node, NULL_TREE);
22162 tree int_ftype_v16qi
22163 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22164 tree v16qi_ftype_pcchar
22165 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22166 tree void_ftype_pchar_v16qi
22167 = build_function_type_list (void_type_node,
22168 pchar_type_node, V16QI_type_node, NULL_TREE);
22170 tree v2di_ftype_v2di_unsigned_unsigned
22171 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22172 unsigned_type_node, unsigned_type_node,
22174 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22175 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22176 unsigned_type_node, unsigned_type_node,
22178 tree v2di_ftype_v2di_v16qi
22179 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22181 tree v2df_ftype_v2df_v2df_v2df
22182 = build_function_type_list (V2DF_type_node,
22183 V2DF_type_node, V2DF_type_node,
22184 V2DF_type_node, NULL_TREE);
22185 tree v4sf_ftype_v4sf_v4sf_v4sf
22186 = build_function_type_list (V4SF_type_node,
22187 V4SF_type_node, V4SF_type_node,
22188 V4SF_type_node, NULL_TREE);
22189 tree v8hi_ftype_v16qi
22190 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22192 tree v4si_ftype_v16qi
22193 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22195 tree v2di_ftype_v16qi
22196 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22198 tree v4si_ftype_v8hi
22199 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22201 tree v2di_ftype_v8hi
22202 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22204 tree v2di_ftype_v4si
22205 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22207 tree v2di_ftype_pv2di
22208 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22210 tree v16qi_ftype_v16qi_v16qi_int
22211 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22212 V16QI_type_node, integer_type_node,
22214 tree v16qi_ftype_v16qi_v16qi_v16qi
22215 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22216 V16QI_type_node, V16QI_type_node,
22218 tree v8hi_ftype_v8hi_v8hi_int
22219 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22220 V8HI_type_node, integer_type_node,
22222 tree v4si_ftype_v4si_v4si_int
22223 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22224 V4SI_type_node, integer_type_node,
22226 tree int_ftype_v2di_v2di
22227 = build_function_type_list (integer_type_node,
22228 V2DI_type_node, V2DI_type_node,
22230 tree int_ftype_v16qi_int_v16qi_int_int
22231 = build_function_type_list (integer_type_node,
22238 tree v16qi_ftype_v16qi_int_v16qi_int_int
22239 = build_function_type_list (V16QI_type_node,
22246 tree int_ftype_v16qi_v16qi_int
22247 = build_function_type_list (integer_type_node,
22254 tree v2di_ftype_v2di
22255 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22257 tree v16qi_ftype_v8hi_v8hi
22258 = build_function_type_list (V16QI_type_node,
22259 V8HI_type_node, V8HI_type_node,
22261 tree v8hi_ftype_v4si_v4si
22262 = build_function_type_list (V8HI_type_node,
22263 V4SI_type_node, V4SI_type_node,
22265 tree v8hi_ftype_v16qi_v16qi
22266 = build_function_type_list (V8HI_type_node,
22267 V16QI_type_node, V16QI_type_node,
22269 tree v4hi_ftype_v8qi_v8qi
22270 = build_function_type_list (V4HI_type_node,
22271 V8QI_type_node, V8QI_type_node,
22273 tree unsigned_ftype_unsigned_uchar
22274 = build_function_type_list (unsigned_type_node,
22275 unsigned_type_node,
22276 unsigned_char_type_node,
22278 tree unsigned_ftype_unsigned_ushort
22279 = build_function_type_list (unsigned_type_node,
22280 unsigned_type_node,
22281 short_unsigned_type_node,
22283 tree unsigned_ftype_unsigned_unsigned
22284 = build_function_type_list (unsigned_type_node,
22285 unsigned_type_node,
22286 unsigned_type_node,
22288 tree uint64_ftype_uint64_uint64
22289 = build_function_type_list (long_long_unsigned_type_node,
22290 long_long_unsigned_type_node,
22291 long_long_unsigned_type_node,
22293 tree float_ftype_float
22294 = build_function_type_list (float_type_node,
22299 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22301 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22303 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22305 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22307 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22309 tree v8sf_ftype_v8sf
22310 = build_function_type_list (V8SF_type_node,
22313 tree v8si_ftype_v8sf
22314 = build_function_type_list (V8SI_type_node,
22317 tree v8sf_ftype_v8si
22318 = build_function_type_list (V8SF_type_node,
22321 tree v4si_ftype_v4df
22322 = build_function_type_list (V4SI_type_node,
22325 tree v4df_ftype_v4df
22326 = build_function_type_list (V4DF_type_node,
22329 tree v4df_ftype_v4si
22330 = build_function_type_list (V4DF_type_node,
22333 tree v4df_ftype_v4sf
22334 = build_function_type_list (V4DF_type_node,
22337 tree v4sf_ftype_v4df
22338 = build_function_type_list (V4SF_type_node,
22341 tree v8sf_ftype_v8sf_v8sf
22342 = build_function_type_list (V8SF_type_node,
22343 V8SF_type_node, V8SF_type_node,
22345 tree v4df_ftype_v4df_v4df
22346 = build_function_type_list (V4DF_type_node,
22347 V4DF_type_node, V4DF_type_node,
22349 tree v8sf_ftype_v8sf_int
22350 = build_function_type_list (V8SF_type_node,
22351 V8SF_type_node, integer_type_node,
22353 tree v4si_ftype_v8si_int
22354 = build_function_type_list (V4SI_type_node,
22355 V8SI_type_node, integer_type_node,
22357 tree v4df_ftype_v4df_int
22358 = build_function_type_list (V4DF_type_node,
22359 V4DF_type_node, integer_type_node,
22361 tree v4sf_ftype_v8sf_int
22362 = build_function_type_list (V4SF_type_node,
22363 V8SF_type_node, integer_type_node,
22365 tree v2df_ftype_v4df_int
22366 = build_function_type_list (V2DF_type_node,
22367 V4DF_type_node, integer_type_node,
22369 tree v8sf_ftype_v8sf_v8sf_int
22370 = build_function_type_list (V8SF_type_node,
22371 V8SF_type_node, V8SF_type_node,
22374 tree v8sf_ftype_v8sf_v8sf_v8sf
22375 = build_function_type_list (V8SF_type_node,
22376 V8SF_type_node, V8SF_type_node,
22379 tree v4df_ftype_v4df_v4df_v4df
22380 = build_function_type_list (V4DF_type_node,
22381 V4DF_type_node, V4DF_type_node,
22384 tree v8si_ftype_v8si_v8si_int
22385 = build_function_type_list (V8SI_type_node,
22386 V8SI_type_node, V8SI_type_node,
22389 tree v4df_ftype_v4df_v4df_int
22390 = build_function_type_list (V4DF_type_node,
22391 V4DF_type_node, V4DF_type_node,
22394 tree v8sf_ftype_pcfloat
22395 = build_function_type_list (V8SF_type_node,
22398 tree v4df_ftype_pcdouble
22399 = build_function_type_list (V4DF_type_node,
22400 pcdouble_type_node,
22402 tree pcv4sf_type_node
22403 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22404 tree pcv2df_type_node
22405 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22406 tree v8sf_ftype_pcv4sf
22407 = build_function_type_list (V8SF_type_node,
22410 tree v4df_ftype_pcv2df
22411 = build_function_type_list (V4DF_type_node,
22414 tree v32qi_ftype_pcchar
22415 = build_function_type_list (V32QI_type_node,
22418 tree void_ftype_pchar_v32qi
22419 = build_function_type_list (void_type_node,
22420 pchar_type_node, V32QI_type_node,
22422 tree v8si_ftype_v8si_v4si_int
22423 = build_function_type_list (V8SI_type_node,
22424 V8SI_type_node, V4SI_type_node,
22427 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22428 tree void_ftype_pv4di_v4di
22429 = build_function_type_list (void_type_node,
22430 pv4di_type_node, V4DI_type_node,
22432 tree v8sf_ftype_v8sf_v4sf_int
22433 = build_function_type_list (V8SF_type_node,
22434 V8SF_type_node, V4SF_type_node,
22437 tree v4df_ftype_v4df_v2df_int
22438 = build_function_type_list (V4DF_type_node,
22439 V4DF_type_node, V2DF_type_node,
22442 tree void_ftype_pfloat_v8sf
22443 = build_function_type_list (void_type_node,
22444 pfloat_type_node, V8SF_type_node,
22446 tree void_ftype_pdouble_v4df
22447 = build_function_type_list (void_type_node,
22448 pdouble_type_node, V4DF_type_node,
22450 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22451 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22452 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22453 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22454 tree pcv8sf_type_node
22455 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22456 tree pcv4df_type_node
22457 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22458 tree v8sf_ftype_pcv8sf_v8sf
22459 = build_function_type_list (V8SF_type_node,
22460 pcv8sf_type_node, V8SF_type_node,
22462 tree v4df_ftype_pcv4df_v4df
22463 = build_function_type_list (V4DF_type_node,
22464 pcv4df_type_node, V4DF_type_node,
22466 tree v4sf_ftype_pcv4sf_v4sf
22467 = build_function_type_list (V4SF_type_node,
22468 pcv4sf_type_node, V4SF_type_node,
22470 tree v2df_ftype_pcv2df_v2df
22471 = build_function_type_list (V2DF_type_node,
22472 pcv2df_type_node, V2DF_type_node,
22474 tree void_ftype_pv8sf_v8sf_v8sf
22475 = build_function_type_list (void_type_node,
22476 pv8sf_type_node, V8SF_type_node,
22479 tree void_ftype_pv4df_v4df_v4df
22480 = build_function_type_list (void_type_node,
22481 pv4df_type_node, V4DF_type_node,
22484 tree void_ftype_pv4sf_v4sf_v4sf
22485 = build_function_type_list (void_type_node,
22486 pv4sf_type_node, V4SF_type_node,
22489 tree void_ftype_pv2df_v2df_v2df
22490 = build_function_type_list (void_type_node,
22491 pv2df_type_node, V2DF_type_node,
22494 tree v4df_ftype_v2df
22495 = build_function_type_list (V4DF_type_node,
22498 tree v8sf_ftype_v4sf
22499 = build_function_type_list (V8SF_type_node,
22502 tree v8si_ftype_v4si
22503 = build_function_type_list (V8SI_type_node,
22506 tree v2df_ftype_v4df
22507 = build_function_type_list (V2DF_type_node,
22510 tree v4sf_ftype_v8sf
22511 = build_function_type_list (V4SF_type_node,
22514 tree v4si_ftype_v8si
22515 = build_function_type_list (V4SI_type_node,
22518 tree int_ftype_v4df
22519 = build_function_type_list (integer_type_node,
22522 tree int_ftype_v8sf
22523 = build_function_type_list (integer_type_node,
22526 tree int_ftype_v8sf_v8sf
22527 = build_function_type_list (integer_type_node,
22528 V8SF_type_node, V8SF_type_node,
22530 tree int_ftype_v4di_v4di
22531 = build_function_type_list (integer_type_node,
22532 V4DI_type_node, V4DI_type_node,
22534 tree int_ftype_v4df_v4df
22535 = build_function_type_list (integer_type_node,
22536 V4DF_type_node, V4DF_type_node,
22538 tree v8sf_ftype_v8sf_v8si
22539 = build_function_type_list (V8SF_type_node,
22540 V8SF_type_node, V8SI_type_node,
22542 tree v4df_ftype_v4df_v4di
22543 = build_function_type_list (V4DF_type_node,
22544 V4DF_type_node, V4DI_type_node,
22546 tree v4sf_ftype_v4sf_v4si
22547 = build_function_type_list (V4SF_type_node,
22548 V4SF_type_node, V4SI_type_node, NULL_TREE);
22549 tree v2df_ftype_v2df_v2di
22550 = build_function_type_list (V2DF_type_node,
22551 V2DF_type_node, V2DI_type_node, NULL_TREE);
22553 /* Integer intrinsics. */
22554 tree uint64_ftype_void
22555 = build_function_type (long_long_unsigned_type_node,
22558 = build_function_type_list (integer_type_node,
22559 integer_type_node, NULL_TREE);
22560 tree int64_ftype_int64
22561 = build_function_type_list (long_long_integer_type_node,
22562 long_long_integer_type_node,
22564 tree uint64_ftype_int
22565 = build_function_type_list (long_long_unsigned_type_node,
22566 integer_type_node, NULL_TREE);
22567 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
22568 tree uint64_ftype_punsigned
22569 = build_function_type_list (long_long_unsigned_type_node,
22570 punsigned_type_node, NULL_TREE);
22571 tree ushort_ftype_ushort_int
22572 = build_function_type_list (short_unsigned_type_node,
22573 short_unsigned_type_node,
22576 tree uchar_ftype_uchar_int
22577 = build_function_type_list (unsigned_char_type_node,
22578 unsigned_char_type_node,
22584 /* Add all special builtins with variable number of operands. */
22585 for (i = 0, d = bdesc_special_args;
22586 i < ARRAY_SIZE (bdesc_special_args);
22594 switch ((enum ix86_special_builtin_type) d->flag)
22596 case VOID_FTYPE_VOID:
22597 type = void_ftype_void;
22599 case UINT64_FTYPE_VOID:
22600 type = uint64_ftype_void;
22602 case UINT64_FTYPE_PUNSIGNED:
22603 type = uint64_ftype_punsigned;
22605 case V32QI_FTYPE_PCCHAR:
22606 type = v32qi_ftype_pcchar;
22608 case V16QI_FTYPE_PCCHAR:
22609 type = v16qi_ftype_pcchar;
22611 case V8SF_FTYPE_PCV4SF:
22612 type = v8sf_ftype_pcv4sf;
22614 case V8SF_FTYPE_PCFLOAT:
22615 type = v8sf_ftype_pcfloat;
22617 case V4DF_FTYPE_PCV2DF:
22618 type = v4df_ftype_pcv2df;
22620 case V4DF_FTYPE_PCDOUBLE:
22621 type = v4df_ftype_pcdouble;
22623 case V4SF_FTYPE_PCFLOAT:
22624 type = v4sf_ftype_pcfloat;
22626 case V2DI_FTYPE_PV2DI:
22627 type = v2di_ftype_pv2di;
22629 case V2DF_FTYPE_PCDOUBLE:
22630 type = v2df_ftype_pcdouble;
22632 case V8SF_FTYPE_PCV8SF_V8SF:
22633 type = v8sf_ftype_pcv8sf_v8sf;
22635 case V4DF_FTYPE_PCV4DF_V4DF:
22636 type = v4df_ftype_pcv4df_v4df;
22638 case V4SF_FTYPE_V4SF_PCV2SF:
22639 type = v4sf_ftype_v4sf_pcv2sf;
22641 case V4SF_FTYPE_PCV4SF_V4SF:
22642 type = v4sf_ftype_pcv4sf_v4sf;
22644 case V2DF_FTYPE_V2DF_PCDOUBLE:
22645 type = v2df_ftype_v2df_pcdouble;
22647 case V2DF_FTYPE_PCV2DF_V2DF:
22648 type = v2df_ftype_pcv2df_v2df;
22650 case VOID_FTYPE_PV2SF_V4SF:
22651 type = void_ftype_pv2sf_v4sf;
22653 case VOID_FTYPE_PV4DI_V4DI:
22654 type = void_ftype_pv4di_v4di;
22656 case VOID_FTYPE_PV2DI_V2DI:
22657 type = void_ftype_pv2di_v2di;
22659 case VOID_FTYPE_PCHAR_V32QI:
22660 type = void_ftype_pchar_v32qi;
22662 case VOID_FTYPE_PCHAR_V16QI:
22663 type = void_ftype_pchar_v16qi;
22665 case VOID_FTYPE_PFLOAT_V8SF:
22666 type = void_ftype_pfloat_v8sf;
22668 case VOID_FTYPE_PFLOAT_V4SF:
22669 type = void_ftype_pfloat_v4sf;
22671 case VOID_FTYPE_PDOUBLE_V4DF:
22672 type = void_ftype_pdouble_v4df;
22674 case VOID_FTYPE_PDOUBLE_V2DF:
22675 type = void_ftype_pdouble_v2df;
22677 case VOID_FTYPE_PDI_DI:
22678 type = void_ftype_pdi_di;
22680 case VOID_FTYPE_PINT_INT:
22681 type = void_ftype_pint_int;
22683 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22684 type = void_ftype_pv8sf_v8sf_v8sf;
22686 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22687 type = void_ftype_pv4df_v4df_v4df;
22689 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22690 type = void_ftype_pv4sf_v4sf_v4sf;
22692 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22693 type = void_ftype_pv2df_v2df_v2df;
22696 gcc_unreachable ();
22699 def_builtin (d->mask, d->name, type, d->code);
22702 /* Add all builtins with variable number of operands. */
22703 for (i = 0, d = bdesc_args;
22704 i < ARRAY_SIZE (bdesc_args);
22712 switch ((enum ix86_builtin_type) d->flag)
22714 case FLOAT_FTYPE_FLOAT:
22715 type = float_ftype_float;
22717 case INT_FTYPE_V8SF_V8SF_PTEST:
22718 type = int_ftype_v8sf_v8sf;
22720 case INT_FTYPE_V4DI_V4DI_PTEST:
22721 type = int_ftype_v4di_v4di;
22723 case INT_FTYPE_V4DF_V4DF_PTEST:
22724 type = int_ftype_v4df_v4df;
22726 case INT_FTYPE_V4SF_V4SF_PTEST:
22727 type = int_ftype_v4sf_v4sf;
22729 case INT_FTYPE_V2DI_V2DI_PTEST:
22730 type = int_ftype_v2di_v2di;
22732 case INT_FTYPE_V2DF_V2DF_PTEST:
22733 type = int_ftype_v2df_v2df;
22735 case INT_FTYPE_INT:
22736 type = int_ftype_int;
22738 case UINT64_FTYPE_INT:
22739 type = uint64_ftype_int;
22741 case INT64_FTYPE_INT64:
22742 type = int64_ftype_int64;
22744 case INT64_FTYPE_V4SF:
22745 type = int64_ftype_v4sf;
22747 case INT64_FTYPE_V2DF:
22748 type = int64_ftype_v2df;
22750 case INT_FTYPE_V16QI:
22751 type = int_ftype_v16qi;
22753 case INT_FTYPE_V8QI:
22754 type = int_ftype_v8qi;
22756 case INT_FTYPE_V8SF:
22757 type = int_ftype_v8sf;
22759 case INT_FTYPE_V4DF:
22760 type = int_ftype_v4df;
22762 case INT_FTYPE_V4SF:
22763 type = int_ftype_v4sf;
22765 case INT_FTYPE_V2DF:
22766 type = int_ftype_v2df;
22768 case V16QI_FTYPE_V16QI:
22769 type = v16qi_ftype_v16qi;
22771 case V8SI_FTYPE_V8SF:
22772 type = v8si_ftype_v8sf;
22774 case V8SI_FTYPE_V4SI:
22775 type = v8si_ftype_v4si;
22777 case V8HI_FTYPE_V8HI:
22778 type = v8hi_ftype_v8hi;
22780 case V8HI_FTYPE_V16QI:
22781 type = v8hi_ftype_v16qi;
22783 case V8QI_FTYPE_V8QI:
22784 type = v8qi_ftype_v8qi;
22786 case V8SF_FTYPE_V8SF:
22787 type = v8sf_ftype_v8sf;
22789 case V8SF_FTYPE_V8SI:
22790 type = v8sf_ftype_v8si;
22792 case V8SF_FTYPE_V4SF:
22793 type = v8sf_ftype_v4sf;
22795 case V4SI_FTYPE_V4DF:
22796 type = v4si_ftype_v4df;
22798 case V4SI_FTYPE_V4SI:
22799 type = v4si_ftype_v4si;
22801 case V4SI_FTYPE_V16QI:
22802 type = v4si_ftype_v16qi;
22804 case V4SI_FTYPE_V8SI:
22805 type = v4si_ftype_v8si;
22807 case V4SI_FTYPE_V8HI:
22808 type = v4si_ftype_v8hi;
22810 case V4SI_FTYPE_V4SF:
22811 type = v4si_ftype_v4sf;
22813 case V4SI_FTYPE_V2DF:
22814 type = v4si_ftype_v2df;
22816 case V4HI_FTYPE_V4HI:
22817 type = v4hi_ftype_v4hi;
22819 case V4DF_FTYPE_V4DF:
22820 type = v4df_ftype_v4df;
22822 case V4DF_FTYPE_V4SI:
22823 type = v4df_ftype_v4si;
22825 case V4DF_FTYPE_V4SF:
22826 type = v4df_ftype_v4sf;
22828 case V4DF_FTYPE_V2DF:
22829 type = v4df_ftype_v2df;
22831 case V4SF_FTYPE_V4SF:
22832 case V4SF_FTYPE_V4SF_VEC_MERGE:
22833 type = v4sf_ftype_v4sf;
22835 case V4SF_FTYPE_V8SF:
22836 type = v4sf_ftype_v8sf;
22838 case V4SF_FTYPE_V4SI:
22839 type = v4sf_ftype_v4si;
22841 case V4SF_FTYPE_V4DF:
22842 type = v4sf_ftype_v4df;
22844 case V4SF_FTYPE_V2DF:
22845 type = v4sf_ftype_v2df;
22847 case V2DI_FTYPE_V2DI:
22848 type = v2di_ftype_v2di;
22850 case V2DI_FTYPE_V16QI:
22851 type = v2di_ftype_v16qi;
22853 case V2DI_FTYPE_V8HI:
22854 type = v2di_ftype_v8hi;
22856 case V2DI_FTYPE_V4SI:
22857 type = v2di_ftype_v4si;
22859 case V2SI_FTYPE_V2SI:
22860 type = v2si_ftype_v2si;
22862 case V2SI_FTYPE_V4SF:
22863 type = v2si_ftype_v4sf;
22865 case V2SI_FTYPE_V2DF:
22866 type = v2si_ftype_v2df;
22868 case V2SI_FTYPE_V2SF:
22869 type = v2si_ftype_v2sf;
22871 case V2DF_FTYPE_V4DF:
22872 type = v2df_ftype_v4df;
22874 case V2DF_FTYPE_V4SF:
22875 type = v2df_ftype_v4sf;
22877 case V2DF_FTYPE_V2DF:
22878 case V2DF_FTYPE_V2DF_VEC_MERGE:
22879 type = v2df_ftype_v2df;
22881 case V2DF_FTYPE_V2SI:
22882 type = v2df_ftype_v2si;
22884 case V2DF_FTYPE_V4SI:
22885 type = v2df_ftype_v4si;
22887 case V2SF_FTYPE_V2SF:
22888 type = v2sf_ftype_v2sf;
22890 case V2SF_FTYPE_V2SI:
22891 type = v2sf_ftype_v2si;
22893 case V16QI_FTYPE_V16QI_V16QI:
22894 type = v16qi_ftype_v16qi_v16qi;
22896 case V16QI_FTYPE_V8HI_V8HI:
22897 type = v16qi_ftype_v8hi_v8hi;
22899 case V8QI_FTYPE_V8QI_V8QI:
22900 type = v8qi_ftype_v8qi_v8qi;
22902 case V8QI_FTYPE_V4HI_V4HI:
22903 type = v8qi_ftype_v4hi_v4hi;
22905 case V8HI_FTYPE_V8HI_V8HI:
22906 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22907 type = v8hi_ftype_v8hi_v8hi;
22909 case V8HI_FTYPE_V16QI_V16QI:
22910 type = v8hi_ftype_v16qi_v16qi;
22912 case V8HI_FTYPE_V4SI_V4SI:
22913 type = v8hi_ftype_v4si_v4si;
22915 case V8HI_FTYPE_V8HI_SI_COUNT:
22916 type = v8hi_ftype_v8hi_int;
22918 case V8SF_FTYPE_V8SF_V8SF:
22919 type = v8sf_ftype_v8sf_v8sf;
22921 case V8SF_FTYPE_V8SF_V8SI:
22922 type = v8sf_ftype_v8sf_v8si;
22924 case V4SI_FTYPE_V4SI_V4SI:
22925 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22926 type = v4si_ftype_v4si_v4si;
22928 case V4SI_FTYPE_V8HI_V8HI:
22929 type = v4si_ftype_v8hi_v8hi;
22931 case V4SI_FTYPE_V4SF_V4SF:
22932 type = v4si_ftype_v4sf_v4sf;
22934 case V4SI_FTYPE_V2DF_V2DF:
22935 type = v4si_ftype_v2df_v2df;
22937 case V4SI_FTYPE_V4SI_SI_COUNT:
22938 type = v4si_ftype_v4si_int;
22940 case V4HI_FTYPE_V4HI_V4HI:
22941 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22942 type = v4hi_ftype_v4hi_v4hi;
22944 case V4HI_FTYPE_V8QI_V8QI:
22945 type = v4hi_ftype_v8qi_v8qi;
22947 case V4HI_FTYPE_V2SI_V2SI:
22948 type = v4hi_ftype_v2si_v2si;
22950 case V4HI_FTYPE_V4HI_SI_COUNT:
22951 type = v4hi_ftype_v4hi_int;
22953 case V4DF_FTYPE_V4DF_V4DF:
22954 type = v4df_ftype_v4df_v4df;
22956 case V4DF_FTYPE_V4DF_V4DI:
22957 type = v4df_ftype_v4df_v4di;
22959 case V4SF_FTYPE_V4SF_V4SF:
22960 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22961 type = v4sf_ftype_v4sf_v4sf;
22963 case V4SF_FTYPE_V4SF_V4SI:
22964 type = v4sf_ftype_v4sf_v4si;
22966 case V4SF_FTYPE_V4SF_V2SI:
22967 type = v4sf_ftype_v4sf_v2si;
22969 case V4SF_FTYPE_V4SF_V2DF:
22970 type = v4sf_ftype_v4sf_v2df;
22972 case V4SF_FTYPE_V4SF_DI:
22973 type = v4sf_ftype_v4sf_int64;
22975 case V4SF_FTYPE_V4SF_SI:
22976 type = v4sf_ftype_v4sf_int;
22978 case V2DI_FTYPE_V2DI_V2DI:
22979 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22980 type = v2di_ftype_v2di_v2di;
22982 case V2DI_FTYPE_V16QI_V16QI:
22983 type = v2di_ftype_v16qi_v16qi;
22985 case V2DI_FTYPE_V4SI_V4SI:
22986 type = v2di_ftype_v4si_v4si;
22988 case V2DI_FTYPE_V2DI_V16QI:
22989 type = v2di_ftype_v2di_v16qi;
22991 case V2DI_FTYPE_V2DF_V2DF:
22992 type = v2di_ftype_v2df_v2df;
22994 case V2DI_FTYPE_V2DI_SI_COUNT:
22995 type = v2di_ftype_v2di_int;
22997 case V2SI_FTYPE_V2SI_V2SI:
22998 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22999 type = v2si_ftype_v2si_v2si;
23001 case V2SI_FTYPE_V4HI_V4HI:
23002 type = v2si_ftype_v4hi_v4hi;
23004 case V2SI_FTYPE_V2SF_V2SF:
23005 type = v2si_ftype_v2sf_v2sf;
23007 case V2SI_FTYPE_V2SI_SI_COUNT:
23008 type = v2si_ftype_v2si_int;
23010 case V2DF_FTYPE_V2DF_V2DF:
23011 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23012 type = v2df_ftype_v2df_v2df;
23014 case V2DF_FTYPE_V2DF_V4SF:
23015 type = v2df_ftype_v2df_v4sf;
23017 case V2DF_FTYPE_V2DF_V2DI:
23018 type = v2df_ftype_v2df_v2di;
23020 case V2DF_FTYPE_V2DF_DI:
23021 type = v2df_ftype_v2df_int64;
23023 case V2DF_FTYPE_V2DF_SI:
23024 type = v2df_ftype_v2df_int;
23026 case V2SF_FTYPE_V2SF_V2SF:
23027 type = v2sf_ftype_v2sf_v2sf;
23029 case V1DI_FTYPE_V1DI_V1DI:
23030 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23031 type = v1di_ftype_v1di_v1di;
23033 case V1DI_FTYPE_V8QI_V8QI:
23034 type = v1di_ftype_v8qi_v8qi;
23036 case V1DI_FTYPE_V2SI_V2SI:
23037 type = v1di_ftype_v2si_v2si;
23039 case V1DI_FTYPE_V1DI_SI_COUNT:
23040 type = v1di_ftype_v1di_int;
23042 case UINT64_FTYPE_UINT64_UINT64:
23043 type = uint64_ftype_uint64_uint64;
23045 case UINT_FTYPE_UINT_UINT:
23046 type = unsigned_ftype_unsigned_unsigned;
23048 case UINT_FTYPE_UINT_USHORT:
23049 type = unsigned_ftype_unsigned_ushort;
23051 case UINT_FTYPE_UINT_UCHAR:
23052 type = unsigned_ftype_unsigned_uchar;
23054 case UINT16_FTYPE_UINT16_INT:
23055 type = ushort_ftype_ushort_int;
23057 case UINT8_FTYPE_UINT8_INT:
23058 type = uchar_ftype_uchar_int;
23060 case V8HI_FTYPE_V8HI_INT:
23061 type = v8hi_ftype_v8hi_int;
23063 case V8SF_FTYPE_V8SF_INT:
23064 type = v8sf_ftype_v8sf_int;
23066 case V4SI_FTYPE_V4SI_INT:
23067 type = v4si_ftype_v4si_int;
23069 case V4SI_FTYPE_V8SI_INT:
23070 type = v4si_ftype_v8si_int;
23072 case V4HI_FTYPE_V4HI_INT:
23073 type = v4hi_ftype_v4hi_int;
23075 case V4DF_FTYPE_V4DF_INT:
23076 type = v4df_ftype_v4df_int;
23078 case V4SF_FTYPE_V4SF_INT:
23079 type = v4sf_ftype_v4sf_int;
23081 case V4SF_FTYPE_V8SF_INT:
23082 type = v4sf_ftype_v8sf_int;
23084 case V2DI_FTYPE_V2DI_INT:
23085 case V2DI2TI_FTYPE_V2DI_INT:
23086 type = v2di_ftype_v2di_int;
23088 case V2DF_FTYPE_V2DF_INT:
23089 type = v2df_ftype_v2df_int;
23091 case V2DF_FTYPE_V4DF_INT:
23092 type = v2df_ftype_v4df_int;
23094 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23095 type = v16qi_ftype_v16qi_v16qi_v16qi;
23097 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23098 type = v8sf_ftype_v8sf_v8sf_v8sf;
23100 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23101 type = v4df_ftype_v4df_v4df_v4df;
23103 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23104 type = v4sf_ftype_v4sf_v4sf_v4sf;
23106 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23107 type = v2df_ftype_v2df_v2df_v2df;
23109 case V16QI_FTYPE_V16QI_V16QI_INT:
23110 type = v16qi_ftype_v16qi_v16qi_int;
23112 case V8SI_FTYPE_V8SI_V8SI_INT:
23113 type = v8si_ftype_v8si_v8si_int;
23115 case V8SI_FTYPE_V8SI_V4SI_INT:
23116 type = v8si_ftype_v8si_v4si_int;
23118 case V8HI_FTYPE_V8HI_V8HI_INT:
23119 type = v8hi_ftype_v8hi_v8hi_int;
23121 case V8SF_FTYPE_V8SF_V8SF_INT:
23122 type = v8sf_ftype_v8sf_v8sf_int;
23124 case V8SF_FTYPE_V8SF_V4SF_INT:
23125 type = v8sf_ftype_v8sf_v4sf_int;
23127 case V4SI_FTYPE_V4SI_V4SI_INT:
23128 type = v4si_ftype_v4si_v4si_int;
23130 case V4DF_FTYPE_V4DF_V4DF_INT:
23131 type = v4df_ftype_v4df_v4df_int;
23133 case V4DF_FTYPE_V4DF_V2DF_INT:
23134 type = v4df_ftype_v4df_v2df_int;
23136 case V4SF_FTYPE_V4SF_V4SF_INT:
23137 type = v4sf_ftype_v4sf_v4sf_int;
23139 case V2DI_FTYPE_V2DI_V2DI_INT:
23140 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23141 type = v2di_ftype_v2di_v2di_int;
23143 case V2DF_FTYPE_V2DF_V2DF_INT:
23144 type = v2df_ftype_v2df_v2df_int;
23146 case V2DI_FTYPE_V2DI_UINT_UINT:
23147 type = v2di_ftype_v2di_unsigned_unsigned;
23149 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23150 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23152 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23153 type = v1di_ftype_v1di_v1di_int;
23156 gcc_unreachable ();
23159 def_builtin_const (d->mask, d->name, type, d->code);
23162 /* pcmpestr[im] insns. */
23163 for (i = 0, d = bdesc_pcmpestr;
23164 i < ARRAY_SIZE (bdesc_pcmpestr);
23167 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23168 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23170 ftype = int_ftype_v16qi_int_v16qi_int_int;
23171 def_builtin_const (d->mask, d->name, ftype, d->code);
23174 /* pcmpistr[im] insns. */
23175 for (i = 0, d = bdesc_pcmpistr;
23176 i < ARRAY_SIZE (bdesc_pcmpistr);
23179 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23180 ftype = v16qi_ftype_v16qi_v16qi_int;
23182 ftype = int_ftype_v16qi_v16qi_int;
23183 def_builtin_const (d->mask, d->name, ftype, d->code);
23186 /* comi/ucomi insns. */
23187 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23188 if (d->mask == OPTION_MASK_ISA_SSE2)
23189 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23191 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23194 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23195 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23197 /* SSE or 3DNow!A */
23198 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23201 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23203 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23204 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23207 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23208 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23211 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23212 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23213 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23214 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23215 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23216 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23219 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23222 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23223 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23225 /* Access to the vec_init patterns. */
23226 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23227 integer_type_node, NULL_TREE);
23228 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23230 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23231 short_integer_type_node,
23232 short_integer_type_node,
23233 short_integer_type_node, NULL_TREE);
23234 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23236 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23237 char_type_node, char_type_node,
23238 char_type_node, char_type_node,
23239 char_type_node, char_type_node,
23240 char_type_node, NULL_TREE);
23241 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23243 /* Access to the vec_extract patterns. */
23244 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23245 integer_type_node, NULL_TREE);
23246 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23248 ftype = build_function_type_list (long_long_integer_type_node,
23249 V2DI_type_node, integer_type_node,
23251 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23253 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23254 integer_type_node, NULL_TREE);
23255 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23257 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23258 integer_type_node, NULL_TREE);
23259 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23261 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23262 integer_type_node, NULL_TREE);
23263 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23265 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23266 integer_type_node, NULL_TREE);
23267 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23269 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23270 integer_type_node, NULL_TREE);
23271 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23273 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23274 integer_type_node, NULL_TREE);
23275 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23277 /* Access to the vec_set patterns. */
23278 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23280 integer_type_node, NULL_TREE);
23281 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23283 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23285 integer_type_node, NULL_TREE);
23286 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23288 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23290 integer_type_node, NULL_TREE);
23291 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23293 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23295 integer_type_node, NULL_TREE);
23296 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23298 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23300 integer_type_node, NULL_TREE);
23301 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23303 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23305 integer_type_node, NULL_TREE);
23306 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23307 /* Add FMA4 multi-arg argument instructions */
23308 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23310 tree mtype = NULL_TREE;
23315 switch ((enum multi_arg_type)d->flag)
23317 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23318 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23319 case MULTI_ARG_3_SF2: mtype = v8sf_ftype_v8sf_v8sf_v8sf; break;
23320 case MULTI_ARG_3_DF2: mtype = v4df_ftype_v4df_v4df_v4df; break;
23322 case MULTI_ARG_UNKNOWN:
23324 gcc_unreachable ();
23328 def_builtin_const (d->mask, d->name, mtype, d->code);
23332 /* Internal method for ix86_init_builtins. */
23335 ix86_init_builtins_va_builtins_abi (void)
23337 tree ms_va_ref, sysv_va_ref;
23338 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23339 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23340 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23341 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23345 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23346 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23347 ms_va_ref = build_reference_type (ms_va_list_type_node);
23349 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23352 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23353 fnvoid_va_start_ms =
23354 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23355 fnvoid_va_end_sysv =
23356 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23357 fnvoid_va_start_sysv =
23358 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23360 fnvoid_va_copy_ms =
23361 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23363 fnvoid_va_copy_sysv =
23364 build_function_type_list (void_type_node, sysv_va_ref,
23365 sysv_va_ref, NULL_TREE);
23367 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23368 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23369 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23370 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23371 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23372 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23373 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23374 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23375 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23376 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23377 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23378 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23382 ix86_init_builtins (void)
23384 tree float128_type_node = make_node (REAL_TYPE);
23387 /* The __float80 type. */
23388 if (TYPE_MODE (long_double_type_node) == XFmode)
23389 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23393 /* The __float80 type. */
23394 tree float80_type_node = make_node (REAL_TYPE);
23396 TYPE_PRECISION (float80_type_node) = 80;
23397 layout_type (float80_type_node);
23398 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23402 /* The __float128 type. */
23403 TYPE_PRECISION (float128_type_node) = 128;
23404 layout_type (float128_type_node);
23405 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23408 /* TFmode support builtins. */
23409 ftype = build_function_type (float128_type_node, void_list_node);
23410 decl = add_builtin_function ("__builtin_infq", ftype,
23411 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23413 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23415 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23416 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23418 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23420 /* We will expand them to normal call if SSE2 isn't available since
23421 they are used by libgcc. */
23422 ftype = build_function_type_list (float128_type_node,
23423 float128_type_node,
23425 decl = add_builtin_function ("__builtin_fabsq", ftype,
23426 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23427 "__fabstf2", NULL_TREE);
23428 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23429 TREE_READONLY (decl) = 1;
23431 ftype = build_function_type_list (float128_type_node,
23432 float128_type_node,
23433 float128_type_node,
23435 decl = add_builtin_function ("__builtin_copysignq", ftype,
23436 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23437 "__copysigntf3", NULL_TREE);
23438 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23439 TREE_READONLY (decl) = 1;
23441 ix86_init_mmx_sse_builtins ();
23443 ix86_init_builtins_va_builtins_abi ();
23446 /* Errors in the source file can cause expand_expr to return const0_rtx
23447 where we expect a vector. To avoid crashing, use one of the vector
23448 clear instructions. */
23450 safe_vector_operand (rtx x, enum machine_mode mode)
23452 if (x == const0_rtx)
23453 x = CONST0_RTX (mode);
23457 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23460 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23463 tree arg0 = CALL_EXPR_ARG (exp, 0);
23464 tree arg1 = CALL_EXPR_ARG (exp, 1);
23465 rtx op0 = expand_normal (arg0);
23466 rtx op1 = expand_normal (arg1);
23467 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23468 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23469 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23471 if (VECTOR_MODE_P (mode0))
23472 op0 = safe_vector_operand (op0, mode0);
23473 if (VECTOR_MODE_P (mode1))
23474 op1 = safe_vector_operand (op1, mode1);
23476 if (optimize || !target
23477 || GET_MODE (target) != tmode
23478 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23479 target = gen_reg_rtx (tmode);
23481 if (GET_MODE (op1) == SImode && mode1 == TImode)
23483 rtx x = gen_reg_rtx (V4SImode);
23484 emit_insn (gen_sse2_loadd (x, op1));
23485 op1 = gen_lowpart (TImode, x);
23488 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23489 op0 = copy_to_mode_reg (mode0, op0);
23490 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23491 op1 = copy_to_mode_reg (mode1, op1);
23493 pat = GEN_FCN (icode) (target, op0, op1);
23502 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23505 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23506 enum multi_arg_type m_type,
23507 enum rtx_code sub_code)
23512 bool comparison_p = false;
23514 bool last_arg_constant = false;
23515 int num_memory = 0;
23518 enum machine_mode mode;
23521 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23525 case MULTI_ARG_3_SF:
23526 case MULTI_ARG_3_DF:
23527 case MULTI_ARG_3_SF2:
23528 case MULTI_ARG_3_DF2:
23532 case MULTI_ARG_UNKNOWN:
23534 gcc_unreachable ();
23537 if (optimize || !target
23538 || GET_MODE (target) != tmode
23539 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23540 target = gen_reg_rtx (tmode);
23542 gcc_assert (nargs <= 4);
23544 for (i = 0; i < nargs; i++)
23546 tree arg = CALL_EXPR_ARG (exp, i);
23547 rtx op = expand_normal (arg);
23548 int adjust = (comparison_p) ? 1 : 0;
23549 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23551 if (last_arg_constant && i == nargs-1)
23553 if (!CONST_INT_P (op))
23555 error ("last argument must be an immediate");
23556 return gen_reg_rtx (tmode);
23561 if (VECTOR_MODE_P (mode))
23562 op = safe_vector_operand (op, mode);
23564 /* If we aren't optimizing, only allow one memory operand to be
23566 if (memory_operand (op, mode))
23569 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23572 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23574 op = force_reg (mode, op);
23578 args[i].mode = mode;
23584 pat = GEN_FCN (icode) (target, args[0].op);
23589 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23590 GEN_INT ((int)sub_code));
23591 else if (! comparison_p)
23592 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23595 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23599 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23604 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23608 gcc_unreachable ();
23618 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23619 insns with vec_merge. */
23622 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23626 tree arg0 = CALL_EXPR_ARG (exp, 0);
23627 rtx op1, op0 = expand_normal (arg0);
23628 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23629 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23631 if (optimize || !target
23632 || GET_MODE (target) != tmode
23633 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23634 target = gen_reg_rtx (tmode);
23636 if (VECTOR_MODE_P (mode0))
23637 op0 = safe_vector_operand (op0, mode0);
23639 if ((optimize && !register_operand (op0, mode0))
23640 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23641 op0 = copy_to_mode_reg (mode0, op0);
23644 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23645 op1 = copy_to_mode_reg (mode0, op1);
23647 pat = GEN_FCN (icode) (target, op0, op1);
23654 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23657 ix86_expand_sse_compare (const struct builtin_description *d,
23658 tree exp, rtx target, bool swap)
23661 tree arg0 = CALL_EXPR_ARG (exp, 0);
23662 tree arg1 = CALL_EXPR_ARG (exp, 1);
23663 rtx op0 = expand_normal (arg0);
23664 rtx op1 = expand_normal (arg1);
23666 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23667 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23668 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23669 enum rtx_code comparison = d->comparison;
23671 if (VECTOR_MODE_P (mode0))
23672 op0 = safe_vector_operand (op0, mode0);
23673 if (VECTOR_MODE_P (mode1))
23674 op1 = safe_vector_operand (op1, mode1);
23676 /* Swap operands if we have a comparison that isn't available in
23680 rtx tmp = gen_reg_rtx (mode1);
23681 emit_move_insn (tmp, op1);
23686 if (optimize || !target
23687 || GET_MODE (target) != tmode
23688 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23689 target = gen_reg_rtx (tmode);
23691 if ((optimize && !register_operand (op0, mode0))
23692 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23693 op0 = copy_to_mode_reg (mode0, op0);
23694 if ((optimize && !register_operand (op1, mode1))
23695 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23696 op1 = copy_to_mode_reg (mode1, op1);
23698 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23699 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23706 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23709 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23713 tree arg0 = CALL_EXPR_ARG (exp, 0);
23714 tree arg1 = CALL_EXPR_ARG (exp, 1);
23715 rtx op0 = expand_normal (arg0);
23716 rtx op1 = expand_normal (arg1);
23717 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23718 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23719 enum rtx_code comparison = d->comparison;
23721 if (VECTOR_MODE_P (mode0))
23722 op0 = safe_vector_operand (op0, mode0);
23723 if (VECTOR_MODE_P (mode1))
23724 op1 = safe_vector_operand (op1, mode1);
23726 /* Swap operands if we have a comparison that isn't available in
23728 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23735 target = gen_reg_rtx (SImode);
23736 emit_move_insn (target, const0_rtx);
23737 target = gen_rtx_SUBREG (QImode, target, 0);
23739 if ((optimize && !register_operand (op0, mode0))
23740 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23741 op0 = copy_to_mode_reg (mode0, op0);
23742 if ((optimize && !register_operand (op1, mode1))
23743 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23744 op1 = copy_to_mode_reg (mode1, op1);
23746 pat = GEN_FCN (d->icode) (op0, op1);
23750 emit_insn (gen_rtx_SET (VOIDmode,
23751 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23752 gen_rtx_fmt_ee (comparison, QImode,
23756 return SUBREG_REG (target);
23759 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23762 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23766 tree arg0 = CALL_EXPR_ARG (exp, 0);
23767 tree arg1 = CALL_EXPR_ARG (exp, 1);
23768 rtx op0 = expand_normal (arg0);
23769 rtx op1 = expand_normal (arg1);
23770 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23771 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23772 enum rtx_code comparison = d->comparison;
23774 if (VECTOR_MODE_P (mode0))
23775 op0 = safe_vector_operand (op0, mode0);
23776 if (VECTOR_MODE_P (mode1))
23777 op1 = safe_vector_operand (op1, mode1);
23779 target = gen_reg_rtx (SImode);
23780 emit_move_insn (target, const0_rtx);
23781 target = gen_rtx_SUBREG (QImode, target, 0);
23783 if ((optimize && !register_operand (op0, mode0))
23784 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23785 op0 = copy_to_mode_reg (mode0, op0);
23786 if ((optimize && !register_operand (op1, mode1))
23787 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23788 op1 = copy_to_mode_reg (mode1, op1);
23790 pat = GEN_FCN (d->icode) (op0, op1);
23794 emit_insn (gen_rtx_SET (VOIDmode,
23795 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23796 gen_rtx_fmt_ee (comparison, QImode,
23800 return SUBREG_REG (target);
23803 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23806 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23807 tree exp, rtx target)
23810 tree arg0 = CALL_EXPR_ARG (exp, 0);
23811 tree arg1 = CALL_EXPR_ARG (exp, 1);
23812 tree arg2 = CALL_EXPR_ARG (exp, 2);
23813 tree arg3 = CALL_EXPR_ARG (exp, 3);
23814 tree arg4 = CALL_EXPR_ARG (exp, 4);
23815 rtx scratch0, scratch1;
23816 rtx op0 = expand_normal (arg0);
23817 rtx op1 = expand_normal (arg1);
23818 rtx op2 = expand_normal (arg2);
23819 rtx op3 = expand_normal (arg3);
23820 rtx op4 = expand_normal (arg4);
23821 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23823 tmode0 = insn_data[d->icode].operand[0].mode;
23824 tmode1 = insn_data[d->icode].operand[1].mode;
23825 modev2 = insn_data[d->icode].operand[2].mode;
23826 modei3 = insn_data[d->icode].operand[3].mode;
23827 modev4 = insn_data[d->icode].operand[4].mode;
23828 modei5 = insn_data[d->icode].operand[5].mode;
23829 modeimm = insn_data[d->icode].operand[6].mode;
23831 if (VECTOR_MODE_P (modev2))
23832 op0 = safe_vector_operand (op0, modev2);
23833 if (VECTOR_MODE_P (modev4))
23834 op2 = safe_vector_operand (op2, modev4);
23836 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23837 op0 = copy_to_mode_reg (modev2, op0);
23838 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23839 op1 = copy_to_mode_reg (modei3, op1);
23840 if ((optimize && !register_operand (op2, modev4))
23841 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23842 op2 = copy_to_mode_reg (modev4, op2);
23843 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23844 op3 = copy_to_mode_reg (modei5, op3);
23846 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23848 error ("the fifth argument must be a 8-bit immediate");
23852 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23854 if (optimize || !target
23855 || GET_MODE (target) != tmode0
23856 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23857 target = gen_reg_rtx (tmode0);
23859 scratch1 = gen_reg_rtx (tmode1);
23861 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23863 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23865 if (optimize || !target
23866 || GET_MODE (target) != tmode1
23867 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23868 target = gen_reg_rtx (tmode1);
23870 scratch0 = gen_reg_rtx (tmode0);
23872 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23876 gcc_assert (d->flag);
23878 scratch0 = gen_reg_rtx (tmode0);
23879 scratch1 = gen_reg_rtx (tmode1);
23881 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23891 target = gen_reg_rtx (SImode);
23892 emit_move_insn (target, const0_rtx);
23893 target = gen_rtx_SUBREG (QImode, target, 0);
23896 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23897 gen_rtx_fmt_ee (EQ, QImode,
23898 gen_rtx_REG ((enum machine_mode) d->flag,
23901 return SUBREG_REG (target);
23908 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23911 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23912 tree exp, rtx target)
23915 tree arg0 = CALL_EXPR_ARG (exp, 0);
23916 tree arg1 = CALL_EXPR_ARG (exp, 1);
23917 tree arg2 = CALL_EXPR_ARG (exp, 2);
23918 rtx scratch0, scratch1;
23919 rtx op0 = expand_normal (arg0);
23920 rtx op1 = expand_normal (arg1);
23921 rtx op2 = expand_normal (arg2);
23922 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23924 tmode0 = insn_data[d->icode].operand[0].mode;
23925 tmode1 = insn_data[d->icode].operand[1].mode;
23926 modev2 = insn_data[d->icode].operand[2].mode;
23927 modev3 = insn_data[d->icode].operand[3].mode;
23928 modeimm = insn_data[d->icode].operand[4].mode;
23930 if (VECTOR_MODE_P (modev2))
23931 op0 = safe_vector_operand (op0, modev2);
23932 if (VECTOR_MODE_P (modev3))
23933 op1 = safe_vector_operand (op1, modev3);
23935 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23936 op0 = copy_to_mode_reg (modev2, op0);
23937 if ((optimize && !register_operand (op1, modev3))
23938 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23939 op1 = copy_to_mode_reg (modev3, op1);
23941 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23943 error ("the third argument must be a 8-bit immediate");
23947 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23949 if (optimize || !target
23950 || GET_MODE (target) != tmode0
23951 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23952 target = gen_reg_rtx (tmode0);
23954 scratch1 = gen_reg_rtx (tmode1);
23956 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23958 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23960 if (optimize || !target
23961 || GET_MODE (target) != tmode1
23962 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23963 target = gen_reg_rtx (tmode1);
23965 scratch0 = gen_reg_rtx (tmode0);
23967 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23971 gcc_assert (d->flag);
23973 scratch0 = gen_reg_rtx (tmode0);
23974 scratch1 = gen_reg_rtx (tmode1);
23976 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23986 target = gen_reg_rtx (SImode);
23987 emit_move_insn (target, const0_rtx);
23988 target = gen_rtx_SUBREG (QImode, target, 0);
23991 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23992 gen_rtx_fmt_ee (EQ, QImode,
23993 gen_rtx_REG ((enum machine_mode) d->flag,
23996 return SUBREG_REG (target);
24002 /* Subroutine of ix86_expand_builtin to take care of insns with
24003 variable number of operands. */
24006 ix86_expand_args_builtin (const struct builtin_description *d,
24007 tree exp, rtx target)
24009 rtx pat, real_target;
24010 unsigned int i, nargs;
24011 unsigned int nargs_constant = 0;
24012 int num_memory = 0;
24016 enum machine_mode mode;
24018 bool last_arg_count = false;
24019 enum insn_code icode = d->icode;
24020 const struct insn_data *insn_p = &insn_data[icode];
24021 enum machine_mode tmode = insn_p->operand[0].mode;
24022 enum machine_mode rmode = VOIDmode;
24024 enum rtx_code comparison = d->comparison;
24026 switch ((enum ix86_builtin_type) d->flag)
24028 case INT_FTYPE_V8SF_V8SF_PTEST:
24029 case INT_FTYPE_V4DI_V4DI_PTEST:
24030 case INT_FTYPE_V4DF_V4DF_PTEST:
24031 case INT_FTYPE_V4SF_V4SF_PTEST:
24032 case INT_FTYPE_V2DI_V2DI_PTEST:
24033 case INT_FTYPE_V2DF_V2DF_PTEST:
24034 return ix86_expand_sse_ptest (d, exp, target);
24035 case FLOAT128_FTYPE_FLOAT128:
24036 case FLOAT_FTYPE_FLOAT:
24037 case INT_FTYPE_INT:
24038 case UINT64_FTYPE_INT:
24039 case INT64_FTYPE_INT64:
24040 case INT64_FTYPE_V4SF:
24041 case INT64_FTYPE_V2DF:
24042 case INT_FTYPE_V16QI:
24043 case INT_FTYPE_V8QI:
24044 case INT_FTYPE_V8SF:
24045 case INT_FTYPE_V4DF:
24046 case INT_FTYPE_V4SF:
24047 case INT_FTYPE_V2DF:
24048 case V16QI_FTYPE_V16QI:
24049 case V8SI_FTYPE_V8SF:
24050 case V8SI_FTYPE_V4SI:
24051 case V8HI_FTYPE_V8HI:
24052 case V8HI_FTYPE_V16QI:
24053 case V8QI_FTYPE_V8QI:
24054 case V8SF_FTYPE_V8SF:
24055 case V8SF_FTYPE_V8SI:
24056 case V8SF_FTYPE_V4SF:
24057 case V4SI_FTYPE_V4SI:
24058 case V4SI_FTYPE_V16QI:
24059 case V4SI_FTYPE_V4SF:
24060 case V4SI_FTYPE_V8SI:
24061 case V4SI_FTYPE_V8HI:
24062 case V4SI_FTYPE_V4DF:
24063 case V4SI_FTYPE_V2DF:
24064 case V4HI_FTYPE_V4HI:
24065 case V4DF_FTYPE_V4DF:
24066 case V4DF_FTYPE_V4SI:
24067 case V4DF_FTYPE_V4SF:
24068 case V4DF_FTYPE_V2DF:
24069 case V4SF_FTYPE_V4SF:
24070 case V4SF_FTYPE_V4SI:
24071 case V4SF_FTYPE_V8SF:
24072 case V4SF_FTYPE_V4DF:
24073 case V4SF_FTYPE_V2DF:
24074 case V2DI_FTYPE_V2DI:
24075 case V2DI_FTYPE_V16QI:
24076 case V2DI_FTYPE_V8HI:
24077 case V2DI_FTYPE_V4SI:
24078 case V2DF_FTYPE_V2DF:
24079 case V2DF_FTYPE_V4SI:
24080 case V2DF_FTYPE_V4DF:
24081 case V2DF_FTYPE_V4SF:
24082 case V2DF_FTYPE_V2SI:
24083 case V2SI_FTYPE_V2SI:
24084 case V2SI_FTYPE_V4SF:
24085 case V2SI_FTYPE_V2SF:
24086 case V2SI_FTYPE_V2DF:
24087 case V2SF_FTYPE_V2SF:
24088 case V2SF_FTYPE_V2SI:
24091 case V4SF_FTYPE_V4SF_VEC_MERGE:
24092 case V2DF_FTYPE_V2DF_VEC_MERGE:
24093 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24094 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24095 case V16QI_FTYPE_V16QI_V16QI:
24096 case V16QI_FTYPE_V8HI_V8HI:
24097 case V8QI_FTYPE_V8QI_V8QI:
24098 case V8QI_FTYPE_V4HI_V4HI:
24099 case V8HI_FTYPE_V8HI_V8HI:
24100 case V8HI_FTYPE_V16QI_V16QI:
24101 case V8HI_FTYPE_V4SI_V4SI:
24102 case V8SF_FTYPE_V8SF_V8SF:
24103 case V8SF_FTYPE_V8SF_V8SI:
24104 case V4SI_FTYPE_V4SI_V4SI:
24105 case V4SI_FTYPE_V8HI_V8HI:
24106 case V4SI_FTYPE_V4SF_V4SF:
24107 case V4SI_FTYPE_V2DF_V2DF:
24108 case V4HI_FTYPE_V4HI_V4HI:
24109 case V4HI_FTYPE_V8QI_V8QI:
24110 case V4HI_FTYPE_V2SI_V2SI:
24111 case V4DF_FTYPE_V4DF_V4DF:
24112 case V4DF_FTYPE_V4DF_V4DI:
24113 case V4SF_FTYPE_V4SF_V4SF:
24114 case V4SF_FTYPE_V4SF_V4SI:
24115 case V4SF_FTYPE_V4SF_V2SI:
24116 case V4SF_FTYPE_V4SF_V2DF:
24117 case V4SF_FTYPE_V4SF_DI:
24118 case V4SF_FTYPE_V4SF_SI:
24119 case V2DI_FTYPE_V2DI_V2DI:
24120 case V2DI_FTYPE_V16QI_V16QI:
24121 case V2DI_FTYPE_V4SI_V4SI:
24122 case V2DI_FTYPE_V2DI_V16QI:
24123 case V2DI_FTYPE_V2DF_V2DF:
24124 case V2SI_FTYPE_V2SI_V2SI:
24125 case V2SI_FTYPE_V4HI_V4HI:
24126 case V2SI_FTYPE_V2SF_V2SF:
24127 case V2DF_FTYPE_V2DF_V2DF:
24128 case V2DF_FTYPE_V2DF_V4SF:
24129 case V2DF_FTYPE_V2DF_V2DI:
24130 case V2DF_FTYPE_V2DF_DI:
24131 case V2DF_FTYPE_V2DF_SI:
24132 case V2SF_FTYPE_V2SF_V2SF:
24133 case V1DI_FTYPE_V1DI_V1DI:
24134 case V1DI_FTYPE_V8QI_V8QI:
24135 case V1DI_FTYPE_V2SI_V2SI:
24136 if (comparison == UNKNOWN)
24137 return ix86_expand_binop_builtin (icode, exp, target);
24140 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24141 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24142 gcc_assert (comparison != UNKNOWN);
24146 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24147 case V8HI_FTYPE_V8HI_SI_COUNT:
24148 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24149 case V4SI_FTYPE_V4SI_SI_COUNT:
24150 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24151 case V4HI_FTYPE_V4HI_SI_COUNT:
24152 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24153 case V2DI_FTYPE_V2DI_SI_COUNT:
24154 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24155 case V2SI_FTYPE_V2SI_SI_COUNT:
24156 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24157 case V1DI_FTYPE_V1DI_SI_COUNT:
24159 last_arg_count = true;
24161 case UINT64_FTYPE_UINT64_UINT64:
24162 case UINT_FTYPE_UINT_UINT:
24163 case UINT_FTYPE_UINT_USHORT:
24164 case UINT_FTYPE_UINT_UCHAR:
24165 case UINT16_FTYPE_UINT16_INT:
24166 case UINT8_FTYPE_UINT8_INT:
24169 case V2DI2TI_FTYPE_V2DI_INT:
24172 nargs_constant = 1;
24174 case V8HI_FTYPE_V8HI_INT:
24175 case V8SF_FTYPE_V8SF_INT:
24176 case V4SI_FTYPE_V4SI_INT:
24177 case V4SI_FTYPE_V8SI_INT:
24178 case V4HI_FTYPE_V4HI_INT:
24179 case V4DF_FTYPE_V4DF_INT:
24180 case V4SF_FTYPE_V4SF_INT:
24181 case V4SF_FTYPE_V8SF_INT:
24182 case V2DI_FTYPE_V2DI_INT:
24183 case V2DF_FTYPE_V2DF_INT:
24184 case V2DF_FTYPE_V4DF_INT:
24186 nargs_constant = 1;
24188 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24189 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24190 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24191 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24192 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24195 case V16QI_FTYPE_V16QI_V16QI_INT:
24196 case V8HI_FTYPE_V8HI_V8HI_INT:
24197 case V8SI_FTYPE_V8SI_V8SI_INT:
24198 case V8SI_FTYPE_V8SI_V4SI_INT:
24199 case V8SF_FTYPE_V8SF_V8SF_INT:
24200 case V8SF_FTYPE_V8SF_V4SF_INT:
24201 case V4SI_FTYPE_V4SI_V4SI_INT:
24202 case V4DF_FTYPE_V4DF_V4DF_INT:
24203 case V4DF_FTYPE_V4DF_V2DF_INT:
24204 case V4SF_FTYPE_V4SF_V4SF_INT:
24205 case V2DI_FTYPE_V2DI_V2DI_INT:
24206 case V2DF_FTYPE_V2DF_V2DF_INT:
24208 nargs_constant = 1;
24210 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24213 nargs_constant = 1;
24215 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24218 nargs_constant = 1;
24220 case V2DI_FTYPE_V2DI_UINT_UINT:
24222 nargs_constant = 2;
24224 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24226 nargs_constant = 2;
24229 gcc_unreachable ();
24232 gcc_assert (nargs <= ARRAY_SIZE (args));
24234 if (comparison != UNKNOWN)
24236 gcc_assert (nargs == 2);
24237 return ix86_expand_sse_compare (d, exp, target, swap);
24240 if (rmode == VOIDmode || rmode == tmode)
24244 || GET_MODE (target) != tmode
24245 || ! (*insn_p->operand[0].predicate) (target, tmode))
24246 target = gen_reg_rtx (tmode);
24247 real_target = target;
24251 target = gen_reg_rtx (rmode);
24252 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24255 for (i = 0; i < nargs; i++)
24257 tree arg = CALL_EXPR_ARG (exp, i);
24258 rtx op = expand_normal (arg);
24259 enum machine_mode mode = insn_p->operand[i + 1].mode;
24260 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24262 if (last_arg_count && (i + 1) == nargs)
24264 /* SIMD shift insns take either an 8-bit immediate or
24265 register as count. But builtin functions take int as
24266 count. If count doesn't match, we put it in register. */
24269 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24270 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24271 op = copy_to_reg (op);
24274 else if ((nargs - i) <= nargs_constant)
24279 case CODE_FOR_sse4_1_roundpd:
24280 case CODE_FOR_sse4_1_roundps:
24281 case CODE_FOR_sse4_1_roundsd:
24282 case CODE_FOR_sse4_1_roundss:
24283 case CODE_FOR_sse4_1_blendps:
24284 case CODE_FOR_avx_blendpd256:
24285 case CODE_FOR_avx_vpermilv4df:
24286 case CODE_FOR_avx_roundpd256:
24287 case CODE_FOR_avx_roundps256:
24288 error ("the last argument must be a 4-bit immediate");
24291 case CODE_FOR_sse4_1_blendpd:
24292 case CODE_FOR_avx_vpermilv2df:
24293 error ("the last argument must be a 2-bit immediate");
24296 case CODE_FOR_avx_vextractf128v4df:
24297 case CODE_FOR_avx_vextractf128v8sf:
24298 case CODE_FOR_avx_vextractf128v8si:
24299 case CODE_FOR_avx_vinsertf128v4df:
24300 case CODE_FOR_avx_vinsertf128v8sf:
24301 case CODE_FOR_avx_vinsertf128v8si:
24302 error ("the last argument must be a 1-bit immediate");
24305 case CODE_FOR_avx_cmpsdv2df3:
24306 case CODE_FOR_avx_cmpssv4sf3:
24307 case CODE_FOR_avx_cmppdv2df3:
24308 case CODE_FOR_avx_cmppsv4sf3:
24309 case CODE_FOR_avx_cmppdv4df3:
24310 case CODE_FOR_avx_cmppsv8sf3:
24311 error ("the last argument must be a 5-bit immediate");
24315 switch (nargs_constant)
24318 if ((nargs - i) == nargs_constant)
24320 error ("the next to last argument must be an 8-bit immediate");
24324 error ("the last argument must be an 8-bit immediate");
24327 gcc_unreachable ();
24334 if (VECTOR_MODE_P (mode))
24335 op = safe_vector_operand (op, mode);
24337 /* If we aren't optimizing, only allow one memory operand to
24339 if (memory_operand (op, mode))
24342 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24344 if (optimize || !match || num_memory > 1)
24345 op = copy_to_mode_reg (mode, op);
24349 op = copy_to_reg (op);
24350 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24355 args[i].mode = mode;
24361 pat = GEN_FCN (icode) (real_target, args[0].op);
24364 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24367 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24371 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24372 args[2].op, args[3].op);
24375 gcc_unreachable ();
24385 /* Subroutine of ix86_expand_builtin to take care of special insns
24386 with variable number of operands. */
24389 ix86_expand_special_args_builtin (const struct builtin_description *d,
24390 tree exp, rtx target)
24394 unsigned int i, nargs, arg_adjust, memory;
24398 enum machine_mode mode;
24400 enum insn_code icode = d->icode;
24401 bool last_arg_constant = false;
24402 const struct insn_data *insn_p = &insn_data[icode];
24403 enum machine_mode tmode = insn_p->operand[0].mode;
24404 enum { load, store } klass;
24406 switch ((enum ix86_special_builtin_type) d->flag)
24408 case VOID_FTYPE_VOID:
24409 emit_insn (GEN_FCN (icode) (target));
24411 case UINT64_FTYPE_VOID:
24416 case UINT64_FTYPE_PUNSIGNED:
24417 case V2DI_FTYPE_PV2DI:
24418 case V32QI_FTYPE_PCCHAR:
24419 case V16QI_FTYPE_PCCHAR:
24420 case V8SF_FTYPE_PCV4SF:
24421 case V8SF_FTYPE_PCFLOAT:
24422 case V4SF_FTYPE_PCFLOAT:
24423 case V4DF_FTYPE_PCV2DF:
24424 case V4DF_FTYPE_PCDOUBLE:
24425 case V2DF_FTYPE_PCDOUBLE:
24430 case VOID_FTYPE_PV2SF_V4SF:
24431 case VOID_FTYPE_PV4DI_V4DI:
24432 case VOID_FTYPE_PV2DI_V2DI:
24433 case VOID_FTYPE_PCHAR_V32QI:
24434 case VOID_FTYPE_PCHAR_V16QI:
24435 case VOID_FTYPE_PFLOAT_V8SF:
24436 case VOID_FTYPE_PFLOAT_V4SF:
24437 case VOID_FTYPE_PDOUBLE_V4DF:
24438 case VOID_FTYPE_PDOUBLE_V2DF:
24439 case VOID_FTYPE_PDI_DI:
24440 case VOID_FTYPE_PINT_INT:
24443 /* Reserve memory operand for target. */
24444 memory = ARRAY_SIZE (args);
24446 case V4SF_FTYPE_V4SF_PCV2SF:
24447 case V2DF_FTYPE_V2DF_PCDOUBLE:
24452 case V8SF_FTYPE_PCV8SF_V8SF:
24453 case V4DF_FTYPE_PCV4DF_V4DF:
24454 case V4SF_FTYPE_PCV4SF_V4SF:
24455 case V2DF_FTYPE_PCV2DF_V2DF:
24460 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24461 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24462 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24463 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24466 /* Reserve memory operand for target. */
24467 memory = ARRAY_SIZE (args);
24470 gcc_unreachable ();
24473 gcc_assert (nargs <= ARRAY_SIZE (args));
24475 if (klass == store)
24477 arg = CALL_EXPR_ARG (exp, 0);
24478 op = expand_normal (arg);
24479 gcc_assert (target == 0);
24480 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24488 || GET_MODE (target) != tmode
24489 || ! (*insn_p->operand[0].predicate) (target, tmode))
24490 target = gen_reg_rtx (tmode);
24493 for (i = 0; i < nargs; i++)
24495 enum machine_mode mode = insn_p->operand[i + 1].mode;
24498 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24499 op = expand_normal (arg);
24500 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24502 if (last_arg_constant && (i + 1) == nargs)
24508 error ("the last argument must be an 8-bit immediate");
24516 /* This must be the memory operand. */
24517 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24518 gcc_assert (GET_MODE (op) == mode
24519 || GET_MODE (op) == VOIDmode);
24523 /* This must be register. */
24524 if (VECTOR_MODE_P (mode))
24525 op = safe_vector_operand (op, mode);
24527 gcc_assert (GET_MODE (op) == mode
24528 || GET_MODE (op) == VOIDmode);
24529 op = copy_to_mode_reg (mode, op);
24534 args[i].mode = mode;
24540 pat = GEN_FCN (icode) (target);
24543 pat = GEN_FCN (icode) (target, args[0].op);
24546 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24549 gcc_unreachable ();
24555 return klass == store ? 0 : target;
24558 /* Return the integer constant in ARG. Constrain it to be in the range
24559 of the subparts of VEC_TYPE; issue an error if not. */
24562 get_element_number (tree vec_type, tree arg)
24564 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24566 if (!host_integerp (arg, 1)
24567 || (elt = tree_low_cst (arg, 1), elt > max))
24569 error ("selector must be an integer constant in the range 0..%wi", max);
24576 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24577 ix86_expand_vector_init. We DO have language-level syntax for this, in
24578 the form of (type){ init-list }. Except that since we can't place emms
24579 instructions from inside the compiler, we can't allow the use of MMX
24580 registers unless the user explicitly asks for it. So we do *not* define
24581 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24582 we have builtins invoked by mmintrin.h that gives us license to emit
24583 these sorts of instructions. */
24586 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24588 enum machine_mode tmode = TYPE_MODE (type);
24589 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24590 int i, n_elt = GET_MODE_NUNITS (tmode);
24591 rtvec v = rtvec_alloc (n_elt);
24593 gcc_assert (VECTOR_MODE_P (tmode));
24594 gcc_assert (call_expr_nargs (exp) == n_elt);
24596 for (i = 0; i < n_elt; ++i)
24598 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24599 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24602 if (!target || !register_operand (target, tmode))
24603 target = gen_reg_rtx (tmode);
24605 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24609 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24610 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24611 had a language-level syntax for referencing vector elements. */
24614 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24616 enum machine_mode tmode, mode0;
24621 arg0 = CALL_EXPR_ARG (exp, 0);
24622 arg1 = CALL_EXPR_ARG (exp, 1);
24624 op0 = expand_normal (arg0);
24625 elt = get_element_number (TREE_TYPE (arg0), arg1);
24627 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24628 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24629 gcc_assert (VECTOR_MODE_P (mode0));
24631 op0 = force_reg (mode0, op0);
24633 if (optimize || !target || !register_operand (target, tmode))
24634 target = gen_reg_rtx (tmode);
24636 ix86_expand_vector_extract (true, target, op0, elt);
24641 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24642 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24643 a language-level syntax for referencing vector elements. */
24646 ix86_expand_vec_set_builtin (tree exp)
24648 enum machine_mode tmode, mode1;
24649 tree arg0, arg1, arg2;
24651 rtx op0, op1, target;
24653 arg0 = CALL_EXPR_ARG (exp, 0);
24654 arg1 = CALL_EXPR_ARG (exp, 1);
24655 arg2 = CALL_EXPR_ARG (exp, 2);
24657 tmode = TYPE_MODE (TREE_TYPE (arg0));
24658 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24659 gcc_assert (VECTOR_MODE_P (tmode));
24661 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24662 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24663 elt = get_element_number (TREE_TYPE (arg0), arg2);
24665 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24666 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24668 op0 = force_reg (tmode, op0);
24669 op1 = force_reg (mode1, op1);
24671 /* OP0 is the source of these builtin functions and shouldn't be
24672 modified. Create a copy, use it and return it as target. */
24673 target = gen_reg_rtx (tmode);
24674 emit_move_insn (target, op0);
24675 ix86_expand_vector_set (true, target, op1, elt);
24680 /* Expand an expression EXP that calls a built-in function,
24681 with result going to TARGET if that's convenient
24682 (and in mode MODE if that's convenient).
24683 SUBTARGET may be used as the target for computing one of EXP's operands.
24684 IGNORE is nonzero if the value is to be ignored. */
24687 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24688 enum machine_mode mode ATTRIBUTE_UNUSED,
24689 int ignore ATTRIBUTE_UNUSED)
24691 const struct builtin_description *d;
24693 enum insn_code icode;
24694 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24695 tree arg0, arg1, arg2;
24696 rtx op0, op1, op2, pat;
24697 enum machine_mode mode0, mode1, mode2;
24698 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24700 /* Determine whether the builtin function is available under the current ISA.
24701 Originally the builtin was not created if it wasn't applicable to the
24702 current ISA based on the command line switches. With function specific
24703 options, we need to check in the context of the function making the call
24704 whether it is supported. */
24705 if (ix86_builtins_isa[fcode].isa
24706 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24708 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24709 NULL, NULL, false);
24712 error ("%qE needs unknown isa option", fndecl);
24715 gcc_assert (opts != NULL);
24716 error ("%qE needs isa option %s", fndecl, opts);
24724 case IX86_BUILTIN_MASKMOVQ:
24725 case IX86_BUILTIN_MASKMOVDQU:
24726 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24727 ? CODE_FOR_mmx_maskmovq
24728 : CODE_FOR_sse2_maskmovdqu);
24729 /* Note the arg order is different from the operand order. */
24730 arg1 = CALL_EXPR_ARG (exp, 0);
24731 arg2 = CALL_EXPR_ARG (exp, 1);
24732 arg0 = CALL_EXPR_ARG (exp, 2);
24733 op0 = expand_normal (arg0);
24734 op1 = expand_normal (arg1);
24735 op2 = expand_normal (arg2);
24736 mode0 = insn_data[icode].operand[0].mode;
24737 mode1 = insn_data[icode].operand[1].mode;
24738 mode2 = insn_data[icode].operand[2].mode;
24740 op0 = force_reg (Pmode, op0);
24741 op0 = gen_rtx_MEM (mode1, op0);
24743 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24744 op0 = copy_to_mode_reg (mode0, op0);
24745 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24746 op1 = copy_to_mode_reg (mode1, op1);
24747 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24748 op2 = copy_to_mode_reg (mode2, op2);
24749 pat = GEN_FCN (icode) (op0, op1, op2);
24755 case IX86_BUILTIN_LDMXCSR:
24756 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24757 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24758 emit_move_insn (target, op0);
24759 emit_insn (gen_sse_ldmxcsr (target));
24762 case IX86_BUILTIN_STMXCSR:
24763 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24764 emit_insn (gen_sse_stmxcsr (target));
24765 return copy_to_mode_reg (SImode, target);
24767 case IX86_BUILTIN_CLFLUSH:
24768 arg0 = CALL_EXPR_ARG (exp, 0);
24769 op0 = expand_normal (arg0);
24770 icode = CODE_FOR_sse2_clflush;
24771 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24772 op0 = copy_to_mode_reg (Pmode, op0);
24774 emit_insn (gen_sse2_clflush (op0));
24777 case IX86_BUILTIN_MONITOR:
24778 arg0 = CALL_EXPR_ARG (exp, 0);
24779 arg1 = CALL_EXPR_ARG (exp, 1);
24780 arg2 = CALL_EXPR_ARG (exp, 2);
24781 op0 = expand_normal (arg0);
24782 op1 = expand_normal (arg1);
24783 op2 = expand_normal (arg2);
24785 op0 = copy_to_mode_reg (Pmode, op0);
24787 op1 = copy_to_mode_reg (SImode, op1);
24789 op2 = copy_to_mode_reg (SImode, op2);
24790 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24793 case IX86_BUILTIN_MWAIT:
24794 arg0 = CALL_EXPR_ARG (exp, 0);
24795 arg1 = CALL_EXPR_ARG (exp, 1);
24796 op0 = expand_normal (arg0);
24797 op1 = expand_normal (arg1);
24799 op0 = copy_to_mode_reg (SImode, op0);
24801 op1 = copy_to_mode_reg (SImode, op1);
24802 emit_insn (gen_sse3_mwait (op0, op1));
24805 case IX86_BUILTIN_VEC_INIT_V2SI:
24806 case IX86_BUILTIN_VEC_INIT_V4HI:
24807 case IX86_BUILTIN_VEC_INIT_V8QI:
24808 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24810 case IX86_BUILTIN_VEC_EXT_V2DF:
24811 case IX86_BUILTIN_VEC_EXT_V2DI:
24812 case IX86_BUILTIN_VEC_EXT_V4SF:
24813 case IX86_BUILTIN_VEC_EXT_V4SI:
24814 case IX86_BUILTIN_VEC_EXT_V8HI:
24815 case IX86_BUILTIN_VEC_EXT_V2SI:
24816 case IX86_BUILTIN_VEC_EXT_V4HI:
24817 case IX86_BUILTIN_VEC_EXT_V16QI:
24818 return ix86_expand_vec_ext_builtin (exp, target);
24820 case IX86_BUILTIN_VEC_SET_V2DI:
24821 case IX86_BUILTIN_VEC_SET_V4SF:
24822 case IX86_BUILTIN_VEC_SET_V4SI:
24823 case IX86_BUILTIN_VEC_SET_V8HI:
24824 case IX86_BUILTIN_VEC_SET_V4HI:
24825 case IX86_BUILTIN_VEC_SET_V16QI:
24826 return ix86_expand_vec_set_builtin (exp);
24828 case IX86_BUILTIN_INFQ:
24829 case IX86_BUILTIN_HUGE_VALQ:
24831 REAL_VALUE_TYPE inf;
24835 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24837 tmp = validize_mem (force_const_mem (mode, tmp));
24840 target = gen_reg_rtx (mode);
24842 emit_move_insn (target, tmp);
24850 for (i = 0, d = bdesc_special_args;
24851 i < ARRAY_SIZE (bdesc_special_args);
24853 if (d->code == fcode)
24854 return ix86_expand_special_args_builtin (d, exp, target);
24856 for (i = 0, d = bdesc_args;
24857 i < ARRAY_SIZE (bdesc_args);
24859 if (d->code == fcode)
24862 case IX86_BUILTIN_FABSQ:
24863 case IX86_BUILTIN_COPYSIGNQ:
24865 /* Emit a normal call if SSE2 isn't available. */
24866 return expand_call (exp, target, ignore);
24868 return ix86_expand_args_builtin (d, exp, target);
24871 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24872 if (d->code == fcode)
24873 return ix86_expand_sse_comi (d, exp, target);
24875 for (i = 0, d = bdesc_pcmpestr;
24876 i < ARRAY_SIZE (bdesc_pcmpestr);
24878 if (d->code == fcode)
24879 return ix86_expand_sse_pcmpestr (d, exp, target);
24881 for (i = 0, d = bdesc_pcmpistr;
24882 i < ARRAY_SIZE (bdesc_pcmpistr);
24884 if (d->code == fcode)
24885 return ix86_expand_sse_pcmpistr (d, exp, target);
24887 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24888 if (d->code == fcode)
24889 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24890 (enum multi_arg_type)d->flag,
24893 gcc_unreachable ();
24896 /* Returns a function decl for a vectorized version of the builtin function
24897 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24898 if it is not available. */
24901 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24904 enum machine_mode in_mode, out_mode;
24907 if (TREE_CODE (type_out) != VECTOR_TYPE
24908 || TREE_CODE (type_in) != VECTOR_TYPE)
24911 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24912 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24913 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24914 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24918 case BUILT_IN_SQRT:
24919 if (out_mode == DFmode && out_n == 2
24920 && in_mode == DFmode && in_n == 2)
24921 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24924 case BUILT_IN_SQRTF:
24925 if (out_mode == SFmode && out_n == 4
24926 && in_mode == SFmode && in_n == 4)
24927 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24930 case BUILT_IN_LRINT:
24931 if (out_mode == SImode && out_n == 4
24932 && in_mode == DFmode && in_n == 2)
24933 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24936 case BUILT_IN_LRINTF:
24937 if (out_mode == SImode && out_n == 4
24938 && in_mode == SFmode && in_n == 4)
24939 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24942 case BUILT_IN_COPYSIGN:
24943 if (out_mode == DFmode && out_n == 2
24944 && in_mode == DFmode && in_n == 2)
24945 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
24948 case BUILT_IN_COPYSIGNF:
24949 if (out_mode == SFmode && out_n == 4
24950 && in_mode == SFmode && in_n == 4)
24951 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
24958 /* Dispatch to a handler for a vectorization library. */
24959 if (ix86_veclib_handler)
24960 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
24966 /* Handler for an SVML-style interface to
24967 a library with vectorized intrinsics. */
24970 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24973 tree fntype, new_fndecl, args;
24976 enum machine_mode el_mode, in_mode;
24979 /* The SVML is suitable for unsafe math only. */
24980 if (!flag_unsafe_math_optimizations)
24983 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24984 n = TYPE_VECTOR_SUBPARTS (type_out);
24985 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24986 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24987 if (el_mode != in_mode
24995 case BUILT_IN_LOG10:
24997 case BUILT_IN_TANH:
24999 case BUILT_IN_ATAN:
25000 case BUILT_IN_ATAN2:
25001 case BUILT_IN_ATANH:
25002 case BUILT_IN_CBRT:
25003 case BUILT_IN_SINH:
25005 case BUILT_IN_ASINH:
25006 case BUILT_IN_ASIN:
25007 case BUILT_IN_COSH:
25009 case BUILT_IN_ACOSH:
25010 case BUILT_IN_ACOS:
25011 if (el_mode != DFmode || n != 2)
25015 case BUILT_IN_EXPF:
25016 case BUILT_IN_LOGF:
25017 case BUILT_IN_LOG10F:
25018 case BUILT_IN_POWF:
25019 case BUILT_IN_TANHF:
25020 case BUILT_IN_TANF:
25021 case BUILT_IN_ATANF:
25022 case BUILT_IN_ATAN2F:
25023 case BUILT_IN_ATANHF:
25024 case BUILT_IN_CBRTF:
25025 case BUILT_IN_SINHF:
25026 case BUILT_IN_SINF:
25027 case BUILT_IN_ASINHF:
25028 case BUILT_IN_ASINF:
25029 case BUILT_IN_COSHF:
25030 case BUILT_IN_COSF:
25031 case BUILT_IN_ACOSHF:
25032 case BUILT_IN_ACOSF:
25033 if (el_mode != SFmode || n != 4)
25041 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25043 if (fn == BUILT_IN_LOGF)
25044 strcpy (name, "vmlsLn4");
25045 else if (fn == BUILT_IN_LOG)
25046 strcpy (name, "vmldLn2");
25049 sprintf (name, "vmls%s", bname+10);
25050 name[strlen (name)-1] = '4';
25053 sprintf (name, "vmld%s2", bname+10);
25055 /* Convert to uppercase. */
25059 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25060 args = TREE_CHAIN (args))
25064 fntype = build_function_type_list (type_out, type_in, NULL);
25066 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25068 /* Build a function declaration for the vectorized function. */
25069 new_fndecl = build_decl (BUILTINS_LOCATION,
25070 FUNCTION_DECL, get_identifier (name), fntype);
25071 TREE_PUBLIC (new_fndecl) = 1;
25072 DECL_EXTERNAL (new_fndecl) = 1;
25073 DECL_IS_NOVOPS (new_fndecl) = 1;
25074 TREE_READONLY (new_fndecl) = 1;
25079 /* Handler for an ACML-style interface to
25080 a library with vectorized intrinsics. */
25083 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25085 char name[20] = "__vr.._";
25086 tree fntype, new_fndecl, args;
25089 enum machine_mode el_mode, in_mode;
25092 /* The ACML is 64bits only and suitable for unsafe math only as
25093 it does not correctly support parts of IEEE with the required
25094 precision such as denormals. */
25096 || !flag_unsafe_math_optimizations)
25099 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25100 n = TYPE_VECTOR_SUBPARTS (type_out);
25101 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25102 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25103 if (el_mode != in_mode
25113 case BUILT_IN_LOG2:
25114 case BUILT_IN_LOG10:
25117 if (el_mode != DFmode
25122 case BUILT_IN_SINF:
25123 case BUILT_IN_COSF:
25124 case BUILT_IN_EXPF:
25125 case BUILT_IN_POWF:
25126 case BUILT_IN_LOGF:
25127 case BUILT_IN_LOG2F:
25128 case BUILT_IN_LOG10F:
25131 if (el_mode != SFmode
25140 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25141 sprintf (name + 7, "%s", bname+10);
25144 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25145 args = TREE_CHAIN (args))
25149 fntype = build_function_type_list (type_out, type_in, NULL);
25151 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25153 /* Build a function declaration for the vectorized function. */
25154 new_fndecl = build_decl (BUILTINS_LOCATION,
25155 FUNCTION_DECL, get_identifier (name), fntype);
25156 TREE_PUBLIC (new_fndecl) = 1;
25157 DECL_EXTERNAL (new_fndecl) = 1;
25158 DECL_IS_NOVOPS (new_fndecl) = 1;
25159 TREE_READONLY (new_fndecl) = 1;
25165 /* Returns a decl of a function that implements conversion of an integer vector
25166 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25167 side of the conversion.
25168 Return NULL_TREE if it is not available. */
25171 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25173 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
25179 switch (TYPE_MODE (type))
25182 return TYPE_UNSIGNED (type)
25183 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
25184 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25189 case FIX_TRUNC_EXPR:
25190 switch (TYPE_MODE (type))
25193 return TYPE_UNSIGNED (type)
25195 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25205 /* Returns a code for a target-specific builtin that implements
25206 reciprocal of the function, or NULL_TREE if not available. */
25209 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25210 bool sqrt ATTRIBUTE_UNUSED)
25212 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25213 && flag_finite_math_only && !flag_trapping_math
25214 && flag_unsafe_math_optimizations))
25218 /* Machine dependent builtins. */
25221 /* Vectorized version of sqrt to rsqrt conversion. */
25222 case IX86_BUILTIN_SQRTPS_NR:
25223 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25229 /* Normal builtins. */
25232 /* Sqrt to rsqrt conversion. */
25233 case BUILT_IN_SQRTF:
25234 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25241 /* Store OPERAND to the memory after reload is completed. This means
25242 that we can't easily use assign_stack_local. */
25244 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25248 gcc_assert (reload_completed);
25249 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25251 result = gen_rtx_MEM (mode,
25252 gen_rtx_PLUS (Pmode,
25254 GEN_INT (-RED_ZONE_SIZE)));
25255 emit_move_insn (result, operand);
25257 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25263 operand = gen_lowpart (DImode, operand);
25267 gen_rtx_SET (VOIDmode,
25268 gen_rtx_MEM (DImode,
25269 gen_rtx_PRE_DEC (DImode,
25270 stack_pointer_rtx)),
25274 gcc_unreachable ();
25276 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25285 split_di (&operand, 1, operands, operands + 1);
25287 gen_rtx_SET (VOIDmode,
25288 gen_rtx_MEM (SImode,
25289 gen_rtx_PRE_DEC (Pmode,
25290 stack_pointer_rtx)),
25293 gen_rtx_SET (VOIDmode,
25294 gen_rtx_MEM (SImode,
25295 gen_rtx_PRE_DEC (Pmode,
25296 stack_pointer_rtx)),
25301 /* Store HImodes as SImodes. */
25302 operand = gen_lowpart (SImode, operand);
25306 gen_rtx_SET (VOIDmode,
25307 gen_rtx_MEM (GET_MODE (operand),
25308 gen_rtx_PRE_DEC (SImode,
25309 stack_pointer_rtx)),
25313 gcc_unreachable ();
25315 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25320 /* Free operand from the memory. */
25322 ix86_free_from_memory (enum machine_mode mode)
25324 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25328 if (mode == DImode || TARGET_64BIT)
25332 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25333 to pop or add instruction if registers are available. */
25334 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25335 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25340 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25341 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25343 static const enum reg_class *
25344 i386_ira_cover_classes (void)
25346 static const enum reg_class sse_fpmath_classes[] = {
25347 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
25349 static const enum reg_class no_sse_fpmath_classes[] = {
25350 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
25353 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
25356 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25357 QImode must go into class Q_REGS.
25358 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25359 movdf to do mem-to-mem moves through integer regs. */
25361 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25363 enum machine_mode mode = GET_MODE (x);
25365 /* We're only allowed to return a subclass of CLASS. Many of the
25366 following checks fail for NO_REGS, so eliminate that early. */
25367 if (regclass == NO_REGS)
25370 /* All classes can load zeros. */
25371 if (x == CONST0_RTX (mode))
25374 /* Force constants into memory if we are loading a (nonzero) constant into
25375 an MMX or SSE register. This is because there are no MMX/SSE instructions
25376 to load from a constant. */
25378 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25381 /* Prefer SSE regs only, if we can use them for math. */
25382 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25383 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25385 /* Floating-point constants need more complex checks. */
25386 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25388 /* General regs can load everything. */
25389 if (reg_class_subset_p (regclass, GENERAL_REGS))
25392 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25393 zero above. We only want to wind up preferring 80387 registers if
25394 we plan on doing computation with them. */
25396 && standard_80387_constant_p (x))
25398 /* Limit class to non-sse. */
25399 if (regclass == FLOAT_SSE_REGS)
25401 if (regclass == FP_TOP_SSE_REGS)
25403 if (regclass == FP_SECOND_SSE_REGS)
25404 return FP_SECOND_REG;
25405 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25412 /* Generally when we see PLUS here, it's the function invariant
25413 (plus soft-fp const_int). Which can only be computed into general
25415 if (GET_CODE (x) == PLUS)
25416 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25418 /* QImode constants are easy to load, but non-constant QImode data
25419 must go into Q_REGS. */
25420 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25422 if (reg_class_subset_p (regclass, Q_REGS))
25424 if (reg_class_subset_p (Q_REGS, regclass))
25432 /* Discourage putting floating-point values in SSE registers unless
25433 SSE math is being used, and likewise for the 387 registers. */
25435 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25437 enum machine_mode mode = GET_MODE (x);
25439 /* Restrict the output reload class to the register bank that we are doing
25440 math on. If we would like not to return a subset of CLASS, reject this
25441 alternative: if reload cannot do this, it will still use its choice. */
25442 mode = GET_MODE (x);
25443 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25444 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25446 if (X87_FLOAT_MODE_P (mode))
25448 if (regclass == FP_TOP_SSE_REGS)
25450 else if (regclass == FP_SECOND_SSE_REGS)
25451 return FP_SECOND_REG;
25453 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25459 static enum reg_class
25460 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25461 enum machine_mode mode,
25462 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25464 /* QImode spills from non-QI registers require
25465 intermediate register on 32bit targets. */
25466 if (!in_p && mode == QImode && !TARGET_64BIT
25467 && (rclass == GENERAL_REGS
25468 || rclass == LEGACY_REGS
25469 || rclass == INDEX_REGS))
25478 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25479 regno = true_regnum (x);
25481 /* Return Q_REGS if the operand is in memory. */
25489 /* If we are copying between general and FP registers, we need a memory
25490 location. The same is true for SSE and MMX registers.
25492 To optimize register_move_cost performance, allow inline variant.
25494 The macro can't work reliably when one of the CLASSES is class containing
25495 registers from multiple units (SSE, MMX, integer). We avoid this by never
25496 combining those units in single alternative in the machine description.
25497 Ensure that this constraint holds to avoid unexpected surprises.
25499 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25500 enforce these sanity checks. */
25503 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25504 enum machine_mode mode, int strict)
25506 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25507 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25508 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25509 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25510 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25511 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25513 gcc_assert (!strict);
25517 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25520 /* ??? This is a lie. We do have moves between mmx/general, and for
25521 mmx/sse2. But by saying we need secondary memory we discourage the
25522 register allocator from using the mmx registers unless needed. */
25523 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25526 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25528 /* SSE1 doesn't have any direct moves from other classes. */
25532 /* If the target says that inter-unit moves are more expensive
25533 than moving through memory, then don't generate them. */
25534 if (!TARGET_INTER_UNIT_MOVES)
25537 /* Between SSE and general, we have moves no larger than word size. */
25538 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25546 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25547 enum machine_mode mode, int strict)
25549 return inline_secondary_memory_needed (class1, class2, mode, strict);
25552 /* Return true if the registers in CLASS cannot represent the change from
25553 modes FROM to TO. */
25556 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25557 enum reg_class regclass)
25562 /* x87 registers can't do subreg at all, as all values are reformatted
25563 to extended precision. */
25564 if (MAYBE_FLOAT_CLASS_P (regclass))
25567 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25569 /* Vector registers do not support QI or HImode loads. If we don't
25570 disallow a change to these modes, reload will assume it's ok to
25571 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25572 the vec_dupv4hi pattern. */
25573 if (GET_MODE_SIZE (from) < 4)
25576 /* Vector registers do not support subreg with nonzero offsets, which
25577 are otherwise valid for integer registers. Since we can't see
25578 whether we have a nonzero offset from here, prohibit all
25579 nonparadoxical subregs changing size. */
25580 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25587 /* Return the cost of moving data of mode M between a
25588 register and memory. A value of 2 is the default; this cost is
25589 relative to those in `REGISTER_MOVE_COST'.
25591 This function is used extensively by register_move_cost that is used to
25592 build tables at startup. Make it inline in this case.
25593 When IN is 2, return maximum of in and out move cost.
25595 If moving between registers and memory is more expensive than
25596 between two registers, you should define this macro to express the
25599 Model also increased moving costs of QImode registers in non
25603 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25607 if (FLOAT_CLASS_P (regclass))
25625 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25626 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25628 if (SSE_CLASS_P (regclass))
25631 switch (GET_MODE_SIZE (mode))
25646 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25647 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25649 if (MMX_CLASS_P (regclass))
25652 switch (GET_MODE_SIZE (mode))
25664 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25665 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25667 switch (GET_MODE_SIZE (mode))
25670 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25673 return ix86_cost->int_store[0];
25674 if (TARGET_PARTIAL_REG_DEPENDENCY
25675 && optimize_function_for_speed_p (cfun))
25676 cost = ix86_cost->movzbl_load;
25678 cost = ix86_cost->int_load[0];
25680 return MAX (cost, ix86_cost->int_store[0]);
25686 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25688 return ix86_cost->movzbl_load;
25690 return ix86_cost->int_store[0] + 4;
25695 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25696 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25698 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25699 if (mode == TFmode)
25702 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25704 cost = ix86_cost->int_load[2];
25706 cost = ix86_cost->int_store[2];
25707 return (cost * (((int) GET_MODE_SIZE (mode)
25708 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25713 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25715 return inline_memory_move_cost (mode, regclass, in);
25719 /* Return the cost of moving data from a register in class CLASS1 to
25720 one in class CLASS2.
25722 It is not required that the cost always equal 2 when FROM is the same as TO;
25723 on some machines it is expensive to move between registers if they are not
25724 general registers. */
25727 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25728 enum reg_class class2)
25730 /* In case we require secondary memory, compute cost of the store followed
25731 by load. In order to avoid bad register allocation choices, we need
25732 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25734 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25738 cost += inline_memory_move_cost (mode, class1, 2);
25739 cost += inline_memory_move_cost (mode, class2, 2);
25741 /* In case of copying from general_purpose_register we may emit multiple
25742 stores followed by single load causing memory size mismatch stall.
25743 Count this as arbitrarily high cost of 20. */
25744 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25747 /* In the case of FP/MMX moves, the registers actually overlap, and we
25748 have to switch modes in order to treat them differently. */
25749 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25750 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25756 /* Moves between SSE/MMX and integer unit are expensive. */
25757 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25758 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25760 /* ??? By keeping returned value relatively high, we limit the number
25761 of moves between integer and MMX/SSE registers for all targets.
25762 Additionally, high value prevents problem with x86_modes_tieable_p(),
25763 where integer modes in MMX/SSE registers are not tieable
25764 because of missing QImode and HImode moves to, from or between
25765 MMX/SSE registers. */
25766 return MAX (8, ix86_cost->mmxsse_to_integer);
25768 if (MAYBE_FLOAT_CLASS_P (class1))
25769 return ix86_cost->fp_move;
25770 if (MAYBE_SSE_CLASS_P (class1))
25771 return ix86_cost->sse_move;
25772 if (MAYBE_MMX_CLASS_P (class1))
25773 return ix86_cost->mmx_move;
25777 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25780 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25782 /* Flags and only flags can only hold CCmode values. */
25783 if (CC_REGNO_P (regno))
25784 return GET_MODE_CLASS (mode) == MODE_CC;
25785 if (GET_MODE_CLASS (mode) == MODE_CC
25786 || GET_MODE_CLASS (mode) == MODE_RANDOM
25787 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25789 if (FP_REGNO_P (regno))
25790 return VALID_FP_MODE_P (mode);
25791 if (SSE_REGNO_P (regno))
25793 /* We implement the move patterns for all vector modes into and
25794 out of SSE registers, even when no operation instructions
25795 are available. OImode move is available only when AVX is
25797 return ((TARGET_AVX && mode == OImode)
25798 || VALID_AVX256_REG_MODE (mode)
25799 || VALID_SSE_REG_MODE (mode)
25800 || VALID_SSE2_REG_MODE (mode)
25801 || VALID_MMX_REG_MODE (mode)
25802 || VALID_MMX_REG_MODE_3DNOW (mode));
25804 if (MMX_REGNO_P (regno))
25806 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25807 so if the register is available at all, then we can move data of
25808 the given mode into or out of it. */
25809 return (VALID_MMX_REG_MODE (mode)
25810 || VALID_MMX_REG_MODE_3DNOW (mode));
25813 if (mode == QImode)
25815 /* Take care for QImode values - they can be in non-QI regs,
25816 but then they do cause partial register stalls. */
25817 if (regno <= BX_REG || TARGET_64BIT)
25819 if (!TARGET_PARTIAL_REG_STALL)
25821 return reload_in_progress || reload_completed;
25823 /* We handle both integer and floats in the general purpose registers. */
25824 else if (VALID_INT_MODE_P (mode))
25826 else if (VALID_FP_MODE_P (mode))
25828 else if (VALID_DFP_MODE_P (mode))
25830 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25831 on to use that value in smaller contexts, this can easily force a
25832 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25833 supporting DImode, allow it. */
25834 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25840 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25841 tieable integer mode. */
25844 ix86_tieable_integer_mode_p (enum machine_mode mode)
25853 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25856 return TARGET_64BIT;
25863 /* Return true if MODE1 is accessible in a register that can hold MODE2
25864 without copying. That is, all register classes that can hold MODE2
25865 can also hold MODE1. */
25868 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25870 if (mode1 == mode2)
25873 if (ix86_tieable_integer_mode_p (mode1)
25874 && ix86_tieable_integer_mode_p (mode2))
25877 /* MODE2 being XFmode implies fp stack or general regs, which means we
25878 can tie any smaller floating point modes to it. Note that we do not
25879 tie this with TFmode. */
25880 if (mode2 == XFmode)
25881 return mode1 == SFmode || mode1 == DFmode;
25883 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25884 that we can tie it with SFmode. */
25885 if (mode2 == DFmode)
25886 return mode1 == SFmode;
25888 /* If MODE2 is only appropriate for an SSE register, then tie with
25889 any other mode acceptable to SSE registers. */
25890 if (GET_MODE_SIZE (mode2) == 16
25891 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25892 return (GET_MODE_SIZE (mode1) == 16
25893 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25895 /* If MODE2 is appropriate for an MMX register, then tie
25896 with any other mode acceptable to MMX registers. */
25897 if (GET_MODE_SIZE (mode2) == 8
25898 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25899 return (GET_MODE_SIZE (mode1) == 8
25900 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25905 /* Compute a (partial) cost for rtx X. Return true if the complete
25906 cost has been computed, and false if subexpressions should be
25907 scanned. In either case, *TOTAL contains the cost result. */
25910 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25912 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25913 enum machine_mode mode = GET_MODE (x);
25914 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25922 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25924 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25926 else if (flag_pic && SYMBOLIC_CONST (x)
25928 || (!GET_CODE (x) != LABEL_REF
25929 && (GET_CODE (x) != SYMBOL_REF
25930 || !SYMBOL_REF_LOCAL_P (x)))))
25937 if (mode == VOIDmode)
25940 switch (standard_80387_constant_p (x))
25945 default: /* Other constants */
25950 /* Start with (MEM (SYMBOL_REF)), since that's where
25951 it'll probably end up. Add a penalty for size. */
25952 *total = (COSTS_N_INSNS (1)
25953 + (flag_pic != 0 && !TARGET_64BIT)
25954 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25960 /* The zero extensions is often completely free on x86_64, so make
25961 it as cheap as possible. */
25962 if (TARGET_64BIT && mode == DImode
25963 && GET_MODE (XEXP (x, 0)) == SImode)
25965 else if (TARGET_ZERO_EXTEND_WITH_AND)
25966 *total = cost->add;
25968 *total = cost->movzx;
25972 *total = cost->movsx;
25976 if (CONST_INT_P (XEXP (x, 1))
25977 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25979 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25982 *total = cost->add;
25985 if ((value == 2 || value == 3)
25986 && cost->lea <= cost->shift_const)
25988 *total = cost->lea;
25998 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26000 if (CONST_INT_P (XEXP (x, 1)))
26002 if (INTVAL (XEXP (x, 1)) > 32)
26003 *total = cost->shift_const + COSTS_N_INSNS (2);
26005 *total = cost->shift_const * 2;
26009 if (GET_CODE (XEXP (x, 1)) == AND)
26010 *total = cost->shift_var * 2;
26012 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26017 if (CONST_INT_P (XEXP (x, 1)))
26018 *total = cost->shift_const;
26020 *total = cost->shift_var;
26025 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26027 /* ??? SSE scalar cost should be used here. */
26028 *total = cost->fmul;
26031 else if (X87_FLOAT_MODE_P (mode))
26033 *total = cost->fmul;
26036 else if (FLOAT_MODE_P (mode))
26038 /* ??? SSE vector cost should be used here. */
26039 *total = cost->fmul;
26044 rtx op0 = XEXP (x, 0);
26045 rtx op1 = XEXP (x, 1);
26047 if (CONST_INT_P (XEXP (x, 1)))
26049 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26050 for (nbits = 0; value != 0; value &= value - 1)
26054 /* This is arbitrary. */
26057 /* Compute costs correctly for widening multiplication. */
26058 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26059 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26060 == GET_MODE_SIZE (mode))
26062 int is_mulwiden = 0;
26063 enum machine_mode inner_mode = GET_MODE (op0);
26065 if (GET_CODE (op0) == GET_CODE (op1))
26066 is_mulwiden = 1, op1 = XEXP (op1, 0);
26067 else if (CONST_INT_P (op1))
26069 if (GET_CODE (op0) == SIGN_EXTEND)
26070 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26073 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26077 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26080 *total = (cost->mult_init[MODE_INDEX (mode)]
26081 + nbits * cost->mult_bit
26082 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26091 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26092 /* ??? SSE cost should be used here. */
26093 *total = cost->fdiv;
26094 else if (X87_FLOAT_MODE_P (mode))
26095 *total = cost->fdiv;
26096 else if (FLOAT_MODE_P (mode))
26097 /* ??? SSE vector cost should be used here. */
26098 *total = cost->fdiv;
26100 *total = cost->divide[MODE_INDEX (mode)];
26104 if (GET_MODE_CLASS (mode) == MODE_INT
26105 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26107 if (GET_CODE (XEXP (x, 0)) == PLUS
26108 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26109 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26110 && CONSTANT_P (XEXP (x, 1)))
26112 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26113 if (val == 2 || val == 4 || val == 8)
26115 *total = cost->lea;
26116 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26117 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26118 outer_code, speed);
26119 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26123 else if (GET_CODE (XEXP (x, 0)) == MULT
26124 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26126 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26127 if (val == 2 || val == 4 || val == 8)
26129 *total = cost->lea;
26130 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26131 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26135 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26137 *total = cost->lea;
26138 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26139 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26140 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26147 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26149 /* ??? SSE cost should be used here. */
26150 *total = cost->fadd;
26153 else if (X87_FLOAT_MODE_P (mode))
26155 *total = cost->fadd;
26158 else if (FLOAT_MODE_P (mode))
26160 /* ??? SSE vector cost should be used here. */
26161 *total = cost->fadd;
26169 if (!TARGET_64BIT && mode == DImode)
26171 *total = (cost->add * 2
26172 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26173 << (GET_MODE (XEXP (x, 0)) != DImode))
26174 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26175 << (GET_MODE (XEXP (x, 1)) != DImode)));
26181 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26183 /* ??? SSE cost should be used here. */
26184 *total = cost->fchs;
26187 else if (X87_FLOAT_MODE_P (mode))
26189 *total = cost->fchs;
26192 else if (FLOAT_MODE_P (mode))
26194 /* ??? SSE vector cost should be used here. */
26195 *total = cost->fchs;
26201 if (!TARGET_64BIT && mode == DImode)
26202 *total = cost->add * 2;
26204 *total = cost->add;
26208 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26209 && XEXP (XEXP (x, 0), 1) == const1_rtx
26210 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26211 && XEXP (x, 1) == const0_rtx)
26213 /* This kind of construct is implemented using test[bwl].
26214 Treat it as if we had an AND. */
26215 *total = (cost->add
26216 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26217 + rtx_cost (const1_rtx, outer_code, speed));
26223 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26228 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26229 /* ??? SSE cost should be used here. */
26230 *total = cost->fabs;
26231 else if (X87_FLOAT_MODE_P (mode))
26232 *total = cost->fabs;
26233 else if (FLOAT_MODE_P (mode))
26234 /* ??? SSE vector cost should be used here. */
26235 *total = cost->fabs;
26239 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26240 /* ??? SSE cost should be used here. */
26241 *total = cost->fsqrt;
26242 else if (X87_FLOAT_MODE_P (mode))
26243 *total = cost->fsqrt;
26244 else if (FLOAT_MODE_P (mode))
26245 /* ??? SSE vector cost should be used here. */
26246 *total = cost->fsqrt;
26250 if (XINT (x, 1) == UNSPEC_TP)
26261 static int current_machopic_label_num;
26263 /* Given a symbol name and its associated stub, write out the
26264 definition of the stub. */
26267 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26269 unsigned int length;
26270 char *binder_name, *symbol_name, lazy_ptr_name[32];
26271 int label = ++current_machopic_label_num;
26273 /* For 64-bit we shouldn't get here. */
26274 gcc_assert (!TARGET_64BIT);
26276 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26277 symb = (*targetm.strip_name_encoding) (symb);
26279 length = strlen (stub);
26280 binder_name = XALLOCAVEC (char, length + 32);
26281 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26283 length = strlen (symb);
26284 symbol_name = XALLOCAVEC (char, length + 32);
26285 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26287 sprintf (lazy_ptr_name, "L%d$lz", label);
26290 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26292 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26294 fprintf (file, "%s:\n", stub);
26295 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26299 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26300 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26301 fprintf (file, "\tjmp\t*%%edx\n");
26304 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26306 fprintf (file, "%s:\n", binder_name);
26310 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26311 fputs ("\tpushl\t%eax\n", file);
26314 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26316 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
26318 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26319 fprintf (file, "%s:\n", lazy_ptr_name);
26320 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26321 fprintf (file, ASM_LONG "%s\n", binder_name);
26325 darwin_x86_file_end (void)
26327 darwin_file_end ();
26330 #endif /* TARGET_MACHO */
26332 /* Order the registers for register allocator. */
26335 x86_order_regs_for_local_alloc (void)
26340 /* First allocate the local general purpose registers. */
26341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26342 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26343 reg_alloc_order [pos++] = i;
26345 /* Global general purpose registers. */
26346 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26347 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26348 reg_alloc_order [pos++] = i;
26350 /* x87 registers come first in case we are doing FP math
26352 if (!TARGET_SSE_MATH)
26353 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26354 reg_alloc_order [pos++] = i;
26356 /* SSE registers. */
26357 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26358 reg_alloc_order [pos++] = i;
26359 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26360 reg_alloc_order [pos++] = i;
26362 /* x87 registers. */
26363 if (TARGET_SSE_MATH)
26364 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26365 reg_alloc_order [pos++] = i;
26367 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26368 reg_alloc_order [pos++] = i;
26370 /* Initialize the rest of array as we do not allocate some registers
26372 while (pos < FIRST_PSEUDO_REGISTER)
26373 reg_alloc_order [pos++] = 0;
26376 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26377 struct attribute_spec.handler. */
26379 ix86_handle_abi_attribute (tree *node, tree name,
26380 tree args ATTRIBUTE_UNUSED,
26381 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26383 if (TREE_CODE (*node) != FUNCTION_TYPE
26384 && TREE_CODE (*node) != METHOD_TYPE
26385 && TREE_CODE (*node) != FIELD_DECL
26386 && TREE_CODE (*node) != TYPE_DECL)
26388 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26390 *no_add_attrs = true;
26395 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26397 *no_add_attrs = true;
26401 /* Can combine regparm with all attributes but fastcall. */
26402 if (is_attribute_p ("ms_abi", name))
26404 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26406 error ("ms_abi and sysv_abi attributes are not compatible");
26411 else if (is_attribute_p ("sysv_abi", name))
26413 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26415 error ("ms_abi and sysv_abi attributes are not compatible");
26424 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26425 struct attribute_spec.handler. */
26427 ix86_handle_struct_attribute (tree *node, tree name,
26428 tree args ATTRIBUTE_UNUSED,
26429 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26432 if (DECL_P (*node))
26434 if (TREE_CODE (*node) == TYPE_DECL)
26435 type = &TREE_TYPE (*node);
26440 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26441 || TREE_CODE (*type) == UNION_TYPE)))
26443 warning (OPT_Wattributes, "%qE attribute ignored",
26445 *no_add_attrs = true;
26448 else if ((is_attribute_p ("ms_struct", name)
26449 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26450 || ((is_attribute_p ("gcc_struct", name)
26451 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26453 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26455 *no_add_attrs = true;
26462 ix86_ms_bitfield_layout_p (const_tree record_type)
26464 return (TARGET_MS_BITFIELD_LAYOUT &&
26465 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26466 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26469 /* Returns an expression indicating where the this parameter is
26470 located on entry to the FUNCTION. */
26473 x86_this_parameter (tree function)
26475 tree type = TREE_TYPE (function);
26476 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26481 const int *parm_regs;
26483 if (ix86_function_type_abi (type) == MS_ABI)
26484 parm_regs = x86_64_ms_abi_int_parameter_registers;
26486 parm_regs = x86_64_int_parameter_registers;
26487 return gen_rtx_REG (DImode, parm_regs[aggr]);
26490 nregs = ix86_function_regparm (type, function);
26492 if (nregs > 0 && !stdarg_p (type))
26496 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26497 regno = aggr ? DX_REG : CX_REG;
26505 return gen_rtx_MEM (SImode,
26506 plus_constant (stack_pointer_rtx, 4));
26509 return gen_rtx_REG (SImode, regno);
26512 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26515 /* Determine whether x86_output_mi_thunk can succeed. */
26518 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26519 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26520 HOST_WIDE_INT vcall_offset, const_tree function)
26522 /* 64-bit can handle anything. */
26526 /* For 32-bit, everything's fine if we have one free register. */
26527 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26530 /* Need a free register for vcall_offset. */
26534 /* Need a free register for GOT references. */
26535 if (flag_pic && !(*targetm.binds_local_p) (function))
26538 /* Otherwise ok. */
26542 /* Output the assembler code for a thunk function. THUNK_DECL is the
26543 declaration for the thunk function itself, FUNCTION is the decl for
26544 the target function. DELTA is an immediate constant offset to be
26545 added to THIS. If VCALL_OFFSET is nonzero, the word at
26546 *(*this + vcall_offset) should be added to THIS. */
26549 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26550 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26551 HOST_WIDE_INT vcall_offset, tree function)
26554 rtx this_param = x86_this_parameter (function);
26557 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26558 pull it in now and let DELTA benefit. */
26559 if (REG_P (this_param))
26560 this_reg = this_param;
26561 else if (vcall_offset)
26563 /* Put the this parameter into %eax. */
26564 xops[0] = this_param;
26565 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26566 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26569 this_reg = NULL_RTX;
26571 /* Adjust the this parameter by a fixed constant. */
26574 xops[0] = GEN_INT (delta);
26575 xops[1] = this_reg ? this_reg : this_param;
26578 if (!x86_64_general_operand (xops[0], DImode))
26580 tmp = gen_rtx_REG (DImode, R10_REG);
26582 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26584 xops[1] = this_param;
26586 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26589 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26592 /* Adjust the this parameter by a value stored in the vtable. */
26596 tmp = gen_rtx_REG (DImode, R10_REG);
26599 int tmp_regno = CX_REG;
26600 if (lookup_attribute ("fastcall",
26601 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26602 tmp_regno = AX_REG;
26603 tmp = gen_rtx_REG (SImode, tmp_regno);
26606 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26608 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26610 /* Adjust the this parameter. */
26611 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26612 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26614 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26615 xops[0] = GEN_INT (vcall_offset);
26617 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26618 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26620 xops[1] = this_reg;
26621 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26624 /* If necessary, drop THIS back to its stack slot. */
26625 if (this_reg && this_reg != this_param)
26627 xops[0] = this_reg;
26628 xops[1] = this_param;
26629 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26632 xops[0] = XEXP (DECL_RTL (function), 0);
26635 if (!flag_pic || (*targetm.binds_local_p) (function))
26636 output_asm_insn ("jmp\t%P0", xops);
26637 /* All thunks should be in the same object as their target,
26638 and thus binds_local_p should be true. */
26639 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26640 gcc_unreachable ();
26643 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26644 tmp = gen_rtx_CONST (Pmode, tmp);
26645 tmp = gen_rtx_MEM (QImode, tmp);
26647 output_asm_insn ("jmp\t%A0", xops);
26652 if (!flag_pic || (*targetm.binds_local_p) (function))
26653 output_asm_insn ("jmp\t%P0", xops);
26658 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26659 tmp = (gen_rtx_SYMBOL_REF
26661 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26662 tmp = gen_rtx_MEM (QImode, tmp);
26664 output_asm_insn ("jmp\t%0", xops);
26667 #endif /* TARGET_MACHO */
26669 tmp = gen_rtx_REG (SImode, CX_REG);
26670 output_set_got (tmp, NULL_RTX);
26673 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26674 output_asm_insn ("jmp\t{*}%1", xops);
26680 x86_file_start (void)
26682 default_file_start ();
26684 darwin_file_start ();
26686 if (X86_FILE_START_VERSION_DIRECTIVE)
26687 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26688 if (X86_FILE_START_FLTUSED)
26689 fputs ("\t.global\t__fltused\n", asm_out_file);
26690 if (ix86_asm_dialect == ASM_INTEL)
26691 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26695 x86_field_alignment (tree field, int computed)
26697 enum machine_mode mode;
26698 tree type = TREE_TYPE (field);
26700 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26702 mode = TYPE_MODE (strip_array_types (type));
26703 if (mode == DFmode || mode == DCmode
26704 || GET_MODE_CLASS (mode) == MODE_INT
26705 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26706 return MIN (32, computed);
26710 /* Output assembler code to FILE to increment profiler label # LABELNO
26711 for profiling a function entry. */
26713 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26717 #ifndef NO_PROFILE_COUNTERS
26718 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
26721 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26722 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
26724 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26728 #ifndef NO_PROFILE_COUNTERS
26729 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
26732 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
26736 #ifndef NO_PROFILE_COUNTERS
26737 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
26740 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26744 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26745 /* We don't have exact information about the insn sizes, but we may assume
26746 quite safely that we are informed about all 1 byte insns and memory
26747 address sizes. This is enough to eliminate unnecessary padding in
26751 min_insn_size (rtx insn)
26755 if (!INSN_P (insn) || !active_insn_p (insn))
26758 /* Discard alignments we've emit and jump instructions. */
26759 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26760 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26762 if (JUMP_TABLE_DATA_P (insn))
26765 /* Important case - calls are always 5 bytes.
26766 It is common to have many calls in the row. */
26768 && symbolic_reference_mentioned_p (PATTERN (insn))
26769 && !SIBLING_CALL_P (insn))
26771 len = get_attr_length (insn);
26775 /* For normal instructions we rely on get_attr_length being exact,
26776 with a few exceptions. */
26777 if (!JUMP_P (insn))
26779 enum attr_type type = get_attr_type (insn);
26784 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
26785 || asm_noperands (PATTERN (insn)) >= 0)
26792 /* Otherwise trust get_attr_length. */
26796 l = get_attr_length_address (insn);
26797 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26806 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26810 ix86_avoid_jump_mispredicts (void)
26812 rtx insn, start = get_insns ();
26813 int nbytes = 0, njumps = 0;
26816 /* Look for all minimal intervals of instructions containing 4 jumps.
26817 The intervals are bounded by START and INSN. NBYTES is the total
26818 size of instructions in the interval including INSN and not including
26819 START. When the NBYTES is smaller than 16 bytes, it is possible
26820 that the end of START and INSN ends up in the same 16byte page.
26822 The smallest offset in the page INSN can start is the case where START
26823 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26824 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26826 for (insn = start; insn; insn = NEXT_INSN (insn))
26830 if (LABEL_P (insn))
26832 int align = label_to_alignment (insn);
26833 int max_skip = label_to_max_skip (insn);
26837 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26838 already in the current 16 byte page, because otherwise
26839 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26840 bytes to reach 16 byte boundary. */
26842 || (align <= 3 && max_skip != (1 << align) - 1))
26845 fprintf (dump_file, "Label %i with max_skip %i\n",
26846 INSN_UID (insn), max_skip);
26849 while (nbytes + max_skip >= 16)
26851 start = NEXT_INSN (start);
26852 if ((JUMP_P (start)
26853 && GET_CODE (PATTERN (start)) != ADDR_VEC
26854 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26856 njumps--, isjump = 1;
26859 nbytes -= min_insn_size (start);
26865 min_size = min_insn_size (insn);
26866 nbytes += min_size;
26868 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
26869 INSN_UID (insn), min_size);
26871 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26872 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26880 start = NEXT_INSN (start);
26881 if ((JUMP_P (start)
26882 && GET_CODE (PATTERN (start)) != ADDR_VEC
26883 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26885 njumps--, isjump = 1;
26888 nbytes -= min_insn_size (start);
26890 gcc_assert (njumps >= 0);
26892 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26893 INSN_UID (start), INSN_UID (insn), nbytes);
26895 if (njumps == 3 && isjump && nbytes < 16)
26897 int padsize = 15 - nbytes + min_insn_size (insn);
26900 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26901 INSN_UID (insn), padsize);
26902 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
26908 /* AMD Athlon works faster
26909 when RET is not destination of conditional jump or directly preceded
26910 by other jump instruction. We avoid the penalty by inserting NOP just
26911 before the RET instructions in such cases. */
26913 ix86_pad_returns (void)
26918 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26920 basic_block bb = e->src;
26921 rtx ret = BB_END (bb);
26923 bool replace = false;
26925 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26926 || optimize_bb_for_size_p (bb))
26928 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26929 if (active_insn_p (prev) || LABEL_P (prev))
26931 if (prev && LABEL_P (prev))
26936 FOR_EACH_EDGE (e, ei, bb->preds)
26937 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26938 && !(e->flags & EDGE_FALLTHRU))
26943 prev = prev_active_insn (ret);
26945 && ((JUMP_P (prev) && any_condjump_p (prev))
26948 /* Empty functions get branch mispredict even when the jump destination
26949 is not visible to us. */
26950 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26955 emit_jump_insn_before (gen_return_internal_long (), ret);
26961 /* Implement machine specific optimizations. We implement padding of returns
26962 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26966 if (optimize && optimize_function_for_speed_p (cfun))
26968 if (TARGET_PAD_RETURNS)
26969 ix86_pad_returns ();
26970 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26971 if (TARGET_FOUR_JUMP_LIMIT)
26972 ix86_avoid_jump_mispredicts ();
26977 /* Return nonzero when QImode register that must be represented via REX prefix
26980 x86_extended_QIreg_mentioned_p (rtx insn)
26983 extract_insn_cached (insn);
26984 for (i = 0; i < recog_data.n_operands; i++)
26985 if (REG_P (recog_data.operand[i])
26986 && REGNO (recog_data.operand[i]) > BX_REG)
26991 /* Return nonzero when P points to register encoded via REX prefix.
26992 Called via for_each_rtx. */
26994 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26996 unsigned int regno;
26999 regno = REGNO (*p);
27000 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27003 /* Return true when INSN mentions register that must be encoded using REX
27006 x86_extended_reg_mentioned_p (rtx insn)
27008 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27009 extended_reg_mentioned_1, NULL);
27012 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27013 optabs would emit if we didn't have TFmode patterns. */
27016 x86_emit_floatuns (rtx operands[2])
27018 rtx neglab, donelab, i0, i1, f0, in, out;
27019 enum machine_mode mode, inmode;
27021 inmode = GET_MODE (operands[1]);
27022 gcc_assert (inmode == SImode || inmode == DImode);
27025 in = force_reg (inmode, operands[1]);
27026 mode = GET_MODE (out);
27027 neglab = gen_label_rtx ();
27028 donelab = gen_label_rtx ();
27029 f0 = gen_reg_rtx (mode);
27031 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27033 expand_float (out, in, 0);
27035 emit_jump_insn (gen_jump (donelab));
27038 emit_label (neglab);
27040 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27042 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27044 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27046 expand_float (f0, i0, 0);
27048 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27050 emit_label (donelab);
27053 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27054 with all elements equal to VAR. Return true if successful. */
27057 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27058 rtx target, rtx val)
27060 enum machine_mode hmode, smode, wsmode, wvmode;
27075 val = force_reg (GET_MODE_INNER (mode), val);
27076 x = gen_rtx_VEC_DUPLICATE (mode, val);
27077 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27083 if (TARGET_SSE || TARGET_3DNOW_A)
27085 val = gen_lowpart (SImode, val);
27086 x = gen_rtx_TRUNCATE (HImode, val);
27087 x = gen_rtx_VEC_DUPLICATE (mode, x);
27088 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27110 /* Extend HImode to SImode using a paradoxical SUBREG. */
27111 tmp1 = gen_reg_rtx (SImode);
27112 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27113 /* Insert the SImode value as low element of V4SImode vector. */
27114 tmp2 = gen_reg_rtx (V4SImode);
27115 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27116 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27117 CONST0_RTX (V4SImode),
27119 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27120 /* Cast the V4SImode vector back to a V8HImode vector. */
27121 tmp1 = gen_reg_rtx (V8HImode);
27122 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27123 /* Duplicate the low short through the whole low SImode word. */
27124 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27125 /* Cast the V8HImode vector back to a V4SImode vector. */
27126 tmp2 = gen_reg_rtx (V4SImode);
27127 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27128 /* Replicate the low element of the V4SImode vector. */
27129 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27130 /* Cast the V2SImode back to V8HImode, and store in target. */
27131 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27142 /* Extend QImode to SImode using a paradoxical SUBREG. */
27143 tmp1 = gen_reg_rtx (SImode);
27144 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27145 /* Insert the SImode value as low element of V4SImode vector. */
27146 tmp2 = gen_reg_rtx (V4SImode);
27147 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27148 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27149 CONST0_RTX (V4SImode),
27151 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27152 /* Cast the V4SImode vector back to a V16QImode vector. */
27153 tmp1 = gen_reg_rtx (V16QImode);
27154 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27155 /* Duplicate the low byte through the whole low SImode word. */
27156 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27157 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27158 /* Cast the V16QImode vector back to a V4SImode vector. */
27159 tmp2 = gen_reg_rtx (V4SImode);
27160 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27161 /* Replicate the low element of the V4SImode vector. */
27162 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27163 /* Cast the V2SImode back to V16QImode, and store in target. */
27164 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27172 /* Replicate the value once into the next wider mode and recurse. */
27173 val = convert_modes (wsmode, smode, val, true);
27174 x = expand_simple_binop (wsmode, ASHIFT, val,
27175 GEN_INT (GET_MODE_BITSIZE (smode)),
27176 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27177 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27179 x = gen_reg_rtx (wvmode);
27180 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27181 gcc_unreachable ();
27182 emit_move_insn (target, gen_lowpart (mode, x));
27205 rtx tmp = gen_reg_rtx (hmode);
27206 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27207 emit_insn (gen_rtx_SET (VOIDmode, target,
27208 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27217 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27218 whose ONE_VAR element is VAR, and other elements are zero. Return true
27222 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27223 rtx target, rtx var, int one_var)
27225 enum machine_mode vsimode;
27228 bool use_vector_set = false;
27233 /* For SSE4.1, we normally use vector set. But if the second
27234 element is zero and inter-unit moves are OK, we use movq
27236 use_vector_set = (TARGET_64BIT
27238 && !(TARGET_INTER_UNIT_MOVES
27244 use_vector_set = TARGET_SSE4_1;
27247 use_vector_set = TARGET_SSE2;
27250 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27257 use_vector_set = TARGET_AVX;
27260 /* Use ix86_expand_vector_set in 64bit mode only. */
27261 use_vector_set = TARGET_AVX && TARGET_64BIT;
27267 if (use_vector_set)
27269 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27270 var = force_reg (GET_MODE_INNER (mode), var);
27271 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27287 var = force_reg (GET_MODE_INNER (mode), var);
27288 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27289 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27294 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27295 new_target = gen_reg_rtx (mode);
27297 new_target = target;
27298 var = force_reg (GET_MODE_INNER (mode), var);
27299 x = gen_rtx_VEC_DUPLICATE (mode, var);
27300 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27301 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27304 /* We need to shuffle the value to the correct position, so
27305 create a new pseudo to store the intermediate result. */
27307 /* With SSE2, we can use the integer shuffle insns. */
27308 if (mode != V4SFmode && TARGET_SSE2)
27310 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27312 GEN_INT (one_var == 1 ? 0 : 1),
27313 GEN_INT (one_var == 2 ? 0 : 1),
27314 GEN_INT (one_var == 3 ? 0 : 1)));
27315 if (target != new_target)
27316 emit_move_insn (target, new_target);
27320 /* Otherwise convert the intermediate result to V4SFmode and
27321 use the SSE1 shuffle instructions. */
27322 if (mode != V4SFmode)
27324 tmp = gen_reg_rtx (V4SFmode);
27325 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27330 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27332 GEN_INT (one_var == 1 ? 0 : 1),
27333 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27334 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27336 if (mode != V4SFmode)
27337 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27338 else if (tmp != target)
27339 emit_move_insn (target, tmp);
27341 else if (target != new_target)
27342 emit_move_insn (target, new_target);
27347 vsimode = V4SImode;
27353 vsimode = V2SImode;
27359 /* Zero extend the variable element to SImode and recurse. */
27360 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27362 x = gen_reg_rtx (vsimode);
27363 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27365 gcc_unreachable ();
27367 emit_move_insn (target, gen_lowpart (mode, x));
27375 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27376 consisting of the values in VALS. It is known that all elements
27377 except ONE_VAR are constants. Return true if successful. */
27380 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27381 rtx target, rtx vals, int one_var)
27383 rtx var = XVECEXP (vals, 0, one_var);
27384 enum machine_mode wmode;
27387 const_vec = copy_rtx (vals);
27388 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27389 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27397 /* For the two element vectors, it's just as easy to use
27398 the general case. */
27402 /* Use ix86_expand_vector_set in 64bit mode only. */
27425 /* There's no way to set one QImode entry easily. Combine
27426 the variable value with its adjacent constant value, and
27427 promote to an HImode set. */
27428 x = XVECEXP (vals, 0, one_var ^ 1);
27431 var = convert_modes (HImode, QImode, var, true);
27432 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27433 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27434 x = GEN_INT (INTVAL (x) & 0xff);
27438 var = convert_modes (HImode, QImode, var, true);
27439 x = gen_int_mode (INTVAL (x) << 8, HImode);
27441 if (x != const0_rtx)
27442 var = expand_simple_binop (HImode, IOR, var, x, var,
27443 1, OPTAB_LIB_WIDEN);
27445 x = gen_reg_rtx (wmode);
27446 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27447 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27449 emit_move_insn (target, gen_lowpart (mode, x));
27456 emit_move_insn (target, const_vec);
27457 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27461 /* A subroutine of ix86_expand_vector_init_general. Use vector
27462 concatenate to handle the most general case: all values variable,
27463 and none identical. */
27466 ix86_expand_vector_init_concat (enum machine_mode mode,
27467 rtx target, rtx *ops, int n)
27469 enum machine_mode cmode, hmode = VOIDmode;
27470 rtx first[8], second[4];
27510 gcc_unreachable ();
27513 if (!register_operand (ops[1], cmode))
27514 ops[1] = force_reg (cmode, ops[1]);
27515 if (!register_operand (ops[0], cmode))
27516 ops[0] = force_reg (cmode, ops[0]);
27517 emit_insn (gen_rtx_SET (VOIDmode, target,
27518 gen_rtx_VEC_CONCAT (mode, ops[0],
27538 gcc_unreachable ();
27554 gcc_unreachable ();
27559 /* FIXME: We process inputs backward to help RA. PR 36222. */
27562 for (; i > 0; i -= 2, j--)
27564 first[j] = gen_reg_rtx (cmode);
27565 v = gen_rtvec (2, ops[i - 1], ops[i]);
27566 ix86_expand_vector_init (false, first[j],
27567 gen_rtx_PARALLEL (cmode, v));
27573 gcc_assert (hmode != VOIDmode);
27574 for (i = j = 0; i < n; i += 2, j++)
27576 second[j] = gen_reg_rtx (hmode);
27577 ix86_expand_vector_init_concat (hmode, second [j],
27581 ix86_expand_vector_init_concat (mode, target, second, n);
27584 ix86_expand_vector_init_concat (mode, target, first, n);
27588 gcc_unreachable ();
27592 /* A subroutine of ix86_expand_vector_init_general. Use vector
27593 interleave to handle the most general case: all values variable,
27594 and none identical. */
27597 ix86_expand_vector_init_interleave (enum machine_mode mode,
27598 rtx target, rtx *ops, int n)
27600 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27603 rtx (*gen_load_even) (rtx, rtx, rtx);
27604 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27605 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27610 gen_load_even = gen_vec_setv8hi;
27611 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27612 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27613 inner_mode = HImode;
27614 first_imode = V4SImode;
27615 second_imode = V2DImode;
27616 third_imode = VOIDmode;
27619 gen_load_even = gen_vec_setv16qi;
27620 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27621 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27622 inner_mode = QImode;
27623 first_imode = V8HImode;
27624 second_imode = V4SImode;
27625 third_imode = V2DImode;
27628 gcc_unreachable ();
27631 for (i = 0; i < n; i++)
27633 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27634 op0 = gen_reg_rtx (SImode);
27635 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27637 /* Insert the SImode value as low element of V4SImode vector. */
27638 op1 = gen_reg_rtx (V4SImode);
27639 op0 = gen_rtx_VEC_MERGE (V4SImode,
27640 gen_rtx_VEC_DUPLICATE (V4SImode,
27642 CONST0_RTX (V4SImode),
27644 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27646 /* Cast the V4SImode vector back to a vector in orignal mode. */
27647 op0 = gen_reg_rtx (mode);
27648 emit_move_insn (op0, gen_lowpart (mode, op1));
27650 /* Load even elements into the second positon. */
27651 emit_insn ((*gen_load_even) (op0,
27652 force_reg (inner_mode,
27656 /* Cast vector to FIRST_IMODE vector. */
27657 ops[i] = gen_reg_rtx (first_imode);
27658 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27661 /* Interleave low FIRST_IMODE vectors. */
27662 for (i = j = 0; i < n; i += 2, j++)
27664 op0 = gen_reg_rtx (first_imode);
27665 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27667 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27668 ops[j] = gen_reg_rtx (second_imode);
27669 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27672 /* Interleave low SECOND_IMODE vectors. */
27673 switch (second_imode)
27676 for (i = j = 0; i < n / 2; i += 2, j++)
27678 op0 = gen_reg_rtx (second_imode);
27679 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27682 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27684 ops[j] = gen_reg_rtx (third_imode);
27685 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27687 second_imode = V2DImode;
27688 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27692 op0 = gen_reg_rtx (second_imode);
27693 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27696 /* Cast the SECOND_IMODE vector back to a vector on original
27698 emit_insn (gen_rtx_SET (VOIDmode, target,
27699 gen_lowpart (mode, op0)));
27703 gcc_unreachable ();
27707 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27708 all values variable, and none identical. */
27711 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27712 rtx target, rtx vals)
27714 rtx ops[32], op0, op1;
27715 enum machine_mode half_mode = VOIDmode;
27722 if (!mmx_ok && !TARGET_SSE)
27734 n = GET_MODE_NUNITS (mode);
27735 for (i = 0; i < n; i++)
27736 ops[i] = XVECEXP (vals, 0, i);
27737 ix86_expand_vector_init_concat (mode, target, ops, n);
27741 half_mode = V16QImode;
27745 half_mode = V8HImode;
27749 n = GET_MODE_NUNITS (mode);
27750 for (i = 0; i < n; i++)
27751 ops[i] = XVECEXP (vals, 0, i);
27752 op0 = gen_reg_rtx (half_mode);
27753 op1 = gen_reg_rtx (half_mode);
27754 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27756 ix86_expand_vector_init_interleave (half_mode, op1,
27757 &ops [n >> 1], n >> 2);
27758 emit_insn (gen_rtx_SET (VOIDmode, target,
27759 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27763 if (!TARGET_SSE4_1)
27771 /* Don't use ix86_expand_vector_init_interleave if we can't
27772 move from GPR to SSE register directly. */
27773 if (!TARGET_INTER_UNIT_MOVES)
27776 n = GET_MODE_NUNITS (mode);
27777 for (i = 0; i < n; i++)
27778 ops[i] = XVECEXP (vals, 0, i);
27779 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27787 gcc_unreachable ();
27791 int i, j, n_elts, n_words, n_elt_per_word;
27792 enum machine_mode inner_mode;
27793 rtx words[4], shift;
27795 inner_mode = GET_MODE_INNER (mode);
27796 n_elts = GET_MODE_NUNITS (mode);
27797 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27798 n_elt_per_word = n_elts / n_words;
27799 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27801 for (i = 0; i < n_words; ++i)
27803 rtx word = NULL_RTX;
27805 for (j = 0; j < n_elt_per_word; ++j)
27807 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27808 elt = convert_modes (word_mode, inner_mode, elt, true);
27814 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27815 word, 1, OPTAB_LIB_WIDEN);
27816 word = expand_simple_binop (word_mode, IOR, word, elt,
27817 word, 1, OPTAB_LIB_WIDEN);
27825 emit_move_insn (target, gen_lowpart (mode, words[0]));
27826 else if (n_words == 2)
27828 rtx tmp = gen_reg_rtx (mode);
27829 emit_clobber (tmp);
27830 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27831 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27832 emit_move_insn (target, tmp);
27834 else if (n_words == 4)
27836 rtx tmp = gen_reg_rtx (V4SImode);
27837 gcc_assert (word_mode == SImode);
27838 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27839 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27840 emit_move_insn (target, gen_lowpart (mode, tmp));
27843 gcc_unreachable ();
27847 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27848 instructions unless MMX_OK is true. */
27851 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27853 enum machine_mode mode = GET_MODE (target);
27854 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27855 int n_elts = GET_MODE_NUNITS (mode);
27856 int n_var = 0, one_var = -1;
27857 bool all_same = true, all_const_zero = true;
27861 for (i = 0; i < n_elts; ++i)
27863 x = XVECEXP (vals, 0, i);
27864 if (!(CONST_INT_P (x)
27865 || GET_CODE (x) == CONST_DOUBLE
27866 || GET_CODE (x) == CONST_FIXED))
27867 n_var++, one_var = i;
27868 else if (x != CONST0_RTX (inner_mode))
27869 all_const_zero = false;
27870 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27874 /* Constants are best loaded from the constant pool. */
27877 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27881 /* If all values are identical, broadcast the value. */
27883 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27884 XVECEXP (vals, 0, 0)))
27887 /* Values where only one field is non-constant are best loaded from
27888 the pool and overwritten via move later. */
27892 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27893 XVECEXP (vals, 0, one_var),
27897 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27901 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27905 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27907 enum machine_mode mode = GET_MODE (target);
27908 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27909 enum machine_mode half_mode;
27910 bool use_vec_merge = false;
27912 static rtx (*gen_extract[6][2]) (rtx, rtx)
27914 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27915 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27916 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27917 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27918 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27919 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27921 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27923 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27924 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27925 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27926 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27927 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27928 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27938 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27939 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27941 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27943 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27944 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27950 use_vec_merge = TARGET_SSE4_1;
27958 /* For the two element vectors, we implement a VEC_CONCAT with
27959 the extraction of the other element. */
27961 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27962 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27965 op0 = val, op1 = tmp;
27967 op0 = tmp, op1 = val;
27969 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27970 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27975 use_vec_merge = TARGET_SSE4_1;
27982 use_vec_merge = true;
27986 /* tmp = target = A B C D */
27987 tmp = copy_to_reg (target);
27988 /* target = A A B B */
27989 emit_insn (gen_sse_unpcklps (target, target, target));
27990 /* target = X A B B */
27991 ix86_expand_vector_set (false, target, val, 0);
27992 /* target = A X C D */
27993 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27994 const1_rtx, const0_rtx,
27995 GEN_INT (2+4), GEN_INT (3+4)));
27999 /* tmp = target = A B C D */
28000 tmp = copy_to_reg (target);
28001 /* tmp = X B C D */
28002 ix86_expand_vector_set (false, tmp, val, 0);
28003 /* target = A B X D */
28004 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28005 const0_rtx, const1_rtx,
28006 GEN_INT (0+4), GEN_INT (3+4)));
28010 /* tmp = target = A B C D */
28011 tmp = copy_to_reg (target);
28012 /* tmp = X B C D */
28013 ix86_expand_vector_set (false, tmp, val, 0);
28014 /* target = A B X D */
28015 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28016 const0_rtx, const1_rtx,
28017 GEN_INT (2+4), GEN_INT (0+4)));
28021 gcc_unreachable ();
28026 use_vec_merge = TARGET_SSE4_1;
28030 /* Element 0 handled by vec_merge below. */
28033 use_vec_merge = true;
28039 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28040 store into element 0, then shuffle them back. */
28044 order[0] = GEN_INT (elt);
28045 order[1] = const1_rtx;
28046 order[2] = const2_rtx;
28047 order[3] = GEN_INT (3);
28048 order[elt] = const0_rtx;
28050 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28051 order[1], order[2], order[3]));
28053 ix86_expand_vector_set (false, target, val, 0);
28055 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28056 order[1], order[2], order[3]));
28060 /* For SSE1, we have to reuse the V4SF code. */
28061 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28062 gen_lowpart (SFmode, val), elt);
28067 use_vec_merge = TARGET_SSE2;
28070 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28074 use_vec_merge = TARGET_SSE4_1;
28081 half_mode = V16QImode;
28087 half_mode = V8HImode;
28093 half_mode = V4SImode;
28099 half_mode = V2DImode;
28105 half_mode = V4SFmode;
28111 half_mode = V2DFmode;
28117 /* Compute offset. */
28121 gcc_assert (i <= 1);
28123 /* Extract the half. */
28124 tmp = gen_reg_rtx (half_mode);
28125 emit_insn ((*gen_extract[j][i]) (tmp, target));
28127 /* Put val in tmp at elt. */
28128 ix86_expand_vector_set (false, tmp, val, elt);
28131 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28140 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28141 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28142 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28146 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28148 emit_move_insn (mem, target);
28150 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28151 emit_move_insn (tmp, val);
28153 emit_move_insn (target, mem);
28158 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28160 enum machine_mode mode = GET_MODE (vec);
28161 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28162 bool use_vec_extr = false;
28175 use_vec_extr = true;
28179 use_vec_extr = TARGET_SSE4_1;
28191 tmp = gen_reg_rtx (mode);
28192 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28193 GEN_INT (elt), GEN_INT (elt),
28194 GEN_INT (elt+4), GEN_INT (elt+4)));
28198 tmp = gen_reg_rtx (mode);
28199 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28203 gcc_unreachable ();
28206 use_vec_extr = true;
28211 use_vec_extr = TARGET_SSE4_1;
28225 tmp = gen_reg_rtx (mode);
28226 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28227 GEN_INT (elt), GEN_INT (elt),
28228 GEN_INT (elt), GEN_INT (elt)));
28232 tmp = gen_reg_rtx (mode);
28233 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28237 gcc_unreachable ();
28240 use_vec_extr = true;
28245 /* For SSE1, we have to reuse the V4SF code. */
28246 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28247 gen_lowpart (V4SFmode, vec), elt);
28253 use_vec_extr = TARGET_SSE2;
28256 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28260 use_vec_extr = TARGET_SSE4_1;
28264 /* ??? Could extract the appropriate HImode element and shift. */
28271 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28272 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28274 /* Let the rtl optimizers know about the zero extension performed. */
28275 if (inner_mode == QImode || inner_mode == HImode)
28277 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28278 target = gen_lowpart (SImode, target);
28281 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28285 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28287 emit_move_insn (mem, vec);
28289 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28290 emit_move_insn (target, tmp);
28294 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28295 pattern to reduce; DEST is the destination; IN is the input vector. */
28298 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28300 rtx tmp1, tmp2, tmp3;
28302 tmp1 = gen_reg_rtx (V4SFmode);
28303 tmp2 = gen_reg_rtx (V4SFmode);
28304 tmp3 = gen_reg_rtx (V4SFmode);
28306 emit_insn (gen_sse_movhlps (tmp1, in, in));
28307 emit_insn (fn (tmp2, tmp1, in));
28309 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28310 const1_rtx, const1_rtx,
28311 GEN_INT (1+4), GEN_INT (1+4)));
28312 emit_insn (fn (dest, tmp2, tmp3));
28315 /* Target hook for scalar_mode_supported_p. */
28317 ix86_scalar_mode_supported_p (enum machine_mode mode)
28319 if (DECIMAL_FLOAT_MODE_P (mode))
28320 return default_decimal_float_supported_p ();
28321 else if (mode == TFmode)
28324 return default_scalar_mode_supported_p (mode);
28327 /* Implements target hook vector_mode_supported_p. */
28329 ix86_vector_mode_supported_p (enum machine_mode mode)
28331 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28333 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28335 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28337 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28339 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28344 /* Target hook for c_mode_for_suffix. */
28345 static enum machine_mode
28346 ix86_c_mode_for_suffix (char suffix)
28356 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28358 We do this in the new i386 backend to maintain source compatibility
28359 with the old cc0-based compiler. */
28362 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28363 tree inputs ATTRIBUTE_UNUSED,
28366 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28368 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28373 /* Implements target vector targetm.asm.encode_section_info. This
28374 is not used by netware. */
28376 static void ATTRIBUTE_UNUSED
28377 ix86_encode_section_info (tree decl, rtx rtl, int first)
28379 default_encode_section_info (decl, rtl, first);
28381 if (TREE_CODE (decl) == VAR_DECL
28382 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28383 && ix86_in_large_data_p (decl))
28384 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28387 /* Worker function for REVERSE_CONDITION. */
28390 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28392 return (mode != CCFPmode && mode != CCFPUmode
28393 ? reverse_condition (code)
28394 : reverse_condition_maybe_unordered (code));
28397 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28401 output_387_reg_move (rtx insn, rtx *operands)
28403 if (REG_P (operands[0]))
28405 if (REG_P (operands[1])
28406 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28408 if (REGNO (operands[0]) == FIRST_STACK_REG)
28409 return output_387_ffreep (operands, 0);
28410 return "fstp\t%y0";
28412 if (STACK_TOP_P (operands[0]))
28413 return "fld%Z1\t%y1";
28416 else if (MEM_P (operands[0]))
28418 gcc_assert (REG_P (operands[1]));
28419 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28420 return "fstp%Z0\t%y0";
28423 /* There is no non-popping store to memory for XFmode.
28424 So if we need one, follow the store with a load. */
28425 if (GET_MODE (operands[0]) == XFmode)
28426 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28428 return "fst%Z0\t%y0";
28435 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28436 FP status register is set. */
28439 ix86_emit_fp_unordered_jump (rtx label)
28441 rtx reg = gen_reg_rtx (HImode);
28444 emit_insn (gen_x86_fnstsw_1 (reg));
28446 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28448 emit_insn (gen_x86_sahf_1 (reg));
28450 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28451 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28455 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28457 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28458 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28461 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28462 gen_rtx_LABEL_REF (VOIDmode, label),
28464 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28466 emit_jump_insn (temp);
28467 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28470 /* Output code to perform a log1p XFmode calculation. */
28472 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28474 rtx label1 = gen_label_rtx ();
28475 rtx label2 = gen_label_rtx ();
28477 rtx tmp = gen_reg_rtx (XFmode);
28478 rtx tmp2 = gen_reg_rtx (XFmode);
28481 emit_insn (gen_absxf2 (tmp, op1));
28482 test = gen_rtx_GE (VOIDmode, tmp,
28483 CONST_DOUBLE_FROM_REAL_VALUE (
28484 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28486 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28488 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28489 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28490 emit_jump (label2);
28492 emit_label (label1);
28493 emit_move_insn (tmp, CONST1_RTX (XFmode));
28494 emit_insn (gen_addxf3 (tmp, op1, tmp));
28495 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28496 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28498 emit_label (label2);
28501 /* Output code to perform a Newton-Rhapson approximation of a single precision
28502 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28504 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28506 rtx x0, x1, e0, e1, two;
28508 x0 = gen_reg_rtx (mode);
28509 e0 = gen_reg_rtx (mode);
28510 e1 = gen_reg_rtx (mode);
28511 x1 = gen_reg_rtx (mode);
28513 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28515 if (VECTOR_MODE_P (mode))
28516 two = ix86_build_const_vector (SFmode, true, two);
28518 two = force_reg (mode, two);
28520 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28522 /* x0 = rcp(b) estimate */
28523 emit_insn (gen_rtx_SET (VOIDmode, x0,
28524 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28527 emit_insn (gen_rtx_SET (VOIDmode, e0,
28528 gen_rtx_MULT (mode, x0, b)));
28530 emit_insn (gen_rtx_SET (VOIDmode, e1,
28531 gen_rtx_MINUS (mode, two, e0)));
28533 emit_insn (gen_rtx_SET (VOIDmode, x1,
28534 gen_rtx_MULT (mode, x0, e1)));
28536 emit_insn (gen_rtx_SET (VOIDmode, res,
28537 gen_rtx_MULT (mode, a, x1)));
28540 /* Output code to perform a Newton-Rhapson approximation of a
28541 single precision floating point [reciprocal] square root. */
28543 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28546 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28549 x0 = gen_reg_rtx (mode);
28550 e0 = gen_reg_rtx (mode);
28551 e1 = gen_reg_rtx (mode);
28552 e2 = gen_reg_rtx (mode);
28553 e3 = gen_reg_rtx (mode);
28555 real_from_integer (&r, VOIDmode, -3, -1, 0);
28556 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28558 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28559 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28561 if (VECTOR_MODE_P (mode))
28563 mthree = ix86_build_const_vector (SFmode, true, mthree);
28564 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28567 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28568 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28570 /* x0 = rsqrt(a) estimate */
28571 emit_insn (gen_rtx_SET (VOIDmode, x0,
28572 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28575 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28580 zero = gen_reg_rtx (mode);
28581 mask = gen_reg_rtx (mode);
28583 zero = force_reg (mode, CONST0_RTX(mode));
28584 emit_insn (gen_rtx_SET (VOIDmode, mask,
28585 gen_rtx_NE (mode, zero, a)));
28587 emit_insn (gen_rtx_SET (VOIDmode, x0,
28588 gen_rtx_AND (mode, x0, mask)));
28592 emit_insn (gen_rtx_SET (VOIDmode, e0,
28593 gen_rtx_MULT (mode, x0, a)));
28595 emit_insn (gen_rtx_SET (VOIDmode, e1,
28596 gen_rtx_MULT (mode, e0, x0)));
28599 mthree = force_reg (mode, mthree);
28600 emit_insn (gen_rtx_SET (VOIDmode, e2,
28601 gen_rtx_PLUS (mode, e1, mthree)));
28603 mhalf = force_reg (mode, mhalf);
28605 /* e3 = -.5 * x0 */
28606 emit_insn (gen_rtx_SET (VOIDmode, e3,
28607 gen_rtx_MULT (mode, x0, mhalf)));
28609 /* e3 = -.5 * e0 */
28610 emit_insn (gen_rtx_SET (VOIDmode, e3,
28611 gen_rtx_MULT (mode, e0, mhalf)));
28612 /* ret = e2 * e3 */
28613 emit_insn (gen_rtx_SET (VOIDmode, res,
28614 gen_rtx_MULT (mode, e2, e3)));
28617 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28619 static void ATTRIBUTE_UNUSED
28620 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28623 /* With Binutils 2.15, the "@unwind" marker must be specified on
28624 every occurrence of the ".eh_frame" section, not just the first
28627 && strcmp (name, ".eh_frame") == 0)
28629 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28630 flags & SECTION_WRITE ? "aw" : "a");
28633 default_elf_asm_named_section (name, flags, decl);
28636 /* Return the mangling of TYPE if it is an extended fundamental type. */
28638 static const char *
28639 ix86_mangle_type (const_tree type)
28641 type = TYPE_MAIN_VARIANT (type);
28643 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28644 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28647 switch (TYPE_MODE (type))
28650 /* __float128 is "g". */
28653 /* "long double" or __float80 is "e". */
28660 /* For 32-bit code we can save PIC register setup by using
28661 __stack_chk_fail_local hidden function instead of calling
28662 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28663 register, so it is better to call __stack_chk_fail directly. */
28666 ix86_stack_protect_fail (void)
28668 return TARGET_64BIT
28669 ? default_external_stack_protect_fail ()
28670 : default_hidden_stack_protect_fail ();
28673 /* Select a format to encode pointers in exception handling data. CODE
28674 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28675 true if the symbol may be affected by dynamic relocations.
28677 ??? All x86 object file formats are capable of representing this.
28678 After all, the relocation needed is the same as for the call insn.
28679 Whether or not a particular assembler allows us to enter such, I
28680 guess we'll have to see. */
28682 asm_preferred_eh_data_format (int code, int global)
28686 int type = DW_EH_PE_sdata8;
28688 || ix86_cmodel == CM_SMALL_PIC
28689 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28690 type = DW_EH_PE_sdata4;
28691 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28693 if (ix86_cmodel == CM_SMALL
28694 || (ix86_cmodel == CM_MEDIUM && code))
28695 return DW_EH_PE_udata4;
28696 return DW_EH_PE_absptr;
28699 /* Expand copysign from SIGN to the positive value ABS_VALUE
28700 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28703 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28705 enum machine_mode mode = GET_MODE (sign);
28706 rtx sgn = gen_reg_rtx (mode);
28707 if (mask == NULL_RTX)
28709 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28710 if (!VECTOR_MODE_P (mode))
28712 /* We need to generate a scalar mode mask in this case. */
28713 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28714 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28715 mask = gen_reg_rtx (mode);
28716 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28720 mask = gen_rtx_NOT (mode, mask);
28721 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28722 gen_rtx_AND (mode, mask, sign)));
28723 emit_insn (gen_rtx_SET (VOIDmode, result,
28724 gen_rtx_IOR (mode, abs_value, sgn)));
28727 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28728 mask for masking out the sign-bit is stored in *SMASK, if that is
28731 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28733 enum machine_mode mode = GET_MODE (op0);
28736 xa = gen_reg_rtx (mode);
28737 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28738 if (!VECTOR_MODE_P (mode))
28740 /* We need to generate a scalar mode mask in this case. */
28741 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28742 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28743 mask = gen_reg_rtx (mode);
28744 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28746 emit_insn (gen_rtx_SET (VOIDmode, xa,
28747 gen_rtx_AND (mode, op0, mask)));
28755 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28756 swapping the operands if SWAP_OPERANDS is true. The expanded
28757 code is a forward jump to a newly created label in case the
28758 comparison is true. The generated label rtx is returned. */
28760 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28761 bool swap_operands)
28772 label = gen_label_rtx ();
28773 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28774 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28775 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28776 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28777 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28778 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28779 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28780 JUMP_LABEL (tmp) = label;
28785 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28786 using comparison code CODE. Operands are swapped for the comparison if
28787 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28789 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28790 bool swap_operands)
28792 enum machine_mode mode = GET_MODE (op0);
28793 rtx mask = gen_reg_rtx (mode);
28802 if (mode == DFmode)
28803 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28804 gen_rtx_fmt_ee (code, mode, op0, op1)));
28806 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28807 gen_rtx_fmt_ee (code, mode, op0, op1)));
28812 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28813 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28815 ix86_gen_TWO52 (enum machine_mode mode)
28817 REAL_VALUE_TYPE TWO52r;
28820 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28821 TWO52 = const_double_from_real_value (TWO52r, mode);
28822 TWO52 = force_reg (mode, TWO52);
28827 /* Expand SSE sequence for computing lround from OP1 storing
28830 ix86_expand_lround (rtx op0, rtx op1)
28832 /* C code for the stuff we're doing below:
28833 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28836 enum machine_mode mode = GET_MODE (op1);
28837 const struct real_format *fmt;
28838 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28841 /* load nextafter (0.5, 0.0) */
28842 fmt = REAL_MODE_FORMAT (mode);
28843 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28844 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28846 /* adj = copysign (0.5, op1) */
28847 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28848 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28850 /* adj = op1 + adj */
28851 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28853 /* op0 = (imode)adj */
28854 expand_fix (op0, adj, 0);
28857 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28860 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28862 /* C code for the stuff we're doing below (for do_floor):
28864 xi -= (double)xi > op1 ? 1 : 0;
28867 enum machine_mode fmode = GET_MODE (op1);
28868 enum machine_mode imode = GET_MODE (op0);
28869 rtx ireg, freg, label, tmp;
28871 /* reg = (long)op1 */
28872 ireg = gen_reg_rtx (imode);
28873 expand_fix (ireg, op1, 0);
28875 /* freg = (double)reg */
28876 freg = gen_reg_rtx (fmode);
28877 expand_float (freg, ireg, 0);
28879 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28880 label = ix86_expand_sse_compare_and_jump (UNLE,
28881 freg, op1, !do_floor);
28882 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28883 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28884 emit_move_insn (ireg, tmp);
28886 emit_label (label);
28887 LABEL_NUSES (label) = 1;
28889 emit_move_insn (op0, ireg);
28892 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28893 result in OPERAND0. */
28895 ix86_expand_rint (rtx operand0, rtx operand1)
28897 /* C code for the stuff we're doing below:
28898 xa = fabs (operand1);
28899 if (!isless (xa, 2**52))
28901 xa = xa + 2**52 - 2**52;
28902 return copysign (xa, operand1);
28904 enum machine_mode mode = GET_MODE (operand0);
28905 rtx res, xa, label, TWO52, mask;
28907 res = gen_reg_rtx (mode);
28908 emit_move_insn (res, operand1);
28910 /* xa = abs (operand1) */
28911 xa = ix86_expand_sse_fabs (res, &mask);
28913 /* if (!isless (xa, TWO52)) goto label; */
28914 TWO52 = ix86_gen_TWO52 (mode);
28915 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28917 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28918 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28920 ix86_sse_copysign_to_positive (res, xa, res, mask);
28922 emit_label (label);
28923 LABEL_NUSES (label) = 1;
28925 emit_move_insn (operand0, res);
28928 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28931 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28933 /* C code for the stuff we expand below.
28934 double xa = fabs (x), x2;
28935 if (!isless (xa, TWO52))
28937 xa = xa + TWO52 - TWO52;
28938 x2 = copysign (xa, x);
28947 enum machine_mode mode = GET_MODE (operand0);
28948 rtx xa, TWO52, tmp, label, one, res, mask;
28950 TWO52 = ix86_gen_TWO52 (mode);
28952 /* Temporary for holding the result, initialized to the input
28953 operand to ease control flow. */
28954 res = gen_reg_rtx (mode);
28955 emit_move_insn (res, operand1);
28957 /* xa = abs (operand1) */
28958 xa = ix86_expand_sse_fabs (res, &mask);
28960 /* if (!isless (xa, TWO52)) goto label; */
28961 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28963 /* xa = xa + TWO52 - TWO52; */
28964 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28965 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28967 /* xa = copysign (xa, operand1) */
28968 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28970 /* generate 1.0 or -1.0 */
28971 one = force_reg (mode,
28972 const_double_from_real_value (do_floor
28973 ? dconst1 : dconstm1, mode));
28975 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28976 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28977 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28978 gen_rtx_AND (mode, one, tmp)));
28979 /* We always need to subtract here to preserve signed zero. */
28980 tmp = expand_simple_binop (mode, MINUS,
28981 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28982 emit_move_insn (res, tmp);
28984 emit_label (label);
28985 LABEL_NUSES (label) = 1;
28987 emit_move_insn (operand0, res);
28990 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28993 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28995 /* C code for the stuff we expand below.
28996 double xa = fabs (x), x2;
28997 if (!isless (xa, TWO52))
28999 x2 = (double)(long)x;
29006 if (HONOR_SIGNED_ZEROS (mode))
29007 return copysign (x2, x);
29010 enum machine_mode mode = GET_MODE (operand0);
29011 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29013 TWO52 = ix86_gen_TWO52 (mode);
29015 /* Temporary for holding the result, initialized to the input
29016 operand to ease control flow. */
29017 res = gen_reg_rtx (mode);
29018 emit_move_insn (res, operand1);
29020 /* xa = abs (operand1) */
29021 xa = ix86_expand_sse_fabs (res, &mask);
29023 /* if (!isless (xa, TWO52)) goto label; */
29024 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29026 /* xa = (double)(long)x */
29027 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29028 expand_fix (xi, res, 0);
29029 expand_float (xa, xi, 0);
29032 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29034 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29035 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29036 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29037 gen_rtx_AND (mode, one, tmp)));
29038 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29039 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29040 emit_move_insn (res, tmp);
29042 if (HONOR_SIGNED_ZEROS (mode))
29043 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29045 emit_label (label);
29046 LABEL_NUSES (label) = 1;
29048 emit_move_insn (operand0, res);
29051 /* Expand SSE sequence for computing round from OPERAND1 storing
29052 into OPERAND0. Sequence that works without relying on DImode truncation
29053 via cvttsd2siq that is only available on 64bit targets. */
29055 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29057 /* C code for the stuff we expand below.
29058 double xa = fabs (x), xa2, x2;
29059 if (!isless (xa, TWO52))
29061 Using the absolute value and copying back sign makes
29062 -0.0 -> -0.0 correct.
29063 xa2 = xa + TWO52 - TWO52;
29068 else if (dxa > 0.5)
29070 x2 = copysign (xa2, x);
29073 enum machine_mode mode = GET_MODE (operand0);
29074 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29076 TWO52 = ix86_gen_TWO52 (mode);
29078 /* Temporary for holding the result, initialized to the input
29079 operand to ease control flow. */
29080 res = gen_reg_rtx (mode);
29081 emit_move_insn (res, operand1);
29083 /* xa = abs (operand1) */
29084 xa = ix86_expand_sse_fabs (res, &mask);
29086 /* if (!isless (xa, TWO52)) goto label; */
29087 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29089 /* xa2 = xa + TWO52 - TWO52; */
29090 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29091 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29093 /* dxa = xa2 - xa; */
29094 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29096 /* generate 0.5, 1.0 and -0.5 */
29097 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29098 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29099 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29103 tmp = gen_reg_rtx (mode);
29104 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29105 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29106 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29107 gen_rtx_AND (mode, one, tmp)));
29108 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29109 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29110 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29111 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29112 gen_rtx_AND (mode, one, tmp)));
29113 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29115 /* res = copysign (xa2, operand1) */
29116 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29118 emit_label (label);
29119 LABEL_NUSES (label) = 1;
29121 emit_move_insn (operand0, res);
29124 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29127 ix86_expand_trunc (rtx operand0, rtx operand1)
29129 /* C code for SSE variant we expand below.
29130 double xa = fabs (x), x2;
29131 if (!isless (xa, TWO52))
29133 x2 = (double)(long)x;
29134 if (HONOR_SIGNED_ZEROS (mode))
29135 return copysign (x2, x);
29138 enum machine_mode mode = GET_MODE (operand0);
29139 rtx xa, xi, TWO52, label, res, mask;
29141 TWO52 = ix86_gen_TWO52 (mode);
29143 /* Temporary for holding the result, initialized to the input
29144 operand to ease control flow. */
29145 res = gen_reg_rtx (mode);
29146 emit_move_insn (res, operand1);
29148 /* xa = abs (operand1) */
29149 xa = ix86_expand_sse_fabs (res, &mask);
29151 /* if (!isless (xa, TWO52)) goto label; */
29152 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29154 /* x = (double)(long)x */
29155 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29156 expand_fix (xi, res, 0);
29157 expand_float (res, xi, 0);
29159 if (HONOR_SIGNED_ZEROS (mode))
29160 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29162 emit_label (label);
29163 LABEL_NUSES (label) = 1;
29165 emit_move_insn (operand0, res);
29168 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29171 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29173 enum machine_mode mode = GET_MODE (operand0);
29174 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29176 /* C code for SSE variant we expand below.
29177 double xa = fabs (x), x2;
29178 if (!isless (xa, TWO52))
29180 xa2 = xa + TWO52 - TWO52;
29184 x2 = copysign (xa2, x);
29188 TWO52 = ix86_gen_TWO52 (mode);
29190 /* Temporary for holding the result, initialized to the input
29191 operand to ease control flow. */
29192 res = gen_reg_rtx (mode);
29193 emit_move_insn (res, operand1);
29195 /* xa = abs (operand1) */
29196 xa = ix86_expand_sse_fabs (res, &smask);
29198 /* if (!isless (xa, TWO52)) goto label; */
29199 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29201 /* res = xa + TWO52 - TWO52; */
29202 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29203 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29204 emit_move_insn (res, tmp);
29207 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29209 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29210 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29211 emit_insn (gen_rtx_SET (VOIDmode, mask,
29212 gen_rtx_AND (mode, mask, one)));
29213 tmp = expand_simple_binop (mode, MINUS,
29214 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29215 emit_move_insn (res, tmp);
29217 /* res = copysign (res, operand1) */
29218 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29220 emit_label (label);
29221 LABEL_NUSES (label) = 1;
29223 emit_move_insn (operand0, res);
29226 /* Expand SSE sequence for computing round from OPERAND1 storing
29229 ix86_expand_round (rtx operand0, rtx operand1)
29231 /* C code for the stuff we're doing below:
29232 double xa = fabs (x);
29233 if (!isless (xa, TWO52))
29235 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29236 return copysign (xa, x);
29238 enum machine_mode mode = GET_MODE (operand0);
29239 rtx res, TWO52, xa, label, xi, half, mask;
29240 const struct real_format *fmt;
29241 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29243 /* Temporary for holding the result, initialized to the input
29244 operand to ease control flow. */
29245 res = gen_reg_rtx (mode);
29246 emit_move_insn (res, operand1);
29248 TWO52 = ix86_gen_TWO52 (mode);
29249 xa = ix86_expand_sse_fabs (res, &mask);
29250 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29252 /* load nextafter (0.5, 0.0) */
29253 fmt = REAL_MODE_FORMAT (mode);
29254 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29255 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29257 /* xa = xa + 0.5 */
29258 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29259 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29261 /* xa = (double)(int64_t)xa */
29262 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29263 expand_fix (xi, xa, 0);
29264 expand_float (xa, xi, 0);
29266 /* res = copysign (xa, operand1) */
29267 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29269 emit_label (label);
29270 LABEL_NUSES (label) = 1;
29272 emit_move_insn (operand0, res);
29275 /* Validate whether a FMA4 instruction is valid or not.
29276 OPERANDS is the array of operands.
29277 NUM is the number of operands.
29278 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29279 NUM_MEMORY is the maximum number of memory operands to accept.
29280 NUM_MEMORY less than zero is a special case to allow an operand
29281 of an instruction to be memory operation.
29282 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29285 ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29286 bool uses_oc0, int num_memory, bool commutative)
29292 /* Count the number of memory arguments */
29295 for (i = 0; i < num; i++)
29297 enum machine_mode mode = GET_MODE (operands[i]);
29298 if (register_operand (operands[i], mode))
29301 else if (memory_operand (operands[i], mode))
29303 mem_mask |= (1 << i);
29309 rtx pattern = PATTERN (insn);
29311 /* allow 0 for pcmov */
29312 if (GET_CODE (pattern) != SET
29313 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29315 || operands[i] != CONST0_RTX (mode))
29320 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29321 a memory operation. */
29322 if (num_memory < 0)
29324 num_memory = -num_memory;
29325 if ((mem_mask & (1 << (num-1))) != 0)
29327 mem_mask &= ~(1 << (num-1));
29332 /* If there were no memory operations, allow the insn */
29336 /* Do not allow the destination register to be a memory operand. */
29337 else if (mem_mask & (1 << 0))
29340 /* If there are too many memory operations, disallow the instruction. While
29341 the hardware only allows 1 memory reference, before register allocation
29342 for some insns, we allow two memory operations sometimes in order to allow
29343 code like the following to be optimized:
29345 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29347 or similar cases that are vectorized into using the vfmaddss
29349 else if (mem_count > num_memory)
29352 /* Don't allow more than one memory operation if not optimizing. */
29353 else if (mem_count > 1 && !optimize)
29356 else if (num == 4 && mem_count == 1)
29358 /* formats (destination is the first argument), example vfmaddss:
29359 xmm1, xmm1, xmm2, xmm3/mem
29360 xmm1, xmm1, xmm2/mem, xmm3
29361 xmm1, xmm2, xmm3/mem, xmm1
29362 xmm1, xmm2/mem, xmm3, xmm1 */
29364 return ((mem_mask == (1 << 1))
29365 || (mem_mask == (1 << 2))
29366 || (mem_mask == (1 << 3)));
29368 /* format, example vpmacsdd:
29369 xmm1, xmm2, xmm3/mem, xmm1 */
29371 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29373 return (mem_mask == (1 << 2));
29376 else if (num == 4 && num_memory == 2)
29378 /* If there are two memory operations, we can load one of the memory ops
29379 into the destination register. This is for optimizing the
29380 multiply/add ops, which the combiner has optimized both the multiply
29381 and the add insns to have a memory operation. We have to be careful
29382 that the destination doesn't overlap with the inputs. */
29383 rtx op0 = operands[0];
29385 if (reg_mentioned_p (op0, operands[1])
29386 || reg_mentioned_p (op0, operands[2])
29387 || reg_mentioned_p (op0, operands[3]))
29390 /* formats (destination is the first argument), example vfmaddss:
29391 xmm1, xmm1, xmm2, xmm3/mem
29392 xmm1, xmm1, xmm2/mem, xmm3
29393 xmm1, xmm2, xmm3/mem, xmm1
29394 xmm1, xmm2/mem, xmm3, xmm1
29396 For the oc0 case, we will load either operands[1] or operands[3] into
29397 operands[0], so any combination of 2 memory operands is ok. */
29401 /* format, example vpmacsdd:
29402 xmm1, xmm2, xmm3/mem, xmm1
29404 For the integer multiply/add instructions be more restrictive and
29405 require operands[2] and operands[3] to be the memory operands. */
29407 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29409 return (mem_mask == ((1 << 2) | (1 << 3)));
29412 else if (num == 3 && num_memory == 1)
29414 /* formats, example vprotb:
29415 xmm1, xmm2, xmm3/mem
29416 xmm1, xmm2/mem, xmm3 */
29418 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29420 /* format, example vpcomeq:
29421 xmm1, xmm2, xmm3/mem */
29423 return (mem_mask == (1 << 2));
29427 gcc_unreachable ();
29433 /* Fixup an FMA4 instruction that has 2 memory input references into a form the
29434 hardware will allow by using the destination register to load one of the
29435 memory operations. Presently this is used by the multiply/add routines to
29436 allow 2 memory references. */
29439 ix86_expand_fma4_multiple_memory (rtx operands[],
29441 enum machine_mode mode)
29443 rtx op0 = operands[0];
29445 || memory_operand (op0, mode)
29446 || reg_mentioned_p (op0, operands[1])
29447 || reg_mentioned_p (op0, operands[2])
29448 || reg_mentioned_p (op0, operands[3]))
29449 gcc_unreachable ();
29451 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29452 the destination register. */
29453 if (memory_operand (operands[1], mode))
29455 emit_move_insn (op0, operands[1]);
29458 else if (memory_operand (operands[3], mode))
29460 emit_move_insn (op0, operands[3]);
29464 gcc_unreachable ();
29469 /* Table of valid machine attributes. */
29470 static const struct attribute_spec ix86_attribute_table[] =
29472 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29473 /* Stdcall attribute says callee is responsible for popping arguments
29474 if they are not variable. */
29475 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29476 /* Fastcall attribute says callee is responsible for popping arguments
29477 if they are not variable. */
29478 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29479 /* Cdecl attribute says the callee is a normal C declaration */
29480 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29481 /* Regparm attribute specifies how many integer arguments are to be
29482 passed in registers. */
29483 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29484 /* Sseregparm attribute says we are using x86_64 calling conventions
29485 for FP arguments. */
29486 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29487 /* force_align_arg_pointer says this function realigns the stack at entry. */
29488 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29489 false, true, true, ix86_handle_cconv_attribute },
29490 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29491 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29492 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29493 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29495 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29496 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29497 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29498 SUBTARGET_ATTRIBUTE_TABLE,
29500 /* ms_abi and sysv_abi calling convention function attributes. */
29501 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29502 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29504 { NULL, 0, 0, false, false, false, NULL }
29507 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29509 x86_builtin_vectorization_cost (bool runtime_test)
29511 /* If the branch of the runtime test is taken - i.e. - the vectorized
29512 version is skipped - this incurs a misprediction cost (because the
29513 vectorized version is expected to be the fall-through). So we subtract
29514 the latency of a mispredicted branch from the costs that are incured
29515 when the vectorized version is executed.
29517 TODO: The values in individual target tables have to be tuned or new
29518 fields may be needed. For eg. on K8, the default branch path is the
29519 not-taken path. If the taken path is predicted correctly, the minimum
29520 penalty of going down the taken-path is 1 cycle. If the taken-path is
29521 not predicted correctly, then the minimum penalty is 10 cycles. */
29525 return (-(ix86_cost->cond_taken_branch_cost));
29531 /* This function returns the calling abi specific va_list type node.
29532 It returns the FNDECL specific va_list type. */
29535 ix86_fn_abi_va_list (tree fndecl)
29538 return va_list_type_node;
29539 gcc_assert (fndecl != NULL_TREE);
29541 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29542 return ms_va_list_type_node;
29544 return sysv_va_list_type_node;
29547 /* Returns the canonical va_list type specified by TYPE. If there
29548 is no valid TYPE provided, it return NULL_TREE. */
29551 ix86_canonical_va_list_type (tree type)
29555 /* Resolve references and pointers to va_list type. */
29556 if (INDIRECT_REF_P (type))
29557 type = TREE_TYPE (type);
29558 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29559 type = TREE_TYPE (type);
29563 wtype = va_list_type_node;
29564 gcc_assert (wtype != NULL_TREE);
29566 if (TREE_CODE (wtype) == ARRAY_TYPE)
29568 /* If va_list is an array type, the argument may have decayed
29569 to a pointer type, e.g. by being passed to another function.
29570 In that case, unwrap both types so that we can compare the
29571 underlying records. */
29572 if (TREE_CODE (htype) == ARRAY_TYPE
29573 || POINTER_TYPE_P (htype))
29575 wtype = TREE_TYPE (wtype);
29576 htype = TREE_TYPE (htype);
29579 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29580 return va_list_type_node;
29581 wtype = sysv_va_list_type_node;
29582 gcc_assert (wtype != NULL_TREE);
29584 if (TREE_CODE (wtype) == ARRAY_TYPE)
29586 /* If va_list is an array type, the argument may have decayed
29587 to a pointer type, e.g. by being passed to another function.
29588 In that case, unwrap both types so that we can compare the
29589 underlying records. */
29590 if (TREE_CODE (htype) == ARRAY_TYPE
29591 || POINTER_TYPE_P (htype))
29593 wtype = TREE_TYPE (wtype);
29594 htype = TREE_TYPE (htype);
29597 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29598 return sysv_va_list_type_node;
29599 wtype = ms_va_list_type_node;
29600 gcc_assert (wtype != NULL_TREE);
29602 if (TREE_CODE (wtype) == ARRAY_TYPE)
29604 /* If va_list is an array type, the argument may have decayed
29605 to a pointer type, e.g. by being passed to another function.
29606 In that case, unwrap both types so that we can compare the
29607 underlying records. */
29608 if (TREE_CODE (htype) == ARRAY_TYPE
29609 || POINTER_TYPE_P (htype))
29611 wtype = TREE_TYPE (wtype);
29612 htype = TREE_TYPE (htype);
29615 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29616 return ms_va_list_type_node;
29619 return std_canonical_va_list_type (type);
29622 /* Iterate through the target-specific builtin types for va_list.
29623 IDX denotes the iterator, *PTREE is set to the result type of
29624 the va_list builtin, and *PNAME to its internal type.
29625 Returns zero if there is no element for this index, otherwise
29626 IDX should be increased upon the next call.
29627 Note, do not iterate a base builtin's name like __builtin_va_list.
29628 Used from c_common_nodes_and_builtins. */
29631 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29637 *ptree = ms_va_list_type_node;
29638 *pname = "__builtin_ms_va_list";
29641 *ptree = sysv_va_list_type_node;
29642 *pname = "__builtin_sysv_va_list";
29650 /* Initialize the GCC target structure. */
29651 #undef TARGET_RETURN_IN_MEMORY
29652 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29654 #undef TARGET_LEGITIMIZE_ADDRESS
29655 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
29657 #undef TARGET_ATTRIBUTE_TABLE
29658 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29659 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29660 # undef TARGET_MERGE_DECL_ATTRIBUTES
29661 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29664 #undef TARGET_COMP_TYPE_ATTRIBUTES
29665 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29667 #undef TARGET_INIT_BUILTINS
29668 #define TARGET_INIT_BUILTINS ix86_init_builtins
29669 #undef TARGET_EXPAND_BUILTIN
29670 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29672 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29673 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29674 ix86_builtin_vectorized_function
29676 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29677 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29679 #undef TARGET_BUILTIN_RECIPROCAL
29680 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29682 #undef TARGET_ASM_FUNCTION_EPILOGUE
29683 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29685 #undef TARGET_ENCODE_SECTION_INFO
29686 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29687 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29689 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29692 #undef TARGET_ASM_OPEN_PAREN
29693 #define TARGET_ASM_OPEN_PAREN ""
29694 #undef TARGET_ASM_CLOSE_PAREN
29695 #define TARGET_ASM_CLOSE_PAREN ""
29697 #undef TARGET_ASM_BYTE_OP
29698 #define TARGET_ASM_BYTE_OP ASM_BYTE
29700 #undef TARGET_ASM_ALIGNED_HI_OP
29701 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29702 #undef TARGET_ASM_ALIGNED_SI_OP
29703 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29705 #undef TARGET_ASM_ALIGNED_DI_OP
29706 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29709 #undef TARGET_ASM_UNALIGNED_HI_OP
29710 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29711 #undef TARGET_ASM_UNALIGNED_SI_OP
29712 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29713 #undef TARGET_ASM_UNALIGNED_DI_OP
29714 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29716 #undef TARGET_SCHED_ADJUST_COST
29717 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29718 #undef TARGET_SCHED_ISSUE_RATE
29719 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29720 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29721 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29722 ia32_multipass_dfa_lookahead
29724 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29725 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29728 #undef TARGET_HAVE_TLS
29729 #define TARGET_HAVE_TLS true
29731 #undef TARGET_CANNOT_FORCE_CONST_MEM
29732 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29733 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29734 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29736 #undef TARGET_DELEGITIMIZE_ADDRESS
29737 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29739 #undef TARGET_MS_BITFIELD_LAYOUT_P
29740 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29743 #undef TARGET_BINDS_LOCAL_P
29744 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29746 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29747 #undef TARGET_BINDS_LOCAL_P
29748 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29751 #undef TARGET_ASM_OUTPUT_MI_THUNK
29752 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29753 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29754 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29756 #undef TARGET_ASM_FILE_START
29757 #define TARGET_ASM_FILE_START x86_file_start
29759 #undef TARGET_DEFAULT_TARGET_FLAGS
29760 #define TARGET_DEFAULT_TARGET_FLAGS \
29762 | TARGET_SUBTARGET_DEFAULT \
29763 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29765 #undef TARGET_HANDLE_OPTION
29766 #define TARGET_HANDLE_OPTION ix86_handle_option
29768 #undef TARGET_RTX_COSTS
29769 #define TARGET_RTX_COSTS ix86_rtx_costs
29770 #undef TARGET_ADDRESS_COST
29771 #define TARGET_ADDRESS_COST ix86_address_cost
29773 #undef TARGET_FIXED_CONDITION_CODE_REGS
29774 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29775 #undef TARGET_CC_MODES_COMPATIBLE
29776 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29778 #undef TARGET_MACHINE_DEPENDENT_REORG
29779 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29781 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29782 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29784 #undef TARGET_BUILD_BUILTIN_VA_LIST
29785 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29787 #undef TARGET_FN_ABI_VA_LIST
29788 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29790 #undef TARGET_CANONICAL_VA_LIST_TYPE
29791 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29793 #undef TARGET_EXPAND_BUILTIN_VA_START
29794 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29796 #undef TARGET_MD_ASM_CLOBBERS
29797 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29799 #undef TARGET_PROMOTE_PROTOTYPES
29800 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29801 #undef TARGET_STRUCT_VALUE_RTX
29802 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29803 #undef TARGET_SETUP_INCOMING_VARARGS
29804 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29805 #undef TARGET_MUST_PASS_IN_STACK
29806 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29807 #undef TARGET_PASS_BY_REFERENCE
29808 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29809 #undef TARGET_INTERNAL_ARG_POINTER
29810 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29811 #undef TARGET_UPDATE_STACK_BOUNDARY
29812 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29813 #undef TARGET_GET_DRAP_RTX
29814 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29815 #undef TARGET_STRICT_ARGUMENT_NAMING
29816 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29817 #undef TARGET_STATIC_CHAIN
29818 #define TARGET_STATIC_CHAIN ix86_static_chain
29819 #undef TARGET_TRAMPOLINE_INIT
29820 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
29822 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29823 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29825 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29826 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29828 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29829 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29831 #undef TARGET_C_MODE_FOR_SUFFIX
29832 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29835 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29836 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29839 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29840 #undef TARGET_INSERT_ATTRIBUTES
29841 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29844 #undef TARGET_MANGLE_TYPE
29845 #define TARGET_MANGLE_TYPE ix86_mangle_type
29847 #undef TARGET_STACK_PROTECT_FAIL
29848 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29850 #undef TARGET_FUNCTION_VALUE
29851 #define TARGET_FUNCTION_VALUE ix86_function_value
29853 #undef TARGET_SECONDARY_RELOAD
29854 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29856 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29857 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29859 #undef TARGET_SET_CURRENT_FUNCTION
29860 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29862 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29863 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29865 #undef TARGET_OPTION_SAVE
29866 #define TARGET_OPTION_SAVE ix86_function_specific_save
29868 #undef TARGET_OPTION_RESTORE
29869 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29871 #undef TARGET_OPTION_PRINT
29872 #define TARGET_OPTION_PRINT ix86_function_specific_print
29874 #undef TARGET_CAN_INLINE_P
29875 #define TARGET_CAN_INLINE_P ix86_can_inline_p
29877 #undef TARGET_EXPAND_TO_RTL_HOOK
29878 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29880 #undef TARGET_LEGITIMATE_ADDRESS_P
29881 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
29883 #undef TARGET_IRA_COVER_CLASSES
29884 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
29886 #undef TARGET_FRAME_POINTER_REQUIRED
29887 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
29889 #undef TARGET_CAN_ELIMINATE
29890 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
29892 struct gcc_target targetm = TARGET_INITIALIZER;
29894 #include "gt-i386.h"
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