1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-codes.h"
35 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "common/common-target.h"
49 #include "langhooks.h"
55 #include "tm-constrs.h"
59 #include "sched-int.h"
63 #include "diagnostic.h"
65 enum upper_128bits_state
72 typedef struct block_info_def
74 /* State of the upper 128bits of AVX registers at exit. */
75 enum upper_128bits_state state;
76 /* TRUE if state of the upper 128bits of AVX registers is unchanged
79 /* TRUE if block has been processed. */
81 /* TRUE if block has been scanned. */
83 /* Previous state of the upper 128bits of AVX registers at entry. */
84 enum upper_128bits_state prev;
87 #define BLOCK_INFO(B) ((block_info) (B)->aux)
89 enum call_avx256_state
91 /* Callee returns 256bit AVX register. */
92 callee_return_avx256 = -1,
93 /* Callee returns and passes 256bit AVX register. */
94 callee_return_pass_avx256,
95 /* Callee passes 256bit AVX register. */
97 /* Callee doesn't return nor passe 256bit AVX register, or no
98 256bit AVX register in function return. */
100 /* vzeroupper intrinsic. */
104 /* Check if a 256bit AVX register is referenced in stores. */
107 check_avx256_stores (rtx dest, const_rtx set, void *data)
110 && VALID_AVX256_REG_MODE (GET_MODE (dest)))
111 || (GET_CODE (set) == SET
112 && REG_P (SET_SRC (set))
113 && VALID_AVX256_REG_MODE (GET_MODE (SET_SRC (set)))))
115 enum upper_128bits_state *state
116 = (enum upper_128bits_state *) data;
121 /* Helper function for move_or_delete_vzeroupper_1. Look for vzeroupper
122 in basic block BB. Delete it if upper 128bit AVX registers are
123 unused. If it isn't deleted, move it to just before a jump insn.
125 STATE is state of the upper 128bits of AVX registers at entry. */
128 move_or_delete_vzeroupper_2 (basic_block bb,
129 enum upper_128bits_state state)
132 rtx vzeroupper_insn = NULL_RTX;
137 if (BLOCK_INFO (bb)->unchanged)
140 fprintf (dump_file, " [bb %i] unchanged: upper 128bits: %d\n",
143 BLOCK_INFO (bb)->state = state;
147 if (BLOCK_INFO (bb)->scanned && BLOCK_INFO (bb)->prev == state)
150 fprintf (dump_file, " [bb %i] scanned: upper 128bits: %d\n",
151 bb->index, BLOCK_INFO (bb)->state);
155 BLOCK_INFO (bb)->prev = state;
158 fprintf (dump_file, " [bb %i] entry: upper 128bits: %d\n",
163 /* BB_END changes when it is deleted. */
164 bb_end = BB_END (bb);
166 while (insn != bb_end)
168 insn = NEXT_INSN (insn);
170 if (!NONDEBUG_INSN_P (insn))
173 /* Move vzeroupper before jump/call. */
174 if (JUMP_P (insn) || CALL_P (insn))
176 if (!vzeroupper_insn)
179 if (PREV_INSN (insn) != vzeroupper_insn)
183 fprintf (dump_file, "Move vzeroupper after:\n");
184 print_rtl_single (dump_file, PREV_INSN (insn));
185 fprintf (dump_file, "before:\n");
186 print_rtl_single (dump_file, insn);
188 reorder_insns_nobb (vzeroupper_insn, vzeroupper_insn,
191 vzeroupper_insn = NULL_RTX;
195 pat = PATTERN (insn);
197 /* Check insn for vzeroupper intrinsic. */
198 if (GET_CODE (pat) == UNSPEC_VOLATILE
199 && XINT (pat, 1) == UNSPECV_VZEROUPPER)
203 /* Found vzeroupper intrinsic. */
204 fprintf (dump_file, "Found vzeroupper:\n");
205 print_rtl_single (dump_file, insn);
210 /* Check insn for vzeroall intrinsic. */
211 if (GET_CODE (pat) == PARALLEL
212 && GET_CODE (XVECEXP (pat, 0, 0)) == UNSPEC_VOLATILE
213 && XINT (XVECEXP (pat, 0, 0), 1) == UNSPECV_VZEROALL)
218 /* Delete pending vzeroupper insertion. */
221 delete_insn (vzeroupper_insn);
222 vzeroupper_insn = NULL_RTX;
225 else if (state != used)
227 note_stores (pat, check_avx256_stores, &state);
234 /* Process vzeroupper intrinsic. */
235 avx256 = INTVAL (XVECEXP (pat, 0, 0));
239 /* Since the upper 128bits are cleared, callee must not pass
240 256bit AVX register. We only need to check if callee
241 returns 256bit AVX register. */
242 if (avx256 == callee_return_avx256)
248 /* Remove unnecessary vzeroupper since upper 128bits are
252 fprintf (dump_file, "Delete redundant vzeroupper:\n");
253 print_rtl_single (dump_file, insn);
259 /* Set state to UNUSED if callee doesn't return 256bit AVX
261 if (avx256 != callee_return_pass_avx256)
264 if (avx256 == callee_return_pass_avx256
265 || avx256 == callee_pass_avx256)
267 /* Must remove vzeroupper since callee passes in 256bit
271 fprintf (dump_file, "Delete callee pass vzeroupper:\n");
272 print_rtl_single (dump_file, insn);
278 vzeroupper_insn = insn;
284 BLOCK_INFO (bb)->state = state;
285 BLOCK_INFO (bb)->unchanged = unchanged;
286 BLOCK_INFO (bb)->scanned = true;
289 fprintf (dump_file, " [bb %i] exit: %s: upper 128bits: %d\n",
290 bb->index, unchanged ? "unchanged" : "changed",
294 /* Helper function for move_or_delete_vzeroupper. Process vzeroupper
295 in BLOCK and check its predecessor blocks. Treat UNKNOWN state
296 as USED if UNKNOWN_IS_UNUSED is true. Return TRUE if the exit
300 move_or_delete_vzeroupper_1 (basic_block block, bool unknown_is_unused)
304 enum upper_128bits_state state, old_state, new_state;
308 fprintf (dump_file, " Process [bb %i]: status: %d\n",
309 block->index, BLOCK_INFO (block)->processed);
311 if (BLOCK_INFO (block)->processed)
316 /* Check all predecessor edges of this block. */
317 seen_unknown = false;
318 FOR_EACH_EDGE (e, ei, block->preds)
322 switch (BLOCK_INFO (e->src)->state)
325 if (!unknown_is_unused)
339 old_state = BLOCK_INFO (block)->state;
340 move_or_delete_vzeroupper_2 (block, state);
341 new_state = BLOCK_INFO (block)->state;
343 if (state != unknown || new_state == used)
344 BLOCK_INFO (block)->processed = true;
346 /* Need to rescan if the upper 128bits of AVX registers are changed
348 if (new_state != old_state)
350 if (new_state == used)
351 cfun->machine->rescan_vzeroupper_p = 1;
358 /* Go through the instruction stream looking for vzeroupper. Delete
359 it if upper 128bit AVX registers are unused. If it isn't deleted,
360 move it to just before a jump insn. */
363 move_or_delete_vzeroupper (void)
368 fibheap_t worklist, pending, fibheap_swap;
369 sbitmap visited, in_worklist, in_pending, sbitmap_swap;
374 /* Set up block info for each basic block. */
375 alloc_aux_for_blocks (sizeof (struct block_info_def));
377 /* Process outgoing edges of entry point. */
379 fprintf (dump_file, "Process outgoing edges of entry point\n");
381 FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR->succs)
383 move_or_delete_vzeroupper_2 (e->dest,
384 cfun->machine->caller_pass_avx256_p
386 BLOCK_INFO (e->dest)->processed = true;
389 /* Compute reverse completion order of depth first search of the CFG
390 so that the data-flow runs faster. */
391 rc_order = XNEWVEC (int, n_basic_blocks - NUM_FIXED_BLOCKS);
392 bb_order = XNEWVEC (int, last_basic_block);
393 pre_and_rev_post_order_compute (NULL, rc_order, false);
394 for (i = 0; i < n_basic_blocks - NUM_FIXED_BLOCKS; i++)
395 bb_order[rc_order[i]] = i;
398 worklist = fibheap_new ();
399 pending = fibheap_new ();
400 visited = sbitmap_alloc (last_basic_block);
401 in_worklist = sbitmap_alloc (last_basic_block);
402 in_pending = sbitmap_alloc (last_basic_block);
403 sbitmap_zero (in_worklist);
405 /* Don't check outgoing edges of entry point. */
406 sbitmap_ones (in_pending);
408 if (BLOCK_INFO (bb)->processed)
409 RESET_BIT (in_pending, bb->index);
412 move_or_delete_vzeroupper_1 (bb, false);
413 fibheap_insert (pending, bb_order[bb->index], bb);
417 fprintf (dump_file, "Check remaining basic blocks\n");
419 while (!fibheap_empty (pending))
421 fibheap_swap = pending;
423 worklist = fibheap_swap;
424 sbitmap_swap = in_pending;
425 in_pending = in_worklist;
426 in_worklist = sbitmap_swap;
428 sbitmap_zero (visited);
430 cfun->machine->rescan_vzeroupper_p = 0;
432 while (!fibheap_empty (worklist))
434 bb = (basic_block) fibheap_extract_min (worklist);
435 RESET_BIT (in_worklist, bb->index);
436 gcc_assert (!TEST_BIT (visited, bb->index));
437 if (!TEST_BIT (visited, bb->index))
441 SET_BIT (visited, bb->index);
443 if (move_or_delete_vzeroupper_1 (bb, false))
444 FOR_EACH_EDGE (e, ei, bb->succs)
446 if (e->dest == EXIT_BLOCK_PTR
447 || BLOCK_INFO (e->dest)->processed)
450 if (TEST_BIT (visited, e->dest->index))
452 if (!TEST_BIT (in_pending, e->dest->index))
454 /* Send E->DEST to next round. */
455 SET_BIT (in_pending, e->dest->index);
456 fibheap_insert (pending,
457 bb_order[e->dest->index],
461 else if (!TEST_BIT (in_worklist, e->dest->index))
463 /* Add E->DEST to current round. */
464 SET_BIT (in_worklist, e->dest->index);
465 fibheap_insert (worklist, bb_order[e->dest->index],
472 if (!cfun->machine->rescan_vzeroupper_p)
477 fibheap_delete (worklist);
478 fibheap_delete (pending);
479 sbitmap_free (visited);
480 sbitmap_free (in_worklist);
481 sbitmap_free (in_pending);
484 fprintf (dump_file, "Process remaining basic blocks\n");
487 move_or_delete_vzeroupper_1 (bb, true);
489 free_aux_for_blocks ();
492 static rtx legitimize_dllimport_symbol (rtx, bool);
494 #ifndef CHECK_STACK_LIMIT
495 #define CHECK_STACK_LIMIT (-1)
498 /* Return index of given mode in mult and division cost tables. */
499 #define MODE_INDEX(mode) \
500 ((mode) == QImode ? 0 \
501 : (mode) == HImode ? 1 \
502 : (mode) == SImode ? 2 \
503 : (mode) == DImode ? 3 \
506 /* Processor costs (relative to an add) */
507 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
508 #define COSTS_N_BYTES(N) ((N) * 2)
510 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
513 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
514 COSTS_N_BYTES (2), /* cost of an add instruction */
515 COSTS_N_BYTES (3), /* cost of a lea instruction */
516 COSTS_N_BYTES (2), /* variable shift costs */
517 COSTS_N_BYTES (3), /* constant shift costs */
518 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
519 COSTS_N_BYTES (3), /* HI */
520 COSTS_N_BYTES (3), /* SI */
521 COSTS_N_BYTES (3), /* DI */
522 COSTS_N_BYTES (5)}, /* other */
523 0, /* cost of multiply per each bit set */
524 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
525 COSTS_N_BYTES (3), /* HI */
526 COSTS_N_BYTES (3), /* SI */
527 COSTS_N_BYTES (3), /* DI */
528 COSTS_N_BYTES (5)}, /* other */
529 COSTS_N_BYTES (3), /* cost of movsx */
530 COSTS_N_BYTES (3), /* cost of movzx */
531 0, /* "large" insn */
533 2, /* cost for loading QImode using movzbl */
534 {2, 2, 2}, /* cost of loading integer registers
535 in QImode, HImode and SImode.
536 Relative to reg-reg move (2). */
537 {2, 2, 2}, /* cost of storing integer registers */
538 2, /* cost of reg,reg fld/fst */
539 {2, 2, 2}, /* cost of loading fp registers
540 in SFmode, DFmode and XFmode */
541 {2, 2, 2}, /* cost of storing fp registers
542 in SFmode, DFmode and XFmode */
543 3, /* cost of moving MMX register */
544 {3, 3}, /* cost of loading MMX registers
545 in SImode and DImode */
546 {3, 3}, /* cost of storing MMX registers
547 in SImode and DImode */
548 3, /* cost of moving SSE register */
549 {3, 3, 3}, /* cost of loading SSE registers
550 in SImode, DImode and TImode */
551 {3, 3, 3}, /* cost of storing SSE registers
552 in SImode, DImode and TImode */
553 3, /* MMX or SSE register to integer */
554 0, /* size of l1 cache */
555 0, /* size of l2 cache */
556 0, /* size of prefetch block */
557 0, /* number of parallel prefetches */
559 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
561 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
562 COSTS_N_BYTES (2), /* cost of FABS instruction. */
563 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
564 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
565 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
566 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
567 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
568 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 1, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 1, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
582 /* Processor costs (relative to an add) */
584 struct processor_costs i386_cost = { /* 386 specific costs */
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (1), /* cost of a lea instruction */
587 COSTS_N_INSNS (3), /* variable shift costs */
588 COSTS_N_INSNS (2), /* constant shift costs */
589 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (6), /* HI */
591 COSTS_N_INSNS (6), /* SI */
592 COSTS_N_INSNS (6), /* DI */
593 COSTS_N_INSNS (6)}, /* other */
594 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (23), /* HI */
597 COSTS_N_INSNS (23), /* SI */
598 COSTS_N_INSNS (23), /* DI */
599 COSTS_N_INSNS (23)}, /* other */
600 COSTS_N_INSNS (3), /* cost of movsx */
601 COSTS_N_INSNS (2), /* cost of movzx */
602 15, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {2, 4, 2}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {2, 4, 2}, /* cost of storing integer registers */
609 2, /* cost of reg,reg fld/fst */
610 {8, 8, 8}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {8, 8, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 8}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 8}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 8, 16}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 8, 16}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 3, /* MMX or SSE register to integer */
625 0, /* size of l1 cache */
626 0, /* size of l2 cache */
627 0, /* size of prefetch block */
628 0, /* number of parallel prefetches */
630 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (22), /* cost of FABS instruction. */
634 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
636 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
637 DUMMY_STRINGOP_ALGS},
638 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
639 DUMMY_STRINGOP_ALGS},
640 1, /* scalar_stmt_cost. */
641 1, /* scalar load_cost. */
642 1, /* scalar_store_cost. */
643 1, /* vec_stmt_cost. */
644 1, /* vec_to_scalar_cost. */
645 1, /* scalar_to_vec_cost. */
646 1, /* vec_align_load_cost. */
647 2, /* vec_unalign_load_cost. */
648 1, /* vec_store_cost. */
649 3, /* cond_taken_branch_cost. */
650 1, /* cond_not_taken_branch_cost. */
654 struct processor_costs i486_cost = { /* 486 specific costs */
655 COSTS_N_INSNS (1), /* cost of an add instruction */
656 COSTS_N_INSNS (1), /* cost of a lea instruction */
657 COSTS_N_INSNS (3), /* variable shift costs */
658 COSTS_N_INSNS (2), /* constant shift costs */
659 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
660 COSTS_N_INSNS (12), /* HI */
661 COSTS_N_INSNS (12), /* SI */
662 COSTS_N_INSNS (12), /* DI */
663 COSTS_N_INSNS (12)}, /* other */
664 1, /* cost of multiply per each bit set */
665 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
666 COSTS_N_INSNS (40), /* HI */
667 COSTS_N_INSNS (40), /* SI */
668 COSTS_N_INSNS (40), /* DI */
669 COSTS_N_INSNS (40)}, /* other */
670 COSTS_N_INSNS (3), /* cost of movsx */
671 COSTS_N_INSNS (2), /* cost of movzx */
672 15, /* "large" insn */
674 4, /* cost for loading QImode using movzbl */
675 {2, 4, 2}, /* cost of loading integer registers
676 in QImode, HImode and SImode.
677 Relative to reg-reg move (2). */
678 {2, 4, 2}, /* cost of storing integer registers */
679 2, /* cost of reg,reg fld/fst */
680 {8, 8, 8}, /* cost of loading fp registers
681 in SFmode, DFmode and XFmode */
682 {8, 8, 8}, /* cost of storing fp registers
683 in SFmode, DFmode and XFmode */
684 2, /* cost of moving MMX register */
685 {4, 8}, /* cost of loading MMX registers
686 in SImode and DImode */
687 {4, 8}, /* cost of storing MMX registers
688 in SImode and DImode */
689 2, /* cost of moving SSE register */
690 {4, 8, 16}, /* cost of loading SSE registers
691 in SImode, DImode and TImode */
692 {4, 8, 16}, /* cost of storing SSE registers
693 in SImode, DImode and TImode */
694 3, /* MMX or SSE register to integer */
695 4, /* size of l1 cache. 486 has 8kB cache
696 shared for code and data, so 4kB is
697 not really precise. */
698 4, /* size of l2 cache */
699 0, /* size of prefetch block */
700 0, /* number of parallel prefetches */
702 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
703 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
704 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
705 COSTS_N_INSNS (3), /* cost of FABS instruction. */
706 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
707 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
708 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
709 DUMMY_STRINGOP_ALGS},
710 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
711 DUMMY_STRINGOP_ALGS},
712 1, /* scalar_stmt_cost. */
713 1, /* scalar load_cost. */
714 1, /* scalar_store_cost. */
715 1, /* vec_stmt_cost. */
716 1, /* vec_to_scalar_cost. */
717 1, /* scalar_to_vec_cost. */
718 1, /* vec_align_load_cost. */
719 2, /* vec_unalign_load_cost. */
720 1, /* vec_store_cost. */
721 3, /* cond_taken_branch_cost. */
722 1, /* cond_not_taken_branch_cost. */
726 struct processor_costs pentium_cost = {
727 COSTS_N_INSNS (1), /* cost of an add instruction */
728 COSTS_N_INSNS (1), /* cost of a lea instruction */
729 COSTS_N_INSNS (4), /* variable shift costs */
730 COSTS_N_INSNS (1), /* constant shift costs */
731 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
732 COSTS_N_INSNS (11), /* HI */
733 COSTS_N_INSNS (11), /* SI */
734 COSTS_N_INSNS (11), /* DI */
735 COSTS_N_INSNS (11)}, /* other */
736 0, /* cost of multiply per each bit set */
737 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
738 COSTS_N_INSNS (25), /* HI */
739 COSTS_N_INSNS (25), /* SI */
740 COSTS_N_INSNS (25), /* DI */
741 COSTS_N_INSNS (25)}, /* other */
742 COSTS_N_INSNS (3), /* cost of movsx */
743 COSTS_N_INSNS (2), /* cost of movzx */
744 8, /* "large" insn */
746 6, /* cost for loading QImode using movzbl */
747 {2, 4, 2}, /* cost of loading integer registers
748 in QImode, HImode and SImode.
749 Relative to reg-reg move (2). */
750 {2, 4, 2}, /* cost of storing integer registers */
751 2, /* cost of reg,reg fld/fst */
752 {2, 2, 6}, /* cost of loading fp registers
753 in SFmode, DFmode and XFmode */
754 {4, 4, 6}, /* cost of storing fp registers
755 in SFmode, DFmode and XFmode */
756 8, /* cost of moving MMX register */
757 {8, 8}, /* cost of loading MMX registers
758 in SImode and DImode */
759 {8, 8}, /* cost of storing MMX registers
760 in SImode and DImode */
761 2, /* cost of moving SSE register */
762 {4, 8, 16}, /* cost of loading SSE registers
763 in SImode, DImode and TImode */
764 {4, 8, 16}, /* cost of storing SSE registers
765 in SImode, DImode and TImode */
766 3, /* MMX or SSE register to integer */
767 8, /* size of l1 cache. */
768 8, /* size of l2 cache */
769 0, /* size of prefetch block */
770 0, /* number of parallel prefetches */
772 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
773 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
774 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
775 COSTS_N_INSNS (1), /* cost of FABS instruction. */
776 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
777 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
778 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
779 DUMMY_STRINGOP_ALGS},
780 {{libcall, {{-1, rep_prefix_4_byte}}},
781 DUMMY_STRINGOP_ALGS},
782 1, /* scalar_stmt_cost. */
783 1, /* scalar load_cost. */
784 1, /* scalar_store_cost. */
785 1, /* vec_stmt_cost. */
786 1, /* vec_to_scalar_cost. */
787 1, /* scalar_to_vec_cost. */
788 1, /* vec_align_load_cost. */
789 2, /* vec_unalign_load_cost. */
790 1, /* vec_store_cost. */
791 3, /* cond_taken_branch_cost. */
792 1, /* cond_not_taken_branch_cost. */
796 struct processor_costs pentiumpro_cost = {
797 COSTS_N_INSNS (1), /* cost of an add instruction */
798 COSTS_N_INSNS (1), /* cost of a lea instruction */
799 COSTS_N_INSNS (1), /* variable shift costs */
800 COSTS_N_INSNS (1), /* constant shift costs */
801 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
802 COSTS_N_INSNS (4), /* HI */
803 COSTS_N_INSNS (4), /* SI */
804 COSTS_N_INSNS (4), /* DI */
805 COSTS_N_INSNS (4)}, /* other */
806 0, /* cost of multiply per each bit set */
807 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
808 COSTS_N_INSNS (17), /* HI */
809 COSTS_N_INSNS (17), /* SI */
810 COSTS_N_INSNS (17), /* DI */
811 COSTS_N_INSNS (17)}, /* other */
812 COSTS_N_INSNS (1), /* cost of movsx */
813 COSTS_N_INSNS (1), /* cost of movzx */
814 8, /* "large" insn */
816 2, /* cost for loading QImode using movzbl */
817 {4, 4, 4}, /* cost of loading integer registers
818 in QImode, HImode and SImode.
819 Relative to reg-reg move (2). */
820 {2, 2, 2}, /* cost of storing integer registers */
821 2, /* cost of reg,reg fld/fst */
822 {2, 2, 6}, /* cost of loading fp registers
823 in SFmode, DFmode and XFmode */
824 {4, 4, 6}, /* cost of storing fp registers
825 in SFmode, DFmode and XFmode */
826 2, /* cost of moving MMX register */
827 {2, 2}, /* cost of loading MMX registers
828 in SImode and DImode */
829 {2, 2}, /* cost of storing MMX registers
830 in SImode and DImode */
831 2, /* cost of moving SSE register */
832 {2, 2, 8}, /* cost of loading SSE registers
833 in SImode, DImode and TImode */
834 {2, 2, 8}, /* cost of storing SSE registers
835 in SImode, DImode and TImode */
836 3, /* MMX or SSE register to integer */
837 8, /* size of l1 cache. */
838 256, /* size of l2 cache */
839 32, /* size of prefetch block */
840 6, /* number of parallel prefetches */
842 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
843 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
844 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
845 COSTS_N_INSNS (2), /* cost of FABS instruction. */
846 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
847 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
848 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
849 (we ensure the alignment). For small blocks inline loop is still a
850 noticeable win, for bigger blocks either rep movsl or rep movsb is
851 way to go. Rep movsb has apparently more expensive startup time in CPU,
852 but after 4K the difference is down in the noise. */
853 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
854 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
855 DUMMY_STRINGOP_ALGS},
856 {{rep_prefix_4_byte, {{1024, unrolled_loop},
857 {8192, rep_prefix_4_byte}, {-1, libcall}}},
858 DUMMY_STRINGOP_ALGS},
859 1, /* scalar_stmt_cost. */
860 1, /* scalar load_cost. */
861 1, /* scalar_store_cost. */
862 1, /* vec_stmt_cost. */
863 1, /* vec_to_scalar_cost. */
864 1, /* scalar_to_vec_cost. */
865 1, /* vec_align_load_cost. */
866 2, /* vec_unalign_load_cost. */
867 1, /* vec_store_cost. */
868 3, /* cond_taken_branch_cost. */
869 1, /* cond_not_taken_branch_cost. */
873 struct processor_costs geode_cost = {
874 COSTS_N_INSNS (1), /* cost of an add instruction */
875 COSTS_N_INSNS (1), /* cost of a lea instruction */
876 COSTS_N_INSNS (2), /* variable shift costs */
877 COSTS_N_INSNS (1), /* constant shift costs */
878 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
879 COSTS_N_INSNS (4), /* HI */
880 COSTS_N_INSNS (7), /* SI */
881 COSTS_N_INSNS (7), /* DI */
882 COSTS_N_INSNS (7)}, /* other */
883 0, /* cost of multiply per each bit set */
884 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
885 COSTS_N_INSNS (23), /* HI */
886 COSTS_N_INSNS (39), /* SI */
887 COSTS_N_INSNS (39), /* DI */
888 COSTS_N_INSNS (39)}, /* other */
889 COSTS_N_INSNS (1), /* cost of movsx */
890 COSTS_N_INSNS (1), /* cost of movzx */
891 8, /* "large" insn */
893 1, /* cost for loading QImode using movzbl */
894 {1, 1, 1}, /* cost of loading integer registers
895 in QImode, HImode and SImode.
896 Relative to reg-reg move (2). */
897 {1, 1, 1}, /* cost of storing integer registers */
898 1, /* cost of reg,reg fld/fst */
899 {1, 1, 1}, /* cost of loading fp registers
900 in SFmode, DFmode and XFmode */
901 {4, 6, 6}, /* cost of storing fp registers
902 in SFmode, DFmode and XFmode */
904 1, /* cost of moving MMX register */
905 {1, 1}, /* cost of loading MMX registers
906 in SImode and DImode */
907 {1, 1}, /* cost of storing MMX registers
908 in SImode and DImode */
909 1, /* cost of moving SSE register */
910 {1, 1, 1}, /* cost of loading SSE registers
911 in SImode, DImode and TImode */
912 {1, 1, 1}, /* cost of storing SSE registers
913 in SImode, DImode and TImode */
914 1, /* MMX or SSE register to integer */
915 64, /* size of l1 cache. */
916 128, /* size of l2 cache. */
917 32, /* size of prefetch block */
918 1, /* number of parallel prefetches */
920 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
921 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
922 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
923 COSTS_N_INSNS (1), /* cost of FABS instruction. */
924 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
925 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
926 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
927 DUMMY_STRINGOP_ALGS},
928 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
929 DUMMY_STRINGOP_ALGS},
930 1, /* scalar_stmt_cost. */
931 1, /* scalar load_cost. */
932 1, /* scalar_store_cost. */
933 1, /* vec_stmt_cost. */
934 1, /* vec_to_scalar_cost. */
935 1, /* scalar_to_vec_cost. */
936 1, /* vec_align_load_cost. */
937 2, /* vec_unalign_load_cost. */
938 1, /* vec_store_cost. */
939 3, /* cond_taken_branch_cost. */
940 1, /* cond_not_taken_branch_cost. */
944 struct processor_costs k6_cost = {
945 COSTS_N_INSNS (1), /* cost of an add instruction */
946 COSTS_N_INSNS (2), /* cost of a lea instruction */
947 COSTS_N_INSNS (1), /* variable shift costs */
948 COSTS_N_INSNS (1), /* constant shift costs */
949 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
950 COSTS_N_INSNS (3), /* HI */
951 COSTS_N_INSNS (3), /* SI */
952 COSTS_N_INSNS (3), /* DI */
953 COSTS_N_INSNS (3)}, /* other */
954 0, /* cost of multiply per each bit set */
955 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
956 COSTS_N_INSNS (18), /* HI */
957 COSTS_N_INSNS (18), /* SI */
958 COSTS_N_INSNS (18), /* DI */
959 COSTS_N_INSNS (18)}, /* other */
960 COSTS_N_INSNS (2), /* cost of movsx */
961 COSTS_N_INSNS (2), /* cost of movzx */
962 8, /* "large" insn */
964 3, /* cost for loading QImode using movzbl */
965 {4, 5, 4}, /* cost of loading integer registers
966 in QImode, HImode and SImode.
967 Relative to reg-reg move (2). */
968 {2, 3, 2}, /* cost of storing integer registers */
969 4, /* cost of reg,reg fld/fst */
970 {6, 6, 6}, /* cost of loading fp registers
971 in SFmode, DFmode and XFmode */
972 {4, 4, 4}, /* cost of storing fp registers
973 in SFmode, DFmode and XFmode */
974 2, /* cost of moving MMX register */
975 {2, 2}, /* cost of loading MMX registers
976 in SImode and DImode */
977 {2, 2}, /* cost of storing MMX registers
978 in SImode and DImode */
979 2, /* cost of moving SSE register */
980 {2, 2, 8}, /* cost of loading SSE registers
981 in SImode, DImode and TImode */
982 {2, 2, 8}, /* cost of storing SSE registers
983 in SImode, DImode and TImode */
984 6, /* MMX or SSE register to integer */
985 32, /* size of l1 cache. */
986 32, /* size of l2 cache. Some models
987 have integrated l2 cache, but
988 optimizing for k6 is not important
989 enough to worry about that. */
990 32, /* size of prefetch block */
991 1, /* number of parallel prefetches */
993 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
994 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
995 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
996 COSTS_N_INSNS (2), /* cost of FABS instruction. */
997 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
998 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
999 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
1000 DUMMY_STRINGOP_ALGS},
1001 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
1002 DUMMY_STRINGOP_ALGS},
1003 1, /* scalar_stmt_cost. */
1004 1, /* scalar load_cost. */
1005 1, /* scalar_store_cost. */
1006 1, /* vec_stmt_cost. */
1007 1, /* vec_to_scalar_cost. */
1008 1, /* scalar_to_vec_cost. */
1009 1, /* vec_align_load_cost. */
1010 2, /* vec_unalign_load_cost. */
1011 1, /* vec_store_cost. */
1012 3, /* cond_taken_branch_cost. */
1013 1, /* cond_not_taken_branch_cost. */
1017 struct processor_costs athlon_cost = {
1018 COSTS_N_INSNS (1), /* cost of an add instruction */
1019 COSTS_N_INSNS (2), /* cost of a lea instruction */
1020 COSTS_N_INSNS (1), /* variable shift costs */
1021 COSTS_N_INSNS (1), /* constant shift costs */
1022 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
1023 COSTS_N_INSNS (5), /* HI */
1024 COSTS_N_INSNS (5), /* SI */
1025 COSTS_N_INSNS (5), /* DI */
1026 COSTS_N_INSNS (5)}, /* other */
1027 0, /* cost of multiply per each bit set */
1028 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1029 COSTS_N_INSNS (26), /* HI */
1030 COSTS_N_INSNS (42), /* SI */
1031 COSTS_N_INSNS (74), /* DI */
1032 COSTS_N_INSNS (74)}, /* other */
1033 COSTS_N_INSNS (1), /* cost of movsx */
1034 COSTS_N_INSNS (1), /* cost of movzx */
1035 8, /* "large" insn */
1037 4, /* cost for loading QImode using movzbl */
1038 {3, 4, 3}, /* cost of loading integer registers
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1041 {3, 4, 3}, /* cost of storing integer registers */
1042 4, /* cost of reg,reg fld/fst */
1043 {4, 4, 12}, /* cost of loading fp registers
1044 in SFmode, DFmode and XFmode */
1045 {6, 6, 8}, /* cost of storing fp registers
1046 in SFmode, DFmode and XFmode */
1047 2, /* cost of moving MMX register */
1048 {4, 4}, /* cost of loading MMX registers
1049 in SImode and DImode */
1050 {4, 4}, /* cost of storing MMX registers
1051 in SImode and DImode */
1052 2, /* cost of moving SSE register */
1053 {4, 4, 6}, /* cost of loading SSE registers
1054 in SImode, DImode and TImode */
1055 {4, 4, 5}, /* cost of storing SSE registers
1056 in SImode, DImode and TImode */
1057 5, /* MMX or SSE register to integer */
1058 64, /* size of l1 cache. */
1059 256, /* size of l2 cache. */
1060 64, /* size of prefetch block */
1061 6, /* number of parallel prefetches */
1062 5, /* Branch cost */
1063 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
1064 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
1065 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
1066 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1067 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1068 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
1069 /* For some reason, Athlon deals better with REP prefix (relative to loops)
1070 compared to K8. Alignment becomes important after 8 bytes for memcpy and
1071 128 bytes for memset. */
1072 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
1073 DUMMY_STRINGOP_ALGS},
1074 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
1075 DUMMY_STRINGOP_ALGS},
1076 1, /* scalar_stmt_cost. */
1077 1, /* scalar load_cost. */
1078 1, /* scalar_store_cost. */
1079 1, /* vec_stmt_cost. */
1080 1, /* vec_to_scalar_cost. */
1081 1, /* scalar_to_vec_cost. */
1082 1, /* vec_align_load_cost. */
1083 2, /* vec_unalign_load_cost. */
1084 1, /* vec_store_cost. */
1085 3, /* cond_taken_branch_cost. */
1086 1, /* cond_not_taken_branch_cost. */
1090 struct processor_costs k8_cost = {
1091 COSTS_N_INSNS (1), /* cost of an add instruction */
1092 COSTS_N_INSNS (2), /* cost of a lea instruction */
1093 COSTS_N_INSNS (1), /* variable shift costs */
1094 COSTS_N_INSNS (1), /* constant shift costs */
1095 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1096 COSTS_N_INSNS (4), /* HI */
1097 COSTS_N_INSNS (3), /* SI */
1098 COSTS_N_INSNS (4), /* DI */
1099 COSTS_N_INSNS (5)}, /* other */
1100 0, /* cost of multiply per each bit set */
1101 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1102 COSTS_N_INSNS (26), /* HI */
1103 COSTS_N_INSNS (42), /* SI */
1104 COSTS_N_INSNS (74), /* DI */
1105 COSTS_N_INSNS (74)}, /* other */
1106 COSTS_N_INSNS (1), /* cost of movsx */
1107 COSTS_N_INSNS (1), /* cost of movzx */
1108 8, /* "large" insn */
1110 4, /* cost for loading QImode using movzbl */
1111 {3, 4, 3}, /* cost of loading integer registers
1112 in QImode, HImode and SImode.
1113 Relative to reg-reg move (2). */
1114 {3, 4, 3}, /* cost of storing integer registers */
1115 4, /* cost of reg,reg fld/fst */
1116 {4, 4, 12}, /* cost of loading fp registers
1117 in SFmode, DFmode and XFmode */
1118 {6, 6, 8}, /* cost of storing fp registers
1119 in SFmode, DFmode and XFmode */
1120 2, /* cost of moving MMX register */
1121 {3, 3}, /* cost of loading MMX registers
1122 in SImode and DImode */
1123 {4, 4}, /* cost of storing MMX registers
1124 in SImode and DImode */
1125 2, /* cost of moving SSE register */
1126 {4, 3, 6}, /* cost of loading SSE registers
1127 in SImode, DImode and TImode */
1128 {4, 4, 5}, /* cost of storing SSE registers
1129 in SImode, DImode and TImode */
1130 5, /* MMX or SSE register to integer */
1131 64, /* size of l1 cache. */
1132 512, /* size of l2 cache. */
1133 64, /* size of prefetch block */
1134 /* New AMD processors never drop prefetches; if they cannot be performed
1135 immediately, they are queued. We set number of simultaneous prefetches
1136 to a large constant to reflect this (it probably is not a good idea not
1137 to limit number of prefetches at all, as their execution also takes some
1139 100, /* number of parallel prefetches */
1140 3, /* Branch cost */
1141 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
1142 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
1143 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
1144 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1145 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1146 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
1147 /* K8 has optimized REP instruction for medium sized blocks, but for very
1148 small blocks it is better to use loop. For large blocks, libcall can
1149 do nontemporary accesses and beat inline considerably. */
1150 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
1151 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1152 {{libcall, {{8, loop}, {24, unrolled_loop},
1153 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1154 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1155 4, /* scalar_stmt_cost. */
1156 2, /* scalar load_cost. */
1157 2, /* scalar_store_cost. */
1158 5, /* vec_stmt_cost. */
1159 0, /* vec_to_scalar_cost. */
1160 2, /* scalar_to_vec_cost. */
1161 2, /* vec_align_load_cost. */
1162 3, /* vec_unalign_load_cost. */
1163 3, /* vec_store_cost. */
1164 3, /* cond_taken_branch_cost. */
1165 2, /* cond_not_taken_branch_cost. */
1168 struct processor_costs amdfam10_cost = {
1169 COSTS_N_INSNS (1), /* cost of an add instruction */
1170 COSTS_N_INSNS (2), /* cost of a lea instruction */
1171 COSTS_N_INSNS (1), /* variable shift costs */
1172 COSTS_N_INSNS (1), /* constant shift costs */
1173 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1174 COSTS_N_INSNS (4), /* HI */
1175 COSTS_N_INSNS (3), /* SI */
1176 COSTS_N_INSNS (4), /* DI */
1177 COSTS_N_INSNS (5)}, /* other */
1178 0, /* cost of multiply per each bit set */
1179 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
1180 COSTS_N_INSNS (35), /* HI */
1181 COSTS_N_INSNS (51), /* SI */
1182 COSTS_N_INSNS (83), /* DI */
1183 COSTS_N_INSNS (83)}, /* other */
1184 COSTS_N_INSNS (1), /* cost of movsx */
1185 COSTS_N_INSNS (1), /* cost of movzx */
1186 8, /* "large" insn */
1188 4, /* cost for loading QImode using movzbl */
1189 {3, 4, 3}, /* cost of loading integer registers
1190 in QImode, HImode and SImode.
1191 Relative to reg-reg move (2). */
1192 {3, 4, 3}, /* cost of storing integer registers */
1193 4, /* cost of reg,reg fld/fst */
1194 {4, 4, 12}, /* cost of loading fp registers
1195 in SFmode, DFmode and XFmode */
1196 {6, 6, 8}, /* cost of storing fp registers
1197 in SFmode, DFmode and XFmode */
1198 2, /* cost of moving MMX register */
1199 {3, 3}, /* cost of loading MMX registers
1200 in SImode and DImode */
1201 {4, 4}, /* cost of storing MMX registers
1202 in SImode and DImode */
1203 2, /* cost of moving SSE register */
1204 {4, 4, 3}, /* cost of loading SSE registers
1205 in SImode, DImode and TImode */
1206 {4, 4, 5}, /* cost of storing SSE registers
1207 in SImode, DImode and TImode */
1208 3, /* MMX or SSE register to integer */
1210 MOVD reg64, xmmreg Double FSTORE 4
1211 MOVD reg32, xmmreg Double FSTORE 4
1213 MOVD reg64, xmmreg Double FADD 3
1215 MOVD reg32, xmmreg Double FADD 3
1217 64, /* size of l1 cache. */
1218 512, /* size of l2 cache. */
1219 64, /* size of prefetch block */
1220 /* New AMD processors never drop prefetches; if they cannot be performed
1221 immediately, they are queued. We set number of simultaneous prefetches
1222 to a large constant to reflect this (it probably is not a good idea not
1223 to limit number of prefetches at all, as their execution also takes some
1225 100, /* number of parallel prefetches */
1226 2, /* Branch cost */
1227 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
1228 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
1229 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
1230 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1231 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1232 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
1234 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
1235 very small blocks it is better to use loop. For large blocks, libcall can
1236 do nontemporary accesses and beat inline considerably. */
1237 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
1238 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1239 {{libcall, {{8, loop}, {24, unrolled_loop},
1240 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1241 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1242 4, /* scalar_stmt_cost. */
1243 2, /* scalar load_cost. */
1244 2, /* scalar_store_cost. */
1245 6, /* vec_stmt_cost. */
1246 0, /* vec_to_scalar_cost. */
1247 2, /* scalar_to_vec_cost. */
1248 2, /* vec_align_load_cost. */
1249 2, /* vec_unalign_load_cost. */
1250 2, /* vec_store_cost. */
1251 2, /* cond_taken_branch_cost. */
1252 1, /* cond_not_taken_branch_cost. */
1255 struct processor_costs bdver1_cost = {
1256 COSTS_N_INSNS (1), /* cost of an add instruction */
1257 COSTS_N_INSNS (1), /* cost of a lea instruction */
1258 COSTS_N_INSNS (1), /* variable shift costs */
1259 COSTS_N_INSNS (1), /* constant shift costs */
1260 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
1261 COSTS_N_INSNS (4), /* HI */
1262 COSTS_N_INSNS (4), /* SI */
1263 COSTS_N_INSNS (6), /* DI */
1264 COSTS_N_INSNS (6)}, /* other */
1265 0, /* cost of multiply per each bit set */
1266 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
1267 COSTS_N_INSNS (35), /* HI */
1268 COSTS_N_INSNS (51), /* SI */
1269 COSTS_N_INSNS (83), /* DI */
1270 COSTS_N_INSNS (83)}, /* other */
1271 COSTS_N_INSNS (1), /* cost of movsx */
1272 COSTS_N_INSNS (1), /* cost of movzx */
1273 8, /* "large" insn */
1275 4, /* cost for loading QImode using movzbl */
1276 {5, 5, 4}, /* cost of loading integer registers
1277 in QImode, HImode and SImode.
1278 Relative to reg-reg move (2). */
1279 {4, 4, 4}, /* cost of storing integer registers */
1280 2, /* cost of reg,reg fld/fst */
1281 {5, 5, 12}, /* cost of loading fp registers
1282 in SFmode, DFmode and XFmode */
1283 {4, 4, 8}, /* cost of storing fp registers
1284 in SFmode, DFmode and XFmode */
1285 2, /* cost of moving MMX register */
1286 {4, 4}, /* cost of loading MMX registers
1287 in SImode and DImode */
1288 {4, 4}, /* cost of storing MMX registers
1289 in SImode and DImode */
1290 2, /* cost of moving SSE register */
1291 {4, 4, 4}, /* cost of loading SSE registers
1292 in SImode, DImode and TImode */
1293 {4, 4, 4}, /* cost of storing SSE registers
1294 in SImode, DImode and TImode */
1295 2, /* MMX or SSE register to integer */
1297 MOVD reg64, xmmreg Double FSTORE 4
1298 MOVD reg32, xmmreg Double FSTORE 4
1300 MOVD reg64, xmmreg Double FADD 3
1302 MOVD reg32, xmmreg Double FADD 3
1304 16, /* size of l1 cache. */
1305 2048, /* size of l2 cache. */
1306 64, /* size of prefetch block */
1307 /* New AMD processors never drop prefetches; if they cannot be performed
1308 immediately, they are queued. We set number of simultaneous prefetches
1309 to a large constant to reflect this (it probably is not a good idea not
1310 to limit number of prefetches at all, as their execution also takes some
1312 100, /* number of parallel prefetches */
1313 2, /* Branch cost */
1314 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
1315 COSTS_N_INSNS (6), /* cost of FMUL instruction. */
1316 COSTS_N_INSNS (42), /* cost of FDIV instruction. */
1317 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1318 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1319 COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
1321 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
1322 very small blocks it is better to use loop. For large blocks, libcall
1323 can do nontemporary accesses and beat inline considerably. */
1324 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
1325 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1326 {{libcall, {{8, loop}, {24, unrolled_loop},
1327 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1328 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1329 6, /* scalar_stmt_cost. */
1330 4, /* scalar load_cost. */
1331 4, /* scalar_store_cost. */
1332 6, /* vec_stmt_cost. */
1333 0, /* vec_to_scalar_cost. */
1334 2, /* scalar_to_vec_cost. */
1335 4, /* vec_align_load_cost. */
1336 4, /* vec_unalign_load_cost. */
1337 4, /* vec_store_cost. */
1338 2, /* cond_taken_branch_cost. */
1339 1, /* cond_not_taken_branch_cost. */
1342 struct processor_costs bdver2_cost = {
1343 COSTS_N_INSNS (1), /* cost of an add instruction */
1344 COSTS_N_INSNS (1), /* cost of a lea instruction */
1345 COSTS_N_INSNS (1), /* variable shift costs */
1346 COSTS_N_INSNS (1), /* constant shift costs */
1347 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
1348 COSTS_N_INSNS (4), /* HI */
1349 COSTS_N_INSNS (4), /* SI */
1350 COSTS_N_INSNS (6), /* DI */
1351 COSTS_N_INSNS (6)}, /* other */
1352 0, /* cost of multiply per each bit set */
1353 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
1354 COSTS_N_INSNS (35), /* HI */
1355 COSTS_N_INSNS (51), /* SI */
1356 COSTS_N_INSNS (83), /* DI */
1357 COSTS_N_INSNS (83)}, /* other */
1358 COSTS_N_INSNS (1), /* cost of movsx */
1359 COSTS_N_INSNS (1), /* cost of movzx */
1360 8, /* "large" insn */
1362 4, /* cost for loading QImode using movzbl */
1363 {5, 5, 4}, /* cost of loading integer registers
1364 in QImode, HImode and SImode.
1365 Relative to reg-reg move (2). */
1366 {4, 4, 4}, /* cost of storing integer registers */
1367 2, /* cost of reg,reg fld/fst */
1368 {5, 5, 12}, /* cost of loading fp registers
1369 in SFmode, DFmode and XFmode */
1370 {4, 4, 8}, /* cost of storing fp registers
1371 in SFmode, DFmode and XFmode */
1372 2, /* cost of moving MMX register */
1373 {4, 4}, /* cost of loading MMX registers
1374 in SImode and DImode */
1375 {4, 4}, /* cost of storing MMX registers
1376 in SImode and DImode */
1377 2, /* cost of moving SSE register */
1378 {4, 4, 4}, /* cost of loading SSE registers
1379 in SImode, DImode and TImode */
1380 {4, 4, 4}, /* cost of storing SSE registers
1381 in SImode, DImode and TImode */
1382 2, /* MMX or SSE register to integer */
1384 MOVD reg64, xmmreg Double FSTORE 4
1385 MOVD reg32, xmmreg Double FSTORE 4
1387 MOVD reg64, xmmreg Double FADD 3
1389 MOVD reg32, xmmreg Double FADD 3
1391 16, /* size of l1 cache. */
1392 2048, /* size of l2 cache. */
1393 64, /* size of prefetch block */
1394 /* New AMD processors never drop prefetches; if they cannot be performed
1395 immediately, they are queued. We set number of simultaneous prefetches
1396 to a large constant to reflect this (it probably is not a good idea not
1397 to limit number of prefetches at all, as their execution also takes some
1399 100, /* number of parallel prefetches */
1400 2, /* Branch cost */
1401 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
1402 COSTS_N_INSNS (6), /* cost of FMUL instruction. */
1403 COSTS_N_INSNS (42), /* cost of FDIV instruction. */
1404 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1405 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1406 COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
1408 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1409 very small blocks it is better to use loop. For large blocks, libcall
1410 can do nontemporary accesses and beat inline considerably. */
1411 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
1412 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1413 {{libcall, {{8, loop}, {24, unrolled_loop},
1414 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1415 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1416 6, /* scalar_stmt_cost. */
1417 4, /* scalar load_cost. */
1418 4, /* scalar_store_cost. */
1419 6, /* vec_stmt_cost. */
1420 0, /* vec_to_scalar_cost. */
1421 2, /* scalar_to_vec_cost. */
1422 4, /* vec_align_load_cost. */
1423 4, /* vec_unalign_load_cost. */
1424 4, /* vec_store_cost. */
1425 2, /* cond_taken_branch_cost. */
1426 1, /* cond_not_taken_branch_cost. */
1429 struct processor_costs btver1_cost = {
1430 COSTS_N_INSNS (1), /* cost of an add instruction */
1431 COSTS_N_INSNS (2), /* cost of a lea instruction */
1432 COSTS_N_INSNS (1), /* variable shift costs */
1433 COSTS_N_INSNS (1), /* constant shift costs */
1434 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1435 COSTS_N_INSNS (4), /* HI */
1436 COSTS_N_INSNS (3), /* SI */
1437 COSTS_N_INSNS (4), /* DI */
1438 COSTS_N_INSNS (5)}, /* other */
1439 0, /* cost of multiply per each bit set */
1440 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
1441 COSTS_N_INSNS (35), /* HI */
1442 COSTS_N_INSNS (51), /* SI */
1443 COSTS_N_INSNS (83), /* DI */
1444 COSTS_N_INSNS (83)}, /* other */
1445 COSTS_N_INSNS (1), /* cost of movsx */
1446 COSTS_N_INSNS (1), /* cost of movzx */
1447 8, /* "large" insn */
1449 4, /* cost for loading QImode using movzbl */
1450 {3, 4, 3}, /* cost of loading integer registers
1451 in QImode, HImode and SImode.
1452 Relative to reg-reg move (2). */
1453 {3, 4, 3}, /* cost of storing integer registers */
1454 4, /* cost of reg,reg fld/fst */
1455 {4, 4, 12}, /* cost of loading fp registers
1456 in SFmode, DFmode and XFmode */
1457 {6, 6, 8}, /* cost of storing fp registers
1458 in SFmode, DFmode and XFmode */
1459 2, /* cost of moving MMX register */
1460 {3, 3}, /* cost of loading MMX registers
1461 in SImode and DImode */
1462 {4, 4}, /* cost of storing MMX registers
1463 in SImode and DImode */
1464 2, /* cost of moving SSE register */
1465 {4, 4, 3}, /* cost of loading SSE registers
1466 in SImode, DImode and TImode */
1467 {4, 4, 5}, /* cost of storing SSE registers
1468 in SImode, DImode and TImode */
1469 3, /* MMX or SSE register to integer */
1471 MOVD reg64, xmmreg Double FSTORE 4
1472 MOVD reg32, xmmreg Double FSTORE 4
1474 MOVD reg64, xmmreg Double FADD 3
1476 MOVD reg32, xmmreg Double FADD 3
1478 32, /* size of l1 cache. */
1479 512, /* size of l2 cache. */
1480 64, /* size of prefetch block */
1481 100, /* number of parallel prefetches */
1482 2, /* Branch cost */
1483 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
1484 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
1485 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
1486 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1487 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1488 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
1490 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1491 very small blocks it is better to use loop. For large blocks, libcall can
1492 do nontemporary accesses and beat inline considerably. */
1493 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
1494 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1495 {{libcall, {{8, loop}, {24, unrolled_loop},
1496 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1497 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1498 4, /* scalar_stmt_cost. */
1499 2, /* scalar load_cost. */
1500 2, /* scalar_store_cost. */
1501 6, /* vec_stmt_cost. */
1502 0, /* vec_to_scalar_cost. */
1503 2, /* scalar_to_vec_cost. */
1504 2, /* vec_align_load_cost. */
1505 2, /* vec_unalign_load_cost. */
1506 2, /* vec_store_cost. */
1507 2, /* cond_taken_branch_cost. */
1508 1, /* cond_not_taken_branch_cost. */
1512 struct processor_costs pentium4_cost = {
1513 COSTS_N_INSNS (1), /* cost of an add instruction */
1514 COSTS_N_INSNS (3), /* cost of a lea instruction */
1515 COSTS_N_INSNS (4), /* variable shift costs */
1516 COSTS_N_INSNS (4), /* constant shift costs */
1517 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
1518 COSTS_N_INSNS (15), /* HI */
1519 COSTS_N_INSNS (15), /* SI */
1520 COSTS_N_INSNS (15), /* DI */
1521 COSTS_N_INSNS (15)}, /* other */
1522 0, /* cost of multiply per each bit set */
1523 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
1524 COSTS_N_INSNS (56), /* HI */
1525 COSTS_N_INSNS (56), /* SI */
1526 COSTS_N_INSNS (56), /* DI */
1527 COSTS_N_INSNS (56)}, /* other */
1528 COSTS_N_INSNS (1), /* cost of movsx */
1529 COSTS_N_INSNS (1), /* cost of movzx */
1530 16, /* "large" insn */
1532 2, /* cost for loading QImode using movzbl */
1533 {4, 5, 4}, /* cost of loading integer registers
1534 in QImode, HImode and SImode.
1535 Relative to reg-reg move (2). */
1536 {2, 3, 2}, /* cost of storing integer registers */
1537 2, /* cost of reg,reg fld/fst */
1538 {2, 2, 6}, /* cost of loading fp registers
1539 in SFmode, DFmode and XFmode */
1540 {4, 4, 6}, /* cost of storing fp registers
1541 in SFmode, DFmode and XFmode */
1542 2, /* cost of moving MMX register */
1543 {2, 2}, /* cost of loading MMX registers
1544 in SImode and DImode */
1545 {2, 2}, /* cost of storing MMX registers
1546 in SImode and DImode */
1547 12, /* cost of moving SSE register */
1548 {12, 12, 12}, /* cost of loading SSE registers
1549 in SImode, DImode and TImode */
1550 {2, 2, 8}, /* cost of storing SSE registers
1551 in SImode, DImode and TImode */
1552 10, /* MMX or SSE register to integer */
1553 8, /* size of l1 cache. */
1554 256, /* size of l2 cache. */
1555 64, /* size of prefetch block */
1556 6, /* number of parallel prefetches */
1557 2, /* Branch cost */
1558 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
1559 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
1560 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
1561 COSTS_N_INSNS (2), /* cost of FABS instruction. */
1562 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
1563 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
1564 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
1565 DUMMY_STRINGOP_ALGS},
1566 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
1568 DUMMY_STRINGOP_ALGS},
1569 1, /* scalar_stmt_cost. */
1570 1, /* scalar load_cost. */
1571 1, /* scalar_store_cost. */
1572 1, /* vec_stmt_cost. */
1573 1, /* vec_to_scalar_cost. */
1574 1, /* scalar_to_vec_cost. */
1575 1, /* vec_align_load_cost. */
1576 2, /* vec_unalign_load_cost. */
1577 1, /* vec_store_cost. */
1578 3, /* cond_taken_branch_cost. */
1579 1, /* cond_not_taken_branch_cost. */
1583 struct processor_costs nocona_cost = {
1584 COSTS_N_INSNS (1), /* cost of an add instruction */
1585 COSTS_N_INSNS (1), /* cost of a lea instruction */
1586 COSTS_N_INSNS (1), /* variable shift costs */
1587 COSTS_N_INSNS (1), /* constant shift costs */
1588 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
1589 COSTS_N_INSNS (10), /* HI */
1590 COSTS_N_INSNS (10), /* SI */
1591 COSTS_N_INSNS (10), /* DI */
1592 COSTS_N_INSNS (10)}, /* other */
1593 0, /* cost of multiply per each bit set */
1594 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
1595 COSTS_N_INSNS (66), /* HI */
1596 COSTS_N_INSNS (66), /* SI */
1597 COSTS_N_INSNS (66), /* DI */
1598 COSTS_N_INSNS (66)}, /* other */
1599 COSTS_N_INSNS (1), /* cost of movsx */
1600 COSTS_N_INSNS (1), /* cost of movzx */
1601 16, /* "large" insn */
1602 17, /* MOVE_RATIO */
1603 4, /* cost for loading QImode using movzbl */
1604 {4, 4, 4}, /* cost of loading integer registers
1605 in QImode, HImode and SImode.
1606 Relative to reg-reg move (2). */
1607 {4, 4, 4}, /* cost of storing integer registers */
1608 3, /* cost of reg,reg fld/fst */
1609 {12, 12, 12}, /* cost of loading fp registers
1610 in SFmode, DFmode and XFmode */
1611 {4, 4, 4}, /* cost of storing fp registers
1612 in SFmode, DFmode and XFmode */
1613 6, /* cost of moving MMX register */
1614 {12, 12}, /* cost of loading MMX registers
1615 in SImode and DImode */
1616 {12, 12}, /* cost of storing MMX registers
1617 in SImode and DImode */
1618 6, /* cost of moving SSE register */
1619 {12, 12, 12}, /* cost of loading SSE registers
1620 in SImode, DImode and TImode */
1621 {12, 12, 12}, /* cost of storing SSE registers
1622 in SImode, DImode and TImode */
1623 8, /* MMX or SSE register to integer */
1624 8, /* size of l1 cache. */
1625 1024, /* size of l2 cache. */
1626 128, /* size of prefetch block */
1627 8, /* number of parallel prefetches */
1628 1, /* Branch cost */
1629 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
1630 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1631 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
1632 COSTS_N_INSNS (3), /* cost of FABS instruction. */
1633 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
1634 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
1635 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
1636 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
1637 {100000, unrolled_loop}, {-1, libcall}}}},
1638 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
1640 {libcall, {{24, loop}, {64, unrolled_loop},
1641 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1642 1, /* scalar_stmt_cost. */
1643 1, /* scalar load_cost. */
1644 1, /* scalar_store_cost. */
1645 1, /* vec_stmt_cost. */
1646 1, /* vec_to_scalar_cost. */
1647 1, /* scalar_to_vec_cost. */
1648 1, /* vec_align_load_cost. */
1649 2, /* vec_unalign_load_cost. */
1650 1, /* vec_store_cost. */
1651 3, /* cond_taken_branch_cost. */
1652 1, /* cond_not_taken_branch_cost. */
1656 struct processor_costs atom_cost = {
1657 COSTS_N_INSNS (1), /* cost of an add instruction */
1658 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1659 COSTS_N_INSNS (1), /* variable shift costs */
1660 COSTS_N_INSNS (1), /* constant shift costs */
1661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1662 COSTS_N_INSNS (4), /* HI */
1663 COSTS_N_INSNS (3), /* SI */
1664 COSTS_N_INSNS (4), /* DI */
1665 COSTS_N_INSNS (2)}, /* other */
1666 0, /* cost of multiply per each bit set */
1667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1668 COSTS_N_INSNS (26), /* HI */
1669 COSTS_N_INSNS (42), /* SI */
1670 COSTS_N_INSNS (74), /* DI */
1671 COSTS_N_INSNS (74)}, /* other */
1672 COSTS_N_INSNS (1), /* cost of movsx */
1673 COSTS_N_INSNS (1), /* cost of movzx */
1674 8, /* "large" insn */
1675 17, /* MOVE_RATIO */
1676 4, /* cost for loading QImode using movzbl */
1677 {4, 4, 4}, /* cost of loading integer registers
1678 in QImode, HImode and SImode.
1679 Relative to reg-reg move (2). */
1680 {4, 4, 4}, /* cost of storing integer registers */
1681 4, /* cost of reg,reg fld/fst */
1682 {12, 12, 12}, /* cost of loading fp registers
1683 in SFmode, DFmode and XFmode */
1684 {6, 6, 8}, /* cost of storing fp registers
1685 in SFmode, DFmode and XFmode */
1686 2, /* cost of moving MMX register */
1687 {8, 8}, /* cost of loading MMX registers
1688 in SImode and DImode */
1689 {8, 8}, /* cost of storing MMX registers
1690 in SImode and DImode */
1691 2, /* cost of moving SSE register */
1692 {8, 8, 8}, /* cost of loading SSE registers
1693 in SImode, DImode and TImode */
1694 {8, 8, 8}, /* cost of storing SSE registers
1695 in SImode, DImode and TImode */
1696 5, /* MMX or SSE register to integer */
1697 32, /* size of l1 cache. */
1698 256, /* size of l2 cache. */
1699 64, /* size of prefetch block */
1700 6, /* number of parallel prefetches */
1701 3, /* Branch cost */
1702 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1703 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1704 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1705 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1706 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1707 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1708 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1709 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1710 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1711 {{libcall, {{8, loop}, {15, unrolled_loop},
1712 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1713 {libcall, {{24, loop}, {32, unrolled_loop},
1714 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1715 1, /* scalar_stmt_cost. */
1716 1, /* scalar load_cost. */
1717 1, /* scalar_store_cost. */
1718 1, /* vec_stmt_cost. */
1719 1, /* vec_to_scalar_cost. */
1720 1, /* scalar_to_vec_cost. */
1721 1, /* vec_align_load_cost. */
1722 2, /* vec_unalign_load_cost. */
1723 1, /* vec_store_cost. */
1724 3, /* cond_taken_branch_cost. */
1725 1, /* cond_not_taken_branch_cost. */
1728 /* Generic64 should produce code tuned for Nocona and K8. */
1730 struct processor_costs generic64_cost = {
1731 COSTS_N_INSNS (1), /* cost of an add instruction */
1732 /* On all chips taken into consideration lea is 2 cycles and more. With
1733 this cost however our current implementation of synth_mult results in
1734 use of unnecessary temporary registers causing regression on several
1735 SPECfp benchmarks. */
1736 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1737 COSTS_N_INSNS (1), /* variable shift costs */
1738 COSTS_N_INSNS (1), /* constant shift costs */
1739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1740 COSTS_N_INSNS (4), /* HI */
1741 COSTS_N_INSNS (3), /* SI */
1742 COSTS_N_INSNS (4), /* DI */
1743 COSTS_N_INSNS (2)}, /* other */
1744 0, /* cost of multiply per each bit set */
1745 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1746 COSTS_N_INSNS (26), /* HI */
1747 COSTS_N_INSNS (42), /* SI */
1748 COSTS_N_INSNS (74), /* DI */
1749 COSTS_N_INSNS (74)}, /* other */
1750 COSTS_N_INSNS (1), /* cost of movsx */
1751 COSTS_N_INSNS (1), /* cost of movzx */
1752 8, /* "large" insn */
1753 17, /* MOVE_RATIO */
1754 4, /* cost for loading QImode using movzbl */
1755 {4, 4, 4}, /* cost of loading integer registers
1756 in QImode, HImode and SImode.
1757 Relative to reg-reg move (2). */
1758 {4, 4, 4}, /* cost of storing integer registers */
1759 4, /* cost of reg,reg fld/fst */
1760 {12, 12, 12}, /* cost of loading fp registers
1761 in SFmode, DFmode and XFmode */
1762 {6, 6, 8}, /* cost of storing fp registers
1763 in SFmode, DFmode and XFmode */
1764 2, /* cost of moving MMX register */
1765 {8, 8}, /* cost of loading MMX registers
1766 in SImode and DImode */
1767 {8, 8}, /* cost of storing MMX registers
1768 in SImode and DImode */
1769 2, /* cost of moving SSE register */
1770 {8, 8, 8}, /* cost of loading SSE registers
1771 in SImode, DImode and TImode */
1772 {8, 8, 8}, /* cost of storing SSE registers
1773 in SImode, DImode and TImode */
1774 5, /* MMX or SSE register to integer */
1775 32, /* size of l1 cache. */
1776 512, /* size of l2 cache. */
1777 64, /* size of prefetch block */
1778 6, /* number of parallel prefetches */
1779 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1780 value is increased to perhaps more appropriate value of 5. */
1781 3, /* Branch cost */
1782 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1783 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1784 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1785 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1786 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1787 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1788 {DUMMY_STRINGOP_ALGS,
1789 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1790 {DUMMY_STRINGOP_ALGS,
1791 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1792 1, /* scalar_stmt_cost. */
1793 1, /* scalar load_cost. */
1794 1, /* scalar_store_cost. */
1795 1, /* vec_stmt_cost. */
1796 1, /* vec_to_scalar_cost. */
1797 1, /* scalar_to_vec_cost. */
1798 1, /* vec_align_load_cost. */
1799 2, /* vec_unalign_load_cost. */
1800 1, /* vec_store_cost. */
1801 3, /* cond_taken_branch_cost. */
1802 1, /* cond_not_taken_branch_cost. */
1805 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1808 struct processor_costs generic32_cost = {
1809 COSTS_N_INSNS (1), /* cost of an add instruction */
1810 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1811 COSTS_N_INSNS (1), /* variable shift costs */
1812 COSTS_N_INSNS (1), /* constant shift costs */
1813 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1814 COSTS_N_INSNS (4), /* HI */
1815 COSTS_N_INSNS (3), /* SI */
1816 COSTS_N_INSNS (4), /* DI */
1817 COSTS_N_INSNS (2)}, /* other */
1818 0, /* cost of multiply per each bit set */
1819 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1820 COSTS_N_INSNS (26), /* HI */
1821 COSTS_N_INSNS (42), /* SI */
1822 COSTS_N_INSNS (74), /* DI */
1823 COSTS_N_INSNS (74)}, /* other */
1824 COSTS_N_INSNS (1), /* cost of movsx */
1825 COSTS_N_INSNS (1), /* cost of movzx */
1826 8, /* "large" insn */
1827 17, /* MOVE_RATIO */
1828 4, /* cost for loading QImode using movzbl */
1829 {4, 4, 4}, /* cost of loading integer registers
1830 in QImode, HImode and SImode.
1831 Relative to reg-reg move (2). */
1832 {4, 4, 4}, /* cost of storing integer registers */
1833 4, /* cost of reg,reg fld/fst */
1834 {12, 12, 12}, /* cost of loading fp registers
1835 in SFmode, DFmode and XFmode */
1836 {6, 6, 8}, /* cost of storing fp registers
1837 in SFmode, DFmode and XFmode */
1838 2, /* cost of moving MMX register */
1839 {8, 8}, /* cost of loading MMX registers
1840 in SImode and DImode */
1841 {8, 8}, /* cost of storing MMX registers
1842 in SImode and DImode */
1843 2, /* cost of moving SSE register */
1844 {8, 8, 8}, /* cost of loading SSE registers
1845 in SImode, DImode and TImode */
1846 {8, 8, 8}, /* cost of storing SSE registers
1847 in SImode, DImode and TImode */
1848 5, /* MMX or SSE register to integer */
1849 32, /* size of l1 cache. */
1850 256, /* size of l2 cache. */
1851 64, /* size of prefetch block */
1852 6, /* number of parallel prefetches */
1853 3, /* Branch cost */
1854 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1855 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1856 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1857 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1858 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1859 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1860 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1861 DUMMY_STRINGOP_ALGS},
1862 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1863 DUMMY_STRINGOP_ALGS},
1864 1, /* scalar_stmt_cost. */
1865 1, /* scalar load_cost. */
1866 1, /* scalar_store_cost. */
1867 1, /* vec_stmt_cost. */
1868 1, /* vec_to_scalar_cost. */
1869 1, /* scalar_to_vec_cost. */
1870 1, /* vec_align_load_cost. */
1871 2, /* vec_unalign_load_cost. */
1872 1, /* vec_store_cost. */
1873 3, /* cond_taken_branch_cost. */
1874 1, /* cond_not_taken_branch_cost. */
1877 const struct processor_costs *ix86_cost = &pentium_cost;
1879 /* Processor feature/optimization bitmasks. */
1880 #define m_386 (1<<PROCESSOR_I386)
1881 #define m_486 (1<<PROCESSOR_I486)
1882 #define m_PENT (1<<PROCESSOR_PENTIUM)
1883 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1884 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1885 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1886 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1887 #define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
1888 #define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
1889 #define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
1890 #define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
1891 #define m_COREI7 (m_COREI7_32 | m_COREI7_64)
1892 #define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
1893 #define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
1894 #define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
1895 #define m_ATOM (1<<PROCESSOR_ATOM)
1897 #define m_GEODE (1<<PROCESSOR_GEODE)
1898 #define m_K6 (1<<PROCESSOR_K6)
1899 #define m_K6_GEODE (m_K6 | m_GEODE)
1900 #define m_K8 (1<<PROCESSOR_K8)
1901 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1902 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1903 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1904 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1905 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1906 #define m_BDVER (m_BDVER1 | m_BDVER2)
1907 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1908 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1)
1910 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1911 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1913 /* Generic instruction choice should be common subset of supported CPUs
1914 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1915 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1917 /* Feature tests against the various tunings. */
1918 unsigned char ix86_tune_features[X86_TUNE_LAST];
1920 /* Feature tests against the various tunings used to create ix86_tune_features
1921 based on the processor mask. */
1922 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1923 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1924 negatively, so enabling for Generic64 seems like good code size
1925 tradeoff. We can't enable it for 32bit generic because it does not
1926 work well with PPro base chips. */
1927 m_386 | m_CORE2I7_64 | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC64,
1929 /* X86_TUNE_PUSH_MEMORY */
1930 m_386 | m_P4_NOCONA | m_CORE2I7 | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
1932 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1935 /* X86_TUNE_UNROLL_STRLEN */
1936 m_486 | m_PENT | m_PPRO | m_ATOM | m_CORE2I7 | m_K6 | m_AMD_MULTIPLE | m_GENERIC,
1938 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1939 on simulation result. But after P4 was made, no performance benefit
1940 was observed with branch hints. It also increases the code size.
1941 As a result, icc never generates branch hints. */
1944 /* X86_TUNE_DOUBLE_WITH_ADD */
1947 /* X86_TUNE_USE_SAHF */
1948 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC,
1950 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1951 partial dependencies. */
1952 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GEODE | m_AMD_MULTIPLE | m_GENERIC,
1954 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1955 register stalls on Generic32 compilation setting as well. However
1956 in current implementation the partial register stalls are not eliminated
1957 very well - they can be introduced via subregs synthesized by combine
1958 and can happen in caller/callee saving sequences. Because this option
1959 pays back little on PPro based chips and is in conflict with partial reg
1960 dependencies used by Athlon/P4 based chips, it is better to leave it off
1961 for generic32 for now. */
1964 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1965 m_CORE2I7 | m_GENERIC,
1967 /* X86_TUNE_USE_HIMODE_FIOP */
1968 m_386 | m_486 | m_K6_GEODE,
1970 /* X86_TUNE_USE_SIMODE_FIOP */
1971 ~(m_PENT | m_PPRO | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC),
1973 /* X86_TUNE_USE_MOV0 */
1976 /* X86_TUNE_USE_CLTD */
1977 ~(m_PENT | m_CORE2I7 | m_ATOM | m_K6 | m_GENERIC),
1979 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1982 /* X86_TUNE_SPLIT_LONG_MOVES */
1985 /* X86_TUNE_READ_MODIFY_WRITE */
1988 /* X86_TUNE_READ_MODIFY */
1991 /* X86_TUNE_PROMOTE_QIMODE */
1992 m_386 | m_486 | m_PENT | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
1994 /* X86_TUNE_FAST_PREFIX */
1995 ~(m_386 | m_486 | m_PENT),
1997 /* X86_TUNE_SINGLE_STRINGOP */
1998 m_386 | m_P4_NOCONA,
2000 /* X86_TUNE_QIMODE_MATH */
2003 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
2004 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
2005 might be considered for Generic32 if our scheme for avoiding partial
2006 stalls was more effective. */
2009 /* X86_TUNE_PROMOTE_QI_REGS */
2012 /* X86_TUNE_PROMOTE_HI_REGS */
2015 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
2016 over esp addition. */
2017 m_386 | m_486 | m_PENT | m_PPRO,
2019 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
2020 over esp addition. */
2023 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
2024 over esp subtraction. */
2025 m_386 | m_486 | m_PENT | m_K6_GEODE,
2027 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
2028 over esp subtraction. */
2029 m_PENT | m_K6_GEODE,
2031 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
2032 for DFmode copies */
2033 ~(m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GEODE | m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
2035 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
2036 m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
2038 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
2039 conflict here in between PPro/Pentium4 based chips that thread 128bit
2040 SSE registers as single units versus K8 based chips that divide SSE
2041 registers to two 64bit halves. This knob promotes all store destinations
2042 to be 128bit to allow register renaming on 128bit SSE units, but usually
2043 results in one extra microop on 64bit SSE units. Experimental results
2044 shows that disabling this option on P4 brings over 20% SPECfp regression,
2045 while enabling it on K8 brings roughly 2.4% regression that can be partly
2046 masked by careful scheduling of moves. */
2047 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC,
2049 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
2050 m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER1,
2052 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
2055 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
2058 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
2059 are resolved on SSE register parts instead of whole registers, so we may
2060 maintain just lower part of scalar values in proper format leaving the
2061 upper part undefined. */
2064 /* X86_TUNE_SSE_TYPELESS_STORES */
2067 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
2068 m_PPRO | m_P4_NOCONA,
2070 /* X86_TUNE_MEMORY_MISMATCH_STALL */
2071 m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
2073 /* X86_TUNE_PROLOGUE_USING_MOVE */
2074 m_PPRO | m_CORE2I7 | m_ATOM | m_ATHLON_K8 | m_GENERIC,
2076 /* X86_TUNE_EPILOGUE_USING_MOVE */
2077 m_PPRO | m_CORE2I7 | m_ATOM | m_ATHLON_K8 | m_GENERIC,
2079 /* X86_TUNE_SHIFT1 */
2082 /* X86_TUNE_USE_FFREEP */
2085 /* X86_TUNE_INTER_UNIT_MOVES */
2086 ~(m_AMD_MULTIPLE | m_GENERIC),
2088 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
2089 ~(m_AMDFAM10 | m_BDVER ),
2091 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
2092 than 4 branch instructions in the 16 byte window. */
2093 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
2095 /* X86_TUNE_SCHEDULE */
2096 m_PENT | m_PPRO | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
2098 /* X86_TUNE_USE_BT */
2099 m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
2101 /* X86_TUNE_USE_INCDEC */
2102 ~(m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GENERIC),
2104 /* X86_TUNE_PAD_RETURNS */
2105 m_CORE2I7 | m_AMD_MULTIPLE | m_GENERIC,
2107 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
2110 /* X86_TUNE_EXT_80387_CONSTANTS */
2111 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC,
2113 /* X86_TUNE_SHORTEN_X87_SSE */
2116 /* X86_TUNE_AVOID_VECTOR_DECODE */
2117 m_CORE2I7_64 | m_K8 | m_GENERIC64,
2119 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
2120 and SImode multiply, but 386 and 486 do HImode multiply faster. */
2123 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
2124 vector path on AMD machines. */
2125 m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64,
2127 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
2129 m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64,
2131 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
2135 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
2136 but one byte longer. */
2139 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
2140 operand that cannot be represented using a modRM byte. The XOR
2141 replacement is long decoded, so this split helps here as well. */
2144 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
2146 m_CORE2I7 | m_AMDFAM10 | m_GENERIC,
2148 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
2149 from integer to FP. */
2152 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
2153 with a subsequent conditional jump instruction into a single
2154 compare-and-branch uop. */
2157 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2158 will impact LEA instruction selection. */
2161 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2165 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2166 at -O3. For the moment, the prefetching seems badly tuned for Intel
2168 m_K6_GEODE | m_AMD_MULTIPLE,
2170 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2171 the auto-vectorizer. */
2174 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2175 during reassociation of integer computation. */
2178 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2179 during reassociation of fp computation. */
2183 /* Feature tests against the various architecture variations. */
2184 unsigned char ix86_arch_features[X86_ARCH_LAST];
2186 /* Feature tests against the various architecture variations, used to create
2187 ix86_arch_features based on the processor mask. */
2188 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
2189 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2190 ~(m_386 | m_486 | m_PENT | m_K6),
2192 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2195 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2198 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2201 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2205 static const unsigned int x86_accumulate_outgoing_args
2206 = m_PPRO | m_P4_NOCONA | m_ATOM | m_CORE2I7 | m_AMD_MULTIPLE | m_GENERIC;
2208 static const unsigned int x86_arch_always_fancy_math_387
2209 = m_PENT | m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC;
2211 static const unsigned int x86_avx256_split_unaligned_load
2212 = m_COREI7 | m_GENERIC;
2214 static const unsigned int x86_avx256_split_unaligned_store
2215 = m_COREI7 | m_BDVER | m_GENERIC;
2217 /* In case the average insn count for single function invocation is
2218 lower than this constant, emit fast (but longer) prologue and
2220 #define FAST_PROLOGUE_INSN_COUNT 20
2222 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2223 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
2224 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
2225 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
2227 /* Array of the smallest class containing reg number REGNO, indexed by
2228 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2230 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
2232 /* ax, dx, cx, bx */
2233 AREG, DREG, CREG, BREG,
2234 /* si, di, bp, sp */
2235 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
2237 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
2238 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
2241 /* flags, fpsr, fpcr, frame */
2242 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
2244 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
2247 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
2250 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
2251 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
2252 /* SSE REX registers */
2253 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
2257 /* The "default" register map used in 32bit mode. */
2259 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
2261 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
2262 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
2263 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
2264 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
2265 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
2266 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
2267 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
2270 /* The "default" register map used in 64bit mode. */
2272 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
2274 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
2275 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
2276 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
2277 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
2278 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
2279 8,9,10,11,12,13,14,15, /* extended integer registers */
2280 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
2283 /* Define the register numbers to be used in Dwarf debugging information.
2284 The SVR4 reference port C compiler uses the following register numbers
2285 in its Dwarf output code:
2286 0 for %eax (gcc regno = 0)
2287 1 for %ecx (gcc regno = 2)
2288 2 for %edx (gcc regno = 1)
2289 3 for %ebx (gcc regno = 3)
2290 4 for %esp (gcc regno = 7)
2291 5 for %ebp (gcc regno = 6)
2292 6 for %esi (gcc regno = 4)
2293 7 for %edi (gcc regno = 5)
2294 The following three DWARF register numbers are never generated by
2295 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2296 believes these numbers have these meanings.
2297 8 for %eip (no gcc equivalent)
2298 9 for %eflags (gcc regno = 17)
2299 10 for %trapno (no gcc equivalent)
2300 It is not at all clear how we should number the FP stack registers
2301 for the x86 architecture. If the version of SDB on x86/svr4 were
2302 a bit less brain dead with respect to floating-point then we would
2303 have a precedent to follow with respect to DWARF register numbers
2304 for x86 FP registers, but the SDB on x86/svr4 is so completely
2305 broken with respect to FP registers that it is hardly worth thinking
2306 of it as something to strive for compatibility with.
2307 The version of x86/svr4 SDB I have at the moment does (partially)
2308 seem to believe that DWARF register number 11 is associated with
2309 the x86 register %st(0), but that's about all. Higher DWARF
2310 register numbers don't seem to be associated with anything in
2311 particular, and even for DWARF regno 11, SDB only seems to under-
2312 stand that it should say that a variable lives in %st(0) (when
2313 asked via an `=' command) if we said it was in DWARF regno 11,
2314 but SDB still prints garbage when asked for the value of the
2315 variable in question (via a `/' command).
2316 (Also note that the labels SDB prints for various FP stack regs
2317 when doing an `x' command are all wrong.)
2318 Note that these problems generally don't affect the native SVR4
2319 C compiler because it doesn't allow the use of -O with -g and
2320 because when it is *not* optimizing, it allocates a memory
2321 location for each floating-point variable, and the memory
2322 location is what gets described in the DWARF AT_location
2323 attribute for the variable in question.
2324 Regardless of the severe mental illness of the x86/svr4 SDB, we
2325 do something sensible here and we use the following DWARF
2326 register numbers. Note that these are all stack-top-relative
2328 11 for %st(0) (gcc regno = 8)
2329 12 for %st(1) (gcc regno = 9)
2330 13 for %st(2) (gcc regno = 10)
2331 14 for %st(3) (gcc regno = 11)
2332 15 for %st(4) (gcc regno = 12)
2333 16 for %st(5) (gcc regno = 13)
2334 17 for %st(6) (gcc regno = 14)
2335 18 for %st(7) (gcc regno = 15)
2337 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
2339 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
2340 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
2341 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
2342 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
2343 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
2344 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
2345 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
2348 /* Define parameter passing and return registers. */
2350 static int const x86_64_int_parameter_registers[6] =
2352 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
2355 static int const x86_64_ms_abi_int_parameter_registers[4] =
2357 CX_REG, DX_REG, R8_REG, R9_REG
2360 static int const x86_64_int_return_registers[4] =
2362 AX_REG, DX_REG, DI_REG, SI_REG
2365 /* Define the structure for the machine field in struct function. */
2367 struct GTY(()) stack_local_entry {
2368 unsigned short mode;
2371 struct stack_local_entry *next;
2374 /* Structure describing stack frame layout.
2375 Stack grows downward:
2381 saved static chain if ix86_static_chain_on_stack
2383 saved frame pointer if frame_pointer_needed
2384 <- HARD_FRAME_POINTER
2390 <- sse_regs_save_offset
2393 [va_arg registers] |
2397 [padding2] | = to_allocate
2406 int outgoing_arguments_size;
2407 HOST_WIDE_INT frame;
2409 /* The offsets relative to ARG_POINTER. */
2410 HOST_WIDE_INT frame_pointer_offset;
2411 HOST_WIDE_INT hard_frame_pointer_offset;
2412 HOST_WIDE_INT stack_pointer_offset;
2413 HOST_WIDE_INT hfp_save_offset;
2414 HOST_WIDE_INT reg_save_offset;
2415 HOST_WIDE_INT sse_reg_save_offset;
2417 /* When save_regs_using_mov is set, emit prologue using
2418 move instead of push instructions. */
2419 bool save_regs_using_mov;
2422 /* Which cpu are we scheduling for. */
2423 enum attr_cpu ix86_schedule;
2425 /* Which cpu are we optimizing for. */
2426 enum processor_type ix86_tune;
2428 /* Which instruction set architecture to use. */
2429 enum processor_type ix86_arch;
2431 /* true if sse prefetch instruction is not NOOP. */
2432 int x86_prefetch_sse;
2434 /* -mstackrealign option */
2435 static const char ix86_force_align_arg_pointer_string[]
2436 = "force_align_arg_pointer";
2438 static rtx (*ix86_gen_leave) (void);
2439 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
2440 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
2441 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx, rtx);
2442 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
2443 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
2444 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
2445 static rtx (*ix86_gen_allocate_stack_worker) (rtx, rtx);
2446 static rtx (*ix86_gen_adjust_stack_and_probe) (rtx, rtx, rtx);
2447 static rtx (*ix86_gen_probe_stack_range) (rtx, rtx, rtx);
2449 /* Preferred alignment for stack boundary in bits. */
2450 unsigned int ix86_preferred_stack_boundary;
2452 /* Alignment for incoming stack boundary in bits specified at
2454 static unsigned int ix86_user_incoming_stack_boundary;
2456 /* Default alignment for incoming stack boundary in bits. */
2457 static unsigned int ix86_default_incoming_stack_boundary;
2459 /* Alignment for incoming stack boundary in bits. */
2460 unsigned int ix86_incoming_stack_boundary;
2462 /* Calling abi specific va_list type nodes. */
2463 static GTY(()) tree sysv_va_list_type_node;
2464 static GTY(()) tree ms_va_list_type_node;
2466 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2467 char internal_label_prefix[16];
2468 int internal_label_prefix_len;
2470 /* Fence to use after loop using movnt. */
2473 /* Register class used for passing given 64bit part of the argument.
2474 These represent classes as documented by the PS ABI, with the exception
2475 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2476 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2478 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2479 whenever possible (upper half does contain padding). */
2480 enum x86_64_reg_class
2483 X86_64_INTEGER_CLASS,
2484 X86_64_INTEGERSI_CLASS,
2491 X86_64_COMPLEX_X87_CLASS,
2495 #define MAX_CLASSES 4
2497 /* Table of constants used by fldpi, fldln2, etc.... */
2498 static REAL_VALUE_TYPE ext_80387_constants_table [5];
2499 static bool ext_80387_constants_init = 0;
2502 static struct machine_function * ix86_init_machine_status (void);
2503 static rtx ix86_function_value (const_tree, const_tree, bool);
2504 static bool ix86_function_value_regno_p (const unsigned int);
2505 static unsigned int ix86_function_arg_boundary (enum machine_mode,
2507 static rtx ix86_static_chain (const_tree, bool);
2508 static int ix86_function_regparm (const_tree, const_tree);
2509 static void ix86_compute_frame_layout (struct ix86_frame *);
2510 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
2512 static void ix86_add_new_builtins (HOST_WIDE_INT);
2513 static tree ix86_canonical_va_list_type (tree);
2514 static void predict_jump (int);
2515 static unsigned int split_stack_prologue_scratch_regno (void);
2516 static bool i386_asm_output_addr_const_extra (FILE *, rtx);
2518 enum ix86_function_specific_strings
2520 IX86_FUNCTION_SPECIFIC_ARCH,
2521 IX86_FUNCTION_SPECIFIC_TUNE,
2522 IX86_FUNCTION_SPECIFIC_MAX
2525 static char *ix86_target_string (HOST_WIDE_INT, int, const char *,
2526 const char *, enum fpmath_unit, bool);
2527 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
2528 static void ix86_function_specific_save (struct cl_target_option *);
2529 static void ix86_function_specific_restore (struct cl_target_option *);
2530 static void ix86_function_specific_print (FILE *, int,
2531 struct cl_target_option *);
2532 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
2533 static bool ix86_valid_target_attribute_inner_p (tree, char *[],
2534 struct gcc_options *);
2535 static bool ix86_can_inline_p (tree, tree);
2536 static void ix86_set_current_function (tree);
2537 static unsigned int ix86_minimum_incoming_stack_boundary (bool);
2539 static enum calling_abi ix86_function_abi (const_tree);
2542 #ifndef SUBTARGET32_DEFAULT_CPU
2543 #define SUBTARGET32_DEFAULT_CPU "i386"
2546 /* The svr4 ABI for the i386 says that records and unions are returned
2548 #ifndef DEFAULT_PCC_STRUCT_RETURN
2549 #define DEFAULT_PCC_STRUCT_RETURN 1
2552 /* Whether -mtune= or -march= were specified */
2553 static int ix86_tune_defaulted;
2554 static int ix86_arch_specified;
2556 /* Vectorization library interface and handlers. */
2557 static tree (*ix86_veclib_handler) (enum built_in_function, tree, tree);
2559 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2560 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2562 /* Processor target table, indexed by processor number */
2565 const struct processor_costs *cost; /* Processor costs */
2566 const int align_loop; /* Default alignments. */
2567 const int align_loop_max_skip;
2568 const int align_jump;
2569 const int align_jump_max_skip;
2570 const int align_func;
2573 static const struct ptt processor_target_table[PROCESSOR_max] =
2575 {&i386_cost, 4, 3, 4, 3, 4},
2576 {&i486_cost, 16, 15, 16, 15, 16},
2577 {&pentium_cost, 16, 7, 16, 7, 16},
2578 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2579 {&geode_cost, 0, 0, 0, 0, 0},
2580 {&k6_cost, 32, 7, 32, 7, 32},
2581 {&athlon_cost, 16, 7, 16, 7, 16},
2582 {&pentium4_cost, 0, 0, 0, 0, 0},
2583 {&k8_cost, 16, 7, 16, 7, 16},
2584 {&nocona_cost, 0, 0, 0, 0, 0},
2585 /* Core 2 32-bit. */
2586 {&generic32_cost, 16, 10, 16, 10, 16},
2587 /* Core 2 64-bit. */
2588 {&generic64_cost, 16, 10, 16, 10, 16},
2589 /* Core i7 32-bit. */
2590 {&generic32_cost, 16, 10, 16, 10, 16},
2591 /* Core i7 64-bit. */
2592 {&generic64_cost, 16, 10, 16, 10, 16},
2593 {&generic32_cost, 16, 7, 16, 7, 16},
2594 {&generic64_cost, 16, 10, 16, 10, 16},
2595 {&amdfam10_cost, 32, 24, 32, 7, 32},
2596 {&bdver1_cost, 32, 24, 32, 7, 32},
2597 {&bdver2_cost, 32, 24, 32, 7, 32},
2598 {&btver1_cost, 32, 24, 32, 7, 32},
2599 {&atom_cost, 16, 15, 16, 7, 16}
2602 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2632 /* Return true if a red-zone is in use. */
2635 ix86_using_red_zone (void)
2637 return TARGET_RED_ZONE && !TARGET_64BIT_MS_ABI;
2640 /* Return a string that documents the current -m options. The caller is
2641 responsible for freeing the string. */
2644 ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
2645 const char *tune, enum fpmath_unit fpmath,
2648 struct ix86_target_opts
2650 const char *option; /* option string */
2651 HOST_WIDE_INT mask; /* isa mask options */
2654 /* This table is ordered so that options like -msse4.2 that imply
2655 preceding options while match those first. */
2656 static struct ix86_target_opts isa_opts[] =
2658 { "-m64", OPTION_MASK_ISA_64BIT },
2659 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2660 { "-mfma", OPTION_MASK_ISA_FMA },
2661 { "-mxop", OPTION_MASK_ISA_XOP },
2662 { "-mlwp", OPTION_MASK_ISA_LWP },
2663 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2664 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2665 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2666 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2667 { "-msse3", OPTION_MASK_ISA_SSE3 },
2668 { "-msse2", OPTION_MASK_ISA_SSE2 },
2669 { "-msse", OPTION_MASK_ISA_SSE },
2670 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2671 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2672 { "-mmmx", OPTION_MASK_ISA_MMX },
2673 { "-mabm", OPTION_MASK_ISA_ABM },
2674 { "-mbmi", OPTION_MASK_ISA_BMI },
2675 { "-mbmi2", OPTION_MASK_ISA_BMI2 },
2676 { "-mlzcnt", OPTION_MASK_ISA_LZCNT },
2677 { "-mtbm", OPTION_MASK_ISA_TBM },
2678 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2679 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2680 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2681 { "-maes", OPTION_MASK_ISA_AES },
2682 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2683 { "-mfsgsbase", OPTION_MASK_ISA_FSGSBASE },
2684 { "-mrdrnd", OPTION_MASK_ISA_RDRND },
2685 { "-mf16c", OPTION_MASK_ISA_F16C },
2689 static struct ix86_target_opts flag_opts[] =
2691 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2692 { "-m80387", MASK_80387 },
2693 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2694 { "-malign-double", MASK_ALIGN_DOUBLE },
2695 { "-mcld", MASK_CLD },
2696 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2697 { "-mieee-fp", MASK_IEEE_FP },
2698 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2699 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2700 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2701 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2702 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2703 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2704 { "-mno-red-zone", MASK_NO_RED_ZONE },
2705 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2706 { "-mrecip", MASK_RECIP },
2707 { "-mrtd", MASK_RTD },
2708 { "-msseregparm", MASK_SSEREGPARM },
2709 { "-mstack-arg-probe", MASK_STACK_PROBE },
2710 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2711 { "-mvect8-ret-in-mem", MASK_VECT8_RETURNS },
2712 { "-m8bit-idiv", MASK_USE_8BIT_IDIV },
2713 { "-mvzeroupper", MASK_VZEROUPPER },
2714 { "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD},
2715 { "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE},
2716 { "-mprefer-avx128", MASK_PREFER_AVX128},
2719 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2722 char target_other[40];
2731 memset (opts, '\0', sizeof (opts));
2733 /* Add -march= option. */
2736 opts[num][0] = "-march=";
2737 opts[num++][1] = arch;
2740 /* Add -mtune= option. */
2743 opts[num][0] = "-mtune=";
2744 opts[num++][1] = tune;
2747 /* Pick out the options in isa options. */
2748 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2750 if ((isa & isa_opts[i].mask) != 0)
2752 opts[num++][0] = isa_opts[i].option;
2753 isa &= ~ isa_opts[i].mask;
2757 if (isa && add_nl_p)
2759 opts[num++][0] = isa_other;
2760 sprintf (isa_other, "(other isa: %#" HOST_WIDE_INT_PRINT "x)",
2764 /* Add flag options. */
2765 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2767 if ((flags & flag_opts[i].mask) != 0)
2769 opts[num++][0] = flag_opts[i].option;
2770 flags &= ~ flag_opts[i].mask;
2774 if (flags && add_nl_p)
2776 opts[num++][0] = target_other;
2777 sprintf (target_other, "(other flags: %#x)", flags);
2780 /* Add -fpmath= option. */
2783 opts[num][0] = "-mfpmath=";
2784 switch ((int) fpmath)
2787 opts[num++][1] = "387";
2791 opts[num++][1] = "sse";
2794 case FPMATH_387 | FPMATH_SSE:
2795 opts[num++][1] = "sse+387";
2807 gcc_assert (num < ARRAY_SIZE (opts));
2809 /* Size the string. */
2811 sep_len = (add_nl_p) ? 3 : 1;
2812 for (i = 0; i < num; i++)
2815 for (j = 0; j < 2; j++)
2817 len += strlen (opts[i][j]);
2820 /* Build the string. */
2821 ret = ptr = (char *) xmalloc (len);
2824 for (i = 0; i < num; i++)
2828 for (j = 0; j < 2; j++)
2829 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2836 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2844 for (j = 0; j < 2; j++)
2847 memcpy (ptr, opts[i][j], len2[j]);
2849 line_len += len2[j];
2854 gcc_assert (ret + len >= ptr);
2859 /* Return true, if profiling code should be emitted before
2860 prologue. Otherwise it returns false.
2861 Note: For x86 with "hotfix" it is sorried. */
2863 ix86_profile_before_prologue (void)
2865 return flag_fentry != 0;
2868 /* Function that is callable from the debugger to print the current
2871 ix86_debug_options (void)
2873 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2874 ix86_arch_string, ix86_tune_string,
2879 fprintf (stderr, "%s\n\n", opts);
2883 fputs ("<no options>\n\n", stderr);
2888 /* Override various settings based on options. If MAIN_ARGS_P, the
2889 options are from the command line, otherwise they are from
2893 ix86_option_override_internal (bool main_args_p)
2896 unsigned int ix86_arch_mask, ix86_tune_mask;
2897 const bool ix86_tune_specified = (ix86_tune_string != NULL);
2902 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2903 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2904 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2905 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2906 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2907 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2908 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2909 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2910 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2911 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2912 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2913 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2914 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2915 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2916 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2917 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2918 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2919 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2920 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2921 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2922 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2923 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2924 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2925 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2926 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2927 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2928 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2929 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2930 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2931 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2932 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2933 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2934 /* if this reaches 64, need to widen struct pta flags below */
2938 const char *const name; /* processor name or nickname. */
2939 const enum processor_type processor;
2940 const enum attr_cpu schedule;
2941 const unsigned HOST_WIDE_INT flags;
2943 const processor_alias_table[] =
2945 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2946 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2947 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2948 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2949 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2950 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2951 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2952 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2953 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2954 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2955 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2956 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2957 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2959 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2961 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2962 PTA_MMX | PTA_SSE | PTA_SSE2},
2963 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2964 PTA_MMX |PTA_SSE | PTA_SSE2},
2965 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2966 PTA_MMX | PTA_SSE | PTA_SSE2},
2967 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2968 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2969 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2970 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2971 | PTA_CX16 | PTA_NO_SAHF},
2972 {"core2", PROCESSOR_CORE2_64, CPU_CORE2,
2973 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2974 | PTA_SSSE3 | PTA_CX16},
2975 {"corei7", PROCESSOR_COREI7_64, CPU_COREI7,
2976 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2977 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16},
2978 {"corei7-avx", PROCESSOR_COREI7_64, CPU_COREI7,
2979 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2980 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
2981 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL},
2982 {"core-avx-i", PROCESSOR_COREI7_64, CPU_COREI7,
2983 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2984 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
2985 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
2986 | PTA_RDRND | PTA_F16C},
2987 {"core-avx2", PROCESSOR_COREI7_64, CPU_COREI7,
2988 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2989 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
2990 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
2991 | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
2992 | PTA_FMA | PTA_MOVBE},
2993 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2994 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2995 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2996 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2997 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2998 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2999 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
3000 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
3001 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
3002 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
3003 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
3004 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
3005 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
3006 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
3007 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
3008 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
3009 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
3010 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
3011 {"x86-64", PROCESSOR_K8, CPU_K8,
3012 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
3013 {"k8", PROCESSOR_K8, CPU_K8,
3014 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3015 | PTA_SSE2 | PTA_NO_SAHF},
3016 {"k8-sse3", PROCESSOR_K8, CPU_K8,
3017 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3018 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
3019 {"opteron", PROCESSOR_K8, CPU_K8,
3020 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3021 | PTA_SSE2 | PTA_NO_SAHF},
3022 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
3023 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3024 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
3025 {"athlon64", PROCESSOR_K8, CPU_K8,
3026 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3027 | PTA_SSE2 | PTA_NO_SAHF},
3028 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
3029 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3030 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
3031 {"athlon-fx", PROCESSOR_K8, CPU_K8,
3032 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3033 | PTA_SSE2 | PTA_NO_SAHF},
3034 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
3035 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3036 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
3037 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
3038 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
3039 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
3040 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
3041 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
3042 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
3043 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
3044 | PTA_XOP | PTA_LWP},
3045 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
3046 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
3047 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
3048 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
3049 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
3051 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
3052 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
3053 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16},
3054 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
3055 0 /* flags are only used for -march switch. */ },
3056 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
3057 PTA_64BIT /* flags are only used for -march switch. */ },
3060 /* -mrecip options. */
3063 const char *string; /* option name */
3064 unsigned int mask; /* mask bits to set */
3066 const recip_options[] =
3068 { "all", RECIP_MASK_ALL },
3069 { "none", RECIP_MASK_NONE },
3070 { "div", RECIP_MASK_DIV },
3071 { "sqrt", RECIP_MASK_SQRT },
3072 { "vec-div", RECIP_MASK_VEC_DIV },
3073 { "vec-sqrt", RECIP_MASK_VEC_SQRT },
3076 int const pta_size = ARRAY_SIZE (processor_alias_table);
3078 /* Set up prefix/suffix so the error messages refer to either the command
3079 line argument, or the attribute(target). */
3088 prefix = "option(\"";
3093 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3094 SUBTARGET_OVERRIDE_OPTIONS;
3097 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3098 SUBSUBTARGET_OVERRIDE_OPTIONS;
3102 ix86_isa_flags |= OPTION_MASK_ISA_64BIT;
3104 /* -fPIC is the default for x86_64. */
3105 if (TARGET_MACHO && TARGET_64BIT)
3108 /* Need to check -mtune=generic first. */
3109 if (ix86_tune_string)
3111 if (!strcmp (ix86_tune_string, "generic")
3112 || !strcmp (ix86_tune_string, "i686")
3113 /* As special support for cross compilers we read -mtune=native
3114 as -mtune=generic. With native compilers we won't see the
3115 -mtune=native, as it was changed by the driver. */
3116 || !strcmp (ix86_tune_string, "native"))
3119 ix86_tune_string = "generic64";
3121 ix86_tune_string = "generic32";
3123 /* If this call is for setting the option attribute, allow the
3124 generic32/generic64 that was previously set. */
3125 else if (!main_args_p
3126 && (!strcmp (ix86_tune_string, "generic32")
3127 || !strcmp (ix86_tune_string, "generic64")))
3129 else if (!strncmp (ix86_tune_string, "generic", 7))
3130 error ("bad value (%s) for %stune=%s %s",
3131 ix86_tune_string, prefix, suffix, sw);
3132 else if (!strcmp (ix86_tune_string, "x86-64"))
3133 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated; use "
3134 "%stune=k8%s or %stune=generic%s instead as appropriate",
3135 prefix, suffix, prefix, suffix, prefix, suffix);
3139 if (ix86_arch_string)
3140 ix86_tune_string = ix86_arch_string;
3141 if (!ix86_tune_string)
3143 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
3144 ix86_tune_defaulted = 1;
3147 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3148 need to use a sensible tune option. */
3149 if (!strcmp (ix86_tune_string, "generic")
3150 || !strcmp (ix86_tune_string, "x86-64")
3151 || !strcmp (ix86_tune_string, "i686"))
3154 ix86_tune_string = "generic64";
3156 ix86_tune_string = "generic32";
3160 if (ix86_stringop_alg == rep_prefix_8_byte && !TARGET_64BIT)
3162 /* rep; movq isn't available in 32-bit code. */
3163 error ("-mstringop-strategy=rep_8byte not supported for 32-bit code");
3164 ix86_stringop_alg = no_stringop;
3167 if (!ix86_arch_string)
3168 ix86_arch_string = TARGET_64BIT ? "x86-64" : SUBTARGET32_DEFAULT_CPU;
3170 ix86_arch_specified = 1;
3172 if (!global_options_set.x_ix86_abi)
3173 ix86_abi = DEFAULT_ABI;
3175 if (global_options_set.x_ix86_cmodel)
3177 switch (ix86_cmodel)
3182 ix86_cmodel = CM_SMALL_PIC;
3184 error ("code model %qs not supported in the %s bit mode",
3191 ix86_cmodel = CM_MEDIUM_PIC;
3193 error ("code model %qs not supported in the %s bit mode",
3195 else if (TARGET_X32)
3196 error ("code model %qs not supported in x32 mode",
3203 ix86_cmodel = CM_LARGE_PIC;
3205 error ("code model %qs not supported in the %s bit mode",
3207 else if (TARGET_X32)
3208 error ("code model %qs not supported in x32 mode",
3214 error ("code model %s does not support PIC mode", "32");
3216 error ("code model %qs not supported in the %s bit mode",
3223 error ("code model %s does not support PIC mode", "kernel");
3224 ix86_cmodel = CM_32;
3227 error ("code model %qs not supported in the %s bit mode",
3237 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3238 use of rip-relative addressing. This eliminates fixups that
3239 would otherwise be needed if this object is to be placed in a
3240 DLL, and is essentially just as efficient as direct addressing. */
3241 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
3242 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
3243 else if (TARGET_64BIT)
3244 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
3246 ix86_cmodel = CM_32;
3248 if (TARGET_MACHO && ix86_asm_dialect == ASM_INTEL)
3250 error ("-masm=intel not supported in this configuration");
3251 ix86_asm_dialect = ASM_ATT;
3253 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
3254 sorry ("%i-bit mode not compiled in",
3255 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
3257 for (i = 0; i < pta_size; i++)
3258 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
3260 ix86_schedule = processor_alias_table[i].schedule;
3261 ix86_arch = processor_alias_table[i].processor;
3262 /* Default cpu tuning to the architecture. */
3263 ix86_tune = ix86_arch;
3265 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3266 error ("CPU you selected does not support x86-64 "
3269 if (processor_alias_table[i].flags & PTA_MMX
3270 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
3271 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
3272 if (processor_alias_table[i].flags & PTA_3DNOW
3273 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
3274 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
3275 if (processor_alias_table[i].flags & PTA_3DNOW_A
3276 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
3277 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
3278 if (processor_alias_table[i].flags & PTA_SSE
3279 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
3280 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
3281 if (processor_alias_table[i].flags & PTA_SSE2
3282 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
3283 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
3284 if (processor_alias_table[i].flags & PTA_SSE3
3285 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
3286 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
3287 if (processor_alias_table[i].flags & PTA_SSSE3
3288 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
3289 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
3290 if (processor_alias_table[i].flags & PTA_SSE4_1
3291 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
3292 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
3293 if (processor_alias_table[i].flags & PTA_SSE4_2
3294 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
3295 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
3296 if (processor_alias_table[i].flags & PTA_AVX
3297 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
3298 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
3299 if (processor_alias_table[i].flags & PTA_AVX2
3300 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
3301 ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
3302 if (processor_alias_table[i].flags & PTA_FMA
3303 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
3304 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
3305 if (processor_alias_table[i].flags & PTA_SSE4A
3306 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
3307 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
3308 if (processor_alias_table[i].flags & PTA_FMA4
3309 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
3310 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
3311 if (processor_alias_table[i].flags & PTA_XOP
3312 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
3313 ix86_isa_flags |= OPTION_MASK_ISA_XOP;
3314 if (processor_alias_table[i].flags & PTA_LWP
3315 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
3316 ix86_isa_flags |= OPTION_MASK_ISA_LWP;
3317 if (processor_alias_table[i].flags & PTA_ABM
3318 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
3319 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
3320 if (processor_alias_table[i].flags & PTA_BMI
3321 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
3322 ix86_isa_flags |= OPTION_MASK_ISA_BMI;
3323 if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
3324 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
3325 ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
3326 if (processor_alias_table[i].flags & PTA_TBM
3327 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
3328 ix86_isa_flags |= OPTION_MASK_ISA_TBM;
3329 if (processor_alias_table[i].flags & PTA_BMI2
3330 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
3331 ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
3332 if (processor_alias_table[i].flags & PTA_CX16
3333 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
3334 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
3335 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
3336 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
3337 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
3338 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
3339 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
3340 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
3341 if (processor_alias_table[i].flags & PTA_MOVBE
3342 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
3343 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
3344 if (processor_alias_table[i].flags & PTA_AES
3345 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
3346 ix86_isa_flags |= OPTION_MASK_ISA_AES;
3347 if (processor_alias_table[i].flags & PTA_PCLMUL
3348 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
3349 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
3350 if (processor_alias_table[i].flags & PTA_FSGSBASE
3351 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
3352 ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
3353 if (processor_alias_table[i].flags & PTA_RDRND
3354 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
3355 ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
3356 if (processor_alias_table[i].flags & PTA_F16C
3357 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
3358 ix86_isa_flags |= OPTION_MASK_ISA_F16C;
3359 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
3360 x86_prefetch_sse = true;
3365 if (!strcmp (ix86_arch_string, "generic"))
3366 error ("generic CPU can be used only for %stune=%s %s",
3367 prefix, suffix, sw);
3368 else if (!strncmp (ix86_arch_string, "generic", 7) || i == pta_size)
3369 error ("bad value (%s) for %sarch=%s %s",
3370 ix86_arch_string, prefix, suffix, sw);
3372 ix86_arch_mask = 1u << ix86_arch;
3373 for (i = 0; i < X86_ARCH_LAST; ++i)
3374 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3376 for (i = 0; i < pta_size; i++)
3377 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3379 ix86_schedule = processor_alias_table[i].schedule;
3380 ix86_tune = processor_alias_table[i].processor;
3383 if (!(processor_alias_table[i].flags & PTA_64BIT))
3385 if (ix86_tune_defaulted)
3387 ix86_tune_string = "x86-64";
3388 for (i = 0; i < pta_size; i++)
3389 if (! strcmp (ix86_tune_string,
3390 processor_alias_table[i].name))
3392 ix86_schedule = processor_alias_table[i].schedule;
3393 ix86_tune = processor_alias_table[i].processor;
3396 error ("CPU you selected does not support x86-64 "
3402 /* Adjust tuning when compiling for 32-bit ABI. */
3405 case PROCESSOR_GENERIC64:
3406 ix86_tune = PROCESSOR_GENERIC32;
3407 ix86_schedule = CPU_PENTIUMPRO;
3410 case PROCESSOR_CORE2_64:
3411 ix86_tune = PROCESSOR_CORE2_32;
3414 case PROCESSOR_COREI7_64:
3415 ix86_tune = PROCESSOR_COREI7_32;
3422 /* Intel CPUs have always interpreted SSE prefetch instructions as
3423 NOPs; so, we can enable SSE prefetch instructions even when
3424 -mtune (rather than -march) points us to a processor that has them.
3425 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3426 higher processors. */
3428 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3429 x86_prefetch_sse = true;
3433 if (ix86_tune_specified && i == pta_size)
3434 error ("bad value (%s) for %stune=%s %s",
3435 ix86_tune_string, prefix, suffix, sw);
3437 ix86_tune_mask = 1u << ix86_tune;
3438 for (i = 0; i < X86_TUNE_LAST; ++i)
3439 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3441 #ifndef USE_IX86_FRAME_POINTER
3442 #define USE_IX86_FRAME_POINTER 0
3445 #ifndef USE_X86_64_FRAME_POINTER
3446 #define USE_X86_64_FRAME_POINTER 0
3449 /* Set the default values for switches whose default depends on TARGET_64BIT
3450 in case they weren't overwritten by command line options. */
3453 if (optimize >= 1 && !global_options_set.x_flag_omit_frame_pointer)
3454 flag_omit_frame_pointer = !USE_X86_64_FRAME_POINTER;
3455 if (flag_asynchronous_unwind_tables == 2)
3456 flag_unwind_tables = flag_asynchronous_unwind_tables = 1;
3457 if (flag_pcc_struct_return == 2)
3458 flag_pcc_struct_return = 0;
3462 if (optimize >= 1 && !global_options_set.x_flag_omit_frame_pointer)
3463 flag_omit_frame_pointer = !(USE_IX86_FRAME_POINTER || optimize_size);
3464 if (flag_asynchronous_unwind_tables == 2)
3465 flag_asynchronous_unwind_tables = !USE_IX86_FRAME_POINTER;
3466 if (flag_pcc_struct_return == 2)
3467 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
3471 ix86_cost = &ix86_size_cost;
3473 ix86_cost = processor_target_table[ix86_tune].cost;
3475 /* Arrange to set up i386_stack_locals for all functions. */
3476 init_machine_status = ix86_init_machine_status;
3478 /* Validate -mregparm= value. */
3479 if (global_options_set.x_ix86_regparm)
3482 warning (0, "-mregparm is ignored in 64-bit mode");
3483 if (ix86_regparm > REGPARM_MAX)
3485 error ("-mregparm=%d is not between 0 and %d",
3486 ix86_regparm, REGPARM_MAX);
3491 ix86_regparm = REGPARM_MAX;
3493 /* Default align_* from the processor table. */
3494 if (align_loops == 0)
3496 align_loops = processor_target_table[ix86_tune].align_loop;
3497 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3499 if (align_jumps == 0)
3501 align_jumps = processor_target_table[ix86_tune].align_jump;
3502 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3504 if (align_functions == 0)
3506 align_functions = processor_target_table[ix86_tune].align_func;
3509 /* Provide default for -mbranch-cost= value. */
3510 if (!global_options_set.x_ix86_branch_cost)
3511 ix86_branch_cost = ix86_cost->branch_cost;
3515 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3517 /* Enable by default the SSE and MMX builtins. Do allow the user to
3518 explicitly disable any of these. In particular, disabling SSE and
3519 MMX for kernel code is extremely useful. */
3520 if (!ix86_arch_specified)
3522 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3523 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3526 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3530 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3532 if (!ix86_arch_specified)
3534 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3536 /* i386 ABI does not specify red zone. It still makes sense to use it
3537 when programmer takes care to stack from being destroyed. */
3538 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3539 target_flags |= MASK_NO_RED_ZONE;
3542 /* Keep nonleaf frame pointers. */
3543 if (flag_omit_frame_pointer)
3544 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3545 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3546 flag_omit_frame_pointer = 1;
3548 /* If we're doing fast math, we don't care about comparison order
3549 wrt NaNs. This lets us use a shorter comparison sequence. */
3550 if (flag_finite_math_only)
3551 target_flags &= ~MASK_IEEE_FP;
3553 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3554 since the insns won't need emulation. */
3555 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3556 target_flags &= ~MASK_NO_FANCY_MATH_387;
3558 /* Likewise, if the target doesn't have a 387, or we've specified
3559 software floating point, don't use 387 inline intrinsics. */
3561 target_flags |= MASK_NO_FANCY_MATH_387;
3563 /* Turn on MMX builtins for -msse. */
3566 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3567 x86_prefetch_sse = true;
3570 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3571 if (TARGET_SSE4_2 || TARGET_ABM)
3572 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3574 /* Turn on lzcnt instruction for -mabm. */
3576 ix86_isa_flags |= OPTION_MASK_ISA_LZCNT & ~ix86_isa_flags_explicit;
3578 /* Validate -mpreferred-stack-boundary= value or default it to
3579 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3580 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3581 if (global_options_set.x_ix86_preferred_stack_boundary_arg)
3583 int min = (TARGET_64BIT ? 4 : 2);
3584 int max = (TARGET_SEH ? 4 : 12);
3586 if (ix86_preferred_stack_boundary_arg < min
3587 || ix86_preferred_stack_boundary_arg > max)
3590 error ("-mpreferred-stack-boundary is not supported "
3593 error ("-mpreferred-stack-boundary=%d is not between %d and %d",
3594 ix86_preferred_stack_boundary_arg, min, max);
3597 ix86_preferred_stack_boundary
3598 = (1 << ix86_preferred_stack_boundary_arg) * BITS_PER_UNIT;
3601 /* Set the default value for -mstackrealign. */
3602 if (ix86_force_align_arg_pointer == -1)
3603 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3605 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3607 /* Validate -mincoming-stack-boundary= value or default it to
3608 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3609 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3610 if (global_options_set.x_ix86_incoming_stack_boundary_arg)
3612 if (ix86_incoming_stack_boundary_arg < (TARGET_64BIT ? 4 : 2)
3613 || ix86_incoming_stack_boundary_arg > 12)
3614 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3615 ix86_incoming_stack_boundary_arg, TARGET_64BIT ? 4 : 2);
3618 ix86_user_incoming_stack_boundary
3619 = (1 << ix86_incoming_stack_boundary_arg) * BITS_PER_UNIT;
3620 ix86_incoming_stack_boundary
3621 = ix86_user_incoming_stack_boundary;
3625 /* Accept -msseregparm only if at least SSE support is enabled. */
3626 if (TARGET_SSEREGPARM
3628 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3630 if (global_options_set.x_ix86_fpmath)
3632 if (ix86_fpmath & FPMATH_SSE)
3636 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3637 ix86_fpmath = FPMATH_387;
3639 else if ((ix86_fpmath & FPMATH_387) && !TARGET_80387)
3641 warning (0, "387 instruction set disabled, using SSE arithmetics");
3642 ix86_fpmath = FPMATH_SSE;
3647 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3649 /* If the i387 is disabled, then do not return values in it. */
3651 target_flags &= ~MASK_FLOAT_RETURNS;
3653 /* Use external vectorized library in vectorizing intrinsics. */
3654 if (global_options_set.x_ix86_veclibabi_type)
3655 switch (ix86_veclibabi_type)
3657 case ix86_veclibabi_type_svml:
3658 ix86_veclib_handler = ix86_veclibabi_svml;
3661 case ix86_veclibabi_type_acml:
3662 ix86_veclib_handler = ix86_veclibabi_acml;
3669 if ((!USE_IX86_FRAME_POINTER
3670 || (x86_accumulate_outgoing_args & ix86_tune_mask))
3671 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3673 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3675 /* ??? Unwind info is not correct around the CFG unless either a frame
3676 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3677 unwind info generation to be aware of the CFG and propagating states
3679 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3680 || flag_exceptions || flag_non_call_exceptions)
3681 && flag_omit_frame_pointer
3682 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3684 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3685 warning (0, "unwind tables currently require either a frame pointer "
3686 "or %saccumulate-outgoing-args%s for correctness",
3688 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3691 /* If stack probes are required, the space used for large function
3692 arguments on the stack must also be probed, so enable
3693 -maccumulate-outgoing-args so this happens in the prologue. */
3694 if (TARGET_STACK_PROBE
3695 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3697 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3698 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3699 "for correctness", prefix, suffix);
3700 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3703 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3706 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3707 p = strchr (internal_label_prefix, 'X');
3708 internal_label_prefix_len = p - internal_label_prefix;
3712 /* When scheduling description is not available, disable scheduler pass
3713 so it won't slow down the compilation and make x87 code slower. */
3714 if (!TARGET_SCHEDULE)
3715 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3717 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3718 ix86_cost->simultaneous_prefetches,
3719 global_options.x_param_values,
3720 global_options_set.x_param_values);
3721 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, ix86_cost->prefetch_block,
3722 global_options.x_param_values,
3723 global_options_set.x_param_values);
3724 maybe_set_param_value (PARAM_L1_CACHE_SIZE, ix86_cost->l1_cache_size,
3725 global_options.x_param_values,
3726 global_options_set.x_param_values);
3727 maybe_set_param_value (PARAM_L2_CACHE_SIZE, ix86_cost->l2_cache_size,
3728 global_options.x_param_values,
3729 global_options_set.x_param_values);
3731 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3732 if (flag_prefetch_loop_arrays < 0
3735 && TARGET_SOFTWARE_PREFETCHING_BENEFICIAL)
3736 flag_prefetch_loop_arrays = 1;
3738 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3739 can be optimized to ap = __builtin_next_arg (0). */
3740 if (!TARGET_64BIT && !flag_split_stack)
3741 targetm.expand_builtin_va_start = NULL;
3745 ix86_gen_leave = gen_leave_rex64;
3746 ix86_gen_add3 = gen_adddi3;
3747 ix86_gen_sub3 = gen_subdi3;
3748 ix86_gen_sub3_carry = gen_subdi3_carry;
3749 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3750 ix86_gen_monitor = gen_sse3_monitor64;
3751 ix86_gen_andsp = gen_anddi3;
3752 ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_di;
3753 ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probedi;
3754 ix86_gen_probe_stack_range = gen_probe_stack_rangedi;
3758 ix86_gen_leave = gen_leave;
3759 ix86_gen_add3 = gen_addsi3;
3760 ix86_gen_sub3 = gen_subsi3;
3761 ix86_gen_sub3_carry = gen_subsi3_carry;
3762 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3763 ix86_gen_monitor = gen_sse3_monitor;
3764 ix86_gen_andsp = gen_andsi3;
3765 ix86_gen_allocate_stack_worker = gen_allocate_stack_worker_probe_si;
3766 ix86_gen_adjust_stack_and_probe = gen_adjust_stack_and_probesi;
3767 ix86_gen_probe_stack_range = gen_probe_stack_rangesi;
3771 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3773 target_flags |= MASK_CLD & ~target_flags_explicit;
3776 if (!TARGET_64BIT && flag_pic)
3778 if (flag_fentry > 0)
3779 sorry ("-mfentry isn%'t supported for 32-bit in combination "
3783 else if (TARGET_SEH)
3785 if (flag_fentry == 0)
3786 sorry ("-mno-fentry isn%'t compatible with SEH");
3789 else if (flag_fentry < 0)
3791 #if defined(PROFILE_BEFORE_PROLOGUE)
3800 /* When not optimize for size, enable vzeroupper optimization for
3801 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3802 AVX unaligned load/store. */
3805 if (flag_expensive_optimizations
3806 && !(target_flags_explicit & MASK_VZEROUPPER))
3807 target_flags |= MASK_VZEROUPPER;
3808 if ((x86_avx256_split_unaligned_load & ix86_tune_mask)
3809 && !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
3810 target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
3811 if ((x86_avx256_split_unaligned_store & ix86_tune_mask)
3812 && !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_STORE))
3813 target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
3814 /* Enable 128-bit AVX instruction generation for the auto-vectorizer. */
3815 if (TARGET_AVX128_OPTIMAL && !(target_flags_explicit & MASK_PREFER_AVX128))
3816 target_flags |= MASK_PREFER_AVX128;
3821 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3822 target_flags &= ~MASK_VZEROUPPER;
3825 if (ix86_recip_name)
3827 char *p = ASTRDUP (ix86_recip_name);
3829 unsigned int mask, i;
3832 while ((q = strtok (p, ",")) != NULL)
3843 if (!strcmp (q, "default"))
3844 mask = RECIP_MASK_ALL;
3847 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3848 if (!strcmp (q, recip_options[i].string))
3850 mask = recip_options[i].mask;
3854 if (i == ARRAY_SIZE (recip_options))
3856 error ("unknown option for -mrecip=%s", q);
3858 mask = RECIP_MASK_NONE;
3862 recip_mask_explicit |= mask;
3864 recip_mask &= ~mask;
3871 recip_mask |= RECIP_MASK_ALL & ~recip_mask_explicit;
3872 else if (target_flags_explicit & MASK_RECIP)
3873 recip_mask &= ~(RECIP_MASK_ALL & ~recip_mask_explicit);
3875 /* Save the initial options in case the user does function specific
3878 target_option_default_node = target_option_current_node
3879 = build_target_option_node ();
3882 /* Return TRUE if VAL is passed in register with 256bit AVX modes. */
3885 function_pass_avx256_p (const_rtx val)
3890 if (REG_P (val) && VALID_AVX256_REG_MODE (GET_MODE (val)))
3893 if (GET_CODE (val) == PARALLEL)
3898 for (i = XVECLEN (val, 0) - 1; i >= 0; i--)
3900 r = XVECEXP (val, 0, i);
3901 if (GET_CODE (r) == EXPR_LIST
3903 && REG_P (XEXP (r, 0))
3904 && (GET_MODE (XEXP (r, 0)) == OImode
3905 || VALID_AVX256_REG_MODE (GET_MODE (XEXP (r, 0)))))
3913 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3916 ix86_option_override (void)
3918 ix86_option_override_internal (true);
3921 /* Update register usage after having seen the compiler flags. */
3924 ix86_conditional_register_usage (void)
3929 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3931 if (fixed_regs[i] > 1)
3932 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3933 if (call_used_regs[i] > 1)
3934 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3937 /* The PIC register, if it exists, is fixed. */
3938 j = PIC_OFFSET_TABLE_REGNUM;
3939 if (j != INVALID_REGNUM)
3940 fixed_regs[j] = call_used_regs[j] = 1;
3942 /* The 64-bit MS_ABI changes the set of call-used registers. */
3943 if (TARGET_64BIT_MS_ABI)
3945 call_used_regs[SI_REG] = 0;
3946 call_used_regs[DI_REG] = 0;
3947 call_used_regs[XMM6_REG] = 0;
3948 call_used_regs[XMM7_REG] = 0;
3949 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3950 call_used_regs[i] = 0;
3953 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3954 other call-clobbered regs for 64-bit. */
3957 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3959 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3960 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3961 && call_used_regs[i])
3962 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3965 /* If MMX is disabled, squash the registers. */
3967 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3968 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3969 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3971 /* If SSE is disabled, squash the registers. */
3973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3974 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3975 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3977 /* If the FPU is disabled, squash the registers. */
3978 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3979 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3980 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3981 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3983 /* If 32-bit, squash the 64-bit registers. */
3986 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3988 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3994 /* Save the current options */
3997 ix86_function_specific_save (struct cl_target_option *ptr)
3999 ptr->arch = ix86_arch;
4000 ptr->schedule = ix86_schedule;
4001 ptr->tune = ix86_tune;
4002 ptr->branch_cost = ix86_branch_cost;
4003 ptr->tune_defaulted = ix86_tune_defaulted;
4004 ptr->arch_specified = ix86_arch_specified;
4005 ptr->x_ix86_isa_flags_explicit = ix86_isa_flags_explicit;
4006 ptr->ix86_target_flags_explicit = target_flags_explicit;
4007 ptr->x_recip_mask_explicit = recip_mask_explicit;
4009 /* The fields are char but the variables are not; make sure the
4010 values fit in the fields. */
4011 gcc_assert (ptr->arch == ix86_arch);
4012 gcc_assert (ptr->schedule == ix86_schedule);
4013 gcc_assert (ptr->tune == ix86_tune);
4014 gcc_assert (ptr->branch_cost == ix86_branch_cost);
4017 /* Restore the current options */
4020 ix86_function_specific_restore (struct cl_target_option *ptr)
4022 enum processor_type old_tune = ix86_tune;
4023 enum processor_type old_arch = ix86_arch;
4024 unsigned int ix86_arch_mask, ix86_tune_mask;
4027 ix86_arch = (enum processor_type) ptr->arch;
4028 ix86_schedule = (enum attr_cpu) ptr->schedule;
4029 ix86_tune = (enum processor_type) ptr->tune;
4030 ix86_branch_cost = ptr->branch_cost;
4031 ix86_tune_defaulted = ptr->tune_defaulted;
4032 ix86_arch_specified = ptr->arch_specified;
4033 ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
4034 target_flags_explicit = ptr->ix86_target_flags_explicit;
4035 recip_mask_explicit = ptr->x_recip_mask_explicit;
4037 /* Recreate the arch feature tests if the arch changed */
4038 if (old_arch != ix86_arch)
4040 ix86_arch_mask = 1u << ix86_arch;
4041 for (i = 0; i < X86_ARCH_LAST; ++i)
4042 ix86_arch_features[i]
4043 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
4046 /* Recreate the tune optimization tests */
4047 if (old_tune != ix86_tune)
4049 ix86_tune_mask = 1u << ix86_tune;
4050 for (i = 0; i < X86_TUNE_LAST; ++i)
4051 ix86_tune_features[i]
4052 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
4056 /* Print the current options */
4059 ix86_function_specific_print (FILE *file, int indent,
4060 struct cl_target_option *ptr)
4063 = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags,
4064 NULL, NULL, ptr->x_ix86_fpmath, false);
4066 fprintf (file, "%*sarch = %d (%s)\n",
4069 ((ptr->arch < TARGET_CPU_DEFAULT_max)
4070 ? cpu_names[ptr->arch]
4073 fprintf (file, "%*stune = %d (%s)\n",
4076 ((ptr->tune < TARGET_CPU_DEFAULT_max)
4077 ? cpu_names[ptr->tune]
4080 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
4084 fprintf (file, "%*s%s\n", indent, "", target_string);
4085 free (target_string);
4090 /* Inner function to process the attribute((target(...))), take an argument and
4091 set the current options from the argument. If we have a list, recursively go
4095 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
4096 struct gcc_options *enum_opts_set)
4101 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4102 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4103 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4104 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4105 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4121 enum ix86_opt_type type;
4126 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
4127 IX86_ATTR_ISA ("abm", OPT_mabm),
4128 IX86_ATTR_ISA ("bmi", OPT_mbmi),
4129 IX86_ATTR_ISA ("bmi2", OPT_mbmi2),
4130 IX86_ATTR_ISA ("lzcnt", OPT_mlzcnt),
4131 IX86_ATTR_ISA ("tbm", OPT_mtbm),
4132 IX86_ATTR_ISA ("aes", OPT_maes),
4133 IX86_ATTR_ISA ("avx", OPT_mavx),
4134 IX86_ATTR_ISA ("avx2", OPT_mavx2),
4135 IX86_ATTR_ISA ("mmx", OPT_mmmx),
4136 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
4137 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
4138 IX86_ATTR_ISA ("sse", OPT_msse),
4139 IX86_ATTR_ISA ("sse2", OPT_msse2),
4140 IX86_ATTR_ISA ("sse3", OPT_msse3),
4141 IX86_ATTR_ISA ("sse4", OPT_msse4),
4142 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
4143 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
4144 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
4145 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
4146 IX86_ATTR_ISA ("fma4", OPT_mfma4),
4147 IX86_ATTR_ISA ("fma", OPT_mfma),
4148 IX86_ATTR_ISA ("xop", OPT_mxop),
4149 IX86_ATTR_ISA ("lwp", OPT_mlwp),
4150 IX86_ATTR_ISA ("fsgsbase", OPT_mfsgsbase),
4151 IX86_ATTR_ISA ("rdrnd", OPT_mrdrnd),
4152 IX86_ATTR_ISA ("f16c", OPT_mf16c),
4155 IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
4157 /* string options */
4158 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
4159 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
4162 IX86_ATTR_YES ("cld",
4166 IX86_ATTR_NO ("fancy-math-387",
4167 OPT_mfancy_math_387,
4168 MASK_NO_FANCY_MATH_387),
4170 IX86_ATTR_YES ("ieee-fp",
4174 IX86_ATTR_YES ("inline-all-stringops",
4175 OPT_minline_all_stringops,
4176 MASK_INLINE_ALL_STRINGOPS),
4178 IX86_ATTR_YES ("inline-stringops-dynamically",
4179 OPT_minline_stringops_dynamically,
4180 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4182 IX86_ATTR_NO ("align-stringops",
4183 OPT_mno_align_stringops,
4184 MASK_NO_ALIGN_STRINGOPS),
4186 IX86_ATTR_YES ("recip",
4192 /* If this is a list, recurse to get the options. */
4193 if (TREE_CODE (args) == TREE_LIST)
4197 for (; args; args = TREE_CHAIN (args))
4198 if (TREE_VALUE (args)
4199 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args),
4200 p_strings, enum_opts_set))
4206 else if (TREE_CODE (args) != STRING_CST)
4209 /* Handle multiple arguments separated by commas. */
4210 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
4212 while (next_optstr && *next_optstr != '\0')
4214 char *p = next_optstr;
4216 char *comma = strchr (next_optstr, ',');
4217 const char *opt_string;
4218 size_t len, opt_len;
4223 enum ix86_opt_type type = ix86_opt_unknown;
4229 len = comma - next_optstr;
4230 next_optstr = comma + 1;
4238 /* Recognize no-xxx. */
4239 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
4248 /* Find the option. */
4251 for (i = 0; i < ARRAY_SIZE (attrs); i++)
4253 type = attrs[i].type;
4254 opt_len = attrs[i].len;
4255 if (ch == attrs[i].string[0]
4256 && ((type != ix86_opt_str && type != ix86_opt_enum)
4259 && memcmp (p, attrs[i].string, opt_len) == 0)
4262 mask = attrs[i].mask;
4263 opt_string = attrs[i].string;
4268 /* Process the option. */
4271 error ("attribute(target(\"%s\")) is unknown", orig_p);
4275 else if (type == ix86_opt_isa)
4277 struct cl_decoded_option decoded;
4279 generate_option (opt, NULL, opt_set_p, CL_TARGET, &decoded);
4280 ix86_handle_option (&global_options, &global_options_set,
4281 &decoded, input_location);
4284 else if (type == ix86_opt_yes || type == ix86_opt_no)
4286 if (type == ix86_opt_no)
4287 opt_set_p = !opt_set_p;
4290 target_flags |= mask;
4292 target_flags &= ~mask;
4295 else if (type == ix86_opt_str)
4299 error ("option(\"%s\") was already specified", opt_string);
4303 p_strings[opt] = xstrdup (p + opt_len);
4306 else if (type == ix86_opt_enum)
4311 arg_ok = opt_enum_arg_to_value (opt, p + opt_len, &value, CL_TARGET);
4313 set_option (&global_options, enum_opts_set, opt, value,
4314 p + opt_len, DK_UNSPECIFIED, input_location,
4318 error ("attribute(target(\"%s\")) is unknown", orig_p);
4330 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4333 ix86_valid_target_attribute_tree (tree args)
4335 const char *orig_arch_string = ix86_arch_string;
4336 const char *orig_tune_string = ix86_tune_string;
4337 enum fpmath_unit orig_fpmath_set = global_options_set.x_ix86_fpmath;
4338 int orig_tune_defaulted = ix86_tune_defaulted;
4339 int orig_arch_specified = ix86_arch_specified;
4340 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL };
4343 struct cl_target_option *def
4344 = TREE_TARGET_OPTION (target_option_default_node);
4345 struct gcc_options enum_opts_set;
4347 memset (&enum_opts_set, 0, sizeof (enum_opts_set));
4349 /* Process each of the options on the chain. */
4350 if (! ix86_valid_target_attribute_inner_p (args, option_strings,
4354 /* If the changed options are different from the default, rerun
4355 ix86_option_override_internal, and then save the options away.
4356 The string options are are attribute options, and will be undone
4357 when we copy the save structure. */
4358 if (ix86_isa_flags != def->x_ix86_isa_flags
4359 || target_flags != def->x_target_flags
4360 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
4361 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
4362 || enum_opts_set.x_ix86_fpmath)
4364 /* If we are using the default tune= or arch=, undo the string assigned,
4365 and use the default. */
4366 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
4367 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
4368 else if (!orig_arch_specified)
4369 ix86_arch_string = NULL;
4371 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
4372 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
4373 else if (orig_tune_defaulted)
4374 ix86_tune_string = NULL;
4376 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4377 if (enum_opts_set.x_ix86_fpmath)
4378 global_options_set.x_ix86_fpmath = (enum fpmath_unit) 1;
4379 else if (!TARGET_64BIT && TARGET_SSE)
4381 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
4382 global_options_set.x_ix86_fpmath = (enum fpmath_unit) 1;
4385 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4386 ix86_option_override_internal (false);
4388 /* Add any builtin functions with the new isa if any. */
4389 ix86_add_new_builtins (ix86_isa_flags);
4391 /* Save the current options unless we are validating options for
4393 t = build_target_option_node ();
4395 ix86_arch_string = orig_arch_string;
4396 ix86_tune_string = orig_tune_string;
4397 global_options_set.x_ix86_fpmath = orig_fpmath_set;
4399 /* Free up memory allocated to hold the strings */
4400 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
4401 free (option_strings[i]);
4407 /* Hook to validate attribute((target("string"))). */
4410 ix86_valid_target_attribute_p (tree fndecl,
4411 tree ARG_UNUSED (name),
4413 int ARG_UNUSED (flags))
4415 struct cl_target_option cur_target;
4417 tree old_optimize = build_optimization_node ();
4418 tree new_target, new_optimize;
4419 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
4421 /* If the function changed the optimization levels as well as setting target
4422 options, start with the optimizations specified. */
4423 if (func_optimize && func_optimize != old_optimize)
4424 cl_optimization_restore (&global_options,
4425 TREE_OPTIMIZATION (func_optimize));
4427 /* The target attributes may also change some optimization flags, so update
4428 the optimization options if necessary. */
4429 cl_target_option_save (&cur_target, &global_options);
4430 new_target = ix86_valid_target_attribute_tree (args);
4431 new_optimize = build_optimization_node ();
4438 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
4440 if (old_optimize != new_optimize)
4441 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
4444 cl_target_option_restore (&global_options, &cur_target);
4446 if (old_optimize != new_optimize)
4447 cl_optimization_restore (&global_options,
4448 TREE_OPTIMIZATION (old_optimize));
4454 /* Hook to determine if one function can safely inline another. */
4457 ix86_can_inline_p (tree caller, tree callee)
4460 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
4461 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
4463 /* If callee has no option attributes, then it is ok to inline. */
4467 /* If caller has no option attributes, but callee does then it is not ok to
4469 else if (!caller_tree)
4474 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
4475 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
4477 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4478 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4480 if ((caller_opts->x_ix86_isa_flags & callee_opts->x_ix86_isa_flags)
4481 != callee_opts->x_ix86_isa_flags)
4484 /* See if we have the same non-isa options. */
4485 else if (caller_opts->x_target_flags != callee_opts->x_target_flags)
4488 /* See if arch, tune, etc. are the same. */
4489 else if (caller_opts->arch != callee_opts->arch)
4492 else if (caller_opts->tune != callee_opts->tune)
4495 else if (caller_opts->x_ix86_fpmath != callee_opts->x_ix86_fpmath)
4498 else if (caller_opts->branch_cost != callee_opts->branch_cost)
4509 /* Remember the last target of ix86_set_current_function. */
4510 static GTY(()) tree ix86_previous_fndecl;
4512 /* Establish appropriate back-end context for processing the function
4513 FNDECL. The argument might be NULL to indicate processing at top
4514 level, outside of any function scope. */
4516 ix86_set_current_function (tree fndecl)
4518 /* Only change the context if the function changes. This hook is called
4519 several times in the course of compiling a function, and we don't want to
4520 slow things down too much or call target_reinit when it isn't safe. */
4521 if (fndecl && fndecl != ix86_previous_fndecl)
4523 tree old_tree = (ix86_previous_fndecl
4524 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
4527 tree new_tree = (fndecl
4528 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
4531 ix86_previous_fndecl = fndecl;
4532 if (old_tree == new_tree)
4537 cl_target_option_restore (&global_options,
4538 TREE_TARGET_OPTION (new_tree));
4544 struct cl_target_option *def
4545 = TREE_TARGET_OPTION (target_option_current_node);
4547 cl_target_option_restore (&global_options, def);
4554 /* Return true if this goes in large data/bss. */
4557 ix86_in_large_data_p (tree exp)
4559 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4562 /* Functions are never large data. */
4563 if (TREE_CODE (exp) == FUNCTION_DECL)
4566 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4568 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4569 if (strcmp (section, ".ldata") == 0
4570 || strcmp (section, ".lbss") == 0)
4576 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4578 /* If this is an incomplete type with size 0, then we can't put it
4579 in data because it might be too big when completed. */
4580 if (!size || size > ix86_section_threshold)
4587 /* Switch to the appropriate section for output of DECL.
4588 DECL is either a `VAR_DECL' node or a constant of some sort.
4589 RELOC indicates whether forming the initial value of DECL requires
4590 link-time relocations. */
4592 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4596 x86_64_elf_select_section (tree decl, int reloc,
4597 unsigned HOST_WIDE_INT align)
4599 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4600 && ix86_in_large_data_p (decl))
4602 const char *sname = NULL;
4603 unsigned int flags = SECTION_WRITE;
4604 switch (categorize_decl_for_section (decl, reloc))
4609 case SECCAT_DATA_REL:
4610 sname = ".ldata.rel";
4612 case SECCAT_DATA_REL_LOCAL:
4613 sname = ".ldata.rel.local";
4615 case SECCAT_DATA_REL_RO:
4616 sname = ".ldata.rel.ro";
4618 case SECCAT_DATA_REL_RO_LOCAL:
4619 sname = ".ldata.rel.ro.local";
4623 flags |= SECTION_BSS;
4626 case SECCAT_RODATA_MERGE_STR:
4627 case SECCAT_RODATA_MERGE_STR_INIT:
4628 case SECCAT_RODATA_MERGE_CONST:
4632 case SECCAT_SRODATA:
4639 /* We don't split these for medium model. Place them into
4640 default sections and hope for best. */
4645 /* We might get called with string constants, but get_named_section
4646 doesn't like them as they are not DECLs. Also, we need to set
4647 flags in that case. */
4649 return get_section (sname, flags, NULL);
4650 return get_named_section (decl, sname, reloc);
4653 return default_elf_select_section (decl, reloc, align);
4656 /* Build up a unique section name, expressed as a
4657 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4658 RELOC indicates whether the initial value of EXP requires
4659 link-time relocations. */
4661 static void ATTRIBUTE_UNUSED
4662 x86_64_elf_unique_section (tree decl, int reloc)
4664 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4665 && ix86_in_large_data_p (decl))
4667 const char *prefix = NULL;
4668 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4669 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4671 switch (categorize_decl_for_section (decl, reloc))
4674 case SECCAT_DATA_REL:
4675 case SECCAT_DATA_REL_LOCAL:
4676 case SECCAT_DATA_REL_RO:
4677 case SECCAT_DATA_REL_RO_LOCAL:
4678 prefix = one_only ? ".ld" : ".ldata";
4681 prefix = one_only ? ".lb" : ".lbss";
4684 case SECCAT_RODATA_MERGE_STR:
4685 case SECCAT_RODATA_MERGE_STR_INIT:
4686 case SECCAT_RODATA_MERGE_CONST:
4687 prefix = one_only ? ".lr" : ".lrodata";
4689 case SECCAT_SRODATA:
4696 /* We don't split these for medium model. Place them into
4697 default sections and hope for best. */
4702 const char *name, *linkonce;
4705 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4706 name = targetm.strip_name_encoding (name);
4708 /* If we're using one_only, then there needs to be a .gnu.linkonce
4709 prefix to the section name. */
4710 linkonce = one_only ? ".gnu.linkonce" : "";
4712 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4714 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4718 default_unique_section (decl, reloc);
4721 #ifdef COMMON_ASM_OP
4722 /* This says how to output assembler code to declare an
4723 uninitialized external linkage data object.
4725 For medium model x86-64 we need to use .largecomm opcode for
4728 x86_elf_aligned_common (FILE *file,
4729 const char *name, unsigned HOST_WIDE_INT size,
4732 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4733 && size > (unsigned int)ix86_section_threshold)
4734 fputs (".largecomm\t", file);
4736 fputs (COMMON_ASM_OP, file);
4737 assemble_name (file, name);
4738 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4739 size, align / BITS_PER_UNIT);
4743 /* Utility function for targets to use in implementing
4744 ASM_OUTPUT_ALIGNED_BSS. */
4747 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4748 const char *name, unsigned HOST_WIDE_INT size,
4751 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4752 && size > (unsigned int)ix86_section_threshold)
4753 switch_to_section (get_named_section (decl, ".lbss", 0));
4755 switch_to_section (bss_section);
4756 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4757 #ifdef ASM_DECLARE_OBJECT_NAME
4758 last_assemble_variable_decl = decl;
4759 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4761 /* Standard thing is just output label for the object. */
4762 ASM_OUTPUT_LABEL (file, name);
4763 #endif /* ASM_DECLARE_OBJECT_NAME */
4764 ASM_OUTPUT_SKIP (file, size ? size : 1);
4767 /* Decide whether we must probe the stack before any space allocation
4768 on this target. It's essentially TARGET_STACK_PROBE except when
4769 -fstack-check causes the stack to be already probed differently. */
4772 ix86_target_stack_probe (void)
4774 /* Do not probe the stack twice if static stack checking is enabled. */
4775 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
4778 return TARGET_STACK_PROBE;
4781 /* Decide whether we can make a sibling call to a function. DECL is the
4782 declaration of the function being targeted by the call and EXP is the
4783 CALL_EXPR representing the call. */
4786 ix86_function_ok_for_sibcall (tree decl, tree exp)
4788 tree type, decl_or_type;
4791 /* If we are generating position-independent code, we cannot sibcall
4792 optimize any indirect call, or a direct call to a global function,
4793 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4797 && (!decl || !targetm.binds_local_p (decl)))
4800 /* If we need to align the outgoing stack, then sibcalling would
4801 unalign the stack, which may break the called function. */
4802 if (ix86_minimum_incoming_stack_boundary (true)
4803 < PREFERRED_STACK_BOUNDARY)
4808 decl_or_type = decl;
4809 type = TREE_TYPE (decl);
4813 /* We're looking at the CALL_EXPR, we need the type of the function. */
4814 type = CALL_EXPR_FN (exp); /* pointer expression */
4815 type = TREE_TYPE (type); /* pointer type */
4816 type = TREE_TYPE (type); /* function type */
4817 decl_or_type = type;
4820 /* Check that the return value locations are the same. Like
4821 if we are returning floats on the 80387 register stack, we cannot
4822 make a sibcall from a function that doesn't return a float to a
4823 function that does or, conversely, from a function that does return
4824 a float to a function that doesn't; the necessary stack adjustment
4825 would not be executed. This is also the place we notice
4826 differences in the return value ABI. Note that it is ok for one
4827 of the functions to have void return type as long as the return
4828 value of the other is passed in a register. */
4829 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4830 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4832 if (STACK_REG_P (a) || STACK_REG_P (b))
4834 if (!rtx_equal_p (a, b))
4837 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4839 /* Disable sibcall if we need to generate vzeroupper after
4841 if (TARGET_VZEROUPPER
4842 && cfun->machine->callee_return_avx256_p
4843 && !cfun->machine->caller_return_avx256_p)
4846 else if (!rtx_equal_p (a, b))
4851 /* The SYSV ABI has more call-clobbered registers;
4852 disallow sibcalls from MS to SYSV. */
4853 if (cfun->machine->call_abi == MS_ABI
4854 && ix86_function_type_abi (type) == SYSV_ABI)
4859 /* If this call is indirect, we'll need to be able to use a
4860 call-clobbered register for the address of the target function.
4861 Make sure that all such registers are not used for passing
4862 parameters. Note that DLLIMPORT functions are indirect. */
4864 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4866 if (ix86_function_regparm (type, NULL) >= 3)
4868 /* ??? Need to count the actual number of registers to be used,
4869 not the possible number of registers. Fix later. */
4875 /* Otherwise okay. That also includes certain types of indirect calls. */
4879 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4880 and "sseregparm" calling convention attributes;
4881 arguments as in struct attribute_spec.handler. */
4884 ix86_handle_cconv_attribute (tree *node, tree name,
4886 int flags ATTRIBUTE_UNUSED,
4889 if (TREE_CODE (*node) != FUNCTION_TYPE
4890 && TREE_CODE (*node) != METHOD_TYPE
4891 && TREE_CODE (*node) != FIELD_DECL
4892 && TREE_CODE (*node) != TYPE_DECL)
4894 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4896 *no_add_attrs = true;
4900 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4901 if (is_attribute_p ("regparm", name))
4905 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4907 error ("fastcall and regparm attributes are not compatible");
4910 if (lookup_attribute ("thiscall", TYPE_ATTRIBUTES (*node)))
4912 error ("regparam and thiscall attributes are not compatible");
4915 cst = TREE_VALUE (args);
4916 if (TREE_CODE (cst) != INTEGER_CST)
4918 warning (OPT_Wattributes,
4919 "%qE attribute requires an integer constant argument",
4921 *no_add_attrs = true;
4923 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4925 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4927 *no_add_attrs = true;
4935 /* Do not warn when emulating the MS ABI. */
4936 if ((TREE_CODE (*node) != FUNCTION_TYPE
4937 && TREE_CODE (*node) != METHOD_TYPE)
4938 || ix86_function_type_abi (*node) != MS_ABI)
4939 warning (OPT_Wattributes, "%qE attribute ignored",
4941 *no_add_attrs = true;
4945 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4946 if (is_attribute_p ("fastcall", name))
4948 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4950 error ("fastcall and cdecl attributes are not compatible");
4952 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4954 error ("fastcall and stdcall attributes are not compatible");
4956 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4958 error ("fastcall and regparm attributes are not compatible");
4960 if (lookup_attribute ("thiscall", TYPE_ATTRIBUTES (*node)))
4962 error ("fastcall and thiscall attributes are not compatible");
4966 /* Can combine stdcall with fastcall (redundant), regparm and
4968 else if (is_attribute_p ("stdcall", name))
4970 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4972 error ("stdcall and cdecl attributes are not compatible");
4974 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4976 error ("stdcall and fastcall attributes are not compatible");
4978 if (lookup_attribute ("thiscall", TYPE_ATTRIBUTES (*node)))
4980 error ("stdcall and thiscall attributes are not compatible");
4984 /* Can combine cdecl with regparm and sseregparm. */
4985 else if (is_attribute_p ("cdecl", name))
4987 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4989 error ("stdcall and cdecl attributes are not compatible");
4991 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4993 error ("fastcall and cdecl attributes are not compatible");
4995 if (lookup_attribute ("thiscall", TYPE_ATTRIBUTES (*node)))
4997 error ("cdecl and thiscall attributes are not compatible");
5000 else if (is_attribute_p ("thiscall", name))
5002 if (TREE_CODE (*node) != METHOD_TYPE && pedantic)
5003 warning (OPT_Wattributes, "%qE attribute is used for none class-method",
5005 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
5007 error ("stdcall and thiscall attributes are not compatible");
5009 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
5011 error ("fastcall and thiscall attributes are not compatible");
5013 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
5015 error ("cdecl and thiscall attributes are not compatible");
5019 /* Can combine sseregparm with all attributes. */
5024 /* The transactional memory builtins are implicitly regparm or fastcall
5025 depending on the ABI. Override the generic do-nothing attribute that
5026 these builtins were declared with, and replace it with one of the two
5027 attributes that we expect elsewhere. */
5030 ix86_handle_tm_regparm_attribute (tree *node, tree name ATTRIBUTE_UNUSED,
5031 tree args ATTRIBUTE_UNUSED,
5032 int flags ATTRIBUTE_UNUSED,
5037 /* In no case do we want to add the placeholder attribute. */
5038 *no_add_attrs = true;
5040 /* The 64-bit ABI is unchanged for transactional memory. */
5044 /* ??? Is there a better way to validate 32-bit windows? We have
5045 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5046 if (CHECK_STACK_LIMIT > 0)
5047 alt = tree_cons (get_identifier ("fastcall"), NULL, NULL);
5050 alt = tree_cons (NULL, build_int_cst (NULL, 2), NULL);
5051 alt = tree_cons (get_identifier ("regparm"), alt, NULL);
5053 decl_attributes (node, alt, flags);
5058 /* This function determines from TYPE the calling-convention. */
5061 ix86_get_callcvt (const_tree type)
5063 unsigned int ret = 0;
5068 return IX86_CALLCVT_CDECL;
5070 attrs = TYPE_ATTRIBUTES (type);
5071 if (attrs != NULL_TREE)
5073 if (lookup_attribute ("cdecl", attrs))
5074 ret |= IX86_CALLCVT_CDECL;
5075 else if (lookup_attribute ("stdcall", attrs))
5076 ret |= IX86_CALLCVT_STDCALL;
5077 else if (lookup_attribute ("fastcall", attrs))
5078 ret |= IX86_CALLCVT_FASTCALL;
5079 else if (lookup_attribute ("thiscall", attrs))
5080 ret |= IX86_CALLCVT_THISCALL;
5082 /* Regparam isn't allowed for thiscall and fastcall. */
5083 if ((ret & (IX86_CALLCVT_THISCALL | IX86_CALLCVT_FASTCALL)) == 0)
5085 if (lookup_attribute ("regparm", attrs))
5086 ret |= IX86_CALLCVT_REGPARM;
5087 if (lookup_attribute ("sseregparm", attrs))
5088 ret |= IX86_CALLCVT_SSEREGPARM;
5091 if (IX86_BASE_CALLCVT(ret) != 0)
5095 is_stdarg = stdarg_p (type);
5096 if (TARGET_RTD && !is_stdarg)
5097 return IX86_CALLCVT_STDCALL | ret;
5101 || TREE_CODE (type) != METHOD_TYPE
5102 || ix86_function_type_abi (type) != MS_ABI)
5103 return IX86_CALLCVT_CDECL | ret;
5105 return IX86_CALLCVT_THISCALL;
5108 /* Return 0 if the attributes for two types are incompatible, 1 if they
5109 are compatible, and 2 if they are nearly compatible (which causes a
5110 warning to be generated). */
5113 ix86_comp_type_attributes (const_tree type1, const_tree type2)
5115 unsigned int ccvt1, ccvt2;
5117 if (TREE_CODE (type1) != FUNCTION_TYPE
5118 && TREE_CODE (type1) != METHOD_TYPE)
5121 ccvt1 = ix86_get_callcvt (type1);
5122 ccvt2 = ix86_get_callcvt (type2);
5125 if (ix86_function_regparm (type1, NULL)
5126 != ix86_function_regparm (type2, NULL))
5132 /* Return the regparm value for a function with the indicated TYPE and DECL.
5133 DECL may be NULL when calling function indirectly
5134 or considering a libcall. */
5137 ix86_function_regparm (const_tree type, const_tree decl)
5144 return (ix86_function_type_abi (type) == SYSV_ABI
5145 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
5146 ccvt = ix86_get_callcvt (type);
5147 regparm = ix86_regparm;
5149 if ((ccvt & IX86_CALLCVT_REGPARM) != 0)
5151 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
5154 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
5158 else if ((ccvt & IX86_CALLCVT_FASTCALL) != 0)
5160 else if ((ccvt & IX86_CALLCVT_THISCALL) != 0)
5163 /* Use register calling convention for local functions when possible. */
5165 && TREE_CODE (decl) == FUNCTION_DECL
5167 && !(profile_flag && !flag_fentry))
5169 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5170 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
5171 if (i && i->local && i->can_change_signature)
5173 int local_regparm, globals = 0, regno;
5175 /* Make sure no regparm register is taken by a
5176 fixed register variable. */
5177 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
5178 if (fixed_regs[local_regparm])
5181 /* We don't want to use regparm(3) for nested functions as
5182 these use a static chain pointer in the third argument. */
5183 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
5186 /* In 32-bit mode save a register for the split stack. */
5187 if (!TARGET_64BIT && local_regparm == 3 && flag_split_stack)
5190 /* Each fixed register usage increases register pressure,
5191 so less registers should be used for argument passing.
5192 This functionality can be overriden by an explicit
5194 for (regno = 0; regno <= DI_REG; regno++)
5195 if (fixed_regs[regno])
5199 = globals < local_regparm ? local_regparm - globals : 0;
5201 if (local_regparm > regparm)
5202 regparm = local_regparm;
5209 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5210 DFmode (2) arguments in SSE registers for a function with the
5211 indicated TYPE and DECL. DECL may be NULL when calling function
5212 indirectly or considering a libcall. Otherwise return 0. */
5215 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
5217 gcc_assert (!TARGET_64BIT);
5219 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5220 by the sseregparm attribute. */
5221 if (TARGET_SSEREGPARM
5222 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
5229 error ("calling %qD with attribute sseregparm without "
5230 "SSE/SSE2 enabled", decl);
5232 error ("calling %qT with attribute sseregparm without "
5233 "SSE/SSE2 enabled", type);
5241 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5242 (and DFmode for SSE2) arguments in SSE registers. */
5243 if (decl && TARGET_SSE_MATH && optimize
5244 && !(profile_flag && !flag_fentry))
5246 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5247 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
5248 if (i && i->local && i->can_change_signature)
5249 return TARGET_SSE2 ? 2 : 1;
5255 /* Return true if EAX is live at the start of the function. Used by
5256 ix86_expand_prologue to determine if we need special help before
5257 calling allocate_stack_worker. */
5260 ix86_eax_live_at_start_p (void)
5262 /* Cheat. Don't bother working forward from ix86_function_regparm
5263 to the function type to whether an actual argument is located in
5264 eax. Instead just look at cfg info, which is still close enough
5265 to correct at this point. This gives false positives for broken
5266 functions that might use uninitialized data that happens to be
5267 allocated in eax, but who cares? */
5268 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
5272 ix86_keep_aggregate_return_pointer (tree fntype)
5278 attr = lookup_attribute ("callee_pop_aggregate_return",
5279 TYPE_ATTRIBUTES (fntype));
5281 return (TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr))) == 0);
5283 /* For 32-bit MS-ABI the default is to keep aggregate
5285 if (ix86_function_type_abi (fntype) == MS_ABI)
5288 return KEEP_AGGREGATE_RETURN_POINTER != 0;
5291 /* Value is the number of bytes of arguments automatically
5292 popped when returning from a subroutine call.
5293 FUNDECL is the declaration node of the function (as a tree),
5294 FUNTYPE is the data type of the function (as a tree),
5295 or for a library call it is an identifier node for the subroutine name.
5296 SIZE is the number of bytes of arguments passed on the stack.
5298 On the 80386, the RTD insn may be used to pop them if the number
5299 of args is fixed, but if the number is variable then the caller
5300 must pop them all. RTD can't be used for library calls now
5301 because the library is compiled with the Unix compiler.
5302 Use of RTD is a selectable option, since it is incompatible with
5303 standard Unix calling sequences. If the option is not selected,
5304 the caller must always pop the args.
5306 The attribute stdcall is equivalent to RTD on a per module basis. */
5309 ix86_return_pops_args (tree fundecl, tree funtype, int size)
5313 /* None of the 64-bit ABIs pop arguments. */
5317 ccvt = ix86_get_callcvt (funtype);
5319 if ((ccvt & (IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL
5320 | IX86_CALLCVT_THISCALL)) != 0
5321 && ! stdarg_p (funtype))
5324 /* Lose any fake structure return argument if it is passed on the stack. */
5325 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
5326 && !ix86_keep_aggregate_return_pointer (funtype))
5328 int nregs = ix86_function_regparm (funtype, fundecl);
5330 return GET_MODE_SIZE (Pmode);
5336 /* Argument support functions. */
5338 /* Return true when register may be used to pass function parameters. */
5340 ix86_function_arg_regno_p (int regno)
5343 const int *parm_regs;
5348 return (regno < REGPARM_MAX
5349 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
5351 return (regno < REGPARM_MAX
5352 || (TARGET_MMX && MMX_REGNO_P (regno)
5353 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
5354 || (TARGET_SSE && SSE_REGNO_P (regno)
5355 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
5360 if (SSE_REGNO_P (regno) && TARGET_SSE)
5365 if (TARGET_SSE && SSE_REGNO_P (regno)
5366 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
5370 /* TODO: The function should depend on current function ABI but
5371 builtins.c would need updating then. Therefore we use the
5374 /* RAX is used as hidden argument to va_arg functions. */
5375 if (ix86_abi == SYSV_ABI && regno == AX_REG)
5378 if (ix86_abi == MS_ABI)
5379 parm_regs = x86_64_ms_abi_int_parameter_registers;
5381 parm_regs = x86_64_int_parameter_registers;
5382 for (i = 0; i < (ix86_abi == MS_ABI
5383 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
5384 if (regno == parm_regs[i])
5389 /* Return if we do not know how to pass TYPE solely in registers. */
5392 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
5394 if (must_pass_in_stack_var_size_or_pad (mode, type))
5397 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5398 The layout_type routine is crafty and tries to trick us into passing
5399 currently unsupported vector types on the stack by using TImode. */
5400 return (!TARGET_64BIT && mode == TImode
5401 && type && TREE_CODE (type) != VECTOR_TYPE);
5404 /* It returns the size, in bytes, of the area reserved for arguments passed
5405 in registers for the function represented by fndecl dependent to the used
5408 ix86_reg_parm_stack_space (const_tree fndecl)
5410 enum calling_abi call_abi = SYSV_ABI;
5411 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
5412 call_abi = ix86_function_abi (fndecl);
5414 call_abi = ix86_function_type_abi (fndecl);
5415 if (TARGET_64BIT && call_abi == MS_ABI)
5420 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5423 ix86_function_type_abi (const_tree fntype)
5425 if (fntype != NULL_TREE && TYPE_ATTRIBUTES (fntype) != NULL_TREE)
5427 enum calling_abi abi = ix86_abi;
5428 if (abi == SYSV_ABI)
5430 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
5433 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
5441 ix86_function_ms_hook_prologue (const_tree fn)
5443 if (fn && lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fn)))
5445 if (decl_function_context (fn) != NULL_TREE)
5446 error_at (DECL_SOURCE_LOCATION (fn),
5447 "ms_hook_prologue is not compatible with nested function");
5454 static enum calling_abi
5455 ix86_function_abi (const_tree fndecl)
5459 return ix86_function_type_abi (TREE_TYPE (fndecl));
5462 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5465 ix86_cfun_abi (void)
5469 return cfun->machine->call_abi;
5472 /* Write the extra assembler code needed to declare a function properly. */
5475 ix86_asm_output_function_label (FILE *asm_out_file, const char *fname,
5478 bool is_ms_hook = ix86_function_ms_hook_prologue (decl);
5482 int i, filler_count = (TARGET_64BIT ? 32 : 16);
5483 unsigned int filler_cc = 0xcccccccc;
5485 for (i = 0; i < filler_count; i += 4)
5486 fprintf (asm_out_file, ASM_LONG " %#x\n", filler_cc);
5489 #ifdef SUBTARGET_ASM_UNWIND_INIT
5490 SUBTARGET_ASM_UNWIND_INIT (asm_out_file);
5493 ASM_OUTPUT_LABEL (asm_out_file, fname);
5495 /* Output magic byte marker, if hot-patch attribute is set. */
5500 /* leaq [%rsp + 0], %rsp */
5501 asm_fprintf (asm_out_file, ASM_BYTE
5502 "0x48, 0x8d, 0xa4, 0x24, 0x00, 0x00, 0x00, 0x00\n");
5506 /* movl.s %edi, %edi
5508 movl.s %esp, %ebp */
5509 asm_fprintf (asm_out_file, ASM_BYTE
5510 "0x8b, 0xff, 0x55, 0x8b, 0xec\n");
5516 extern void init_regs (void);
5518 /* Implementation of call abi switching target hook. Specific to FNDECL
5519 the specific call register sets are set. See also
5520 ix86_conditional_register_usage for more details. */
5522 ix86_call_abi_override (const_tree fndecl)
5524 if (fndecl == NULL_TREE)
5525 cfun->machine->call_abi = ix86_abi;
5527 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
5530 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5531 expensive re-initialization of init_regs each time we switch function context
5532 since this is needed only during RTL expansion. */
5534 ix86_maybe_switch_abi (void)
5537 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
5541 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5542 for a call to a function whose data type is FNTYPE.
5543 For a library call, FNTYPE is 0. */
5546 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
5547 tree fntype, /* tree ptr for function decl */
5548 rtx libname, /* SYMBOL_REF of library name or 0 */
5552 struct cgraph_local_info *i;
5555 memset (cum, 0, sizeof (*cum));
5557 /* Initialize for the current callee. */
5560 cfun->machine->callee_pass_avx256_p = false;
5561 cfun->machine->callee_return_avx256_p = false;
5566 i = cgraph_local_info (fndecl);
5567 cum->call_abi = ix86_function_abi (fndecl);
5568 fnret_type = TREE_TYPE (TREE_TYPE (fndecl));
5573 cum->call_abi = ix86_function_type_abi (fntype);
5575 fnret_type = TREE_TYPE (fntype);
5580 if (TARGET_VZEROUPPER && fnret_type)
5582 rtx fnret_value = ix86_function_value (fnret_type, fntype,
5584 if (function_pass_avx256_p (fnret_value))
5586 /* The return value of this function uses 256bit AVX modes. */
5588 cfun->machine->callee_return_avx256_p = true;
5590 cfun->machine->caller_return_avx256_p = true;
5594 cum->caller = caller;
5596 /* Set up the number of registers to use for passing arguments. */
5598 if (TARGET_64BIT && cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
5599 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
5600 "or subtarget optimization implying it");
5601 cum->nregs = ix86_regparm;
5604 cum->nregs = (cum->call_abi == SYSV_ABI
5605 ? X86_64_REGPARM_MAX
5606 : X86_64_MS_REGPARM_MAX);
5610 cum->sse_nregs = SSE_REGPARM_MAX;
5613 cum->sse_nregs = (cum->call_abi == SYSV_ABI
5614 ? X86_64_SSE_REGPARM_MAX
5615 : X86_64_MS_SSE_REGPARM_MAX);
5619 cum->mmx_nregs = MMX_REGPARM_MAX;
5620 cum->warn_avx = true;
5621 cum->warn_sse = true;
5622 cum->warn_mmx = true;
5624 /* Because type might mismatch in between caller and callee, we need to
5625 use actual type of function for local calls.
5626 FIXME: cgraph_analyze can be told to actually record if function uses
5627 va_start so for local functions maybe_vaarg can be made aggressive
5629 FIXME: once typesytem is fixed, we won't need this code anymore. */
5630 if (i && i->local && i->can_change_signature)
5631 fntype = TREE_TYPE (fndecl);
5632 cum->maybe_vaarg = (fntype
5633 ? (!prototype_p (fntype) || stdarg_p (fntype))
5638 /* If there are variable arguments, then we won't pass anything
5639 in registers in 32-bit mode. */
5640 if (stdarg_p (fntype))
5651 /* Use ecx and edx registers if function has fastcall attribute,
5652 else look for regparm information. */
5655 unsigned int ccvt = ix86_get_callcvt (fntype);
5656 if ((ccvt & IX86_CALLCVT_THISCALL) != 0)
5659 cum->fastcall = 1; /* Same first register as in fastcall. */
5661 else if ((ccvt & IX86_CALLCVT_FASTCALL) != 0)
5667 cum->nregs = ix86_function_regparm (fntype, fndecl);
5670 /* Set up the number of SSE registers used for passing SFmode
5671 and DFmode arguments. Warn for mismatching ABI. */
5672 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
5676 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5677 But in the case of vector types, it is some vector mode.
5679 When we have only some of our vector isa extensions enabled, then there
5680 are some modes for which vector_mode_supported_p is false. For these
5681 modes, the generic vector support in gcc will choose some non-vector mode
5682 in order to implement the type. By computing the natural mode, we'll
5683 select the proper ABI location for the operand and not depend on whatever
5684 the middle-end decides to do with these vector types.
5686 The midde-end can't deal with the vector types > 16 bytes. In this
5687 case, we return the original mode and warn ABI change if CUM isn't
5690 static enum machine_mode
5691 type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum)
5693 enum machine_mode mode = TYPE_MODE (type);
5695 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
5697 HOST_WIDE_INT size = int_size_in_bytes (type);
5698 if ((size == 8 || size == 16 || size == 32)
5699 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5700 && TYPE_VECTOR_SUBPARTS (type) > 1)
5702 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
5704 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5705 mode = MIN_MODE_VECTOR_FLOAT;
5707 mode = MIN_MODE_VECTOR_INT;
5709 /* Get the mode which has this inner mode and number of units. */
5710 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
5711 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
5712 && GET_MODE_INNER (mode) == innermode)
5714 if (size == 32 && !TARGET_AVX)
5716 static bool warnedavx;
5723 warning (0, "AVX vector argument without AVX "
5724 "enabled changes the ABI");
5726 return TYPE_MODE (type);
5739 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5740 this may not agree with the mode that the type system has chosen for the
5741 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5742 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5745 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
5750 if (orig_mode != BLKmode)
5751 tmp = gen_rtx_REG (orig_mode, regno);
5754 tmp = gen_rtx_REG (mode, regno);
5755 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
5756 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5762 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5763 of this code is to classify each 8bytes of incoming argument by the register
5764 class and assign registers accordingly. */
5766 /* Return the union class of CLASS1 and CLASS2.
5767 See the x86-64 PS ABI for details. */
5769 static enum x86_64_reg_class
5770 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5772 /* Rule #1: If both classes are equal, this is the resulting class. */
5773 if (class1 == class2)
5776 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5778 if (class1 == X86_64_NO_CLASS)
5780 if (class2 == X86_64_NO_CLASS)
5783 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5784 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5785 return X86_64_MEMORY_CLASS;
5787 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5788 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5789 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5790 return X86_64_INTEGERSI_CLASS;
5791 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5792 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5793 return X86_64_INTEGER_CLASS;
5795 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5797 if (class1 == X86_64_X87_CLASS
5798 || class1 == X86_64_X87UP_CLASS
5799 || class1 == X86_64_COMPLEX_X87_CLASS
5800 || class2 == X86_64_X87_CLASS
5801 || class2 == X86_64_X87UP_CLASS
5802 || class2 == X86_64_COMPLEX_X87_CLASS)
5803 return X86_64_MEMORY_CLASS;
5805 /* Rule #6: Otherwise class SSE is used. */
5806 return X86_64_SSE_CLASS;
5809 /* Classify the argument of type TYPE and mode MODE.
5810 CLASSES will be filled by the register class used to pass each word
5811 of the operand. The number of words is returned. In case the parameter
5812 should be passed in memory, 0 is returned. As a special case for zero
5813 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5815 BIT_OFFSET is used internally for handling records and specifies offset
5816 of the offset in bits modulo 256 to avoid overflow cases.
5818 See the x86-64 PS ABI for details.
5822 classify_argument (enum machine_mode mode, const_tree type,
5823 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5825 HOST_WIDE_INT bytes =
5826 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5827 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5829 /* Variable sized entities are always passed/returned in memory. */
5833 if (mode != VOIDmode
5834 && targetm.calls.must_pass_in_stack (mode, type))
5837 if (type && AGGREGATE_TYPE_P (type))
5841 enum x86_64_reg_class subclasses[MAX_CLASSES];
5843 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5847 for (i = 0; i < words; i++)
5848 classes[i] = X86_64_NO_CLASS;
5850 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5851 signalize memory class, so handle it as special case. */
5854 classes[0] = X86_64_NO_CLASS;
5858 /* Classify each field of record and merge classes. */
5859 switch (TREE_CODE (type))
5862 /* And now merge the fields of structure. */
5863 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5865 if (TREE_CODE (field) == FIELD_DECL)
5869 if (TREE_TYPE (field) == error_mark_node)
5872 /* Bitfields are always classified as integer. Handle them
5873 early, since later code would consider them to be
5874 misaligned integers. */
5875 if (DECL_BIT_FIELD (field))
5877 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5878 i < ((int_bit_position (field) + (bit_offset % 64))
5879 + tree_low_cst (DECL_SIZE (field), 0)
5882 merge_classes (X86_64_INTEGER_CLASS,
5889 type = TREE_TYPE (field);
5891 /* Flexible array member is ignored. */
5892 if (TYPE_MODE (type) == BLKmode
5893 && TREE_CODE (type) == ARRAY_TYPE
5894 && TYPE_SIZE (type) == NULL_TREE
5895 && TYPE_DOMAIN (type) != NULL_TREE
5896 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5901 if (!warned && warn_psabi)
5904 inform (input_location,
5905 "the ABI of passing struct with"
5906 " a flexible array member has"
5907 " changed in GCC 4.4");
5911 num = classify_argument (TYPE_MODE (type), type,
5913 (int_bit_position (field)
5914 + bit_offset) % 256);
5917 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5918 for (i = 0; i < num && (i + pos) < words; i++)
5920 merge_classes (subclasses[i], classes[i + pos]);
5927 /* Arrays are handled as small records. */
5930 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5931 TREE_TYPE (type), subclasses, bit_offset);
5935 /* The partial classes are now full classes. */
5936 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5937 subclasses[0] = X86_64_SSE_CLASS;
5938 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5939 && !((bit_offset % 64) == 0 && bytes == 4))
5940 subclasses[0] = X86_64_INTEGER_CLASS;
5942 for (i = 0; i < words; i++)
5943 classes[i] = subclasses[i % num];
5948 case QUAL_UNION_TYPE:
5949 /* Unions are similar to RECORD_TYPE but offset is always 0.
5951 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5953 if (TREE_CODE (field) == FIELD_DECL)
5957 if (TREE_TYPE (field) == error_mark_node)
5960 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5961 TREE_TYPE (field), subclasses,
5965 for (i = 0; i < num; i++)
5966 classes[i] = merge_classes (subclasses[i], classes[i]);
5977 /* When size > 16 bytes, if the first one isn't
5978 X86_64_SSE_CLASS or any other ones aren't
5979 X86_64_SSEUP_CLASS, everything should be passed in
5981 if (classes[0] != X86_64_SSE_CLASS)
5984 for (i = 1; i < words; i++)
5985 if (classes[i] != X86_64_SSEUP_CLASS)
5989 /* Final merger cleanup. */
5990 for (i = 0; i < words; i++)
5992 /* If one class is MEMORY, everything should be passed in
5994 if (classes[i] == X86_64_MEMORY_CLASS)
5997 /* The X86_64_SSEUP_CLASS should be always preceded by
5998 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5999 if (classes[i] == X86_64_SSEUP_CLASS
6000 && classes[i - 1] != X86_64_SSE_CLASS
6001 && classes[i - 1] != X86_64_SSEUP_CLASS)
6003 /* The first one should never be X86_64_SSEUP_CLASS. */
6004 gcc_assert (i != 0);
6005 classes[i] = X86_64_SSE_CLASS;
6008 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6009 everything should be passed in memory. */
6010 if (classes[i] == X86_64_X87UP_CLASS
6011 && (classes[i - 1] != X86_64_X87_CLASS))
6015 /* The first one should never be X86_64_X87UP_CLASS. */
6016 gcc_assert (i != 0);
6017 if (!warned && warn_psabi)
6020 inform (input_location,
6021 "the ABI of passing union with long double"
6022 " has changed in GCC 4.4");
6030 /* Compute alignment needed. We align all types to natural boundaries with
6031 exception of XFmode that is aligned to 64bits. */
6032 if (mode != VOIDmode && mode != BLKmode)
6034 int mode_alignment = GET_MODE_BITSIZE (mode);
6037 mode_alignment = 128;
6038 else if (mode == XCmode)
6039 mode_alignment = 256;
6040 if (COMPLEX_MODE_P (mode))
6041 mode_alignment /= 2;
6042 /* Misaligned fields are always returned in memory. */
6043 if (bit_offset % mode_alignment)
6047 /* for V1xx modes, just use the base mode */
6048 if (VECTOR_MODE_P (mode) && mode != V1DImode && mode != V1TImode
6049 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
6050 mode = GET_MODE_INNER (mode);
6052 /* Classification of atomic types. */
6057 classes[0] = X86_64_SSE_CLASS;
6060 classes[0] = X86_64_SSE_CLASS;
6061 classes[1] = X86_64_SSEUP_CLASS;
6071 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
6075 classes[0] = X86_64_INTEGERSI_CLASS;
6078 else if (size <= 64)
6080 classes[0] = X86_64_INTEGER_CLASS;
6083 else if (size <= 64+32)
6085 classes[0] = X86_64_INTEGER_CLASS;
6086 classes[1] = X86_64_INTEGERSI_CLASS;
6089 else if (size <= 64+64)
6091 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
6099 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
6103 /* OImode shouldn't be used directly. */
6108 if (!(bit_offset % 64))
6109 classes[0] = X86_64_SSESF_CLASS;
6111 classes[0] = X86_64_SSE_CLASS;
6114 classes[0] = X86_64_SSEDF_CLASS;
6117 classes[0] = X86_64_X87_CLASS;
6118 classes[1] = X86_64_X87UP_CLASS;
6121 classes[0] = X86_64_SSE_CLASS;
6122 classes[1] = X86_64_SSEUP_CLASS;
6125 classes[0] = X86_64_SSE_CLASS;
6126 if (!(bit_offset % 64))
6132 if (!warned && warn_psabi)
6135 inform (input_location,
6136 "the ABI of passing structure with complex float"
6137 " member has changed in GCC 4.4");
6139 classes[1] = X86_64_SSESF_CLASS;
6143 classes[0] = X86_64_SSEDF_CLASS;
6144 classes[1] = X86_64_SSEDF_CLASS;
6147 classes[0] = X86_64_COMPLEX_X87_CLASS;
6150 /* This modes is larger than 16 bytes. */
6158 classes[0] = X86_64_SSE_CLASS;
6159 classes[1] = X86_64_SSEUP_CLASS;
6160 classes[2] = X86_64_SSEUP_CLASS;
6161 classes[3] = X86_64_SSEUP_CLASS;
6169 classes[0] = X86_64_SSE_CLASS;
6170 classes[1] = X86_64_SSEUP_CLASS;
6178 classes[0] = X86_64_SSE_CLASS;
6184 gcc_assert (VECTOR_MODE_P (mode));
6189 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
6191 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
6192 classes[0] = X86_64_INTEGERSI_CLASS;
6194 classes[0] = X86_64_INTEGER_CLASS;
6195 classes[1] = X86_64_INTEGER_CLASS;
6196 return 1 + (bytes > 8);
6200 /* Examine the argument and return set number of register required in each
6201 class. Return 0 iff parameter should be passed in memory. */
6203 examine_argument (enum machine_mode mode, const_tree type, int in_return,
6204 int *int_nregs, int *sse_nregs)
6206 enum x86_64_reg_class regclass[MAX_CLASSES];
6207 int n = classify_argument (mode, type, regclass, 0);
6213 for (n--; n >= 0; n--)
6214 switch (regclass[n])
6216 case X86_64_INTEGER_CLASS:
6217 case X86_64_INTEGERSI_CLASS:
6220 case X86_64_SSE_CLASS:
6221 case X86_64_SSESF_CLASS:
6222 case X86_64_SSEDF_CLASS:
6225 case X86_64_NO_CLASS:
6226 case X86_64_SSEUP_CLASS:
6228 case X86_64_X87_CLASS:
6229 case X86_64_X87UP_CLASS:
6233 case X86_64_COMPLEX_X87_CLASS:
6234 return in_return ? 2 : 0;
6235 case X86_64_MEMORY_CLASS:
6241 /* Construct container for the argument used by GCC interface. See
6242 FUNCTION_ARG for the detailed description. */
6245 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
6246 const_tree type, int in_return, int nintregs, int nsseregs,
6247 const int *intreg, int sse_regno)
6249 /* The following variables hold the static issued_error state. */
6250 static bool issued_sse_arg_error;
6251 static bool issued_sse_ret_error;
6252 static bool issued_x87_ret_error;
6254 enum machine_mode tmpmode;
6256 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
6257 enum x86_64_reg_class regclass[MAX_CLASSES];
6261 int needed_sseregs, needed_intregs;
6262 rtx exp[MAX_CLASSES];
6265 n = classify_argument (mode, type, regclass, 0);
6268 if (!examine_argument (mode, type, in_return, &needed_intregs,
6271 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
6274 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6275 some less clueful developer tries to use floating-point anyway. */
6276 if (needed_sseregs && !TARGET_SSE)
6280 if (!issued_sse_ret_error)
6282 error ("SSE register return with SSE disabled");
6283 issued_sse_ret_error = true;
6286 else if (!issued_sse_arg_error)
6288 error ("SSE register argument with SSE disabled");
6289 issued_sse_arg_error = true;
6294 /* Likewise, error if the ABI requires us to return values in the
6295 x87 registers and the user specified -mno-80387. */
6296 if (!TARGET_80387 && in_return)
6297 for (i = 0; i < n; i++)
6298 if (regclass[i] == X86_64_X87_CLASS
6299 || regclass[i] == X86_64_X87UP_CLASS
6300 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
6302 if (!issued_x87_ret_error)
6304 error ("x87 register return with x87 disabled");
6305 issued_x87_ret_error = true;
6310 /* First construct simple cases. Avoid SCmode, since we want to use
6311 single register to pass this type. */
6312 if (n == 1 && mode != SCmode)
6313 switch (regclass[0])
6315 case X86_64_INTEGER_CLASS:
6316 case X86_64_INTEGERSI_CLASS:
6317 return gen_rtx_REG (mode, intreg[0]);
6318 case X86_64_SSE_CLASS:
6319 case X86_64_SSESF_CLASS:
6320 case X86_64_SSEDF_CLASS:
6321 if (mode != BLKmode)
6322 return gen_reg_or_parallel (mode, orig_mode,
6323 SSE_REGNO (sse_regno));
6325 case X86_64_X87_CLASS:
6326 case X86_64_COMPLEX_X87_CLASS:
6327 return gen_rtx_REG (mode, FIRST_STACK_REG);
6328 case X86_64_NO_CLASS:
6329 /* Zero sized array, struct or class. */
6334 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
6335 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
6336 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
6338 && regclass[0] == X86_64_SSE_CLASS
6339 && regclass[1] == X86_64_SSEUP_CLASS
6340 && regclass[2] == X86_64_SSEUP_CLASS
6341 && regclass[3] == X86_64_SSEUP_CLASS
6343 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
6346 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
6347 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
6348 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
6349 && regclass[1] == X86_64_INTEGER_CLASS
6350 && (mode == CDImode || mode == TImode || mode == TFmode)
6351 && intreg[0] + 1 == intreg[1])
6352 return gen_rtx_REG (mode, intreg[0]);
6354 /* Otherwise figure out the entries of the PARALLEL. */
6355 for (i = 0; i < n; i++)
6359 switch (regclass[i])
6361 case X86_64_NO_CLASS:
6363 case X86_64_INTEGER_CLASS:
6364 case X86_64_INTEGERSI_CLASS:
6365 /* Merge TImodes on aligned occasions here too. */
6366 if (i * 8 + 8 > bytes)
6367 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
6368 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
6372 /* We've requested 24 bytes we don't have mode for. Use DImode. */
6373 if (tmpmode == BLKmode)
6375 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
6376 gen_rtx_REG (tmpmode, *intreg),
6380 case X86_64_SSESF_CLASS:
6381 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
6382 gen_rtx_REG (SFmode,
6383 SSE_REGNO (sse_regno)),
6387 case X86_64_SSEDF_CLASS:
6388 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
6389 gen_rtx_REG (DFmode,
6390 SSE_REGNO (sse_regno)),
6394 case X86_64_SSE_CLASS:
6402 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
6412 && regclass[1] == X86_64_SSEUP_CLASS
6413 && regclass[2] == X86_64_SSEUP_CLASS
6414 && regclass[3] == X86_64_SSEUP_CLASS);
6421 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
6422 gen_rtx_REG (tmpmode,
6423 SSE_REGNO (sse_regno)),
6432 /* Empty aligned struct, union or class. */
6436 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
6437 for (i = 0; i < nexps; i++)
6438 XVECEXP (ret, 0, i) = exp [i];
6442 /* Update the data in CUM to advance over an argument of mode MODE
6443 and data type TYPE. (TYPE is null for libcalls where that information
6444 may not be available.) */
6447 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6448 const_tree type, HOST_WIDE_INT bytes,
6449 HOST_WIDE_INT words)
6465 cum->words += words;
6466 cum->nregs -= words;
6467 cum->regno += words;
6469 if (cum->nregs <= 0)
6477 /* OImode shouldn't be used directly. */
6481 if (cum->float_in_sse < 2)
6484 if (cum->float_in_sse < 1)
6501 if (!type || !AGGREGATE_TYPE_P (type))
6503 cum->sse_words += words;
6504 cum->sse_nregs -= 1;
6505 cum->sse_regno += 1;
6506 if (cum->sse_nregs <= 0)
6520 if (!type || !AGGREGATE_TYPE_P (type))
6522 cum->mmx_words += words;
6523 cum->mmx_nregs -= 1;
6524 cum->mmx_regno += 1;
6525 if (cum->mmx_nregs <= 0)
6536 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6537 const_tree type, HOST_WIDE_INT words, bool named)
6539 int int_nregs, sse_nregs;
6541 /* Unnamed 256bit vector mode parameters are passed on stack. */
6542 if (!named && VALID_AVX256_REG_MODE (mode))
6545 if (examine_argument (mode, type, 0, &int_nregs, &sse_nregs)
6546 && sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
6548 cum->nregs -= int_nregs;
6549 cum->sse_nregs -= sse_nregs;
6550 cum->regno += int_nregs;
6551 cum->sse_regno += sse_nregs;
6555 int align = ix86_function_arg_boundary (mode, type) / BITS_PER_WORD;
6556 cum->words = (cum->words + align - 1) & ~(align - 1);
6557 cum->words += words;
6562 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
6563 HOST_WIDE_INT words)
6565 /* Otherwise, this should be passed indirect. */
6566 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
6568 cum->words += words;
6576 /* Update the data in CUM to advance over an argument of mode MODE and
6577 data type TYPE. (TYPE is null for libcalls where that information
6578 may not be available.) */
6581 ix86_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
6582 const_tree type, bool named)
6584 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6585 HOST_WIDE_INT bytes, words;
6587 if (mode == BLKmode)
6588 bytes = int_size_in_bytes (type);
6590 bytes = GET_MODE_SIZE (mode);
6591 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6594 mode = type_natural_mode (type, NULL);
6596 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6597 function_arg_advance_ms_64 (cum, bytes, words);
6598 else if (TARGET_64BIT)
6599 function_arg_advance_64 (cum, mode, type, words, named);
6601 function_arg_advance_32 (cum, mode, type, bytes, words);
6604 /* Define where to put the arguments to a function.
6605 Value is zero to push the argument on the stack,
6606 or a hard register in which to store the argument.
6608 MODE is the argument's machine mode.
6609 TYPE is the data type of the argument (as a tree).
6610 This is null for libcalls where that information may
6612 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6613 the preceding args and about the function being called.
6614 NAMED is nonzero if this argument is a named parameter
6615 (otherwise it is an extra parameter matching an ellipsis). */
6618 function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
6619 enum machine_mode orig_mode, const_tree type,
6620 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
6622 static bool warnedsse, warnedmmx;
6624 /* Avoid the AL settings for the Unix64 ABI. */
6625 if (mode == VOIDmode)
6641 if (words <= cum->nregs)
6643 int regno = cum->regno;
6645 /* Fastcall allocates the first two DWORD (SImode) or
6646 smaller arguments to ECX and EDX if it isn't an
6652 || (type && AGGREGATE_TYPE_P (type)))
6655 /* ECX not EAX is the first allocated register. */
6656 if (regno == AX_REG)
6659 return gen_rtx_REG (mode, regno);
6664 if (cum->float_in_sse < 2)
6667 if (cum->float_in_sse < 1)
6671 /* In 32bit, we pass TImode in xmm registers. */
6678 if (!type || !AGGREGATE_TYPE_P (type))
6680 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
6683 warning (0, "SSE vector argument without SSE enabled "
6687 return gen_reg_or_parallel (mode, orig_mode,
6688 cum->sse_regno + FIRST_SSE_REG);
6693 /* OImode shouldn't be used directly. */
6702 if (!type || !AGGREGATE_TYPE_P (type))
6705 return gen_reg_or_parallel (mode, orig_mode,
6706 cum->sse_regno + FIRST_SSE_REG);
6716 if (!type || !AGGREGATE_TYPE_P (type))
6718 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
6721 warning (0, "MMX vector argument without MMX enabled "
6725 return gen_reg_or_parallel (mode, orig_mode,
6726 cum->mmx_regno + FIRST_MMX_REG);
6735 function_arg_64 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
6736 enum machine_mode orig_mode, const_tree type, bool named)
6738 /* Handle a hidden AL argument containing number of registers
6739 for varargs x86-64 functions. */
6740 if (mode == VOIDmode)
6741 return GEN_INT (cum->maybe_vaarg
6742 ? (cum->sse_nregs < 0
6743 ? X86_64_SSE_REGPARM_MAX
6758 /* Unnamed 256bit vector mode parameters are passed on stack. */
6764 return construct_container (mode, orig_mode, type, 0, cum->nregs,
6766 &x86_64_int_parameter_registers [cum->regno],
6771 function_arg_ms_64 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
6772 enum machine_mode orig_mode, bool named,
6773 HOST_WIDE_INT bytes)
6777 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6778 We use value of -2 to specify that current function call is MSABI. */
6779 if (mode == VOIDmode)
6780 return GEN_INT (-2);
6782 /* If we've run out of registers, it goes on the stack. */
6783 if (cum->nregs == 0)
6786 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6788 /* Only floating point modes are passed in anything but integer regs. */
6789 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6792 regno = cum->regno + FIRST_SSE_REG;
6797 /* Unnamed floating parameters are passed in both the
6798 SSE and integer registers. */
6799 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6800 t2 = gen_rtx_REG (mode, regno);
6801 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6802 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6803 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6806 /* Handle aggregated types passed in register. */
6807 if (orig_mode == BLKmode)
6809 if (bytes > 0 && bytes <= 8)
6810 mode = (bytes > 4 ? DImode : SImode);
6811 if (mode == BLKmode)
6815 return gen_reg_or_parallel (mode, orig_mode, regno);
6818 /* Return where to put the arguments to a function.
6819 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6821 MODE is the argument's machine mode. TYPE is the data type of the
6822 argument. It is null for libcalls where that information may not be
6823 available. CUM gives information about the preceding args and about
6824 the function being called. NAMED is nonzero if this argument is a
6825 named parameter (otherwise it is an extra parameter matching an
6829 ix86_function_arg (cumulative_args_t cum_v, enum machine_mode omode,
6830 const_tree type, bool named)
6832 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6833 enum machine_mode mode = omode;
6834 HOST_WIDE_INT bytes, words;
6837 if (mode == BLKmode)
6838 bytes = int_size_in_bytes (type);
6840 bytes = GET_MODE_SIZE (mode);
6841 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6843 /* To simplify the code below, represent vector types with a vector mode
6844 even if MMX/SSE are not active. */
6845 if (type && TREE_CODE (type) == VECTOR_TYPE)
6846 mode = type_natural_mode (type, cum);
6848 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6849 arg = function_arg_ms_64 (cum, mode, omode, named, bytes);
6850 else if (TARGET_64BIT)
6851 arg = function_arg_64 (cum, mode, omode, type, named);
6853 arg = function_arg_32 (cum, mode, omode, type, bytes, words);
6855 if (TARGET_VZEROUPPER && function_pass_avx256_p (arg))
6857 /* This argument uses 256bit AVX modes. */
6859 cfun->machine->callee_pass_avx256_p = true;
6861 cfun->machine->caller_pass_avx256_p = true;
6867 /* A C expression that indicates when an argument must be passed by
6868 reference. If nonzero for an argument, a copy of that argument is
6869 made in memory and a pointer to the argument is passed instead of
6870 the argument itself. The pointer is passed in whatever way is
6871 appropriate for passing a pointer to that type. */
6874 ix86_pass_by_reference (cumulative_args_t cum_v ATTRIBUTE_UNUSED,
6875 enum machine_mode mode ATTRIBUTE_UNUSED,
6876 const_tree type, bool named ATTRIBUTE_UNUSED)
6878 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6880 /* See Windows x64 Software Convention. */
6881 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6883 int msize = (int) GET_MODE_SIZE (mode);
6886 /* Arrays are passed by reference. */
6887 if (TREE_CODE (type) == ARRAY_TYPE)
6890 if (AGGREGATE_TYPE_P (type))
6892 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6893 are passed by reference. */
6894 msize = int_size_in_bytes (type);
6898 /* __m128 is passed by reference. */
6900 case 1: case 2: case 4: case 8:
6906 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6912 /* Return true when TYPE should be 128bit aligned for 32bit argument
6913 passing ABI. XXX: This function is obsolete and is only used for
6914 checking psABI compatibility with previous versions of GCC. */
6917 ix86_compat_aligned_value_p (const_tree type)
6919 enum machine_mode mode = TYPE_MODE (type);
6920 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6924 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6926 if (TYPE_ALIGN (type) < 128)
6929 if (AGGREGATE_TYPE_P (type))
6931 /* Walk the aggregates recursively. */
6932 switch (TREE_CODE (type))
6936 case QUAL_UNION_TYPE:
6940 /* Walk all the structure fields. */
6941 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6943 if (TREE_CODE (field) == FIELD_DECL
6944 && ix86_compat_aligned_value_p (TREE_TYPE (field)))
6951 /* Just for use if some languages passes arrays by value. */
6952 if (ix86_compat_aligned_value_p (TREE_TYPE (type)))
6963 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
6964 XXX: This function is obsolete and is only used for checking psABI
6965 compatibility with previous versions of GCC. */
6968 ix86_compat_function_arg_boundary (enum machine_mode mode,
6969 const_tree type, unsigned int align)
6971 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6972 natural boundaries. */
6973 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6975 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6976 make an exception for SSE modes since these require 128bit
6979 The handling here differs from field_alignment. ICC aligns MMX
6980 arguments to 4 byte boundaries, while structure fields are aligned
6981 to 8 byte boundaries. */
6984 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6985 align = PARM_BOUNDARY;
6989 if (!ix86_compat_aligned_value_p (type))
6990 align = PARM_BOUNDARY;
6993 if (align > BIGGEST_ALIGNMENT)
6994 align = BIGGEST_ALIGNMENT;
6998 /* Return true when TYPE should be 128bit aligned for 32bit argument
7002 ix86_contains_aligned_value_p (const_tree type)
7004 enum machine_mode mode = TYPE_MODE (type);
7006 if (mode == XFmode || mode == XCmode)
7009 if (TYPE_ALIGN (type) < 128)
7012 if (AGGREGATE_TYPE_P (type))
7014 /* Walk the aggregates recursively. */
7015 switch (TREE_CODE (type))
7019 case QUAL_UNION_TYPE:
7023 /* Walk all the structure fields. */
7024 for (field = TYPE_FIELDS (type);
7026 field = DECL_CHAIN (field))
7028 if (TREE_CODE (field) == FIELD_DECL
7029 && ix86_contains_aligned_value_p (TREE_TYPE (field)))
7036 /* Just for use if some languages passes arrays by value. */
7037 if (ix86_contains_aligned_value_p (TREE_TYPE (type)))
7046 return TYPE_ALIGN (type) >= 128;
7051 /* Gives the alignment boundary, in bits, of an argument with the
7052 specified mode and type. */
7055 ix86_function_arg_boundary (enum machine_mode mode, const_tree type)
7060 /* Since the main variant type is used for call, we convert it to
7061 the main variant type. */
7062 type = TYPE_MAIN_VARIANT (type);
7063 align = TYPE_ALIGN (type);
7066 align = GET_MODE_ALIGNMENT (mode);
7067 if (align < PARM_BOUNDARY)
7068 align = PARM_BOUNDARY;
7072 unsigned int saved_align = align;
7076 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7079 if (mode == XFmode || mode == XCmode)
7080 align = PARM_BOUNDARY;
7082 else if (!ix86_contains_aligned_value_p (type))
7083 align = PARM_BOUNDARY;
7086 align = PARM_BOUNDARY;
7091 && align != ix86_compat_function_arg_boundary (mode, type,
7095 inform (input_location,
7096 "The ABI for passing parameters with %d-byte"
7097 " alignment has changed in GCC 4.6",
7098 align / BITS_PER_UNIT);
7105 /* Return true if N is a possible register number of function value. */
7108 ix86_function_value_regno_p (const unsigned int regno)
7115 case FIRST_FLOAT_REG:
7116 /* TODO: The function should depend on current function ABI but
7117 builtins.c would need updating then. Therefore we use the
7119 if (TARGET_64BIT && ix86_abi == MS_ABI)
7121 return TARGET_FLOAT_RETURNS_IN_80387;
7127 if (TARGET_MACHO || TARGET_64BIT)
7135 /* Define how to find the value returned by a function.
7136 VALTYPE is the data type of the value (as a tree).
7137 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7138 otherwise, FUNC is 0. */
7141 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
7142 const_tree fntype, const_tree fn)
7146 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7147 we normally prevent this case when mmx is not available. However
7148 some ABIs may require the result to be returned like DImode. */
7149 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
7150 regno = FIRST_MMX_REG;
7152 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7153 we prevent this case when sse is not available. However some ABIs
7154 may require the result to be returned like integer TImode. */
7155 else if (mode == TImode
7156 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
7157 regno = FIRST_SSE_REG;
7159 /* 32-byte vector modes in %ymm0. */
7160 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
7161 regno = FIRST_SSE_REG;
7163 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7164 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
7165 regno = FIRST_FLOAT_REG;
7167 /* Most things go in %eax. */
7170 /* Override FP return register with %xmm0 for local functions when
7171 SSE math is enabled or for functions with sseregparm attribute. */
7172 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
7174 int sse_level = ix86_function_sseregparm (fntype, fn, false);
7175 if ((sse_level >= 1 && mode == SFmode)
7176 || (sse_level == 2 && mode == DFmode))
7177 regno = FIRST_SSE_REG;
7180 /* OImode shouldn't be used directly. */
7181 gcc_assert (mode != OImode);
7183 return gen_rtx_REG (orig_mode, regno);
7187 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
7192 /* Handle libcalls, which don't provide a type node. */
7193 if (valtype == NULL)
7207 regno = FIRST_SSE_REG;
7211 regno = FIRST_FLOAT_REG;
7219 return gen_rtx_REG (mode, regno);
7221 else if (POINTER_TYPE_P (valtype))
7223 /* Pointers are always returned in Pmode. */
7227 ret = construct_container (mode, orig_mode, valtype, 1,
7228 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
7229 x86_64_int_return_registers, 0);
7231 /* For zero sized structures, construct_container returns NULL, but we
7232 need to keep rest of compiler happy by returning meaningful value. */
7234 ret = gen_rtx_REG (orig_mode, AX_REG);
7240 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
7242 unsigned int regno = AX_REG;
7246 switch (GET_MODE_SIZE (mode))
7249 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
7250 && !COMPLEX_MODE_P (mode))
7251 regno = FIRST_SSE_REG;
7255 if (mode == SFmode || mode == DFmode)
7256 regno = FIRST_SSE_REG;
7262 return gen_rtx_REG (orig_mode, regno);
7266 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
7267 enum machine_mode orig_mode, enum machine_mode mode)
7269 const_tree fn, fntype;
7272 if (fntype_or_decl && DECL_P (fntype_or_decl))
7273 fn = fntype_or_decl;
7274 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
7276 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
7277 return function_value_ms_64 (orig_mode, mode);
7278 else if (TARGET_64BIT)
7279 return function_value_64 (orig_mode, mode, valtype);
7281 return function_value_32 (orig_mode, mode, fntype, fn);
7285 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
7286 bool outgoing ATTRIBUTE_UNUSED)
7288 enum machine_mode mode, orig_mode;
7290 orig_mode = TYPE_MODE (valtype);
7291 mode = type_natural_mode (valtype, NULL);
7292 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
7295 /* Pointer function arguments and return values are promoted to Pmode. */
7297 static enum machine_mode
7298 ix86_promote_function_mode (const_tree type, enum machine_mode mode,
7299 int *punsignedp, const_tree fntype,
7302 if (type != NULL_TREE && POINTER_TYPE_P (type))
7304 *punsignedp = POINTERS_EXTEND_UNSIGNED;
7307 return default_promote_function_mode (type, mode, punsignedp, fntype,
7312 ix86_libcall_value (enum machine_mode mode)
7314 return ix86_function_value_1 (NULL, NULL, mode, mode);
7317 /* Return true iff type is returned in memory. */
7319 static bool ATTRIBUTE_UNUSED
7320 return_in_memory_32 (const_tree type, enum machine_mode mode)
7324 if (mode == BLKmode)
7327 size = int_size_in_bytes (type);
7329 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
7332 if (VECTOR_MODE_P (mode) || mode == TImode)
7334 /* User-created vectors small enough to fit in EAX. */
7338 /* MMX/3dNow values are returned in MM0,
7339 except when it doesn't exits or the ABI prescribes otherwise. */
7341 return !TARGET_MMX || TARGET_VECT8_RETURNS;
7343 /* SSE values are returned in XMM0, except when it doesn't exist. */
7347 /* AVX values are returned in YMM0, except when it doesn't exist. */
7358 /* OImode shouldn't be used directly. */
7359 gcc_assert (mode != OImode);
7364 static bool ATTRIBUTE_UNUSED
7365 return_in_memory_64 (const_tree type, enum machine_mode mode)
7367 int needed_intregs, needed_sseregs;
7368 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
7371 static bool ATTRIBUTE_UNUSED
7372 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
7374 HOST_WIDE_INT size = int_size_in_bytes (type);
7376 /* __m128 is returned in xmm0. */
7377 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
7378 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
7381 /* Otherwise, the size must be exactly in [1248]. */
7382 return size != 1 && size != 2 && size != 4 && size != 8;
7386 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7388 #ifdef SUBTARGET_RETURN_IN_MEMORY
7389 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
7391 const enum machine_mode mode = type_natural_mode (type, NULL);
7395 if (ix86_function_type_abi (fntype) == MS_ABI)
7396 return return_in_memory_ms_64 (type, mode);
7398 return return_in_memory_64 (type, mode);
7401 return return_in_memory_32 (type, mode);
7405 /* When returning SSE vector types, we have a choice of either
7406 (1) being abi incompatible with a -march switch, or
7407 (2) generating an error.
7408 Given no good solution, I think the safest thing is one warning.
7409 The user won't be able to use -Werror, but....
7411 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7412 called in response to actually generating a caller or callee that
7413 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7414 via aggregate_value_p for general type probing from tree-ssa. */
7417 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
7419 static bool warnedsse, warnedmmx;
7421 if (!TARGET_64BIT && type)
7423 /* Look at the return type of the function, not the function type. */
7424 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
7426 if (!TARGET_SSE && !warnedsse)
7429 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
7432 warning (0, "SSE vector return without SSE enabled "
7437 if (!TARGET_MMX && !warnedmmx)
7439 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
7442 warning (0, "MMX vector return without MMX enabled "
7452 /* Create the va_list data type. */
7454 /* Returns the calling convention specific va_list date type.
7455 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7458 ix86_build_builtin_va_list_abi (enum calling_abi abi)
7460 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7462 /* For i386 we use plain pointer to argument area. */
7463 if (!TARGET_64BIT || abi == MS_ABI)
7464 return build_pointer_type (char_type_node);
7466 record = lang_hooks.types.make_type (RECORD_TYPE);
7467 type_decl = build_decl (BUILTINS_LOCATION,
7468 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7470 f_gpr = build_decl (BUILTINS_LOCATION,
7471 FIELD_DECL, get_identifier ("gp_offset"),
7472 unsigned_type_node);
7473 f_fpr = build_decl (BUILTINS_LOCATION,
7474 FIELD_DECL, get_identifier ("fp_offset"),
7475 unsigned_type_node);
7476 f_ovf = build_decl (BUILTINS_LOCATION,
7477 FIELD_DECL, get_identifier ("overflow_arg_area"),
7479 f_sav = build_decl (BUILTINS_LOCATION,
7480 FIELD_DECL, get_identifier ("reg_save_area"),
7483 va_list_gpr_counter_field = f_gpr;
7484 va_list_fpr_counter_field = f_fpr;
7486 DECL_FIELD_CONTEXT (f_gpr) = record;
7487 DECL_FIELD_CONTEXT (f_fpr) = record;
7488 DECL_FIELD_CONTEXT (f_ovf) = record;
7489 DECL_FIELD_CONTEXT (f_sav) = record;
7491 TYPE_STUB_DECL (record) = type_decl;
7492 TYPE_NAME (record) = type_decl;
7493 TYPE_FIELDS (record) = f_gpr;
7494 DECL_CHAIN (f_gpr) = f_fpr;
7495 DECL_CHAIN (f_fpr) = f_ovf;
7496 DECL_CHAIN (f_ovf) = f_sav;
7498 layout_type (record);
7500 /* The correct type is an array type of one element. */
7501 return build_array_type (record, build_index_type (size_zero_node));
7504 /* Setup the builtin va_list data type and for 64-bit the additional
7505 calling convention specific va_list data types. */
7508 ix86_build_builtin_va_list (void)
7510 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
7512 /* Initialize abi specific va_list builtin types. */
7516 if (ix86_abi == MS_ABI)
7518 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
7519 if (TREE_CODE (t) != RECORD_TYPE)
7520 t = build_variant_type_copy (t);
7521 sysv_va_list_type_node = t;
7526 if (TREE_CODE (t) != RECORD_TYPE)
7527 t = build_variant_type_copy (t);
7528 sysv_va_list_type_node = t;
7530 if (ix86_abi != MS_ABI)
7532 t = ix86_build_builtin_va_list_abi (MS_ABI);
7533 if (TREE_CODE (t) != RECORD_TYPE)
7534 t = build_variant_type_copy (t);
7535 ms_va_list_type_node = t;
7540 if (TREE_CODE (t) != RECORD_TYPE)
7541 t = build_variant_type_copy (t);
7542 ms_va_list_type_node = t;
7549 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7552 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
7558 /* GPR size of varargs save area. */
7559 if (cfun->va_list_gpr_size)
7560 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
7562 ix86_varargs_gpr_size = 0;
7564 /* FPR size of varargs save area. We don't need it if we don't pass
7565 anything in SSE registers. */
7566 if (TARGET_SSE && cfun->va_list_fpr_size)
7567 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
7569 ix86_varargs_fpr_size = 0;
7571 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
7574 save_area = frame_pointer_rtx;
7575 set = get_varargs_alias_set ();
7577 max = cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
7578 if (max > X86_64_REGPARM_MAX)
7579 max = X86_64_REGPARM_MAX;
7581 for (i = cum->regno; i < max; i++)
7583 mem = gen_rtx_MEM (Pmode,
7584 plus_constant (save_area, i * UNITS_PER_WORD));
7585 MEM_NOTRAP_P (mem) = 1;
7586 set_mem_alias_set (mem, set);
7587 emit_move_insn (mem, gen_rtx_REG (Pmode,
7588 x86_64_int_parameter_registers[i]));
7591 if (ix86_varargs_fpr_size)
7593 enum machine_mode smode;
7596 /* Now emit code to save SSE registers. The AX parameter contains number
7597 of SSE parameter registers used to call this function, though all we
7598 actually check here is the zero/non-zero status. */
7600 label = gen_label_rtx ();
7601 test = gen_rtx_EQ (VOIDmode, gen_rtx_REG (QImode, AX_REG), const0_rtx);
7602 emit_jump_insn (gen_cbranchqi4 (test, XEXP (test, 0), XEXP (test, 1),
7605 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7606 we used movdqa (i.e. TImode) instead? Perhaps even better would
7607 be if we could determine the real mode of the data, via a hook
7608 into pass_stdarg. Ignore all that for now. */
7610 if (crtl->stack_alignment_needed < GET_MODE_ALIGNMENT (smode))
7611 crtl->stack_alignment_needed = GET_MODE_ALIGNMENT (smode);
7613 max = cum->sse_regno + cfun->va_list_fpr_size / 16;
7614 if (max > X86_64_SSE_REGPARM_MAX)
7615 max = X86_64_SSE_REGPARM_MAX;
7617 for (i = cum->sse_regno; i < max; ++i)
7619 mem = plus_constant (save_area, i * 16 + ix86_varargs_gpr_size);
7620 mem = gen_rtx_MEM (smode, mem);
7621 MEM_NOTRAP_P (mem) = 1;
7622 set_mem_alias_set (mem, set);
7623 set_mem_align (mem, GET_MODE_ALIGNMENT (smode));
7625 emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i)));
7633 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
7635 alias_set_type set = get_varargs_alias_set ();
7638 /* Reset to zero, as there might be a sysv vaarg used
7640 ix86_varargs_gpr_size = 0;
7641 ix86_varargs_fpr_size = 0;
7643 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
7647 mem = gen_rtx_MEM (Pmode,
7648 plus_constant (virtual_incoming_args_rtx,
7649 i * UNITS_PER_WORD));
7650 MEM_NOTRAP_P (mem) = 1;
7651 set_mem_alias_set (mem, set);
7653 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
7654 emit_move_insn (mem, reg);
7659 ix86_setup_incoming_varargs (cumulative_args_t cum_v, enum machine_mode mode,
7660 tree type, int *pretend_size ATTRIBUTE_UNUSED,
7663 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7664 CUMULATIVE_ARGS next_cum;
7667 /* This argument doesn't appear to be used anymore. Which is good,
7668 because the old code here didn't suppress rtl generation. */
7669 gcc_assert (!no_rtl);
7674 fntype = TREE_TYPE (current_function_decl);
7676 /* For varargs, we do not want to skip the dummy va_dcl argument.
7677 For stdargs, we do want to skip the last named argument. */
7679 if (stdarg_p (fntype))
7680 ix86_function_arg_advance (pack_cumulative_args (&next_cum), mode, type,
7683 if (cum->call_abi == MS_ABI)
7684 setup_incoming_varargs_ms_64 (&next_cum);
7686 setup_incoming_varargs_64 (&next_cum);
7689 /* Checks if TYPE is of kind va_list char *. */
7692 is_va_list_char_pointer (tree type)
7696 /* For 32-bit it is always true. */
7699 canonic = ix86_canonical_va_list_type (type);
7700 return (canonic == ms_va_list_type_node
7701 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
7704 /* Implement va_start. */
7707 ix86_va_start (tree valist, rtx nextarg)
7709 HOST_WIDE_INT words, n_gpr, n_fpr;
7710 tree f_gpr, f_fpr, f_ovf, f_sav;
7711 tree gpr, fpr, ovf, sav, t;
7715 if (flag_split_stack
7716 && cfun->machine->split_stack_varargs_pointer == NULL_RTX)
7718 unsigned int scratch_regno;
7720 /* When we are splitting the stack, we can't refer to the stack
7721 arguments using internal_arg_pointer, because they may be on
7722 the old stack. The split stack prologue will arrange to
7723 leave a pointer to the old stack arguments in a scratch
7724 register, which we here copy to a pseudo-register. The split
7725 stack prologue can't set the pseudo-register directly because
7726 it (the prologue) runs before any registers have been saved. */
7728 scratch_regno = split_stack_prologue_scratch_regno ();
7729 if (scratch_regno != INVALID_REGNUM)
7733 reg = gen_reg_rtx (Pmode);
7734 cfun->machine->split_stack_varargs_pointer = reg;
7737 emit_move_insn (reg, gen_rtx_REG (Pmode, scratch_regno));
7741 push_topmost_sequence ();
7742 emit_insn_after (seq, entry_of_function ());
7743 pop_topmost_sequence ();
7747 /* Only 64bit target needs something special. */
7748 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
7750 if (cfun->machine->split_stack_varargs_pointer == NULL_RTX)
7751 std_expand_builtin_va_start (valist, nextarg);
7756 va_r = expand_expr (valist, NULL_RTX, VOIDmode, EXPAND_WRITE);
7757 next = expand_binop (ptr_mode, add_optab,
7758 cfun->machine->split_stack_varargs_pointer,
7759 crtl->args.arg_offset_rtx,
7760 NULL_RTX, 0, OPTAB_LIB_WIDEN);
7761 convert_move (va_r, next, 0);
7766 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
7767 f_fpr = DECL_CHAIN (f_gpr);
7768 f_ovf = DECL_CHAIN (f_fpr);
7769 f_sav = DECL_CHAIN (f_ovf);
7771 valist = build_simple_mem_ref (valist);
7772 TREE_TYPE (valist) = TREE_TYPE (sysv_va_list_type_node);
7773 /* The following should be folded into the MEM_REF offset. */
7774 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), unshare_expr (valist),
7776 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
7778 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
7780 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
7783 /* Count number of gp and fp argument registers used. */
7784 words = crtl->args.info.words;
7785 n_gpr = crtl->args.info.regno;
7786 n_fpr = crtl->args.info.sse_regno;
7788 if (cfun->va_list_gpr_size)
7790 type = TREE_TYPE (gpr);
7791 t = build2 (MODIFY_EXPR, type,
7792 gpr, build_int_cst (type, n_gpr * 8));
7793 TREE_SIDE_EFFECTS (t) = 1;
7794 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7797 if (TARGET_SSE && cfun->va_list_fpr_size)
7799 type = TREE_TYPE (fpr);
7800 t = build2 (MODIFY_EXPR, type, fpr,
7801 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
7802 TREE_SIDE_EFFECTS (t) = 1;
7803 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7806 /* Find the overflow area. */
7807 type = TREE_TYPE (ovf);
7808 if (cfun->machine->split_stack_varargs_pointer == NULL_RTX)
7809 ovf_rtx = crtl->args.internal_arg_pointer;
7811 ovf_rtx = cfun->machine->split_stack_varargs_pointer;
7812 t = make_tree (type, ovf_rtx);
7814 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
7815 t = build2 (MODIFY_EXPR, type, ovf, t);
7816 TREE_SIDE_EFFECTS (t) = 1;
7817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7819 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
7821 /* Find the register save area.
7822 Prologue of the function save it right above stack frame. */
7823 type = TREE_TYPE (sav);
7824 t = make_tree (type, frame_pointer_rtx);
7825 if (!ix86_varargs_gpr_size)
7826 t = fold_build_pointer_plus_hwi (t, -8 * X86_64_REGPARM_MAX);
7827 t = build2 (MODIFY_EXPR, type, sav, t);
7828 TREE_SIDE_EFFECTS (t) = 1;
7829 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7833 /* Implement va_arg. */
7836 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
7839 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
7840 tree f_gpr, f_fpr, f_ovf, f_sav;
7841 tree gpr, fpr, ovf, sav, t;
7843 tree lab_false, lab_over = NULL_TREE;
7848 enum machine_mode nat_mode;
7849 unsigned int arg_boundary;
7851 /* Only 64bit target needs something special. */
7852 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
7853 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
7855 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
7856 f_fpr = DECL_CHAIN (f_gpr);
7857 f_ovf = DECL_CHAIN (f_fpr);
7858 f_sav = DECL_CHAIN (f_ovf);
7860 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
7861 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
7862 valist = build_va_arg_indirect_ref (valist);
7863 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7864 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7865 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7867 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
7869 type = build_pointer_type (type);
7870 size = int_size_in_bytes (type);
7871 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7873 nat_mode = type_natural_mode (type, NULL);
7882 /* Unnamed 256bit vector mode parameters are passed on stack. */
7883 if (!TARGET_64BIT_MS_ABI)
7890 container = construct_container (nat_mode, TYPE_MODE (type),
7891 type, 0, X86_64_REGPARM_MAX,
7892 X86_64_SSE_REGPARM_MAX, intreg,
7897 /* Pull the value out of the saved registers. */
7899 addr = create_tmp_var (ptr_type_node, "addr");
7903 int needed_intregs, needed_sseregs;
7905 tree int_addr, sse_addr;
7907 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7908 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7910 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
7912 need_temp = (!REG_P (container)
7913 && ((needed_intregs && TYPE_ALIGN (type) > 64)
7914 || TYPE_ALIGN (type) > 128));
7916 /* In case we are passing structure, verify that it is consecutive block
7917 on the register save area. If not we need to do moves. */
7918 if (!need_temp && !REG_P (container))
7920 /* Verify that all registers are strictly consecutive */
7921 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7925 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7927 rtx slot = XVECEXP (container, 0, i);
7928 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7929 || INTVAL (XEXP (slot, 1)) != i * 16)
7937 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7939 rtx slot = XVECEXP (container, 0, i);
7940 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7941 || INTVAL (XEXP (slot, 1)) != i * 8)
7953 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7954 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7957 /* First ensure that we fit completely in registers. */
7960 t = build_int_cst (TREE_TYPE (gpr),
7961 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7962 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7963 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7964 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7965 gimplify_and_add (t, pre_p);
7969 t = build_int_cst (TREE_TYPE (fpr),
7970 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7971 + X86_64_REGPARM_MAX * 8);
7972 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7973 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7974 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7975 gimplify_and_add (t, pre_p);
7978 /* Compute index to start of area used for integer regs. */
7981 /* int_addr = gpr + sav; */
7982 t = fold_build_pointer_plus (sav, gpr);
7983 gimplify_assign (int_addr, t, pre_p);
7987 /* sse_addr = fpr + sav; */
7988 t = fold_build_pointer_plus (sav, fpr);
7989 gimplify_assign (sse_addr, t, pre_p);
7993 int i, prev_size = 0;
7994 tree temp = create_tmp_var (type, "va_arg_tmp");
7997 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7998 gimplify_assign (addr, t, pre_p);
8000 for (i = 0; i < XVECLEN (container, 0); i++)
8002 rtx slot = XVECEXP (container, 0, i);
8003 rtx reg = XEXP (slot, 0);
8004 enum machine_mode mode = GET_MODE (reg);
8010 tree dest_addr, dest;
8011 int cur_size = GET_MODE_SIZE (mode);
8013 gcc_assert (prev_size <= INTVAL (XEXP (slot, 1)));
8014 prev_size = INTVAL (XEXP (slot, 1));
8015 if (prev_size + cur_size > size)
8017 cur_size = size - prev_size;
8018 mode = mode_for_size (cur_size * BITS_PER_UNIT, MODE_INT, 1);
8019 if (mode == BLKmode)
8022 piece_type = lang_hooks.types.type_for_mode (mode, 1);
8023 if (mode == GET_MODE (reg))
8024 addr_type = build_pointer_type (piece_type);
8026 addr_type = build_pointer_type_for_mode (piece_type, ptr_mode,
8028 daddr_type = build_pointer_type_for_mode (piece_type, ptr_mode,
8031 if (SSE_REGNO_P (REGNO (reg)))
8033 src_addr = sse_addr;
8034 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
8038 src_addr = int_addr;
8039 src_offset = REGNO (reg) * 8;
8041 src_addr = fold_convert (addr_type, src_addr);
8042 src_addr = fold_build_pointer_plus_hwi (src_addr, src_offset);
8044 dest_addr = fold_convert (daddr_type, addr);
8045 dest_addr = fold_build_pointer_plus_hwi (dest_addr, prev_size);
8046 if (cur_size == GET_MODE_SIZE (mode))
8048 src = build_va_arg_indirect_ref (src_addr);
8049 dest = build_va_arg_indirect_ref (dest_addr);
8051 gimplify_assign (dest, src, pre_p);
8056 = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
8057 3, dest_addr, src_addr,
8058 size_int (cur_size));
8059 gimplify_and_add (copy, pre_p);
8061 prev_size += cur_size;
8067 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
8068 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
8069 gimplify_assign (gpr, t, pre_p);
8074 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
8075 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
8076 gimplify_assign (fpr, t, pre_p);
8079 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8081 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8084 /* ... otherwise out of the overflow area. */
8086 /* When we align parameter on stack for caller, if the parameter
8087 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8088 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8089 here with caller. */
8090 arg_boundary = ix86_function_arg_boundary (VOIDmode, type);
8091 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
8092 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
8094 /* Care for on-stack alignment if needed. */
8095 if (arg_boundary <= 64 || size == 0)
8099 HOST_WIDE_INT align = arg_boundary / 8;
8100 t = fold_build_pointer_plus_hwi (ovf, align - 1);
8101 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
8102 build_int_cst (TREE_TYPE (t), -align));
8105 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8106 gimplify_assign (addr, t, pre_p);
8108 t = fold_build_pointer_plus_hwi (t, rsize * UNITS_PER_WORD);
8109 gimplify_assign (unshare_expr (ovf), t, pre_p);
8112 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8114 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
8115 addr = fold_convert (ptrtype, addr);
8118 addr = build_va_arg_indirect_ref (addr);
8119 return build_va_arg_indirect_ref (addr);
8122 /* Return true if OPNUM's MEM should be matched
8123 in movabs* patterns. */
8126 ix86_check_movabs (rtx insn, int opnum)
8130 set = PATTERN (insn);
8131 if (GET_CODE (set) == PARALLEL)
8132 set = XVECEXP (set, 0, 0);
8133 gcc_assert (GET_CODE (set) == SET);
8134 mem = XEXP (set, opnum);
8135 while (GET_CODE (mem) == SUBREG)
8136 mem = SUBREG_REG (mem);
8137 gcc_assert (MEM_P (mem));
8138 return volatile_ok || !MEM_VOLATILE_P (mem);
8141 /* Initialize the table of extra 80387 mathematical constants. */
8144 init_ext_80387_constants (void)
8146 static const char * cst[5] =
8148 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
8149 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
8150 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
8151 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
8152 "3.1415926535897932385128089594061862044", /* 4: fldpi */
8156 for (i = 0; i < 5; i++)
8158 real_from_string (&ext_80387_constants_table[i], cst[i]);
8159 /* Ensure each constant is rounded to XFmode precision. */
8160 real_convert (&ext_80387_constants_table[i],
8161 XFmode, &ext_80387_constants_table[i]);
8164 ext_80387_constants_init = 1;
8167 /* Return non-zero if the constant is something that
8168 can be loaded with a special instruction. */
8171 standard_80387_constant_p (rtx x)
8173 enum machine_mode mode = GET_MODE (x);
8177 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
8180 if (x == CONST0_RTX (mode))
8182 if (x == CONST1_RTX (mode))
8185 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8187 /* For XFmode constants, try to find a special 80387 instruction when
8188 optimizing for size or on those CPUs that benefit from them. */
8190 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
8194 if (! ext_80387_constants_init)
8195 init_ext_80387_constants ();
8197 for (i = 0; i < 5; i++)
8198 if (real_identical (&r, &ext_80387_constants_table[i]))
8202 /* Load of the constant -0.0 or -1.0 will be split as
8203 fldz;fchs or fld1;fchs sequence. */
8204 if (real_isnegzero (&r))
8206 if (real_identical (&r, &dconstm1))
8212 /* Return the opcode of the special instruction to be used to load
8216 standard_80387_constant_opcode (rtx x)
8218 switch (standard_80387_constant_p (x))
8242 /* Return the CONST_DOUBLE representing the 80387 constant that is
8243 loaded by the specified special instruction. The argument IDX
8244 matches the return value from standard_80387_constant_p. */
8247 standard_80387_constant_rtx (int idx)
8251 if (! ext_80387_constants_init)
8252 init_ext_80387_constants ();
8268 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
8272 /* Return 1 if X is all 0s and 2 if x is all 1s
8273 in supported SSE/AVX vector mode. */
8276 standard_sse_constant_p (rtx x)
8278 enum machine_mode mode = GET_MODE (x);
8280 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
8282 if (vector_all_ones_operand (x, mode))
8304 /* Return the opcode of the special instruction to be used to load
8308 standard_sse_constant_opcode (rtx insn, rtx x)
8310 switch (standard_sse_constant_p (x))
8313 switch (get_attr_mode (insn))
8316 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
8317 return "%vpxor\t%0, %d0";
8319 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
8320 return "%vxorpd\t%0, %d0";
8322 return "%vxorps\t%0, %d0";
8325 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
8326 return "vpxor\t%x0, %x0, %x0";
8328 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
8329 return "vxorpd\t%x0, %x0, %x0";
8331 return "vxorps\t%x0, %x0, %x0";
8339 return "vpcmpeqd\t%0, %0, %0";
8341 return "pcmpeqd\t%0, %0";
8349 /* Returns true if OP contains a symbol reference */
8352 symbolic_reference_mentioned_p (rtx op)
8357 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
8360 fmt = GET_RTX_FORMAT (GET_CODE (op));
8361 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
8367 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
8368 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
8372 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
8379 /* Return true if it is appropriate to emit `ret' instructions in the
8380 body of a function. Do this only if the epilogue is simple, needing a
8381 couple of insns. Prior to reloading, we can't tell how many registers
8382 must be saved, so return false then. Return false if there is no frame
8383 marker to de-allocate. */
8386 ix86_can_use_return_insn_p (void)
8388 struct ix86_frame frame;
8390 if (! reload_completed || frame_pointer_needed)
8393 /* Don't allow more than 32k pop, since that's all we can do
8394 with one instruction. */
8395 if (crtl->args.pops_args && crtl->args.size >= 32768)
8398 ix86_compute_frame_layout (&frame);
8399 return (frame.stack_pointer_offset == UNITS_PER_WORD
8400 && (frame.nregs + frame.nsseregs) == 0);
8403 /* Value should be nonzero if functions must have frame pointers.
8404 Zero means the frame pointer need not be set up (and parms may
8405 be accessed via the stack pointer) in functions that seem suitable. */
8408 ix86_frame_pointer_required (void)
8410 /* If we accessed previous frames, then the generated code expects
8411 to be able to access the saved ebp value in our frame. */
8412 if (cfun->machine->accesses_prev_frame)
8415 /* Several x86 os'es need a frame pointer for other reasons,
8416 usually pertaining to setjmp. */
8417 if (SUBTARGET_FRAME_POINTER_REQUIRED)
8420 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8421 if (TARGET_32BIT_MS_ABI && cfun->calls_setjmp)
8424 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8425 allocation is 4GB. */
8426 if (TARGET_64BIT_MS_ABI && get_frame_size () > SEH_MAX_FRAME_SIZE)
8429 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8430 turns off the frame pointer by default. Turn it back on now if
8431 we've not got a leaf function. */
8432 if (TARGET_OMIT_LEAF_FRAME_POINTER
8433 && (!current_function_is_leaf
8434 || ix86_current_function_calls_tls_descriptor))
8437 if (crtl->profile && !flag_fentry)
8443 /* Record that the current function accesses previous call frames. */
8446 ix86_setup_frame_addresses (void)
8448 cfun->machine->accesses_prev_frame = 1;
8451 #ifndef USE_HIDDEN_LINKONCE
8452 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8453 # define USE_HIDDEN_LINKONCE 1
8455 # define USE_HIDDEN_LINKONCE 0
8459 static int pic_labels_used;
8461 /* Fills in the label name that should be used for a pc thunk for
8462 the given register. */
8465 get_pc_thunk_name (char name[32], unsigned int regno)
8467 gcc_assert (!TARGET_64BIT);
8469 if (USE_HIDDEN_LINKONCE)
8470 sprintf (name, "__x86.get_pc_thunk.%s", reg_names[regno]);
8472 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
8476 /* This function generates code for -fpic that loads %ebx with
8477 the return address of the caller and then returns. */
8480 ix86_code_end (void)
8485 for (regno = AX_REG; regno <= SP_REG; regno++)
8490 if (!(pic_labels_used & (1 << regno)))
8493 get_pc_thunk_name (name, regno);
8495 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
8496 get_identifier (name),
8497 build_function_type_list (void_type_node, NULL_TREE));
8498 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
8499 NULL_TREE, void_type_node);
8500 TREE_PUBLIC (decl) = 1;
8501 TREE_STATIC (decl) = 1;
8506 switch_to_section (darwin_sections[text_coal_section]);
8507 fputs ("\t.weak_definition\t", asm_out_file);
8508 assemble_name (asm_out_file, name);
8509 fputs ("\n\t.private_extern\t", asm_out_file);
8510 assemble_name (asm_out_file, name);
8511 putc ('\n', asm_out_file);
8512 ASM_OUTPUT_LABEL (asm_out_file, name);
8513 DECL_WEAK (decl) = 1;
8517 if (USE_HIDDEN_LINKONCE)
8519 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
8521 targetm.asm_out.unique_section (decl, 0);
8522 switch_to_section (get_named_section (decl, NULL, 0));
8524 targetm.asm_out.globalize_label (asm_out_file, name);
8525 fputs ("\t.hidden\t", asm_out_file);
8526 assemble_name (asm_out_file, name);
8527 putc ('\n', asm_out_file);
8528 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
8532 switch_to_section (text_section);
8533 ASM_OUTPUT_LABEL (asm_out_file, name);
8536 DECL_INITIAL (decl) = make_node (BLOCK);
8537 current_function_decl = decl;
8538 init_function_start (decl);
8539 first_function_block_is_cold = false;
8540 /* Make sure unwind info is emitted for the thunk if needed. */
8541 final_start_function (emit_barrier (), asm_out_file, 1);
8543 /* Pad stack IP move with 4 instructions (two NOPs count
8544 as one instruction). */
8545 if (TARGET_PAD_SHORT_FUNCTION)
8550 fputs ("\tnop\n", asm_out_file);
8553 xops[0] = gen_rtx_REG (Pmode, regno);
8554 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8555 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
8556 fputs ("\tret\n", asm_out_file);
8557 final_end_function ();
8558 init_insn_lengths ();
8559 free_after_compilation (cfun);
8561 current_function_decl = NULL;
8564 if (flag_split_stack)
8565 file_end_indicate_split_stack ();
8568 /* Emit code for the SET_GOT patterns. */
8571 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
8577 if (TARGET_VXWORKS_RTP && flag_pic)
8579 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8580 xops[2] = gen_rtx_MEM (Pmode,
8581 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
8582 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
8584 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8585 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8586 an unadorned address. */
8587 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
8588 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
8589 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
8593 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
8597 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
8599 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
8602 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8603 is what will be referenced by the Mach-O PIC subsystem. */
8605 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
8608 targetm.asm_out.internal_label (asm_out_file, "L",
8609 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
8614 get_pc_thunk_name (name, REGNO (dest));
8615 pic_labels_used |= 1 << REGNO (dest);
8617 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
8618 xops[2] = gen_rtx_MEM (QImode, xops[2]);
8619 output_asm_insn ("call\t%X2", xops);
8620 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8621 is what will be referenced by the Mach-O PIC subsystem. */
8624 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
8626 targetm.asm_out.internal_label (asm_out_file, "L",
8627 CODE_LABEL_NUMBER (label));
8632 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
8637 /* Generate an "push" pattern for input ARG. */
8642 struct machine_function *m = cfun->machine;
8644 if (m->fs.cfa_reg == stack_pointer_rtx)
8645 m->fs.cfa_offset += UNITS_PER_WORD;
8646 m->fs.sp_offset += UNITS_PER_WORD;
8648 return gen_rtx_SET (VOIDmode,
8650 gen_rtx_PRE_DEC (Pmode,
8651 stack_pointer_rtx)),
8655 /* Generate an "pop" pattern for input ARG. */
8660 return gen_rtx_SET (VOIDmode,
8663 gen_rtx_POST_INC (Pmode,
8664 stack_pointer_rtx)));
8667 /* Return >= 0 if there is an unused call-clobbered register available
8668 for the entire function. */
8671 ix86_select_alt_pic_regnum (void)
8673 if (current_function_is_leaf
8675 && !ix86_current_function_calls_tls_descriptor)
8678 /* Can't use the same register for both PIC and DRAP. */
8680 drap = REGNO (crtl->drap_reg);
8683 for (i = 2; i >= 0; --i)
8684 if (i != drap && !df_regs_ever_live_p (i))
8688 return INVALID_REGNUM;
8691 /* Return TRUE if we need to save REGNO. */
8694 ix86_save_reg (unsigned int regno, bool maybe_eh_return)
8696 if (pic_offset_table_rtx
8697 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
8698 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8700 || crtl->calls_eh_return
8701 || crtl->uses_const_pool))
8702 return ix86_select_alt_pic_regnum () == INVALID_REGNUM;
8704 if (crtl->calls_eh_return && maybe_eh_return)
8709 unsigned test = EH_RETURN_DATA_REGNO (i);
8710 if (test == INVALID_REGNUM)
8717 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
8720 return (df_regs_ever_live_p (regno)
8721 && !call_used_regs[regno]
8722 && !fixed_regs[regno]
8723 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
8726 /* Return number of saved general prupose registers. */
8729 ix86_nsaved_regs (void)
8734 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8735 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8740 /* Return number of saved SSE registrers. */
8743 ix86_nsaved_sseregs (void)
8748 if (!TARGET_64BIT_MS_ABI)
8750 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8751 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8756 /* Given FROM and TO register numbers, say whether this elimination is
8757 allowed. If stack alignment is needed, we can only replace argument
8758 pointer with hard frame pointer, or replace frame pointer with stack
8759 pointer. Otherwise, frame pointer elimination is automatically
8760 handled and all other eliminations are valid. */
8763 ix86_can_eliminate (const int from, const int to)
8765 if (stack_realign_fp)
8766 return ((from == ARG_POINTER_REGNUM
8767 && to == HARD_FRAME_POINTER_REGNUM)
8768 || (from == FRAME_POINTER_REGNUM
8769 && to == STACK_POINTER_REGNUM));
8771 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
8774 /* Return the offset between two registers, one to be eliminated, and the other
8775 its replacement, at the start of a routine. */
8778 ix86_initial_elimination_offset (int from, int to)
8780 struct ix86_frame frame;
8781 ix86_compute_frame_layout (&frame);
8783 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8784 return frame.hard_frame_pointer_offset;
8785 else if (from == FRAME_POINTER_REGNUM
8786 && to == HARD_FRAME_POINTER_REGNUM)
8787 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
8790 gcc_assert (to == STACK_POINTER_REGNUM);
8792 if (from == ARG_POINTER_REGNUM)
8793 return frame.stack_pointer_offset;
8795 gcc_assert (from == FRAME_POINTER_REGNUM);
8796 return frame.stack_pointer_offset - frame.frame_pointer_offset;
8800 /* In a dynamically-aligned function, we can't know the offset from
8801 stack pointer to frame pointer, so we must ensure that setjmp
8802 eliminates fp against the hard fp (%ebp) rather than trying to
8803 index from %esp up to the top of the frame across a gap that is
8804 of unknown (at compile-time) size. */
8806 ix86_builtin_setjmp_frame_value (void)
8808 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
8811 /* When using -fsplit-stack, the allocation routines set a field in
8812 the TCB to the bottom of the stack plus this much space, measured
8815 #define SPLIT_STACK_AVAILABLE 256
8817 /* Fill structure ix86_frame about frame of currently computed function. */
8820 ix86_compute_frame_layout (struct ix86_frame *frame)
8822 unsigned int stack_alignment_needed;
8823 HOST_WIDE_INT offset;
8824 unsigned int preferred_alignment;
8825 HOST_WIDE_INT size = get_frame_size ();
8826 HOST_WIDE_INT to_allocate;
8828 frame->nregs = ix86_nsaved_regs ();
8829 frame->nsseregs = ix86_nsaved_sseregs ();
8831 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
8832 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
8834 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8835 function prologues and leaf. */
8836 if ((TARGET_64BIT_MS_ABI && preferred_alignment < 16)
8837 && (!current_function_is_leaf || cfun->calls_alloca != 0
8838 || ix86_current_function_calls_tls_descriptor))
8840 preferred_alignment = 16;
8841 stack_alignment_needed = 16;
8842 crtl->preferred_stack_boundary = 128;
8843 crtl->stack_alignment_needed = 128;
8846 gcc_assert (!size || stack_alignment_needed);
8847 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
8848 gcc_assert (preferred_alignment <= stack_alignment_needed);
8850 /* For SEH we have to limit the amount of code movement into the prologue.
8851 At present we do this via a BLOCKAGE, at which point there's very little
8852 scheduling that can be done, which means that there's very little point
8853 in doing anything except PUSHs. */
8855 cfun->machine->use_fast_prologue_epilogue = false;
8857 /* During reload iteration the amount of registers saved can change.
8858 Recompute the value as needed. Do not recompute when amount of registers
8859 didn't change as reload does multiple calls to the function and does not
8860 expect the decision to change within single iteration. */
8861 else if (!optimize_function_for_size_p (cfun)
8862 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
8864 int count = frame->nregs;
8865 struct cgraph_node *node = cgraph_get_node (current_function_decl);
8867 cfun->machine->use_fast_prologue_epilogue_nregs = count;
8869 /* The fast prologue uses move instead of push to save registers. This
8870 is significantly longer, but also executes faster as modern hardware
8871 can execute the moves in parallel, but can't do that for push/pop.
8873 Be careful about choosing what prologue to emit: When function takes
8874 many instructions to execute we may use slow version as well as in
8875 case function is known to be outside hot spot (this is known with
8876 feedback only). Weight the size of function by number of registers
8877 to save as it is cheap to use one or two push instructions but very
8878 slow to use many of them. */
8880 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
8881 if (node->frequency < NODE_FREQUENCY_NORMAL
8882 || (flag_branch_probabilities
8883 && node->frequency < NODE_FREQUENCY_HOT))
8884 cfun->machine->use_fast_prologue_epilogue = false;
8886 cfun->machine->use_fast_prologue_epilogue
8887 = !expensive_function_p (count);
8890 frame->save_regs_using_mov
8891 = (TARGET_PROLOGUE_USING_MOVE && cfun->machine->use_fast_prologue_epilogue
8892 /* If static stack checking is enabled and done with probes,
8893 the registers need to be saved before allocating the frame. */
8894 && flag_stack_check != STATIC_BUILTIN_STACK_CHECK);
8896 /* Skip return address. */
8897 offset = UNITS_PER_WORD;
8899 /* Skip pushed static chain. */
8900 if (ix86_static_chain_on_stack)
8901 offset += UNITS_PER_WORD;
8903 /* Skip saved base pointer. */
8904 if (frame_pointer_needed)
8905 offset += UNITS_PER_WORD;
8906 frame->hfp_save_offset = offset;
8908 /* The traditional frame pointer location is at the top of the frame. */
8909 frame->hard_frame_pointer_offset = offset;
8911 /* Register save area */
8912 offset += frame->nregs * UNITS_PER_WORD;
8913 frame->reg_save_offset = offset;
8915 /* On SEH target, registers are pushed just before the frame pointer
8918 frame->hard_frame_pointer_offset = offset;
8920 /* Align and set SSE register save area. */
8921 if (frame->nsseregs)
8923 /* The only ABI that has saved SSE registers (Win64) also has a
8924 16-byte aligned default stack, and thus we don't need to be
8925 within the re-aligned local stack frame to save them. */
8926 gcc_assert (INCOMING_STACK_BOUNDARY >= 128);
8927 offset = (offset + 16 - 1) & -16;
8928 offset += frame->nsseregs * 16;
8930 frame->sse_reg_save_offset = offset;
8932 /* The re-aligned stack starts here. Values before this point are not
8933 directly comparable with values below this point. In order to make
8934 sure that no value happens to be the same before and after, force
8935 the alignment computation below to add a non-zero value. */
8936 if (stack_realign_fp)
8937 offset = (offset + stack_alignment_needed) & -stack_alignment_needed;
8940 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
8941 offset += frame->va_arg_size;
8943 /* Align start of frame for local function. */
8944 if (stack_realign_fp
8945 || offset != frame->sse_reg_save_offset
8947 || !current_function_is_leaf
8948 || cfun->calls_alloca
8949 || ix86_current_function_calls_tls_descriptor)
8950 offset = (offset + stack_alignment_needed - 1) & -stack_alignment_needed;
8952 /* Frame pointer points here. */
8953 frame->frame_pointer_offset = offset;
8957 /* Add outgoing arguments area. Can be skipped if we eliminated
8958 all the function calls as dead code.
8959 Skipping is however impossible when function calls alloca. Alloca
8960 expander assumes that last crtl->outgoing_args_size
8961 of stack frame are unused. */
8962 if (ACCUMULATE_OUTGOING_ARGS
8963 && (!current_function_is_leaf || cfun->calls_alloca
8964 || ix86_current_function_calls_tls_descriptor))
8966 offset += crtl->outgoing_args_size;
8967 frame->outgoing_arguments_size = crtl->outgoing_args_size;
8970 frame->outgoing_arguments_size = 0;
8972 /* Align stack boundary. Only needed if we're calling another function
8974 if (!current_function_is_leaf || cfun->calls_alloca
8975 || ix86_current_function_calls_tls_descriptor)
8976 offset = (offset + preferred_alignment - 1) & -preferred_alignment;
8978 /* We've reached end of stack frame. */
8979 frame->stack_pointer_offset = offset;
8981 /* Size prologue needs to allocate. */
8982 to_allocate = offset - frame->sse_reg_save_offset;
8984 if ((!to_allocate && frame->nregs <= 1)
8985 || (TARGET_64BIT && to_allocate >= (HOST_WIDE_INT) 0x80000000))
8986 frame->save_regs_using_mov = false;
8988 if (ix86_using_red_zone ()
8989 && current_function_sp_is_unchanging
8990 && current_function_is_leaf
8991 && !ix86_current_function_calls_tls_descriptor)
8993 frame->red_zone_size = to_allocate;
8994 if (frame->save_regs_using_mov)
8995 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
8996 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
8997 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
9000 frame->red_zone_size = 0;
9001 frame->stack_pointer_offset -= frame->red_zone_size;
9003 /* The SEH frame pointer location is near the bottom of the frame.
9004 This is enforced by the fact that the difference between the
9005 stack pointer and the frame pointer is limited to 240 bytes in
9006 the unwind data structure. */
9011 /* If we can leave the frame pointer where it is, do so. Also, returns
9012 the establisher frame for __builtin_frame_address (0). */
9013 diff = frame->stack_pointer_offset - frame->hard_frame_pointer_offset;
9014 if (diff <= SEH_MAX_FRAME_SIZE
9015 && (diff > 240 || (diff & 15) != 0)
9016 && !crtl->accesses_prior_frames)
9018 /* Ideally we'd determine what portion of the local stack frame
9019 (within the constraint of the lowest 240) is most heavily used.
9020 But without that complication, simply bias the frame pointer
9021 by 128 bytes so as to maximize the amount of the local stack
9022 frame that is addressable with 8-bit offsets. */
9023 frame->hard_frame_pointer_offset = frame->stack_pointer_offset - 128;
9028 /* This is semi-inlined memory_address_length, but simplified
9029 since we know that we're always dealing with reg+offset, and
9030 to avoid having to create and discard all that rtl. */
9033 choose_baseaddr_len (unsigned int regno, HOST_WIDE_INT offset)
9039 /* EBP and R13 cannot be encoded without an offset. */
9040 len = (regno == BP_REG || regno == R13_REG);
9042 else if (IN_RANGE (offset, -128, 127))
9045 /* ESP and R12 must be encoded with a SIB byte. */
9046 if (regno == SP_REG || regno == R12_REG)
9052 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9053 The valid base registers are taken from CFUN->MACHINE->FS. */
9056 choose_baseaddr (HOST_WIDE_INT cfa_offset)
9058 const struct machine_function *m = cfun->machine;
9059 rtx base_reg = NULL;
9060 HOST_WIDE_INT base_offset = 0;
9062 if (m->use_fast_prologue_epilogue)
9064 /* Choose the base register most likely to allow the most scheduling
9065 opportunities. Generally FP is valid througout the function,
9066 while DRAP must be reloaded within the epilogue. But choose either
9067 over the SP due to increased encoding size. */
9071 base_reg = hard_frame_pointer_rtx;
9072 base_offset = m->fs.fp_offset - cfa_offset;
9074 else if (m->fs.drap_valid)
9076 base_reg = crtl->drap_reg;
9077 base_offset = 0 - cfa_offset;
9079 else if (m->fs.sp_valid)
9081 base_reg = stack_pointer_rtx;
9082 base_offset = m->fs.sp_offset - cfa_offset;
9087 HOST_WIDE_INT toffset;
9090 /* Choose the base register with the smallest address encoding.
9091 With a tie, choose FP > DRAP > SP. */
9094 base_reg = stack_pointer_rtx;
9095 base_offset = m->fs.sp_offset - cfa_offset;
9096 len = choose_baseaddr_len (STACK_POINTER_REGNUM, base_offset);
9098 if (m->fs.drap_valid)
9100 toffset = 0 - cfa_offset;
9101 tlen = choose_baseaddr_len (REGNO (crtl->drap_reg), toffset);
9104 base_reg = crtl->drap_reg;
9105 base_offset = toffset;
9111 toffset = m->fs.fp_offset - cfa_offset;
9112 tlen = choose_baseaddr_len (HARD_FRAME_POINTER_REGNUM, toffset);
9115 base_reg = hard_frame_pointer_rtx;
9116 base_offset = toffset;
9121 gcc_assert (base_reg != NULL);
9123 return plus_constant (base_reg, base_offset);
9126 /* Emit code to save registers in the prologue. */
9129 ix86_emit_save_regs (void)
9134 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
9135 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
9137 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
9138 RTX_FRAME_RELATED_P (insn) = 1;
9142 /* Emit a single register save at CFA - CFA_OFFSET. */
9145 ix86_emit_save_reg_using_mov (enum machine_mode mode, unsigned int regno,
9146 HOST_WIDE_INT cfa_offset)
9148 struct machine_function *m = cfun->machine;
9149 rtx reg = gen_rtx_REG (mode, regno);
9150 rtx mem, addr, base, insn;
9152 addr = choose_baseaddr (cfa_offset);
9153 mem = gen_frame_mem (mode, addr);
9155 /* For SSE saves, we need to indicate the 128-bit alignment. */
9156 set_mem_align (mem, GET_MODE_ALIGNMENT (mode));
9158 insn = emit_move_insn (mem, reg);
9159 RTX_FRAME_RELATED_P (insn) = 1;
9162 if (GET_CODE (base) == PLUS)
9163 base = XEXP (base, 0);
9164 gcc_checking_assert (REG_P (base));
9166 /* When saving registers into a re-aligned local stack frame, avoid
9167 any tricky guessing by dwarf2out. */
9168 if (m->fs.realigned)
9170 gcc_checking_assert (stack_realign_drap);
9172 if (regno == REGNO (crtl->drap_reg))
9174 /* A bit of a hack. We force the DRAP register to be saved in
9175 the re-aligned stack frame, which provides us with a copy
9176 of the CFA that will last past the prologue. Install it. */
9177 gcc_checking_assert (cfun->machine->fs.fp_valid);
9178 addr = plus_constant (hard_frame_pointer_rtx,
9179 cfun->machine->fs.fp_offset - cfa_offset);
9180 mem = gen_rtx_MEM (mode, addr);
9181 add_reg_note (insn, REG_CFA_DEF_CFA, mem);
9185 /* The frame pointer is a stable reference within the
9186 aligned frame. Use it. */
9187 gcc_checking_assert (cfun->machine->fs.fp_valid);
9188 addr = plus_constant (hard_frame_pointer_rtx,
9189 cfun->machine->fs.fp_offset - cfa_offset);
9190 mem = gen_rtx_MEM (mode, addr);
9191 add_reg_note (insn, REG_CFA_EXPRESSION,
9192 gen_rtx_SET (VOIDmode, mem, reg));
9196 /* The memory may not be relative to the current CFA register,
9197 which means that we may need to generate a new pattern for
9198 use by the unwind info. */
9199 else if (base != m->fs.cfa_reg)
9201 addr = plus_constant (m->fs.cfa_reg, m->fs.cfa_offset - cfa_offset);
9202 mem = gen_rtx_MEM (mode, addr);
9203 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (VOIDmode, mem, reg));
9207 /* Emit code to save registers using MOV insns.
9208 First register is stored at CFA - CFA_OFFSET. */
9210 ix86_emit_save_regs_using_mov (HOST_WIDE_INT cfa_offset)
9214 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9215 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
9217 ix86_emit_save_reg_using_mov (Pmode, regno, cfa_offset);
9218 cfa_offset -= UNITS_PER_WORD;
9222 /* Emit code to save SSE registers using MOV insns.
9223 First register is stored at CFA - CFA_OFFSET. */
9225 ix86_emit_save_sse_regs_using_mov (HOST_WIDE_INT cfa_offset)
9229 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9230 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
9232 ix86_emit_save_reg_using_mov (V4SFmode, regno, cfa_offset);
9237 static GTY(()) rtx queued_cfa_restores;
9239 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9240 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9241 Don't add the note if the previously saved value will be left untouched
9242 within stack red-zone till return, as unwinders can find the same value
9243 in the register and on the stack. */
9246 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT cfa_offset)
9248 if (!crtl->shrink_wrapped
9249 && cfa_offset <= cfun->machine->fs.red_zone_offset)
9254 add_reg_note (insn, REG_CFA_RESTORE, reg);
9255 RTX_FRAME_RELATED_P (insn) = 1;
9259 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
9262 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9265 ix86_add_queued_cfa_restore_notes (rtx insn)
9268 if (!queued_cfa_restores)
9270 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
9272 XEXP (last, 1) = REG_NOTES (insn);
9273 REG_NOTES (insn) = queued_cfa_restores;
9274 queued_cfa_restores = NULL_RTX;
9275 RTX_FRAME_RELATED_P (insn) = 1;
9278 /* Expand prologue or epilogue stack adjustment.
9279 The pattern exist to put a dependency on all ebp-based memory accesses.
9280 STYLE should be negative if instructions should be marked as frame related,
9281 zero if %r11 register is live and cannot be freely used and positive
9285 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
9286 int style, bool set_cfa)
9288 struct machine_function *m = cfun->machine;
9290 bool add_frame_related_expr = false;
9293 insn = gen_pro_epilogue_adjust_stack_si_add (dest, src, offset);
9294 else if (x86_64_immediate_operand (offset, DImode))
9295 insn = gen_pro_epilogue_adjust_stack_di_add (dest, src, offset);
9299 /* r11 is used by indirect sibcall return as well, set before the
9300 epilogue and used after the epilogue. */
9302 tmp = gen_rtx_REG (DImode, R11_REG);
9305 gcc_assert (src != hard_frame_pointer_rtx
9306 && dest != hard_frame_pointer_rtx);
9307 tmp = hard_frame_pointer_rtx;
9309 insn = emit_insn (gen_rtx_SET (DImode, tmp, offset));
9311 add_frame_related_expr = true;
9313 insn = gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp);
9316 insn = emit_insn (insn);
9318 ix86_add_queued_cfa_restore_notes (insn);
9324 gcc_assert (m->fs.cfa_reg == src);
9325 m->fs.cfa_offset += INTVAL (offset);
9326 m->fs.cfa_reg = dest;
9328 r = gen_rtx_PLUS (Pmode, src, offset);
9329 r = gen_rtx_SET (VOIDmode, dest, r);
9330 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9331 RTX_FRAME_RELATED_P (insn) = 1;
9335 RTX_FRAME_RELATED_P (insn) = 1;
9336 if (add_frame_related_expr)
9338 rtx r = gen_rtx_PLUS (Pmode, src, offset);
9339 r = gen_rtx_SET (VOIDmode, dest, r);
9340 add_reg_note (insn, REG_FRAME_RELATED_EXPR, r);
9344 if (dest == stack_pointer_rtx)
9346 HOST_WIDE_INT ooffset = m->fs.sp_offset;
9347 bool valid = m->fs.sp_valid;
9349 if (src == hard_frame_pointer_rtx)
9351 valid = m->fs.fp_valid;
9352 ooffset = m->fs.fp_offset;
9354 else if (src == crtl->drap_reg)
9356 valid = m->fs.drap_valid;
9361 /* Else there are two possibilities: SP itself, which we set
9362 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9363 taken care of this by hand along the eh_return path. */
9364 gcc_checking_assert (src == stack_pointer_rtx
9365 || offset == const0_rtx);
9368 m->fs.sp_offset = ooffset - INTVAL (offset);
9369 m->fs.sp_valid = valid;
9373 /* Find an available register to be used as dynamic realign argument
9374 pointer regsiter. Such a register will be written in prologue and
9375 used in begin of body, so it must not be
9376 1. parameter passing register.
9378 We reuse static-chain register if it is available. Otherwise, we
9379 use DI for i386 and R13 for x86-64. We chose R13 since it has
9382 Return: the regno of chosen register. */
9385 find_drap_reg (void)
9387 tree decl = cfun->decl;
9391 /* Use R13 for nested function or function need static chain.
9392 Since function with tail call may use any caller-saved
9393 registers in epilogue, DRAP must not use caller-saved
9394 register in such case. */
9395 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
9402 /* Use DI for nested function or function need static chain.
9403 Since function with tail call may use any caller-saved
9404 registers in epilogue, DRAP must not use caller-saved
9405 register in such case. */
9406 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
9409 /* Reuse static chain register if it isn't used for parameter
9411 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2)
9413 unsigned int ccvt = ix86_get_callcvt (TREE_TYPE (decl));
9414 if ((ccvt & (IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) == 0)
9421 /* Return minimum incoming stack alignment. */
9424 ix86_minimum_incoming_stack_boundary (bool sibcall)
9426 unsigned int incoming_stack_boundary;
9428 /* Prefer the one specified at command line. */
9429 if (ix86_user_incoming_stack_boundary)
9430 incoming_stack_boundary = ix86_user_incoming_stack_boundary;
9431 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9432 if -mstackrealign is used, it isn't used for sibcall check and
9433 estimated stack alignment is 128bit. */
9436 && ix86_force_align_arg_pointer
9437 && crtl->stack_alignment_estimated == 128)
9438 incoming_stack_boundary = MIN_STACK_BOUNDARY;
9440 incoming_stack_boundary = ix86_default_incoming_stack_boundary;
9442 /* Incoming stack alignment can be changed on individual functions
9443 via force_align_arg_pointer attribute. We use the smallest
9444 incoming stack boundary. */
9445 if (incoming_stack_boundary > MIN_STACK_BOUNDARY
9446 && lookup_attribute (ix86_force_align_arg_pointer_string,
9447 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
9448 incoming_stack_boundary = MIN_STACK_BOUNDARY;
9450 /* The incoming stack frame has to be aligned at least at
9451 parm_stack_boundary. */
9452 if (incoming_stack_boundary < crtl->parm_stack_boundary)
9453 incoming_stack_boundary = crtl->parm_stack_boundary;
9455 /* Stack at entrance of main is aligned by runtime. We use the
9456 smallest incoming stack boundary. */
9457 if (incoming_stack_boundary > MAIN_STACK_BOUNDARY
9458 && DECL_NAME (current_function_decl)
9459 && MAIN_NAME_P (DECL_NAME (current_function_decl))
9460 && DECL_FILE_SCOPE_P (current_function_decl))
9461 incoming_stack_boundary = MAIN_STACK_BOUNDARY;
9463 return incoming_stack_boundary;
9466 /* Update incoming stack boundary and estimated stack alignment. */
9469 ix86_update_stack_boundary (void)
9471 ix86_incoming_stack_boundary
9472 = ix86_minimum_incoming_stack_boundary (false);
9474 /* x86_64 vararg needs 16byte stack alignment for register save
9478 && crtl->stack_alignment_estimated < 128)
9479 crtl->stack_alignment_estimated = 128;
9482 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9483 needed or an rtx for DRAP otherwise. */
9486 ix86_get_drap_rtx (void)
9488 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
9489 crtl->need_drap = true;
9491 if (stack_realign_drap)
9493 /* Assign DRAP to vDRAP and returns vDRAP */
9494 unsigned int regno = find_drap_reg ();
9499 arg_ptr = gen_rtx_REG (Pmode, regno);
9500 crtl->drap_reg = arg_ptr;
9503 drap_vreg = copy_to_reg (arg_ptr);
9507 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
9510 add_reg_note (insn, REG_CFA_SET_VDRAP, drap_vreg);
9511 RTX_FRAME_RELATED_P (insn) = 1;
9519 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9522 ix86_internal_arg_pointer (void)
9524 return virtual_incoming_args_rtx;
9527 struct scratch_reg {
9532 /* Return a short-lived scratch register for use on function entry.
9533 In 32-bit mode, it is valid only after the registers are saved
9534 in the prologue. This register must be released by means of
9535 release_scratch_register_on_entry once it is dead. */
9538 get_scratch_register_on_entry (struct scratch_reg *sr)
9546 /* We always use R11 in 64-bit mode. */
9551 tree decl = current_function_decl, fntype = TREE_TYPE (decl);
9553 = lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)) != NULL_TREE;
9554 bool static_chain_p = DECL_STATIC_CHAIN (decl);
9555 int regparm = ix86_function_regparm (fntype, decl);
9557 = crtl->drap_reg ? REGNO (crtl->drap_reg) : INVALID_REGNUM;
9559 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9560 for the static chain register. */
9561 if ((regparm < 1 || (fastcall_p && !static_chain_p))
9562 && drap_regno != AX_REG)
9564 else if (regparm < 2 && drap_regno != DX_REG)
9566 /* ecx is the static chain register. */
9567 else if (regparm < 3 && !fastcall_p && !static_chain_p
9568 && drap_regno != CX_REG)
9570 else if (ix86_save_reg (BX_REG, true))
9572 /* esi is the static chain register. */
9573 else if (!(regparm == 3 && static_chain_p)
9574 && ix86_save_reg (SI_REG, true))
9576 else if (ix86_save_reg (DI_REG, true))
9580 regno = (drap_regno == AX_REG ? DX_REG : AX_REG);
9585 sr->reg = gen_rtx_REG (Pmode, regno);
9588 rtx insn = emit_insn (gen_push (sr->reg));
9589 RTX_FRAME_RELATED_P (insn) = 1;
9593 /* Release a scratch register obtained from the preceding function. */
9596 release_scratch_register_on_entry (struct scratch_reg *sr)
9600 rtx x, insn = emit_insn (gen_pop (sr->reg));
9602 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9603 RTX_FRAME_RELATED_P (insn) = 1;
9604 x = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (UNITS_PER_WORD));
9605 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
9606 add_reg_note (insn, REG_FRAME_RELATED_EXPR, x);
9610 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9612 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9615 ix86_adjust_stack_and_probe (const HOST_WIDE_INT size)
9617 /* We skip the probe for the first interval + a small dope of 4 words and
9618 probe that many bytes past the specified size to maintain a protection
9619 area at the botton of the stack. */
9620 const int dope = 4 * UNITS_PER_WORD;
9621 rtx size_rtx = GEN_INT (size), last;
9623 /* See if we have a constant small number of probes to generate. If so,
9624 that's the easy case. The run-time loop is made up of 11 insns in the
9625 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9626 for n # of intervals. */
9627 if (size <= 5 * PROBE_INTERVAL)
9629 HOST_WIDE_INT i, adjust;
9630 bool first_probe = true;
9632 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9633 values of N from 1 until it exceeds SIZE. If only one probe is
9634 needed, this will not generate any code. Then adjust and probe
9635 to PROBE_INTERVAL + SIZE. */
9636 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
9640 adjust = 2 * PROBE_INTERVAL + dope;
9641 first_probe = false;
9644 adjust = PROBE_INTERVAL;
9646 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9647 plus_constant (stack_pointer_rtx, -adjust)));
9648 emit_stack_probe (stack_pointer_rtx);
9652 adjust = size + PROBE_INTERVAL + dope;
9654 adjust = size + PROBE_INTERVAL - i;
9656 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9657 plus_constant (stack_pointer_rtx, -adjust)));
9658 emit_stack_probe (stack_pointer_rtx);
9660 /* Adjust back to account for the additional first interval. */
9661 last = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9662 plus_constant (stack_pointer_rtx,
9663 PROBE_INTERVAL + dope)));
9666 /* Otherwise, do the same as above, but in a loop. Note that we must be
9667 extra careful with variables wrapping around because we might be at
9668 the very top (or the very bottom) of the address space and we have
9669 to be able to handle this case properly; in particular, we use an
9670 equality test for the loop condition. */
9673 HOST_WIDE_INT rounded_size;
9674 struct scratch_reg sr;
9676 get_scratch_register_on_entry (&sr);
9679 /* Step 1: round SIZE to the previous multiple of the interval. */
9681 rounded_size = size & -PROBE_INTERVAL;
9684 /* Step 2: compute initial and final value of the loop counter. */
9686 /* SP = SP_0 + PROBE_INTERVAL. */
9687 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9688 plus_constant (stack_pointer_rtx,
9689 - (PROBE_INTERVAL + dope))));
9691 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9692 emit_move_insn (sr.reg, GEN_INT (-rounded_size));
9693 emit_insn (gen_rtx_SET (VOIDmode, sr.reg,
9694 gen_rtx_PLUS (Pmode, sr.reg,
9695 stack_pointer_rtx)));
9700 while (SP != LAST_ADDR)
9702 SP = SP + PROBE_INTERVAL
9706 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9707 values of N from 1 until it is equal to ROUNDED_SIZE. */
9709 emit_insn (ix86_gen_adjust_stack_and_probe (sr.reg, sr.reg, size_rtx));
9712 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9713 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9715 if (size != rounded_size)
9717 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9718 plus_constant (stack_pointer_rtx,
9719 rounded_size - size)));
9720 emit_stack_probe (stack_pointer_rtx);
9723 /* Adjust back to account for the additional first interval. */
9724 last = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9725 plus_constant (stack_pointer_rtx,
9726 PROBE_INTERVAL + dope)));
9728 release_scratch_register_on_entry (&sr);
9731 gcc_assert (cfun->machine->fs.cfa_reg != stack_pointer_rtx);
9733 /* Even if the stack pointer isn't the CFA register, we need to correctly
9734 describe the adjustments made to it, in particular differentiate the
9735 frame-related ones from the frame-unrelated ones. */
9738 rtx expr = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));
9739 XVECEXP (expr, 0, 0)
9740 = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9741 plus_constant (stack_pointer_rtx, -size));
9742 XVECEXP (expr, 0, 1)
9743 = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9744 plus_constant (stack_pointer_rtx,
9745 PROBE_INTERVAL + dope + size));
9746 add_reg_note (last, REG_FRAME_RELATED_EXPR, expr);
9747 RTX_FRAME_RELATED_P (last) = 1;
9749 cfun->machine->fs.sp_offset += size;
9752 /* Make sure nothing is scheduled before we are done. */
9753 emit_insn (gen_blockage ());
9756 /* Adjust the stack pointer up to REG while probing it. */
9759 output_adjust_stack_and_probe (rtx reg)
9761 static int labelno = 0;
9762 char loop_lab[32], end_lab[32];
9765 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
9766 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
9768 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
9770 /* Jump to END_LAB if SP == LAST_ADDR. */
9771 xops[0] = stack_pointer_rtx;
9773 output_asm_insn ("cmp%z0\t{%1, %0|%0, %1}", xops);
9774 fputs ("\tje\t", asm_out_file);
9775 assemble_name_raw (asm_out_file, end_lab);
9776 fputc ('\n', asm_out_file);
9778 /* SP = SP + PROBE_INTERVAL. */
9779 xops[1] = GEN_INT (PROBE_INTERVAL);
9780 output_asm_insn ("sub%z0\t{%1, %0|%0, %1}", xops);
9783 xops[1] = const0_rtx;
9784 output_asm_insn ("or%z0\t{%1, (%0)|DWORD PTR [%0], %1}", xops);
9786 fprintf (asm_out_file, "\tjmp\t");
9787 assemble_name_raw (asm_out_file, loop_lab);
9788 fputc ('\n', asm_out_file);
9790 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
9795 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9796 inclusive. These are offsets from the current stack pointer. */
9799 ix86_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
9801 /* See if we have a constant small number of probes to generate. If so,
9802 that's the easy case. The run-time loop is made up of 7 insns in the
9803 generic case while the compile-time loop is made up of n insns for n #
9805 if (size <= 7 * PROBE_INTERVAL)
9809 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9810 it exceeds SIZE. If only one probe is needed, this will not
9811 generate any code. Then probe at FIRST + SIZE. */
9812 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
9813 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + i)));
9815 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + size)));
9818 /* Otherwise, do the same as above, but in a loop. Note that we must be
9819 extra careful with variables wrapping around because we might be at
9820 the very top (or the very bottom) of the address space and we have
9821 to be able to handle this case properly; in particular, we use an
9822 equality test for the loop condition. */
9825 HOST_WIDE_INT rounded_size, last;
9826 struct scratch_reg sr;
9828 get_scratch_register_on_entry (&sr);
9831 /* Step 1: round SIZE to the previous multiple of the interval. */
9833 rounded_size = size & -PROBE_INTERVAL;
9836 /* Step 2: compute initial and final value of the loop counter. */
9838 /* TEST_OFFSET = FIRST. */
9839 emit_move_insn (sr.reg, GEN_INT (-first));
9841 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9842 last = first + rounded_size;
9847 while (TEST_ADDR != LAST_ADDR)
9849 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9853 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9854 until it is equal to ROUNDED_SIZE. */
9856 emit_insn (ix86_gen_probe_stack_range (sr.reg, sr.reg, GEN_INT (-last)));
9859 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9860 that SIZE is equal to ROUNDED_SIZE. */
9862 if (size != rounded_size)
9863 emit_stack_probe (plus_constant (gen_rtx_PLUS (Pmode,
9866 rounded_size - size));
9868 release_scratch_register_on_entry (&sr);
9871 /* Make sure nothing is scheduled before we are done. */
9872 emit_insn (gen_blockage ());
9875 /* Probe a range of stack addresses from REG to END, inclusive. These are
9876 offsets from the current stack pointer. */
9879 output_probe_stack_range (rtx reg, rtx end)
9881 static int labelno = 0;
9882 char loop_lab[32], end_lab[32];
9885 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
9886 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
9888 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
9890 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
9893 output_asm_insn ("cmp%z0\t{%1, %0|%0, %1}", xops);
9894 fputs ("\tje\t", asm_out_file);
9895 assemble_name_raw (asm_out_file, end_lab);
9896 fputc ('\n', asm_out_file);
9898 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
9899 xops[1] = GEN_INT (PROBE_INTERVAL);
9900 output_asm_insn ("sub%z0\t{%1, %0|%0, %1}", xops);
9902 /* Probe at TEST_ADDR. */
9903 xops[0] = stack_pointer_rtx;
9905 xops[2] = const0_rtx;
9906 output_asm_insn ("or%z0\t{%2, (%0,%1)|DWORD PTR [%0+%1], %2}", xops);
9908 fprintf (asm_out_file, "\tjmp\t");
9909 assemble_name_raw (asm_out_file, loop_lab);
9910 fputc ('\n', asm_out_file);
9912 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
9917 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
9918 to be generated in correct form. */
9920 ix86_finalize_stack_realign_flags (void)
9922 /* Check if stack realign is really needed after reload, and
9923 stores result in cfun */
9924 unsigned int incoming_stack_boundary
9925 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
9926 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
9927 unsigned int stack_realign = (incoming_stack_boundary
9928 < (current_function_is_leaf
9929 ? crtl->max_used_stack_slot_alignment
9930 : crtl->stack_alignment_needed));
9932 if (crtl->stack_realign_finalized)
9934 /* After stack_realign_needed is finalized, we can't no longer
9936 gcc_assert (crtl->stack_realign_needed == stack_realign);
9940 /* If the only reason for frame_pointer_needed is that we conservatively
9941 assumed stack realignment might be needed, but in the end nothing that
9942 needed the stack alignment had been spilled, clear frame_pointer_needed
9943 and say we don't need stack realignment. */
9946 && frame_pointer_needed
9947 && current_function_is_leaf
9948 && flag_omit_frame_pointer
9949 && current_function_sp_is_unchanging
9950 && !ix86_current_function_calls_tls_descriptor
9951 && !crtl->accesses_prior_frames
9952 && !cfun->calls_alloca
9953 && !crtl->calls_eh_return
9954 && !(flag_stack_check && STACK_CHECK_MOVING_SP)
9955 && !ix86_frame_pointer_required ()
9956 && get_frame_size () == 0
9957 && ix86_nsaved_sseregs () == 0
9958 && ix86_varargs_gpr_size + ix86_varargs_fpr_size == 0)
9960 HARD_REG_SET set_up_by_prologue, prologue_used;
9963 CLEAR_HARD_REG_SET (prologue_used);
9964 CLEAR_HARD_REG_SET (set_up_by_prologue);
9965 add_to_hard_reg_set (&set_up_by_prologue, Pmode, STACK_POINTER_REGNUM);
9966 add_to_hard_reg_set (&set_up_by_prologue, Pmode, ARG_POINTER_REGNUM);
9967 add_to_hard_reg_set (&set_up_by_prologue, Pmode,
9968 HARD_FRAME_POINTER_REGNUM);
9972 FOR_BB_INSNS (bb, insn)
9973 if (NONDEBUG_INSN_P (insn)
9974 && requires_stack_frame_p (insn, prologue_used,
9975 set_up_by_prologue))
9977 crtl->stack_realign_needed = stack_realign;
9978 crtl->stack_realign_finalized = true;
9983 frame_pointer_needed = false;
9984 stack_realign = false;
9985 crtl->max_used_stack_slot_alignment = incoming_stack_boundary;
9986 crtl->stack_alignment_needed = incoming_stack_boundary;
9987 crtl->stack_alignment_estimated = incoming_stack_boundary;
9988 if (crtl->preferred_stack_boundary > incoming_stack_boundary)
9989 crtl->preferred_stack_boundary = incoming_stack_boundary;
9990 df_finish_pass (true);
9991 df_scan_alloc (NULL);
9993 df_compute_regs_ever_live (true);
9997 crtl->stack_realign_needed = stack_realign;
9998 crtl->stack_realign_finalized = true;
10001 /* Expand the prologue into a bunch of separate insns. */
10004 ix86_expand_prologue (void)
10006 struct machine_function *m = cfun->machine;
10009 struct ix86_frame frame;
10010 HOST_WIDE_INT allocate;
10011 bool int_registers_saved;
10012 bool sse_registers_saved;
10014 ix86_finalize_stack_realign_flags ();
10016 /* DRAP should not coexist with stack_realign_fp */
10017 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
10019 memset (&m->fs, 0, sizeof (m->fs));
10021 /* Initialize CFA state for before the prologue. */
10022 m->fs.cfa_reg = stack_pointer_rtx;
10023 m->fs.cfa_offset = INCOMING_FRAME_SP_OFFSET;
10025 /* Track SP offset to the CFA. We continue tracking this after we've
10026 swapped the CFA register away from SP. In the case of re-alignment
10027 this is fudged; we're interested to offsets within the local frame. */
10028 m->fs.sp_offset = INCOMING_FRAME_SP_OFFSET;
10029 m->fs.sp_valid = true;
10031 ix86_compute_frame_layout (&frame);
10033 if (!TARGET_64BIT && ix86_function_ms_hook_prologue (current_function_decl))
10035 /* We should have already generated an error for any use of
10036 ms_hook on a nested function. */
10037 gcc_checking_assert (!ix86_static_chain_on_stack);
10039 /* Check if profiling is active and we shall use profiling before
10040 prologue variant. If so sorry. */
10041 if (crtl->profile && flag_fentry != 0)
10042 sorry ("ms_hook_prologue attribute isn%'t compatible "
10043 "with -mfentry for 32-bit");
10045 /* In ix86_asm_output_function_label we emitted:
10046 8b ff movl.s %edi,%edi
10048 8b ec movl.s %esp,%ebp
10050 This matches the hookable function prologue in Win32 API
10051 functions in Microsoft Windows XP Service Pack 2 and newer.
10052 Wine uses this to enable Windows apps to hook the Win32 API
10053 functions provided by Wine.
10055 What that means is that we've already set up the frame pointer. */
10057 if (frame_pointer_needed
10058 && !(crtl->drap_reg && crtl->stack_realign_needed))
10062 /* We've decided to use the frame pointer already set up.
10063 Describe this to the unwinder by pretending that both
10064 push and mov insns happen right here.
10066 Putting the unwind info here at the end of the ms_hook
10067 is done so that we can make absolutely certain we get
10068 the required byte sequence at the start of the function,
10069 rather than relying on an assembler that can produce
10070 the exact encoding required.
10072 However it does mean (in the unpatched case) that we have
10073 a 1 insn window where the asynchronous unwind info is
10074 incorrect. However, if we placed the unwind info at
10075 its correct location we would have incorrect unwind info
10076 in the patched case. Which is probably all moot since
10077 I don't expect Wine generates dwarf2 unwind info for the
10078 system libraries that use this feature. */
10080 insn = emit_insn (gen_blockage ());
10082 push = gen_push (hard_frame_pointer_rtx);
10083 mov = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10084 stack_pointer_rtx);
10085 RTX_FRAME_RELATED_P (push) = 1;
10086 RTX_FRAME_RELATED_P (mov) = 1;
10088 RTX_FRAME_RELATED_P (insn) = 1;
10089 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
10090 gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, push, mov)));
10092 /* Note that gen_push incremented m->fs.cfa_offset, even
10093 though we didn't emit the push insn here. */
10094 m->fs.cfa_reg = hard_frame_pointer_rtx;
10095 m->fs.fp_offset = m->fs.cfa_offset;
10096 m->fs.fp_valid = true;
10100 /* The frame pointer is not needed so pop %ebp again.
10101 This leaves us with a pristine state. */
10102 emit_insn (gen_pop (hard_frame_pointer_rtx));
10106 /* The first insn of a function that accepts its static chain on the
10107 stack is to push the register that would be filled in by a direct
10108 call. This insn will be skipped by the trampoline. */
10109 else if (ix86_static_chain_on_stack)
10111 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
10112 emit_insn (gen_blockage ());
10114 /* We don't want to interpret this push insn as a register save,
10115 only as a stack adjustment. The real copy of the register as
10116 a save will be done later, if needed. */
10117 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
10118 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
10119 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
10120 RTX_FRAME_RELATED_P (insn) = 1;
10123 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10124 of DRAP is needed and stack realignment is really needed after reload */
10125 if (stack_realign_drap)
10127 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
10129 /* Only need to push parameter pointer reg if it is caller saved. */
10130 if (!call_used_regs[REGNO (crtl->drap_reg)])
10132 /* Push arg pointer reg */
10133 insn = emit_insn (gen_push (crtl->drap_reg));
10134 RTX_FRAME_RELATED_P (insn) = 1;
10137 /* Grab the argument pointer. */
10138 t = plus_constant (stack_pointer_rtx, m->fs.sp_offset);
10139 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, t));
10140 RTX_FRAME_RELATED_P (insn) = 1;
10141 m->fs.cfa_reg = crtl->drap_reg;
10142 m->fs.cfa_offset = 0;
10144 /* Align the stack. */
10145 insn = emit_insn (ix86_gen_andsp (stack_pointer_rtx,
10147 GEN_INT (-align_bytes)));
10148 RTX_FRAME_RELATED_P (insn) = 1;
10150 /* Replicate the return address on the stack so that return
10151 address can be reached via (argp - 1) slot. This is needed
10152 to implement macro RETURN_ADDR_RTX and intrinsic function
10153 expand_builtin_return_addr etc. */
10154 t = plus_constant (crtl->drap_reg, -UNITS_PER_WORD);
10155 t = gen_frame_mem (Pmode, t);
10156 insn = emit_insn (gen_push (t));
10157 RTX_FRAME_RELATED_P (insn) = 1;
10159 /* For the purposes of frame and register save area addressing,
10160 we've started over with a new frame. */
10161 m->fs.sp_offset = INCOMING_FRAME_SP_OFFSET;
10162 m->fs.realigned = true;
10165 int_registers_saved = (frame.nregs == 0);
10166 sse_registers_saved = (frame.nsseregs == 0);
10168 if (frame_pointer_needed && !m->fs.fp_valid)
10170 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10171 slower on all targets. Also sdb doesn't like it. */
10172 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
10173 RTX_FRAME_RELATED_P (insn) = 1;
10175 /* Push registers now, before setting the frame pointer
10177 if (!int_registers_saved
10179 && !frame.save_regs_using_mov)
10181 ix86_emit_save_regs ();
10182 int_registers_saved = true;
10183 gcc_assert (m->fs.sp_offset == frame.reg_save_offset);
10186 if (m->fs.sp_offset == frame.hard_frame_pointer_offset)
10188 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
10189 RTX_FRAME_RELATED_P (insn) = 1;
10191 if (m->fs.cfa_reg == stack_pointer_rtx)
10192 m->fs.cfa_reg = hard_frame_pointer_rtx;
10193 m->fs.fp_offset = m->fs.sp_offset;
10194 m->fs.fp_valid = true;
10198 if (!int_registers_saved)
10200 /* If saving registers via PUSH, do so now. */
10201 if (!frame.save_regs_using_mov)
10203 ix86_emit_save_regs ();
10204 int_registers_saved = true;
10205 gcc_assert (m->fs.sp_offset == frame.reg_save_offset);
10208 /* When using red zone we may start register saving before allocating
10209 the stack frame saving one cycle of the prologue. However, avoid
10210 doing this if we have to probe the stack; at least on x86_64 the
10211 stack probe can turn into a call that clobbers a red zone location. */
10212 else if (ix86_using_red_zone ()
10213 && (! TARGET_STACK_PROBE
10214 || frame.stack_pointer_offset < CHECK_STACK_LIMIT))
10216 ix86_emit_save_regs_using_mov (frame.reg_save_offset);
10217 int_registers_saved = true;
10221 if (stack_realign_fp)
10223 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
10224 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
10226 /* The computation of the size of the re-aligned stack frame means
10227 that we must allocate the size of the register save area before
10228 performing the actual alignment. Otherwise we cannot guarantee
10229 that there's enough storage above the realignment point. */
10230 if (m->fs.sp_offset != frame.sse_reg_save_offset)
10231 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10232 GEN_INT (m->fs.sp_offset
10233 - frame.sse_reg_save_offset),
10236 /* Align the stack. */
10237 insn = emit_insn (ix86_gen_andsp (stack_pointer_rtx,
10239 GEN_INT (-align_bytes)));
10241 /* For the purposes of register save area addressing, the stack
10242 pointer is no longer valid. As for the value of sp_offset,
10243 see ix86_compute_frame_layout, which we need to match in order
10244 to pass verification of stack_pointer_offset at the end. */
10245 m->fs.sp_offset = (m->fs.sp_offset + align_bytes) & -align_bytes;
10246 m->fs.sp_valid = false;
10249 allocate = frame.stack_pointer_offset - m->fs.sp_offset;
10251 if (flag_stack_usage_info)
10253 /* We start to count from ARG_POINTER. */
10254 HOST_WIDE_INT stack_size = frame.stack_pointer_offset;
10256 /* If it was realigned, take into account the fake frame. */
10257 if (stack_realign_drap)
10259 if (ix86_static_chain_on_stack)
10260 stack_size += UNITS_PER_WORD;
10262 if (!call_used_regs[REGNO (crtl->drap_reg)])
10263 stack_size += UNITS_PER_WORD;
10265 /* This over-estimates by 1 minimal-stack-alignment-unit but
10266 mitigates that by counting in the new return address slot. */
10267 current_function_dynamic_stack_size
10268 += crtl->stack_alignment_needed / BITS_PER_UNIT;
10271 current_function_static_stack_size = stack_size;
10274 /* On SEH target with very large frame size, allocate an area to save
10275 SSE registers (as the very large allocation won't be described). */
10277 && frame.stack_pointer_offset > SEH_MAX_FRAME_SIZE
10278 && !sse_registers_saved)
10280 HOST_WIDE_INT sse_size =
10281 frame.sse_reg_save_offset - frame.reg_save_offset;
10283 gcc_assert (int_registers_saved);
10285 /* No need to do stack checking as the area will be immediately
10287 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10288 GEN_INT (-sse_size), -1,
10289 m->fs.cfa_reg == stack_pointer_rtx);
10290 allocate -= sse_size;
10291 ix86_emit_save_sse_regs_using_mov (frame.sse_reg_save_offset);
10292 sse_registers_saved = true;
10295 /* The stack has already been decremented by the instruction calling us
10296 so probe if the size is non-negative to preserve the protection area. */
10297 if (allocate >= 0 && flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
10299 /* We expect the registers to be saved when probes are used. */
10300 gcc_assert (int_registers_saved);
10302 if (STACK_CHECK_MOVING_SP)
10304 ix86_adjust_stack_and_probe (allocate);
10309 HOST_WIDE_INT size = allocate;
10311 if (TARGET_64BIT && size >= (HOST_WIDE_INT) 0x80000000)
10312 size = 0x80000000 - STACK_CHECK_PROTECT - 1;
10314 if (TARGET_STACK_PROBE)
10315 ix86_emit_probe_stack_range (0, size + STACK_CHECK_PROTECT);
10317 ix86_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
10323 else if (!ix86_target_stack_probe ()
10324 || frame.stack_pointer_offset < CHECK_STACK_LIMIT)
10326 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10327 GEN_INT (-allocate), -1,
10328 m->fs.cfa_reg == stack_pointer_rtx);
10332 rtx eax = gen_rtx_REG (Pmode, AX_REG);
10334 rtx (*adjust_stack_insn)(rtx, rtx, rtx);
10336 bool eax_live = false;
10337 bool r10_live = false;
10340 r10_live = (DECL_STATIC_CHAIN (current_function_decl) != 0);
10341 if (!TARGET_64BIT_MS_ABI)
10342 eax_live = ix86_eax_live_at_start_p ();
10346 emit_insn (gen_push (eax));
10347 allocate -= UNITS_PER_WORD;
10351 r10 = gen_rtx_REG (Pmode, R10_REG);
10352 emit_insn (gen_push (r10));
10353 allocate -= UNITS_PER_WORD;
10356 emit_move_insn (eax, GEN_INT (allocate));
10357 emit_insn (ix86_gen_allocate_stack_worker (eax, eax));
10359 /* Use the fact that AX still contains ALLOCATE. */
10360 adjust_stack_insn = (TARGET_64BIT
10361 ? gen_pro_epilogue_adjust_stack_di_sub
10362 : gen_pro_epilogue_adjust_stack_si_sub);
10364 insn = emit_insn (adjust_stack_insn (stack_pointer_rtx,
10365 stack_pointer_rtx, eax));
10367 /* Note that SEH directives need to continue tracking the stack
10368 pointer even after the frame pointer has been set up. */
10369 if (m->fs.cfa_reg == stack_pointer_rtx || TARGET_SEH)
10371 if (m->fs.cfa_reg == stack_pointer_rtx)
10372 m->fs.cfa_offset += allocate;
10374 RTX_FRAME_RELATED_P (insn) = 1;
10375 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
10376 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10377 plus_constant (stack_pointer_rtx,
10380 m->fs.sp_offset += allocate;
10382 if (r10_live && eax_live)
10384 t = choose_baseaddr (m->fs.sp_offset - allocate);
10385 emit_move_insn (r10, gen_frame_mem (Pmode, t));
10386 t = choose_baseaddr (m->fs.sp_offset - allocate - UNITS_PER_WORD);
10387 emit_move_insn (eax, gen_frame_mem (Pmode, t));
10389 else if (eax_live || r10_live)
10391 t = choose_baseaddr (m->fs.sp_offset - allocate);
10392 emit_move_insn ((eax_live ? eax : r10), gen_frame_mem (Pmode, t));
10395 gcc_assert (m->fs.sp_offset == frame.stack_pointer_offset);
10397 /* If we havn't already set up the frame pointer, do so now. */
10398 if (frame_pointer_needed && !m->fs.fp_valid)
10400 insn = ix86_gen_add3 (hard_frame_pointer_rtx, stack_pointer_rtx,
10401 GEN_INT (frame.stack_pointer_offset
10402 - frame.hard_frame_pointer_offset));
10403 insn = emit_insn (insn);
10404 RTX_FRAME_RELATED_P (insn) = 1;
10405 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
10407 if (m->fs.cfa_reg == stack_pointer_rtx)
10408 m->fs.cfa_reg = hard_frame_pointer_rtx;
10409 m->fs.fp_offset = frame.hard_frame_pointer_offset;
10410 m->fs.fp_valid = true;
10413 if (!int_registers_saved)
10414 ix86_emit_save_regs_using_mov (frame.reg_save_offset);
10415 if (!sse_registers_saved)
10416 ix86_emit_save_sse_regs_using_mov (frame.sse_reg_save_offset);
10418 pic_reg_used = false;
10419 if (pic_offset_table_rtx
10420 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
10423 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
10425 if (alt_pic_reg_used != INVALID_REGNUM)
10426 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
10428 pic_reg_used = true;
10435 if (ix86_cmodel == CM_LARGE_PIC)
10437 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
10438 rtx label = gen_label_rtx ();
10439 emit_label (label);
10440 LABEL_PRESERVE_P (label) = 1;
10441 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
10442 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
10443 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
10444 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
10445 pic_offset_table_rtx, tmp_reg));
10448 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
10452 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
10453 RTX_FRAME_RELATED_P (insn) = 1;
10454 add_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL_RTX);
10458 /* In the pic_reg_used case, make sure that the got load isn't deleted
10459 when mcount needs it. Blockage to avoid call movement across mcount
10460 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10462 if (crtl->profile && !flag_fentry && pic_reg_used)
10463 emit_insn (gen_prologue_use (pic_offset_table_rtx));
10465 if (crtl->drap_reg && !crtl->stack_realign_needed)
10467 /* vDRAP is setup but after reload it turns out stack realign
10468 isn't necessary, here we will emit prologue to setup DRAP
10469 without stack realign adjustment */
10470 t = choose_baseaddr (0);
10471 emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, t));
10474 /* Prevent instructions from being scheduled into register save push
10475 sequence when access to the redzone area is done through frame pointer.
10476 The offset between the frame pointer and the stack pointer is calculated
10477 relative to the value of the stack pointer at the end of the function
10478 prologue, and moving instructions that access redzone area via frame
10479 pointer inside push sequence violates this assumption. */
10480 if (frame_pointer_needed && frame.red_zone_size)
10481 emit_insn (gen_memory_blockage ());
10483 /* Emit cld instruction if stringops are used in the function. */
10484 if (TARGET_CLD && ix86_current_function_needs_cld)
10485 emit_insn (gen_cld ());
10487 /* SEH requires that the prologue end within 256 bytes of the start of
10488 the function. Prevent instruction schedules that would extend that.
10489 Further, prevent alloca modifications to the stack pointer from being
10490 combined with prologue modifications. */
10492 emit_insn (gen_prologue_use (stack_pointer_rtx));
10495 /* Emit code to restore REG using a POP insn. */
10498 ix86_emit_restore_reg_using_pop (rtx reg)
10500 struct machine_function *m = cfun->machine;
10501 rtx insn = emit_insn (gen_pop (reg));
10503 ix86_add_cfa_restore_note (insn, reg, m->fs.sp_offset);
10504 m->fs.sp_offset -= UNITS_PER_WORD;
10506 if (m->fs.cfa_reg == crtl->drap_reg
10507 && REGNO (reg) == REGNO (crtl->drap_reg))
10509 /* Previously we'd represented the CFA as an expression
10510 like *(%ebp - 8). We've just popped that value from
10511 the stack, which means we need to reset the CFA to
10512 the drap register. This will remain until we restore
10513 the stack pointer. */
10514 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
10515 RTX_FRAME_RELATED_P (insn) = 1;
10517 /* This means that the DRAP register is valid for addressing too. */
10518 m->fs.drap_valid = true;
10522 if (m->fs.cfa_reg == stack_pointer_rtx)
10524 rtx x = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
10525 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
10526 add_reg_note (insn, REG_CFA_ADJUST_CFA, x);
10527 RTX_FRAME_RELATED_P (insn) = 1;
10529 m->fs.cfa_offset -= UNITS_PER_WORD;
10532 /* When the frame pointer is the CFA, and we pop it, we are
10533 swapping back to the stack pointer as the CFA. This happens
10534 for stack frames that don't allocate other data, so we assume
10535 the stack pointer is now pointing at the return address, i.e.
10536 the function entry state, which makes the offset be 1 word. */
10537 if (reg == hard_frame_pointer_rtx)
10539 m->fs.fp_valid = false;
10540 if (m->fs.cfa_reg == hard_frame_pointer_rtx)
10542 m->fs.cfa_reg = stack_pointer_rtx;
10543 m->fs.cfa_offset -= UNITS_PER_WORD;
10545 add_reg_note (insn, REG_CFA_DEF_CFA,
10546 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
10547 GEN_INT (m->fs.cfa_offset)));
10548 RTX_FRAME_RELATED_P (insn) = 1;
10553 /* Emit code to restore saved registers using POP insns. */
10556 ix86_emit_restore_regs_using_pop (void)
10558 unsigned int regno;
10560 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
10561 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
10562 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno));
10565 /* Emit code and notes for the LEAVE instruction. */
10568 ix86_emit_leave (void)
10570 struct machine_function *m = cfun->machine;
10571 rtx insn = emit_insn (ix86_gen_leave ());
10573 ix86_add_queued_cfa_restore_notes (insn);
10575 gcc_assert (m->fs.fp_valid);
10576 m->fs.sp_valid = true;
10577 m->fs.sp_offset = m->fs.fp_offset - UNITS_PER_WORD;
10578 m->fs.fp_valid = false;
10580 if (m->fs.cfa_reg == hard_frame_pointer_rtx)
10582 m->fs.cfa_reg = stack_pointer_rtx;
10583 m->fs.cfa_offset = m->fs.sp_offset;
10585 add_reg_note (insn, REG_CFA_DEF_CFA,
10586 plus_constant (stack_pointer_rtx, m->fs.sp_offset));
10587 RTX_FRAME_RELATED_P (insn) = 1;
10589 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx,
10593 /* Emit code to restore saved registers using MOV insns.
10594 First register is restored from CFA - CFA_OFFSET. */
10596 ix86_emit_restore_regs_using_mov (HOST_WIDE_INT cfa_offset,
10597 bool maybe_eh_return)
10599 struct machine_function *m = cfun->machine;
10600 unsigned int regno;
10602 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
10603 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
10605 rtx reg = gen_rtx_REG (Pmode, regno);
10608 mem = choose_baseaddr (cfa_offset);
10609 mem = gen_frame_mem (Pmode, mem);
10610 insn = emit_move_insn (reg, mem);
10612 if (m->fs.cfa_reg == crtl->drap_reg && regno == REGNO (crtl->drap_reg))
10614 /* Previously we'd represented the CFA as an expression
10615 like *(%ebp - 8). We've just popped that value from
10616 the stack, which means we need to reset the CFA to
10617 the drap register. This will remain until we restore
10618 the stack pointer. */
10619 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
10620 RTX_FRAME_RELATED_P (insn) = 1;
10622 /* This means that the DRAP register is valid for addressing. */
10623 m->fs.drap_valid = true;
10626 ix86_add_cfa_restore_note (NULL_RTX, reg, cfa_offset);
10628 cfa_offset -= UNITS_PER_WORD;
10632 /* Emit code to restore saved registers using MOV insns.
10633 First register is restored from CFA - CFA_OFFSET. */
10635 ix86_emit_restore_sse_regs_using_mov (HOST_WIDE_INT cfa_offset,
10636 bool maybe_eh_return)
10638 unsigned int regno;
10640 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
10641 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
10643 rtx reg = gen_rtx_REG (V4SFmode, regno);
10646 mem = choose_baseaddr (cfa_offset);
10647 mem = gen_rtx_MEM (V4SFmode, mem);
10648 set_mem_align (mem, 128);
10649 emit_move_insn (reg, mem);
10651 ix86_add_cfa_restore_note (NULL_RTX, reg, cfa_offset);
10657 /* Emit vzeroupper if needed. */
10660 ix86_maybe_emit_epilogue_vzeroupper (void)
10662 if (TARGET_VZEROUPPER
10663 && !TREE_THIS_VOLATILE (cfun->decl)
10664 && !cfun->machine->caller_return_avx256_p)
10665 emit_insn (gen_avx_vzeroupper (GEN_INT (call_no_avx256)));
10668 /* Restore function stack, frame, and registers. */
10671 ix86_expand_epilogue (int style)
10673 struct machine_function *m = cfun->machine;
10674 struct machine_frame_state frame_state_save = m->fs;
10675 struct ix86_frame frame;
10676 bool restore_regs_via_mov;
10679 ix86_finalize_stack_realign_flags ();
10680 ix86_compute_frame_layout (&frame);
10682 m->fs.sp_valid = (!frame_pointer_needed
10683 || (current_function_sp_is_unchanging
10684 && !stack_realign_fp));
10685 gcc_assert (!m->fs.sp_valid
10686 || m->fs.sp_offset == frame.stack_pointer_offset);
10688 /* The FP must be valid if the frame pointer is present. */
10689 gcc_assert (frame_pointer_needed == m->fs.fp_valid);
10690 gcc_assert (!m->fs.fp_valid
10691 || m->fs.fp_offset == frame.hard_frame_pointer_offset);
10693 /* We must have *some* valid pointer to the stack frame. */
10694 gcc_assert (m->fs.sp_valid || m->fs.fp_valid);
10696 /* The DRAP is never valid at this point. */
10697 gcc_assert (!m->fs.drap_valid);
10699 /* See the comment about red zone and frame
10700 pointer usage in ix86_expand_prologue. */
10701 if (frame_pointer_needed && frame.red_zone_size)
10702 emit_insn (gen_memory_blockage ());
10704 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
10705 gcc_assert (!using_drap || m->fs.cfa_reg == crtl->drap_reg);
10707 /* Determine the CFA offset of the end of the red-zone. */
10708 m->fs.red_zone_offset = 0;
10709 if (ix86_using_red_zone () && crtl->args.pops_args < 65536)
10711 /* The red-zone begins below the return address. */
10712 m->fs.red_zone_offset = RED_ZONE_SIZE + UNITS_PER_WORD;
10714 /* When the register save area is in the aligned portion of
10715 the stack, determine the maximum runtime displacement that
10716 matches up with the aligned frame. */
10717 if (stack_realign_drap)
10718 m->fs.red_zone_offset -= (crtl->stack_alignment_needed / BITS_PER_UNIT
10722 /* Special care must be taken for the normal return case of a function
10723 using eh_return: the eax and edx registers are marked as saved, but
10724 not restored along this path. Adjust the save location to match. */
10725 if (crtl->calls_eh_return && style != 2)
10726 frame.reg_save_offset -= 2 * UNITS_PER_WORD;
10728 /* EH_RETURN requires the use of moves to function properly. */
10729 if (crtl->calls_eh_return)
10730 restore_regs_via_mov = true;
10731 /* SEH requires the use of pops to identify the epilogue. */
10732 else if (TARGET_SEH)
10733 restore_regs_via_mov = false;
10734 /* If we're only restoring one register and sp is not valid then
10735 using a move instruction to restore the register since it's
10736 less work than reloading sp and popping the register. */
10737 else if (!m->fs.sp_valid && frame.nregs <= 1)
10738 restore_regs_via_mov = true;
10739 else if (TARGET_EPILOGUE_USING_MOVE
10740 && cfun->machine->use_fast_prologue_epilogue
10741 && (frame.nregs > 1
10742 || m->fs.sp_offset != frame.reg_save_offset))
10743 restore_regs_via_mov = true;
10744 else if (frame_pointer_needed
10746 && m->fs.sp_offset != frame.reg_save_offset)
10747 restore_regs_via_mov = true;
10748 else if (frame_pointer_needed
10749 && TARGET_USE_LEAVE
10750 && cfun->machine->use_fast_prologue_epilogue
10751 && frame.nregs == 1)
10752 restore_regs_via_mov = true;
10754 restore_regs_via_mov = false;
10756 if (restore_regs_via_mov || frame.nsseregs)
10758 /* Ensure that the entire register save area is addressable via
10759 the stack pointer, if we will restore via sp. */
10761 && m->fs.sp_offset > 0x7fffffff
10762 && !(m->fs.fp_valid || m->fs.drap_valid)
10763 && (frame.nsseregs + frame.nregs) != 0)
10765 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10766 GEN_INT (m->fs.sp_offset
10767 - frame.sse_reg_save_offset),
10769 m->fs.cfa_reg == stack_pointer_rtx);
10773 /* If there are any SSE registers to restore, then we have to do it
10774 via moves, since there's obviously no pop for SSE regs. */
10775 if (frame.nsseregs)
10776 ix86_emit_restore_sse_regs_using_mov (frame.sse_reg_save_offset,
10779 if (restore_regs_via_mov)
10784 ix86_emit_restore_regs_using_mov (frame.reg_save_offset, style == 2);
10786 /* eh_return epilogues need %ecx added to the stack pointer. */
10789 rtx insn, sa = EH_RETURN_STACKADJ_RTX;
10791 /* Stack align doesn't work with eh_return. */
10792 gcc_assert (!stack_realign_drap);
10793 /* Neither does regparm nested functions. */
10794 gcc_assert (!ix86_static_chain_on_stack);
10796 if (frame_pointer_needed)
10798 t = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
10799 t = plus_constant (t, m->fs.fp_offset - UNITS_PER_WORD);
10800 emit_insn (gen_rtx_SET (VOIDmode, sa, t));
10802 t = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
10803 insn = emit_move_insn (hard_frame_pointer_rtx, t);
10805 /* Note that we use SA as a temporary CFA, as the return
10806 address is at the proper place relative to it. We
10807 pretend this happens at the FP restore insn because
10808 prior to this insn the FP would be stored at the wrong
10809 offset relative to SA, and after this insn we have no
10810 other reasonable register to use for the CFA. We don't
10811 bother resetting the CFA to the SP for the duration of
10812 the return insn. */
10813 add_reg_note (insn, REG_CFA_DEF_CFA,
10814 plus_constant (sa, UNITS_PER_WORD));
10815 ix86_add_queued_cfa_restore_notes (insn);
10816 add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
10817 RTX_FRAME_RELATED_P (insn) = 1;
10819 m->fs.cfa_reg = sa;
10820 m->fs.cfa_offset = UNITS_PER_WORD;
10821 m->fs.fp_valid = false;
10823 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
10824 const0_rtx, style, false);
10828 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
10829 t = plus_constant (t, m->fs.sp_offset - UNITS_PER_WORD);
10830 insn = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, t));
10831 ix86_add_queued_cfa_restore_notes (insn);
10833 gcc_assert (m->fs.cfa_reg == stack_pointer_rtx);
10834 if (m->fs.cfa_offset != UNITS_PER_WORD)
10836 m->fs.cfa_offset = UNITS_PER_WORD;
10837 add_reg_note (insn, REG_CFA_DEF_CFA,
10838 plus_constant (stack_pointer_rtx,
10840 RTX_FRAME_RELATED_P (insn) = 1;
10843 m->fs.sp_offset = UNITS_PER_WORD;
10844 m->fs.sp_valid = true;
10849 /* SEH requires that the function end with (1) a stack adjustment
10850 if necessary, (2) a sequence of pops, and (3) a return or
10851 jump instruction. Prevent insns from the function body from
10852 being scheduled into this sequence. */
10855 /* Prevent a catch region from being adjacent to the standard
10856 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
10857 several other flags that would be interesting to test are
10859 if (flag_non_call_exceptions)
10860 emit_insn (gen_nops (const1_rtx));
10862 emit_insn (gen_blockage ());
10865 /* First step is to deallocate the stack frame so that we can
10866 pop the registers. Also do it on SEH target for very large
10867 frame as the emitted instructions aren't allowed by the ABI in
10869 if (!m->fs.sp_valid
10871 && (m->fs.sp_offset - frame.reg_save_offset
10872 >= SEH_MAX_FRAME_SIZE)))
10874 pro_epilogue_adjust_stack (stack_pointer_rtx, hard_frame_pointer_rtx,
10875 GEN_INT (m->fs.fp_offset
10876 - frame.reg_save_offset),
10879 else if (m->fs.sp_offset != frame.reg_save_offset)
10881 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10882 GEN_INT (m->fs.sp_offset
10883 - frame.reg_save_offset),
10885 m->fs.cfa_reg == stack_pointer_rtx);
10888 ix86_emit_restore_regs_using_pop ();
10891 /* If we used a stack pointer and haven't already got rid of it,
10893 if (m->fs.fp_valid)
10895 /* If the stack pointer is valid and pointing at the frame
10896 pointer store address, then we only need a pop. */
10897 if (m->fs.sp_valid && m->fs.sp_offset == frame.hfp_save_offset)
10898 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx);
10899 /* Leave results in shorter dependency chains on CPUs that are
10900 able to grok it fast. */
10901 else if (TARGET_USE_LEAVE
10902 || optimize_function_for_size_p (cfun)
10903 || !cfun->machine->use_fast_prologue_epilogue)
10904 ix86_emit_leave ();
10907 pro_epilogue_adjust_stack (stack_pointer_rtx,
10908 hard_frame_pointer_rtx,
10909 const0_rtx, style, !using_drap);
10910 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx);
10916 int param_ptr_offset = UNITS_PER_WORD;
10919 gcc_assert (stack_realign_drap);
10921 if (ix86_static_chain_on_stack)
10922 param_ptr_offset += UNITS_PER_WORD;
10923 if (!call_used_regs[REGNO (crtl->drap_reg)])
10924 param_ptr_offset += UNITS_PER_WORD;
10926 insn = emit_insn (gen_rtx_SET
10927 (VOIDmode, stack_pointer_rtx,
10928 gen_rtx_PLUS (Pmode,
10930 GEN_INT (-param_ptr_offset))));
10931 m->fs.cfa_reg = stack_pointer_rtx;
10932 m->fs.cfa_offset = param_ptr_offset;
10933 m->fs.sp_offset = param_ptr_offset;
10934 m->fs.realigned = false;
10936 add_reg_note (insn, REG_CFA_DEF_CFA,
10937 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
10938 GEN_INT (param_ptr_offset)));
10939 RTX_FRAME_RELATED_P (insn) = 1;
10941 if (!call_used_regs[REGNO (crtl->drap_reg)])
10942 ix86_emit_restore_reg_using_pop (crtl->drap_reg);
10945 /* At this point the stack pointer must be valid, and we must have
10946 restored all of the registers. We may not have deallocated the
10947 entire stack frame. We've delayed this until now because it may
10948 be possible to merge the local stack deallocation with the
10949 deallocation forced by ix86_static_chain_on_stack. */
10950 gcc_assert (m->fs.sp_valid);
10951 gcc_assert (!m->fs.fp_valid);
10952 gcc_assert (!m->fs.realigned);
10953 if (m->fs.sp_offset != UNITS_PER_WORD)
10955 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10956 GEN_INT (m->fs.sp_offset - UNITS_PER_WORD),
10960 ix86_add_queued_cfa_restore_notes (get_last_insn ());
10962 /* Sibcall epilogues don't want a return instruction. */
10965 m->fs = frame_state_save;
10969 /* Emit vzeroupper if needed. */
10970 ix86_maybe_emit_epilogue_vzeroupper ();
10972 if (crtl->args.pops_args && crtl->args.size)
10974 rtx popc = GEN_INT (crtl->args.pops_args);
10976 /* i386 can only pop 64K bytes. If asked to pop more, pop return
10977 address, do explicit add, and jump indirectly to the caller. */
10979 if (crtl->args.pops_args >= 65536)
10981 rtx ecx = gen_rtx_REG (SImode, CX_REG);
10984 /* There is no "pascal" calling convention in any 64bit ABI. */
10985 gcc_assert (!TARGET_64BIT);
10987 insn = emit_insn (gen_pop (ecx));
10988 m->fs.cfa_offset -= UNITS_PER_WORD;
10989 m->fs.sp_offset -= UNITS_PER_WORD;
10991 add_reg_note (insn, REG_CFA_ADJUST_CFA,
10992 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
10993 add_reg_note (insn, REG_CFA_REGISTER,
10994 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
10995 RTX_FRAME_RELATED_P (insn) = 1;
10997 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
10999 emit_jump_insn (gen_simple_return_indirect_internal (ecx));
11002 emit_jump_insn (gen_simple_return_pop_internal (popc));
11005 emit_jump_insn (gen_simple_return_internal ());
11007 /* Restore the state back to the state from the prologue,
11008 so that it's correct for the next epilogue. */
11009 m->fs = frame_state_save;
11012 /* Reset from the function's potential modifications. */
11015 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
11016 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11018 if (pic_offset_table_rtx)
11019 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
11021 /* Mach-O doesn't support labels at the end of objects, so if
11022 it looks like we might want one, insert a NOP. */
11024 rtx insn = get_last_insn ();
11025 rtx deleted_debug_label = NULL_RTX;
11028 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
11030 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11031 notes only, instead set their CODE_LABEL_NUMBER to -1,
11032 otherwise there would be code generation differences
11033 in between -g and -g0. */
11034 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
11035 deleted_debug_label = insn;
11036 insn = PREV_INSN (insn);
11041 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
11042 fputs ("\tnop\n", file);
11043 else if (deleted_debug_label)
11044 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
11045 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
11046 CODE_LABEL_NUMBER (insn) = -1;
11052 /* Return a scratch register to use in the split stack prologue. The
11053 split stack prologue is used for -fsplit-stack. It is the first
11054 instructions in the function, even before the regular prologue.
11055 The scratch register can be any caller-saved register which is not
11056 used for parameters or for the static chain. */
11058 static unsigned int
11059 split_stack_prologue_scratch_regno (void)
11068 is_fastcall = (lookup_attribute ("fastcall",
11069 TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl)))
11071 regparm = ix86_function_regparm (TREE_TYPE (cfun->decl), cfun->decl);
11075 if (DECL_STATIC_CHAIN (cfun->decl))
11077 sorry ("-fsplit-stack does not support fastcall with "
11078 "nested function");
11079 return INVALID_REGNUM;
11083 else if (regparm < 3)
11085 if (!DECL_STATIC_CHAIN (cfun->decl))
11091 sorry ("-fsplit-stack does not support 2 register "
11092 " parameters for a nested function");
11093 return INVALID_REGNUM;
11100 /* FIXME: We could make this work by pushing a register
11101 around the addition and comparison. */
11102 sorry ("-fsplit-stack does not support 3 register parameters");
11103 return INVALID_REGNUM;
11108 /* A SYMBOL_REF for the function which allocates new stackspace for
11111 static GTY(()) rtx split_stack_fn;
11113 /* A SYMBOL_REF for the more stack function when using the large
11116 static GTY(()) rtx split_stack_fn_large;
11118 /* Handle -fsplit-stack. These are the first instructions in the
11119 function, even before the regular prologue. */
11122 ix86_expand_split_stack_prologue (void)
11124 struct ix86_frame frame;
11125 HOST_WIDE_INT allocate;
11126 unsigned HOST_WIDE_INT args_size;
11127 rtx label, limit, current, jump_insn, allocate_rtx, call_insn, call_fusage;
11128 rtx scratch_reg = NULL_RTX;
11129 rtx varargs_label = NULL_RTX;
11132 gcc_assert (flag_split_stack && reload_completed);
11134 ix86_finalize_stack_realign_flags ();
11135 ix86_compute_frame_layout (&frame);
11136 allocate = frame.stack_pointer_offset - INCOMING_FRAME_SP_OFFSET;
11138 /* This is the label we will branch to if we have enough stack
11139 space. We expect the basic block reordering pass to reverse this
11140 branch if optimizing, so that we branch in the unlikely case. */
11141 label = gen_label_rtx ();
11143 /* We need to compare the stack pointer minus the frame size with
11144 the stack boundary in the TCB. The stack boundary always gives
11145 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11146 can compare directly. Otherwise we need to do an addition. */
11148 limit = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
11149 UNSPEC_STACK_CHECK);
11150 limit = gen_rtx_CONST (Pmode, limit);
11151 limit = gen_rtx_MEM (Pmode, limit);
11152 if (allocate < SPLIT_STACK_AVAILABLE)
11153 current = stack_pointer_rtx;
11156 unsigned int scratch_regno;
11159 /* We need a scratch register to hold the stack pointer minus
11160 the required frame size. Since this is the very start of the
11161 function, the scratch register can be any caller-saved
11162 register which is not used for parameters. */
11163 offset = GEN_INT (- allocate);
11164 scratch_regno = split_stack_prologue_scratch_regno ();
11165 if (scratch_regno == INVALID_REGNUM)
11167 scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
11168 if (!TARGET_64BIT || x86_64_immediate_operand (offset, Pmode))
11170 /* We don't use ix86_gen_add3 in this case because it will
11171 want to split to lea, but when not optimizing the insn
11172 will not be split after this point. */
11173 emit_insn (gen_rtx_SET (VOIDmode, scratch_reg,
11174 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
11179 emit_move_insn (scratch_reg, offset);
11180 emit_insn (gen_adddi3 (scratch_reg, scratch_reg,
11181 stack_pointer_rtx));
11183 current = scratch_reg;
11186 ix86_expand_branch (GEU, current, limit, label);
11187 jump_insn = get_last_insn ();
11188 JUMP_LABEL (jump_insn) = label;
11190 /* Mark the jump as very likely to be taken. */
11191 add_reg_note (jump_insn, REG_BR_PROB,
11192 GEN_INT (REG_BR_PROB_BASE - REG_BR_PROB_BASE / 100));
11194 if (split_stack_fn == NULL_RTX)
11195 split_stack_fn = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
11196 fn = split_stack_fn;
11198 /* Get more stack space. We pass in the desired stack space and the
11199 size of the arguments to copy to the new stack. In 32-bit mode
11200 we push the parameters; __morestack will return on a new stack
11201 anyhow. In 64-bit mode we pass the parameters in r10 and
11203 allocate_rtx = GEN_INT (allocate);
11204 args_size = crtl->args.size >= 0 ? crtl->args.size : 0;
11205 call_fusage = NULL_RTX;
11210 reg10 = gen_rtx_REG (Pmode, R10_REG);
11211 reg11 = gen_rtx_REG (Pmode, R11_REG);
11213 /* If this function uses a static chain, it will be in %r10.
11214 Preserve it across the call to __morestack. */
11215 if (DECL_STATIC_CHAIN (cfun->decl))
11219 rax = gen_rtx_REG (Pmode, AX_REG);
11220 emit_move_insn (rax, reg10);
11221 use_reg (&call_fusage, rax);
11224 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
11226 HOST_WIDE_INT argval;
11228 /* When using the large model we need to load the address
11229 into a register, and we've run out of registers. So we
11230 switch to a different calling convention, and we call a
11231 different function: __morestack_large. We pass the
11232 argument size in the upper 32 bits of r10 and pass the
11233 frame size in the lower 32 bits. */
11234 gcc_assert ((allocate & (HOST_WIDE_INT) 0xffffffff) == allocate);
11235 gcc_assert ((args_size & 0xffffffff) == args_size);
11237 if (split_stack_fn_large == NULL_RTX)
11238 split_stack_fn_large =
11239 gen_rtx_SYMBOL_REF (Pmode, "__morestack_large_model");
11241 if (ix86_cmodel == CM_LARGE_PIC)
11245 label = gen_label_rtx ();
11246 emit_label (label);
11247 LABEL_PRESERVE_P (label) = 1;
11248 emit_insn (gen_set_rip_rex64 (reg10, label));
11249 emit_insn (gen_set_got_offset_rex64 (reg11, label));
11250 emit_insn (gen_adddi3 (reg10, reg10, reg11));
11251 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, split_stack_fn_large),
11253 x = gen_rtx_CONST (Pmode, x);
11254 emit_move_insn (reg11, x);
11255 x = gen_rtx_PLUS (Pmode, reg10, reg11);
11256 x = gen_const_mem (Pmode, x);
11257 emit_move_insn (reg11, x);
11260 emit_move_insn (reg11, split_stack_fn_large);
11264 argval = ((args_size << 16) << 16) + allocate;
11265 emit_move_insn (reg10, GEN_INT (argval));
11269 emit_move_insn (reg10, allocate_rtx);
11270 emit_move_insn (reg11, GEN_INT (args_size));
11271 use_reg (&call_fusage, reg11);
11274 use_reg (&call_fusage, reg10);
11278 emit_insn (gen_push (GEN_INT (args_size)));
11279 emit_insn (gen_push (allocate_rtx));
11281 call_insn = ix86_expand_call (NULL_RTX, gen_rtx_MEM (QImode, fn),
11282 GEN_INT (UNITS_PER_WORD), constm1_rtx,
11284 add_function_usage_to (call_insn, call_fusage);
11286 /* In order to make call/return prediction work right, we now need
11287 to execute a return instruction. See
11288 libgcc/config/i386/morestack.S for the details on how this works.
11290 For flow purposes gcc must not see this as a return
11291 instruction--we need control flow to continue at the subsequent
11292 label. Therefore, we use an unspec. */
11293 gcc_assert (crtl->args.pops_args < 65536);
11294 emit_insn (gen_split_stack_return (GEN_INT (crtl->args.pops_args)));
11296 /* If we are in 64-bit mode and this function uses a static chain,
11297 we saved %r10 in %rax before calling _morestack. */
11298 if (TARGET_64BIT && DECL_STATIC_CHAIN (cfun->decl))
11299 emit_move_insn (gen_rtx_REG (Pmode, R10_REG),
11300 gen_rtx_REG (Pmode, AX_REG));
11302 /* If this function calls va_start, we need to store a pointer to
11303 the arguments on the old stack, because they may not have been
11304 all copied to the new stack. At this point the old stack can be
11305 found at the frame pointer value used by __morestack, because
11306 __morestack has set that up before calling back to us. Here we
11307 store that pointer in a scratch register, and in
11308 ix86_expand_prologue we store the scratch register in a stack
11310 if (cfun->machine->split_stack_varargs_pointer != NULL_RTX)
11312 unsigned int scratch_regno;
11316 scratch_regno = split_stack_prologue_scratch_regno ();
11317 scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
11318 frame_reg = gen_rtx_REG (Pmode, BP_REG);
11322 return address within this function
11323 return address of caller of this function
11325 So we add three words to get to the stack arguments.
11329 return address within this function
11330 first argument to __morestack
11331 second argument to __morestack
11332 return address of caller of this function
11334 So we add five words to get to the stack arguments.
11336 words = TARGET_64BIT ? 3 : 5;
11337 emit_insn (gen_rtx_SET (VOIDmode, scratch_reg,
11338 gen_rtx_PLUS (Pmode, frame_reg,
11339 GEN_INT (words * UNITS_PER_WORD))));
11341 varargs_label = gen_label_rtx ();
11342 emit_jump_insn (gen_jump (varargs_label));
11343 JUMP_LABEL (get_last_insn ()) = varargs_label;
11348 emit_label (label);
11349 LABEL_NUSES (label) = 1;
11351 /* If this function calls va_start, we now have to set the scratch
11352 register for the case where we do not call __morestack. In this
11353 case we need to set it based on the stack pointer. */
11354 if (cfun->machine->split_stack_varargs_pointer != NULL_RTX)
11356 emit_insn (gen_rtx_SET (VOIDmode, scratch_reg,
11357 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
11358 GEN_INT (UNITS_PER_WORD))));
11360 emit_label (varargs_label);
11361 LABEL_NUSES (varargs_label) = 1;
11365 /* We may have to tell the dataflow pass that the split stack prologue
11366 is initializing a scratch register. */
11369 ix86_live_on_entry (bitmap regs)
11371 if (cfun->machine->split_stack_varargs_pointer != NULL_RTX)
11373 gcc_assert (flag_split_stack);
11374 bitmap_set_bit (regs, split_stack_prologue_scratch_regno ());
11378 /* Determine if op is suitable SUBREG RTX for address. */
11381 ix86_address_subreg_operand (rtx op)
11383 enum machine_mode mode;
11388 mode = GET_MODE (op);
11390 if (GET_MODE_CLASS (mode) != MODE_INT)
11393 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11394 failures when the register is one word out of a two word structure. */
11395 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
11398 /* Allow only SUBREGs of non-eliminable hard registers. */
11399 return register_no_elim_operand (op, mode);
11402 /* Extract the parts of an RTL expression that is a valid memory address
11403 for an instruction. Return 0 if the structure of the address is
11404 grossly off. Return -1 if the address contains ASHIFT, so it is not
11405 strictly valid, but still used for computing length of lea instruction. */
11408 ix86_decompose_address (rtx addr, struct ix86_address *out)
11410 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
11411 rtx base_reg, index_reg;
11412 HOST_WIDE_INT scale = 1;
11413 rtx scale_rtx = NULL_RTX;
11416 enum ix86_address_seg seg = SEG_DEFAULT;
11418 /* Allow zero-extended SImode addresses,
11419 they will be emitted with addr32 prefix. */
11420 if (TARGET_64BIT && GET_MODE (addr) == DImode)
11422 if (GET_CODE (addr) == ZERO_EXTEND
11423 && GET_MODE (XEXP (addr, 0)) == SImode)
11424 addr = XEXP (addr, 0);
11425 else if (GET_CODE (addr) == AND
11426 && const_32bit_mask (XEXP (addr, 1), DImode))
11428 addr = XEXP (addr, 0);
11430 /* Strip subreg. */
11431 if (GET_CODE (addr) == SUBREG
11432 && GET_MODE (SUBREG_REG (addr)) == SImode)
11433 addr = SUBREG_REG (addr);
11439 else if (GET_CODE (addr) == SUBREG)
11441 if (ix86_address_subreg_operand (SUBREG_REG (addr)))
11446 else if (GET_CODE (addr) == PLUS)
11448 rtx addends[4], op;
11456 addends[n++] = XEXP (op, 1);
11459 while (GET_CODE (op) == PLUS);
11464 for (i = n; i >= 0; --i)
11467 switch (GET_CODE (op))
11472 index = XEXP (op, 0);
11473 scale_rtx = XEXP (op, 1);
11479 index = XEXP (op, 0);
11480 tmp = XEXP (op, 1);
11481 if (!CONST_INT_P (tmp))
11483 scale = INTVAL (tmp);
11484 if ((unsigned HOST_WIDE_INT) scale > 3)
11486 scale = 1 << scale;
11490 if (XINT (op, 1) == UNSPEC_TP
11491 && TARGET_TLS_DIRECT_SEG_REFS
11492 && seg == SEG_DEFAULT)
11493 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
11499 if (!ix86_address_subreg_operand (SUBREG_REG (op)))
11526 else if (GET_CODE (addr) == MULT)
11528 index = XEXP (addr, 0); /* index*scale */
11529 scale_rtx = XEXP (addr, 1);
11531 else if (GET_CODE (addr) == ASHIFT)
11533 /* We're called for lea too, which implements ashift on occasion. */
11534 index = XEXP (addr, 0);
11535 tmp = XEXP (addr, 1);
11536 if (!CONST_INT_P (tmp))
11538 scale = INTVAL (tmp);
11539 if ((unsigned HOST_WIDE_INT) scale > 3)
11541 scale = 1 << scale;
11545 disp = addr; /* displacement */
11551 else if (GET_CODE (index) == SUBREG
11552 && ix86_address_subreg_operand (SUBREG_REG (index)))
11558 /* Extract the integral value of scale. */
11561 if (!CONST_INT_P (scale_rtx))
11563 scale = INTVAL (scale_rtx);
11566 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
11567 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
11569 /* Avoid useless 0 displacement. */
11570 if (disp == const0_rtx && (base || index))
11573 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11574 if (base_reg && index_reg && scale == 1
11575 && (index_reg == arg_pointer_rtx
11576 || index_reg == frame_pointer_rtx
11577 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
11580 tmp = base, base = index, index = tmp;
11581 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
11584 /* Special case: %ebp cannot be encoded as a base without a displacement.
11588 && (base_reg == hard_frame_pointer_rtx
11589 || base_reg == frame_pointer_rtx
11590 || base_reg == arg_pointer_rtx
11591 || (REG_P (base_reg)
11592 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
11593 || REGNO (base_reg) == R13_REG))))
11596 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11597 Avoid this by transforming to [%esi+0].
11598 Reload calls address legitimization without cfun defined, so we need
11599 to test cfun for being non-NULL. */
11600 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
11601 && base_reg && !index_reg && !disp
11602 && REG_P (base_reg) && REGNO (base_reg) == SI_REG)
11605 /* Special case: encode reg+reg instead of reg*2. */
11606 if (!base && index && scale == 2)
11607 base = index, base_reg = index_reg, scale = 1;
11609 /* Special case: scaling cannot be encoded without base or displacement. */
11610 if (!base && !disp && index && scale != 1)
11614 out->index = index;
11616 out->scale = scale;
11622 /* Return cost of the memory address x.
11623 For i386, it is better to use a complex address than let gcc copy
11624 the address into a reg and make a new pseudo. But not if the address
11625 requires to two regs - that would mean more pseudos with longer
11628 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
11630 struct ix86_address parts;
11632 int ok = ix86_decompose_address (x, &parts);
11636 if (parts.base && GET_CODE (parts.base) == SUBREG)
11637 parts.base = SUBREG_REG (parts.base);
11638 if (parts.index && GET_CODE (parts.index) == SUBREG)
11639 parts.index = SUBREG_REG (parts.index);
11641 /* Attempt to minimize number of registers in the address. */
11643 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
11645 && (!REG_P (parts.index)
11646 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
11650 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
11652 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
11653 && parts.base != parts.index)
11656 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11657 since it's predecode logic can't detect the length of instructions
11658 and it degenerates to vector decoded. Increase cost of such
11659 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11660 to split such addresses or even refuse such addresses at all.
11662 Following addressing modes are affected:
11667 The first and last case may be avoidable by explicitly coding the zero in
11668 memory address, but I don't have AMD-K6 machine handy to check this
11672 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
11673 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
11674 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
11680 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11681 this is used for to form addresses to local data when -fPIC is in
11685 darwin_local_data_pic (rtx disp)
11687 return (GET_CODE (disp) == UNSPEC
11688 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
11691 /* Determine if a given RTX is a valid constant. We already know this
11692 satisfies CONSTANT_P. */
11695 ix86_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
11697 switch (GET_CODE (x))
11702 if (GET_CODE (x) == PLUS)
11704 if (!CONST_INT_P (XEXP (x, 1)))
11709 if (TARGET_MACHO && darwin_local_data_pic (x))
11712 /* Only some unspecs are valid as "constants". */
11713 if (GET_CODE (x) == UNSPEC)
11714 switch (XINT (x, 1))
11717 case UNSPEC_GOTOFF:
11718 case UNSPEC_PLTOFF:
11719 return TARGET_64BIT;
11721 case UNSPEC_NTPOFF:
11722 x = XVECEXP (x, 0, 0);
11723 return (GET_CODE (x) == SYMBOL_REF
11724 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
11725 case UNSPEC_DTPOFF:
11726 x = XVECEXP (x, 0, 0);
11727 return (GET_CODE (x) == SYMBOL_REF
11728 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
11733 /* We must have drilled down to a symbol. */
11734 if (GET_CODE (x) == LABEL_REF)
11736 if (GET_CODE (x) != SYMBOL_REF)
11741 /* TLS symbols are never valid. */
11742 if (SYMBOL_REF_TLS_MODEL (x))
11745 /* DLLIMPORT symbols are never valid. */
11746 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
11747 && SYMBOL_REF_DLLIMPORT_P (x))
11751 /* mdynamic-no-pic */
11752 if (MACHO_DYNAMIC_NO_PIC_P)
11753 return machopic_symbol_defined_p (x);
11758 if (GET_MODE (x) == TImode
11759 && x != CONST0_RTX (TImode)
11765 if (!standard_sse_constant_p (x))
11772 /* Otherwise we handle everything else in the move patterns. */
11776 /* Determine if it's legal to put X into the constant pool. This
11777 is not possible for the address of thread-local symbols, which
11778 is checked above. */
11781 ix86_cannot_force_const_mem (enum machine_mode mode, rtx x)
11783 /* We can always put integral constants and vectors in memory. */
11784 switch (GET_CODE (x))
11794 return !ix86_legitimate_constant_p (mode, x);
11798 /* Nonzero if the constant value X is a legitimate general operand
11799 when generating PIC code. It is given that flag_pic is on and
11800 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11803 legitimate_pic_operand_p (rtx x)
11807 switch (GET_CODE (x))
11810 inner = XEXP (x, 0);
11811 if (GET_CODE (inner) == PLUS
11812 && CONST_INT_P (XEXP (inner, 1)))
11813 inner = XEXP (inner, 0);
11815 /* Only some unspecs are valid as "constants". */
11816 if (GET_CODE (inner) == UNSPEC)
11817 switch (XINT (inner, 1))
11820 case UNSPEC_GOTOFF:
11821 case UNSPEC_PLTOFF:
11822 return TARGET_64BIT;
11824 x = XVECEXP (inner, 0, 0);
11825 return (GET_CODE (x) == SYMBOL_REF
11826 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
11827 case UNSPEC_MACHOPIC_OFFSET:
11828 return legitimate_pic_address_disp_p (x);
11836 return legitimate_pic_address_disp_p (x);
11843 /* Determine if a given CONST RTX is a valid memory displacement
11847 legitimate_pic_address_disp_p (rtx disp)
11851 /* In 64bit mode we can allow direct addresses of symbols and labels
11852 when they are not dynamic symbols. */
11855 rtx op0 = disp, op1;
11857 switch (GET_CODE (disp))
11863 if (GET_CODE (XEXP (disp, 0)) != PLUS)
11865 op0 = XEXP (XEXP (disp, 0), 0);
11866 op1 = XEXP (XEXP (disp, 0), 1);
11867 if (!CONST_INT_P (op1)
11868 || INTVAL (op1) >= 16*1024*1024
11869 || INTVAL (op1) < -16*1024*1024)
11871 if (GET_CODE (op0) == LABEL_REF)
11873 if (GET_CODE (op0) == CONST
11874 && GET_CODE (XEXP (op0, 0)) == UNSPEC
11875 && XINT (XEXP (op0, 0), 1) == UNSPEC_PCREL)
11877 if (GET_CODE (op0) == UNSPEC
11878 && XINT (op0, 1) == UNSPEC_PCREL)
11880 if (GET_CODE (op0) != SYMBOL_REF)
11885 /* TLS references should always be enclosed in UNSPEC. */
11886 if (SYMBOL_REF_TLS_MODEL (op0))
11888 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
11889 && ix86_cmodel != CM_LARGE_PIC)
11897 if (GET_CODE (disp) != CONST)
11899 disp = XEXP (disp, 0);
11903 /* We are unsafe to allow PLUS expressions. This limit allowed distance
11904 of GOT tables. We should not need these anyway. */
11905 if (GET_CODE (disp) != UNSPEC
11906 || (XINT (disp, 1) != UNSPEC_GOTPCREL
11907 && XINT (disp, 1) != UNSPEC_GOTOFF
11908 && XINT (disp, 1) != UNSPEC_PCREL
11909 && XINT (disp, 1) != UNSPEC_PLTOFF))
11912 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
11913 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
11919 if (GET_CODE (disp) == PLUS)
11921 if (!CONST_INT_P (XEXP (disp, 1)))
11923 disp = XEXP (disp, 0);
11927 if (TARGET_MACHO && darwin_local_data_pic (disp))
11930 if (GET_CODE (disp) != UNSPEC)
11933 switch (XINT (disp, 1))
11938 /* We need to check for both symbols and labels because VxWorks loads
11939 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
11941 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
11942 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
11943 case UNSPEC_GOTOFF:
11944 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
11945 While ABI specify also 32bit relocation but we don't produce it in
11946 small PIC model at all. */
11947 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
11948 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
11950 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
11952 case UNSPEC_GOTTPOFF:
11953 case UNSPEC_GOTNTPOFF:
11954 case UNSPEC_INDNTPOFF:
11957 disp = XVECEXP (disp, 0, 0);
11958 return (GET_CODE (disp) == SYMBOL_REF
11959 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
11960 case UNSPEC_NTPOFF:
11961 disp = XVECEXP (disp, 0, 0);
11962 return (GET_CODE (disp) == SYMBOL_REF
11963 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
11964 case UNSPEC_DTPOFF:
11965 disp = XVECEXP (disp, 0, 0);
11966 return (GET_CODE (disp) == SYMBOL_REF
11967 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
11973 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
11974 replace the input X, or the original X if no replacement is called for.
11975 The output parameter *WIN is 1 if the calling macro should goto WIN,
11976 0 if it should not. */
11979 ix86_legitimize_reload_address (rtx x,
11980 enum machine_mode mode ATTRIBUTE_UNUSED,
11981 int opnum, int type,
11982 int ind_levels ATTRIBUTE_UNUSED)
11984 /* Reload can generate:
11986 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
11990 This RTX is rejected from ix86_legitimate_address_p due to
11991 non-strictness of base register 97. Following this rejection,
11992 reload pushes all three components into separate registers,
11993 creating invalid memory address RTX.
11995 Following code reloads only the invalid part of the
11996 memory address RTX. */
11998 if (GET_CODE (x) == PLUS
11999 && REG_P (XEXP (x, 1))
12000 && GET_CODE (XEXP (x, 0)) == PLUS
12001 && REG_P (XEXP (XEXP (x, 0), 1)))
12004 bool something_reloaded = false;
12006 base = XEXP (XEXP (x, 0), 1);
12007 if (!REG_OK_FOR_BASE_STRICT_P (base))
12009 push_reload (base, NULL_RTX, &XEXP (XEXP (x, 0), 1), NULL,
12010 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
12011 opnum, (enum reload_type)type);
12012 something_reloaded = true;
12015 index = XEXP (x, 1);
12016 if (!REG_OK_FOR_INDEX_STRICT_P (index))
12018 push_reload (index, NULL_RTX, &XEXP (x, 1), NULL,
12019 INDEX_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
12020 opnum, (enum reload_type)type);
12021 something_reloaded = true;
12024 gcc_assert (something_reloaded);
12031 /* Recognizes RTL expressions that are valid memory addresses for an
12032 instruction. The MODE argument is the machine mode for the MEM
12033 expression that wants to use this address.
12035 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12036 convert common non-canonical forms to canonical form so that they will
12040 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
12041 rtx addr, bool strict)
12043 struct ix86_address parts;
12044 rtx base, index, disp;
12045 HOST_WIDE_INT scale;
12047 /* Since constant address in x32 is signed extended to 64bit,
12048 we have to prevent addresses from 0x80000000 to 0xffffffff. */
12050 && CONST_INT_P (addr)
12051 && INTVAL (addr) < 0)
12054 if (ix86_decompose_address (addr, &parts) <= 0)
12055 /* Decomposition failed. */
12059 index = parts.index;
12061 scale = parts.scale;
12063 /* Validate base register. */
12070 else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base)))
12071 reg = SUBREG_REG (base);
12073 /* Base is not a register. */
12076 if (GET_MODE (base) != SImode && GET_MODE (base) != DImode)
12079 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
12080 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
12081 /* Base is not valid. */
12085 /* Validate index register. */
12092 else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index)))
12093 reg = SUBREG_REG (index);
12095 /* Index is not a register. */
12098 if (GET_MODE (index) != SImode && GET_MODE (index) != DImode)
12101 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
12102 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
12103 /* Index is not valid. */
12107 /* Index and base should have the same mode. */
12109 && GET_MODE (base) != GET_MODE (index))
12112 /* Validate scale factor. */
12116 /* Scale without index. */
12119 if (scale != 2 && scale != 4 && scale != 8)
12120 /* Scale is not a valid multiplier. */
12124 /* Validate displacement. */
12127 if (GET_CODE (disp) == CONST
12128 && GET_CODE (XEXP (disp, 0)) == UNSPEC
12129 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
12130 switch (XINT (XEXP (disp, 0), 1))
12132 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12133 used. While ABI specify also 32bit relocations, we don't produce
12134 them at all and use IP relative instead. */
12136 case UNSPEC_GOTOFF:
12137 gcc_assert (flag_pic);
12139 goto is_legitimate_pic;
12141 /* 64bit address unspec. */
12144 case UNSPEC_GOTPCREL:
12146 gcc_assert (flag_pic);
12147 goto is_legitimate_pic;
12149 case UNSPEC_GOTTPOFF:
12150 case UNSPEC_GOTNTPOFF:
12151 case UNSPEC_INDNTPOFF:
12152 case UNSPEC_NTPOFF:
12153 case UNSPEC_DTPOFF:
12156 case UNSPEC_STACK_CHECK:
12157 gcc_assert (flag_split_stack);
12161 /* Invalid address unspec. */
12165 else if (SYMBOLIC_CONST (disp)
12169 && MACHOPIC_INDIRECT
12170 && !machopic_operand_p (disp)
12176 if (TARGET_64BIT && (index || base))
12178 /* foo@dtpoff(%rX) is ok. */
12179 if (GET_CODE (disp) != CONST
12180 || GET_CODE (XEXP (disp, 0)) != PLUS
12181 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
12182 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
12183 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
12184 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
12185 /* Non-constant pic memory reference. */
12188 else if ((!TARGET_MACHO || flag_pic)
12189 && ! legitimate_pic_address_disp_p (disp))
12190 /* Displacement is an invalid pic construct. */
12193 else if (MACHO_DYNAMIC_NO_PIC_P
12194 && !ix86_legitimate_constant_p (Pmode, disp))
12195 /* displacment must be referenced via non_lazy_pointer */
12199 /* This code used to verify that a symbolic pic displacement
12200 includes the pic_offset_table_rtx register.
12202 While this is good idea, unfortunately these constructs may
12203 be created by "adds using lea" optimization for incorrect
12212 This code is nonsensical, but results in addressing
12213 GOT table with pic_offset_table_rtx base. We can't
12214 just refuse it easily, since it gets matched by
12215 "addsi3" pattern, that later gets split to lea in the
12216 case output register differs from input. While this
12217 can be handled by separate addsi pattern for this case
12218 that never results in lea, this seems to be easier and
12219 correct fix for crash to disable this test. */
12221 else if (GET_CODE (disp) != LABEL_REF
12222 && !CONST_INT_P (disp)
12223 && (GET_CODE (disp) != CONST
12224 || !ix86_legitimate_constant_p (Pmode, disp))
12225 && (GET_CODE (disp) != SYMBOL_REF
12226 || !ix86_legitimate_constant_p (Pmode, disp)))
12227 /* Displacement is not constant. */
12229 else if (TARGET_64BIT
12230 && !x86_64_immediate_operand (disp, VOIDmode))
12231 /* Displacement is out of range. */
12235 /* Everything looks valid. */
12239 /* Determine if a given RTX is a valid constant address. */
12242 constant_address_p (rtx x)
12244 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
12247 /* Return a unique alias set for the GOT. */
12249 static alias_set_type
12250 ix86_GOT_alias_set (void)
12252 static alias_set_type set = -1;
12254 set = new_alias_set ();
12258 /* Return a legitimate reference for ORIG (an address) using the
12259 register REG. If REG is 0, a new pseudo is generated.
12261 There are two types of references that must be handled:
12263 1. Global data references must load the address from the GOT, via
12264 the PIC reg. An insn is emitted to do this load, and the reg is
12267 2. Static data references, constant pool addresses, and code labels
12268 compute the address as an offset from the GOT, whose base is in
12269 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12270 differentiate them from global data objects. The returned
12271 address is the PIC reg + an unspec constant.
12273 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12274 reg also appears in the address. */
12277 legitimize_pic_address (rtx orig, rtx reg)
12280 rtx new_rtx = orig;
12284 if (TARGET_MACHO && !TARGET_64BIT)
12287 reg = gen_reg_rtx (Pmode);
12288 /* Use the generic Mach-O PIC machinery. */
12289 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
12293 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
12295 else if (TARGET_64BIT
12296 && ix86_cmodel != CM_SMALL_PIC
12297 && gotoff_operand (addr, Pmode))
12300 /* This symbol may be referenced via a displacement from the PIC
12301 base address (@GOTOFF). */
12303 if (reload_in_progress)
12304 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12305 if (GET_CODE (addr) == CONST)
12306 addr = XEXP (addr, 0);
12307 if (GET_CODE (addr) == PLUS)
12309 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
12311 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
12314 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
12315 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12317 tmpreg = gen_reg_rtx (Pmode);
12320 emit_move_insn (tmpreg, new_rtx);
12324 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
12325 tmpreg, 1, OPTAB_DIRECT);
12328 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
12330 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
12332 /* This symbol may be referenced via a displacement from the PIC
12333 base address (@GOTOFF). */
12335 if (reload_in_progress)
12336 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12337 if (GET_CODE (addr) == CONST)
12338 addr = XEXP (addr, 0);
12339 if (GET_CODE (addr) == PLUS)
12341 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
12343 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
12346 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
12347 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12348 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
12352 emit_move_insn (reg, new_rtx);
12356 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
12357 /* We can't use @GOTOFF for text labels on VxWorks;
12358 see gotoff_operand. */
12359 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
12361 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
12363 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
12364 return legitimize_dllimport_symbol (addr, true);
12365 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
12366 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
12367 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
12369 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
12370 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
12374 /* For x64 PE-COFF there is no GOT table. So we use address
12376 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
12378 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PCREL);
12379 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12382 reg = gen_reg_rtx (Pmode);
12383 emit_move_insn (reg, new_rtx);
12386 else if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
12388 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
12389 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12390 new_rtx = gen_const_mem (Pmode, new_rtx);
12391 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
12394 reg = gen_reg_rtx (Pmode);
12395 /* Use directly gen_movsi, otherwise the address is loaded
12396 into register for CSE. We don't want to CSE this addresses,
12397 instead we CSE addresses from the GOT table, so skip this. */
12398 emit_insn (gen_movsi (reg, new_rtx));
12403 /* This symbol must be referenced via a load from the
12404 Global Offset Table (@GOT). */
12406 if (reload_in_progress)
12407 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12408 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
12409 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12411 new_rtx = force_reg (Pmode, new_rtx);
12412 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
12413 new_rtx = gen_const_mem (Pmode, new_rtx);
12414 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
12417 reg = gen_reg_rtx (Pmode);
12418 emit_move_insn (reg, new_rtx);
12424 if (CONST_INT_P (addr)
12425 && !x86_64_immediate_operand (addr, VOIDmode))
12429 emit_move_insn (reg, addr);
12433 new_rtx = force_reg (Pmode, addr);
12435 else if (GET_CODE (addr) == CONST)
12437 addr = XEXP (addr, 0);
12439 /* We must match stuff we generate before. Assume the only
12440 unspecs that can get here are ours. Not that we could do
12441 anything with them anyway.... */
12442 if (GET_CODE (addr) == UNSPEC
12443 || (GET_CODE (addr) == PLUS
12444 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
12446 gcc_assert (GET_CODE (addr) == PLUS);
12448 if (GET_CODE (addr) == PLUS)
12450 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
12452 /* Check first to see if this is a constant offset from a @GOTOFF
12453 symbol reference. */
12454 if (gotoff_operand (op0, Pmode)
12455 && CONST_INT_P (op1))
12459 if (reload_in_progress)
12460 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12461 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
12463 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
12464 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
12465 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
12469 emit_move_insn (reg, new_rtx);
12475 if (INTVAL (op1) < -16*1024*1024
12476 || INTVAL (op1) >= 16*1024*1024)
12478 if (!x86_64_immediate_operand (op1, Pmode))
12479 op1 = force_reg (Pmode, op1);
12480 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
12486 base = legitimize_pic_address (XEXP (addr, 0), reg);
12487 new_rtx = legitimize_pic_address (XEXP (addr, 1),
12488 base == reg ? NULL_RTX : reg);
12490 if (CONST_INT_P (new_rtx))
12491 new_rtx = plus_constant (base, INTVAL (new_rtx));
12494 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
12496 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
12497 new_rtx = XEXP (new_rtx, 1);
12499 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
12507 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12510 get_thread_pointer (bool to_reg)
12512 rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
12514 if (GET_MODE (tp) != Pmode)
12515 tp = convert_to_mode (Pmode, tp, 1);
12518 tp = copy_addr_to_reg (tp);
12523 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12525 static GTY(()) rtx ix86_tls_symbol;
12528 ix86_tls_get_addr (void)
12530 if (!ix86_tls_symbol)
12533 = ((TARGET_ANY_GNU_TLS && !TARGET_64BIT)
12534 ? "___tls_get_addr" : "__tls_get_addr");
12536 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, sym);
12539 return ix86_tls_symbol;
12542 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12544 static GTY(()) rtx ix86_tls_module_base_symbol;
12547 ix86_tls_module_base (void)
12549 if (!ix86_tls_module_base_symbol)
12551 ix86_tls_module_base_symbol
12552 = gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
12554 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
12555 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
12558 return ix86_tls_module_base_symbol;
12561 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12562 false if we expect this to be used for a memory address and true if
12563 we expect to load the address into a register. */
12566 legitimize_tls_address (rtx x, enum tls_model model, bool for_mov)
12568 rtx dest, base, off;
12569 rtx pic = NULL_RTX, tp = NULL_RTX;
12574 case TLS_MODEL_GLOBAL_DYNAMIC:
12575 dest = gen_reg_rtx (Pmode);
12580 pic = pic_offset_table_rtx;
12583 pic = gen_reg_rtx (Pmode);
12584 emit_insn (gen_set_got (pic));
12588 if (TARGET_GNU2_TLS)
12591 emit_insn (gen_tls_dynamic_gnu2_64 (dest, x));
12593 emit_insn (gen_tls_dynamic_gnu2_32 (dest, x, pic));
12595 tp = get_thread_pointer (true);
12596 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
12598 set_unique_reg_note (get_last_insn (), REG_EQUAL, x);
12602 rtx caddr = ix86_tls_get_addr ();
12606 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
12609 emit_call_insn (gen_tls_global_dynamic_64 (rax, x, caddr));
12610 insns = get_insns ();
12613 RTL_CONST_CALL_P (insns) = 1;
12614 emit_libcall_block (insns, dest, rax, x);
12617 emit_insn (gen_tls_global_dynamic_32 (dest, x, pic, caddr));
12621 case TLS_MODEL_LOCAL_DYNAMIC:
12622 base = gen_reg_rtx (Pmode);
12627 pic = pic_offset_table_rtx;
12630 pic = gen_reg_rtx (Pmode);
12631 emit_insn (gen_set_got (pic));
12635 if (TARGET_GNU2_TLS)
12637 rtx tmp = ix86_tls_module_base ();
12640 emit_insn (gen_tls_dynamic_gnu2_64 (base, tmp));
12642 emit_insn (gen_tls_dynamic_gnu2_32 (base, tmp, pic));
12644 tp = get_thread_pointer (true);
12645 set_unique_reg_note (get_last_insn (), REG_EQUAL,
12646 gen_rtx_MINUS (Pmode, tmp, tp));
12650 rtx caddr = ix86_tls_get_addr ();
12654 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, eqv;
12657 emit_call_insn (gen_tls_local_dynamic_base_64 (rax, caddr));
12658 insns = get_insns ();
12661 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12662 share the LD_BASE result with other LD model accesses. */
12663 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
12664 UNSPEC_TLS_LD_BASE);
12666 RTL_CONST_CALL_P (insns) = 1;
12667 emit_libcall_block (insns, base, rax, eqv);
12670 emit_insn (gen_tls_local_dynamic_base_32 (base, pic, caddr));
12673 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
12674 off = gen_rtx_CONST (Pmode, off);
12676 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
12678 if (TARGET_GNU2_TLS)
12680 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
12682 set_unique_reg_note (get_last_insn (), REG_EQUAL, x);
12686 case TLS_MODEL_INITIAL_EXEC:
12689 if (TARGET_SUN_TLS)
12691 /* The Sun linker took the AMD64 TLS spec literally
12692 and can only handle %rax as destination of the
12693 initial executable code sequence. */
12695 dest = gen_reg_rtx (Pmode);
12696 emit_insn (gen_tls_initial_exec_64_sun (dest, x));
12701 type = UNSPEC_GOTNTPOFF;
12705 if (reload_in_progress)
12706 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12707 pic = pic_offset_table_rtx;
12708 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
12710 else if (!TARGET_ANY_GNU_TLS)
12712 pic = gen_reg_rtx (Pmode);
12713 emit_insn (gen_set_got (pic));
12714 type = UNSPEC_GOTTPOFF;
12719 type = UNSPEC_INDNTPOFF;
12722 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
12723 off = gen_rtx_CONST (Pmode, off);
12725 off = gen_rtx_PLUS (Pmode, pic, off);
12726 off = gen_const_mem (Pmode, off);
12727 set_mem_alias_set (off, ix86_GOT_alias_set ());
12729 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
12731 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
12732 off = force_reg (Pmode, off);
12733 return gen_rtx_PLUS (Pmode, base, off);
12737 base = get_thread_pointer (true);
12738 dest = gen_reg_rtx (Pmode);
12739 emit_insn (gen_subsi3 (dest, base, off));
12743 case TLS_MODEL_LOCAL_EXEC:
12744 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
12745 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
12746 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
12747 off = gen_rtx_CONST (Pmode, off);
12749 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
12751 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
12752 return gen_rtx_PLUS (Pmode, base, off);
12756 base = get_thread_pointer (true);
12757 dest = gen_reg_rtx (Pmode);
12758 emit_insn (gen_subsi3 (dest, base, off));
12763 gcc_unreachable ();
12769 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12772 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
12773 htab_t dllimport_map;
12776 get_dllimport_decl (tree decl)
12778 struct tree_map *h, in;
12781 const char *prefix;
12782 size_t namelen, prefixlen;
12787 if (!dllimport_map)
12788 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
12790 in.hash = htab_hash_pointer (decl);
12791 in.base.from = decl;
12792 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
12793 h = (struct tree_map *) *loc;
12797 *loc = h = ggc_alloc_tree_map ();
12799 h->base.from = decl;
12800 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
12801 VAR_DECL, NULL, ptr_type_node);
12802 DECL_ARTIFICIAL (to) = 1;
12803 DECL_IGNORED_P (to) = 1;
12804 DECL_EXTERNAL (to) = 1;
12805 TREE_READONLY (to) = 1;
12807 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
12808 name = targetm.strip_name_encoding (name);
12809 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
12810 ? "*__imp_" : "*__imp__";
12811 namelen = strlen (name);
12812 prefixlen = strlen (prefix);
12813 imp_name = (char *) alloca (namelen + prefixlen + 1);
12814 memcpy (imp_name, prefix, prefixlen);
12815 memcpy (imp_name + prefixlen, name, namelen + 1);
12817 name = ggc_alloc_string (imp_name, namelen + prefixlen);
12818 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
12819 SET_SYMBOL_REF_DECL (rtl, to);
12820 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
12822 rtl = gen_const_mem (Pmode, rtl);
12823 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
12825 SET_DECL_RTL (to, rtl);
12826 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
12831 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
12832 true if we require the result be a register. */
12835 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
12840 gcc_assert (SYMBOL_REF_DECL (symbol));
12841 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
12843 x = DECL_RTL (imp_decl);
12845 x = force_reg (Pmode, x);
12849 /* Try machine-dependent ways of modifying an illegitimate address
12850 to be legitimate. If we find one, return the new, valid address.
12851 This macro is used in only one place: `memory_address' in explow.c.
12853 OLDX is the address as it was before break_out_memory_refs was called.
12854 In some cases it is useful to look at this to decide what needs to be done.
12856 It is always safe for this macro to do nothing. It exists to recognize
12857 opportunities to optimize the output.
12859 For the 80386, we handle X+REG by loading X into a register R and
12860 using R+REG. R will go in a general reg and indexing will be used.
12861 However, if REG is a broken-out memory address or multiplication,
12862 nothing needs to be done because REG can certainly go in a general reg.
12864 When -fpic is used, special handling is needed for symbolic references.
12865 See comments by legitimize_pic_address in i386.c for details. */
12868 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
12869 enum machine_mode mode)
12874 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
12876 return legitimize_tls_address (x, (enum tls_model) log, false);
12877 if (GET_CODE (x) == CONST
12878 && GET_CODE (XEXP (x, 0)) == PLUS
12879 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
12880 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
12882 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
12883 (enum tls_model) log, false);
12884 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
12887 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
12889 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
12890 return legitimize_dllimport_symbol (x, true);
12891 if (GET_CODE (x) == CONST
12892 && GET_CODE (XEXP (x, 0)) == PLUS
12893 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
12894 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
12896 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
12897 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
12901 if (flag_pic && SYMBOLIC_CONST (x))
12902 return legitimize_pic_address (x, 0);
12905 if (MACHO_DYNAMIC_NO_PIC_P && SYMBOLIC_CONST (x))
12906 return machopic_indirect_data_reference (x, 0);
12909 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
12910 if (GET_CODE (x) == ASHIFT
12911 && CONST_INT_P (XEXP (x, 1))
12912 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
12915 log = INTVAL (XEXP (x, 1));
12916 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
12917 GEN_INT (1 << log));
12920 if (GET_CODE (x) == PLUS)
12922 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
12924 if (GET_CODE (XEXP (x, 0)) == ASHIFT
12925 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
12926 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
12929 log = INTVAL (XEXP (XEXP (x, 0), 1));
12930 XEXP (x, 0) = gen_rtx_MULT (Pmode,
12931 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
12932 GEN_INT (1 << log));
12935 if (GET_CODE (XEXP (x, 1)) == ASHIFT
12936 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
12937 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
12940 log = INTVAL (XEXP (XEXP (x, 1), 1));
12941 XEXP (x, 1) = gen_rtx_MULT (Pmode,
12942 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
12943 GEN_INT (1 << log));
12946 /* Put multiply first if it isn't already. */
12947 if (GET_CODE (XEXP (x, 1)) == MULT)
12949 rtx tmp = XEXP (x, 0);
12950 XEXP (x, 0) = XEXP (x, 1);
12955 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
12956 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
12957 created by virtual register instantiation, register elimination, and
12958 similar optimizations. */
12959 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
12962 x = gen_rtx_PLUS (Pmode,
12963 gen_rtx_PLUS (Pmode, XEXP (x, 0),
12964 XEXP (XEXP (x, 1), 0)),
12965 XEXP (XEXP (x, 1), 1));
12969 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
12970 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
12971 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
12972 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
12973 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
12974 && CONSTANT_P (XEXP (x, 1)))
12977 rtx other = NULL_RTX;
12979 if (CONST_INT_P (XEXP (x, 1)))
12981 constant = XEXP (x, 1);
12982 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
12984 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
12986 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
12987 other = XEXP (x, 1);
12995 x = gen_rtx_PLUS (Pmode,
12996 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
12997 XEXP (XEXP (XEXP (x, 0), 1), 0)),
12998 plus_constant (other, INTVAL (constant)));
13002 if (changed && ix86_legitimate_address_p (mode, x, false))
13005 if (GET_CODE (XEXP (x, 0)) == MULT)
13008 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
13011 if (GET_CODE (XEXP (x, 1)) == MULT)
13014 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
13018 && REG_P (XEXP (x, 1))
13019 && REG_P (XEXP (x, 0)))
13022 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
13025 x = legitimize_pic_address (x, 0);
13028 if (changed && ix86_legitimate_address_p (mode, x, false))
13031 if (REG_P (XEXP (x, 0)))
13033 rtx temp = gen_reg_rtx (Pmode);
13034 rtx val = force_operand (XEXP (x, 1), temp);
13037 if (GET_MODE (val) != Pmode)
13038 val = convert_to_mode (Pmode, val, 1);
13039 emit_move_insn (temp, val);
13042 XEXP (x, 1) = temp;
13046 else if (REG_P (XEXP (x, 1)))
13048 rtx temp = gen_reg_rtx (Pmode);
13049 rtx val = force_operand (XEXP (x, 0), temp);
13052 if (GET_MODE (val) != Pmode)
13053 val = convert_to_mode (Pmode, val, 1);
13054 emit_move_insn (temp, val);
13057 XEXP (x, 0) = temp;
13065 /* Print an integer constant expression in assembler syntax. Addition
13066 and subtraction are the only arithmetic that may appear in these
13067 expressions. FILE is the stdio stream to write to, X is the rtx, and
13068 CODE is the operand print code from the output string. */
13071 output_pic_addr_const (FILE *file, rtx x, int code)
13075 switch (GET_CODE (x))
13078 gcc_assert (flag_pic);
13083 if (TARGET_64BIT || ! TARGET_MACHO_BRANCH_ISLANDS)
13084 output_addr_const (file, x);
13087 const char *name = XSTR (x, 0);
13089 /* Mark the decl as referenced so that cgraph will
13090 output the function. */
13091 if (SYMBOL_REF_DECL (x))
13092 mark_decl_referenced (SYMBOL_REF_DECL (x));
13095 if (MACHOPIC_INDIRECT
13096 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
13097 name = machopic_indirection_name (x, /*stub_p=*/true);
13099 assemble_name (file, name);
13101 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
13102 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
13103 fputs ("@PLT", file);
13110 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
13111 assemble_name (asm_out_file, buf);
13115 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
13119 /* This used to output parentheses around the expression,
13120 but that does not work on the 386 (either ATT or BSD assembler). */
13121 output_pic_addr_const (file, XEXP (x, 0), code);
13125 if (GET_MODE (x) == VOIDmode)
13127 /* We can use %d if the number is <32 bits and positive. */
13128 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
13129 fprintf (file, "0x%lx%08lx",
13130 (unsigned long) CONST_DOUBLE_HIGH (x),
13131 (unsigned long) CONST_DOUBLE_LOW (x));
13133 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
13136 /* We can't handle floating point constants;
13137 TARGET_PRINT_OPERAND must handle them. */
13138 output_operand_lossage ("floating constant misused");
13142 /* Some assemblers need integer constants to appear first. */
13143 if (CONST_INT_P (XEXP (x, 0)))
13145 output_pic_addr_const (file, XEXP (x, 0), code);
13147 output_pic_addr_const (file, XEXP (x, 1), code);
13151 gcc_assert (CONST_INT_P (XEXP (x, 1)));
13152 output_pic_addr_const (file, XEXP (x, 1), code);
13154 output_pic_addr_const (file, XEXP (x, 0), code);
13160 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
13161 output_pic_addr_const (file, XEXP (x, 0), code);
13163 output_pic_addr_const (file, XEXP (x, 1), code);
13165 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
13169 if (XINT (x, 1) == UNSPEC_STACK_CHECK)
13171 bool f = i386_asm_output_addr_const_extra (file, x);
13176 gcc_assert (XVECLEN (x, 0) == 1);
13177 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
13178 switch (XINT (x, 1))
13181 fputs ("@GOT", file);
13183 case UNSPEC_GOTOFF:
13184 fputs ("@GOTOFF", file);
13186 case UNSPEC_PLTOFF:
13187 fputs ("@PLTOFF", file);
13190 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
13191 "(%rip)" : "[rip]", file);
13193 case UNSPEC_GOTPCREL:
13194 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
13195 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
13197 case UNSPEC_GOTTPOFF:
13198 /* FIXME: This might be @TPOFF in Sun ld too. */
13199 fputs ("@gottpoff", file);
13202 fputs ("@tpoff", file);
13204 case UNSPEC_NTPOFF:
13206 fputs ("@tpoff", file);
13208 fputs ("@ntpoff", file);
13210 case UNSPEC_DTPOFF:
13211 fputs ("@dtpoff", file);
13213 case UNSPEC_GOTNTPOFF:
13215 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
13216 "@gottpoff(%rip)": "@gottpoff[rip]", file);
13218 fputs ("@gotntpoff", file);
13220 case UNSPEC_INDNTPOFF:
13221 fputs ("@indntpoff", file);
13224 case UNSPEC_MACHOPIC_OFFSET:
13226 machopic_output_function_base_name (file);
13230 output_operand_lossage ("invalid UNSPEC as operand");
13236 output_operand_lossage ("invalid expression as operand");
13240 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13241 We need to emit DTP-relative relocations. */
13243 static void ATTRIBUTE_UNUSED
13244 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
13246 fputs (ASM_LONG, file);
13247 output_addr_const (file, x);
13248 fputs ("@dtpoff", file);
13254 fputs (", 0", file);
13257 gcc_unreachable ();
13261 /* Return true if X is a representation of the PIC register. This copes
13262 with calls from ix86_find_base_term, where the register might have
13263 been replaced by a cselib value. */
13266 ix86_pic_register_p (rtx x)
13268 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
13269 return (pic_offset_table_rtx
13270 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
13272 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
13275 /* Helper function for ix86_delegitimize_address.
13276 Attempt to delegitimize TLS local-exec accesses. */
13279 ix86_delegitimize_tls_address (rtx orig_x)
13281 rtx x = orig_x, unspec;
13282 struct ix86_address addr;
13284 if (!TARGET_TLS_DIRECT_SEG_REFS)
13288 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
13290 if (ix86_decompose_address (x, &addr) == 0
13291 || addr.seg != (TARGET_64BIT ? SEG_FS : SEG_GS)
13292 || addr.disp == NULL_RTX
13293 || GET_CODE (addr.disp) != CONST)
13295 unspec = XEXP (addr.disp, 0);
13296 if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1)))
13297 unspec = XEXP (unspec, 0);
13298 if (GET_CODE (unspec) != UNSPEC || XINT (unspec, 1) != UNSPEC_NTPOFF)
13300 x = XVECEXP (unspec, 0, 0);
13301 gcc_assert (GET_CODE (x) == SYMBOL_REF);
13302 if (unspec != XEXP (addr.disp, 0))
13303 x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.disp, 0), 1));
13306 rtx idx = addr.index;
13307 if (addr.scale != 1)
13308 idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale));
13309 x = gen_rtx_PLUS (Pmode, idx, x);
13312 x = gen_rtx_PLUS (Pmode, addr.base, x);
13313 if (MEM_P (orig_x))
13314 x = replace_equiv_address_nv (orig_x, x);
13318 /* In the name of slightly smaller debug output, and to cater to
13319 general assembler lossage, recognize PIC+GOTOFF and turn it back
13320 into a direct symbol reference.
13322 On Darwin, this is necessary to avoid a crash, because Darwin
13323 has a different PIC label for each routine but the DWARF debugging
13324 information is not associated with any particular routine, so it's
13325 necessary to remove references to the PIC label from RTL stored by
13326 the DWARF output code. */
13329 ix86_delegitimize_address (rtx x)
13331 rtx orig_x = delegitimize_mem_from_attrs (x);
13332 /* addend is NULL or some rtx if x is something+GOTOFF where
13333 something doesn't include the PIC register. */
13334 rtx addend = NULL_RTX;
13335 /* reg_addend is NULL or a multiple of some register. */
13336 rtx reg_addend = NULL_RTX;
13337 /* const_addend is NULL or a const_int. */
13338 rtx const_addend = NULL_RTX;
13339 /* This is the result, or NULL. */
13340 rtx result = NULL_RTX;
13349 if (GET_CODE (x) == CONST
13350 && GET_CODE (XEXP (x, 0)) == PLUS
13351 && GET_MODE (XEXP (x, 0)) == Pmode
13352 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
13353 && GET_CODE (XEXP (XEXP (x, 0), 0)) == UNSPEC
13354 && XINT (XEXP (XEXP (x, 0), 0), 1) == UNSPEC_PCREL)
13356 rtx x2 = XVECEXP (XEXP (XEXP (x, 0), 0), 0, 0);
13357 x = gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 1), x2);
13358 if (MEM_P (orig_x))
13359 x = replace_equiv_address_nv (orig_x, x);
13362 if (GET_CODE (x) != CONST
13363 || GET_CODE (XEXP (x, 0)) != UNSPEC
13364 || (XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
13365 && XINT (XEXP (x, 0), 1) != UNSPEC_PCREL)
13366 || (!MEM_P (orig_x) && XINT (XEXP (x, 0), 1) != UNSPEC_PCREL))
13367 return ix86_delegitimize_tls_address (orig_x);
13368 x = XVECEXP (XEXP (x, 0), 0, 0);
13369 if (GET_MODE (orig_x) != GET_MODE (x) && MEM_P (orig_x))
13371 x = simplify_gen_subreg (GET_MODE (orig_x), x,
13379 if (GET_CODE (x) != PLUS
13380 || GET_CODE (XEXP (x, 1)) != CONST)
13381 return ix86_delegitimize_tls_address (orig_x);
13383 if (ix86_pic_register_p (XEXP (x, 0)))
13384 /* %ebx + GOT/GOTOFF */
13386 else if (GET_CODE (XEXP (x, 0)) == PLUS)
13388 /* %ebx + %reg * scale + GOT/GOTOFF */
13389 reg_addend = XEXP (x, 0);
13390 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
13391 reg_addend = XEXP (reg_addend, 1);
13392 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
13393 reg_addend = XEXP (reg_addend, 0);
13396 reg_addend = NULL_RTX;
13397 addend = XEXP (x, 0);
13401 addend = XEXP (x, 0);
13403 x = XEXP (XEXP (x, 1), 0);
13404 if (GET_CODE (x) == PLUS
13405 && CONST_INT_P (XEXP (x, 1)))
13407 const_addend = XEXP (x, 1);
13411 if (GET_CODE (x) == UNSPEC
13412 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x) && !addend)
13413 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
13414 result = XVECEXP (x, 0, 0);
13416 if (TARGET_MACHO && darwin_local_data_pic (x)
13417 && !MEM_P (orig_x))
13418 result = XVECEXP (x, 0, 0);
13421 return ix86_delegitimize_tls_address (orig_x);
13424 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
13426 result = gen_rtx_PLUS (Pmode, reg_addend, result);
13429 /* If the rest of original X doesn't involve the PIC register, add
13430 addend and subtract pic_offset_table_rtx. This can happen e.g.
13432 leal (%ebx, %ecx, 4), %ecx
13434 movl foo@GOTOFF(%ecx), %edx
13435 in which case we return (%ecx - %ebx) + foo. */
13436 if (pic_offset_table_rtx)
13437 result = gen_rtx_PLUS (Pmode, gen_rtx_MINUS (Pmode, copy_rtx (addend),
13438 pic_offset_table_rtx),
13443 if (GET_MODE (orig_x) != Pmode && MEM_P (orig_x))
13445 result = simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
13446 if (result == NULL_RTX)
13452 /* If X is a machine specific address (i.e. a symbol or label being
13453 referenced as a displacement from the GOT implemented using an
13454 UNSPEC), then return the base term. Otherwise return X. */
13457 ix86_find_base_term (rtx x)
13463 if (GET_CODE (x) != CONST)
13465 term = XEXP (x, 0);
13466 if (GET_CODE (term) == PLUS
13467 && (CONST_INT_P (XEXP (term, 1))
13468 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
13469 term = XEXP (term, 0);
13470 if (GET_CODE (term) != UNSPEC
13471 || (XINT (term, 1) != UNSPEC_GOTPCREL
13472 && XINT (term, 1) != UNSPEC_PCREL))
13475 return XVECEXP (term, 0, 0);
13478 return ix86_delegitimize_address (x);
13482 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
13483 int fp, FILE *file)
13485 const char *suffix;
13487 if (mode == CCFPmode || mode == CCFPUmode)
13489 code = ix86_fp_compare_code_to_integer (code);
13493 code = reverse_condition (code);
13544 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
13548 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13549 Those same assemblers have the same but opposite lossage on cmov. */
13550 if (mode == CCmode)
13551 suffix = fp ? "nbe" : "a";
13552 else if (mode == CCCmode)
13555 gcc_unreachable ();
13571 gcc_unreachable ();
13575 gcc_assert (mode == CCmode || mode == CCCmode);
13592 gcc_unreachable ();
13596 /* ??? As above. */
13597 gcc_assert (mode == CCmode || mode == CCCmode);
13598 suffix = fp ? "nb" : "ae";
13601 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
13605 /* ??? As above. */
13606 if (mode == CCmode)
13608 else if (mode == CCCmode)
13609 suffix = fp ? "nb" : "ae";
13611 gcc_unreachable ();
13614 suffix = fp ? "u" : "p";
13617 suffix = fp ? "nu" : "np";
13620 gcc_unreachable ();
13622 fputs (suffix, file);
13625 /* Print the name of register X to FILE based on its machine mode and number.
13626 If CODE is 'w', pretend the mode is HImode.
13627 If CODE is 'b', pretend the mode is QImode.
13628 If CODE is 'k', pretend the mode is SImode.
13629 If CODE is 'q', pretend the mode is DImode.
13630 If CODE is 'x', pretend the mode is V4SFmode.
13631 If CODE is 't', pretend the mode is V8SFmode.
13632 If CODE is 'h', pretend the reg is the 'high' byte register.
13633 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13634 If CODE is 'd', duplicate the operand for AVX instruction.
13638 print_reg (rtx x, int code, FILE *file)
13641 bool duplicated = code == 'd' && TARGET_AVX;
13643 gcc_assert (x == pc_rtx
13644 || (REGNO (x) != ARG_POINTER_REGNUM
13645 && REGNO (x) != FRAME_POINTER_REGNUM
13646 && REGNO (x) != FLAGS_REG
13647 && REGNO (x) != FPSR_REG
13648 && REGNO (x) != FPCR_REG));
13650 if (ASSEMBLER_DIALECT == ASM_ATT)
13655 gcc_assert (TARGET_64BIT);
13656 fputs ("rip", file);
13660 if (code == 'w' || MMX_REG_P (x))
13662 else if (code == 'b')
13664 else if (code == 'k')
13666 else if (code == 'q')
13668 else if (code == 'y')
13670 else if (code == 'h')
13672 else if (code == 'x')
13674 else if (code == 't')
13677 code = GET_MODE_SIZE (GET_MODE (x));
13679 /* Irritatingly, AMD extended registers use different naming convention
13680 from the normal registers: "r%d[bwd]" */
13681 if (REX_INT_REG_P (x))
13683 gcc_assert (TARGET_64BIT);
13685 fprint_ul (file, REGNO (x) - FIRST_REX_INT_REG + 8);
13689 error ("extended registers have no high halves");
13704 error ("unsupported operand size for extended register");
13714 if (STACK_TOP_P (x))
13723 if (! ANY_FP_REG_P (x))
13724 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
13729 reg = hi_reg_name[REGNO (x)];
13732 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
13734 reg = qi_reg_name[REGNO (x)];
13737 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
13739 reg = qi_high_reg_name[REGNO (x)];
13744 gcc_assert (!duplicated);
13746 fputs (hi_reg_name[REGNO (x)] + 1, file);
13751 gcc_unreachable ();
13757 if (ASSEMBLER_DIALECT == ASM_ATT)
13758 fprintf (file, ", %%%s", reg);
13760 fprintf (file, ", %s", reg);
13764 /* Locate some local-dynamic symbol still in use by this function
13765 so that we can print its name in some tls_local_dynamic_base
13769 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
13773 if (GET_CODE (x) == SYMBOL_REF
13774 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
13776 cfun->machine->some_ld_name = XSTR (x, 0);
13783 static const char *
13784 get_some_local_dynamic_name (void)
13788 if (cfun->machine->some_ld_name)
13789 return cfun->machine->some_ld_name;
13791 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
13792 if (NONDEBUG_INSN_P (insn)
13793 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
13794 return cfun->machine->some_ld_name;
13799 /* Meaning of CODE:
13800 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
13801 C -- print opcode suffix for set/cmov insn.
13802 c -- like C, but print reversed condition
13803 F,f -- likewise, but for floating-point.
13804 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
13806 R -- print the prefix for register names.
13807 z -- print the opcode suffix for the size of the current operand.
13808 Z -- likewise, with special suffixes for x87 instructions.
13809 * -- print a star (in certain assembler syntax)
13810 A -- print an absolute memory reference.
13811 w -- print the operand as if it's a "word" (HImode) even if it isn't.
13812 s -- print a shift double count, followed by the assemblers argument
13814 b -- print the QImode name of the register for the indicated operand.
13815 %b0 would print %al if operands[0] is reg 0.
13816 w -- likewise, print the HImode name of the register.
13817 k -- likewise, print the SImode name of the register.
13818 q -- likewise, print the DImode name of the register.
13819 x -- likewise, print the V4SFmode name of the register.
13820 t -- likewise, print the V8SFmode name of the register.
13821 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
13822 y -- print "st(0)" instead of "st" as a register.
13823 d -- print duplicated register operand for AVX instruction.
13824 D -- print condition for SSE cmp instruction.
13825 P -- if PIC, print an @PLT suffix.
13826 p -- print raw symbol name.
13827 X -- don't print any sort of PIC '@' suffix for a symbol.
13828 & -- print some in-use local-dynamic symbol name.
13829 H -- print a memory address offset by 8; used for sse high-parts
13830 Y -- print condition for XOP pcom* instruction.
13831 + -- print a branch hint as 'cs' or 'ds' prefix
13832 ; -- print a semicolon (after prefixes due to bug in older gas).
13833 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
13834 @ -- print a segment register of thread base pointer load
13838 ix86_print_operand (FILE *file, rtx x, int code)
13845 if (ASSEMBLER_DIALECT == ASM_ATT)
13851 const char *name = get_some_local_dynamic_name ();
13853 output_operand_lossage ("'%%&' used without any "
13854 "local dynamic TLS references");
13856 assemble_name (file, name);
13861 switch (ASSEMBLER_DIALECT)
13868 /* Intel syntax. For absolute addresses, registers should not
13869 be surrounded by braces. */
13873 ix86_print_operand (file, x, 0);
13880 gcc_unreachable ();
13883 ix86_print_operand (file, x, 0);
13888 if (ASSEMBLER_DIALECT == ASM_ATT)
13893 if (ASSEMBLER_DIALECT == ASM_ATT)
13898 if (ASSEMBLER_DIALECT == ASM_ATT)
13903 if (ASSEMBLER_DIALECT == ASM_ATT)
13908 if (ASSEMBLER_DIALECT == ASM_ATT)
13913 if (ASSEMBLER_DIALECT == ASM_ATT)
13918 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
13920 /* Opcodes don't get size suffixes if using Intel opcodes. */
13921 if (ASSEMBLER_DIALECT == ASM_INTEL)
13924 switch (GET_MODE_SIZE (GET_MODE (x)))
13943 output_operand_lossage
13944 ("invalid operand size for operand code '%c'", code);
13949 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
13951 (0, "non-integer operand used with operand code '%c'", code);
13955 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
13956 if (ASSEMBLER_DIALECT == ASM_INTEL)
13959 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
13961 switch (GET_MODE_SIZE (GET_MODE (x)))
13964 #ifdef HAVE_AS_IX86_FILDS
13974 #ifdef HAVE_AS_IX86_FILDQ
13977 fputs ("ll", file);
13985 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
13987 /* 387 opcodes don't get size suffixes
13988 if the operands are registers. */
13989 if (STACK_REG_P (x))
13992 switch (GET_MODE_SIZE (GET_MODE (x)))
14013 output_operand_lossage
14014 ("invalid operand type used with operand code '%c'", code);
14018 output_operand_lossage
14019 ("invalid operand size for operand code '%c'", code);
14037 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
14039 ix86_print_operand (file, x, 0);
14040 fputs (", ", file);
14045 /* Little bit of braindamage here. The SSE compare instructions
14046 does use completely different names for the comparisons that the
14047 fp conditional moves. */
14050 switch (GET_CODE (x))
14053 fputs ("eq", file);
14056 fputs ("eq_us", file);
14059 fputs ("lt", file);
14062 fputs ("nge", file);
14065 fputs ("le", file);
14068 fputs ("ngt", file);
14071 fputs ("unord", file);
14074 fputs ("neq", file);
14077 fputs ("neq_oq", file);
14080 fputs ("ge", file);
14083 fputs ("nlt", file);
14086 fputs ("gt", file);
14089 fputs ("nle", file);
14092 fputs ("ord", file);
14095 output_operand_lossage ("operand is not a condition code, "
14096 "invalid operand code 'D'");
14102 switch (GET_CODE (x))
14106 fputs ("eq", file);
14110 fputs ("lt", file);
14114 fputs ("le", file);
14117 fputs ("unord", file);
14121 fputs ("neq", file);
14125 fputs ("nlt", file);
14129 fputs ("nle", file);
14132 fputs ("ord", file);
14135 output_operand_lossage ("operand is not a condition code, "
14136 "invalid operand code 'D'");
14142 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14143 if (ASSEMBLER_DIALECT == ASM_ATT)
14145 switch (GET_MODE (x))
14147 case HImode: putc ('w', file); break;
14149 case SFmode: putc ('l', file); break;
14151 case DFmode: putc ('q', file); break;
14152 default: gcc_unreachable ();
14159 if (!COMPARISON_P (x))
14161 output_operand_lossage ("operand is neither a constant nor a "
14162 "condition code, invalid operand code "
14166 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
14169 if (!COMPARISON_P (x))
14171 output_operand_lossage ("operand is neither a constant nor a "
14172 "condition code, invalid operand code "
14176 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14177 if (ASSEMBLER_DIALECT == ASM_ATT)
14180 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
14183 /* Like above, but reverse condition */
14185 /* Check to see if argument to %c is really a constant
14186 and not a condition code which needs to be reversed. */
14187 if (!COMPARISON_P (x))
14189 output_operand_lossage ("operand is neither a constant nor a "
14190 "condition code, invalid operand "
14194 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
14197 if (!COMPARISON_P (x))
14199 output_operand_lossage ("operand is neither a constant nor a "
14200 "condition code, invalid operand "
14204 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14205 if (ASSEMBLER_DIALECT == ASM_ATT)
14208 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
14212 if (!offsettable_memref_p (x))
14214 output_operand_lossage ("operand is not an offsettable memory "
14215 "reference, invalid operand "
14219 /* It doesn't actually matter what mode we use here, as we're
14220 only going to use this for printing. */
14221 x = adjust_address_nv (x, DImode, 8);
14229 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
14232 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
14235 int pred_val = INTVAL (XEXP (x, 0));
14237 if (pred_val < REG_BR_PROB_BASE * 45 / 100
14238 || pred_val > REG_BR_PROB_BASE * 55 / 100)
14240 int taken = pred_val > REG_BR_PROB_BASE / 2;
14241 int cputaken = final_forward_branch_p (current_output_insn) == 0;
14243 /* Emit hints only in the case default branch prediction
14244 heuristics would fail. */
14245 if (taken != cputaken)
14247 /* We use 3e (DS) prefix for taken branches and
14248 2e (CS) prefix for not taken branches. */
14250 fputs ("ds ; ", file);
14252 fputs ("cs ; ", file);
14260 switch (GET_CODE (x))
14263 fputs ("neq", file);
14266 fputs ("eq", file);
14270 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
14274 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
14278 fputs ("le", file);
14282 fputs ("lt", file);
14285 fputs ("unord", file);
14288 fputs ("ord", file);
14291 fputs ("ueq", file);
14294 fputs ("nlt", file);
14297 fputs ("nle", file);
14300 fputs ("ule", file);
14303 fputs ("ult", file);
14306 fputs ("une", file);
14309 output_operand_lossage ("operand is not a condition code, "
14310 "invalid operand code 'Y'");
14316 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14322 if (ASSEMBLER_DIALECT == ASM_ATT)
14325 /* The kernel uses a different segment register for performance
14326 reasons; a system call would not have to trash the userspace
14327 segment register, which would be expensive. */
14328 if (TARGET_64BIT && ix86_cmodel != CM_KERNEL)
14329 fputs ("fs", file);
14331 fputs ("gs", file);
14335 putc (TARGET_AVX2 ? 'i' : 'f', file);
14339 output_operand_lossage ("invalid operand code '%c'", code);
14344 print_reg (x, code, file);
14346 else if (MEM_P (x))
14348 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14349 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
14350 && GET_MODE (x) != BLKmode)
14353 switch (GET_MODE_SIZE (GET_MODE (x)))
14355 case 1: size = "BYTE"; break;
14356 case 2: size = "WORD"; break;
14357 case 4: size = "DWORD"; break;
14358 case 8: size = "QWORD"; break;
14359 case 12: size = "TBYTE"; break;
14361 if (GET_MODE (x) == XFmode)
14366 case 32: size = "YMMWORD"; break;
14368 gcc_unreachable ();
14371 /* Check for explicit size override (codes 'b', 'w', 'k',
14375 else if (code == 'w')
14377 else if (code == 'k')
14379 else if (code == 'q')
14381 else if (code == 'x')
14384 fputs (size, file);
14385 fputs (" PTR ", file);
14389 /* Avoid (%rip) for call operands. */
14390 if (CONSTANT_ADDRESS_P (x) && code == 'P'
14391 && !CONST_INT_P (x))
14392 output_addr_const (file, x);
14393 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
14394 output_operand_lossage ("invalid constraints for operand");
14396 output_address (x);
14399 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14404 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
14405 REAL_VALUE_TO_TARGET_SINGLE (r, l);
14407 if (ASSEMBLER_DIALECT == ASM_ATT)
14409 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14411 fprintf (file, "0x%08llx", (unsigned long long) (int) l);
14413 fprintf (file, "0x%08x", (unsigned int) l);
14416 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14421 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
14422 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
14424 if (ASSEMBLER_DIALECT == ASM_ATT)
14426 fprintf (file, "0x%lx%08lx", l[1] & 0xffffffff, l[0] & 0xffffffff);
14429 /* These float cases don't actually occur as immediate operands. */
14430 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
14434 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
14435 fputs (dstr, file);
14440 /* We have patterns that allow zero sets of memory, for instance.
14441 In 64-bit mode, we should probably support all 8-byte vectors,
14442 since we can in fact encode that into an immediate. */
14443 if (GET_CODE (x) == CONST_VECTOR)
14445 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
14449 if (code != 'P' && code != 'p')
14451 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
14453 if (ASSEMBLER_DIALECT == ASM_ATT)
14456 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
14457 || GET_CODE (x) == LABEL_REF)
14459 if (ASSEMBLER_DIALECT == ASM_ATT)
14462 fputs ("OFFSET FLAT:", file);
14465 if (CONST_INT_P (x))
14466 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
14467 else if (flag_pic || MACHOPIC_INDIRECT)
14468 output_pic_addr_const (file, x, code);
14470 output_addr_const (file, x);
14475 ix86_print_operand_punct_valid_p (unsigned char code)
14477 return (code == '@' || code == '*' || code == '+'
14478 || code == '&' || code == ';' || code == '~');
14481 /* Print a memory operand whose address is ADDR. */
14484 ix86_print_operand_address (FILE *file, rtx addr)
14486 struct ix86_address parts;
14487 rtx base, index, disp;
14492 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_VSIBADDR)
14494 ok = ix86_decompose_address (XVECEXP (addr, 0, 0), &parts);
14495 gcc_assert (parts.index == NULL_RTX);
14496 parts.index = XVECEXP (addr, 0, 1);
14497 parts.scale = INTVAL (XVECEXP (addr, 0, 2));
14498 addr = XVECEXP (addr, 0, 0);
14502 ok = ix86_decompose_address (addr, &parts);
14506 if (parts.base && GET_CODE (parts.base) == SUBREG)
14508 rtx tmp = SUBREG_REG (parts.base);
14509 parts.base = simplify_subreg (GET_MODE (parts.base),
14510 tmp, GET_MODE (tmp), 0);
14513 if (parts.index && GET_CODE (parts.index) == SUBREG)
14515 rtx tmp = SUBREG_REG (parts.index);
14516 parts.index = simplify_subreg (GET_MODE (parts.index),
14517 tmp, GET_MODE (tmp), 0);
14521 index = parts.index;
14523 scale = parts.scale;
14531 if (ASSEMBLER_DIALECT == ASM_ATT)
14533 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
14536 gcc_unreachable ();
14539 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14540 if (TARGET_64BIT && !base && !index)
14544 if (GET_CODE (disp) == CONST
14545 && GET_CODE (XEXP (disp, 0)) == PLUS
14546 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
14547 symbol = XEXP (XEXP (disp, 0), 0);
14549 if (GET_CODE (symbol) == LABEL_REF
14550 || (GET_CODE (symbol) == SYMBOL_REF
14551 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
14554 if (!base && !index)
14556 /* Displacement only requires special attention. */
14558 if (CONST_INT_P (disp))
14560 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
14561 fputs ("ds:", file);
14562 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
14565 output_pic_addr_const (file, disp, 0);
14567 output_addr_const (file, disp);
14573 /* Print SImode registers for zero-extended addresses to force
14574 addr32 prefix. Otherwise print DImode registers to avoid it. */
14576 code = ((GET_CODE (addr) == ZERO_EXTEND
14577 || GET_CODE (addr) == AND)
14581 if (ASSEMBLER_DIALECT == ASM_ATT)
14586 output_pic_addr_const (file, disp, 0);
14587 else if (GET_CODE (disp) == LABEL_REF)
14588 output_asm_label (disp);
14590 output_addr_const (file, disp);
14595 print_reg (base, code, file);
14599 print_reg (index, vsib ? 0 : code, file);
14600 if (scale != 1 || vsib)
14601 fprintf (file, ",%d", scale);
14607 rtx offset = NULL_RTX;
14611 /* Pull out the offset of a symbol; print any symbol itself. */
14612 if (GET_CODE (disp) == CONST
14613 && GET_CODE (XEXP (disp, 0)) == PLUS
14614 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
14616 offset = XEXP (XEXP (disp, 0), 1);
14617 disp = gen_rtx_CONST (VOIDmode,
14618 XEXP (XEXP (disp, 0), 0));
14622 output_pic_addr_const (file, disp, 0);
14623 else if (GET_CODE (disp) == LABEL_REF)
14624 output_asm_label (disp);
14625 else if (CONST_INT_P (disp))
14628 output_addr_const (file, disp);
14634 print_reg (base, code, file);
14637 if (INTVAL (offset) >= 0)
14639 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
14643 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
14650 print_reg (index, vsib ? 0 : code, file);
14651 if (scale != 1 || vsib)
14652 fprintf (file, "*%d", scale);
14659 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14662 i386_asm_output_addr_const_extra (FILE *file, rtx x)
14666 if (GET_CODE (x) != UNSPEC)
14669 op = XVECEXP (x, 0, 0);
14670 switch (XINT (x, 1))
14672 case UNSPEC_GOTTPOFF:
14673 output_addr_const (file, op);
14674 /* FIXME: This might be @TPOFF in Sun ld. */
14675 fputs ("@gottpoff", file);
14678 output_addr_const (file, op);
14679 fputs ("@tpoff", file);
14681 case UNSPEC_NTPOFF:
14682 output_addr_const (file, op);
14684 fputs ("@tpoff", file);
14686 fputs ("@ntpoff", file);
14688 case UNSPEC_DTPOFF:
14689 output_addr_const (file, op);
14690 fputs ("@dtpoff", file);
14692 case UNSPEC_GOTNTPOFF:
14693 output_addr_const (file, op);
14695 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
14696 "@gottpoff(%rip)" : "@gottpoff[rip]", file);
14698 fputs ("@gotntpoff", file);
14700 case UNSPEC_INDNTPOFF:
14701 output_addr_const (file, op);
14702 fputs ("@indntpoff", file);
14705 case UNSPEC_MACHOPIC_OFFSET:
14706 output_addr_const (file, op);
14708 machopic_output_function_base_name (file);
14712 case UNSPEC_STACK_CHECK:
14716 gcc_assert (flag_split_stack);
14718 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14719 offset = TARGET_THREAD_SPLIT_STACK_OFFSET;
14721 gcc_unreachable ();
14724 fprintf (file, "%s:%d", TARGET_64BIT ? "%fs" : "%gs", offset);
14735 /* Split one or more double-mode RTL references into pairs of half-mode
14736 references. The RTL can be REG, offsettable MEM, integer constant, or
14737 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14738 split and "num" is its length. lo_half and hi_half are output arrays
14739 that parallel "operands". */
14742 split_double_mode (enum machine_mode mode, rtx operands[],
14743 int num, rtx lo_half[], rtx hi_half[])
14745 enum machine_mode half_mode;
14751 half_mode = DImode;
14754 half_mode = SImode;
14757 gcc_unreachable ();
14760 byte = GET_MODE_SIZE (half_mode);
14764 rtx op = operands[num];
14766 /* simplify_subreg refuse to split volatile memory addresses,
14767 but we still have to handle it. */
14770 lo_half[num] = adjust_address (op, half_mode, 0);
14771 hi_half[num] = adjust_address (op, half_mode, byte);
14775 lo_half[num] = simplify_gen_subreg (half_mode, op,
14776 GET_MODE (op) == VOIDmode
14777 ? mode : GET_MODE (op), 0);
14778 hi_half[num] = simplify_gen_subreg (half_mode, op,
14779 GET_MODE (op) == VOIDmode
14780 ? mode : GET_MODE (op), byte);
14785 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
14786 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
14787 is the expression of the binary operation. The output may either be
14788 emitted here, or returned to the caller, like all output_* functions.
14790 There is no guarantee that the operands are the same mode, as they
14791 might be within FLOAT or FLOAT_EXTEND expressions. */
14793 #ifndef SYSV386_COMPAT
14794 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
14795 wants to fix the assemblers because that causes incompatibility
14796 with gcc. No-one wants to fix gcc because that causes
14797 incompatibility with assemblers... You can use the option of
14798 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
14799 #define SYSV386_COMPAT 1
14803 output_387_binary_op (rtx insn, rtx *operands)
14805 static char buf[40];
14808 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
14810 #ifdef ENABLE_CHECKING
14811 /* Even if we do not want to check the inputs, this documents input
14812 constraints. Which helps in understanding the following code. */
14813 if (STACK_REG_P (operands[0])
14814 && ((REG_P (operands[1])
14815 && REGNO (operands[0]) == REGNO (operands[1])
14816 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
14817 || (REG_P (operands[2])
14818 && REGNO (operands[0]) == REGNO (operands[2])
14819 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
14820 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
14823 gcc_assert (is_sse);
14826 switch (GET_CODE (operands[3]))
14829 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
14830 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
14838 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
14839 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
14847 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
14848 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
14856 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
14857 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
14865 gcc_unreachable ();
14872 strcpy (buf, ssep);
14873 if (GET_MODE (operands[0]) == SFmode)
14874 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
14876 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
14880 strcpy (buf, ssep + 1);
14881 if (GET_MODE (operands[0]) == SFmode)
14882 strcat (buf, "ss\t{%2, %0|%0, %2}");
14884 strcat (buf, "sd\t{%2, %0|%0, %2}");
14890 switch (GET_CODE (operands[3]))
14894 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
14896 rtx temp = operands[2];
14897 operands[2] = operands[1];
14898 operands[1] = temp;
14901 /* know operands[0] == operands[1]. */
14903 if (MEM_P (operands[2]))
14909 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
14911 if (STACK_TOP_P (operands[0]))
14912 /* How is it that we are storing to a dead operand[2]?
14913 Well, presumably operands[1] is dead too. We can't
14914 store the result to st(0) as st(0) gets popped on this
14915 instruction. Instead store to operands[2] (which I
14916 think has to be st(1)). st(1) will be popped later.
14917 gcc <= 2.8.1 didn't have this check and generated
14918 assembly code that the Unixware assembler rejected. */
14919 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
14921 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
14925 if (STACK_TOP_P (operands[0]))
14926 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
14928 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
14933 if (MEM_P (operands[1]))
14939 if (MEM_P (operands[2]))
14945 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
14948 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
14949 derived assemblers, confusingly reverse the direction of
14950 the operation for fsub{r} and fdiv{r} when the
14951 destination register is not st(0). The Intel assembler
14952 doesn't have this brain damage. Read !SYSV386_COMPAT to
14953 figure out what the hardware really does. */
14954 if (STACK_TOP_P (operands[0]))
14955 p = "{p\t%0, %2|rp\t%2, %0}";
14957 p = "{rp\t%2, %0|p\t%0, %2}";
14959 if (STACK_TOP_P (operands[0]))
14960 /* As above for fmul/fadd, we can't store to st(0). */
14961 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
14963 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
14968 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
14971 if (STACK_TOP_P (operands[0]))
14972 p = "{rp\t%0, %1|p\t%1, %0}";
14974 p = "{p\t%1, %0|rp\t%0, %1}";
14976 if (STACK_TOP_P (operands[0]))
14977 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
14979 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
14984 if (STACK_TOP_P (operands[0]))
14986 if (STACK_TOP_P (operands[1]))
14987 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
14989 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
14992 else if (STACK_TOP_P (operands[1]))
14995 p = "{\t%1, %0|r\t%0, %1}";
14997 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
15003 p = "{r\t%2, %0|\t%0, %2}";
15005 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
15011 gcc_unreachable ();
15018 /* Return needed mode for entity in optimize_mode_switching pass. */
15021 ix86_mode_needed (int entity, rtx insn)
15023 enum attr_i387_cw mode;
15025 /* The mode UNINITIALIZED is used to store control word after a
15026 function call or ASM pattern. The mode ANY specify that function
15027 has no requirements on the control word and make no changes in the
15028 bits we are interested in. */
15031 || (NONJUMP_INSN_P (insn)
15032 && (asm_noperands (PATTERN (insn)) >= 0
15033 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
15034 return I387_CW_UNINITIALIZED;
15036 if (recog_memoized (insn) < 0)
15037 return I387_CW_ANY;
15039 mode = get_attr_i387_cw (insn);
15044 if (mode == I387_CW_TRUNC)
15049 if (mode == I387_CW_FLOOR)
15054 if (mode == I387_CW_CEIL)
15059 if (mode == I387_CW_MASK_PM)
15064 gcc_unreachable ();
15067 return I387_CW_ANY;
15070 /* Output code to initialize control word copies used by trunc?f?i and
15071 rounding patterns. CURRENT_MODE is set to current control word,
15072 while NEW_MODE is set to new control word. */
15075 emit_i387_cw_initialization (int mode)
15077 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
15080 enum ix86_stack_slot slot;
15082 rtx reg = gen_reg_rtx (HImode);
15084 emit_insn (gen_x86_fnstcw_1 (stored_mode));
15085 emit_move_insn (reg, copy_rtx (stored_mode));
15087 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
15088 || optimize_function_for_size_p (cfun))
15092 case I387_CW_TRUNC:
15093 /* round toward zero (truncate) */
15094 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
15095 slot = SLOT_CW_TRUNC;
15098 case I387_CW_FLOOR:
15099 /* round down toward -oo */
15100 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
15101 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
15102 slot = SLOT_CW_FLOOR;
15106 /* round up toward +oo */
15107 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
15108 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
15109 slot = SLOT_CW_CEIL;
15112 case I387_CW_MASK_PM:
15113 /* mask precision exception for nearbyint() */
15114 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
15115 slot = SLOT_CW_MASK_PM;
15119 gcc_unreachable ();
15126 case I387_CW_TRUNC:
15127 /* round toward zero (truncate) */
15128 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
15129 slot = SLOT_CW_TRUNC;
15132 case I387_CW_FLOOR:
15133 /* round down toward -oo */
15134 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
15135 slot = SLOT_CW_FLOOR;
15139 /* round up toward +oo */
15140 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
15141 slot = SLOT_CW_CEIL;
15144 case I387_CW_MASK_PM:
15145 /* mask precision exception for nearbyint() */
15146 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
15147 slot = SLOT_CW_MASK_PM;
15151 gcc_unreachable ();
15155 gcc_assert (slot < MAX_386_STACK_LOCALS);
15157 new_mode = assign_386_stack_local (HImode, slot);
15158 emit_move_insn (new_mode, reg);
15161 /* Output code for INSN to convert a float to a signed int. OPERANDS
15162 are the insn operands. The output may be [HSD]Imode and the input
15163 operand may be [SDX]Fmode. */
15166 output_fix_trunc (rtx insn, rtx *operands, bool fisttp)
15168 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
15169 int dimode_p = GET_MODE (operands[0]) == DImode;
15170 int round_mode = get_attr_i387_cw (insn);
15172 /* Jump through a hoop or two for DImode, since the hardware has no
15173 non-popping instruction. We used to do this a different way, but
15174 that was somewhat fragile and broke with post-reload splitters. */
15175 if ((dimode_p || fisttp) && !stack_top_dies)
15176 output_asm_insn ("fld\t%y1", operands);
15178 gcc_assert (STACK_TOP_P (operands[1]));
15179 gcc_assert (MEM_P (operands[0]));
15180 gcc_assert (GET_MODE (operands[1]) != TFmode);
15183 output_asm_insn ("fisttp%Z0\t%0", operands);
15186 if (round_mode != I387_CW_ANY)
15187 output_asm_insn ("fldcw\t%3", operands);
15188 if (stack_top_dies || dimode_p)
15189 output_asm_insn ("fistp%Z0\t%0", operands);
15191 output_asm_insn ("fist%Z0\t%0", operands);
15192 if (round_mode != I387_CW_ANY)
15193 output_asm_insn ("fldcw\t%2", operands);
15199 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15200 have the values zero or one, indicates the ffreep insn's operand
15201 from the OPERANDS array. */
15203 static const char *
15204 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
15206 if (TARGET_USE_FFREEP)
15207 #ifdef HAVE_AS_IX86_FFREEP
15208 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
15211 static char retval[32];
15212 int regno = REGNO (operands[opno]);
15214 gcc_assert (FP_REGNO_P (regno));
15216 regno -= FIRST_STACK_REG;
15218 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
15223 return opno ? "fstp\t%y1" : "fstp\t%y0";
15227 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15228 should be used. UNORDERED_P is true when fucom should be used. */
15231 output_fp_compare (rtx insn, rtx *operands, bool eflags_p, bool unordered_p)
15233 int stack_top_dies;
15234 rtx cmp_op0, cmp_op1;
15235 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
15239 cmp_op0 = operands[0];
15240 cmp_op1 = operands[1];
15244 cmp_op0 = operands[1];
15245 cmp_op1 = operands[2];
15250 if (GET_MODE (operands[0]) == SFmode)
15252 return "%vucomiss\t{%1, %0|%0, %1}";
15254 return "%vcomiss\t{%1, %0|%0, %1}";
15257 return "%vucomisd\t{%1, %0|%0, %1}";
15259 return "%vcomisd\t{%1, %0|%0, %1}";
15262 gcc_assert (STACK_TOP_P (cmp_op0));
15264 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
15266 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
15268 if (stack_top_dies)
15270 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
15271 return output_387_ffreep (operands, 1);
15274 return "ftst\n\tfnstsw\t%0";
15277 if (STACK_REG_P (cmp_op1)
15279 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
15280 && REGNO (cmp_op1) != FIRST_STACK_REG)
15282 /* If both the top of the 387 stack dies, and the other operand
15283 is also a stack register that dies, then this must be a
15284 `fcompp' float compare */
15288 /* There is no double popping fcomi variant. Fortunately,
15289 eflags is immune from the fstp's cc clobbering. */
15291 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
15293 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
15294 return output_387_ffreep (operands, 0);
15299 return "fucompp\n\tfnstsw\t%0";
15301 return "fcompp\n\tfnstsw\t%0";
15306 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15308 static const char * const alt[16] =
15310 "fcom%Z2\t%y2\n\tfnstsw\t%0",
15311 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
15312 "fucom%Z2\t%y2\n\tfnstsw\t%0",
15313 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
15315 "ficom%Z2\t%y2\n\tfnstsw\t%0",
15316 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
15320 "fcomi\t{%y1, %0|%0, %y1}",
15321 "fcomip\t{%y1, %0|%0, %y1}",
15322 "fucomi\t{%y1, %0|%0, %y1}",
15323 "fucomip\t{%y1, %0|%0, %y1}",
15334 mask = eflags_p << 3;
15335 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
15336 mask |= unordered_p << 1;
15337 mask |= stack_top_dies;
15339 gcc_assert (mask < 16);
15348 ix86_output_addr_vec_elt (FILE *file, int value)
15350 const char *directive = ASM_LONG;
15354 directive = ASM_QUAD;
15356 gcc_assert (!TARGET_64BIT);
15359 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
15363 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
15365 const char *directive = ASM_LONG;
15368 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
15369 directive = ASM_QUAD;
15371 gcc_assert (!TARGET_64BIT);
15373 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15374 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
15375 fprintf (file, "%s%s%d-%s%d\n",
15376 directive, LPREFIX, value, LPREFIX, rel);
15377 else if (HAVE_AS_GOTOFF_IN_DATA)
15378 fprintf (file, ASM_LONG "%s%d@GOTOFF\n", LPREFIX, value);
15380 else if (TARGET_MACHO)
15382 fprintf (file, ASM_LONG "%s%d-", LPREFIX, value);
15383 machopic_output_function_base_name (file);
15388 asm_fprintf (file, ASM_LONG "%U%s+[.-%s%d]\n",
15389 GOT_SYMBOL_NAME, LPREFIX, value);
15392 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15396 ix86_expand_clear (rtx dest)
15400 /* We play register width games, which are only valid after reload. */
15401 gcc_assert (reload_completed);
15403 /* Avoid HImode and its attendant prefix byte. */
15404 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
15405 dest = gen_rtx_REG (SImode, REGNO (dest));
15406 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
15408 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15409 if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
15411 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
15412 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
15418 /* X is an unchanging MEM. If it is a constant pool reference, return
15419 the constant pool rtx, else NULL. */
15422 maybe_get_pool_constant (rtx x)
15424 x = ix86_delegitimize_address (XEXP (x, 0));
15426 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
15427 return get_pool_constant (x);
15433 ix86_expand_move (enum machine_mode mode, rtx operands[])
15436 enum tls_model model;
15441 if (GET_CODE (op1) == SYMBOL_REF)
15443 model = SYMBOL_REF_TLS_MODEL (op1);
15446 op1 = legitimize_tls_address (op1, model, true);
15447 op1 = force_operand (op1, op0);
15450 if (GET_MODE (op1) != mode)
15451 op1 = convert_to_mode (mode, op1, 1);
15453 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
15454 && SYMBOL_REF_DLLIMPORT_P (op1))
15455 op1 = legitimize_dllimport_symbol (op1, false);
15457 else if (GET_CODE (op1) == CONST
15458 && GET_CODE (XEXP (op1, 0)) == PLUS
15459 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
15461 rtx addend = XEXP (XEXP (op1, 0), 1);
15462 rtx symbol = XEXP (XEXP (op1, 0), 0);
15465 model = SYMBOL_REF_TLS_MODEL (symbol);
15467 tmp = legitimize_tls_address (symbol, model, true);
15468 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
15469 && SYMBOL_REF_DLLIMPORT_P (symbol))
15470 tmp = legitimize_dllimport_symbol (symbol, true);
15474 tmp = force_operand (tmp, NULL);
15475 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
15476 op0, 1, OPTAB_DIRECT);
15479 if (GET_MODE (tmp) != mode)
15480 op1 = convert_to_mode (mode, tmp, 1);
15484 if ((flag_pic || MACHOPIC_INDIRECT)
15485 && symbolic_operand (op1, mode))
15487 if (TARGET_MACHO && !TARGET_64BIT)
15490 /* dynamic-no-pic */
15491 if (MACHOPIC_INDIRECT)
15493 rtx temp = ((reload_in_progress
15494 || ((op0 && REG_P (op0))
15496 ? op0 : gen_reg_rtx (Pmode));
15497 op1 = machopic_indirect_data_reference (op1, temp);
15499 op1 = machopic_legitimize_pic_address (op1, mode,
15500 temp == op1 ? 0 : temp);
15502 if (op0 != op1 && GET_CODE (op0) != MEM)
15504 rtx insn = gen_rtx_SET (VOIDmode, op0, op1);
15508 if (GET_CODE (op0) == MEM)
15509 op1 = force_reg (Pmode, op1);
15513 if (GET_CODE (temp) != REG)
15514 temp = gen_reg_rtx (Pmode);
15515 temp = legitimize_pic_address (op1, temp);
15520 /* dynamic-no-pic */
15526 op1 = force_reg (mode, op1);
15527 else if (!(TARGET_64BIT && x86_64_movabs_operand (op1, DImode)))
15529 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
15530 op1 = legitimize_pic_address (op1, reg);
15533 if (GET_MODE (op1) != mode)
15534 op1 = convert_to_mode (mode, op1, 1);
15541 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
15542 || !push_operand (op0, mode))
15544 op1 = force_reg (mode, op1);
15546 if (push_operand (op0, mode)
15547 && ! general_no_elim_operand (op1, mode))
15548 op1 = copy_to_mode_reg (mode, op1);
15550 /* Force large constants in 64bit compilation into register
15551 to get them CSEed. */
15552 if (can_create_pseudo_p ()
15553 && (mode == DImode) && TARGET_64BIT
15554 && immediate_operand (op1, mode)
15555 && !x86_64_zext_immediate_operand (op1, VOIDmode)
15556 && !register_operand (op0, mode)
15558 op1 = copy_to_mode_reg (mode, op1);
15560 if (can_create_pseudo_p ()
15561 && FLOAT_MODE_P (mode)
15562 && GET_CODE (op1) == CONST_DOUBLE)
15564 /* If we are loading a floating point constant to a register,
15565 force the value to memory now, since we'll get better code
15566 out the back end. */
15568 op1 = validize_mem (force_const_mem (mode, op1));
15569 if (!register_operand (op0, mode))
15571 rtx temp = gen_reg_rtx (mode);
15572 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
15573 emit_move_insn (op0, temp);
15579 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
15583 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
15585 rtx op0 = operands[0], op1 = operands[1];
15586 unsigned int align = GET_MODE_ALIGNMENT (mode);
15588 /* Force constants other than zero into memory. We do not know how
15589 the instructions used to build constants modify the upper 64 bits
15590 of the register, once we have that information we may be able
15591 to handle some of them more efficiently. */
15592 if (can_create_pseudo_p ()
15593 && register_operand (op0, mode)
15594 && (CONSTANT_P (op1)
15595 || (GET_CODE (op1) == SUBREG
15596 && CONSTANT_P (SUBREG_REG (op1))))
15597 && !standard_sse_constant_p (op1))
15598 op1 = validize_mem (force_const_mem (mode, op1));
15600 /* We need to check memory alignment for SSE mode since attribute
15601 can make operands unaligned. */
15602 if (can_create_pseudo_p ()
15603 && SSE_REG_MODE_P (mode)
15604 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
15605 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
15609 /* ix86_expand_vector_move_misalign() does not like constants ... */
15610 if (CONSTANT_P (op1)
15611 || (GET_CODE (op1) == SUBREG
15612 && CONSTANT_P (SUBREG_REG (op1))))
15613 op1 = validize_mem (force_const_mem (mode, op1));
15615 /* ... nor both arguments in memory. */
15616 if (!register_operand (op0, mode)
15617 && !register_operand (op1, mode))
15618 op1 = force_reg (mode, op1);
15620 tmp[0] = op0; tmp[1] = op1;
15621 ix86_expand_vector_move_misalign (mode, tmp);
15625 /* Make operand1 a register if it isn't already. */
15626 if (can_create_pseudo_p ()
15627 && !register_operand (op0, mode)
15628 && !register_operand (op1, mode))
15630 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
15634 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
15637 /* Split 32-byte AVX unaligned load and store if needed. */
15640 ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
15643 rtx (*extract) (rtx, rtx, rtx);
15644 rtx (*move_unaligned) (rtx, rtx);
15645 enum machine_mode mode;
15647 switch (GET_MODE (op0))
15650 gcc_unreachable ();
15652 extract = gen_avx_vextractf128v32qi;
15653 move_unaligned = gen_avx_movdqu256;
15657 extract = gen_avx_vextractf128v8sf;
15658 move_unaligned = gen_avx_movups256;
15662 extract = gen_avx_vextractf128v4df;
15663 move_unaligned = gen_avx_movupd256;
15668 if (MEM_P (op1) && TARGET_AVX256_SPLIT_UNALIGNED_LOAD)
15670 rtx r = gen_reg_rtx (mode);
15671 m = adjust_address (op1, mode, 0);
15672 emit_move_insn (r, m);
15673 m = adjust_address (op1, mode, 16);
15674 r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m);
15675 emit_move_insn (op0, r);
15677 else if (MEM_P (op0) && TARGET_AVX256_SPLIT_UNALIGNED_STORE)
15679 m = adjust_address (op0, mode, 0);
15680 emit_insn (extract (m, op1, const0_rtx));
15681 m = adjust_address (op0, mode, 16);
15682 emit_insn (extract (m, op1, const1_rtx));
15685 emit_insn (move_unaligned (op0, op1));
15688 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
15689 straight to ix86_expand_vector_move. */
15690 /* Code generation for scalar reg-reg moves of single and double precision data:
15691 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
15695 if (x86_sse_partial_reg_dependency == true)
15700 Code generation for scalar loads of double precision data:
15701 if (x86_sse_split_regs == true)
15702 movlpd mem, reg (gas syntax)
15706 Code generation for unaligned packed loads of single precision data
15707 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
15708 if (x86_sse_unaligned_move_optimal)
15711 if (x86_sse_partial_reg_dependency == true)
15723 Code generation for unaligned packed loads of double precision data
15724 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
15725 if (x86_sse_unaligned_move_optimal)
15728 if (x86_sse_split_regs == true)
15741 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
15750 switch (GET_MODE_CLASS (mode))
15752 case MODE_VECTOR_INT:
15754 switch (GET_MODE_SIZE (mode))
15757 /* If we're optimizing for size, movups is the smallest. */
15758 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
15760 op0 = gen_lowpart (V4SFmode, op0);
15761 op1 = gen_lowpart (V4SFmode, op1);
15762 emit_insn (gen_sse_movups (op0, op1));
15765 op0 = gen_lowpart (V16QImode, op0);
15766 op1 = gen_lowpart (V16QImode, op1);
15767 emit_insn (gen_sse2_movdqu (op0, op1));
15770 op0 = gen_lowpart (V32QImode, op0);
15771 op1 = gen_lowpart (V32QImode, op1);
15772 ix86_avx256_split_vector_move_misalign (op0, op1);
15775 gcc_unreachable ();
15778 case MODE_VECTOR_FLOAT:
15779 op0 = gen_lowpart (mode, op0);
15780 op1 = gen_lowpart (mode, op1);
15785 emit_insn (gen_sse_movups (op0, op1));
15788 ix86_avx256_split_vector_move_misalign (op0, op1);
15791 if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
15793 op0 = gen_lowpart (V4SFmode, op0);
15794 op1 = gen_lowpart (V4SFmode, op1);
15795 emit_insn (gen_sse_movups (op0, op1));
15798 emit_insn (gen_sse2_movupd (op0, op1));
15801 ix86_avx256_split_vector_move_misalign (op0, op1);
15804 gcc_unreachable ();
15809 gcc_unreachable ();
15817 /* If we're optimizing for size, movups is the smallest. */
15818 if (optimize_insn_for_size_p ()
15819 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
15821 op0 = gen_lowpart (V4SFmode, op0);
15822 op1 = gen_lowpart (V4SFmode, op1);
15823 emit_insn (gen_sse_movups (op0, op1));
15827 /* ??? If we have typed data, then it would appear that using
15828 movdqu is the only way to get unaligned data loaded with
15830 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
15832 op0 = gen_lowpart (V16QImode, op0);
15833 op1 = gen_lowpart (V16QImode, op1);
15834 emit_insn (gen_sse2_movdqu (op0, op1));
15838 if (TARGET_SSE2 && mode == V2DFmode)
15842 if (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL)
15844 op0 = gen_lowpart (V2DFmode, op0);
15845 op1 = gen_lowpart (V2DFmode, op1);
15846 emit_insn (gen_sse2_movupd (op0, op1));
15850 /* When SSE registers are split into halves, we can avoid
15851 writing to the top half twice. */
15852 if (TARGET_SSE_SPLIT_REGS)
15854 emit_clobber (op0);
15859 /* ??? Not sure about the best option for the Intel chips.
15860 The following would seem to satisfy; the register is
15861 entirely cleared, breaking the dependency chain. We
15862 then store to the upper half, with a dependency depth
15863 of one. A rumor has it that Intel recommends two movsd
15864 followed by an unpacklpd, but this is unconfirmed. And
15865 given that the dependency depth of the unpacklpd would
15866 still be one, I'm not sure why this would be better. */
15867 zero = CONST0_RTX (V2DFmode);
15870 m = adjust_address (op1, DFmode, 0);
15871 emit_insn (gen_sse2_loadlpd (op0, zero, m));
15872 m = adjust_address (op1, DFmode, 8);
15873 emit_insn (gen_sse2_loadhpd (op0, op0, m));
15877 if (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL)
15879 op0 = gen_lowpart (V4SFmode, op0);
15880 op1 = gen_lowpart (V4SFmode, op1);
15881 emit_insn (gen_sse_movups (op0, op1));
15885 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
15886 emit_move_insn (op0, CONST0_RTX (mode));
15888 emit_clobber (op0);
15890 if (mode != V4SFmode)
15891 op0 = gen_lowpart (V4SFmode, op0);
15892 m = adjust_address (op1, V2SFmode, 0);
15893 emit_insn (gen_sse_loadlps (op0, op0, m));
15894 m = adjust_address (op1, V2SFmode, 8);
15895 emit_insn (gen_sse_loadhps (op0, op0, m));
15898 else if (MEM_P (op0))
15900 /* If we're optimizing for size, movups is the smallest. */
15901 if (optimize_insn_for_size_p ()
15902 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
15904 op0 = gen_lowpart (V4SFmode, op0);
15905 op1 = gen_lowpart (V4SFmode, op1);
15906 emit_insn (gen_sse_movups (op0, op1));
15910 /* ??? Similar to above, only less clear because of quote
15911 typeless stores unquote. */
15912 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
15913 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
15915 op0 = gen_lowpart (V16QImode, op0);
15916 op1 = gen_lowpart (V16QImode, op1);
15917 emit_insn (gen_sse2_movdqu (op0, op1));
15921 if (TARGET_SSE2 && mode == V2DFmode)
15923 if (TARGET_SSE_UNALIGNED_STORE_OPTIMAL)
15925 op0 = gen_lowpart (V2DFmode, op0);
15926 op1 = gen_lowpart (V2DFmode, op1);
15927 emit_insn (gen_sse2_movupd (op0, op1));
15931 m = adjust_address (op0, DFmode, 0);
15932 emit_insn (gen_sse2_storelpd (m, op1));
15933 m = adjust_address (op0, DFmode, 8);
15934 emit_insn (gen_sse2_storehpd (m, op1));
15939 if (mode != V4SFmode)
15940 op1 = gen_lowpart (V4SFmode, op1);
15942 if (TARGET_SSE_UNALIGNED_STORE_OPTIMAL)
15944 op0 = gen_lowpart (V4SFmode, op0);
15945 emit_insn (gen_sse_movups (op0, op1));
15949 m = adjust_address (op0, V2SFmode, 0);
15950 emit_insn (gen_sse_storelps (m, op1));
15951 m = adjust_address (op0, V2SFmode, 8);
15952 emit_insn (gen_sse_storehps (m, op1));
15957 gcc_unreachable ();
15960 /* Expand a push in MODE. This is some mode for which we do not support
15961 proper push instructions, at least from the registers that we expect
15962 the value to live in. */
15965 ix86_expand_push (enum machine_mode mode, rtx x)
15969 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
15970 GEN_INT (-GET_MODE_SIZE (mode)),
15971 stack_pointer_rtx, 1, OPTAB_DIRECT);
15972 if (tmp != stack_pointer_rtx)
15973 emit_move_insn (stack_pointer_rtx, tmp);
15975 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
15977 /* When we push an operand onto stack, it has to be aligned at least
15978 at the function argument boundary. However since we don't have
15979 the argument type, we can't determine the actual argument
15981 emit_move_insn (tmp, x);
15984 /* Helper function of ix86_fixup_binary_operands to canonicalize
15985 operand order. Returns true if the operands should be swapped. */
15988 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
15991 rtx dst = operands[0];
15992 rtx src1 = operands[1];
15993 rtx src2 = operands[2];
15995 /* If the operation is not commutative, we can't do anything. */
15996 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
15999 /* Highest priority is that src1 should match dst. */
16000 if (rtx_equal_p (dst, src1))
16002 if (rtx_equal_p (dst, src2))
16005 /* Next highest priority is that immediate constants come second. */
16006 if (immediate_operand (src2, mode))
16008 if (immediate_operand (src1, mode))
16011 /* Lowest priority is that memory references should come second. */
16021 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16022 destination to use for the operation. If different from the true
16023 destination in operands[0], a copy operation will be required. */
16026 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
16029 rtx dst = operands[0];
16030 rtx src1 = operands[1];
16031 rtx src2 = operands[2];
16033 /* Canonicalize operand order. */
16034 if (ix86_swap_binary_operands_p (code, mode, operands))
16038 /* It is invalid to swap operands of different modes. */
16039 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
16046 /* Both source operands cannot be in memory. */
16047 if (MEM_P (src1) && MEM_P (src2))
16049 /* Optimization: Only read from memory once. */
16050 if (rtx_equal_p (src1, src2))
16052 src2 = force_reg (mode, src2);
16056 src2 = force_reg (mode, src2);
16059 /* If the destination is memory, and we do not have matching source
16060 operands, do things in registers. */
16061 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
16062 dst = gen_reg_rtx (mode);
16064 /* Source 1 cannot be a constant. */
16065 if (CONSTANT_P (src1))
16066 src1 = force_reg (mode, src1);
16068 /* Source 1 cannot be a non-matching memory. */
16069 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
16070 src1 = force_reg (mode, src1);
16072 /* Improve address combine. */
16074 && GET_MODE_CLASS (mode) == MODE_INT
16076 src2 = force_reg (mode, src2);
16078 operands[1] = src1;
16079 operands[2] = src2;
16083 /* Similarly, but assume that the destination has already been
16084 set up properly. */
16087 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
16088 enum machine_mode mode, rtx operands[])
16090 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
16091 gcc_assert (dst == operands[0]);
16094 /* Attempt to expand a binary operator. Make the expansion closer to the
16095 actual machine, then just general_operand, which will allow 3 separate
16096 memory references (one output, two input) in a single insn. */
16099 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
16102 rtx src1, src2, dst, op, clob;
16104 dst = ix86_fixup_binary_operands (code, mode, operands);
16105 src1 = operands[1];
16106 src2 = operands[2];
16108 /* Emit the instruction. */
16110 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
16111 if (reload_in_progress)
16113 /* Reload doesn't know about the flags register, and doesn't know that
16114 it doesn't want to clobber it. We can only do this with PLUS. */
16115 gcc_assert (code == PLUS);
16118 else if (reload_completed
16120 && !rtx_equal_p (dst, src1))
16122 /* This is going to be an LEA; avoid splitting it later. */
16127 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
16128 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
16131 /* Fix up the destination if needed. */
16132 if (dst != operands[0])
16133 emit_move_insn (operands[0], dst);
16136 /* Return TRUE or FALSE depending on whether the binary operator meets the
16137 appropriate constraints. */
16140 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
16143 rtx dst = operands[0];
16144 rtx src1 = operands[1];
16145 rtx src2 = operands[2];
16147 /* Both source operands cannot be in memory. */
16148 if (MEM_P (src1) && MEM_P (src2))
16151 /* Canonicalize operand order for commutative operators. */
16152 if (ix86_swap_binary_operands_p (code, mode, operands))
16159 /* If the destination is memory, we must have a matching source operand. */
16160 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
16163 /* Source 1 cannot be a constant. */
16164 if (CONSTANT_P (src1))
16167 /* Source 1 cannot be a non-matching memory. */
16168 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
16169 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16170 return (code == AND
16173 || (TARGET_64BIT && mode == DImode))
16174 && satisfies_constraint_L (src2));
16179 /* Attempt to expand a unary operator. Make the expansion closer to the
16180 actual machine, then just general_operand, which will allow 2 separate
16181 memory references (one output, one input) in a single insn. */
16184 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
16187 int matching_memory;
16188 rtx src, dst, op, clob;
16193 /* If the destination is memory, and we do not have matching source
16194 operands, do things in registers. */
16195 matching_memory = 0;
16198 if (rtx_equal_p (dst, src))
16199 matching_memory = 1;
16201 dst = gen_reg_rtx (mode);
16204 /* When source operand is memory, destination must match. */
16205 if (MEM_P (src) && !matching_memory)
16206 src = force_reg (mode, src);
16208 /* Emit the instruction. */
16210 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
16211 if (reload_in_progress || code == NOT)
16213 /* Reload doesn't know about the flags register, and doesn't know that
16214 it doesn't want to clobber it. */
16215 gcc_assert (code == NOT);
16220 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
16221 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
16224 /* Fix up the destination if needed. */
16225 if (dst != operands[0])
16226 emit_move_insn (operands[0], dst);
16229 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16230 divisor are within the range [0-255]. */
16233 ix86_split_idivmod (enum machine_mode mode, rtx operands[],
16236 rtx end_label, qimode_label;
16237 rtx insn, div, mod;
16238 rtx scratch, tmp0, tmp1, tmp2;
16239 rtx (*gen_divmod4_1) (rtx, rtx, rtx, rtx);
16240 rtx (*gen_zero_extend) (rtx, rtx);
16241 rtx (*gen_test_ccno_1) (rtx, rtx);
16246 gen_divmod4_1 = signed_p ? gen_divmodsi4_1 : gen_udivmodsi4_1;
16247 gen_test_ccno_1 = gen_testsi_ccno_1;
16248 gen_zero_extend = gen_zero_extendqisi2;
16251 gen_divmod4_1 = signed_p ? gen_divmoddi4_1 : gen_udivmoddi4_1;
16252 gen_test_ccno_1 = gen_testdi_ccno_1;
16253 gen_zero_extend = gen_zero_extendqidi2;
16256 gcc_unreachable ();
16259 end_label = gen_label_rtx ();
16260 qimode_label = gen_label_rtx ();
16262 scratch = gen_reg_rtx (mode);
16264 /* Use 8bit unsigned divimod if dividend and divisor are within
16265 the range [0-255]. */
16266 emit_move_insn (scratch, operands[2]);
16267 scratch = expand_simple_binop (mode, IOR, scratch, operands[3],
16268 scratch, 1, OPTAB_DIRECT);
16269 emit_insn (gen_test_ccno_1 (scratch, GEN_INT (-0x100)));
16270 tmp0 = gen_rtx_REG (CCNOmode, FLAGS_REG);
16271 tmp0 = gen_rtx_EQ (VOIDmode, tmp0, const0_rtx);
16272 tmp0 = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp0,
16273 gen_rtx_LABEL_REF (VOIDmode, qimode_label),
16275 insn = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp0));
16276 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16277 JUMP_LABEL (insn) = qimode_label;
16279 /* Generate original signed/unsigned divimod. */
16280 div = gen_divmod4_1 (operands[0], operands[1],
16281 operands[2], operands[3]);
16284 /* Branch to the end. */
16285 emit_jump_insn (gen_jump (end_label));
16288 /* Generate 8bit unsigned divide. */
16289 emit_label (qimode_label);
16290 /* Don't use operands[0] for result of 8bit divide since not all
16291 registers support QImode ZERO_EXTRACT. */
16292 tmp0 = simplify_gen_subreg (HImode, scratch, mode, 0);
16293 tmp1 = simplify_gen_subreg (HImode, operands[2], mode, 0);
16294 tmp2 = simplify_gen_subreg (QImode, operands[3], mode, 0);
16295 emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, tmp2));
16299 div = gen_rtx_DIV (SImode, operands[2], operands[3]);
16300 mod = gen_rtx_MOD (SImode, operands[2], operands[3]);
16304 div = gen_rtx_UDIV (SImode, operands[2], operands[3]);
16305 mod = gen_rtx_UMOD (SImode, operands[2], operands[3]);
16308 /* Extract remainder from AH. */
16309 tmp1 = gen_rtx_ZERO_EXTRACT (mode, tmp0, GEN_INT (8), GEN_INT (8));
16310 if (REG_P (operands[1]))
16311 insn = emit_move_insn (operands[1], tmp1);
16314 /* Need a new scratch register since the old one has result
16316 scratch = gen_reg_rtx (mode);
16317 emit_move_insn (scratch, tmp1);
16318 insn = emit_move_insn (operands[1], scratch);
16320 set_unique_reg_note (insn, REG_EQUAL, mod);
16322 /* Zero extend quotient from AL. */
16323 tmp1 = gen_lowpart (QImode, tmp0);
16324 insn = emit_insn (gen_zero_extend (operands[0], tmp1));
16325 set_unique_reg_note (insn, REG_EQUAL, div);
16327 emit_label (end_label);
16330 #define LEA_MAX_STALL (3)
16331 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16333 /* Increase given DISTANCE in half-cycles according to
16334 dependencies between PREV and NEXT instructions.
16335 Add 1 half-cycle if there is no dependency and
16336 go to next cycle if there is some dependecy. */
16338 static unsigned int
16339 increase_distance (rtx prev, rtx next, unsigned int distance)
16344 if (!prev || !next)
16345 return distance + (distance & 1) + 2;
16347 if (!DF_INSN_USES (next) || !DF_INSN_DEFS (prev))
16348 return distance + 1;
16350 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
16351 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
16352 if (!DF_REF_IS_ARTIFICIAL (*def_rec)
16353 && DF_REF_REGNO (*use_rec) == DF_REF_REGNO (*def_rec))
16354 return distance + (distance & 1) + 2;
16356 return distance + 1;
16359 /* Function checks if instruction INSN defines register number
16360 REGNO1 or REGNO2. */
16363 insn_defines_reg (unsigned int regno1, unsigned int regno2,
16368 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
16369 if (DF_REF_REG_DEF_P (*def_rec)
16370 && !DF_REF_IS_ARTIFICIAL (*def_rec)
16371 && (regno1 == DF_REF_REGNO (*def_rec)
16372 || regno2 == DF_REF_REGNO (*def_rec)))
16380 /* Function checks if instruction INSN uses register number
16381 REGNO as a part of address expression. */
16384 insn_uses_reg_mem (unsigned int regno, rtx insn)
16388 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
16389 if (DF_REF_REG_MEM_P (*use_rec) && regno == DF_REF_REGNO (*use_rec))
16395 /* Search backward for non-agu definition of register number REGNO1
16396 or register number REGNO2 in basic block starting from instruction
16397 START up to head of basic block or instruction INSN.
16399 Function puts true value into *FOUND var if definition was found
16400 and false otherwise.
16402 Distance in half-cycles between START and found instruction or head
16403 of BB is added to DISTANCE and returned. */
16406 distance_non_agu_define_in_bb (unsigned int regno1, unsigned int regno2,
16407 rtx insn, int distance,
16408 rtx start, bool *found)
16410 basic_block bb = start ? BLOCK_FOR_INSN (start) : NULL;
16418 && distance < LEA_SEARCH_THRESHOLD)
16420 if (NONDEBUG_INSN_P (prev) && NONJUMP_INSN_P (prev))
16422 distance = increase_distance (prev, next, distance);
16423 if (insn_defines_reg (regno1, regno2, prev))
16425 if (recog_memoized (prev) < 0
16426 || get_attr_type (prev) != TYPE_LEA)
16435 if (prev == BB_HEAD (bb))
16438 prev = PREV_INSN (prev);
16444 /* Search backward for non-agu definition of register number REGNO1
16445 or register number REGNO2 in INSN's basic block until
16446 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16447 2. Reach neighbour BBs boundary, or
16448 3. Reach agu definition.
16449 Returns the distance between the non-agu definition point and INSN.
16450 If no definition point, returns -1. */
16453 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
16456 basic_block bb = BLOCK_FOR_INSN (insn);
16458 bool found = false;
16460 if (insn != BB_HEAD (bb))
16461 distance = distance_non_agu_define_in_bb (regno1, regno2, insn,
16462 distance, PREV_INSN (insn),
16465 if (!found && distance < LEA_SEARCH_THRESHOLD)
16469 bool simple_loop = false;
16471 FOR_EACH_EDGE (e, ei, bb->preds)
16474 simple_loop = true;
16479 distance = distance_non_agu_define_in_bb (regno1, regno2,
16481 BB_END (bb), &found);
16484 int shortest_dist = -1;
16485 bool found_in_bb = false;
16487 FOR_EACH_EDGE (e, ei, bb->preds)
16490 = distance_non_agu_define_in_bb (regno1, regno2,
16496 if (shortest_dist < 0)
16497 shortest_dist = bb_dist;
16498 else if (bb_dist > 0)
16499 shortest_dist = MIN (bb_dist, shortest_dist);
16505 distance = shortest_dist;
16509 /* get_attr_type may modify recog data. We want to make sure
16510 that recog data is valid for instruction INSN, on which
16511 distance_non_agu_define is called. INSN is unchanged here. */
16512 extract_insn_cached (insn);
16517 return distance >> 1;
16520 /* Return the distance in half-cycles between INSN and the next
16521 insn that uses register number REGNO in memory address added
16522 to DISTANCE. Return -1 if REGNO0 is set.
16524 Put true value into *FOUND if register usage was found and
16526 Put true value into *REDEFINED if register redefinition was
16527 found and false otherwise. */
16530 distance_agu_use_in_bb (unsigned int regno,
16531 rtx insn, int distance, rtx start,
16532 bool *found, bool *redefined)
16534 basic_block bb = start ? BLOCK_FOR_INSN (start) : NULL;
16539 *redefined = false;
16543 && distance < LEA_SEARCH_THRESHOLD)
16545 if (NONDEBUG_INSN_P (next) && NONJUMP_INSN_P (next))
16547 distance = increase_distance(prev, next, distance);
16548 if (insn_uses_reg_mem (regno, next))
16550 /* Return DISTANCE if OP0 is used in memory
16551 address in NEXT. */
16556 if (insn_defines_reg (regno, INVALID_REGNUM, next))
16558 /* Return -1 if OP0 is set in NEXT. */
16566 if (next == BB_END (bb))
16569 next = NEXT_INSN (next);
16575 /* Return the distance between INSN and the next insn that uses
16576 register number REGNO0 in memory address. Return -1 if no such
16577 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
16580 distance_agu_use (unsigned int regno0, rtx insn)
16582 basic_block bb = BLOCK_FOR_INSN (insn);
16584 bool found = false;
16585 bool redefined = false;
16587 if (insn != BB_END (bb))
16588 distance = distance_agu_use_in_bb (regno0, insn, distance,
16590 &found, &redefined);
16592 if (!found && !redefined && distance < LEA_SEARCH_THRESHOLD)
16596 bool simple_loop = false;
16598 FOR_EACH_EDGE (e, ei, bb->succs)
16601 simple_loop = true;
16606 distance = distance_agu_use_in_bb (regno0, insn,
16607 distance, BB_HEAD (bb),
16608 &found, &redefined);
16611 int shortest_dist = -1;
16612 bool found_in_bb = false;
16613 bool redefined_in_bb = false;
16615 FOR_EACH_EDGE (e, ei, bb->succs)
16618 = distance_agu_use_in_bb (regno0, insn,
16619 distance, BB_HEAD (e->dest),
16620 &found_in_bb, &redefined_in_bb);
16623 if (shortest_dist < 0)
16624 shortest_dist = bb_dist;
16625 else if (bb_dist > 0)
16626 shortest_dist = MIN (bb_dist, shortest_dist);
16632 distance = shortest_dist;
16636 if (!found || redefined)
16639 return distance >> 1;
16642 /* Define this macro to tune LEA priority vs ADD, it take effect when
16643 there is a dilemma of choicing LEA or ADD
16644 Negative value: ADD is more preferred than LEA
16646 Positive value: LEA is more preferred than ADD*/
16647 #define IX86_LEA_PRIORITY 0
16649 /* Return true if usage of lea INSN has performance advantage
16650 over a sequence of instructions. Instructions sequence has
16651 SPLIT_COST cycles higher latency than lea latency. */
16654 ix86_lea_outperforms (rtx insn, unsigned int regno0, unsigned int regno1,
16655 unsigned int regno2, unsigned int split_cost)
16657 int dist_define, dist_use;
16659 dist_define = distance_non_agu_define (regno1, regno2, insn);
16660 dist_use = distance_agu_use (regno0, insn);
16662 if (dist_define < 0 || dist_define >= LEA_MAX_STALL)
16664 /* If there is no non AGU operand definition, no AGU
16665 operand usage and split cost is 0 then both lea
16666 and non lea variants have same priority. Currently
16667 we prefer lea for 64 bit code and non lea on 32 bit
16669 if (dist_use < 0 && split_cost == 0)
16670 return TARGET_64BIT || IX86_LEA_PRIORITY;
16675 /* With longer definitions distance lea is more preferable.
16676 Here we change it to take into account splitting cost and
16678 dist_define += split_cost + IX86_LEA_PRIORITY;
16680 /* If there is no use in memory addess then we just check
16681 that split cost does not exceed AGU stall. */
16683 return dist_define >= LEA_MAX_STALL;
16685 /* If this insn has both backward non-agu dependence and forward
16686 agu dependence, the one with short distance takes effect. */
16687 return dist_define >= dist_use;
16690 /* Return true if it is legal to clobber flags by INSN and
16691 false otherwise. */
16694 ix86_ok_to_clobber_flags (rtx insn)
16696 basic_block bb = BLOCK_FOR_INSN (insn);
16702 if (NONDEBUG_INSN_P (insn))
16704 for (use = DF_INSN_USES (insn); *use; use++)
16705 if (DF_REF_REG_USE_P (*use) && DF_REF_REGNO (*use) == FLAGS_REG)
16708 if (insn_defines_reg (FLAGS_REG, INVALID_REGNUM, insn))
16712 if (insn == BB_END (bb))
16715 insn = NEXT_INSN (insn);
16718 live = df_get_live_out(bb);
16719 return !REGNO_REG_SET_P (live, FLAGS_REG);
16722 /* Return true if we need to split op0 = op1 + op2 into a sequence of
16723 move and add to avoid AGU stalls. */
16726 ix86_avoid_lea_for_add (rtx insn, rtx operands[])
16728 unsigned int regno0 = true_regnum (operands[0]);
16729 unsigned int regno1 = true_regnum (operands[1]);
16730 unsigned int regno2 = true_regnum (operands[2]);
16732 /* Check if we need to optimize. */
16733 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
16736 /* Check it is correct to split here. */
16737 if (!ix86_ok_to_clobber_flags(insn))
16740 /* We need to split only adds with non destructive
16741 destination operand. */
16742 if (regno0 == regno1 || regno0 == regno2)
16745 return !ix86_lea_outperforms (insn, regno0, regno1, regno2, 1);
16748 /* Return true if we should emit lea instruction instead of mov
16752 ix86_use_lea_for_mov (rtx insn, rtx operands[])
16754 unsigned int regno0;
16755 unsigned int regno1;
16757 /* Check if we need to optimize. */
16758 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
16761 /* Use lea for reg to reg moves only. */
16762 if (!REG_P (operands[0]) || !REG_P (operands[1]))
16765 regno0 = true_regnum (operands[0]);
16766 regno1 = true_regnum (operands[1]);
16768 return ix86_lea_outperforms (insn, regno0, regno1, -1, 0);
16771 /* Return true if we need to split lea into a sequence of
16772 instructions to avoid AGU stalls. */
16775 ix86_avoid_lea_for_addr (rtx insn, rtx operands[])
16777 unsigned int regno0 = true_regnum (operands[0]) ;
16778 unsigned int regno1 = -1;
16779 unsigned int regno2 = -1;
16780 unsigned int split_cost = 0;
16781 struct ix86_address parts;
16784 /* Check we need to optimize. */
16785 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
16788 /* Check it is correct to split here. */
16789 if (!ix86_ok_to_clobber_flags(insn))
16792 ok = ix86_decompose_address (operands[1], &parts);
16795 /* We should not split into add if non legitimate pic
16796 operand is used as displacement. */
16797 if (parts.disp && flag_pic && !LEGITIMATE_PIC_OPERAND_P (parts.disp))
16801 regno1 = true_regnum (parts.base);
16803 regno2 = true_regnum (parts.index);
16805 /* Compute how many cycles we will add to execution time
16806 if split lea into a sequence of instructions. */
16807 if (parts.base || parts.index)
16809 /* Have to use mov instruction if non desctructive
16810 destination form is used. */
16811 if (regno1 != regno0 && regno2 != regno0)
16814 /* Have to add index to base if both exist. */
16815 if (parts.base && parts.index)
16818 /* Have to use shift and adds if scale is 2 or greater. */
16819 if (parts.scale > 1)
16821 if (regno0 != regno1)
16823 else if (regno2 == regno0)
16826 split_cost += parts.scale;
16829 /* Have to use add instruction with immediate if
16830 disp is non zero. */
16831 if (parts.disp && parts.disp != const0_rtx)
16834 /* Subtract the price of lea. */
16838 return !ix86_lea_outperforms (insn, regno0, regno1, regno2, split_cost);
16841 /* Emit x86 binary operand CODE in mode MODE, where the first operand
16842 matches destination. RTX includes clobber of FLAGS_REG. */
16845 ix86_emit_binop (enum rtx_code code, enum machine_mode mode,
16850 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, dst, src));
16851 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
16853 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
16856 /* Split lea instructions into a sequence of instructions
16857 which are executed on ALU to avoid AGU stalls.
16858 It is assumed that it is allowed to clobber flags register
16859 at lea position. */
16862 ix86_split_lea_for_addr (rtx operands[], enum machine_mode mode)
16864 unsigned int regno0 = true_regnum (operands[0]) ;
16865 unsigned int regno1 = INVALID_REGNUM;
16866 unsigned int regno2 = INVALID_REGNUM;
16867 struct ix86_address parts;
16871 ok = ix86_decompose_address (operands[1], &parts);
16876 if (GET_MODE (parts.base) != mode)
16877 parts.base = gen_rtx_SUBREG (mode, parts.base, 0);
16878 regno1 = true_regnum (parts.base);
16883 if (GET_MODE (parts.index) != mode)
16884 parts.index = gen_rtx_SUBREG (mode, parts.index, 0);
16885 regno2 = true_regnum (parts.index);
16888 if (parts.scale > 1)
16890 /* Case r1 = r1 + ... */
16891 if (regno1 == regno0)
16893 /* If we have a case r1 = r1 + C * r1 then we
16894 should use multiplication which is very
16895 expensive. Assume cost model is wrong if we
16896 have such case here. */
16897 gcc_assert (regno2 != regno0);
16899 for (adds = parts.scale; adds > 0; adds--)
16900 ix86_emit_binop (PLUS, mode, operands[0], parts.index);
16904 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
16905 if (regno0 != regno2)
16906 emit_insn (gen_rtx_SET (VOIDmode, operands[0], parts.index));
16908 /* Use shift for scaling. */
16909 ix86_emit_binop (ASHIFT, mode, operands[0],
16910 GEN_INT (exact_log2 (parts.scale)));
16913 ix86_emit_binop (PLUS, mode, operands[0], parts.base);
16915 if (parts.disp && parts.disp != const0_rtx)
16916 ix86_emit_binop (PLUS, mode, operands[0], parts.disp);
16919 else if (!parts.base && !parts.index)
16921 gcc_assert(parts.disp);
16922 emit_insn (gen_rtx_SET (VOIDmode, operands[0], parts.disp));
16928 if (regno0 != regno2)
16929 emit_insn (gen_rtx_SET (VOIDmode, operands[0], parts.index));
16931 else if (!parts.index)
16933 if (regno0 != regno1)
16934 emit_insn (gen_rtx_SET (VOIDmode, operands[0], parts.base));
16938 if (regno0 == regno1)
16940 else if (regno0 == regno2)
16944 emit_insn (gen_rtx_SET (VOIDmode, operands[0], parts.base));
16948 ix86_emit_binop (PLUS, mode, operands[0], tmp);
16951 if (parts.disp && parts.disp != const0_rtx)
16952 ix86_emit_binop (PLUS, mode, operands[0], parts.disp);
16956 /* Return true if it is ok to optimize an ADD operation to LEA
16957 operation to avoid flag register consumation. For most processors,
16958 ADD is faster than LEA. For the processors like ATOM, if the
16959 destination register of LEA holds an actual address which will be
16960 used soon, LEA is better and otherwise ADD is better. */
16963 ix86_lea_for_add_ok (rtx insn, rtx operands[])
16965 unsigned int regno0 = true_regnum (operands[0]);
16966 unsigned int regno1 = true_regnum (operands[1]);
16967 unsigned int regno2 = true_regnum (operands[2]);
16969 /* If a = b + c, (a!=b && a!=c), must use lea form. */
16970 if (regno0 != regno1 && regno0 != regno2)
16973 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
16976 return ix86_lea_outperforms (insn, regno0, regno1, regno2, 0);
16979 /* Return true if destination reg of SET_BODY is shift count of
16983 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
16989 /* Retrieve destination of SET_BODY. */
16990 switch (GET_CODE (set_body))
16993 set_dest = SET_DEST (set_body);
16994 if (!set_dest || !REG_P (set_dest))
16998 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
16999 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
17007 /* Retrieve shift count of USE_BODY. */
17008 switch (GET_CODE (use_body))
17011 shift_rtx = XEXP (use_body, 1);
17014 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
17015 if (ix86_dep_by_shift_count_body (set_body,
17016 XVECEXP (use_body, 0, i)))
17024 && (GET_CODE (shift_rtx) == ASHIFT
17025 || GET_CODE (shift_rtx) == LSHIFTRT
17026 || GET_CODE (shift_rtx) == ASHIFTRT
17027 || GET_CODE (shift_rtx) == ROTATE
17028 || GET_CODE (shift_rtx) == ROTATERT))
17030 rtx shift_count = XEXP (shift_rtx, 1);
17032 /* Return true if shift count is dest of SET_BODY. */
17033 if (REG_P (shift_count)
17034 && true_regnum (set_dest) == true_regnum (shift_count))
17041 /* Return true if destination reg of SET_INSN is shift count of
17045 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
17047 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
17048 PATTERN (use_insn));
17051 /* Return TRUE or FALSE depending on whether the unary operator meets the
17052 appropriate constraints. */
17055 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
17056 enum machine_mode mode ATTRIBUTE_UNUSED,
17057 rtx operands[2] ATTRIBUTE_UNUSED)
17059 /* If one of operands is memory, source and destination must match. */
17060 if ((MEM_P (operands[0])
17061 || MEM_P (operands[1]))
17062 && ! rtx_equal_p (operands[0], operands[1]))
17067 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17068 are ok, keeping in mind the possible movddup alternative. */
17071 ix86_vec_interleave_v2df_operator_ok (rtx operands[3], bool high)
17073 if (MEM_P (operands[0]))
17074 return rtx_equal_p (operands[0], operands[1 + high]);
17075 if (MEM_P (operands[1]) && MEM_P (operands[2]))
17076 return TARGET_SSE3 && rtx_equal_p (operands[1], operands[2]);
17080 /* Post-reload splitter for converting an SF or DFmode value in an
17081 SSE register into an unsigned SImode. */
17084 ix86_split_convert_uns_si_sse (rtx operands[])
17086 enum machine_mode vecmode;
17087 rtx value, large, zero_or_two31, input, two31, x;
17089 large = operands[1];
17090 zero_or_two31 = operands[2];
17091 input = operands[3];
17092 two31 = operands[4];
17093 vecmode = GET_MODE (large);
17094 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
17096 /* Load up the value into the low element. We must ensure that the other
17097 elements are valid floats -- zero is the easiest such value. */
17100 if (vecmode == V4SFmode)
17101 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
17103 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
17107 input = gen_rtx_REG (vecmode, REGNO (input));
17108 emit_move_insn (value, CONST0_RTX (vecmode));
17109 if (vecmode == V4SFmode)
17110 emit_insn (gen_sse_movss (value, value, input));
17112 emit_insn (gen_sse2_movsd (value, value, input));
17115 emit_move_insn (large, two31);
17116 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
17118 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
17119 emit_insn (gen_rtx_SET (VOIDmode, large, x));
17121 x = gen_rtx_AND (vecmode, zero_or_two31, large);
17122 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
17124 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
17125 emit_insn (gen_rtx_SET (VOIDmode, value, x));
17127 large = gen_rtx_REG (V4SImode, REGNO (large));
17128 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
17130 x = gen_rtx_REG (V4SImode, REGNO (value));
17131 if (vecmode == V4SFmode)
17132 emit_insn (gen_fix_truncv4sfv4si2 (x, value));
17134 emit_insn (gen_sse2_cvttpd2dq (x, value));
17137 emit_insn (gen_xorv4si3 (value, value, large));
17140 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17141 Expects the 64-bit DImode to be supplied in a pair of integral
17142 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17143 -mfpmath=sse, !optimize_size only. */
17146 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
17148 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
17149 rtx int_xmm, fp_xmm;
17150 rtx biases, exponents;
17153 int_xmm = gen_reg_rtx (V4SImode);
17154 if (TARGET_INTER_UNIT_MOVES)
17155 emit_insn (gen_movdi_to_sse (int_xmm, input));
17156 else if (TARGET_SSE_SPLIT_REGS)
17158 emit_clobber (int_xmm);
17159 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
17163 x = gen_reg_rtx (V2DImode);
17164 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
17165 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
17168 x = gen_rtx_CONST_VECTOR (V4SImode,
17169 gen_rtvec (4, GEN_INT (0x43300000UL),
17170 GEN_INT (0x45300000UL),
17171 const0_rtx, const0_rtx));
17172 exponents = validize_mem (force_const_mem (V4SImode, x));
17174 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17175 emit_insn (gen_vec_interleave_lowv4si (int_xmm, int_xmm, exponents));
17177 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17178 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17179 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17180 (0x1.0p84 + double(fp_value_hi_xmm)).
17181 Note these exponents differ by 32. */
17183 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
17185 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17186 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17187 real_ldexp (&bias_lo_rvt, &dconst1, 52);
17188 real_ldexp (&bias_hi_rvt, &dconst1, 84);
17189 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
17190 x = const_double_from_real_value (bias_hi_rvt, DFmode);
17191 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
17192 biases = validize_mem (force_const_mem (V2DFmode, biases));
17193 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
17195 /* Add the upper and lower DFmode values together. */
17197 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
17200 x = copy_to_mode_reg (V2DFmode, fp_xmm);
17201 emit_insn (gen_vec_interleave_highv2df (fp_xmm, fp_xmm, fp_xmm));
17202 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
17205 ix86_expand_vector_extract (false, target, fp_xmm, 0);
17208 /* Not used, but eases macroization of patterns. */
17210 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
17211 rtx input ATTRIBUTE_UNUSED)
17213 gcc_unreachable ();
17216 /* Convert an unsigned SImode value into a DFmode. Only currently used
17217 for SSE, but applicable anywhere. */
17220 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
17222 REAL_VALUE_TYPE TWO31r;
17225 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
17226 NULL, 1, OPTAB_DIRECT);
17228 fp = gen_reg_rtx (DFmode);
17229 emit_insn (gen_floatsidf2 (fp, x));
17231 real_ldexp (&TWO31r, &dconst1, 31);
17232 x = const_double_from_real_value (TWO31r, DFmode);
17234 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
17236 emit_move_insn (target, x);
17239 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17240 32-bit mode; otherwise we have a direct convert instruction. */
17243 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
17245 REAL_VALUE_TYPE TWO32r;
17246 rtx fp_lo, fp_hi, x;
17248 fp_lo = gen_reg_rtx (DFmode);
17249 fp_hi = gen_reg_rtx (DFmode);
17251 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
17253 real_ldexp (&TWO32r, &dconst1, 32);
17254 x = const_double_from_real_value (TWO32r, DFmode);
17255 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
17257 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
17259 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
17262 emit_move_insn (target, x);
17265 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17266 For x86_32, -mfpmath=sse, !optimize_size only. */
17268 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
17270 REAL_VALUE_TYPE ONE16r;
17271 rtx fp_hi, fp_lo, int_hi, int_lo, x;
17273 real_ldexp (&ONE16r, &dconst1, 16);
17274 x = const_double_from_real_value (ONE16r, SFmode);
17275 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
17276 NULL, 0, OPTAB_DIRECT);
17277 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
17278 NULL, 0, OPTAB_DIRECT);
17279 fp_hi = gen_reg_rtx (SFmode);
17280 fp_lo = gen_reg_rtx (SFmode);
17281 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
17282 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
17283 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
17285 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
17287 if (!rtx_equal_p (target, fp_hi))
17288 emit_move_insn (target, fp_hi);
17291 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17292 a vector of unsigned ints VAL to vector of floats TARGET. */
17295 ix86_expand_vector_convert_uns_vsivsf (rtx target, rtx val)
17298 REAL_VALUE_TYPE TWO16r;
17299 enum machine_mode intmode = GET_MODE (val);
17300 enum machine_mode fltmode = GET_MODE (target);
17301 rtx (*cvt) (rtx, rtx);
17303 if (intmode == V4SImode)
17304 cvt = gen_floatv4siv4sf2;
17306 cvt = gen_floatv8siv8sf2;
17307 tmp[0] = ix86_build_const_vector (intmode, 1, GEN_INT (0xffff));
17308 tmp[0] = force_reg (intmode, tmp[0]);
17309 tmp[1] = expand_simple_binop (intmode, AND, val, tmp[0], NULL_RTX, 1,
17311 tmp[2] = expand_simple_binop (intmode, LSHIFTRT, val, GEN_INT (16),
17312 NULL_RTX, 1, OPTAB_DIRECT);
17313 tmp[3] = gen_reg_rtx (fltmode);
17314 emit_insn (cvt (tmp[3], tmp[1]));
17315 tmp[4] = gen_reg_rtx (fltmode);
17316 emit_insn (cvt (tmp[4], tmp[2]));
17317 real_ldexp (&TWO16r, &dconst1, 16);
17318 tmp[5] = const_double_from_real_value (TWO16r, SFmode);
17319 tmp[5] = force_reg (fltmode, ix86_build_const_vector (fltmode, 1, tmp[5]));
17320 tmp[6] = expand_simple_binop (fltmode, MULT, tmp[4], tmp[5], NULL_RTX, 1,
17322 tmp[7] = expand_simple_binop (fltmode, PLUS, tmp[3], tmp[6], target, 1,
17324 if (tmp[7] != target)
17325 emit_move_insn (target, tmp[7]);
17328 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17329 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17330 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17331 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17334 ix86_expand_adjust_ufix_to_sfix_si (rtx val, rtx *xorp)
17336 REAL_VALUE_TYPE TWO31r;
17337 rtx two31r, tmp[4];
17338 enum machine_mode mode = GET_MODE (val);
17339 enum machine_mode scalarmode = GET_MODE_INNER (mode);
17340 enum machine_mode intmode = GET_MODE_SIZE (mode) == 32 ? V8SImode : V4SImode;
17341 rtx (*cmp) (rtx, rtx, rtx, rtx);
17344 for (i = 0; i < 3; i++)
17345 tmp[i] = gen_reg_rtx (mode);
17346 real_ldexp (&TWO31r, &dconst1, 31);
17347 two31r = const_double_from_real_value (TWO31r, scalarmode);
17348 two31r = ix86_build_const_vector (mode, 1, two31r);
17349 two31r = force_reg (mode, two31r);
17352 case V8SFmode: cmp = gen_avx_maskcmpv8sf3; break;
17353 case V4SFmode: cmp = gen_sse_maskcmpv4sf3; break;
17354 case V4DFmode: cmp = gen_avx_maskcmpv4df3; break;
17355 case V2DFmode: cmp = gen_sse2_maskcmpv2df3; break;
17356 default: gcc_unreachable ();
17358 tmp[3] = gen_rtx_LE (mode, two31r, val);
17359 emit_insn (cmp (tmp[0], two31r, val, tmp[3]));
17360 tmp[1] = expand_simple_binop (mode, AND, tmp[0], two31r, tmp[1],
17362 if (intmode == V4SImode || TARGET_AVX2)
17363 *xorp = expand_simple_binop (intmode, ASHIFT,
17364 gen_lowpart (intmode, tmp[0]),
17365 GEN_INT (31), NULL_RTX, 0,
17369 rtx two31 = GEN_INT ((unsigned HOST_WIDE_INT) 1 << 31);
17370 two31 = ix86_build_const_vector (intmode, 1, two31);
17371 *xorp = expand_simple_binop (intmode, AND,
17372 gen_lowpart (intmode, tmp[0]),
17373 two31, NULL_RTX, 0,
17376 return expand_simple_binop (mode, MINUS, val, tmp[1], tmp[2],
17380 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17381 then replicate the value for all elements of the vector
17385 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
17389 enum machine_mode scalar_mode;
17406 n_elt = GET_MODE_NUNITS (mode);
17407 v = rtvec_alloc (n_elt);
17408 scalar_mode = GET_MODE_INNER (mode);
17410 RTVEC_ELT (v, 0) = value;
17412 for (i = 1; i < n_elt; ++i)
17413 RTVEC_ELT (v, i) = vect ? value : CONST0_RTX (scalar_mode);
17415 return gen_rtx_CONST_VECTOR (mode, v);
17418 gcc_unreachable ();
17422 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
17423 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
17424 for an SSE register. If VECT is true, then replicate the mask for
17425 all elements of the vector register. If INVERT is true, then create
17426 a mask excluding the sign bit. */
17429 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
17431 enum machine_mode vec_mode, imode;
17432 HOST_WIDE_INT hi, lo;
17437 /* Find the sign bit, sign extended to 2*HWI. */
17445 mode = GET_MODE_INNER (mode);
17447 lo = 0x80000000, hi = lo < 0;
17455 mode = GET_MODE_INNER (mode);
17457 if (HOST_BITS_PER_WIDE_INT >= 64)
17458 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
17460 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
17465 vec_mode = VOIDmode;
17466 if (HOST_BITS_PER_WIDE_INT >= 64)
17469 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
17476 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
17480 lo = ~lo, hi = ~hi;
17486 mask = immed_double_const (lo, hi, imode);
17488 vec = gen_rtvec (2, v, mask);
17489 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
17490 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
17497 gcc_unreachable ();
17501 lo = ~lo, hi = ~hi;
17503 /* Force this value into the low part of a fp vector constant. */
17504 mask = immed_double_const (lo, hi, imode);
17505 mask = gen_lowpart (mode, mask);
17507 if (vec_mode == VOIDmode)
17508 return force_reg (mode, mask);
17510 v = ix86_build_const_vector (vec_mode, vect, mask);
17511 return force_reg (vec_mode, v);
17514 /* Generate code for floating point ABS or NEG. */
17517 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
17520 rtx mask, set, dst, src;
17521 bool use_sse = false;
17522 bool vector_mode = VECTOR_MODE_P (mode);
17523 enum machine_mode vmode = mode;
17527 else if (mode == TFmode)
17529 else if (TARGET_SSE_MATH)
17531 use_sse = SSE_FLOAT_MODE_P (mode);
17532 if (mode == SFmode)
17534 else if (mode == DFmode)
17538 /* NEG and ABS performed with SSE use bitwise mask operations.
17539 Create the appropriate mask now. */
17541 mask = ix86_build_signbit_mask (vmode, vector_mode, code == ABS);
17548 set = gen_rtx_fmt_e (code, mode, src);
17549 set = gen_rtx_SET (VOIDmode, dst, set);
17556 use = gen_rtx_USE (VOIDmode, mask);
17558 par = gen_rtvec (2, set, use);
17561 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
17562 par = gen_rtvec (3, set, use, clob);
17564 emit_insn (gen_rtx_PARALLEL (VOIDmode, par));
17570 /* Expand a copysign operation. Special case operand 0 being a constant. */
17573 ix86_expand_copysign (rtx operands[])
17575 enum machine_mode mode, vmode;
17576 rtx dest, op0, op1, mask, nmask;
17578 dest = operands[0];
17582 mode = GET_MODE (dest);
17584 if (mode == SFmode)
17586 else if (mode == DFmode)
17591 if (GET_CODE (op0) == CONST_DOUBLE)
17593 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
17595 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
17596 op0 = simplify_unary_operation (ABS, mode, op0, mode);
17598 if (mode == SFmode || mode == DFmode)
17600 if (op0 == CONST0_RTX (mode))
17601 op0 = CONST0_RTX (vmode);
17604 rtx v = ix86_build_const_vector (vmode, false, op0);
17606 op0 = force_reg (vmode, v);
17609 else if (op0 != CONST0_RTX (mode))
17610 op0 = force_reg (mode, op0);
17612 mask = ix86_build_signbit_mask (vmode, 0, 0);
17614 if (mode == SFmode)
17615 copysign_insn = gen_copysignsf3_const;
17616 else if (mode == DFmode)
17617 copysign_insn = gen_copysigndf3_const;
17619 copysign_insn = gen_copysigntf3_const;
17621 emit_insn (copysign_insn (dest, op0, op1, mask));
17625 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
17627 nmask = ix86_build_signbit_mask (vmode, 0, 1);
17628 mask = ix86_build_signbit_mask (vmode, 0, 0);
17630 if (mode == SFmode)
17631 copysign_insn = gen_copysignsf3_var;
17632 else if (mode == DFmode)
17633 copysign_insn = gen_copysigndf3_var;
17635 copysign_insn = gen_copysigntf3_var;
17637 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
17641 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
17642 be a constant, and so has already been expanded into a vector constant. */
17645 ix86_split_copysign_const (rtx operands[])
17647 enum machine_mode mode, vmode;
17648 rtx dest, op0, mask, x;
17650 dest = operands[0];
17652 mask = operands[3];
17654 mode = GET_MODE (dest);
17655 vmode = GET_MODE (mask);
17657 dest = simplify_gen_subreg (vmode, dest, mode, 0);
17658 x = gen_rtx_AND (vmode, dest, mask);
17659 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
17661 if (op0 != CONST0_RTX (vmode))
17663 x = gen_rtx_IOR (vmode, dest, op0);
17664 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
17668 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
17669 so we have to do two masks. */
17672 ix86_split_copysign_var (rtx operands[])
17674 enum machine_mode mode, vmode;
17675 rtx dest, scratch, op0, op1, mask, nmask, x;
17677 dest = operands[0];
17678 scratch = operands[1];
17681 nmask = operands[4];
17682 mask = operands[5];
17684 mode = GET_MODE (dest);
17685 vmode = GET_MODE (mask);
17687 if (rtx_equal_p (op0, op1))
17689 /* Shouldn't happen often (it's useless, obviously), but when it does
17690 we'd generate incorrect code if we continue below. */
17691 emit_move_insn (dest, op0);
17695 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
17697 gcc_assert (REGNO (op1) == REGNO (scratch));
17699 x = gen_rtx_AND (vmode, scratch, mask);
17700 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
17703 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
17704 x = gen_rtx_NOT (vmode, dest);
17705 x = gen_rtx_AND (vmode, x, op0);
17706 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
17710 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
17712 x = gen_rtx_AND (vmode, scratch, mask);
17714 else /* alternative 2,4 */
17716 gcc_assert (REGNO (mask) == REGNO (scratch));
17717 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
17718 x = gen_rtx_AND (vmode, scratch, op1);
17720 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
17722 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
17724 dest = simplify_gen_subreg (vmode, op0, mode, 0);
17725 x = gen_rtx_AND (vmode, dest, nmask);
17727 else /* alternative 3,4 */
17729 gcc_assert (REGNO (nmask) == REGNO (dest));
17731 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
17732 x = gen_rtx_AND (vmode, dest, op0);
17734 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
17737 x = gen_rtx_IOR (vmode, dest, scratch);
17738 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
17741 /* Return TRUE or FALSE depending on whether the first SET in INSN
17742 has source and destination with matching CC modes, and that the
17743 CC mode is at least as constrained as REQ_MODE. */
17746 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
17749 enum machine_mode set_mode;
17751 set = PATTERN (insn);
17752 if (GET_CODE (set) == PARALLEL)
17753 set = XVECEXP (set, 0, 0);
17754 gcc_assert (GET_CODE (set) == SET);
17755 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
17757 set_mode = GET_MODE (SET_DEST (set));
17761 if (req_mode != CCNOmode
17762 && (req_mode != CCmode
17763 || XEXP (SET_SRC (set), 1) != const0_rtx))
17767 if (req_mode == CCGCmode)
17771 if (req_mode == CCGOCmode || req_mode == CCNOmode)
17775 if (req_mode == CCZmode)
17785 if (set_mode != req_mode)
17790 gcc_unreachable ();
17793 return GET_MODE (SET_SRC (set)) == set_mode;
17796 /* Generate insn patterns to do an integer compare of OPERANDS. */
17799 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
17801 enum machine_mode cmpmode;
17804 cmpmode = SELECT_CC_MODE (code, op0, op1);
17805 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
17807 /* This is very simple, but making the interface the same as in the
17808 FP case makes the rest of the code easier. */
17809 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
17810 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
17812 /* Return the test that should be put into the flags user, i.e.
17813 the bcc, scc, or cmov instruction. */
17814 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
17817 /* Figure out whether to use ordered or unordered fp comparisons.
17818 Return the appropriate mode to use. */
17821 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
17823 /* ??? In order to make all comparisons reversible, we do all comparisons
17824 non-trapping when compiling for IEEE. Once gcc is able to distinguish
17825 all forms trapping and nontrapping comparisons, we can make inequality
17826 comparisons trapping again, since it results in better code when using
17827 FCOM based compares. */
17828 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
17832 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
17834 enum machine_mode mode = GET_MODE (op0);
17836 if (SCALAR_FLOAT_MODE_P (mode))
17838 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
17839 return ix86_fp_compare_mode (code);
17844 /* Only zero flag is needed. */
17845 case EQ: /* ZF=0 */
17846 case NE: /* ZF!=0 */
17848 /* Codes needing carry flag. */
17849 case GEU: /* CF=0 */
17850 case LTU: /* CF=1 */
17851 /* Detect overflow checks. They need just the carry flag. */
17852 if (GET_CODE (op0) == PLUS
17853 && rtx_equal_p (op1, XEXP (op0, 0)))
17857 case GTU: /* CF=0 & ZF=0 */
17858 case LEU: /* CF=1 | ZF=1 */
17859 /* Detect overflow checks. They need just the carry flag. */
17860 if (GET_CODE (op0) == MINUS
17861 && rtx_equal_p (op1, XEXP (op0, 0)))
17865 /* Codes possibly doable only with sign flag when
17866 comparing against zero. */
17867 case GE: /* SF=OF or SF=0 */
17868 case LT: /* SF<>OF or SF=1 */
17869 if (op1 == const0_rtx)
17872 /* For other cases Carry flag is not required. */
17874 /* Codes doable only with sign flag when comparing
17875 against zero, but we miss jump instruction for it
17876 so we need to use relational tests against overflow
17877 that thus needs to be zero. */
17878 case GT: /* ZF=0 & SF=OF */
17879 case LE: /* ZF=1 | SF<>OF */
17880 if (op1 == const0_rtx)
17884 /* strcmp pattern do (use flags) and combine may ask us for proper
17889 gcc_unreachable ();
17893 /* Return the fixed registers used for condition codes. */
17896 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
17903 /* If two condition code modes are compatible, return a condition code
17904 mode which is compatible with both. Otherwise, return
17907 static enum machine_mode
17908 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
17913 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
17916 if ((m1 == CCGCmode && m2 == CCGOCmode)
17917 || (m1 == CCGOCmode && m2 == CCGCmode))
17923 gcc_unreachable ();
17953 /* These are only compatible with themselves, which we already
17960 /* Return a comparison we can do and that it is equivalent to
17961 swap_condition (code) apart possibly from orderedness.
17962 But, never change orderedness if TARGET_IEEE_FP, returning
17963 UNKNOWN in that case if necessary. */
17965 static enum rtx_code
17966 ix86_fp_swap_condition (enum rtx_code code)
17970 case GT: /* GTU - CF=0 & ZF=0 */
17971 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
17972 case GE: /* GEU - CF=0 */
17973 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
17974 case UNLT: /* LTU - CF=1 */
17975 return TARGET_IEEE_FP ? UNKNOWN : GT;
17976 case UNLE: /* LEU - CF=1 | ZF=1 */
17977 return TARGET_IEEE_FP ? UNKNOWN : GE;
17979 return swap_condition (code);
17983 /* Return cost of comparison CODE using the best strategy for performance.
17984 All following functions do use number of instructions as a cost metrics.
17985 In future this should be tweaked to compute bytes for optimize_size and
17986 take into account performance of various instructions on various CPUs. */
17989 ix86_fp_comparison_cost (enum rtx_code code)
17993 /* The cost of code using bit-twiddling on %ah. */
18010 arith_cost = TARGET_IEEE_FP ? 5 : 4;
18014 arith_cost = TARGET_IEEE_FP ? 6 : 4;
18017 gcc_unreachable ();
18020 switch (ix86_fp_comparison_strategy (code))
18022 case IX86_FPCMP_COMI:
18023 return arith_cost > 4 ? 3 : 2;
18024 case IX86_FPCMP_SAHF:
18025 return arith_cost > 4 ? 4 : 3;
18031 /* Return strategy to use for floating-point. We assume that fcomi is always
18032 preferrable where available, since that is also true when looking at size
18033 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18035 enum ix86_fpcmp_strategy
18036 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
18038 /* Do fcomi/sahf based test when profitable. */
18041 return IX86_FPCMP_COMI;
18043 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
18044 return IX86_FPCMP_SAHF;
18046 return IX86_FPCMP_ARITH;
18049 /* Swap, force into registers, or otherwise massage the two operands
18050 to a fp comparison. The operands are updated in place; the new
18051 comparison code is returned. */
18053 static enum rtx_code
18054 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
18056 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
18057 rtx op0 = *pop0, op1 = *pop1;
18058 enum machine_mode op_mode = GET_MODE (op0);
18059 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
18061 /* All of the unordered compare instructions only work on registers.
18062 The same is true of the fcomi compare instructions. The XFmode
18063 compare instructions require registers except when comparing
18064 against zero or when converting operand 1 from fixed point to
18068 && (fpcmp_mode == CCFPUmode
18069 || (op_mode == XFmode
18070 && ! (standard_80387_constant_p (op0) == 1
18071 || standard_80387_constant_p (op1) == 1)
18072 && GET_CODE (op1) != FLOAT)
18073 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
18075 op0 = force_reg (op_mode, op0);
18076 op1 = force_reg (op_mode, op1);
18080 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18081 things around if they appear profitable, otherwise force op0
18082 into a register. */
18084 if (standard_80387_constant_p (op0) == 0
18086 && ! (standard_80387_constant_p (op1) == 0
18089 enum rtx_code new_code = ix86_fp_swap_condition (code);
18090 if (new_code != UNKNOWN)
18093 tmp = op0, op0 = op1, op1 = tmp;
18099 op0 = force_reg (op_mode, op0);
18101 if (CONSTANT_P (op1))
18103 int tmp = standard_80387_constant_p (op1);
18105 op1 = validize_mem (force_const_mem (op_mode, op1));
18109 op1 = force_reg (op_mode, op1);
18112 op1 = force_reg (op_mode, op1);
18116 /* Try to rearrange the comparison to make it cheaper. */
18117 if (ix86_fp_comparison_cost (code)
18118 > ix86_fp_comparison_cost (swap_condition (code))
18119 && (REG_P (op1) || can_create_pseudo_p ()))
18122 tmp = op0, op0 = op1, op1 = tmp;
18123 code = swap_condition (code);
18125 op0 = force_reg (op_mode, op0);
18133 /* Convert comparison codes we use to represent FP comparison to integer
18134 code that will result in proper branch. Return UNKNOWN if no such code
18138 ix86_fp_compare_code_to_integer (enum rtx_code code)
18167 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18170 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
18172 enum machine_mode fpcmp_mode, intcmp_mode;
18175 fpcmp_mode = ix86_fp_compare_mode (code);
18176 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
18178 /* Do fcomi/sahf based test when profitable. */
18179 switch (ix86_fp_comparison_strategy (code))
18181 case IX86_FPCMP_COMI:
18182 intcmp_mode = fpcmp_mode;
18183 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
18184 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
18189 case IX86_FPCMP_SAHF:
18190 intcmp_mode = fpcmp_mode;
18191 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
18192 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
18196 scratch = gen_reg_rtx (HImode);
18197 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
18198 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
18201 case IX86_FPCMP_ARITH:
18202 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18203 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
18204 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
18206 scratch = gen_reg_rtx (HImode);
18207 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
18209 /* In the unordered case, we have to check C2 for NaN's, which
18210 doesn't happen to work out to anything nice combination-wise.
18211 So do some bit twiddling on the value we've got in AH to come
18212 up with an appropriate set of condition codes. */
18214 intcmp_mode = CCNOmode;
18219 if (code == GT || !TARGET_IEEE_FP)
18221 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
18226 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18227 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
18228 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
18229 intcmp_mode = CCmode;
18235 if (code == LT && TARGET_IEEE_FP)
18237 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18238 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
18239 intcmp_mode = CCmode;
18244 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
18250 if (code == GE || !TARGET_IEEE_FP)
18252 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
18257 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18258 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
18264 if (code == LE && TARGET_IEEE_FP)
18266 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18267 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
18268 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
18269 intcmp_mode = CCmode;
18274 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
18280 if (code == EQ && TARGET_IEEE_FP)
18282 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18283 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
18284 intcmp_mode = CCmode;
18289 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
18295 if (code == NE && TARGET_IEEE_FP)
18297 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
18298 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
18304 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
18310 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
18314 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
18319 gcc_unreachable ();
18327 /* Return the test that should be put into the flags user, i.e.
18328 the bcc, scc, or cmov instruction. */
18329 return gen_rtx_fmt_ee (code, VOIDmode,
18330 gen_rtx_REG (intcmp_mode, FLAGS_REG),
18335 ix86_expand_compare (enum rtx_code code, rtx op0, rtx op1)
18339 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
18340 ret = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
18342 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
18344 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
18345 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
18348 ret = ix86_expand_int_compare (code, op0, op1);
18354 ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
18356 enum machine_mode mode = GET_MODE (op0);
18368 tmp = ix86_expand_compare (code, op0, op1);
18369 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18370 gen_rtx_LABEL_REF (VOIDmode, label),
18372 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18379 /* Expand DImode branch into multiple compare+branch. */
18381 rtx lo[2], hi[2], label2;
18382 enum rtx_code code1, code2, code3;
18383 enum machine_mode submode;
18385 if (CONSTANT_P (op0) && !CONSTANT_P (op1))
18387 tmp = op0, op0 = op1, op1 = tmp;
18388 code = swap_condition (code);
18391 split_double_mode (mode, &op0, 1, lo+0, hi+0);
18392 split_double_mode (mode, &op1, 1, lo+1, hi+1);
18394 submode = mode == DImode ? SImode : DImode;
18396 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18397 avoid two branches. This costs one extra insn, so disable when
18398 optimizing for size. */
18400 if ((code == EQ || code == NE)
18401 && (!optimize_insn_for_size_p ()
18402 || hi[1] == const0_rtx || lo[1] == const0_rtx))
18407 if (hi[1] != const0_rtx)
18408 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
18409 NULL_RTX, 0, OPTAB_WIDEN);
18412 if (lo[1] != const0_rtx)
18413 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
18414 NULL_RTX, 0, OPTAB_WIDEN);
18416 tmp = expand_binop (submode, ior_optab, xor1, xor0,
18417 NULL_RTX, 0, OPTAB_WIDEN);
18419 ix86_expand_branch (code, tmp, const0_rtx, label);
18423 /* Otherwise, if we are doing less-than or greater-or-equal-than,
18424 op1 is a constant and the low word is zero, then we can just
18425 examine the high word. Similarly for low word -1 and
18426 less-or-equal-than or greater-than. */
18428 if (CONST_INT_P (hi[1]))
18431 case LT: case LTU: case GE: case GEU:
18432 if (lo[1] == const0_rtx)
18434 ix86_expand_branch (code, hi[0], hi[1], label);
18438 case LE: case LEU: case GT: case GTU:
18439 if (lo[1] == constm1_rtx)
18441 ix86_expand_branch (code, hi[0], hi[1], label);
18449 /* Otherwise, we need two or three jumps. */
18451 label2 = gen_label_rtx ();
18454 code2 = swap_condition (code);
18455 code3 = unsigned_condition (code);
18459 case LT: case GT: case LTU: case GTU:
18462 case LE: code1 = LT; code2 = GT; break;
18463 case GE: code1 = GT; code2 = LT; break;
18464 case LEU: code1 = LTU; code2 = GTU; break;
18465 case GEU: code1 = GTU; code2 = LTU; break;
18467 case EQ: code1 = UNKNOWN; code2 = NE; break;
18468 case NE: code2 = UNKNOWN; break;
18471 gcc_unreachable ();
18476 * if (hi(a) < hi(b)) goto true;
18477 * if (hi(a) > hi(b)) goto false;
18478 * if (lo(a) < lo(b)) goto true;
18482 if (code1 != UNKNOWN)
18483 ix86_expand_branch (code1, hi[0], hi[1], label);
18484 if (code2 != UNKNOWN)
18485 ix86_expand_branch (code2, hi[0], hi[1], label2);
18487 ix86_expand_branch (code3, lo[0], lo[1], label);
18489 if (code2 != UNKNOWN)
18490 emit_label (label2);
18495 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC);
18500 /* Split branch based on floating point condition. */
18502 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
18503 rtx target1, rtx target2, rtx tmp, rtx pushed)
18508 if (target2 != pc_rtx)
18511 code = reverse_condition_maybe_unordered (code);
18516 condition = ix86_expand_fp_compare (code, op1, op2,
18519 /* Remove pushed operand from stack. */
18521 ix86_free_from_memory (GET_MODE (pushed));
18523 i = emit_jump_insn (gen_rtx_SET
18525 gen_rtx_IF_THEN_ELSE (VOIDmode,
18526 condition, target1, target2)));
18527 if (split_branch_probability >= 0)
18528 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
18532 ix86_expand_setcc (rtx dest, enum rtx_code code, rtx op0, rtx op1)
18536 gcc_assert (GET_MODE (dest) == QImode);
18538 ret = ix86_expand_compare (code, op0, op1);
18539 PUT_MODE (ret, QImode);
18540 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
18543 /* Expand comparison setting or clearing carry flag. Return true when
18544 successful and set pop for the operation. */
18546 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
18548 enum machine_mode mode =
18549 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
18551 /* Do not handle double-mode compares that go through special path. */
18552 if (mode == (TARGET_64BIT ? TImode : DImode))
18555 if (SCALAR_FLOAT_MODE_P (mode))
18557 rtx compare_op, compare_seq;
18559 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
18561 /* Shortcut: following common codes never translate
18562 into carry flag compares. */
18563 if (code == EQ || code == NE || code == UNEQ || code == LTGT
18564 || code == ORDERED || code == UNORDERED)
18567 /* These comparisons require zero flag; swap operands so they won't. */
18568 if ((code == GT || code == UNLE || code == LE || code == UNGT)
18569 && !TARGET_IEEE_FP)
18574 code = swap_condition (code);
18577 /* Try to expand the comparison and verify that we end up with
18578 carry flag based comparison. This fails to be true only when
18579 we decide to expand comparison using arithmetic that is not
18580 too common scenario. */
18582 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
18583 compare_seq = get_insns ();
18586 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
18587 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
18588 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
18590 code = GET_CODE (compare_op);
18592 if (code != LTU && code != GEU)
18595 emit_insn (compare_seq);
18600 if (!INTEGRAL_MODE_P (mode))
18609 /* Convert a==0 into (unsigned)a<1. */
18612 if (op1 != const0_rtx)
18615 code = (code == EQ ? LTU : GEU);
18618 /* Convert a>b into b<a or a>=b-1. */
18621 if (CONST_INT_P (op1))
18623 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
18624 /* Bail out on overflow. We still can swap operands but that
18625 would force loading of the constant into register. */
18626 if (op1 == const0_rtx
18627 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
18629 code = (code == GTU ? GEU : LTU);
18636 code = (code == GTU ? LTU : GEU);
18640 /* Convert a>=0 into (unsigned)a<0x80000000. */
18643 if (mode == DImode || op1 != const0_rtx)
18645 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
18646 code = (code == LT ? GEU : LTU);
18650 if (mode == DImode || op1 != constm1_rtx)
18652 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
18653 code = (code == LE ? GEU : LTU);
18659 /* Swapping operands may cause constant to appear as first operand. */
18660 if (!nonimmediate_operand (op0, VOIDmode))
18662 if (!can_create_pseudo_p ())
18664 op0 = force_reg (mode, op0);
18666 *pop = ix86_expand_compare (code, op0, op1);
18667 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
18672 ix86_expand_int_movcc (rtx operands[])
18674 enum rtx_code code = GET_CODE (operands[1]), compare_code;
18675 rtx compare_seq, compare_op;
18676 enum machine_mode mode = GET_MODE (operands[0]);
18677 bool sign_bit_compare_p = false;
18678 rtx op0 = XEXP (operands[1], 0);
18679 rtx op1 = XEXP (operands[1], 1);
18682 compare_op = ix86_expand_compare (code, op0, op1);
18683 compare_seq = get_insns ();
18686 compare_code = GET_CODE (compare_op);
18688 if ((op1 == const0_rtx && (code == GE || code == LT))
18689 || (op1 == constm1_rtx && (code == GT || code == LE)))
18690 sign_bit_compare_p = true;
18692 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
18693 HImode insns, we'd be swallowed in word prefix ops. */
18695 if ((mode != HImode || TARGET_FAST_PREFIX)
18696 && (mode != (TARGET_64BIT ? TImode : DImode))
18697 && CONST_INT_P (operands[2])
18698 && CONST_INT_P (operands[3]))
18700 rtx out = operands[0];
18701 HOST_WIDE_INT ct = INTVAL (operands[2]);
18702 HOST_WIDE_INT cf = INTVAL (operands[3]);
18703 HOST_WIDE_INT diff;
18706 /* Sign bit compares are better done using shifts than we do by using
18708 if (sign_bit_compare_p
18709 || ix86_expand_carry_flag_compare (code, op0, op1, &compare_op))
18711 /* Detect overlap between destination and compare sources. */
18714 if (!sign_bit_compare_p)
18717 bool fpcmp = false;
18719 compare_code = GET_CODE (compare_op);
18721 flags = XEXP (compare_op, 0);
18723 if (GET_MODE (flags) == CCFPmode
18724 || GET_MODE (flags) == CCFPUmode)
18728 = ix86_fp_compare_code_to_integer (compare_code);
18731 /* To simplify rest of code, restrict to the GEU case. */
18732 if (compare_code == LTU)
18734 HOST_WIDE_INT tmp = ct;
18737 compare_code = reverse_condition (compare_code);
18738 code = reverse_condition (code);
18743 PUT_CODE (compare_op,
18744 reverse_condition_maybe_unordered
18745 (GET_CODE (compare_op)));
18747 PUT_CODE (compare_op,
18748 reverse_condition (GET_CODE (compare_op)));
18752 if (reg_overlap_mentioned_p (out, op0)
18753 || reg_overlap_mentioned_p (out, op1))
18754 tmp = gen_reg_rtx (mode);
18756 if (mode == DImode)
18757 emit_insn (gen_x86_movdicc_0_m1 (tmp, flags, compare_op));
18759 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
18760 flags, compare_op));
18764 if (code == GT || code == GE)
18765 code = reverse_condition (code);
18768 HOST_WIDE_INT tmp = ct;
18773 tmp = emit_store_flag (tmp, code, op0, op1, VOIDmode, 0, -1);
18786 tmp = expand_simple_binop (mode, PLUS,
18788 copy_rtx (tmp), 1, OPTAB_DIRECT);
18799 tmp = expand_simple_binop (mode, IOR,
18801 copy_rtx (tmp), 1, OPTAB_DIRECT);
18803 else if (diff == -1 && ct)
18813 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
18815 tmp = expand_simple_binop (mode, PLUS,
18816 copy_rtx (tmp), GEN_INT (cf),
18817 copy_rtx (tmp), 1, OPTAB_DIRECT);
18825 * andl cf - ct, dest
18835 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
18838 tmp = expand_simple_binop (mode, AND,
18840 gen_int_mode (cf - ct, mode),
18841 copy_rtx (tmp), 1, OPTAB_DIRECT);
18843 tmp = expand_simple_binop (mode, PLUS,
18844 copy_rtx (tmp), GEN_INT (ct),
18845 copy_rtx (tmp), 1, OPTAB_DIRECT);
18848 if (!rtx_equal_p (tmp, out))
18849 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
18856 enum machine_mode cmp_mode = GET_MODE (op0);
18859 tmp = ct, ct = cf, cf = tmp;
18862 if (SCALAR_FLOAT_MODE_P (cmp_mode))
18864 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
18866 /* We may be reversing unordered compare to normal compare, that
18867 is not valid in general (we may convert non-trapping condition
18868 to trapping one), however on i386 we currently emit all
18869 comparisons unordered. */
18870 compare_code = reverse_condition_maybe_unordered (compare_code);
18871 code = reverse_condition_maybe_unordered (code);
18875 compare_code = reverse_condition (compare_code);
18876 code = reverse_condition (code);
18880 compare_code = UNKNOWN;
18881 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
18882 && CONST_INT_P (op1))
18884 if (op1 == const0_rtx
18885 && (code == LT || code == GE))
18886 compare_code = code;
18887 else if (op1 == constm1_rtx)
18891 else if (code == GT)
18896 /* Optimize dest = (op0 < 0) ? -1 : cf. */
18897 if (compare_code != UNKNOWN
18898 && GET_MODE (op0) == GET_MODE (out)
18899 && (cf == -1 || ct == -1))
18901 /* If lea code below could be used, only optimize
18902 if it results in a 2 insn sequence. */
18904 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
18905 || diff == 3 || diff == 5 || diff == 9)
18906 || (compare_code == LT && ct == -1)
18907 || (compare_code == GE && cf == -1))
18910 * notl op1 (if necessary)
18918 code = reverse_condition (code);
18921 out = emit_store_flag (out, code, op0, op1, VOIDmode, 0, -1);
18923 out = expand_simple_binop (mode, IOR,
18925 out, 1, OPTAB_DIRECT);
18926 if (out != operands[0])
18927 emit_move_insn (operands[0], out);
18934 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
18935 || diff == 3 || diff == 5 || diff == 9)
18936 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
18938 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
18944 * lea cf(dest*(ct-cf)),dest
18948 * This also catches the degenerate setcc-only case.
18954 out = emit_store_flag (out, code, op0, op1, VOIDmode, 0, 1);
18957 /* On x86_64 the lea instruction operates on Pmode, so we need
18958 to get arithmetics done in proper mode to match. */
18960 tmp = copy_rtx (out);
18964 out1 = copy_rtx (out);
18965 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
18969 tmp = gen_rtx_PLUS (mode, tmp, out1);
18975 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
18978 if (!rtx_equal_p (tmp, out))
18981 out = force_operand (tmp, copy_rtx (out));
18983 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
18985 if (!rtx_equal_p (out, operands[0]))
18986 emit_move_insn (operands[0], copy_rtx (out));
18992 * General case: Jumpful:
18993 * xorl dest,dest cmpl op1, op2
18994 * cmpl op1, op2 movl ct, dest
18995 * setcc dest jcc 1f
18996 * decl dest movl cf, dest
18997 * andl (cf-ct),dest 1:
19000 * Size 20. Size 14.
19002 * This is reasonably steep, but branch mispredict costs are
19003 * high on modern cpus, so consider failing only if optimizing
19007 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
19008 && BRANCH_COST (optimize_insn_for_speed_p (),
19013 enum machine_mode cmp_mode = GET_MODE (op0);
19018 if (SCALAR_FLOAT_MODE_P (cmp_mode))
19020 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
19022 /* We may be reversing unordered compare to normal compare,
19023 that is not valid in general (we may convert non-trapping
19024 condition to trapping one), however on i386 we currently
19025 emit all comparisons unordered. */
19026 code = reverse_condition_maybe_unordered (code);
19030 code = reverse_condition (code);
19031 if (compare_code != UNKNOWN)
19032 compare_code = reverse_condition (compare_code);
19036 if (compare_code != UNKNOWN)
19038 /* notl op1 (if needed)
19043 For x < 0 (resp. x <= -1) there will be no notl,
19044 so if possible swap the constants to get rid of the
19046 True/false will be -1/0 while code below (store flag
19047 followed by decrement) is 0/-1, so the constants need
19048 to be exchanged once more. */
19050 if (compare_code == GE || !cf)
19052 code = reverse_condition (code);
19057 HOST_WIDE_INT tmp = cf;
19062 out = emit_store_flag (out, code, op0, op1, VOIDmode, 0, -1);
19066 out = emit_store_flag (out, code, op0, op1, VOIDmode, 0, 1);
19068 out = expand_simple_binop (mode, PLUS, copy_rtx (out),
19070 copy_rtx (out), 1, OPTAB_DIRECT);
19073 out = expand_simple_binop (mode, AND, copy_rtx (out),
19074 gen_int_mode (cf - ct, mode),
19075 copy_rtx (out), 1, OPTAB_DIRECT);
19077 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
19078 copy_rtx (out), 1, OPTAB_DIRECT);
19079 if (!rtx_equal_p (out, operands[0]))
19080 emit_move_insn (operands[0], copy_rtx (out));
19086 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
19088 /* Try a few things more with specific constants and a variable. */
19091 rtx var, orig_out, out, tmp;
19093 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
19096 /* If one of the two operands is an interesting constant, load a
19097 constant with the above and mask it in with a logical operation. */
19099 if (CONST_INT_P (operands[2]))
19102 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
19103 operands[3] = constm1_rtx, op = and_optab;
19104 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
19105 operands[3] = const0_rtx, op = ior_optab;
19109 else if (CONST_INT_P (operands[3]))
19112 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
19113 operands[2] = constm1_rtx, op = and_optab;
19114 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
19115 operands[2] = const0_rtx, op = ior_optab;
19122 orig_out = operands[0];
19123 tmp = gen_reg_rtx (mode);
19126 /* Recurse to get the constant loaded. */
19127 if (ix86_expand_int_movcc (operands) == 0)
19130 /* Mask in the interesting variable. */
19131 out = expand_binop (mode, op, var, tmp, orig_out, 0,
19133 if (!rtx_equal_p (out, orig_out))
19134 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
19140 * For comparison with above,
19150 if (! nonimmediate_operand (operands[2], mode))
19151 operands[2] = force_reg (mode, operands[2]);
19152 if (! nonimmediate_operand (operands[3], mode))
19153 operands[3] = force_reg (mode, operands[3]);
19155 if (! register_operand (operands[2], VOIDmode)
19157 || ! register_operand (operands[3], VOIDmode)))
19158 operands[2] = force_reg (mode, operands[2]);
19161 && ! register_operand (operands[3], VOIDmode))
19162 operands[3] = force_reg (mode, operands[3]);
19164 emit_insn (compare_seq);
19165 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
19166 gen_rtx_IF_THEN_ELSE (mode,
19167 compare_op, operands[2],
19172 /* Swap, force into registers, or otherwise massage the two operands
19173 to an sse comparison with a mask result. Thus we differ a bit from
19174 ix86_prepare_fp_compare_args which expects to produce a flags result.
19176 The DEST operand exists to help determine whether to commute commutative
19177 operators. The POP0/POP1 operands are updated in place. The new
19178 comparison code is returned, or UNKNOWN if not implementable. */
19180 static enum rtx_code
19181 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
19182 rtx *pop0, rtx *pop1)
19190 /* AVX supports all the needed comparisons. */
19193 /* We have no LTGT as an operator. We could implement it with
19194 NE & ORDERED, but this requires an extra temporary. It's
19195 not clear that it's worth it. */
19202 /* These are supported directly. */
19209 /* AVX has 3 operand comparisons, no need to swap anything. */
19212 /* For commutative operators, try to canonicalize the destination
19213 operand to be first in the comparison - this helps reload to
19214 avoid extra moves. */
19215 if (!dest || !rtx_equal_p (dest, *pop1))
19223 /* These are not supported directly before AVX, and furthermore
19224 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19225 comparison operands to transform into something that is
19230 code = swap_condition (code);
19234 gcc_unreachable ();
19240 /* Detect conditional moves that exactly match min/max operational
19241 semantics. Note that this is IEEE safe, as long as we don't
19242 interchange the operands.
19244 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19245 and TRUE if the operation is successful and instructions are emitted. */
19248 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
19249 rtx cmp_op1, rtx if_true, rtx if_false)
19251 enum machine_mode mode;
19257 else if (code == UNGE)
19260 if_true = if_false;
19266 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
19268 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
19273 mode = GET_MODE (dest);
19275 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19276 but MODE may be a vector mode and thus not appropriate. */
19277 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
19279 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
19282 if_true = force_reg (mode, if_true);
19283 v = gen_rtvec (2, if_true, if_false);
19284 tmp = gen_rtx_UNSPEC (mode, v, u);
19288 code = is_min ? SMIN : SMAX;
19289 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
19292 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
19296 /* Expand an sse vector comparison. Return the register with the result. */
19299 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
19300 rtx op_true, rtx op_false)
19302 enum machine_mode mode = GET_MODE (dest);
19303 enum machine_mode cmp_mode = GET_MODE (cmp_op0);
19306 cmp_op0 = force_reg (cmp_mode, cmp_op0);
19307 if (!nonimmediate_operand (cmp_op1, cmp_mode))
19308 cmp_op1 = force_reg (cmp_mode, cmp_op1);
19311 || reg_overlap_mentioned_p (dest, op_true)
19312 || reg_overlap_mentioned_p (dest, op_false))
19313 dest = gen_reg_rtx (mode);
19315 x = gen_rtx_fmt_ee (code, cmp_mode, cmp_op0, cmp_op1);
19316 if (cmp_mode != mode)
19318 x = force_reg (cmp_mode, x);
19319 convert_move (dest, x, false);
19322 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
19327 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19328 operations. This is used for both scalar and vector conditional moves. */
19331 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
19333 enum machine_mode mode = GET_MODE (dest);
19336 if (vector_all_ones_operand (op_true, mode)
19337 && rtx_equal_p (op_false, CONST0_RTX (mode)))
19339 emit_insn (gen_rtx_SET (VOIDmode, dest, cmp));
19341 else if (op_false == CONST0_RTX (mode))
19343 op_true = force_reg (mode, op_true);
19344 x = gen_rtx_AND (mode, cmp, op_true);
19345 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
19347 else if (op_true == CONST0_RTX (mode))
19349 op_false = force_reg (mode, op_false);
19350 x = gen_rtx_NOT (mode, cmp);
19351 x = gen_rtx_AND (mode, x, op_false);
19352 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
19354 else if (INTEGRAL_MODE_P (mode) && op_true == CONSTM1_RTX (mode))
19356 op_false = force_reg (mode, op_false);
19357 x = gen_rtx_IOR (mode, cmp, op_false);
19358 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
19360 else if (TARGET_XOP)
19362 op_true = force_reg (mode, op_true);
19364 if (!nonimmediate_operand (op_false, mode))
19365 op_false = force_reg (mode, op_false);
19367 emit_insn (gen_rtx_SET (mode, dest,
19368 gen_rtx_IF_THEN_ELSE (mode, cmp,
19374 rtx (*gen) (rtx, rtx, rtx, rtx) = NULL;
19376 if (!nonimmediate_operand (op_true, mode))
19377 op_true = force_reg (mode, op_true);
19379 op_false = force_reg (mode, op_false);
19385 gen = gen_sse4_1_blendvps;
19389 gen = gen_sse4_1_blendvpd;
19397 gen = gen_sse4_1_pblendvb;
19398 dest = gen_lowpart (V16QImode, dest);
19399 op_false = gen_lowpart (V16QImode, op_false);
19400 op_true = gen_lowpart (V16QImode, op_true);
19401 cmp = gen_lowpart (V16QImode, cmp);
19406 gen = gen_avx_blendvps256;
19410 gen = gen_avx_blendvpd256;
19418 gen = gen_avx2_pblendvb;
19419 dest = gen_lowpart (V32QImode, dest);
19420 op_false = gen_lowpart (V32QImode, op_false);
19421 op_true = gen_lowpart (V32QImode, op_true);
19422 cmp = gen_lowpart (V32QImode, cmp);
19430 emit_insn (gen (dest, op_false, op_true, cmp));
19433 op_true = force_reg (mode, op_true);
19435 t2 = gen_reg_rtx (mode);
19437 t3 = gen_reg_rtx (mode);
19441 x = gen_rtx_AND (mode, op_true, cmp);
19442 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
19444 x = gen_rtx_NOT (mode, cmp);
19445 x = gen_rtx_AND (mode, x, op_false);
19446 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
19448 x = gen_rtx_IOR (mode, t3, t2);
19449 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
19454 /* Expand a floating-point conditional move. Return true if successful. */
19457 ix86_expand_fp_movcc (rtx operands[])
19459 enum machine_mode mode = GET_MODE (operands[0]);
19460 enum rtx_code code = GET_CODE (operands[1]);
19461 rtx tmp, compare_op;
19462 rtx op0 = XEXP (operands[1], 0);
19463 rtx op1 = XEXP (operands[1], 1);
19465 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
19467 enum machine_mode cmode;
19469 /* Since we've no cmove for sse registers, don't force bad register
19470 allocation just to gain access to it. Deny movcc when the
19471 comparison mode doesn't match the move mode. */
19472 cmode = GET_MODE (op0);
19473 if (cmode == VOIDmode)
19474 cmode = GET_MODE (op1);
19478 code = ix86_prepare_sse_fp_compare_args (operands[0], code, &op0, &op1);
19479 if (code == UNKNOWN)
19482 if (ix86_expand_sse_fp_minmax (operands[0], code, op0, op1,
19483 operands[2], operands[3]))
19486 tmp = ix86_expand_sse_cmp (operands[0], code, op0, op1,
19487 operands[2], operands[3]);
19488 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
19492 /* The floating point conditional move instructions don't directly
19493 support conditions resulting from a signed integer comparison. */
19495 compare_op = ix86_expand_compare (code, op0, op1);
19496 if (!fcmov_comparison_operator (compare_op, VOIDmode))
19498 tmp = gen_reg_rtx (QImode);
19499 ix86_expand_setcc (tmp, code, op0, op1);
19501 compare_op = ix86_expand_compare (NE, tmp, const0_rtx);
19504 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
19505 gen_rtx_IF_THEN_ELSE (mode, compare_op,
19506 operands[2], operands[3])));
19511 /* Expand a floating-point vector conditional move; a vcond operation
19512 rather than a movcc operation. */
19515 ix86_expand_fp_vcond (rtx operands[])
19517 enum rtx_code code = GET_CODE (operands[3]);
19520 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
19521 &operands[4], &operands[5]);
19522 if (code == UNKNOWN)
19525 switch (GET_CODE (operands[3]))
19528 temp = ix86_expand_sse_cmp (operands[0], ORDERED, operands[4],
19529 operands[5], operands[0], operands[0]);
19530 cmp = ix86_expand_sse_cmp (operands[0], NE, operands[4],
19531 operands[5], operands[1], operands[2]);
19535 temp = ix86_expand_sse_cmp (operands[0], UNORDERED, operands[4],
19536 operands[5], operands[0], operands[0]);
19537 cmp = ix86_expand_sse_cmp (operands[0], EQ, operands[4],
19538 operands[5], operands[1], operands[2]);
19542 gcc_unreachable ();
19544 cmp = expand_simple_binop (GET_MODE (cmp), code, temp, cmp, cmp, 1,
19546 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
19550 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
19551 operands[5], operands[1], operands[2]))
19554 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
19555 operands[1], operands[2]);
19556 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
19560 /* Expand a signed/unsigned integral vector conditional move. */
19563 ix86_expand_int_vcond (rtx operands[])
19565 enum machine_mode data_mode = GET_MODE (operands[0]);
19566 enum machine_mode mode = GET_MODE (operands[4]);
19567 enum rtx_code code = GET_CODE (operands[3]);
19568 bool negate = false;
19571 cop0 = operands[4];
19572 cop1 = operands[5];
19574 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
19575 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
19576 if ((code == LT || code == GE)
19577 && data_mode == mode
19578 && cop1 == CONST0_RTX (mode)
19579 && operands[1 + (code == LT)] == CONST0_RTX (data_mode)
19580 && GET_MODE_SIZE (GET_MODE_INNER (data_mode)) > 1
19581 && GET_MODE_SIZE (GET_MODE_INNER (data_mode)) <= 8
19582 && (GET_MODE_SIZE (data_mode) == 16
19583 || (TARGET_AVX2 && GET_MODE_SIZE (data_mode) == 32)))
19585 rtx negop = operands[2 - (code == LT)];
19586 int shift = GET_MODE_BITSIZE (GET_MODE_INNER (data_mode)) - 1;
19587 if (negop == CONST1_RTX (data_mode))
19589 rtx res = expand_simple_binop (mode, LSHIFTRT, cop0, GEN_INT (shift),
19590 operands[0], 1, OPTAB_DIRECT);
19591 if (res != operands[0])
19592 emit_move_insn (operands[0], res);
19595 else if (GET_MODE_INNER (data_mode) != DImode
19596 && vector_all_ones_operand (negop, data_mode))
19598 rtx res = expand_simple_binop (mode, ASHIFTRT, cop0, GEN_INT (shift),
19599 operands[0], 0, OPTAB_DIRECT);
19600 if (res != operands[0])
19601 emit_move_insn (operands[0], res);
19606 if (!nonimmediate_operand (cop1, mode))
19607 cop1 = force_reg (mode, cop1);
19608 if (!general_operand (operands[1], data_mode))
19609 operands[1] = force_reg (data_mode, operands[1]);
19610 if (!general_operand (operands[2], data_mode))
19611 operands[2] = force_reg (data_mode, operands[2]);
19613 /* XOP supports all of the comparisons on all 128-bit vector int types. */
19615 && (mode == V16QImode || mode == V8HImode
19616 || mode == V4SImode || mode == V2DImode))
19620 /* Canonicalize the comparison to EQ, GT, GTU. */
19631 code = reverse_condition (code);
19637 code = reverse_condition (code);
19643 code = swap_condition (code);
19644 x = cop0, cop0 = cop1, cop1 = x;
19648 gcc_unreachable ();
19651 /* Only SSE4.1/SSE4.2 supports V2DImode. */
19652 if (mode == V2DImode)
19657 /* SSE4.1 supports EQ. */
19658 if (!TARGET_SSE4_1)
19664 /* SSE4.2 supports GT/GTU. */
19665 if (!TARGET_SSE4_2)
19670 gcc_unreachable ();
19674 /* Unsigned parallel compare is not supported by the hardware.
19675 Play some tricks to turn this into a signed comparison
19679 cop0 = force_reg (mode, cop0);
19689 rtx (*gen_sub3) (rtx, rtx, rtx);
19693 case V8SImode: gen_sub3 = gen_subv8si3; break;
19694 case V4DImode: gen_sub3 = gen_subv4di3; break;
19695 case V4SImode: gen_sub3 = gen_subv4si3; break;
19696 case V2DImode: gen_sub3 = gen_subv2di3; break;
19698 gcc_unreachable ();
19700 /* Subtract (-(INT MAX) - 1) from both operands to make
19702 mask = ix86_build_signbit_mask (mode, true, false);
19703 t1 = gen_reg_rtx (mode);
19704 emit_insn (gen_sub3 (t1, cop0, mask));
19706 t2 = gen_reg_rtx (mode);
19707 emit_insn (gen_sub3 (t2, cop1, mask));
19719 /* Perform a parallel unsigned saturating subtraction. */
19720 x = gen_reg_rtx (mode);
19721 emit_insn (gen_rtx_SET (VOIDmode, x,
19722 gen_rtx_US_MINUS (mode, cop0, cop1)));
19725 cop1 = CONST0_RTX (mode);
19731 gcc_unreachable ();
19736 /* Allow the comparison to be done in one mode, but the movcc to
19737 happen in another mode. */
19738 if (data_mode == mode)
19740 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
19741 operands[1+negate], operands[2-negate]);
19745 gcc_assert (GET_MODE_SIZE (data_mode) == GET_MODE_SIZE (mode));
19746 x = ix86_expand_sse_cmp (gen_lowpart (mode, operands[0]),
19748 operands[1+negate], operands[2-negate]);
19749 x = gen_lowpart (data_mode, x);
19752 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
19753 operands[2-negate]);
19757 /* Expand a variable vector permutation. */
19760 ix86_expand_vec_perm (rtx operands[])
19762 rtx target = operands[0];
19763 rtx op0 = operands[1];
19764 rtx op1 = operands[2];
19765 rtx mask = operands[3];
19766 rtx t1, t2, t3, t4, vt, vt2, vec[32];
19767 enum machine_mode mode = GET_MODE (op0);
19768 enum machine_mode maskmode = GET_MODE (mask);
19770 bool one_operand_shuffle = rtx_equal_p (op0, op1);
19772 /* Number of elements in the vector. */
19773 w = GET_MODE_NUNITS (mode);
19774 e = GET_MODE_UNIT_SIZE (mode);
19775 gcc_assert (w <= 32);
19779 if (mode == V4DImode || mode == V4DFmode || mode == V16HImode)
19781 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
19782 an constant shuffle operand. With a tiny bit of effort we can
19783 use VPERMD instead. A re-interpretation stall for V4DFmode is
19784 unfortunate but there's no avoiding it.
19785 Similarly for V16HImode we don't have instructions for variable
19786 shuffling, while for V32QImode we can use after preparing suitable
19787 masks vpshufb; vpshufb; vpermq; vpor. */
19789 if (mode == V16HImode)
19791 maskmode = mode = V32QImode;
19797 maskmode = mode = V8SImode;
19801 t1 = gen_reg_rtx (maskmode);
19803 /* Replicate the low bits of the V4DImode mask into V8SImode:
19805 t1 = { A A B B C C D D }. */
19806 for (i = 0; i < w / 2; ++i)
19807 vec[i*2 + 1] = vec[i*2] = GEN_INT (i * 2);
19808 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
19809 vt = force_reg (maskmode, vt);
19810 mask = gen_lowpart (maskmode, mask);
19811 if (maskmode == V8SImode)
19812 emit_insn (gen_avx2_permvarv8si (t1, mask, vt));
19814 emit_insn (gen_avx2_pshufbv32qi3 (t1, mask, vt));
19816 /* Multiply the shuffle indicies by two. */
19817 t1 = expand_simple_binop (maskmode, PLUS, t1, t1, t1, 1,
19820 /* Add one to the odd shuffle indicies:
19821 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
19822 for (i = 0; i < w / 2; ++i)
19824 vec[i * 2] = const0_rtx;
19825 vec[i * 2 + 1] = const1_rtx;
19827 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
19828 vt = force_const_mem (maskmode, vt);
19829 t1 = expand_simple_binop (maskmode, PLUS, t1, vt, t1, 1,
19832 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
19833 operands[3] = mask = t1;
19834 target = gen_lowpart (mode, target);
19835 op0 = gen_lowpart (mode, op0);
19836 op1 = gen_lowpart (mode, op1);
19842 /* The VPERMD and VPERMPS instructions already properly ignore
19843 the high bits of the shuffle elements. No need for us to
19844 perform an AND ourselves. */
19845 if (one_operand_shuffle)
19846 emit_insn (gen_avx2_permvarv8si (target, op0, mask));
19849 t1 = gen_reg_rtx (V8SImode);
19850 t2 = gen_reg_rtx (V8SImode);
19851 emit_insn (gen_avx2_permvarv8si (t1, op0, mask));
19852 emit_insn (gen_avx2_permvarv8si (t2, op1, mask));
19858 mask = gen_lowpart (V8SFmode, mask);
19859 if (one_operand_shuffle)
19860 emit_insn (gen_avx2_permvarv8sf (target, op0, mask));
19863 t1 = gen_reg_rtx (V8SFmode);
19864 t2 = gen_reg_rtx (V8SFmode);
19865 emit_insn (gen_avx2_permvarv8sf (t1, op0, mask));
19866 emit_insn (gen_avx2_permvarv8sf (t2, op1, mask));
19872 /* By combining the two 128-bit input vectors into one 256-bit
19873 input vector, we can use VPERMD and VPERMPS for the full
19874 two-operand shuffle. */
19875 t1 = gen_reg_rtx (V8SImode);
19876 t2 = gen_reg_rtx (V8SImode);
19877 emit_insn (gen_avx_vec_concatv8si (t1, op0, op1));
19878 emit_insn (gen_avx_vec_concatv8si (t2, mask, mask));
19879 emit_insn (gen_avx2_permvarv8si (t1, t1, t2));
19880 emit_insn (gen_avx_vextractf128v8si (target, t1, const0_rtx));
19884 t1 = gen_reg_rtx (V8SFmode);
19885 t2 = gen_reg_rtx (V8SImode);
19886 mask = gen_lowpart (V4SImode, mask);
19887 emit_insn (gen_avx_vec_concatv8sf (t1, op0, op1));
19888 emit_insn (gen_avx_vec_concatv8si (t2, mask, mask));
19889 emit_insn (gen_avx2_permvarv8sf (t1, t1, t2));
19890 emit_insn (gen_avx_vextractf128v8sf (target, t1, const0_rtx));
19894 t1 = gen_reg_rtx (V32QImode);
19895 t2 = gen_reg_rtx (V32QImode);
19896 t3 = gen_reg_rtx (V32QImode);
19897 vt2 = GEN_INT (128);
19898 for (i = 0; i < 32; i++)
19900 vt = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, vec));
19901 vt = force_reg (V32QImode, vt);
19902 for (i = 0; i < 32; i++)
19903 vec[i] = i < 16 ? vt2 : const0_rtx;
19904 vt2 = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, vec));
19905 vt2 = force_reg (V32QImode, vt2);
19906 /* From mask create two adjusted masks, which contain the same
19907 bits as mask in the low 7 bits of each vector element.
19908 The first mask will have the most significant bit clear
19909 if it requests element from the same 128-bit lane
19910 and MSB set if it requests element from the other 128-bit lane.
19911 The second mask will have the opposite values of the MSB,
19912 and additionally will have its 128-bit lanes swapped.
19913 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
19914 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
19915 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
19916 stands for other 12 bytes. */
19917 /* The bit whether element is from the same lane or the other
19918 lane is bit 4, so shift it up by 3 to the MSB position. */
19919 emit_insn (gen_ashlv4di3 (gen_lowpart (V4DImode, t1),
19920 gen_lowpart (V4DImode, mask),
19922 /* Clear MSB bits from the mask just in case it had them set. */
19923 emit_insn (gen_avx2_andnotv32qi3 (t2, vt, mask));
19924 /* After this t1 will have MSB set for elements from other lane. */
19925 emit_insn (gen_xorv32qi3 (t1, t1, vt2));
19926 /* Clear bits other than MSB. */
19927 emit_insn (gen_andv32qi3 (t1, t1, vt));
19928 /* Or in the lower bits from mask into t3. */
19929 emit_insn (gen_iorv32qi3 (t3, t1, t2));
19930 /* And invert MSB bits in t1, so MSB is set for elements from the same
19932 emit_insn (gen_xorv32qi3 (t1, t1, vt));
19933 /* Swap 128-bit lanes in t3. */
19934 emit_insn (gen_avx2_permv4di_1 (gen_lowpart (V4DImode, t3),
19935 gen_lowpart (V4DImode, t3),
19936 const2_rtx, GEN_INT (3),
19937 const0_rtx, const1_rtx));
19938 /* And or in the lower bits from mask into t1. */
19939 emit_insn (gen_iorv32qi3 (t1, t1, t2));
19940 if (one_operand_shuffle)
19942 /* Each of these shuffles will put 0s in places where
19943 element from the other 128-bit lane is needed, otherwise
19944 will shuffle in the requested value. */
19945 emit_insn (gen_avx2_pshufbv32qi3 (t3, op0, t3));
19946 emit_insn (gen_avx2_pshufbv32qi3 (t1, op0, t1));
19947 /* For t3 the 128-bit lanes are swapped again. */
19948 emit_insn (gen_avx2_permv4di_1 (gen_lowpart (V4DImode, t3),
19949 gen_lowpart (V4DImode, t3),
19950 const2_rtx, GEN_INT (3),
19951 const0_rtx, const1_rtx));
19952 /* And oring both together leads to the result. */
19953 emit_insn (gen_iorv32qi3 (target, t1, t3));
19957 t4 = gen_reg_rtx (V32QImode);
19958 /* Similarly to the above one_operand_shuffle code,
19959 just for repeated twice for each operand. merge_two:
19960 code will merge the two results together. */
19961 emit_insn (gen_avx2_pshufbv32qi3 (t4, op0, t3));
19962 emit_insn (gen_avx2_pshufbv32qi3 (t3, op1, t3));
19963 emit_insn (gen_avx2_pshufbv32qi3 (t2, op0, t1));
19964 emit_insn (gen_avx2_pshufbv32qi3 (t1, op1, t1));
19965 emit_insn (gen_avx2_permv4di_1 (gen_lowpart (V4DImode, t4),
19966 gen_lowpart (V4DImode, t4),
19967 const2_rtx, GEN_INT (3),
19968 const0_rtx, const1_rtx));
19969 emit_insn (gen_avx2_permv4di_1 (gen_lowpart (V4DImode, t3),
19970 gen_lowpart (V4DImode, t3),
19971 const2_rtx, GEN_INT (3),
19972 const0_rtx, const1_rtx));
19973 emit_insn (gen_iorv32qi3 (t4, t2, t4));
19974 emit_insn (gen_iorv32qi3 (t3, t1, t3));
19980 gcc_assert (GET_MODE_SIZE (mode) <= 16);
19987 /* The XOP VPPERM insn supports three inputs. By ignoring the
19988 one_operand_shuffle special case, we avoid creating another
19989 set of constant vectors in memory. */
19990 one_operand_shuffle = false;
19992 /* mask = mask & {2*w-1, ...} */
19993 vt = GEN_INT (2*w - 1);
19997 /* mask = mask & {w-1, ...} */
19998 vt = GEN_INT (w - 1);
20001 for (i = 0; i < w; i++)
20003 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
20004 mask = expand_simple_binop (maskmode, AND, mask, vt,
20005 NULL_RTX, 0, OPTAB_DIRECT);
20007 /* For non-QImode operations, convert the word permutation control
20008 into a byte permutation control. */
20009 if (mode != V16QImode)
20011 mask = expand_simple_binop (maskmode, ASHIFT, mask,
20012 GEN_INT (exact_log2 (e)),
20013 NULL_RTX, 0, OPTAB_DIRECT);
20015 /* Convert mask to vector of chars. */
20016 mask = force_reg (V16QImode, gen_lowpart (V16QImode, mask));
20018 /* Replicate each of the input bytes into byte positions:
20019 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20020 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20021 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20022 for (i = 0; i < 16; ++i)
20023 vec[i] = GEN_INT (i/e * e);
20024 vt = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, vec));
20025 vt = force_const_mem (V16QImode, vt);
20027 emit_insn (gen_xop_pperm (mask, mask, mask, vt));
20029 emit_insn (gen_ssse3_pshufbv16qi3 (mask, mask, vt));
20031 /* Convert it into the byte positions by doing
20032 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20033 for (i = 0; i < 16; ++i)
20034 vec[i] = GEN_INT (i % e);
20035 vt = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, vec));
20036 vt = force_const_mem (V16QImode, vt);
20037 emit_insn (gen_addv16qi3 (mask, mask, vt));
20040 /* The actual shuffle operations all operate on V16QImode. */
20041 op0 = gen_lowpart (V16QImode, op0);
20042 op1 = gen_lowpart (V16QImode, op1);
20043 target = gen_lowpart (V16QImode, target);
20047 emit_insn (gen_xop_pperm (target, op0, op1, mask));
20049 else if (one_operand_shuffle)
20051 emit_insn (gen_ssse3_pshufbv16qi3 (target, op0, mask));
20058 /* Shuffle the two input vectors independently. */
20059 t1 = gen_reg_rtx (V16QImode);
20060 t2 = gen_reg_rtx (V16QImode);
20061 emit_insn (gen_ssse3_pshufbv16qi3 (t1, op0, mask));
20062 emit_insn (gen_ssse3_pshufbv16qi3 (t2, op1, mask));
20065 /* Then merge them together. The key is whether any given control
20066 element contained a bit set that indicates the second word. */
20067 mask = operands[3];
20069 if (maskmode == V2DImode && !TARGET_SSE4_1)
20071 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20072 more shuffle to convert the V2DI input mask into a V4SI
20073 input mask. At which point the masking that expand_int_vcond
20074 will work as desired. */
20075 rtx t3 = gen_reg_rtx (V4SImode);
20076 emit_insn (gen_sse2_pshufd_1 (t3, gen_lowpart (V4SImode, mask),
20077 const0_rtx, const0_rtx,
20078 const2_rtx, const2_rtx));
20080 maskmode = V4SImode;
20084 for (i = 0; i < w; i++)
20086 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
20087 vt = force_reg (maskmode, vt);
20088 mask = expand_simple_binop (maskmode, AND, mask, vt,
20089 NULL_RTX, 0, OPTAB_DIRECT);
20091 xops[0] = gen_lowpart (mode, operands[0]);
20092 xops[1] = gen_lowpart (mode, t2);
20093 xops[2] = gen_lowpart (mode, t1);
20094 xops[3] = gen_rtx_EQ (maskmode, mask, vt);
20097 ok = ix86_expand_int_vcond (xops);
20102 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20103 true if we should do zero extension, else sign extension. HIGH_P is
20104 true if we want the N/2 high elements, else the low elements. */
20107 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
20109 enum machine_mode imode = GET_MODE (operands[1]);
20114 rtx (*unpack)(rtx, rtx);
20115 rtx (*extract)(rtx, rtx) = NULL;
20116 enum machine_mode halfmode = BLKmode;
20122 unpack = gen_avx2_zero_extendv16qiv16hi2;
20124 unpack = gen_avx2_sign_extendv16qiv16hi2;
20125 halfmode = V16QImode;
20127 = high_p ? gen_vec_extract_hi_v32qi : gen_vec_extract_lo_v32qi;
20131 unpack = gen_avx2_zero_extendv8hiv8si2;
20133 unpack = gen_avx2_sign_extendv8hiv8si2;
20134 halfmode = V8HImode;
20136 = high_p ? gen_vec_extract_hi_v16hi : gen_vec_extract_lo_v16hi;
20140 unpack = gen_avx2_zero_extendv4siv4di2;
20142 unpack = gen_avx2_sign_extendv4siv4di2;
20143 halfmode = V4SImode;
20145 = high_p ? gen_vec_extract_hi_v8si : gen_vec_extract_lo_v8si;
20149 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
20151 unpack = gen_sse4_1_sign_extendv8qiv8hi2;
20155 unpack = gen_sse4_1_zero_extendv4hiv4si2;
20157 unpack = gen_sse4_1_sign_extendv4hiv4si2;
20161 unpack = gen_sse4_1_zero_extendv2siv2di2;
20163 unpack = gen_sse4_1_sign_extendv2siv2di2;
20166 gcc_unreachable ();
20169 if (GET_MODE_SIZE (imode) == 32)
20171 tmp = gen_reg_rtx (halfmode);
20172 emit_insn (extract (tmp, operands[1]));
20176 /* Shift higher 8 bytes to lower 8 bytes. */
20177 tmp = gen_reg_rtx (imode);
20178 emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, tmp),
20179 gen_lowpart (V1TImode, operands[1]),
20185 emit_insn (unpack (operands[0], tmp));
20189 rtx (*unpack)(rtx, rtx, rtx);
20195 unpack = gen_vec_interleave_highv16qi;
20197 unpack = gen_vec_interleave_lowv16qi;
20201 unpack = gen_vec_interleave_highv8hi;
20203 unpack = gen_vec_interleave_lowv8hi;
20207 unpack = gen_vec_interleave_highv4si;
20209 unpack = gen_vec_interleave_lowv4si;
20212 gcc_unreachable ();
20215 dest = gen_lowpart (imode, operands[0]);
20218 tmp = force_reg (imode, CONST0_RTX (imode));
20220 tmp = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
20221 operands[1], pc_rtx, pc_rtx);
20223 emit_insn (unpack (dest, operands[1], tmp));
20227 /* Expand conditional increment or decrement using adb/sbb instructions.
20228 The default case using setcc followed by the conditional move can be
20229 done by generic code. */
20231 ix86_expand_int_addcc (rtx operands[])
20233 enum rtx_code code = GET_CODE (operands[1]);
20235 rtx (*insn)(rtx, rtx, rtx, rtx, rtx);
20237 rtx val = const0_rtx;
20238 bool fpcmp = false;
20239 enum machine_mode mode;
20240 rtx op0 = XEXP (operands[1], 0);
20241 rtx op1 = XEXP (operands[1], 1);
20243 if (operands[3] != const1_rtx
20244 && operands[3] != constm1_rtx)
20246 if (!ix86_expand_carry_flag_compare (code, op0, op1, &compare_op))
20248 code = GET_CODE (compare_op);
20250 flags = XEXP (compare_op, 0);
20252 if (GET_MODE (flags) == CCFPmode
20253 || GET_MODE (flags) == CCFPUmode)
20256 code = ix86_fp_compare_code_to_integer (code);
20263 PUT_CODE (compare_op,
20264 reverse_condition_maybe_unordered
20265 (GET_CODE (compare_op)));
20267 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
20270 mode = GET_MODE (operands[0]);
20272 /* Construct either adc or sbb insn. */
20273 if ((code == LTU) == (operands[3] == constm1_rtx))
20278 insn = gen_subqi3_carry;
20281 insn = gen_subhi3_carry;
20284 insn = gen_subsi3_carry;
20287 insn = gen_subdi3_carry;
20290 gcc_unreachable ();
20298 insn = gen_addqi3_carry;
20301 insn = gen_addhi3_carry;
20304 insn = gen_addsi3_carry;
20307 insn = gen_adddi3_carry;
20310 gcc_unreachable ();
20313 emit_insn (insn (operands[0], operands[2], val, flags, compare_op));
20319 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20320 but works for floating pointer parameters and nonoffsetable memories.
20321 For pushes, it returns just stack offsets; the values will be saved
20322 in the right order. Maximally three parts are generated. */
20325 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
20330 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
20332 size = (GET_MODE_SIZE (mode) + 4) / 8;
20334 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
20335 gcc_assert (size >= 2 && size <= 4);
20337 /* Optimize constant pool reference to immediates. This is used by fp
20338 moves, that force all constants to memory to allow combining. */
20339 if (MEM_P (operand) && MEM_READONLY_P (operand))
20341 rtx tmp = maybe_get_pool_constant (operand);
20346 if (MEM_P (operand) && !offsettable_memref_p (operand))
20348 /* The only non-offsetable memories we handle are pushes. */
20349 int ok = push_operand (operand, VOIDmode);
20353 operand = copy_rtx (operand);
20354 PUT_MODE (operand, Pmode);
20355 parts[0] = parts[1] = parts[2] = parts[3] = operand;
20359 if (GET_CODE (operand) == CONST_VECTOR)
20361 enum machine_mode imode = int_mode_for_mode (mode);
20362 /* Caution: if we looked through a constant pool memory above,
20363 the operand may actually have a different mode now. That's
20364 ok, since we want to pun this all the way back to an integer. */
20365 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
20366 gcc_assert (operand != NULL);
20372 if (mode == DImode)
20373 split_double_mode (mode, &operand, 1, &parts[0], &parts[1]);
20378 if (REG_P (operand))
20380 gcc_assert (reload_completed);
20381 for (i = 0; i < size; i++)
20382 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
20384 else if (offsettable_memref_p (operand))
20386 operand = adjust_address (operand, SImode, 0);
20387 parts[0] = operand;
20388 for (i = 1; i < size; i++)
20389 parts[i] = adjust_address (operand, SImode, 4 * i);
20391 else if (GET_CODE (operand) == CONST_DOUBLE)
20396 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
20400 real_to_target (l, &r, mode);
20401 parts[3] = gen_int_mode (l[3], SImode);
20402 parts[2] = gen_int_mode (l[2], SImode);
20405 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
20406 parts[2] = gen_int_mode (l[2], SImode);
20409 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
20412 gcc_unreachable ();
20414 parts[1] = gen_int_mode (l[1], SImode);
20415 parts[0] = gen_int_mode (l[0], SImode);
20418 gcc_unreachable ();
20423 if (mode == TImode)
20424 split_double_mode (mode, &operand, 1, &parts[0], &parts[1]);
20425 if (mode == XFmode || mode == TFmode)
20427 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
20428 if (REG_P (operand))
20430 gcc_assert (reload_completed);
20431 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
20432 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
20434 else if (offsettable_memref_p (operand))
20436 operand = adjust_address (operand, DImode, 0);
20437 parts[0] = operand;
20438 parts[1] = adjust_address (operand, upper_mode, 8);
20440 else if (GET_CODE (operand) == CONST_DOUBLE)
20445 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
20446 real_to_target (l, &r, mode);
20448 /* Do not use shift by 32 to avoid warning on 32bit systems. */
20449 if (HOST_BITS_PER_WIDE_INT >= 64)
20452 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
20453 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
20456 parts[0] = immed_double_const (l[0], l[1], DImode);
20458 if (upper_mode == SImode)
20459 parts[1] = gen_int_mode (l[2], SImode);
20460 else if (HOST_BITS_PER_WIDE_INT >= 64)
20463 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
20464 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
20467 parts[1] = immed_double_const (l[2], l[3], DImode);
20470 gcc_unreachable ();
20477 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
20478 Return false when normal moves are needed; true when all required
20479 insns have been emitted. Operands 2-4 contain the input values
20480 int the correct order; operands 5-7 contain the output values. */
20483 ix86_split_long_move (rtx operands[])
20488 int collisions = 0;
20489 enum machine_mode mode = GET_MODE (operands[0]);
20490 bool collisionparts[4];
20492 /* The DFmode expanders may ask us to move double.
20493 For 64bit target this is single move. By hiding the fact
20494 here we simplify i386.md splitters. */
20495 if (TARGET_64BIT && GET_MODE_SIZE (GET_MODE (operands[0])) == 8)
20497 /* Optimize constant pool reference to immediates. This is used by
20498 fp moves, that force all constants to memory to allow combining. */
20500 if (MEM_P (operands[1])
20501 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
20502 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
20503 operands[1] = get_pool_constant (XEXP (operands[1], 0));
20504 if (push_operand (operands[0], VOIDmode))
20506 operands[0] = copy_rtx (operands[0]);
20507 PUT_MODE (operands[0], Pmode);
20510 operands[0] = gen_lowpart (DImode, operands[0]);
20511 operands[1] = gen_lowpart (DImode, operands[1]);
20512 emit_move_insn (operands[0], operands[1]);
20516 /* The only non-offsettable memory we handle is push. */
20517 if (push_operand (operands[0], VOIDmode))
20520 gcc_assert (!MEM_P (operands[0])
20521 || offsettable_memref_p (operands[0]));
20523 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
20524 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
20526 /* When emitting push, take care for source operands on the stack. */
20527 if (push && MEM_P (operands[1])
20528 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
20530 rtx src_base = XEXP (part[1][nparts - 1], 0);
20532 /* Compensate for the stack decrement by 4. */
20533 if (!TARGET_64BIT && nparts == 3
20534 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
20535 src_base = plus_constant (src_base, 4);
20537 /* src_base refers to the stack pointer and is
20538 automatically decreased by emitted push. */
20539 for (i = 0; i < nparts; i++)
20540 part[1][i] = change_address (part[1][i],
20541 GET_MODE (part[1][i]), src_base);
20544 /* We need to do copy in the right order in case an address register
20545 of the source overlaps the destination. */
20546 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
20550 for (i = 0; i < nparts; i++)
20553 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
20554 if (collisionparts[i])
20558 /* Collision in the middle part can be handled by reordering. */
20559 if (collisions == 1 && nparts == 3 && collisionparts [1])
20561 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
20562 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
20564 else if (collisions == 1
20566 && (collisionparts [1] || collisionparts [2]))
20568 if (collisionparts [1])
20570 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
20571 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
20575 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
20576 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
20580 /* If there are more collisions, we can't handle it by reordering.
20581 Do an lea to the last part and use only one colliding move. */
20582 else if (collisions > 1)
20588 base = part[0][nparts - 1];
20590 /* Handle the case when the last part isn't valid for lea.
20591 Happens in 64-bit mode storing the 12-byte XFmode. */
20592 if (GET_MODE (base) != Pmode)
20593 base = gen_rtx_REG (Pmode, REGNO (base));
20595 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
20596 part[1][0] = replace_equiv_address (part[1][0], base);
20597 for (i = 1; i < nparts; i++)
20599 tmp = plus_constant (base, UNITS_PER_WORD * i);
20600 part[1][i] = replace_equiv_address (part[1][i], tmp);
20611 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
20612 emit_insn (gen_addsi3 (stack_pointer_rtx,
20613 stack_pointer_rtx, GEN_INT (-4)));
20614 emit_move_insn (part[0][2], part[1][2]);
20616 else if (nparts == 4)
20618 emit_move_insn (part[0][3], part[1][3]);
20619 emit_move_insn (part[0][2], part[1][2]);
20624 /* In 64bit mode we don't have 32bit push available. In case this is
20625 register, it is OK - we will just use larger counterpart. We also
20626 retype memory - these comes from attempt to avoid REX prefix on
20627 moving of second half of TFmode value. */
20628 if (GET_MODE (part[1][1]) == SImode)
20630 switch (GET_CODE (part[1][1]))
20633 part[1][1] = adjust_address (part[1][1], DImode, 0);
20637 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
20641 gcc_unreachable ();
20644 if (GET_MODE (part[1][0]) == SImode)
20645 part[1][0] = part[1][1];
20648 emit_move_insn (part[0][1], part[1][1]);
20649 emit_move_insn (part[0][0], part[1][0]);
20653 /* Choose correct order to not overwrite the source before it is copied. */
20654 if ((REG_P (part[0][0])
20655 && REG_P (part[1][1])
20656 && (REGNO (part[0][0]) == REGNO (part[1][1])
20658 && REGNO (part[0][0]) == REGNO (part[1][2]))
20660 && REGNO (part[0][0]) == REGNO (part[1][3]))))
20662 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
20664 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
20666 operands[2 + i] = part[0][j];
20667 operands[6 + i] = part[1][j];
20672 for (i = 0; i < nparts; i++)
20674 operands[2 + i] = part[0][i];
20675 operands[6 + i] = part[1][i];
20679 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
20680 if (optimize_insn_for_size_p ())
20682 for (j = 0; j < nparts - 1; j++)
20683 if (CONST_INT_P (operands[6 + j])
20684 && operands[6 + j] != const0_rtx
20685 && REG_P (operands[2 + j]))
20686 for (i = j; i < nparts - 1; i++)
20687 if (CONST_INT_P (operands[7 + i])
20688 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
20689 operands[7 + i] = operands[2 + j];
20692 for (i = 0; i < nparts; i++)
20693 emit_move_insn (operands[2 + i], operands[6 + i]);
20698 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
20699 left shift by a constant, either using a single shift or
20700 a sequence of add instructions. */
20703 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
20705 rtx (*insn)(rtx, rtx, rtx);
20708 || (count * ix86_cost->add <= ix86_cost->shift_const
20709 && !optimize_insn_for_size_p ()))
20711 insn = mode == DImode ? gen_addsi3 : gen_adddi3;
20712 while (count-- > 0)
20713 emit_insn (insn (operand, operand, operand));
20717 insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3;
20718 emit_insn (insn (operand, operand, GEN_INT (count)));
20723 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
20725 rtx (*gen_ashl3)(rtx, rtx, rtx);
20726 rtx (*gen_shld)(rtx, rtx, rtx);
20727 int half_width = GET_MODE_BITSIZE (mode) >> 1;
20729 rtx low[2], high[2];
20732 if (CONST_INT_P (operands[2]))
20734 split_double_mode (mode, operands, 2, low, high);
20735 count = INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode) - 1);
20737 if (count >= half_width)
20739 emit_move_insn (high[0], low[1]);
20740 emit_move_insn (low[0], const0_rtx);
20742 if (count > half_width)
20743 ix86_expand_ashl_const (high[0], count - half_width, mode);
20747 gen_shld = mode == DImode ? gen_x86_shld : gen_x86_64_shld;
20749 if (!rtx_equal_p (operands[0], operands[1]))
20750 emit_move_insn (operands[0], operands[1]);
20752 emit_insn (gen_shld (high[0], low[0], GEN_INT (count)));
20753 ix86_expand_ashl_const (low[0], count, mode);
20758 split_double_mode (mode, operands, 1, low, high);
20760 gen_ashl3 = mode == DImode ? gen_ashlsi3 : gen_ashldi3;
20762 if (operands[1] == const1_rtx)
20764 /* Assuming we've chosen a QImode capable registers, then 1 << N
20765 can be done with two 32/64-bit shifts, no branches, no cmoves. */
20766 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
20768 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
20770 ix86_expand_clear (low[0]);
20771 ix86_expand_clear (high[0]);
20772 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (half_width)));
20774 d = gen_lowpart (QImode, low[0]);
20775 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
20776 s = gen_rtx_EQ (QImode, flags, const0_rtx);
20777 emit_insn (gen_rtx_SET (VOIDmode, d, s));
20779 d = gen_lowpart (QImode, high[0]);
20780 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
20781 s = gen_rtx_NE (QImode, flags, const0_rtx);
20782 emit_insn (gen_rtx_SET (VOIDmode, d, s));
20785 /* Otherwise, we can get the same results by manually performing
20786 a bit extract operation on bit 5/6, and then performing the two
20787 shifts. The two methods of getting 0/1 into low/high are exactly
20788 the same size. Avoiding the shift in the bit extract case helps
20789 pentium4 a bit; no one else seems to care much either way. */
20792 enum machine_mode half_mode;
20793 rtx (*gen_lshr3)(rtx, rtx, rtx);
20794 rtx (*gen_and3)(rtx, rtx, rtx);
20795 rtx (*gen_xor3)(rtx, rtx, rtx);
20796 HOST_WIDE_INT bits;
20799 if (mode == DImode)
20801 half_mode = SImode;
20802 gen_lshr3 = gen_lshrsi3;
20803 gen_and3 = gen_andsi3;
20804 gen_xor3 = gen_xorsi3;
20809 half_mode = DImode;
20810 gen_lshr3 = gen_lshrdi3;
20811 gen_and3 = gen_anddi3;
20812 gen_xor3 = gen_xordi3;
20816 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
20817 x = gen_rtx_ZERO_EXTEND (half_mode, operands[2]);
20819 x = gen_lowpart (half_mode, operands[2]);
20820 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
20822 emit_insn (gen_lshr3 (high[0], high[0], GEN_INT (bits)));
20823 emit_insn (gen_and3 (high[0], high[0], const1_rtx));
20824 emit_move_insn (low[0], high[0]);
20825 emit_insn (gen_xor3 (low[0], low[0], const1_rtx));
20828 emit_insn (gen_ashl3 (low[0], low[0], operands[2]));
20829 emit_insn (gen_ashl3 (high[0], high[0], operands[2]));
20833 if (operands[1] == constm1_rtx)
20835 /* For -1 << N, we can avoid the shld instruction, because we
20836 know that we're shifting 0...31/63 ones into a -1. */
20837 emit_move_insn (low[0], constm1_rtx);
20838 if (optimize_insn_for_size_p ())
20839 emit_move_insn (high[0], low[0]);
20841 emit_move_insn (high[0], constm1_rtx);
20845 gen_shld = mode == DImode ? gen_x86_shld : gen_x86_64_shld;
20847 if (!rtx_equal_p (operands[0], operands[1]))
20848 emit_move_insn (operands[0], operands[1]);
20850 split_double_mode (mode, operands, 1, low, high);
20851 emit_insn (gen_shld (high[0], low[0], operands[2]));
20854 emit_insn (gen_ashl3 (low[0], low[0], operands[2]));
20856 if (TARGET_CMOVE && scratch)
20858 rtx (*gen_x86_shift_adj_1)(rtx, rtx, rtx, rtx)
20859 = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1;
20861 ix86_expand_clear (scratch);
20862 emit_insn (gen_x86_shift_adj_1 (high[0], low[0], operands[2], scratch));
20866 rtx (*gen_x86_shift_adj_2)(rtx, rtx, rtx)
20867 = mode == DImode ? gen_x86_shiftsi_adj_2 : gen_x86_shiftdi_adj_2;
20869 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
20874 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
20876 rtx (*gen_ashr3)(rtx, rtx, rtx)
20877 = mode == DImode ? gen_ashrsi3 : gen_ashrdi3;
20878 rtx (*gen_shrd)(rtx, rtx, rtx);
20879 int half_width = GET_MODE_BITSIZE (mode) >> 1;
20881 rtx low[2], high[2];
20884 if (CONST_INT_P (operands[2]))
20886 split_double_mode (mode, operands, 2, low, high);
20887 count = INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode) - 1);
20889 if (count == GET_MODE_BITSIZE (mode) - 1)
20891 emit_move_insn (high[0], high[1]);
20892 emit_insn (gen_ashr3 (high[0], high[0],
20893 GEN_INT (half_width - 1)));
20894 emit_move_insn (low[0], high[0]);
20897 else if (count >= half_width)
20899 emit_move_insn (low[0], high[1]);
20900 emit_move_insn (high[0], low[0]);
20901 emit_insn (gen_ashr3 (high[0], high[0],
20902 GEN_INT (half_width - 1)));
20904 if (count > half_width)
20905 emit_insn (gen_ashr3 (low[0], low[0],
20906 GEN_INT (count - half_width)));
20910 gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd;
20912 if (!rtx_equal_p (operands[0], operands[1]))
20913 emit_move_insn (operands[0], operands[1]);
20915 emit_insn (gen_shrd (low[0], high[0], GEN_INT (count)));
20916 emit_insn (gen_ashr3 (high[0], high[0], GEN_INT (count)));
20921 gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd;
20923 if (!rtx_equal_p (operands[0], operands[1]))
20924 emit_move_insn (operands[0], operands[1]);
20926 split_double_mode (mode, operands, 1, low, high);
20928 emit_insn (gen_shrd (low[0], high[0], operands[2]));
20929 emit_insn (gen_ashr3 (high[0], high[0], operands[2]));
20931 if (TARGET_CMOVE && scratch)
20933 rtx (*gen_x86_shift_adj_1)(rtx, rtx, rtx, rtx)
20934 = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1;
20936 emit_move_insn (scratch, high[0]);
20937 emit_insn (gen_ashr3 (scratch, scratch,
20938 GEN_INT (half_width - 1)));
20939 emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2],
20944 rtx (*gen_x86_shift_adj_3)(rtx, rtx, rtx)
20945 = mode == DImode ? gen_x86_shiftsi_adj_3 : gen_x86_shiftdi_adj_3;
20947 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
20953 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
20955 rtx (*gen_lshr3)(rtx, rtx, rtx)
20956 = mode == DImode ? gen_lshrsi3 : gen_lshrdi3;
20957 rtx (*gen_shrd)(rtx, rtx, rtx);
20958 int half_width = GET_MODE_BITSIZE (mode) >> 1;
20960 rtx low[2], high[2];
20963 if (CONST_INT_P (operands[2]))
20965 split_double_mode (mode, operands, 2, low, high);
20966 count = INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode) - 1);
20968 if (count >= half_width)
20970 emit_move_insn (low[0], high[1]);
20971 ix86_expand_clear (high[0]);
20973 if (count > half_width)
20974 emit_insn (gen_lshr3 (low[0], low[0],
20975 GEN_INT (count - half_width)));
20979 gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd;
20981 if (!rtx_equal_p (operands[0], operands[1]))
20982 emit_move_insn (operands[0], operands[1]);
20984 emit_insn (gen_shrd (low[0], high[0], GEN_INT (count)));
20985 emit_insn (gen_lshr3 (high[0], high[0], GEN_INT (count)));
20990 gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd;
20992 if (!rtx_equal_p (operands[0], operands[1]))
20993 emit_move_insn (operands[0], operands[1]);
20995 split_double_mode (mode, operands, 1, low, high);
20997 emit_insn (gen_shrd (low[0], high[0], operands[2]));
20998 emit_insn (gen_lshr3 (high[0], high[0], operands[2]));
21000 if (TARGET_CMOVE && scratch)
21002 rtx (*gen_x86_shift_adj_1)(rtx, rtx, rtx, rtx)
21003 = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1;
21005 ix86_expand_clear (scratch);
21006 emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2],
21011 rtx (*gen_x86_shift_adj_2)(rtx, rtx, rtx)
21012 = mode == DImode ? gen_x86_shiftsi_adj_2 : gen_x86_shiftdi_adj_2;
21014 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
21019 /* Predict just emitted jump instruction to be taken with probability PROB. */
21021 predict_jump (int prob)
21023 rtx insn = get_last_insn ();
21024 gcc_assert (JUMP_P (insn));
21025 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
21028 /* Helper function for the string operations below. Dest VARIABLE whether
21029 it is aligned to VALUE bytes. If true, jump to the label. */
21031 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
21033 rtx label = gen_label_rtx ();
21034 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
21035 if (GET_MODE (variable) == DImode)
21036 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
21038 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
21039 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
21042 predict_jump (REG_BR_PROB_BASE * 50 / 100);
21044 predict_jump (REG_BR_PROB_BASE * 90 / 100);
21048 /* Adjust COUNTER by the VALUE. */
21050 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
21052 rtx (*gen_add)(rtx, rtx, rtx)
21053 = GET_MODE (countreg) == DImode ? gen_adddi3 : gen_addsi3;
21055 emit_insn (gen_add (countreg, countreg, GEN_INT (-value)));
21058 /* Zero extend possibly SImode EXP to Pmode register. */
21060 ix86_zero_extend_to_Pmode (rtx exp)
21063 if (GET_MODE (exp) == VOIDmode)
21064 return force_reg (Pmode, exp);
21065 if (GET_MODE (exp) == Pmode)
21066 return copy_to_mode_reg (Pmode, exp);
21067 r = gen_reg_rtx (Pmode);
21068 emit_insn (gen_zero_extendsidi2 (r, exp));
21072 /* Divide COUNTREG by SCALE. */
21074 scale_counter (rtx countreg, int scale)
21080 if (CONST_INT_P (countreg))
21081 return GEN_INT (INTVAL (countreg) / scale);
21082 gcc_assert (REG_P (countreg));
21084 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
21085 GEN_INT (exact_log2 (scale)),
21086 NULL, 1, OPTAB_DIRECT);
21090 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21091 DImode for constant loop counts. */
21093 static enum machine_mode
21094 counter_mode (rtx count_exp)
21096 if (GET_MODE (count_exp) != VOIDmode)
21097 return GET_MODE (count_exp);
21098 if (!CONST_INT_P (count_exp))
21100 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
21105 /* When SRCPTR is non-NULL, output simple loop to move memory
21106 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21107 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21108 equivalent loop to set memory by VALUE (supposed to be in MODE).
21110 The size is rounded down to whole number of chunk size moved at once.
21111 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21115 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
21116 rtx destptr, rtx srcptr, rtx value,
21117 rtx count, enum machine_mode mode, int unroll,
21120 rtx out_label, top_label, iter, tmp;
21121 enum machine_mode iter_mode = counter_mode (count);
21122 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
21123 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
21129 top_label = gen_label_rtx ();
21130 out_label = gen_label_rtx ();
21131 iter = gen_reg_rtx (iter_mode);
21133 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
21134 NULL, 1, OPTAB_DIRECT);
21135 /* Those two should combine. */
21136 if (piece_size == const1_rtx)
21138 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
21140 predict_jump (REG_BR_PROB_BASE * 10 / 100);
21142 emit_move_insn (iter, const0_rtx);
21144 emit_label (top_label);
21146 tmp = convert_modes (Pmode, iter_mode, iter, true);
21147 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
21148 destmem = change_address (destmem, mode, x_addr);
21152 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
21153 srcmem = change_address (srcmem, mode, y_addr);
21155 /* When unrolling for chips that reorder memory reads and writes,
21156 we can save registers by using single temporary.
21157 Also using 4 temporaries is overkill in 32bit mode. */
21158 if (!TARGET_64BIT && 0)
21160 for (i = 0; i < unroll; i++)
21165 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
21167 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
21169 emit_move_insn (destmem, srcmem);
21175 gcc_assert (unroll <= 4);
21176 for (i = 0; i < unroll; i++)
21178 tmpreg[i] = gen_reg_rtx (mode);
21182 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
21184 emit_move_insn (tmpreg[i], srcmem);
21186 for (i = 0; i < unroll; i++)
21191 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
21193 emit_move_insn (destmem, tmpreg[i]);
21198 for (i = 0; i < unroll; i++)
21202 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
21203 emit_move_insn (destmem, value);
21206 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
21207 true, OPTAB_LIB_WIDEN);
21209 emit_move_insn (iter, tmp);
21211 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
21213 if (expected_size != -1)
21215 expected_size /= GET_MODE_SIZE (mode) * unroll;
21216 if (expected_size == 0)
21218 else if (expected_size > REG_BR_PROB_BASE)
21219 predict_jump (REG_BR_PROB_BASE - 1);
21221 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
21224 predict_jump (REG_BR_PROB_BASE * 80 / 100);
21225 iter = ix86_zero_extend_to_Pmode (iter);
21226 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
21227 true, OPTAB_LIB_WIDEN);
21228 if (tmp != destptr)
21229 emit_move_insn (destptr, tmp);
21232 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
21233 true, OPTAB_LIB_WIDEN);
21235 emit_move_insn (srcptr, tmp);
21237 emit_label (out_label);
21240 /* Output "rep; mov" instruction.
21241 Arguments have same meaning as for previous function */
21243 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
21244 rtx destptr, rtx srcptr,
21246 enum machine_mode mode)
21251 HOST_WIDE_INT rounded_count;
21253 /* If the size is known, it is shorter to use rep movs. */
21254 if (mode == QImode && CONST_INT_P (count)
21255 && !(INTVAL (count) & 3))
21258 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
21259 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
21260 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
21261 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
21262 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
21263 if (mode != QImode)
21265 destexp = gen_rtx_ASHIFT (Pmode, countreg,
21266 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
21267 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
21268 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
21269 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
21270 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
21274 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
21275 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
21277 if (CONST_INT_P (count))
21279 rounded_count = (INTVAL (count)
21280 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
21281 destmem = shallow_copy_rtx (destmem);
21282 srcmem = shallow_copy_rtx (srcmem);
21283 set_mem_size (destmem, rounded_count);
21284 set_mem_size (srcmem, rounded_count);
21288 if (MEM_SIZE_KNOWN_P (destmem))
21289 clear_mem_size (destmem);
21290 if (MEM_SIZE_KNOWN_P (srcmem))
21291 clear_mem_size (srcmem);
21293 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
21297 /* Output "rep; stos" instruction.
21298 Arguments have same meaning as for previous function */
21300 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
21301 rtx count, enum machine_mode mode,
21306 HOST_WIDE_INT rounded_count;
21308 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
21309 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
21310 value = force_reg (mode, gen_lowpart (mode, value));
21311 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
21312 if (mode != QImode)
21314 destexp = gen_rtx_ASHIFT (Pmode, countreg,
21315 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
21316 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
21319 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
21320 if (orig_value == const0_rtx && CONST_INT_P (count))
21322 rounded_count = (INTVAL (count)
21323 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
21324 destmem = shallow_copy_rtx (destmem);
21325 set_mem_size (destmem, rounded_count);
21327 else if (MEM_SIZE_KNOWN_P (destmem))
21328 clear_mem_size (destmem);
21329 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
21333 emit_strmov (rtx destmem, rtx srcmem,
21334 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
21336 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
21337 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
21338 emit_insn (gen_strmov (destptr, dest, srcptr, src));
21341 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21343 expand_movmem_epilogue (rtx destmem, rtx srcmem,
21344 rtx destptr, rtx srcptr, rtx count, int max_size)
21347 if (CONST_INT_P (count))
21349 HOST_WIDE_INT countval = INTVAL (count);
21352 if ((countval & 0x10) && max_size > 16)
21356 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
21357 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
21360 gcc_unreachable ();
21363 if ((countval & 0x08) && max_size > 8)
21366 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
21369 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
21370 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
21374 if ((countval & 0x04) && max_size > 4)
21376 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
21379 if ((countval & 0x02) && max_size > 2)
21381 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
21384 if ((countval & 0x01) && max_size > 1)
21386 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
21393 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
21394 count, 1, OPTAB_DIRECT);
21395 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
21396 count, QImode, 1, 4);
21400 /* When there are stringops, we can cheaply increase dest and src pointers.
21401 Otherwise we save code size by maintaining offset (zero is readily
21402 available from preceding rep operation) and using x86 addressing modes.
21404 if (TARGET_SINGLE_STRINGOP)
21408 rtx label = ix86_expand_aligntest (count, 4, true);
21409 src = change_address (srcmem, SImode, srcptr);
21410 dest = change_address (destmem, SImode, destptr);
21411 emit_insn (gen_strmov (destptr, dest, srcptr, src));
21412 emit_label (label);
21413 LABEL_NUSES (label) = 1;
21417 rtx label = ix86_expand_aligntest (count, 2, true);
21418 src = change_address (srcmem, HImode, srcptr);
21419 dest = change_address (destmem, HImode, destptr);
21420 emit_insn (gen_strmov (destptr, dest, srcptr, src));
21421 emit_label (label);
21422 LABEL_NUSES (label) = 1;
21426 rtx label = ix86_expand_aligntest (count, 1, true);
21427 src = change_address (srcmem, QImode, srcptr);
21428 dest = change_address (destmem, QImode, destptr);
21429 emit_insn (gen_strmov (destptr, dest, srcptr, src));
21430 emit_label (label);
21431 LABEL_NUSES (label) = 1;
21436 rtx offset = force_reg (Pmode, const0_rtx);
21441 rtx label = ix86_expand_aligntest (count, 4, true);
21442 src = change_address (srcmem, SImode, srcptr);
21443 dest = change_address (destmem, SImode, destptr);
21444 emit_move_insn (dest, src);
21445 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
21446 true, OPTAB_LIB_WIDEN);
21448 emit_move_insn (offset, tmp);
21449 emit_label (label);
21450 LABEL_NUSES (label) = 1;
21454 rtx label = ix86_expand_aligntest (count, 2, true);
21455 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
21456 src = change_address (srcmem, HImode, tmp);
21457 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
21458 dest = change_address (destmem, HImode, tmp);
21459 emit_move_insn (dest, src);
21460 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
21461 true, OPTAB_LIB_WIDEN);
21463 emit_move_insn (offset, tmp);
21464 emit_label (label);
21465 LABEL_NUSES (label) = 1;
21469 rtx label = ix86_expand_aligntest (count, 1, true);
21470 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
21471 src = change_address (srcmem, QImode, tmp);
21472 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
21473 dest = change_address (destmem, QImode, tmp);
21474 emit_move_insn (dest, src);
21475 emit_label (label);
21476 LABEL_NUSES (label) = 1;
21481 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
21483 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
21484 rtx count, int max_size)
21487 expand_simple_binop (counter_mode (count), AND, count,
21488 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
21489 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
21490 gen_lowpart (QImode, value), count, QImode,
21494 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
21496 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
21500 if (CONST_INT_P (count))
21502 HOST_WIDE_INT countval = INTVAL (count);
21505 if ((countval & 0x10) && max_size > 16)
21509 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
21510 emit_insn (gen_strset (destptr, dest, value));
21511 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
21512 emit_insn (gen_strset (destptr, dest, value));
21515 gcc_unreachable ();
21518 if ((countval & 0x08) && max_size > 8)
21522 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
21523 emit_insn (gen_strset (destptr, dest, value));
21527 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
21528 emit_insn (gen_strset (destptr, dest, value));
21529 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
21530 emit_insn (gen_strset (destptr, dest, value));
21534 if ((countval & 0x04) && max_size > 4)
21536 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
21537 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
21540 if ((countval & 0x02) && max_size > 2)
21542 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
21543 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
21546 if ((countval & 0x01) && max_size > 1)
21548 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
21549 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
21556 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
21561 rtx label = ix86_expand_aligntest (count, 16, true);
21564 dest = change_address (destmem, DImode, destptr);
21565 emit_insn (gen_strset (destptr, dest, value));
21566 emit_insn (gen_strset (destptr, dest, value));
21570 dest = change_address (destmem, SImode, destptr);
21571 emit_insn (gen_strset (destptr, dest, value));
21572 emit_insn (gen_strset (destptr, dest, value));
21573 emit_insn (gen_strset (destptr, dest, value));
21574 emit_insn (gen_strset (destptr, dest, value));
21576 emit_label (label);
21577 LABEL_NUSES (label) = 1;
21581 rtx label = ix86_expand_aligntest (count, 8, true);
21584 dest = change_address (destmem, DImode, destptr);
21585 emit_insn (gen_strset (destptr, dest, value));
21589 dest = change_address (destmem, SImode, destptr);
21590 emit_insn (gen_strset (destptr, dest, value));
21591 emit_insn (gen_strset (destptr, dest, value));
21593 emit_label (label);
21594 LABEL_NUSES (label) = 1;
21598 rtx label = ix86_expand_aligntest (count, 4, true);
21599 dest = change_address (destmem, SImode, destptr);
21600 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
21601 emit_label (label);
21602 LABEL_NUSES (label) = 1;
21606 rtx label = ix86_expand_aligntest (count, 2, true);
21607 dest = change_address (destmem, HImode, destptr);
21608 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
21609 emit_label (label);
21610 LABEL_NUSES (label) = 1;
21614 rtx label = ix86_expand_aligntest (count, 1, true);
21615 dest = change_address (destmem, QImode, destptr);
21616 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
21617 emit_label (label);
21618 LABEL_NUSES (label) = 1;
21622 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
21623 DESIRED_ALIGNMENT. */
21625 expand_movmem_prologue (rtx destmem, rtx srcmem,
21626 rtx destptr, rtx srcptr, rtx count,
21627 int align, int desired_alignment)
21629 if (align <= 1 && desired_alignment > 1)
21631 rtx label = ix86_expand_aligntest (destptr, 1, false);
21632 srcmem = change_address (srcmem, QImode, srcptr);
21633 destmem = change_address (destmem, QImode, destptr);
21634 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
21635 ix86_adjust_counter (count, 1);
21636 emit_label (label);
21637 LABEL_NUSES (label) = 1;
21639 if (align <= 2 && desired_alignment > 2)
21641 rtx label = ix86_expand_aligntest (destptr, 2, false);
21642 srcmem = change_address (srcmem, HImode, srcptr);
21643 destmem = change_address (destmem, HImode, destptr);
21644 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
21645 ix86_adjust_counter (count, 2);
21646 emit_label (label);
21647 LABEL_NUSES (label) = 1;
21649 if (align <= 4 && desired_alignment > 4)
21651 rtx label = ix86_expand_aligntest (destptr, 4, false);
21652 srcmem = change_address (srcmem, SImode, srcptr);
21653 destmem = change_address (destmem, SImode, destptr);
21654 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
21655 ix86_adjust_counter (count, 4);
21656 emit_label (label);
21657 LABEL_NUSES (label) = 1;
21659 gcc_assert (desired_alignment <= 8);
21662 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
21663 ALIGN_BYTES is how many bytes need to be copied. */
21665 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
21666 int desired_align, int align_bytes)
21669 rtx orig_dst = dst;
21670 rtx orig_src = src;
21672 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
21673 if (src_align_bytes >= 0)
21674 src_align_bytes = desired_align - src_align_bytes;
21675 if (align_bytes & 1)
21677 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
21678 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
21680 emit_insn (gen_strmov (destreg, dst, srcreg, src));
21682 if (align_bytes & 2)
21684 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
21685 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
21686 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
21687 set_mem_align (dst, 2 * BITS_PER_UNIT);
21688 if (src_align_bytes >= 0
21689 && (src_align_bytes & 1) == (align_bytes & 1)
21690 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
21691 set_mem_align (src, 2 * BITS_PER_UNIT);
21693 emit_insn (gen_strmov (destreg, dst, srcreg, src));
21695 if (align_bytes & 4)
21697 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
21698 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
21699 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
21700 set_mem_align (dst, 4 * BITS_PER_UNIT);
21701 if (src_align_bytes >= 0)
21703 unsigned int src_align = 0;
21704 if ((src_align_bytes & 3) == (align_bytes & 3))
21706 else if ((src_align_bytes & 1) == (align_bytes & 1))
21708 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
21709 set_mem_align (src, src_align * BITS_PER_UNIT);
21712 emit_insn (gen_strmov (destreg, dst, srcreg, src));
21714 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
21715 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
21716 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
21717 set_mem_align (dst, desired_align * BITS_PER_UNIT);
21718 if (src_align_bytes >= 0)
21720 unsigned int src_align = 0;
21721 if ((src_align_bytes & 7) == (align_bytes & 7))
21723 else if ((src_align_bytes & 3) == (align_bytes & 3))
21725 else if ((src_align_bytes & 1) == (align_bytes & 1))
21727 if (src_align > (unsigned int) desired_align)
21728 src_align = desired_align;
21729 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
21730 set_mem_align (src, src_align * BITS_PER_UNIT);
21732 if (MEM_SIZE_KNOWN_P (orig_dst))
21733 set_mem_size (dst, MEM_SIZE (orig_dst) - align_bytes);
21734 if (MEM_SIZE_KNOWN_P (orig_src))
21735 set_mem_size (src, MEM_SIZE (orig_src) - align_bytes);
21740 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
21741 DESIRED_ALIGNMENT. */
21743 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
21744 int align, int desired_alignment)
21746 if (align <= 1 && desired_alignment > 1)
21748 rtx label = ix86_expand_aligntest (destptr, 1, false);
21749 destmem = change_address (destmem, QImode, destptr);
21750 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
21751 ix86_adjust_counter (count, 1);
21752 emit_label (label);
21753 LABEL_NUSES (label) = 1;
21755 if (align <= 2 && desired_alignment > 2)
21757 rtx label = ix86_expand_aligntest (destptr, 2, false);
21758 destmem = change_address (destmem, HImode, destptr);
21759 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
21760 ix86_adjust_counter (count, 2);
21761 emit_label (label);
21762 LABEL_NUSES (label) = 1;
21764 if (align <= 4 && desired_alignment > 4)
21766 rtx label = ix86_expand_aligntest (destptr, 4, false);
21767 destmem = change_address (destmem, SImode, destptr);
21768 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
21769 ix86_adjust_counter (count, 4);
21770 emit_label (label);
21771 LABEL_NUSES (label) = 1;
21773 gcc_assert (desired_alignment <= 8);
21776 /* Set enough from DST to align DST known to by aligned by ALIGN to
21777 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
21779 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
21780 int desired_align, int align_bytes)
21783 rtx orig_dst = dst;
21784 if (align_bytes & 1)
21786 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
21788 emit_insn (gen_strset (destreg, dst,
21789 gen_lowpart (QImode, value)));
21791 if (align_bytes & 2)
21793 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
21794 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
21795 set_mem_align (dst, 2 * BITS_PER_UNIT);
21797 emit_insn (gen_strset (destreg, dst,
21798 gen_lowpart (HImode, value)));
21800 if (align_bytes & 4)
21802 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
21803 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
21804 set_mem_align (dst, 4 * BITS_PER_UNIT);
21806 emit_insn (gen_strset (destreg, dst,
21807 gen_lowpart (SImode, value)));
21809 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
21810 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
21811 set_mem_align (dst, desired_align * BITS_PER_UNIT);
21812 if (MEM_SIZE_KNOWN_P (orig_dst))
21813 set_mem_size (dst, MEM_SIZE (orig_dst) - align_bytes);
21817 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
21818 static enum stringop_alg
21819 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
21820 int *dynamic_check)
21822 const struct stringop_algs * algs;
21823 bool optimize_for_speed;
21824 /* Algorithms using the rep prefix want at least edi and ecx;
21825 additionally, memset wants eax and memcpy wants esi. Don't
21826 consider such algorithms if the user has appropriated those
21827 registers for their own purposes. */
21828 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
21830 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
21832 #define ALG_USABLE_P(alg) (rep_prefix_usable \
21833 || (alg != rep_prefix_1_byte \
21834 && alg != rep_prefix_4_byte \
21835 && alg != rep_prefix_8_byte))
21836 const struct processor_costs *cost;
21838 /* Even if the string operation call is cold, we still might spend a lot
21839 of time processing large blocks. */
21840 if (optimize_function_for_size_p (cfun)
21841 || (optimize_insn_for_size_p ()
21842 && expected_size != -1 && expected_size < 256))
21843 optimize_for_speed = false;
21845 optimize_for_speed = true;
21847 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
21849 *dynamic_check = -1;
21851 algs = &cost->memset[TARGET_64BIT != 0];
21853 algs = &cost->memcpy[TARGET_64BIT != 0];
21854 if (ix86_stringop_alg != no_stringop && ALG_USABLE_P (ix86_stringop_alg))
21855 return ix86_stringop_alg;
21856 /* rep; movq or rep; movl is the smallest variant. */
21857 else if (!optimize_for_speed)
21859 if (!count || (count & 3))
21860 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
21862 return rep_prefix_usable ? rep_prefix_4_byte : loop;
21864 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
21866 else if (expected_size != -1 && expected_size < 4)
21867 return loop_1_byte;
21868 else if (expected_size != -1)
21871 enum stringop_alg alg = libcall;
21872 for (i = 0; i < MAX_STRINGOP_ALGS; i++)
21874 /* We get here if the algorithms that were not libcall-based
21875 were rep-prefix based and we are unable to use rep prefixes
21876 based on global register usage. Break out of the loop and
21877 use the heuristic below. */
21878 if (algs->size[i].max == 0)
21880 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
21882 enum stringop_alg candidate = algs->size[i].alg;
21884 if (candidate != libcall && ALG_USABLE_P (candidate))
21886 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
21887 last non-libcall inline algorithm. */
21888 if (TARGET_INLINE_ALL_STRINGOPS)
21890 /* When the current size is best to be copied by a libcall,
21891 but we are still forced to inline, run the heuristic below
21892 that will pick code for medium sized blocks. */
21893 if (alg != libcall)
21897 else if (ALG_USABLE_P (candidate))
21901 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
21903 /* When asked to inline the call anyway, try to pick meaningful choice.
21904 We look for maximal size of block that is faster to copy by hand and
21905 take blocks of at most of that size guessing that average size will
21906 be roughly half of the block.
21908 If this turns out to be bad, we might simply specify the preferred
21909 choice in ix86_costs. */
21910 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
21911 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
21914 enum stringop_alg alg;
21916 bool any_alg_usable_p = true;
21918 for (i = 0; i < MAX_STRINGOP_ALGS; i++)
21920 enum stringop_alg candidate = algs->size[i].alg;
21921 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
21923 if (candidate != libcall && candidate
21924 && ALG_USABLE_P (candidate))
21925 max = algs->size[i].max;
21927 /* If there aren't any usable algorithms, then recursing on
21928 smaller sizes isn't going to find anything. Just return the
21929 simple byte-at-a-time copy loop. */
21930 if (!any_alg_usable_p)
21932 /* Pick something reasonable. */
21933 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
21934 *dynamic_check = 128;
21935 return loop_1_byte;
21939 alg = decide_alg (count, max / 2, memset, dynamic_check);
21940 gcc_assert (*dynamic_check == -1);
21941 gcc_assert (alg != libcall);
21942 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
21943 *dynamic_check = max;
21946 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
21947 #undef ALG_USABLE_P
21950 /* Decide on alignment. We know that the operand is already aligned to ALIGN
21951 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
21953 decide_alignment (int align,
21954 enum stringop_alg alg,
21957 int desired_align = 0;
21961 gcc_unreachable ();
21963 case unrolled_loop:
21964 desired_align = GET_MODE_SIZE (Pmode);
21966 case rep_prefix_8_byte:
21969 case rep_prefix_4_byte:
21970 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
21971 copying whole cacheline at once. */
21972 if (TARGET_PENTIUMPRO)
21977 case rep_prefix_1_byte:
21978 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
21979 copying whole cacheline at once. */
21980 if (TARGET_PENTIUMPRO)
21994 if (desired_align < align)
21995 desired_align = align;
21996 if (expected_size != -1 && expected_size < 4)
21997 desired_align = align;
21998 return desired_align;
22001 /* Return the smallest power of 2 greater than VAL. */
22003 smallest_pow2_greater_than (int val)
22011 /* Expand string move (memcpy) operation. Use i386 string operations
22012 when profitable. expand_setmem contains similar code. The code
22013 depends upon architecture, block size and alignment, but always has
22014 the same overall structure:
22016 1) Prologue guard: Conditional that jumps up to epilogues for small
22017 blocks that can be handled by epilogue alone. This is faster
22018 but also needed for correctness, since prologue assume the block
22019 is larger than the desired alignment.
22021 Optional dynamic check for size and libcall for large
22022 blocks is emitted here too, with -minline-stringops-dynamically.
22024 2) Prologue: copy first few bytes in order to get destination
22025 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22026 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22027 copied. We emit either a jump tree on power of two sized
22028 blocks, or a byte loop.
22030 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22031 with specified algorithm.
22033 4) Epilogue: code copying tail of the block that is too small to be
22034 handled by main body (or up to size guarded by prologue guard). */
22037 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
22038 rtx expected_align_exp, rtx expected_size_exp)
22044 rtx jump_around_label = NULL;
22045 HOST_WIDE_INT align = 1;
22046 unsigned HOST_WIDE_INT count = 0;
22047 HOST_WIDE_INT expected_size = -1;
22048 int size_needed = 0, epilogue_size_needed;
22049 int desired_align = 0, align_bytes = 0;
22050 enum stringop_alg alg;
22052 bool need_zero_guard = false;
22054 if (CONST_INT_P (align_exp))
22055 align = INTVAL (align_exp);
22056 /* i386 can do misaligned access on reasonably increased cost. */
22057 if (CONST_INT_P (expected_align_exp)
22058 && INTVAL (expected_align_exp) > align)
22059 align = INTVAL (expected_align_exp);
22060 /* ALIGN is the minimum of destination and source alignment, but we care here
22061 just about destination alignment. */
22062 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
22063 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
22065 if (CONST_INT_P (count_exp))
22066 count = expected_size = INTVAL (count_exp);
22067 if (CONST_INT_P (expected_size_exp) && count == 0)
22068 expected_size = INTVAL (expected_size_exp);
22070 /* Make sure we don't need to care about overflow later on. */
22071 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
22074 /* Step 0: Decide on preferred algorithm, desired alignment and
22075 size of chunks to be copied by main loop. */
22077 alg = decide_alg (count, expected_size, false, &dynamic_check);
22078 desired_align = decide_alignment (align, alg, expected_size);
22080 if (!TARGET_ALIGN_STRINGOPS)
22081 align = desired_align;
22083 if (alg == libcall)
22085 gcc_assert (alg != no_stringop);
22087 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
22088 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
22089 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
22094 gcc_unreachable ();
22096 need_zero_guard = true;
22097 size_needed = GET_MODE_SIZE (Pmode);
22099 case unrolled_loop:
22100 need_zero_guard = true;
22101 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
22103 case rep_prefix_8_byte:
22106 case rep_prefix_4_byte:
22109 case rep_prefix_1_byte:
22113 need_zero_guard = true;
22118 epilogue_size_needed = size_needed;
22120 /* Step 1: Prologue guard. */
22122 /* Alignment code needs count to be in register. */
22123 if (CONST_INT_P (count_exp) && desired_align > align)
22125 if (INTVAL (count_exp) > desired_align
22126 && INTVAL (count_exp) > size_needed)
22129 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
22130 if (align_bytes <= 0)
22133 align_bytes = desired_align - align_bytes;
22135 if (align_bytes == 0)
22136 count_exp = force_reg (counter_mode (count_exp), count_exp);
22138 gcc_assert (desired_align >= 1 && align >= 1);
22140 /* Ensure that alignment prologue won't copy past end of block. */
22141 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
22143 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
22144 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22145 Make sure it is power of 2. */
22146 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
22150 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
22152 /* If main algorithm works on QImode, no epilogue is needed.
22153 For small sizes just don't align anything. */
22154 if (size_needed == 1)
22155 desired_align = align;
22162 label = gen_label_rtx ();
22163 emit_cmp_and_jump_insns (count_exp,
22164 GEN_INT (epilogue_size_needed),
22165 LTU, 0, counter_mode (count_exp), 1, label);
22166 if (expected_size == -1 || expected_size < epilogue_size_needed)
22167 predict_jump (REG_BR_PROB_BASE * 60 / 100);
22169 predict_jump (REG_BR_PROB_BASE * 20 / 100);
22173 /* Emit code to decide on runtime whether library call or inline should be
22175 if (dynamic_check != -1)
22177 if (CONST_INT_P (count_exp))
22179 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
22181 emit_block_move_via_libcall (dst, src, count_exp, false);
22182 count_exp = const0_rtx;
22188 rtx hot_label = gen_label_rtx ();
22189 jump_around_label = gen_label_rtx ();
22190 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
22191 LEU, 0, GET_MODE (count_exp), 1, hot_label);
22192 predict_jump (REG_BR_PROB_BASE * 90 / 100);
22193 emit_block_move_via_libcall (dst, src, count_exp, false);
22194 emit_jump (jump_around_label);
22195 emit_label (hot_label);
22199 /* Step 2: Alignment prologue. */
22201 if (desired_align > align)
22203 if (align_bytes == 0)
22205 /* Except for the first move in epilogue, we no longer know
22206 constant offset in aliasing info. It don't seems to worth
22207 the pain to maintain it for the first move, so throw away
22209 src = change_address (src, BLKmode, srcreg);
22210 dst = change_address (dst, BLKmode, destreg);
22211 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
22216 /* If we know how many bytes need to be stored before dst is
22217 sufficiently aligned, maintain aliasing info accurately. */
22218 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
22219 desired_align, align_bytes);
22220 count_exp = plus_constant (count_exp, -align_bytes);
22221 count -= align_bytes;
22223 if (need_zero_guard
22224 && (count < (unsigned HOST_WIDE_INT) size_needed
22225 || (align_bytes == 0
22226 && count < ((unsigned HOST_WIDE_INT) size_needed
22227 + desired_align - align))))
22229 /* It is possible that we copied enough so the main loop will not
22231 gcc_assert (size_needed > 1);
22232 if (label == NULL_RTX)
22233 label = gen_label_rtx ();
22234 emit_cmp_and_jump_insns (count_exp,
22235 GEN_INT (size_needed),
22236 LTU, 0, counter_mode (count_exp), 1, label);
22237 if (expected_size == -1
22238 || expected_size < (desired_align - align) / 2 + size_needed)
22239 predict_jump (REG_BR_PROB_BASE * 20 / 100);
22241 predict_jump (REG_BR_PROB_BASE * 60 / 100);
22244 if (label && size_needed == 1)
22246 emit_label (label);
22247 LABEL_NUSES (label) = 1;
22249 epilogue_size_needed = 1;
22251 else if (label == NULL_RTX)
22252 epilogue_size_needed = size_needed;
22254 /* Step 3: Main loop. */
22260 gcc_unreachable ();
22262 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
22263 count_exp, QImode, 1, expected_size);
22266 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
22267 count_exp, Pmode, 1, expected_size);
22269 case unrolled_loop:
22270 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22271 registers for 4 temporaries anyway. */
22272 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
22273 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
22276 case rep_prefix_8_byte:
22277 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
22280 case rep_prefix_4_byte:
22281 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
22284 case rep_prefix_1_byte:
22285 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
22289 /* Adjust properly the offset of src and dest memory for aliasing. */
22290 if (CONST_INT_P (count_exp))
22292 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
22293 (count / size_needed) * size_needed);
22294 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
22295 (count / size_needed) * size_needed);
22299 src = change_address (src, BLKmode, srcreg);
22300 dst = change_address (dst, BLKmode, destreg);
22303 /* Step 4: Epilogue to copy the remaining bytes. */
22307 /* When the main loop is done, COUNT_EXP might hold original count,
22308 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22309 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22310 bytes. Compensate if needed. */
22312 if (size_needed < epilogue_size_needed)
22315 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
22316 GEN_INT (size_needed - 1), count_exp, 1,
22318 if (tmp != count_exp)
22319 emit_move_insn (count_exp, tmp);
22321 emit_label (label);
22322 LABEL_NUSES (label) = 1;
22325 if (count_exp != const0_rtx && epilogue_size_needed > 1)
22326 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
22327 epilogue_size_needed);
22328 if (jump_around_label)
22329 emit_label (jump_around_label);
22333 /* Helper function for memcpy. For QImode value 0xXY produce
22334 0xXYXYXYXY of wide specified by MODE. This is essentially
22335 a * 0x10101010, but we can do slightly better than
22336 synth_mult by unwinding the sequence by hand on CPUs with
22339 promote_duplicated_reg (enum machine_mode mode, rtx val)
22341 enum machine_mode valmode = GET_MODE (val);
22343 int nops = mode == DImode ? 3 : 2;
22345 gcc_assert (mode == SImode || mode == DImode);
22346 if (val == const0_rtx)
22347 return copy_to_mode_reg (mode, const0_rtx);
22348 if (CONST_INT_P (val))
22350 HOST_WIDE_INT v = INTVAL (val) & 255;
22354 if (mode == DImode)
22355 v |= (v << 16) << 16;
22356 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
22359 if (valmode == VOIDmode)
22361 if (valmode != QImode)
22362 val = gen_lowpart (QImode, val);
22363 if (mode == QImode)
22365 if (!TARGET_PARTIAL_REG_STALL)
22367 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
22368 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
22369 <= (ix86_cost->shift_const + ix86_cost->add) * nops
22370 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
22372 rtx reg = convert_modes (mode, QImode, val, true);
22373 tmp = promote_duplicated_reg (mode, const1_rtx);
22374 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
22379 rtx reg = convert_modes (mode, QImode, val, true);
22381 if (!TARGET_PARTIAL_REG_STALL)
22382 if (mode == SImode)
22383 emit_insn (gen_movsi_insv_1 (reg, reg));
22385 emit_insn (gen_movdi_insv_1 (reg, reg));
22388 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
22389 NULL, 1, OPTAB_DIRECT);
22391 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
22393 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
22394 NULL, 1, OPTAB_DIRECT);
22395 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
22396 if (mode == SImode)
22398 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
22399 NULL, 1, OPTAB_DIRECT);
22400 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
22405 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
22406 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
22407 alignment from ALIGN to DESIRED_ALIGN. */
22409 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
22414 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
22415 promoted_val = promote_duplicated_reg (DImode, val);
22416 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
22417 promoted_val = promote_duplicated_reg (SImode, val);
22418 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
22419 promoted_val = promote_duplicated_reg (HImode, val);
22421 promoted_val = val;
22423 return promoted_val;
22426 /* Expand string clear operation (bzero). Use i386 string operations when
22427 profitable. See expand_movmem comment for explanation of individual
22428 steps performed. */
22430 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
22431 rtx expected_align_exp, rtx expected_size_exp)
22436 rtx jump_around_label = NULL;
22437 HOST_WIDE_INT align = 1;
22438 unsigned HOST_WIDE_INT count = 0;
22439 HOST_WIDE_INT expected_size = -1;
22440 int size_needed = 0, epilogue_size_needed;
22441 int desired_align = 0, align_bytes = 0;
22442 enum stringop_alg alg;
22443 rtx promoted_val = NULL;
22444 bool force_loopy_epilogue = false;
22446 bool need_zero_guard = false;
22448 if (CONST_INT_P (align_exp))
22449 align = INTVAL (align_exp);
22450 /* i386 can do misaligned access on reasonably increased cost. */
22451 if (CONST_INT_P (expected_align_exp)
22452 && INTVAL (expected_align_exp) > align)
22453 align = INTVAL (expected_align_exp);
22454 if (CONST_INT_P (count_exp))
22455 count = expected_size = INTVAL (count_exp);
22456 if (CONST_INT_P (expected_size_exp) && count == 0)
22457 expected_size = INTVAL (expected_size_exp);
22459 /* Make sure we don't need to care about overflow later on. */
22460 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
22463 /* Step 0: Decide on preferred algorithm, desired alignment and
22464 size of chunks to be copied by main loop. */
22466 alg = decide_alg (count, expected_size, true, &dynamic_check);
22467 desired_align = decide_alignment (align, alg, expected_size);
22469 if (!TARGET_ALIGN_STRINGOPS)
22470 align = desired_align;
22472 if (alg == libcall)
22474 gcc_assert (alg != no_stringop);
22476 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
22477 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
22482 gcc_unreachable ();
22484 need_zero_guard = true;
22485 size_needed = GET_MODE_SIZE (Pmode);
22487 case unrolled_loop:
22488 need_zero_guard = true;
22489 size_needed = GET_MODE_SIZE (Pmode) * 4;
22491 case rep_prefix_8_byte:
22494 case rep_prefix_4_byte:
22497 case rep_prefix_1_byte:
22501 need_zero_guard = true;
22505 epilogue_size_needed = size_needed;
22507 /* Step 1: Prologue guard. */
22509 /* Alignment code needs count to be in register. */
22510 if (CONST_INT_P (count_exp) && desired_align > align)
22512 if (INTVAL (count_exp) > desired_align
22513 && INTVAL (count_exp) > size_needed)
22516 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
22517 if (align_bytes <= 0)
22520 align_bytes = desired_align - align_bytes;
22522 if (align_bytes == 0)
22524 enum machine_mode mode = SImode;
22525 if (TARGET_64BIT && (count & ~0xffffffff))
22527 count_exp = force_reg (mode, count_exp);
22530 /* Do the cheap promotion to allow better CSE across the
22531 main loop and epilogue (ie one load of the big constant in the
22532 front of all code. */
22533 if (CONST_INT_P (val_exp))
22534 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
22535 desired_align, align);
22536 /* Ensure that alignment prologue won't copy past end of block. */
22537 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
22539 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
22540 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
22541 Make sure it is power of 2. */
22542 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
22544 /* To improve performance of small blocks, we jump around the VAL
22545 promoting mode. This mean that if the promoted VAL is not constant,
22546 we might not use it in the epilogue and have to use byte
22548 if (epilogue_size_needed > 2 && !promoted_val)
22549 force_loopy_epilogue = true;
22552 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
22554 /* If main algorithm works on QImode, no epilogue is needed.
22555 For small sizes just don't align anything. */
22556 if (size_needed == 1)
22557 desired_align = align;
22564 label = gen_label_rtx ();
22565 emit_cmp_and_jump_insns (count_exp,
22566 GEN_INT (epilogue_size_needed),
22567 LTU, 0, counter_mode (count_exp), 1, label);
22568 if (expected_size == -1 || expected_size <= epilogue_size_needed)
22569 predict_jump (REG_BR_PROB_BASE * 60 / 100);
22571 predict_jump (REG_BR_PROB_BASE * 20 / 100);
22574 if (dynamic_check != -1)
22576 rtx hot_label = gen_label_rtx ();
22577 jump_around_label = gen_label_rtx ();
22578 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
22579 LEU, 0, counter_mode (count_exp), 1, hot_label);
22580 predict_jump (REG_BR_PROB_BASE * 90 / 100);
22581 set_storage_via_libcall (dst, count_exp, val_exp, false);
22582 emit_jump (jump_around_label);
22583 emit_label (hot_label);
22586 /* Step 2: Alignment prologue. */
22588 /* Do the expensive promotion once we branched off the small blocks. */
22590 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
22591 desired_align, align);
22592 gcc_assert (desired_align >= 1 && align >= 1);
22594 if (desired_align > align)
22596 if (align_bytes == 0)
22598 /* Except for the first move in epilogue, we no longer know
22599 constant offset in aliasing info. It don't seems to worth
22600 the pain to maintain it for the first move, so throw away
22602 dst = change_address (dst, BLKmode, destreg);
22603 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
22608 /* If we know how many bytes need to be stored before dst is
22609 sufficiently aligned, maintain aliasing info accurately. */
22610 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
22611 desired_align, align_bytes);
22612 count_exp = plus_constant (count_exp, -align_bytes);
22613 count -= align_bytes;
22615 if (need_zero_guard
22616 && (count < (unsigned HOST_WIDE_INT) size_needed
22617 || (align_bytes == 0
22618 && count < ((unsigned HOST_WIDE_INT) size_needed
22619 + desired_align - align))))
22621 /* It is possible that we copied enough so the main loop will not
22623 gcc_assert (size_needed > 1);
22624 if (label == NULL_RTX)
22625 label = gen_label_rtx ();
22626 emit_cmp_and_jump_insns (count_exp,
22627 GEN_INT (size_needed),
22628 LTU, 0, counter_mode (count_exp), 1, label);
22629 if (expected_size == -1
22630 || expected_size < (desired_align - align) / 2 + size_needed)
22631 predict_jump (REG_BR_PROB_BASE * 20 / 100);
22633 predict_jump (REG_BR_PROB_BASE * 60 / 100);
22636 if (label && size_needed == 1)
22638 emit_label (label);
22639 LABEL_NUSES (label) = 1;
22641 promoted_val = val_exp;
22642 epilogue_size_needed = 1;
22644 else if (label == NULL_RTX)
22645 epilogue_size_needed = size_needed;
22647 /* Step 3: Main loop. */
22653 gcc_unreachable ();
22655 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
22656 count_exp, QImode, 1, expected_size);
22659 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
22660 count_exp, Pmode, 1, expected_size);
22662 case unrolled_loop:
22663 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
22664 count_exp, Pmode, 4, expected_size);
22666 case rep_prefix_8_byte:
22667 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
22670 case rep_prefix_4_byte:
22671 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
22674 case rep_prefix_1_byte:
22675 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
22679 /* Adjust properly the offset of src and dest memory for aliasing. */
22680 if (CONST_INT_P (count_exp))
22681 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
22682 (count / size_needed) * size_needed);
22684 dst = change_address (dst, BLKmode, destreg);
22686 /* Step 4: Epilogue to copy the remaining bytes. */
22690 /* When the main loop is done, COUNT_EXP might hold original count,
22691 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22692 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22693 bytes. Compensate if needed. */
22695 if (size_needed < epilogue_size_needed)
22698 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
22699 GEN_INT (size_needed - 1), count_exp, 1,
22701 if (tmp != count_exp)
22702 emit_move_insn (count_exp, tmp);
22704 emit_label (label);
22705 LABEL_NUSES (label) = 1;
22708 if (count_exp != const0_rtx && epilogue_size_needed > 1)
22710 if (force_loopy_epilogue)
22711 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
22712 epilogue_size_needed);
22714 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
22715 epilogue_size_needed);
22717 if (jump_around_label)
22718 emit_label (jump_around_label);
22722 /* Expand the appropriate insns for doing strlen if not just doing
22725 out = result, initialized with the start address
22726 align_rtx = alignment of the address.
22727 scratch = scratch register, initialized with the startaddress when
22728 not aligned, otherwise undefined
22730 This is just the body. It needs the initializations mentioned above and
22731 some address computing at the end. These things are done in i386.md. */
22734 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
22738 rtx align_2_label = NULL_RTX;
22739 rtx align_3_label = NULL_RTX;
22740 rtx align_4_label = gen_label_rtx ();
22741 rtx end_0_label = gen_label_rtx ();
22743 rtx tmpreg = gen_reg_rtx (SImode);
22744 rtx scratch = gen_reg_rtx (SImode);
22748 if (CONST_INT_P (align_rtx))
22749 align = INTVAL (align_rtx);
22751 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
22753 /* Is there a known alignment and is it less than 4? */
22756 rtx scratch1 = gen_reg_rtx (Pmode);
22757 emit_move_insn (scratch1, out);
22758 /* Is there a known alignment and is it not 2? */
22761 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
22762 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
22764 /* Leave just the 3 lower bits. */
22765 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
22766 NULL_RTX, 0, OPTAB_WIDEN);
22768 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
22769 Pmode, 1, align_4_label);
22770 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
22771 Pmode, 1, align_2_label);
22772 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
22773 Pmode, 1, align_3_label);
22777 /* Since the alignment is 2, we have to check 2 or 0 bytes;
22778 check if is aligned to 4 - byte. */
22780 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
22781 NULL_RTX, 0, OPTAB_WIDEN);
22783 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
22784 Pmode, 1, align_4_label);
22787 mem = change_address (src, QImode, out);
22789 /* Now compare the bytes. */
22791 /* Compare the first n unaligned byte on a byte per byte basis. */
22792 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
22793 QImode, 1, end_0_label);
22795 /* Increment the address. */
22796 emit_insn (ix86_gen_add3 (out, out, const1_rtx));
22798 /* Not needed with an alignment of 2 */
22801 emit_label (align_2_label);
22803 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
22806 emit_insn (ix86_gen_add3 (out, out, const1_rtx));
22808 emit_label (align_3_label);
22811 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
22814 emit_insn (ix86_gen_add3 (out, out, const1_rtx));
22817 /* Generate loop to check 4 bytes at a time. It is not a good idea to
22818 align this loop. It gives only huge programs, but does not help to
22820 emit_label (align_4_label);
22822 mem = change_address (src, SImode, out);
22823 emit_move_insn (scratch, mem);
22824 emit_insn (ix86_gen_add3 (out, out, GEN_INT (4)));
22826 /* This formula yields a nonzero result iff one of the bytes is zero.
22827 This saves three branches inside loop and many cycles. */
22829 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
22830 emit_insn (gen_one_cmplsi2 (scratch, scratch));
22831 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
22832 emit_insn (gen_andsi3 (tmpreg, tmpreg,
22833 gen_int_mode (0x80808080, SImode)));
22834 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
22839 rtx reg = gen_reg_rtx (SImode);
22840 rtx reg2 = gen_reg_rtx (Pmode);
22841 emit_move_insn (reg, tmpreg);
22842 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
22844 /* If zero is not in the first two bytes, move two bytes forward. */
22845 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
22846 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
22847 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
22848 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
22849 gen_rtx_IF_THEN_ELSE (SImode, tmp,
22852 /* Emit lea manually to avoid clobbering of flags. */
22853 emit_insn (gen_rtx_SET (SImode, reg2,
22854 gen_rtx_PLUS (Pmode, out, const2_rtx)));
22856 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
22857 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
22858 emit_insn (gen_rtx_SET (VOIDmode, out,
22859 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
22865 rtx end_2_label = gen_label_rtx ();
22866 /* Is zero in the first two bytes? */
22868 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
22869 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
22870 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
22871 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
22872 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
22874 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
22875 JUMP_LABEL (tmp) = end_2_label;
22877 /* Not in the first two. Move two bytes forward. */
22878 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
22879 emit_insn (ix86_gen_add3 (out, out, const2_rtx));
22881 emit_label (end_2_label);
22885 /* Avoid branch in fixing the byte. */
22886 tmpreg = gen_lowpart (QImode, tmpreg);
22887 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
22888 tmp = gen_rtx_REG (CCmode, FLAGS_REG);
22889 cmp = gen_rtx_LTU (VOIDmode, tmp, const0_rtx);
22890 emit_insn (ix86_gen_sub3_carry (out, out, GEN_INT (3), tmp, cmp));
22892 emit_label (end_0_label);
22895 /* Expand strlen. */
22898 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
22900 rtx addr, scratch1, scratch2, scratch3, scratch4;
22902 /* The generic case of strlen expander is long. Avoid it's
22903 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
22905 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
22906 && !TARGET_INLINE_ALL_STRINGOPS
22907 && !optimize_insn_for_size_p ()
22908 && (!CONST_INT_P (align) || INTVAL (align) < 4))
22911 addr = force_reg (Pmode, XEXP (src, 0));
22912 scratch1 = gen_reg_rtx (Pmode);
22914 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
22915 && !optimize_insn_for_size_p ())
22917 /* Well it seems that some optimizer does not combine a call like
22918 foo(strlen(bar), strlen(bar));
22919 when the move and the subtraction is done here. It does calculate
22920 the length just once when these instructions are done inside of
22921 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
22922 often used and I use one fewer register for the lifetime of
22923 output_strlen_unroll() this is better. */
22925 emit_move_insn (out, addr);
22927 ix86_expand_strlensi_unroll_1 (out, src, align);
22929 /* strlensi_unroll_1 returns the address of the zero at the end of
22930 the string, like memchr(), so compute the length by subtracting
22931 the start address. */
22932 emit_insn (ix86_gen_sub3 (out, out, addr));
22938 /* Can't use this if the user has appropriated eax, ecx, or edi. */
22939 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
22942 scratch2 = gen_reg_rtx (Pmode);
22943 scratch3 = gen_reg_rtx (Pmode);
22944 scratch4 = force_reg (Pmode, constm1_rtx);
22946 emit_move_insn (scratch3, addr);
22947 eoschar = force_reg (QImode, eoschar);
22949 src = replace_equiv_address_nv (src, scratch3);
22951 /* If .md starts supporting :P, this can be done in .md. */
22952 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
22953 scratch4), UNSPEC_SCAS);
22954 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
22955 emit_insn (ix86_gen_one_cmpl2 (scratch2, scratch1));
22956 emit_insn (ix86_gen_add3 (out, scratch2, constm1_rtx));
22961 /* For given symbol (function) construct code to compute address of it's PLT
22962 entry in large x86-64 PIC model. */
22964 construct_plt_address (rtx symbol)
22966 rtx tmp = gen_reg_rtx (Pmode);
22967 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
22969 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
22970 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
22972 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
22973 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
22978 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
22980 rtx pop, bool sibcall)
22982 /* We need to represent that SI and DI registers are clobbered
22984 static int clobbered_registers[] = {
22985 XMM6_REG, XMM7_REG, XMM8_REG,
22986 XMM9_REG, XMM10_REG, XMM11_REG,
22987 XMM12_REG, XMM13_REG, XMM14_REG,
22988 XMM15_REG, SI_REG, DI_REG
22990 rtx vec[ARRAY_SIZE (clobbered_registers) + 3];
22991 rtx use = NULL, call;
22992 unsigned int vec_len;
22994 if (pop == const0_rtx)
22996 gcc_assert (!TARGET_64BIT || !pop);
22998 if (TARGET_MACHO && !TARGET_64BIT)
23001 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
23002 fnaddr = machopic_indirect_call_target (fnaddr);
23007 /* Static functions and indirect calls don't need the pic register. */
23008 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
23009 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
23010 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
23011 use_reg (&use, pic_offset_table_rtx);
23014 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
23016 rtx al = gen_rtx_REG (QImode, AX_REG);
23017 emit_move_insn (al, callarg2);
23018 use_reg (&use, al);
23021 if (ix86_cmodel == CM_LARGE_PIC
23023 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
23024 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
23025 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
23027 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
23028 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
23030 fnaddr = XEXP (fnaddr, 0);
23031 if (GET_MODE (fnaddr) != Pmode)
23032 fnaddr = convert_to_mode (Pmode, fnaddr, 1);
23033 fnaddr = gen_rtx_MEM (QImode, copy_to_mode_reg (Pmode, fnaddr));
23037 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
23039 call = gen_rtx_SET (VOIDmode, retval, call);
23040 vec[vec_len++] = call;
23044 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
23045 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
23046 vec[vec_len++] = pop;
23049 if (TARGET_64BIT_MS_ABI
23050 && (!callarg2 || INTVAL (callarg2) != -2))
23054 vec[vec_len++] = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
23055 UNSPEC_MS_TO_SYSV_CALL);
23057 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
23059 = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
23061 gen_rtx_REG (SSE_REGNO_P (clobbered_registers[i])
23063 clobbered_registers[i]));
23066 /* Add UNSPEC_CALL_NEEDS_VZEROUPPER decoration. */
23067 if (TARGET_VZEROUPPER)
23070 if (cfun->machine->callee_pass_avx256_p)
23072 if (cfun->machine->callee_return_avx256_p)
23073 avx256 = callee_return_pass_avx256;
23075 avx256 = callee_pass_avx256;
23077 else if (cfun->machine->callee_return_avx256_p)
23078 avx256 = callee_return_avx256;
23080 avx256 = call_no_avx256;
23082 if (reload_completed)
23083 emit_insn (gen_avx_vzeroupper (GEN_INT (avx256)));
23085 vec[vec_len++] = gen_rtx_UNSPEC (VOIDmode,
23086 gen_rtvec (1, GEN_INT (avx256)),
23087 UNSPEC_CALL_NEEDS_VZEROUPPER);
23091 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (vec_len, vec));
23092 call = emit_call_insn (call);
23094 CALL_INSN_FUNCTION_USAGE (call) = use;
23100 ix86_split_call_vzeroupper (rtx insn, rtx vzeroupper)
23102 rtx pat = PATTERN (insn);
23103 rtvec vec = XVEC (pat, 0);
23104 int len = GET_NUM_ELEM (vec) - 1;
23106 /* Strip off the last entry of the parallel. */
23107 gcc_assert (GET_CODE (RTVEC_ELT (vec, len)) == UNSPEC);
23108 gcc_assert (XINT (RTVEC_ELT (vec, len), 1) == UNSPEC_CALL_NEEDS_VZEROUPPER);
23110 pat = RTVEC_ELT (vec, 0);
23112 pat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (len, &RTVEC_ELT (vec, 0)));
23114 emit_insn (gen_avx_vzeroupper (vzeroupper));
23115 emit_call_insn (pat);
23118 /* Output the assembly for a call instruction. */
23121 ix86_output_call_insn (rtx insn, rtx call_op)
23123 bool direct_p = constant_call_address_operand (call_op, Pmode);
23124 bool seh_nop_p = false;
23127 if (SIBLING_CALL_P (insn))
23131 /* SEH epilogue detection requires the indirect branch case
23132 to include REX.W. */
23133 else if (TARGET_SEH)
23134 xasm = "rex.W jmp %A0";
23138 output_asm_insn (xasm, &call_op);
23142 /* SEH unwinding can require an extra nop to be emitted in several
23143 circumstances. Determine if we have one of those. */
23148 for (i = NEXT_INSN (insn); i ; i = NEXT_INSN (i))
23150 /* If we get to another real insn, we don't need the nop. */
23154 /* If we get to the epilogue note, prevent a catch region from
23155 being adjacent to the standard epilogue sequence. If non-
23156 call-exceptions, we'll have done this during epilogue emission. */
23157 if (NOTE_P (i) && NOTE_KIND (i) == NOTE_INSN_EPILOGUE_BEG
23158 && !flag_non_call_exceptions
23159 && !can_throw_internal (insn))
23166 /* If we didn't find a real insn following the call, prevent the
23167 unwinder from looking into the next function. */
23173 xasm = "call\t%P0";
23175 xasm = "call\t%A0";
23177 output_asm_insn (xasm, &call_op);
23185 /* Clear stack slot assignments remembered from previous functions.
23186 This is called from INIT_EXPANDERS once before RTL is emitted for each
23189 static struct machine_function *
23190 ix86_init_machine_status (void)
23192 struct machine_function *f;
23194 f = ggc_alloc_cleared_machine_function ();
23195 f->use_fast_prologue_epilogue_nregs = -1;
23196 f->tls_descriptor_call_expanded_p = 0;
23197 f->call_abi = ix86_abi;
23202 /* Return a MEM corresponding to a stack slot with mode MODE.
23203 Allocate a new slot if necessary.
23205 The RTL for a function can have several slots available: N is
23206 which slot to use. */
23209 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
23211 struct stack_local_entry *s;
23213 gcc_assert (n < MAX_386_STACK_LOCALS);
23215 /* Virtual slot is valid only before vregs are instantiated. */
23216 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
23218 for (s = ix86_stack_locals; s; s = s->next)
23219 if (s->mode == mode && s->n == n)
23220 return validize_mem (copy_rtx (s->rtl));
23222 s = ggc_alloc_stack_local_entry ();
23225 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
23227 s->next = ix86_stack_locals;
23228 ix86_stack_locals = s;
23229 return validize_mem (s->rtl);
23232 /* Calculate the length of the memory address in the instruction encoding.
23233 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23234 or other prefixes. */
23237 memory_address_length (rtx addr)
23239 struct ix86_address parts;
23240 rtx base, index, disp;
23244 if (GET_CODE (addr) == PRE_DEC
23245 || GET_CODE (addr) == POST_INC
23246 || GET_CODE (addr) == PRE_MODIFY
23247 || GET_CODE (addr) == POST_MODIFY)
23250 ok = ix86_decompose_address (addr, &parts);
23253 if (parts.base && GET_CODE (parts.base) == SUBREG)
23254 parts.base = SUBREG_REG (parts.base);
23255 if (parts.index && GET_CODE (parts.index) == SUBREG)
23256 parts.index = SUBREG_REG (parts.index);
23259 index = parts.index;
23262 /* Add length of addr32 prefix. */
23263 len = (GET_CODE (addr) == ZERO_EXTEND
23264 || GET_CODE (addr) == AND);
23267 - esp as the base always wants an index,
23268 - ebp as the base always wants a displacement,
23269 - r12 as the base always wants an index,
23270 - r13 as the base always wants a displacement. */
23272 /* Register Indirect. */
23273 if (base && !index && !disp)
23275 /* esp (for its index) and ebp (for its displacement) need
23276 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23279 && (addr == arg_pointer_rtx
23280 || addr == frame_pointer_rtx
23281 || REGNO (addr) == SP_REG
23282 || REGNO (addr) == BP_REG
23283 || REGNO (addr) == R12_REG
23284 || REGNO (addr) == R13_REG))
23288 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23289 is not disp32, but disp32(%rip), so for disp32
23290 SIB byte is needed, unless print_operand_address
23291 optimizes it into disp32(%rip) or (%rip) is implied
23293 else if (disp && !base && !index)
23300 if (GET_CODE (disp) == CONST)
23301 symbol = XEXP (disp, 0);
23302 if (GET_CODE (symbol) == PLUS
23303 && CONST_INT_P (XEXP (symbol, 1)))
23304 symbol = XEXP (symbol, 0);
23306 if (GET_CODE (symbol) != LABEL_REF
23307 && (GET_CODE (symbol) != SYMBOL_REF
23308 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
23309 && (GET_CODE (symbol) != UNSPEC
23310 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
23311 && XINT (symbol, 1) != UNSPEC_PCREL
23312 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
23319 /* Find the length of the displacement constant. */
23322 if (base && satisfies_constraint_K (disp))
23327 /* ebp always wants a displacement. Similarly r13. */
23328 else if (base && REG_P (base)
23329 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
23332 /* An index requires the two-byte modrm form.... */
23334 /* ...like esp (or r12), which always wants an index. */
23335 || base == arg_pointer_rtx
23336 || base == frame_pointer_rtx
23337 || (base && REG_P (base)
23338 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
23355 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23356 is set, expect that insn have 8bit immediate alternative. */
23358 ix86_attr_length_immediate_default (rtx insn, bool shortform)
23362 extract_insn_cached (insn);
23363 for (i = recog_data.n_operands - 1; i >= 0; --i)
23364 if (CONSTANT_P (recog_data.operand[i]))
23366 enum attr_mode mode = get_attr_mode (insn);
23369 if (shortform && CONST_INT_P (recog_data.operand[i]))
23371 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
23378 ival = trunc_int_for_mode (ival, HImode);
23381 ival = trunc_int_for_mode (ival, SImode);
23386 if (IN_RANGE (ival, -128, 127))
23403 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
23408 fatal_insn ("unknown insn mode", insn);
23413 /* Compute default value for "length_address" attribute. */
23415 ix86_attr_length_address_default (rtx insn)
23419 if (get_attr_type (insn) == TYPE_LEA)
23421 rtx set = PATTERN (insn), addr;
23423 if (GET_CODE (set) == PARALLEL)
23424 set = XVECEXP (set, 0, 0);
23426 gcc_assert (GET_CODE (set) == SET);
23428 addr = SET_SRC (set);
23429 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
23431 if (GET_CODE (addr) == ZERO_EXTEND)
23432 addr = XEXP (addr, 0);
23433 if (GET_CODE (addr) == SUBREG)
23434 addr = SUBREG_REG (addr);
23437 return memory_address_length (addr);
23440 extract_insn_cached (insn);
23441 for (i = recog_data.n_operands - 1; i >= 0; --i)
23442 if (MEM_P (recog_data.operand[i]))
23444 constrain_operands_cached (reload_completed);
23445 if (which_alternative != -1)
23447 const char *constraints = recog_data.constraints[i];
23448 int alt = which_alternative;
23450 while (*constraints == '=' || *constraints == '+')
23453 while (*constraints++ != ',')
23455 /* Skip ignored operands. */
23456 if (*constraints == 'X')
23459 return memory_address_length (XEXP (recog_data.operand[i], 0));
23464 /* Compute default value for "length_vex" attribute. It includes
23465 2 or 3 byte VEX prefix and 1 opcode byte. */
23468 ix86_attr_length_vex_default (rtx insn, bool has_0f_opcode, bool has_vex_w)
23472 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
23473 byte VEX prefix. */
23474 if (!has_0f_opcode || has_vex_w)
23477 /* We can always use 2 byte VEX prefix in 32bit. */
23481 extract_insn_cached (insn);
23483 for (i = recog_data.n_operands - 1; i >= 0; --i)
23484 if (REG_P (recog_data.operand[i]))
23486 /* REX.W bit uses 3 byte VEX prefix. */
23487 if (GET_MODE (recog_data.operand[i]) == DImode
23488 && GENERAL_REG_P (recog_data.operand[i]))
23493 /* REX.X or REX.B bits use 3 byte VEX prefix. */
23494 if (MEM_P (recog_data.operand[i])
23495 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
23502 /* Return the maximum number of instructions a cpu can issue. */
23505 ix86_issue_rate (void)
23509 case PROCESSOR_PENTIUM:
23510 case PROCESSOR_ATOM:
23514 case PROCESSOR_PENTIUMPRO:
23515 case PROCESSOR_PENTIUM4:
23516 case PROCESSOR_CORE2_32:
23517 case PROCESSOR_CORE2_64:
23518 case PROCESSOR_COREI7_32:
23519 case PROCESSOR_COREI7_64:
23520 case PROCESSOR_ATHLON:
23522 case PROCESSOR_AMDFAM10:
23523 case PROCESSOR_NOCONA:
23524 case PROCESSOR_GENERIC32:
23525 case PROCESSOR_GENERIC64:
23526 case PROCESSOR_BDVER1:
23527 case PROCESSOR_BDVER2:
23528 case PROCESSOR_BTVER1:
23536 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
23537 by DEP_INSN and nothing set by DEP_INSN. */
23540 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
23544 /* Simplify the test for uninteresting insns. */
23545 if (insn_type != TYPE_SETCC
23546 && insn_type != TYPE_ICMOV
23547 && insn_type != TYPE_FCMOV
23548 && insn_type != TYPE_IBR)
23551 if ((set = single_set (dep_insn)) != 0)
23553 set = SET_DEST (set);
23556 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
23557 && XVECLEN (PATTERN (dep_insn), 0) == 2
23558 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
23559 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
23561 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
23562 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
23567 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
23570 /* This test is true if the dependent insn reads the flags but
23571 not any other potentially set register. */
23572 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
23575 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
23581 /* Return true iff USE_INSN has a memory address with operands set by
23585 ix86_agi_dependent (rtx set_insn, rtx use_insn)
23588 extract_insn_cached (use_insn);
23589 for (i = recog_data.n_operands - 1; i >= 0; --i)
23590 if (MEM_P (recog_data.operand[i]))
23592 rtx addr = XEXP (recog_data.operand[i], 0);
23593 return modified_in_p (addr, set_insn) != 0;
23599 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
23601 enum attr_type insn_type, dep_insn_type;
23602 enum attr_memory memory;
23604 int dep_insn_code_number;
23606 /* Anti and output dependencies have zero cost on all CPUs. */
23607 if (REG_NOTE_KIND (link) != 0)
23610 dep_insn_code_number = recog_memoized (dep_insn);
23612 /* If we can't recognize the insns, we can't really do anything. */
23613 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
23616 insn_type = get_attr_type (insn);
23617 dep_insn_type = get_attr_type (dep_insn);
23621 case PROCESSOR_PENTIUM:
23622 /* Address Generation Interlock adds a cycle of latency. */
23623 if (insn_type == TYPE_LEA)
23625 rtx addr = PATTERN (insn);
23627 if (GET_CODE (addr) == PARALLEL)
23628 addr = XVECEXP (addr, 0, 0);
23630 gcc_assert (GET_CODE (addr) == SET);
23632 addr = SET_SRC (addr);
23633 if (modified_in_p (addr, dep_insn))
23636 else if (ix86_agi_dependent (dep_insn, insn))
23639 /* ??? Compares pair with jump/setcc. */
23640 if (ix86_flags_dependent (insn, dep_insn, insn_type))
23643 /* Floating point stores require value to be ready one cycle earlier. */
23644 if (insn_type == TYPE_FMOV
23645 && get_attr_memory (insn) == MEMORY_STORE
23646 && !ix86_agi_dependent (dep_insn, insn))
23650 case PROCESSOR_PENTIUMPRO:
23651 memory = get_attr_memory (insn);
23653 /* INT->FP conversion is expensive. */
23654 if (get_attr_fp_int_src (dep_insn))
23657 /* There is one cycle extra latency between an FP op and a store. */
23658 if (insn_type == TYPE_FMOV
23659 && (set = single_set (dep_insn)) != NULL_RTX
23660 && (set2 = single_set (insn)) != NULL_RTX
23661 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
23662 && MEM_P (SET_DEST (set2)))
23665 /* Show ability of reorder buffer to hide latency of load by executing
23666 in parallel with previous instruction in case
23667 previous instruction is not needed to compute the address. */
23668 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
23669 && !ix86_agi_dependent (dep_insn, insn))
23671 /* Claim moves to take one cycle, as core can issue one load
23672 at time and the next load can start cycle later. */
23673 if (dep_insn_type == TYPE_IMOV
23674 || dep_insn_type == TYPE_FMOV)
23682 memory = get_attr_memory (insn);
23684 /* The esp dependency is resolved before the instruction is really
23686 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
23687 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
23690 /* INT->FP conversion is expensive. */
23691 if (get_attr_fp_int_src (dep_insn))
23694 /* Show ability of reorder buffer to hide latency of load by executing
23695 in parallel with previous instruction in case
23696 previous instruction is not needed to compute the address. */
23697 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
23698 && !ix86_agi_dependent (dep_insn, insn))
23700 /* Claim moves to take one cycle, as core can issue one load
23701 at time and the next load can start cycle later. */
23702 if (dep_insn_type == TYPE_IMOV
23703 || dep_insn_type == TYPE_FMOV)
23712 case PROCESSOR_ATHLON:
23714 case PROCESSOR_AMDFAM10:
23715 case PROCESSOR_BDVER1:
23716 case PROCESSOR_BDVER2:
23717 case PROCESSOR_BTVER1:
23718 case PROCESSOR_ATOM:
23719 case PROCESSOR_GENERIC32:
23720 case PROCESSOR_GENERIC64:
23721 memory = get_attr_memory (insn);
23723 /* Show ability of reorder buffer to hide latency of load by executing
23724 in parallel with previous instruction in case
23725 previous instruction is not needed to compute the address. */
23726 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
23727 && !ix86_agi_dependent (dep_insn, insn))
23729 enum attr_unit unit = get_attr_unit (insn);
23732 /* Because of the difference between the length of integer and
23733 floating unit pipeline preparation stages, the memory operands
23734 for floating point are cheaper.
23736 ??? For Athlon it the difference is most probably 2. */
23737 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
23740 loadcost = TARGET_ATHLON ? 2 : 0;
23742 if (cost >= loadcost)
23755 /* How many alternative schedules to try. This should be as wide as the
23756 scheduling freedom in the DFA, but no wider. Making this value too
23757 large results extra work for the scheduler. */
23760 ia32_multipass_dfa_lookahead (void)
23764 case PROCESSOR_PENTIUM:
23767 case PROCESSOR_PENTIUMPRO:
23771 case PROCESSOR_CORE2_32:
23772 case PROCESSOR_CORE2_64:
23773 case PROCESSOR_COREI7_32:
23774 case PROCESSOR_COREI7_64:
23775 /* Generally, we want haifa-sched:max_issue() to look ahead as far
23776 as many instructions can be executed on a cycle, i.e.,
23777 issue_rate. I wonder why tuning for many CPUs does not do this. */
23778 return ix86_issue_rate ();
23787 /* Model decoder of Core 2/i7.
23788 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
23789 track the instruction fetch block boundaries and make sure that long
23790 (9+ bytes) instructions are assigned to D0. */
23792 /* Maximum length of an insn that can be handled by
23793 a secondary decoder unit. '8' for Core 2/i7. */
23794 static int core2i7_secondary_decoder_max_insn_size;
23796 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
23797 '16' for Core 2/i7. */
23798 static int core2i7_ifetch_block_size;
23800 /* Maximum number of instructions decoder can handle per cycle.
23801 '6' for Core 2/i7. */
23802 static int core2i7_ifetch_block_max_insns;
23804 typedef struct ix86_first_cycle_multipass_data_ *
23805 ix86_first_cycle_multipass_data_t;
23806 typedef const struct ix86_first_cycle_multipass_data_ *
23807 const_ix86_first_cycle_multipass_data_t;
23809 /* A variable to store target state across calls to max_issue within
23811 static struct ix86_first_cycle_multipass_data_ _ix86_first_cycle_multipass_data,
23812 *ix86_first_cycle_multipass_data = &_ix86_first_cycle_multipass_data;
23814 /* Initialize DATA. */
23816 core2i7_first_cycle_multipass_init (void *_data)
23818 ix86_first_cycle_multipass_data_t data
23819 = (ix86_first_cycle_multipass_data_t) _data;
23821 data->ifetch_block_len = 0;
23822 data->ifetch_block_n_insns = 0;
23823 data->ready_try_change = NULL;
23824 data->ready_try_change_size = 0;
23827 /* Advancing the cycle; reset ifetch block counts. */
23829 core2i7_dfa_post_advance_cycle (void)
23831 ix86_first_cycle_multipass_data_t data = ix86_first_cycle_multipass_data;
23833 gcc_assert (data->ifetch_block_n_insns <= core2i7_ifetch_block_max_insns);
23835 data->ifetch_block_len = 0;
23836 data->ifetch_block_n_insns = 0;
23839 static int min_insn_size (rtx);
23841 /* Filter out insns from ready_try that the core will not be able to issue
23842 on current cycle due to decoder. */
23844 core2i7_first_cycle_multipass_filter_ready_try
23845 (const_ix86_first_cycle_multipass_data_t data,
23846 char *ready_try, int n_ready, bool first_cycle_insn_p)
23853 if (ready_try[n_ready])
23856 insn = get_ready_element (n_ready);
23857 insn_size = min_insn_size (insn);
23859 if (/* If this is a too long an insn for a secondary decoder ... */
23860 (!first_cycle_insn_p
23861 && insn_size > core2i7_secondary_decoder_max_insn_size)
23862 /* ... or it would not fit into the ifetch block ... */
23863 || data->ifetch_block_len + insn_size > core2i7_ifetch_block_size
23864 /* ... or the decoder is full already ... */
23865 || data->ifetch_block_n_insns + 1 > core2i7_ifetch_block_max_insns)
23866 /* ... mask the insn out. */
23868 ready_try[n_ready] = 1;
23870 if (data->ready_try_change)
23871 SET_BIT (data->ready_try_change, n_ready);
23876 /* Prepare for a new round of multipass lookahead scheduling. */
23878 core2i7_first_cycle_multipass_begin (void *_data, char *ready_try, int n_ready,
23879 bool first_cycle_insn_p)
23881 ix86_first_cycle_multipass_data_t data
23882 = (ix86_first_cycle_multipass_data_t) _data;
23883 const_ix86_first_cycle_multipass_data_t prev_data
23884 = ix86_first_cycle_multipass_data;
23886 /* Restore the state from the end of the previous round. */
23887 data->ifetch_block_len = prev_data->ifetch_block_len;
23888 data->ifetch_block_n_insns = prev_data->ifetch_block_n_insns;
23890 /* Filter instructions that cannot be issued on current cycle due to
23891 decoder restrictions. */
23892 core2i7_first_cycle_multipass_filter_ready_try (data, ready_try, n_ready,
23893 first_cycle_insn_p);
23896 /* INSN is being issued in current solution. Account for its impact on
23897 the decoder model. */
23899 core2i7_first_cycle_multipass_issue (void *_data, char *ready_try, int n_ready,
23900 rtx insn, const void *_prev_data)
23902 ix86_first_cycle_multipass_data_t data
23903 = (ix86_first_cycle_multipass_data_t) _data;
23904 const_ix86_first_cycle_multipass_data_t prev_data
23905 = (const_ix86_first_cycle_multipass_data_t) _prev_data;
23907 int insn_size = min_insn_size (insn);
23909 data->ifetch_block_len = prev_data->ifetch_block_len + insn_size;
23910 data->ifetch_block_n_insns = prev_data->ifetch_block_n_insns + 1;
23911 gcc_assert (data->ifetch_block_len <= core2i7_ifetch_block_size
23912 && data->ifetch_block_n_insns <= core2i7_ifetch_block_max_insns);
23914 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
23915 if (!data->ready_try_change)
23917 data->ready_try_change = sbitmap_alloc (n_ready);
23918 data->ready_try_change_size = n_ready;
23920 else if (data->ready_try_change_size < n_ready)
23922 data->ready_try_change = sbitmap_resize (data->ready_try_change,
23924 data->ready_try_change_size = n_ready;
23926 sbitmap_zero (data->ready_try_change);
23928 /* Filter out insns from ready_try that the core will not be able to issue
23929 on current cycle due to decoder. */
23930 core2i7_first_cycle_multipass_filter_ready_try (data, ready_try, n_ready,
23934 /* Revert the effect on ready_try. */
23936 core2i7_first_cycle_multipass_backtrack (const void *_data,
23938 int n_ready ATTRIBUTE_UNUSED)
23940 const_ix86_first_cycle_multipass_data_t data
23941 = (const_ix86_first_cycle_multipass_data_t) _data;
23942 unsigned int i = 0;
23943 sbitmap_iterator sbi;
23945 gcc_assert (sbitmap_last_set_bit (data->ready_try_change) < n_ready);
23946 EXECUTE_IF_SET_IN_SBITMAP (data->ready_try_change, 0, i, sbi)
23952 /* Save the result of multipass lookahead scheduling for the next round. */
23954 core2i7_first_cycle_multipass_end (const void *_data)
23956 const_ix86_first_cycle_multipass_data_t data
23957 = (const_ix86_first_cycle_multipass_data_t) _data;
23958 ix86_first_cycle_multipass_data_t next_data
23959 = ix86_first_cycle_multipass_data;
23963 next_data->ifetch_block_len = data->ifetch_block_len;
23964 next_data->ifetch_block_n_insns = data->ifetch_block_n_insns;
23968 /* Deallocate target data. */
23970 core2i7_first_cycle_multipass_fini (void *_data)
23972 ix86_first_cycle_multipass_data_t data
23973 = (ix86_first_cycle_multipass_data_t) _data;
23975 if (data->ready_try_change)
23977 sbitmap_free (data->ready_try_change);
23978 data->ready_try_change = NULL;
23979 data->ready_try_change_size = 0;
23983 /* Prepare for scheduling pass. */
23985 ix86_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
23986 int verbose ATTRIBUTE_UNUSED,
23987 int max_uid ATTRIBUTE_UNUSED)
23989 /* Install scheduling hooks for current CPU. Some of these hooks are used
23990 in time-critical parts of the scheduler, so we only set them up when
23991 they are actually used. */
23994 case PROCESSOR_CORE2_32:
23995 case PROCESSOR_CORE2_64:
23996 case PROCESSOR_COREI7_32:
23997 case PROCESSOR_COREI7_64:
23998 targetm.sched.dfa_post_advance_cycle
23999 = core2i7_dfa_post_advance_cycle;
24000 targetm.sched.first_cycle_multipass_init
24001 = core2i7_first_cycle_multipass_init;
24002 targetm.sched.first_cycle_multipass_begin
24003 = core2i7_first_cycle_multipass_begin;
24004 targetm.sched.first_cycle_multipass_issue
24005 = core2i7_first_cycle_multipass_issue;
24006 targetm.sched.first_cycle_multipass_backtrack
24007 = core2i7_first_cycle_multipass_backtrack;
24008 targetm.sched.first_cycle_multipass_end
24009 = core2i7_first_cycle_multipass_end;
24010 targetm.sched.first_cycle_multipass_fini
24011 = core2i7_first_cycle_multipass_fini;
24013 /* Set decoder parameters. */
24014 core2i7_secondary_decoder_max_insn_size = 8;
24015 core2i7_ifetch_block_size = 16;
24016 core2i7_ifetch_block_max_insns = 6;
24020 targetm.sched.dfa_post_advance_cycle = NULL;
24021 targetm.sched.first_cycle_multipass_init = NULL;
24022 targetm.sched.first_cycle_multipass_begin = NULL;
24023 targetm.sched.first_cycle_multipass_issue = NULL;
24024 targetm.sched.first_cycle_multipass_backtrack = NULL;
24025 targetm.sched.first_cycle_multipass_end = NULL;
24026 targetm.sched.first_cycle_multipass_fini = NULL;
24032 /* Compute the alignment given to a constant that is being placed in memory.
24033 EXP is the constant and ALIGN is the alignment that the object would
24035 The value of this function is used instead of that alignment to align
24039 ix86_constant_alignment (tree exp, int align)
24041 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
24042 || TREE_CODE (exp) == INTEGER_CST)
24044 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
24046 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
24049 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
24050 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
24051 return BITS_PER_WORD;
24056 /* Compute the alignment for a static variable.
24057 TYPE is the data type, and ALIGN is the alignment that
24058 the object would ordinarily have. The value of this function is used
24059 instead of that alignment to align the object. */
24062 ix86_data_alignment (tree type, int align)
24064 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
24066 if (AGGREGATE_TYPE_P (type)
24067 && TYPE_SIZE (type)
24068 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
24069 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
24070 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
24071 && align < max_align)
24074 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24075 to 16byte boundary. */
24078 if (AGGREGATE_TYPE_P (type)
24079 && TYPE_SIZE (type)
24080 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
24081 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
24082 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
24086 if (TREE_CODE (type) == ARRAY_TYPE)
24088 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
24090 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
24093 else if (TREE_CODE (type) == COMPLEX_TYPE)
24096 if (TYPE_MODE (type) == DCmode && align < 64)
24098 if ((TYPE_MODE (type) == XCmode
24099 || TYPE_MODE (type) == TCmode) && align < 128)
24102 else if ((TREE_CODE (type) == RECORD_TYPE
24103 || TREE_CODE (type) == UNION_TYPE
24104 || TREE_CODE (type) == QUAL_UNION_TYPE)
24105 && TYPE_FIELDS (type))
24107 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
24109 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
24112 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
24113 || TREE_CODE (type) == INTEGER_TYPE)
24115 if (TYPE_MODE (type) == DFmode && align < 64)
24117 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
24124 /* Compute the alignment for a local variable or a stack slot. EXP is
24125 the data type or decl itself, MODE is the widest mode available and
24126 ALIGN is the alignment that the object would ordinarily have. The
24127 value of this macro is used instead of that alignment to align the
24131 ix86_local_alignment (tree exp, enum machine_mode mode,
24132 unsigned int align)
24136 if (exp && DECL_P (exp))
24138 type = TREE_TYPE (exp);
24147 /* Don't do dynamic stack realignment for long long objects with
24148 -mpreferred-stack-boundary=2. */
24151 && ix86_preferred_stack_boundary < 64
24152 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
24153 && (!type || !TYPE_USER_ALIGN (type))
24154 && (!decl || !DECL_USER_ALIGN (decl)))
24157 /* If TYPE is NULL, we are allocating a stack slot for caller-save
24158 register in MODE. We will return the largest alignment of XF
24162 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
24163 align = GET_MODE_ALIGNMENT (DFmode);
24167 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24168 to 16byte boundary. Exact wording is:
24170 An array uses the same alignment as its elements, except that a local or
24171 global array variable of length at least 16 bytes or
24172 a C99 variable-length array variable always has alignment of at least 16 bytes.
24174 This was added to allow use of aligned SSE instructions at arrays. This
24175 rule is meant for static storage (where compiler can not do the analysis
24176 by itself). We follow it for automatic variables only when convenient.
24177 We fully control everything in the function compiled and functions from
24178 other unit can not rely on the alignment.
24180 Exclude va_list type. It is the common case of local array where
24181 we can not benefit from the alignment. */
24182 if (TARGET_64BIT && optimize_function_for_speed_p (cfun)
24185 if (AGGREGATE_TYPE_P (type)
24186 && (va_list_type_node == NULL_TREE
24187 || (TYPE_MAIN_VARIANT (type)
24188 != TYPE_MAIN_VARIANT (va_list_type_node)))
24189 && TYPE_SIZE (type)
24190 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
24191 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
24192 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
24195 if (TREE_CODE (type) == ARRAY_TYPE)
24197 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
24199 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
24202 else if (TREE_CODE (type) == COMPLEX_TYPE)
24204 if (TYPE_MODE (type) == DCmode && align < 64)
24206 if ((TYPE_MODE (type) == XCmode
24207 || TYPE_MODE (type) == TCmode) && align < 128)
24210 else if ((TREE_CODE (type) == RECORD_TYPE
24211 || TREE_CODE (type) == UNION_TYPE
24212 || TREE_CODE (type) == QUAL_UNION_TYPE)
24213 && TYPE_FIELDS (type))
24215 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
24217 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
24220 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
24221 || TREE_CODE (type) == INTEGER_TYPE)
24224 if (TYPE_MODE (type) == DFmode && align < 64)
24226 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
24232 /* Compute the minimum required alignment for dynamic stack realignment
24233 purposes for a local variable, parameter or a stack slot. EXP is
24234 the data type or decl itself, MODE is its mode and ALIGN is the
24235 alignment that the object would ordinarily have. */
24238 ix86_minimum_alignment (tree exp, enum machine_mode mode,
24239 unsigned int align)
24243 if (exp && DECL_P (exp))
24245 type = TREE_TYPE (exp);
24254 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
24257 /* Don't do dynamic stack realignment for long long objects with
24258 -mpreferred-stack-boundary=2. */
24259 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
24260 && (!type || !TYPE_USER_ALIGN (type))
24261 && (!decl || !DECL_USER_ALIGN (decl)))
24267 /* Find a location for the static chain incoming to a nested function.
24268 This is a register, unless all free registers are used by arguments. */
24271 ix86_static_chain (const_tree fndecl, bool incoming_p)
24275 if (!DECL_STATIC_CHAIN (fndecl))
24280 /* We always use R10 in 64-bit mode. */
24288 /* By default in 32-bit mode we use ECX to pass the static chain. */
24291 fntype = TREE_TYPE (fndecl);
24292 ccvt = ix86_get_callcvt (fntype);
24293 if ((ccvt & (IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) != 0)
24295 /* Fastcall functions use ecx/edx for arguments, which leaves
24296 us with EAX for the static chain.
24297 Thiscall functions use ecx for arguments, which also
24298 leaves us with EAX for the static chain. */
24301 else if (ix86_function_regparm (fntype, fndecl) == 3)
24303 /* For regparm 3, we have no free call-clobbered registers in
24304 which to store the static chain. In order to implement this,
24305 we have the trampoline push the static chain to the stack.
24306 However, we can't push a value below the return address when
24307 we call the nested function directly, so we have to use an
24308 alternate entry point. For this we use ESI, and have the
24309 alternate entry point push ESI, so that things appear the
24310 same once we're executing the nested function. */
24313 if (fndecl == current_function_decl)
24314 ix86_static_chain_on_stack = true;
24315 return gen_frame_mem (SImode,
24316 plus_constant (arg_pointer_rtx, -8));
24322 return gen_rtx_REG (Pmode, regno);
24325 /* Emit RTL insns to initialize the variable parts of a trampoline.
24326 FNDECL is the decl of the target address; M_TRAMP is a MEM for
24327 the trampoline, and CHAIN_VALUE is an RTX for the static chain
24328 to be passed to the target function. */
24331 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
24337 fnaddr = XEXP (DECL_RTL (fndecl), 0);
24343 /* Load the function address to r11. Try to load address using
24344 the shorter movl instead of movabs. We may want to support
24345 movq for kernel mode, but kernel does not use trampolines at
24347 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
24349 fnaddr = copy_to_mode_reg (DImode, fnaddr);
24351 mem = adjust_address (m_tramp, HImode, offset);
24352 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
24354 mem = adjust_address (m_tramp, SImode, offset + 2);
24355 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
24360 mem = adjust_address (m_tramp, HImode, offset);
24361 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
24363 mem = adjust_address (m_tramp, DImode, offset + 2);
24364 emit_move_insn (mem, fnaddr);
24368 /* Load static chain using movabs to r10. Use the
24369 shorter movl instead of movabs for x32. */
24381 mem = adjust_address (m_tramp, HImode, offset);
24382 emit_move_insn (mem, gen_int_mode (opcode, HImode));
24384 mem = adjust_address (m_tramp, ptr_mode, offset + 2);
24385 emit_move_insn (mem, chain_value);
24388 /* Jump to r11; the last (unused) byte is a nop, only there to
24389 pad the write out to a single 32-bit store. */
24390 mem = adjust_address (m_tramp, SImode, offset);
24391 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
24398 /* Depending on the static chain location, either load a register
24399 with a constant, or push the constant to the stack. All of the
24400 instructions are the same size. */
24401 chain = ix86_static_chain (fndecl, true);
24404 switch (REGNO (chain))
24407 opcode = 0xb8; break;
24409 opcode = 0xb9; break;
24411 gcc_unreachable ();
24417 mem = adjust_address (m_tramp, QImode, offset);
24418 emit_move_insn (mem, gen_int_mode (opcode, QImode));
24420 mem = adjust_address (m_tramp, SImode, offset + 1);
24421 emit_move_insn (mem, chain_value);
24424 mem = adjust_address (m_tramp, QImode, offset);
24425 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
24427 mem = adjust_address (m_tramp, SImode, offset + 1);
24429 /* Compute offset from the end of the jmp to the target function.
24430 In the case in which the trampoline stores the static chain on
24431 the stack, we need to skip the first insn which pushes the
24432 (call-saved) register static chain; this push is 1 byte. */
24434 disp = expand_binop (SImode, sub_optab, fnaddr,
24435 plus_constant (XEXP (m_tramp, 0),
24436 offset - (MEM_P (chain) ? 1 : 0)),
24437 NULL_RTX, 1, OPTAB_DIRECT);
24438 emit_move_insn (mem, disp);
24441 gcc_assert (offset <= TRAMPOLINE_SIZE);
24443 #ifdef HAVE_ENABLE_EXECUTE_STACK
24444 #ifdef CHECK_EXECUTE_STACK_ENABLED
24445 if (CHECK_EXECUTE_STACK_ENABLED)
24447 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
24448 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
24452 /* The following file contains several enumerations and data structures
24453 built from the definitions in i386-builtin-types.def. */
24455 #include "i386-builtin-types.inc"
24457 /* Table for the ix86 builtin non-function types. */
24458 static GTY(()) tree ix86_builtin_type_tab[(int) IX86_BT_LAST_CPTR + 1];
24460 /* Retrieve an element from the above table, building some of
24461 the types lazily. */
24464 ix86_get_builtin_type (enum ix86_builtin_type tcode)
24466 unsigned int index;
24469 gcc_assert ((unsigned)tcode < ARRAY_SIZE(ix86_builtin_type_tab));
24471 type = ix86_builtin_type_tab[(int) tcode];
24475 gcc_assert (tcode > IX86_BT_LAST_PRIM);
24476 if (tcode <= IX86_BT_LAST_VECT)
24478 enum machine_mode mode;
24480 index = tcode - IX86_BT_LAST_PRIM - 1;
24481 itype = ix86_get_builtin_type (ix86_builtin_type_vect_base[index]);
24482 mode = ix86_builtin_type_vect_mode[index];
24484 type = build_vector_type_for_mode (itype, mode);
24490 index = tcode - IX86_BT_LAST_VECT - 1;
24491 if (tcode <= IX86_BT_LAST_PTR)
24492 quals = TYPE_UNQUALIFIED;
24494 quals = TYPE_QUAL_CONST;
24496 itype = ix86_get_builtin_type (ix86_builtin_type_ptr_base[index]);
24497 if (quals != TYPE_UNQUALIFIED)
24498 itype = build_qualified_type (itype, quals);
24500 type = build_pointer_type (itype);
24503 ix86_builtin_type_tab[(int) tcode] = type;
24507 /* Table for the ix86 builtin function types. */
24508 static GTY(()) tree ix86_builtin_func_type_tab[(int) IX86_BT_LAST_ALIAS + 1];
24510 /* Retrieve an element from the above table, building some of
24511 the types lazily. */
24514 ix86_get_builtin_func_type (enum ix86_builtin_func_type tcode)
24518 gcc_assert ((unsigned)tcode < ARRAY_SIZE (ix86_builtin_func_type_tab));
24520 type = ix86_builtin_func_type_tab[(int) tcode];
24524 if (tcode <= IX86_BT_LAST_FUNC)
24526 unsigned start = ix86_builtin_func_start[(int) tcode];
24527 unsigned after = ix86_builtin_func_start[(int) tcode + 1];
24528 tree rtype, atype, args = void_list_node;
24531 rtype = ix86_get_builtin_type (ix86_builtin_func_args[start]);
24532 for (i = after - 1; i > start; --i)
24534 atype = ix86_get_builtin_type (ix86_builtin_func_args[i]);
24535 args = tree_cons (NULL, atype, args);
24538 type = build_function_type (rtype, args);
24542 unsigned index = tcode - IX86_BT_LAST_FUNC - 1;
24543 enum ix86_builtin_func_type icode;
24545 icode = ix86_builtin_func_alias_base[index];
24546 type = ix86_get_builtin_func_type (icode);
24549 ix86_builtin_func_type_tab[(int) tcode] = type;
24554 /* Codes for all the SSE/MMX builtins. */
24557 IX86_BUILTIN_ADDPS,
24558 IX86_BUILTIN_ADDSS,
24559 IX86_BUILTIN_DIVPS,
24560 IX86_BUILTIN_DIVSS,
24561 IX86_BUILTIN_MULPS,
24562 IX86_BUILTIN_MULSS,
24563 IX86_BUILTIN_SUBPS,
24564 IX86_BUILTIN_SUBSS,
24566 IX86_BUILTIN_CMPEQPS,
24567 IX86_BUILTIN_CMPLTPS,
24568 IX86_BUILTIN_CMPLEPS,
24569 IX86_BUILTIN_CMPGTPS,
24570 IX86_BUILTIN_CMPGEPS,
24571 IX86_BUILTIN_CMPNEQPS,
24572 IX86_BUILTIN_CMPNLTPS,
24573 IX86_BUILTIN_CMPNLEPS,
24574 IX86_BUILTIN_CMPNGTPS,
24575 IX86_BUILTIN_CMPNGEPS,
24576 IX86_BUILTIN_CMPORDPS,
24577 IX86_BUILTIN_CMPUNORDPS,
24578 IX86_BUILTIN_CMPEQSS,
24579 IX86_BUILTIN_CMPLTSS,
24580 IX86_BUILTIN_CMPLESS,
24581 IX86_BUILTIN_CMPNEQSS,
24582 IX86_BUILTIN_CMPNLTSS,
24583 IX86_BUILTIN_CMPNLESS,
24584 IX86_BUILTIN_CMPNGTSS,
24585 IX86_BUILTIN_CMPNGESS,
24586 IX86_BUILTIN_CMPORDSS,
24587 IX86_BUILTIN_CMPUNORDSS,
24589 IX86_BUILTIN_COMIEQSS,
24590 IX86_BUILTIN_COMILTSS,
24591 IX86_BUILTIN_COMILESS,
24592 IX86_BUILTIN_COMIGTSS,
24593 IX86_BUILTIN_COMIGESS,
24594 IX86_BUILTIN_COMINEQSS,
24595 IX86_BUILTIN_UCOMIEQSS,
24596 IX86_BUILTIN_UCOMILTSS,
24597 IX86_BUILTIN_UCOMILESS,
24598 IX86_BUILTIN_UCOMIGTSS,
24599 IX86_BUILTIN_UCOMIGESS,
24600 IX86_BUILTIN_UCOMINEQSS,
24602 IX86_BUILTIN_CVTPI2PS,
24603 IX86_BUILTIN_CVTPS2PI,
24604 IX86_BUILTIN_CVTSI2SS,
24605 IX86_BUILTIN_CVTSI642SS,
24606 IX86_BUILTIN_CVTSS2SI,
24607 IX86_BUILTIN_CVTSS2SI64,
24608 IX86_BUILTIN_CVTTPS2PI,
24609 IX86_BUILTIN_CVTTSS2SI,
24610 IX86_BUILTIN_CVTTSS2SI64,
24612 IX86_BUILTIN_MAXPS,
24613 IX86_BUILTIN_MAXSS,
24614 IX86_BUILTIN_MINPS,
24615 IX86_BUILTIN_MINSS,
24617 IX86_BUILTIN_LOADUPS,
24618 IX86_BUILTIN_STOREUPS,
24619 IX86_BUILTIN_MOVSS,
24621 IX86_BUILTIN_MOVHLPS,
24622 IX86_BUILTIN_MOVLHPS,
24623 IX86_BUILTIN_LOADHPS,
24624 IX86_BUILTIN_LOADLPS,
24625 IX86_BUILTIN_STOREHPS,
24626 IX86_BUILTIN_STORELPS,
24628 IX86_BUILTIN_MASKMOVQ,
24629 IX86_BUILTIN_MOVMSKPS,
24630 IX86_BUILTIN_PMOVMSKB,
24632 IX86_BUILTIN_MOVNTPS,
24633 IX86_BUILTIN_MOVNTQ,
24635 IX86_BUILTIN_LOADDQU,
24636 IX86_BUILTIN_STOREDQU,
24638 IX86_BUILTIN_PACKSSWB,
24639 IX86_BUILTIN_PACKSSDW,
24640 IX86_BUILTIN_PACKUSWB,
24642 IX86_BUILTIN_PADDB,
24643 IX86_BUILTIN_PADDW,
24644 IX86_BUILTIN_PADDD,
24645 IX86_BUILTIN_PADDQ,
24646 IX86_BUILTIN_PADDSB,
24647 IX86_BUILTIN_PADDSW,
24648 IX86_BUILTIN_PADDUSB,
24649 IX86_BUILTIN_PADDUSW,
24650 IX86_BUILTIN_PSUBB,
24651 IX86_BUILTIN_PSUBW,
24652 IX86_BUILTIN_PSUBD,
24653 IX86_BUILTIN_PSUBQ,
24654 IX86_BUILTIN_PSUBSB,
24655 IX86_BUILTIN_PSUBSW,
24656 IX86_BUILTIN_PSUBUSB,
24657 IX86_BUILTIN_PSUBUSW,
24660 IX86_BUILTIN_PANDN,
24664 IX86_BUILTIN_PAVGB,
24665 IX86_BUILTIN_PAVGW,
24667 IX86_BUILTIN_PCMPEQB,
24668 IX86_BUILTIN_PCMPEQW,
24669 IX86_BUILTIN_PCMPEQD,
24670 IX86_BUILTIN_PCMPGTB,
24671 IX86_BUILTIN_PCMPGTW,
24672 IX86_BUILTIN_PCMPGTD,
24674 IX86_BUILTIN_PMADDWD,
24676 IX86_BUILTIN_PMAXSW,
24677 IX86_BUILTIN_PMAXUB,
24678 IX86_BUILTIN_PMINSW,
24679 IX86_BUILTIN_PMINUB,
24681 IX86_BUILTIN_PMULHUW,
24682 IX86_BUILTIN_PMULHW,
24683 IX86_BUILTIN_PMULLW,
24685 IX86_BUILTIN_PSADBW,
24686 IX86_BUILTIN_PSHUFW,
24688 IX86_BUILTIN_PSLLW,
24689 IX86_BUILTIN_PSLLD,
24690 IX86_BUILTIN_PSLLQ,
24691 IX86_BUILTIN_PSRAW,
24692 IX86_BUILTIN_PSRAD,
24693 IX86_BUILTIN_PSRLW,
24694 IX86_BUILTIN_PSRLD,
24695 IX86_BUILTIN_PSRLQ,
24696 IX86_BUILTIN_PSLLWI,
24697 IX86_BUILTIN_PSLLDI,
24698 IX86_BUILTIN_PSLLQI,
24699 IX86_BUILTIN_PSRAWI,
24700 IX86_BUILTIN_PSRADI,
24701 IX86_BUILTIN_PSRLWI,
24702 IX86_BUILTIN_PSRLDI,
24703 IX86_BUILTIN_PSRLQI,
24705 IX86_BUILTIN_PUNPCKHBW,
24706 IX86_BUILTIN_PUNPCKHWD,
24707 IX86_BUILTIN_PUNPCKHDQ,
24708 IX86_BUILTIN_PUNPCKLBW,
24709 IX86_BUILTIN_PUNPCKLWD,
24710 IX86_BUILTIN_PUNPCKLDQ,
24712 IX86_BUILTIN_SHUFPS,
24714 IX86_BUILTIN_RCPPS,
24715 IX86_BUILTIN_RCPSS,
24716 IX86_BUILTIN_RSQRTPS,
24717 IX86_BUILTIN_RSQRTPS_NR,
24718 IX86_BUILTIN_RSQRTSS,
24719 IX86_BUILTIN_RSQRTF,
24720 IX86_BUILTIN_SQRTPS,
24721 IX86_BUILTIN_SQRTPS_NR,
24722 IX86_BUILTIN_SQRTSS,
24724 IX86_BUILTIN_UNPCKHPS,
24725 IX86_BUILTIN_UNPCKLPS,
24727 IX86_BUILTIN_ANDPS,
24728 IX86_BUILTIN_ANDNPS,
24730 IX86_BUILTIN_XORPS,
24733 IX86_BUILTIN_LDMXCSR,
24734 IX86_BUILTIN_STMXCSR,
24735 IX86_BUILTIN_SFENCE,
24737 /* 3DNow! Original */
24738 IX86_BUILTIN_FEMMS,
24739 IX86_BUILTIN_PAVGUSB,
24740 IX86_BUILTIN_PF2ID,
24741 IX86_BUILTIN_PFACC,
24742 IX86_BUILTIN_PFADD,
24743 IX86_BUILTIN_PFCMPEQ,
24744 IX86_BUILTIN_PFCMPGE,
24745 IX86_BUILTIN_PFCMPGT,
24746 IX86_BUILTIN_PFMAX,
24747 IX86_BUILTIN_PFMIN,
24748 IX86_BUILTIN_PFMUL,
24749 IX86_BUILTIN_PFRCP,
24750 IX86_BUILTIN_PFRCPIT1,
24751 IX86_BUILTIN_PFRCPIT2,
24752 IX86_BUILTIN_PFRSQIT1,
24753 IX86_BUILTIN_PFRSQRT,
24754 IX86_BUILTIN_PFSUB,
24755 IX86_BUILTIN_PFSUBR,
24756 IX86_BUILTIN_PI2FD,
24757 IX86_BUILTIN_PMULHRW,
24759 /* 3DNow! Athlon Extensions */
24760 IX86_BUILTIN_PF2IW,
24761 IX86_BUILTIN_PFNACC,
24762 IX86_BUILTIN_PFPNACC,
24763 IX86_BUILTIN_PI2FW,
24764 IX86_BUILTIN_PSWAPDSI,
24765 IX86_BUILTIN_PSWAPDSF,
24768 IX86_BUILTIN_ADDPD,
24769 IX86_BUILTIN_ADDSD,
24770 IX86_BUILTIN_DIVPD,
24771 IX86_BUILTIN_DIVSD,
24772 IX86_BUILTIN_MULPD,
24773 IX86_BUILTIN_MULSD,
24774 IX86_BUILTIN_SUBPD,
24775 IX86_BUILTIN_SUBSD,
24777 IX86_BUILTIN_CMPEQPD,
24778 IX86_BUILTIN_CMPLTPD,
24779 IX86_BUILTIN_CMPLEPD,
24780 IX86_BUILTIN_CMPGTPD,
24781 IX86_BUILTIN_CMPGEPD,
24782 IX86_BUILTIN_CMPNEQPD,
24783 IX86_BUILTIN_CMPNLTPD,
24784 IX86_BUILTIN_CMPNLEPD,
24785 IX86_BUILTIN_CMPNGTPD,
24786 IX86_BUILTIN_CMPNGEPD,
24787 IX86_BUILTIN_CMPORDPD,
24788 IX86_BUILTIN_CMPUNORDPD,
24789 IX86_BUILTIN_CMPEQSD,
24790 IX86_BUILTIN_CMPLTSD,
24791 IX86_BUILTIN_CMPLESD,
24792 IX86_BUILTIN_CMPNEQSD,
24793 IX86_BUILTIN_CMPNLTSD,
24794 IX86_BUILTIN_CMPNLESD,
24795 IX86_BUILTIN_CMPORDSD,
24796 IX86_BUILTIN_CMPUNORDSD,
24798 IX86_BUILTIN_COMIEQSD,
24799 IX86_BUILTIN_COMILTSD,
24800 IX86_BUILTIN_COMILESD,
24801 IX86_BUILTIN_COMIGTSD,
24802 IX86_BUILTIN_COMIGESD,
24803 IX86_BUILTIN_COMINEQSD,
24804 IX86_BUILTIN_UCOMIEQSD,
24805 IX86_BUILTIN_UCOMILTSD,
24806 IX86_BUILTIN_UCOMILESD,
24807 IX86_BUILTIN_UCOMIGTSD,
24808 IX86_BUILTIN_UCOMIGESD,
24809 IX86_BUILTIN_UCOMINEQSD,
24811 IX86_BUILTIN_MAXPD,
24812 IX86_BUILTIN_MAXSD,
24813 IX86_BUILTIN_MINPD,
24814 IX86_BUILTIN_MINSD,
24816 IX86_BUILTIN_ANDPD,
24817 IX86_BUILTIN_ANDNPD,
24819 IX86_BUILTIN_XORPD,
24821 IX86_BUILTIN_SQRTPD,
24822 IX86_BUILTIN_SQRTSD,
24824 IX86_BUILTIN_UNPCKHPD,
24825 IX86_BUILTIN_UNPCKLPD,
24827 IX86_BUILTIN_SHUFPD,
24829 IX86_BUILTIN_LOADUPD,
24830 IX86_BUILTIN_STOREUPD,
24831 IX86_BUILTIN_MOVSD,
24833 IX86_BUILTIN_LOADHPD,
24834 IX86_BUILTIN_LOADLPD,
24836 IX86_BUILTIN_CVTDQ2PD,
24837 IX86_BUILTIN_CVTDQ2PS,
24839 IX86_BUILTIN_CVTPD2DQ,
24840 IX86_BUILTIN_CVTPD2PI,
24841 IX86_BUILTIN_CVTPD2PS,
24842 IX86_BUILTIN_CVTTPD2DQ,
24843 IX86_BUILTIN_CVTTPD2PI,
24845 IX86_BUILTIN_CVTPI2PD,
24846 IX86_BUILTIN_CVTSI2SD,
24847 IX86_BUILTIN_CVTSI642SD,
24849 IX86_BUILTIN_CVTSD2SI,
24850 IX86_BUILTIN_CVTSD2SI64,
24851 IX86_BUILTIN_CVTSD2SS,
24852 IX86_BUILTIN_CVTSS2SD,
24853 IX86_BUILTIN_CVTTSD2SI,
24854 IX86_BUILTIN_CVTTSD2SI64,
24856 IX86_BUILTIN_CVTPS2DQ,
24857 IX86_BUILTIN_CVTPS2PD,
24858 IX86_BUILTIN_CVTTPS2DQ,
24860 IX86_BUILTIN_MOVNTI,
24861 IX86_BUILTIN_MOVNTI64,
24862 IX86_BUILTIN_MOVNTPD,
24863 IX86_BUILTIN_MOVNTDQ,
24865 IX86_BUILTIN_MOVQ128,
24868 IX86_BUILTIN_MASKMOVDQU,
24869 IX86_BUILTIN_MOVMSKPD,
24870 IX86_BUILTIN_PMOVMSKB128,
24872 IX86_BUILTIN_PACKSSWB128,
24873 IX86_BUILTIN_PACKSSDW128,
24874 IX86_BUILTIN_PACKUSWB128,
24876 IX86_BUILTIN_PADDB128,
24877 IX86_BUILTIN_PADDW128,
24878 IX86_BUILTIN_PADDD128,
24879 IX86_BUILTIN_PADDQ128,
24880 IX86_BUILTIN_PADDSB128,
24881 IX86_BUILTIN_PADDSW128,
24882 IX86_BUILTIN_PADDUSB128,
24883 IX86_BUILTIN_PADDUSW128,
24884 IX86_BUILTIN_PSUBB128,
24885 IX86_BUILTIN_PSUBW128,
24886 IX86_BUILTIN_PSUBD128,
24887 IX86_BUILTIN_PSUBQ128,
24888 IX86_BUILTIN_PSUBSB128,
24889 IX86_BUILTIN_PSUBSW128,
24890 IX86_BUILTIN_PSUBUSB128,
24891 IX86_BUILTIN_PSUBUSW128,
24893 IX86_BUILTIN_PAND128,
24894 IX86_BUILTIN_PANDN128,
24895 IX86_BUILTIN_POR128,
24896 IX86_BUILTIN_PXOR128,
24898 IX86_BUILTIN_PAVGB128,
24899 IX86_BUILTIN_PAVGW128,
24901 IX86_BUILTIN_PCMPEQB128,
24902 IX86_BUILTIN_PCMPEQW128,
24903 IX86_BUILTIN_PCMPEQD128,
24904 IX86_BUILTIN_PCMPGTB128,
24905 IX86_BUILTIN_PCMPGTW128,
24906 IX86_BUILTIN_PCMPGTD128,
24908 IX86_BUILTIN_PMADDWD128,
24910 IX86_BUILTIN_PMAXSW128,
24911 IX86_BUILTIN_PMAXUB128,
24912 IX86_BUILTIN_PMINSW128,
24913 IX86_BUILTIN_PMINUB128,
24915 IX86_BUILTIN_PMULUDQ,
24916 IX86_BUILTIN_PMULUDQ128,
24917 IX86_BUILTIN_PMULHUW128,
24918 IX86_BUILTIN_PMULHW128,
24919 IX86_BUILTIN_PMULLW128,
24921 IX86_BUILTIN_PSADBW128,
24922 IX86_BUILTIN_PSHUFHW,
24923 IX86_BUILTIN_PSHUFLW,
24924 IX86_BUILTIN_PSHUFD,
24926 IX86_BUILTIN_PSLLDQI128,
24927 IX86_BUILTIN_PSLLWI128,
24928 IX86_BUILTIN_PSLLDI128,
24929 IX86_BUILTIN_PSLLQI128,
24930 IX86_BUILTIN_PSRAWI128,
24931 IX86_BUILTIN_PSRADI128,
24932 IX86_BUILTIN_PSRLDQI128,
24933 IX86_BUILTIN_PSRLWI128,
24934 IX86_BUILTIN_PSRLDI128,
24935 IX86_BUILTIN_PSRLQI128,
24937 IX86_BUILTIN_PSLLDQ128,
24938 IX86_BUILTIN_PSLLW128,
24939 IX86_BUILTIN_PSLLD128,
24940 IX86_BUILTIN_PSLLQ128,
24941 IX86_BUILTIN_PSRAW128,
24942 IX86_BUILTIN_PSRAD128,
24943 IX86_BUILTIN_PSRLW128,
24944 IX86_BUILTIN_PSRLD128,
24945 IX86_BUILTIN_PSRLQ128,
24947 IX86_BUILTIN_PUNPCKHBW128,
24948 IX86_BUILTIN_PUNPCKHWD128,
24949 IX86_BUILTIN_PUNPCKHDQ128,
24950 IX86_BUILTIN_PUNPCKHQDQ128,
24951 IX86_BUILTIN_PUNPCKLBW128,
24952 IX86_BUILTIN_PUNPCKLWD128,
24953 IX86_BUILTIN_PUNPCKLDQ128,
24954 IX86_BUILTIN_PUNPCKLQDQ128,
24956 IX86_BUILTIN_CLFLUSH,
24957 IX86_BUILTIN_MFENCE,
24958 IX86_BUILTIN_LFENCE,
24959 IX86_BUILTIN_PAUSE,
24961 IX86_BUILTIN_BSRSI,
24962 IX86_BUILTIN_BSRDI,
24963 IX86_BUILTIN_RDPMC,
24964 IX86_BUILTIN_RDTSC,
24965 IX86_BUILTIN_RDTSCP,
24966 IX86_BUILTIN_ROLQI,
24967 IX86_BUILTIN_ROLHI,
24968 IX86_BUILTIN_RORQI,
24969 IX86_BUILTIN_RORHI,
24972 IX86_BUILTIN_ADDSUBPS,
24973 IX86_BUILTIN_HADDPS,
24974 IX86_BUILTIN_HSUBPS,
24975 IX86_BUILTIN_MOVSHDUP,
24976 IX86_BUILTIN_MOVSLDUP,
24977 IX86_BUILTIN_ADDSUBPD,
24978 IX86_BUILTIN_HADDPD,
24979 IX86_BUILTIN_HSUBPD,
24980 IX86_BUILTIN_LDDQU,
24982 IX86_BUILTIN_MONITOR,
24983 IX86_BUILTIN_MWAIT,
24986 IX86_BUILTIN_PHADDW,
24987 IX86_BUILTIN_PHADDD,
24988 IX86_BUILTIN_PHADDSW,
24989 IX86_BUILTIN_PHSUBW,
24990 IX86_BUILTIN_PHSUBD,
24991 IX86_BUILTIN_PHSUBSW,
24992 IX86_BUILTIN_PMADDUBSW,
24993 IX86_BUILTIN_PMULHRSW,
24994 IX86_BUILTIN_PSHUFB,
24995 IX86_BUILTIN_PSIGNB,
24996 IX86_BUILTIN_PSIGNW,
24997 IX86_BUILTIN_PSIGND,
24998 IX86_BUILTIN_PALIGNR,
24999 IX86_BUILTIN_PABSB,
25000 IX86_BUILTIN_PABSW,
25001 IX86_BUILTIN_PABSD,
25003 IX86_BUILTIN_PHADDW128,
25004 IX86_BUILTIN_PHADDD128,
25005 IX86_BUILTIN_PHADDSW128,
25006 IX86_BUILTIN_PHSUBW128,
25007 IX86_BUILTIN_PHSUBD128,
25008 IX86_BUILTIN_PHSUBSW128,
25009 IX86_BUILTIN_PMADDUBSW128,
25010 IX86_BUILTIN_PMULHRSW128,
25011 IX86_BUILTIN_PSHUFB128,
25012 IX86_BUILTIN_PSIGNB128,
25013 IX86_BUILTIN_PSIGNW128,
25014 IX86_BUILTIN_PSIGND128,
25015 IX86_BUILTIN_PALIGNR128,
25016 IX86_BUILTIN_PABSB128,
25017 IX86_BUILTIN_PABSW128,
25018 IX86_BUILTIN_PABSD128,
25020 /* AMDFAM10 - SSE4A New Instructions. */
25021 IX86_BUILTIN_MOVNTSD,
25022 IX86_BUILTIN_MOVNTSS,
25023 IX86_BUILTIN_EXTRQI,
25024 IX86_BUILTIN_EXTRQ,
25025 IX86_BUILTIN_INSERTQI,
25026 IX86_BUILTIN_INSERTQ,
25029 IX86_BUILTIN_BLENDPD,
25030 IX86_BUILTIN_BLENDPS,
25031 IX86_BUILTIN_BLENDVPD,
25032 IX86_BUILTIN_BLENDVPS,
25033 IX86_BUILTIN_PBLENDVB128,
25034 IX86_BUILTIN_PBLENDW128,
25039 IX86_BUILTIN_INSERTPS128,
25041 IX86_BUILTIN_MOVNTDQA,
25042 IX86_BUILTIN_MPSADBW128,
25043 IX86_BUILTIN_PACKUSDW128,
25044 IX86_BUILTIN_PCMPEQQ,
25045 IX86_BUILTIN_PHMINPOSUW128,
25047 IX86_BUILTIN_PMAXSB128,
25048 IX86_BUILTIN_PMAXSD128,
25049 IX86_BUILTIN_PMAXUD128,
25050 IX86_BUILTIN_PMAXUW128,
25052 IX86_BUILTIN_PMINSB128,
25053 IX86_BUILTIN_PMINSD128,
25054 IX86_BUILTIN_PMINUD128,
25055 IX86_BUILTIN_PMINUW128,
25057 IX86_BUILTIN_PMOVSXBW128,
25058 IX86_BUILTIN_PMOVSXBD128,
25059 IX86_BUILTIN_PMOVSXBQ128,
25060 IX86_BUILTIN_PMOVSXWD128,
25061 IX86_BUILTIN_PMOVSXWQ128,
25062 IX86_BUILTIN_PMOVSXDQ128,
25064 IX86_BUILTIN_PMOVZXBW128,
25065 IX86_BUILTIN_PMOVZXBD128,
25066 IX86_BUILTIN_PMOVZXBQ128,
25067 IX86_BUILTIN_PMOVZXWD128,
25068 IX86_BUILTIN_PMOVZXWQ128,
25069 IX86_BUILTIN_PMOVZXDQ128,
25071 IX86_BUILTIN_PMULDQ128,
25072 IX86_BUILTIN_PMULLD128,
25074 IX86_BUILTIN_ROUNDSD,
25075 IX86_BUILTIN_ROUNDSS,
25077 IX86_BUILTIN_ROUNDPD,
25078 IX86_BUILTIN_ROUNDPS,
25080 IX86_BUILTIN_FLOORPD,
25081 IX86_BUILTIN_CEILPD,
25082 IX86_BUILTIN_TRUNCPD,
25083 IX86_BUILTIN_RINTPD,
25084 IX86_BUILTIN_ROUNDPD_AZ,
25086 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
25087 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
25088 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
25090 IX86_BUILTIN_FLOORPS,
25091 IX86_BUILTIN_CEILPS,
25092 IX86_BUILTIN_TRUNCPS,
25093 IX86_BUILTIN_RINTPS,
25094 IX86_BUILTIN_ROUNDPS_AZ,
25096 IX86_BUILTIN_FLOORPS_SFIX,
25097 IX86_BUILTIN_CEILPS_SFIX,
25098 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
25100 IX86_BUILTIN_PTESTZ,
25101 IX86_BUILTIN_PTESTC,
25102 IX86_BUILTIN_PTESTNZC,
25104 IX86_BUILTIN_VEC_INIT_V2SI,
25105 IX86_BUILTIN_VEC_INIT_V4HI,
25106 IX86_BUILTIN_VEC_INIT_V8QI,
25107 IX86_BUILTIN_VEC_EXT_V2DF,
25108 IX86_BUILTIN_VEC_EXT_V2DI,
25109 IX86_BUILTIN_VEC_EXT_V4SF,
25110 IX86_BUILTIN_VEC_EXT_V4SI,
25111 IX86_BUILTIN_VEC_EXT_V8HI,
25112 IX86_BUILTIN_VEC_EXT_V2SI,
25113 IX86_BUILTIN_VEC_EXT_V4HI,
25114 IX86_BUILTIN_VEC_EXT_V16QI,
25115 IX86_BUILTIN_VEC_SET_V2DI,
25116 IX86_BUILTIN_VEC_SET_V4SF,
25117 IX86_BUILTIN_VEC_SET_V4SI,
25118 IX86_BUILTIN_VEC_SET_V8HI,
25119 IX86_BUILTIN_VEC_SET_V4HI,
25120 IX86_BUILTIN_VEC_SET_V16QI,
25122 IX86_BUILTIN_VEC_PACK_SFIX,
25123 IX86_BUILTIN_VEC_PACK_SFIX256,
25126 IX86_BUILTIN_CRC32QI,
25127 IX86_BUILTIN_CRC32HI,
25128 IX86_BUILTIN_CRC32SI,
25129 IX86_BUILTIN_CRC32DI,
25131 IX86_BUILTIN_PCMPESTRI128,
25132 IX86_BUILTIN_PCMPESTRM128,
25133 IX86_BUILTIN_PCMPESTRA128,
25134 IX86_BUILTIN_PCMPESTRC128,
25135 IX86_BUILTIN_PCMPESTRO128,
25136 IX86_BUILTIN_PCMPESTRS128,
25137 IX86_BUILTIN_PCMPESTRZ128,
25138 IX86_BUILTIN_PCMPISTRI128,
25139 IX86_BUILTIN_PCMPISTRM128,
25140 IX86_BUILTIN_PCMPISTRA128,
25141 IX86_BUILTIN_PCMPISTRC128,
25142 IX86_BUILTIN_PCMPISTRO128,
25143 IX86_BUILTIN_PCMPISTRS128,
25144 IX86_BUILTIN_PCMPISTRZ128,
25146 IX86_BUILTIN_PCMPGTQ,
25148 /* AES instructions */
25149 IX86_BUILTIN_AESENC128,
25150 IX86_BUILTIN_AESENCLAST128,
25151 IX86_BUILTIN_AESDEC128,
25152 IX86_BUILTIN_AESDECLAST128,
25153 IX86_BUILTIN_AESIMC128,
25154 IX86_BUILTIN_AESKEYGENASSIST128,
25156 /* PCLMUL instruction */
25157 IX86_BUILTIN_PCLMULQDQ128,
25160 IX86_BUILTIN_ADDPD256,
25161 IX86_BUILTIN_ADDPS256,
25162 IX86_BUILTIN_ADDSUBPD256,
25163 IX86_BUILTIN_ADDSUBPS256,
25164 IX86_BUILTIN_ANDPD256,
25165 IX86_BUILTIN_ANDPS256,
25166 IX86_BUILTIN_ANDNPD256,
25167 IX86_BUILTIN_ANDNPS256,
25168 IX86_BUILTIN_BLENDPD256,
25169 IX86_BUILTIN_BLENDPS256,
25170 IX86_BUILTIN_BLENDVPD256,
25171 IX86_BUILTIN_BLENDVPS256,
25172 IX86_BUILTIN_DIVPD256,
25173 IX86_BUILTIN_DIVPS256,
25174 IX86_BUILTIN_DPPS256,
25175 IX86_BUILTIN_HADDPD256,
25176 IX86_BUILTIN_HADDPS256,
25177 IX86_BUILTIN_HSUBPD256,
25178 IX86_BUILTIN_HSUBPS256,
25179 IX86_BUILTIN_MAXPD256,
25180 IX86_BUILTIN_MAXPS256,
25181 IX86_BUILTIN_MINPD256,
25182 IX86_BUILTIN_MINPS256,
25183 IX86_BUILTIN_MULPD256,
25184 IX86_BUILTIN_MULPS256,
25185 IX86_BUILTIN_ORPD256,
25186 IX86_BUILTIN_ORPS256,
25187 IX86_BUILTIN_SHUFPD256,
25188 IX86_BUILTIN_SHUFPS256,
25189 IX86_BUILTIN_SUBPD256,
25190 IX86_BUILTIN_SUBPS256,
25191 IX86_BUILTIN_XORPD256,
25192 IX86_BUILTIN_XORPS256,
25193 IX86_BUILTIN_CMPSD,
25194 IX86_BUILTIN_CMPSS,
25195 IX86_BUILTIN_CMPPD,
25196 IX86_BUILTIN_CMPPS,
25197 IX86_BUILTIN_CMPPD256,
25198 IX86_BUILTIN_CMPPS256,
25199 IX86_BUILTIN_CVTDQ2PD256,
25200 IX86_BUILTIN_CVTDQ2PS256,
25201 IX86_BUILTIN_CVTPD2PS256,
25202 IX86_BUILTIN_CVTPS2DQ256,
25203 IX86_BUILTIN_CVTPS2PD256,
25204 IX86_BUILTIN_CVTTPD2DQ256,
25205 IX86_BUILTIN_CVTPD2DQ256,
25206 IX86_BUILTIN_CVTTPS2DQ256,
25207 IX86_BUILTIN_EXTRACTF128PD256,
25208 IX86_BUILTIN_EXTRACTF128PS256,
25209 IX86_BUILTIN_EXTRACTF128SI256,
25210 IX86_BUILTIN_VZEROALL,
25211 IX86_BUILTIN_VZEROUPPER,
25212 IX86_BUILTIN_VPERMILVARPD,
25213 IX86_BUILTIN_VPERMILVARPS,
25214 IX86_BUILTIN_VPERMILVARPD256,
25215 IX86_BUILTIN_VPERMILVARPS256,
25216 IX86_BUILTIN_VPERMILPD,
25217 IX86_BUILTIN_VPERMILPS,
25218 IX86_BUILTIN_VPERMILPD256,
25219 IX86_BUILTIN_VPERMILPS256,
25220 IX86_BUILTIN_VPERMIL2PD,
25221 IX86_BUILTIN_VPERMIL2PS,
25222 IX86_BUILTIN_VPERMIL2PD256,
25223 IX86_BUILTIN_VPERMIL2PS256,
25224 IX86_BUILTIN_VPERM2F128PD256,
25225 IX86_BUILTIN_VPERM2F128PS256,
25226 IX86_BUILTIN_VPERM2F128SI256,
25227 IX86_BUILTIN_VBROADCASTSS,
25228 IX86_BUILTIN_VBROADCASTSD256,
25229 IX86_BUILTIN_VBROADCASTSS256,
25230 IX86_BUILTIN_VBROADCASTPD256,
25231 IX86_BUILTIN_VBROADCASTPS256,
25232 IX86_BUILTIN_VINSERTF128PD256,
25233 IX86_BUILTIN_VINSERTF128PS256,
25234 IX86_BUILTIN_VINSERTF128SI256,
25235 IX86_BUILTIN_LOADUPD256,
25236 IX86_BUILTIN_LOADUPS256,
25237 IX86_BUILTIN_STOREUPD256,
25238 IX86_BUILTIN_STOREUPS256,
25239 IX86_BUILTIN_LDDQU256,
25240 IX86_BUILTIN_MOVNTDQ256,
25241 IX86_BUILTIN_MOVNTPD256,
25242 IX86_BUILTIN_MOVNTPS256,
25243 IX86_BUILTIN_LOADDQU256,
25244 IX86_BUILTIN_STOREDQU256,
25245 IX86_BUILTIN_MASKLOADPD,
25246 IX86_BUILTIN_MASKLOADPS,
25247 IX86_BUILTIN_MASKSTOREPD,
25248 IX86_BUILTIN_MASKSTOREPS,
25249 IX86_BUILTIN_MASKLOADPD256,
25250 IX86_BUILTIN_MASKLOADPS256,
25251 IX86_BUILTIN_MASKSTOREPD256,
25252 IX86_BUILTIN_MASKSTOREPS256,
25253 IX86_BUILTIN_MOVSHDUP256,
25254 IX86_BUILTIN_MOVSLDUP256,
25255 IX86_BUILTIN_MOVDDUP256,
25257 IX86_BUILTIN_SQRTPD256,
25258 IX86_BUILTIN_SQRTPS256,
25259 IX86_BUILTIN_SQRTPS_NR256,
25260 IX86_BUILTIN_RSQRTPS256,
25261 IX86_BUILTIN_RSQRTPS_NR256,
25263 IX86_BUILTIN_RCPPS256,
25265 IX86_BUILTIN_ROUNDPD256,
25266 IX86_BUILTIN_ROUNDPS256,
25268 IX86_BUILTIN_FLOORPD256,
25269 IX86_BUILTIN_CEILPD256,
25270 IX86_BUILTIN_TRUNCPD256,
25271 IX86_BUILTIN_RINTPD256,
25272 IX86_BUILTIN_ROUNDPD_AZ256,
25274 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
25275 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
25276 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
25278 IX86_BUILTIN_FLOORPS256,
25279 IX86_BUILTIN_CEILPS256,
25280 IX86_BUILTIN_TRUNCPS256,
25281 IX86_BUILTIN_RINTPS256,
25282 IX86_BUILTIN_ROUNDPS_AZ256,
25284 IX86_BUILTIN_FLOORPS_SFIX256,
25285 IX86_BUILTIN_CEILPS_SFIX256,
25286 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
25288 IX86_BUILTIN_UNPCKHPD256,
25289 IX86_BUILTIN_UNPCKLPD256,
25290 IX86_BUILTIN_UNPCKHPS256,
25291 IX86_BUILTIN_UNPCKLPS256,
25293 IX86_BUILTIN_SI256_SI,
25294 IX86_BUILTIN_PS256_PS,
25295 IX86_BUILTIN_PD256_PD,
25296 IX86_BUILTIN_SI_SI256,
25297 IX86_BUILTIN_PS_PS256,
25298 IX86_BUILTIN_PD_PD256,
25300 IX86_BUILTIN_VTESTZPD,
25301 IX86_BUILTIN_VTESTCPD,
25302 IX86_BUILTIN_VTESTNZCPD,
25303 IX86_BUILTIN_VTESTZPS,
25304 IX86_BUILTIN_VTESTCPS,
25305 IX86_BUILTIN_VTESTNZCPS,
25306 IX86_BUILTIN_VTESTZPD256,
25307 IX86_BUILTIN_VTESTCPD256,
25308 IX86_BUILTIN_VTESTNZCPD256,
25309 IX86_BUILTIN_VTESTZPS256,
25310 IX86_BUILTIN_VTESTCPS256,
25311 IX86_BUILTIN_VTESTNZCPS256,
25312 IX86_BUILTIN_PTESTZ256,
25313 IX86_BUILTIN_PTESTC256,
25314 IX86_BUILTIN_PTESTNZC256,
25316 IX86_BUILTIN_MOVMSKPD256,
25317 IX86_BUILTIN_MOVMSKPS256,
25320 IX86_BUILTIN_MPSADBW256,
25321 IX86_BUILTIN_PABSB256,
25322 IX86_BUILTIN_PABSW256,
25323 IX86_BUILTIN_PABSD256,
25324 IX86_BUILTIN_PACKSSDW256,
25325 IX86_BUILTIN_PACKSSWB256,
25326 IX86_BUILTIN_PACKUSDW256,
25327 IX86_BUILTIN_PACKUSWB256,
25328 IX86_BUILTIN_PADDB256,
25329 IX86_BUILTIN_PADDW256,
25330 IX86_BUILTIN_PADDD256,
25331 IX86_BUILTIN_PADDQ256,
25332 IX86_BUILTIN_PADDSB256,
25333 IX86_BUILTIN_PADDSW256,
25334 IX86_BUILTIN_PADDUSB256,
25335 IX86_BUILTIN_PADDUSW256,
25336 IX86_BUILTIN_PALIGNR256,
25337 IX86_BUILTIN_AND256I,
25338 IX86_BUILTIN_ANDNOT256I,
25339 IX86_BUILTIN_PAVGB256,
25340 IX86_BUILTIN_PAVGW256,
25341 IX86_BUILTIN_PBLENDVB256,
25342 IX86_BUILTIN_PBLENDVW256,
25343 IX86_BUILTIN_PCMPEQB256,
25344 IX86_BUILTIN_PCMPEQW256,
25345 IX86_BUILTIN_PCMPEQD256,
25346 IX86_BUILTIN_PCMPEQQ256,
25347 IX86_BUILTIN_PCMPGTB256,
25348 IX86_BUILTIN_PCMPGTW256,
25349 IX86_BUILTIN_PCMPGTD256,
25350 IX86_BUILTIN_PCMPGTQ256,
25351 IX86_BUILTIN_PHADDW256,
25352 IX86_BUILTIN_PHADDD256,
25353 IX86_BUILTIN_PHADDSW256,
25354 IX86_BUILTIN_PHSUBW256,
25355 IX86_BUILTIN_PHSUBD256,
25356 IX86_BUILTIN_PHSUBSW256,
25357 IX86_BUILTIN_PMADDUBSW256,
25358 IX86_BUILTIN_PMADDWD256,
25359 IX86_BUILTIN_PMAXSB256,
25360 IX86_BUILTIN_PMAXSW256,
25361 IX86_BUILTIN_PMAXSD256,
25362 IX86_BUILTIN_PMAXUB256,
25363 IX86_BUILTIN_PMAXUW256,
25364 IX86_BUILTIN_PMAXUD256,
25365 IX86_BUILTIN_PMINSB256,
25366 IX86_BUILTIN_PMINSW256,
25367 IX86_BUILTIN_PMINSD256,
25368 IX86_BUILTIN_PMINUB256,
25369 IX86_BUILTIN_PMINUW256,
25370 IX86_BUILTIN_PMINUD256,
25371 IX86_BUILTIN_PMOVMSKB256,
25372 IX86_BUILTIN_PMOVSXBW256,
25373 IX86_BUILTIN_PMOVSXBD256,
25374 IX86_BUILTIN_PMOVSXBQ256,
25375 IX86_BUILTIN_PMOVSXWD256,
25376 IX86_BUILTIN_PMOVSXWQ256,
25377 IX86_BUILTIN_PMOVSXDQ256,
25378 IX86_BUILTIN_PMOVZXBW256,
25379 IX86_BUILTIN_PMOVZXBD256,
25380 IX86_BUILTIN_PMOVZXBQ256,
25381 IX86_BUILTIN_PMOVZXWD256,
25382 IX86_BUILTIN_PMOVZXWQ256,
25383 IX86_BUILTIN_PMOVZXDQ256,
25384 IX86_BUILTIN_PMULDQ256,
25385 IX86_BUILTIN_PMULHRSW256,
25386 IX86_BUILTIN_PMULHUW256,
25387 IX86_BUILTIN_PMULHW256,
25388 IX86_BUILTIN_PMULLW256,
25389 IX86_BUILTIN_PMULLD256,
25390 IX86_BUILTIN_PMULUDQ256,
25391 IX86_BUILTIN_POR256,
25392 IX86_BUILTIN_PSADBW256,
25393 IX86_BUILTIN_PSHUFB256,
25394 IX86_BUILTIN_PSHUFD256,
25395 IX86_BUILTIN_PSHUFHW256,
25396 IX86_BUILTIN_PSHUFLW256,
25397 IX86_BUILTIN_PSIGNB256,
25398 IX86_BUILTIN_PSIGNW256,
25399 IX86_BUILTIN_PSIGND256,
25400 IX86_BUILTIN_PSLLDQI256,
25401 IX86_BUILTIN_PSLLWI256,
25402 IX86_BUILTIN_PSLLW256,
25403 IX86_BUILTIN_PSLLDI256,
25404 IX86_BUILTIN_PSLLD256,
25405 IX86_BUILTIN_PSLLQI256,
25406 IX86_BUILTIN_PSLLQ256,
25407 IX86_BUILTIN_PSRAWI256,
25408 IX86_BUILTIN_PSRAW256,
25409 IX86_BUILTIN_PSRADI256,
25410 IX86_BUILTIN_PSRAD256,
25411 IX86_BUILTIN_PSRLDQI256,
25412 IX86_BUILTIN_PSRLWI256,
25413 IX86_BUILTIN_PSRLW256,
25414 IX86_BUILTIN_PSRLDI256,
25415 IX86_BUILTIN_PSRLD256,
25416 IX86_BUILTIN_PSRLQI256,
25417 IX86_BUILTIN_PSRLQ256,
25418 IX86_BUILTIN_PSUBB256,
25419 IX86_BUILTIN_PSUBW256,
25420 IX86_BUILTIN_PSUBD256,
25421 IX86_BUILTIN_PSUBQ256,
25422 IX86_BUILTIN_PSUBSB256,
25423 IX86_BUILTIN_PSUBSW256,
25424 IX86_BUILTIN_PSUBUSB256,
25425 IX86_BUILTIN_PSUBUSW256,
25426 IX86_BUILTIN_PUNPCKHBW256,
25427 IX86_BUILTIN_PUNPCKHWD256,
25428 IX86_BUILTIN_PUNPCKHDQ256,
25429 IX86_BUILTIN_PUNPCKHQDQ256,
25430 IX86_BUILTIN_PUNPCKLBW256,
25431 IX86_BUILTIN_PUNPCKLWD256,
25432 IX86_BUILTIN_PUNPCKLDQ256,
25433 IX86_BUILTIN_PUNPCKLQDQ256,
25434 IX86_BUILTIN_PXOR256,
25435 IX86_BUILTIN_MOVNTDQA256,
25436 IX86_BUILTIN_VBROADCASTSS_PS,
25437 IX86_BUILTIN_VBROADCASTSS_PS256,
25438 IX86_BUILTIN_VBROADCASTSD_PD256,
25439 IX86_BUILTIN_VBROADCASTSI256,
25440 IX86_BUILTIN_PBLENDD256,
25441 IX86_BUILTIN_PBLENDD128,
25442 IX86_BUILTIN_PBROADCASTB256,
25443 IX86_BUILTIN_PBROADCASTW256,
25444 IX86_BUILTIN_PBROADCASTD256,
25445 IX86_BUILTIN_PBROADCASTQ256,
25446 IX86_BUILTIN_PBROADCASTB128,
25447 IX86_BUILTIN_PBROADCASTW128,
25448 IX86_BUILTIN_PBROADCASTD128,
25449 IX86_BUILTIN_PBROADCASTQ128,
25450 IX86_BUILTIN_VPERMVARSI256,
25451 IX86_BUILTIN_VPERMDF256,
25452 IX86_BUILTIN_VPERMVARSF256,
25453 IX86_BUILTIN_VPERMDI256,
25454 IX86_BUILTIN_VPERMTI256,
25455 IX86_BUILTIN_VEXTRACT128I256,
25456 IX86_BUILTIN_VINSERT128I256,
25457 IX86_BUILTIN_MASKLOADD,
25458 IX86_BUILTIN_MASKLOADQ,
25459 IX86_BUILTIN_MASKLOADD256,
25460 IX86_BUILTIN_MASKLOADQ256,
25461 IX86_BUILTIN_MASKSTORED,
25462 IX86_BUILTIN_MASKSTOREQ,
25463 IX86_BUILTIN_MASKSTORED256,
25464 IX86_BUILTIN_MASKSTOREQ256,
25465 IX86_BUILTIN_PSLLVV4DI,
25466 IX86_BUILTIN_PSLLVV2DI,
25467 IX86_BUILTIN_PSLLVV8SI,
25468 IX86_BUILTIN_PSLLVV4SI,
25469 IX86_BUILTIN_PSRAVV8SI,
25470 IX86_BUILTIN_PSRAVV4SI,
25471 IX86_BUILTIN_PSRLVV4DI,
25472 IX86_BUILTIN_PSRLVV2DI,
25473 IX86_BUILTIN_PSRLVV8SI,
25474 IX86_BUILTIN_PSRLVV4SI,
25476 IX86_BUILTIN_GATHERSIV2DF,
25477 IX86_BUILTIN_GATHERSIV4DF,
25478 IX86_BUILTIN_GATHERDIV2DF,
25479 IX86_BUILTIN_GATHERDIV4DF,
25480 IX86_BUILTIN_GATHERSIV4SF,
25481 IX86_BUILTIN_GATHERSIV8SF,
25482 IX86_BUILTIN_GATHERDIV4SF,
25483 IX86_BUILTIN_GATHERDIV8SF,
25484 IX86_BUILTIN_GATHERSIV2DI,
25485 IX86_BUILTIN_GATHERSIV4DI,
25486 IX86_BUILTIN_GATHERDIV2DI,
25487 IX86_BUILTIN_GATHERDIV4DI,
25488 IX86_BUILTIN_GATHERSIV4SI,
25489 IX86_BUILTIN_GATHERSIV8SI,
25490 IX86_BUILTIN_GATHERDIV4SI,
25491 IX86_BUILTIN_GATHERDIV8SI,
25493 /* Alternate 4 element gather for the vectorizer where
25494 all operands are 32-byte wide. */
25495 IX86_BUILTIN_GATHERALTSIV4DF,
25496 IX86_BUILTIN_GATHERALTDIV8SF,
25497 IX86_BUILTIN_GATHERALTSIV4DI,
25498 IX86_BUILTIN_GATHERALTDIV8SI,
25500 /* TFmode support builtins. */
25502 IX86_BUILTIN_HUGE_VALQ,
25503 IX86_BUILTIN_FABSQ,
25504 IX86_BUILTIN_COPYSIGNQ,
25506 /* Vectorizer support builtins. */
25507 IX86_BUILTIN_CPYSGNPS,
25508 IX86_BUILTIN_CPYSGNPD,
25509 IX86_BUILTIN_CPYSGNPS256,
25510 IX86_BUILTIN_CPYSGNPD256,
25512 /* FMA4 instructions. */
25513 IX86_BUILTIN_VFMADDSS,
25514 IX86_BUILTIN_VFMADDSD,
25515 IX86_BUILTIN_VFMADDPS,
25516 IX86_BUILTIN_VFMADDPD,
25517 IX86_BUILTIN_VFMADDPS256,
25518 IX86_BUILTIN_VFMADDPD256,
25519 IX86_BUILTIN_VFMADDSUBPS,
25520 IX86_BUILTIN_VFMADDSUBPD,
25521 IX86_BUILTIN_VFMADDSUBPS256,
25522 IX86_BUILTIN_VFMADDSUBPD256,
25524 /* FMA3 instructions. */
25525 IX86_BUILTIN_VFMADDSS3,
25526 IX86_BUILTIN_VFMADDSD3,
25528 /* XOP instructions. */
25529 IX86_BUILTIN_VPCMOV,
25530 IX86_BUILTIN_VPCMOV_V2DI,
25531 IX86_BUILTIN_VPCMOV_V4SI,
25532 IX86_BUILTIN_VPCMOV_V8HI,
25533 IX86_BUILTIN_VPCMOV_V16QI,
25534 IX86_BUILTIN_VPCMOV_V4SF,
25535 IX86_BUILTIN_VPCMOV_V2DF,
25536 IX86_BUILTIN_VPCMOV256,
25537 IX86_BUILTIN_VPCMOV_V4DI256,
25538 IX86_BUILTIN_VPCMOV_V8SI256,
25539 IX86_BUILTIN_VPCMOV_V16HI256,
25540 IX86_BUILTIN_VPCMOV_V32QI256,
25541 IX86_BUILTIN_VPCMOV_V8SF256,
25542 IX86_BUILTIN_VPCMOV_V4DF256,
25544 IX86_BUILTIN_VPPERM,
25546 IX86_BUILTIN_VPMACSSWW,
25547 IX86_BUILTIN_VPMACSWW,
25548 IX86_BUILTIN_VPMACSSWD,
25549 IX86_BUILTIN_VPMACSWD,
25550 IX86_BUILTIN_VPMACSSDD,
25551 IX86_BUILTIN_VPMACSDD,
25552 IX86_BUILTIN_VPMACSSDQL,
25553 IX86_BUILTIN_VPMACSSDQH,
25554 IX86_BUILTIN_VPMACSDQL,
25555 IX86_BUILTIN_VPMACSDQH,
25556 IX86_BUILTIN_VPMADCSSWD,
25557 IX86_BUILTIN_VPMADCSWD,
25559 IX86_BUILTIN_VPHADDBW,
25560 IX86_BUILTIN_VPHADDBD,
25561 IX86_BUILTIN_VPHADDBQ,
25562 IX86_BUILTIN_VPHADDWD,
25563 IX86_BUILTIN_VPHADDWQ,
25564 IX86_BUILTIN_VPHADDDQ,
25565 IX86_BUILTIN_VPHADDUBW,
25566 IX86_BUILTIN_VPHADDUBD,
25567 IX86_BUILTIN_VPHADDUBQ,
25568 IX86_BUILTIN_VPHADDUWD,
25569 IX86_BUILTIN_VPHADDUWQ,
25570 IX86_BUILTIN_VPHADDUDQ,
25571 IX86_BUILTIN_VPHSUBBW,
25572 IX86_BUILTIN_VPHSUBWD,
25573 IX86_BUILTIN_VPHSUBDQ,
25575 IX86_BUILTIN_VPROTB,
25576 IX86_BUILTIN_VPROTW,
25577 IX86_BUILTIN_VPROTD,
25578 IX86_BUILTIN_VPROTQ,
25579 IX86_BUILTIN_VPROTB_IMM,
25580 IX86_BUILTIN_VPROTW_IMM,
25581 IX86_BUILTIN_VPROTD_IMM,
25582 IX86_BUILTIN_VPROTQ_IMM,
25584 IX86_BUILTIN_VPSHLB,
25585 IX86_BUILTIN_VPSHLW,
25586 IX86_BUILTIN_VPSHLD,
25587 IX86_BUILTIN_VPSHLQ,
25588 IX86_BUILTIN_VPSHAB,
25589 IX86_BUILTIN_VPSHAW,
25590 IX86_BUILTIN_VPSHAD,
25591 IX86_BUILTIN_VPSHAQ,
25593 IX86_BUILTIN_VFRCZSS,
25594 IX86_BUILTIN_VFRCZSD,
25595 IX86_BUILTIN_VFRCZPS,
25596 IX86_BUILTIN_VFRCZPD,
25597 IX86_BUILTIN_VFRCZPS256,
25598 IX86_BUILTIN_VFRCZPD256,
25600 IX86_BUILTIN_VPCOMEQUB,
25601 IX86_BUILTIN_VPCOMNEUB,
25602 IX86_BUILTIN_VPCOMLTUB,
25603 IX86_BUILTIN_VPCOMLEUB,
25604 IX86_BUILTIN_VPCOMGTUB,
25605 IX86_BUILTIN_VPCOMGEUB,
25606 IX86_BUILTIN_VPCOMFALSEUB,
25607 IX86_BUILTIN_VPCOMTRUEUB,
25609 IX86_BUILTIN_VPCOMEQUW,
25610 IX86_BUILTIN_VPCOMNEUW,
25611 IX86_BUILTIN_VPCOMLTUW,
25612 IX86_BUILTIN_VPCOMLEUW,
25613 IX86_BUILTIN_VPCOMGTUW,
25614 IX86_BUILTIN_VPCOMGEUW,
25615 IX86_BUILTIN_VPCOMFALSEUW,
25616 IX86_BUILTIN_VPCOMTRUEUW,
25618 IX86_BUILTIN_VPCOMEQUD,
25619 IX86_BUILTIN_VPCOMNEUD,
25620 IX86_BUILTIN_VPCOMLTUD,
25621 IX86_BUILTIN_VPCOMLEUD,
25622 IX86_BUILTIN_VPCOMGTUD,
25623 IX86_BUILTIN_VPCOMGEUD,
25624 IX86_BUILTIN_VPCOMFALSEUD,
25625 IX86_BUILTIN_VPCOMTRUEUD,
25627 IX86_BUILTIN_VPCOMEQUQ,
25628 IX86_BUILTIN_VPCOMNEUQ,
25629 IX86_BUILTIN_VPCOMLTUQ,
25630 IX86_BUILTIN_VPCOMLEUQ,
25631 IX86_BUILTIN_VPCOMGTUQ,
25632 IX86_BUILTIN_VPCOMGEUQ,
25633 IX86_BUILTIN_VPCOMFALSEUQ,
25634 IX86_BUILTIN_VPCOMTRUEUQ,
25636 IX86_BUILTIN_VPCOMEQB,
25637 IX86_BUILTIN_VPCOMNEB,
25638 IX86_BUILTIN_VPCOMLTB,
25639 IX86_BUILTIN_VPCOMLEB,
25640 IX86_BUILTIN_VPCOMGTB,
25641 IX86_BUILTIN_VPCOMGEB,
25642 IX86_BUILTIN_VPCOMFALSEB,
25643 IX86_BUILTIN_VPCOMTRUEB,
25645 IX86_BUILTIN_VPCOMEQW,
25646 IX86_BUILTIN_VPCOMNEW,
25647 IX86_BUILTIN_VPCOMLTW,
25648 IX86_BUILTIN_VPCOMLEW,
25649 IX86_BUILTIN_VPCOMGTW,
25650 IX86_BUILTIN_VPCOMGEW,
25651 IX86_BUILTIN_VPCOMFALSEW,
25652 IX86_BUILTIN_VPCOMTRUEW,
25654 IX86_BUILTIN_VPCOMEQD,
25655 IX86_BUILTIN_VPCOMNED,
25656 IX86_BUILTIN_VPCOMLTD,
25657 IX86_BUILTIN_VPCOMLED,
25658 IX86_BUILTIN_VPCOMGTD,
25659 IX86_BUILTIN_VPCOMGED,
25660 IX86_BUILTIN_VPCOMFALSED,
25661 IX86_BUILTIN_VPCOMTRUED,
25663 IX86_BUILTIN_VPCOMEQQ,
25664 IX86_BUILTIN_VPCOMNEQ,
25665 IX86_BUILTIN_VPCOMLTQ,
25666 IX86_BUILTIN_VPCOMLEQ,
25667 IX86_BUILTIN_VPCOMGTQ,
25668 IX86_BUILTIN_VPCOMGEQ,
25669 IX86_BUILTIN_VPCOMFALSEQ,
25670 IX86_BUILTIN_VPCOMTRUEQ,
25672 /* LWP instructions. */
25673 IX86_BUILTIN_LLWPCB,
25674 IX86_BUILTIN_SLWPCB,
25675 IX86_BUILTIN_LWPVAL32,
25676 IX86_BUILTIN_LWPVAL64,
25677 IX86_BUILTIN_LWPINS32,
25678 IX86_BUILTIN_LWPINS64,
25682 /* BMI instructions. */
25683 IX86_BUILTIN_BEXTR32,
25684 IX86_BUILTIN_BEXTR64,
25687 /* TBM instructions. */
25688 IX86_BUILTIN_BEXTRI32,
25689 IX86_BUILTIN_BEXTRI64,
25691 /* BMI2 instructions. */
25692 IX86_BUILTIN_BZHI32,
25693 IX86_BUILTIN_BZHI64,
25694 IX86_BUILTIN_PDEP32,
25695 IX86_BUILTIN_PDEP64,
25696 IX86_BUILTIN_PEXT32,
25697 IX86_BUILTIN_PEXT64,
25699 /* FSGSBASE instructions. */
25700 IX86_BUILTIN_RDFSBASE32,
25701 IX86_BUILTIN_RDFSBASE64,
25702 IX86_BUILTIN_RDGSBASE32,
25703 IX86_BUILTIN_RDGSBASE64,
25704 IX86_BUILTIN_WRFSBASE32,
25705 IX86_BUILTIN_WRFSBASE64,
25706 IX86_BUILTIN_WRGSBASE32,
25707 IX86_BUILTIN_WRGSBASE64,
25709 /* RDRND instructions. */
25710 IX86_BUILTIN_RDRAND16_STEP,
25711 IX86_BUILTIN_RDRAND32_STEP,
25712 IX86_BUILTIN_RDRAND64_STEP,
25714 /* F16C instructions. */
25715 IX86_BUILTIN_CVTPH2PS,
25716 IX86_BUILTIN_CVTPH2PS256,
25717 IX86_BUILTIN_CVTPS2PH,
25718 IX86_BUILTIN_CVTPS2PH256,
25720 /* CFString built-in for darwin */
25721 IX86_BUILTIN_CFSTRING,
25726 /* Table for the ix86 builtin decls. */
25727 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
25729 /* Table of all of the builtin functions that are possible with different ISA's
25730 but are waiting to be built until a function is declared to use that
25732 struct builtin_isa {
25733 const char *name; /* function name */
25734 enum ix86_builtin_func_type tcode; /* type to use in the declaration */
25735 HOST_WIDE_INT isa; /* isa_flags this builtin is defined for */
25736 bool const_p; /* true if the declaration is constant */
25737 bool set_and_not_built_p;
25740 static struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
25743 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
25744 of which isa_flags to use in the ix86_builtins_isa array. Stores the
25745 function decl in the ix86_builtins array. Returns the function decl or
25746 NULL_TREE, if the builtin was not added.
25748 If the front end has a special hook for builtin functions, delay adding
25749 builtin functions that aren't in the current ISA until the ISA is changed
25750 with function specific optimization. Doing so, can save about 300K for the
25751 default compiler. When the builtin is expanded, check at that time whether
25754 If the front end doesn't have a special hook, record all builtins, even if
25755 it isn't an instruction set in the current ISA in case the user uses
25756 function specific options for a different ISA, so that we don't get scope
25757 errors if a builtin is added in the middle of a function scope. */
25760 def_builtin (HOST_WIDE_INT mask, const char *name,
25761 enum ix86_builtin_func_type tcode,
25762 enum ix86_builtins code)
25764 tree decl = NULL_TREE;
25766 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
25768 ix86_builtins_isa[(int) code].isa = mask;
25770 mask &= ~OPTION_MASK_ISA_64BIT;
25772 || (mask & ix86_isa_flags) != 0
25773 || (lang_hooks.builtin_function
25774 == lang_hooks.builtin_function_ext_scope))
25777 tree type = ix86_get_builtin_func_type (tcode);
25778 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
25780 ix86_builtins[(int) code] = decl;
25781 ix86_builtins_isa[(int) code].set_and_not_built_p = false;
25785 ix86_builtins[(int) code] = NULL_TREE;
25786 ix86_builtins_isa[(int) code].tcode = tcode;
25787 ix86_builtins_isa[(int) code].name = name;
25788 ix86_builtins_isa[(int) code].const_p = false;
25789 ix86_builtins_isa[(int) code].set_and_not_built_p = true;
25796 /* Like def_builtin, but also marks the function decl "const". */
25799 def_builtin_const (HOST_WIDE_INT mask, const char *name,
25800 enum ix86_builtin_func_type tcode, enum ix86_builtins code)
25802 tree decl = def_builtin (mask, name, tcode, code);
25804 TREE_READONLY (decl) = 1;
25806 ix86_builtins_isa[(int) code].const_p = true;
25811 /* Add any new builtin functions for a given ISA that may not have been
25812 declared. This saves a bit of space compared to adding all of the
25813 declarations to the tree, even if we didn't use them. */
25816 ix86_add_new_builtins (HOST_WIDE_INT isa)
25820 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
25822 if ((ix86_builtins_isa[i].isa & isa) != 0
25823 && ix86_builtins_isa[i].set_and_not_built_p)
25827 /* Don't define the builtin again. */
25828 ix86_builtins_isa[i].set_and_not_built_p = false;
25830 type = ix86_get_builtin_func_type (ix86_builtins_isa[i].tcode);
25831 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
25832 type, i, BUILT_IN_MD, NULL,
25835 ix86_builtins[i] = decl;
25836 if (ix86_builtins_isa[i].const_p)
25837 TREE_READONLY (decl) = 1;
25842 /* Bits for builtin_description.flag. */
25844 /* Set when we don't support the comparison natively, and should
25845 swap_comparison in order to support it. */
25846 #define BUILTIN_DESC_SWAP_OPERANDS 1
25848 struct builtin_description
25850 const HOST_WIDE_INT mask;
25851 const enum insn_code icode;
25852 const char *const name;
25853 const enum ix86_builtins code;
25854 const enum rtx_code comparison;
25858 static const struct builtin_description bdesc_comi[] =
25860 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
25861 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
25862 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
25863 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
25864 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
25865 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
25866 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
25867 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
25868 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
25869 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
25870 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
25871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
25872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
25873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
25874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
25875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
25876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
25877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
25878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
25879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
25880 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
25881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
25882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
25883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
25886 static const struct builtin_description bdesc_pcmpestr[] =
25889 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
25890 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
25891 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
25892 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
25893 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
25894 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
25895 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
25898 static const struct builtin_description bdesc_pcmpistr[] =
25901 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
25902 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
25903 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
25904 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
25905 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
25906 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
25907 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
25910 /* Special builtins with variable number of arguments. */
25911 static const struct builtin_description bdesc_special_args[] =
25913 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
25914 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
25915 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
25918 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
25921 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
25924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
25925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
25926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
25928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
25929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
25930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
25931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
25933 /* SSE or 3DNow!A */
25934 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
25935 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
25938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
25939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
25940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
25941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
25942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
25943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
25944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
25945 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
25946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
25947 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
25949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
25950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
25953 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
25956 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
25959 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
25960 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
25963 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
25964 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
25966 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
25967 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
25968 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
25969 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
25970 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
25972 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
25973 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
25974 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
25975 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
25976 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
25977 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
25978 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
25980 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
25981 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
25982 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
25984 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
25985 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
25986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
25987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
25988 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
25989 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
25990 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
25991 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
25994 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
25995 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
25996 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
25997 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
25998 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
25999 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26001 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26002 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26004 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26005 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26006 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26007 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26008 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26009 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26012 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26013 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26014 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26015 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26016 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26017 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26018 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26019 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26022 /* Builtins with variable number of arguments. */
26023 static const struct builtin_description bdesc_args[] =
26025 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26026 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26027 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26028 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26029 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26030 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26031 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26062 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26063 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26066 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26067 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26068 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26069 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
26070 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
26072 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
26073 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
26074 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
26076 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
26078 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26079 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26080 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
26081 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26082 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26083 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
26085 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26086 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26087 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
26088 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26089 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26090 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
26092 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26093 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26098 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
26099 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
26100 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26101 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26103 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26104 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26105 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26106 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26107 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26108 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26109 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26110 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26111 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26112 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26113 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26114 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26115 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26116 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26117 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26120 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
26121 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
26122 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
26123 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26124 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26125 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
26129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26130 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26132 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
26135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
26136 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
26137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
26138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
26139 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
26141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26143 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26144 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26145 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26146 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
26153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
26154 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
26155 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26156 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26157 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26158 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
26159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
26160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
26161 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26162 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
26163 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26164 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
26165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
26166 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
26167 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26168 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
26169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
26170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
26171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26175 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26176 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26180 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26181 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26182 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26183 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26185 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26187 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26190 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26191 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
26194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
26195 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
26197 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
26199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26203 /* SSE MMX or 3Dnow!A */
26204 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26205 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26206 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26208 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26209 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26210 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26211 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26213 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
26214 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
26216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
26219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
26222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
26223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
26224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
26225 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
26227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
26228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
26229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
26230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
26231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
26233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
26235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
26236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
26237 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
26238 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
26240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
26241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
26242 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
26244 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26245 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26246 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26247 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26253 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
26254 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
26255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
26256 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
26258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
26260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
26261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
26262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
26266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
26267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
26268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
26270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
26271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
26272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26275 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26279 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26281 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26282 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26284 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26287 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26288 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26290 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
26292 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26293 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26294 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26295 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26296 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26297 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26298 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26299 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26310 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26311 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
26313 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26315 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26316 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26328 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26329 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26330 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26333 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26334 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26335 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26336 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26337 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26338 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26339 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26340 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
26343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
26344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
26346 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
26349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
26350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
26352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
26354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
26355 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
26356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
26357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
26359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
26360 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26361 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26362 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
26363 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26364 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26365 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
26367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
26368 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26369 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26370 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
26371 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26372 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26373 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
26375 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26376 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26377 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26378 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
26381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
26382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
26384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
26386 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
26387 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
26389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
26392 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
26393 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
26396 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
26397 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26399 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26400 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26401 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26402 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26403 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26404 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
26408 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
26409 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
26410 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
26411 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
26412 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
26414 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26415 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26416 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26417 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26418 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26419 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26420 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26421 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26422 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26423 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26424 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26425 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26426 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
26427 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
26428 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26429 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26430 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26431 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26432 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26433 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26434 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26435 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26436 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26437 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26440 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
26441 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
26444 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26445 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26446 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
26447 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
26448 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26449 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26450 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26451 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
26452 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
26453 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
26455 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
26456 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
26457 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
26458 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
26459 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
26460 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
26461 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
26462 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
26463 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
26464 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
26465 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
26466 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
26467 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
26469 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
26470 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26471 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26472 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26473 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26474 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26475 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26476 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26477 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26478 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26479 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
26480 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26483 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
26484 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
26485 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26486 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26488 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
26489 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
26490 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
26491 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
26493 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
26494 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
26496 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
26497 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
26499 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
26500 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
26501 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
26502 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
26504 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
26505 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
26507 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26508 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
26510 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
26511 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
26512 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
26515 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26516 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
26517 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
26518 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26519 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26522 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
26523 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
26524 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
26525 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26528 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
26529 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
26531 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26532 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26533 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26534 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26537 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
26540 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26541 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26544 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26545 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26548 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26554 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26555 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26556 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26557 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26558 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26559 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26560 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26561 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26562 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26563 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26564 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26565 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
26568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
26569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
26570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
26572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
26573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
26574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
26575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
26576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
26577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
26578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
26579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
26584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
26585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
26586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
26587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
26588 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
26589 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
26590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
26591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
26592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
26593 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
26594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
26595 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
26596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
26597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
26598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
26599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
26600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
26601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
26602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
26603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
26604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
26605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
26607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
26611 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
26612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26613 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26615 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
26620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
26622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
26623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
26624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
26625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
26627 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
26628 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
26630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
26631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
26633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
26634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
26635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
26636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
26638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
26639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
26641 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
26642 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
26644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
26650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
26651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
26652 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
26653 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
26654 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
26656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
26657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
26658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
26659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
26660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
26661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
26662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
26663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
26664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
26665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
26666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
26667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
26668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
26669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
26670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
26672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
26673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
26675 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
26676 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
26678 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
26681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
26682 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
26683 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
26684 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
26685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
26686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
26687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
26688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
26689 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26690 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26691 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26692 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
26698 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
26703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
26704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
26719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
26720 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26721 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26722 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26723 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26724 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26725 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26726 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26727 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26728 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26729 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26730 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26731 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
26733 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
26734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
26735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
26736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
26737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
26738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
26739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
26740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
26741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
26742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
26743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
26744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
26745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mulv4siv4di3 , "__builtin_ia32_pmuldq256" , IX86_BUILTIN_PMULDQ256 , UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
26746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_umulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26747 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26748 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26749 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26750 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_umulv4siv4di3 , "__builtin_ia32_pmuludq256" , IX86_BUILTIN_PMULUDQ256 , UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
26752 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
26754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
26756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
26757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
26758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
26762 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
26763 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
26764 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
26765 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
26766 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
26767 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
26768 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
26769 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
26770 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
26771 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
26772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
26773 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
26774 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
26775 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
26776 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
26777 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
26778 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
26779 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26780 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26781 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26782 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
26792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
26793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26795 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
26798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
26799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
26800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
26801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
26802 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
26803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
26804 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
26805 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
26806 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
26807 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
26808 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
26809 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
26810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
26812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
26813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
26814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
26815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
26816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
26817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
26824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26825 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
26826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26828 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
26831 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26832 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26833 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
26836 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26837 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26840 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
26841 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
26842 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
26843 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
26846 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26847 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26848 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26849 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26850 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
26851 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
26854 /* FMA4 and XOP. */
26855 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
26856 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
26857 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
26858 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
26859 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
26860 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
26861 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
26862 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
26863 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
26864 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
26865 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
26866 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
26867 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
26868 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
26869 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
26870 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
26871 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
26872 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
26873 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
26874 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
26875 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
26876 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
26877 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
26878 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
26879 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
26880 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
26881 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
26882 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
26883 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
26884 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
26885 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
26886 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
26887 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
26888 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
26889 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
26890 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
26891 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
26892 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
26893 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
26894 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
26895 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
26896 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
26897 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
26898 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
26899 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
26900 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
26901 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
26902 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
26903 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
26904 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
26905 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
26906 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
26908 static const struct builtin_description bdesc_multi_arg[] =
26910 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmadd_v4sf,
26911 "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS,
26912 UNKNOWN, (int)MULTI_ARG_3_SF },
26913 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmadd_v2df,
26914 "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD,
26915 UNKNOWN, (int)MULTI_ARG_3_DF },
26917 { OPTION_MASK_ISA_FMA, CODE_FOR_fmai_vmfmadd_v4sf,
26918 "__builtin_ia32_vfmaddss3", IX86_BUILTIN_VFMADDSS3,
26919 UNKNOWN, (int)MULTI_ARG_3_SF },
26920 { OPTION_MASK_ISA_FMA, CODE_FOR_fmai_vmfmadd_v2df,
26921 "__builtin_ia32_vfmaddsd3", IX86_BUILTIN_VFMADDSD3,
26922 UNKNOWN, (int)MULTI_ARG_3_DF },
26924 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmadd_v4sf,
26925 "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS,
26926 UNKNOWN, (int)MULTI_ARG_3_SF },
26927 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmadd_v2df,
26928 "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD,
26929 UNKNOWN, (int)MULTI_ARG_3_DF },
26930 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmadd_v8sf,
26931 "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256,
26932 UNKNOWN, (int)MULTI_ARG_3_SF2 },
26933 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmadd_v4df,
26934 "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256,
26935 UNKNOWN, (int)MULTI_ARG_3_DF2 },
26937 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fmaddsub_v4sf,
26938 "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS,
26939 UNKNOWN, (int)MULTI_ARG_3_SF },
26940 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fmaddsub_v2df,
26941 "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD,
26942 UNKNOWN, (int)MULTI_ARG_3_DF },
26943 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fmaddsub_v8sf,
26944 "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256,
26945 UNKNOWN, (int)MULTI_ARG_3_SF2 },
26946 { OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4, CODE_FOR_fmaddsub_v4df,
26947 "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256,
26948 UNKNOWN, (int)MULTI_ARG_3_DF2 },
26950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
26951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
26952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
26953 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
26954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
26955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
26956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
26958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
26959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
26960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
26961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
26962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
26963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
26964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
26966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
26968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
26969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
26970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
26971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
26972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
26973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
26974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
26975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
26976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
26977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
26978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
26979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
26981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
26982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
26983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
26984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
26985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
26986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
26987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
26988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
26989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
26990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
26991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
26992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
26993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
26994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
26995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
26996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
26998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
26999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
27049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
27050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
27051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
27053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
27054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
27057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
27058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
27059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
27061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
27062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27064 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
27065 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
27066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
27067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
27069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
27070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
27071 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
27072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
27073 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
27074 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
27075 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
27077 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27078 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
27079 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
27080 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
27081 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
27082 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
27083 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
27085 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
27086 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
27087 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
27088 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
27089 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
27090 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
27091 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
27092 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
27094 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
27095 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
27096 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
27097 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
27098 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
27099 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
27100 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
27101 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
27103 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
27104 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
27105 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
27106 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
27110 /* TM vector builtins. */
27112 /* Reuse the existing x86-specific `struct builtin_description' cause
27113 we're lazy. Add casts to make them fit. */
27114 static const struct builtin_description bdesc_tm[] =
27116 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27117 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27118 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27119 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27120 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27121 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27122 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27130 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27132 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27133 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27134 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27135 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27136 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27137 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27138 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27140 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
27142 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
27145 /* TM callbacks. */
27147 /* Return the builtin decl needed to load a vector of TYPE. */
27150 ix86_builtin_tm_load (tree type)
27152 if (TREE_CODE (type) == VECTOR_TYPE)
27154 switch (tree_low_cst (TYPE_SIZE (type), 1))
27157 return builtin_decl_explicit (BUILT_IN_TM_LOAD_M64);
27159 return builtin_decl_explicit (BUILT_IN_TM_LOAD_M128);
27161 return builtin_decl_explicit (BUILT_IN_TM_LOAD_M256);
27167 /* Return the builtin decl needed to store a vector of TYPE. */
27170 ix86_builtin_tm_store (tree type)
27172 if (TREE_CODE (type) == VECTOR_TYPE)
27174 switch (tree_low_cst (TYPE_SIZE (type), 1))
27177 return builtin_decl_explicit (BUILT_IN_TM_STORE_M64);
27179 return builtin_decl_explicit (BUILT_IN_TM_STORE_M128);
27181 return builtin_decl_explicit (BUILT_IN_TM_STORE_M256);
27187 /* Initialize the transactional memory vector load/store builtins. */
27190 ix86_init_tm_builtins (void)
27192 enum ix86_builtin_func_type ftype;
27193 const struct builtin_description *d;
27196 tree attrs_load, attrs_type_load, attrs_store, attrs_type_store;
27197 tree attrs_log, attrs_type_log;
27202 /* If there are no builtins defined, we must be compiling in a
27203 language without trans-mem support. */
27204 if (!builtin_decl_explicit_p (BUILT_IN_TM_LOAD_1))
27207 /* Use whatever attributes a normal TM load has. */
27208 decl = builtin_decl_explicit (BUILT_IN_TM_LOAD_1);
27209 attrs_load = DECL_ATTRIBUTES (decl);
27210 attrs_type_load = TYPE_ATTRIBUTES (TREE_TYPE (decl));
27211 /* Use whatever attributes a normal TM store has. */
27212 decl = builtin_decl_explicit (BUILT_IN_TM_STORE_1);
27213 attrs_store = DECL_ATTRIBUTES (decl);
27214 attrs_type_store = TYPE_ATTRIBUTES (TREE_TYPE (decl));
27215 /* Use whatever attributes a normal TM log has. */
27216 decl = builtin_decl_explicit (BUILT_IN_TM_LOG);
27217 attrs_log = DECL_ATTRIBUTES (decl);
27218 attrs_type_log = TYPE_ATTRIBUTES (TREE_TYPE (decl));
27220 for (i = 0, d = bdesc_tm;
27221 i < ARRAY_SIZE (bdesc_tm);
27224 if ((d->mask & ix86_isa_flags) != 0
27225 || (lang_hooks.builtin_function
27226 == lang_hooks.builtin_function_ext_scope))
27228 tree type, attrs, attrs_type;
27229 enum built_in_function code = (enum built_in_function) d->code;
27231 ftype = (enum ix86_builtin_func_type) d->flag;
27232 type = ix86_get_builtin_func_type (ftype);
27234 if (BUILTIN_TM_LOAD_P (code))
27236 attrs = attrs_load;
27237 attrs_type = attrs_type_load;
27239 else if (BUILTIN_TM_STORE_P (code))
27241 attrs = attrs_store;
27242 attrs_type = attrs_type_store;
27247 attrs_type = attrs_type_log;
27249 decl = add_builtin_function (d->name, type, code, BUILT_IN_NORMAL,
27250 /* The builtin without the prefix for
27251 calling it directly. */
27252 d->name + strlen ("__builtin_"),
27254 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
27255 set the TYPE_ATTRIBUTES. */
27256 decl_attributes (&TREE_TYPE (decl), attrs_type, ATTR_FLAG_BUILT_IN);
27258 set_builtin_decl (code, decl, false);
27263 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
27264 in the current target ISA to allow the user to compile particular modules
27265 with different target specific options that differ from the command line
27268 ix86_init_mmx_sse_builtins (void)
27270 const struct builtin_description * d;
27271 enum ix86_builtin_func_type ftype;
27274 /* Add all special builtins with variable number of operands. */
27275 for (i = 0, d = bdesc_special_args;
27276 i < ARRAY_SIZE (bdesc_special_args);
27282 ftype = (enum ix86_builtin_func_type) d->flag;
27283 def_builtin (d->mask, d->name, ftype, d->code);
27286 /* Add all builtins with variable number of operands. */
27287 for (i = 0, d = bdesc_args;
27288 i < ARRAY_SIZE (bdesc_args);
27294 ftype = (enum ix86_builtin_func_type) d->flag;
27295 def_builtin_const (d->mask, d->name, ftype, d->code);
27298 /* pcmpestr[im] insns. */
27299 for (i = 0, d = bdesc_pcmpestr;
27300 i < ARRAY_SIZE (bdesc_pcmpestr);
27303 if (d->code == IX86_BUILTIN_PCMPESTRM128)
27304 ftype = V16QI_FTYPE_V16QI_INT_V16QI_INT_INT;
27306 ftype = INT_FTYPE_V16QI_INT_V16QI_INT_INT;
27307 def_builtin_const (d->mask, d->name, ftype, d->code);
27310 /* pcmpistr[im] insns. */
27311 for (i = 0, d = bdesc_pcmpistr;
27312 i < ARRAY_SIZE (bdesc_pcmpistr);
27315 if (d->code == IX86_BUILTIN_PCMPISTRM128)
27316 ftype = V16QI_FTYPE_V16QI_V16QI_INT;
27318 ftype = INT_FTYPE_V16QI_V16QI_INT;
27319 def_builtin_const (d->mask, d->name, ftype, d->code);
27322 /* comi/ucomi insns. */
27323 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
27325 if (d->mask == OPTION_MASK_ISA_SSE2)
27326 ftype = INT_FTYPE_V2DF_V2DF;
27328 ftype = INT_FTYPE_V4SF_V4SF;
27329 def_builtin_const (d->mask, d->name, ftype, d->code);
27333 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr",
27334 VOID_FTYPE_UNSIGNED, IX86_BUILTIN_LDMXCSR);
27335 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr",
27336 UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR);
27338 /* SSE or 3DNow!A */
27339 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
27340 "__builtin_ia32_maskmovq", VOID_FTYPE_V8QI_V8QI_PCHAR,
27341 IX86_BUILTIN_MASKMOVQ);
27344 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu",
27345 VOID_FTYPE_V16QI_V16QI_PCHAR, IX86_BUILTIN_MASKMOVDQU);
27347 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush",
27348 VOID_FTYPE_PCVOID, IX86_BUILTIN_CLFLUSH);
27349 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence",
27350 VOID_FTYPE_VOID, IX86_BUILTIN_MFENCE);
27353 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor",
27354 VOID_FTYPE_PCVOID_UNSIGNED_UNSIGNED, IX86_BUILTIN_MONITOR);
27355 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait",
27356 VOID_FTYPE_UNSIGNED_UNSIGNED, IX86_BUILTIN_MWAIT);
27359 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128",
27360 V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESENC128);
27361 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128",
27362 V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESENCLAST128);
27363 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128",
27364 V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESDEC128);
27365 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128",
27366 V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESDECLAST128);
27367 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128",
27368 V2DI_FTYPE_V2DI, IX86_BUILTIN_AESIMC128);
27369 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128",
27370 V2DI_FTYPE_V2DI_INT, IX86_BUILTIN_AESKEYGENASSIST128);
27373 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128",
27374 V2DI_FTYPE_V2DI_V2DI_INT, IX86_BUILTIN_PCLMULQDQ128);
27377 def_builtin (OPTION_MASK_ISA_RDRND, "__builtin_ia32_rdrand16_step",
27378 INT_FTYPE_PUSHORT, IX86_BUILTIN_RDRAND16_STEP);
27379 def_builtin (OPTION_MASK_ISA_RDRND, "__builtin_ia32_rdrand32_step",
27380 INT_FTYPE_PUNSIGNED, IX86_BUILTIN_RDRAND32_STEP);
27381 def_builtin (OPTION_MASK_ISA_RDRND | OPTION_MASK_ISA_64BIT,
27382 "__builtin_ia32_rdrand64_step", INT_FTYPE_PULONGLONG,
27383 IX86_BUILTIN_RDRAND64_STEP);
27386 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2df",
27387 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
27388 IX86_BUILTIN_GATHERSIV2DF);
27390 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4df",
27391 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
27392 IX86_BUILTIN_GATHERSIV4DF);
27394 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2df",
27395 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
27396 IX86_BUILTIN_GATHERDIV2DF);
27398 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4df",
27399 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
27400 IX86_BUILTIN_GATHERDIV4DF);
27402 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4sf",
27403 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
27404 IX86_BUILTIN_GATHERSIV4SF);
27406 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8sf",
27407 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
27408 IX86_BUILTIN_GATHERSIV8SF);
27410 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf",
27411 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
27412 IX86_BUILTIN_GATHERDIV4SF);
27414 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf256",
27415 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
27416 IX86_BUILTIN_GATHERDIV8SF);
27418 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2di",
27419 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
27420 IX86_BUILTIN_GATHERSIV2DI);
27422 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4di",
27423 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
27424 IX86_BUILTIN_GATHERSIV4DI);
27426 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2di",
27427 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
27428 IX86_BUILTIN_GATHERDIV2DI);
27430 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4di",
27431 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
27432 IX86_BUILTIN_GATHERDIV4DI);
27434 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4si",
27435 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
27436 IX86_BUILTIN_GATHERSIV4SI);
27438 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8si",
27439 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
27440 IX86_BUILTIN_GATHERSIV8SI);
27442 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si",
27443 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
27444 IX86_BUILTIN_GATHERDIV4SI);
27446 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si256",
27447 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
27448 IX86_BUILTIN_GATHERDIV8SI);
27450 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ",
27451 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
27452 IX86_BUILTIN_GATHERALTSIV4DF);
27454 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ",
27455 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
27456 IX86_BUILTIN_GATHERALTDIV8SF);
27458 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ",
27459 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
27460 IX86_BUILTIN_GATHERALTSIV4DI);
27462 def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ",
27463 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
27464 IX86_BUILTIN_GATHERALTDIV8SI);
27466 /* MMX access to the vec_init patterns. */
27467 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si",
27468 V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
27470 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi",
27471 V4HI_FTYPE_HI_HI_HI_HI,
27472 IX86_BUILTIN_VEC_INIT_V4HI);
27474 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi",
27475 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
27476 IX86_BUILTIN_VEC_INIT_V8QI);
27478 /* Access to the vec_extract patterns. */
27479 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df",
27480 DOUBLE_FTYPE_V2DF_INT, IX86_BUILTIN_VEC_EXT_V2DF);
27481 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di",
27482 DI_FTYPE_V2DI_INT, IX86_BUILTIN_VEC_EXT_V2DI);
27483 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf",
27484 FLOAT_FTYPE_V4SF_INT, IX86_BUILTIN_VEC_EXT_V4SF);
27485 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si",
27486 SI_FTYPE_V4SI_INT, IX86_BUILTIN_VEC_EXT_V4SI);
27487 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi",
27488 HI_FTYPE_V8HI_INT, IX86_BUILTIN_VEC_EXT_V8HI);
27490 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
27491 "__builtin_ia32_vec_ext_v4hi",
27492 HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
27494 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si",
27495 SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);
27497 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi",
27498 QI_FTYPE_V16QI_INT, IX86_BUILTIN_VEC_EXT_V16QI);
27500 /* Access to the vec_set patterns. */
27501 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT,
27502 "__builtin_ia32_vec_set_v2di",
27503 V2DI_FTYPE_V2DI_DI_INT, IX86_BUILTIN_VEC_SET_V2DI);
27505 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf",
27506 V4SF_FTYPE_V4SF_FLOAT_INT, IX86_BUILTIN_VEC_SET_V4SF);
27508 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si",
27509 V4SI_FTYPE_V4SI_SI_INT, IX86_BUILTIN_VEC_SET_V4SI);
27511 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi",
27512 V8HI_FTYPE_V8HI_HI_INT, IX86_BUILTIN_VEC_SET_V8HI);
27514 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
27515 "__builtin_ia32_vec_set_v4hi",
27516 V4HI_FTYPE_V4HI_HI_INT, IX86_BUILTIN_VEC_SET_V4HI);
27518 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi",
27519 V16QI_FTYPE_V16QI_QI_INT, IX86_BUILTIN_VEC_SET_V16QI);
27521 /* Add FMA4 multi-arg argument instructions */
27522 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
27527 ftype = (enum ix86_builtin_func_type) d->flag;
27528 def_builtin_const (d->mask, d->name, ftype, d->code);
27532 /* Internal method for ix86_init_builtins. */
27535 ix86_init_builtins_va_builtins_abi (void)
27537 tree ms_va_ref, sysv_va_ref;
27538 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
27539 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
27540 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
27541 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
27545 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
27546 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
27547 ms_va_ref = build_reference_type (ms_va_list_type_node);
27549 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
27552 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
27553 fnvoid_va_start_ms =
27554 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
27555 fnvoid_va_end_sysv =
27556 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
27557 fnvoid_va_start_sysv =
27558 build_varargs_function_type_list (void_type_node, sysv_va_ref,
27560 fnvoid_va_copy_ms =
27561 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
27563 fnvoid_va_copy_sysv =
27564 build_function_type_list (void_type_node, sysv_va_ref,
27565 sysv_va_ref, NULL_TREE);
27567 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
27568 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
27569 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
27570 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
27571 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
27572 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
27573 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
27574 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
27575 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
27576 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
27577 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
27578 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
27582 ix86_init_builtin_types (void)
27584 tree float128_type_node, float80_type_node;
27586 /* The __float80 type. */
27587 float80_type_node = long_double_type_node;
27588 if (TYPE_MODE (float80_type_node) != XFmode)
27590 /* The __float80 type. */
27591 float80_type_node = make_node (REAL_TYPE);
27593 TYPE_PRECISION (float80_type_node) = 80;
27594 layout_type (float80_type_node);
27596 lang_hooks.types.register_builtin_type (float80_type_node, "__float80");
27598 /* The __float128 type. */
27599 float128_type_node = make_node (REAL_TYPE);
27600 TYPE_PRECISION (float128_type_node) = 128;
27601 layout_type (float128_type_node);
27602 lang_hooks.types.register_builtin_type (float128_type_node, "__float128");
27604 /* This macro is built by i386-builtin-types.awk. */
27605 DEFINE_BUILTIN_PRIMITIVE_TYPES;
27609 ix86_init_builtins (void)
27613 ix86_init_builtin_types ();
27615 /* TFmode support builtins. */
27616 def_builtin_const (0, "__builtin_infq",
27617 FLOAT128_FTYPE_VOID, IX86_BUILTIN_INFQ);
27618 def_builtin_const (0, "__builtin_huge_valq",
27619 FLOAT128_FTYPE_VOID, IX86_BUILTIN_HUGE_VALQ);
27621 /* We will expand them to normal call if SSE2 isn't available since
27622 they are used by libgcc. */
27623 t = ix86_get_builtin_func_type (FLOAT128_FTYPE_FLOAT128);
27624 t = add_builtin_function ("__builtin_fabsq", t, IX86_BUILTIN_FABSQ,
27625 BUILT_IN_MD, "__fabstf2", NULL_TREE);
27626 TREE_READONLY (t) = 1;
27627 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = t;
27629 t = ix86_get_builtin_func_type (FLOAT128_FTYPE_FLOAT128_FLOAT128);
27630 t = add_builtin_function ("__builtin_copysignq", t, IX86_BUILTIN_COPYSIGNQ,
27631 BUILT_IN_MD, "__copysigntf3", NULL_TREE);
27632 TREE_READONLY (t) = 1;
27633 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = t;
27635 ix86_init_tm_builtins ();
27636 ix86_init_mmx_sse_builtins ();
27639 ix86_init_builtins_va_builtins_abi ();
27641 #ifdef SUBTARGET_INIT_BUILTINS
27642 SUBTARGET_INIT_BUILTINS;
27646 /* Return the ix86 builtin for CODE. */
27649 ix86_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
27651 if (code >= IX86_BUILTIN_MAX)
27652 return error_mark_node;
27654 return ix86_builtins[code];
27657 /* Errors in the source file can cause expand_expr to return const0_rtx
27658 where we expect a vector. To avoid crashing, use one of the vector
27659 clear instructions. */
27661 safe_vector_operand (rtx x, enum machine_mode mode)
27663 if (x == const0_rtx)
27664 x = CONST0_RTX (mode);
27668 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
27671 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
27674 tree arg0 = CALL_EXPR_ARG (exp, 0);
27675 tree arg1 = CALL_EXPR_ARG (exp, 1);
27676 rtx op0 = expand_normal (arg0);
27677 rtx op1 = expand_normal (arg1);
27678 enum machine_mode tmode = insn_data[icode].operand[0].mode;
27679 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
27680 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
27682 if (VECTOR_MODE_P (mode0))
27683 op0 = safe_vector_operand (op0, mode0);
27684 if (VECTOR_MODE_P (mode1))
27685 op1 = safe_vector_operand (op1, mode1);
27687 if (optimize || !target
27688 || GET_MODE (target) != tmode
27689 || !insn_data[icode].operand[0].predicate (target, tmode))
27690 target = gen_reg_rtx (tmode);
27692 if (GET_MODE (op1) == SImode && mode1 == TImode)
27694 rtx x = gen_reg_rtx (V4SImode);
27695 emit_insn (gen_sse2_loadd (x, op1));
27696 op1 = gen_lowpart (TImode, x);
27699 if (!insn_data[icode].operand[1].predicate (op0, mode0))
27700 op0 = copy_to_mode_reg (mode0, op0);
27701 if (!insn_data[icode].operand[2].predicate (op1, mode1))
27702 op1 = copy_to_mode_reg (mode1, op1);
27704 pat = GEN_FCN (icode) (target, op0, op1);
27713 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
27716 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
27717 enum ix86_builtin_func_type m_type,
27718 enum rtx_code sub_code)
27723 bool comparison_p = false;
27725 bool last_arg_constant = false;
27726 int num_memory = 0;
27729 enum machine_mode mode;
27732 enum machine_mode tmode = insn_data[icode].operand[0].mode;
27736 case MULTI_ARG_4_DF2_DI_I:
27737 case MULTI_ARG_4_DF2_DI_I1:
27738 case MULTI_ARG_4_SF2_SI_I:
27739 case MULTI_ARG_4_SF2_SI_I1:
27741 last_arg_constant = true;
27744 case MULTI_ARG_3_SF:
27745 case MULTI_ARG_3_DF:
27746 case MULTI_ARG_3_SF2:
27747 case MULTI_ARG_3_DF2:
27748 case MULTI_ARG_3_DI:
27749 case MULTI_ARG_3_SI:
27750 case MULTI_ARG_3_SI_DI:
27751 case MULTI_ARG_3_HI:
27752 case MULTI_ARG_3_HI_SI:
27753 case MULTI_ARG_3_QI:
27754 case MULTI_ARG_3_DI2:
27755 case MULTI_ARG_3_SI2:
27756 case MULTI_ARG_3_HI2:
27757 case MULTI_ARG_3_QI2:
27761 case MULTI_ARG_2_SF:
27762 case MULTI_ARG_2_DF:
27763 case MULTI_ARG_2_DI:
27764 case MULTI_ARG_2_SI:
27765 case MULTI_ARG_2_HI:
27766 case MULTI_ARG_2_QI:
27770 case MULTI_ARG_2_DI_IMM:
27771 case MULTI_ARG_2_SI_IMM:
27772 case MULTI_ARG_2_HI_IMM:
27773 case MULTI_ARG_2_QI_IMM:
27775 last_arg_constant = true;
27778 case MULTI_ARG_1_SF:
27779 case MULTI_ARG_1_DF:
27780 case MULTI_ARG_1_SF2:
27781 case MULTI_ARG_1_DF2:
27782 case MULTI_ARG_1_DI:
27783 case MULTI_ARG_1_SI:
27784 case MULTI_ARG_1_HI:
27785 case MULTI_ARG_1_QI:
27786 case MULTI_ARG_1_SI_DI:
27787 case MULTI_ARG_1_HI_DI:
27788 case MULTI_ARG_1_HI_SI:
27789 case MULTI_ARG_1_QI_DI:
27790 case MULTI_ARG_1_QI_SI:
27791 case MULTI_ARG_1_QI_HI:
27795 case MULTI_ARG_2_DI_CMP:
27796 case MULTI_ARG_2_SI_CMP:
27797 case MULTI_ARG_2_HI_CMP:
27798 case MULTI_ARG_2_QI_CMP:
27800 comparison_p = true;
27803 case MULTI_ARG_2_SF_TF:
27804 case MULTI_ARG_2_DF_TF:
27805 case MULTI_ARG_2_DI_TF:
27806 case MULTI_ARG_2_SI_TF:
27807 case MULTI_ARG_2_HI_TF:
27808 case MULTI_ARG_2_QI_TF:
27814 gcc_unreachable ();
27817 if (optimize || !target
27818 || GET_MODE (target) != tmode
27819 || !insn_data[icode].operand[0].predicate (target, tmode))
27820 target = gen_reg_rtx (tmode);
27822 gcc_assert (nargs <= 4);
27824 for (i = 0; i < nargs; i++)
27826 tree arg = CALL_EXPR_ARG (exp, i);
27827 rtx op = expand_normal (arg);
27828 int adjust = (comparison_p) ? 1 : 0;
27829 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
27831 if (last_arg_constant && i == nargs - 1)
27833 if (!insn_data[icode].operand[i + 1].predicate (op, mode))
27835 enum insn_code new_icode = icode;
27838 case CODE_FOR_xop_vpermil2v2df3:
27839 case CODE_FOR_xop_vpermil2v4sf3:
27840 case CODE_FOR_xop_vpermil2v4df3:
27841 case CODE_FOR_xop_vpermil2v8sf3:
27842 error ("the last argument must be a 2-bit immediate");
27843 return gen_reg_rtx (tmode);
27844 case CODE_FOR_xop_rotlv2di3:
27845 new_icode = CODE_FOR_rotlv2di3;
27847 case CODE_FOR_xop_rotlv4si3:
27848 new_icode = CODE_FOR_rotlv4si3;
27850 case CODE_FOR_xop_rotlv8hi3:
27851 new_icode = CODE_FOR_rotlv8hi3;
27853 case CODE_FOR_xop_rotlv16qi3:
27854 new_icode = CODE_FOR_rotlv16qi3;
27856 if (CONST_INT_P (op))
27858 int mask = GET_MODE_BITSIZE (GET_MODE_INNER (tmode)) - 1;
27859 op = GEN_INT (INTVAL (op) & mask);
27860 gcc_checking_assert
27861 (insn_data[icode].operand[i + 1].predicate (op, mode));
27865 gcc_checking_assert
27867 && insn_data[new_icode].operand[0].mode == tmode
27868 && insn_data[new_icode].operand[1].mode == tmode
27869 && insn_data[new_icode].operand[2].mode == mode
27870 && insn_data[new_icode].operand[0].predicate
27871 == insn_data[icode].operand[0].predicate
27872 && insn_data[new_icode].operand[1].predicate
27873 == insn_data[icode].operand[1].predicate);
27879 gcc_unreachable ();
27886 if (VECTOR_MODE_P (mode))
27887 op = safe_vector_operand (op, mode);
27889 /* If we aren't optimizing, only allow one memory operand to be
27891 if (memory_operand (op, mode))
27894 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
27897 || !insn_data[icode].operand[i+adjust+1].predicate (op, mode)
27899 op = force_reg (mode, op);
27903 args[i].mode = mode;
27909 pat = GEN_FCN (icode) (target, args[0].op);
27914 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
27915 GEN_INT ((int)sub_code));
27916 else if (! comparison_p)
27917 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
27920 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
27924 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
27929 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
27933 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op, args[3].op);
27937 gcc_unreachable ();
27947 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
27948 insns with vec_merge. */
27951 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
27955 tree arg0 = CALL_EXPR_ARG (exp, 0);
27956 rtx op1, op0 = expand_normal (arg0);
27957 enum machine_mode tmode = insn_data[icode].operand[0].mode;
27958 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
27960 if (optimize || !target
27961 || GET_MODE (target) != tmode
27962 || !insn_data[icode].operand[0].predicate (target, tmode))
27963 target = gen_reg_rtx (tmode);
27965 if (VECTOR_MODE_P (mode0))
27966 op0 = safe_vector_operand (op0, mode0);
27968 if ((optimize && !register_operand (op0, mode0))
27969 || !insn_data[icode].operand[1].predicate (op0, mode0))
27970 op0 = copy_to_mode_reg (mode0, op0);
27973 if (!insn_data[icode].operand[2].predicate (op1, mode0))
27974 op1 = copy_to_mode_reg (mode0, op1);
27976 pat = GEN_FCN (icode) (target, op0, op1);
27983 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
27986 ix86_expand_sse_compare (const struct builtin_description *d,
27987 tree exp, rtx target, bool swap)
27990 tree arg0 = CALL_EXPR_ARG (exp, 0);
27991 tree arg1 = CALL_EXPR_ARG (exp, 1);
27992 rtx op0 = expand_normal (arg0);
27993 rtx op1 = expand_normal (arg1);
27995 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
27996 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
27997 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
27998 enum rtx_code comparison = d->comparison;
28000 if (VECTOR_MODE_P (mode0))
28001 op0 = safe_vector_operand (op0, mode0);
28002 if (VECTOR_MODE_P (mode1))
28003 op1 = safe_vector_operand (op1, mode1);
28005 /* Swap operands if we have a comparison that isn't available in
28009 rtx tmp = gen_reg_rtx (mode1);
28010 emit_move_insn (tmp, op1);
28015 if (optimize || !target
28016 || GET_MODE (target) != tmode
28017 || !insn_data[d->icode].operand[0].predicate (target, tmode))
28018 target = gen_reg_rtx (tmode);
28020 if ((optimize && !register_operand (op0, mode0))
28021 || !insn_data[d->icode].operand[1].predicate (op0, mode0))
28022 op0 = copy_to_mode_reg (mode0, op0);
28023 if ((optimize && !register_operand (op1, mode1))
28024 || !insn_data[d->icode].operand[2].predicate (op1, mode1))
28025 op1 = copy_to_mode_reg (mode1, op1);
28027 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
28028 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
28035 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
28038 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
28042 tree arg0 = CALL_EXPR_ARG (exp, 0);
28043 tree arg1 = CALL_EXPR_ARG (exp, 1);
28044 rtx op0 = expand_normal (arg0);
28045 rtx op1 = expand_normal (arg1);
28046 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
28047 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
28048 enum rtx_code comparison = d->comparison;
28050 if (VECTOR_MODE_P (mode0))
28051 op0 = safe_vector_operand (op0, mode0);
28052 if (VECTOR_MODE_P (mode1))
28053 op1 = safe_vector_operand (op1, mode1);
28055 /* Swap operands if we have a comparison that isn't available in
28057 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
28064 target = gen_reg_rtx (SImode);
28065 emit_move_insn (target, const0_rtx);
28066 target = gen_rtx_SUBREG (QImode, target, 0);
28068 if ((optimize && !register_operand (op0, mode0))
28069 || !insn_data[d->icode].operand[0].predicate (op0, mode0))
28070 op0 = copy_to_mode_reg (mode0, op0);
28071 if ((optimize && !register_operand (op1, mode1))
28072 || !insn_data[d->icode].operand[1].predicate (op1, mode1))
28073 op1 = copy_to_mode_reg (mode1, op1);
28075 pat = GEN_FCN (d->icode) (op0, op1);
28079 emit_insn (gen_rtx_SET (VOIDmode,
28080 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
28081 gen_rtx_fmt_ee (comparison, QImode,
28085 return SUBREG_REG (target);
28088 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
28091 ix86_expand_sse_round (const struct builtin_description *d, tree exp,
28095 tree arg0 = CALL_EXPR_ARG (exp, 0);
28096 rtx op1, op0 = expand_normal (arg0);
28097 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
28098 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
28100 if (optimize || target == 0
28101 || GET_MODE (target) != tmode
28102 || !insn_data[d->icode].operand[0].predicate (target, tmode))
28103 target = gen_reg_rtx (tmode);
28105 if (VECTOR_MODE_P (mode0))
28106 op0 = safe_vector_operand (op0, mode0);
28108 if ((optimize && !register_operand (op0, mode0))
28109 || !insn_data[d->icode].operand[0].predicate (op0, mode0))
28110 op0 = copy_to_mode_reg (mode0, op0);
28112 op1 = GEN_INT (d->comparison);
28114 pat = GEN_FCN (d->icode) (target, op0, op1);
28122 ix86_expand_sse_round_vec_pack_sfix (const struct builtin_description *d,
28123 tree exp, rtx target)
28126 tree arg0 = CALL_EXPR_ARG (exp, 0);
28127 tree arg1 = CALL_EXPR_ARG (exp, 1);
28128 rtx op0 = expand_normal (arg0);
28129 rtx op1 = expand_normal (arg1);
28131 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
28132 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
28133 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
28135 if (optimize || target == 0
28136 || GET_MODE (target) != tmode
28137 || !insn_data[d->icode].operand[0].predicate (target, tmode))
28138 target = gen_reg_rtx (tmode);
28140 op0 = safe_vector_operand (op0, mode0);
28141 op1 = safe_vector_operand (op1, mode1);
28143 if ((optimize && !register_operand (op0, mode0))
28144 || !insn_data[d->icode].operand[0].predicate (op0, mode0))
28145 op0 = copy_to_mode_reg (mode0, op0);
28146 if ((optimize && !register_operand (op1, mode1))
28147 || !insn_data[d->icode].operand[1].predicate (op1, mode1))
28148 op1 = copy_to_mode_reg (mode1, op1);
28150 op2 = GEN_INT (d->comparison);
28152 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
28159 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
28162 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
28166 tree arg0 = CALL_EXPR_ARG (exp, 0);
28167 tree arg1 = CALL_EXPR_ARG (exp, 1);
28168 rtx op0 = expand_normal (arg0);
28169 rtx op1 = expand_normal (arg1);
28170 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
28171 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
28172 enum rtx_code comparison = d->comparison;
28174 if (VECTOR_MODE_P (mode0))
28175 op0 = safe_vector_operand (op0, mode0);
28176 if (VECTOR_MODE_P (mode1))
28177 op1 = safe_vector_operand (op1, mode1);
28179 target = gen_reg_rtx (SImode);
28180 emit_move_insn (target, const0_rtx);
28181 target = gen_rtx_SUBREG (QImode, target, 0);
28183 if ((optimize && !register_operand (op0, mode0))
28184 || !insn_data[d->icode].operand[0].predicate (op0, mode0))
28185 op0 = copy_to_mode_reg (mode0, op0);
28186 if ((optimize && !register_operand (op1, mode1))
28187 || !insn_data[d->icode].operand[1].predicate (op1, mode1))
28188 op1 = copy_to_mode_reg (mode1, op1);
28190 pat = GEN_FCN (d->icode) (op0, op1);
28194 emit_insn (gen_rtx_SET (VOIDmode,
28195 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
28196 gen_rtx_fmt_ee (comparison, QImode,
28200 return SUBREG_REG (target);
28203 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
28206 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
28207 tree exp, rtx target)
28210 tree arg0 = CALL_EXPR_ARG (exp, 0);
28211 tree arg1 = CALL_EXPR_ARG (exp, 1);
28212 tree arg2 = CALL_EXPR_ARG (exp, 2);
28213 tree arg3 = CALL_EXPR_ARG (exp, 3);
28214 tree arg4 = CALL_EXPR_ARG (exp, 4);
28215 rtx scratch0, scratch1;
28216 rtx op0 = expand_normal (arg0);
28217 rtx op1 = expand_normal (arg1);
28218 rtx op2 = expand_normal (arg2);
28219 rtx op3 = expand_normal (arg3);
28220 rtx op4 = expand_normal (arg4);
28221 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
28223 tmode0 = insn_data[d->icode].operand[0].mode;
28224 tmode1 = insn_data[d->icode].operand[1].mode;
28225 modev2 = insn_data[d->icode].operand[2].mode;
28226 modei3 = insn_data[d->icode].operand[3].mode;
28227 modev4 = insn_data[d->icode].operand[4].mode;
28228 modei5 = insn_data[d->icode].operand[5].mode;
28229 modeimm = insn_data[d->icode].operand[6].mode;
28231 if (VECTOR_MODE_P (modev2))
28232 op0 = safe_vector_operand (op0, modev2);
28233 if (VECTOR_MODE_P (modev4))
28234 op2 = safe_vector_operand (op2, modev4);
28236 if (!insn_data[d->icode].operand[2].predicate (op0, modev2))
28237 op0 = copy_to_mode_reg (modev2, op0);
28238 if (!insn_data[d->icode].operand[3].predicate (op1, modei3))
28239 op1 = copy_to_mode_reg (modei3, op1);
28240 if ((optimize && !register_operand (op2, modev4))
28241 || !insn_data[d->icode].operand[4].predicate (op2, modev4))
28242 op2 = copy_to_mode_reg (modev4, op2);
28243 if (!insn_data[d->icode].operand[5].predicate (op3, modei5))
28244 op3 = copy_to_mode_reg (modei5, op3);
28246 if (!insn_data[d->icode].operand[6].predicate (op4, modeimm))
28248 error ("the fifth argument must be an 8-bit immediate");
28252 if (d->code == IX86_BUILTIN_PCMPESTRI128)
28254 if (optimize || !target
28255 || GET_MODE (target) != tmode0
28256 || !insn_data[d->icode].operand[0].predicate (target, tmode0))
28257 target = gen_reg_rtx (tmode0);
28259 scratch1 = gen_reg_rtx (tmode1);
28261 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
28263 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
28265 if (optimize || !target
28266 || GET_MODE (target) != tmode1
28267 || !insn_data[d->icode].operand[1].predicate (target, tmode1))
28268 target = gen_reg_rtx (tmode1);
28270 scratch0 = gen_reg_rtx (tmode0);
28272 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
28276 gcc_assert (d->flag);
28278 scratch0 = gen_reg_rtx (tmode0);
28279 scratch1 = gen_reg_rtx (tmode1);
28281 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
28291 target = gen_reg_rtx (SImode);
28292 emit_move_insn (target, const0_rtx);
28293 target = gen_rtx_SUBREG (QImode, target, 0);
28296 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
28297 gen_rtx_fmt_ee (EQ, QImode,
28298 gen_rtx_REG ((enum machine_mode) d->flag,
28301 return SUBREG_REG (target);
28308 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
28311 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
28312 tree exp, rtx target)
28315 tree arg0 = CALL_EXPR_ARG (exp, 0);
28316 tree arg1 = CALL_EXPR_ARG (exp, 1);
28317 tree arg2 = CALL_EXPR_ARG (exp, 2);
28318 rtx scratch0, scratch1;
28319 rtx op0 = expand_normal (arg0);
28320 rtx op1 = expand_normal (arg1);
28321 rtx op2 = expand_normal (arg2);
28322 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
28324 tmode0 = insn_data[d->icode].operand[0].mode;
28325 tmode1 = insn_data[d->icode].operand[1].mode;
28326 modev2 = insn_data[d->icode].operand[2].mode;
28327 modev3 = insn_data[d->icode].operand[3].mode;
28328 modeimm = insn_data[d->icode].operand[4].mode;
28330 if (VECTOR_MODE_P (modev2))
28331 op0 = safe_vector_operand (op0, modev2);
28332 if (VECTOR_MODE_P (modev3))
28333 op1 = safe_vector_operand (op1, modev3);
28335 if (!insn_data[d->icode].operand[2].predicate (op0, modev2))
28336 op0 = copy_to_mode_reg (modev2, op0);
28337 if ((optimize && !register_operand (op1, modev3))
28338 || !insn_data[d->icode].operand[3].predicate (op1, modev3))
28339 op1 = copy_to_mode_reg (modev3, op1);
28341 if (!insn_data[d->icode].operand[4].predicate (op2, modeimm))
28343 error ("the third argument must be an 8-bit immediate");
28347 if (d->code == IX86_BUILTIN_PCMPISTRI128)
28349 if (optimize || !target
28350 || GET_MODE (target) != tmode0
28351 || !insn_data[d->icode].operand[0].predicate (target, tmode0))
28352 target = gen_reg_rtx (tmode0);
28354 scratch1 = gen_reg_rtx (tmode1);
28356 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
28358 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
28360 if (optimize || !target
28361 || GET_MODE (target) != tmode1
28362 || !insn_data[d->icode].operand[1].predicate (target, tmode1))
28363 target = gen_reg_rtx (tmode1);
28365 scratch0 = gen_reg_rtx (tmode0);
28367 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
28371 gcc_assert (d->flag);
28373 scratch0 = gen_reg_rtx (tmode0);
28374 scratch1 = gen_reg_rtx (tmode1);
28376 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
28386 target = gen_reg_rtx (SImode);
28387 emit_move_insn (target, const0_rtx);
28388 target = gen_rtx_SUBREG (QImode, target, 0);
28391 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
28392 gen_rtx_fmt_ee (EQ, QImode,
28393 gen_rtx_REG ((enum machine_mode) d->flag,
28396 return SUBREG_REG (target);
28402 /* Subroutine of ix86_expand_builtin to take care of insns with
28403 variable number of operands. */
28406 ix86_expand_args_builtin (const struct builtin_description *d,
28407 tree exp, rtx target)
28409 rtx pat, real_target;
28410 unsigned int i, nargs;
28411 unsigned int nargs_constant = 0;
28412 int num_memory = 0;
28416 enum machine_mode mode;
28418 bool last_arg_count = false;
28419 enum insn_code icode = d->icode;
28420 const struct insn_data_d *insn_p = &insn_data[icode];
28421 enum machine_mode tmode = insn_p->operand[0].mode;
28422 enum machine_mode rmode = VOIDmode;
28424 enum rtx_code comparison = d->comparison;
28426 switch ((enum ix86_builtin_func_type) d->flag)
28428 case V2DF_FTYPE_V2DF_ROUND:
28429 case V4DF_FTYPE_V4DF_ROUND:
28430 case V4SF_FTYPE_V4SF_ROUND:
28431 case V8SF_FTYPE_V8SF_ROUND:
28432 case V4SI_FTYPE_V4SF_ROUND:
28433 case V8SI_FTYPE_V8SF_ROUND:
28434 return ix86_expand_sse_round (d, exp, target);
28435 case V4SI_FTYPE_V2DF_V2DF_ROUND:
28436 case V8SI_FTYPE_V4DF_V4DF_ROUND:
28437 return ix86_expand_sse_round_vec_pack_sfix (d, exp, target);
28438 case INT_FTYPE_V8SF_V8SF_PTEST:
28439 case INT_FTYPE_V4DI_V4DI_PTEST:
28440 case INT_FTYPE_V4DF_V4DF_PTEST:
28441 case INT_FTYPE_V4SF_V4SF_PTEST:
28442 case INT_FTYPE_V2DI_V2DI_PTEST:
28443 case INT_FTYPE_V2DF_V2DF_PTEST:
28444 return ix86_expand_sse_ptest (d, exp, target);
28445 case FLOAT128_FTYPE_FLOAT128:
28446 case FLOAT_FTYPE_FLOAT:
28447 case INT_FTYPE_INT:
28448 case UINT64_FTYPE_INT:
28449 case UINT16_FTYPE_UINT16:
28450 case INT64_FTYPE_INT64:
28451 case INT64_FTYPE_V4SF:
28452 case INT64_FTYPE_V2DF:
28453 case INT_FTYPE_V16QI:
28454 case INT_FTYPE_V8QI:
28455 case INT_FTYPE_V8SF:
28456 case INT_FTYPE_V4DF:
28457 case INT_FTYPE_V4SF:
28458 case INT_FTYPE_V2DF:
28459 case INT_FTYPE_V32QI:
28460 case V16QI_FTYPE_V16QI:
28461 case V8SI_FTYPE_V8SF:
28462 case V8SI_FTYPE_V4SI:
28463 case V8HI_FTYPE_V8HI:
28464 case V8HI_FTYPE_V16QI:
28465 case V8QI_FTYPE_V8QI:
28466 case V8SF_FTYPE_V8SF:
28467 case V8SF_FTYPE_V8SI:
28468 case V8SF_FTYPE_V4SF:
28469 case V8SF_FTYPE_V8HI:
28470 case V4SI_FTYPE_V4SI:
28471 case V4SI_FTYPE_V16QI:
28472 case V4SI_FTYPE_V4SF:
28473 case V4SI_FTYPE_V8SI:
28474 case V4SI_FTYPE_V8HI:
28475 case V4SI_FTYPE_V4DF:
28476 case V4SI_FTYPE_V2DF:
28477 case V4HI_FTYPE_V4HI:
28478 case V4DF_FTYPE_V4DF:
28479 case V4DF_FTYPE_V4SI:
28480 case V4DF_FTYPE_V4SF:
28481 case V4DF_FTYPE_V2DF:
28482 case V4SF_FTYPE_V4SF:
28483 case V4SF_FTYPE_V4SI:
28484 case V4SF_FTYPE_V8SF:
28485 case V4SF_FTYPE_V4DF:
28486 case V4SF_FTYPE_V8HI:
28487 case V4SF_FTYPE_V2DF:
28488 case V2DI_FTYPE_V2DI:
28489 case V2DI_FTYPE_V16QI:
28490 case V2DI_FTYPE_V8HI:
28491 case V2DI_FTYPE_V4SI:
28492 case V2DF_FTYPE_V2DF:
28493 case V2DF_FTYPE_V4SI:
28494 case V2DF_FTYPE_V4DF:
28495 case V2DF_FTYPE_V4SF:
28496 case V2DF_FTYPE_V2SI:
28497 case V2SI_FTYPE_V2SI:
28498 case V2SI_FTYPE_V4SF:
28499 case V2SI_FTYPE_V2SF:
28500 case V2SI_FTYPE_V2DF:
28501 case V2SF_FTYPE_V2SF:
28502 case V2SF_FTYPE_V2SI:
28503 case V32QI_FTYPE_V32QI:
28504 case V32QI_FTYPE_V16QI:
28505 case V16HI_FTYPE_V16HI:
28506 case V16HI_FTYPE_V8HI:
28507 case V8SI_FTYPE_V8SI:
28508 case V16HI_FTYPE_V16QI:
28509 case V8SI_FTYPE_V16QI:
28510 case V4DI_FTYPE_V16QI:
28511 case V8SI_FTYPE_V8HI:
28512 case V4DI_FTYPE_V8HI:
28513 case V4DI_FTYPE_V4SI:
28514 case V4DI_FTYPE_V2DI:
28517 case V4SF_FTYPE_V4SF_VEC_MERGE:
28518 case V2DF_FTYPE_V2DF_VEC_MERGE:
28519 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
28520 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
28521 case V16QI_FTYPE_V16QI_V16QI:
28522 case V16QI_FTYPE_V8HI_V8HI:
28523 case V8QI_FTYPE_V8QI_V8QI:
28524 case V8QI_FTYPE_V4HI_V4HI:
28525 case V8HI_FTYPE_V8HI_V8HI:
28526 case V8HI_FTYPE_V16QI_V16QI:
28527 case V8HI_FTYPE_V4SI_V4SI:
28528 case V8SF_FTYPE_V8SF_V8SF:
28529 case V8SF_FTYPE_V8SF_V8SI:
28530 case V4SI_FTYPE_V4SI_V4SI:
28531 case V4SI_FTYPE_V8HI_V8HI:
28532 case V4SI_FTYPE_V4SF_V4SF:
28533 case V4SI_FTYPE_V2DF_V2DF:
28534 case V4HI_FTYPE_V4HI_V4HI:
28535 case V4HI_FTYPE_V8QI_V8QI:
28536 case V4HI_FTYPE_V2SI_V2SI:
28537 case V4DF_FTYPE_V4DF_V4DF:
28538 case V4DF_FTYPE_V4DF_V4DI:
28539 case V4SF_FTYPE_V4SF_V4SF:
28540 case V4SF_FTYPE_V4SF_V4SI:
28541 case V4SF_FTYPE_V4SF_V2SI:
28542 case V4SF_FTYPE_V4SF_V2DF:
28543 case V4SF_FTYPE_V4SF_DI:
28544 case V4SF_FTYPE_V4SF_SI:
28545 case V2DI_FTYPE_V2DI_V2DI:
28546 case V2DI_FTYPE_V16QI_V16QI:
28547 case V2DI_FTYPE_V4SI_V4SI:
28548 case V2DI_FTYPE_V2DI_V16QI:
28549 case V2DI_FTYPE_V2DF_V2DF:
28550 case V2SI_FTYPE_V2SI_V2SI:
28551 case V2SI_FTYPE_V4HI_V4HI:
28552 case V2SI_FTYPE_V2SF_V2SF:
28553 case V2DF_FTYPE_V2DF_V2DF:
28554 case V2DF_FTYPE_V2DF_V4SF:
28555 case V2DF_FTYPE_V2DF_V2DI:
28556 case V2DF_FTYPE_V2DF_DI:
28557 case V2DF_FTYPE_V2DF_SI:
28558 case V2SF_FTYPE_V2SF_V2SF:
28559 case V1DI_FTYPE_V1DI_V1DI:
28560 case V1DI_FTYPE_V8QI_V8QI:
28561 case V1DI_FTYPE_V2SI_V2SI:
28562 case V32QI_FTYPE_V16HI_V16HI:
28563 case V16HI_FTYPE_V8SI_V8SI:
28564 case V32QI_FTYPE_V32QI_V32QI:
28565 case V16HI_FTYPE_V32QI_V32QI:
28566 case V16HI_FTYPE_V16HI_V16HI:
28567 case V8SI_FTYPE_V4DF_V4DF:
28568 case V8SI_FTYPE_V8SI_V8SI:
28569 case V8SI_FTYPE_V16HI_V16HI:
28570 case V4DI_FTYPE_V4DI_V4DI:
28571 case V4DI_FTYPE_V8SI_V8SI:
28572 if (comparison == UNKNOWN)
28573 return ix86_expand_binop_builtin (icode, exp, target);
28576 case V4SF_FTYPE_V4SF_V4SF_SWAP:
28577 case V2DF_FTYPE_V2DF_V2DF_SWAP:
28578 gcc_assert (comparison != UNKNOWN);
28582 case V16HI_FTYPE_V16HI_V8HI_COUNT:
28583 case V16HI_FTYPE_V16HI_SI_COUNT:
28584 case V8SI_FTYPE_V8SI_V4SI_COUNT:
28585 case V8SI_FTYPE_V8SI_SI_COUNT:
28586 case V4DI_FTYPE_V4DI_V2DI_COUNT:
28587 case V4DI_FTYPE_V4DI_INT_COUNT:
28588 case V8HI_FTYPE_V8HI_V8HI_COUNT:
28589 case V8HI_FTYPE_V8HI_SI_COUNT:
28590 case V4SI_FTYPE_V4SI_V4SI_COUNT:
28591 case V4SI_FTYPE_V4SI_SI_COUNT:
28592 case V4HI_FTYPE_V4HI_V4HI_COUNT:
28593 case V4HI_FTYPE_V4HI_SI_COUNT:
28594 case V2DI_FTYPE_V2DI_V2DI_COUNT:
28595 case V2DI_FTYPE_V2DI_SI_COUNT:
28596 case V2SI_FTYPE_V2SI_V2SI_COUNT:
28597 case V2SI_FTYPE_V2SI_SI_COUNT:
28598 case V1DI_FTYPE_V1DI_V1DI_COUNT:
28599 case V1DI_FTYPE_V1DI_SI_COUNT:
28601 last_arg_count = true;
28603 case UINT64_FTYPE_UINT64_UINT64:
28604 case UINT_FTYPE_UINT_UINT:
28605 case UINT_FTYPE_UINT_USHORT:
28606 case UINT_FTYPE_UINT_UCHAR:
28607 case UINT16_FTYPE_UINT16_INT:
28608 case UINT8_FTYPE_UINT8_INT:
28611 case V2DI_FTYPE_V2DI_INT_CONVERT:
28614 nargs_constant = 1;
28616 case V4DI_FTYPE_V4DI_INT_CONVERT:
28619 nargs_constant = 1;
28621 case V8HI_FTYPE_V8HI_INT:
28622 case V8HI_FTYPE_V8SF_INT:
28623 case V8HI_FTYPE_V4SF_INT:
28624 case V8SF_FTYPE_V8SF_INT:
28625 case V4SI_FTYPE_V4SI_INT:
28626 case V4SI_FTYPE_V8SI_INT:
28627 case V4HI_FTYPE_V4HI_INT:
28628 case V4DF_FTYPE_V4DF_INT:
28629 case V4SF_FTYPE_V4SF_INT:
28630 case V4SF_FTYPE_V8SF_INT:
28631 case V2DI_FTYPE_V2DI_INT:
28632 case V2DF_FTYPE_V2DF_INT:
28633 case V2DF_FTYPE_V4DF_INT:
28634 case V16HI_FTYPE_V16HI_INT:
28635 case V8SI_FTYPE_V8SI_INT:
28636 case V4DI_FTYPE_V4DI_INT:
28637 case V2DI_FTYPE_V4DI_INT:
28639 nargs_constant = 1;
28641 case V16QI_FTYPE_V16QI_V16QI_V16QI:
28642 case V8SF_FTYPE_V8SF_V8SF_V8SF:
28643 case V4DF_FTYPE_V4DF_V4DF_V4DF:
28644 case V4SF_FTYPE_V4SF_V4SF_V4SF:
28645 case V2DF_FTYPE_V2DF_V2DF_V2DF:
28646 case V32QI_FTYPE_V32QI_V32QI_V32QI:
28649 case V32QI_FTYPE_V32QI_V32QI_INT:
28650 case V16HI_FTYPE_V16HI_V16HI_INT:
28651 case V16QI_FTYPE_V16QI_V16QI_INT:
28652 case V4DI_FTYPE_V4DI_V4DI_INT:
28653 case V8HI_FTYPE_V8HI_V8HI_INT:
28654 case V8SI_FTYPE_V8SI_V8SI_INT:
28655 case V8SI_FTYPE_V8SI_V4SI_INT:
28656 case V8SF_FTYPE_V8SF_V8SF_INT:
28657 case V8SF_FTYPE_V8SF_V4SF_INT:
28658 case V4SI_FTYPE_V4SI_V4SI_INT:
28659 case V4DF_FTYPE_V4DF_V4DF_INT:
28660 case V4DF_FTYPE_V4DF_V2DF_INT:
28661 case V4SF_FTYPE_V4SF_V4SF_INT:
28662 case V2DI_FTYPE_V2DI_V2DI_INT:
28663 case V4DI_FTYPE_V4DI_V2DI_INT:
28664 case V2DF_FTYPE_V2DF_V2DF_INT:
28666 nargs_constant = 1;
28668 case V4DI_FTYPE_V4DI_V4DI_INT_CONVERT:
28671 nargs_constant = 1;
28673 case V2DI_FTYPE_V2DI_V2DI_INT_CONVERT:
28676 nargs_constant = 1;
28678 case V1DI_FTYPE_V1DI_V1DI_INT_CONVERT:
28681 nargs_constant = 1;
28683 case V2DI_FTYPE_V2DI_UINT_UINT:
28685 nargs_constant = 2;
28687 case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
28688 case V4DF_FTYPE_V4DF_V4DF_V4DI_INT:
28689 case V4SF_FTYPE_V4SF_V4SF_V4SI_INT:
28690 case V8SF_FTYPE_V8SF_V8SF_V8SI_INT:
28692 nargs_constant = 1;
28694 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
28696 nargs_constant = 2;
28699 gcc_unreachable ();
28702 gcc_assert (nargs <= ARRAY_SIZE (args));
28704 if (comparison != UNKNOWN)
28706 gcc_assert (nargs == 2);
28707 return ix86_expand_sse_compare (d, exp, target, swap);
28710 if (rmode == VOIDmode || rmode == tmode)
28714 || GET_MODE (target) != tmode
28715 || !insn_p->operand[0].predicate (target, tmode))
28716 target = gen_reg_rtx (tmode);
28717 real_target = target;
28721 target = gen_reg_rtx (rmode);
28722 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
28725 for (i = 0; i < nargs; i++)
28727 tree arg = CALL_EXPR_ARG (exp, i);
28728 rtx op = expand_normal (arg);
28729 enum machine_mode mode = insn_p->operand[i + 1].mode;
28730 bool match = insn_p->operand[i + 1].predicate (op, mode);
28732 if (last_arg_count && (i + 1) == nargs)
28734 /* SIMD shift insns take either an 8-bit immediate or
28735 register as count. But builtin functions take int as
28736 count. If count doesn't match, we put it in register. */
28739 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
28740 if (!insn_p->operand[i + 1].predicate (op, mode))
28741 op = copy_to_reg (op);
28744 else if ((nargs - i) <= nargs_constant)
28749 case CODE_FOR_avx2_inserti128:
28750 case CODE_FOR_avx2_extracti128:
28751 error ("the last argument must be an 1-bit immediate");
28754 case CODE_FOR_sse4_1_roundsd:
28755 case CODE_FOR_sse4_1_roundss:
28757 case CODE_FOR_sse4_1_roundpd:
28758 case CODE_FOR_sse4_1_roundps:
28759 case CODE_FOR_avx_roundpd256:
28760 case CODE_FOR_avx_roundps256:
28762 case CODE_FOR_sse4_1_roundpd_vec_pack_sfix:
28763 case CODE_FOR_sse4_1_roundps_sfix:
28764 case CODE_FOR_avx_roundpd_vec_pack_sfix256:
28765 case CODE_FOR_avx_roundps_sfix256:
28767 case CODE_FOR_sse4_1_blendps:
28768 case CODE_FOR_avx_blendpd256:
28769 case CODE_FOR_avx_vpermilv4df:
28770 error ("the last argument must be a 4-bit immediate");
28773 case CODE_FOR_sse4_1_blendpd:
28774 case CODE_FOR_avx_vpermilv2df:
28775 case CODE_FOR_xop_vpermil2v2df3:
28776 case CODE_FOR_xop_vpermil2v4sf3:
28777 case CODE_FOR_xop_vpermil2v4df3:
28778 case CODE_FOR_xop_vpermil2v8sf3:
28779 error ("the last argument must be a 2-bit immediate");
28782 case CODE_FOR_avx_vextractf128v4df:
28783 case CODE_FOR_avx_vextractf128v8sf:
28784 case CODE_FOR_avx_vextractf128v8si:
28785 case CODE_FOR_avx_vinsertf128v4df:
28786 case CODE_FOR_avx_vinsertf128v8sf:
28787 case CODE_FOR_avx_vinsertf128v8si:
28788 error ("the last argument must be a 1-bit immediate");
28791 case CODE_FOR_avx_vmcmpv2df3:
28792 case CODE_FOR_avx_vmcmpv4sf3:
28793 case CODE_FOR_avx_cmpv2df3:
28794 case CODE_FOR_avx_cmpv4sf3:
28795 case CODE_FOR_avx_cmpv4df3:
28796 case CODE_FOR_avx_cmpv8sf3:
28797 error ("the last argument must be a 5-bit immediate");
28801 switch (nargs_constant)
28804 if ((nargs - i) == nargs_constant)
28806 error ("the next to last argument must be an 8-bit immediate");
28810 error ("the last argument must be an 8-bit immediate");
28813 gcc_unreachable ();
28820 if (VECTOR_MODE_P (mode))
28821 op = safe_vector_operand (op, mode);
28823 /* If we aren't optimizing, only allow one memory operand to
28825 if (memory_operand (op, mode))
28828 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
28830 if (optimize || !match || num_memory > 1)
28831 op = copy_to_mode_reg (mode, op);
28835 op = copy_to_reg (op);
28836 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
28841 args[i].mode = mode;
28847 pat = GEN_FCN (icode) (real_target, args[0].op);
28850 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
28853 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
28857 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
28858 args[2].op, args[3].op);
28861 gcc_unreachable ();
28871 /* Subroutine of ix86_expand_builtin to take care of special insns
28872 with variable number of operands. */
28875 ix86_expand_special_args_builtin (const struct builtin_description *d,
28876 tree exp, rtx target)
28880 unsigned int i, nargs, arg_adjust, memory;
28884 enum machine_mode mode;
28886 enum insn_code icode = d->icode;
28887 bool last_arg_constant = false;
28888 const struct insn_data_d *insn_p = &insn_data[icode];
28889 enum machine_mode tmode = insn_p->operand[0].mode;
28890 enum { load, store } klass;
28892 switch ((enum ix86_builtin_func_type) d->flag)
28894 case VOID_FTYPE_VOID:
28895 if (icode == CODE_FOR_avx_vzeroupper)
28896 target = GEN_INT (vzeroupper_intrinsic);
28897 emit_insn (GEN_FCN (icode) (target));
28899 case VOID_FTYPE_UINT64:
28900 case VOID_FTYPE_UNSIGNED:
28905 case UINT64_FTYPE_VOID:
28906 case UNSIGNED_FTYPE_VOID:
28911 case UINT64_FTYPE_PUNSIGNED:
28912 case V2DI_FTYPE_PV2DI:
28913 case V4DI_FTYPE_PV4DI:
28914 case V32QI_FTYPE_PCCHAR:
28915 case V16QI_FTYPE_PCCHAR:
28916 case V8SF_FTYPE_PCV4SF:
28917 case V8SF_FTYPE_PCFLOAT:
28918 case V4SF_FTYPE_PCFLOAT:
28919 case V4DF_FTYPE_PCV2DF:
28920 case V4DF_FTYPE_PCDOUBLE:
28921 case V2DF_FTYPE_PCDOUBLE:
28922 case VOID_FTYPE_PVOID:
28927 case VOID_FTYPE_PV2SF_V4SF:
28928 case VOID_FTYPE_PV4DI_V4DI:
28929 case VOID_FTYPE_PV2DI_V2DI:
28930 case VOID_FTYPE_PCHAR_V32QI:
28931 case VOID_FTYPE_PCHAR_V16QI:
28932 case VOID_FTYPE_PFLOAT_V8SF:
28933 case VOID_FTYPE_PFLOAT_V4SF:
28934 case VOID_FTYPE_PDOUBLE_V4DF:
28935 case VOID_FTYPE_PDOUBLE_V2DF:
28936 case VOID_FTYPE_PLONGLONG_LONGLONG:
28937 case VOID_FTYPE_PULONGLONG_ULONGLONG:
28938 case VOID_FTYPE_PINT_INT:
28941 /* Reserve memory operand for target. */
28942 memory = ARRAY_SIZE (args);
28944 case V4SF_FTYPE_V4SF_PCV2SF:
28945 case V2DF_FTYPE_V2DF_PCDOUBLE:
28950 case V8SF_FTYPE_PCV8SF_V8SI:
28951 case V4DF_FTYPE_PCV4DF_V4DI:
28952 case V4SF_FTYPE_PCV4SF_V4SI:
28953 case V2DF_FTYPE_PCV2DF_V2DI:
28954 case V8SI_FTYPE_PCV8SI_V8SI:
28955 case V4DI_FTYPE_PCV4DI_V4DI:
28956 case V4SI_FTYPE_PCV4SI_V4SI:
28957 case V2DI_FTYPE_PCV2DI_V2DI:
28962 case VOID_FTYPE_PV8SF_V8SI_V8SF:
28963 case VOID_FTYPE_PV4DF_V4DI_V4DF:
28964 case VOID_FTYPE_PV4SF_V4SI_V4SF:
28965 case VOID_FTYPE_PV2DF_V2DI_V2DF:
28966 case VOID_FTYPE_PV8SI_V8SI_V8SI:
28967 case VOID_FTYPE_PV4DI_V4DI_V4DI:
28968 case VOID_FTYPE_PV4SI_V4SI_V4SI:
28969 case VOID_FTYPE_PV2DI_V2DI_V2DI:
28972 /* Reserve memory operand for target. */
28973 memory = ARRAY_SIZE (args);
28975 case VOID_FTYPE_UINT_UINT_UINT:
28976 case VOID_FTYPE_UINT64_UINT_UINT:
28977 case UCHAR_FTYPE_UINT_UINT_UINT:
28978 case UCHAR_FTYPE_UINT64_UINT_UINT:
28981 memory = ARRAY_SIZE (args);
28982 last_arg_constant = true;
28985 gcc_unreachable ();
28988 gcc_assert (nargs <= ARRAY_SIZE (args));
28990 if (klass == store)
28992 arg = CALL_EXPR_ARG (exp, 0);
28993 op = expand_normal (arg);
28994 gcc_assert (target == 0);
28997 if (GET_MODE (op) != Pmode)
28998 op = convert_to_mode (Pmode, op, 1);
28999 target = gen_rtx_MEM (tmode, force_reg (Pmode, op));
29002 target = force_reg (tmode, op);
29010 || !register_operand (target, tmode)
29011 || GET_MODE (target) != tmode)
29012 target = gen_reg_rtx (tmode);
29015 for (i = 0; i < nargs; i++)
29017 enum machine_mode mode = insn_p->operand[i + 1].mode;
29020 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
29021 op = expand_normal (arg);
29022 match = insn_p->operand[i + 1].predicate (op, mode);
29024 if (last_arg_constant && (i + 1) == nargs)
29028 if (icode == CODE_FOR_lwp_lwpvalsi3
29029 || icode == CODE_FOR_lwp_lwpinssi3
29030 || icode == CODE_FOR_lwp_lwpvaldi3
29031 || icode == CODE_FOR_lwp_lwpinsdi3)
29032 error ("the last argument must be a 32-bit immediate");
29034 error ("the last argument must be an 8-bit immediate");
29042 /* This must be the memory operand. */
29043 if (GET_MODE (op) != Pmode)
29044 op = convert_to_mode (Pmode, op, 1);
29045 op = gen_rtx_MEM (mode, force_reg (Pmode, op));
29046 gcc_assert (GET_MODE (op) == mode
29047 || GET_MODE (op) == VOIDmode);
29051 /* This must be register. */
29052 if (VECTOR_MODE_P (mode))
29053 op = safe_vector_operand (op, mode);
29055 gcc_assert (GET_MODE (op) == mode
29056 || GET_MODE (op) == VOIDmode);
29057 op = copy_to_mode_reg (mode, op);
29062 args[i].mode = mode;
29068 pat = GEN_FCN (icode) (target);
29071 pat = GEN_FCN (icode) (target, args[0].op);
29074 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
29077 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
29080 gcc_unreachable ();
29086 return klass == store ? 0 : target;
29089 /* Return the integer constant in ARG. Constrain it to be in the range
29090 of the subparts of VEC_TYPE; issue an error if not. */
29093 get_element_number (tree vec_type, tree arg)
29095 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
29097 if (!host_integerp (arg, 1)
29098 || (elt = tree_low_cst (arg, 1), elt > max))
29100 error ("selector must be an integer constant in the range 0..%wi", max);
29107 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
29108 ix86_expand_vector_init. We DO have language-level syntax for this, in
29109 the form of (type){ init-list }. Except that since we can't place emms
29110 instructions from inside the compiler, we can't allow the use of MMX
29111 registers unless the user explicitly asks for it. So we do *not* define
29112 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
29113 we have builtins invoked by mmintrin.h that gives us license to emit
29114 these sorts of instructions. */
29117 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
29119 enum machine_mode tmode = TYPE_MODE (type);
29120 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
29121 int i, n_elt = GET_MODE_NUNITS (tmode);
29122 rtvec v = rtvec_alloc (n_elt);
29124 gcc_assert (VECTOR_MODE_P (tmode));
29125 gcc_assert (call_expr_nargs (exp) == n_elt);
29127 for (i = 0; i < n_elt; ++i)
29129 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
29130 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
29133 if (!target || !register_operand (target, tmode))
29134 target = gen_reg_rtx (tmode);
29136 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
29140 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
29141 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
29142 had a language-level syntax for referencing vector elements. */
29145 ix86_expand_vec_ext_builtin (tree exp, rtx target)
29147 enum machine_mode tmode, mode0;
29152 arg0 = CALL_EXPR_ARG (exp, 0);
29153 arg1 = CALL_EXPR_ARG (exp, 1);
29155 op0 = expand_normal (arg0);
29156 elt = get_element_number (TREE_TYPE (arg0), arg1);
29158 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
29159 mode0 = TYPE_MODE (TREE_TYPE (arg0));
29160 gcc_assert (VECTOR_MODE_P (mode0));
29162 op0 = force_reg (mode0, op0);
29164 if (optimize || !target || !register_operand (target, tmode))
29165 target = gen_reg_rtx (tmode);
29167 ix86_expand_vector_extract (true, target, op0, elt);
29172 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
29173 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
29174 a language-level syntax for referencing vector elements. */
29177 ix86_expand_vec_set_builtin (tree exp)
29179 enum machine_mode tmode, mode1;
29180 tree arg0, arg1, arg2;
29182 rtx op0, op1, target;
29184 arg0 = CALL_EXPR_ARG (exp, 0);
29185 arg1 = CALL_EXPR_ARG (exp, 1);
29186 arg2 = CALL_EXPR_ARG (exp, 2);
29188 tmode = TYPE_MODE (TREE_TYPE (arg0));
29189 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
29190 gcc_assert (VECTOR_MODE_P (tmode));
29192 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
29193 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
29194 elt = get_element_number (TREE_TYPE (arg0), arg2);
29196 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
29197 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
29199 op0 = force_reg (tmode, op0);
29200 op1 = force_reg (mode1, op1);
29202 /* OP0 is the source of these builtin functions and shouldn't be
29203 modified. Create a copy, use it and return it as target. */
29204 target = gen_reg_rtx (tmode);
29205 emit_move_insn (target, op0);
29206 ix86_expand_vector_set (true, target, op1, elt);
29211 /* Expand an expression EXP that calls a built-in function,
29212 with result going to TARGET if that's convenient
29213 (and in mode MODE if that's convenient).
29214 SUBTARGET may be used as the target for computing one of EXP's operands.
29215 IGNORE is nonzero if the value is to be ignored. */
29218 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
29219 enum machine_mode mode ATTRIBUTE_UNUSED,
29220 int ignore ATTRIBUTE_UNUSED)
29222 const struct builtin_description *d;
29224 enum insn_code icode;
29225 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
29226 tree arg0, arg1, arg2, arg3, arg4;
29227 rtx op0, op1, op2, op3, op4, pat;
29228 enum machine_mode mode0, mode1, mode2, mode3, mode4;
29229 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
29231 /* Determine whether the builtin function is available under the current ISA.
29232 Originally the builtin was not created if it wasn't applicable to the
29233 current ISA based on the command line switches. With function specific
29234 options, we need to check in the context of the function making the call
29235 whether it is supported. */
29236 if (ix86_builtins_isa[fcode].isa
29237 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
29239 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
29240 NULL, (enum fpmath_unit) 0, false);
29243 error ("%qE needs unknown isa option", fndecl);
29246 gcc_assert (opts != NULL);
29247 error ("%qE needs isa option %s", fndecl, opts);
29255 case IX86_BUILTIN_MASKMOVQ:
29256 case IX86_BUILTIN_MASKMOVDQU:
29257 icode = (fcode == IX86_BUILTIN_MASKMOVQ
29258 ? CODE_FOR_mmx_maskmovq
29259 : CODE_FOR_sse2_maskmovdqu);
29260 /* Note the arg order is different from the operand order. */
29261 arg1 = CALL_EXPR_ARG (exp, 0);
29262 arg2 = CALL_EXPR_ARG (exp, 1);
29263 arg0 = CALL_EXPR_ARG (exp, 2);
29264 op0 = expand_normal (arg0);
29265 op1 = expand_normal (arg1);
29266 op2 = expand_normal (arg2);
29267 mode0 = insn_data[icode].operand[0].mode;
29268 mode1 = insn_data[icode].operand[1].mode;
29269 mode2 = insn_data[icode].operand[2].mode;
29271 if (GET_MODE (op0) != Pmode)
29272 op0 = convert_to_mode (Pmode, op0, 1);
29273 op0 = gen_rtx_MEM (mode1, force_reg (Pmode, op0));
29275 if (!insn_data[icode].operand[0].predicate (op0, mode0))
29276 op0 = copy_to_mode_reg (mode0, op0);
29277 if (!insn_data[icode].operand[1].predicate (op1, mode1))
29278 op1 = copy_to_mode_reg (mode1, op1);
29279 if (!insn_data[icode].operand[2].predicate (op2, mode2))
29280 op2 = copy_to_mode_reg (mode2, op2);
29281 pat = GEN_FCN (icode) (op0, op1, op2);
29287 case IX86_BUILTIN_LDMXCSR:
29288 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
29289 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
29290 emit_move_insn (target, op0);
29291 emit_insn (gen_sse_ldmxcsr (target));
29294 case IX86_BUILTIN_STMXCSR:
29295 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
29296 emit_insn (gen_sse_stmxcsr (target));
29297 return copy_to_mode_reg (SImode, target);
29299 case IX86_BUILTIN_CLFLUSH:
29300 arg0 = CALL_EXPR_ARG (exp, 0);
29301 op0 = expand_normal (arg0);
29302 icode = CODE_FOR_sse2_clflush;
29303 if (!insn_data[icode].operand[0].predicate (op0, Pmode))
29305 if (GET_MODE (op0) != Pmode)
29306 op0 = convert_to_mode (Pmode, op0, 1);
29307 op0 = force_reg (Pmode, op0);
29310 emit_insn (gen_sse2_clflush (op0));
29313 case IX86_BUILTIN_MONITOR:
29314 arg0 = CALL_EXPR_ARG (exp, 0);
29315 arg1 = CALL_EXPR_ARG (exp, 1);
29316 arg2 = CALL_EXPR_ARG (exp, 2);
29317 op0 = expand_normal (arg0);
29318 op1 = expand_normal (arg1);
29319 op2 = expand_normal (arg2);
29322 if (GET_MODE (op0) != Pmode)
29323 op0 = convert_to_mode (Pmode, op0, 1);
29324 op0 = force_reg (Pmode, op0);
29327 op1 = copy_to_mode_reg (SImode, op1);
29329 op2 = copy_to_mode_reg (SImode, op2);
29330 emit_insn (ix86_gen_monitor (op0, op1, op2));
29333 case IX86_BUILTIN_MWAIT:
29334 arg0 = CALL_EXPR_ARG (exp, 0);
29335 arg1 = CALL_EXPR_ARG (exp, 1);
29336 op0 = expand_normal (arg0);
29337 op1 = expand_normal (arg1);
29339 op0 = copy_to_mode_reg (SImode, op0);
29341 op1 = copy_to_mode_reg (SImode, op1);
29342 emit_insn (gen_sse3_mwait (op0, op1));
29345 case IX86_BUILTIN_VEC_INIT_V2SI:
29346 case IX86_BUILTIN_VEC_INIT_V4HI:
29347 case IX86_BUILTIN_VEC_INIT_V8QI:
29348 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
29350 case IX86_BUILTIN_VEC_EXT_V2DF:
29351 case IX86_BUILTIN_VEC_EXT_V2DI:
29352 case IX86_BUILTIN_VEC_EXT_V4SF:
29353 case IX86_BUILTIN_VEC_EXT_V4SI:
29354 case IX86_BUILTIN_VEC_EXT_V8HI:
29355 case IX86_BUILTIN_VEC_EXT_V2SI:
29356 case IX86_BUILTIN_VEC_EXT_V4HI:
29357 case IX86_BUILTIN_VEC_EXT_V16QI:
29358 return ix86_expand_vec_ext_builtin (exp, target);
29360 case IX86_BUILTIN_VEC_SET_V2DI:
29361 case IX86_BUILTIN_VEC_SET_V4SF:
29362 case IX86_BUILTIN_VEC_SET_V4SI:
29363 case IX86_BUILTIN_VEC_SET_V8HI:
29364 case IX86_BUILTIN_VEC_SET_V4HI:
29365 case IX86_BUILTIN_VEC_SET_V16QI:
29366 return ix86_expand_vec_set_builtin (exp);
29368 case IX86_BUILTIN_INFQ:
29369 case IX86_BUILTIN_HUGE_VALQ:
29371 REAL_VALUE_TYPE inf;
29375 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
29377 tmp = validize_mem (force_const_mem (mode, tmp));
29380 target = gen_reg_rtx (mode);
29382 emit_move_insn (target, tmp);
29386 case IX86_BUILTIN_LLWPCB:
29387 arg0 = CALL_EXPR_ARG (exp, 0);
29388 op0 = expand_normal (arg0);
29389 icode = CODE_FOR_lwp_llwpcb;
29390 if (!insn_data[icode].operand[0].predicate (op0, Pmode))
29392 if (GET_MODE (op0) != Pmode)
29393 op0 = convert_to_mode (Pmode, op0, 1);
29394 op0 = force_reg (Pmode, op0);
29396 emit_insn (gen_lwp_llwpcb (op0));
29399 case IX86_BUILTIN_SLWPCB:
29400 icode = CODE_FOR_lwp_slwpcb;
29402 || !insn_data[icode].operand[0].predicate (target, Pmode))
29403 target = gen_reg_rtx (Pmode);
29404 emit_insn (gen_lwp_slwpcb (target));
29407 case IX86_BUILTIN_BEXTRI32:
29408 case IX86_BUILTIN_BEXTRI64:
29409 arg0 = CALL_EXPR_ARG (exp, 0);
29410 arg1 = CALL_EXPR_ARG (exp, 1);
29411 op0 = expand_normal (arg0);
29412 op1 = expand_normal (arg1);
29413 icode = (fcode == IX86_BUILTIN_BEXTRI32
29414 ? CODE_FOR_tbm_bextri_si
29415 : CODE_FOR_tbm_bextri_di);
29416 if (!CONST_INT_P (op1))
29418 error ("last argument must be an immediate");
29423 unsigned char length = (INTVAL (op1) >> 8) & 0xFF;
29424 unsigned char lsb_index = INTVAL (op1) & 0xFF;
29425 op1 = GEN_INT (length);
29426 op2 = GEN_INT (lsb_index);
29427 pat = GEN_FCN (icode) (target, op0, op1, op2);
29433 case IX86_BUILTIN_RDRAND16_STEP:
29434 icode = CODE_FOR_rdrandhi_1;
29438 case IX86_BUILTIN_RDRAND32_STEP:
29439 icode = CODE_FOR_rdrandsi_1;
29443 case IX86_BUILTIN_RDRAND64_STEP:
29444 icode = CODE_FOR_rdranddi_1;
29448 op0 = gen_reg_rtx (mode0);
29449 emit_insn (GEN_FCN (icode) (op0));
29451 arg0 = CALL_EXPR_ARG (exp, 0);
29452 op1 = expand_normal (arg0);
29453 if (!address_operand (op1, VOIDmode))
29455 op1 = convert_memory_address (Pmode, op1);
29456 op1 = copy_addr_to_reg (op1);
29458 emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
29460 op1 = gen_reg_rtx (SImode);
29461 emit_move_insn (op1, CONST1_RTX (SImode));
29463 /* Emit SImode conditional move. */
29464 if (mode0 == HImode)
29466 op2 = gen_reg_rtx (SImode);
29467 emit_insn (gen_zero_extendhisi2 (op2, op0));
29469 else if (mode0 == SImode)
29472 op2 = gen_rtx_SUBREG (SImode, op0, 0);
29475 target = gen_reg_rtx (SImode);
29477 pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),
29479 emit_insn (gen_rtx_SET (VOIDmode, target,
29480 gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1)));
29483 case IX86_BUILTIN_GATHERSIV2DF:
29484 icode = CODE_FOR_avx2_gathersiv2df;
29486 case IX86_BUILTIN_GATHERSIV4DF:
29487 icode = CODE_FOR_avx2_gathersiv4df;
29489 case IX86_BUILTIN_GATHERDIV2DF:
29490 icode = CODE_FOR_avx2_gatherdiv2df;
29492 case IX86_BUILTIN_GATHERDIV4DF:
29493 icode = CODE_FOR_avx2_gatherdiv4df;
29495 case IX86_BUILTIN_GATHERSIV4SF:
29496 icode = CODE_FOR_avx2_gathersiv4sf;
29498 case IX86_BUILTIN_GATHERSIV8SF:
29499 icode = CODE_FOR_avx2_gathersiv8sf;
29501 case IX86_BUILTIN_GATHERDIV4SF:
29502 icode = CODE_FOR_avx2_gatherdiv4sf;
29504 case IX86_BUILTIN_GATHERDIV8SF:
29505 icode = CODE_FOR_avx2_gatherdiv8sf;
29507 case IX86_BUILTIN_GATHERSIV2DI:
29508 icode = CODE_FOR_avx2_gathersiv2di;
29510 case IX86_BUILTIN_GATHERSIV4DI:
29511 icode = CODE_FOR_avx2_gathersiv4di;
29513 case IX86_BUILTIN_GATHERDIV2DI:
29514 icode = CODE_FOR_avx2_gatherdiv2di;
29516 case IX86_BUILTIN_GATHERDIV4DI:
29517 icode = CODE_FOR_avx2_gatherdiv4di;
29519 case IX86_BUILTIN_GATHERSIV4SI:
29520 icode = CODE_FOR_avx2_gathersiv4si;
29522 case IX86_BUILTIN_GATHERSIV8SI:
29523 icode = CODE_FOR_avx2_gathersiv8si;
29525 case IX86_BUILTIN_GATHERDIV4SI:
29526 icode = CODE_FOR_avx2_gatherdiv4si;
29528 case IX86_BUILTIN_GATHERDIV8SI:
29529 icode = CODE_FOR_avx2_gatherdiv8si;
29531 case IX86_BUILTIN_GATHERALTSIV4DF:
29532 icode = CODE_FOR_avx2_gathersiv4df;
29534 case IX86_BUILTIN_GATHERALTDIV8SF:
29535 icode = CODE_FOR_avx2_gatherdiv8sf;
29537 case IX86_BUILTIN_GATHERALTSIV4DI:
29538 icode = CODE_FOR_avx2_gathersiv4di;
29540 case IX86_BUILTIN_GATHERALTDIV8SI:
29541 icode = CODE_FOR_avx2_gatherdiv8si;
29545 arg0 = CALL_EXPR_ARG (exp, 0);
29546 arg1 = CALL_EXPR_ARG (exp, 1);
29547 arg2 = CALL_EXPR_ARG (exp, 2);
29548 arg3 = CALL_EXPR_ARG (exp, 3);
29549 arg4 = CALL_EXPR_ARG (exp, 4);
29550 op0 = expand_normal (arg0);
29551 op1 = expand_normal (arg1);
29552 op2 = expand_normal (arg2);
29553 op3 = expand_normal (arg3);
29554 op4 = expand_normal (arg4);
29555 /* Note the arg order is different from the operand order. */
29556 mode0 = insn_data[icode].operand[1].mode;
29557 mode2 = insn_data[icode].operand[3].mode;
29558 mode3 = insn_data[icode].operand[4].mode;
29559 mode4 = insn_data[icode].operand[5].mode;
29561 if (target == NULL_RTX
29562 || GET_MODE (target) != insn_data[icode].operand[0].mode)
29563 subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode);
29565 subtarget = target;
29567 if (fcode == IX86_BUILTIN_GATHERALTSIV4DF
29568 || fcode == IX86_BUILTIN_GATHERALTSIV4DI)
29570 rtx half = gen_reg_rtx (V4SImode);
29571 if (!nonimmediate_operand (op2, V8SImode))
29572 op2 = copy_to_mode_reg (V8SImode, op2);
29573 emit_insn (gen_vec_extract_lo_v8si (half, op2));
29576 else if (fcode == IX86_BUILTIN_GATHERALTDIV8SF
29577 || fcode == IX86_BUILTIN_GATHERALTDIV8SI)
29579 rtx (*gen) (rtx, rtx);
29580 rtx half = gen_reg_rtx (mode0);
29581 if (mode0 == V4SFmode)
29582 gen = gen_vec_extract_lo_v8sf;
29584 gen = gen_vec_extract_lo_v8si;
29585 if (!nonimmediate_operand (op0, GET_MODE (op0)))
29586 op0 = copy_to_mode_reg (GET_MODE (op0), op0);
29587 emit_insn (gen (half, op0));
29589 if (!nonimmediate_operand (op3, GET_MODE (op3)))
29590 op3 = copy_to_mode_reg (GET_MODE (op3), op3);
29591 emit_insn (gen (half, op3));
29595 /* Force memory operand only with base register here. But we
29596 don't want to do it on memory operand for other builtin
29598 if (GET_MODE (op1) != Pmode)
29599 op1 = convert_to_mode (Pmode, op1, 1);
29600 op1 = force_reg (Pmode, op1);
29602 if (!insn_data[icode].operand[1].predicate (op0, mode0))
29603 op0 = copy_to_mode_reg (mode0, op0);
29604 if (!insn_data[icode].operand[2].predicate (op1, Pmode))
29605 op1 = copy_to_mode_reg (Pmode, op1);
29606 if (!insn_data[icode].operand[3].predicate (op2, mode2))
29607 op2 = copy_to_mode_reg (mode2, op2);
29608 if (!insn_data[icode].operand[4].predicate (op3, mode3))
29609 op3 = copy_to_mode_reg (mode3, op3);
29610 if (!insn_data[icode].operand[5].predicate (op4, mode4))
29612 error ("last argument must be scale 1, 2, 4, 8");
29616 /* Optimize. If mask is known to have all high bits set,
29617 replace op0 with pc_rtx to signal that the instruction
29618 overwrites the whole destination and doesn't use its
29619 previous contents. */
29622 if (TREE_CODE (arg3) == VECTOR_CST)
29625 unsigned int negative = 0;
29626 for (elt = TREE_VECTOR_CST_ELTS (arg3);
29627 elt; elt = TREE_CHAIN (elt))
29629 tree cst = TREE_VALUE (elt);
29630 if (TREE_CODE (cst) == INTEGER_CST
29631 && tree_int_cst_sign_bit (cst))
29633 else if (TREE_CODE (cst) == REAL_CST
29634 && REAL_VALUE_NEGATIVE (TREE_REAL_CST (cst)))
29637 if (negative == TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg3)))
29640 else if (TREE_CODE (arg3) == SSA_NAME)
29642 /* Recognize also when mask is like:
29643 __v2df src = _mm_setzero_pd ();
29644 __v2df mask = _mm_cmpeq_pd (src, src);
29646 __v8sf src = _mm256_setzero_ps ();
29647 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
29648 as that is a cheaper way to load all ones into
29649 a register than having to load a constant from
29651 gimple def_stmt = SSA_NAME_DEF_STMT (arg3);
29652 if (is_gimple_call (def_stmt))
29654 tree fndecl = gimple_call_fndecl (def_stmt);
29656 && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
29657 switch ((unsigned int) DECL_FUNCTION_CODE (fndecl))
29659 case IX86_BUILTIN_CMPPD:
29660 case IX86_BUILTIN_CMPPS:
29661 case IX86_BUILTIN_CMPPD256:
29662 case IX86_BUILTIN_CMPPS256:
29663 if (!integer_zerop (gimple_call_arg (def_stmt, 2)))
29666 case IX86_BUILTIN_CMPEQPD:
29667 case IX86_BUILTIN_CMPEQPS:
29668 if (initializer_zerop (gimple_call_arg (def_stmt, 0))
29669 && initializer_zerop (gimple_call_arg (def_stmt,
29680 pat = GEN_FCN (icode) (subtarget, op0, op1, op2, op3, op4);
29685 if (fcode == IX86_BUILTIN_GATHERDIV8SF
29686 || fcode == IX86_BUILTIN_GATHERDIV8SI)
29688 enum machine_mode tmode = GET_MODE (subtarget) == V8SFmode
29689 ? V4SFmode : V4SImode;
29690 if (target == NULL_RTX)
29691 target = gen_reg_rtx (tmode);
29692 if (tmode == V4SFmode)
29693 emit_insn (gen_vec_extract_lo_v8sf (target, subtarget));
29695 emit_insn (gen_vec_extract_lo_v8si (target, subtarget));
29698 target = subtarget;
29706 for (i = 0, d = bdesc_special_args;
29707 i < ARRAY_SIZE (bdesc_special_args);
29709 if (d->code == fcode)
29710 return ix86_expand_special_args_builtin (d, exp, target);
29712 for (i = 0, d = bdesc_args;
29713 i < ARRAY_SIZE (bdesc_args);
29715 if (d->code == fcode)
29718 case IX86_BUILTIN_FABSQ:
29719 case IX86_BUILTIN_COPYSIGNQ:
29721 /* Emit a normal call if SSE2 isn't available. */
29722 return expand_call (exp, target, ignore);
29724 return ix86_expand_args_builtin (d, exp, target);
29727 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
29728 if (d->code == fcode)
29729 return ix86_expand_sse_comi (d, exp, target);
29731 for (i = 0, d = bdesc_pcmpestr;
29732 i < ARRAY_SIZE (bdesc_pcmpestr);
29734 if (d->code == fcode)
29735 return ix86_expand_sse_pcmpestr (d, exp, target);
29737 for (i = 0, d = bdesc_pcmpistr;
29738 i < ARRAY_SIZE (bdesc_pcmpistr);
29740 if (d->code == fcode)
29741 return ix86_expand_sse_pcmpistr (d, exp, target);
29743 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
29744 if (d->code == fcode)
29745 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
29746 (enum ix86_builtin_func_type)
29747 d->flag, d->comparison);
29749 gcc_unreachable ();
29752 /* Returns a function decl for a vectorized version of the builtin function
29753 with builtin function code FN and the result vector type TYPE, or NULL_TREE
29754 if it is not available. */
29757 ix86_builtin_vectorized_function (tree fndecl, tree type_out,
29760 enum machine_mode in_mode, out_mode;
29762 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
29764 if (TREE_CODE (type_out) != VECTOR_TYPE
29765 || TREE_CODE (type_in) != VECTOR_TYPE
29766 || DECL_BUILT_IN_CLASS (fndecl) != BUILT_IN_NORMAL)
29769 out_mode = TYPE_MODE (TREE_TYPE (type_out));
29770 out_n = TYPE_VECTOR_SUBPARTS (type_out);
29771 in_mode = TYPE_MODE (TREE_TYPE (type_in));
29772 in_n = TYPE_VECTOR_SUBPARTS (type_in);
29776 case BUILT_IN_SQRT:
29777 if (out_mode == DFmode && in_mode == DFmode)
29779 if (out_n == 2 && in_n == 2)
29780 return ix86_builtins[IX86_BUILTIN_SQRTPD];
29781 else if (out_n == 4 && in_n == 4)
29782 return ix86_builtins[IX86_BUILTIN_SQRTPD256];
29786 case BUILT_IN_SQRTF:
29787 if (out_mode == SFmode && in_mode == SFmode)
29789 if (out_n == 4 && in_n == 4)
29790 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
29791 else if (out_n == 8 && in_n == 8)
29792 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR256];
29796 case BUILT_IN_IFLOOR:
29797 case BUILT_IN_LFLOOR:
29798 case BUILT_IN_LLFLOOR:
29799 /* The round insn does not trap on denormals. */
29800 if (flag_trapping_math || !TARGET_ROUND)
29803 if (out_mode == SImode && in_mode == DFmode)
29805 if (out_n == 4 && in_n == 2)
29806 return ix86_builtins[IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX];
29807 else if (out_n == 8 && in_n == 4)
29808 return ix86_builtins[IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256];
29812 case BUILT_IN_IFLOORF:
29813 case BUILT_IN_LFLOORF:
29814 case BUILT_IN_LLFLOORF:
29815 /* The round insn does not trap on denormals. */
29816 if (flag_trapping_math || !TARGET_ROUND)
29819 if (out_mode == SImode && in_mode == SFmode)
29821 if (out_n == 4 && in_n == 4)
29822 return ix86_builtins[IX86_BUILTIN_FLOORPS_SFIX];
29823 else if (out_n == 8 && in_n == 8)
29824 return ix86_builtins[IX86_BUILTIN_FLOORPS_SFIX256];
29828 case BUILT_IN_ICEIL:
29829 case BUILT_IN_LCEIL:
29830 case BUILT_IN_LLCEIL:
29831 /* The round insn does not trap on denormals. */
29832 if (flag_trapping_math || !TARGET_ROUND)
29835 if (out_mode == SImode && in_mode == DFmode)
29837 if (out_n == 4 && in_n == 2)
29838 return ix86_builtins[IX86_BUILTIN_CEILPD_VEC_PACK_SFIX];
29839 else if (out_n == 8 && in_n == 4)
29840 return ix86_builtins[IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256];
29844 case BUILT_IN_ICEILF:
29845 case BUILT_IN_LCEILF:
29846 case BUILT_IN_LLCEILF:
29847 /* The round insn does not trap on denormals. */
29848 if (flag_trapping_math || !TARGET_ROUND)
29851 if (out_mode == SImode && in_mode == SFmode)
29853 if (out_n == 4 && in_n == 4)
29854 return ix86_builtins[IX86_BUILTIN_CEILPS_SFIX];
29855 else if (out_n == 8 && in_n == 8)
29856 return ix86_builtins[IX86_BUILTIN_CEILPS_SFIX256];
29860 case BUILT_IN_IRINT:
29861 case BUILT_IN_LRINT:
29862 case BUILT_IN_LLRINT:
29863 if (out_mode == SImode && in_mode == DFmode)
29865 if (out_n == 4 && in_n == 2)
29866 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
29867 else if (out_n == 8 && in_n == 4)
29868 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX256];
29872 case BUILT_IN_IRINTF:
29873 case BUILT_IN_LRINTF:
29874 case BUILT_IN_LLRINTF:
29875 if (out_mode == SImode && in_mode == SFmode)
29877 if (out_n == 4 && in_n == 4)
29878 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
29879 else if (out_n == 8 && in_n == 8)
29880 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ256];
29884 case BUILT_IN_IROUND:
29885 case BUILT_IN_LROUND:
29886 case BUILT_IN_LLROUND:
29887 /* The round insn does not trap on denormals. */
29888 if (flag_trapping_math || !TARGET_ROUND)
29891 if (out_mode == SImode && in_mode == DFmode)
29893 if (out_n == 4 && in_n == 2)
29894 return ix86_builtins[IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX];
29895 else if (out_n == 8 && in_n == 4)
29896 return ix86_builtins[IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256];
29900 case BUILT_IN_IROUNDF:
29901 case BUILT_IN_LROUNDF:
29902 case BUILT_IN_LLROUNDF:
29903 /* The round insn does not trap on denormals. */
29904 if (flag_trapping_math || !TARGET_ROUND)
29907 if (out_mode == SImode && in_mode == SFmode)
29909 if (out_n == 4 && in_n == 4)
29910 return ix86_builtins[IX86_BUILTIN_ROUNDPS_AZ_SFIX];
29911 else if (out_n == 8 && in_n == 8)
29912 return ix86_builtins[IX86_BUILTIN_ROUNDPS_AZ_SFIX256];
29916 case BUILT_IN_COPYSIGN:
29917 if (out_mode == DFmode && in_mode == DFmode)
29919 if (out_n == 2 && in_n == 2)
29920 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
29921 else if (out_n == 4 && in_n == 4)
29922 return ix86_builtins[IX86_BUILTIN_CPYSGNPD256];
29926 case BUILT_IN_COPYSIGNF:
29927 if (out_mode == SFmode && in_mode == SFmode)
29929 if (out_n == 4 && in_n == 4)
29930 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
29931 else if (out_n == 8 && in_n == 8)
29932 return ix86_builtins[IX86_BUILTIN_CPYSGNPS256];
29936 case BUILT_IN_FLOOR:
29937 /* The round insn does not trap on denormals. */
29938 if (flag_trapping_math || !TARGET_ROUND)
29941 if (out_mode == DFmode && in_mode == DFmode)
29943 if (out_n == 2 && in_n == 2)
29944 return ix86_builtins[IX86_BUILTIN_FLOORPD];
29945 else if (out_n == 4 && in_n == 4)
29946 return ix86_builtins[IX86_BUILTIN_FLOORPD256];
29950 case BUILT_IN_FLOORF:
29951 /* The round insn does not trap on denormals. */
29952 if (flag_trapping_math || !TARGET_ROUND)
29955 if (out_mode == SFmode && in_mode == SFmode)
29957 if (out_n == 4 && in_n == 4)
29958 return ix86_builtins[IX86_BUILTIN_FLOORPS];
29959 else if (out_n == 8 && in_n == 8)
29960 return ix86_builtins[IX86_BUILTIN_FLOORPS256];
29964 case BUILT_IN_CEIL:
29965 /* The round insn does not trap on denormals. */
29966 if (flag_trapping_math || !TARGET_ROUND)
29969 if (out_mode == DFmode && in_mode == DFmode)
29971 if (out_n == 2 && in_n == 2)
29972 return ix86_builtins[IX86_BUILTIN_CEILPD];
29973 else if (out_n == 4 && in_n == 4)
29974 return ix86_builtins[IX86_BUILTIN_CEILPD256];
29978 case BUILT_IN_CEILF:
29979 /* The round insn does not trap on denormals. */
29980 if (flag_trapping_math || !TARGET_ROUND)
29983 if (out_mode == SFmode && in_mode == SFmode)
29985 if (out_n == 4 && in_n == 4)
29986 return ix86_builtins[IX86_BUILTIN_CEILPS];
29987 else if (out_n == 8 && in_n == 8)
29988 return ix86_builtins[IX86_BUILTIN_CEILPS256];
29992 case BUILT_IN_TRUNC:
29993 /* The round insn does not trap on denormals. */
29994 if (flag_trapping_math || !TARGET_ROUND)
29997 if (out_mode == DFmode && in_mode == DFmode)
29999 if (out_n == 2 && in_n == 2)
30000 return ix86_builtins[IX86_BUILTIN_TRUNCPD];
30001 else if (out_n == 4 && in_n == 4)
30002 return ix86_builtins[IX86_BUILTIN_TRUNCPD256];
30006 case BUILT_IN_TRUNCF:
30007 /* The round insn does not trap on denormals. */
30008 if (flag_trapping_math || !TARGET_ROUND)
30011 if (out_mode == SFmode && in_mode == SFmode)
30013 if (out_n == 4 && in_n == 4)
30014 return ix86_builtins[IX86_BUILTIN_TRUNCPS];
30015 else if (out_n == 8 && in_n == 8)
30016 return ix86_builtins[IX86_BUILTIN_TRUNCPS256];
30020 case BUILT_IN_RINT:
30021 /* The round insn does not trap on denormals. */
30022 if (flag_trapping_math || !TARGET_ROUND)
30025 if (out_mode == DFmode && in_mode == DFmode)
30027 if (out_n == 2 && in_n == 2)
30028 return ix86_builtins[IX86_BUILTIN_RINTPD];
30029 else if (out_n == 4 && in_n == 4)
30030 return ix86_builtins[IX86_BUILTIN_RINTPD256];
30034 case BUILT_IN_RINTF:
30035 /* The round insn does not trap on denormals. */
30036 if (flag_trapping_math || !TARGET_ROUND)
30039 if (out_mode == SFmode && in_mode == SFmode)
30041 if (out_n == 4 && in_n == 4)
30042 return ix86_builtins[IX86_BUILTIN_RINTPS];
30043 else if (out_n == 8 && in_n == 8)
30044 return ix86_builtins[IX86_BUILTIN_RINTPS256];
30048 case BUILT_IN_ROUND:
30049 /* The round insn does not trap on denormals. */
30050 if (flag_trapping_math || !TARGET_ROUND)
30053 if (out_mode == DFmode && in_mode == DFmode)
30055 if (out_n == 2 && in_n == 2)
30056 return ix86_builtins[IX86_BUILTIN_ROUNDPD_AZ];
30057 else if (out_n == 4 && in_n == 4)
30058 return ix86_builtins[IX86_BUILTIN_ROUNDPD_AZ256];
30062 case BUILT_IN_ROUNDF:
30063 /* The round insn does not trap on denormals. */
30064 if (flag_trapping_math || !TARGET_ROUND)
30067 if (out_mode == SFmode && in_mode == SFmode)
30069 if (out_n == 4 && in_n == 4)
30070 return ix86_builtins[IX86_BUILTIN_ROUNDPS_AZ];
30071 else if (out_n == 8 && in_n == 8)
30072 return ix86_builtins[IX86_BUILTIN_ROUNDPS_AZ256];
30077 if (out_mode == DFmode && in_mode == DFmode)
30079 if (out_n == 2 && in_n == 2)
30080 return ix86_builtins[IX86_BUILTIN_VFMADDPD];
30081 if (out_n == 4 && in_n == 4)
30082 return ix86_builtins[IX86_BUILTIN_VFMADDPD256];
30086 case BUILT_IN_FMAF:
30087 if (out_mode == SFmode && in_mode == SFmode)
30089 if (out_n == 4 && in_n == 4)
30090 return ix86_builtins[IX86_BUILTIN_VFMADDPS];
30091 if (out_n == 8 && in_n == 8)
30092 return ix86_builtins[IX86_BUILTIN_VFMADDPS256];
30100 /* Dispatch to a handler for a vectorization library. */
30101 if (ix86_veclib_handler)
30102 return ix86_veclib_handler ((enum built_in_function) fn, type_out,
30108 /* Handler for an SVML-style interface to
30109 a library with vectorized intrinsics. */
30112 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
30115 tree fntype, new_fndecl, args;
30118 enum machine_mode el_mode, in_mode;
30121 /* The SVML is suitable for unsafe math only. */
30122 if (!flag_unsafe_math_optimizations)
30125 el_mode = TYPE_MODE (TREE_TYPE (type_out));
30126 n = TYPE_VECTOR_SUBPARTS (type_out);
30127 in_mode = TYPE_MODE (TREE_TYPE (type_in));
30128 in_n = TYPE_VECTOR_SUBPARTS (type_in);
30129 if (el_mode != in_mode
30137 case BUILT_IN_LOG10:
30139 case BUILT_IN_TANH:
30141 case BUILT_IN_ATAN:
30142 case BUILT_IN_ATAN2:
30143 case BUILT_IN_ATANH:
30144 case BUILT_IN_CBRT:
30145 case BUILT_IN_SINH:
30147 case BUILT_IN_ASINH:
30148 case BUILT_IN_ASIN:
30149 case BUILT_IN_COSH:
30151 case BUILT_IN_ACOSH:
30152 case BUILT_IN_ACOS:
30153 if (el_mode != DFmode || n != 2)
30157 case BUILT_IN_EXPF:
30158 case BUILT_IN_LOGF:
30159 case BUILT_IN_LOG10F:
30160 case BUILT_IN_POWF:
30161 case BUILT_IN_TANHF:
30162 case BUILT_IN_TANF:
30163 case BUILT_IN_ATANF:
30164 case BUILT_IN_ATAN2F:
30165 case BUILT_IN_ATANHF:
30166 case BUILT_IN_CBRTF:
30167 case BUILT_IN_SINHF:
30168 case BUILT_IN_SINF:
30169 case BUILT_IN_ASINHF:
30170 case BUILT_IN_ASINF:
30171 case BUILT_IN_COSHF:
30172 case BUILT_IN_COSF:
30173 case BUILT_IN_ACOSHF:
30174 case BUILT_IN_ACOSF:
30175 if (el_mode != SFmode || n != 4)
30183 bname = IDENTIFIER_POINTER (DECL_NAME (builtin_decl_implicit (fn)));
30185 if (fn == BUILT_IN_LOGF)
30186 strcpy (name, "vmlsLn4");
30187 else if (fn == BUILT_IN_LOG)
30188 strcpy (name, "vmldLn2");
30191 sprintf (name, "vmls%s", bname+10);
30192 name[strlen (name)-1] = '4';
30195 sprintf (name, "vmld%s2", bname+10);
30197 /* Convert to uppercase. */
30201 for (args = DECL_ARGUMENTS (builtin_decl_implicit (fn));
30203 args = TREE_CHAIN (args))
30207 fntype = build_function_type_list (type_out, type_in, NULL);
30209 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
30211 /* Build a function declaration for the vectorized function. */
30212 new_fndecl = build_decl (BUILTINS_LOCATION,
30213 FUNCTION_DECL, get_identifier (name), fntype);
30214 TREE_PUBLIC (new_fndecl) = 1;
30215 DECL_EXTERNAL (new_fndecl) = 1;
30216 DECL_IS_NOVOPS (new_fndecl) = 1;
30217 TREE_READONLY (new_fndecl) = 1;
30222 /* Handler for an ACML-style interface to
30223 a library with vectorized intrinsics. */
30226 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
30228 char name[20] = "__vr.._";
30229 tree fntype, new_fndecl, args;
30232 enum machine_mode el_mode, in_mode;
30235 /* The ACML is 64bits only and suitable for unsafe math only as
30236 it does not correctly support parts of IEEE with the required
30237 precision such as denormals. */
30239 || !flag_unsafe_math_optimizations)
30242 el_mode = TYPE_MODE (TREE_TYPE (type_out));
30243 n = TYPE_VECTOR_SUBPARTS (type_out);
30244 in_mode = TYPE_MODE (TREE_TYPE (type_in));
30245 in_n = TYPE_VECTOR_SUBPARTS (type_in);
30246 if (el_mode != in_mode
30256 case BUILT_IN_LOG2:
30257 case BUILT_IN_LOG10:
30260 if (el_mode != DFmode
30265 case BUILT_IN_SINF:
30266 case BUILT_IN_COSF:
30267 case BUILT_IN_EXPF:
30268 case BUILT_IN_POWF:
30269 case BUILT_IN_LOGF:
30270 case BUILT_IN_LOG2F:
30271 case BUILT_IN_LOG10F:
30274 if (el_mode != SFmode
30283 bname = IDENTIFIER_POINTER (DECL_NAME (builtin_decl_implicit (fn)));
30284 sprintf (name + 7, "%s", bname+10);
30287 for (args = DECL_ARGUMENTS (builtin_decl_implicit (fn));
30289 args = TREE_CHAIN (args))
30293 fntype = build_function_type_list (type_out, type_in, NULL);
30295 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
30297 /* Build a function declaration for the vectorized function. */
30298 new_fndecl = build_decl (BUILTINS_LOCATION,
30299 FUNCTION_DECL, get_identifier (name), fntype);
30300 TREE_PUBLIC (new_fndecl) = 1;
30301 DECL_EXTERNAL (new_fndecl) = 1;
30302 DECL_IS_NOVOPS (new_fndecl) = 1;
30303 TREE_READONLY (new_fndecl) = 1;
30308 /* Returns a decl of a function that implements gather load with
30309 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
30310 Return NULL_TREE if it is not available. */
30313 ix86_vectorize_builtin_gather (const_tree mem_vectype,
30314 const_tree index_type, int scale)
30317 enum ix86_builtins code;
30322 if ((TREE_CODE (index_type) != INTEGER_TYPE
30323 && !POINTER_TYPE_P (index_type))
30324 || (TYPE_MODE (index_type) != SImode
30325 && TYPE_MODE (index_type) != DImode))
30328 if (TYPE_PRECISION (index_type) > POINTER_SIZE)
30331 /* v*gather* insn sign extends index to pointer mode. */
30332 if (TYPE_PRECISION (index_type) < POINTER_SIZE
30333 && TYPE_UNSIGNED (index_type))
30338 || (scale & (scale - 1)) != 0)
30341 si = TYPE_MODE (index_type) == SImode;
30342 switch (TYPE_MODE (mem_vectype))
30345 code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF;
30348 code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF;
30351 code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI;
30354 code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI;
30357 code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF;
30360 code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF;
30363 code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI;
30366 code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI;
30372 return ix86_builtins[code];
30375 /* Returns a code for a target-specific builtin that implements
30376 reciprocal of the function, or NULL_TREE if not available. */
30379 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
30380 bool sqrt ATTRIBUTE_UNUSED)
30382 if (! (TARGET_SSE_MATH && !optimize_insn_for_size_p ()
30383 && flag_finite_math_only && !flag_trapping_math
30384 && flag_unsafe_math_optimizations))
30388 /* Machine dependent builtins. */
30391 /* Vectorized version of sqrt to rsqrt conversion. */
30392 case IX86_BUILTIN_SQRTPS_NR:
30393 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
30395 case IX86_BUILTIN_SQRTPS_NR256:
30396 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR256];
30402 /* Normal builtins. */
30405 /* Sqrt to rsqrt conversion. */
30406 case BUILT_IN_SQRTF:
30407 return ix86_builtins[IX86_BUILTIN_RSQRTF];
30414 /* Helper for avx_vpermilps256_operand et al. This is also used by
30415 the expansion functions to turn the parallel back into a mask.
30416 The return value is 0 for no match and the imm8+1 for a match. */
30419 avx_vpermilp_parallel (rtx par, enum machine_mode mode)
30421 unsigned i, nelt = GET_MODE_NUNITS (mode);
30423 unsigned char ipar[8];
30425 if (XVECLEN (par, 0) != (int) nelt)
30428 /* Validate that all of the elements are constants, and not totally
30429 out of range. Copy the data into an integral array to make the
30430 subsequent checks easier. */
30431 for (i = 0; i < nelt; ++i)
30433 rtx er = XVECEXP (par, 0, i);
30434 unsigned HOST_WIDE_INT ei;
30436 if (!CONST_INT_P (er))
30447 /* In the 256-bit DFmode case, we can only move elements within
30449 for (i = 0; i < 2; ++i)
30453 mask |= ipar[i] << i;
30455 for (i = 2; i < 4; ++i)
30459 mask |= (ipar[i] - 2) << i;
30464 /* In the 256-bit SFmode case, we have full freedom of movement
30465 within the low 128-bit lane, but the high 128-bit lane must
30466 mirror the exact same pattern. */
30467 for (i = 0; i < 4; ++i)
30468 if (ipar[i] + 4 != ipar[i + 4])
30475 /* In the 128-bit case, we've full freedom in the placement of
30476 the elements from the source operand. */
30477 for (i = 0; i < nelt; ++i)
30478 mask |= ipar[i] << (i * (nelt / 2));
30482 gcc_unreachable ();
30485 /* Make sure success has a non-zero value by adding one. */
30489 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
30490 the expansion functions to turn the parallel back into a mask.
30491 The return value is 0 for no match and the imm8+1 for a match. */
30494 avx_vperm2f128_parallel (rtx par, enum machine_mode mode)
30496 unsigned i, nelt = GET_MODE_NUNITS (mode), nelt2 = nelt / 2;
30498 unsigned char ipar[8];
30500 if (XVECLEN (par, 0) != (int) nelt)
30503 /* Validate that all of the elements are constants, and not totally
30504 out of range. Copy the data into an integral array to make the
30505 subsequent checks easier. */
30506 for (i = 0; i < nelt; ++i)
30508 rtx er = XVECEXP (par, 0, i);
30509 unsigned HOST_WIDE_INT ei;
30511 if (!CONST_INT_P (er))
30514 if (ei >= 2 * nelt)
30519 /* Validate that the halves of the permute are halves. */
30520 for (i = 0; i < nelt2 - 1; ++i)
30521 if (ipar[i] + 1 != ipar[i + 1])
30523 for (i = nelt2; i < nelt - 1; ++i)
30524 if (ipar[i] + 1 != ipar[i + 1])
30527 /* Reconstruct the mask. */
30528 for (i = 0; i < 2; ++i)
30530 unsigned e = ipar[i * nelt2];
30534 mask |= e << (i * 4);
30537 /* Make sure success has a non-zero value by adding one. */
30541 /* Store OPERAND to the memory after reload is completed. This means
30542 that we can't easily use assign_stack_local. */
30544 ix86_force_to_memory (enum machine_mode mode, rtx operand)
30548 gcc_assert (reload_completed);
30549 if (ix86_using_red_zone ())
30551 result = gen_rtx_MEM (mode,
30552 gen_rtx_PLUS (Pmode,
30554 GEN_INT (-RED_ZONE_SIZE)));
30555 emit_move_insn (result, operand);
30557 else if (TARGET_64BIT)
30563 operand = gen_lowpart (DImode, operand);
30567 gen_rtx_SET (VOIDmode,
30568 gen_rtx_MEM (DImode,
30569 gen_rtx_PRE_DEC (DImode,
30570 stack_pointer_rtx)),
30574 gcc_unreachable ();
30576 result = gen_rtx_MEM (mode, stack_pointer_rtx);
30585 split_double_mode (mode, &operand, 1, operands, operands + 1);
30587 gen_rtx_SET (VOIDmode,
30588 gen_rtx_MEM (SImode,
30589 gen_rtx_PRE_DEC (Pmode,
30590 stack_pointer_rtx)),
30593 gen_rtx_SET (VOIDmode,
30594 gen_rtx_MEM (SImode,
30595 gen_rtx_PRE_DEC (Pmode,
30596 stack_pointer_rtx)),
30601 /* Store HImodes as SImodes. */
30602 operand = gen_lowpart (SImode, operand);
30606 gen_rtx_SET (VOIDmode,
30607 gen_rtx_MEM (GET_MODE (operand),
30608 gen_rtx_PRE_DEC (SImode,
30609 stack_pointer_rtx)),
30613 gcc_unreachable ();
30615 result = gen_rtx_MEM (mode, stack_pointer_rtx);
30620 /* Free operand from the memory. */
30622 ix86_free_from_memory (enum machine_mode mode)
30624 if (!ix86_using_red_zone ())
30628 if (mode == DImode || TARGET_64BIT)
30632 /* Use LEA to deallocate stack space. In peephole2 it will be converted
30633 to pop or add instruction if registers are available. */
30634 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
30635 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
30640 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
30642 Put float CONST_DOUBLE in the constant pool instead of fp regs.
30643 QImode must go into class Q_REGS.
30644 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
30645 movdf to do mem-to-mem moves through integer regs. */
30648 ix86_preferred_reload_class (rtx x, reg_class_t regclass)
30650 enum machine_mode mode = GET_MODE (x);
30652 /* We're only allowed to return a subclass of CLASS. Many of the
30653 following checks fail for NO_REGS, so eliminate that early. */
30654 if (regclass == NO_REGS)
30657 /* All classes can load zeros. */
30658 if (x == CONST0_RTX (mode))
30661 /* Force constants into memory if we are loading a (nonzero) constant into
30662 an MMX or SSE register. This is because there are no MMX/SSE instructions
30663 to load from a constant. */
30665 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
30668 /* Prefer SSE regs only, if we can use them for math. */
30669 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
30670 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
30672 /* Floating-point constants need more complex checks. */
30673 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
30675 /* General regs can load everything. */
30676 if (reg_class_subset_p (regclass, GENERAL_REGS))
30679 /* Floats can load 0 and 1 plus some others. Note that we eliminated
30680 zero above. We only want to wind up preferring 80387 registers if
30681 we plan on doing computation with them. */
30683 && standard_80387_constant_p (x) > 0)
30685 /* Limit class to non-sse. */
30686 if (regclass == FLOAT_SSE_REGS)
30688 if (regclass == FP_TOP_SSE_REGS)
30690 if (regclass == FP_SECOND_SSE_REGS)
30691 return FP_SECOND_REG;
30692 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
30699 /* Generally when we see PLUS here, it's the function invariant
30700 (plus soft-fp const_int). Which can only be computed into general
30702 if (GET_CODE (x) == PLUS)
30703 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
30705 /* QImode constants are easy to load, but non-constant QImode data
30706 must go into Q_REGS. */
30707 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
30709 if (reg_class_subset_p (regclass, Q_REGS))
30711 if (reg_class_subset_p (Q_REGS, regclass))
30719 /* Discourage putting floating-point values in SSE registers unless
30720 SSE math is being used, and likewise for the 387 registers. */
30722 ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
30724 enum machine_mode mode = GET_MODE (x);
30726 /* Restrict the output reload class to the register bank that we are doing
30727 math on. If we would like not to return a subset of CLASS, reject this
30728 alternative: if reload cannot do this, it will still use its choice. */
30729 mode = GET_MODE (x);
30730 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
30731 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
30733 if (X87_FLOAT_MODE_P (mode))
30735 if (regclass == FP_TOP_SSE_REGS)
30737 else if (regclass == FP_SECOND_SSE_REGS)
30738 return FP_SECOND_REG;
30740 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
30747 ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
30748 enum machine_mode mode, secondary_reload_info *sri)
30750 /* Double-word spills from general registers to non-offsettable memory
30751 references (zero-extended addresses) require special handling. */
30754 && GET_MODE_SIZE (mode) > UNITS_PER_WORD
30755 && rclass == GENERAL_REGS
30756 && !offsettable_memref_p (x))
30759 ? CODE_FOR_reload_noff_load
30760 : CODE_FOR_reload_noff_store);
30761 /* Add the cost of moving address to a temporary. */
30762 sri->extra_cost = 1;
30767 /* QImode spills from non-QI registers require
30768 intermediate register on 32bit targets. */
30770 && !in_p && mode == QImode
30771 && (rclass == GENERAL_REGS
30772 || rclass == LEGACY_REGS
30773 || rclass == INDEX_REGS))
30782 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
30783 regno = true_regnum (x);
30785 /* Return Q_REGS if the operand is in memory. */
30790 /* This condition handles corner case where an expression involving
30791 pointers gets vectorized. We're trying to use the address of a
30792 stack slot as a vector initializer.
30794 (set (reg:V2DI 74 [ vect_cst_.2 ])
30795 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
30797 Eventually frame gets turned into sp+offset like this:
30799 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
30800 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
30801 (const_int 392 [0x188]))))
30803 That later gets turned into:
30805 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
30806 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
30807 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
30809 We'll have the following reload recorded:
30811 Reload 0: reload_in (DI) =
30812 (plus:DI (reg/f:DI 7 sp)
30813 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
30814 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
30815 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
30816 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
30817 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
30818 reload_reg_rtx: (reg:V2DI 22 xmm1)
30820 Which isn't going to work since SSE instructions can't handle scalar
30821 additions. Returning GENERAL_REGS forces the addition into integer
30822 register and reload can handle subsequent reloads without problems. */
30824 if (in_p && GET_CODE (x) == PLUS
30825 && SSE_CLASS_P (rclass)
30826 && SCALAR_INT_MODE_P (mode))
30827 return GENERAL_REGS;
30832 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
30835 ix86_class_likely_spilled_p (reg_class_t rclass)
30846 case SSE_FIRST_REG:
30848 case FP_SECOND_REG:
30858 /* If we are copying between general and FP registers, we need a memory
30859 location. The same is true for SSE and MMX registers.
30861 To optimize register_move_cost performance, allow inline variant.
30863 The macro can't work reliably when one of the CLASSES is class containing
30864 registers from multiple units (SSE, MMX, integer). We avoid this by never
30865 combining those units in single alternative in the machine description.
30866 Ensure that this constraint holds to avoid unexpected surprises.
30868 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
30869 enforce these sanity checks. */
30872 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
30873 enum machine_mode mode, int strict)
30875 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
30876 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
30877 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
30878 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
30879 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
30880 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
30882 gcc_assert (!strict);
30886 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
30889 /* ??? This is a lie. We do have moves between mmx/general, and for
30890 mmx/sse2. But by saying we need secondary memory we discourage the
30891 register allocator from using the mmx registers unless needed. */
30892 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
30895 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
30897 /* SSE1 doesn't have any direct moves from other classes. */
30901 /* If the target says that inter-unit moves are more expensive
30902 than moving through memory, then don't generate them. */
30903 if (!TARGET_INTER_UNIT_MOVES)
30906 /* Between SSE and general, we have moves no larger than word size. */
30907 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
30915 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
30916 enum machine_mode mode, int strict)
30918 return inline_secondary_memory_needed (class1, class2, mode, strict);
30921 /* Implement the TARGET_CLASS_MAX_NREGS hook.
30923 On the 80386, this is the size of MODE in words,
30924 except in the FP regs, where a single reg is always enough. */
30926 static unsigned char
30927 ix86_class_max_nregs (reg_class_t rclass, enum machine_mode mode)
30929 if (MAYBE_INTEGER_CLASS_P (rclass))
30931 if (mode == XFmode)
30932 return (TARGET_64BIT ? 2 : 3);
30933 else if (mode == XCmode)
30934 return (TARGET_64BIT ? 4 : 6);
30936 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
30940 if (COMPLEX_MODE_P (mode))
30947 /* Return true if the registers in CLASS cannot represent the change from
30948 modes FROM to TO. */
30951 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
30952 enum reg_class regclass)
30957 /* x87 registers can't do subreg at all, as all values are reformatted
30958 to extended precision. */
30959 if (MAYBE_FLOAT_CLASS_P (regclass))
30962 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
30964 /* Vector registers do not support QI or HImode loads. If we don't
30965 disallow a change to these modes, reload will assume it's ok to
30966 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
30967 the vec_dupv4hi pattern. */
30968 if (GET_MODE_SIZE (from) < 4)
30971 /* Vector registers do not support subreg with nonzero offsets, which
30972 are otherwise valid for integer registers. Since we can't see
30973 whether we have a nonzero offset from here, prohibit all
30974 nonparadoxical subregs changing size. */
30975 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
30982 /* Return the cost of moving data of mode M between a
30983 register and memory. A value of 2 is the default; this cost is
30984 relative to those in `REGISTER_MOVE_COST'.
30986 This function is used extensively by register_move_cost that is used to
30987 build tables at startup. Make it inline in this case.
30988 When IN is 2, return maximum of in and out move cost.
30990 If moving between registers and memory is more expensive than
30991 between two registers, you should define this macro to express the
30994 Model also increased moving costs of QImode registers in non
30998 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
31002 if (FLOAT_CLASS_P (regclass))
31020 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
31021 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
31023 if (SSE_CLASS_P (regclass))
31026 switch (GET_MODE_SIZE (mode))
31041 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
31042 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
31044 if (MMX_CLASS_P (regclass))
31047 switch (GET_MODE_SIZE (mode))
31059 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
31060 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
31062 switch (GET_MODE_SIZE (mode))
31065 if (Q_CLASS_P (regclass) || TARGET_64BIT)
31068 return ix86_cost->int_store[0];
31069 if (TARGET_PARTIAL_REG_DEPENDENCY
31070 && optimize_function_for_speed_p (cfun))
31071 cost = ix86_cost->movzbl_load;
31073 cost = ix86_cost->int_load[0];
31075 return MAX (cost, ix86_cost->int_store[0]);
31081 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
31083 return ix86_cost->movzbl_load;
31085 return ix86_cost->int_store[0] + 4;
31090 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
31091 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
31093 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
31094 if (mode == TFmode)
31097 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
31099 cost = ix86_cost->int_load[2];
31101 cost = ix86_cost->int_store[2];
31102 return (cost * (((int) GET_MODE_SIZE (mode)
31103 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
31108 ix86_memory_move_cost (enum machine_mode mode, reg_class_t regclass,
31111 return inline_memory_move_cost (mode, (enum reg_class) regclass, in ? 1 : 0);
31115 /* Return the cost of moving data from a register in class CLASS1 to
31116 one in class CLASS2.
31118 It is not required that the cost always equal 2 when FROM is the same as TO;
31119 on some machines it is expensive to move between registers if they are not
31120 general registers. */
31123 ix86_register_move_cost (enum machine_mode mode, reg_class_t class1_i,
31124 reg_class_t class2_i)
31126 enum reg_class class1 = (enum reg_class) class1_i;
31127 enum reg_class class2 = (enum reg_class) class2_i;
31129 /* In case we require secondary memory, compute cost of the store followed
31130 by load. In order to avoid bad register allocation choices, we need
31131 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
31133 if (inline_secondary_memory_needed (class1, class2, mode, 0))
31137 cost += inline_memory_move_cost (mode, class1, 2);
31138 cost += inline_memory_move_cost (mode, class2, 2);
31140 /* In case of copying from general_purpose_register we may emit multiple
31141 stores followed by single load causing memory size mismatch stall.
31142 Count this as arbitrarily high cost of 20. */
31143 if (targetm.class_max_nregs (class1, mode)
31144 > targetm.class_max_nregs (class2, mode))
31147 /* In the case of FP/MMX moves, the registers actually overlap, and we
31148 have to switch modes in order to treat them differently. */
31149 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
31150 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
31156 /* Moves between SSE/MMX and integer unit are expensive. */
31157 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
31158 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
31160 /* ??? By keeping returned value relatively high, we limit the number
31161 of moves between integer and MMX/SSE registers for all targets.
31162 Additionally, high value prevents problem with x86_modes_tieable_p(),
31163 where integer modes in MMX/SSE registers are not tieable
31164 because of missing QImode and HImode moves to, from or between
31165 MMX/SSE registers. */
31166 return MAX (8, ix86_cost->mmxsse_to_integer);
31168 if (MAYBE_FLOAT_CLASS_P (class1))
31169 return ix86_cost->fp_move;
31170 if (MAYBE_SSE_CLASS_P (class1))
31171 return ix86_cost->sse_move;
31172 if (MAYBE_MMX_CLASS_P (class1))
31173 return ix86_cost->mmx_move;
31177 /* Return TRUE if hard register REGNO can hold a value of machine-mode
31181 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
31183 /* Flags and only flags can only hold CCmode values. */
31184 if (CC_REGNO_P (regno))
31185 return GET_MODE_CLASS (mode) == MODE_CC;
31186 if (GET_MODE_CLASS (mode) == MODE_CC
31187 || GET_MODE_CLASS (mode) == MODE_RANDOM
31188 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
31190 if (FP_REGNO_P (regno))
31191 return VALID_FP_MODE_P (mode);
31192 if (SSE_REGNO_P (regno))
31194 /* We implement the move patterns for all vector modes into and
31195 out of SSE registers, even when no operation instructions
31196 are available. OImode move is available only when AVX is
31198 return ((TARGET_AVX && mode == OImode)
31199 || VALID_AVX256_REG_MODE (mode)
31200 || VALID_SSE_REG_MODE (mode)
31201 || VALID_SSE2_REG_MODE (mode)
31202 || VALID_MMX_REG_MODE (mode)
31203 || VALID_MMX_REG_MODE_3DNOW (mode));
31205 if (MMX_REGNO_P (regno))
31207 /* We implement the move patterns for 3DNOW modes even in MMX mode,
31208 so if the register is available at all, then we can move data of
31209 the given mode into or out of it. */
31210 return (VALID_MMX_REG_MODE (mode)
31211 || VALID_MMX_REG_MODE_3DNOW (mode));
31214 if (mode == QImode)
31216 /* Take care for QImode values - they can be in non-QI regs,
31217 but then they do cause partial register stalls. */
31218 if (regno <= BX_REG || TARGET_64BIT)
31220 if (!TARGET_PARTIAL_REG_STALL)
31222 return !can_create_pseudo_p ();
31224 /* We handle both integer and floats in the general purpose registers. */
31225 else if (VALID_INT_MODE_P (mode))
31227 else if (VALID_FP_MODE_P (mode))
31229 else if (VALID_DFP_MODE_P (mode))
31231 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
31232 on to use that value in smaller contexts, this can easily force a
31233 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
31234 supporting DImode, allow it. */
31235 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
31241 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
31242 tieable integer mode. */
31245 ix86_tieable_integer_mode_p (enum machine_mode mode)
31254 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
31257 return TARGET_64BIT;
31264 /* Return true if MODE1 is accessible in a register that can hold MODE2
31265 without copying. That is, all register classes that can hold MODE2
31266 can also hold MODE1. */
31269 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
31271 if (mode1 == mode2)
31274 if (ix86_tieable_integer_mode_p (mode1)
31275 && ix86_tieable_integer_mode_p (mode2))
31278 /* MODE2 being XFmode implies fp stack or general regs, which means we
31279 can tie any smaller floating point modes to it. Note that we do not
31280 tie this with TFmode. */
31281 if (mode2 == XFmode)
31282 return mode1 == SFmode || mode1 == DFmode;
31284 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
31285 that we can tie it with SFmode. */
31286 if (mode2 == DFmode)
31287 return mode1 == SFmode;
31289 /* If MODE2 is only appropriate for an SSE register, then tie with
31290 any other mode acceptable to SSE registers. */
31291 if (GET_MODE_SIZE (mode2) == 16
31292 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
31293 return (GET_MODE_SIZE (mode1) == 16
31294 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
31296 /* If MODE2 is appropriate for an MMX register, then tie
31297 with any other mode acceptable to MMX registers. */
31298 if (GET_MODE_SIZE (mode2) == 8
31299 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
31300 return (GET_MODE_SIZE (mode1) == 8
31301 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
31306 /* Compute a (partial) cost for rtx X. Return true if the complete
31307 cost has been computed, and false if subexpressions should be
31308 scanned. In either case, *TOTAL contains the cost result. */
31311 ix86_rtx_costs (rtx x, int code, int outer_code_i, int opno, int *total,
31314 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
31315 enum machine_mode mode = GET_MODE (x);
31316 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
31324 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
31326 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
31328 else if (flag_pic && SYMBOLIC_CONST (x)
31330 || (!GET_CODE (x) != LABEL_REF
31331 && (GET_CODE (x) != SYMBOL_REF
31332 || !SYMBOL_REF_LOCAL_P (x)))))
31339 if (mode == VOIDmode)
31342 switch (standard_80387_constant_p (x))
31347 default: /* Other constants */
31352 /* Start with (MEM (SYMBOL_REF)), since that's where
31353 it'll probably end up. Add a penalty for size. */
31354 *total = (COSTS_N_INSNS (1)
31355 + (flag_pic != 0 && !TARGET_64BIT)
31356 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
31362 /* The zero extensions is often completely free on x86_64, so make
31363 it as cheap as possible. */
31364 if (TARGET_64BIT && mode == DImode
31365 && GET_MODE (XEXP (x, 0)) == SImode)
31367 else if (TARGET_ZERO_EXTEND_WITH_AND)
31368 *total = cost->add;
31370 *total = cost->movzx;
31374 *total = cost->movsx;
31378 if (CONST_INT_P (XEXP (x, 1))
31379 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
31381 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
31384 *total = cost->add;
31387 if ((value == 2 || value == 3)
31388 && cost->lea <= cost->shift_const)
31390 *total = cost->lea;
31400 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
31402 if (CONST_INT_P (XEXP (x, 1)))
31404 if (INTVAL (XEXP (x, 1)) > 32)
31405 *total = cost->shift_const + COSTS_N_INSNS (2);
31407 *total = cost->shift_const * 2;
31411 if (GET_CODE (XEXP (x, 1)) == AND)
31412 *total = cost->shift_var * 2;
31414 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
31419 if (CONST_INT_P (XEXP (x, 1)))
31420 *total = cost->shift_const;
31422 *total = cost->shift_var;
31430 gcc_assert (FLOAT_MODE_P (mode));
31431 gcc_assert (TARGET_FMA || TARGET_FMA4);
31433 /* ??? SSE scalar/vector cost should be used here. */
31434 /* ??? Bald assumption that fma has the same cost as fmul. */
31435 *total = cost->fmul;
31436 *total += rtx_cost (XEXP (x, 1), FMA, 1, speed);
31438 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
31440 if (GET_CODE (sub) == NEG)
31441 sub = XEXP (sub, 0);
31442 *total += rtx_cost (sub, FMA, 0, speed);
31445 if (GET_CODE (sub) == NEG)
31446 sub = XEXP (sub, 0);
31447 *total += rtx_cost (sub, FMA, 2, speed);
31452 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31454 /* ??? SSE scalar cost should be used here. */
31455 *total = cost->fmul;
31458 else if (X87_FLOAT_MODE_P (mode))
31460 *total = cost->fmul;
31463 else if (FLOAT_MODE_P (mode))
31465 /* ??? SSE vector cost should be used here. */
31466 *total = cost->fmul;
31471 rtx op0 = XEXP (x, 0);
31472 rtx op1 = XEXP (x, 1);
31474 if (CONST_INT_P (XEXP (x, 1)))
31476 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
31477 for (nbits = 0; value != 0; value &= value - 1)
31481 /* This is arbitrary. */
31484 /* Compute costs correctly for widening multiplication. */
31485 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
31486 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
31487 == GET_MODE_SIZE (mode))
31489 int is_mulwiden = 0;
31490 enum machine_mode inner_mode = GET_MODE (op0);
31492 if (GET_CODE (op0) == GET_CODE (op1))
31493 is_mulwiden = 1, op1 = XEXP (op1, 0);
31494 else if (CONST_INT_P (op1))
31496 if (GET_CODE (op0) == SIGN_EXTEND)
31497 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
31500 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
31504 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
31507 *total = (cost->mult_init[MODE_INDEX (mode)]
31508 + nbits * cost->mult_bit
31509 + rtx_cost (op0, outer_code, opno, speed)
31510 + rtx_cost (op1, outer_code, opno, speed));
31519 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31520 /* ??? SSE cost should be used here. */
31521 *total = cost->fdiv;
31522 else if (X87_FLOAT_MODE_P (mode))
31523 *total = cost->fdiv;
31524 else if (FLOAT_MODE_P (mode))
31525 /* ??? SSE vector cost should be used here. */
31526 *total = cost->fdiv;
31528 *total = cost->divide[MODE_INDEX (mode)];
31532 if (GET_MODE_CLASS (mode) == MODE_INT
31533 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
31535 if (GET_CODE (XEXP (x, 0)) == PLUS
31536 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
31537 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
31538 && CONSTANT_P (XEXP (x, 1)))
31540 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
31541 if (val == 2 || val == 4 || val == 8)
31543 *total = cost->lea;
31544 *total += rtx_cost (XEXP (XEXP (x, 0), 1),
31545 outer_code, opno, speed);
31546 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
31547 outer_code, opno, speed);
31548 *total += rtx_cost (XEXP (x, 1), outer_code, opno, speed);
31552 else if (GET_CODE (XEXP (x, 0)) == MULT
31553 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
31555 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
31556 if (val == 2 || val == 4 || val == 8)
31558 *total = cost->lea;
31559 *total += rtx_cost (XEXP (XEXP (x, 0), 0),
31560 outer_code, opno, speed);
31561 *total += rtx_cost (XEXP (x, 1), outer_code, opno, speed);
31565 else if (GET_CODE (XEXP (x, 0)) == PLUS)
31567 *total = cost->lea;
31568 *total += rtx_cost (XEXP (XEXP (x, 0), 0),
31569 outer_code, opno, speed);
31570 *total += rtx_cost (XEXP (XEXP (x, 0), 1),
31571 outer_code, opno, speed);
31572 *total += rtx_cost (XEXP (x, 1), outer_code, opno, speed);
31579 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31581 /* ??? SSE cost should be used here. */
31582 *total = cost->fadd;
31585 else if (X87_FLOAT_MODE_P (mode))
31587 *total = cost->fadd;
31590 else if (FLOAT_MODE_P (mode))
31592 /* ??? SSE vector cost should be used here. */
31593 *total = cost->fadd;
31601 if (!TARGET_64BIT && mode == DImode)
31603 *total = (cost->add * 2
31604 + (rtx_cost (XEXP (x, 0), outer_code, opno, speed)
31605 << (GET_MODE (XEXP (x, 0)) != DImode))
31606 + (rtx_cost (XEXP (x, 1), outer_code, opno, speed)
31607 << (GET_MODE (XEXP (x, 1)) != DImode)));
31613 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31615 /* ??? SSE cost should be used here. */
31616 *total = cost->fchs;
31619 else if (X87_FLOAT_MODE_P (mode))
31621 *total = cost->fchs;
31624 else if (FLOAT_MODE_P (mode))
31626 /* ??? SSE vector cost should be used here. */
31627 *total = cost->fchs;
31633 if (!TARGET_64BIT && mode == DImode)
31634 *total = cost->add * 2;
31636 *total = cost->add;
31640 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
31641 && XEXP (XEXP (x, 0), 1) == const1_rtx
31642 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
31643 && XEXP (x, 1) == const0_rtx)
31645 /* This kind of construct is implemented using test[bwl].
31646 Treat it as if we had an AND. */
31647 *total = (cost->add
31648 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, opno, speed)
31649 + rtx_cost (const1_rtx, outer_code, opno, speed));
31655 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
31660 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31661 /* ??? SSE cost should be used here. */
31662 *total = cost->fabs;
31663 else if (X87_FLOAT_MODE_P (mode))
31664 *total = cost->fabs;
31665 else if (FLOAT_MODE_P (mode))
31666 /* ??? SSE vector cost should be used here. */
31667 *total = cost->fabs;
31671 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
31672 /* ??? SSE cost should be used here. */
31673 *total = cost->fsqrt;
31674 else if (X87_FLOAT_MODE_P (mode))
31675 *total = cost->fsqrt;
31676 else if (FLOAT_MODE_P (mode))
31677 /* ??? SSE vector cost should be used here. */
31678 *total = cost->fsqrt;
31682 if (XINT (x, 1) == UNSPEC_TP)
31689 case VEC_DUPLICATE:
31690 /* ??? Assume all of these vector manipulation patterns are
31691 recognizable. In which case they all pretty much have the
31693 *total = COSTS_N_INSNS (1);
31703 static int current_machopic_label_num;
31705 /* Given a symbol name and its associated stub, write out the
31706 definition of the stub. */
31709 machopic_output_stub (FILE *file, const char *symb, const char *stub)
31711 unsigned int length;
31712 char *binder_name, *symbol_name, lazy_ptr_name[32];
31713 int label = ++current_machopic_label_num;
31715 /* For 64-bit we shouldn't get here. */
31716 gcc_assert (!TARGET_64BIT);
31718 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
31719 symb = targetm.strip_name_encoding (symb);
31721 length = strlen (stub);
31722 binder_name = XALLOCAVEC (char, length + 32);
31723 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
31725 length = strlen (symb);
31726 symbol_name = XALLOCAVEC (char, length + 32);
31727 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
31729 sprintf (lazy_ptr_name, "L%d$lz", label);
31731 if (MACHOPIC_ATT_STUB)
31732 switch_to_section (darwin_sections[machopic_picsymbol_stub3_section]);
31733 else if (MACHOPIC_PURE)
31734 switch_to_section (darwin_sections[machopic_picsymbol_stub2_section]);
31736 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
31738 fprintf (file, "%s:\n", stub);
31739 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
31741 if (MACHOPIC_ATT_STUB)
31743 fprintf (file, "\thlt ; hlt ; hlt ; hlt ; hlt\n");
31745 else if (MACHOPIC_PURE)
31748 /* 25-byte PIC stub using "CALL get_pc_thunk". */
31749 rtx tmp = gen_rtx_REG (SImode, 2 /* ECX */);
31750 output_set_got (tmp, NULL_RTX); /* "CALL ___<cpu>.get_pc_thunk.cx". */
31751 fprintf (file, "LPC$%d:\tmovl\t%s-LPC$%d(%%ecx),%%ecx\n",
31752 label, lazy_ptr_name, label);
31753 fprintf (file, "\tjmp\t*%%ecx\n");
31756 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
31758 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
31759 it needs no stub-binding-helper. */
31760 if (MACHOPIC_ATT_STUB)
31763 fprintf (file, "%s:\n", binder_name);
31767 fprintf (file, "\tlea\t%s-%s(%%ecx),%%ecx\n", lazy_ptr_name, binder_name);
31768 fprintf (file, "\tpushl\t%%ecx\n");
31771 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
31773 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
31775 /* N.B. Keep the correspondence of these
31776 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
31777 old-pic/new-pic/non-pic stubs; altering this will break
31778 compatibility with existing dylibs. */
31781 /* 25-byte PIC stub using "CALL get_pc_thunk". */
31782 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr2_section]);
31785 /* 16-byte -mdynamic-no-pic stub. */
31786 switch_to_section(darwin_sections[machopic_lazy_symbol_ptr3_section]);
31788 fprintf (file, "%s:\n", lazy_ptr_name);
31789 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
31790 fprintf (file, ASM_LONG "%s\n", binder_name);
31792 #endif /* TARGET_MACHO */
31794 /* Order the registers for register allocator. */
31797 x86_order_regs_for_local_alloc (void)
31802 /* First allocate the local general purpose registers. */
31803 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
31804 if (GENERAL_REGNO_P (i) && call_used_regs[i])
31805 reg_alloc_order [pos++] = i;
31807 /* Global general purpose registers. */
31808 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
31809 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
31810 reg_alloc_order [pos++] = i;
31812 /* x87 registers come first in case we are doing FP math
31814 if (!TARGET_SSE_MATH)
31815 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
31816 reg_alloc_order [pos++] = i;
31818 /* SSE registers. */
31819 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
31820 reg_alloc_order [pos++] = i;
31821 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
31822 reg_alloc_order [pos++] = i;
31824 /* x87 registers. */
31825 if (TARGET_SSE_MATH)
31826 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
31827 reg_alloc_order [pos++] = i;
31829 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
31830 reg_alloc_order [pos++] = i;
31832 /* Initialize the rest of array as we do not allocate some registers
31834 while (pos < FIRST_PSEUDO_REGISTER)
31835 reg_alloc_order [pos++] = 0;
31838 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
31839 in struct attribute_spec handler. */
31841 ix86_handle_callee_pop_aggregate_return (tree *node, tree name,
31843 int flags ATTRIBUTE_UNUSED,
31844 bool *no_add_attrs)
31846 if (TREE_CODE (*node) != FUNCTION_TYPE
31847 && TREE_CODE (*node) != METHOD_TYPE
31848 && TREE_CODE (*node) != FIELD_DECL
31849 && TREE_CODE (*node) != TYPE_DECL)
31851 warning (OPT_Wattributes, "%qE attribute only applies to functions",
31853 *no_add_attrs = true;
31858 warning (OPT_Wattributes, "%qE attribute only available for 32-bit",
31860 *no_add_attrs = true;
31863 if (is_attribute_p ("callee_pop_aggregate_return", name))
31867 cst = TREE_VALUE (args);
31868 if (TREE_CODE (cst) != INTEGER_CST)
31870 warning (OPT_Wattributes,
31871 "%qE attribute requires an integer constant argument",
31873 *no_add_attrs = true;
31875 else if (compare_tree_int (cst, 0) != 0
31876 && compare_tree_int (cst, 1) != 0)
31878 warning (OPT_Wattributes,
31879 "argument to %qE attribute is neither zero, nor one",
31881 *no_add_attrs = true;
31890 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
31891 struct attribute_spec.handler. */
31893 ix86_handle_abi_attribute (tree *node, tree name,
31894 tree args ATTRIBUTE_UNUSED,
31895 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
31897 if (TREE_CODE (*node) != FUNCTION_TYPE
31898 && TREE_CODE (*node) != METHOD_TYPE
31899 && TREE_CODE (*node) != FIELD_DECL
31900 && TREE_CODE (*node) != TYPE_DECL)
31902 warning (OPT_Wattributes, "%qE attribute only applies to functions",
31904 *no_add_attrs = true;
31908 /* Can combine regparm with all attributes but fastcall. */
31909 if (is_attribute_p ("ms_abi", name))
31911 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
31913 error ("ms_abi and sysv_abi attributes are not compatible");
31918 else if (is_attribute_p ("sysv_abi", name))
31920 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
31922 error ("ms_abi and sysv_abi attributes are not compatible");
31931 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
31932 struct attribute_spec.handler. */
31934 ix86_handle_struct_attribute (tree *node, tree name,
31935 tree args ATTRIBUTE_UNUSED,
31936 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
31939 if (DECL_P (*node))
31941 if (TREE_CODE (*node) == TYPE_DECL)
31942 type = &TREE_TYPE (*node);
31947 if (!(type && RECORD_OR_UNION_TYPE_P (*type)))
31949 warning (OPT_Wattributes, "%qE attribute ignored",
31951 *no_add_attrs = true;
31954 else if ((is_attribute_p ("ms_struct", name)
31955 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
31956 || ((is_attribute_p ("gcc_struct", name)
31957 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
31959 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
31961 *no_add_attrs = true;
31968 ix86_handle_fndecl_attribute (tree *node, tree name,
31969 tree args ATTRIBUTE_UNUSED,
31970 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
31972 if (TREE_CODE (*node) != FUNCTION_DECL)
31974 warning (OPT_Wattributes, "%qE attribute only applies to functions",
31976 *no_add_attrs = true;
31982 ix86_ms_bitfield_layout_p (const_tree record_type)
31984 return ((TARGET_MS_BITFIELD_LAYOUT
31985 && !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
31986 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type)));
31989 /* Returns an expression indicating where the this parameter is
31990 located on entry to the FUNCTION. */
31993 x86_this_parameter (tree function)
31995 tree type = TREE_TYPE (function);
31996 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
32001 const int *parm_regs;
32003 if (ix86_function_type_abi (type) == MS_ABI)
32004 parm_regs = x86_64_ms_abi_int_parameter_registers;
32006 parm_regs = x86_64_int_parameter_registers;
32007 return gen_rtx_REG (DImode, parm_regs[aggr]);
32010 nregs = ix86_function_regparm (type, function);
32012 if (nregs > 0 && !stdarg_p (type))
32015 unsigned int ccvt = ix86_get_callcvt (type);
32017 if ((ccvt & IX86_CALLCVT_FASTCALL) != 0)
32018 regno = aggr ? DX_REG : CX_REG;
32019 else if ((ccvt & IX86_CALLCVT_THISCALL) != 0)
32023 return gen_rtx_MEM (SImode,
32024 plus_constant (stack_pointer_rtx, 4));
32033 return gen_rtx_MEM (SImode,
32034 plus_constant (stack_pointer_rtx, 4));
32037 return gen_rtx_REG (SImode, regno);
32040 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
32043 /* Determine whether x86_output_mi_thunk can succeed. */
32046 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
32047 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
32048 HOST_WIDE_INT vcall_offset, const_tree function)
32050 /* 64-bit can handle anything. */
32054 /* For 32-bit, everything's fine if we have one free register. */
32055 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
32058 /* Need a free register for vcall_offset. */
32062 /* Need a free register for GOT references. */
32063 if (flag_pic && !targetm.binds_local_p (function))
32066 /* Otherwise ok. */
32070 /* Output the assembler code for a thunk function. THUNK_DECL is the
32071 declaration for the thunk function itself, FUNCTION is the decl for
32072 the target function. DELTA is an immediate constant offset to be
32073 added to THIS. If VCALL_OFFSET is nonzero, the word at
32074 *(*this + vcall_offset) should be added to THIS. */
32077 x86_output_mi_thunk (FILE *file,
32078 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
32079 HOST_WIDE_INT vcall_offset, tree function)
32081 rtx this_param = x86_this_parameter (function);
32082 rtx this_reg, tmp, fnaddr;
32084 emit_note (NOTE_INSN_PROLOGUE_END);
32086 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
32087 pull it in now and let DELTA benefit. */
32088 if (REG_P (this_param))
32089 this_reg = this_param;
32090 else if (vcall_offset)
32092 /* Put the this parameter into %eax. */
32093 this_reg = gen_rtx_REG (Pmode, AX_REG);
32094 emit_move_insn (this_reg, this_param);
32097 this_reg = NULL_RTX;
32099 /* Adjust the this parameter by a fixed constant. */
32102 rtx delta_rtx = GEN_INT (delta);
32103 rtx delta_dst = this_reg ? this_reg : this_param;
32107 if (!x86_64_general_operand (delta_rtx, Pmode))
32109 tmp = gen_rtx_REG (Pmode, R10_REG);
32110 emit_move_insn (tmp, delta_rtx);
32115 ix86_emit_binop (PLUS, Pmode, delta_dst, delta_rtx);
32118 /* Adjust the this parameter by a value stored in the vtable. */
32121 rtx vcall_addr, vcall_mem, this_mem;
32122 unsigned int tmp_regno;
32125 tmp_regno = R10_REG;
32128 unsigned int ccvt = ix86_get_callcvt (TREE_TYPE (function));
32129 if ((ccvt & (IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) != 0)
32130 tmp_regno = AX_REG;
32132 tmp_regno = CX_REG;
32134 tmp = gen_rtx_REG (Pmode, tmp_regno);
32136 this_mem = gen_rtx_MEM (ptr_mode, this_reg);
32137 if (Pmode != ptr_mode)
32138 this_mem = gen_rtx_ZERO_EXTEND (Pmode, this_mem);
32139 emit_move_insn (tmp, this_mem);
32141 /* Adjust the this parameter. */
32142 vcall_addr = plus_constant (tmp, vcall_offset);
32144 && !ix86_legitimate_address_p (ptr_mode, vcall_addr, true))
32146 rtx tmp2 = gen_rtx_REG (Pmode, R11_REG);
32147 emit_move_insn (tmp2, GEN_INT (vcall_offset));
32148 vcall_addr = gen_rtx_PLUS (Pmode, tmp, tmp2);
32151 vcall_mem = gen_rtx_MEM (ptr_mode, vcall_addr);
32152 if (Pmode != ptr_mode)
32153 emit_insn (gen_addsi_1_zext (this_reg,
32154 gen_rtx_REG (ptr_mode,
32158 ix86_emit_binop (PLUS, Pmode, this_reg, vcall_mem);
32161 /* If necessary, drop THIS back to its stack slot. */
32162 if (this_reg && this_reg != this_param)
32163 emit_move_insn (this_param, this_reg);
32165 fnaddr = XEXP (DECL_RTL (function), 0);
32168 if (!flag_pic || targetm.binds_local_p (function)
32169 || cfun->machine->call_abi == MS_ABI)
32173 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOTPCREL);
32174 tmp = gen_rtx_CONST (Pmode, tmp);
32175 fnaddr = gen_rtx_MEM (Pmode, tmp);
32180 if (!flag_pic || targetm.binds_local_p (function))
32183 else if (TARGET_MACHO)
32185 fnaddr = machopic_indirect_call_target (DECL_RTL (function));
32186 fnaddr = XEXP (fnaddr, 0);
32188 #endif /* TARGET_MACHO */
32191 tmp = gen_rtx_REG (Pmode, CX_REG);
32192 output_set_got (tmp, NULL_RTX);
32194 fnaddr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, fnaddr), UNSPEC_GOT);
32195 fnaddr = gen_rtx_PLUS (Pmode, fnaddr, tmp);
32196 fnaddr = gen_rtx_MEM (Pmode, fnaddr);
32200 /* Our sibling call patterns do not allow memories, because we have no
32201 predicate that can distinguish between frame and non-frame memory.
32202 For our purposes here, we can get away with (ab)using a jump pattern,
32203 because we're going to do no optimization. */
32204 if (MEM_P (fnaddr))
32205 emit_jump_insn (gen_indirect_jump (fnaddr));
32208 tmp = gen_rtx_MEM (QImode, fnaddr);
32209 tmp = gen_rtx_CALL (VOIDmode, tmp, const0_rtx);
32210 tmp = emit_call_insn (tmp);
32211 SIBLING_CALL_P (tmp) = 1;
32215 /* Emit just enough of rest_of_compilation to get the insns emitted.
32216 Note that use_thunk calls assemble_start_function et al. */
32217 tmp = get_insns ();
32218 insn_locators_alloc ();
32219 shorten_branches (tmp);
32220 final_start_function (tmp, file, 1);
32221 final (tmp, file, 1);
32222 final_end_function ();
32226 x86_file_start (void)
32228 default_file_start ();
32230 darwin_file_start ();
32232 if (X86_FILE_START_VERSION_DIRECTIVE)
32233 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
32234 if (X86_FILE_START_FLTUSED)
32235 fputs ("\t.global\t__fltused\n", asm_out_file);
32236 if (ix86_asm_dialect == ASM_INTEL)
32237 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
32241 x86_field_alignment (tree field, int computed)
32243 enum machine_mode mode;
32244 tree type = TREE_TYPE (field);
32246 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
32248 mode = TYPE_MODE (strip_array_types (type));
32249 if (mode == DFmode || mode == DCmode
32250 || GET_MODE_CLASS (mode) == MODE_INT
32251 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
32252 return MIN (32, computed);
32256 /* Output assembler code to FILE to increment profiler label # LABELNO
32257 for profiling a function entry. */
32259 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
32261 const char *mcount_name = (flag_fentry ? MCOUNT_NAME_BEFORE_PROLOGUE
32266 #ifndef NO_PROFILE_COUNTERS
32267 fprintf (file, "\tleaq\t%sP%d(%%rip),%%r11\n", LPREFIX, labelno);
32270 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
32271 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", mcount_name);
32273 fprintf (file, "\tcall\t%s\n", mcount_name);
32277 #ifndef NO_PROFILE_COUNTERS
32278 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
32281 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", mcount_name);
32285 #ifndef NO_PROFILE_COUNTERS
32286 fprintf (file, "\tmovl\t$%sP%d,%%" PROFILE_COUNT_REGISTER "\n",
32289 fprintf (file, "\tcall\t%s\n", mcount_name);
32293 /* We don't have exact information about the insn sizes, but we may assume
32294 quite safely that we are informed about all 1 byte insns and memory
32295 address sizes. This is enough to eliminate unnecessary padding in
32299 min_insn_size (rtx insn)
32303 if (!INSN_P (insn) || !active_insn_p (insn))
32306 /* Discard alignments we've emit and jump instructions. */
32307 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
32308 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
32310 if (JUMP_TABLE_DATA_P (insn))
32313 /* Important case - calls are always 5 bytes.
32314 It is common to have many calls in the row. */
32316 && symbolic_reference_mentioned_p (PATTERN (insn))
32317 && !SIBLING_CALL_P (insn))
32319 len = get_attr_length (insn);
32323 /* For normal instructions we rely on get_attr_length being exact,
32324 with a few exceptions. */
32325 if (!JUMP_P (insn))
32327 enum attr_type type = get_attr_type (insn);
32332 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
32333 || asm_noperands (PATTERN (insn)) >= 0)
32340 /* Otherwise trust get_attr_length. */
32344 l = get_attr_length_address (insn);
32345 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
32354 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
32356 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
32360 ix86_avoid_jump_mispredicts (void)
32362 rtx insn, start = get_insns ();
32363 int nbytes = 0, njumps = 0;
32366 /* Look for all minimal intervals of instructions containing 4 jumps.
32367 The intervals are bounded by START and INSN. NBYTES is the total
32368 size of instructions in the interval including INSN and not including
32369 START. When the NBYTES is smaller than 16 bytes, it is possible
32370 that the end of START and INSN ends up in the same 16byte page.
32372 The smallest offset in the page INSN can start is the case where START
32373 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
32374 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
32376 for (insn = start; insn; insn = NEXT_INSN (insn))
32380 if (LABEL_P (insn))
32382 int align = label_to_alignment (insn);
32383 int max_skip = label_to_max_skip (insn);
32387 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
32388 already in the current 16 byte page, because otherwise
32389 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
32390 bytes to reach 16 byte boundary. */
32392 || (align <= 3 && max_skip != (1 << align) - 1))
32395 fprintf (dump_file, "Label %i with max_skip %i\n",
32396 INSN_UID (insn), max_skip);
32399 while (nbytes + max_skip >= 16)
32401 start = NEXT_INSN (start);
32402 if ((JUMP_P (start)
32403 && GET_CODE (PATTERN (start)) != ADDR_VEC
32404 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
32406 njumps--, isjump = 1;
32409 nbytes -= min_insn_size (start);
32415 min_size = min_insn_size (insn);
32416 nbytes += min_size;
32418 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
32419 INSN_UID (insn), min_size);
32421 && GET_CODE (PATTERN (insn)) != ADDR_VEC
32422 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
32430 start = NEXT_INSN (start);
32431 if ((JUMP_P (start)
32432 && GET_CODE (PATTERN (start)) != ADDR_VEC
32433 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
32435 njumps--, isjump = 1;
32438 nbytes -= min_insn_size (start);
32440 gcc_assert (njumps >= 0);
32442 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
32443 INSN_UID (start), INSN_UID (insn), nbytes);
32445 if (njumps == 3 && isjump && nbytes < 16)
32447 int padsize = 15 - nbytes + min_insn_size (insn);
32450 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
32451 INSN_UID (insn), padsize);
32452 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
32458 /* AMD Athlon works faster
32459 when RET is not destination of conditional jump or directly preceded
32460 by other jump instruction. We avoid the penalty by inserting NOP just
32461 before the RET instructions in such cases. */
32463 ix86_pad_returns (void)
32468 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
32470 basic_block bb = e->src;
32471 rtx ret = BB_END (bb);
32473 bool replace = false;
32475 if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret))
32476 || optimize_bb_for_size_p (bb))
32478 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
32479 if (active_insn_p (prev) || LABEL_P (prev))
32481 if (prev && LABEL_P (prev))
32486 FOR_EACH_EDGE (e, ei, bb->preds)
32487 if (EDGE_FREQUENCY (e) && e->src->index >= 0
32488 && !(e->flags & EDGE_FALLTHRU))
32493 prev = prev_active_insn (ret);
32495 && ((JUMP_P (prev) && any_condjump_p (prev))
32498 /* Empty functions get branch mispredict even when
32499 the jump destination is not visible to us. */
32500 if (!prev && !optimize_function_for_size_p (cfun))
32505 emit_jump_insn_before (gen_simple_return_internal_long (), ret);
32511 /* Count the minimum number of instructions in BB. Return 4 if the
32512 number of instructions >= 4. */
32515 ix86_count_insn_bb (basic_block bb)
32518 int insn_count = 0;
32520 /* Count number of instructions in this block. Return 4 if the number
32521 of instructions >= 4. */
32522 FOR_BB_INSNS (bb, insn)
32524 /* Only happen in exit blocks. */
32526 && ANY_RETURN_P (PATTERN (insn)))
32529 if (NONDEBUG_INSN_P (insn)
32530 && GET_CODE (PATTERN (insn)) != USE
32531 && GET_CODE (PATTERN (insn)) != CLOBBER)
32534 if (insn_count >= 4)
32543 /* Count the minimum number of instructions in code path in BB.
32544 Return 4 if the number of instructions >= 4. */
32547 ix86_count_insn (basic_block bb)
32551 int min_prev_count;
32553 /* Only bother counting instructions along paths with no
32554 more than 2 basic blocks between entry and exit. Given
32555 that BB has an edge to exit, determine if a predecessor
32556 of BB has an edge from entry. If so, compute the number
32557 of instructions in the predecessor block. If there
32558 happen to be multiple such blocks, compute the minimum. */
32559 min_prev_count = 4;
32560 FOR_EACH_EDGE (e, ei, bb->preds)
32563 edge_iterator prev_ei;
32565 if (e->src == ENTRY_BLOCK_PTR)
32567 min_prev_count = 0;
32570 FOR_EACH_EDGE (prev_e, prev_ei, e->src->preds)
32572 if (prev_e->src == ENTRY_BLOCK_PTR)
32574 int count = ix86_count_insn_bb (e->src);
32575 if (count < min_prev_count)
32576 min_prev_count = count;
32582 if (min_prev_count < 4)
32583 min_prev_count += ix86_count_insn_bb (bb);
32585 return min_prev_count;
32588 /* Pad short funtion to 4 instructions. */
32591 ix86_pad_short_function (void)
32596 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
32598 rtx ret = BB_END (e->src);
32599 if (JUMP_P (ret) && ANY_RETURN_P (PATTERN (ret)))
32601 int insn_count = ix86_count_insn (e->src);
32603 /* Pad short function. */
32604 if (insn_count < 4)
32608 /* Find epilogue. */
32611 || NOTE_KIND (insn) != NOTE_INSN_EPILOGUE_BEG))
32612 insn = PREV_INSN (insn);
32617 /* Two NOPs count as one instruction. */
32618 insn_count = 2 * (4 - insn_count);
32619 emit_insn_before (gen_nops (GEN_INT (insn_count)), insn);
32625 /* Implement machine specific optimizations. We implement padding of returns
32626 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
32630 /* We are freeing block_for_insn in the toplev to keep compatibility
32631 with old MDEP_REORGS that are not CFG based. Recompute it now. */
32632 compute_bb_for_insn ();
32634 /* Run the vzeroupper optimization if needed. */
32635 if (TARGET_VZEROUPPER)
32636 move_or_delete_vzeroupper ();
32638 if (optimize && optimize_function_for_speed_p (cfun))
32640 if (TARGET_PAD_SHORT_FUNCTION)
32641 ix86_pad_short_function ();
32642 else if (TARGET_PAD_RETURNS)
32643 ix86_pad_returns ();
32644 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
32645 if (TARGET_FOUR_JUMP_LIMIT)
32646 ix86_avoid_jump_mispredicts ();
32651 /* Return nonzero when QImode register that must be represented via REX prefix
32654 x86_extended_QIreg_mentioned_p (rtx insn)
32657 extract_insn_cached (insn);
32658 for (i = 0; i < recog_data.n_operands; i++)
32659 if (REG_P (recog_data.operand[i])
32660 && REGNO (recog_data.operand[i]) > BX_REG)
32665 /* Return nonzero when P points to register encoded via REX prefix.
32666 Called via for_each_rtx. */
32668 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
32670 unsigned int regno;
32673 regno = REGNO (*p);
32674 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
32677 /* Return true when INSN mentions register that must be encoded using REX
32680 x86_extended_reg_mentioned_p (rtx insn)
32682 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
32683 extended_reg_mentioned_1, NULL);
32686 /* If profitable, negate (without causing overflow) integer constant
32687 of mode MODE at location LOC. Return true in this case. */
32689 x86_maybe_negate_const_int (rtx *loc, enum machine_mode mode)
32693 if (!CONST_INT_P (*loc))
32699 /* DImode x86_64 constants must fit in 32 bits. */
32700 gcc_assert (x86_64_immediate_operand (*loc, mode));
32711 gcc_unreachable ();
32714 /* Avoid overflows. */
32715 if (mode_signbit_p (mode, *loc))
32718 val = INTVAL (*loc);
32720 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
32721 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
32722 if ((val < 0 && val != -128)
32725 *loc = GEN_INT (-val);
32732 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
32733 optabs would emit if we didn't have TFmode patterns. */
32736 x86_emit_floatuns (rtx operands[2])
32738 rtx neglab, donelab, i0, i1, f0, in, out;
32739 enum machine_mode mode, inmode;
32741 inmode = GET_MODE (operands[1]);
32742 gcc_assert (inmode == SImode || inmode == DImode);
32745 in = force_reg (inmode, operands[1]);
32746 mode = GET_MODE (out);
32747 neglab = gen_label_rtx ();
32748 donelab = gen_label_rtx ();
32749 f0 = gen_reg_rtx (mode);
32751 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
32753 expand_float (out, in, 0);
32755 emit_jump_insn (gen_jump (donelab));
32758 emit_label (neglab);
32760 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
32762 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
32764 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
32766 expand_float (f0, i0, 0);
32768 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
32770 emit_label (donelab);
32773 /* AVX2 does support 32-byte integer vector operations,
32774 thus the longest vector we are faced with is V32QImode. */
32775 #define MAX_VECT_LEN 32
32777 struct expand_vec_perm_d
32779 rtx target, op0, op1;
32780 unsigned char perm[MAX_VECT_LEN];
32781 enum machine_mode vmode;
32782 unsigned char nelt;
32786 static bool expand_vec_perm_1 (struct expand_vec_perm_d *d);
32787 static bool expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d);
32789 /* Get a vector mode of the same size as the original but with elements
32790 twice as wide. This is only guaranteed to apply to integral vectors. */
32792 static inline enum machine_mode
32793 get_mode_wider_vector (enum machine_mode o)
32795 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
32796 enum machine_mode n = GET_MODE_WIDER_MODE (o);
32797 gcc_assert (GET_MODE_NUNITS (o) == GET_MODE_NUNITS (n) * 2);
32798 gcc_assert (GET_MODE_SIZE (o) == GET_MODE_SIZE (n));
32802 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
32803 with all elements equal to VAR. Return true if successful. */
32806 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
32807 rtx target, rtx val)
32830 /* First attempt to recognize VAL as-is. */
32831 dup = gen_rtx_VEC_DUPLICATE (mode, val);
32832 insn = emit_insn (gen_rtx_SET (VOIDmode, target, dup));
32833 if (recog_memoized (insn) < 0)
32836 /* If that fails, force VAL into a register. */
32839 XEXP (dup, 0) = force_reg (GET_MODE_INNER (mode), val);
32840 seq = get_insns ();
32843 emit_insn_before (seq, insn);
32845 ok = recog_memoized (insn) >= 0;
32854 if (TARGET_SSE || TARGET_3DNOW_A)
32858 val = gen_lowpart (SImode, val);
32859 x = gen_rtx_TRUNCATE (HImode, val);
32860 x = gen_rtx_VEC_DUPLICATE (mode, x);
32861 emit_insn (gen_rtx_SET (VOIDmode, target, x));
32874 struct expand_vec_perm_d dperm;
32878 memset (&dperm, 0, sizeof (dperm));
32879 dperm.target = target;
32880 dperm.vmode = mode;
32881 dperm.nelt = GET_MODE_NUNITS (mode);
32882 dperm.op0 = dperm.op1 = gen_reg_rtx (mode);
32884 /* Extend to SImode using a paradoxical SUBREG. */
32885 tmp1 = gen_reg_rtx (SImode);
32886 emit_move_insn (tmp1, gen_lowpart (SImode, val));
32888 /* Insert the SImode value as low element of a V4SImode vector. */
32889 tmp2 = gen_lowpart (V4SImode, dperm.op0);
32890 emit_insn (gen_vec_setv4si_0 (tmp2, CONST0_RTX (V4SImode), tmp1));
32892 ok = (expand_vec_perm_1 (&dperm)
32893 || expand_vec_perm_broadcast_1 (&dperm));
32905 /* Replicate the value once into the next wider mode and recurse. */
32907 enum machine_mode smode, wsmode, wvmode;
32910 smode = GET_MODE_INNER (mode);
32911 wvmode = get_mode_wider_vector (mode);
32912 wsmode = GET_MODE_INNER (wvmode);
32914 val = convert_modes (wsmode, smode, val, true);
32915 x = expand_simple_binop (wsmode, ASHIFT, val,
32916 GEN_INT (GET_MODE_BITSIZE (smode)),
32917 NULL_RTX, 1, OPTAB_LIB_WIDEN);
32918 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
32920 x = gen_lowpart (wvmode, target);
32921 ok = ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val);
32929 enum machine_mode hvmode = (mode == V16HImode ? V8HImode : V16QImode);
32930 rtx x = gen_reg_rtx (hvmode);
32932 ok = ix86_expand_vector_init_duplicate (false, hvmode, x, val);
32935 x = gen_rtx_VEC_CONCAT (mode, x, x);
32936 emit_insn (gen_rtx_SET (VOIDmode, target, x));
32945 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
32946 whose ONE_VAR element is VAR, and other elements are zero. Return true
32950 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
32951 rtx target, rtx var, int one_var)
32953 enum machine_mode vsimode;
32956 bool use_vector_set = false;
32961 /* For SSE4.1, we normally use vector set. But if the second
32962 element is zero and inter-unit moves are OK, we use movq
32964 use_vector_set = (TARGET_64BIT
32966 && !(TARGET_INTER_UNIT_MOVES
32972 use_vector_set = TARGET_SSE4_1;
32975 use_vector_set = TARGET_SSE2;
32978 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
32985 use_vector_set = TARGET_AVX;
32988 /* Use ix86_expand_vector_set in 64bit mode only. */
32989 use_vector_set = TARGET_AVX && TARGET_64BIT;
32995 if (use_vector_set)
32997 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
32998 var = force_reg (GET_MODE_INNER (mode), var);
32999 ix86_expand_vector_set (mmx_ok, target, var, one_var);
33015 var = force_reg (GET_MODE_INNER (mode), var);
33016 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
33017 emit_insn (gen_rtx_SET (VOIDmode, target, x));
33022 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
33023 new_target = gen_reg_rtx (mode);
33025 new_target = target;
33026 var = force_reg (GET_MODE_INNER (mode), var);
33027 x = gen_rtx_VEC_DUPLICATE (mode, var);
33028 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
33029 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
33032 /* We need to shuffle the value to the correct position, so
33033 create a new pseudo to store the intermediate result. */
33035 /* With SSE2, we can use the integer shuffle insns. */
33036 if (mode != V4SFmode && TARGET_SSE2)
33038 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
33040 GEN_INT (one_var == 1 ? 0 : 1),
33041 GEN_INT (one_var == 2 ? 0 : 1),
33042 GEN_INT (one_var == 3 ? 0 : 1)));
33043 if (target != new_target)
33044 emit_move_insn (target, new_target);
33048 /* Otherwise convert the intermediate result to V4SFmode and
33049 use the SSE1 shuffle instructions. */
33050 if (mode != V4SFmode)
33052 tmp = gen_reg_rtx (V4SFmode);
33053 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
33058 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
33060 GEN_INT (one_var == 1 ? 0 : 1),
33061 GEN_INT (one_var == 2 ? 0+4 : 1+4),
33062 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
33064 if (mode != V4SFmode)
33065 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
33066 else if (tmp != target)
33067 emit_move_insn (target, tmp);
33069 else if (target != new_target)
33070 emit_move_insn (target, new_target);
33075 vsimode = V4SImode;
33081 vsimode = V2SImode;
33087 /* Zero extend the variable element to SImode and recurse. */
33088 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
33090 x = gen_reg_rtx (vsimode);
33091 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
33093 gcc_unreachable ();
33095 emit_move_insn (target, gen_lowpart (mode, x));
33103 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
33104 consisting of the values in VALS. It is known that all elements
33105 except ONE_VAR are constants. Return true if successful. */
33108 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
33109 rtx target, rtx vals, int one_var)
33111 rtx var = XVECEXP (vals, 0, one_var);
33112 enum machine_mode wmode;
33115 const_vec = copy_rtx (vals);
33116 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
33117 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
33125 /* For the two element vectors, it's just as easy to use
33126 the general case. */
33130 /* Use ix86_expand_vector_set in 64bit mode only. */
33153 /* There's no way to set one QImode entry easily. Combine
33154 the variable value with its adjacent constant value, and
33155 promote to an HImode set. */
33156 x = XVECEXP (vals, 0, one_var ^ 1);
33159 var = convert_modes (HImode, QImode, var, true);
33160 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
33161 NULL_RTX, 1, OPTAB_LIB_WIDEN);
33162 x = GEN_INT (INTVAL (x) & 0xff);
33166 var = convert_modes (HImode, QImode, var, true);
33167 x = gen_int_mode (INTVAL (x) << 8, HImode);
33169 if (x != const0_rtx)
33170 var = expand_simple_binop (HImode, IOR, var, x, var,
33171 1, OPTAB_LIB_WIDEN);
33173 x = gen_reg_rtx (wmode);
33174 emit_move_insn (x, gen_lowpart (wmode, const_vec));
33175 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
33177 emit_move_insn (target, gen_lowpart (mode, x));
33184 emit_move_insn (target, const_vec);
33185 ix86_expand_vector_set (mmx_ok, target, var, one_var);
33189 /* A subroutine of ix86_expand_vector_init_general. Use vector
33190 concatenate to handle the most general case: all values variable,
33191 and none identical. */
33194 ix86_expand_vector_init_concat (enum machine_mode mode,
33195 rtx target, rtx *ops, int n)
33197 enum machine_mode cmode, hmode = VOIDmode;
33198 rtx first[8], second[4];
33238 gcc_unreachable ();
33241 if (!register_operand (ops[1], cmode))
33242 ops[1] = force_reg (cmode, ops[1]);
33243 if (!register_operand (ops[0], cmode))
33244 ops[0] = force_reg (cmode, ops[0]);
33245 emit_insn (gen_rtx_SET (VOIDmode, target,
33246 gen_rtx_VEC_CONCAT (mode, ops[0],
33266 gcc_unreachable ();
33282 gcc_unreachable ();
33287 /* FIXME: We process inputs backward to help RA. PR 36222. */
33290 for (; i > 0; i -= 2, j--)
33292 first[j] = gen_reg_rtx (cmode);
33293 v = gen_rtvec (2, ops[i - 1], ops[i]);
33294 ix86_expand_vector_init (false, first[j],
33295 gen_rtx_PARALLEL (cmode, v));
33301 gcc_assert (hmode != VOIDmode);
33302 for (i = j = 0; i < n; i += 2, j++)
33304 second[j] = gen_reg_rtx (hmode);
33305 ix86_expand_vector_init_concat (hmode, second [j],
33309 ix86_expand_vector_init_concat (mode, target, second, n);
33312 ix86_expand_vector_init_concat (mode, target, first, n);
33316 gcc_unreachable ();
33320 /* A subroutine of ix86_expand_vector_init_general. Use vector
33321 interleave to handle the most general case: all values variable,
33322 and none identical. */
33325 ix86_expand_vector_init_interleave (enum machine_mode mode,
33326 rtx target, rtx *ops, int n)
33328 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
33331 rtx (*gen_load_even) (rtx, rtx, rtx);
33332 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
33333 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
33338 gen_load_even = gen_vec_setv8hi;
33339 gen_interleave_first_low = gen_vec_interleave_lowv4si;
33340 gen_interleave_second_low = gen_vec_interleave_lowv2di;
33341 inner_mode = HImode;
33342 first_imode = V4SImode;
33343 second_imode = V2DImode;
33344 third_imode = VOIDmode;
33347 gen_load_even = gen_vec_setv16qi;
33348 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
33349 gen_interleave_second_low = gen_vec_interleave_lowv4si;
33350 inner_mode = QImode;
33351 first_imode = V8HImode;
33352 second_imode = V4SImode;
33353 third_imode = V2DImode;
33356 gcc_unreachable ();
33359 for (i = 0; i < n; i++)
33361 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
33362 op0 = gen_reg_rtx (SImode);
33363 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
33365 /* Insert the SImode value as low element of V4SImode vector. */
33366 op1 = gen_reg_rtx (V4SImode);
33367 op0 = gen_rtx_VEC_MERGE (V4SImode,
33368 gen_rtx_VEC_DUPLICATE (V4SImode,
33370 CONST0_RTX (V4SImode),
33372 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
33374 /* Cast the V4SImode vector back to a vector in orignal mode. */
33375 op0 = gen_reg_rtx (mode);
33376 emit_move_insn (op0, gen_lowpart (mode, op1));
33378 /* Load even elements into the second positon. */
33379 emit_insn (gen_load_even (op0,
33380 force_reg (inner_mode,
33384 /* Cast vector to FIRST_IMODE vector. */
33385 ops[i] = gen_reg_rtx (first_imode);
33386 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
33389 /* Interleave low FIRST_IMODE vectors. */
33390 for (i = j = 0; i < n; i += 2, j++)
33392 op0 = gen_reg_rtx (first_imode);
33393 emit_insn (gen_interleave_first_low (op0, ops[i], ops[i + 1]));
33395 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
33396 ops[j] = gen_reg_rtx (second_imode);
33397 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
33400 /* Interleave low SECOND_IMODE vectors. */
33401 switch (second_imode)
33404 for (i = j = 0; i < n / 2; i += 2, j++)
33406 op0 = gen_reg_rtx (second_imode);
33407 emit_insn (gen_interleave_second_low (op0, ops[i],
33410 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
33412 ops[j] = gen_reg_rtx (third_imode);
33413 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
33415 second_imode = V2DImode;
33416 gen_interleave_second_low = gen_vec_interleave_lowv2di;
33420 op0 = gen_reg_rtx (second_imode);
33421 emit_insn (gen_interleave_second_low (op0, ops[0],
33424 /* Cast the SECOND_IMODE vector back to a vector on original
33426 emit_insn (gen_rtx_SET (VOIDmode, target,
33427 gen_lowpart (mode, op0)));
33431 gcc_unreachable ();
33435 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
33436 all values variable, and none identical. */
33439 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
33440 rtx target, rtx vals)
33442 rtx ops[32], op0, op1;
33443 enum machine_mode half_mode = VOIDmode;
33450 if (!mmx_ok && !TARGET_SSE)
33462 n = GET_MODE_NUNITS (mode);
33463 for (i = 0; i < n; i++)
33464 ops[i] = XVECEXP (vals, 0, i);
33465 ix86_expand_vector_init_concat (mode, target, ops, n);
33469 half_mode = V16QImode;
33473 half_mode = V8HImode;
33477 n = GET_MODE_NUNITS (mode);
33478 for (i = 0; i < n; i++)
33479 ops[i] = XVECEXP (vals, 0, i);
33480 op0 = gen_reg_rtx (half_mode);
33481 op1 = gen_reg_rtx (half_mode);
33482 ix86_expand_vector_init_interleave (half_mode, op0, ops,
33484 ix86_expand_vector_init_interleave (half_mode, op1,
33485 &ops [n >> 1], n >> 2);
33486 emit_insn (gen_rtx_SET (VOIDmode, target,
33487 gen_rtx_VEC_CONCAT (mode, op0, op1)));
33491 if (!TARGET_SSE4_1)
33499 /* Don't use ix86_expand_vector_init_interleave if we can't
33500 move from GPR to SSE register directly. */
33501 if (!TARGET_INTER_UNIT_MOVES)
33504 n = GET_MODE_NUNITS (mode);
33505 for (i = 0; i < n; i++)
33506 ops[i] = XVECEXP (vals, 0, i);
33507 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
33515 gcc_unreachable ();
33519 int i, j, n_elts, n_words, n_elt_per_word;
33520 enum machine_mode inner_mode;
33521 rtx words[4], shift;
33523 inner_mode = GET_MODE_INNER (mode);
33524 n_elts = GET_MODE_NUNITS (mode);
33525 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
33526 n_elt_per_word = n_elts / n_words;
33527 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
33529 for (i = 0; i < n_words; ++i)
33531 rtx word = NULL_RTX;
33533 for (j = 0; j < n_elt_per_word; ++j)
33535 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
33536 elt = convert_modes (word_mode, inner_mode, elt, true);
33542 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
33543 word, 1, OPTAB_LIB_WIDEN);
33544 word = expand_simple_binop (word_mode, IOR, word, elt,
33545 word, 1, OPTAB_LIB_WIDEN);
33553 emit_move_insn (target, gen_lowpart (mode, words[0]));
33554 else if (n_words == 2)
33556 rtx tmp = gen_reg_rtx (mode);
33557 emit_clobber (tmp);
33558 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
33559 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
33560 emit_move_insn (target, tmp);
33562 else if (n_words == 4)
33564 rtx tmp = gen_reg_rtx (V4SImode);
33565 gcc_assert (word_mode == SImode);
33566 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
33567 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
33568 emit_move_insn (target, gen_lowpart (mode, tmp));
33571 gcc_unreachable ();
33575 /* Initialize vector TARGET via VALS. Suppress the use of MMX
33576 instructions unless MMX_OK is true. */
33579 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
33581 enum machine_mode mode = GET_MODE (target);
33582 enum machine_mode inner_mode = GET_MODE_INNER (mode);
33583 int n_elts = GET_MODE_NUNITS (mode);
33584 int n_var = 0, one_var = -1;
33585 bool all_same = true, all_const_zero = true;
33589 for (i = 0; i < n_elts; ++i)
33591 x = XVECEXP (vals, 0, i);
33592 if (!(CONST_INT_P (x)
33593 || GET_CODE (x) == CONST_DOUBLE
33594 || GET_CODE (x) == CONST_FIXED))
33595 n_var++, one_var = i;
33596 else if (x != CONST0_RTX (inner_mode))
33597 all_const_zero = false;
33598 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
33602 /* Constants are best loaded from the constant pool. */
33605 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
33609 /* If all values are identical, broadcast the value. */
33611 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
33612 XVECEXP (vals, 0, 0)))
33615 /* Values where only one field is non-constant are best loaded from
33616 the pool and overwritten via move later. */
33620 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
33621 XVECEXP (vals, 0, one_var),
33625 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
33629 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
33633 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
33635 enum machine_mode mode = GET_MODE (target);
33636 enum machine_mode inner_mode = GET_MODE_INNER (mode);
33637 enum machine_mode half_mode;
33638 bool use_vec_merge = false;
33640 static rtx (*gen_extract[6][2]) (rtx, rtx)
33642 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
33643 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
33644 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
33645 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
33646 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
33647 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
33649 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
33651 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
33652 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
33653 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
33654 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
33655 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
33656 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
33666 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
33667 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
33669 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
33671 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
33672 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
33678 use_vec_merge = TARGET_SSE4_1 && TARGET_64BIT;
33682 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
33683 ix86_expand_vector_extract (false, tmp, target, 1 - elt);
33685 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
33687 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
33688 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
33695 /* For the two element vectors, we implement a VEC_CONCAT with
33696 the extraction of the other element. */
33698 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
33699 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
33702 op0 = val, op1 = tmp;
33704 op0 = tmp, op1 = val;
33706 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
33707 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
33712 use_vec_merge = TARGET_SSE4_1;
33719 use_vec_merge = true;
33723 /* tmp = target = A B C D */
33724 tmp = copy_to_reg (target);
33725 /* target = A A B B */
33726 emit_insn (gen_vec_interleave_lowv4sf (target, target, target));
33727 /* target = X A B B */
33728 ix86_expand_vector_set (false, target, val, 0);
33729 /* target = A X C D */
33730 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
33731 const1_rtx, const0_rtx,
33732 GEN_INT (2+4), GEN_INT (3+4)));
33736 /* tmp = target = A B C D */
33737 tmp = copy_to_reg (target);
33738 /* tmp = X B C D */
33739 ix86_expand_vector_set (false, tmp, val, 0);
33740 /* target = A B X D */
33741 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
33742 const0_rtx, const1_rtx,
33743 GEN_INT (0+4), GEN_INT (3+4)));
33747 /* tmp = target = A B C D */
33748 tmp = copy_to_reg (target);
33749 /* tmp = X B C D */
33750 ix86_expand_vector_set (false, tmp, val, 0);
33751 /* target = A B X D */
33752 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
33753 const0_rtx, const1_rtx,
33754 GEN_INT (2+4), GEN_INT (0+4)));
33758 gcc_unreachable ();
33763 use_vec_merge = TARGET_SSE4_1;
33767 /* Element 0 handled by vec_merge below. */
33770 use_vec_merge = true;
33776 /* With SSE2, use integer shuffles to swap element 0 and ELT,
33777 store into element 0, then shuffle them back. */
33781 order[0] = GEN_INT (elt);
33782 order[1] = const1_rtx;
33783 order[2] = const2_rtx;
33784 order[3] = GEN_INT (3);
33785 order[elt] = const0_rtx;
33787 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
33788 order[1], order[2], order[3]));
33790 ix86_expand_vector_set (false, target, val, 0);
33792 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
33793 order[1], order[2], order[3]));
33797 /* For SSE1, we have to reuse the V4SF code. */
33798 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
33799 gen_lowpart (SFmode, val), elt);
33804 use_vec_merge = TARGET_SSE2;
33807 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
33811 use_vec_merge = TARGET_SSE4_1;
33818 half_mode = V16QImode;
33824 half_mode = V8HImode;
33830 half_mode = V4SImode;
33836 half_mode = V2DImode;
33842 half_mode = V4SFmode;
33848 half_mode = V2DFmode;
33854 /* Compute offset. */
33858 gcc_assert (i <= 1);
33860 /* Extract the half. */
33861 tmp = gen_reg_rtx (half_mode);
33862 emit_insn (gen_extract[j][i] (tmp, target));
33864 /* Put val in tmp at elt. */
33865 ix86_expand_vector_set (false, tmp, val, elt);
33868 emit_insn (gen_insert[j][i] (target, target, tmp));
33877 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
33878 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
33879 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
33883 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
33885 emit_move_insn (mem, target);
33887 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
33888 emit_move_insn (tmp, val);
33890 emit_move_insn (target, mem);
33895 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
33897 enum machine_mode mode = GET_MODE (vec);
33898 enum machine_mode inner_mode = GET_MODE_INNER (mode);
33899 bool use_vec_extr = false;
33912 use_vec_extr = true;
33916 use_vec_extr = TARGET_SSE4_1;
33928 tmp = gen_reg_rtx (mode);
33929 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
33930 GEN_INT (elt), GEN_INT (elt),
33931 GEN_INT (elt+4), GEN_INT (elt+4)));
33935 tmp = gen_reg_rtx (mode);
33936 emit_insn (gen_vec_interleave_highv4sf (tmp, vec, vec));
33940 gcc_unreachable ();
33943 use_vec_extr = true;
33948 use_vec_extr = TARGET_SSE4_1;
33962 tmp = gen_reg_rtx (mode);
33963 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
33964 GEN_INT (elt), GEN_INT (elt),
33965 GEN_INT (elt), GEN_INT (elt)));
33969 tmp = gen_reg_rtx (mode);
33970 emit_insn (gen_vec_interleave_highv4si (tmp, vec, vec));
33974 gcc_unreachable ();
33977 use_vec_extr = true;
33982 /* For SSE1, we have to reuse the V4SF code. */
33983 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
33984 gen_lowpart (V4SFmode, vec), elt);
33990 use_vec_extr = TARGET_SSE2;
33993 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
33997 use_vec_extr = TARGET_SSE4_1;
34003 tmp = gen_reg_rtx (V4SFmode);
34005 emit_insn (gen_vec_extract_lo_v8sf (tmp, vec));
34007 emit_insn (gen_vec_extract_hi_v8sf (tmp, vec));
34008 ix86_expand_vector_extract (false, target, tmp, elt & 3);
34016 tmp = gen_reg_rtx (V2DFmode);
34018 emit_insn (gen_vec_extract_lo_v4df (tmp, vec));
34020 emit_insn (gen_vec_extract_hi_v4df (tmp, vec));
34021 ix86_expand_vector_extract (false, target, tmp, elt & 1);
34029 tmp = gen_reg_rtx (V16QImode);
34031 emit_insn (gen_vec_extract_lo_v32qi (tmp, vec));
34033 emit_insn (gen_vec_extract_hi_v32qi (tmp, vec));
34034 ix86_expand_vector_extract (false, target, tmp, elt & 15);
34042 tmp = gen_reg_rtx (V8HImode);
34044 emit_insn (gen_vec_extract_lo_v16hi (tmp, vec));
34046 emit_insn (gen_vec_extract_hi_v16hi (tmp, vec));
34047 ix86_expand_vector_extract (false, target, tmp, elt & 7);
34055 tmp = gen_reg_rtx (V4SImode);
34057 emit_insn (gen_vec_extract_lo_v8si (tmp, vec));
34059 emit_insn (gen_vec_extract_hi_v8si (tmp, vec));
34060 ix86_expand_vector_extract (false, target, tmp, elt & 3);
34068 tmp = gen_reg_rtx (V2DImode);
34070 emit_insn (gen_vec_extract_lo_v4di (tmp, vec));
34072 emit_insn (gen_vec_extract_hi_v4di (tmp, vec));
34073 ix86_expand_vector_extract (false, target, tmp, elt & 1);
34079 /* ??? Could extract the appropriate HImode element and shift. */
34086 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
34087 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
34089 /* Let the rtl optimizers know about the zero extension performed. */
34090 if (inner_mode == QImode || inner_mode == HImode)
34092 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
34093 target = gen_lowpart (SImode, target);
34096 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
34100 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
34102 emit_move_insn (mem, vec);
34104 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
34105 emit_move_insn (target, tmp);
34109 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
34110 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
34111 The upper bits of DEST are undefined, though they shouldn't cause
34112 exceptions (some bits from src or all zeros are ok). */
34115 emit_reduc_half (rtx dest, rtx src, int i)
34118 switch (GET_MODE (src))
34122 tem = gen_sse_movhlps (dest, src, src);
34124 tem = gen_sse_shufps_v4sf (dest, src, src, const1_rtx, const1_rtx,
34125 GEN_INT (1 + 4), GEN_INT (1 + 4));
34128 tem = gen_vec_interleave_highv2df (dest, src, src);
34134 tem = gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, dest),
34135 gen_lowpart (V1TImode, src),
34140 tem = gen_avx_vperm2f128v8sf3 (dest, src, src, const1_rtx);
34142 tem = gen_avx_shufps256 (dest, src, src,
34143 GEN_INT (i == 128 ? 2 + (3 << 2) : 1));
34147 tem = gen_avx_vperm2f128v4df3 (dest, src, src, const1_rtx);
34149 tem = gen_avx_shufpd256 (dest, src, src, const1_rtx);
34156 tem = gen_avx2_permv2ti (gen_lowpart (V4DImode, dest),
34157 gen_lowpart (V4DImode, src),
34158 gen_lowpart (V4DImode, src),
34161 tem = gen_avx2_lshrv2ti3 (gen_lowpart (V2TImode, dest),
34162 gen_lowpart (V2TImode, src),
34166 gcc_unreachable ();
34171 /* Expand a vector reduction. FN is the binary pattern to reduce;
34172 DEST is the destination; IN is the input vector. */
34175 ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
34177 rtx half, dst, vec = in;
34178 enum machine_mode mode = GET_MODE (in);
34181 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
34183 && mode == V8HImode
34184 && fn == gen_uminv8hi3)
34186 emit_insn (gen_sse4_1_phminposuw (dest, in));
34190 for (i = GET_MODE_BITSIZE (mode);
34191 i > GET_MODE_BITSIZE (GET_MODE_INNER (mode));
34194 half = gen_reg_rtx (mode);
34195 emit_reduc_half (half, vec, i);
34196 if (i == GET_MODE_BITSIZE (GET_MODE_INNER (mode)) * 2)
34199 dst = gen_reg_rtx (mode);
34200 emit_insn (fn (dst, half, vec));
34205 /* Target hook for scalar_mode_supported_p. */
34207 ix86_scalar_mode_supported_p (enum machine_mode mode)
34209 if (DECIMAL_FLOAT_MODE_P (mode))
34210 return default_decimal_float_supported_p ();
34211 else if (mode == TFmode)
34214 return default_scalar_mode_supported_p (mode);
34217 /* Implements target hook vector_mode_supported_p. */
34219 ix86_vector_mode_supported_p (enum machine_mode mode)
34221 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
34223 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
34225 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
34227 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
34229 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
34234 /* Target hook for c_mode_for_suffix. */
34235 static enum machine_mode
34236 ix86_c_mode_for_suffix (char suffix)
34246 /* Worker function for TARGET_MD_ASM_CLOBBERS.
34248 We do this in the new i386 backend to maintain source compatibility
34249 with the old cc0-based compiler. */
34252 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
34253 tree inputs ATTRIBUTE_UNUSED,
34256 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
34258 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
34263 /* Implements target vector targetm.asm.encode_section_info. */
34265 static void ATTRIBUTE_UNUSED
34266 ix86_encode_section_info (tree decl, rtx rtl, int first)
34268 default_encode_section_info (decl, rtl, first);
34270 if (TREE_CODE (decl) == VAR_DECL
34271 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
34272 && ix86_in_large_data_p (decl))
34273 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
34276 /* Worker function for REVERSE_CONDITION. */
34279 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
34281 return (mode != CCFPmode && mode != CCFPUmode
34282 ? reverse_condition (code)
34283 : reverse_condition_maybe_unordered (code));
34286 /* Output code to perform an x87 FP register move, from OPERANDS[1]
34290 output_387_reg_move (rtx insn, rtx *operands)
34292 if (REG_P (operands[0]))
34294 if (REG_P (operands[1])
34295 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
34297 if (REGNO (operands[0]) == FIRST_STACK_REG)
34298 return output_387_ffreep (operands, 0);
34299 return "fstp\t%y0";
34301 if (STACK_TOP_P (operands[0]))
34302 return "fld%Z1\t%y1";
34305 else if (MEM_P (operands[0]))
34307 gcc_assert (REG_P (operands[1]));
34308 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
34309 return "fstp%Z0\t%y0";
34312 /* There is no non-popping store to memory for XFmode.
34313 So if we need one, follow the store with a load. */
34314 if (GET_MODE (operands[0]) == XFmode)
34315 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
34317 return "fst%Z0\t%y0";
34324 /* Output code to perform a conditional jump to LABEL, if C2 flag in
34325 FP status register is set. */
34328 ix86_emit_fp_unordered_jump (rtx label)
34330 rtx reg = gen_reg_rtx (HImode);
34333 emit_insn (gen_x86_fnstsw_1 (reg));
34335 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
34337 emit_insn (gen_x86_sahf_1 (reg));
34339 temp = gen_rtx_REG (CCmode, FLAGS_REG);
34340 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
34344 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
34346 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
34347 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
34350 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
34351 gen_rtx_LABEL_REF (VOIDmode, label),
34353 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
34355 emit_jump_insn (temp);
34356 predict_jump (REG_BR_PROB_BASE * 10 / 100);
34359 /* Output code to perform a log1p XFmode calculation. */
34361 void ix86_emit_i387_log1p (rtx op0, rtx op1)
34363 rtx label1 = gen_label_rtx ();
34364 rtx label2 = gen_label_rtx ();
34366 rtx tmp = gen_reg_rtx (XFmode);
34367 rtx tmp2 = gen_reg_rtx (XFmode);
34370 emit_insn (gen_absxf2 (tmp, op1));
34371 test = gen_rtx_GE (VOIDmode, tmp,
34372 CONST_DOUBLE_FROM_REAL_VALUE (
34373 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
34375 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
34377 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
34378 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
34379 emit_jump (label2);
34381 emit_label (label1);
34382 emit_move_insn (tmp, CONST1_RTX (XFmode));
34383 emit_insn (gen_addxf3 (tmp, op1, tmp));
34384 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
34385 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
34387 emit_label (label2);
34390 /* Emit code for round calculation. */
34391 void ix86_emit_i387_round (rtx op0, rtx op1)
34393 enum machine_mode inmode = GET_MODE (op1);
34394 enum machine_mode outmode = GET_MODE (op0);
34395 rtx e1, e2, res, tmp, tmp1, half;
34396 rtx scratch = gen_reg_rtx (HImode);
34397 rtx flags = gen_rtx_REG (CCNOmode, FLAGS_REG);
34398 rtx jump_label = gen_label_rtx ();
34400 rtx (*gen_abs) (rtx, rtx);
34401 rtx (*gen_neg) (rtx, rtx);
34406 gen_abs = gen_abssf2;
34409 gen_abs = gen_absdf2;
34412 gen_abs = gen_absxf2;
34415 gcc_unreachable ();
34421 gen_neg = gen_negsf2;
34424 gen_neg = gen_negdf2;
34427 gen_neg = gen_negxf2;
34430 gen_neg = gen_neghi2;
34433 gen_neg = gen_negsi2;
34436 gen_neg = gen_negdi2;
34439 gcc_unreachable ();
34442 e1 = gen_reg_rtx (inmode);
34443 e2 = gen_reg_rtx (inmode);
34444 res = gen_reg_rtx (outmode);
34446 half = CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, inmode);
34448 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
34450 /* scratch = fxam(op1) */
34451 emit_insn (gen_rtx_SET (VOIDmode, scratch,
34452 gen_rtx_UNSPEC (HImode, gen_rtvec (1, op1),
34454 /* e1 = fabs(op1) */
34455 emit_insn (gen_abs (e1, op1));
34457 /* e2 = e1 + 0.5 */
34458 half = force_reg (inmode, half);
34459 emit_insn (gen_rtx_SET (VOIDmode, e2,
34460 gen_rtx_PLUS (inmode, e1, half)));
34462 /* res = floor(e2) */
34463 if (inmode != XFmode)
34465 tmp1 = gen_reg_rtx (XFmode);
34467 emit_insn (gen_rtx_SET (VOIDmode, tmp1,
34468 gen_rtx_FLOAT_EXTEND (XFmode, e2)));
34478 rtx tmp0 = gen_reg_rtx (XFmode);
34480 emit_insn (gen_frndintxf2_floor (tmp0, tmp1));
34482 emit_insn (gen_rtx_SET (VOIDmode, res,
34483 gen_rtx_UNSPEC (outmode, gen_rtvec (1, tmp0),
34484 UNSPEC_TRUNC_NOOP)));
34488 emit_insn (gen_frndintxf2_floor (res, tmp1));
34491 emit_insn (gen_lfloorxfhi2 (res, tmp1));
34494 emit_insn (gen_lfloorxfsi2 (res, tmp1));
34497 emit_insn (gen_lfloorxfdi2 (res, tmp1));
34500 gcc_unreachable ();
34503 /* flags = signbit(a) */
34504 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x02)));
34506 /* if (flags) then res = -res */
34507 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode,
34508 gen_rtx_EQ (VOIDmode, flags, const0_rtx),
34509 gen_rtx_LABEL_REF (VOIDmode, jump_label),
34511 insn = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
34512 predict_jump (REG_BR_PROB_BASE * 50 / 100);
34513 JUMP_LABEL (insn) = jump_label;
34515 emit_insn (gen_neg (res, res));
34517 emit_label (jump_label);
34518 LABEL_NUSES (jump_label) = 1;
34520 emit_move_insn (op0, res);
34523 /* Output code to perform a Newton-Rhapson approximation of a single precision
34524 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
34526 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
34528 rtx x0, x1, e0, e1;
34530 x0 = gen_reg_rtx (mode);
34531 e0 = gen_reg_rtx (mode);
34532 e1 = gen_reg_rtx (mode);
34533 x1 = gen_reg_rtx (mode);
34535 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
34537 b = force_reg (mode, b);
34539 /* x0 = rcp(b) estimate */
34540 emit_insn (gen_rtx_SET (VOIDmode, x0,
34541 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
34544 emit_insn (gen_rtx_SET (VOIDmode, e0,
34545 gen_rtx_MULT (mode, x0, b)));
34548 emit_insn (gen_rtx_SET (VOIDmode, e0,
34549 gen_rtx_MULT (mode, x0, e0)));
34552 emit_insn (gen_rtx_SET (VOIDmode, e1,
34553 gen_rtx_PLUS (mode, x0, x0)));
34556 emit_insn (gen_rtx_SET (VOIDmode, x1,
34557 gen_rtx_MINUS (mode, e1, e0)));
34560 emit_insn (gen_rtx_SET (VOIDmode, res,
34561 gen_rtx_MULT (mode, a, x1)));
34564 /* Output code to perform a Newton-Rhapson approximation of a
34565 single precision floating point [reciprocal] square root. */
34567 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
34570 rtx x0, e0, e1, e2, e3, mthree, mhalf;
34573 x0 = gen_reg_rtx (mode);
34574 e0 = gen_reg_rtx (mode);
34575 e1 = gen_reg_rtx (mode);
34576 e2 = gen_reg_rtx (mode);
34577 e3 = gen_reg_rtx (mode);
34579 real_from_integer (&r, VOIDmode, -3, -1, 0);
34580 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
34582 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
34583 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
34585 if (VECTOR_MODE_P (mode))
34587 mthree = ix86_build_const_vector (mode, true, mthree);
34588 mhalf = ix86_build_const_vector (mode, true, mhalf);
34591 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
34592 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
34594 a = force_reg (mode, a);
34596 /* x0 = rsqrt(a) estimate */
34597 emit_insn (gen_rtx_SET (VOIDmode, x0,
34598 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
34601 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
34606 zero = gen_reg_rtx (mode);
34607 mask = gen_reg_rtx (mode);
34609 zero = force_reg (mode, CONST0_RTX(mode));
34610 emit_insn (gen_rtx_SET (VOIDmode, mask,
34611 gen_rtx_NE (mode, zero, a)));
34613 emit_insn (gen_rtx_SET (VOIDmode, x0,
34614 gen_rtx_AND (mode, x0, mask)));
34618 emit_insn (gen_rtx_SET (VOIDmode, e0,
34619 gen_rtx_MULT (mode, x0, a)));
34621 emit_insn (gen_rtx_SET (VOIDmode, e1,
34622 gen_rtx_MULT (mode, e0, x0)));
34625 mthree = force_reg (mode, mthree);
34626 emit_insn (gen_rtx_SET (VOIDmode, e2,
34627 gen_rtx_PLUS (mode, e1, mthree)));
34629 mhalf = force_reg (mode, mhalf);
34631 /* e3 = -.5 * x0 */
34632 emit_insn (gen_rtx_SET (VOIDmode, e3,
34633 gen_rtx_MULT (mode, x0, mhalf)));
34635 /* e3 = -.5 * e0 */
34636 emit_insn (gen_rtx_SET (VOIDmode, e3,
34637 gen_rtx_MULT (mode, e0, mhalf)));
34638 /* ret = e2 * e3 */
34639 emit_insn (gen_rtx_SET (VOIDmode, res,
34640 gen_rtx_MULT (mode, e2, e3)));
34643 #ifdef TARGET_SOLARIS
34644 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
34647 i386_solaris_elf_named_section (const char *name, unsigned int flags,
34650 /* With Binutils 2.15, the "@unwind" marker must be specified on
34651 every occurrence of the ".eh_frame" section, not just the first
34654 && strcmp (name, ".eh_frame") == 0)
34656 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
34657 flags & SECTION_WRITE ? "aw" : "a");
34662 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
34664 solaris_elf_asm_comdat_section (name, flags, decl);
34669 default_elf_asm_named_section (name, flags, decl);
34671 #endif /* TARGET_SOLARIS */
34673 /* Return the mangling of TYPE if it is an extended fundamental type. */
34675 static const char *
34676 ix86_mangle_type (const_tree type)
34678 type = TYPE_MAIN_VARIANT (type);
34680 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
34681 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
34684 switch (TYPE_MODE (type))
34687 /* __float128 is "g". */
34690 /* "long double" or __float80 is "e". */
34697 /* For 32-bit code we can save PIC register setup by using
34698 __stack_chk_fail_local hidden function instead of calling
34699 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
34700 register, so it is better to call __stack_chk_fail directly. */
34702 static tree ATTRIBUTE_UNUSED
34703 ix86_stack_protect_fail (void)
34705 return TARGET_64BIT
34706 ? default_external_stack_protect_fail ()
34707 : default_hidden_stack_protect_fail ();
34710 /* Select a format to encode pointers in exception handling data. CODE
34711 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
34712 true if the symbol may be affected by dynamic relocations.
34714 ??? All x86 object file formats are capable of representing this.
34715 After all, the relocation needed is the same as for the call insn.
34716 Whether or not a particular assembler allows us to enter such, I
34717 guess we'll have to see. */
34719 asm_preferred_eh_data_format (int code, int global)
34723 int type = DW_EH_PE_sdata8;
34725 || ix86_cmodel == CM_SMALL_PIC
34726 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
34727 type = DW_EH_PE_sdata4;
34728 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
34730 if (ix86_cmodel == CM_SMALL
34731 || (ix86_cmodel == CM_MEDIUM && code))
34732 return DW_EH_PE_udata4;
34733 return DW_EH_PE_absptr;
34736 /* Expand copysign from SIGN to the positive value ABS_VALUE
34737 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
34740 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
34742 enum machine_mode mode = GET_MODE (sign);
34743 rtx sgn = gen_reg_rtx (mode);
34744 if (mask == NULL_RTX)
34746 enum machine_mode vmode;
34748 if (mode == SFmode)
34750 else if (mode == DFmode)
34755 mask = ix86_build_signbit_mask (vmode, VECTOR_MODE_P (mode), false);
34756 if (!VECTOR_MODE_P (mode))
34758 /* We need to generate a scalar mode mask in this case. */
34759 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
34760 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
34761 mask = gen_reg_rtx (mode);
34762 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
34766 mask = gen_rtx_NOT (mode, mask);
34767 emit_insn (gen_rtx_SET (VOIDmode, sgn,
34768 gen_rtx_AND (mode, mask, sign)));
34769 emit_insn (gen_rtx_SET (VOIDmode, result,
34770 gen_rtx_IOR (mode, abs_value, sgn)));
34773 /* Expand fabs (OP0) and return a new rtx that holds the result. The
34774 mask for masking out the sign-bit is stored in *SMASK, if that is
34777 ix86_expand_sse_fabs (rtx op0, rtx *smask)
34779 enum machine_mode vmode, mode = GET_MODE (op0);
34782 xa = gen_reg_rtx (mode);
34783 if (mode == SFmode)
34785 else if (mode == DFmode)
34789 mask = ix86_build_signbit_mask (vmode, VECTOR_MODE_P (mode), true);
34790 if (!VECTOR_MODE_P (mode))
34792 /* We need to generate a scalar mode mask in this case. */
34793 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
34794 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
34795 mask = gen_reg_rtx (mode);
34796 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
34798 emit_insn (gen_rtx_SET (VOIDmode, xa,
34799 gen_rtx_AND (mode, op0, mask)));
34807 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
34808 swapping the operands if SWAP_OPERANDS is true. The expanded
34809 code is a forward jump to a newly created label in case the
34810 comparison is true. The generated label rtx is returned. */
34812 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
34813 bool swap_operands)
34824 label = gen_label_rtx ();
34825 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
34826 emit_insn (gen_rtx_SET (VOIDmode, tmp,
34827 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
34828 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
34829 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
34830 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
34831 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
34832 JUMP_LABEL (tmp) = label;
34837 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
34838 using comparison code CODE. Operands are swapped for the comparison if
34839 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
34841 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
34842 bool swap_operands)
34844 rtx (*insn)(rtx, rtx, rtx, rtx);
34845 enum machine_mode mode = GET_MODE (op0);
34846 rtx mask = gen_reg_rtx (mode);
34855 insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse;
34857 emit_insn (insn (mask, op0, op1,
34858 gen_rtx_fmt_ee (code, mode, op0, op1)));
34862 /* Generate and return a rtx of mode MODE for 2**n where n is the number
34863 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
34865 ix86_gen_TWO52 (enum machine_mode mode)
34867 REAL_VALUE_TYPE TWO52r;
34870 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
34871 TWO52 = const_double_from_real_value (TWO52r, mode);
34872 TWO52 = force_reg (mode, TWO52);
34877 /* Expand SSE sequence for computing lround from OP1 storing
34880 ix86_expand_lround (rtx op0, rtx op1)
34882 /* C code for the stuff we're doing below:
34883 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
34886 enum machine_mode mode = GET_MODE (op1);
34887 const struct real_format *fmt;
34888 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
34891 /* load nextafter (0.5, 0.0) */
34892 fmt = REAL_MODE_FORMAT (mode);
34893 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
34894 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
34896 /* adj = copysign (0.5, op1) */
34897 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
34898 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
34900 /* adj = op1 + adj */
34901 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
34903 /* op0 = (imode)adj */
34904 expand_fix (op0, adj, 0);
34907 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
34910 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
34912 /* C code for the stuff we're doing below (for do_floor):
34914 xi -= (double)xi > op1 ? 1 : 0;
34917 enum machine_mode fmode = GET_MODE (op1);
34918 enum machine_mode imode = GET_MODE (op0);
34919 rtx ireg, freg, label, tmp;
34921 /* reg = (long)op1 */
34922 ireg = gen_reg_rtx (imode);
34923 expand_fix (ireg, op1, 0);
34925 /* freg = (double)reg */
34926 freg = gen_reg_rtx (fmode);
34927 expand_float (freg, ireg, 0);
34929 /* ireg = (freg > op1) ? ireg - 1 : ireg */
34930 label = ix86_expand_sse_compare_and_jump (UNLE,
34931 freg, op1, !do_floor);
34932 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
34933 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
34934 emit_move_insn (ireg, tmp);
34936 emit_label (label);
34937 LABEL_NUSES (label) = 1;
34939 emit_move_insn (op0, ireg);
34942 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
34943 result in OPERAND0. */
34945 ix86_expand_rint (rtx operand0, rtx operand1)
34947 /* C code for the stuff we're doing below:
34948 xa = fabs (operand1);
34949 if (!isless (xa, 2**52))
34951 xa = xa + 2**52 - 2**52;
34952 return copysign (xa, operand1);
34954 enum machine_mode mode = GET_MODE (operand0);
34955 rtx res, xa, label, TWO52, mask;
34957 res = gen_reg_rtx (mode);
34958 emit_move_insn (res, operand1);
34960 /* xa = abs (operand1) */
34961 xa = ix86_expand_sse_fabs (res, &mask);
34963 /* if (!isless (xa, TWO52)) goto label; */
34964 TWO52 = ix86_gen_TWO52 (mode);
34965 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
34967 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
34968 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
34970 ix86_sse_copysign_to_positive (res, xa, res, mask);
34972 emit_label (label);
34973 LABEL_NUSES (label) = 1;
34975 emit_move_insn (operand0, res);
34978 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
34981 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
34983 /* C code for the stuff we expand below.
34984 double xa = fabs (x), x2;
34985 if (!isless (xa, TWO52))
34987 xa = xa + TWO52 - TWO52;
34988 x2 = copysign (xa, x);
34997 enum machine_mode mode = GET_MODE (operand0);
34998 rtx xa, TWO52, tmp, label, one, res, mask;
35000 TWO52 = ix86_gen_TWO52 (mode);
35002 /* Temporary for holding the result, initialized to the input
35003 operand to ease control flow. */
35004 res = gen_reg_rtx (mode);
35005 emit_move_insn (res, operand1);
35007 /* xa = abs (operand1) */
35008 xa = ix86_expand_sse_fabs (res, &mask);
35010 /* if (!isless (xa, TWO52)) goto label; */
35011 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35013 /* xa = xa + TWO52 - TWO52; */
35014 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
35015 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
35017 /* xa = copysign (xa, operand1) */
35018 ix86_sse_copysign_to_positive (xa, xa, res, mask);
35020 /* generate 1.0 or -1.0 */
35021 one = force_reg (mode,
35022 const_double_from_real_value (do_floor
35023 ? dconst1 : dconstm1, mode));
35025 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
35026 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
35027 emit_insn (gen_rtx_SET (VOIDmode, tmp,
35028 gen_rtx_AND (mode, one, tmp)));
35029 /* We always need to subtract here to preserve signed zero. */
35030 tmp = expand_simple_binop (mode, MINUS,
35031 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
35032 emit_move_insn (res, tmp);
35034 emit_label (label);
35035 LABEL_NUSES (label) = 1;
35037 emit_move_insn (operand0, res);
35040 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
35043 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
35045 /* C code for the stuff we expand below.
35046 double xa = fabs (x), x2;
35047 if (!isless (xa, TWO52))
35049 x2 = (double)(long)x;
35056 if (HONOR_SIGNED_ZEROS (mode))
35057 return copysign (x2, x);
35060 enum machine_mode mode = GET_MODE (operand0);
35061 rtx xa, xi, TWO52, tmp, label, one, res, mask;
35063 TWO52 = ix86_gen_TWO52 (mode);
35065 /* Temporary for holding the result, initialized to the input
35066 operand to ease control flow. */
35067 res = gen_reg_rtx (mode);
35068 emit_move_insn (res, operand1);
35070 /* xa = abs (operand1) */
35071 xa = ix86_expand_sse_fabs (res, &mask);
35073 /* if (!isless (xa, TWO52)) goto label; */
35074 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35076 /* xa = (double)(long)x */
35077 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
35078 expand_fix (xi, res, 0);
35079 expand_float (xa, xi, 0);
35082 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
35084 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
35085 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
35086 emit_insn (gen_rtx_SET (VOIDmode, tmp,
35087 gen_rtx_AND (mode, one, tmp)));
35088 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
35089 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
35090 emit_move_insn (res, tmp);
35092 if (HONOR_SIGNED_ZEROS (mode))
35093 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
35095 emit_label (label);
35096 LABEL_NUSES (label) = 1;
35098 emit_move_insn (operand0, res);
35101 /* Expand SSE sequence for computing round from OPERAND1 storing
35102 into OPERAND0. Sequence that works without relying on DImode truncation
35103 via cvttsd2siq that is only available on 64bit targets. */
35105 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
35107 /* C code for the stuff we expand below.
35108 double xa = fabs (x), xa2, x2;
35109 if (!isless (xa, TWO52))
35111 Using the absolute value and copying back sign makes
35112 -0.0 -> -0.0 correct.
35113 xa2 = xa + TWO52 - TWO52;
35118 else if (dxa > 0.5)
35120 x2 = copysign (xa2, x);
35123 enum machine_mode mode = GET_MODE (operand0);
35124 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
35126 TWO52 = ix86_gen_TWO52 (mode);
35128 /* Temporary for holding the result, initialized to the input
35129 operand to ease control flow. */
35130 res = gen_reg_rtx (mode);
35131 emit_move_insn (res, operand1);
35133 /* xa = abs (operand1) */
35134 xa = ix86_expand_sse_fabs (res, &mask);
35136 /* if (!isless (xa, TWO52)) goto label; */
35137 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35139 /* xa2 = xa + TWO52 - TWO52; */
35140 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
35141 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
35143 /* dxa = xa2 - xa; */
35144 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
35146 /* generate 0.5, 1.0 and -0.5 */
35147 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
35148 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
35149 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
35153 tmp = gen_reg_rtx (mode);
35154 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
35155 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
35156 emit_insn (gen_rtx_SET (VOIDmode, tmp,
35157 gen_rtx_AND (mode, one, tmp)));
35158 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
35159 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
35160 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
35161 emit_insn (gen_rtx_SET (VOIDmode, tmp,
35162 gen_rtx_AND (mode, one, tmp)));
35163 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
35165 /* res = copysign (xa2, operand1) */
35166 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
35168 emit_label (label);
35169 LABEL_NUSES (label) = 1;
35171 emit_move_insn (operand0, res);
35174 /* Expand SSE sequence for computing trunc from OPERAND1 storing
35177 ix86_expand_trunc (rtx operand0, rtx operand1)
35179 /* C code for SSE variant we expand below.
35180 double xa = fabs (x), x2;
35181 if (!isless (xa, TWO52))
35183 x2 = (double)(long)x;
35184 if (HONOR_SIGNED_ZEROS (mode))
35185 return copysign (x2, x);
35188 enum machine_mode mode = GET_MODE (operand0);
35189 rtx xa, xi, TWO52, label, res, mask;
35191 TWO52 = ix86_gen_TWO52 (mode);
35193 /* Temporary for holding the result, initialized to the input
35194 operand to ease control flow. */
35195 res = gen_reg_rtx (mode);
35196 emit_move_insn (res, operand1);
35198 /* xa = abs (operand1) */
35199 xa = ix86_expand_sse_fabs (res, &mask);
35201 /* if (!isless (xa, TWO52)) goto label; */
35202 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35204 /* x = (double)(long)x */
35205 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
35206 expand_fix (xi, res, 0);
35207 expand_float (res, xi, 0);
35209 if (HONOR_SIGNED_ZEROS (mode))
35210 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
35212 emit_label (label);
35213 LABEL_NUSES (label) = 1;
35215 emit_move_insn (operand0, res);
35218 /* Expand SSE sequence for computing trunc from OPERAND1 storing
35221 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
35223 enum machine_mode mode = GET_MODE (operand0);
35224 rtx xa, mask, TWO52, label, one, res, smask, tmp;
35226 /* C code for SSE variant we expand below.
35227 double xa = fabs (x), x2;
35228 if (!isless (xa, TWO52))
35230 xa2 = xa + TWO52 - TWO52;
35234 x2 = copysign (xa2, x);
35238 TWO52 = ix86_gen_TWO52 (mode);
35240 /* Temporary for holding the result, initialized to the input
35241 operand to ease control flow. */
35242 res = gen_reg_rtx (mode);
35243 emit_move_insn (res, operand1);
35245 /* xa = abs (operand1) */
35246 xa = ix86_expand_sse_fabs (res, &smask);
35248 /* if (!isless (xa, TWO52)) goto label; */
35249 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35251 /* res = xa + TWO52 - TWO52; */
35252 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
35253 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
35254 emit_move_insn (res, tmp);
35257 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
35259 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
35260 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
35261 emit_insn (gen_rtx_SET (VOIDmode, mask,
35262 gen_rtx_AND (mode, mask, one)));
35263 tmp = expand_simple_binop (mode, MINUS,
35264 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
35265 emit_move_insn (res, tmp);
35267 /* res = copysign (res, operand1) */
35268 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
35270 emit_label (label);
35271 LABEL_NUSES (label) = 1;
35273 emit_move_insn (operand0, res);
35276 /* Expand SSE sequence for computing round from OPERAND1 storing
35279 ix86_expand_round (rtx operand0, rtx operand1)
35281 /* C code for the stuff we're doing below:
35282 double xa = fabs (x);
35283 if (!isless (xa, TWO52))
35285 xa = (double)(long)(xa + nextafter (0.5, 0.0));
35286 return copysign (xa, x);
35288 enum machine_mode mode = GET_MODE (operand0);
35289 rtx res, TWO52, xa, label, xi, half, mask;
35290 const struct real_format *fmt;
35291 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
35293 /* Temporary for holding the result, initialized to the input
35294 operand to ease control flow. */
35295 res = gen_reg_rtx (mode);
35296 emit_move_insn (res, operand1);
35298 TWO52 = ix86_gen_TWO52 (mode);
35299 xa = ix86_expand_sse_fabs (res, &mask);
35300 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
35302 /* load nextafter (0.5, 0.0) */
35303 fmt = REAL_MODE_FORMAT (mode);
35304 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
35305 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
35307 /* xa = xa + 0.5 */
35308 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
35309 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
35311 /* xa = (double)(int64_t)xa */
35312 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
35313 expand_fix (xi, xa, 0);
35314 expand_float (xa, xi, 0);
35316 /* res = copysign (xa, operand1) */
35317 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
35319 emit_label (label);
35320 LABEL_NUSES (label) = 1;
35322 emit_move_insn (operand0, res);
35325 /* Expand SSE sequence for computing round
35326 from OP1 storing into OP0 using sse4 round insn. */
35328 ix86_expand_round_sse4 (rtx op0, rtx op1)
35330 enum machine_mode mode = GET_MODE (op0);
35331 rtx e1, e2, res, half;
35332 const struct real_format *fmt;
35333 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
35334 rtx (*gen_copysign) (rtx, rtx, rtx);
35335 rtx (*gen_round) (rtx, rtx, rtx);
35340 gen_copysign = gen_copysignsf3;
35341 gen_round = gen_sse4_1_roundsf2;
35344 gen_copysign = gen_copysigndf3;
35345 gen_round = gen_sse4_1_rounddf2;
35348 gcc_unreachable ();
35351 /* round (a) = trunc (a + copysign (0.5, a)) */
35353 /* load nextafter (0.5, 0.0) */
35354 fmt = REAL_MODE_FORMAT (mode);
35355 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
35356 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
35357 half = const_double_from_real_value (pred_half, mode);
35359 /* e1 = copysign (0.5, op1) */
35360 e1 = gen_reg_rtx (mode);
35361 emit_insn (gen_copysign (e1, half, op1));
35363 /* e2 = op1 + e1 */
35364 e2 = expand_simple_binop (mode, PLUS, op1, e1, NULL_RTX, 0, OPTAB_DIRECT);
35366 /* res = trunc (e2) */
35367 res = gen_reg_rtx (mode);
35368 emit_insn (gen_round (res, e2, GEN_INT (ROUND_TRUNC)));
35370 emit_move_insn (op0, res);
35374 /* Table of valid machine attributes. */
35375 static const struct attribute_spec ix86_attribute_table[] =
35377 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
35378 affects_type_identity } */
35379 /* Stdcall attribute says callee is responsible for popping arguments
35380 if they are not variable. */
35381 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute,
35383 /* Fastcall attribute says callee is responsible for popping arguments
35384 if they are not variable. */
35385 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute,
35387 /* Thiscall attribute says callee is responsible for popping arguments
35388 if they are not variable. */
35389 { "thiscall", 0, 0, false, true, true, ix86_handle_cconv_attribute,
35391 /* Cdecl attribute says the callee is a normal C declaration */
35392 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute,
35394 /* Regparm attribute specifies how many integer arguments are to be
35395 passed in registers. */
35396 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute,
35398 /* Sseregparm attribute says we are using x86_64 calling conventions
35399 for FP arguments. */
35400 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute,
35402 /* The transactional memory builtins are implicitly regparm or fastcall
35403 depending on the ABI. Override the generic do-nothing attribute that
35404 these builtins were declared with. */
35405 { "*tm regparm", 0, 0, false, true, true, ix86_handle_tm_regparm_attribute,
35407 /* force_align_arg_pointer says this function realigns the stack at entry. */
35408 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
35409 false, true, true, ix86_handle_cconv_attribute, false },
35410 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
35411 { "dllimport", 0, 0, false, false, false, handle_dll_attribute, false },
35412 { "dllexport", 0, 0, false, false, false, handle_dll_attribute, false },
35413 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute,
35416 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute,
35418 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute,
35420 #ifdef SUBTARGET_ATTRIBUTE_TABLE
35421 SUBTARGET_ATTRIBUTE_TABLE,
35423 /* ms_abi and sysv_abi calling convention function attributes. */
35424 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute, true },
35425 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute, true },
35426 { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute,
35428 { "callee_pop_aggregate_return", 1, 1, false, true, true,
35429 ix86_handle_callee_pop_aggregate_return, true },
35431 { NULL, 0, 0, false, false, false, NULL, false }
35434 /* Implement targetm.vectorize.builtin_vectorization_cost. */
35436 ix86_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
35437 tree vectype ATTRIBUTE_UNUSED,
35438 int misalign ATTRIBUTE_UNUSED)
35440 switch (type_of_cost)
35443 return ix86_cost->scalar_stmt_cost;
35446 return ix86_cost->scalar_load_cost;
35449 return ix86_cost->scalar_store_cost;
35452 return ix86_cost->vec_stmt_cost;
35455 return ix86_cost->vec_align_load_cost;
35458 return ix86_cost->vec_store_cost;
35460 case vec_to_scalar:
35461 return ix86_cost->vec_to_scalar_cost;
35463 case scalar_to_vec:
35464 return ix86_cost->scalar_to_vec_cost;
35466 case unaligned_load:
35467 case unaligned_store:
35468 return ix86_cost->vec_unalign_load_cost;
35470 case cond_branch_taken:
35471 return ix86_cost->cond_taken_branch_cost;
35473 case cond_branch_not_taken:
35474 return ix86_cost->cond_not_taken_branch_cost;
35477 case vec_promote_demote:
35478 return ix86_cost->vec_stmt_cost;
35481 gcc_unreachable ();
35485 /* Construct (set target (vec_select op0 (parallel perm))) and
35486 return true if that's a valid instruction in the active ISA. */
35489 expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt)
35491 rtx rperm[MAX_VECT_LEN], x;
35494 for (i = 0; i < nelt; ++i)
35495 rperm[i] = GEN_INT (perm[i]);
35497 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
35498 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
35499 x = gen_rtx_SET (VOIDmode, target, x);
35502 if (recog_memoized (x) < 0)
35510 /* Similar, but generate a vec_concat from op0 and op1 as well. */
35513 expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
35514 const unsigned char *perm, unsigned nelt)
35516 enum machine_mode v2mode;
35519 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
35520 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
35521 return expand_vselect (target, x, perm, nelt);
35524 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
35525 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
35528 expand_vec_perm_blend (struct expand_vec_perm_d *d)
35530 enum machine_mode vmode = d->vmode;
35531 unsigned i, mask, nelt = d->nelt;
35532 rtx target, op0, op1, x;
35533 rtx rperm[32], vperm;
35535 if (d->op0 == d->op1)
35537 if (TARGET_AVX2 && GET_MODE_SIZE (vmode) == 32)
35539 else if (TARGET_AVX && (vmode == V4DFmode || vmode == V8SFmode))
35541 else if (TARGET_SSE4_1 && GET_MODE_SIZE (vmode) == 16)
35546 /* This is a blend, not a permute. Elements must stay in their
35547 respective lanes. */
35548 for (i = 0; i < nelt; ++i)
35550 unsigned e = d->perm[i];
35551 if (!(e == i || e == i + nelt))
35558 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
35559 decision should be extracted elsewhere, so that we only try that
35560 sequence once all budget==3 options have been tried. */
35561 target = d->target;
35574 for (i = 0; i < nelt; ++i)
35575 mask |= (d->perm[i] >= nelt) << i;
35579 for (i = 0; i < 2; ++i)
35580 mask |= (d->perm[i] >= 2 ? 15 : 0) << (i * 4);
35585 for (i = 0; i < 4; ++i)
35586 mask |= (d->perm[i] >= 4 ? 3 : 0) << (i * 2);
35591 /* See if bytes move in pairs so we can use pblendw with
35592 an immediate argument, rather than pblendvb with a vector
35594 for (i = 0; i < 16; i += 2)
35595 if (d->perm[i] + 1 != d->perm[i + 1])
35598 for (i = 0; i < nelt; ++i)
35599 rperm[i] = (d->perm[i] < nelt ? const0_rtx : constm1_rtx);
35602 vperm = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (nelt, rperm));
35603 vperm = force_reg (vmode, vperm);
35605 if (GET_MODE_SIZE (vmode) == 16)
35606 emit_insn (gen_sse4_1_pblendvb (target, op0, op1, vperm));
35608 emit_insn (gen_avx2_pblendvb (target, op0, op1, vperm));
35612 for (i = 0; i < 8; ++i)
35613 mask |= (d->perm[i * 2] >= 16) << i;
35618 target = gen_lowpart (vmode, target);
35619 op0 = gen_lowpart (vmode, op0);
35620 op1 = gen_lowpart (vmode, op1);
35624 /* See if bytes move in pairs. If not, vpblendvb must be used. */
35625 for (i = 0; i < 32; i += 2)
35626 if (d->perm[i] + 1 != d->perm[i + 1])
35628 /* See if bytes move in quadruplets. If yes, vpblendd
35629 with immediate can be used. */
35630 for (i = 0; i < 32; i += 4)
35631 if (d->perm[i] + 2 != d->perm[i + 2])
35635 /* See if bytes move the same in both lanes. If yes,
35636 vpblendw with immediate can be used. */
35637 for (i = 0; i < 16; i += 2)
35638 if (d->perm[i] + 16 != d->perm[i + 16])
35641 /* Use vpblendw. */
35642 for (i = 0; i < 16; ++i)
35643 mask |= (d->perm[i * 2] >= 32) << i;
35648 /* Use vpblendd. */
35649 for (i = 0; i < 8; ++i)
35650 mask |= (d->perm[i * 4] >= 32) << i;
35655 /* See if words move in pairs. If yes, vpblendd can be used. */
35656 for (i = 0; i < 16; i += 2)
35657 if (d->perm[i] + 1 != d->perm[i + 1])
35661 /* See if words move the same in both lanes. If not,
35662 vpblendvb must be used. */
35663 for (i = 0; i < 8; i++)
35664 if (d->perm[i] + 8 != d->perm[i + 8])
35666 /* Use vpblendvb. */
35667 for (i = 0; i < 32; ++i)
35668 rperm[i] = (d->perm[i / 2] < 16 ? const0_rtx : constm1_rtx);
35672 target = gen_lowpart (vmode, target);
35673 op0 = gen_lowpart (vmode, op0);
35674 op1 = gen_lowpart (vmode, op1);
35675 goto finish_pblendvb;
35678 /* Use vpblendw. */
35679 for (i = 0; i < 16; ++i)
35680 mask |= (d->perm[i] >= 16) << i;
35684 /* Use vpblendd. */
35685 for (i = 0; i < 8; ++i)
35686 mask |= (d->perm[i * 2] >= 16) << i;
35691 /* Use vpblendd. */
35692 for (i = 0; i < 4; ++i)
35693 mask |= (d->perm[i] >= 4 ? 3 : 0) << (i * 2);
35698 gcc_unreachable ();
35701 /* This matches five different patterns with the different modes. */
35702 x = gen_rtx_VEC_MERGE (vmode, op1, op0, GEN_INT (mask));
35703 x = gen_rtx_SET (VOIDmode, target, x);
35709 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
35710 in terms of the variable form of vpermilps.
35712 Note that we will have already failed the immediate input vpermilps,
35713 which requires that the high and low part shuffle be identical; the
35714 variable form doesn't require that. */
35717 expand_vec_perm_vpermil (struct expand_vec_perm_d *d)
35719 rtx rperm[8], vperm;
35722 if (!TARGET_AVX || d->vmode != V8SFmode || d->op0 != d->op1)
35725 /* We can only permute within the 128-bit lane. */
35726 for (i = 0; i < 8; ++i)
35728 unsigned e = d->perm[i];
35729 if (i < 4 ? e >= 4 : e < 4)
35736 for (i = 0; i < 8; ++i)
35738 unsigned e = d->perm[i];
35740 /* Within each 128-bit lane, the elements of op0 are numbered
35741 from 0 and the elements of op1 are numbered from 4. */
35747 rperm[i] = GEN_INT (e);
35750 vperm = gen_rtx_CONST_VECTOR (V8SImode, gen_rtvec_v (8, rperm));
35751 vperm = force_reg (V8SImode, vperm);
35752 emit_insn (gen_avx_vpermilvarv8sf3 (d->target, d->op0, vperm));
35757 /* Return true if permutation D can be performed as VMODE permutation
35761 valid_perm_using_mode_p (enum machine_mode vmode, struct expand_vec_perm_d *d)
35763 unsigned int i, j, chunk;
35765 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT
35766 || GET_MODE_CLASS (d->vmode) != MODE_VECTOR_INT
35767 || GET_MODE_SIZE (vmode) != GET_MODE_SIZE (d->vmode))
35770 if (GET_MODE_NUNITS (vmode) >= d->nelt)
35773 chunk = d->nelt / GET_MODE_NUNITS (vmode);
35774 for (i = 0; i < d->nelt; i += chunk)
35775 if (d->perm[i] & (chunk - 1))
35778 for (j = 1; j < chunk; ++j)
35779 if (d->perm[i] + j != d->perm[i + j])
35785 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
35786 in terms of pshufb, vpperm, vpermq, vpermd or vperm2i128. */
35789 expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
35791 unsigned i, nelt, eltsz, mask;
35792 unsigned char perm[32];
35793 enum machine_mode vmode = V16QImode;
35794 rtx rperm[32], vperm, target, op0, op1;
35798 if (d->op0 != d->op1)
35800 if (!TARGET_XOP || GET_MODE_SIZE (d->vmode) != 16)
35803 && valid_perm_using_mode_p (V2TImode, d))
35808 /* Use vperm2i128 insn. The pattern uses
35809 V4DImode instead of V2TImode. */
35810 target = gen_lowpart (V4DImode, d->target);
35811 op0 = gen_lowpart (V4DImode, d->op0);
35812 op1 = gen_lowpart (V4DImode, d->op1);
35814 = GEN_INT (((d->perm[0] & (nelt / 2)) ? 1 : 0)
35815 || ((d->perm[nelt / 2] & (nelt / 2)) ? 2 : 0));
35816 emit_insn (gen_avx2_permv2ti (target, op0, op1, rperm[0]));
35824 if (GET_MODE_SIZE (d->vmode) == 16)
35829 else if (GET_MODE_SIZE (d->vmode) == 32)
35834 /* V4DImode should be already handled through
35835 expand_vselect by vpermq instruction. */
35836 gcc_assert (d->vmode != V4DImode);
35839 if (d->vmode == V8SImode
35840 || d->vmode == V16HImode
35841 || d->vmode == V32QImode)
35843 /* First see if vpermq can be used for
35844 V8SImode/V16HImode/V32QImode. */
35845 if (valid_perm_using_mode_p (V4DImode, d))
35847 for (i = 0; i < 4; i++)
35848 perm[i] = (d->perm[i * nelt / 4] * 4 / nelt) & 3;
35851 return expand_vselect (gen_lowpart (V4DImode, d->target),
35852 gen_lowpart (V4DImode, d->op0),
35856 /* Next see if vpermd can be used. */
35857 if (valid_perm_using_mode_p (V8SImode, d))
35861 if (vmode == V32QImode)
35863 /* vpshufb only works intra lanes, it is not
35864 possible to shuffle bytes in between the lanes. */
35865 for (i = 0; i < nelt; ++i)
35866 if ((d->perm[i] ^ i) & (nelt / 2))
35877 if (vmode == V8SImode)
35878 for (i = 0; i < 8; ++i)
35879 rperm[i] = GEN_INT ((d->perm[i * nelt / 8] * 8 / nelt) & 7);
35882 eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
35883 if (d->op0 != d->op1)
35884 mask = 2 * nelt - 1;
35885 else if (vmode == V16QImode)
35888 mask = nelt / 2 - 1;
35890 for (i = 0; i < nelt; ++i)
35892 unsigned j, e = d->perm[i] & mask;
35893 for (j = 0; j < eltsz; ++j)
35894 rperm[i * eltsz + j] = GEN_INT (e * eltsz + j);
35898 vperm = gen_rtx_CONST_VECTOR (vmode,
35899 gen_rtvec_v (GET_MODE_NUNITS (vmode), rperm));
35900 vperm = force_reg (vmode, vperm);
35902 target = gen_lowpart (vmode, d->target);
35903 op0 = gen_lowpart (vmode, d->op0);
35904 if (d->op0 == d->op1)
35906 if (vmode == V16QImode)
35907 emit_insn (gen_ssse3_pshufbv16qi3 (target, op0, vperm));
35908 else if (vmode == V32QImode)
35909 emit_insn (gen_avx2_pshufbv32qi3 (target, op0, vperm));
35911 emit_insn (gen_avx2_permvarv8si (target, op0, vperm));
35915 op1 = gen_lowpart (vmode, d->op1);
35916 emit_insn (gen_xop_pperm (target, op0, op1, vperm));
35922 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
35923 in a single instruction. */
35926 expand_vec_perm_1 (struct expand_vec_perm_d *d)
35928 unsigned i, nelt = d->nelt;
35929 unsigned char perm2[MAX_VECT_LEN];
35931 /* Check plain VEC_SELECT first, because AVX has instructions that could
35932 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
35933 input where SEL+CONCAT may not. */
35934 if (d->op0 == d->op1)
35936 int mask = nelt - 1;
35937 bool identity_perm = true;
35938 bool broadcast_perm = true;
35940 for (i = 0; i < nelt; i++)
35942 perm2[i] = d->perm[i] & mask;
35944 identity_perm = false;
35946 broadcast_perm = false;
35952 emit_move_insn (d->target, d->op0);
35955 else if (broadcast_perm && TARGET_AVX2)
35957 /* Use vpbroadcast{b,w,d}. */
35958 rtx op = d->op0, (*gen) (rtx, rtx) = NULL;
35962 op = gen_lowpart (V16QImode, op);
35963 gen = gen_avx2_pbroadcastv32qi;
35966 op = gen_lowpart (V8HImode, op);
35967 gen = gen_avx2_pbroadcastv16hi;
35970 op = gen_lowpart (V4SImode, op);
35971 gen = gen_avx2_pbroadcastv8si;
35974 gen = gen_avx2_pbroadcastv16qi;
35977 gen = gen_avx2_pbroadcastv8hi;
35979 /* For other modes prefer other shuffles this function creates. */
35985 emit_insn (gen (d->target, op));
35990 if (expand_vselect (d->target, d->op0, perm2, nelt))
35993 /* There are plenty of patterns in sse.md that are written for
35994 SEL+CONCAT and are not replicated for a single op. Perhaps
35995 that should be changed, to avoid the nastiness here. */
35997 /* Recognize interleave style patterns, which means incrementing
35998 every other permutation operand. */
35999 for (i = 0; i < nelt; i += 2)
36001 perm2[i] = d->perm[i] & mask;
36002 perm2[i + 1] = (d->perm[i + 1] & mask) + nelt;
36004 if (expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, nelt))
36007 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
36010 for (i = 0; i < nelt; i += 4)
36012 perm2[i + 0] = d->perm[i + 0] & mask;
36013 perm2[i + 1] = d->perm[i + 1] & mask;
36014 perm2[i + 2] = (d->perm[i + 2] & mask) + nelt;
36015 perm2[i + 3] = (d->perm[i + 3] & mask) + nelt;
36018 if (expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, nelt))
36023 /* Finally, try the fully general two operand permute. */
36024 if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt))
36027 /* Recognize interleave style patterns with reversed operands. */
36028 if (d->op0 != d->op1)
36030 for (i = 0; i < nelt; ++i)
36032 unsigned e = d->perm[i];
36040 if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
36044 /* Try the SSE4.1 blend variable merge instructions. */
36045 if (expand_vec_perm_blend (d))
36048 /* Try one of the AVX vpermil variable permutations. */
36049 if (expand_vec_perm_vpermil (d))
36052 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
36053 vpshufb, vpermd or vpermq variable permutation. */
36054 if (expand_vec_perm_pshufb (d))
36060 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
36061 in terms of a pair of pshuflw + pshufhw instructions. */
36064 expand_vec_perm_pshuflw_pshufhw (struct expand_vec_perm_d *d)
36066 unsigned char perm2[MAX_VECT_LEN];
36070 if (d->vmode != V8HImode || d->op0 != d->op1)
36073 /* The two permutations only operate in 64-bit lanes. */
36074 for (i = 0; i < 4; ++i)
36075 if (d->perm[i] >= 4)
36077 for (i = 4; i < 8; ++i)
36078 if (d->perm[i] < 4)
36084 /* Emit the pshuflw. */
36085 memcpy (perm2, d->perm, 4);
36086 for (i = 4; i < 8; ++i)
36088 ok = expand_vselect (d->target, d->op0, perm2, 8);
36091 /* Emit the pshufhw. */
36092 memcpy (perm2 + 4, d->perm + 4, 4);
36093 for (i = 0; i < 4; ++i)
36095 ok = expand_vselect (d->target, d->target, perm2, 8);
36101 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
36102 the permutation using the SSSE3 palignr instruction. This succeeds
36103 when all of the elements in PERM fit within one vector and we merely
36104 need to shift them down so that a single vector permutation has a
36105 chance to succeed. */
36108 expand_vec_perm_palignr (struct expand_vec_perm_d *d)
36110 unsigned i, nelt = d->nelt;
36115 /* Even with AVX, palignr only operates on 128-bit vectors. */
36116 if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16)
36119 min = nelt, max = 0;
36120 for (i = 0; i < nelt; ++i)
36122 unsigned e = d->perm[i];
36128 if (min == 0 || max - min >= nelt)
36131 /* Given that we have SSSE3, we know we'll be able to implement the
36132 single operand permutation after the palignr with pshufb. */
36136 shift = GEN_INT (min * GET_MODE_BITSIZE (GET_MODE_INNER (d->vmode)));
36137 emit_insn (gen_ssse3_palignrti (gen_lowpart (TImode, d->target),
36138 gen_lowpart (TImode, d->op1),
36139 gen_lowpart (TImode, d->op0), shift));
36141 d->op0 = d->op1 = d->target;
36144 for (i = 0; i < nelt; ++i)
36146 unsigned e = d->perm[i] - min;
36152 /* Test for the degenerate case where the alignment by itself
36153 produces the desired permutation. */
36157 ok = expand_vec_perm_1 (d);
36163 static bool expand_vec_perm_interleave3 (struct expand_vec_perm_d *d);
36165 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
36166 a two vector permutation into a single vector permutation by using
36167 an interleave operation to merge the vectors. */
36170 expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
36172 struct expand_vec_perm_d dremap, dfinal;
36173 unsigned i, nelt = d->nelt, nelt2 = nelt / 2;
36174 unsigned HOST_WIDE_INT contents;
36175 unsigned char remap[2 * MAX_VECT_LEN];
36177 bool ok, same_halves = false;
36179 if (GET_MODE_SIZE (d->vmode) == 16)
36181 if (d->op0 == d->op1)
36184 else if (GET_MODE_SIZE (d->vmode) == 32)
36188 /* For 32-byte modes allow even d->op0 == d->op1.
36189 The lack of cross-lane shuffling in some instructions
36190 might prevent a single insn shuffle. */
36192 dfinal.testing_p = true;
36193 /* If expand_vec_perm_interleave3 can expand this into
36194 a 3 insn sequence, give up and let it be expanded as
36195 3 insn sequence. While that is one insn longer,
36196 it doesn't need a memory operand and in the common
36197 case that both interleave low and high permutations
36198 with the same operands are adjacent needs 4 insns
36199 for both after CSE. */
36200 if (expand_vec_perm_interleave3 (&dfinal))
36206 /* Examine from whence the elements come. */
36208 for (i = 0; i < nelt; ++i)
36209 contents |= ((unsigned HOST_WIDE_INT) 1) << d->perm[i];
36211 memset (remap, 0xff, sizeof (remap));
36214 if (GET_MODE_SIZE (d->vmode) == 16)
36216 unsigned HOST_WIDE_INT h1, h2, h3, h4;
36218 /* Split the two input vectors into 4 halves. */
36219 h1 = (((unsigned HOST_WIDE_INT) 1) << nelt2) - 1;
36224 /* If the elements from the low halves use interleave low, and similarly
36225 for interleave high. If the elements are from mis-matched halves, we
36226 can use shufps for V4SF/V4SI or do a DImode shuffle. */
36227 if ((contents & (h1 | h3)) == contents)
36230 for (i = 0; i < nelt2; ++i)
36233 remap[i + nelt] = i * 2 + 1;
36234 dremap.perm[i * 2] = i;
36235 dremap.perm[i * 2 + 1] = i + nelt;
36237 if (!TARGET_SSE2 && d->vmode == V4SImode)
36238 dremap.vmode = V4SFmode;
36240 else if ((contents & (h2 | h4)) == contents)
36243 for (i = 0; i < nelt2; ++i)
36245 remap[i + nelt2] = i * 2;
36246 remap[i + nelt + nelt2] = i * 2 + 1;
36247 dremap.perm[i * 2] = i + nelt2;
36248 dremap.perm[i * 2 + 1] = i + nelt + nelt2;
36250 if (!TARGET_SSE2 && d->vmode == V4SImode)
36251 dremap.vmode = V4SFmode;
36253 else if ((contents & (h1 | h4)) == contents)
36256 for (i = 0; i < nelt2; ++i)
36259 remap[i + nelt + nelt2] = i + nelt2;
36260 dremap.perm[i] = i;
36261 dremap.perm[i + nelt2] = i + nelt + nelt2;
36266 dremap.vmode = V2DImode;
36268 dremap.perm[0] = 0;
36269 dremap.perm[1] = 3;
36272 else if ((contents & (h2 | h3)) == contents)
36275 for (i = 0; i < nelt2; ++i)
36277 remap[i + nelt2] = i;
36278 remap[i + nelt] = i + nelt2;
36279 dremap.perm[i] = i + nelt2;
36280 dremap.perm[i + nelt2] = i + nelt;
36285 dremap.vmode = V2DImode;
36287 dremap.perm[0] = 1;
36288 dremap.perm[1] = 2;
36296 unsigned int nelt4 = nelt / 4, nzcnt = 0;
36297 unsigned HOST_WIDE_INT q[8];
36298 unsigned int nonzero_halves[4];
36300 /* Split the two input vectors into 8 quarters. */
36301 q[0] = (((unsigned HOST_WIDE_INT) 1) << nelt4) - 1;
36302 for (i = 1; i < 8; ++i)
36303 q[i] = q[0] << (nelt4 * i);
36304 for (i = 0; i < 4; ++i)
36305 if (((q[2 * i] | q[2 * i + 1]) & contents) != 0)
36307 nonzero_halves[nzcnt] = i;
36313 gcc_assert (d->op0 == d->op1);
36314 nonzero_halves[1] = nonzero_halves[0];
36315 same_halves = true;
36317 else if (d->op0 == d->op1)
36319 gcc_assert (nonzero_halves[0] == 0);
36320 gcc_assert (nonzero_halves[1] == 1);
36325 if (d->perm[0] / nelt2 == nonzero_halves[1])
36327 /* Attempt to increase the likelyhood that dfinal
36328 shuffle will be intra-lane. */
36329 char tmph = nonzero_halves[0];
36330 nonzero_halves[0] = nonzero_halves[1];
36331 nonzero_halves[1] = tmph;
36334 /* vperm2f128 or vperm2i128. */
36335 for (i = 0; i < nelt2; ++i)
36337 remap[i + nonzero_halves[1] * nelt2] = i + nelt2;
36338 remap[i + nonzero_halves[0] * nelt2] = i;
36339 dremap.perm[i + nelt2] = i + nonzero_halves[1] * nelt2;
36340 dremap.perm[i] = i + nonzero_halves[0] * nelt2;
36343 if (d->vmode != V8SFmode
36344 && d->vmode != V4DFmode
36345 && d->vmode != V8SImode)
36347 dremap.vmode = V8SImode;
36349 for (i = 0; i < 4; ++i)
36351 dremap.perm[i] = i + nonzero_halves[0] * 4;
36352 dremap.perm[i + 4] = i + nonzero_halves[1] * 4;
36356 else if (d->op0 == d->op1)
36358 else if (TARGET_AVX2
36359 && (contents & (q[0] | q[2] | q[4] | q[6])) == contents)
36362 for (i = 0; i < nelt4; ++i)
36365 remap[i + nelt] = i * 2 + 1;
36366 remap[i + nelt2] = i * 2 + nelt2;
36367 remap[i + nelt + nelt2] = i * 2 + nelt2 + 1;
36368 dremap.perm[i * 2] = i;
36369 dremap.perm[i * 2 + 1] = i + nelt;
36370 dremap.perm[i * 2 + nelt2] = i + nelt2;
36371 dremap.perm[i * 2 + nelt2 + 1] = i + nelt + nelt2;
36374 else if (TARGET_AVX2
36375 && (contents & (q[1] | q[3] | q[5] | q[7])) == contents)
36378 for (i = 0; i < nelt4; ++i)
36380 remap[i + nelt4] = i * 2;
36381 remap[i + nelt + nelt4] = i * 2 + 1;
36382 remap[i + nelt2 + nelt4] = i * 2 + nelt2;
36383 remap[i + nelt + nelt2 + nelt4] = i * 2 + nelt2 + 1;
36384 dremap.perm[i * 2] = i + nelt4;
36385 dremap.perm[i * 2 + 1] = i + nelt + nelt4;
36386 dremap.perm[i * 2 + nelt2] = i + nelt2 + nelt4;
36387 dremap.perm[i * 2 + nelt2 + 1] = i + nelt + nelt2 + nelt4;
36394 /* Use the remapping array set up above to move the elements from their
36395 swizzled locations into their final destinations. */
36397 for (i = 0; i < nelt; ++i)
36399 unsigned e = remap[d->perm[i]];
36400 gcc_assert (e < nelt);
36401 /* If same_halves is true, both halves of the remapped vector are the
36402 same. Avoid cross-lane accesses if possible. */
36403 if (same_halves && i >= nelt2)
36405 gcc_assert (e < nelt2);
36406 dfinal.perm[i] = e + nelt2;
36409 dfinal.perm[i] = e;
36411 dfinal.op0 = gen_reg_rtx (dfinal.vmode);
36412 dfinal.op1 = dfinal.op0;
36413 dremap.target = dfinal.op0;
36415 /* Test if the final remap can be done with a single insn. For V4SFmode or
36416 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
36418 ok = expand_vec_perm_1 (&dfinal);
36419 seq = get_insns ();
36428 if (dremap.vmode != dfinal.vmode)
36430 dremap.target = gen_lowpart (dremap.vmode, dremap.target);
36431 dremap.op0 = gen_lowpart (dremap.vmode, dremap.op0);
36432 dremap.op1 = gen_lowpart (dremap.vmode, dremap.op1);
36435 ok = expand_vec_perm_1 (&dremap);
36442 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
36443 a single vector cross-lane permutation into vpermq followed
36444 by any of the single insn permutations. */
36447 expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d)
36449 struct expand_vec_perm_d dremap, dfinal;
36450 unsigned i, j, nelt = d->nelt, nelt2 = nelt / 2, nelt4 = nelt / 4;
36451 unsigned contents[2];
36455 && (d->vmode == V32QImode || d->vmode == V16HImode)
36456 && d->op0 == d->op1))
36461 for (i = 0; i < nelt2; ++i)
36463 contents[0] |= 1u << (d->perm[i] / nelt4);
36464 contents[1] |= 1u << (d->perm[i + nelt2] / nelt4);
36467 for (i = 0; i < 2; ++i)
36469 unsigned int cnt = 0;
36470 for (j = 0; j < 4; ++j)
36471 if ((contents[i] & (1u << j)) != 0 && ++cnt > 2)
36479 dremap.vmode = V4DImode;
36481 dremap.target = gen_reg_rtx (V4DImode);
36482 dremap.op0 = gen_lowpart (V4DImode, d->op0);
36483 dremap.op1 = dremap.op0;
36484 for (i = 0; i < 2; ++i)
36486 unsigned int cnt = 0;
36487 for (j = 0; j < 4; ++j)
36488 if ((contents[i] & (1u << j)) != 0)
36489 dremap.perm[2 * i + cnt++] = j;
36490 for (; cnt < 2; ++cnt)
36491 dremap.perm[2 * i + cnt] = 0;
36495 dfinal.op0 = gen_lowpart (dfinal.vmode, dremap.target);
36496 dfinal.op1 = dfinal.op0;
36497 for (i = 0, j = 0; i < nelt; ++i)
36501 dfinal.perm[i] = (d->perm[i] & (nelt4 - 1)) | (j ? nelt2 : 0);
36502 if ((d->perm[i] / nelt4) == dremap.perm[j])
36504 else if ((d->perm[i] / nelt4) == dremap.perm[j + 1])
36505 dfinal.perm[i] |= nelt4;
36507 gcc_unreachable ();
36510 ok = expand_vec_perm_1 (&dremap);
36513 ok = expand_vec_perm_1 (&dfinal);
36519 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
36520 a two vector permutation using 2 intra-lane interleave insns
36521 and cross-lane shuffle for 32-byte vectors. */
36524 expand_vec_perm_interleave3 (struct expand_vec_perm_d *d)
36527 rtx (*gen) (rtx, rtx, rtx);
36529 if (d->op0 == d->op1)
36531 if (TARGET_AVX2 && GET_MODE_SIZE (d->vmode) == 32)
36533 else if (TARGET_AVX && (d->vmode == V8SFmode || d->vmode == V4DFmode))
36539 if (d->perm[0] != 0 && d->perm[0] != nelt / 2)
36541 for (i = 0; i < nelt; i += 2)
36542 if (d->perm[i] != d->perm[0] + i / 2
36543 || d->perm[i + 1] != d->perm[0] + i / 2 + nelt)
36553 gen = gen_vec_interleave_highv32qi;
36555 gen = gen_vec_interleave_lowv32qi;
36559 gen = gen_vec_interleave_highv16hi;
36561 gen = gen_vec_interleave_lowv16hi;
36565 gen = gen_vec_interleave_highv8si;
36567 gen = gen_vec_interleave_lowv8si;
36571 gen = gen_vec_interleave_highv4di;
36573 gen = gen_vec_interleave_lowv4di;
36577 gen = gen_vec_interleave_highv8sf;
36579 gen = gen_vec_interleave_lowv8sf;
36583 gen = gen_vec_interleave_highv4df;
36585 gen = gen_vec_interleave_lowv4df;
36588 gcc_unreachable ();
36591 emit_insn (gen (d->target, d->op0, d->op1));
36595 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
36596 permutation with two pshufb insns and an ior. We should have already
36597 failed all two instruction sequences. */
36600 expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
36602 rtx rperm[2][16], vperm, l, h, op, m128;
36603 unsigned int i, nelt, eltsz;
36605 if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16)
36607 gcc_assert (d->op0 != d->op1);
36610 eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
36612 /* Generate two permutation masks. If the required element is within
36613 the given vector it is shuffled into the proper lane. If the required
36614 element is in the other vector, force a zero into the lane by setting
36615 bit 7 in the permutation mask. */
36616 m128 = GEN_INT (-128);
36617 for (i = 0; i < nelt; ++i)
36619 unsigned j, e = d->perm[i];
36620 unsigned which = (e >= nelt);
36624 for (j = 0; j < eltsz; ++j)
36626 rperm[which][i*eltsz + j] = GEN_INT (e*eltsz + j);
36627 rperm[1-which][i*eltsz + j] = m128;
36631 vperm = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, rperm[0]));
36632 vperm = force_reg (V16QImode, vperm);
36634 l = gen_reg_rtx (V16QImode);
36635 op = gen_lowpart (V16QImode, d->op0);
36636 emit_insn (gen_ssse3_pshufbv16qi3 (l, op, vperm));
36638 vperm = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, rperm[1]));
36639 vperm = force_reg (V16QImode, vperm);
36641 h = gen_reg_rtx (V16QImode);
36642 op = gen_lowpart (V16QImode, d->op1);
36643 emit_insn (gen_ssse3_pshufbv16qi3 (h, op, vperm));
36645 op = gen_lowpart (V16QImode, d->target);
36646 emit_insn (gen_iorv16qi3 (op, l, h));
36651 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
36652 with two vpshufb insns, vpermq and vpor. We should have already failed
36653 all two or three instruction sequences. */
36656 expand_vec_perm_vpshufb2_vpermq (struct expand_vec_perm_d *d)
36658 rtx rperm[2][32], vperm, l, h, hp, op, m128;
36659 unsigned int i, nelt, eltsz;
36662 || d->op0 != d->op1
36663 || (d->vmode != V32QImode && d->vmode != V16HImode))
36670 eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
36672 /* Generate two permutation masks. If the required element is within
36673 the same lane, it is shuffled in. If the required element from the
36674 other lane, force a zero by setting bit 7 in the permutation mask.
36675 In the other mask the mask has non-negative elements if element
36676 is requested from the other lane, but also moved to the other lane,
36677 so that the result of vpshufb can have the two V2TImode halves
36679 m128 = GEN_INT (-128);
36680 for (i = 0; i < nelt; ++i)
36682 unsigned j, e = d->perm[i] & (nelt / 2 - 1);
36683 unsigned which = ((d->perm[i] ^ i) & (nelt / 2)) * eltsz;
36685 for (j = 0; j < eltsz; ++j)
36687 rperm[!!which][(i * eltsz + j) ^ which] = GEN_INT (e * eltsz + j);
36688 rperm[!which][(i * eltsz + j) ^ (which ^ 16)] = m128;
36692 vperm = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, rperm[1]));
36693 vperm = force_reg (V32QImode, vperm);
36695 h = gen_reg_rtx (V32QImode);
36696 op = gen_lowpart (V32QImode, d->op0);
36697 emit_insn (gen_avx2_pshufbv32qi3 (h, op, vperm));
36699 /* Swap the 128-byte lanes of h into hp. */
36700 hp = gen_reg_rtx (V4DImode);
36701 op = gen_lowpart (V4DImode, h);
36702 emit_insn (gen_avx2_permv4di_1 (hp, op, const2_rtx, GEN_INT (3), const0_rtx,
36705 vperm = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, rperm[0]));
36706 vperm = force_reg (V32QImode, vperm);
36708 l = gen_reg_rtx (V32QImode);
36709 op = gen_lowpart (V32QImode, d->op0);
36710 emit_insn (gen_avx2_pshufbv32qi3 (l, op, vperm));
36712 op = gen_lowpart (V32QImode, d->target);
36713 emit_insn (gen_iorv32qi3 (op, l, gen_lowpart (V32QImode, hp)));
36718 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
36719 and extract-odd permutations of two V32QImode and V16QImode operand
36720 with two vpshufb insns, vpor and vpermq. We should have already
36721 failed all two or three instruction sequences. */
36724 expand_vec_perm_vpshufb2_vpermq_even_odd (struct expand_vec_perm_d *d)
36726 rtx rperm[2][32], vperm, l, h, ior, op, m128;
36727 unsigned int i, nelt, eltsz;
36730 || d->op0 == d->op1
36731 || (d->vmode != V32QImode && d->vmode != V16HImode))
36734 for (i = 0; i < d->nelt; ++i)
36735 if ((d->perm[i] ^ (i * 2)) & (3 * d->nelt / 2))
36742 eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
36744 /* Generate two permutation masks. In the first permutation mask
36745 the first quarter will contain indexes for the first half
36746 of the op0, the second quarter will contain bit 7 set, third quarter
36747 will contain indexes for the second half of the op0 and the
36748 last quarter bit 7 set. In the second permutation mask
36749 the first quarter will contain bit 7 set, the second quarter
36750 indexes for the first half of the op1, the third quarter bit 7 set
36751 and last quarter indexes for the second half of the op1.
36752 I.e. the first mask e.g. for V32QImode extract even will be:
36753 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
36754 (all values masked with 0xf except for -128) and second mask
36755 for extract even will be
36756 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
36757 m128 = GEN_INT (-128);
36758 for (i = 0; i < nelt; ++i)
36760 unsigned j, e = d->perm[i] & (nelt / 2 - 1);
36761 unsigned which = d->perm[i] >= nelt;
36762 unsigned xorv = (i >= nelt / 4 && i < 3 * nelt / 4) ? 24 : 0;
36764 for (j = 0; j < eltsz; ++j)
36766 rperm[which][(i * eltsz + j) ^ xorv] = GEN_INT (e * eltsz + j);
36767 rperm[1 - which][(i * eltsz + j) ^ xorv] = m128;
36771 vperm = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, rperm[0]));
36772 vperm = force_reg (V32QImode, vperm);
36774 l = gen_reg_rtx (V32QImode);
36775 op = gen_lowpart (V32QImode, d->op0);
36776 emit_insn (gen_avx2_pshufbv32qi3 (l, op, vperm));
36778 vperm = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, rperm[1]));
36779 vperm = force_reg (V32QImode, vperm);
36781 h = gen_reg_rtx (V32QImode);
36782 op = gen_lowpart (V32QImode, d->op1);
36783 emit_insn (gen_avx2_pshufbv32qi3 (h, op, vperm));
36785 ior = gen_reg_rtx (V32QImode);
36786 emit_insn (gen_iorv32qi3 (ior, l, h));
36788 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
36789 op = gen_lowpart (V4DImode, d->target);
36790 ior = gen_lowpart (V4DImode, ior);
36791 emit_insn (gen_avx2_permv4di_1 (op, ior, const0_rtx, const2_rtx,
36792 const1_rtx, GEN_INT (3)));
36797 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
36798 and extract-odd permutations. */
36801 expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd)
36808 t1 = gen_reg_rtx (V4DFmode);
36809 t2 = gen_reg_rtx (V4DFmode);
36811 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
36812 emit_insn (gen_avx_vperm2f128v4df3 (t1, d->op0, d->op1, GEN_INT (0x20)));
36813 emit_insn (gen_avx_vperm2f128v4df3 (t2, d->op0, d->op1, GEN_INT (0x31)));
36815 /* Now an unpck[lh]pd will produce the result required. */
36817 t3 = gen_avx_unpckhpd256 (d->target, t1, t2);
36819 t3 = gen_avx_unpcklpd256 (d->target, t1, t2);
36825 int mask = odd ? 0xdd : 0x88;
36827 t1 = gen_reg_rtx (V8SFmode);
36828 t2 = gen_reg_rtx (V8SFmode);
36829 t3 = gen_reg_rtx (V8SFmode);
36831 /* Shuffle within the 128-bit lanes to produce:
36832 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
36833 emit_insn (gen_avx_shufps256 (t1, d->op0, d->op1,
36836 /* Shuffle the lanes around to produce:
36837 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
36838 emit_insn (gen_avx_vperm2f128v8sf3 (t2, t1, t1,
36841 /* Shuffle within the 128-bit lanes to produce:
36842 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
36843 emit_insn (gen_avx_shufps256 (t3, t1, t2, GEN_INT (0x44)));
36845 /* Shuffle within the 128-bit lanes to produce:
36846 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
36847 emit_insn (gen_avx_shufps256 (t2, t1, t2, GEN_INT (0xee)));
36849 /* Shuffle the lanes around to produce:
36850 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
36851 emit_insn (gen_avx_vperm2f128v8sf3 (d->target, t3, t2,
36860 /* These are always directly implementable by expand_vec_perm_1. */
36861 gcc_unreachable ();
36865 return expand_vec_perm_pshufb2 (d);
36868 /* We need 2*log2(N)-1 operations to achieve odd/even
36869 with interleave. */
36870 t1 = gen_reg_rtx (V8HImode);
36871 t2 = gen_reg_rtx (V8HImode);
36872 emit_insn (gen_vec_interleave_highv8hi (t1, d->op0, d->op1));
36873 emit_insn (gen_vec_interleave_lowv8hi (d->target, d->op0, d->op1));
36874 emit_insn (gen_vec_interleave_highv8hi (t2, d->target, t1));
36875 emit_insn (gen_vec_interleave_lowv8hi (d->target, d->target, t1));
36877 t3 = gen_vec_interleave_highv8hi (d->target, d->target, t2);
36879 t3 = gen_vec_interleave_lowv8hi (d->target, d->target, t2);
36886 return expand_vec_perm_pshufb2 (d);
36889 t1 = gen_reg_rtx (V16QImode);
36890 t2 = gen_reg_rtx (V16QImode);
36891 t3 = gen_reg_rtx (V16QImode);
36892 emit_insn (gen_vec_interleave_highv16qi (t1, d->op0, d->op1));
36893 emit_insn (gen_vec_interleave_lowv16qi (d->target, d->op0, d->op1));
36894 emit_insn (gen_vec_interleave_highv16qi (t2, d->target, t1));
36895 emit_insn (gen_vec_interleave_lowv16qi (d->target, d->target, t1));
36896 emit_insn (gen_vec_interleave_highv16qi (t3, d->target, t2));
36897 emit_insn (gen_vec_interleave_lowv16qi (d->target, d->target, t2));
36899 t3 = gen_vec_interleave_highv16qi (d->target, d->target, t3);
36901 t3 = gen_vec_interleave_lowv16qi (d->target, d->target, t3);
36908 return expand_vec_perm_vpshufb2_vpermq_even_odd (d);
36913 struct expand_vec_perm_d d_copy = *d;
36914 d_copy.vmode = V4DFmode;
36915 d_copy.target = gen_lowpart (V4DFmode, d->target);
36916 d_copy.op0 = gen_lowpart (V4DFmode, d->op0);
36917 d_copy.op1 = gen_lowpart (V4DFmode, d->op1);
36918 return expand_vec_perm_even_odd_1 (&d_copy, odd);
36921 t1 = gen_reg_rtx (V4DImode);
36922 t2 = gen_reg_rtx (V4DImode);
36924 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
36925 emit_insn (gen_avx2_permv2ti (t1, d->op0, d->op1, GEN_INT (0x20)));
36926 emit_insn (gen_avx2_permv2ti (t2, d->op0, d->op1, GEN_INT (0x31)));
36928 /* Now an vpunpck[lh]qdq will produce the result required. */
36930 t3 = gen_avx2_interleave_highv4di (d->target, t1, t2);
36932 t3 = gen_avx2_interleave_lowv4di (d->target, t1, t2);
36939 struct expand_vec_perm_d d_copy = *d;
36940 d_copy.vmode = V8SFmode;
36941 d_copy.target = gen_lowpart (V8SFmode, d->target);
36942 d_copy.op0 = gen_lowpart (V8SFmode, d->op0);
36943 d_copy.op1 = gen_lowpart (V8SFmode, d->op1);
36944 return expand_vec_perm_even_odd_1 (&d_copy, odd);
36947 t1 = gen_reg_rtx (V8SImode);
36948 t2 = gen_reg_rtx (V8SImode);
36950 /* Shuffle the lanes around into
36951 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
36952 emit_insn (gen_avx2_permv2ti (gen_lowpart (V4DImode, t1),
36953 gen_lowpart (V4DImode, d->op0),
36954 gen_lowpart (V4DImode, d->op1),
36956 emit_insn (gen_avx2_permv2ti (gen_lowpart (V4DImode, t2),
36957 gen_lowpart (V4DImode, d->op0),
36958 gen_lowpart (V4DImode, d->op1),
36961 /* Swap the 2nd and 3rd position in each lane into
36962 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
36963 emit_insn (gen_avx2_pshufdv3 (t1, t1,
36964 GEN_INT (2 * 4 + 1 * 16 + 3 * 64)));
36965 emit_insn (gen_avx2_pshufdv3 (t2, t2,
36966 GEN_INT (2 * 4 + 1 * 16 + 3 * 64)));
36968 /* Now an vpunpck[lh]qdq will produce
36969 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
36971 t3 = gen_avx2_interleave_highv4di (gen_lowpart (V4DImode, d->target),
36972 gen_lowpart (V4DImode, t1),
36973 gen_lowpart (V4DImode, t2));
36975 t3 = gen_avx2_interleave_lowv4di (gen_lowpart (V4DImode, d->target),
36976 gen_lowpart (V4DImode, t1),
36977 gen_lowpart (V4DImode, t2));
36982 gcc_unreachable ();
36988 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
36989 extract-even and extract-odd permutations. */
36992 expand_vec_perm_even_odd (struct expand_vec_perm_d *d)
36994 unsigned i, odd, nelt = d->nelt;
36997 if (odd != 0 && odd != 1)
37000 for (i = 1; i < nelt; ++i)
37001 if (d->perm[i] != 2 * i + odd)
37004 return expand_vec_perm_even_odd_1 (d, odd);
37007 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
37008 permutations. We assume that expand_vec_perm_1 has already failed. */
37011 expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d)
37013 unsigned elt = d->perm[0], nelt2 = d->nelt / 2;
37014 enum machine_mode vmode = d->vmode;
37015 unsigned char perm2[4];
37023 /* These are special-cased in sse.md so that we can optionally
37024 use the vbroadcast instruction. They expand to two insns
37025 if the input happens to be in a register. */
37026 gcc_unreachable ();
37032 /* These are always implementable using standard shuffle patterns. */
37033 gcc_unreachable ();
37037 /* These can be implemented via interleave. We save one insn by
37038 stopping once we have promoted to V4SImode and then use pshufd. */
37042 rtx (*gen) (rtx, rtx, rtx)
37043 = vmode == V16QImode ? gen_vec_interleave_lowv16qi
37044 : gen_vec_interleave_lowv8hi;
37048 gen = vmode == V16QImode ? gen_vec_interleave_highv16qi
37049 : gen_vec_interleave_highv8hi;
37054 dest = gen_reg_rtx (vmode);
37055 emit_insn (gen (dest, op0, op0));
37056 vmode = get_mode_wider_vector (vmode);
37057 op0 = gen_lowpart (vmode, dest);
37059 while (vmode != V4SImode);
37061 memset (perm2, elt, 4);
37062 ok = expand_vselect (gen_lowpart (V4SImode, d->target), op0, perm2, 4);
37070 /* For AVX2 broadcasts of the first element vpbroadcast* or
37071 vpermq should be used by expand_vec_perm_1. */
37072 gcc_assert (!TARGET_AVX2 || d->perm[0]);
37076 gcc_unreachable ();
37080 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
37081 broadcast permutations. */
37084 expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
37086 unsigned i, elt, nelt = d->nelt;
37088 if (d->op0 != d->op1)
37092 for (i = 1; i < nelt; ++i)
37093 if (d->perm[i] != elt)
37096 return expand_vec_perm_broadcast_1 (d);
37099 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
37100 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
37101 all the shorter instruction sequences. */
37104 expand_vec_perm_vpshufb4_vpermq2 (struct expand_vec_perm_d *d)
37106 rtx rperm[4][32], vperm, l[2], h[2], op, m128;
37107 unsigned int i, nelt, eltsz;
37111 || d->op0 == d->op1
37112 || (d->vmode != V32QImode && d->vmode != V16HImode))
37119 eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
37121 /* Generate 4 permutation masks. If the required element is within
37122 the same lane, it is shuffled in. If the required element from the
37123 other lane, force a zero by setting bit 7 in the permutation mask.
37124 In the other mask the mask has non-negative elements if element
37125 is requested from the other lane, but also moved to the other lane,
37126 so that the result of vpshufb can have the two V2TImode halves
37128 m128 = GEN_INT (-128);
37129 for (i = 0; i < 32; ++i)
37131 rperm[0][i] = m128;
37132 rperm[1][i] = m128;
37133 rperm[2][i] = m128;
37134 rperm[3][i] = m128;
37140 for (i = 0; i < nelt; ++i)
37142 unsigned j, e = d->perm[i] & (nelt / 2 - 1);
37143 unsigned xlane = ((d->perm[i] ^ i) & (nelt / 2)) * eltsz;
37144 unsigned int which = ((d->perm[i] & nelt) ? 2 : 0) + (xlane ? 1 : 0);
37146 for (j = 0; j < eltsz; ++j)
37147 rperm[which][(i * eltsz + j) ^ xlane] = GEN_INT (e * eltsz + j);
37148 used[which] = true;
37151 for (i = 0; i < 2; ++i)
37153 if (!used[2 * i + 1])
37158 vperm = gen_rtx_CONST_VECTOR (V32QImode,
37159 gen_rtvec_v (32, rperm[2 * i + 1]));
37160 vperm = force_reg (V32QImode, vperm);
37161 h[i] = gen_reg_rtx (V32QImode);
37162 op = gen_lowpart (V32QImode, i ? d->op1 : d->op0);
37163 emit_insn (gen_avx2_pshufbv32qi3 (h[i], op, vperm));
37166 /* Swap the 128-byte lanes of h[X]. */
37167 for (i = 0; i < 2; ++i)
37169 if (h[i] == NULL_RTX)
37171 op = gen_reg_rtx (V4DImode);
37172 emit_insn (gen_avx2_permv4di_1 (op, gen_lowpart (V4DImode, h[i]),
37173 const2_rtx, GEN_INT (3), const0_rtx,
37175 h[i] = gen_lowpart (V32QImode, op);
37178 for (i = 0; i < 2; ++i)
37185 vperm = gen_rtx_CONST_VECTOR (V32QImode, gen_rtvec_v (32, rperm[2 * i]));
37186 vperm = force_reg (V32QImode, vperm);
37187 l[i] = gen_reg_rtx (V32QImode);
37188 op = gen_lowpart (V32QImode, i ? d->op1 : d->op0);
37189 emit_insn (gen_avx2_pshufbv32qi3 (l[i], op, vperm));
37192 for (i = 0; i < 2; ++i)
37196 op = gen_reg_rtx (V32QImode);
37197 emit_insn (gen_iorv32qi3 (op, l[i], h[i]));
37204 gcc_assert (l[0] && l[1]);
37205 op = gen_lowpart (V32QImode, d->target);
37206 emit_insn (gen_iorv32qi3 (op, l[0], l[1]));
37210 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
37211 With all of the interface bits taken care of, perform the expansion
37212 in D and return true on success. */
37215 ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
37217 /* Try a single instruction expansion. */
37218 if (expand_vec_perm_1 (d))
37221 /* Try sequences of two instructions. */
37223 if (expand_vec_perm_pshuflw_pshufhw (d))
37226 if (expand_vec_perm_palignr (d))
37229 if (expand_vec_perm_interleave2 (d))
37232 if (expand_vec_perm_broadcast (d))
37235 if (expand_vec_perm_vpermq_perm_1 (d))
37238 /* Try sequences of three instructions. */
37240 if (expand_vec_perm_pshufb2 (d))
37243 if (expand_vec_perm_interleave3 (d))
37246 /* Try sequences of four instructions. */
37248 if (expand_vec_perm_vpshufb2_vpermq (d))
37251 if (expand_vec_perm_vpshufb2_vpermq_even_odd (d))
37254 /* ??? Look for narrow permutations whose element orderings would
37255 allow the promotion to a wider mode. */
37257 /* ??? Look for sequences of interleave or a wider permute that place
37258 the data into the correct lanes for a half-vector shuffle like
37259 pshuf[lh]w or vpermilps. */
37261 /* ??? Look for sequences of interleave that produce the desired results.
37262 The combinatorics of punpck[lh] get pretty ugly... */
37264 if (expand_vec_perm_even_odd (d))
37267 /* Even longer sequences. */
37268 if (expand_vec_perm_vpshufb4_vpermq2 (d))
37275 ix86_expand_vec_perm_const (rtx operands[4])
37277 struct expand_vec_perm_d d;
37278 unsigned char perm[MAX_VECT_LEN];
37279 int i, nelt, which;
37282 d.target = operands[0];
37283 d.op0 = operands[1];
37284 d.op1 = operands[2];
37287 d.vmode = GET_MODE (d.target);
37288 gcc_assert (VECTOR_MODE_P (d.vmode));
37289 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
37290 d.testing_p = false;
37292 gcc_assert (GET_CODE (sel) == CONST_VECTOR);
37293 gcc_assert (XVECLEN (sel, 0) == nelt);
37294 gcc_checking_assert (sizeof (d.perm) == sizeof (perm));
37296 for (i = which = 0; i < nelt; ++i)
37298 rtx e = XVECEXP (sel, 0, i);
37299 int ei = INTVAL (e) & (2 * nelt - 1);
37301 which |= (ei < nelt ? 1 : 2);
37312 if (!rtx_equal_p (d.op0, d.op1))
37315 /* The elements of PERM do not suggest that only the first operand
37316 is used, but both operands are identical. Allow easier matching
37317 of the permutation by folding the permutation into the single
37319 for (i = 0; i < nelt; ++i)
37320 if (d.perm[i] >= nelt)
37329 for (i = 0; i < nelt; ++i)
37335 if (ix86_expand_vec_perm_const_1 (&d))
37338 /* If the mask says both arguments are needed, but they are the same,
37339 the above tried to expand with d.op0 == d.op1. If that didn't work,
37340 retry with d.op0 != d.op1 as that is what testing has been done with. */
37341 if (which == 3 && d.op0 == d.op1)
37346 memcpy (d.perm, perm, sizeof (perm));
37347 d.op1 = gen_reg_rtx (d.vmode);
37349 ok = ix86_expand_vec_perm_const_1 (&d);
37350 seq = get_insns ();
37354 emit_move_insn (d.op1, d.op0);
37363 /* Implement targetm.vectorize.vec_perm_const_ok. */
37366 ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode,
37367 const unsigned char *sel)
37369 struct expand_vec_perm_d d;
37370 unsigned int i, nelt, which;
37374 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
37375 d.testing_p = true;
37377 /* Given sufficient ISA support we can just return true here
37378 for selected vector modes. */
37379 if (GET_MODE_SIZE (d.vmode) == 16)
37381 /* All implementable with a single vpperm insn. */
37384 /* All implementable with 2 pshufb + 1 ior. */
37387 /* All implementable with shufpd or unpck[lh]pd. */
37392 /* Extract the values from the vector CST into the permutation
37394 memcpy (d.perm, sel, nelt);
37395 for (i = which = 0; i < nelt; ++i)
37397 unsigned char e = d.perm[i];
37398 gcc_assert (e < 2 * nelt);
37399 which |= (e < nelt ? 1 : 2);
37402 /* For all elements from second vector, fold the elements to first. */
37404 for (i = 0; i < nelt; ++i)
37407 /* Check whether the mask can be applied to the vector type. */
37408 one_vec = (which != 3);
37410 /* Implementable with shufps or pshufd. */
37411 if (one_vec && (d.vmode == V4SFmode || d.vmode == V4SImode))
37414 /* Otherwise we have to go through the motions and see if we can
37415 figure out how to generate the requested permutation. */
37416 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
37417 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
37419 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
37422 ret = ix86_expand_vec_perm_const_1 (&d);
37429 ix86_expand_vec_extract_even_odd (rtx targ, rtx op0, rtx op1, unsigned odd)
37431 struct expand_vec_perm_d d;
37437 d.vmode = GET_MODE (targ);
37438 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
37439 d.testing_p = false;
37441 for (i = 0; i < nelt; ++i)
37442 d.perm[i] = i * 2 + odd;
37444 /* We'll either be able to implement the permutation directly... */
37445 if (expand_vec_perm_1 (&d))
37448 /* ... or we use the special-case patterns. */
37449 expand_vec_perm_even_odd_1 (&d, odd);
37452 /* Expand an insert into a vector register through pinsr insn.
37453 Return true if successful. */
37456 ix86_expand_pinsr (rtx *operands)
37458 rtx dst = operands[0];
37459 rtx src = operands[3];
37461 unsigned int size = INTVAL (operands[1]);
37462 unsigned int pos = INTVAL (operands[2]);
37464 if (GET_CODE (dst) == SUBREG)
37466 pos += SUBREG_BYTE (dst) * BITS_PER_UNIT;
37467 dst = SUBREG_REG (dst);
37470 if (GET_CODE (src) == SUBREG)
37471 src = SUBREG_REG (src);
37473 switch (GET_MODE (dst))
37480 enum machine_mode srcmode, dstmode;
37481 rtx (*pinsr)(rtx, rtx, rtx, rtx);
37483 srcmode = mode_for_size (size, MODE_INT, 0);
37488 if (!TARGET_SSE4_1)
37490 dstmode = V16QImode;
37491 pinsr = gen_sse4_1_pinsrb;
37497 dstmode = V8HImode;
37498 pinsr = gen_sse2_pinsrw;
37502 if (!TARGET_SSE4_1)
37504 dstmode = V4SImode;
37505 pinsr = gen_sse4_1_pinsrd;
37509 gcc_assert (TARGET_64BIT);
37510 if (!TARGET_SSE4_1)
37512 dstmode = V2DImode;
37513 pinsr = gen_sse4_1_pinsrq;
37520 dst = gen_lowpart (dstmode, dst);
37521 src = gen_lowpart (srcmode, src);
37525 emit_insn (pinsr (dst, dst, src, GEN_INT (1 << pos)));
37534 /* This function returns the calling abi specific va_list type node.
37535 It returns the FNDECL specific va_list type. */
37538 ix86_fn_abi_va_list (tree fndecl)
37541 return va_list_type_node;
37542 gcc_assert (fndecl != NULL_TREE);
37544 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
37545 return ms_va_list_type_node;
37547 return sysv_va_list_type_node;
37550 /* Returns the canonical va_list type specified by TYPE. If there
37551 is no valid TYPE provided, it return NULL_TREE. */
37554 ix86_canonical_va_list_type (tree type)
37558 /* Resolve references and pointers to va_list type. */
37559 if (TREE_CODE (type) == MEM_REF)
37560 type = TREE_TYPE (type);
37561 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
37562 type = TREE_TYPE (type);
37563 else if (POINTER_TYPE_P (type) && TREE_CODE (TREE_TYPE (type)) == ARRAY_TYPE)
37564 type = TREE_TYPE (type);
37566 if (TARGET_64BIT && va_list_type_node != NULL_TREE)
37568 wtype = va_list_type_node;
37569 gcc_assert (wtype != NULL_TREE);
37571 if (TREE_CODE (wtype) == ARRAY_TYPE)
37573 /* If va_list is an array type, the argument may have decayed
37574 to a pointer type, e.g. by being passed to another function.
37575 In that case, unwrap both types so that we can compare the
37576 underlying records. */
37577 if (TREE_CODE (htype) == ARRAY_TYPE
37578 || POINTER_TYPE_P (htype))
37580 wtype = TREE_TYPE (wtype);
37581 htype = TREE_TYPE (htype);
37584 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
37585 return va_list_type_node;
37586 wtype = sysv_va_list_type_node;
37587 gcc_assert (wtype != NULL_TREE);
37589 if (TREE_CODE (wtype) == ARRAY_TYPE)
37591 /* If va_list is an array type, the argument may have decayed
37592 to a pointer type, e.g. by being passed to another function.
37593 In that case, unwrap both types so that we can compare the
37594 underlying records. */
37595 if (TREE_CODE (htype) == ARRAY_TYPE
37596 || POINTER_TYPE_P (htype))
37598 wtype = TREE_TYPE (wtype);
37599 htype = TREE_TYPE (htype);
37602 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
37603 return sysv_va_list_type_node;
37604 wtype = ms_va_list_type_node;
37605 gcc_assert (wtype != NULL_TREE);
37607 if (TREE_CODE (wtype) == ARRAY_TYPE)
37609 /* If va_list is an array type, the argument may have decayed
37610 to a pointer type, e.g. by being passed to another function.
37611 In that case, unwrap both types so that we can compare the
37612 underlying records. */
37613 if (TREE_CODE (htype) == ARRAY_TYPE
37614 || POINTER_TYPE_P (htype))
37616 wtype = TREE_TYPE (wtype);
37617 htype = TREE_TYPE (htype);
37620 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
37621 return ms_va_list_type_node;
37624 return std_canonical_va_list_type (type);
37627 /* Iterate through the target-specific builtin types for va_list.
37628 IDX denotes the iterator, *PTREE is set to the result type of
37629 the va_list builtin, and *PNAME to its internal type.
37630 Returns zero if there is no element for this index, otherwise
37631 IDX should be increased upon the next call.
37632 Note, do not iterate a base builtin's name like __builtin_va_list.
37633 Used from c_common_nodes_and_builtins. */
37636 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
37646 *ptree = ms_va_list_type_node;
37647 *pname = "__builtin_ms_va_list";
37651 *ptree = sysv_va_list_type_node;
37652 *pname = "__builtin_sysv_va_list";
37660 #undef TARGET_SCHED_DISPATCH
37661 #define TARGET_SCHED_DISPATCH has_dispatch
37662 #undef TARGET_SCHED_DISPATCH_DO
37663 #define TARGET_SCHED_DISPATCH_DO do_dispatch
37664 #undef TARGET_SCHED_REASSOCIATION_WIDTH
37665 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
37667 /* The size of the dispatch window is the total number of bytes of
37668 object code allowed in a window. */
37669 #define DISPATCH_WINDOW_SIZE 16
37671 /* Number of dispatch windows considered for scheduling. */
37672 #define MAX_DISPATCH_WINDOWS 3
37674 /* Maximum number of instructions in a window. */
37677 /* Maximum number of immediate operands in a window. */
37680 /* Maximum number of immediate bits allowed in a window. */
37681 #define MAX_IMM_SIZE 128
37683 /* Maximum number of 32 bit immediates allowed in a window. */
37684 #define MAX_IMM_32 4
37686 /* Maximum number of 64 bit immediates allowed in a window. */
37687 #define MAX_IMM_64 2
37689 /* Maximum total of loads or prefetches allowed in a window. */
37692 /* Maximum total of stores allowed in a window. */
37693 #define MAX_STORE 1
37699 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
37700 enum dispatch_group {
37715 /* Number of allowable groups in a dispatch window. It is an array
37716 indexed by dispatch_group enum. 100 is used as a big number,
37717 because the number of these kind of operations does not have any
37718 effect in dispatch window, but we need them for other reasons in
37720 static unsigned int num_allowable_groups[disp_last] = {
37721 0, 2, 1, 1, 2, 4, 4, 2, 1, BIG, BIG
37724 char group_name[disp_last + 1][16] = {
37725 "disp_no_group", "disp_load", "disp_store", "disp_load_store",
37726 "disp_prefetch", "disp_imm", "disp_imm_32", "disp_imm_64",
37727 "disp_branch", "disp_cmp", "disp_jcc", "disp_last"
37730 /* Instruction path. */
37733 path_single, /* Single micro op. */
37734 path_double, /* Double micro op. */
37735 path_multi, /* Instructions with more than 2 micro op.. */
37739 /* sched_insn_info defines a window to the instructions scheduled in
37740 the basic block. It contains a pointer to the insn_info table and
37741 the instruction scheduled.
37743 Windows are allocated for each basic block and are linked
37745 typedef struct sched_insn_info_s {
37747 enum dispatch_group group;
37748 enum insn_path path;
37753 /* Linked list of dispatch windows. This is a two way list of
37754 dispatch windows of a basic block. It contains information about
37755 the number of uops in the window and the total number of
37756 instructions and of bytes in the object code for this dispatch
37758 typedef struct dispatch_windows_s {
37759 int num_insn; /* Number of insn in the window. */
37760 int num_uops; /* Number of uops in the window. */
37761 int window_size; /* Number of bytes in the window. */
37762 int window_num; /* Window number between 0 or 1. */
37763 int num_imm; /* Number of immediates in an insn. */
37764 int num_imm_32; /* Number of 32 bit immediates in an insn. */
37765 int num_imm_64; /* Number of 64 bit immediates in an insn. */
37766 int imm_size; /* Total immediates in the window. */
37767 int num_loads; /* Total memory loads in the window. */
37768 int num_stores; /* Total memory stores in the window. */
37769 int violation; /* Violation exists in window. */
37770 sched_insn_info *window; /* Pointer to the window. */
37771 struct dispatch_windows_s *next;
37772 struct dispatch_windows_s *prev;
37773 } dispatch_windows;
37775 /* Immediate valuse used in an insn. */
37776 typedef struct imm_info_s
37783 static dispatch_windows *dispatch_window_list;
37784 static dispatch_windows *dispatch_window_list1;
37786 /* Get dispatch group of insn. */
37788 static enum dispatch_group
37789 get_mem_group (rtx insn)
37791 enum attr_memory memory;
37793 if (INSN_CODE (insn) < 0)
37794 return disp_no_group;
37795 memory = get_attr_memory (insn);
37796 if (memory == MEMORY_STORE)
37799 if (memory == MEMORY_LOAD)
37802 if (memory == MEMORY_BOTH)
37803 return disp_load_store;
37805 return disp_no_group;
37808 /* Return true if insn is a compare instruction. */
37813 enum attr_type type;
37815 type = get_attr_type (insn);
37816 return (type == TYPE_TEST
37817 || type == TYPE_ICMP
37818 || type == TYPE_FCMP
37819 || GET_CODE (PATTERN (insn)) == COMPARE);
37822 /* Return true if a dispatch violation encountered. */
37825 dispatch_violation (void)
37827 if (dispatch_window_list->next)
37828 return dispatch_window_list->next->violation;
37829 return dispatch_window_list->violation;
37832 /* Return true if insn is a branch instruction. */
37835 is_branch (rtx insn)
37837 return (CALL_P (insn) || JUMP_P (insn));
37840 /* Return true if insn is a prefetch instruction. */
37843 is_prefetch (rtx insn)
37845 return NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == PREFETCH;
37848 /* This function initializes a dispatch window and the list container holding a
37849 pointer to the window. */
37852 init_window (int window_num)
37855 dispatch_windows *new_list;
37857 if (window_num == 0)
37858 new_list = dispatch_window_list;
37860 new_list = dispatch_window_list1;
37862 new_list->num_insn = 0;
37863 new_list->num_uops = 0;
37864 new_list->window_size = 0;
37865 new_list->next = NULL;
37866 new_list->prev = NULL;
37867 new_list->window_num = window_num;
37868 new_list->num_imm = 0;
37869 new_list->num_imm_32 = 0;
37870 new_list->num_imm_64 = 0;
37871 new_list->imm_size = 0;
37872 new_list->num_loads = 0;
37873 new_list->num_stores = 0;
37874 new_list->violation = false;
37876 for (i = 0; i < MAX_INSN; i++)
37878 new_list->window[i].insn = NULL;
37879 new_list->window[i].group = disp_no_group;
37880 new_list->window[i].path = no_path;
37881 new_list->window[i].byte_len = 0;
37882 new_list->window[i].imm_bytes = 0;
37887 /* This function allocates and initializes a dispatch window and the
37888 list container holding a pointer to the window. */
37890 static dispatch_windows *
37891 allocate_window (void)
37893 dispatch_windows *new_list = XNEW (struct dispatch_windows_s);
37894 new_list->window = XNEWVEC (struct sched_insn_info_s, MAX_INSN + 1);
37899 /* This routine initializes the dispatch scheduling information. It
37900 initiates building dispatch scheduler tables and constructs the
37901 first dispatch window. */
37904 init_dispatch_sched (void)
37906 /* Allocate a dispatch list and a window. */
37907 dispatch_window_list = allocate_window ();
37908 dispatch_window_list1 = allocate_window ();
37913 /* This function returns true if a branch is detected. End of a basic block
37914 does not have to be a branch, but here we assume only branches end a
37918 is_end_basic_block (enum dispatch_group group)
37920 return group == disp_branch;
37923 /* This function is called when the end of a window processing is reached. */
37926 process_end_window (void)
37928 gcc_assert (dispatch_window_list->num_insn <= MAX_INSN);
37929 if (dispatch_window_list->next)
37931 gcc_assert (dispatch_window_list1->num_insn <= MAX_INSN);
37932 gcc_assert (dispatch_window_list->window_size
37933 + dispatch_window_list1->window_size <= 48);
37939 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
37940 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
37941 for 48 bytes of instructions. Note that these windows are not dispatch
37942 windows that their sizes are DISPATCH_WINDOW_SIZE. */
37944 static dispatch_windows *
37945 allocate_next_window (int window_num)
37947 if (window_num == 0)
37949 if (dispatch_window_list->next)
37952 return dispatch_window_list;
37955 dispatch_window_list->next = dispatch_window_list1;
37956 dispatch_window_list1->prev = dispatch_window_list;
37958 return dispatch_window_list1;
37961 /* Increment the number of immediate operands of an instruction. */
37964 find_constant_1 (rtx *in_rtx, imm_info *imm_values)
37969 switch ( GET_CODE (*in_rtx))
37974 (imm_values->imm)++;
37975 if (x86_64_immediate_operand (*in_rtx, SImode))
37976 (imm_values->imm32)++;
37978 (imm_values->imm64)++;
37982 (imm_values->imm)++;
37983 (imm_values->imm64)++;
37987 if (LABEL_KIND (*in_rtx) == LABEL_NORMAL)
37989 (imm_values->imm)++;
37990 (imm_values->imm32)++;
38001 /* Compute number of immediate operands of an instruction. */
38004 find_constant (rtx in_rtx, imm_info *imm_values)
38006 for_each_rtx (INSN_P (in_rtx) ? &PATTERN (in_rtx) : &in_rtx,
38007 (rtx_function) find_constant_1, (void *) imm_values);
38010 /* Return total size of immediate operands of an instruction along with number
38011 of corresponding immediate-operands. It initializes its parameters to zero
38012 befor calling FIND_CONSTANT.
38013 INSN is the input instruction. IMM is the total of immediates.
38014 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
38018 get_num_immediates (rtx insn, int *imm, int *imm32, int *imm64)
38020 imm_info imm_values = {0, 0, 0};
38022 find_constant (insn, &imm_values);
38023 *imm = imm_values.imm;
38024 *imm32 = imm_values.imm32;
38025 *imm64 = imm_values.imm64;
38026 return imm_values.imm32 * 4 + imm_values.imm64 * 8;
38029 /* This function indicates if an operand of an instruction is an
38033 has_immediate (rtx insn)
38035 int num_imm_operand;
38036 int num_imm32_operand;
38037 int num_imm64_operand;
38040 return get_num_immediates (insn, &num_imm_operand, &num_imm32_operand,
38041 &num_imm64_operand);
38045 /* Return single or double path for instructions. */
38047 static enum insn_path
38048 get_insn_path (rtx insn)
38050 enum attr_amdfam10_decode path = get_attr_amdfam10_decode (insn);
38052 if ((int)path == 0)
38053 return path_single;
38055 if ((int)path == 1)
38056 return path_double;
38061 /* Return insn dispatch group. */
38063 static enum dispatch_group
38064 get_insn_group (rtx insn)
38066 enum dispatch_group group = get_mem_group (insn);
38070 if (is_branch (insn))
38071 return disp_branch;
38076 if (has_immediate (insn))
38079 if (is_prefetch (insn))
38080 return disp_prefetch;
38082 return disp_no_group;
38085 /* Count number of GROUP restricted instructions in a dispatch
38086 window WINDOW_LIST. */
38089 count_num_restricted (rtx insn, dispatch_windows *window_list)
38091 enum dispatch_group group = get_insn_group (insn);
38093 int num_imm_operand;
38094 int num_imm32_operand;
38095 int num_imm64_operand;
38097 if (group == disp_no_group)
38100 if (group == disp_imm)
38102 imm_size = get_num_immediates (insn, &num_imm_operand, &num_imm32_operand,
38103 &num_imm64_operand);
38104 if (window_list->imm_size + imm_size > MAX_IMM_SIZE
38105 || num_imm_operand + window_list->num_imm > MAX_IMM
38106 || (num_imm32_operand > 0
38107 && (window_list->num_imm_32 + num_imm32_operand > MAX_IMM_32
38108 || window_list->num_imm_64 * 2 + num_imm32_operand > MAX_IMM_32))
38109 || (num_imm64_operand > 0
38110 && (window_list->num_imm_64 + num_imm64_operand > MAX_IMM_64
38111 || window_list->num_imm_32 + num_imm64_operand * 2 > MAX_IMM_32))
38112 || (window_list->imm_size + imm_size == MAX_IMM_SIZE
38113 && num_imm64_operand > 0
38114 && ((window_list->num_imm_64 > 0
38115 && window_list->num_insn >= 2)
38116 || window_list->num_insn >= 3)))
38122 if ((group == disp_load_store
38123 && (window_list->num_loads >= MAX_LOAD
38124 || window_list->num_stores >= MAX_STORE))
38125 || ((group == disp_load
38126 || group == disp_prefetch)
38127 && window_list->num_loads >= MAX_LOAD)
38128 || (group == disp_store
38129 && window_list->num_stores >= MAX_STORE))
38135 /* This function returns true if insn satisfies dispatch rules on the
38136 last window scheduled. */
38139 fits_dispatch_window (rtx insn)
38141 dispatch_windows *window_list = dispatch_window_list;
38142 dispatch_windows *window_list_next = dispatch_window_list->next;
38143 unsigned int num_restrict;
38144 enum dispatch_group group = get_insn_group (insn);
38145 enum insn_path path = get_insn_path (insn);
38148 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
38149 instructions should be given the lowest priority in the
38150 scheduling process in Haifa scheduler to make sure they will be
38151 scheduled in the same dispatch window as the refrence to them. */
38152 if (group == disp_jcc || group == disp_cmp)
38155 /* Check nonrestricted. */
38156 if (group == disp_no_group || group == disp_branch)
38159 /* Get last dispatch window. */
38160 if (window_list_next)
38161 window_list = window_list_next;
38163 if (window_list->window_num == 1)
38165 sum = window_list->prev->window_size + window_list->window_size;
38168 || (min_insn_size (insn) + sum) >= 48)
38169 /* Window 1 is full. Go for next window. */
38173 num_restrict = count_num_restricted (insn, window_list);
38175 if (num_restrict > num_allowable_groups[group])
38178 /* See if it fits in the first window. */
38179 if (window_list->window_num == 0)
38181 /* The first widow should have only single and double path
38183 if (path == path_double
38184 && (window_list->num_uops + 2) > MAX_INSN)
38186 else if (path != path_single)
38192 /* Add an instruction INSN with NUM_UOPS micro-operations to the
38193 dispatch window WINDOW_LIST. */
38196 add_insn_window (rtx insn, dispatch_windows *window_list, int num_uops)
38198 int byte_len = min_insn_size (insn);
38199 int num_insn = window_list->num_insn;
38201 sched_insn_info *window = window_list->window;
38202 enum dispatch_group group = get_insn_group (insn);
38203 enum insn_path path = get_insn_path (insn);
38204 int num_imm_operand;
38205 int num_imm32_operand;
38206 int num_imm64_operand;
38208 if (!window_list->violation && group != disp_cmp
38209 && !fits_dispatch_window (insn))
38210 window_list->violation = true;
38212 imm_size = get_num_immediates (insn, &num_imm_operand, &num_imm32_operand,
38213 &num_imm64_operand);
38215 /* Initialize window with new instruction. */
38216 window[num_insn].insn = insn;
38217 window[num_insn].byte_len = byte_len;
38218 window[num_insn].group = group;
38219 window[num_insn].path = path;
38220 window[num_insn].imm_bytes = imm_size;
38222 window_list->window_size += byte_len;
38223 window_list->num_insn = num_insn + 1;
38224 window_list->num_uops = window_list->num_uops + num_uops;
38225 window_list->imm_size += imm_size;
38226 window_list->num_imm += num_imm_operand;
38227 window_list->num_imm_32 += num_imm32_operand;
38228 window_list->num_imm_64 += num_imm64_operand;
38230 if (group == disp_store)
38231 window_list->num_stores += 1;
38232 else if (group == disp_load
38233 || group == disp_prefetch)
38234 window_list->num_loads += 1;
38235 else if (group == disp_load_store)
38237 window_list->num_stores += 1;
38238 window_list->num_loads += 1;
38242 /* Adds a scheduled instruction, INSN, to the current dispatch window.
38243 If the total bytes of instructions or the number of instructions in
38244 the window exceed allowable, it allocates a new window. */
38247 add_to_dispatch_window (rtx insn)
38250 dispatch_windows *window_list;
38251 dispatch_windows *next_list;
38252 dispatch_windows *window0_list;
38253 enum insn_path path;
38254 enum dispatch_group insn_group;
38262 if (INSN_CODE (insn) < 0)
38265 byte_len = min_insn_size (insn);
38266 window_list = dispatch_window_list;
38267 next_list = window_list->next;
38268 path = get_insn_path (insn);
38269 insn_group = get_insn_group (insn);
38271 /* Get the last dispatch window. */
38273 window_list = dispatch_window_list->next;
38275 if (path == path_single)
38277 else if (path == path_double)
38280 insn_num_uops = (int) path;
38282 /* If current window is full, get a new window.
38283 Window number zero is full, if MAX_INSN uops are scheduled in it.
38284 Window number one is full, if window zero's bytes plus window
38285 one's bytes is 32, or if the bytes of the new instruction added
38286 to the total makes it greater than 48, or it has already MAX_INSN
38287 instructions in it. */
38288 num_insn = window_list->num_insn;
38289 num_uops = window_list->num_uops;
38290 window_num = window_list->window_num;
38291 insn_fits = fits_dispatch_window (insn);
38293 if (num_insn >= MAX_INSN
38294 || num_uops + insn_num_uops > MAX_INSN
38297 window_num = ~window_num & 1;
38298 window_list = allocate_next_window (window_num);
38301 if (window_num == 0)
38303 add_insn_window (insn, window_list, insn_num_uops);
38304 if (window_list->num_insn >= MAX_INSN
38305 && insn_group == disp_branch)
38307 process_end_window ();
38311 else if (window_num == 1)
38313 window0_list = window_list->prev;
38314 sum = window0_list->window_size + window_list->window_size;
38316 || (byte_len + sum) >= 48)
38318 process_end_window ();
38319 window_list = dispatch_window_list;
38322 add_insn_window (insn, window_list, insn_num_uops);
38325 gcc_unreachable ();
38327 if (is_end_basic_block (insn_group))
38329 /* End of basic block is reached do end-basic-block process. */
38330 process_end_window ();
38335 /* Print the dispatch window, WINDOW_NUM, to FILE. */
38337 DEBUG_FUNCTION static void
38338 debug_dispatch_window_file (FILE *file, int window_num)
38340 dispatch_windows *list;
38343 if (window_num == 0)
38344 list = dispatch_window_list;
38346 list = dispatch_window_list1;
38348 fprintf (file, "Window #%d:\n", list->window_num);
38349 fprintf (file, " num_insn = %d, num_uops = %d, window_size = %d\n",
38350 list->num_insn, list->num_uops, list->window_size);
38351 fprintf (file, " num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n",
38352 list->num_imm, list->num_imm_32, list->num_imm_64, list->imm_size);
38354 fprintf (file, " num_loads = %d, num_stores = %d\n", list->num_loads,
38356 fprintf (file, " insn info:\n");
38358 for (i = 0; i < MAX_INSN; i++)
38360 if (!list->window[i].insn)
38362 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
38363 i, group_name[list->window[i].group],
38364 i, (void *)list->window[i].insn,
38365 i, list->window[i].path,
38366 i, list->window[i].byte_len,
38367 i, list->window[i].imm_bytes);
38371 /* Print to stdout a dispatch window. */
38373 DEBUG_FUNCTION void
38374 debug_dispatch_window (int window_num)
38376 debug_dispatch_window_file (stdout, window_num);
38379 /* Print INSN dispatch information to FILE. */
38381 DEBUG_FUNCTION static void
38382 debug_insn_dispatch_info_file (FILE *file, rtx insn)
38385 enum insn_path path;
38386 enum dispatch_group group;
38388 int num_imm_operand;
38389 int num_imm32_operand;
38390 int num_imm64_operand;
38392 if (INSN_CODE (insn) < 0)
38395 byte_len = min_insn_size (insn);
38396 path = get_insn_path (insn);
38397 group = get_insn_group (insn);
38398 imm_size = get_num_immediates (insn, &num_imm_operand, &num_imm32_operand,
38399 &num_imm64_operand);
38401 fprintf (file, " insn info:\n");
38402 fprintf (file, " group = %s, path = %d, byte_len = %d\n",
38403 group_name[group], path, byte_len);
38404 fprintf (file, " num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n",
38405 num_imm_operand, num_imm32_operand, num_imm64_operand, imm_size);
38408 /* Print to STDERR the status of the ready list with respect to
38409 dispatch windows. */
38411 DEBUG_FUNCTION void
38412 debug_ready_dispatch (void)
38415 int no_ready = number_in_ready ();
38417 fprintf (stdout, "Number of ready: %d\n", no_ready);
38419 for (i = 0; i < no_ready; i++)
38420 debug_insn_dispatch_info_file (stdout, get_ready_element (i));
38423 /* This routine is the driver of the dispatch scheduler. */
38426 do_dispatch (rtx insn, int mode)
38428 if (mode == DISPATCH_INIT)
38429 init_dispatch_sched ();
38430 else if (mode == ADD_TO_DISPATCH_WINDOW)
38431 add_to_dispatch_window (insn);
38434 /* Return TRUE if Dispatch Scheduling is supported. */
38437 has_dispatch (rtx insn, int action)
38439 if ((ix86_tune == PROCESSOR_BDVER1 || ix86_tune == PROCESSOR_BDVER2)
38440 && flag_dispatch_scheduler)
38446 case IS_DISPATCH_ON:
38451 return is_cmp (insn);
38453 case DISPATCH_VIOLATION:
38454 return dispatch_violation ();
38456 case FITS_DISPATCH_WINDOW:
38457 return fits_dispatch_window (insn);
38463 /* Implementation of reassociation_width target hook used by
38464 reassoc phase to identify parallelism level in reassociated
38465 tree. Statements tree_code is passed in OPC. Arguments type
38468 Currently parallel reassociation is enabled for Atom
38469 processors only and we set reassociation width to be 2
38470 because Atom may issue up to 2 instructions per cycle.
38472 Return value should be fixed if parallel reassociation is
38473 enabled for other processors. */
38476 ix86_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
38477 enum machine_mode mode)
38481 if (INTEGRAL_MODE_P (mode) && TARGET_REASSOC_INT_TO_PARALLEL)
38483 else if (FLOAT_MODE_P (mode) && TARGET_REASSOC_FP_TO_PARALLEL)
38489 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
38490 place emms and femms instructions. */
38492 static enum machine_mode
38493 ix86_preferred_simd_mode (enum machine_mode mode)
38501 return (TARGET_AVX && !TARGET_PREFER_AVX128) ? V32QImode : V16QImode;
38503 return (TARGET_AVX && !TARGET_PREFER_AVX128) ? V16HImode : V8HImode;
38505 return (TARGET_AVX && !TARGET_PREFER_AVX128) ? V8SImode : V4SImode;
38507 return (TARGET_AVX && !TARGET_PREFER_AVX128) ? V4DImode : V2DImode;
38510 if (TARGET_AVX && !TARGET_PREFER_AVX128)
38516 if (!TARGET_VECTORIZE_DOUBLE)
38518 else if (TARGET_AVX && !TARGET_PREFER_AVX128)
38520 else if (TARGET_SSE2)
38529 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
38532 static unsigned int
38533 ix86_autovectorize_vector_sizes (void)
38535 return (TARGET_AVX && !TARGET_PREFER_AVX128) ? 32 | 16 : 0;
38538 /* Initialize the GCC target structure. */
38539 #undef TARGET_RETURN_IN_MEMORY
38540 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
38542 #undef TARGET_LEGITIMIZE_ADDRESS
38543 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
38545 #undef TARGET_ATTRIBUTE_TABLE
38546 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
38547 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38548 # undef TARGET_MERGE_DECL_ATTRIBUTES
38549 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
38552 #undef TARGET_COMP_TYPE_ATTRIBUTES
38553 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
38555 #undef TARGET_INIT_BUILTINS
38556 #define TARGET_INIT_BUILTINS ix86_init_builtins
38557 #undef TARGET_BUILTIN_DECL
38558 #define TARGET_BUILTIN_DECL ix86_builtin_decl
38559 #undef TARGET_EXPAND_BUILTIN
38560 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
38562 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
38563 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
38564 ix86_builtin_vectorized_function
38566 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
38567 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
38569 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
38570 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
38572 #undef TARGET_VECTORIZE_BUILTIN_GATHER
38573 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
38575 #undef TARGET_BUILTIN_RECIPROCAL
38576 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
38578 #undef TARGET_ASM_FUNCTION_EPILOGUE
38579 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
38581 #undef TARGET_ENCODE_SECTION_INFO
38582 #ifndef SUBTARGET_ENCODE_SECTION_INFO
38583 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
38585 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
38588 #undef TARGET_ASM_OPEN_PAREN
38589 #define TARGET_ASM_OPEN_PAREN ""
38590 #undef TARGET_ASM_CLOSE_PAREN
38591 #define TARGET_ASM_CLOSE_PAREN ""
38593 #undef TARGET_ASM_BYTE_OP
38594 #define TARGET_ASM_BYTE_OP ASM_BYTE
38596 #undef TARGET_ASM_ALIGNED_HI_OP
38597 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
38598 #undef TARGET_ASM_ALIGNED_SI_OP
38599 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
38601 #undef TARGET_ASM_ALIGNED_DI_OP
38602 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
38605 #undef TARGET_PROFILE_BEFORE_PROLOGUE
38606 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
38608 #undef TARGET_ASM_UNALIGNED_HI_OP
38609 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
38610 #undef TARGET_ASM_UNALIGNED_SI_OP
38611 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
38612 #undef TARGET_ASM_UNALIGNED_DI_OP
38613 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
38615 #undef TARGET_PRINT_OPERAND
38616 #define TARGET_PRINT_OPERAND ix86_print_operand
38617 #undef TARGET_PRINT_OPERAND_ADDRESS
38618 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
38619 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
38620 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
38621 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
38622 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
38624 #undef TARGET_SCHED_INIT_GLOBAL
38625 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
38626 #undef TARGET_SCHED_ADJUST_COST
38627 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
38628 #undef TARGET_SCHED_ISSUE_RATE
38629 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
38630 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
38631 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
38632 ia32_multipass_dfa_lookahead
38634 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
38635 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
38638 #undef TARGET_HAVE_TLS
38639 #define TARGET_HAVE_TLS true
38641 #undef TARGET_CANNOT_FORCE_CONST_MEM
38642 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
38643 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
38644 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
38646 #undef TARGET_DELEGITIMIZE_ADDRESS
38647 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
38649 #undef TARGET_MS_BITFIELD_LAYOUT_P
38650 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
38653 #undef TARGET_BINDS_LOCAL_P
38654 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
38656 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38657 #undef TARGET_BINDS_LOCAL_P
38658 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
38661 #undef TARGET_ASM_OUTPUT_MI_THUNK
38662 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
38663 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
38664 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
38666 #undef TARGET_ASM_FILE_START
38667 #define TARGET_ASM_FILE_START x86_file_start
38669 #undef TARGET_OPTION_OVERRIDE
38670 #define TARGET_OPTION_OVERRIDE ix86_option_override
38672 #undef TARGET_REGISTER_MOVE_COST
38673 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
38674 #undef TARGET_MEMORY_MOVE_COST
38675 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
38676 #undef TARGET_RTX_COSTS
38677 #define TARGET_RTX_COSTS ix86_rtx_costs
38678 #undef TARGET_ADDRESS_COST
38679 #define TARGET_ADDRESS_COST ix86_address_cost
38681 #undef TARGET_FIXED_CONDITION_CODE_REGS
38682 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
38683 #undef TARGET_CC_MODES_COMPATIBLE
38684 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
38686 #undef TARGET_MACHINE_DEPENDENT_REORG
38687 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
38689 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
38690 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
38692 #undef TARGET_BUILD_BUILTIN_VA_LIST
38693 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
38695 #undef TARGET_ENUM_VA_LIST_P
38696 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
38698 #undef TARGET_FN_ABI_VA_LIST
38699 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
38701 #undef TARGET_CANONICAL_VA_LIST_TYPE
38702 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
38704 #undef TARGET_EXPAND_BUILTIN_VA_START
38705 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
38707 #undef TARGET_MD_ASM_CLOBBERS
38708 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
38710 #undef TARGET_PROMOTE_PROTOTYPES
38711 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
38712 #undef TARGET_STRUCT_VALUE_RTX
38713 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
38714 #undef TARGET_SETUP_INCOMING_VARARGS
38715 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
38716 #undef TARGET_MUST_PASS_IN_STACK
38717 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
38718 #undef TARGET_FUNCTION_ARG_ADVANCE
38719 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
38720 #undef TARGET_FUNCTION_ARG
38721 #define TARGET_FUNCTION_ARG ix86_function_arg
38722 #undef TARGET_FUNCTION_ARG_BOUNDARY
38723 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
38724 #undef TARGET_PASS_BY_REFERENCE
38725 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
38726 #undef TARGET_INTERNAL_ARG_POINTER
38727 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
38728 #undef TARGET_UPDATE_STACK_BOUNDARY
38729 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
38730 #undef TARGET_GET_DRAP_RTX
38731 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
38732 #undef TARGET_STRICT_ARGUMENT_NAMING
38733 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
38734 #undef TARGET_STATIC_CHAIN
38735 #define TARGET_STATIC_CHAIN ix86_static_chain
38736 #undef TARGET_TRAMPOLINE_INIT
38737 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
38738 #undef TARGET_RETURN_POPS_ARGS
38739 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
38741 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
38742 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
38744 #undef TARGET_SCALAR_MODE_SUPPORTED_P
38745 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
38747 #undef TARGET_VECTOR_MODE_SUPPORTED_P
38748 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
38750 #undef TARGET_C_MODE_FOR_SUFFIX
38751 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
38754 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
38755 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
38758 #ifdef SUBTARGET_INSERT_ATTRIBUTES
38759 #undef TARGET_INSERT_ATTRIBUTES
38760 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
38763 #undef TARGET_MANGLE_TYPE
38764 #define TARGET_MANGLE_TYPE ix86_mangle_type
38767 #undef TARGET_STACK_PROTECT_FAIL
38768 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
38771 #undef TARGET_FUNCTION_VALUE
38772 #define TARGET_FUNCTION_VALUE ix86_function_value
38774 #undef TARGET_FUNCTION_VALUE_REGNO_P
38775 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
38777 #undef TARGET_PROMOTE_FUNCTION_MODE
38778 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
38780 #undef TARGET_SECONDARY_RELOAD
38781 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
38783 #undef TARGET_CLASS_MAX_NREGS
38784 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
38786 #undef TARGET_PREFERRED_RELOAD_CLASS
38787 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
38788 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
38789 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
38790 #undef TARGET_CLASS_LIKELY_SPILLED_P
38791 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
38793 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
38794 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
38795 ix86_builtin_vectorization_cost
38796 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
38797 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
38798 ix86_vectorize_vec_perm_const_ok
38799 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
38800 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
38801 ix86_preferred_simd_mode
38802 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
38803 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
38804 ix86_autovectorize_vector_sizes
38806 #undef TARGET_SET_CURRENT_FUNCTION
38807 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
38809 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
38810 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
38812 #undef TARGET_OPTION_SAVE
38813 #define TARGET_OPTION_SAVE ix86_function_specific_save
38815 #undef TARGET_OPTION_RESTORE
38816 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
38818 #undef TARGET_OPTION_PRINT
38819 #define TARGET_OPTION_PRINT ix86_function_specific_print
38821 #undef TARGET_CAN_INLINE_P
38822 #define TARGET_CAN_INLINE_P ix86_can_inline_p
38824 #undef TARGET_EXPAND_TO_RTL_HOOK
38825 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
38827 #undef TARGET_LEGITIMATE_ADDRESS_P
38828 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
38830 #undef TARGET_LEGITIMATE_CONSTANT_P
38831 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
38833 #undef TARGET_FRAME_POINTER_REQUIRED
38834 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
38836 #undef TARGET_CAN_ELIMINATE
38837 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
38839 #undef TARGET_EXTRA_LIVE_ON_ENTRY
38840 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
38842 #undef TARGET_ASM_CODE_END
38843 #define TARGET_ASM_CODE_END ix86_code_end
38845 #undef TARGET_CONDITIONAL_REGISTER_USAGE
38846 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
38849 #undef TARGET_INIT_LIBFUNCS
38850 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
38853 struct gcc_target targetm = TARGET_INITIALIZER;
38855 #include "gt-i386.h"