1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #include "tm-constrs.h"
56 static int x86_builtin_vectorization_cost (bool);
58 #ifndef CHECK_STACK_LIMIT
59 #define CHECK_STACK_LIMIT (-1)
62 /* Return index of given mode in mult and division cost tables. */
63 #define MODE_INDEX(mode) \
64 ((mode) == QImode ? 0 \
65 : (mode) == HImode ? 1 \
66 : (mode) == SImode ? 2 \
67 : (mode) == DImode ? 3 \
70 /* Processor costs (relative to an add) */
71 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
72 #define COSTS_N_BYTES(N) ((N) * 2)
74 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
77 struct processor_costs size_cost = { /* costs for tuning for size */
78 COSTS_N_BYTES (2), /* cost of an add instruction */
79 COSTS_N_BYTES (3), /* cost of a lea instruction */
80 COSTS_N_BYTES (2), /* variable shift costs */
81 COSTS_N_BYTES (3), /* constant shift costs */
82 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
83 COSTS_N_BYTES (3), /* HI */
84 COSTS_N_BYTES (3), /* SI */
85 COSTS_N_BYTES (3), /* DI */
86 COSTS_N_BYTES (5)}, /* other */
87 0, /* cost of multiply per each bit set */
88 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
89 COSTS_N_BYTES (3), /* HI */
90 COSTS_N_BYTES (3), /* SI */
91 COSTS_N_BYTES (3), /* DI */
92 COSTS_N_BYTES (5)}, /* other */
93 COSTS_N_BYTES (3), /* cost of movsx */
94 COSTS_N_BYTES (3), /* cost of movzx */
97 2, /* cost for loading QImode using movzbl */
98 {2, 2, 2}, /* cost of loading integer registers
99 in QImode, HImode and SImode.
100 Relative to reg-reg move (2). */
101 {2, 2, 2}, /* cost of storing integer registers */
102 2, /* cost of reg,reg fld/fst */
103 {2, 2, 2}, /* cost of loading fp registers
104 in SFmode, DFmode and XFmode */
105 {2, 2, 2}, /* cost of storing fp registers
106 in SFmode, DFmode and XFmode */
107 3, /* cost of moving MMX register */
108 {3, 3}, /* cost of loading MMX registers
109 in SImode and DImode */
110 {3, 3}, /* cost of storing MMX registers
111 in SImode and DImode */
112 3, /* cost of moving SSE register */
113 {3, 3, 3}, /* cost of loading SSE registers
114 in SImode, DImode and TImode */
115 {3, 3, 3}, /* cost of storing SSE registers
116 in SImode, DImode and TImode */
117 3, /* MMX or SSE register to integer */
118 0, /* size of l1 cache */
119 0, /* size of l2 cache */
120 0, /* size of prefetch block */
121 0, /* number of parallel prefetches */
123 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
124 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
125 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
126 COSTS_N_BYTES (2), /* cost of FABS instruction. */
127 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
128 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
129 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
130 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 1, /* scalar_stmt_cost. */
134 1, /* scalar load_cost. */
135 1, /* scalar_store_cost. */
136 1, /* vec_stmt_cost. */
137 1, /* vec_to_scalar_cost. */
138 1, /* scalar_to_vec_cost. */
139 1, /* vec_align_load_cost. */
140 1, /* vec_unalign_load_cost. */
141 1, /* vec_store_cost. */
142 1, /* cond_taken_branch_cost. */
143 1, /* cond_not_taken_branch_cost. */
146 /* Processor costs (relative to an add) */
148 struct processor_costs i386_cost = { /* 386 specific costs */
149 COSTS_N_INSNS (1), /* cost of an add instruction */
150 COSTS_N_INSNS (1), /* cost of a lea instruction */
151 COSTS_N_INSNS (3), /* variable shift costs */
152 COSTS_N_INSNS (2), /* constant shift costs */
153 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
154 COSTS_N_INSNS (6), /* HI */
155 COSTS_N_INSNS (6), /* SI */
156 COSTS_N_INSNS (6), /* DI */
157 COSTS_N_INSNS (6)}, /* other */
158 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
159 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
160 COSTS_N_INSNS (23), /* HI */
161 COSTS_N_INSNS (23), /* SI */
162 COSTS_N_INSNS (23), /* DI */
163 COSTS_N_INSNS (23)}, /* other */
164 COSTS_N_INSNS (3), /* cost of movsx */
165 COSTS_N_INSNS (2), /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of storing fp registers
177 in SFmode, DFmode and XFmode */
178 2, /* cost of moving MMX register */
179 {4, 8}, /* cost of loading MMX registers
180 in SImode and DImode */
181 {4, 8}, /* cost of storing MMX registers
182 in SImode and DImode */
183 2, /* cost of moving SSE register */
184 {4, 8, 16}, /* cost of loading SSE registers
185 in SImode, DImode and TImode */
186 {4, 8, 16}, /* cost of storing SSE registers
187 in SImode, DImode and TImode */
188 3, /* MMX or SSE register to integer */
189 0, /* size of l1 cache */
190 0, /* size of l2 cache */
191 0, /* size of prefetch block */
192 0, /* number of parallel prefetches */
194 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
195 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
196 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
197 COSTS_N_INSNS (22), /* cost of FABS instruction. */
198 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
199 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
200 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
201 DUMMY_STRINGOP_ALGS},
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 1, /* scalar_stmt_cost. */
205 1, /* scalar load_cost. */
206 1, /* scalar_store_cost. */
207 1, /* vec_stmt_cost. */
208 1, /* vec_to_scalar_cost. */
209 1, /* scalar_to_vec_cost. */
210 1, /* vec_align_load_cost. */
211 2, /* vec_unalign_load_cost. */
212 1, /* vec_store_cost. */
213 3, /* cond_taken_branch_cost. */
214 1, /* cond_not_taken_branch_cost. */
218 struct processor_costs i486_cost = { /* 486 specific costs */
219 COSTS_N_INSNS (1), /* cost of an add instruction */
220 COSTS_N_INSNS (1), /* cost of a lea instruction */
221 COSTS_N_INSNS (3), /* variable shift costs */
222 COSTS_N_INSNS (2), /* constant shift costs */
223 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
224 COSTS_N_INSNS (12), /* HI */
225 COSTS_N_INSNS (12), /* SI */
226 COSTS_N_INSNS (12), /* DI */
227 COSTS_N_INSNS (12)}, /* other */
228 1, /* cost of multiply per each bit set */
229 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
230 COSTS_N_INSNS (40), /* HI */
231 COSTS_N_INSNS (40), /* SI */
232 COSTS_N_INSNS (40), /* DI */
233 COSTS_N_INSNS (40)}, /* other */
234 COSTS_N_INSNS (3), /* cost of movsx */
235 COSTS_N_INSNS (2), /* cost of movzx */
236 15, /* "large" insn */
238 4, /* cost for loading QImode using movzbl */
239 {2, 4, 2}, /* cost of loading integer registers
240 in QImode, HImode and SImode.
241 Relative to reg-reg move (2). */
242 {2, 4, 2}, /* cost of storing integer registers */
243 2, /* cost of reg,reg fld/fst */
244 {8, 8, 8}, /* cost of loading fp registers
245 in SFmode, DFmode and XFmode */
246 {8, 8, 8}, /* cost of storing fp registers
247 in SFmode, DFmode and XFmode */
248 2, /* cost of moving MMX register */
249 {4, 8}, /* cost of loading MMX registers
250 in SImode and DImode */
251 {4, 8}, /* cost of storing MMX registers
252 in SImode and DImode */
253 2, /* cost of moving SSE register */
254 {4, 8, 16}, /* cost of loading SSE registers
255 in SImode, DImode and TImode */
256 {4, 8, 16}, /* cost of storing SSE registers
257 in SImode, DImode and TImode */
258 3, /* MMX or SSE register to integer */
259 4, /* size of l1 cache. 486 has 8kB cache
260 shared for code and data, so 4kB is
261 not really precise. */
262 4, /* size of l2 cache */
263 0, /* size of prefetch block */
264 0, /* number of parallel prefetches */
266 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
267 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
268 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
269 COSTS_N_INSNS (3), /* cost of FABS instruction. */
270 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
271 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
272 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
273 DUMMY_STRINGOP_ALGS},
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 1, /* scalar_stmt_cost. */
277 1, /* scalar load_cost. */
278 1, /* scalar_store_cost. */
279 1, /* vec_stmt_cost. */
280 1, /* vec_to_scalar_cost. */
281 1, /* scalar_to_vec_cost. */
282 1, /* vec_align_load_cost. */
283 2, /* vec_unalign_load_cost. */
284 1, /* vec_store_cost. */
285 3, /* cond_taken_branch_cost. */
286 1, /* cond_not_taken_branch_cost. */
290 struct processor_costs pentium_cost = {
291 COSTS_N_INSNS (1), /* cost of an add instruction */
292 COSTS_N_INSNS (1), /* cost of a lea instruction */
293 COSTS_N_INSNS (4), /* variable shift costs */
294 COSTS_N_INSNS (1), /* constant shift costs */
295 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
296 COSTS_N_INSNS (11), /* HI */
297 COSTS_N_INSNS (11), /* SI */
298 COSTS_N_INSNS (11), /* DI */
299 COSTS_N_INSNS (11)}, /* other */
300 0, /* cost of multiply per each bit set */
301 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
302 COSTS_N_INSNS (25), /* HI */
303 COSTS_N_INSNS (25), /* SI */
304 COSTS_N_INSNS (25), /* DI */
305 COSTS_N_INSNS (25)}, /* other */
306 COSTS_N_INSNS (3), /* cost of movsx */
307 COSTS_N_INSNS (2), /* cost of movzx */
308 8, /* "large" insn */
310 6, /* cost for loading QImode using movzbl */
311 {2, 4, 2}, /* cost of loading integer registers
312 in QImode, HImode and SImode.
313 Relative to reg-reg move (2). */
314 {2, 4, 2}, /* cost of storing integer registers */
315 2, /* cost of reg,reg fld/fst */
316 {2, 2, 6}, /* cost of loading fp registers
317 in SFmode, DFmode and XFmode */
318 {4, 4, 6}, /* cost of storing fp registers
319 in SFmode, DFmode and XFmode */
320 8, /* cost of moving MMX register */
321 {8, 8}, /* cost of loading MMX registers
322 in SImode and DImode */
323 {8, 8}, /* cost of storing MMX registers
324 in SImode and DImode */
325 2, /* cost of moving SSE register */
326 {4, 8, 16}, /* cost of loading SSE registers
327 in SImode, DImode and TImode */
328 {4, 8, 16}, /* cost of storing SSE registers
329 in SImode, DImode and TImode */
330 3, /* MMX or SSE register to integer */
331 8, /* size of l1 cache. */
332 8, /* size of l2 cache */
333 0, /* size of prefetch block */
334 0, /* number of parallel prefetches */
336 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
337 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
338 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
339 COSTS_N_INSNS (1), /* cost of FABS instruction. */
340 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
341 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
342 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
343 DUMMY_STRINGOP_ALGS},
344 {{libcall, {{-1, rep_prefix_4_byte}}},
345 DUMMY_STRINGOP_ALGS},
346 1, /* scalar_stmt_cost. */
347 1, /* scalar load_cost. */
348 1, /* scalar_store_cost. */
349 1, /* vec_stmt_cost. */
350 1, /* vec_to_scalar_cost. */
351 1, /* scalar_to_vec_cost. */
352 1, /* vec_align_load_cost. */
353 2, /* vec_unalign_load_cost. */
354 1, /* vec_store_cost. */
355 3, /* cond_taken_branch_cost. */
356 1, /* cond_not_taken_branch_cost. */
360 struct processor_costs pentiumpro_cost = {
361 COSTS_N_INSNS (1), /* cost of an add instruction */
362 COSTS_N_INSNS (1), /* cost of a lea instruction */
363 COSTS_N_INSNS (1), /* variable shift costs */
364 COSTS_N_INSNS (1), /* constant shift costs */
365 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
366 COSTS_N_INSNS (4), /* HI */
367 COSTS_N_INSNS (4), /* SI */
368 COSTS_N_INSNS (4), /* DI */
369 COSTS_N_INSNS (4)}, /* other */
370 0, /* cost of multiply per each bit set */
371 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
372 COSTS_N_INSNS (17), /* HI */
373 COSTS_N_INSNS (17), /* SI */
374 COSTS_N_INSNS (17), /* DI */
375 COSTS_N_INSNS (17)}, /* other */
376 COSTS_N_INSNS (1), /* cost of movsx */
377 COSTS_N_INSNS (1), /* cost of movzx */
378 8, /* "large" insn */
380 2, /* cost for loading QImode using movzbl */
381 {4, 4, 4}, /* cost of loading integer registers
382 in QImode, HImode and SImode.
383 Relative to reg-reg move (2). */
384 {2, 2, 2}, /* cost of storing integer registers */
385 2, /* cost of reg,reg fld/fst */
386 {2, 2, 6}, /* cost of loading fp registers
387 in SFmode, DFmode and XFmode */
388 {4, 4, 6}, /* cost of storing fp registers
389 in SFmode, DFmode and XFmode */
390 2, /* cost of moving MMX register */
391 {2, 2}, /* cost of loading MMX registers
392 in SImode and DImode */
393 {2, 2}, /* cost of storing MMX registers
394 in SImode and DImode */
395 2, /* cost of moving SSE register */
396 {2, 2, 8}, /* cost of loading SSE registers
397 in SImode, DImode and TImode */
398 {2, 2, 8}, /* cost of storing SSE registers
399 in SImode, DImode and TImode */
400 3, /* MMX or SSE register to integer */
401 8, /* size of l1 cache. */
402 256, /* size of l2 cache */
403 32, /* size of prefetch block */
404 6, /* number of parallel prefetches */
406 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
407 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
408 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
409 COSTS_N_INSNS (2), /* cost of FABS instruction. */
410 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
411 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
412 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
413 the alignment). For small blocks inline loop is still a noticeable win, for bigger
414 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
415 more expensive startup time in CPU, but after 4K the difference is down in the noise.
417 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
418 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
419 DUMMY_STRINGOP_ALGS},
420 {{rep_prefix_4_byte, {{1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, libcall}}},
422 DUMMY_STRINGOP_ALGS},
423 1, /* scalar_stmt_cost. */
424 1, /* scalar load_cost. */
425 1, /* scalar_store_cost. */
426 1, /* vec_stmt_cost. */
427 1, /* vec_to_scalar_cost. */
428 1, /* scalar_to_vec_cost. */
429 1, /* vec_align_load_cost. */
430 2, /* vec_unalign_load_cost. */
431 1, /* vec_store_cost. */
432 3, /* cond_taken_branch_cost. */
433 1, /* cond_not_taken_branch_cost. */
437 struct processor_costs geode_cost = {
438 COSTS_N_INSNS (1), /* cost of an add instruction */
439 COSTS_N_INSNS (1), /* cost of a lea instruction */
440 COSTS_N_INSNS (2), /* variable shift costs */
441 COSTS_N_INSNS (1), /* constant shift costs */
442 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
443 COSTS_N_INSNS (4), /* HI */
444 COSTS_N_INSNS (7), /* SI */
445 COSTS_N_INSNS (7), /* DI */
446 COSTS_N_INSNS (7)}, /* other */
447 0, /* cost of multiply per each bit set */
448 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
449 COSTS_N_INSNS (23), /* HI */
450 COSTS_N_INSNS (39), /* SI */
451 COSTS_N_INSNS (39), /* DI */
452 COSTS_N_INSNS (39)}, /* other */
453 COSTS_N_INSNS (1), /* cost of movsx */
454 COSTS_N_INSNS (1), /* cost of movzx */
455 8, /* "large" insn */
457 1, /* cost for loading QImode using movzbl */
458 {1, 1, 1}, /* cost of loading integer registers
459 in QImode, HImode and SImode.
460 Relative to reg-reg move (2). */
461 {1, 1, 1}, /* cost of storing integer registers */
462 1, /* cost of reg,reg fld/fst */
463 {1, 1, 1}, /* cost of loading fp registers
464 in SFmode, DFmode and XFmode */
465 {4, 6, 6}, /* cost of storing fp registers
466 in SFmode, DFmode and XFmode */
468 1, /* cost of moving MMX register */
469 {1, 1}, /* cost of loading MMX registers
470 in SImode and DImode */
471 {1, 1}, /* cost of storing MMX registers
472 in SImode and DImode */
473 1, /* cost of moving SSE register */
474 {1, 1, 1}, /* cost of loading SSE registers
475 in SImode, DImode and TImode */
476 {1, 1, 1}, /* cost of storing SSE registers
477 in SImode, DImode and TImode */
478 1, /* MMX or SSE register to integer */
479 64, /* size of l1 cache. */
480 128, /* size of l2 cache. */
481 32, /* size of prefetch block */
482 1, /* number of parallel prefetches */
484 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
485 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
486 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
487 COSTS_N_INSNS (1), /* cost of FABS instruction. */
488 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
489 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
490 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
491 DUMMY_STRINGOP_ALGS},
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 1, /* scalar_stmt_cost. */
495 1, /* scalar load_cost. */
496 1, /* scalar_store_cost. */
497 1, /* vec_stmt_cost. */
498 1, /* vec_to_scalar_cost. */
499 1, /* scalar_to_vec_cost. */
500 1, /* vec_align_load_cost. */
501 2, /* vec_unalign_load_cost. */
502 1, /* vec_store_cost. */
503 3, /* cond_taken_branch_cost. */
504 1, /* cond_not_taken_branch_cost. */
508 struct processor_costs k6_cost = {
509 COSTS_N_INSNS (1), /* cost of an add instruction */
510 COSTS_N_INSNS (2), /* cost of a lea instruction */
511 COSTS_N_INSNS (1), /* variable shift costs */
512 COSTS_N_INSNS (1), /* constant shift costs */
513 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
514 COSTS_N_INSNS (3), /* HI */
515 COSTS_N_INSNS (3), /* SI */
516 COSTS_N_INSNS (3), /* DI */
517 COSTS_N_INSNS (3)}, /* other */
518 0, /* cost of multiply per each bit set */
519 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
520 COSTS_N_INSNS (18), /* HI */
521 COSTS_N_INSNS (18), /* SI */
522 COSTS_N_INSNS (18), /* DI */
523 COSTS_N_INSNS (18)}, /* other */
524 COSTS_N_INSNS (2), /* cost of movsx */
525 COSTS_N_INSNS (2), /* cost of movzx */
526 8, /* "large" insn */
528 3, /* cost for loading QImode using movzbl */
529 {4, 5, 4}, /* cost of loading integer registers
530 in QImode, HImode and SImode.
531 Relative to reg-reg move (2). */
532 {2, 3, 2}, /* cost of storing integer registers */
533 4, /* cost of reg,reg fld/fst */
534 {6, 6, 6}, /* cost of loading fp registers
535 in SFmode, DFmode and XFmode */
536 {4, 4, 4}, /* cost of storing fp registers
537 in SFmode, DFmode and XFmode */
538 2, /* cost of moving MMX register */
539 {2, 2}, /* cost of loading MMX registers
540 in SImode and DImode */
541 {2, 2}, /* cost of storing MMX registers
542 in SImode and DImode */
543 2, /* cost of moving SSE register */
544 {2, 2, 8}, /* cost of loading SSE registers
545 in SImode, DImode and TImode */
546 {2, 2, 8}, /* cost of storing SSE registers
547 in SImode, DImode and TImode */
548 6, /* MMX or SSE register to integer */
549 32, /* size of l1 cache. */
550 32, /* size of l2 cache. Some models
551 have integrated l2 cache, but
552 optimizing for k6 is not important
553 enough to worry about that. */
554 32, /* size of prefetch block */
555 1, /* number of parallel prefetches */
557 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
558 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
559 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
560 COSTS_N_INSNS (2), /* cost of FABS instruction. */
561 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
562 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
563 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
564 DUMMY_STRINGOP_ALGS},
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 1, /* scalar_stmt_cost. */
568 1, /* scalar load_cost. */
569 1, /* scalar_store_cost. */
570 1, /* vec_stmt_cost. */
571 1, /* vec_to_scalar_cost. */
572 1, /* scalar_to_vec_cost. */
573 1, /* vec_align_load_cost. */
574 2, /* vec_unalign_load_cost. */
575 1, /* vec_store_cost. */
576 3, /* cond_taken_branch_cost. */
577 1, /* cond_not_taken_branch_cost. */
581 struct processor_costs athlon_cost = {
582 COSTS_N_INSNS (1), /* cost of an add instruction */
583 COSTS_N_INSNS (2), /* cost of a lea instruction */
584 COSTS_N_INSNS (1), /* variable shift costs */
585 COSTS_N_INSNS (1), /* constant shift costs */
586 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
587 COSTS_N_INSNS (5), /* HI */
588 COSTS_N_INSNS (5), /* SI */
589 COSTS_N_INSNS (5), /* DI */
590 COSTS_N_INSNS (5)}, /* other */
591 0, /* cost of multiply per each bit set */
592 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
593 COSTS_N_INSNS (26), /* HI */
594 COSTS_N_INSNS (42), /* SI */
595 COSTS_N_INSNS (74), /* DI */
596 COSTS_N_INSNS (74)}, /* other */
597 COSTS_N_INSNS (1), /* cost of movsx */
598 COSTS_N_INSNS (1), /* cost of movzx */
599 8, /* "large" insn */
601 4, /* cost for loading QImode using movzbl */
602 {3, 4, 3}, /* cost of loading integer registers
603 in QImode, HImode and SImode.
604 Relative to reg-reg move (2). */
605 {3, 4, 3}, /* cost of storing integer registers */
606 4, /* cost of reg,reg fld/fst */
607 {4, 4, 12}, /* cost of loading fp registers
608 in SFmode, DFmode and XFmode */
609 {6, 6, 8}, /* cost of storing fp registers
610 in SFmode, DFmode and XFmode */
611 2, /* cost of moving MMX register */
612 {4, 4}, /* cost of loading MMX registers
613 in SImode and DImode */
614 {4, 4}, /* cost of storing MMX registers
615 in SImode and DImode */
616 2, /* cost of moving SSE register */
617 {4, 4, 6}, /* cost of loading SSE registers
618 in SImode, DImode and TImode */
619 {4, 4, 5}, /* cost of storing SSE registers
620 in SImode, DImode and TImode */
621 5, /* MMX or SSE register to integer */
622 64, /* size of l1 cache. */
623 256, /* size of l2 cache. */
624 64, /* size of prefetch block */
625 6, /* number of parallel prefetches */
627 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
628 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
629 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
630 COSTS_N_INSNS (2), /* cost of FABS instruction. */
631 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
632 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
633 /* For some reason, Athlon deals better with REP prefix (relative to loops)
634 compared to K8. Alignment becomes important after 8 bytes for memcpy and
635 128 bytes for memset. */
636 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
637 DUMMY_STRINGOP_ALGS},
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 1, /* scalar_stmt_cost. */
641 1, /* scalar load_cost. */
642 1, /* scalar_store_cost. */
643 1, /* vec_stmt_cost. */
644 1, /* vec_to_scalar_cost. */
645 1, /* scalar_to_vec_cost. */
646 1, /* vec_align_load_cost. */
647 2, /* vec_unalign_load_cost. */
648 1, /* vec_store_cost. */
649 3, /* cond_taken_branch_cost. */
650 1, /* cond_not_taken_branch_cost. */
654 struct processor_costs k8_cost = {
655 COSTS_N_INSNS (1), /* cost of an add instruction */
656 COSTS_N_INSNS (2), /* cost of a lea instruction */
657 COSTS_N_INSNS (1), /* variable shift costs */
658 COSTS_N_INSNS (1), /* constant shift costs */
659 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
660 COSTS_N_INSNS (4), /* HI */
661 COSTS_N_INSNS (3), /* SI */
662 COSTS_N_INSNS (4), /* DI */
663 COSTS_N_INSNS (5)}, /* other */
664 0, /* cost of multiply per each bit set */
665 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
666 COSTS_N_INSNS (26), /* HI */
667 COSTS_N_INSNS (42), /* SI */
668 COSTS_N_INSNS (74), /* DI */
669 COSTS_N_INSNS (74)}, /* other */
670 COSTS_N_INSNS (1), /* cost of movsx */
671 COSTS_N_INSNS (1), /* cost of movzx */
672 8, /* "large" insn */
674 4, /* cost for loading QImode using movzbl */
675 {3, 4, 3}, /* cost of loading integer registers
676 in QImode, HImode and SImode.
677 Relative to reg-reg move (2). */
678 {3, 4, 3}, /* cost of storing integer registers */
679 4, /* cost of reg,reg fld/fst */
680 {4, 4, 12}, /* cost of loading fp registers
681 in SFmode, DFmode and XFmode */
682 {6, 6, 8}, /* cost of storing fp registers
683 in SFmode, DFmode and XFmode */
684 2, /* cost of moving MMX register */
685 {3, 3}, /* cost of loading MMX registers
686 in SImode and DImode */
687 {4, 4}, /* cost of storing MMX registers
688 in SImode and DImode */
689 2, /* cost of moving SSE register */
690 {4, 3, 6}, /* cost of loading SSE registers
691 in SImode, DImode and TImode */
692 {4, 4, 5}, /* cost of storing SSE registers
693 in SImode, DImode and TImode */
694 5, /* MMX or SSE register to integer */
695 64, /* size of l1 cache. */
696 512, /* size of l2 cache. */
697 64, /* size of prefetch block */
698 /* New AMD processors never drop prefetches; if they cannot be performed
699 immediately, they are queued. We set number of simultaneous prefetches
700 to a large constant to reflect this (it probably is not a good idea not
701 to limit number of prefetches at all, as their execution also takes some
703 100, /* number of parallel prefetches */
705 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
706 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
707 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
708 COSTS_N_INSNS (2), /* cost of FABS instruction. */
709 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
710 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
711 /* K8 has optimized REP instruction for medium sized blocks, but for very small
712 blocks it is better to use loop. For large blocks, libcall can do
713 nontemporary accesses and beat inline considerably. */
714 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
715 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
716 {{libcall, {{8, loop}, {24, unrolled_loop},
717 {2048, rep_prefix_4_byte}, {-1, libcall}}},
718 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 4, /* scalar_stmt_cost. */
720 2, /* scalar load_cost. */
721 2, /* scalar_store_cost. */
722 5, /* vec_stmt_cost. */
723 0, /* vec_to_scalar_cost. */
724 2, /* scalar_to_vec_cost. */
725 2, /* vec_align_load_cost. */
726 3, /* vec_unalign_load_cost. */
727 3, /* vec_store_cost. */
728 3, /* cond_taken_branch_cost. */
729 2, /* cond_not_taken_branch_cost. */
732 struct processor_costs amdfam10_cost = {
733 COSTS_N_INSNS (1), /* cost of an add instruction */
734 COSTS_N_INSNS (2), /* cost of a lea instruction */
735 COSTS_N_INSNS (1), /* variable shift costs */
736 COSTS_N_INSNS (1), /* constant shift costs */
737 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
738 COSTS_N_INSNS (4), /* HI */
739 COSTS_N_INSNS (3), /* SI */
740 COSTS_N_INSNS (4), /* DI */
741 COSTS_N_INSNS (5)}, /* other */
742 0, /* cost of multiply per each bit set */
743 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
744 COSTS_N_INSNS (35), /* HI */
745 COSTS_N_INSNS (51), /* SI */
746 COSTS_N_INSNS (83), /* DI */
747 COSTS_N_INSNS (83)}, /* other */
748 COSTS_N_INSNS (1), /* cost of movsx */
749 COSTS_N_INSNS (1), /* cost of movzx */
750 8, /* "large" insn */
752 4, /* cost for loading QImode using movzbl */
753 {3, 4, 3}, /* cost of loading integer registers
754 in QImode, HImode and SImode.
755 Relative to reg-reg move (2). */
756 {3, 4, 3}, /* cost of storing integer registers */
757 4, /* cost of reg,reg fld/fst */
758 {4, 4, 12}, /* cost of loading fp registers
759 in SFmode, DFmode and XFmode */
760 {6, 6, 8}, /* cost of storing fp registers
761 in SFmode, DFmode and XFmode */
762 2, /* cost of moving MMX register */
763 {3, 3}, /* cost of loading MMX registers
764 in SImode and DImode */
765 {4, 4}, /* cost of storing MMX registers
766 in SImode and DImode */
767 2, /* cost of moving SSE register */
768 {4, 4, 3}, /* cost of loading SSE registers
769 in SImode, DImode and TImode */
770 {4, 4, 5}, /* cost of storing SSE registers
771 in SImode, DImode and TImode */
772 3, /* MMX or SSE register to integer */
774 MOVD reg64, xmmreg Double FSTORE 4
775 MOVD reg32, xmmreg Double FSTORE 4
777 MOVD reg64, xmmreg Double FADD 3
779 MOVD reg32, xmmreg Double FADD 3
781 64, /* size of l1 cache. */
782 512, /* size of l2 cache. */
783 64, /* size of prefetch block */
784 /* New AMD processors never drop prefetches; if they cannot be performed
785 immediately, they are queued. We set number of simultaneous prefetches
786 to a large constant to reflect this (it probably is not a good idea not
787 to limit number of prefetches at all, as their execution also takes some
789 100, /* number of parallel prefetches */
791 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
792 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
793 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
794 COSTS_N_INSNS (2), /* cost of FABS instruction. */
795 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
796 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
798 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
799 very small blocks it is better to use loop. For large blocks, libcall can
800 do nontemporary accesses and beat inline considerably. */
801 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
802 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
803 {{libcall, {{8, loop}, {24, unrolled_loop},
804 {2048, rep_prefix_4_byte}, {-1, libcall}}},
805 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 4, /* scalar_stmt_cost. */
807 2, /* scalar load_cost. */
808 2, /* scalar_store_cost. */
809 6, /* vec_stmt_cost. */
810 0, /* vec_to_scalar_cost. */
811 2, /* scalar_to_vec_cost. */
812 2, /* vec_align_load_cost. */
813 2, /* vec_unalign_load_cost. */
814 2, /* vec_store_cost. */
815 2, /* cond_taken_branch_cost. */
816 1, /* cond_not_taken_branch_cost. */
820 struct processor_costs pentium4_cost = {
821 COSTS_N_INSNS (1), /* cost of an add instruction */
822 COSTS_N_INSNS (3), /* cost of a lea instruction */
823 COSTS_N_INSNS (4), /* variable shift costs */
824 COSTS_N_INSNS (4), /* constant shift costs */
825 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
826 COSTS_N_INSNS (15), /* HI */
827 COSTS_N_INSNS (15), /* SI */
828 COSTS_N_INSNS (15), /* DI */
829 COSTS_N_INSNS (15)}, /* other */
830 0, /* cost of multiply per each bit set */
831 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
832 COSTS_N_INSNS (56), /* HI */
833 COSTS_N_INSNS (56), /* SI */
834 COSTS_N_INSNS (56), /* DI */
835 COSTS_N_INSNS (56)}, /* other */
836 COSTS_N_INSNS (1), /* cost of movsx */
837 COSTS_N_INSNS (1), /* cost of movzx */
838 16, /* "large" insn */
840 2, /* cost for loading QImode using movzbl */
841 {4, 5, 4}, /* cost of loading integer registers
842 in QImode, HImode and SImode.
843 Relative to reg-reg move (2). */
844 {2, 3, 2}, /* cost of storing integer registers */
845 2, /* cost of reg,reg fld/fst */
846 {2, 2, 6}, /* cost of loading fp registers
847 in SFmode, DFmode and XFmode */
848 {4, 4, 6}, /* cost of storing fp registers
849 in SFmode, DFmode and XFmode */
850 2, /* cost of moving MMX register */
851 {2, 2}, /* cost of loading MMX registers
852 in SImode and DImode */
853 {2, 2}, /* cost of storing MMX registers
854 in SImode and DImode */
855 12, /* cost of moving SSE register */
856 {12, 12, 12}, /* cost of loading SSE registers
857 in SImode, DImode and TImode */
858 {2, 2, 8}, /* cost of storing SSE registers
859 in SImode, DImode and TImode */
860 10, /* MMX or SSE register to integer */
861 8, /* size of l1 cache. */
862 256, /* size of l2 cache. */
863 64, /* size of prefetch block */
864 6, /* number of parallel prefetches */
866 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
867 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
868 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
869 COSTS_N_INSNS (2), /* cost of FABS instruction. */
870 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
871 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
872 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
873 DUMMY_STRINGOP_ALGS},
874 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
876 DUMMY_STRINGOP_ALGS},
877 1, /* scalar_stmt_cost. */
878 1, /* scalar load_cost. */
879 1, /* scalar_store_cost. */
880 1, /* vec_stmt_cost. */
881 1, /* vec_to_scalar_cost. */
882 1, /* scalar_to_vec_cost. */
883 1, /* vec_align_load_cost. */
884 2, /* vec_unalign_load_cost. */
885 1, /* vec_store_cost. */
886 3, /* cond_taken_branch_cost. */
887 1, /* cond_not_taken_branch_cost. */
891 struct processor_costs nocona_cost = {
892 COSTS_N_INSNS (1), /* cost of an add instruction */
893 COSTS_N_INSNS (1), /* cost of a lea instruction */
894 COSTS_N_INSNS (1), /* variable shift costs */
895 COSTS_N_INSNS (1), /* constant shift costs */
896 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
897 COSTS_N_INSNS (10), /* HI */
898 COSTS_N_INSNS (10), /* SI */
899 COSTS_N_INSNS (10), /* DI */
900 COSTS_N_INSNS (10)}, /* other */
901 0, /* cost of multiply per each bit set */
902 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
903 COSTS_N_INSNS (66), /* HI */
904 COSTS_N_INSNS (66), /* SI */
905 COSTS_N_INSNS (66), /* DI */
906 COSTS_N_INSNS (66)}, /* other */
907 COSTS_N_INSNS (1), /* cost of movsx */
908 COSTS_N_INSNS (1), /* cost of movzx */
909 16, /* "large" insn */
911 4, /* cost for loading QImode using movzbl */
912 {4, 4, 4}, /* cost of loading integer registers
913 in QImode, HImode and SImode.
914 Relative to reg-reg move (2). */
915 {4, 4, 4}, /* cost of storing integer registers */
916 3, /* cost of reg,reg fld/fst */
917 {12, 12, 12}, /* cost of loading fp registers
918 in SFmode, DFmode and XFmode */
919 {4, 4, 4}, /* cost of storing fp registers
920 in SFmode, DFmode and XFmode */
921 6, /* cost of moving MMX register */
922 {12, 12}, /* cost of loading MMX registers
923 in SImode and DImode */
924 {12, 12}, /* cost of storing MMX registers
925 in SImode and DImode */
926 6, /* cost of moving SSE register */
927 {12, 12, 12}, /* cost of loading SSE registers
928 in SImode, DImode and TImode */
929 {12, 12, 12}, /* cost of storing SSE registers
930 in SImode, DImode and TImode */
931 8, /* MMX or SSE register to integer */
932 8, /* size of l1 cache. */
933 1024, /* size of l2 cache. */
934 128, /* size of prefetch block */
935 8, /* number of parallel prefetches */
937 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
938 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
939 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
940 COSTS_N_INSNS (3), /* cost of FABS instruction. */
941 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
942 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
943 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
944 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
945 {100000, unrolled_loop}, {-1, libcall}}}},
946 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
948 {libcall, {{24, loop}, {64, unrolled_loop},
949 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
950 1, /* scalar_stmt_cost. */
951 1, /* scalar load_cost. */
952 1, /* scalar_store_cost. */
953 1, /* vec_stmt_cost. */
954 1, /* vec_to_scalar_cost. */
955 1, /* scalar_to_vec_cost. */
956 1, /* vec_align_load_cost. */
957 2, /* vec_unalign_load_cost. */
958 1, /* vec_store_cost. */
959 3, /* cond_taken_branch_cost. */
960 1, /* cond_not_taken_branch_cost. */
964 struct processor_costs core2_cost = {
965 COSTS_N_INSNS (1), /* cost of an add instruction */
966 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
967 COSTS_N_INSNS (1), /* variable shift costs */
968 COSTS_N_INSNS (1), /* constant shift costs */
969 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
970 COSTS_N_INSNS (3), /* HI */
971 COSTS_N_INSNS (3), /* SI */
972 COSTS_N_INSNS (3), /* DI */
973 COSTS_N_INSNS (3)}, /* other */
974 0, /* cost of multiply per each bit set */
975 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
976 COSTS_N_INSNS (22), /* HI */
977 COSTS_N_INSNS (22), /* SI */
978 COSTS_N_INSNS (22), /* DI */
979 COSTS_N_INSNS (22)}, /* other */
980 COSTS_N_INSNS (1), /* cost of movsx */
981 COSTS_N_INSNS (1), /* cost of movzx */
982 8, /* "large" insn */
984 2, /* cost for loading QImode using movzbl */
985 {6, 6, 6}, /* cost of loading integer registers
986 in QImode, HImode and SImode.
987 Relative to reg-reg move (2). */
988 {4, 4, 4}, /* cost of storing integer registers */
989 2, /* cost of reg,reg fld/fst */
990 {6, 6, 6}, /* cost of loading fp registers
991 in SFmode, DFmode and XFmode */
992 {4, 4, 4}, /* cost of loading integer registers */
993 2, /* cost of moving MMX register */
994 {6, 6}, /* cost of loading MMX registers
995 in SImode and DImode */
996 {4, 4}, /* cost of storing MMX registers
997 in SImode and DImode */
998 2, /* cost of moving SSE register */
999 {6, 6, 6}, /* cost of loading SSE registers
1000 in SImode, DImode and TImode */
1001 {4, 4, 4}, /* cost of storing SSE registers
1002 in SImode, DImode and TImode */
1003 2, /* MMX or SSE register to integer */
1004 32, /* size of l1 cache. */
1005 2048, /* size of l2 cache. */
1006 128, /* size of prefetch block */
1007 8, /* number of parallel prefetches */
1008 3, /* Branch cost */
1009 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1010 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1011 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1012 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1013 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1014 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1015 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1016 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1017 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1018 {{libcall, {{8, loop}, {15, unrolled_loop},
1019 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1020 {libcall, {{24, loop}, {32, unrolled_loop},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 1, /* scalar_stmt_cost. */
1023 1, /* scalar load_cost. */
1024 1, /* scalar_store_cost. */
1025 1, /* vec_stmt_cost. */
1026 1, /* vec_to_scalar_cost. */
1027 1, /* scalar_to_vec_cost. */
1028 1, /* vec_align_load_cost. */
1029 2, /* vec_unalign_load_cost. */
1030 1, /* vec_store_cost. */
1031 3, /* cond_taken_branch_cost. */
1032 1, /* cond_not_taken_branch_cost. */
1035 /* Generic64 should produce code tuned for Nocona and K8. */
1037 struct processor_costs generic64_cost = {
1038 COSTS_N_INSNS (1), /* cost of an add instruction */
1039 /* On all chips taken into consideration lea is 2 cycles and more. With
1040 this cost however our current implementation of synth_mult results in
1041 use of unnecessary temporary registers causing regression on several
1042 SPECfp benchmarks. */
1043 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1044 COSTS_N_INSNS (1), /* variable shift costs */
1045 COSTS_N_INSNS (1), /* constant shift costs */
1046 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1047 COSTS_N_INSNS (4), /* HI */
1048 COSTS_N_INSNS (3), /* SI */
1049 COSTS_N_INSNS (4), /* DI */
1050 COSTS_N_INSNS (2)}, /* other */
1051 0, /* cost of multiply per each bit set */
1052 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1053 COSTS_N_INSNS (26), /* HI */
1054 COSTS_N_INSNS (42), /* SI */
1055 COSTS_N_INSNS (74), /* DI */
1056 COSTS_N_INSNS (74)}, /* other */
1057 COSTS_N_INSNS (1), /* cost of movsx */
1058 COSTS_N_INSNS (1), /* cost of movzx */
1059 8, /* "large" insn */
1060 17, /* MOVE_RATIO */
1061 4, /* cost for loading QImode using movzbl */
1062 {4, 4, 4}, /* cost of loading integer registers
1063 in QImode, HImode and SImode.
1064 Relative to reg-reg move (2). */
1065 {4, 4, 4}, /* cost of storing integer registers */
1066 4, /* cost of reg,reg fld/fst */
1067 {12, 12, 12}, /* cost of loading fp registers
1068 in SFmode, DFmode and XFmode */
1069 {6, 6, 8}, /* cost of storing fp registers
1070 in SFmode, DFmode and XFmode */
1071 2, /* cost of moving MMX register */
1072 {8, 8}, /* cost of loading MMX registers
1073 in SImode and DImode */
1074 {8, 8}, /* cost of storing MMX registers
1075 in SImode and DImode */
1076 2, /* cost of moving SSE register */
1077 {8, 8, 8}, /* cost of loading SSE registers
1078 in SImode, DImode and TImode */
1079 {8, 8, 8}, /* cost of storing SSE registers
1080 in SImode, DImode and TImode */
1081 5, /* MMX or SSE register to integer */
1082 32, /* size of l1 cache. */
1083 512, /* size of l2 cache. */
1084 64, /* size of prefetch block */
1085 6, /* number of parallel prefetches */
1086 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1087 is increased to perhaps more appropriate value of 5. */
1088 3, /* Branch cost */
1089 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1090 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1091 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1092 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1093 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1094 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1095 {DUMMY_STRINGOP_ALGS,
1096 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 1, /* scalar_stmt_cost. */
1100 1, /* scalar load_cost. */
1101 1, /* scalar_store_cost. */
1102 1, /* vec_stmt_cost. */
1103 1, /* vec_to_scalar_cost. */
1104 1, /* scalar_to_vec_cost. */
1105 1, /* vec_align_load_cost. */
1106 2, /* vec_unalign_load_cost. */
1107 1, /* vec_store_cost. */
1108 3, /* cond_taken_branch_cost. */
1109 1, /* cond_not_taken_branch_cost. */
1112 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1114 struct processor_costs generic32_cost = {
1115 COSTS_N_INSNS (1), /* cost of an add instruction */
1116 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1117 COSTS_N_INSNS (1), /* variable shift costs */
1118 COSTS_N_INSNS (1), /* constant shift costs */
1119 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1120 COSTS_N_INSNS (4), /* HI */
1121 COSTS_N_INSNS (3), /* SI */
1122 COSTS_N_INSNS (4), /* DI */
1123 COSTS_N_INSNS (2)}, /* other */
1124 0, /* cost of multiply per each bit set */
1125 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1126 COSTS_N_INSNS (26), /* HI */
1127 COSTS_N_INSNS (42), /* SI */
1128 COSTS_N_INSNS (74), /* DI */
1129 COSTS_N_INSNS (74)}, /* other */
1130 COSTS_N_INSNS (1), /* cost of movsx */
1131 COSTS_N_INSNS (1), /* cost of movzx */
1132 8, /* "large" insn */
1133 17, /* MOVE_RATIO */
1134 4, /* cost for loading QImode using movzbl */
1135 {4, 4, 4}, /* cost of loading integer registers
1136 in QImode, HImode and SImode.
1137 Relative to reg-reg move (2). */
1138 {4, 4, 4}, /* cost of storing integer registers */
1139 4, /* cost of reg,reg fld/fst */
1140 {12, 12, 12}, /* cost of loading fp registers
1141 in SFmode, DFmode and XFmode */
1142 {6, 6, 8}, /* cost of storing fp registers
1143 in SFmode, DFmode and XFmode */
1144 2, /* cost of moving MMX register */
1145 {8, 8}, /* cost of loading MMX registers
1146 in SImode and DImode */
1147 {8, 8}, /* cost of storing MMX registers
1148 in SImode and DImode */
1149 2, /* cost of moving SSE register */
1150 {8, 8, 8}, /* cost of loading SSE registers
1151 in SImode, DImode and TImode */
1152 {8, 8, 8}, /* cost of storing SSE registers
1153 in SImode, DImode and TImode */
1154 5, /* MMX or SSE register to integer */
1155 32, /* size of l1 cache. */
1156 256, /* size of l2 cache. */
1157 64, /* size of prefetch block */
1158 6, /* number of parallel prefetches */
1159 3, /* Branch cost */
1160 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1161 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1162 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1163 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1164 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1165 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1166 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1167 DUMMY_STRINGOP_ALGS},
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 1, /* scalar_stmt_cost. */
1171 1, /* scalar load_cost. */
1172 1, /* scalar_store_cost. */
1173 1, /* vec_stmt_cost. */
1174 1, /* vec_to_scalar_cost. */
1175 1, /* scalar_to_vec_cost. */
1176 1, /* vec_align_load_cost. */
1177 2, /* vec_unalign_load_cost. */
1178 1, /* vec_store_cost. */
1179 3, /* cond_taken_branch_cost. */
1180 1, /* cond_not_taken_branch_cost. */
1183 const struct processor_costs *ix86_cost = &pentium_cost;
1185 /* Processor feature/optimization bitmasks. */
1186 #define m_386 (1<<PROCESSOR_I386)
1187 #define m_486 (1<<PROCESSOR_I486)
1188 #define m_PENT (1<<PROCESSOR_PENTIUM)
1189 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1190 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1191 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1192 #define m_CORE2 (1<<PROCESSOR_CORE2)
1194 #define m_GEODE (1<<PROCESSOR_GEODE)
1195 #define m_K6 (1<<PROCESSOR_K6)
1196 #define m_K6_GEODE (m_K6 | m_GEODE)
1197 #define m_K8 (1<<PROCESSOR_K8)
1198 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1199 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1200 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1201 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1203 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1204 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1206 /* Generic instruction choice should be common subset of supported CPUs
1207 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1208 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1210 /* Feature tests against the various tunings. */
1211 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1212 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1213 negatively, so enabling for Generic64 seems like good code size
1214 tradeoff. We can't enable it for 32bit generic because it does not
1215 work well with PPro base chips. */
1216 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1218 /* X86_TUNE_PUSH_MEMORY */
1219 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1220 | m_NOCONA | m_CORE2 | m_GENERIC,
1222 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1225 /* X86_TUNE_USE_BIT_TEST */
1228 /* X86_TUNE_UNROLL_STRLEN */
1229 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1231 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1232 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1234 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1235 on simulation result. But after P4 was made, no performance benefit
1236 was observed with branch hints. It also increases the code size.
1237 As a result, icc never generates branch hints. */
1240 /* X86_TUNE_DOUBLE_WITH_ADD */
1243 /* X86_TUNE_USE_SAHF */
1244 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1245 | m_NOCONA | m_CORE2 | m_GENERIC,
1247 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1248 partial dependencies. */
1249 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1250 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1252 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1253 register stalls on Generic32 compilation setting as well. However
1254 in current implementation the partial register stalls are not eliminated
1255 very well - they can be introduced via subregs synthesized by combine
1256 and can happen in caller/callee saving sequences. Because this option
1257 pays back little on PPro based chips and is in conflict with partial reg
1258 dependencies used by Athlon/P4 based chips, it is better to leave it off
1259 for generic32 for now. */
1262 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1263 m_CORE2 | m_GENERIC,
1265 /* X86_TUNE_USE_HIMODE_FIOP */
1266 m_386 | m_486 | m_K6_GEODE,
1268 /* X86_TUNE_USE_SIMODE_FIOP */
1269 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1271 /* X86_TUNE_USE_MOV0 */
1274 /* X86_TUNE_USE_CLTD */
1275 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1277 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1280 /* X86_TUNE_SPLIT_LONG_MOVES */
1283 /* X86_TUNE_READ_MODIFY_WRITE */
1286 /* X86_TUNE_READ_MODIFY */
1289 /* X86_TUNE_PROMOTE_QIMODE */
1290 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1291 | m_GENERIC /* | m_PENT4 ? */,
1293 /* X86_TUNE_FAST_PREFIX */
1294 ~(m_PENT | m_486 | m_386),
1296 /* X86_TUNE_SINGLE_STRINGOP */
1297 m_386 | m_PENT4 | m_NOCONA,
1299 /* X86_TUNE_QIMODE_MATH */
1302 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1303 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1304 might be considered for Generic32 if our scheme for avoiding partial
1305 stalls was more effective. */
1308 /* X86_TUNE_PROMOTE_QI_REGS */
1311 /* X86_TUNE_PROMOTE_HI_REGS */
1314 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1315 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1317 /* X86_TUNE_ADD_ESP_8 */
1318 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1319 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1321 /* X86_TUNE_SUB_ESP_4 */
1322 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1324 /* X86_TUNE_SUB_ESP_8 */
1325 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1326 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1328 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1329 for DFmode copies */
1330 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1331 | m_GENERIC | m_GEODE),
1333 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1334 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1336 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1337 conflict here in between PPro/Pentium4 based chips that thread 128bit
1338 SSE registers as single units versus K8 based chips that divide SSE
1339 registers to two 64bit halves. This knob promotes all store destinations
1340 to be 128bit to allow register renaming on 128bit SSE units, but usually
1341 results in one extra microop on 64bit SSE units. Experimental results
1342 shows that disabling this option on P4 brings over 20% SPECfp regression,
1343 while enabling it on K8 brings roughly 2.4% regression that can be partly
1344 masked by careful scheduling of moves. */
1345 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1347 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1350 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1351 are resolved on SSE register parts instead of whole registers, so we may
1352 maintain just lower part of scalar values in proper format leaving the
1353 upper part undefined. */
1356 /* X86_TUNE_SSE_TYPELESS_STORES */
1359 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1360 m_PPRO | m_PENT4 | m_NOCONA,
1362 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1363 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1365 /* X86_TUNE_PROLOGUE_USING_MOVE */
1366 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1368 /* X86_TUNE_EPILOGUE_USING_MOVE */
1369 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1371 /* X86_TUNE_SHIFT1 */
1374 /* X86_TUNE_USE_FFREEP */
1377 /* X86_TUNE_INTER_UNIT_MOVES */
1378 ~(m_AMD_MULTIPLE | m_GENERIC),
1380 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1383 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1384 than 4 branch instructions in the 16 byte window. */
1385 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1387 /* X86_TUNE_SCHEDULE */
1388 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1390 /* X86_TUNE_USE_BT */
1393 /* X86_TUNE_USE_INCDEC */
1394 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1396 /* X86_TUNE_PAD_RETURNS */
1397 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1399 /* X86_TUNE_EXT_80387_CONSTANTS */
1400 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1402 /* X86_TUNE_SHORTEN_X87_SSE */
1405 /* X86_TUNE_AVOID_VECTOR_DECODE */
1408 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1409 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1412 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1413 vector path on AMD machines. */
1414 m_K8 | m_GENERIC64 | m_AMDFAM10,
1416 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1418 m_K8 | m_GENERIC64 | m_AMDFAM10,
1420 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1424 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1425 but one byte longer. */
1428 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1429 operand that cannot be represented using a modRM byte. The XOR
1430 replacement is long decoded, so this split helps here as well. */
1433 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1434 from integer to FP. */
1438 /* Feature tests against the various architecture variations. */
1439 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1440 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1441 ~(m_386 | m_486 | m_PENT | m_K6),
1443 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1446 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1449 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1452 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1456 static const unsigned int x86_accumulate_outgoing_args
1457 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1459 static const unsigned int x86_arch_always_fancy_math_387
1460 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1461 | m_NOCONA | m_CORE2 | m_GENERIC;
1463 static enum stringop_alg stringop_alg = no_stringop;
1465 /* In case the average insn count for single function invocation is
1466 lower than this constant, emit fast (but longer) prologue and
1468 #define FAST_PROLOGUE_INSN_COUNT 20
1470 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1471 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1472 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1473 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1475 /* Array of the smallest class containing reg number REGNO, indexed by
1476 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1478 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1480 /* ax, dx, cx, bx */
1481 AREG, DREG, CREG, BREG,
1482 /* si, di, bp, sp */
1483 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1485 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1486 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1489 /* flags, fpsr, fpcr, frame */
1490 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1492 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1495 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1498 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1499 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1500 /* SSE REX registers */
1501 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1505 /* The "default" register map used in 32bit mode. */
1507 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1509 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1510 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1511 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1512 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1513 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1514 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1515 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1518 static int const x86_64_int_parameter_registers[6] =
1520 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1521 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1524 static int const x86_64_ms_abi_int_parameter_registers[4] =
1526 2 /*RCX*/, 1 /*RDX*/,
1527 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1530 static int const x86_64_int_return_registers[4] =
1532 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1535 /* The "default" register map used in 64bit mode. */
1536 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1538 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1539 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1540 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1541 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1542 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1543 8,9,10,11,12,13,14,15, /* extended integer registers */
1544 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1547 /* Define the register numbers to be used in Dwarf debugging information.
1548 The SVR4 reference port C compiler uses the following register numbers
1549 in its Dwarf output code:
1550 0 for %eax (gcc regno = 0)
1551 1 for %ecx (gcc regno = 2)
1552 2 for %edx (gcc regno = 1)
1553 3 for %ebx (gcc regno = 3)
1554 4 for %esp (gcc regno = 7)
1555 5 for %ebp (gcc regno = 6)
1556 6 for %esi (gcc regno = 4)
1557 7 for %edi (gcc regno = 5)
1558 The following three DWARF register numbers are never generated by
1559 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1560 believes these numbers have these meanings.
1561 8 for %eip (no gcc equivalent)
1562 9 for %eflags (gcc regno = 17)
1563 10 for %trapno (no gcc equivalent)
1564 It is not at all clear how we should number the FP stack registers
1565 for the x86 architecture. If the version of SDB on x86/svr4 were
1566 a bit less brain dead with respect to floating-point then we would
1567 have a precedent to follow with respect to DWARF register numbers
1568 for x86 FP registers, but the SDB on x86/svr4 is so completely
1569 broken with respect to FP registers that it is hardly worth thinking
1570 of it as something to strive for compatibility with.
1571 The version of x86/svr4 SDB I have at the moment does (partially)
1572 seem to believe that DWARF register number 11 is associated with
1573 the x86 register %st(0), but that's about all. Higher DWARF
1574 register numbers don't seem to be associated with anything in
1575 particular, and even for DWARF regno 11, SDB only seems to under-
1576 stand that it should say that a variable lives in %st(0) (when
1577 asked via an `=' command) if we said it was in DWARF regno 11,
1578 but SDB still prints garbage when asked for the value of the
1579 variable in question (via a `/' command).
1580 (Also note that the labels SDB prints for various FP stack regs
1581 when doing an `x' command are all wrong.)
1582 Note that these problems generally don't affect the native SVR4
1583 C compiler because it doesn't allow the use of -O with -g and
1584 because when it is *not* optimizing, it allocates a memory
1585 location for each floating-point variable, and the memory
1586 location is what gets described in the DWARF AT_location
1587 attribute for the variable in question.
1588 Regardless of the severe mental illness of the x86/svr4 SDB, we
1589 do something sensible here and we use the following DWARF
1590 register numbers. Note that these are all stack-top-relative
1592 11 for %st(0) (gcc regno = 8)
1593 12 for %st(1) (gcc regno = 9)
1594 13 for %st(2) (gcc regno = 10)
1595 14 for %st(3) (gcc regno = 11)
1596 15 for %st(4) (gcc regno = 12)
1597 16 for %st(5) (gcc regno = 13)
1598 17 for %st(6) (gcc regno = 14)
1599 18 for %st(7) (gcc regno = 15)
1601 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1603 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1604 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1605 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1606 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1607 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1608 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1609 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1612 /* Test and compare insns in i386.md store the information needed to
1613 generate branch and scc insns here. */
1615 rtx ix86_compare_op0 = NULL_RTX;
1616 rtx ix86_compare_op1 = NULL_RTX;
1617 rtx ix86_compare_emitted = NULL_RTX;
1619 /* Size of the register save area. */
1620 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1622 /* Define the structure for the machine field in struct function. */
1624 struct stack_local_entry GTY(())
1626 unsigned short mode;
1629 struct stack_local_entry *next;
1632 /* Structure describing stack frame layout.
1633 Stack grows downward:
1639 saved frame pointer if frame_pointer_needed
1640 <- HARD_FRAME_POINTER
1645 [va_arg registers] (
1646 > to_allocate <- FRAME_POINTER
1656 HOST_WIDE_INT frame;
1658 int outgoing_arguments_size;
1661 HOST_WIDE_INT to_allocate;
1662 /* The offsets relative to ARG_POINTER. */
1663 HOST_WIDE_INT frame_pointer_offset;
1664 HOST_WIDE_INT hard_frame_pointer_offset;
1665 HOST_WIDE_INT stack_pointer_offset;
1667 /* When save_regs_using_mov is set, emit prologue using
1668 move instead of push instructions. */
1669 bool save_regs_using_mov;
1672 /* Code model option. */
1673 enum cmodel ix86_cmodel;
1675 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1677 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1679 /* Which unit we are generating floating point math for. */
1680 enum fpmath_unit ix86_fpmath;
1682 /* Which cpu are we scheduling for. */
1683 enum processor_type ix86_tune;
1685 /* Which instruction set architecture to use. */
1686 enum processor_type ix86_arch;
1688 /* true if sse prefetch instruction is not NOOP. */
1689 int x86_prefetch_sse;
1691 /* ix86_regparm_string as a number */
1692 static int ix86_regparm;
1694 /* -mstackrealign option */
1695 extern int ix86_force_align_arg_pointer;
1696 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1698 /* Preferred alignment for stack boundary in bits. */
1699 unsigned int ix86_preferred_stack_boundary;
1701 /* Values 1-5: see jump.c */
1702 int ix86_branch_cost;
1704 /* Variables which are this size or smaller are put in the data/bss
1705 or ldata/lbss sections. */
1707 int ix86_section_threshold = 65536;
1709 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1710 char internal_label_prefix[16];
1711 int internal_label_prefix_len;
1713 /* Fence to use after loop using movnt. */
1716 /* Register class used for passing given 64bit part of the argument.
1717 These represent classes as documented by the PS ABI, with the exception
1718 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1719 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1721 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1722 whenever possible (upper half does contain padding). */
1723 enum x86_64_reg_class
1726 X86_64_INTEGER_CLASS,
1727 X86_64_INTEGERSI_CLASS,
1734 X86_64_COMPLEX_X87_CLASS,
1737 static const char * const x86_64_reg_class_name[] =
1739 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1740 "sseup", "x87", "x87up", "cplx87", "no"
1743 #define MAX_CLASSES 4
1745 /* Table of constants used by fldpi, fldln2, etc.... */
1746 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1747 static bool ext_80387_constants_init = 0;
1750 static struct machine_function * ix86_init_machine_status (void);
1751 static rtx ix86_function_value (const_tree, const_tree, bool);
1752 static int ix86_function_regparm (const_tree, const_tree);
1753 static void ix86_compute_frame_layout (struct ix86_frame *);
1754 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1758 /* The svr4 ABI for the i386 says that records and unions are returned
1760 #ifndef DEFAULT_PCC_STRUCT_RETURN
1761 #define DEFAULT_PCC_STRUCT_RETURN 1
1764 /* Bit flags that specify the ISA we are compiling for. */
1765 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1767 /* A mask of ix86_isa_flags that includes bit X if X
1768 was set or cleared on the command line. */
1769 static int ix86_isa_flags_explicit;
1771 /* Define a set of ISAs which are available when a given ISA is
1772 enabled. MMX and SSE ISAs are handled separately. */
1774 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1775 #define OPTION_MASK_ISA_3DNOW_SET \
1776 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1778 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1779 #define OPTION_MASK_ISA_SSE2_SET \
1780 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1781 #define OPTION_MASK_ISA_SSE3_SET \
1782 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1783 #define OPTION_MASK_ISA_SSSE3_SET \
1784 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1785 #define OPTION_MASK_ISA_SSE4_1_SET \
1786 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1787 #define OPTION_MASK_ISA_SSE4_2_SET \
1788 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1790 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1792 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1794 #define OPTION_MASK_ISA_SSE4A_SET \
1795 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1796 #define OPTION_MASK_ISA_SSE5_SET \
1797 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1799 /* Define a set of ISAs which aren't available when a given ISA is
1800 disabled. MMX and SSE ISAs are handled separately. */
1802 #define OPTION_MASK_ISA_MMX_UNSET \
1803 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1804 #define OPTION_MASK_ISA_3DNOW_UNSET \
1805 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1806 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1808 #define OPTION_MASK_ISA_SSE_UNSET \
1809 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1810 #define OPTION_MASK_ISA_SSE2_UNSET \
1811 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1812 #define OPTION_MASK_ISA_SSE3_UNSET \
1813 (OPTION_MASK_ISA_SSE3 \
1814 | OPTION_MASK_ISA_SSSE3_UNSET \
1815 | OPTION_MASK_ISA_SSE4A_UNSET )
1816 #define OPTION_MASK_ISA_SSSE3_UNSET \
1817 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1818 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1819 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1820 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1822 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1824 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1826 #define OPTION_MASK_ISA_SSE4A_UNSET \
1827 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1829 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1831 /* Vectorization library interface and handlers. */
1832 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1833 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1835 /* Implement TARGET_HANDLE_OPTION. */
1838 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1845 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1846 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1850 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1851 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1858 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1859 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1863 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1864 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1874 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1875 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1879 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1880 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1887 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1888 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1892 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1893 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1900 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1901 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1905 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1906 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1913 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1914 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1918 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1919 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1926 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1927 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1931 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1932 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1939 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1940 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1944 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1945 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1950 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1951 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1955 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1956 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1962 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1963 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1967 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1968 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1975 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1976 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1980 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1981 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1990 /* Sometimes certain combinations of command options do not make
1991 sense on a particular target machine. You can define a macro
1992 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1993 defined, is executed once just after all the command options have
1996 Don't use this macro to turn on various extra optimizations for
1997 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2000 override_options (void)
2003 int ix86_tune_defaulted = 0;
2004 int ix86_arch_specified = 0;
2005 unsigned int ix86_arch_mask, ix86_tune_mask;
2007 /* Comes from final.c -- no real reason to change it. */
2008 #define MAX_CODE_ALIGN 16
2012 const struct processor_costs *cost; /* Processor costs */
2013 const int align_loop; /* Default alignments. */
2014 const int align_loop_max_skip;
2015 const int align_jump;
2016 const int align_jump_max_skip;
2017 const int align_func;
2019 const processor_target_table[PROCESSOR_max] =
2021 {&i386_cost, 4, 3, 4, 3, 4},
2022 {&i486_cost, 16, 15, 16, 15, 16},
2023 {&pentium_cost, 16, 7, 16, 7, 16},
2024 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2025 {&geode_cost, 0, 0, 0, 0, 0},
2026 {&k6_cost, 32, 7, 32, 7, 32},
2027 {&athlon_cost, 16, 7, 16, 7, 16},
2028 {&pentium4_cost, 0, 0, 0, 0, 0},
2029 {&k8_cost, 16, 7, 16, 7, 16},
2030 {&nocona_cost, 0, 0, 0, 0, 0},
2031 {&core2_cost, 16, 10, 16, 10, 16},
2032 {&generic32_cost, 16, 7, 16, 7, 16},
2033 {&generic64_cost, 16, 10, 16, 10, 16},
2034 {&amdfam10_cost, 32, 24, 32, 7, 32}
2037 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2068 PTA_PREFETCH_SSE = 1 << 4,
2070 PTA_3DNOW_A = 1 << 6,
2074 PTA_POPCNT = 1 << 10,
2076 PTA_SSE4A = 1 << 12,
2077 PTA_NO_SAHF = 1 << 13,
2078 PTA_SSE4_1 = 1 << 14,
2079 PTA_SSE4_2 = 1 << 15,
2085 const char *const name; /* processor name or nickname. */
2086 const enum processor_type processor;
2087 const unsigned /*enum pta_flags*/ flags;
2089 const processor_alias_table[] =
2091 {"i386", PROCESSOR_I386, 0},
2092 {"i486", PROCESSOR_I486, 0},
2093 {"i586", PROCESSOR_PENTIUM, 0},
2094 {"pentium", PROCESSOR_PENTIUM, 0},
2095 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2096 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2097 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2098 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2099 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2100 {"i686", PROCESSOR_PENTIUMPRO, 0},
2101 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2102 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2103 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2104 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2105 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2106 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2107 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2108 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2109 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2110 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2111 | PTA_CX16 | PTA_NO_SAHF)},
2112 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2113 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2116 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2117 |PTA_PREFETCH_SSE)},
2118 {"k6", PROCESSOR_K6, PTA_MMX},
2119 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2120 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2121 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2122 | PTA_PREFETCH_SSE)},
2123 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2124 | PTA_PREFETCH_SSE)},
2125 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2127 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2129 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2131 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2132 | PTA_MMX | PTA_SSE | PTA_SSE2
2134 {"k8", PROCESSOR_K8, (PTA_64BIT
2135 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2136 | PTA_SSE | PTA_SSE2
2138 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2139 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2140 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2142 {"opteron", PROCESSOR_K8, (PTA_64BIT
2143 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2144 | PTA_SSE | PTA_SSE2
2146 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2147 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2148 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2150 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2151 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2152 | PTA_SSE | PTA_SSE2
2154 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2155 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2156 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2158 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2159 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2160 | PTA_SSE | PTA_SSE2
2162 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2163 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2164 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2166 | PTA_CX16 | PTA_ABM)},
2167 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2168 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2169 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2171 | PTA_CX16 | PTA_ABM)},
2172 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2173 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2176 int const pta_size = ARRAY_SIZE (processor_alias_table);
2178 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2179 SUBTARGET_OVERRIDE_OPTIONS;
2182 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2183 SUBSUBTARGET_OVERRIDE_OPTIONS;
2186 /* -fPIC is the default for x86_64. */
2187 if (TARGET_MACHO && TARGET_64BIT)
2190 /* Set the default values for switches whose default depends on TARGET_64BIT
2191 in case they weren't overwritten by command line options. */
2194 /* Mach-O doesn't support omitting the frame pointer for now. */
2195 if (flag_omit_frame_pointer == 2)
2196 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2197 if (flag_asynchronous_unwind_tables == 2)
2198 flag_asynchronous_unwind_tables = 1;
2199 if (flag_pcc_struct_return == 2)
2200 flag_pcc_struct_return = 0;
2204 if (flag_omit_frame_pointer == 2)
2205 flag_omit_frame_pointer = 0;
2206 if (flag_asynchronous_unwind_tables == 2)
2207 flag_asynchronous_unwind_tables = 0;
2208 if (flag_pcc_struct_return == 2)
2209 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2212 /* Need to check -mtune=generic first. */
2213 if (ix86_tune_string)
2215 if (!strcmp (ix86_tune_string, "generic")
2216 || !strcmp (ix86_tune_string, "i686")
2217 /* As special support for cross compilers we read -mtune=native
2218 as -mtune=generic. With native compilers we won't see the
2219 -mtune=native, as it was changed by the driver. */
2220 || !strcmp (ix86_tune_string, "native"))
2223 ix86_tune_string = "generic64";
2225 ix86_tune_string = "generic32";
2227 else if (!strncmp (ix86_tune_string, "generic", 7))
2228 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2232 if (ix86_arch_string)
2233 ix86_tune_string = ix86_arch_string;
2234 if (!ix86_tune_string)
2236 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2237 ix86_tune_defaulted = 1;
2240 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2241 need to use a sensible tune option. */
2242 if (!strcmp (ix86_tune_string, "generic")
2243 || !strcmp (ix86_tune_string, "x86-64")
2244 || !strcmp (ix86_tune_string, "i686"))
2247 ix86_tune_string = "generic64";
2249 ix86_tune_string = "generic32";
2252 if (ix86_stringop_string)
2254 if (!strcmp (ix86_stringop_string, "rep_byte"))
2255 stringop_alg = rep_prefix_1_byte;
2256 else if (!strcmp (ix86_stringop_string, "libcall"))
2257 stringop_alg = libcall;
2258 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2259 stringop_alg = rep_prefix_4_byte;
2260 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2261 stringop_alg = rep_prefix_8_byte;
2262 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2263 stringop_alg = loop_1_byte;
2264 else if (!strcmp (ix86_stringop_string, "loop"))
2265 stringop_alg = loop;
2266 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2267 stringop_alg = unrolled_loop;
2269 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2271 if (!strcmp (ix86_tune_string, "x86-64"))
2272 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2273 "-mtune=generic instead as appropriate.");
2275 if (!ix86_arch_string)
2276 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2278 ix86_arch_specified = 1;
2280 if (!strcmp (ix86_arch_string, "generic"))
2281 error ("generic CPU can be used only for -mtune= switch");
2282 if (!strncmp (ix86_arch_string, "generic", 7))
2283 error ("bad value (%s) for -march= switch", ix86_arch_string);
2285 if (ix86_cmodel_string != 0)
2287 if (!strcmp (ix86_cmodel_string, "small"))
2288 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2289 else if (!strcmp (ix86_cmodel_string, "medium"))
2290 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2291 else if (!strcmp (ix86_cmodel_string, "large"))
2292 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2294 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2295 else if (!strcmp (ix86_cmodel_string, "32"))
2296 ix86_cmodel = CM_32;
2297 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2298 ix86_cmodel = CM_KERNEL;
2300 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2304 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2305 use of rip-relative addressing. This eliminates fixups that
2306 would otherwise be needed if this object is to be placed in a
2307 DLL, and is essentially just as efficient as direct addressing. */
2308 if (TARGET_64BIT_MS_ABI)
2309 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2310 else if (TARGET_64BIT)
2311 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2313 ix86_cmodel = CM_32;
2315 if (ix86_asm_string != 0)
2318 && !strcmp (ix86_asm_string, "intel"))
2319 ix86_asm_dialect = ASM_INTEL;
2320 else if (!strcmp (ix86_asm_string, "att"))
2321 ix86_asm_dialect = ASM_ATT;
2323 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2325 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2326 error ("code model %qs not supported in the %s bit mode",
2327 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2328 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2329 sorry ("%i-bit mode not compiled in",
2330 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2332 for (i = 0; i < pta_size; i++)
2333 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2335 ix86_arch = processor_alias_table[i].processor;
2336 /* Default cpu tuning to the architecture. */
2337 ix86_tune = ix86_arch;
2339 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2340 error ("CPU you selected does not support x86-64 "
2343 if (processor_alias_table[i].flags & PTA_MMX
2344 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2345 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2346 if (processor_alias_table[i].flags & PTA_3DNOW
2347 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2348 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2349 if (processor_alias_table[i].flags & PTA_3DNOW_A
2350 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2351 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2352 if (processor_alias_table[i].flags & PTA_SSE
2353 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2354 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2355 if (processor_alias_table[i].flags & PTA_SSE2
2356 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2357 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2358 if (processor_alias_table[i].flags & PTA_SSE3
2359 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2360 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2361 if (processor_alias_table[i].flags & PTA_SSSE3
2362 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2363 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2364 if (processor_alias_table[i].flags & PTA_SSE4_1
2365 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2366 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2367 if (processor_alias_table[i].flags & PTA_SSE4_2
2368 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2369 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2370 if (processor_alias_table[i].flags & PTA_SSE4A
2371 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2372 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2373 if (processor_alias_table[i].flags & PTA_SSE5
2374 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2375 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2377 if (processor_alias_table[i].flags & PTA_ABM)
2379 if (processor_alias_table[i].flags & PTA_CX16)
2380 x86_cmpxchg16b = true;
2381 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2383 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2384 x86_prefetch_sse = true;
2385 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2392 error ("bad value (%s) for -march= switch", ix86_arch_string);
2394 ix86_arch_mask = 1u << ix86_arch;
2395 for (i = 0; i < X86_ARCH_LAST; ++i)
2396 ix86_arch_features[i] &= ix86_arch_mask;
2398 for (i = 0; i < pta_size; i++)
2399 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2401 ix86_tune = processor_alias_table[i].processor;
2402 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2404 if (ix86_tune_defaulted)
2406 ix86_tune_string = "x86-64";
2407 for (i = 0; i < pta_size; i++)
2408 if (! strcmp (ix86_tune_string,
2409 processor_alias_table[i].name))
2411 ix86_tune = processor_alias_table[i].processor;
2414 error ("CPU you selected does not support x86-64 "
2417 /* Intel CPUs have always interpreted SSE prefetch instructions as
2418 NOPs; so, we can enable SSE prefetch instructions even when
2419 -mtune (rather than -march) points us to a processor that has them.
2420 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2421 higher processors. */
2423 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2424 x86_prefetch_sse = true;
2428 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2430 ix86_tune_mask = 1u << ix86_tune;
2431 for (i = 0; i < X86_TUNE_LAST; ++i)
2432 ix86_tune_features[i] &= ix86_tune_mask;
2435 ix86_cost = &size_cost;
2437 ix86_cost = processor_target_table[ix86_tune].cost;
2439 /* Arrange to set up i386_stack_locals for all functions. */
2440 init_machine_status = ix86_init_machine_status;
2442 /* Validate -mregparm= value. */
2443 if (ix86_regparm_string)
2446 warning (0, "-mregparm is ignored in 64-bit mode");
2447 i = atoi (ix86_regparm_string);
2448 if (i < 0 || i > REGPARM_MAX)
2449 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2454 ix86_regparm = REGPARM_MAX;
2456 /* If the user has provided any of the -malign-* options,
2457 warn and use that value only if -falign-* is not set.
2458 Remove this code in GCC 3.2 or later. */
2459 if (ix86_align_loops_string)
2461 warning (0, "-malign-loops is obsolete, use -falign-loops");
2462 if (align_loops == 0)
2464 i = atoi (ix86_align_loops_string);
2465 if (i < 0 || i > MAX_CODE_ALIGN)
2466 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2468 align_loops = 1 << i;
2472 if (ix86_align_jumps_string)
2474 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2475 if (align_jumps == 0)
2477 i = atoi (ix86_align_jumps_string);
2478 if (i < 0 || i > MAX_CODE_ALIGN)
2479 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2481 align_jumps = 1 << i;
2485 if (ix86_align_funcs_string)
2487 warning (0, "-malign-functions is obsolete, use -falign-functions");
2488 if (align_functions == 0)
2490 i = atoi (ix86_align_funcs_string);
2491 if (i < 0 || i > MAX_CODE_ALIGN)
2492 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2494 align_functions = 1 << i;
2498 /* Default align_* from the processor table. */
2499 if (align_loops == 0)
2501 align_loops = processor_target_table[ix86_tune].align_loop;
2502 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2504 if (align_jumps == 0)
2506 align_jumps = processor_target_table[ix86_tune].align_jump;
2507 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2509 if (align_functions == 0)
2511 align_functions = processor_target_table[ix86_tune].align_func;
2514 /* Validate -mbranch-cost= value, or provide default. */
2515 ix86_branch_cost = ix86_cost->branch_cost;
2516 if (ix86_branch_cost_string)
2518 i = atoi (ix86_branch_cost_string);
2520 error ("-mbranch-cost=%d is not between 0 and 5", i);
2522 ix86_branch_cost = i;
2524 if (ix86_section_threshold_string)
2526 i = atoi (ix86_section_threshold_string);
2528 error ("-mlarge-data-threshold=%d is negative", i);
2530 ix86_section_threshold = i;
2533 if (ix86_tls_dialect_string)
2535 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2536 ix86_tls_dialect = TLS_DIALECT_GNU;
2537 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2538 ix86_tls_dialect = TLS_DIALECT_GNU2;
2539 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2540 ix86_tls_dialect = TLS_DIALECT_SUN;
2542 error ("bad value (%s) for -mtls-dialect= switch",
2543 ix86_tls_dialect_string);
2546 if (ix87_precision_string)
2548 i = atoi (ix87_precision_string);
2549 if (i != 32 && i != 64 && i != 80)
2550 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2555 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2557 /* Enable by default the SSE and MMX builtins. Do allow the user to
2558 explicitly disable any of these. In particular, disabling SSE and
2559 MMX for kernel code is extremely useful. */
2560 if (!ix86_arch_specified)
2562 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2563 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2566 warning (0, "-mrtd is ignored in 64bit mode");
2570 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2572 if (!ix86_arch_specified)
2574 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2576 /* i386 ABI does not specify red zone. It still makes sense to use it
2577 when programmer takes care to stack from being destroyed. */
2578 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2579 target_flags |= MASK_NO_RED_ZONE;
2582 /* Keep nonleaf frame pointers. */
2583 if (flag_omit_frame_pointer)
2584 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2585 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2586 flag_omit_frame_pointer = 1;
2588 /* If we're doing fast math, we don't care about comparison order
2589 wrt NaNs. This lets us use a shorter comparison sequence. */
2590 if (flag_finite_math_only)
2591 target_flags &= ~MASK_IEEE_FP;
2593 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2594 since the insns won't need emulation. */
2595 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2596 target_flags &= ~MASK_NO_FANCY_MATH_387;
2598 /* Likewise, if the target doesn't have a 387, or we've specified
2599 software floating point, don't use 387 inline intrinsics. */
2601 target_flags |= MASK_NO_FANCY_MATH_387;
2603 /* Turn on MMX builtins for -msse. */
2606 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2607 x86_prefetch_sse = true;
2610 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2611 if (TARGET_SSE4_2 || TARGET_ABM)
2614 /* Validate -mpreferred-stack-boundary= value, or provide default.
2615 The default of 128 bits is for Pentium III's SSE __m128. We can't
2616 change it because of optimize_size. Otherwise, we can't mix object
2617 files compiled with -Os and -On. */
2618 ix86_preferred_stack_boundary = 128;
2619 if (ix86_preferred_stack_boundary_string)
2621 i = atoi (ix86_preferred_stack_boundary_string);
2622 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2623 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2624 TARGET_64BIT ? 4 : 2);
2626 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2629 /* Accept -msseregparm only if at least SSE support is enabled. */
2630 if (TARGET_SSEREGPARM
2632 error ("-msseregparm used without SSE enabled");
2634 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2635 if (ix86_fpmath_string != 0)
2637 if (! strcmp (ix86_fpmath_string, "387"))
2638 ix86_fpmath = FPMATH_387;
2639 else if (! strcmp (ix86_fpmath_string, "sse"))
2643 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2644 ix86_fpmath = FPMATH_387;
2647 ix86_fpmath = FPMATH_SSE;
2649 else if (! strcmp (ix86_fpmath_string, "387,sse")
2650 || ! strcmp (ix86_fpmath_string, "sse,387"))
2654 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2655 ix86_fpmath = FPMATH_387;
2657 else if (!TARGET_80387)
2659 warning (0, "387 instruction set disabled, using SSE arithmetics");
2660 ix86_fpmath = FPMATH_SSE;
2663 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2666 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2669 /* If the i387 is disabled, then do not return values in it. */
2671 target_flags &= ~MASK_FLOAT_RETURNS;
2673 /* Use external vectorized library in vectorizing intrinsics. */
2674 if (ix86_veclibabi_string)
2676 if (strcmp (ix86_veclibabi_string, "acml") == 0)
2677 ix86_veclib_handler = ix86_veclibabi_acml;
2679 error ("unknown vectorization library ABI type (%s) for "
2680 "-mveclibabi= switch", ix86_veclibabi_string);
2683 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2684 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2686 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2688 /* ??? Unwind info is not correct around the CFG unless either a frame
2689 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2690 unwind info generation to be aware of the CFG and propagating states
2692 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2693 || flag_exceptions || flag_non_call_exceptions)
2694 && flag_omit_frame_pointer
2695 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2697 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2698 warning (0, "unwind tables currently require either a frame pointer "
2699 "or -maccumulate-outgoing-args for correctness");
2700 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2703 /* If stack probes are required, the space used for large function
2704 arguments on the stack must also be probed, so enable
2705 -maccumulate-outgoing-args so this happens in the prologue. */
2706 if (TARGET_STACK_PROBE
2707 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2709 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2710 warning (0, "stack probing requires -maccumulate-outgoing-args "
2712 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2715 /* For sane SSE instruction set generation we need fcomi instruction.
2716 It is safe to enable all CMOVE instructions. */
2720 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2723 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2724 p = strchr (internal_label_prefix, 'X');
2725 internal_label_prefix_len = p - internal_label_prefix;
2729 /* When scheduling description is not available, disable scheduler pass
2730 so it won't slow down the compilation and make x87 code slower. */
2731 if (!TARGET_SCHEDULE)
2732 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2734 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2735 set_param_value ("simultaneous-prefetches",
2736 ix86_cost->simultaneous_prefetches);
2737 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2738 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2739 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2740 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2741 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2742 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2744 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2745 can be optimized to ap = __builtin_next_arg (0). */
2746 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
2747 targetm.expand_builtin_va_start = NULL;
2750 /* Return true if this goes in large data/bss. */
2753 ix86_in_large_data_p (tree exp)
2755 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2758 /* Functions are never large data. */
2759 if (TREE_CODE (exp) == FUNCTION_DECL)
2762 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2764 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2765 if (strcmp (section, ".ldata") == 0
2766 || strcmp (section, ".lbss") == 0)
2772 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2774 /* If this is an incomplete type with size 0, then we can't put it
2775 in data because it might be too big when completed. */
2776 if (!size || size > ix86_section_threshold)
2783 /* Switch to the appropriate section for output of DECL.
2784 DECL is either a `VAR_DECL' node or a constant of some sort.
2785 RELOC indicates whether forming the initial value of DECL requires
2786 link-time relocations. */
2788 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2792 x86_64_elf_select_section (tree decl, int reloc,
2793 unsigned HOST_WIDE_INT align)
2795 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2796 && ix86_in_large_data_p (decl))
2798 const char *sname = NULL;
2799 unsigned int flags = SECTION_WRITE;
2800 switch (categorize_decl_for_section (decl, reloc))
2805 case SECCAT_DATA_REL:
2806 sname = ".ldata.rel";
2808 case SECCAT_DATA_REL_LOCAL:
2809 sname = ".ldata.rel.local";
2811 case SECCAT_DATA_REL_RO:
2812 sname = ".ldata.rel.ro";
2814 case SECCAT_DATA_REL_RO_LOCAL:
2815 sname = ".ldata.rel.ro.local";
2819 flags |= SECTION_BSS;
2822 case SECCAT_RODATA_MERGE_STR:
2823 case SECCAT_RODATA_MERGE_STR_INIT:
2824 case SECCAT_RODATA_MERGE_CONST:
2828 case SECCAT_SRODATA:
2835 /* We don't split these for medium model. Place them into
2836 default sections and hope for best. */
2841 /* We might get called with string constants, but get_named_section
2842 doesn't like them as they are not DECLs. Also, we need to set
2843 flags in that case. */
2845 return get_section (sname, flags, NULL);
2846 return get_named_section (decl, sname, reloc);
2849 return default_elf_select_section (decl, reloc, align);
2852 /* Build up a unique section name, expressed as a
2853 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2854 RELOC indicates whether the initial value of EXP requires
2855 link-time relocations. */
2857 static void ATTRIBUTE_UNUSED
2858 x86_64_elf_unique_section (tree decl, int reloc)
2860 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2861 && ix86_in_large_data_p (decl))
2863 const char *prefix = NULL;
2864 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2865 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2867 switch (categorize_decl_for_section (decl, reloc))
2870 case SECCAT_DATA_REL:
2871 case SECCAT_DATA_REL_LOCAL:
2872 case SECCAT_DATA_REL_RO:
2873 case SECCAT_DATA_REL_RO_LOCAL:
2874 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2877 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2880 case SECCAT_RODATA_MERGE_STR:
2881 case SECCAT_RODATA_MERGE_STR_INIT:
2882 case SECCAT_RODATA_MERGE_CONST:
2883 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2885 case SECCAT_SRODATA:
2892 /* We don't split these for medium model. Place them into
2893 default sections and hope for best. */
2901 plen = strlen (prefix);
2903 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2904 name = targetm.strip_name_encoding (name);
2905 nlen = strlen (name);
2907 string = (char *) alloca (nlen + plen + 1);
2908 memcpy (string, prefix, plen);
2909 memcpy (string + plen, name, nlen + 1);
2911 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2915 default_unique_section (decl, reloc);
2918 #ifdef COMMON_ASM_OP
2919 /* This says how to output assembler code to declare an
2920 uninitialized external linkage data object.
2922 For medium model x86-64 we need to use .largecomm opcode for
2925 x86_elf_aligned_common (FILE *file,
2926 const char *name, unsigned HOST_WIDE_INT size,
2929 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2930 && size > (unsigned int)ix86_section_threshold)
2931 fprintf (file, ".largecomm\t");
2933 fprintf (file, "%s", COMMON_ASM_OP);
2934 assemble_name (file, name);
2935 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2936 size, align / BITS_PER_UNIT);
2940 /* Utility function for targets to use in implementing
2941 ASM_OUTPUT_ALIGNED_BSS. */
2944 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2945 const char *name, unsigned HOST_WIDE_INT size,
2948 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2949 && size > (unsigned int)ix86_section_threshold)
2950 switch_to_section (get_named_section (decl, ".lbss", 0));
2952 switch_to_section (bss_section);
2953 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2954 #ifdef ASM_DECLARE_OBJECT_NAME
2955 last_assemble_variable_decl = decl;
2956 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2958 /* Standard thing is just output label for the object. */
2959 ASM_OUTPUT_LABEL (file, name);
2960 #endif /* ASM_DECLARE_OBJECT_NAME */
2961 ASM_OUTPUT_SKIP (file, size ? size : 1);
2965 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2967 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2968 make the problem with not enough registers even worse. */
2969 #ifdef INSN_SCHEDULING
2971 flag_schedule_insns = 0;
2975 /* The Darwin libraries never set errno, so we might as well
2976 avoid calling them when that's the only reason we would. */
2977 flag_errno_math = 0;
2979 /* The default values of these switches depend on the TARGET_64BIT
2980 that is not known at this moment. Mark these values with 2 and
2981 let user the to override these. In case there is no command line option
2982 specifying them, we will set the defaults in override_options. */
2984 flag_omit_frame_pointer = 2;
2985 flag_pcc_struct_return = 2;
2986 flag_asynchronous_unwind_tables = 2;
2987 flag_vect_cost_model = 1;
2988 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2989 SUBTARGET_OPTIMIZATION_OPTIONS;
2993 /* Decide whether we can make a sibling call to a function. DECL is the
2994 declaration of the function being targeted by the call and EXP is the
2995 CALL_EXPR representing the call. */
2998 ix86_function_ok_for_sibcall (tree decl, tree exp)
3003 /* If we are generating position-independent code, we cannot sibcall
3004 optimize any indirect call, or a direct call to a global function,
3005 as the PLT requires %ebx be live. */
3006 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3013 func = TREE_TYPE (CALL_EXPR_FN (exp));
3014 if (POINTER_TYPE_P (func))
3015 func = TREE_TYPE (func);
3018 /* Check that the return value locations are the same. Like
3019 if we are returning floats on the 80387 register stack, we cannot
3020 make a sibcall from a function that doesn't return a float to a
3021 function that does or, conversely, from a function that does return
3022 a float to a function that doesn't; the necessary stack adjustment
3023 would not be executed. This is also the place we notice
3024 differences in the return value ABI. Note that it is ok for one
3025 of the functions to have void return type as long as the return
3026 value of the other is passed in a register. */
3027 a = ix86_function_value (TREE_TYPE (exp), func, false);
3028 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3030 if (STACK_REG_P (a) || STACK_REG_P (b))
3032 if (!rtx_equal_p (a, b))
3035 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3037 else if (!rtx_equal_p (a, b))
3040 /* If this call is indirect, we'll need to be able to use a call-clobbered
3041 register for the address of the target function. Make sure that all
3042 such registers are not used for passing parameters. */
3043 if (!decl && !TARGET_64BIT)
3047 /* We're looking at the CALL_EXPR, we need the type of the function. */
3048 type = CALL_EXPR_FN (exp); /* pointer expression */
3049 type = TREE_TYPE (type); /* pointer type */
3050 type = TREE_TYPE (type); /* function type */
3052 if (ix86_function_regparm (type, NULL) >= 3)
3054 /* ??? Need to count the actual number of registers to be used,
3055 not the possible number of registers. Fix later. */
3060 /* Dllimport'd functions are also called indirectly. */
3061 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3062 && decl && DECL_DLLIMPORT_P (decl)
3063 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3066 /* If we forced aligned the stack, then sibcalling would unalign the
3067 stack, which may break the called function. */
3068 if (cfun->machine->force_align_arg_pointer)
3071 /* Otherwise okay. That also includes certain types of indirect calls. */
3075 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3076 calling convention attributes;
3077 arguments as in struct attribute_spec.handler. */
3080 ix86_handle_cconv_attribute (tree *node, tree name,
3082 int flags ATTRIBUTE_UNUSED,
3085 if (TREE_CODE (*node) != FUNCTION_TYPE
3086 && TREE_CODE (*node) != METHOD_TYPE
3087 && TREE_CODE (*node) != FIELD_DECL
3088 && TREE_CODE (*node) != TYPE_DECL)
3090 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3091 IDENTIFIER_POINTER (name));
3092 *no_add_attrs = true;
3096 /* Can combine regparm with all attributes but fastcall. */
3097 if (is_attribute_p ("regparm", name))
3101 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3103 error ("fastcall and regparm attributes are not compatible");
3106 cst = TREE_VALUE (args);
3107 if (TREE_CODE (cst) != INTEGER_CST)
3109 warning (OPT_Wattributes,
3110 "%qs attribute requires an integer constant argument",
3111 IDENTIFIER_POINTER (name));
3112 *no_add_attrs = true;
3114 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3116 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3117 IDENTIFIER_POINTER (name), REGPARM_MAX);
3118 *no_add_attrs = true;
3122 && lookup_attribute (ix86_force_align_arg_pointer_string,
3123 TYPE_ATTRIBUTES (*node))
3124 && compare_tree_int (cst, REGPARM_MAX-1))
3126 error ("%s functions limited to %d register parameters",
3127 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3135 /* Do not warn when emulating the MS ABI. */
3136 if (!TARGET_64BIT_MS_ABI)
3137 warning (OPT_Wattributes, "%qs attribute ignored",
3138 IDENTIFIER_POINTER (name));
3139 *no_add_attrs = true;
3143 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3144 if (is_attribute_p ("fastcall", name))
3146 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3148 error ("fastcall and cdecl attributes are not compatible");
3150 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3152 error ("fastcall and stdcall attributes are not compatible");
3154 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3156 error ("fastcall and regparm attributes are not compatible");
3160 /* Can combine stdcall with fastcall (redundant), regparm and
3162 else if (is_attribute_p ("stdcall", name))
3164 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3166 error ("stdcall and cdecl attributes are not compatible");
3168 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3170 error ("stdcall and fastcall attributes are not compatible");
3174 /* Can combine cdecl with regparm and sseregparm. */
3175 else if (is_attribute_p ("cdecl", name))
3177 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3179 error ("stdcall and cdecl attributes are not compatible");
3181 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3183 error ("fastcall and cdecl attributes are not compatible");
3187 /* Can combine sseregparm with all attributes. */
3192 /* Return 0 if the attributes for two types are incompatible, 1 if they
3193 are compatible, and 2 if they are nearly compatible (which causes a
3194 warning to be generated). */
3197 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3199 /* Check for mismatch of non-default calling convention. */
3200 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3202 if (TREE_CODE (type1) != FUNCTION_TYPE
3203 && TREE_CODE (type1) != METHOD_TYPE)
3206 /* Check for mismatched fastcall/regparm types. */
3207 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3208 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3209 || (ix86_function_regparm (type1, NULL)
3210 != ix86_function_regparm (type2, NULL)))
3213 /* Check for mismatched sseregparm types. */
3214 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3215 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3218 /* Check for mismatched return types (cdecl vs stdcall). */
3219 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3220 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3226 /* Return the regparm value for a function with the indicated TYPE and DECL.
3227 DECL may be NULL when calling function indirectly
3228 or considering a libcall. */
3231 ix86_function_regparm (const_tree type, const_tree decl)
3234 int regparm = ix86_regparm;
3239 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3241 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3243 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3246 /* Use register calling convention for local functions when possible. */
3247 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3248 && flag_unit_at_a_time && !profile_flag)
3250 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3251 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3254 int local_regparm, globals = 0, regno;
3257 /* Make sure no regparm register is taken by a
3258 fixed register variable. */
3259 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3260 if (fixed_regs[local_regparm])
3263 /* We can't use regparm(3) for nested functions as these use
3264 static chain pointer in third argument. */
3265 if (local_regparm == 3
3266 && (decl_function_context (decl)
3267 || ix86_force_align_arg_pointer)
3268 && !DECL_NO_STATIC_CHAIN (decl))
3271 /* If the function realigns its stackpointer, the prologue will
3272 clobber %ecx. If we've already generated code for the callee,
3273 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3274 scanning the attributes for the self-realigning property. */
3275 f = DECL_STRUCT_FUNCTION (decl);
3276 if (local_regparm == 3
3277 && (f ? !!f->machine->force_align_arg_pointer
3278 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3279 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3282 /* Each fixed register usage increases register pressure,
3283 so less registers should be used for argument passing.
3284 This functionality can be overriden by an explicit
3286 for (regno = 0; regno <= DI_REG; regno++)
3287 if (fixed_regs[regno])
3291 = globals < local_regparm ? local_regparm - globals : 0;
3293 if (local_regparm > regparm)
3294 regparm = local_regparm;
3301 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3302 DFmode (2) arguments in SSE registers for a function with the
3303 indicated TYPE and DECL. DECL may be NULL when calling function
3304 indirectly or considering a libcall. Otherwise return 0. */
3307 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3309 gcc_assert (!TARGET_64BIT);
3311 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3312 by the sseregparm attribute. */
3313 if (TARGET_SSEREGPARM
3314 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3321 error ("Calling %qD with attribute sseregparm without "
3322 "SSE/SSE2 enabled", decl);
3324 error ("Calling %qT with attribute sseregparm without "
3325 "SSE/SSE2 enabled", type);
3333 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3334 (and DFmode for SSE2) arguments in SSE registers. */
3335 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3337 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3338 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3340 return TARGET_SSE2 ? 2 : 1;
3346 /* Return true if EAX is live at the start of the function. Used by
3347 ix86_expand_prologue to determine if we need special help before
3348 calling allocate_stack_worker. */
3351 ix86_eax_live_at_start_p (void)
3353 /* Cheat. Don't bother working forward from ix86_function_regparm
3354 to the function type to whether an actual argument is located in
3355 eax. Instead just look at cfg info, which is still close enough
3356 to correct at this point. This gives false positives for broken
3357 functions that might use uninitialized data that happens to be
3358 allocated in eax, but who cares? */
3359 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3362 /* Value is the number of bytes of arguments automatically
3363 popped when returning from a subroutine call.
3364 FUNDECL is the declaration node of the function (as a tree),
3365 FUNTYPE is the data type of the function (as a tree),
3366 or for a library call it is an identifier node for the subroutine name.
3367 SIZE is the number of bytes of arguments passed on the stack.
3369 On the 80386, the RTD insn may be used to pop them if the number
3370 of args is fixed, but if the number is variable then the caller
3371 must pop them all. RTD can't be used for library calls now
3372 because the library is compiled with the Unix compiler.
3373 Use of RTD is a selectable option, since it is incompatible with
3374 standard Unix calling sequences. If the option is not selected,
3375 the caller must always pop the args.
3377 The attribute stdcall is equivalent to RTD on a per module basis. */
3380 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3384 /* None of the 64-bit ABIs pop arguments. */
3388 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3390 /* Cdecl functions override -mrtd, and never pop the stack. */
3391 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3393 /* Stdcall and fastcall functions will pop the stack if not
3395 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3396 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3399 if (rtd && ! stdarg_p (funtype))
3403 /* Lose any fake structure return argument if it is passed on the stack. */
3404 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3405 && !KEEP_AGGREGATE_RETURN_POINTER)
3407 int nregs = ix86_function_regparm (funtype, fundecl);
3409 return GET_MODE_SIZE (Pmode);
3415 /* Argument support functions. */
3417 /* Return true when register may be used to pass function parameters. */
3419 ix86_function_arg_regno_p (int regno)
3422 const int *parm_regs;
3427 return (regno < REGPARM_MAX
3428 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3430 return (regno < REGPARM_MAX
3431 || (TARGET_MMX && MMX_REGNO_P (regno)
3432 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3433 || (TARGET_SSE && SSE_REGNO_P (regno)
3434 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3439 if (SSE_REGNO_P (regno) && TARGET_SSE)
3444 if (TARGET_SSE && SSE_REGNO_P (regno)
3445 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3449 /* RAX is used as hidden argument to va_arg functions. */
3450 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3453 if (TARGET_64BIT_MS_ABI)
3454 parm_regs = x86_64_ms_abi_int_parameter_registers;
3456 parm_regs = x86_64_int_parameter_registers;
3457 for (i = 0; i < REGPARM_MAX; i++)
3458 if (regno == parm_regs[i])
3463 /* Return if we do not know how to pass TYPE solely in registers. */
3466 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3468 if (must_pass_in_stack_var_size_or_pad (mode, type))
3471 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3472 The layout_type routine is crafty and tries to trick us into passing
3473 currently unsupported vector types on the stack by using TImode. */
3474 return (!TARGET_64BIT && mode == TImode
3475 && type && TREE_CODE (type) != VECTOR_TYPE);
3478 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3479 for a call to a function whose data type is FNTYPE.
3480 For a library call, FNTYPE is 0. */
3483 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3484 tree fntype, /* tree ptr for function decl */
3485 rtx libname, /* SYMBOL_REF of library name or 0 */
3488 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3489 memset (cum, 0, sizeof (*cum));
3491 /* Set up the number of registers to use for passing arguments. */
3492 cum->nregs = ix86_regparm;
3494 cum->sse_nregs = SSE_REGPARM_MAX;
3496 cum->mmx_nregs = MMX_REGPARM_MAX;
3497 cum->warn_sse = true;
3498 cum->warn_mmx = true;
3500 /* Because type might mismatch in between caller and callee, we need to
3501 use actual type of function for local calls.
3502 FIXME: cgraph_analyze can be told to actually record if function uses
3503 va_start so for local functions maybe_vaarg can be made aggressive
3505 FIXME: once typesytem is fixed, we won't need this code anymore. */
3507 fntype = TREE_TYPE (fndecl);
3508 cum->maybe_vaarg = (fntype
3509 ? (!prototype_p (fntype) || stdarg_p (fntype))
3514 /* If there are variable arguments, then we won't pass anything
3515 in registers in 32-bit mode. */
3516 if (cum->maybe_vaarg)
3526 /* Use ecx and edx registers if function has fastcall attribute,
3527 else look for regparm information. */
3530 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3536 cum->nregs = ix86_function_regparm (fntype, fndecl);
3539 /* Set up the number of SSE registers used for passing SFmode
3540 and DFmode arguments. Warn for mismatching ABI. */
3541 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3545 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3546 But in the case of vector types, it is some vector mode.
3548 When we have only some of our vector isa extensions enabled, then there
3549 are some modes for which vector_mode_supported_p is false. For these
3550 modes, the generic vector support in gcc will choose some non-vector mode
3551 in order to implement the type. By computing the natural mode, we'll
3552 select the proper ABI location for the operand and not depend on whatever
3553 the middle-end decides to do with these vector types. */
3555 static enum machine_mode
3556 type_natural_mode (const_tree type)
3558 enum machine_mode mode = TYPE_MODE (type);
3560 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3562 HOST_WIDE_INT size = int_size_in_bytes (type);
3563 if ((size == 8 || size == 16)
3564 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3565 && TYPE_VECTOR_SUBPARTS (type) > 1)
3567 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3569 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3570 mode = MIN_MODE_VECTOR_FLOAT;
3572 mode = MIN_MODE_VECTOR_INT;
3574 /* Get the mode which has this inner mode and number of units. */
3575 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3576 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3577 && GET_MODE_INNER (mode) == innermode)
3587 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3588 this may not agree with the mode that the type system has chosen for the
3589 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3590 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3593 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3598 if (orig_mode != BLKmode)
3599 tmp = gen_rtx_REG (orig_mode, regno);
3602 tmp = gen_rtx_REG (mode, regno);
3603 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3604 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3610 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3611 of this code is to classify each 8bytes of incoming argument by the register
3612 class and assign registers accordingly. */
3614 /* Return the union class of CLASS1 and CLASS2.
3615 See the x86-64 PS ABI for details. */
3617 static enum x86_64_reg_class
3618 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3620 /* Rule #1: If both classes are equal, this is the resulting class. */
3621 if (class1 == class2)
3624 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3626 if (class1 == X86_64_NO_CLASS)
3628 if (class2 == X86_64_NO_CLASS)
3631 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3632 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3633 return X86_64_MEMORY_CLASS;
3635 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3636 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3637 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3638 return X86_64_INTEGERSI_CLASS;
3639 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3640 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3641 return X86_64_INTEGER_CLASS;
3643 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3645 if (class1 == X86_64_X87_CLASS
3646 || class1 == X86_64_X87UP_CLASS
3647 || class1 == X86_64_COMPLEX_X87_CLASS
3648 || class2 == X86_64_X87_CLASS
3649 || class2 == X86_64_X87UP_CLASS
3650 || class2 == X86_64_COMPLEX_X87_CLASS)
3651 return X86_64_MEMORY_CLASS;
3653 /* Rule #6: Otherwise class SSE is used. */
3654 return X86_64_SSE_CLASS;
3657 /* Classify the argument of type TYPE and mode MODE.
3658 CLASSES will be filled by the register class used to pass each word
3659 of the operand. The number of words is returned. In case the parameter
3660 should be passed in memory, 0 is returned. As a special case for zero
3661 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3663 BIT_OFFSET is used internally for handling records and specifies offset
3664 of the offset in bits modulo 256 to avoid overflow cases.
3666 See the x86-64 PS ABI for details.
3670 classify_argument (enum machine_mode mode, const_tree type,
3671 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3673 HOST_WIDE_INT bytes =
3674 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3675 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3677 /* Variable sized entities are always passed/returned in memory. */
3681 if (mode != VOIDmode
3682 && targetm.calls.must_pass_in_stack (mode, type))
3685 if (type && AGGREGATE_TYPE_P (type))
3689 enum x86_64_reg_class subclasses[MAX_CLASSES];
3691 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3695 for (i = 0; i < words; i++)
3696 classes[i] = X86_64_NO_CLASS;
3698 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3699 signalize memory class, so handle it as special case. */
3702 classes[0] = X86_64_NO_CLASS;
3706 /* Classify each field of record and merge classes. */
3707 switch (TREE_CODE (type))
3710 /* And now merge the fields of structure. */
3711 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3713 if (TREE_CODE (field) == FIELD_DECL)
3717 if (TREE_TYPE (field) == error_mark_node)
3720 /* Bitfields are always classified as integer. Handle them
3721 early, since later code would consider them to be
3722 misaligned integers. */
3723 if (DECL_BIT_FIELD (field))
3725 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3726 i < ((int_bit_position (field) + (bit_offset % 64))
3727 + tree_low_cst (DECL_SIZE (field), 0)
3730 merge_classes (X86_64_INTEGER_CLASS,
3735 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3736 TREE_TYPE (field), subclasses,
3737 (int_bit_position (field)
3738 + bit_offset) % 256);
3741 for (i = 0; i < num; i++)
3744 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3746 merge_classes (subclasses[i], classes[i + pos]);
3754 /* Arrays are handled as small records. */
3757 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3758 TREE_TYPE (type), subclasses, bit_offset);
3762 /* The partial classes are now full classes. */
3763 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3764 subclasses[0] = X86_64_SSE_CLASS;
3765 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3766 subclasses[0] = X86_64_INTEGER_CLASS;
3768 for (i = 0; i < words; i++)
3769 classes[i] = subclasses[i % num];
3774 case QUAL_UNION_TYPE:
3775 /* Unions are similar to RECORD_TYPE but offset is always 0.
3777 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3779 if (TREE_CODE (field) == FIELD_DECL)
3783 if (TREE_TYPE (field) == error_mark_node)
3786 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3787 TREE_TYPE (field), subclasses,
3791 for (i = 0; i < num; i++)
3792 classes[i] = merge_classes (subclasses[i], classes[i]);
3801 /* Final merger cleanup. */
3802 for (i = 0; i < words; i++)
3804 /* If one class is MEMORY, everything should be passed in
3806 if (classes[i] == X86_64_MEMORY_CLASS)
3809 /* The X86_64_SSEUP_CLASS should be always preceded by
3810 X86_64_SSE_CLASS. */
3811 if (classes[i] == X86_64_SSEUP_CLASS
3812 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3813 classes[i] = X86_64_SSE_CLASS;
3815 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3816 if (classes[i] == X86_64_X87UP_CLASS
3817 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3818 classes[i] = X86_64_SSE_CLASS;
3823 /* Compute alignment needed. We align all types to natural boundaries with
3824 exception of XFmode that is aligned to 64bits. */
3825 if (mode != VOIDmode && mode != BLKmode)
3827 int mode_alignment = GET_MODE_BITSIZE (mode);
3830 mode_alignment = 128;
3831 else if (mode == XCmode)
3832 mode_alignment = 256;
3833 if (COMPLEX_MODE_P (mode))
3834 mode_alignment /= 2;
3835 /* Misaligned fields are always returned in memory. */
3836 if (bit_offset % mode_alignment)
3840 /* for V1xx modes, just use the base mode */
3841 if (VECTOR_MODE_P (mode) && mode != V1DImode
3842 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3843 mode = GET_MODE_INNER (mode);
3845 /* Classification of atomic types. */
3850 classes[0] = X86_64_SSE_CLASS;
3853 classes[0] = X86_64_SSE_CLASS;
3854 classes[1] = X86_64_SSEUP_CLASS;
3863 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3864 classes[0] = X86_64_INTEGERSI_CLASS;
3866 classes[0] = X86_64_INTEGER_CLASS;
3870 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3875 if (!(bit_offset % 64))
3876 classes[0] = X86_64_SSESF_CLASS;
3878 classes[0] = X86_64_SSE_CLASS;
3881 classes[0] = X86_64_SSEDF_CLASS;
3884 classes[0] = X86_64_X87_CLASS;
3885 classes[1] = X86_64_X87UP_CLASS;
3888 classes[0] = X86_64_SSE_CLASS;
3889 classes[1] = X86_64_SSEUP_CLASS;
3892 classes[0] = X86_64_SSE_CLASS;
3895 classes[0] = X86_64_SSEDF_CLASS;
3896 classes[1] = X86_64_SSEDF_CLASS;
3899 classes[0] = X86_64_COMPLEX_X87_CLASS;
3902 /* This modes is larger than 16 bytes. */
3910 classes[0] = X86_64_SSE_CLASS;
3911 classes[1] = X86_64_SSEUP_CLASS;
3918 classes[0] = X86_64_SSE_CLASS;
3924 gcc_assert (VECTOR_MODE_P (mode));
3929 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3931 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3932 classes[0] = X86_64_INTEGERSI_CLASS;
3934 classes[0] = X86_64_INTEGER_CLASS;
3935 classes[1] = X86_64_INTEGER_CLASS;
3936 return 1 + (bytes > 8);
3940 /* Examine the argument and return set number of register required in each
3941 class. Return 0 iff parameter should be passed in memory. */
3943 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3944 int *int_nregs, int *sse_nregs)
3946 enum x86_64_reg_class regclass[MAX_CLASSES];
3947 int n = classify_argument (mode, type, regclass, 0);
3953 for (n--; n >= 0; n--)
3954 switch (regclass[n])
3956 case X86_64_INTEGER_CLASS:
3957 case X86_64_INTEGERSI_CLASS:
3960 case X86_64_SSE_CLASS:
3961 case X86_64_SSESF_CLASS:
3962 case X86_64_SSEDF_CLASS:
3965 case X86_64_NO_CLASS:
3966 case X86_64_SSEUP_CLASS:
3968 case X86_64_X87_CLASS:
3969 case X86_64_X87UP_CLASS:
3973 case X86_64_COMPLEX_X87_CLASS:
3974 return in_return ? 2 : 0;
3975 case X86_64_MEMORY_CLASS:
3981 /* Construct container for the argument used by GCC interface. See
3982 FUNCTION_ARG for the detailed description. */
3985 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3986 const_tree type, int in_return, int nintregs, int nsseregs,
3987 const int *intreg, int sse_regno)
3989 /* The following variables hold the static issued_error state. */
3990 static bool issued_sse_arg_error;
3991 static bool issued_sse_ret_error;
3992 static bool issued_x87_ret_error;
3994 enum machine_mode tmpmode;
3996 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3997 enum x86_64_reg_class regclass[MAX_CLASSES];
4001 int needed_sseregs, needed_intregs;
4002 rtx exp[MAX_CLASSES];
4005 n = classify_argument (mode, type, regclass, 0);
4008 if (!examine_argument (mode, type, in_return, &needed_intregs,
4011 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4014 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4015 some less clueful developer tries to use floating-point anyway. */
4016 if (needed_sseregs && !TARGET_SSE)
4020 if (!issued_sse_ret_error)
4022 error ("SSE register return with SSE disabled");
4023 issued_sse_ret_error = true;
4026 else if (!issued_sse_arg_error)
4028 error ("SSE register argument with SSE disabled");
4029 issued_sse_arg_error = true;
4034 /* Likewise, error if the ABI requires us to return values in the
4035 x87 registers and the user specified -mno-80387. */
4036 if (!TARGET_80387 && in_return)
4037 for (i = 0; i < n; i++)
4038 if (regclass[i] == X86_64_X87_CLASS
4039 || regclass[i] == X86_64_X87UP_CLASS
4040 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4042 if (!issued_x87_ret_error)
4044 error ("x87 register return with x87 disabled");
4045 issued_x87_ret_error = true;
4050 /* First construct simple cases. Avoid SCmode, since we want to use
4051 single register to pass this type. */
4052 if (n == 1 && mode != SCmode)
4053 switch (regclass[0])
4055 case X86_64_INTEGER_CLASS:
4056 case X86_64_INTEGERSI_CLASS:
4057 return gen_rtx_REG (mode, intreg[0]);
4058 case X86_64_SSE_CLASS:
4059 case X86_64_SSESF_CLASS:
4060 case X86_64_SSEDF_CLASS:
4061 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4062 case X86_64_X87_CLASS:
4063 case X86_64_COMPLEX_X87_CLASS:
4064 return gen_rtx_REG (mode, FIRST_STACK_REG);
4065 case X86_64_NO_CLASS:
4066 /* Zero sized array, struct or class. */
4071 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4072 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4073 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4076 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4077 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4078 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4079 && regclass[1] == X86_64_INTEGER_CLASS
4080 && (mode == CDImode || mode == TImode || mode == TFmode)
4081 && intreg[0] + 1 == intreg[1])
4082 return gen_rtx_REG (mode, intreg[0]);
4084 /* Otherwise figure out the entries of the PARALLEL. */
4085 for (i = 0; i < n; i++)
4087 switch (regclass[i])
4089 case X86_64_NO_CLASS:
4091 case X86_64_INTEGER_CLASS:
4092 case X86_64_INTEGERSI_CLASS:
4093 /* Merge TImodes on aligned occasions here too. */
4094 if (i * 8 + 8 > bytes)
4095 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4096 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4100 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4101 if (tmpmode == BLKmode)
4103 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4104 gen_rtx_REG (tmpmode, *intreg),
4108 case X86_64_SSESF_CLASS:
4109 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4110 gen_rtx_REG (SFmode,
4111 SSE_REGNO (sse_regno)),
4115 case X86_64_SSEDF_CLASS:
4116 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4117 gen_rtx_REG (DFmode,
4118 SSE_REGNO (sse_regno)),
4122 case X86_64_SSE_CLASS:
4123 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4127 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4128 gen_rtx_REG (tmpmode,
4129 SSE_REGNO (sse_regno)),
4131 if (tmpmode == TImode)
4140 /* Empty aligned struct, union or class. */
4144 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4145 for (i = 0; i < nexps; i++)
4146 XVECEXP (ret, 0, i) = exp [i];
4150 /* Update the data in CUM to advance over an argument of mode MODE
4151 and data type TYPE. (TYPE is null for libcalls where that information
4152 may not be available.) */
4155 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4156 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4172 cum->words += words;
4173 cum->nregs -= words;
4174 cum->regno += words;
4176 if (cum->nregs <= 0)
4184 if (cum->float_in_sse < 2)
4187 if (cum->float_in_sse < 1)
4198 if (!type || !AGGREGATE_TYPE_P (type))
4200 cum->sse_words += words;
4201 cum->sse_nregs -= 1;
4202 cum->sse_regno += 1;
4203 if (cum->sse_nregs <= 0)
4216 if (!type || !AGGREGATE_TYPE_P (type))
4218 cum->mmx_words += words;
4219 cum->mmx_nregs -= 1;
4220 cum->mmx_regno += 1;
4221 if (cum->mmx_nregs <= 0)
4232 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4233 tree type, HOST_WIDE_INT words)
4235 int int_nregs, sse_nregs;
4237 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4238 cum->words += words;
4239 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4241 cum->nregs -= int_nregs;
4242 cum->sse_nregs -= sse_nregs;
4243 cum->regno += int_nregs;
4244 cum->sse_regno += sse_nregs;
4247 cum->words += words;
4251 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4252 HOST_WIDE_INT words)
4254 /* Otherwise, this should be passed indirect. */
4255 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4257 cum->words += words;
4266 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4267 tree type, int named ATTRIBUTE_UNUSED)
4269 HOST_WIDE_INT bytes, words;
4271 if (mode == BLKmode)
4272 bytes = int_size_in_bytes (type);
4274 bytes = GET_MODE_SIZE (mode);
4275 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4278 mode = type_natural_mode (type);
4280 if (TARGET_64BIT_MS_ABI)
4281 function_arg_advance_ms_64 (cum, bytes, words);
4282 else if (TARGET_64BIT)
4283 function_arg_advance_64 (cum, mode, type, words);
4285 function_arg_advance_32 (cum, mode, type, bytes, words);
4288 /* Define where to put the arguments to a function.
4289 Value is zero to push the argument on the stack,
4290 or a hard register in which to store the argument.
4292 MODE is the argument's machine mode.
4293 TYPE is the data type of the argument (as a tree).
4294 This is null for libcalls where that information may
4296 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4297 the preceding args and about the function being called.
4298 NAMED is nonzero if this argument is a named parameter
4299 (otherwise it is an extra parameter matching an ellipsis). */
4302 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4303 enum machine_mode orig_mode, tree type,
4304 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4306 static bool warnedsse, warnedmmx;
4308 /* Avoid the AL settings for the Unix64 ABI. */
4309 if (mode == VOIDmode)
4325 if (words <= cum->nregs)
4327 int regno = cum->regno;
4329 /* Fastcall allocates the first two DWORD (SImode) or
4330 smaller arguments to ECX and EDX if it isn't an
4336 || (type && AGGREGATE_TYPE_P (type)))
4339 /* ECX not EAX is the first allocated register. */
4340 if (regno == AX_REG)
4343 return gen_rtx_REG (mode, regno);
4348 if (cum->float_in_sse < 2)
4351 if (cum->float_in_sse < 1)
4361 if (!type || !AGGREGATE_TYPE_P (type))
4363 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4366 warning (0, "SSE vector argument without SSE enabled "
4370 return gen_reg_or_parallel (mode, orig_mode,
4371 cum->sse_regno + FIRST_SSE_REG);
4380 if (!type || !AGGREGATE_TYPE_P (type))
4382 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4385 warning (0, "MMX vector argument without MMX enabled "
4389 return gen_reg_or_parallel (mode, orig_mode,
4390 cum->mmx_regno + FIRST_MMX_REG);
4399 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4400 enum machine_mode orig_mode, tree type)
4402 /* Handle a hidden AL argument containing number of registers
4403 for varargs x86-64 functions. */
4404 if (mode == VOIDmode)
4405 return GEN_INT (cum->maybe_vaarg
4406 ? (cum->sse_nregs < 0
4411 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4413 &x86_64_int_parameter_registers [cum->regno],
4418 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4419 enum machine_mode orig_mode, int named)
4423 /* Avoid the AL settings for the Unix64 ABI. */
4424 if (mode == VOIDmode)
4427 /* If we've run out of registers, it goes on the stack. */
4428 if (cum->nregs == 0)
4431 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4433 /* Only floating point modes are passed in anything but integer regs. */
4434 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4437 regno = cum->regno + FIRST_SSE_REG;
4442 /* Unnamed floating parameters are passed in both the
4443 SSE and integer registers. */
4444 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4445 t2 = gen_rtx_REG (mode, regno);
4446 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4447 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4448 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4452 return gen_reg_or_parallel (mode, orig_mode, regno);
4456 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4457 tree type, int named)
4459 enum machine_mode mode = omode;
4460 HOST_WIDE_INT bytes, words;
4462 if (mode == BLKmode)
4463 bytes = int_size_in_bytes (type);
4465 bytes = GET_MODE_SIZE (mode);
4466 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4468 /* To simplify the code below, represent vector types with a vector mode
4469 even if MMX/SSE are not active. */
4470 if (type && TREE_CODE (type) == VECTOR_TYPE)
4471 mode = type_natural_mode (type);
4473 if (TARGET_64BIT_MS_ABI)
4474 return function_arg_ms_64 (cum, mode, omode, named);
4475 else if (TARGET_64BIT)
4476 return function_arg_64 (cum, mode, omode, type);
4478 return function_arg_32 (cum, mode, omode, type, bytes, words);
4481 /* A C expression that indicates when an argument must be passed by
4482 reference. If nonzero for an argument, a copy of that argument is
4483 made in memory and a pointer to the argument is passed instead of
4484 the argument itself. The pointer is passed in whatever way is
4485 appropriate for passing a pointer to that type. */
4488 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4489 enum machine_mode mode ATTRIBUTE_UNUSED,
4490 const_tree type, bool named ATTRIBUTE_UNUSED)
4492 if (TARGET_64BIT_MS_ABI)
4496 /* Arrays are passed by reference. */
4497 if (TREE_CODE (type) == ARRAY_TYPE)
4500 if (AGGREGATE_TYPE_P (type))
4502 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4503 are passed by reference. */
4504 int el2 = exact_log2 (int_size_in_bytes (type));
4505 return !(el2 >= 0 && el2 <= 3);
4509 /* __m128 is passed by reference. */
4510 /* ??? How to handle complex? For now treat them as structs,
4511 and pass them by reference if they're too large. */
4512 if (GET_MODE_SIZE (mode) > 8)
4515 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4521 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4522 ABI. Only called if TARGET_SSE. */
4524 contains_128bit_aligned_vector_p (tree type)
4526 enum machine_mode mode = TYPE_MODE (type);
4527 if (SSE_REG_MODE_P (mode)
4528 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4530 if (TYPE_ALIGN (type) < 128)
4533 if (AGGREGATE_TYPE_P (type))
4535 /* Walk the aggregates recursively. */
4536 switch (TREE_CODE (type))
4540 case QUAL_UNION_TYPE:
4544 /* Walk all the structure fields. */
4545 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4547 if (TREE_CODE (field) == FIELD_DECL
4548 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4555 /* Just for use if some languages passes arrays by value. */
4556 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4567 /* Gives the alignment boundary, in bits, of an argument with the
4568 specified mode and type. */
4571 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4575 align = TYPE_ALIGN (type);
4577 align = GET_MODE_ALIGNMENT (mode);
4578 if (align < PARM_BOUNDARY)
4579 align = PARM_BOUNDARY;
4582 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4583 make an exception for SSE modes since these require 128bit
4586 The handling here differs from field_alignment. ICC aligns MMX
4587 arguments to 4 byte boundaries, while structure fields are aligned
4588 to 8 byte boundaries. */
4590 align = PARM_BOUNDARY;
4593 if (!SSE_REG_MODE_P (mode))
4594 align = PARM_BOUNDARY;
4598 if (!contains_128bit_aligned_vector_p (type))
4599 align = PARM_BOUNDARY;
4607 /* Return true if N is a possible register number of function value. */
4610 ix86_function_value_regno_p (int regno)
4617 case FIRST_FLOAT_REG:
4618 if (TARGET_64BIT_MS_ABI)
4620 return TARGET_FLOAT_RETURNS_IN_80387;
4626 if (TARGET_MACHO || TARGET_64BIT)
4634 /* Define how to find the value returned by a function.
4635 VALTYPE is the data type of the value (as a tree).
4636 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4637 otherwise, FUNC is 0. */
4640 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4641 const_tree fntype, const_tree fn)
4645 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4646 we normally prevent this case when mmx is not available. However
4647 some ABIs may require the result to be returned like DImode. */
4648 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4649 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4651 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4652 we prevent this case when sse is not available. However some ABIs
4653 may require the result to be returned like integer TImode. */
4654 else if (mode == TImode
4655 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4656 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4658 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4659 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4660 regno = FIRST_FLOAT_REG;
4662 /* Most things go in %eax. */
4665 /* Override FP return register with %xmm0 for local functions when
4666 SSE math is enabled or for functions with sseregparm attribute. */
4667 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4669 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4670 if ((sse_level >= 1 && mode == SFmode)
4671 || (sse_level == 2 && mode == DFmode))
4672 regno = FIRST_SSE_REG;
4675 return gen_rtx_REG (orig_mode, regno);
4679 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4684 /* Handle libcalls, which don't provide a type node. */
4685 if (valtype == NULL)
4697 return gen_rtx_REG (mode, FIRST_SSE_REG);
4700 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4704 return gen_rtx_REG (mode, AX_REG);
4708 ret = construct_container (mode, orig_mode, valtype, 1,
4709 REGPARM_MAX, SSE_REGPARM_MAX,
4710 x86_64_int_return_registers, 0);
4712 /* For zero sized structures, construct_container returns NULL, but we
4713 need to keep rest of compiler happy by returning meaningful value. */
4715 ret = gen_rtx_REG (orig_mode, AX_REG);
4721 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4723 unsigned int regno = AX_REG;
4727 if (mode == SFmode || mode == DFmode)
4728 regno = FIRST_SSE_REG;
4729 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4730 regno = FIRST_SSE_REG;
4733 return gen_rtx_REG (orig_mode, regno);
4737 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4738 enum machine_mode orig_mode, enum machine_mode mode)
4740 const_tree fn, fntype;
4743 if (fntype_or_decl && DECL_P (fntype_or_decl))
4744 fn = fntype_or_decl;
4745 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4747 if (TARGET_64BIT_MS_ABI)
4748 return function_value_ms_64 (orig_mode, mode);
4749 else if (TARGET_64BIT)
4750 return function_value_64 (orig_mode, mode, valtype);
4752 return function_value_32 (orig_mode, mode, fntype, fn);
4756 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4757 bool outgoing ATTRIBUTE_UNUSED)
4759 enum machine_mode mode, orig_mode;
4761 orig_mode = TYPE_MODE (valtype);
4762 mode = type_natural_mode (valtype);
4763 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4767 ix86_libcall_value (enum machine_mode mode)
4769 return ix86_function_value_1 (NULL, NULL, mode, mode);
4772 /* Return true iff type is returned in memory. */
4775 return_in_memory_32 (const_tree type, enum machine_mode mode)
4779 if (mode == BLKmode)
4782 size = int_size_in_bytes (type);
4784 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4787 if (VECTOR_MODE_P (mode) || mode == TImode)
4789 /* User-created vectors small enough to fit in EAX. */
4793 /* MMX/3dNow values are returned in MM0,
4794 except when it doesn't exits. */
4796 return (TARGET_MMX ? 0 : 1);
4798 /* SSE values are returned in XMM0, except when it doesn't exist. */
4800 return (TARGET_SSE ? 0 : 1);
4815 return_in_memory_64 (const_tree type, enum machine_mode mode)
4817 int needed_intregs, needed_sseregs;
4818 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4822 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4824 HOST_WIDE_INT size = int_size_in_bytes (type);
4826 /* __m128 and friends are returned in xmm0. */
4827 if (!COMPLEX_MODE_P (mode) && size == 16 && VECTOR_MODE_P (mode))
4830 /* Otherwise, the size must be exactly in [1248]. But not for complex. */
4831 return (size != 1 && size != 2 && size != 4 && size != 8)
4832 || COMPLEX_MODE_P (mode);
4836 ix86_return_in_memory (const_tree type)
4838 const enum machine_mode mode = type_natural_mode (type);
4840 if (TARGET_64BIT_MS_ABI)
4841 return return_in_memory_ms_64 (type, mode);
4842 else if (TARGET_64BIT)
4843 return return_in_memory_64 (type, mode);
4845 return return_in_memory_32 (type, mode);
4848 /* Return false iff TYPE is returned in memory. This version is used
4849 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4850 but differs notably in that when MMX is available, 8-byte vectors
4851 are returned in memory, rather than in MMX registers. */
4854 ix86_sol10_return_in_memory (const_tree type)
4857 enum machine_mode mode = type_natural_mode (type);
4860 return return_in_memory_64 (type, mode);
4862 if (mode == BLKmode)
4865 size = int_size_in_bytes (type);
4867 if (VECTOR_MODE_P (mode))
4869 /* Return in memory only if MMX registers *are* available. This
4870 seems backwards, but it is consistent with the existing
4877 else if (mode == TImode)
4879 else if (mode == XFmode)
4885 /* When returning SSE vector types, we have a choice of either
4886 (1) being abi incompatible with a -march switch, or
4887 (2) generating an error.
4888 Given no good solution, I think the safest thing is one warning.
4889 The user won't be able to use -Werror, but....
4891 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4892 called in response to actually generating a caller or callee that
4893 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4894 via aggregate_value_p for general type probing from tree-ssa. */
4897 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4899 static bool warnedsse, warnedmmx;
4901 if (!TARGET_64BIT && type)
4903 /* Look at the return type of the function, not the function type. */
4904 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4906 if (!TARGET_SSE && !warnedsse)
4909 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4912 warning (0, "SSE vector return without SSE enabled "
4917 if (!TARGET_MMX && !warnedmmx)
4919 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4922 warning (0, "MMX vector return without MMX enabled "
4932 /* Create the va_list data type. */
4935 ix86_build_builtin_va_list (void)
4937 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4939 /* For i386 we use plain pointer to argument area. */
4940 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4941 return build_pointer_type (char_type_node);
4943 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4944 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4946 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4947 unsigned_type_node);
4948 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4949 unsigned_type_node);
4950 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4952 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4955 va_list_gpr_counter_field = f_gpr;
4956 va_list_fpr_counter_field = f_fpr;
4958 DECL_FIELD_CONTEXT (f_gpr) = record;
4959 DECL_FIELD_CONTEXT (f_fpr) = record;
4960 DECL_FIELD_CONTEXT (f_ovf) = record;
4961 DECL_FIELD_CONTEXT (f_sav) = record;
4963 TREE_CHAIN (record) = type_decl;
4964 TYPE_NAME (record) = type_decl;
4965 TYPE_FIELDS (record) = f_gpr;
4966 TREE_CHAIN (f_gpr) = f_fpr;
4967 TREE_CHAIN (f_fpr) = f_ovf;
4968 TREE_CHAIN (f_ovf) = f_sav;
4970 layout_type (record);
4972 /* The correct type is an array type of one element. */
4973 return build_array_type (record, build_index_type (size_zero_node));
4976 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4979 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4989 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4992 /* Indicate to allocate space on the stack for varargs save area. */
4993 ix86_save_varrargs_registers = 1;
4994 /* We need 16-byte stack alignment to save SSE registers. If user
4995 asked for lower preferred_stack_boundary, lets just hope that he knows
4996 what he is doing and won't varargs SSE values.
4998 We also may end up assuming that only 64bit values are stored in SSE
4999 register let some floating point program work. */
5000 if (ix86_preferred_stack_boundary >= 128)
5001 cfun->stack_alignment_needed = 128;
5003 save_area = frame_pointer_rtx;
5004 set = get_varargs_alias_set ();
5006 for (i = cum->regno;
5008 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5011 mem = gen_rtx_MEM (Pmode,
5012 plus_constant (save_area, i * UNITS_PER_WORD));
5013 MEM_NOTRAP_P (mem) = 1;
5014 set_mem_alias_set (mem, set);
5015 emit_move_insn (mem, gen_rtx_REG (Pmode,
5016 x86_64_int_parameter_registers[i]));
5019 if (cum->sse_nregs && cfun->va_list_fpr_size)
5021 /* Now emit code to save SSE registers. The AX parameter contains number
5022 of SSE parameter registers used to call this function. We use
5023 sse_prologue_save insn template that produces computed jump across
5024 SSE saves. We need some preparation work to get this working. */
5026 label = gen_label_rtx ();
5027 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5029 /* Compute address to jump to :
5030 label - 5*eax + nnamed_sse_arguments*5 */
5031 tmp_reg = gen_reg_rtx (Pmode);
5032 nsse_reg = gen_reg_rtx (Pmode);
5033 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5034 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5035 gen_rtx_MULT (Pmode, nsse_reg,
5040 gen_rtx_CONST (DImode,
5041 gen_rtx_PLUS (DImode,
5043 GEN_INT (cum->sse_regno * 4))));
5045 emit_move_insn (nsse_reg, label_ref);
5046 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5048 /* Compute address of memory block we save into. We always use pointer
5049 pointing 127 bytes after first byte to store - this is needed to keep
5050 instruction size limited by 4 bytes. */
5051 tmp_reg = gen_reg_rtx (Pmode);
5052 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5053 plus_constant (save_area,
5054 8 * REGPARM_MAX + 127)));
5055 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5056 MEM_NOTRAP_P (mem) = 1;
5057 set_mem_alias_set (mem, set);
5058 set_mem_align (mem, BITS_PER_WORD);
5060 /* And finally do the dirty job! */
5061 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5062 GEN_INT (cum->sse_regno), label));
5067 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5069 alias_set_type set = get_varargs_alias_set ();
5072 for (i = cum->regno; i < REGPARM_MAX; i++)
5076 mem = gen_rtx_MEM (Pmode,
5077 plus_constant (virtual_incoming_args_rtx,
5078 i * UNITS_PER_WORD));
5079 MEM_NOTRAP_P (mem) = 1;
5080 set_mem_alias_set (mem, set);
5082 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5083 emit_move_insn (mem, reg);
5088 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5089 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5092 CUMULATIVE_ARGS next_cum;
5095 /* This argument doesn't appear to be used anymore. Which is good,
5096 because the old code here didn't suppress rtl generation. */
5097 gcc_assert (!no_rtl);
5102 fntype = TREE_TYPE (current_function_decl);
5104 /* For varargs, we do not want to skip the dummy va_dcl argument.
5105 For stdargs, we do want to skip the last named argument. */
5107 if (stdarg_p (fntype))
5108 function_arg_advance (&next_cum, mode, type, 1);
5110 if (TARGET_64BIT_MS_ABI)
5111 setup_incoming_varargs_ms_64 (&next_cum);
5113 setup_incoming_varargs_64 (&next_cum);
5116 /* Implement va_start. */
5119 ix86_va_start (tree valist, rtx nextarg)
5121 HOST_WIDE_INT words, n_gpr, n_fpr;
5122 tree f_gpr, f_fpr, f_ovf, f_sav;
5123 tree gpr, fpr, ovf, sav, t;
5126 /* Only 64bit target needs something special. */
5127 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5129 std_expand_builtin_va_start (valist, nextarg);
5133 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5134 f_fpr = TREE_CHAIN (f_gpr);
5135 f_ovf = TREE_CHAIN (f_fpr);
5136 f_sav = TREE_CHAIN (f_ovf);
5138 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5139 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5140 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5141 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5142 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5144 /* Count number of gp and fp argument registers used. */
5145 words = current_function_args_info.words;
5146 n_gpr = current_function_args_info.regno;
5147 n_fpr = current_function_args_info.sse_regno;
5149 if (cfun->va_list_gpr_size)
5151 type = TREE_TYPE (gpr);
5152 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5153 build_int_cst (type, n_gpr * 8));
5154 TREE_SIDE_EFFECTS (t) = 1;
5155 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5158 if (cfun->va_list_fpr_size)
5160 type = TREE_TYPE (fpr);
5161 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5162 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5163 TREE_SIDE_EFFECTS (t) = 1;
5164 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5167 /* Find the overflow area. */
5168 type = TREE_TYPE (ovf);
5169 t = make_tree (type, virtual_incoming_args_rtx);
5171 t = build2 (POINTER_PLUS_EXPR, type, t,
5172 size_int (words * UNITS_PER_WORD));
5173 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5174 TREE_SIDE_EFFECTS (t) = 1;
5175 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5177 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5179 /* Find the register save area.
5180 Prologue of the function save it right above stack frame. */
5181 type = TREE_TYPE (sav);
5182 t = make_tree (type, frame_pointer_rtx);
5183 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5184 TREE_SIDE_EFFECTS (t) = 1;
5185 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5189 /* Implement va_arg. */
5192 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5194 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5195 tree f_gpr, f_fpr, f_ovf, f_sav;
5196 tree gpr, fpr, ovf, sav, t;
5198 tree lab_false, lab_over = NULL_TREE;
5203 enum machine_mode nat_mode;
5205 /* Only 64bit target needs something special. */
5206 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5207 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5209 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5210 f_fpr = TREE_CHAIN (f_gpr);
5211 f_ovf = TREE_CHAIN (f_fpr);
5212 f_sav = TREE_CHAIN (f_ovf);
5214 valist = build_va_arg_indirect_ref (valist);
5215 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5216 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5217 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5218 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5220 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5222 type = build_pointer_type (type);
5223 size = int_size_in_bytes (type);
5224 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5226 nat_mode = type_natural_mode (type);
5227 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5228 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5230 /* Pull the value out of the saved registers. */
5232 addr = create_tmp_var (ptr_type_node, "addr");
5233 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5237 int needed_intregs, needed_sseregs;
5239 tree int_addr, sse_addr;
5241 lab_false = create_artificial_label ();
5242 lab_over = create_artificial_label ();
5244 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5246 need_temp = (!REG_P (container)
5247 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5248 || TYPE_ALIGN (type) > 128));
5250 /* In case we are passing structure, verify that it is consecutive block
5251 on the register save area. If not we need to do moves. */
5252 if (!need_temp && !REG_P (container))
5254 /* Verify that all registers are strictly consecutive */
5255 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5259 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5261 rtx slot = XVECEXP (container, 0, i);
5262 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5263 || INTVAL (XEXP (slot, 1)) != i * 16)
5271 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5273 rtx slot = XVECEXP (container, 0, i);
5274 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5275 || INTVAL (XEXP (slot, 1)) != i * 8)
5287 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5288 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5289 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5290 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5293 /* First ensure that we fit completely in registers. */
5296 t = build_int_cst (TREE_TYPE (gpr),
5297 (REGPARM_MAX - needed_intregs + 1) * 8);
5298 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5299 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5300 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5301 gimplify_and_add (t, pre_p);
5305 t = build_int_cst (TREE_TYPE (fpr),
5306 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5308 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5309 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5310 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5311 gimplify_and_add (t, pre_p);
5314 /* Compute index to start of area used for integer regs. */
5317 /* int_addr = gpr + sav; */
5318 t = fold_convert (sizetype, gpr);
5319 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5320 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5321 gimplify_and_add (t, pre_p);
5325 /* sse_addr = fpr + sav; */
5326 t = fold_convert (sizetype, fpr);
5327 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5328 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5329 gimplify_and_add (t, pre_p);
5334 tree temp = create_tmp_var (type, "va_arg_tmp");
5337 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5338 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5339 gimplify_and_add (t, pre_p);
5341 for (i = 0; i < XVECLEN (container, 0); i++)
5343 rtx slot = XVECEXP (container, 0, i);
5344 rtx reg = XEXP (slot, 0);
5345 enum machine_mode mode = GET_MODE (reg);
5346 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5347 tree addr_type = build_pointer_type (piece_type);
5350 tree dest_addr, dest;
5352 if (SSE_REGNO_P (REGNO (reg)))
5354 src_addr = sse_addr;
5355 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5359 src_addr = int_addr;
5360 src_offset = REGNO (reg) * 8;
5362 src_addr = fold_convert (addr_type, src_addr);
5363 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5364 size_int (src_offset));
5365 src = build_va_arg_indirect_ref (src_addr);
5367 dest_addr = fold_convert (addr_type, addr);
5368 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5369 size_int (INTVAL (XEXP (slot, 1))));
5370 dest = build_va_arg_indirect_ref (dest_addr);
5372 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5373 gimplify_and_add (t, pre_p);
5379 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5380 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5381 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5382 gimplify_and_add (t, pre_p);
5386 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5387 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5388 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5389 gimplify_and_add (t, pre_p);
5392 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5393 gimplify_and_add (t, pre_p);
5395 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5396 append_to_statement_list (t, pre_p);
5399 /* ... otherwise out of the overflow area. */
5401 /* Care for on-stack alignment if needed. */
5402 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5403 || integer_zerop (TYPE_SIZE (type)))
5407 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5408 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5409 size_int (align - 1));
5410 t = fold_convert (sizetype, t);
5411 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5413 t = fold_convert (TREE_TYPE (ovf), t);
5415 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5417 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5418 gimplify_and_add (t2, pre_p);
5420 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5421 size_int (rsize * UNITS_PER_WORD));
5422 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5423 gimplify_and_add (t, pre_p);
5427 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5428 append_to_statement_list (t, pre_p);
5431 ptrtype = build_pointer_type (type);
5432 addr = fold_convert (ptrtype, addr);
5435 addr = build_va_arg_indirect_ref (addr);
5436 return build_va_arg_indirect_ref (addr);
5439 /* Return nonzero if OPNUM's MEM should be matched
5440 in movabs* patterns. */
5443 ix86_check_movabs (rtx insn, int opnum)
5447 set = PATTERN (insn);
5448 if (GET_CODE (set) == PARALLEL)
5449 set = XVECEXP (set, 0, 0);
5450 gcc_assert (GET_CODE (set) == SET);
5451 mem = XEXP (set, opnum);
5452 while (GET_CODE (mem) == SUBREG)
5453 mem = SUBREG_REG (mem);
5454 gcc_assert (MEM_P (mem));
5455 return (volatile_ok || !MEM_VOLATILE_P (mem));
5458 /* Initialize the table of extra 80387 mathematical constants. */
5461 init_ext_80387_constants (void)
5463 static const char * cst[5] =
5465 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5466 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5467 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5468 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5469 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5473 for (i = 0; i < 5; i++)
5475 real_from_string (&ext_80387_constants_table[i], cst[i]);
5476 /* Ensure each constant is rounded to XFmode precision. */
5477 real_convert (&ext_80387_constants_table[i],
5478 XFmode, &ext_80387_constants_table[i]);
5481 ext_80387_constants_init = 1;
5484 /* Return true if the constant is something that can be loaded with
5485 a special instruction. */
5488 standard_80387_constant_p (rtx x)
5490 enum machine_mode mode = GET_MODE (x);
5494 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5497 if (x == CONST0_RTX (mode))
5499 if (x == CONST1_RTX (mode))
5502 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5504 /* For XFmode constants, try to find a special 80387 instruction when
5505 optimizing for size or on those CPUs that benefit from them. */
5507 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5511 if (! ext_80387_constants_init)
5512 init_ext_80387_constants ();
5514 for (i = 0; i < 5; i++)
5515 if (real_identical (&r, &ext_80387_constants_table[i]))
5519 /* Load of the constant -0.0 or -1.0 will be split as
5520 fldz;fchs or fld1;fchs sequence. */
5521 if (real_isnegzero (&r))
5523 if (real_identical (&r, &dconstm1))
5529 /* Return the opcode of the special instruction to be used to load
5533 standard_80387_constant_opcode (rtx x)
5535 switch (standard_80387_constant_p (x))
5559 /* Return the CONST_DOUBLE representing the 80387 constant that is
5560 loaded by the specified special instruction. The argument IDX
5561 matches the return value from standard_80387_constant_p. */
5564 standard_80387_constant_rtx (int idx)
5568 if (! ext_80387_constants_init)
5569 init_ext_80387_constants ();
5585 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5589 /* Return 1 if mode is a valid mode for sse. */
5591 standard_sse_mode_p (enum machine_mode mode)
5608 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5611 standard_sse_constant_p (rtx x)
5613 enum machine_mode mode = GET_MODE (x);
5615 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5617 if (vector_all_ones_operand (x, mode)
5618 && standard_sse_mode_p (mode))
5619 return TARGET_SSE2 ? 2 : -1;
5624 /* Return the opcode of the special instruction to be used to load
5628 standard_sse_constant_opcode (rtx insn, rtx x)
5630 switch (standard_sse_constant_p (x))
5633 if (get_attr_mode (insn) == MODE_V4SF)
5634 return "xorps\t%0, %0";
5635 else if (get_attr_mode (insn) == MODE_V2DF)
5636 return "xorpd\t%0, %0";
5638 return "pxor\t%0, %0";
5640 return "pcmpeqd\t%0, %0";
5645 /* Returns 1 if OP contains a symbol reference */
5648 symbolic_reference_mentioned_p (rtx op)
5653 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5656 fmt = GET_RTX_FORMAT (GET_CODE (op));
5657 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5663 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5664 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5668 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5675 /* Return 1 if it is appropriate to emit `ret' instructions in the
5676 body of a function. Do this only if the epilogue is simple, needing a
5677 couple of insns. Prior to reloading, we can't tell how many registers
5678 must be saved, so return 0 then. Return 0 if there is no frame
5679 marker to de-allocate. */
5682 ix86_can_use_return_insn_p (void)
5684 struct ix86_frame frame;
5686 if (! reload_completed || frame_pointer_needed)
5689 /* Don't allow more than 32 pop, since that's all we can do
5690 with one instruction. */
5691 if (current_function_pops_args
5692 && current_function_args_size >= 32768)
5695 ix86_compute_frame_layout (&frame);
5696 return frame.to_allocate == 0 && frame.nregs == 0;
5699 /* Value should be nonzero if functions must have frame pointers.
5700 Zero means the frame pointer need not be set up (and parms may
5701 be accessed via the stack pointer) in functions that seem suitable. */
5704 ix86_frame_pointer_required (void)
5706 /* If we accessed previous frames, then the generated code expects
5707 to be able to access the saved ebp value in our frame. */
5708 if (cfun->machine->accesses_prev_frame)
5711 /* Several x86 os'es need a frame pointer for other reasons,
5712 usually pertaining to setjmp. */
5713 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5716 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5717 the frame pointer by default. Turn it back on now if we've not
5718 got a leaf function. */
5719 if (TARGET_OMIT_LEAF_FRAME_POINTER
5720 && (!current_function_is_leaf
5721 || ix86_current_function_calls_tls_descriptor))
5724 if (current_function_profile)
5730 /* Record that the current function accesses previous call frames. */
5733 ix86_setup_frame_addresses (void)
5735 cfun->machine->accesses_prev_frame = 1;
5738 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5739 # define USE_HIDDEN_LINKONCE 1
5741 # define USE_HIDDEN_LINKONCE 0
5744 static int pic_labels_used;
5746 /* Fills in the label name that should be used for a pc thunk for
5747 the given register. */
5750 get_pc_thunk_name (char name[32], unsigned int regno)
5752 gcc_assert (!TARGET_64BIT);
5754 if (USE_HIDDEN_LINKONCE)
5755 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5757 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5761 /* This function generates code for -fpic that loads %ebx with
5762 the return address of the caller and then returns. */
5765 ix86_file_end (void)
5770 for (regno = 0; regno < 8; ++regno)
5774 if (! ((pic_labels_used >> regno) & 1))
5777 get_pc_thunk_name (name, regno);
5782 switch_to_section (darwin_sections[text_coal_section]);
5783 fputs ("\t.weak_definition\t", asm_out_file);
5784 assemble_name (asm_out_file, name);
5785 fputs ("\n\t.private_extern\t", asm_out_file);
5786 assemble_name (asm_out_file, name);
5787 fputs ("\n", asm_out_file);
5788 ASM_OUTPUT_LABEL (asm_out_file, name);
5792 if (USE_HIDDEN_LINKONCE)
5796 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5798 TREE_PUBLIC (decl) = 1;
5799 TREE_STATIC (decl) = 1;
5800 DECL_ONE_ONLY (decl) = 1;
5802 (*targetm.asm_out.unique_section) (decl, 0);
5803 switch_to_section (get_named_section (decl, NULL, 0));
5805 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5806 fputs ("\t.hidden\t", asm_out_file);
5807 assemble_name (asm_out_file, name);
5808 fputc ('\n', asm_out_file);
5809 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5813 switch_to_section (text_section);
5814 ASM_OUTPUT_LABEL (asm_out_file, name);
5817 xops[0] = gen_rtx_REG (SImode, regno);
5818 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5819 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5820 output_asm_insn ("ret", xops);
5823 if (NEED_INDICATE_EXEC_STACK)
5824 file_end_indicate_exec_stack ();
5827 /* Emit code for the SET_GOT patterns. */
5830 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5836 if (TARGET_VXWORKS_RTP && flag_pic)
5838 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5839 xops[2] = gen_rtx_MEM (Pmode,
5840 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5841 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5843 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5844 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5845 an unadorned address. */
5846 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5847 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5848 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5852 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5854 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5856 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5859 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5861 output_asm_insn ("call\t%a2", xops);
5864 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5865 is what will be referenced by the Mach-O PIC subsystem. */
5867 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5870 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5871 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5874 output_asm_insn ("pop{l}\t%0", xops);
5879 get_pc_thunk_name (name, REGNO (dest));
5880 pic_labels_used |= 1 << REGNO (dest);
5882 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5883 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5884 output_asm_insn ("call\t%X2", xops);
5885 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5886 is what will be referenced by the Mach-O PIC subsystem. */
5889 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5891 targetm.asm_out.internal_label (asm_out_file, "L",
5892 CODE_LABEL_NUMBER (label));
5899 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5900 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5902 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5907 /* Generate an "push" pattern for input ARG. */
5912 return gen_rtx_SET (VOIDmode,
5914 gen_rtx_PRE_DEC (Pmode,
5915 stack_pointer_rtx)),
5919 /* Return >= 0 if there is an unused call-clobbered register available
5920 for the entire function. */
5923 ix86_select_alt_pic_regnum (void)
5925 if (current_function_is_leaf && !current_function_profile
5926 && !ix86_current_function_calls_tls_descriptor)
5929 for (i = 2; i >= 0; --i)
5930 if (!df_regs_ever_live_p (i))
5934 return INVALID_REGNUM;
5937 /* Return 1 if we need to save REGNO. */
5939 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5941 if (pic_offset_table_rtx
5942 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5943 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
5944 || current_function_profile
5945 || current_function_calls_eh_return
5946 || current_function_uses_const_pool))
5948 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5953 if (current_function_calls_eh_return && maybe_eh_return)
5958 unsigned test = EH_RETURN_DATA_REGNO (i);
5959 if (test == INVALID_REGNUM)
5966 if (cfun->machine->force_align_arg_pointer
5967 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5970 return (df_regs_ever_live_p (regno)
5971 && !call_used_regs[regno]
5972 && !fixed_regs[regno]
5973 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5976 /* Return number of registers to be saved on the stack. */
5979 ix86_nsaved_regs (void)
5984 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5985 if (ix86_save_reg (regno, true))
5990 /* Return the offset between two registers, one to be eliminated, and the other
5991 its replacement, at the start of a routine. */
5994 ix86_initial_elimination_offset (int from, int to)
5996 struct ix86_frame frame;
5997 ix86_compute_frame_layout (&frame);
5999 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6000 return frame.hard_frame_pointer_offset;
6001 else if (from == FRAME_POINTER_REGNUM
6002 && to == HARD_FRAME_POINTER_REGNUM)
6003 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6006 gcc_assert (to == STACK_POINTER_REGNUM);
6008 if (from == ARG_POINTER_REGNUM)
6009 return frame.stack_pointer_offset;
6011 gcc_assert (from == FRAME_POINTER_REGNUM);
6012 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6016 /* Fill structure ix86_frame about frame of currently computed function. */
6019 ix86_compute_frame_layout (struct ix86_frame *frame)
6021 HOST_WIDE_INT total_size;
6022 unsigned int stack_alignment_needed;
6023 HOST_WIDE_INT offset;
6024 unsigned int preferred_alignment;
6025 HOST_WIDE_INT size = get_frame_size ();
6027 frame->nregs = ix86_nsaved_regs ();
6030 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
6031 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
6033 /* During reload iteration the amount of registers saved can change.
6034 Recompute the value as needed. Do not recompute when amount of registers
6035 didn't change as reload does multiple calls to the function and does not
6036 expect the decision to change within single iteration. */
6038 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6040 int count = frame->nregs;
6042 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6043 /* The fast prologue uses move instead of push to save registers. This
6044 is significantly longer, but also executes faster as modern hardware
6045 can execute the moves in parallel, but can't do that for push/pop.
6047 Be careful about choosing what prologue to emit: When function takes
6048 many instructions to execute we may use slow version as well as in
6049 case function is known to be outside hot spot (this is known with
6050 feedback only). Weight the size of function by number of registers
6051 to save as it is cheap to use one or two push instructions but very
6052 slow to use many of them. */
6054 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6055 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6056 || (flag_branch_probabilities
6057 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6058 cfun->machine->use_fast_prologue_epilogue = false;
6060 cfun->machine->use_fast_prologue_epilogue
6061 = !expensive_function_p (count);
6063 if (TARGET_PROLOGUE_USING_MOVE
6064 && cfun->machine->use_fast_prologue_epilogue)
6065 frame->save_regs_using_mov = true;
6067 frame->save_regs_using_mov = false;
6070 /* Skip return address and saved base pointer. */
6071 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6073 frame->hard_frame_pointer_offset = offset;
6075 /* Do some sanity checking of stack_alignment_needed and
6076 preferred_alignment, since i386 port is the only using those features
6077 that may break easily. */
6079 gcc_assert (!size || stack_alignment_needed);
6080 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6081 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6082 gcc_assert (stack_alignment_needed
6083 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6085 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6086 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6088 /* Register save area */
6089 offset += frame->nregs * UNITS_PER_WORD;
6092 if (ix86_save_varrargs_registers)
6094 offset += X86_64_VARARGS_SIZE;
6095 frame->va_arg_size = X86_64_VARARGS_SIZE;
6098 frame->va_arg_size = 0;
6100 /* Align start of frame for local function. */
6101 frame->padding1 = ((offset + stack_alignment_needed - 1)
6102 & -stack_alignment_needed) - offset;
6104 offset += frame->padding1;
6106 /* Frame pointer points here. */
6107 frame->frame_pointer_offset = offset;
6111 /* Add outgoing arguments area. Can be skipped if we eliminated
6112 all the function calls as dead code.
6113 Skipping is however impossible when function calls alloca. Alloca
6114 expander assumes that last current_function_outgoing_args_size
6115 of stack frame are unused. */
6116 if (ACCUMULATE_OUTGOING_ARGS
6117 && (!current_function_is_leaf || current_function_calls_alloca
6118 || ix86_current_function_calls_tls_descriptor))
6120 offset += current_function_outgoing_args_size;
6121 frame->outgoing_arguments_size = current_function_outgoing_args_size;
6124 frame->outgoing_arguments_size = 0;
6126 /* Align stack boundary. Only needed if we're calling another function
6128 if (!current_function_is_leaf || current_function_calls_alloca
6129 || ix86_current_function_calls_tls_descriptor)
6130 frame->padding2 = ((offset + preferred_alignment - 1)
6131 & -preferred_alignment) - offset;
6133 frame->padding2 = 0;
6135 offset += frame->padding2;
6137 /* We've reached end of stack frame. */
6138 frame->stack_pointer_offset = offset;
6140 /* Size prologue needs to allocate. */
6141 frame->to_allocate =
6142 (size + frame->padding1 + frame->padding2
6143 + frame->outgoing_arguments_size + frame->va_arg_size);
6145 if ((!frame->to_allocate && frame->nregs <= 1)
6146 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6147 frame->save_regs_using_mov = false;
6149 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6150 && current_function_is_leaf
6151 && !ix86_current_function_calls_tls_descriptor)
6153 frame->red_zone_size = frame->to_allocate;
6154 if (frame->save_regs_using_mov)
6155 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6156 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6157 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6160 frame->red_zone_size = 0;
6161 frame->to_allocate -= frame->red_zone_size;
6162 frame->stack_pointer_offset -= frame->red_zone_size;
6164 fprintf (stderr, "\n");
6165 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6166 fprintf (stderr, "size: %ld\n", (long)size);
6167 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6168 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6169 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6170 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6171 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6172 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6173 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6174 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6175 (long)frame->hard_frame_pointer_offset);
6176 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6177 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6178 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
6179 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6183 /* Emit code to save registers in the prologue. */
6186 ix86_emit_save_regs (void)
6191 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6192 if (ix86_save_reg (regno, true))
6194 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6195 RTX_FRAME_RELATED_P (insn) = 1;
6199 /* Emit code to save registers using MOV insns. First register
6200 is restored from POINTER + OFFSET. */
6202 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6207 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6208 if (ix86_save_reg (regno, true))
6210 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6212 gen_rtx_REG (Pmode, regno));
6213 RTX_FRAME_RELATED_P (insn) = 1;
6214 offset += UNITS_PER_WORD;
6218 /* Expand prologue or epilogue stack adjustment.
6219 The pattern exist to put a dependency on all ebp-based memory accesses.
6220 STYLE should be negative if instructions should be marked as frame related,
6221 zero if %r11 register is live and cannot be freely used and positive
6225 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6230 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6231 else if (x86_64_immediate_operand (offset, DImode))
6232 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6236 /* r11 is used by indirect sibcall return as well, set before the
6237 epilogue and used after the epilogue. ATM indirect sibcall
6238 shouldn't be used together with huge frame sizes in one
6239 function because of the frame_size check in sibcall.c. */
6241 r11 = gen_rtx_REG (DImode, R11_REG);
6242 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6244 RTX_FRAME_RELATED_P (insn) = 1;
6245 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6249 RTX_FRAME_RELATED_P (insn) = 1;
6252 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6255 ix86_internal_arg_pointer (void)
6257 bool has_force_align_arg_pointer =
6258 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6259 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6260 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6261 && DECL_NAME (current_function_decl)
6262 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6263 && DECL_FILE_SCOPE_P (current_function_decl))
6264 || ix86_force_align_arg_pointer
6265 || has_force_align_arg_pointer)
6267 /* Nested functions can't realign the stack due to a register
6269 if (DECL_CONTEXT (current_function_decl)
6270 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6272 if (ix86_force_align_arg_pointer)
6273 warning (0, "-mstackrealign ignored for nested functions");
6274 if (has_force_align_arg_pointer)
6275 error ("%s not supported for nested functions",
6276 ix86_force_align_arg_pointer_string);
6277 return virtual_incoming_args_rtx;
6279 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6280 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6283 return virtual_incoming_args_rtx;
6286 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6287 This is called from dwarf2out.c to emit call frame instructions
6288 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6290 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6292 rtx unspec = SET_SRC (pattern);
6293 gcc_assert (GET_CODE (unspec) == UNSPEC);
6297 case UNSPEC_REG_SAVE:
6298 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6299 SET_DEST (pattern));
6301 case UNSPEC_DEF_CFA:
6302 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6303 INTVAL (XVECEXP (unspec, 0, 0)));
6310 /* Expand the prologue into a bunch of separate insns. */
6313 ix86_expand_prologue (void)
6317 struct ix86_frame frame;
6318 HOST_WIDE_INT allocate;
6320 ix86_compute_frame_layout (&frame);
6322 if (cfun->machine->force_align_arg_pointer)
6326 /* Grab the argument pointer. */
6327 x = plus_constant (stack_pointer_rtx, 4);
6328 y = cfun->machine->force_align_arg_pointer;
6329 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6330 RTX_FRAME_RELATED_P (insn) = 1;
6332 /* The unwind info consists of two parts: install the fafp as the cfa,
6333 and record the fafp as the "save register" of the stack pointer.
6334 The later is there in order that the unwinder can see where it
6335 should restore the stack pointer across the and insn. */
6336 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6337 x = gen_rtx_SET (VOIDmode, y, x);
6338 RTX_FRAME_RELATED_P (x) = 1;
6339 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6341 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6342 RTX_FRAME_RELATED_P (y) = 1;
6343 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6344 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6345 REG_NOTES (insn) = x;
6347 /* Align the stack. */
6348 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6351 /* And here we cheat like madmen with the unwind info. We force the
6352 cfa register back to sp+4, which is exactly what it was at the
6353 start of the function. Re-pushing the return address results in
6354 the return at the same spot relative to the cfa, and thus is
6355 correct wrt the unwind info. */
6356 x = cfun->machine->force_align_arg_pointer;
6357 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6358 insn = emit_insn (gen_push (x));
6359 RTX_FRAME_RELATED_P (insn) = 1;
6362 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6363 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6364 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6365 REG_NOTES (insn) = x;
6368 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6369 slower on all targets. Also sdb doesn't like it. */
6371 if (frame_pointer_needed)
6373 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6374 RTX_FRAME_RELATED_P (insn) = 1;
6376 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6377 RTX_FRAME_RELATED_P (insn) = 1;
6380 allocate = frame.to_allocate;
6382 if (!frame.save_regs_using_mov)
6383 ix86_emit_save_regs ();
6385 allocate += frame.nregs * UNITS_PER_WORD;
6387 /* When using red zone we may start register saving before allocating
6388 the stack frame saving one cycle of the prologue. However I will
6389 avoid doing this if I am going to have to probe the stack since
6390 at least on x86_64 the stack probe can turn into a call that clobbers
6391 a red zone location */
6392 if (TARGET_RED_ZONE && frame.save_regs_using_mov
6393 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6394 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6395 : stack_pointer_rtx,
6396 -frame.nregs * UNITS_PER_WORD);
6400 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6401 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6402 GEN_INT (-allocate), -1);
6405 /* Only valid for Win32. */
6406 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6410 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6412 if (TARGET_64BIT_MS_ABI)
6415 eax_live = ix86_eax_live_at_start_p ();
6419 emit_insn (gen_push (eax));
6420 allocate -= UNITS_PER_WORD;
6423 emit_move_insn (eax, GEN_INT (allocate));
6426 insn = gen_allocate_stack_worker_64 (eax);
6428 insn = gen_allocate_stack_worker_32 (eax);
6429 insn = emit_insn (insn);
6430 RTX_FRAME_RELATED_P (insn) = 1;
6431 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6432 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6433 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6434 t, REG_NOTES (insn));
6438 if (frame_pointer_needed)
6439 t = plus_constant (hard_frame_pointer_rtx,
6442 - frame.nregs * UNITS_PER_WORD);
6444 t = plus_constant (stack_pointer_rtx, allocate);
6445 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6449 if (frame.save_regs_using_mov
6450 && !(TARGET_RED_ZONE
6451 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6453 if (!frame_pointer_needed || !frame.to_allocate)
6454 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6456 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6457 -frame.nregs * UNITS_PER_WORD);
6460 pic_reg_used = false;
6461 if (pic_offset_table_rtx
6462 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6463 || current_function_profile))
6465 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6467 if (alt_pic_reg_used != INVALID_REGNUM)
6468 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6470 pic_reg_used = true;
6477 if (ix86_cmodel == CM_LARGE_PIC)
6479 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6480 rtx label = gen_label_rtx ();
6482 LABEL_PRESERVE_P (label) = 1;
6483 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6484 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6485 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6486 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6487 pic_offset_table_rtx, tmp_reg));
6490 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6493 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6496 /* Prevent function calls from being scheduled before the call to mcount.
6497 In the pic_reg_used case, make sure that the got load isn't deleted. */
6498 if (current_function_profile)
6501 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6502 emit_insn (gen_blockage ());
6506 /* Emit code to restore saved registers using MOV insns. First register
6507 is restored from POINTER + OFFSET. */
6509 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6510 int maybe_eh_return)
6513 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6515 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6516 if (ix86_save_reg (regno, maybe_eh_return))
6518 /* Ensure that adjust_address won't be forced to produce pointer
6519 out of range allowed by x86-64 instruction set. */
6520 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6524 r11 = gen_rtx_REG (DImode, R11_REG);
6525 emit_move_insn (r11, GEN_INT (offset));
6526 emit_insn (gen_adddi3 (r11, r11, pointer));
6527 base_address = gen_rtx_MEM (Pmode, r11);
6530 emit_move_insn (gen_rtx_REG (Pmode, regno),
6531 adjust_address (base_address, Pmode, offset));
6532 offset += UNITS_PER_WORD;
6536 /* Restore function stack, frame, and registers. */
6539 ix86_expand_epilogue (int style)
6542 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6543 struct ix86_frame frame;
6544 HOST_WIDE_INT offset;
6546 ix86_compute_frame_layout (&frame);
6548 /* Calculate start of saved registers relative to ebp. Special care
6549 must be taken for the normal return case of a function using
6550 eh_return: the eax and edx registers are marked as saved, but not
6551 restored along this path. */
6552 offset = frame.nregs;
6553 if (current_function_calls_eh_return && style != 2)
6555 offset *= -UNITS_PER_WORD;
6557 /* If we're only restoring one register and sp is not valid then
6558 using a move instruction to restore the register since it's
6559 less work than reloading sp and popping the register.
6561 The default code result in stack adjustment using add/lea instruction,
6562 while this code results in LEAVE instruction (or discrete equivalent),
6563 so it is profitable in some other cases as well. Especially when there
6564 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6565 and there is exactly one register to pop. This heuristic may need some
6566 tuning in future. */
6567 if ((!sp_valid && frame.nregs <= 1)
6568 || (TARGET_EPILOGUE_USING_MOVE
6569 && cfun->machine->use_fast_prologue_epilogue
6570 && (frame.nregs > 1 || frame.to_allocate))
6571 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6572 || (frame_pointer_needed && TARGET_USE_LEAVE
6573 && cfun->machine->use_fast_prologue_epilogue
6574 && frame.nregs == 1)
6575 || current_function_calls_eh_return)
6577 /* Restore registers. We can use ebp or esp to address the memory
6578 locations. If both are available, default to ebp, since offsets
6579 are known to be small. Only exception is esp pointing directly to the
6580 end of block of saved registers, where we may simplify addressing
6583 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6584 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6585 frame.to_allocate, style == 2);
6587 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6588 offset, style == 2);
6590 /* eh_return epilogues need %ecx added to the stack pointer. */
6593 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6595 if (frame_pointer_needed)
6597 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6598 tmp = plus_constant (tmp, UNITS_PER_WORD);
6599 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6601 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6602 emit_move_insn (hard_frame_pointer_rtx, tmp);
6604 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6609 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6610 tmp = plus_constant (tmp, (frame.to_allocate
6611 + frame.nregs * UNITS_PER_WORD));
6612 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6615 else if (!frame_pointer_needed)
6616 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6617 GEN_INT (frame.to_allocate
6618 + frame.nregs * UNITS_PER_WORD),
6620 /* If not an i386, mov & pop is faster than "leave". */
6621 else if (TARGET_USE_LEAVE || optimize_size
6622 || !cfun->machine->use_fast_prologue_epilogue)
6623 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6626 pro_epilogue_adjust_stack (stack_pointer_rtx,
6627 hard_frame_pointer_rtx,
6630 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6632 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6637 /* First step is to deallocate the stack frame so that we can
6638 pop the registers. */
6641 gcc_assert (frame_pointer_needed);
6642 pro_epilogue_adjust_stack (stack_pointer_rtx,
6643 hard_frame_pointer_rtx,
6644 GEN_INT (offset), style);
6646 else if (frame.to_allocate)
6647 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6648 GEN_INT (frame.to_allocate), style);
6650 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6651 if (ix86_save_reg (regno, false))
6654 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6656 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6658 if (frame_pointer_needed)
6660 /* Leave results in shorter dependency chains on CPUs that are
6661 able to grok it fast. */
6662 if (TARGET_USE_LEAVE)
6663 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6664 else if (TARGET_64BIT)
6665 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6667 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6671 if (cfun->machine->force_align_arg_pointer)
6673 emit_insn (gen_addsi3 (stack_pointer_rtx,
6674 cfun->machine->force_align_arg_pointer,
6678 /* Sibcall epilogues don't want a return instruction. */
6682 if (current_function_pops_args && current_function_args_size)
6684 rtx popc = GEN_INT (current_function_pops_args);
6686 /* i386 can only pop 64K bytes. If asked to pop more, pop
6687 return address, do explicit add, and jump indirectly to the
6690 if (current_function_pops_args >= 65536)
6692 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6694 /* There is no "pascal" calling convention in any 64bit ABI. */
6695 gcc_assert (!TARGET_64BIT);
6697 emit_insn (gen_popsi1 (ecx));
6698 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6699 emit_jump_insn (gen_return_indirect_internal (ecx));
6702 emit_jump_insn (gen_return_pop_internal (popc));
6705 emit_jump_insn (gen_return_internal ());
6708 /* Reset from the function's potential modifications. */
6711 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6712 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6714 if (pic_offset_table_rtx)
6715 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6717 /* Mach-O doesn't support labels at the end of objects, so if
6718 it looks like we might want one, insert a NOP. */
6720 rtx insn = get_last_insn ();
6723 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6724 insn = PREV_INSN (insn);
6728 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6729 fputs ("\tnop\n", file);
6735 /* Extract the parts of an RTL expression that is a valid memory address
6736 for an instruction. Return 0 if the structure of the address is
6737 grossly off. Return -1 if the address contains ASHIFT, so it is not
6738 strictly valid, but still used for computing length of lea instruction. */
6741 ix86_decompose_address (rtx addr, struct ix86_address *out)
6743 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6744 rtx base_reg, index_reg;
6745 HOST_WIDE_INT scale = 1;
6746 rtx scale_rtx = NULL_RTX;
6748 enum ix86_address_seg seg = SEG_DEFAULT;
6750 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6752 else if (GET_CODE (addr) == PLUS)
6762 addends[n++] = XEXP (op, 1);
6765 while (GET_CODE (op) == PLUS);
6770 for (i = n; i >= 0; --i)
6773 switch (GET_CODE (op))
6778 index = XEXP (op, 0);
6779 scale_rtx = XEXP (op, 1);
6783 if (XINT (op, 1) == UNSPEC_TP
6784 && TARGET_TLS_DIRECT_SEG_REFS
6785 && seg == SEG_DEFAULT)
6786 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6815 else if (GET_CODE (addr) == MULT)
6817 index = XEXP (addr, 0); /* index*scale */
6818 scale_rtx = XEXP (addr, 1);
6820 else if (GET_CODE (addr) == ASHIFT)
6824 /* We're called for lea too, which implements ashift on occasion. */
6825 index = XEXP (addr, 0);
6826 tmp = XEXP (addr, 1);
6827 if (!CONST_INT_P (tmp))
6829 scale = INTVAL (tmp);
6830 if ((unsigned HOST_WIDE_INT) scale > 3)
6836 disp = addr; /* displacement */
6838 /* Extract the integral value of scale. */
6841 if (!CONST_INT_P (scale_rtx))
6843 scale = INTVAL (scale_rtx);
6846 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6847 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6849 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6850 if (base_reg && index_reg && scale == 1
6851 && (index_reg == arg_pointer_rtx
6852 || index_reg == frame_pointer_rtx
6853 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6856 tmp = base, base = index, index = tmp;
6857 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6860 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6861 if ((base_reg == hard_frame_pointer_rtx
6862 || base_reg == frame_pointer_rtx
6863 || base_reg == arg_pointer_rtx) && !disp)
6866 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6867 Avoid this by transforming to [%esi+0]. */
6868 if (TARGET_K6 && !optimize_size
6869 && base_reg && !index_reg && !disp
6871 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6874 /* Special case: encode reg+reg instead of reg*2. */
6875 if (!base && index && scale && scale == 2)
6876 base = index, base_reg = index_reg, scale = 1;
6878 /* Special case: scaling cannot be encoded without base or displacement. */
6879 if (!base && !disp && index && scale != 1)
6891 /* Return cost of the memory address x.
6892 For i386, it is better to use a complex address than let gcc copy
6893 the address into a reg and make a new pseudo. But not if the address
6894 requires to two regs - that would mean more pseudos with longer
6897 ix86_address_cost (rtx x)
6899 struct ix86_address parts;
6901 int ok = ix86_decompose_address (x, &parts);
6905 if (parts.base && GET_CODE (parts.base) == SUBREG)
6906 parts.base = SUBREG_REG (parts.base);
6907 if (parts.index && GET_CODE (parts.index) == SUBREG)
6908 parts.index = SUBREG_REG (parts.index);
6910 /* Attempt to minimize number of registers in the address. */
6912 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6914 && (!REG_P (parts.index)
6915 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6919 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6921 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6922 && parts.base != parts.index)
6925 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6926 since it's predecode logic can't detect the length of instructions
6927 and it degenerates to vector decoded. Increase cost of such
6928 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6929 to split such addresses or even refuse such addresses at all.
6931 Following addressing modes are affected:
6936 The first and last case may be avoidable by explicitly coding the zero in
6937 memory address, but I don't have AMD-K6 machine handy to check this
6941 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6942 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6943 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6949 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6950 this is used for to form addresses to local data when -fPIC is in
6954 darwin_local_data_pic (rtx disp)
6956 if (GET_CODE (disp) == MINUS)
6958 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6959 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6960 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6962 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6963 if (! strcmp (sym_name, "<pic base>"))
6971 /* Determine if a given RTX is a valid constant. We already know this
6972 satisfies CONSTANT_P. */
6975 legitimate_constant_p (rtx x)
6977 switch (GET_CODE (x))
6982 if (GET_CODE (x) == PLUS)
6984 if (!CONST_INT_P (XEXP (x, 1)))
6989 if (TARGET_MACHO && darwin_local_data_pic (x))
6992 /* Only some unspecs are valid as "constants". */
6993 if (GET_CODE (x) == UNSPEC)
6994 switch (XINT (x, 1))
6999 return TARGET_64BIT;
7002 x = XVECEXP (x, 0, 0);
7003 return (GET_CODE (x) == SYMBOL_REF
7004 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7006 x = XVECEXP (x, 0, 0);
7007 return (GET_CODE (x) == SYMBOL_REF
7008 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7013 /* We must have drilled down to a symbol. */
7014 if (GET_CODE (x) == LABEL_REF)
7016 if (GET_CODE (x) != SYMBOL_REF)
7021 /* TLS symbols are never valid. */
7022 if (SYMBOL_REF_TLS_MODEL (x))
7025 /* DLLIMPORT symbols are never valid. */
7026 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7027 && SYMBOL_REF_DLLIMPORT_P (x))
7032 if (GET_MODE (x) == TImode
7033 && x != CONST0_RTX (TImode)
7039 if (x == CONST0_RTX (GET_MODE (x)))
7047 /* Otherwise we handle everything else in the move patterns. */
7051 /* Determine if it's legal to put X into the constant pool. This
7052 is not possible for the address of thread-local symbols, which
7053 is checked above. */
7056 ix86_cannot_force_const_mem (rtx x)
7058 /* We can always put integral constants and vectors in memory. */
7059 switch (GET_CODE (x))
7069 return !legitimate_constant_p (x);
7072 /* Determine if a given RTX is a valid constant address. */
7075 constant_address_p (rtx x)
7077 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7080 /* Nonzero if the constant value X is a legitimate general operand
7081 when generating PIC code. It is given that flag_pic is on and
7082 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7085 legitimate_pic_operand_p (rtx x)
7089 switch (GET_CODE (x))
7092 inner = XEXP (x, 0);
7093 if (GET_CODE (inner) == PLUS
7094 && CONST_INT_P (XEXP (inner, 1)))
7095 inner = XEXP (inner, 0);
7097 /* Only some unspecs are valid as "constants". */
7098 if (GET_CODE (inner) == UNSPEC)
7099 switch (XINT (inner, 1))
7104 return TARGET_64BIT;
7106 x = XVECEXP (inner, 0, 0);
7107 return (GET_CODE (x) == SYMBOL_REF
7108 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7116 return legitimate_pic_address_disp_p (x);
7123 /* Determine if a given CONST RTX is a valid memory displacement
7127 legitimate_pic_address_disp_p (rtx disp)
7131 /* In 64bit mode we can allow direct addresses of symbols and labels
7132 when they are not dynamic symbols. */
7135 rtx op0 = disp, op1;
7137 switch (GET_CODE (disp))
7143 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7145 op0 = XEXP (XEXP (disp, 0), 0);
7146 op1 = XEXP (XEXP (disp, 0), 1);
7147 if (!CONST_INT_P (op1)
7148 || INTVAL (op1) >= 16*1024*1024
7149 || INTVAL (op1) < -16*1024*1024)
7151 if (GET_CODE (op0) == LABEL_REF)
7153 if (GET_CODE (op0) != SYMBOL_REF)
7158 /* TLS references should always be enclosed in UNSPEC. */
7159 if (SYMBOL_REF_TLS_MODEL (op0))
7161 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7162 && ix86_cmodel != CM_LARGE_PIC)
7170 if (GET_CODE (disp) != CONST)
7172 disp = XEXP (disp, 0);
7176 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7177 of GOT tables. We should not need these anyway. */
7178 if (GET_CODE (disp) != UNSPEC
7179 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7180 && XINT (disp, 1) != UNSPEC_GOTOFF
7181 && XINT (disp, 1) != UNSPEC_PLTOFF))
7184 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7185 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7191 if (GET_CODE (disp) == PLUS)
7193 if (!CONST_INT_P (XEXP (disp, 1)))
7195 disp = XEXP (disp, 0);
7199 if (TARGET_MACHO && darwin_local_data_pic (disp))
7202 if (GET_CODE (disp) != UNSPEC)
7205 switch (XINT (disp, 1))
7210 /* We need to check for both symbols and labels because VxWorks loads
7211 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7213 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7214 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7216 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7217 While ABI specify also 32bit relocation but we don't produce it in
7218 small PIC model at all. */
7219 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7220 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7222 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7224 case UNSPEC_GOTTPOFF:
7225 case UNSPEC_GOTNTPOFF:
7226 case UNSPEC_INDNTPOFF:
7229 disp = XVECEXP (disp, 0, 0);
7230 return (GET_CODE (disp) == SYMBOL_REF
7231 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7233 disp = XVECEXP (disp, 0, 0);
7234 return (GET_CODE (disp) == SYMBOL_REF
7235 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7237 disp = XVECEXP (disp, 0, 0);
7238 return (GET_CODE (disp) == SYMBOL_REF
7239 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7245 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7246 memory address for an instruction. The MODE argument is the machine mode
7247 for the MEM expression that wants to use this address.
7249 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7250 convert common non-canonical forms to canonical form so that they will
7254 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7255 rtx addr, int strict)
7257 struct ix86_address parts;
7258 rtx base, index, disp;
7259 HOST_WIDE_INT scale;
7260 const char *reason = NULL;
7261 rtx reason_rtx = NULL_RTX;
7263 if (ix86_decompose_address (addr, &parts) <= 0)
7265 reason = "decomposition failed";
7270 index = parts.index;
7272 scale = parts.scale;
7274 /* Validate base register.
7276 Don't allow SUBREG's that span more than a word here. It can lead to spill
7277 failures when the base is one word out of a two word structure, which is
7278 represented internally as a DImode int. */
7287 else if (GET_CODE (base) == SUBREG
7288 && REG_P (SUBREG_REG (base))
7289 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7291 reg = SUBREG_REG (base);
7294 reason = "base is not a register";
7298 if (GET_MODE (base) != Pmode)
7300 reason = "base is not in Pmode";
7304 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7305 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7307 reason = "base is not valid";
7312 /* Validate index register.
7314 Don't allow SUBREG's that span more than a word here -- same as above. */
7323 else if (GET_CODE (index) == SUBREG
7324 && REG_P (SUBREG_REG (index))
7325 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7327 reg = SUBREG_REG (index);
7330 reason = "index is not a register";
7334 if (GET_MODE (index) != Pmode)
7336 reason = "index is not in Pmode";
7340 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7341 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7343 reason = "index is not valid";
7348 /* Validate scale factor. */
7351 reason_rtx = GEN_INT (scale);
7354 reason = "scale without index";
7358 if (scale != 2 && scale != 4 && scale != 8)
7360 reason = "scale is not a valid multiplier";
7365 /* Validate displacement. */
7370 if (GET_CODE (disp) == CONST
7371 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7372 switch (XINT (XEXP (disp, 0), 1))
7374 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7375 used. While ABI specify also 32bit relocations, we don't produce
7376 them at all and use IP relative instead. */
7379 gcc_assert (flag_pic);
7381 goto is_legitimate_pic;
7382 reason = "64bit address unspec";
7385 case UNSPEC_GOTPCREL:
7386 gcc_assert (flag_pic);
7387 goto is_legitimate_pic;
7389 case UNSPEC_GOTTPOFF:
7390 case UNSPEC_GOTNTPOFF:
7391 case UNSPEC_INDNTPOFF:
7397 reason = "invalid address unspec";
7401 else if (SYMBOLIC_CONST (disp)
7405 && MACHOPIC_INDIRECT
7406 && !machopic_operand_p (disp)
7412 if (TARGET_64BIT && (index || base))
7414 /* foo@dtpoff(%rX) is ok. */
7415 if (GET_CODE (disp) != CONST
7416 || GET_CODE (XEXP (disp, 0)) != PLUS
7417 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7418 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7419 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7420 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7422 reason = "non-constant pic memory reference";
7426 else if (! legitimate_pic_address_disp_p (disp))
7428 reason = "displacement is an invalid pic construct";
7432 /* This code used to verify that a symbolic pic displacement
7433 includes the pic_offset_table_rtx register.
7435 While this is good idea, unfortunately these constructs may
7436 be created by "adds using lea" optimization for incorrect
7445 This code is nonsensical, but results in addressing
7446 GOT table with pic_offset_table_rtx base. We can't
7447 just refuse it easily, since it gets matched by
7448 "addsi3" pattern, that later gets split to lea in the
7449 case output register differs from input. While this
7450 can be handled by separate addsi pattern for this case
7451 that never results in lea, this seems to be easier and
7452 correct fix for crash to disable this test. */
7454 else if (GET_CODE (disp) != LABEL_REF
7455 && !CONST_INT_P (disp)
7456 && (GET_CODE (disp) != CONST
7457 || !legitimate_constant_p (disp))
7458 && (GET_CODE (disp) != SYMBOL_REF
7459 || !legitimate_constant_p (disp)))
7461 reason = "displacement is not constant";
7464 else if (TARGET_64BIT
7465 && !x86_64_immediate_operand (disp, VOIDmode))
7467 reason = "displacement is out of range";
7472 /* Everything looks valid. */
7479 /* Return a unique alias set for the GOT. */
7481 static alias_set_type
7482 ix86_GOT_alias_set (void)
7484 static alias_set_type set = -1;
7486 set = new_alias_set ();
7490 /* Return a legitimate reference for ORIG (an address) using the
7491 register REG. If REG is 0, a new pseudo is generated.
7493 There are two types of references that must be handled:
7495 1. Global data references must load the address from the GOT, via
7496 the PIC reg. An insn is emitted to do this load, and the reg is
7499 2. Static data references, constant pool addresses, and code labels
7500 compute the address as an offset from the GOT, whose base is in
7501 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7502 differentiate them from global data objects. The returned
7503 address is the PIC reg + an unspec constant.
7505 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7506 reg also appears in the address. */
7509 legitimize_pic_address (rtx orig, rtx reg)
7516 if (TARGET_MACHO && !TARGET_64BIT)
7519 reg = gen_reg_rtx (Pmode);
7520 /* Use the generic Mach-O PIC machinery. */
7521 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7525 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7527 else if (TARGET_64BIT
7528 && ix86_cmodel != CM_SMALL_PIC
7529 && gotoff_operand (addr, Pmode))
7532 /* This symbol may be referenced via a displacement from the PIC
7533 base address (@GOTOFF). */
7535 if (reload_in_progress)
7536 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7537 if (GET_CODE (addr) == CONST)
7538 addr = XEXP (addr, 0);
7539 if (GET_CODE (addr) == PLUS)
7541 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7543 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7546 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7547 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7549 tmpreg = gen_reg_rtx (Pmode);
7552 emit_move_insn (tmpreg, new_rtx);
7556 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7557 tmpreg, 1, OPTAB_DIRECT);
7560 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7562 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7564 /* This symbol may be referenced via a displacement from the PIC
7565 base address (@GOTOFF). */
7567 if (reload_in_progress)
7568 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7569 if (GET_CODE (addr) == CONST)
7570 addr = XEXP (addr, 0);
7571 if (GET_CODE (addr) == PLUS)
7573 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7575 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7578 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7579 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7580 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7584 emit_move_insn (reg, new_rtx);
7588 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7589 /* We can't use @GOTOFF for text labels on VxWorks;
7590 see gotoff_operand. */
7591 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7593 /* Given that we've already handled dllimport variables separately
7594 in legitimize_address, and all other variables should satisfy
7595 legitimate_pic_address_disp_p, we should never arrive here. */
7596 gcc_assert (!TARGET_64BIT_MS_ABI);
7598 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7600 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7601 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7602 new_rtx = gen_const_mem (Pmode, new_rtx);
7603 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7606 reg = gen_reg_rtx (Pmode);
7607 /* Use directly gen_movsi, otherwise the address is loaded
7608 into register for CSE. We don't want to CSE this addresses,
7609 instead we CSE addresses from the GOT table, so skip this. */
7610 emit_insn (gen_movsi (reg, new_rtx));
7615 /* This symbol must be referenced via a load from the
7616 Global Offset Table (@GOT). */
7618 if (reload_in_progress)
7619 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7620 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7621 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7623 new_rtx = force_reg (Pmode, new_rtx);
7624 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7625 new_rtx = gen_const_mem (Pmode, new_rtx);
7626 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7629 reg = gen_reg_rtx (Pmode);
7630 emit_move_insn (reg, new_rtx);
7636 if (CONST_INT_P (addr)
7637 && !x86_64_immediate_operand (addr, VOIDmode))
7641 emit_move_insn (reg, addr);
7645 new_rtx = force_reg (Pmode, addr);
7647 else if (GET_CODE (addr) == CONST)
7649 addr = XEXP (addr, 0);
7651 /* We must match stuff we generate before. Assume the only
7652 unspecs that can get here are ours. Not that we could do
7653 anything with them anyway.... */
7654 if (GET_CODE (addr) == UNSPEC
7655 || (GET_CODE (addr) == PLUS
7656 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7658 gcc_assert (GET_CODE (addr) == PLUS);
7660 if (GET_CODE (addr) == PLUS)
7662 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7664 /* Check first to see if this is a constant offset from a @GOTOFF
7665 symbol reference. */
7666 if (gotoff_operand (op0, Pmode)
7667 && CONST_INT_P (op1))
7671 if (reload_in_progress)
7672 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7673 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7675 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7676 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7677 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7681 emit_move_insn (reg, new_rtx);
7687 if (INTVAL (op1) < -16*1024*1024
7688 || INTVAL (op1) >= 16*1024*1024)
7690 if (!x86_64_immediate_operand (op1, Pmode))
7691 op1 = force_reg (Pmode, op1);
7692 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7698 base = legitimize_pic_address (XEXP (addr, 0), reg);
7699 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7700 base == reg ? NULL_RTX : reg);
7702 if (CONST_INT_P (new_rtx))
7703 new_rtx = plus_constant (base, INTVAL (new_rtx));
7706 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7708 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7709 new_rtx = XEXP (new_rtx, 1);
7711 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7719 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7722 get_thread_pointer (int to_reg)
7726 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7730 reg = gen_reg_rtx (Pmode);
7731 insn = gen_rtx_SET (VOIDmode, reg, tp);
7732 insn = emit_insn (insn);
7737 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7738 false if we expect this to be used for a memory address and true if
7739 we expect to load the address into a register. */
7742 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7744 rtx dest, base, off, pic, tp;
7749 case TLS_MODEL_GLOBAL_DYNAMIC:
7750 dest = gen_reg_rtx (Pmode);
7751 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7753 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7755 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7758 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7759 insns = get_insns ();
7762 CONST_OR_PURE_CALL_P (insns) = 1;
7763 emit_libcall_block (insns, dest, rax, x);
7765 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7766 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7768 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7770 if (TARGET_GNU2_TLS)
7772 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7774 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7778 case TLS_MODEL_LOCAL_DYNAMIC:
7779 base = gen_reg_rtx (Pmode);
7780 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7782 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7784 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7787 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7788 insns = get_insns ();
7791 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7792 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7793 CONST_OR_PURE_CALL_P (insns) = 1;
7794 emit_libcall_block (insns, base, rax, note);
7796 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7797 emit_insn (gen_tls_local_dynamic_base_64 (base));
7799 emit_insn (gen_tls_local_dynamic_base_32 (base));
7801 if (TARGET_GNU2_TLS)
7803 rtx x = ix86_tls_module_base ();
7805 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7806 gen_rtx_MINUS (Pmode, x, tp));
7809 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7810 off = gen_rtx_CONST (Pmode, off);
7812 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7814 if (TARGET_GNU2_TLS)
7816 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7818 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7823 case TLS_MODEL_INITIAL_EXEC:
7827 type = UNSPEC_GOTNTPOFF;
7831 if (reload_in_progress)
7832 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7833 pic = pic_offset_table_rtx;
7834 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7836 else if (!TARGET_ANY_GNU_TLS)
7838 pic = gen_reg_rtx (Pmode);
7839 emit_insn (gen_set_got (pic));
7840 type = UNSPEC_GOTTPOFF;
7845 type = UNSPEC_INDNTPOFF;
7848 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7849 off = gen_rtx_CONST (Pmode, off);
7851 off = gen_rtx_PLUS (Pmode, pic, off);
7852 off = gen_const_mem (Pmode, off);
7853 set_mem_alias_set (off, ix86_GOT_alias_set ());
7855 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7857 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7858 off = force_reg (Pmode, off);
7859 return gen_rtx_PLUS (Pmode, base, off);
7863 base = get_thread_pointer (true);
7864 dest = gen_reg_rtx (Pmode);
7865 emit_insn (gen_subsi3 (dest, base, off));
7869 case TLS_MODEL_LOCAL_EXEC:
7870 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7871 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7872 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7873 off = gen_rtx_CONST (Pmode, off);
7875 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7877 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7878 return gen_rtx_PLUS (Pmode, base, off);
7882 base = get_thread_pointer (true);
7883 dest = gen_reg_rtx (Pmode);
7884 emit_insn (gen_subsi3 (dest, base, off));
7895 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7898 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7899 htab_t dllimport_map;
7902 get_dllimport_decl (tree decl)
7904 struct tree_map *h, in;
7908 size_t namelen, prefixlen;
7914 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7916 in.hash = htab_hash_pointer (decl);
7917 in.base.from = decl;
7918 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7919 h = (struct tree_map *) *loc;
7923 *loc = h = GGC_NEW (struct tree_map);
7925 h->base.from = decl;
7926 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7927 DECL_ARTIFICIAL (to) = 1;
7928 DECL_IGNORED_P (to) = 1;
7929 DECL_EXTERNAL (to) = 1;
7930 TREE_READONLY (to) = 1;
7932 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7933 name = targetm.strip_name_encoding (name);
7934 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
7935 namelen = strlen (name);
7936 prefixlen = strlen (prefix);
7937 imp_name = (char *) alloca (namelen + prefixlen + 1);
7938 memcpy (imp_name, prefix, prefixlen);
7939 memcpy (imp_name + prefixlen, name, namelen + 1);
7941 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7942 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7943 SET_SYMBOL_REF_DECL (rtl, to);
7944 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7946 rtl = gen_const_mem (Pmode, rtl);
7947 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7949 SET_DECL_RTL (to, rtl);
7950 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
7955 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7956 true if we require the result be a register. */
7959 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7964 gcc_assert (SYMBOL_REF_DECL (symbol));
7965 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7967 x = DECL_RTL (imp_decl);
7969 x = force_reg (Pmode, x);
7973 /* Try machine-dependent ways of modifying an illegitimate address
7974 to be legitimate. If we find one, return the new, valid address.
7975 This macro is used in only one place: `memory_address' in explow.c.
7977 OLDX is the address as it was before break_out_memory_refs was called.
7978 In some cases it is useful to look at this to decide what needs to be done.
7980 MODE and WIN are passed so that this macro can use
7981 GO_IF_LEGITIMATE_ADDRESS.
7983 It is always safe for this macro to do nothing. It exists to recognize
7984 opportunities to optimize the output.
7986 For the 80386, we handle X+REG by loading X into a register R and
7987 using R+REG. R will go in a general reg and indexing will be used.
7988 However, if REG is a broken-out memory address or multiplication,
7989 nothing needs to be done because REG can certainly go in a general reg.
7991 When -fpic is used, special handling is needed for symbolic references.
7992 See comments by legitimize_pic_address in i386.c for details. */
7995 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8000 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8002 return legitimize_tls_address (x, (enum tls_model) log, false);
8003 if (GET_CODE (x) == CONST
8004 && GET_CODE (XEXP (x, 0)) == PLUS
8005 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8006 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8008 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8009 (enum tls_model) log, false);
8010 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8013 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8015 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8016 return legitimize_dllimport_symbol (x, true);
8017 if (GET_CODE (x) == CONST
8018 && GET_CODE (XEXP (x, 0)) == PLUS
8019 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8020 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8022 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8023 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8027 if (flag_pic && SYMBOLIC_CONST (x))
8028 return legitimize_pic_address (x, 0);
8030 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8031 if (GET_CODE (x) == ASHIFT
8032 && CONST_INT_P (XEXP (x, 1))
8033 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8036 log = INTVAL (XEXP (x, 1));
8037 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8038 GEN_INT (1 << log));
8041 if (GET_CODE (x) == PLUS)
8043 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8045 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8046 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8047 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8050 log = INTVAL (XEXP (XEXP (x, 0), 1));
8051 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8052 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8053 GEN_INT (1 << log));
8056 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8057 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8058 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8061 log = INTVAL (XEXP (XEXP (x, 1), 1));
8062 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8063 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8064 GEN_INT (1 << log));
8067 /* Put multiply first if it isn't already. */
8068 if (GET_CODE (XEXP (x, 1)) == MULT)
8070 rtx tmp = XEXP (x, 0);
8071 XEXP (x, 0) = XEXP (x, 1);
8076 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8077 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8078 created by virtual register instantiation, register elimination, and
8079 similar optimizations. */
8080 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8083 x = gen_rtx_PLUS (Pmode,
8084 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8085 XEXP (XEXP (x, 1), 0)),
8086 XEXP (XEXP (x, 1), 1));
8090 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8091 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8092 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8093 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8094 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8095 && CONSTANT_P (XEXP (x, 1)))
8098 rtx other = NULL_RTX;
8100 if (CONST_INT_P (XEXP (x, 1)))
8102 constant = XEXP (x, 1);
8103 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8105 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8107 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8108 other = XEXP (x, 1);
8116 x = gen_rtx_PLUS (Pmode,
8117 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8118 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8119 plus_constant (other, INTVAL (constant)));
8123 if (changed && legitimate_address_p (mode, x, FALSE))
8126 if (GET_CODE (XEXP (x, 0)) == MULT)
8129 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8132 if (GET_CODE (XEXP (x, 1)) == MULT)
8135 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8139 && REG_P (XEXP (x, 1))
8140 && REG_P (XEXP (x, 0)))
8143 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8146 x = legitimize_pic_address (x, 0);
8149 if (changed && legitimate_address_p (mode, x, FALSE))
8152 if (REG_P (XEXP (x, 0)))
8154 rtx temp = gen_reg_rtx (Pmode);
8155 rtx val = force_operand (XEXP (x, 1), temp);
8157 emit_move_insn (temp, val);
8163 else if (REG_P (XEXP (x, 1)))
8165 rtx temp = gen_reg_rtx (Pmode);
8166 rtx val = force_operand (XEXP (x, 0), temp);
8168 emit_move_insn (temp, val);
8178 /* Print an integer constant expression in assembler syntax. Addition
8179 and subtraction are the only arithmetic that may appear in these
8180 expressions. FILE is the stdio stream to write to, X is the rtx, and
8181 CODE is the operand print code from the output string. */
8184 output_pic_addr_const (FILE *file, rtx x, int code)
8188 switch (GET_CODE (x))
8191 gcc_assert (flag_pic);
8196 if (! TARGET_MACHO || TARGET_64BIT)
8197 output_addr_const (file, x);
8200 const char *name = XSTR (x, 0);
8202 /* Mark the decl as referenced so that cgraph will
8203 output the function. */
8204 if (SYMBOL_REF_DECL (x))
8205 mark_decl_referenced (SYMBOL_REF_DECL (x));
8208 if (MACHOPIC_INDIRECT
8209 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8210 name = machopic_indirection_name (x, /*stub_p=*/true);
8212 assemble_name (file, name);
8214 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8215 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8216 fputs ("@PLT", file);
8223 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8224 assemble_name (asm_out_file, buf);
8228 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8232 /* This used to output parentheses around the expression,
8233 but that does not work on the 386 (either ATT or BSD assembler). */
8234 output_pic_addr_const (file, XEXP (x, 0), code);
8238 if (GET_MODE (x) == VOIDmode)
8240 /* We can use %d if the number is <32 bits and positive. */
8241 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8242 fprintf (file, "0x%lx%08lx",
8243 (unsigned long) CONST_DOUBLE_HIGH (x),
8244 (unsigned long) CONST_DOUBLE_LOW (x));
8246 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8249 /* We can't handle floating point constants;
8250 PRINT_OPERAND must handle them. */
8251 output_operand_lossage ("floating constant misused");
8255 /* Some assemblers need integer constants to appear first. */
8256 if (CONST_INT_P (XEXP (x, 0)))
8258 output_pic_addr_const (file, XEXP (x, 0), code);
8260 output_pic_addr_const (file, XEXP (x, 1), code);
8264 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8265 output_pic_addr_const (file, XEXP (x, 1), code);
8267 output_pic_addr_const (file, XEXP (x, 0), code);
8273 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8274 output_pic_addr_const (file, XEXP (x, 0), code);
8276 output_pic_addr_const (file, XEXP (x, 1), code);
8278 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8282 gcc_assert (XVECLEN (x, 0) == 1);
8283 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8284 switch (XINT (x, 1))
8287 fputs ("@GOT", file);
8290 fputs ("@GOTOFF", file);
8293 fputs ("@PLTOFF", file);
8295 case UNSPEC_GOTPCREL:
8296 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8297 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8299 case UNSPEC_GOTTPOFF:
8300 /* FIXME: This might be @TPOFF in Sun ld too. */
8301 fputs ("@GOTTPOFF", file);
8304 fputs ("@TPOFF", file);
8308 fputs ("@TPOFF", file);
8310 fputs ("@NTPOFF", file);
8313 fputs ("@DTPOFF", file);
8315 case UNSPEC_GOTNTPOFF:
8317 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8318 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8320 fputs ("@GOTNTPOFF", file);
8322 case UNSPEC_INDNTPOFF:
8323 fputs ("@INDNTPOFF", file);
8326 output_operand_lossage ("invalid UNSPEC as operand");
8332 output_operand_lossage ("invalid expression as operand");
8336 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8337 We need to emit DTP-relative relocations. */
8339 static void ATTRIBUTE_UNUSED
8340 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8342 fputs (ASM_LONG, file);
8343 output_addr_const (file, x);
8344 fputs ("@DTPOFF", file);
8350 fputs (", 0", file);
8357 /* In the name of slightly smaller debug output, and to cater to
8358 general assembler lossage, recognize PIC+GOTOFF and turn it back
8359 into a direct symbol reference.
8361 On Darwin, this is necessary to avoid a crash, because Darwin
8362 has a different PIC label for each routine but the DWARF debugging
8363 information is not associated with any particular routine, so it's
8364 necessary to remove references to the PIC label from RTL stored by
8365 the DWARF output code. */
8368 ix86_delegitimize_address (rtx orig_x)
8371 /* reg_addend is NULL or a multiple of some register. */
8372 rtx reg_addend = NULL_RTX;
8373 /* const_addend is NULL or a const_int. */
8374 rtx const_addend = NULL_RTX;
8375 /* This is the result, or NULL. */
8376 rtx result = NULL_RTX;
8383 if (GET_CODE (x) != CONST
8384 || GET_CODE (XEXP (x, 0)) != UNSPEC
8385 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8388 return XVECEXP (XEXP (x, 0), 0, 0);
8391 if (GET_CODE (x) != PLUS
8392 || GET_CODE (XEXP (x, 1)) != CONST)
8395 if (REG_P (XEXP (x, 0))
8396 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8397 /* %ebx + GOT/GOTOFF */
8399 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8401 /* %ebx + %reg * scale + GOT/GOTOFF */
8402 reg_addend = XEXP (x, 0);
8403 if (REG_P (XEXP (reg_addend, 0))
8404 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8405 reg_addend = XEXP (reg_addend, 1);
8406 else if (REG_P (XEXP (reg_addend, 1))
8407 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8408 reg_addend = XEXP (reg_addend, 0);
8411 if (!REG_P (reg_addend)
8412 && GET_CODE (reg_addend) != MULT
8413 && GET_CODE (reg_addend) != ASHIFT)
8419 x = XEXP (XEXP (x, 1), 0);
8420 if (GET_CODE (x) == PLUS
8421 && CONST_INT_P (XEXP (x, 1)))
8423 const_addend = XEXP (x, 1);
8427 if (GET_CODE (x) == UNSPEC
8428 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8429 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8430 result = XVECEXP (x, 0, 0);
8432 if (TARGET_MACHO && darwin_local_data_pic (x)
8434 result = XEXP (x, 0);
8440 result = gen_rtx_PLUS (Pmode, result, const_addend);
8442 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8446 /* If X is a machine specific address (i.e. a symbol or label being
8447 referenced as a displacement from the GOT implemented using an
8448 UNSPEC), then return the base term. Otherwise return X. */
8451 ix86_find_base_term (rtx x)
8457 if (GET_CODE (x) != CONST)
8460 if (GET_CODE (term) == PLUS
8461 && (CONST_INT_P (XEXP (term, 1))
8462 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8463 term = XEXP (term, 0);
8464 if (GET_CODE (term) != UNSPEC
8465 || XINT (term, 1) != UNSPEC_GOTPCREL)
8468 term = XVECEXP (term, 0, 0);
8470 if (GET_CODE (term) != SYMBOL_REF
8471 && GET_CODE (term) != LABEL_REF)
8477 term = ix86_delegitimize_address (x);
8479 if (GET_CODE (term) != SYMBOL_REF
8480 && GET_CODE (term) != LABEL_REF)
8487 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8492 if (mode == CCFPmode || mode == CCFPUmode)
8494 enum rtx_code second_code, bypass_code;
8495 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8496 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8497 code = ix86_fp_compare_code_to_integer (code);
8501 code = reverse_condition (code);
8552 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8556 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8557 Those same assemblers have the same but opposite lossage on cmov. */
8559 suffix = fp ? "nbe" : "a";
8560 else if (mode == CCCmode)
8583 gcc_assert (mode == CCmode || mode == CCCmode);
8605 gcc_assert (mode == CCmode || mode == CCCmode);
8606 suffix = fp ? "nb" : "ae";
8609 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8616 else if (mode == CCCmode)
8617 suffix = fp ? "nb" : "ae";
8622 suffix = fp ? "u" : "p";
8625 suffix = fp ? "nu" : "np";
8630 fputs (suffix, file);
8633 /* Print the name of register X to FILE based on its machine mode and number.
8634 If CODE is 'w', pretend the mode is HImode.
8635 If CODE is 'b', pretend the mode is QImode.
8636 If CODE is 'k', pretend the mode is SImode.
8637 If CODE is 'q', pretend the mode is DImode.
8638 If CODE is 'h', pretend the reg is the 'high' byte register.
8639 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8642 print_reg (rtx x, int code, FILE *file)
8644 gcc_assert (x == pc_rtx
8645 || (REGNO (x) != ARG_POINTER_REGNUM
8646 && REGNO (x) != FRAME_POINTER_REGNUM
8647 && REGNO (x) != FLAGS_REG
8648 && REGNO (x) != FPSR_REG
8649 && REGNO (x) != FPCR_REG));
8651 if (ASSEMBLER_DIALECT == ASM_ATT)
8656 gcc_assert (TARGET_64BIT);
8657 fputs ("rip", file);
8661 if (code == 'w' || MMX_REG_P (x))
8663 else if (code == 'b')
8665 else if (code == 'k')
8667 else if (code == 'q')
8669 else if (code == 'y')
8671 else if (code == 'h')
8674 code = GET_MODE_SIZE (GET_MODE (x));
8676 /* Irritatingly, AMD extended registers use different naming convention
8677 from the normal registers. */
8678 if (REX_INT_REG_P (x))
8680 gcc_assert (TARGET_64BIT);
8684 error ("extended registers have no high halves");
8687 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8690 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8693 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8696 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8699 error ("unsupported operand size for extended register");
8707 if (STACK_TOP_P (x))
8709 fputs ("st(0)", file);
8716 if (! ANY_FP_REG_P (x))
8717 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8722 fputs (hi_reg_name[REGNO (x)], file);
8725 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8727 fputs (qi_reg_name[REGNO (x)], file);
8730 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8732 fputs (qi_high_reg_name[REGNO (x)], file);
8739 /* Locate some local-dynamic symbol still in use by this function
8740 so that we can print its name in some tls_local_dynamic_base
8744 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8748 if (GET_CODE (x) == SYMBOL_REF
8749 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8751 cfun->machine->some_ld_name = XSTR (x, 0);
8759 get_some_local_dynamic_name (void)
8763 if (cfun->machine->some_ld_name)
8764 return cfun->machine->some_ld_name;
8766 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8768 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8769 return cfun->machine->some_ld_name;
8775 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8776 C -- print opcode suffix for set/cmov insn.
8777 c -- like C, but print reversed condition
8778 F,f -- likewise, but for floating-point.
8779 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8781 R -- print the prefix for register names.
8782 z -- print the opcode suffix for the size of the current operand.
8783 * -- print a star (in certain assembler syntax)
8784 A -- print an absolute memory reference.
8785 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8786 s -- print a shift double count, followed by the assemblers argument
8788 b -- print the QImode name of the register for the indicated operand.
8789 %b0 would print %al if operands[0] is reg 0.
8790 w -- likewise, print the HImode name of the register.
8791 k -- likewise, print the SImode name of the register.
8792 q -- likewise, print the DImode name of the register.
8793 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8794 y -- print "st(0)" instead of "st" as a register.
8795 D -- print condition for SSE cmp instruction.
8796 P -- if PIC, print an @PLT suffix.
8797 X -- don't print any sort of PIC '@' suffix for a symbol.
8798 & -- print some in-use local-dynamic symbol name.
8799 H -- print a memory address offset by 8; used for sse high-parts
8800 Y -- print condition for SSE5 com* instruction.
8801 + -- print a branch hint as 'cs' or 'ds' prefix
8802 ; -- print a semicolon (after prefixes due to bug in older gas).
8806 print_operand (FILE *file, rtx x, int code)
8813 if (ASSEMBLER_DIALECT == ASM_ATT)
8818 assemble_name (file, get_some_local_dynamic_name ());
8822 switch (ASSEMBLER_DIALECT)
8829 /* Intel syntax. For absolute addresses, registers should not
8830 be surrounded by braces. */
8834 PRINT_OPERAND (file, x, 0);
8844 PRINT_OPERAND (file, x, 0);
8849 if (ASSEMBLER_DIALECT == ASM_ATT)
8854 if (ASSEMBLER_DIALECT == ASM_ATT)
8859 if (ASSEMBLER_DIALECT == ASM_ATT)
8864 if (ASSEMBLER_DIALECT == ASM_ATT)
8869 if (ASSEMBLER_DIALECT == ASM_ATT)
8874 if (ASSEMBLER_DIALECT == ASM_ATT)
8879 /* 387 opcodes don't get size suffixes if the operands are
8881 if (STACK_REG_P (x))
8884 /* Likewise if using Intel opcodes. */
8885 if (ASSEMBLER_DIALECT == ASM_INTEL)
8888 /* This is the size of op from size of operand. */
8889 switch (GET_MODE_SIZE (GET_MODE (x)))
8898 #ifdef HAVE_GAS_FILDS_FISTS
8908 if (GET_MODE (x) == SFmode)
8923 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8925 #ifdef GAS_MNEMONICS
8951 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8953 PRINT_OPERAND (file, x, 0);
8959 /* Little bit of braindamage here. The SSE compare instructions
8960 does use completely different names for the comparisons that the
8961 fp conditional moves. */
8962 switch (GET_CODE (x))
8977 fputs ("unord", file);
8981 fputs ("neq", file);
8985 fputs ("nlt", file);
8989 fputs ("nle", file);
8992 fputs ("ord", file);
8999 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9000 if (ASSEMBLER_DIALECT == ASM_ATT)
9002 switch (GET_MODE (x))
9004 case HImode: putc ('w', file); break;
9006 case SFmode: putc ('l', file); break;
9008 case DFmode: putc ('q', file); break;
9009 default: gcc_unreachable ();
9016 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9019 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9020 if (ASSEMBLER_DIALECT == ASM_ATT)
9023 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9026 /* Like above, but reverse condition */
9028 /* Check to see if argument to %c is really a constant
9029 and not a condition code which needs to be reversed. */
9030 if (!COMPARISON_P (x))
9032 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9035 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9038 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9039 if (ASSEMBLER_DIALECT == ASM_ATT)
9042 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9046 /* It doesn't actually matter what mode we use here, as we're
9047 only going to use this for printing. */
9048 x = adjust_address_nv (x, DImode, 8);
9055 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9058 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9061 int pred_val = INTVAL (XEXP (x, 0));
9063 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9064 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9066 int taken = pred_val > REG_BR_PROB_BASE / 2;
9067 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9069 /* Emit hints only in the case default branch prediction
9070 heuristics would fail. */
9071 if (taken != cputaken)
9073 /* We use 3e (DS) prefix for taken branches and
9074 2e (CS) prefix for not taken branches. */
9076 fputs ("ds ; ", file);
9078 fputs ("cs ; ", file);
9086 switch (GET_CODE (x))
9089 fputs ("neq", file);
9096 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9100 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9111 fputs ("unord", file);
9114 fputs ("ord", file);
9117 fputs ("ueq", file);
9120 fputs ("nlt", file);
9123 fputs ("nle", file);
9126 fputs ("ule", file);
9129 fputs ("ult", file);
9132 fputs ("une", file);
9141 fputs (" ; ", file);
9148 output_operand_lossage ("invalid operand code '%c'", code);
9153 print_reg (x, code, file);
9157 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9158 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9159 && GET_MODE (x) != BLKmode)
9162 switch (GET_MODE_SIZE (GET_MODE (x)))
9164 case 1: size = "BYTE"; break;
9165 case 2: size = "WORD"; break;
9166 case 4: size = "DWORD"; break;
9167 case 8: size = "QWORD"; break;
9168 case 12: size = "XWORD"; break;
9170 if (GET_MODE (x) == XFmode)
9179 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9182 else if (code == 'w')
9184 else if (code == 'k')
9188 fputs (" PTR ", file);
9192 /* Avoid (%rip) for call operands. */
9193 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9194 && !CONST_INT_P (x))
9195 output_addr_const (file, x);
9196 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9197 output_operand_lossage ("invalid constraints for operand");
9202 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9207 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9208 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9210 if (ASSEMBLER_DIALECT == ASM_ATT)
9212 fprintf (file, "0x%08lx", l);
9215 /* These float cases don't actually occur as immediate operands. */
9216 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9220 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9221 fprintf (file, "%s", dstr);
9224 else if (GET_CODE (x) == CONST_DOUBLE
9225 && GET_MODE (x) == XFmode)
9229 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9230 fprintf (file, "%s", dstr);
9235 /* We have patterns that allow zero sets of memory, for instance.
9236 In 64-bit mode, we should probably support all 8-byte vectors,
9237 since we can in fact encode that into an immediate. */
9238 if (GET_CODE (x) == CONST_VECTOR)
9240 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9246 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9248 if (ASSEMBLER_DIALECT == ASM_ATT)
9251 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9252 || GET_CODE (x) == LABEL_REF)
9254 if (ASSEMBLER_DIALECT == ASM_ATT)
9257 fputs ("OFFSET FLAT:", file);
9260 if (CONST_INT_P (x))
9261 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9263 output_pic_addr_const (file, x, code);
9265 output_addr_const (file, x);
9269 /* Print a memory operand whose address is ADDR. */
9272 print_operand_address (FILE *file, rtx addr)
9274 struct ix86_address parts;
9275 rtx base, index, disp;
9277 int ok = ix86_decompose_address (addr, &parts);
9282 index = parts.index;
9284 scale = parts.scale;
9292 if (ASSEMBLER_DIALECT == ASM_ATT)
9294 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9300 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9301 if (TARGET_64BIT && !base && !index)
9305 if (GET_CODE (disp) == CONST
9306 && GET_CODE (XEXP (disp, 0)) == PLUS
9307 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9308 symbol = XEXP (XEXP (disp, 0), 0);
9310 if (GET_CODE (symbol) == LABEL_REF
9311 || (GET_CODE (symbol) == SYMBOL_REF
9312 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9315 if (!base && !index)
9317 /* Displacement only requires special attention. */
9319 if (CONST_INT_P (disp))
9321 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9322 fputs ("ds:", file);
9323 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9326 output_pic_addr_const (file, disp, 0);
9328 output_addr_const (file, disp);
9332 if (ASSEMBLER_DIALECT == ASM_ATT)
9337 output_pic_addr_const (file, disp, 0);
9338 else if (GET_CODE (disp) == LABEL_REF)
9339 output_asm_label (disp);
9341 output_addr_const (file, disp);
9346 print_reg (base, 0, file);
9350 print_reg (index, 0, file);
9352 fprintf (file, ",%d", scale);
9358 rtx offset = NULL_RTX;
9362 /* Pull out the offset of a symbol; print any symbol itself. */
9363 if (GET_CODE (disp) == CONST
9364 && GET_CODE (XEXP (disp, 0)) == PLUS
9365 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9367 offset = XEXP (XEXP (disp, 0), 1);
9368 disp = gen_rtx_CONST (VOIDmode,
9369 XEXP (XEXP (disp, 0), 0));
9373 output_pic_addr_const (file, disp, 0);
9374 else if (GET_CODE (disp) == LABEL_REF)
9375 output_asm_label (disp);
9376 else if (CONST_INT_P (disp))
9379 output_addr_const (file, disp);
9385 print_reg (base, 0, file);
9388 if (INTVAL (offset) >= 0)
9390 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9394 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9401 print_reg (index, 0, file);
9403 fprintf (file, "*%d", scale);
9411 output_addr_const_extra (FILE *file, rtx x)
9415 if (GET_CODE (x) != UNSPEC)
9418 op = XVECEXP (x, 0, 0);
9419 switch (XINT (x, 1))
9421 case UNSPEC_GOTTPOFF:
9422 output_addr_const (file, op);
9423 /* FIXME: This might be @TPOFF in Sun ld. */
9424 fputs ("@GOTTPOFF", file);
9427 output_addr_const (file, op);
9428 fputs ("@TPOFF", file);
9431 output_addr_const (file, op);
9433 fputs ("@TPOFF", file);
9435 fputs ("@NTPOFF", file);
9438 output_addr_const (file, op);
9439 fputs ("@DTPOFF", file);
9441 case UNSPEC_GOTNTPOFF:
9442 output_addr_const (file, op);
9444 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9445 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9447 fputs ("@GOTNTPOFF", file);
9449 case UNSPEC_INDNTPOFF:
9450 output_addr_const (file, op);
9451 fputs ("@INDNTPOFF", file);
9461 /* Split one or more DImode RTL references into pairs of SImode
9462 references. The RTL can be REG, offsettable MEM, integer constant, or
9463 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9464 split and "num" is its length. lo_half and hi_half are output arrays
9465 that parallel "operands". */
9468 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9472 rtx op = operands[num];
9474 /* simplify_subreg refuse to split volatile memory addresses,
9475 but we still have to handle it. */
9478 lo_half[num] = adjust_address (op, SImode, 0);
9479 hi_half[num] = adjust_address (op, SImode, 4);
9483 lo_half[num] = simplify_gen_subreg (SImode, op,
9484 GET_MODE (op) == VOIDmode
9485 ? DImode : GET_MODE (op), 0);
9486 hi_half[num] = simplify_gen_subreg (SImode, op,
9487 GET_MODE (op) == VOIDmode
9488 ? DImode : GET_MODE (op), 4);
9492 /* Split one or more TImode RTL references into pairs of DImode
9493 references. The RTL can be REG, offsettable MEM, integer constant, or
9494 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9495 split and "num" is its length. lo_half and hi_half are output arrays
9496 that parallel "operands". */
9499 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9503 rtx op = operands[num];
9505 /* simplify_subreg refuse to split volatile memory addresses, but we
9506 still have to handle it. */
9509 lo_half[num] = adjust_address (op, DImode, 0);
9510 hi_half[num] = adjust_address (op, DImode, 8);
9514 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9515 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9520 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9521 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9522 is the expression of the binary operation. The output may either be
9523 emitted here, or returned to the caller, like all output_* functions.
9525 There is no guarantee that the operands are the same mode, as they
9526 might be within FLOAT or FLOAT_EXTEND expressions. */
9528 #ifndef SYSV386_COMPAT
9529 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9530 wants to fix the assemblers because that causes incompatibility
9531 with gcc. No-one wants to fix gcc because that causes
9532 incompatibility with assemblers... You can use the option of
9533 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9534 #define SYSV386_COMPAT 1
9538 output_387_binary_op (rtx insn, rtx *operands)
9540 static char buf[30];
9543 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9545 #ifdef ENABLE_CHECKING
9546 /* Even if we do not want to check the inputs, this documents input
9547 constraints. Which helps in understanding the following code. */
9548 if (STACK_REG_P (operands[0])
9549 && ((REG_P (operands[1])
9550 && REGNO (operands[0]) == REGNO (operands[1])
9551 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9552 || (REG_P (operands[2])
9553 && REGNO (operands[0]) == REGNO (operands[2])
9554 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9555 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9558 gcc_assert (is_sse);
9561 switch (GET_CODE (operands[3]))
9564 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9565 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9573 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9574 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9582 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9583 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9591 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9592 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9606 if (GET_MODE (operands[0]) == SFmode)
9607 strcat (buf, "ss\t{%2, %0|%0, %2}");
9609 strcat (buf, "sd\t{%2, %0|%0, %2}");
9614 switch (GET_CODE (operands[3]))
9618 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9620 rtx temp = operands[2];
9621 operands[2] = operands[1];
9625 /* know operands[0] == operands[1]. */
9627 if (MEM_P (operands[2]))
9633 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9635 if (STACK_TOP_P (operands[0]))
9636 /* How is it that we are storing to a dead operand[2]?
9637 Well, presumably operands[1] is dead too. We can't
9638 store the result to st(0) as st(0) gets popped on this
9639 instruction. Instead store to operands[2] (which I
9640 think has to be st(1)). st(1) will be popped later.
9641 gcc <= 2.8.1 didn't have this check and generated
9642 assembly code that the Unixware assembler rejected. */
9643 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9645 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9649 if (STACK_TOP_P (operands[0]))
9650 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9652 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9657 if (MEM_P (operands[1]))
9663 if (MEM_P (operands[2]))
9669 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9672 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9673 derived assemblers, confusingly reverse the direction of
9674 the operation for fsub{r} and fdiv{r} when the
9675 destination register is not st(0). The Intel assembler
9676 doesn't have this brain damage. Read !SYSV386_COMPAT to
9677 figure out what the hardware really does. */
9678 if (STACK_TOP_P (operands[0]))
9679 p = "{p\t%0, %2|rp\t%2, %0}";
9681 p = "{rp\t%2, %0|p\t%0, %2}";
9683 if (STACK_TOP_P (operands[0]))
9684 /* As above for fmul/fadd, we can't store to st(0). */
9685 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9687 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9692 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9695 if (STACK_TOP_P (operands[0]))
9696 p = "{rp\t%0, %1|p\t%1, %0}";
9698 p = "{p\t%1, %0|rp\t%0, %1}";
9700 if (STACK_TOP_P (operands[0]))
9701 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9703 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9708 if (STACK_TOP_P (operands[0]))
9710 if (STACK_TOP_P (operands[1]))
9711 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9713 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9716 else if (STACK_TOP_P (operands[1]))
9719 p = "{\t%1, %0|r\t%0, %1}";
9721 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9727 p = "{r\t%2, %0|\t%0, %2}";
9729 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9742 /* Return needed mode for entity in optimize_mode_switching pass. */
9745 ix86_mode_needed (int entity, rtx insn)
9747 enum attr_i387_cw mode;
9749 /* The mode UNINITIALIZED is used to store control word after a
9750 function call or ASM pattern. The mode ANY specify that function
9751 has no requirements on the control word and make no changes in the
9752 bits we are interested in. */
9755 || (NONJUMP_INSN_P (insn)
9756 && (asm_noperands (PATTERN (insn)) >= 0
9757 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9758 return I387_CW_UNINITIALIZED;
9760 if (recog_memoized (insn) < 0)
9763 mode = get_attr_i387_cw (insn);
9768 if (mode == I387_CW_TRUNC)
9773 if (mode == I387_CW_FLOOR)
9778 if (mode == I387_CW_CEIL)
9783 if (mode == I387_CW_MASK_PM)
9794 /* Output code to initialize control word copies used by trunc?f?i and
9795 rounding patterns. CURRENT_MODE is set to current control word,
9796 while NEW_MODE is set to new control word. */
9799 emit_i387_cw_initialization (int mode)
9801 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9804 enum ix86_stack_slot slot;
9806 rtx reg = gen_reg_rtx (HImode);
9808 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9809 emit_move_insn (reg, copy_rtx (stored_mode));
9811 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9816 /* round toward zero (truncate) */
9817 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9818 slot = SLOT_CW_TRUNC;
9822 /* round down toward -oo */
9823 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9824 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9825 slot = SLOT_CW_FLOOR;
9829 /* round up toward +oo */
9830 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9831 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9832 slot = SLOT_CW_CEIL;
9835 case I387_CW_MASK_PM:
9836 /* mask precision exception for nearbyint() */
9837 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9838 slot = SLOT_CW_MASK_PM;
9850 /* round toward zero (truncate) */
9851 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9852 slot = SLOT_CW_TRUNC;
9856 /* round down toward -oo */
9857 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9858 slot = SLOT_CW_FLOOR;
9862 /* round up toward +oo */
9863 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9864 slot = SLOT_CW_CEIL;
9867 case I387_CW_MASK_PM:
9868 /* mask precision exception for nearbyint() */
9869 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9870 slot = SLOT_CW_MASK_PM;
9878 gcc_assert (slot < MAX_386_STACK_LOCALS);
9880 new_mode = assign_386_stack_local (HImode, slot);
9881 emit_move_insn (new_mode, reg);
9884 /* Output code for INSN to convert a float to a signed int. OPERANDS
9885 are the insn operands. The output may be [HSD]Imode and the input
9886 operand may be [SDX]Fmode. */
9889 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9891 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9892 int dimode_p = GET_MODE (operands[0]) == DImode;
9893 int round_mode = get_attr_i387_cw (insn);
9895 /* Jump through a hoop or two for DImode, since the hardware has no
9896 non-popping instruction. We used to do this a different way, but
9897 that was somewhat fragile and broke with post-reload splitters. */
9898 if ((dimode_p || fisttp) && !stack_top_dies)
9899 output_asm_insn ("fld\t%y1", operands);
9901 gcc_assert (STACK_TOP_P (operands[1]));
9902 gcc_assert (MEM_P (operands[0]));
9903 gcc_assert (GET_MODE (operands[1]) != TFmode);
9906 output_asm_insn ("fisttp%z0\t%0", operands);
9909 if (round_mode != I387_CW_ANY)
9910 output_asm_insn ("fldcw\t%3", operands);
9911 if (stack_top_dies || dimode_p)
9912 output_asm_insn ("fistp%z0\t%0", operands);
9914 output_asm_insn ("fist%z0\t%0", operands);
9915 if (round_mode != I387_CW_ANY)
9916 output_asm_insn ("fldcw\t%2", operands);
9922 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9923 have the values zero or one, indicates the ffreep insn's operand
9924 from the OPERANDS array. */
9927 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9929 if (TARGET_USE_FFREEP)
9930 #if HAVE_AS_IX86_FFREEP
9931 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9934 static char retval[] = ".word\t0xc_df";
9935 int regno = REGNO (operands[opno]);
9937 gcc_assert (FP_REGNO_P (regno));
9939 retval[9] = '0' + (regno - FIRST_STACK_REG);
9944 return opno ? "fstp\t%y1" : "fstp\t%y0";
9948 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9949 should be used. UNORDERED_P is true when fucom should be used. */
9952 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9955 rtx cmp_op0, cmp_op1;
9956 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9960 cmp_op0 = operands[0];
9961 cmp_op1 = operands[1];
9965 cmp_op0 = operands[1];
9966 cmp_op1 = operands[2];
9971 if (GET_MODE (operands[0]) == SFmode)
9973 return "ucomiss\t{%1, %0|%0, %1}";
9975 return "comiss\t{%1, %0|%0, %1}";
9978 return "ucomisd\t{%1, %0|%0, %1}";
9980 return "comisd\t{%1, %0|%0, %1}";
9983 gcc_assert (STACK_TOP_P (cmp_op0));
9985 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9987 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9991 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9992 return output_387_ffreep (operands, 1);
9995 return "ftst\n\tfnstsw\t%0";
9998 if (STACK_REG_P (cmp_op1)
10000 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10001 && REGNO (cmp_op1) != FIRST_STACK_REG)
10003 /* If both the top of the 387 stack dies, and the other operand
10004 is also a stack register that dies, then this must be a
10005 `fcompp' float compare */
10009 /* There is no double popping fcomi variant. Fortunately,
10010 eflags is immune from the fstp's cc clobbering. */
10012 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10014 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10015 return output_387_ffreep (operands, 0);
10020 return "fucompp\n\tfnstsw\t%0";
10022 return "fcompp\n\tfnstsw\t%0";
10027 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10029 static const char * const alt[16] =
10031 "fcom%z2\t%y2\n\tfnstsw\t%0",
10032 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10033 "fucom%z2\t%y2\n\tfnstsw\t%0",
10034 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10036 "ficom%z2\t%y2\n\tfnstsw\t%0",
10037 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10041 "fcomi\t{%y1, %0|%0, %y1}",
10042 "fcomip\t{%y1, %0|%0, %y1}",
10043 "fucomi\t{%y1, %0|%0, %y1}",
10044 "fucomip\t{%y1, %0|%0, %y1}",
10055 mask = eflags_p << 3;
10056 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10057 mask |= unordered_p << 1;
10058 mask |= stack_top_dies;
10060 gcc_assert (mask < 16);
10069 ix86_output_addr_vec_elt (FILE *file, int value)
10071 const char *directive = ASM_LONG;
10075 directive = ASM_QUAD;
10077 gcc_assert (!TARGET_64BIT);
10080 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10084 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10086 const char *directive = ASM_LONG;
10089 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10090 directive = ASM_QUAD;
10092 gcc_assert (!TARGET_64BIT);
10094 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10095 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10096 fprintf (file, "%s%s%d-%s%d\n",
10097 directive, LPREFIX, value, LPREFIX, rel);
10098 else if (HAVE_AS_GOTOFF_IN_DATA)
10099 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10101 else if (TARGET_MACHO)
10103 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10104 machopic_output_function_base_name (file);
10105 fprintf(file, "\n");
10109 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10110 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10113 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10117 ix86_expand_clear (rtx dest)
10121 /* We play register width games, which are only valid after reload. */
10122 gcc_assert (reload_completed);
10124 /* Avoid HImode and its attendant prefix byte. */
10125 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10126 dest = gen_rtx_REG (SImode, REGNO (dest));
10127 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10129 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10130 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10132 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10133 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10139 /* X is an unchanging MEM. If it is a constant pool reference, return
10140 the constant pool rtx, else NULL. */
10143 maybe_get_pool_constant (rtx x)
10145 x = ix86_delegitimize_address (XEXP (x, 0));
10147 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10148 return get_pool_constant (x);
10154 ix86_expand_move (enum machine_mode mode, rtx operands[])
10157 enum tls_model model;
10162 if (GET_CODE (op1) == SYMBOL_REF)
10164 model = SYMBOL_REF_TLS_MODEL (op1);
10167 op1 = legitimize_tls_address (op1, model, true);
10168 op1 = force_operand (op1, op0);
10172 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10173 && SYMBOL_REF_DLLIMPORT_P (op1))
10174 op1 = legitimize_dllimport_symbol (op1, false);
10176 else if (GET_CODE (op1) == CONST
10177 && GET_CODE (XEXP (op1, 0)) == PLUS
10178 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10180 rtx addend = XEXP (XEXP (op1, 0), 1);
10181 rtx symbol = XEXP (XEXP (op1, 0), 0);
10184 model = SYMBOL_REF_TLS_MODEL (symbol);
10186 tmp = legitimize_tls_address (symbol, model, true);
10187 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10188 && SYMBOL_REF_DLLIMPORT_P (symbol))
10189 tmp = legitimize_dllimport_symbol (symbol, true);
10193 tmp = force_operand (tmp, NULL);
10194 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10195 op0, 1, OPTAB_DIRECT);
10201 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10203 if (TARGET_MACHO && !TARGET_64BIT)
10208 rtx temp = ((reload_in_progress
10209 || ((op0 && REG_P (op0))
10211 ? op0 : gen_reg_rtx (Pmode));
10212 op1 = machopic_indirect_data_reference (op1, temp);
10213 op1 = machopic_legitimize_pic_address (op1, mode,
10214 temp == op1 ? 0 : temp);
10216 else if (MACHOPIC_INDIRECT)
10217 op1 = machopic_indirect_data_reference (op1, 0);
10225 op1 = force_reg (Pmode, op1);
10226 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10228 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10229 op1 = legitimize_pic_address (op1, reg);
10238 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10239 || !push_operand (op0, mode))
10241 op1 = force_reg (mode, op1);
10243 if (push_operand (op0, mode)
10244 && ! general_no_elim_operand (op1, mode))
10245 op1 = copy_to_mode_reg (mode, op1);
10247 /* Force large constants in 64bit compilation into register
10248 to get them CSEed. */
10249 if (can_create_pseudo_p ()
10250 && (mode == DImode) && TARGET_64BIT
10251 && immediate_operand (op1, mode)
10252 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10253 && !register_operand (op0, mode)
10255 op1 = copy_to_mode_reg (mode, op1);
10257 if (can_create_pseudo_p ()
10258 && FLOAT_MODE_P (mode)
10259 && GET_CODE (op1) == CONST_DOUBLE)
10261 /* If we are loading a floating point constant to a register,
10262 force the value to memory now, since we'll get better code
10263 out the back end. */
10265 op1 = validize_mem (force_const_mem (mode, op1));
10266 if (!register_operand (op0, mode))
10268 rtx temp = gen_reg_rtx (mode);
10269 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10270 emit_move_insn (op0, temp);
10276 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10280 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10282 rtx op0 = operands[0], op1 = operands[1];
10283 unsigned int align = GET_MODE_ALIGNMENT (mode);
10285 /* Force constants other than zero into memory. We do not know how
10286 the instructions used to build constants modify the upper 64 bits
10287 of the register, once we have that information we may be able
10288 to handle some of them more efficiently. */
10289 if (can_create_pseudo_p ()
10290 && register_operand (op0, mode)
10291 && (CONSTANT_P (op1)
10292 || (GET_CODE (op1) == SUBREG
10293 && CONSTANT_P (SUBREG_REG (op1))))
10294 && standard_sse_constant_p (op1) <= 0)
10295 op1 = validize_mem (force_const_mem (mode, op1));
10297 /* TDmode values are passed as TImode on the stack. TImode values
10298 are moved via xmm registers, and moving them to stack can result in
10299 unaligned memory access. Use ix86_expand_vector_move_misalign()
10300 if memory operand is not aligned correctly. */
10301 if (can_create_pseudo_p ()
10302 && (mode == TImode) && !TARGET_64BIT
10303 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10304 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10308 /* ix86_expand_vector_move_misalign() does not like constants ... */
10309 if (CONSTANT_P (op1)
10310 || (GET_CODE (op1) == SUBREG
10311 && CONSTANT_P (SUBREG_REG (op1))))
10312 op1 = validize_mem (force_const_mem (mode, op1));
10314 /* ... nor both arguments in memory. */
10315 if (!register_operand (op0, mode)
10316 && !register_operand (op1, mode))
10317 op1 = force_reg (mode, op1);
10319 tmp[0] = op0; tmp[1] = op1;
10320 ix86_expand_vector_move_misalign (mode, tmp);
10324 /* Make operand1 a register if it isn't already. */
10325 if (can_create_pseudo_p ()
10326 && !register_operand (op0, mode)
10327 && !register_operand (op1, mode))
10329 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10333 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10336 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10337 straight to ix86_expand_vector_move. */
10338 /* Code generation for scalar reg-reg moves of single and double precision data:
10339 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10343 if (x86_sse_partial_reg_dependency == true)
10348 Code generation for scalar loads of double precision data:
10349 if (x86_sse_split_regs == true)
10350 movlpd mem, reg (gas syntax)
10354 Code generation for unaligned packed loads of single precision data
10355 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10356 if (x86_sse_unaligned_move_optimal)
10359 if (x86_sse_partial_reg_dependency == true)
10371 Code generation for unaligned packed loads of double precision data
10372 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10373 if (x86_sse_unaligned_move_optimal)
10376 if (x86_sse_split_regs == true)
10389 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10398 /* If we're optimizing for size, movups is the smallest. */
10401 op0 = gen_lowpart (V4SFmode, op0);
10402 op1 = gen_lowpart (V4SFmode, op1);
10403 emit_insn (gen_sse_movups (op0, op1));
10407 /* ??? If we have typed data, then it would appear that using
10408 movdqu is the only way to get unaligned data loaded with
10410 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10412 op0 = gen_lowpart (V16QImode, op0);
10413 op1 = gen_lowpart (V16QImode, op1);
10414 emit_insn (gen_sse2_movdqu (op0, op1));
10418 if (TARGET_SSE2 && mode == V2DFmode)
10422 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10424 op0 = gen_lowpart (V2DFmode, op0);
10425 op1 = gen_lowpart (V2DFmode, op1);
10426 emit_insn (gen_sse2_movupd (op0, op1));
10430 /* When SSE registers are split into halves, we can avoid
10431 writing to the top half twice. */
10432 if (TARGET_SSE_SPLIT_REGS)
10434 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10439 /* ??? Not sure about the best option for the Intel chips.
10440 The following would seem to satisfy; the register is
10441 entirely cleared, breaking the dependency chain. We
10442 then store to the upper half, with a dependency depth
10443 of one. A rumor has it that Intel recommends two movsd
10444 followed by an unpacklpd, but this is unconfirmed. And
10445 given that the dependency depth of the unpacklpd would
10446 still be one, I'm not sure why this would be better. */
10447 zero = CONST0_RTX (V2DFmode);
10450 m = adjust_address (op1, DFmode, 0);
10451 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10452 m = adjust_address (op1, DFmode, 8);
10453 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10457 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10459 op0 = gen_lowpart (V4SFmode, op0);
10460 op1 = gen_lowpart (V4SFmode, op1);
10461 emit_insn (gen_sse_movups (op0, op1));
10465 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10466 emit_move_insn (op0, CONST0_RTX (mode));
10468 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10470 if (mode != V4SFmode)
10471 op0 = gen_lowpart (V4SFmode, op0);
10472 m = adjust_address (op1, V2SFmode, 0);
10473 emit_insn (gen_sse_loadlps (op0, op0, m));
10474 m = adjust_address (op1, V2SFmode, 8);
10475 emit_insn (gen_sse_loadhps (op0, op0, m));
10478 else if (MEM_P (op0))
10480 /* If we're optimizing for size, movups is the smallest. */
10483 op0 = gen_lowpart (V4SFmode, op0);
10484 op1 = gen_lowpart (V4SFmode, op1);
10485 emit_insn (gen_sse_movups (op0, op1));
10489 /* ??? Similar to above, only less clear because of quote
10490 typeless stores unquote. */
10491 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10492 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10494 op0 = gen_lowpart (V16QImode, op0);
10495 op1 = gen_lowpart (V16QImode, op1);
10496 emit_insn (gen_sse2_movdqu (op0, op1));
10500 if (TARGET_SSE2 && mode == V2DFmode)
10502 m = adjust_address (op0, DFmode, 0);
10503 emit_insn (gen_sse2_storelpd (m, op1));
10504 m = adjust_address (op0, DFmode, 8);
10505 emit_insn (gen_sse2_storehpd (m, op1));
10509 if (mode != V4SFmode)
10510 op1 = gen_lowpart (V4SFmode, op1);
10511 m = adjust_address (op0, V2SFmode, 0);
10512 emit_insn (gen_sse_storelps (m, op1));
10513 m = adjust_address (op0, V2SFmode, 8);
10514 emit_insn (gen_sse_storehps (m, op1));
10518 gcc_unreachable ();
10521 /* Expand a push in MODE. This is some mode for which we do not support
10522 proper push instructions, at least from the registers that we expect
10523 the value to live in. */
10526 ix86_expand_push (enum machine_mode mode, rtx x)
10530 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10531 GEN_INT (-GET_MODE_SIZE (mode)),
10532 stack_pointer_rtx, 1, OPTAB_DIRECT);
10533 if (tmp != stack_pointer_rtx)
10534 emit_move_insn (stack_pointer_rtx, tmp);
10536 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10537 emit_move_insn (tmp, x);
10540 /* Helper function of ix86_fixup_binary_operands to canonicalize
10541 operand order. Returns true if the operands should be swapped. */
10544 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10547 rtx dst = operands[0];
10548 rtx src1 = operands[1];
10549 rtx src2 = operands[2];
10551 /* If the operation is not commutative, we can't do anything. */
10552 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10555 /* Highest priority is that src1 should match dst. */
10556 if (rtx_equal_p (dst, src1))
10558 if (rtx_equal_p (dst, src2))
10561 /* Next highest priority is that immediate constants come second. */
10562 if (immediate_operand (src2, mode))
10564 if (immediate_operand (src1, mode))
10567 /* Lowest priority is that memory references should come second. */
10577 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10578 destination to use for the operation. If different from the true
10579 destination in operands[0], a copy operation will be required. */
10582 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10585 rtx dst = operands[0];
10586 rtx src1 = operands[1];
10587 rtx src2 = operands[2];
10589 /* Canonicalize operand order. */
10590 if (ix86_swap_binary_operands_p (code, mode, operands))
10597 /* Both source operands cannot be in memory. */
10598 if (MEM_P (src1) && MEM_P (src2))
10600 /* Optimization: Only read from memory once. */
10601 if (rtx_equal_p (src1, src2))
10603 src2 = force_reg (mode, src2);
10607 src2 = force_reg (mode, src2);
10610 /* If the destination is memory, and we do not have matching source
10611 operands, do things in registers. */
10612 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10613 dst = gen_reg_rtx (mode);
10615 /* Source 1 cannot be a constant. */
10616 if (CONSTANT_P (src1))
10617 src1 = force_reg (mode, src1);
10619 /* Source 1 cannot be a non-matching memory. */
10620 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10621 src1 = force_reg (mode, src1);
10623 operands[1] = src1;
10624 operands[2] = src2;
10628 /* Similarly, but assume that the destination has already been
10629 set up properly. */
10632 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10633 enum machine_mode mode, rtx operands[])
10635 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10636 gcc_assert (dst == operands[0]);
10639 /* Attempt to expand a binary operator. Make the expansion closer to the
10640 actual machine, then just general_operand, which will allow 3 separate
10641 memory references (one output, two input) in a single insn. */
10644 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10647 rtx src1, src2, dst, op, clob;
10649 dst = ix86_fixup_binary_operands (code, mode, operands);
10650 src1 = operands[1];
10651 src2 = operands[2];
10653 /* Emit the instruction. */
10655 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10656 if (reload_in_progress)
10658 /* Reload doesn't know about the flags register, and doesn't know that
10659 it doesn't want to clobber it. We can only do this with PLUS. */
10660 gcc_assert (code == PLUS);
10665 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10666 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10669 /* Fix up the destination if needed. */
10670 if (dst != operands[0])
10671 emit_move_insn (operands[0], dst);
10674 /* Return TRUE or FALSE depending on whether the binary operator meets the
10675 appropriate constraints. */
10678 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10681 rtx dst = operands[0];
10682 rtx src1 = operands[1];
10683 rtx src2 = operands[2];
10685 /* Both source operands cannot be in memory. */
10686 if (MEM_P (src1) && MEM_P (src2))
10689 /* Canonicalize operand order for commutative operators. */
10690 if (ix86_swap_binary_operands_p (code, mode, operands))
10697 /* If the destination is memory, we must have a matching source operand. */
10698 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10701 /* Source 1 cannot be a constant. */
10702 if (CONSTANT_P (src1))
10705 /* Source 1 cannot be a non-matching memory. */
10706 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10712 /* Attempt to expand a unary operator. Make the expansion closer to the
10713 actual machine, then just general_operand, which will allow 2 separate
10714 memory references (one output, one input) in a single insn. */
10717 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10720 int matching_memory;
10721 rtx src, dst, op, clob;
10726 /* If the destination is memory, and we do not have matching source
10727 operands, do things in registers. */
10728 matching_memory = 0;
10731 if (rtx_equal_p (dst, src))
10732 matching_memory = 1;
10734 dst = gen_reg_rtx (mode);
10737 /* When source operand is memory, destination must match. */
10738 if (MEM_P (src) && !matching_memory)
10739 src = force_reg (mode, src);
10741 /* Emit the instruction. */
10743 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10744 if (reload_in_progress || code == NOT)
10746 /* Reload doesn't know about the flags register, and doesn't know that
10747 it doesn't want to clobber it. */
10748 gcc_assert (code == NOT);
10753 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10754 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10757 /* Fix up the destination if needed. */
10758 if (dst != operands[0])
10759 emit_move_insn (operands[0], dst);
10762 /* Return TRUE or FALSE depending on whether the unary operator meets the
10763 appropriate constraints. */
10766 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10767 enum machine_mode mode ATTRIBUTE_UNUSED,
10768 rtx operands[2] ATTRIBUTE_UNUSED)
10770 /* If one of operands is memory, source and destination must match. */
10771 if ((MEM_P (operands[0])
10772 || MEM_P (operands[1]))
10773 && ! rtx_equal_p (operands[0], operands[1]))
10778 /* Post-reload splitter for converting an SF or DFmode value in an
10779 SSE register into an unsigned SImode. */
10782 ix86_split_convert_uns_si_sse (rtx operands[])
10784 enum machine_mode vecmode;
10785 rtx value, large, zero_or_two31, input, two31, x;
10787 large = operands[1];
10788 zero_or_two31 = operands[2];
10789 input = operands[3];
10790 two31 = operands[4];
10791 vecmode = GET_MODE (large);
10792 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10794 /* Load up the value into the low element. We must ensure that the other
10795 elements are valid floats -- zero is the easiest such value. */
10798 if (vecmode == V4SFmode)
10799 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10801 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10805 input = gen_rtx_REG (vecmode, REGNO (input));
10806 emit_move_insn (value, CONST0_RTX (vecmode));
10807 if (vecmode == V4SFmode)
10808 emit_insn (gen_sse_movss (value, value, input));
10810 emit_insn (gen_sse2_movsd (value, value, input));
10813 emit_move_insn (large, two31);
10814 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10816 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10817 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10819 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10820 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10822 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10823 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10825 large = gen_rtx_REG (V4SImode, REGNO (large));
10826 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10828 x = gen_rtx_REG (V4SImode, REGNO (value));
10829 if (vecmode == V4SFmode)
10830 emit_insn (gen_sse2_cvttps2dq (x, value));
10832 emit_insn (gen_sse2_cvttpd2dq (x, value));
10835 emit_insn (gen_xorv4si3 (value, value, large));
10838 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10839 Expects the 64-bit DImode to be supplied in a pair of integral
10840 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10841 -mfpmath=sse, !optimize_size only. */
10844 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10846 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10847 rtx int_xmm, fp_xmm;
10848 rtx biases, exponents;
10851 int_xmm = gen_reg_rtx (V4SImode);
10852 if (TARGET_INTER_UNIT_MOVES)
10853 emit_insn (gen_movdi_to_sse (int_xmm, input));
10854 else if (TARGET_SSE_SPLIT_REGS)
10856 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10857 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10861 x = gen_reg_rtx (V2DImode);
10862 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10863 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10866 x = gen_rtx_CONST_VECTOR (V4SImode,
10867 gen_rtvec (4, GEN_INT (0x43300000UL),
10868 GEN_INT (0x45300000UL),
10869 const0_rtx, const0_rtx));
10870 exponents = validize_mem (force_const_mem (V4SImode, x));
10872 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10873 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10875 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10876 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10877 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10878 (0x1.0p84 + double(fp_value_hi_xmm)).
10879 Note these exponents differ by 32. */
10881 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10883 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10884 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10885 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10886 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10887 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10888 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10889 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10890 biases = validize_mem (force_const_mem (V2DFmode, biases));
10891 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10893 /* Add the upper and lower DFmode values together. */
10895 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10898 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10899 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10900 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10903 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10906 /* Convert an unsigned SImode value into a DFmode. Only currently used
10907 for SSE, but applicable anywhere. */
10910 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10912 REAL_VALUE_TYPE TWO31r;
10915 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10916 NULL, 1, OPTAB_DIRECT);
10918 fp = gen_reg_rtx (DFmode);
10919 emit_insn (gen_floatsidf2 (fp, x));
10921 real_ldexp (&TWO31r, &dconst1, 31);
10922 x = const_double_from_real_value (TWO31r, DFmode);
10924 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10926 emit_move_insn (target, x);
10929 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10930 32-bit mode; otherwise we have a direct convert instruction. */
10933 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10935 REAL_VALUE_TYPE TWO32r;
10936 rtx fp_lo, fp_hi, x;
10938 fp_lo = gen_reg_rtx (DFmode);
10939 fp_hi = gen_reg_rtx (DFmode);
10941 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10943 real_ldexp (&TWO32r, &dconst1, 32);
10944 x = const_double_from_real_value (TWO32r, DFmode);
10945 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10947 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10949 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10952 emit_move_insn (target, x);
10955 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10956 For x86_32, -mfpmath=sse, !optimize_size only. */
10958 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10960 REAL_VALUE_TYPE ONE16r;
10961 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10963 real_ldexp (&ONE16r, &dconst1, 16);
10964 x = const_double_from_real_value (ONE16r, SFmode);
10965 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10966 NULL, 0, OPTAB_DIRECT);
10967 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10968 NULL, 0, OPTAB_DIRECT);
10969 fp_hi = gen_reg_rtx (SFmode);
10970 fp_lo = gen_reg_rtx (SFmode);
10971 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10972 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10973 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10975 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10977 if (!rtx_equal_p (target, fp_hi))
10978 emit_move_insn (target, fp_hi);
10981 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10982 then replicate the value for all elements of the vector
10986 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
10993 v = gen_rtvec (4, value, value, value, value);
10994 return gen_rtx_CONST_VECTOR (V4SImode, v);
10998 v = gen_rtvec (2, value, value);
10999 return gen_rtx_CONST_VECTOR (V2DImode, v);
11003 v = gen_rtvec (4, value, value, value, value);
11005 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11006 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11007 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11011 v = gen_rtvec (2, value, value);
11013 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11014 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11017 gcc_unreachable ();
11021 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11022 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11023 for an SSE register. If VECT is true, then replicate the mask for
11024 all elements of the vector register. If INVERT is true, then create
11025 a mask excluding the sign bit. */
11028 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11030 enum machine_mode vec_mode, imode;
11031 HOST_WIDE_INT hi, lo;
11036 /* Find the sign bit, sign extended to 2*HWI. */
11042 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11043 lo = 0x80000000, hi = lo < 0;
11049 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11050 if (HOST_BITS_PER_WIDE_INT >= 64)
11051 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11053 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11059 vec_mode = VOIDmode;
11060 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11061 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11065 gcc_unreachable ();
11069 lo = ~lo, hi = ~hi;
11071 /* Force this value into the low part of a fp vector constant. */
11072 mask = immed_double_const (lo, hi, imode);
11073 mask = gen_lowpart (mode, mask);
11075 if (vec_mode == VOIDmode)
11076 return force_reg (mode, mask);
11078 v = ix86_build_const_vector (mode, vect, mask);
11079 return force_reg (vec_mode, v);
11082 /* Generate code for floating point ABS or NEG. */
11085 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11088 rtx mask, set, use, clob, dst, src;
11089 bool use_sse = false;
11090 bool vector_mode = VECTOR_MODE_P (mode);
11091 enum machine_mode elt_mode = mode;
11095 elt_mode = GET_MODE_INNER (mode);
11098 else if (mode == TFmode)
11100 else if (TARGET_SSE_MATH)
11101 use_sse = SSE_FLOAT_MODE_P (mode);
11103 /* NEG and ABS performed with SSE use bitwise mask operations.
11104 Create the appropriate mask now. */
11106 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11115 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11116 set = gen_rtx_SET (VOIDmode, dst, set);
11121 set = gen_rtx_fmt_e (code, mode, src);
11122 set = gen_rtx_SET (VOIDmode, dst, set);
11125 use = gen_rtx_USE (VOIDmode, mask);
11126 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11127 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11128 gen_rtvec (3, set, use, clob)));
11135 /* Expand a copysign operation. Special case operand 0 being a constant. */
11138 ix86_expand_copysign (rtx operands[])
11140 enum machine_mode mode, vmode;
11141 rtx dest, op0, op1, mask, nmask;
11143 dest = operands[0];
11147 mode = GET_MODE (dest);
11148 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11150 if (GET_CODE (op0) == CONST_DOUBLE)
11152 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11154 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11155 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11157 if (mode == SFmode || mode == DFmode)
11159 if (op0 == CONST0_RTX (mode))
11160 op0 = CONST0_RTX (vmode);
11165 if (mode == SFmode)
11166 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11167 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11169 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11170 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11174 mask = ix86_build_signbit_mask (mode, 0, 0);
11176 if (mode == SFmode)
11177 copysign_insn = gen_copysignsf3_const;
11178 else if (mode == DFmode)
11179 copysign_insn = gen_copysigndf3_const;
11181 copysign_insn = gen_copysigntf3_const;
11183 emit_insn (copysign_insn (dest, op0, op1, mask));
11187 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11189 nmask = ix86_build_signbit_mask (mode, 0, 1);
11190 mask = ix86_build_signbit_mask (mode, 0, 0);
11192 if (mode == SFmode)
11193 copysign_insn = gen_copysignsf3_var;
11194 else if (mode == DFmode)
11195 copysign_insn = gen_copysigndf3_var;
11197 copysign_insn = gen_copysigntf3_var;
11199 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11203 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11204 be a constant, and so has already been expanded into a vector constant. */
11207 ix86_split_copysign_const (rtx operands[])
11209 enum machine_mode mode, vmode;
11210 rtx dest, op0, op1, mask, x;
11212 dest = operands[0];
11215 mask = operands[3];
11217 mode = GET_MODE (dest);
11218 vmode = GET_MODE (mask);
11220 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11221 x = gen_rtx_AND (vmode, dest, mask);
11222 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11224 if (op0 != CONST0_RTX (vmode))
11226 x = gen_rtx_IOR (vmode, dest, op0);
11227 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11231 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11232 so we have to do two masks. */
11235 ix86_split_copysign_var (rtx operands[])
11237 enum machine_mode mode, vmode;
11238 rtx dest, scratch, op0, op1, mask, nmask, x;
11240 dest = operands[0];
11241 scratch = operands[1];
11244 nmask = operands[4];
11245 mask = operands[5];
11247 mode = GET_MODE (dest);
11248 vmode = GET_MODE (mask);
11250 if (rtx_equal_p (op0, op1))
11252 /* Shouldn't happen often (it's useless, obviously), but when it does
11253 we'd generate incorrect code if we continue below. */
11254 emit_move_insn (dest, op0);
11258 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11260 gcc_assert (REGNO (op1) == REGNO (scratch));
11262 x = gen_rtx_AND (vmode, scratch, mask);
11263 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11266 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11267 x = gen_rtx_NOT (vmode, dest);
11268 x = gen_rtx_AND (vmode, x, op0);
11269 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11273 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11275 x = gen_rtx_AND (vmode, scratch, mask);
11277 else /* alternative 2,4 */
11279 gcc_assert (REGNO (mask) == REGNO (scratch));
11280 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11281 x = gen_rtx_AND (vmode, scratch, op1);
11283 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11285 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11287 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11288 x = gen_rtx_AND (vmode, dest, nmask);
11290 else /* alternative 3,4 */
11292 gcc_assert (REGNO (nmask) == REGNO (dest));
11294 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11295 x = gen_rtx_AND (vmode, dest, op0);
11297 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11300 x = gen_rtx_IOR (vmode, dest, scratch);
11301 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11304 /* Return TRUE or FALSE depending on whether the first SET in INSN
11305 has source and destination with matching CC modes, and that the
11306 CC mode is at least as constrained as REQ_MODE. */
11309 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11312 enum machine_mode set_mode;
11314 set = PATTERN (insn);
11315 if (GET_CODE (set) == PARALLEL)
11316 set = XVECEXP (set, 0, 0);
11317 gcc_assert (GET_CODE (set) == SET);
11318 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11320 set_mode = GET_MODE (SET_DEST (set));
11324 if (req_mode != CCNOmode
11325 && (req_mode != CCmode
11326 || XEXP (SET_SRC (set), 1) != const0_rtx))
11330 if (req_mode == CCGCmode)
11334 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11338 if (req_mode == CCZmode)
11345 gcc_unreachable ();
11348 return (GET_MODE (SET_SRC (set)) == set_mode);
11351 /* Generate insn patterns to do an integer compare of OPERANDS. */
11354 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11356 enum machine_mode cmpmode;
11359 cmpmode = SELECT_CC_MODE (code, op0, op1);
11360 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11362 /* This is very simple, but making the interface the same as in the
11363 FP case makes the rest of the code easier. */
11364 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11365 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11367 /* Return the test that should be put into the flags user, i.e.
11368 the bcc, scc, or cmov instruction. */
11369 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11372 /* Figure out whether to use ordered or unordered fp comparisons.
11373 Return the appropriate mode to use. */
11376 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11378 /* ??? In order to make all comparisons reversible, we do all comparisons
11379 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11380 all forms trapping and nontrapping comparisons, we can make inequality
11381 comparisons trapping again, since it results in better code when using
11382 FCOM based compares. */
11383 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11387 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11389 enum machine_mode mode = GET_MODE (op0);
11391 if (SCALAR_FLOAT_MODE_P (mode))
11393 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11394 return ix86_fp_compare_mode (code);
11399 /* Only zero flag is needed. */
11400 case EQ: /* ZF=0 */
11401 case NE: /* ZF!=0 */
11403 /* Codes needing carry flag. */
11404 case GEU: /* CF=0 */
11405 case LTU: /* CF=1 */
11406 /* Detect overflow checks. They need just the carry flag. */
11407 if (GET_CODE (op0) == PLUS
11408 && rtx_equal_p (op1, XEXP (op0, 0)))
11412 case GTU: /* CF=0 & ZF=0 */
11413 case LEU: /* CF=1 | ZF=1 */
11414 /* Detect overflow checks. They need just the carry flag. */
11415 if (GET_CODE (op0) == MINUS
11416 && rtx_equal_p (op1, XEXP (op0, 0)))
11420 /* Codes possibly doable only with sign flag when
11421 comparing against zero. */
11422 case GE: /* SF=OF or SF=0 */
11423 case LT: /* SF<>OF or SF=1 */
11424 if (op1 == const0_rtx)
11427 /* For other cases Carry flag is not required. */
11429 /* Codes doable only with sign flag when comparing
11430 against zero, but we miss jump instruction for it
11431 so we need to use relational tests against overflow
11432 that thus needs to be zero. */
11433 case GT: /* ZF=0 & SF=OF */
11434 case LE: /* ZF=1 | SF<>OF */
11435 if (op1 == const0_rtx)
11439 /* strcmp pattern do (use flags) and combine may ask us for proper
11444 gcc_unreachable ();
11448 /* Return the fixed registers used for condition codes. */
11451 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11458 /* If two condition code modes are compatible, return a condition code
11459 mode which is compatible with both. Otherwise, return
11462 static enum machine_mode
11463 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11468 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11471 if ((m1 == CCGCmode && m2 == CCGOCmode)
11472 || (m1 == CCGOCmode && m2 == CCGCmode))
11478 gcc_unreachable ();
11508 /* These are only compatible with themselves, which we already
11514 /* Split comparison code CODE into comparisons we can do using branch
11515 instructions. BYPASS_CODE is comparison code for branch that will
11516 branch around FIRST_CODE and SECOND_CODE. If some of branches
11517 is not required, set value to UNKNOWN.
11518 We never require more than two branches. */
11521 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11522 enum rtx_code *first_code,
11523 enum rtx_code *second_code)
11525 *first_code = code;
11526 *bypass_code = UNKNOWN;
11527 *second_code = UNKNOWN;
11529 /* The fcomi comparison sets flags as follows:
11539 case GT: /* GTU - CF=0 & ZF=0 */
11540 case GE: /* GEU - CF=0 */
11541 case ORDERED: /* PF=0 */
11542 case UNORDERED: /* PF=1 */
11543 case UNEQ: /* EQ - ZF=1 */
11544 case UNLT: /* LTU - CF=1 */
11545 case UNLE: /* LEU - CF=1 | ZF=1 */
11546 case LTGT: /* EQ - ZF=0 */
11548 case LT: /* LTU - CF=1 - fails on unordered */
11549 *first_code = UNLT;
11550 *bypass_code = UNORDERED;
11552 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11553 *first_code = UNLE;
11554 *bypass_code = UNORDERED;
11556 case EQ: /* EQ - ZF=1 - fails on unordered */
11557 *first_code = UNEQ;
11558 *bypass_code = UNORDERED;
11560 case NE: /* NE - ZF=0 - fails on unordered */
11561 *first_code = LTGT;
11562 *second_code = UNORDERED;
11564 case UNGE: /* GEU - CF=0 - fails on unordered */
11566 *second_code = UNORDERED;
11568 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11570 *second_code = UNORDERED;
11573 gcc_unreachable ();
11575 if (!TARGET_IEEE_FP)
11577 *second_code = UNKNOWN;
11578 *bypass_code = UNKNOWN;
11582 /* Return cost of comparison done fcom + arithmetics operations on AX.
11583 All following functions do use number of instructions as a cost metrics.
11584 In future this should be tweaked to compute bytes for optimize_size and
11585 take into account performance of various instructions on various CPUs. */
11587 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11589 if (!TARGET_IEEE_FP)
11591 /* The cost of code output by ix86_expand_fp_compare. */
11615 gcc_unreachable ();
11619 /* Return cost of comparison done using fcomi operation.
11620 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11622 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11624 enum rtx_code bypass_code, first_code, second_code;
11625 /* Return arbitrarily high cost when instruction is not supported - this
11626 prevents gcc from using it. */
11629 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11630 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11633 /* Return cost of comparison done using sahf operation.
11634 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11636 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11638 enum rtx_code bypass_code, first_code, second_code;
11639 /* Return arbitrarily high cost when instruction is not preferred - this
11640 avoids gcc from using it. */
11641 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11643 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11644 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11647 /* Compute cost of the comparison done using any method.
11648 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11650 ix86_fp_comparison_cost (enum rtx_code code)
11652 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11655 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11656 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11658 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11659 if (min > sahf_cost)
11661 if (min > fcomi_cost)
11666 /* Return true if we should use an FCOMI instruction for this
11670 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11672 enum rtx_code swapped_code = swap_condition (code);
11674 return ((ix86_fp_comparison_cost (code)
11675 == ix86_fp_comparison_fcomi_cost (code))
11676 || (ix86_fp_comparison_cost (swapped_code)
11677 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11680 /* Swap, force into registers, or otherwise massage the two operands
11681 to a fp comparison. The operands are updated in place; the new
11682 comparison code is returned. */
11684 static enum rtx_code
11685 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11687 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11688 rtx op0 = *pop0, op1 = *pop1;
11689 enum machine_mode op_mode = GET_MODE (op0);
11690 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11692 /* All of the unordered compare instructions only work on registers.
11693 The same is true of the fcomi compare instructions. The XFmode
11694 compare instructions require registers except when comparing
11695 against zero or when converting operand 1 from fixed point to
11699 && (fpcmp_mode == CCFPUmode
11700 || (op_mode == XFmode
11701 && ! (standard_80387_constant_p (op0) == 1
11702 || standard_80387_constant_p (op1) == 1)
11703 && GET_CODE (op1) != FLOAT)
11704 || ix86_use_fcomi_compare (code)))
11706 op0 = force_reg (op_mode, op0);
11707 op1 = force_reg (op_mode, op1);
11711 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11712 things around if they appear profitable, otherwise force op0
11713 into a register. */
11715 if (standard_80387_constant_p (op0) == 0
11717 && ! (standard_80387_constant_p (op1) == 0
11721 tmp = op0, op0 = op1, op1 = tmp;
11722 code = swap_condition (code);
11726 op0 = force_reg (op_mode, op0);
11728 if (CONSTANT_P (op1))
11730 int tmp = standard_80387_constant_p (op1);
11732 op1 = validize_mem (force_const_mem (op_mode, op1));
11736 op1 = force_reg (op_mode, op1);
11739 op1 = force_reg (op_mode, op1);
11743 /* Try to rearrange the comparison to make it cheaper. */
11744 if (ix86_fp_comparison_cost (code)
11745 > ix86_fp_comparison_cost (swap_condition (code))
11746 && (REG_P (op1) || can_create_pseudo_p ()))
11749 tmp = op0, op0 = op1, op1 = tmp;
11750 code = swap_condition (code);
11752 op0 = force_reg (op_mode, op0);
11760 /* Convert comparison codes we use to represent FP comparison to integer
11761 code that will result in proper branch. Return UNKNOWN if no such code
11765 ix86_fp_compare_code_to_integer (enum rtx_code code)
11794 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11797 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11798 rtx *second_test, rtx *bypass_test)
11800 enum machine_mode fpcmp_mode, intcmp_mode;
11802 int cost = ix86_fp_comparison_cost (code);
11803 enum rtx_code bypass_code, first_code, second_code;
11805 fpcmp_mode = ix86_fp_compare_mode (code);
11806 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11809 *second_test = NULL_RTX;
11811 *bypass_test = NULL_RTX;
11813 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11815 /* Do fcomi/sahf based test when profitable. */
11816 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11817 && (bypass_code == UNKNOWN || bypass_test)
11818 && (second_code == UNKNOWN || second_test))
11820 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11821 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11827 gcc_assert (TARGET_SAHF);
11830 scratch = gen_reg_rtx (HImode);
11831 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11833 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11836 /* The FP codes work out to act like unsigned. */
11837 intcmp_mode = fpcmp_mode;
11839 if (bypass_code != UNKNOWN)
11840 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11841 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11843 if (second_code != UNKNOWN)
11844 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11845 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11850 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11851 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11852 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11854 scratch = gen_reg_rtx (HImode);
11855 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11857 /* In the unordered case, we have to check C2 for NaN's, which
11858 doesn't happen to work out to anything nice combination-wise.
11859 So do some bit twiddling on the value we've got in AH to come
11860 up with an appropriate set of condition codes. */
11862 intcmp_mode = CCNOmode;
11867 if (code == GT || !TARGET_IEEE_FP)
11869 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11874 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11875 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11876 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11877 intcmp_mode = CCmode;
11883 if (code == LT && TARGET_IEEE_FP)
11885 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11886 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11887 intcmp_mode = CCmode;
11892 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11898 if (code == GE || !TARGET_IEEE_FP)
11900 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11905 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11906 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11913 if (code == LE && TARGET_IEEE_FP)
11915 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11916 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11917 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11918 intcmp_mode = CCmode;
11923 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11929 if (code == EQ && TARGET_IEEE_FP)
11931 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11932 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11933 intcmp_mode = CCmode;
11938 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11945 if (code == NE && TARGET_IEEE_FP)
11947 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11948 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11954 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11960 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11964 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11969 gcc_unreachable ();
11973 /* Return the test that should be put into the flags user, i.e.
11974 the bcc, scc, or cmov instruction. */
11975 return gen_rtx_fmt_ee (code, VOIDmode,
11976 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11981 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11984 op0 = ix86_compare_op0;
11985 op1 = ix86_compare_op1;
11988 *second_test = NULL_RTX;
11990 *bypass_test = NULL_RTX;
11992 if (ix86_compare_emitted)
11994 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
11995 ix86_compare_emitted = NULL_RTX;
11997 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
11999 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12000 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12001 second_test, bypass_test);
12004 ret = ix86_expand_int_compare (code, op0, op1);
12009 /* Return true if the CODE will result in nontrivial jump sequence. */
12011 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12013 enum rtx_code bypass_code, first_code, second_code;
12016 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12017 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12021 ix86_expand_branch (enum rtx_code code, rtx label)
12025 /* If we have emitted a compare insn, go straight to simple.
12026 ix86_expand_compare won't emit anything if ix86_compare_emitted
12028 if (ix86_compare_emitted)
12031 switch (GET_MODE (ix86_compare_op0))
12037 tmp = ix86_expand_compare (code, NULL, NULL);
12038 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12039 gen_rtx_LABEL_REF (VOIDmode, label),
12041 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12050 enum rtx_code bypass_code, first_code, second_code;
12052 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12053 &ix86_compare_op1);
12055 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12057 /* Check whether we will use the natural sequence with one jump. If
12058 so, we can expand jump early. Otherwise delay expansion by
12059 creating compound insn to not confuse optimizers. */
12060 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12062 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12063 gen_rtx_LABEL_REF (VOIDmode, label),
12064 pc_rtx, NULL_RTX, NULL_RTX);
12068 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12069 ix86_compare_op0, ix86_compare_op1);
12070 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12071 gen_rtx_LABEL_REF (VOIDmode, label),
12073 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12075 use_fcomi = ix86_use_fcomi_compare (code);
12076 vec = rtvec_alloc (3 + !use_fcomi);
12077 RTVEC_ELT (vec, 0) = tmp;
12079 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12081 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12084 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12086 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12095 /* Expand DImode branch into multiple compare+branch. */
12097 rtx lo[2], hi[2], label2;
12098 enum rtx_code code1, code2, code3;
12099 enum machine_mode submode;
12101 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12103 tmp = ix86_compare_op0;
12104 ix86_compare_op0 = ix86_compare_op1;
12105 ix86_compare_op1 = tmp;
12106 code = swap_condition (code);
12108 if (GET_MODE (ix86_compare_op0) == DImode)
12110 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12111 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12116 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12117 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12121 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12122 avoid two branches. This costs one extra insn, so disable when
12123 optimizing for size. */
12125 if ((code == EQ || code == NE)
12127 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12132 if (hi[1] != const0_rtx)
12133 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12134 NULL_RTX, 0, OPTAB_WIDEN);
12137 if (lo[1] != const0_rtx)
12138 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12139 NULL_RTX, 0, OPTAB_WIDEN);
12141 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12142 NULL_RTX, 0, OPTAB_WIDEN);
12144 ix86_compare_op0 = tmp;
12145 ix86_compare_op1 = const0_rtx;
12146 ix86_expand_branch (code, label);
12150 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12151 op1 is a constant and the low word is zero, then we can just
12152 examine the high word. Similarly for low word -1 and
12153 less-or-equal-than or greater-than. */
12155 if (CONST_INT_P (hi[1]))
12158 case LT: case LTU: case GE: case GEU:
12159 if (lo[1] == const0_rtx)
12161 ix86_compare_op0 = hi[0];
12162 ix86_compare_op1 = hi[1];
12163 ix86_expand_branch (code, label);
12167 case LE: case LEU: case GT: case GTU:
12168 if (lo[1] == constm1_rtx)
12170 ix86_compare_op0 = hi[0];
12171 ix86_compare_op1 = hi[1];
12172 ix86_expand_branch (code, label);
12180 /* Otherwise, we need two or three jumps. */
12182 label2 = gen_label_rtx ();
12185 code2 = swap_condition (code);
12186 code3 = unsigned_condition (code);
12190 case LT: case GT: case LTU: case GTU:
12193 case LE: code1 = LT; code2 = GT; break;
12194 case GE: code1 = GT; code2 = LT; break;
12195 case LEU: code1 = LTU; code2 = GTU; break;
12196 case GEU: code1 = GTU; code2 = LTU; break;
12198 case EQ: code1 = UNKNOWN; code2 = NE; break;
12199 case NE: code2 = UNKNOWN; break;
12202 gcc_unreachable ();
12207 * if (hi(a) < hi(b)) goto true;
12208 * if (hi(a) > hi(b)) goto false;
12209 * if (lo(a) < lo(b)) goto true;
12213 ix86_compare_op0 = hi[0];
12214 ix86_compare_op1 = hi[1];
12216 if (code1 != UNKNOWN)
12217 ix86_expand_branch (code1, label);
12218 if (code2 != UNKNOWN)
12219 ix86_expand_branch (code2, label2);
12221 ix86_compare_op0 = lo[0];
12222 ix86_compare_op1 = lo[1];
12223 ix86_expand_branch (code3, label);
12225 if (code2 != UNKNOWN)
12226 emit_label (label2);
12231 gcc_unreachable ();
12235 /* Split branch based on floating point condition. */
12237 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12238 rtx target1, rtx target2, rtx tmp, rtx pushed)
12240 rtx second, bypass;
12241 rtx label = NULL_RTX;
12243 int bypass_probability = -1, second_probability = -1, probability = -1;
12246 if (target2 != pc_rtx)
12249 code = reverse_condition_maybe_unordered (code);
12254 condition = ix86_expand_fp_compare (code, op1, op2,
12255 tmp, &second, &bypass);
12257 /* Remove pushed operand from stack. */
12259 ix86_free_from_memory (GET_MODE (pushed));
12261 if (split_branch_probability >= 0)
12263 /* Distribute the probabilities across the jumps.
12264 Assume the BYPASS and SECOND to be always test
12266 probability = split_branch_probability;
12268 /* Value of 1 is low enough to make no need for probability
12269 to be updated. Later we may run some experiments and see
12270 if unordered values are more frequent in practice. */
12272 bypass_probability = 1;
12274 second_probability = 1;
12276 if (bypass != NULL_RTX)
12278 label = gen_label_rtx ();
12279 i = emit_jump_insn (gen_rtx_SET
12281 gen_rtx_IF_THEN_ELSE (VOIDmode,
12283 gen_rtx_LABEL_REF (VOIDmode,
12286 if (bypass_probability >= 0)
12288 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12289 GEN_INT (bypass_probability),
12292 i = emit_jump_insn (gen_rtx_SET
12294 gen_rtx_IF_THEN_ELSE (VOIDmode,
12295 condition, target1, target2)));
12296 if (probability >= 0)
12298 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12299 GEN_INT (probability),
12301 if (second != NULL_RTX)
12303 i = emit_jump_insn (gen_rtx_SET
12305 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12307 if (second_probability >= 0)
12309 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12310 GEN_INT (second_probability),
12313 if (label != NULL_RTX)
12314 emit_label (label);
12318 ix86_expand_setcc (enum rtx_code code, rtx dest)
12320 rtx ret, tmp, tmpreg, equiv;
12321 rtx second_test, bypass_test;
12323 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12324 return 0; /* FAIL */
12326 gcc_assert (GET_MODE (dest) == QImode);
12328 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12329 PUT_MODE (ret, QImode);
12334 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12335 if (bypass_test || second_test)
12337 rtx test = second_test;
12339 rtx tmp2 = gen_reg_rtx (QImode);
12342 gcc_assert (!second_test);
12343 test = bypass_test;
12345 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12347 PUT_MODE (test, QImode);
12348 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12351 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12353 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12356 /* Attach a REG_EQUAL note describing the comparison result. */
12357 if (ix86_compare_op0 && ix86_compare_op1)
12359 equiv = simplify_gen_relational (code, QImode,
12360 GET_MODE (ix86_compare_op0),
12361 ix86_compare_op0, ix86_compare_op1);
12362 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12365 return 1; /* DONE */
12368 /* Expand comparison setting or clearing carry flag. Return true when
12369 successful and set pop for the operation. */
12371 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12373 enum machine_mode mode =
12374 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12376 /* Do not handle DImode compares that go through special path. */
12377 if (mode == (TARGET_64BIT ? TImode : DImode))
12380 if (SCALAR_FLOAT_MODE_P (mode))
12382 rtx second_test = NULL, bypass_test = NULL;
12383 rtx compare_op, compare_seq;
12385 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12387 /* Shortcut: following common codes never translate
12388 into carry flag compares. */
12389 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12390 || code == ORDERED || code == UNORDERED)
12393 /* These comparisons require zero flag; swap operands so they won't. */
12394 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12395 && !TARGET_IEEE_FP)
12400 code = swap_condition (code);
12403 /* Try to expand the comparison and verify that we end up with
12404 carry flag based comparison. This fails to be true only when
12405 we decide to expand comparison using arithmetic that is not
12406 too common scenario. */
12408 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12409 &second_test, &bypass_test);
12410 compare_seq = get_insns ();
12413 if (second_test || bypass_test)
12416 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12417 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12418 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12420 code = GET_CODE (compare_op);
12422 if (code != LTU && code != GEU)
12425 emit_insn (compare_seq);
12430 if (!INTEGRAL_MODE_P (mode))
12439 /* Convert a==0 into (unsigned)a<1. */
12442 if (op1 != const0_rtx)
12445 code = (code == EQ ? LTU : GEU);
12448 /* Convert a>b into b<a or a>=b-1. */
12451 if (CONST_INT_P (op1))
12453 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12454 /* Bail out on overflow. We still can swap operands but that
12455 would force loading of the constant into register. */
12456 if (op1 == const0_rtx
12457 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12459 code = (code == GTU ? GEU : LTU);
12466 code = (code == GTU ? LTU : GEU);
12470 /* Convert a>=0 into (unsigned)a<0x80000000. */
12473 if (mode == DImode || op1 != const0_rtx)
12475 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12476 code = (code == LT ? GEU : LTU);
12480 if (mode == DImode || op1 != constm1_rtx)
12482 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12483 code = (code == LE ? GEU : LTU);
12489 /* Swapping operands may cause constant to appear as first operand. */
12490 if (!nonimmediate_operand (op0, VOIDmode))
12492 if (!can_create_pseudo_p ())
12494 op0 = force_reg (mode, op0);
12496 ix86_compare_op0 = op0;
12497 ix86_compare_op1 = op1;
12498 *pop = ix86_expand_compare (code, NULL, NULL);
12499 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12504 ix86_expand_int_movcc (rtx operands[])
12506 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12507 rtx compare_seq, compare_op;
12508 rtx second_test, bypass_test;
12509 enum machine_mode mode = GET_MODE (operands[0]);
12510 bool sign_bit_compare_p = false;;
12513 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12514 compare_seq = get_insns ();
12517 compare_code = GET_CODE (compare_op);
12519 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12520 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12521 sign_bit_compare_p = true;
12523 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12524 HImode insns, we'd be swallowed in word prefix ops. */
12526 if ((mode != HImode || TARGET_FAST_PREFIX)
12527 && (mode != (TARGET_64BIT ? TImode : DImode))
12528 && CONST_INT_P (operands[2])
12529 && CONST_INT_P (operands[3]))
12531 rtx out = operands[0];
12532 HOST_WIDE_INT ct = INTVAL (operands[2]);
12533 HOST_WIDE_INT cf = INTVAL (operands[3]);
12534 HOST_WIDE_INT diff;
12537 /* Sign bit compares are better done using shifts than we do by using
12539 if (sign_bit_compare_p
12540 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12541 ix86_compare_op1, &compare_op))
12543 /* Detect overlap between destination and compare sources. */
12546 if (!sign_bit_compare_p)
12548 bool fpcmp = false;
12550 compare_code = GET_CODE (compare_op);
12552 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12553 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12556 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12559 /* To simplify rest of code, restrict to the GEU case. */
12560 if (compare_code == LTU)
12562 HOST_WIDE_INT tmp = ct;
12565 compare_code = reverse_condition (compare_code);
12566 code = reverse_condition (code);
12571 PUT_CODE (compare_op,
12572 reverse_condition_maybe_unordered
12573 (GET_CODE (compare_op)));
12575 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12579 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12580 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12581 tmp = gen_reg_rtx (mode);
12583 if (mode == DImode)
12584 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12586 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12590 if (code == GT || code == GE)
12591 code = reverse_condition (code);
12594 HOST_WIDE_INT tmp = ct;
12599 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12600 ix86_compare_op1, VOIDmode, 0, -1);
12613 tmp = expand_simple_binop (mode, PLUS,
12615 copy_rtx (tmp), 1, OPTAB_DIRECT);
12626 tmp = expand_simple_binop (mode, IOR,
12628 copy_rtx (tmp), 1, OPTAB_DIRECT);
12630 else if (diff == -1 && ct)
12640 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12642 tmp = expand_simple_binop (mode, PLUS,
12643 copy_rtx (tmp), GEN_INT (cf),
12644 copy_rtx (tmp), 1, OPTAB_DIRECT);
12652 * andl cf - ct, dest
12662 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12665 tmp = expand_simple_binop (mode, AND,
12667 gen_int_mode (cf - ct, mode),
12668 copy_rtx (tmp), 1, OPTAB_DIRECT);
12670 tmp = expand_simple_binop (mode, PLUS,
12671 copy_rtx (tmp), GEN_INT (ct),
12672 copy_rtx (tmp), 1, OPTAB_DIRECT);
12675 if (!rtx_equal_p (tmp, out))
12676 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12678 return 1; /* DONE */
12683 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12686 tmp = ct, ct = cf, cf = tmp;
12689 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12691 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12693 /* We may be reversing unordered compare to normal compare, that
12694 is not valid in general (we may convert non-trapping condition
12695 to trapping one), however on i386 we currently emit all
12696 comparisons unordered. */
12697 compare_code = reverse_condition_maybe_unordered (compare_code);
12698 code = reverse_condition_maybe_unordered (code);
12702 compare_code = reverse_condition (compare_code);
12703 code = reverse_condition (code);
12707 compare_code = UNKNOWN;
12708 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12709 && CONST_INT_P (ix86_compare_op1))
12711 if (ix86_compare_op1 == const0_rtx
12712 && (code == LT || code == GE))
12713 compare_code = code;
12714 else if (ix86_compare_op1 == constm1_rtx)
12718 else if (code == GT)
12723 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12724 if (compare_code != UNKNOWN
12725 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12726 && (cf == -1 || ct == -1))
12728 /* If lea code below could be used, only optimize
12729 if it results in a 2 insn sequence. */
12731 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12732 || diff == 3 || diff == 5 || diff == 9)
12733 || (compare_code == LT && ct == -1)
12734 || (compare_code == GE && cf == -1))
12737 * notl op1 (if necessary)
12745 code = reverse_condition (code);
12748 out = emit_store_flag (out, code, ix86_compare_op0,
12749 ix86_compare_op1, VOIDmode, 0, -1);
12751 out = expand_simple_binop (mode, IOR,
12753 out, 1, OPTAB_DIRECT);
12754 if (out != operands[0])
12755 emit_move_insn (operands[0], out);
12757 return 1; /* DONE */
12762 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12763 || diff == 3 || diff == 5 || diff == 9)
12764 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12766 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12772 * lea cf(dest*(ct-cf)),dest
12776 * This also catches the degenerate setcc-only case.
12782 out = emit_store_flag (out, code, ix86_compare_op0,
12783 ix86_compare_op1, VOIDmode, 0, 1);
12786 /* On x86_64 the lea instruction operates on Pmode, so we need
12787 to get arithmetics done in proper mode to match. */
12789 tmp = copy_rtx (out);
12793 out1 = copy_rtx (out);
12794 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12798 tmp = gen_rtx_PLUS (mode, tmp, out1);
12804 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12807 if (!rtx_equal_p (tmp, out))
12810 out = force_operand (tmp, copy_rtx (out));
12812 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12814 if (!rtx_equal_p (out, operands[0]))
12815 emit_move_insn (operands[0], copy_rtx (out));
12817 return 1; /* DONE */
12821 * General case: Jumpful:
12822 * xorl dest,dest cmpl op1, op2
12823 * cmpl op1, op2 movl ct, dest
12824 * setcc dest jcc 1f
12825 * decl dest movl cf, dest
12826 * andl (cf-ct),dest 1:
12829 * Size 20. Size 14.
12831 * This is reasonably steep, but branch mispredict costs are
12832 * high on modern cpus, so consider failing only if optimizing
12836 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12837 && BRANCH_COST >= 2)
12841 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12846 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12848 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12850 /* We may be reversing unordered compare to normal compare,
12851 that is not valid in general (we may convert non-trapping
12852 condition to trapping one), however on i386 we currently
12853 emit all comparisons unordered. */
12854 code = reverse_condition_maybe_unordered (code);
12858 code = reverse_condition (code);
12859 if (compare_code != UNKNOWN)
12860 compare_code = reverse_condition (compare_code);
12864 if (compare_code != UNKNOWN)
12866 /* notl op1 (if needed)
12871 For x < 0 (resp. x <= -1) there will be no notl,
12872 so if possible swap the constants to get rid of the
12874 True/false will be -1/0 while code below (store flag
12875 followed by decrement) is 0/-1, so the constants need
12876 to be exchanged once more. */
12878 if (compare_code == GE || !cf)
12880 code = reverse_condition (code);
12885 HOST_WIDE_INT tmp = cf;
12890 out = emit_store_flag (out, code, ix86_compare_op0,
12891 ix86_compare_op1, VOIDmode, 0, -1);
12895 out = emit_store_flag (out, code, ix86_compare_op0,
12896 ix86_compare_op1, VOIDmode, 0, 1);
12898 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12899 copy_rtx (out), 1, OPTAB_DIRECT);
12902 out = expand_simple_binop (mode, AND, copy_rtx (out),
12903 gen_int_mode (cf - ct, mode),
12904 copy_rtx (out), 1, OPTAB_DIRECT);
12906 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12907 copy_rtx (out), 1, OPTAB_DIRECT);
12908 if (!rtx_equal_p (out, operands[0]))
12909 emit_move_insn (operands[0], copy_rtx (out));
12911 return 1; /* DONE */
12915 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12917 /* Try a few things more with specific constants and a variable. */
12920 rtx var, orig_out, out, tmp;
12922 if (BRANCH_COST <= 2)
12923 return 0; /* FAIL */
12925 /* If one of the two operands is an interesting constant, load a
12926 constant with the above and mask it in with a logical operation. */
12928 if (CONST_INT_P (operands[2]))
12931 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12932 operands[3] = constm1_rtx, op = and_optab;
12933 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12934 operands[3] = const0_rtx, op = ior_optab;
12936 return 0; /* FAIL */
12938 else if (CONST_INT_P (operands[3]))
12941 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12942 operands[2] = constm1_rtx, op = and_optab;
12943 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12944 operands[2] = const0_rtx, op = ior_optab;
12946 return 0; /* FAIL */
12949 return 0; /* FAIL */
12951 orig_out = operands[0];
12952 tmp = gen_reg_rtx (mode);
12955 /* Recurse to get the constant loaded. */
12956 if (ix86_expand_int_movcc (operands) == 0)
12957 return 0; /* FAIL */
12959 /* Mask in the interesting variable. */
12960 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12962 if (!rtx_equal_p (out, orig_out))
12963 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12965 return 1; /* DONE */
12969 * For comparison with above,
12979 if (! nonimmediate_operand (operands[2], mode))
12980 operands[2] = force_reg (mode, operands[2]);
12981 if (! nonimmediate_operand (operands[3], mode))
12982 operands[3] = force_reg (mode, operands[3]);
12984 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12986 rtx tmp = gen_reg_rtx (mode);
12987 emit_move_insn (tmp, operands[3]);
12990 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12992 rtx tmp = gen_reg_rtx (mode);
12993 emit_move_insn (tmp, operands[2]);
12997 if (! register_operand (operands[2], VOIDmode)
12999 || ! register_operand (operands[3], VOIDmode)))
13000 operands[2] = force_reg (mode, operands[2]);
13003 && ! register_operand (operands[3], VOIDmode))
13004 operands[3] = force_reg (mode, operands[3]);
13006 emit_insn (compare_seq);
13007 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13008 gen_rtx_IF_THEN_ELSE (mode,
13009 compare_op, operands[2],
13012 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13013 gen_rtx_IF_THEN_ELSE (mode,
13015 copy_rtx (operands[3]),
13016 copy_rtx (operands[0]))));
13018 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13019 gen_rtx_IF_THEN_ELSE (mode,
13021 copy_rtx (operands[2]),
13022 copy_rtx (operands[0]))));
13024 return 1; /* DONE */
13027 /* Swap, force into registers, or otherwise massage the two operands
13028 to an sse comparison with a mask result. Thus we differ a bit from
13029 ix86_prepare_fp_compare_args which expects to produce a flags result.
13031 The DEST operand exists to help determine whether to commute commutative
13032 operators. The POP0/POP1 operands are updated in place. The new
13033 comparison code is returned, or UNKNOWN if not implementable. */
13035 static enum rtx_code
13036 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13037 rtx *pop0, rtx *pop1)
13045 /* We have no LTGT as an operator. We could implement it with
13046 NE & ORDERED, but this requires an extra temporary. It's
13047 not clear that it's worth it. */
13054 /* These are supported directly. */
13061 /* For commutative operators, try to canonicalize the destination
13062 operand to be first in the comparison - this helps reload to
13063 avoid extra moves. */
13064 if (!dest || !rtx_equal_p (dest, *pop1))
13072 /* These are not supported directly. Swap the comparison operands
13073 to transform into something that is supported. */
13077 code = swap_condition (code);
13081 gcc_unreachable ();
13087 /* Detect conditional moves that exactly match min/max operational
13088 semantics. Note that this is IEEE safe, as long as we don't
13089 interchange the operands.
13091 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13092 and TRUE if the operation is successful and instructions are emitted. */
13095 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13096 rtx cmp_op1, rtx if_true, rtx if_false)
13098 enum machine_mode mode;
13104 else if (code == UNGE)
13107 if_true = if_false;
13113 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13115 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13120 mode = GET_MODE (dest);
13122 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13123 but MODE may be a vector mode and thus not appropriate. */
13124 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13126 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13129 if_true = force_reg (mode, if_true);
13130 v = gen_rtvec (2, if_true, if_false);
13131 tmp = gen_rtx_UNSPEC (mode, v, u);
13135 code = is_min ? SMIN : SMAX;
13136 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13139 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13143 /* Expand an sse vector comparison. Return the register with the result. */
13146 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13147 rtx op_true, rtx op_false)
13149 enum machine_mode mode = GET_MODE (dest);
13152 cmp_op0 = force_reg (mode, cmp_op0);
13153 if (!nonimmediate_operand (cmp_op1, mode))
13154 cmp_op1 = force_reg (mode, cmp_op1);
13157 || reg_overlap_mentioned_p (dest, op_true)
13158 || reg_overlap_mentioned_p (dest, op_false))
13159 dest = gen_reg_rtx (mode);
13161 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13162 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13167 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13168 operations. This is used for both scalar and vector conditional moves. */
13171 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13173 enum machine_mode mode = GET_MODE (dest);
13178 rtx pcmov = gen_rtx_SET (mode, dest,
13179 gen_rtx_IF_THEN_ELSE (mode, cmp,
13184 else if (op_false == CONST0_RTX (mode))
13186 op_true = force_reg (mode, op_true);
13187 x = gen_rtx_AND (mode, cmp, op_true);
13188 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13190 else if (op_true == CONST0_RTX (mode))
13192 op_false = force_reg (mode, op_false);
13193 x = gen_rtx_NOT (mode, cmp);
13194 x = gen_rtx_AND (mode, x, op_false);
13195 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13199 op_true = force_reg (mode, op_true);
13200 op_false = force_reg (mode, op_false);
13202 t2 = gen_reg_rtx (mode);
13204 t3 = gen_reg_rtx (mode);
13208 x = gen_rtx_AND (mode, op_true, cmp);
13209 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13211 x = gen_rtx_NOT (mode, cmp);
13212 x = gen_rtx_AND (mode, x, op_false);
13213 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13215 x = gen_rtx_IOR (mode, t3, t2);
13216 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13220 /* Expand a floating-point conditional move. Return true if successful. */
13223 ix86_expand_fp_movcc (rtx operands[])
13225 enum machine_mode mode = GET_MODE (operands[0]);
13226 enum rtx_code code = GET_CODE (operands[1]);
13227 rtx tmp, compare_op, second_test, bypass_test;
13229 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13231 enum machine_mode cmode;
13233 /* Since we've no cmove for sse registers, don't force bad register
13234 allocation just to gain access to it. Deny movcc when the
13235 comparison mode doesn't match the move mode. */
13236 cmode = GET_MODE (ix86_compare_op0);
13237 if (cmode == VOIDmode)
13238 cmode = GET_MODE (ix86_compare_op1);
13242 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13244 &ix86_compare_op1);
13245 if (code == UNKNOWN)
13248 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13249 ix86_compare_op1, operands[2],
13253 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13254 ix86_compare_op1, operands[2], operands[3]);
13255 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13259 /* The floating point conditional move instructions don't directly
13260 support conditions resulting from a signed integer comparison. */
13262 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13264 /* The floating point conditional move instructions don't directly
13265 support signed integer comparisons. */
13267 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13269 gcc_assert (!second_test && !bypass_test);
13270 tmp = gen_reg_rtx (QImode);
13271 ix86_expand_setcc (code, tmp);
13273 ix86_compare_op0 = tmp;
13274 ix86_compare_op1 = const0_rtx;
13275 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13277 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13279 tmp = gen_reg_rtx (mode);
13280 emit_move_insn (tmp, operands[3]);
13283 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13285 tmp = gen_reg_rtx (mode);
13286 emit_move_insn (tmp, operands[2]);
13290 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13291 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13292 operands[2], operands[3])));
13294 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13295 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13296 operands[3], operands[0])));
13298 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13299 gen_rtx_IF_THEN_ELSE (mode, second_test,
13300 operands[2], operands[0])));
13305 /* Expand a floating-point vector conditional move; a vcond operation
13306 rather than a movcc operation. */
13309 ix86_expand_fp_vcond (rtx operands[])
13311 enum rtx_code code = GET_CODE (operands[3]);
13314 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13315 &operands[4], &operands[5]);
13316 if (code == UNKNOWN)
13319 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13320 operands[5], operands[1], operands[2]))
13323 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13324 operands[1], operands[2]);
13325 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13329 /* Expand a signed/unsigned integral vector conditional move. */
13332 ix86_expand_int_vcond (rtx operands[])
13334 enum machine_mode mode = GET_MODE (operands[0]);
13335 enum rtx_code code = GET_CODE (operands[3]);
13336 bool negate = false;
13339 cop0 = operands[4];
13340 cop1 = operands[5];
13342 /* Canonicalize the comparison to EQ, GT, GTU. */
13353 code = reverse_condition (code);
13359 code = reverse_condition (code);
13365 code = swap_condition (code);
13366 x = cop0, cop0 = cop1, cop1 = x;
13370 gcc_unreachable ();
13373 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13374 if (mode == V2DImode)
13379 /* SSE4.1 supports EQ. */
13380 if (!TARGET_SSE4_1)
13386 /* SSE4.2 supports GT/GTU. */
13387 if (!TARGET_SSE4_2)
13392 gcc_unreachable ();
13396 /* Unsigned parallel compare is not supported by the hardware. Play some
13397 tricks to turn this into a signed comparison against 0. */
13400 cop0 = force_reg (mode, cop0);
13409 /* Perform a parallel modulo subtraction. */
13410 t1 = gen_reg_rtx (mode);
13411 emit_insn ((mode == V4SImode
13413 : gen_subv2di3) (t1, cop0, cop1));
13415 /* Extract the original sign bit of op0. */
13416 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13418 t2 = gen_reg_rtx (mode);
13419 emit_insn ((mode == V4SImode
13421 : gen_andv2di3) (t2, cop0, mask));
13423 /* XOR it back into the result of the subtraction. This results
13424 in the sign bit set iff we saw unsigned underflow. */
13425 x = gen_reg_rtx (mode);
13426 emit_insn ((mode == V4SImode
13428 : gen_xorv2di3) (x, t1, t2));
13436 /* Perform a parallel unsigned saturating subtraction. */
13437 x = gen_reg_rtx (mode);
13438 emit_insn (gen_rtx_SET (VOIDmode, x,
13439 gen_rtx_US_MINUS (mode, cop0, cop1)));
13446 gcc_unreachable ();
13450 cop1 = CONST0_RTX (mode);
13453 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13454 operands[1+negate], operands[2-negate]);
13456 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13457 operands[2-negate]);
13461 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13462 true if we should do zero extension, else sign extension. HIGH_P is
13463 true if we want the N/2 high elements, else the low elements. */
13466 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13468 enum machine_mode imode = GET_MODE (operands[1]);
13469 rtx (*unpack)(rtx, rtx, rtx);
13476 unpack = gen_vec_interleave_highv16qi;
13478 unpack = gen_vec_interleave_lowv16qi;
13482 unpack = gen_vec_interleave_highv8hi;
13484 unpack = gen_vec_interleave_lowv8hi;
13488 unpack = gen_vec_interleave_highv4si;
13490 unpack = gen_vec_interleave_lowv4si;
13493 gcc_unreachable ();
13496 dest = gen_lowpart (imode, operands[0]);
13499 se = force_reg (imode, CONST0_RTX (imode));
13501 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13502 operands[1], pc_rtx, pc_rtx);
13504 emit_insn (unpack (dest, operands[1], se));
13507 /* This function performs the same task as ix86_expand_sse_unpack,
13508 but with SSE4.1 instructions. */
13511 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13513 enum machine_mode imode = GET_MODE (operands[1]);
13514 rtx (*unpack)(rtx, rtx);
13521 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13523 unpack = gen_sse4_1_extendv8qiv8hi2;
13527 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13529 unpack = gen_sse4_1_extendv4hiv4si2;
13533 unpack = gen_sse4_1_zero_extendv2siv2di2;
13535 unpack = gen_sse4_1_extendv2siv2di2;
13538 gcc_unreachable ();
13541 dest = operands[0];
13544 /* Shift higher 8 bytes to lower 8 bytes. */
13545 src = gen_reg_rtx (imode);
13546 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13547 gen_lowpart (TImode, operands[1]),
13553 emit_insn (unpack (dest, src));
13556 /* This function performs the same task as ix86_expand_sse_unpack,
13557 but with amdfam15 instructions. */
13559 #define PPERM_SRC 0x00 /* copy source */
13560 #define PPERM_INVERT 0x20 /* invert source */
13561 #define PPERM_REVERSE 0x40 /* bit reverse source */
13562 #define PPERM_REV_INV 0x60 /* bit reverse & invert src */
13563 #define PPERM_ZERO 0x80 /* all 0's */
13564 #define PPERM_ONES 0xa0 /* all 1's */
13565 #define PPERM_SIGN 0xc0 /* propagate sign bit */
13566 #define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
13568 #define PPERM_SRC1 0x00 /* use first source byte */
13569 #define PPERM_SRC2 0x10 /* use second source byte */
13572 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13574 enum machine_mode imode = GET_MODE (operands[1]);
13575 int pperm_bytes[16];
13577 int h = (high_p) ? 8 : 0;
13580 rtvec v = rtvec_alloc (16);
13583 rtx op0 = operands[0], op1 = operands[1];
13588 vs = rtvec_alloc (8);
13589 h2 = (high_p) ? 8 : 0;
13590 for (i = 0; i < 8; i++)
13592 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13593 pperm_bytes[2*i+1] = ((unsigned_p)
13595 : PPERM_SIGN | PPERM_SRC2 | i | h);
13598 for (i = 0; i < 16; i++)
13599 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13601 for (i = 0; i < 8; i++)
13602 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13604 p = gen_rtx_PARALLEL (VOIDmode, vs);
13605 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13607 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13609 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13613 vs = rtvec_alloc (4);
13614 h2 = (high_p) ? 4 : 0;
13615 for (i = 0; i < 4; i++)
13617 sign_extend = ((unsigned_p)
13619 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13620 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13621 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13622 pperm_bytes[4*i+2] = sign_extend;
13623 pperm_bytes[4*i+3] = sign_extend;
13626 for (i = 0; i < 16; i++)
13627 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13629 for (i = 0; i < 4; i++)
13630 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13632 p = gen_rtx_PARALLEL (VOIDmode, vs);
13633 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13635 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13637 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13641 vs = rtvec_alloc (2);
13642 h2 = (high_p) ? 2 : 0;
13643 for (i = 0; i < 2; i++)
13645 sign_extend = ((unsigned_p)
13647 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13648 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13649 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13650 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13651 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13652 pperm_bytes[8*i+4] = sign_extend;
13653 pperm_bytes[8*i+5] = sign_extend;
13654 pperm_bytes[8*i+6] = sign_extend;
13655 pperm_bytes[8*i+7] = sign_extend;
13658 for (i = 0; i < 16; i++)
13659 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13661 for (i = 0; i < 2; i++)
13662 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13664 p = gen_rtx_PARALLEL (VOIDmode, vs);
13665 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13667 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13669 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13673 gcc_unreachable ();
13679 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13680 next narrower integer vector type */
13682 ix86_expand_sse5_pack (rtx operands[3])
13684 enum machine_mode imode = GET_MODE (operands[0]);
13685 int pperm_bytes[16];
13687 rtvec v = rtvec_alloc (16);
13689 rtx op0 = operands[0];
13690 rtx op1 = operands[1];
13691 rtx op2 = operands[2];
13696 for (i = 0; i < 8; i++)
13698 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13699 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13702 for (i = 0; i < 16; i++)
13703 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13705 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13706 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13710 for (i = 0; i < 4; i++)
13712 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13713 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13714 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13715 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13718 for (i = 0; i < 16; i++)
13719 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13721 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13722 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13726 for (i = 0; i < 2; i++)
13728 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13729 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13730 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13731 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13732 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13733 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13734 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13735 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13738 for (i = 0; i < 16; i++)
13739 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13741 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13742 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13746 gcc_unreachable ();
13752 /* Expand conditional increment or decrement using adb/sbb instructions.
13753 The default case using setcc followed by the conditional move can be
13754 done by generic code. */
13756 ix86_expand_int_addcc (rtx operands[])
13758 enum rtx_code code = GET_CODE (operands[1]);
13760 rtx val = const0_rtx;
13761 bool fpcmp = false;
13762 enum machine_mode mode = GET_MODE (operands[0]);
13764 if (operands[3] != const1_rtx
13765 && operands[3] != constm1_rtx)
13767 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13768 ix86_compare_op1, &compare_op))
13770 code = GET_CODE (compare_op);
13772 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13773 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13776 code = ix86_fp_compare_code_to_integer (code);
13783 PUT_CODE (compare_op,
13784 reverse_condition_maybe_unordered
13785 (GET_CODE (compare_op)));
13787 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13789 PUT_MODE (compare_op, mode);
13791 /* Construct either adc or sbb insn. */
13792 if ((code == LTU) == (operands[3] == constm1_rtx))
13794 switch (GET_MODE (operands[0]))
13797 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13800 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13803 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13806 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13809 gcc_unreachable ();
13814 switch (GET_MODE (operands[0]))
13817 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13820 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13823 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13826 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13829 gcc_unreachable ();
13832 return 1; /* DONE */
13836 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13837 works for floating pointer parameters and nonoffsetable memories.
13838 For pushes, it returns just stack offsets; the values will be saved
13839 in the right order. Maximally three parts are generated. */
13842 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13847 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13849 size = (GET_MODE_SIZE (mode) + 4) / 8;
13851 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13852 gcc_assert (size >= 2 && size <= 3);
13854 /* Optimize constant pool reference to immediates. This is used by fp
13855 moves, that force all constants to memory to allow combining. */
13856 if (MEM_P (operand) && MEM_READONLY_P (operand))
13858 rtx tmp = maybe_get_pool_constant (operand);
13863 if (MEM_P (operand) && !offsettable_memref_p (operand))
13865 /* The only non-offsetable memories we handle are pushes. */
13866 int ok = push_operand (operand, VOIDmode);
13870 operand = copy_rtx (operand);
13871 PUT_MODE (operand, Pmode);
13872 parts[0] = parts[1] = parts[2] = operand;
13876 if (GET_CODE (operand) == CONST_VECTOR)
13878 enum machine_mode imode = int_mode_for_mode (mode);
13879 /* Caution: if we looked through a constant pool memory above,
13880 the operand may actually have a different mode now. That's
13881 ok, since we want to pun this all the way back to an integer. */
13882 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13883 gcc_assert (operand != NULL);
13889 if (mode == DImode)
13890 split_di (&operand, 1, &parts[0], &parts[1]);
13893 if (REG_P (operand))
13895 gcc_assert (reload_completed);
13896 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13897 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13899 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13901 else if (offsettable_memref_p (operand))
13903 operand = adjust_address (operand, SImode, 0);
13904 parts[0] = operand;
13905 parts[1] = adjust_address (operand, SImode, 4);
13907 parts[2] = adjust_address (operand, SImode, 8);
13909 else if (GET_CODE (operand) == CONST_DOUBLE)
13914 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13918 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13919 parts[2] = gen_int_mode (l[2], SImode);
13922 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13925 gcc_unreachable ();
13927 parts[1] = gen_int_mode (l[1], SImode);
13928 parts[0] = gen_int_mode (l[0], SImode);
13931 gcc_unreachable ();
13936 if (mode == TImode)
13937 split_ti (&operand, 1, &parts[0], &parts[1]);
13938 if (mode == XFmode || mode == TFmode)
13940 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13941 if (REG_P (operand))
13943 gcc_assert (reload_completed);
13944 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13945 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13947 else if (offsettable_memref_p (operand))
13949 operand = adjust_address (operand, DImode, 0);
13950 parts[0] = operand;
13951 parts[1] = adjust_address (operand, upper_mode, 8);
13953 else if (GET_CODE (operand) == CONST_DOUBLE)
13958 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13959 real_to_target (l, &r, mode);
13961 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13962 if (HOST_BITS_PER_WIDE_INT >= 64)
13965 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13966 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13969 parts[0] = immed_double_const (l[0], l[1], DImode);
13971 if (upper_mode == SImode)
13972 parts[1] = gen_int_mode (l[2], SImode);
13973 else if (HOST_BITS_PER_WIDE_INT >= 64)
13976 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13977 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13980 parts[1] = immed_double_const (l[2], l[3], DImode);
13983 gcc_unreachable ();
13990 /* Emit insns to perform a move or push of DI, DF, and XF values.
13991 Return false when normal moves are needed; true when all required
13992 insns have been emitted. Operands 2-4 contain the input values
13993 int the correct order; operands 5-7 contain the output values. */
13996 ix86_split_long_move (rtx operands[])
14001 int collisions = 0;
14002 enum machine_mode mode = GET_MODE (operands[0]);
14004 /* The DFmode expanders may ask us to move double.
14005 For 64bit target this is single move. By hiding the fact
14006 here we simplify i386.md splitters. */
14007 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14009 /* Optimize constant pool reference to immediates. This is used by
14010 fp moves, that force all constants to memory to allow combining. */
14012 if (MEM_P (operands[1])
14013 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14014 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14015 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14016 if (push_operand (operands[0], VOIDmode))
14018 operands[0] = copy_rtx (operands[0]);
14019 PUT_MODE (operands[0], Pmode);
14022 operands[0] = gen_lowpart (DImode, operands[0]);
14023 operands[1] = gen_lowpart (DImode, operands[1]);
14024 emit_move_insn (operands[0], operands[1]);
14028 /* The only non-offsettable memory we handle is push. */
14029 if (push_operand (operands[0], VOIDmode))
14032 gcc_assert (!MEM_P (operands[0])
14033 || offsettable_memref_p (operands[0]));
14035 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14036 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14038 /* When emitting push, take care for source operands on the stack. */
14039 if (push && MEM_P (operands[1])
14040 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14043 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14044 XEXP (part[1][2], 0));
14045 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14046 XEXP (part[1][1], 0));
14049 /* We need to do copy in the right order in case an address register
14050 of the source overlaps the destination. */
14051 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14053 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14055 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14058 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14061 /* Collision in the middle part can be handled by reordering. */
14062 if (collisions == 1 && nparts == 3
14063 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14066 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14067 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14070 /* If there are more collisions, we can't handle it by reordering.
14071 Do an lea to the last part and use only one colliding move. */
14072 else if (collisions > 1)
14078 base = part[0][nparts - 1];
14080 /* Handle the case when the last part isn't valid for lea.
14081 Happens in 64-bit mode storing the 12-byte XFmode. */
14082 if (GET_MODE (base) != Pmode)
14083 base = gen_rtx_REG (Pmode, REGNO (base));
14085 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14086 part[1][0] = replace_equiv_address (part[1][0], base);
14087 part[1][1] = replace_equiv_address (part[1][1],
14088 plus_constant (base, UNITS_PER_WORD));
14090 part[1][2] = replace_equiv_address (part[1][2],
14091 plus_constant (base, 8));
14101 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14102 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14103 emit_move_insn (part[0][2], part[1][2]);
14108 /* In 64bit mode we don't have 32bit push available. In case this is
14109 register, it is OK - we will just use larger counterpart. We also
14110 retype memory - these comes from attempt to avoid REX prefix on
14111 moving of second half of TFmode value. */
14112 if (GET_MODE (part[1][1]) == SImode)
14114 switch (GET_CODE (part[1][1]))
14117 part[1][1] = adjust_address (part[1][1], DImode, 0);
14121 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14125 gcc_unreachable ();
14128 if (GET_MODE (part[1][0]) == SImode)
14129 part[1][0] = part[1][1];
14132 emit_move_insn (part[0][1], part[1][1]);
14133 emit_move_insn (part[0][0], part[1][0]);
14137 /* Choose correct order to not overwrite the source before it is copied. */
14138 if ((REG_P (part[0][0])
14139 && REG_P (part[1][1])
14140 && (REGNO (part[0][0]) == REGNO (part[1][1])
14142 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14144 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14148 operands[2] = part[0][2];
14149 operands[3] = part[0][1];
14150 operands[4] = part[0][0];
14151 operands[5] = part[1][2];
14152 operands[6] = part[1][1];
14153 operands[7] = part[1][0];
14157 operands[2] = part[0][1];
14158 operands[3] = part[0][0];
14159 operands[5] = part[1][1];
14160 operands[6] = part[1][0];
14167 operands[2] = part[0][0];
14168 operands[3] = part[0][1];
14169 operands[4] = part[0][2];
14170 operands[5] = part[1][0];
14171 operands[6] = part[1][1];
14172 operands[7] = part[1][2];
14176 operands[2] = part[0][0];
14177 operands[3] = part[0][1];
14178 operands[5] = part[1][0];
14179 operands[6] = part[1][1];
14183 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14186 if (CONST_INT_P (operands[5])
14187 && operands[5] != const0_rtx
14188 && REG_P (operands[2]))
14190 if (CONST_INT_P (operands[6])
14191 && INTVAL (operands[6]) == INTVAL (operands[5]))
14192 operands[6] = operands[2];
14195 && CONST_INT_P (operands[7])
14196 && INTVAL (operands[7]) == INTVAL (operands[5]))
14197 operands[7] = operands[2];
14201 && CONST_INT_P (operands[6])
14202 && operands[6] != const0_rtx
14203 && REG_P (operands[3])
14204 && CONST_INT_P (operands[7])
14205 && INTVAL (operands[7]) == INTVAL (operands[6]))
14206 operands[7] = operands[3];
14209 emit_move_insn (operands[2], operands[5]);
14210 emit_move_insn (operands[3], operands[6]);
14212 emit_move_insn (operands[4], operands[7]);
14217 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14218 left shift by a constant, either using a single shift or
14219 a sequence of add instructions. */
14222 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14226 emit_insn ((mode == DImode
14228 : gen_adddi3) (operand, operand, operand));
14230 else if (!optimize_size
14231 && count * ix86_cost->add <= ix86_cost->shift_const)
14234 for (i=0; i<count; i++)
14236 emit_insn ((mode == DImode
14238 : gen_adddi3) (operand, operand, operand));
14242 emit_insn ((mode == DImode
14244 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14248 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14250 rtx low[2], high[2];
14252 const int single_width = mode == DImode ? 32 : 64;
14254 if (CONST_INT_P (operands[2]))
14256 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14257 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14259 if (count >= single_width)
14261 emit_move_insn (high[0], low[1]);
14262 emit_move_insn (low[0], const0_rtx);
14264 if (count > single_width)
14265 ix86_expand_ashl_const (high[0], count - single_width, mode);
14269 if (!rtx_equal_p (operands[0], operands[1]))
14270 emit_move_insn (operands[0], operands[1]);
14271 emit_insn ((mode == DImode
14273 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14274 ix86_expand_ashl_const (low[0], count, mode);
14279 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14281 if (operands[1] == const1_rtx)
14283 /* Assuming we've chosen a QImode capable registers, then 1 << N
14284 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14285 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14287 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14289 ix86_expand_clear (low[0]);
14290 ix86_expand_clear (high[0]);
14291 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14293 d = gen_lowpart (QImode, low[0]);
14294 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14295 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14296 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14298 d = gen_lowpart (QImode, high[0]);
14299 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14300 s = gen_rtx_NE (QImode, flags, const0_rtx);
14301 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14304 /* Otherwise, we can get the same results by manually performing
14305 a bit extract operation on bit 5/6, and then performing the two
14306 shifts. The two methods of getting 0/1 into low/high are exactly
14307 the same size. Avoiding the shift in the bit extract case helps
14308 pentium4 a bit; no one else seems to care much either way. */
14313 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14314 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14316 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14317 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14319 emit_insn ((mode == DImode
14321 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14322 emit_insn ((mode == DImode
14324 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14325 emit_move_insn (low[0], high[0]);
14326 emit_insn ((mode == DImode
14328 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14331 emit_insn ((mode == DImode
14333 : gen_ashldi3) (low[0], low[0], operands[2]));
14334 emit_insn ((mode == DImode
14336 : gen_ashldi3) (high[0], high[0], operands[2]));
14340 if (operands[1] == constm1_rtx)
14342 /* For -1 << N, we can avoid the shld instruction, because we
14343 know that we're shifting 0...31/63 ones into a -1. */
14344 emit_move_insn (low[0], constm1_rtx);
14346 emit_move_insn (high[0], low[0]);
14348 emit_move_insn (high[0], constm1_rtx);
14352 if (!rtx_equal_p (operands[0], operands[1]))
14353 emit_move_insn (operands[0], operands[1]);
14355 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14356 emit_insn ((mode == DImode
14358 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14361 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14363 if (TARGET_CMOVE && scratch)
14365 ix86_expand_clear (scratch);
14366 emit_insn ((mode == DImode
14367 ? gen_x86_shift_adj_1
14368 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14371 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14375 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14377 rtx low[2], high[2];
14379 const int single_width = mode == DImode ? 32 : 64;
14381 if (CONST_INT_P (operands[2]))
14383 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14384 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14386 if (count == single_width * 2 - 1)
14388 emit_move_insn (high[0], high[1]);
14389 emit_insn ((mode == DImode
14391 : gen_ashrdi3) (high[0], high[0],
14392 GEN_INT (single_width - 1)));
14393 emit_move_insn (low[0], high[0]);
14396 else if (count >= single_width)
14398 emit_move_insn (low[0], high[1]);
14399 emit_move_insn (high[0], low[0]);
14400 emit_insn ((mode == DImode
14402 : gen_ashrdi3) (high[0], high[0],
14403 GEN_INT (single_width - 1)));
14404 if (count > single_width)
14405 emit_insn ((mode == DImode
14407 : gen_ashrdi3) (low[0], low[0],
14408 GEN_INT (count - single_width)));
14412 if (!rtx_equal_p (operands[0], operands[1]))
14413 emit_move_insn (operands[0], operands[1]);
14414 emit_insn ((mode == DImode
14416 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14417 emit_insn ((mode == DImode
14419 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14424 if (!rtx_equal_p (operands[0], operands[1]))
14425 emit_move_insn (operands[0], operands[1]);
14427 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14429 emit_insn ((mode == DImode
14431 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14432 emit_insn ((mode == DImode
14434 : gen_ashrdi3) (high[0], high[0], operands[2]));
14436 if (TARGET_CMOVE && scratch)
14438 emit_move_insn (scratch, high[0]);
14439 emit_insn ((mode == DImode
14441 : gen_ashrdi3) (scratch, scratch,
14442 GEN_INT (single_width - 1)));
14443 emit_insn ((mode == DImode
14444 ? gen_x86_shift_adj_1
14445 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14449 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14454 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14456 rtx low[2], high[2];
14458 const int single_width = mode == DImode ? 32 : 64;
14460 if (CONST_INT_P (operands[2]))
14462 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14463 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14465 if (count >= single_width)
14467 emit_move_insn (low[0], high[1]);
14468 ix86_expand_clear (high[0]);
14470 if (count > single_width)
14471 emit_insn ((mode == DImode
14473 : gen_lshrdi3) (low[0], low[0],
14474 GEN_INT (count - single_width)));
14478 if (!rtx_equal_p (operands[0], operands[1]))
14479 emit_move_insn (operands[0], operands[1]);
14480 emit_insn ((mode == DImode
14482 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14483 emit_insn ((mode == DImode
14485 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14490 if (!rtx_equal_p (operands[0], operands[1]))
14491 emit_move_insn (operands[0], operands[1]);
14493 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14495 emit_insn ((mode == DImode
14497 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14498 emit_insn ((mode == DImode
14500 : gen_lshrdi3) (high[0], high[0], operands[2]));
14502 /* Heh. By reversing the arguments, we can reuse this pattern. */
14503 if (TARGET_CMOVE && scratch)
14505 ix86_expand_clear (scratch);
14506 emit_insn ((mode == DImode
14507 ? gen_x86_shift_adj_1
14508 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14512 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14516 /* Predict just emitted jump instruction to be taken with probability PROB. */
14518 predict_jump (int prob)
14520 rtx insn = get_last_insn ();
14521 gcc_assert (JUMP_P (insn));
14523 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14528 /* Helper function for the string operations below. Dest VARIABLE whether
14529 it is aligned to VALUE bytes. If true, jump to the label. */
14531 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14533 rtx label = gen_label_rtx ();
14534 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14535 if (GET_MODE (variable) == DImode)
14536 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14538 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14539 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14542 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14544 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14548 /* Adjust COUNTER by the VALUE. */
14550 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14552 if (GET_MODE (countreg) == DImode)
14553 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14555 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14558 /* Zero extend possibly SImode EXP to Pmode register. */
14560 ix86_zero_extend_to_Pmode (rtx exp)
14563 if (GET_MODE (exp) == VOIDmode)
14564 return force_reg (Pmode, exp);
14565 if (GET_MODE (exp) == Pmode)
14566 return copy_to_mode_reg (Pmode, exp);
14567 r = gen_reg_rtx (Pmode);
14568 emit_insn (gen_zero_extendsidi2 (r, exp));
14572 /* Divide COUNTREG by SCALE. */
14574 scale_counter (rtx countreg, int scale)
14577 rtx piece_size_mask;
14581 if (CONST_INT_P (countreg))
14582 return GEN_INT (INTVAL (countreg) / scale);
14583 gcc_assert (REG_P (countreg));
14585 piece_size_mask = GEN_INT (scale - 1);
14586 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14587 GEN_INT (exact_log2 (scale)),
14588 NULL, 1, OPTAB_DIRECT);
14592 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14593 DImode for constant loop counts. */
14595 static enum machine_mode
14596 counter_mode (rtx count_exp)
14598 if (GET_MODE (count_exp) != VOIDmode)
14599 return GET_MODE (count_exp);
14600 if (GET_CODE (count_exp) != CONST_INT)
14602 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14607 /* When SRCPTR is non-NULL, output simple loop to move memory
14608 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14609 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14610 equivalent loop to set memory by VALUE (supposed to be in MODE).
14612 The size is rounded down to whole number of chunk size moved at once.
14613 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14617 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14618 rtx destptr, rtx srcptr, rtx value,
14619 rtx count, enum machine_mode mode, int unroll,
14622 rtx out_label, top_label, iter, tmp;
14623 enum machine_mode iter_mode = counter_mode (count);
14624 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14625 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14631 top_label = gen_label_rtx ();
14632 out_label = gen_label_rtx ();
14633 iter = gen_reg_rtx (iter_mode);
14635 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14636 NULL, 1, OPTAB_DIRECT);
14637 /* Those two should combine. */
14638 if (piece_size == const1_rtx)
14640 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14642 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14644 emit_move_insn (iter, const0_rtx);
14646 emit_label (top_label);
14648 tmp = convert_modes (Pmode, iter_mode, iter, true);
14649 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14650 destmem = change_address (destmem, mode, x_addr);
14654 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14655 srcmem = change_address (srcmem, mode, y_addr);
14657 /* When unrolling for chips that reorder memory reads and writes,
14658 we can save registers by using single temporary.
14659 Also using 4 temporaries is overkill in 32bit mode. */
14660 if (!TARGET_64BIT && 0)
14662 for (i = 0; i < unroll; i++)
14667 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14669 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14671 emit_move_insn (destmem, srcmem);
14677 gcc_assert (unroll <= 4);
14678 for (i = 0; i < unroll; i++)
14680 tmpreg[i] = gen_reg_rtx (mode);
14684 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14686 emit_move_insn (tmpreg[i], srcmem);
14688 for (i = 0; i < unroll; i++)
14693 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14695 emit_move_insn (destmem, tmpreg[i]);
14700 for (i = 0; i < unroll; i++)
14704 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14705 emit_move_insn (destmem, value);
14708 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14709 true, OPTAB_LIB_WIDEN);
14711 emit_move_insn (iter, tmp);
14713 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14715 if (expected_size != -1)
14717 expected_size /= GET_MODE_SIZE (mode) * unroll;
14718 if (expected_size == 0)
14720 else if (expected_size > REG_BR_PROB_BASE)
14721 predict_jump (REG_BR_PROB_BASE - 1);
14723 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14726 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14727 iter = ix86_zero_extend_to_Pmode (iter);
14728 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14729 true, OPTAB_LIB_WIDEN);
14730 if (tmp != destptr)
14731 emit_move_insn (destptr, tmp);
14734 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14735 true, OPTAB_LIB_WIDEN);
14737 emit_move_insn (srcptr, tmp);
14739 emit_label (out_label);
14742 /* Output "rep; mov" instruction.
14743 Arguments have same meaning as for previous function */
14745 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14746 rtx destptr, rtx srcptr,
14748 enum machine_mode mode)
14754 /* If the size is known, it is shorter to use rep movs. */
14755 if (mode == QImode && CONST_INT_P (count)
14756 && !(INTVAL (count) & 3))
14759 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14760 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14761 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14762 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14763 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14764 if (mode != QImode)
14766 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14767 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14768 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14769 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14770 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14771 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14775 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14776 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14778 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14782 /* Output "rep; stos" instruction.
14783 Arguments have same meaning as for previous function */
14785 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14787 enum machine_mode mode)
14792 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14793 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14794 value = force_reg (mode, gen_lowpart (mode, value));
14795 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14796 if (mode != QImode)
14798 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14799 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14800 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14803 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14804 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14808 emit_strmov (rtx destmem, rtx srcmem,
14809 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14811 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14812 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14813 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14816 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14818 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14819 rtx destptr, rtx srcptr, rtx count, int max_size)
14822 if (CONST_INT_P (count))
14824 HOST_WIDE_INT countval = INTVAL (count);
14827 if ((countval & 0x10) && max_size > 16)
14831 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14832 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14835 gcc_unreachable ();
14838 if ((countval & 0x08) && max_size > 8)
14841 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14844 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14845 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14849 if ((countval & 0x04) && max_size > 4)
14851 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14854 if ((countval & 0x02) && max_size > 2)
14856 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14859 if ((countval & 0x01) && max_size > 1)
14861 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14868 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14869 count, 1, OPTAB_DIRECT);
14870 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14871 count, QImode, 1, 4);
14875 /* When there are stringops, we can cheaply increase dest and src pointers.
14876 Otherwise we save code size by maintaining offset (zero is readily
14877 available from preceding rep operation) and using x86 addressing modes.
14879 if (TARGET_SINGLE_STRINGOP)
14883 rtx label = ix86_expand_aligntest (count, 4, true);
14884 src = change_address (srcmem, SImode, srcptr);
14885 dest = change_address (destmem, SImode, destptr);
14886 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14887 emit_label (label);
14888 LABEL_NUSES (label) = 1;
14892 rtx label = ix86_expand_aligntest (count, 2, true);
14893 src = change_address (srcmem, HImode, srcptr);
14894 dest = change_address (destmem, HImode, destptr);
14895 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14896 emit_label (label);
14897 LABEL_NUSES (label) = 1;
14901 rtx label = ix86_expand_aligntest (count, 1, true);
14902 src = change_address (srcmem, QImode, srcptr);
14903 dest = change_address (destmem, QImode, destptr);
14904 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14905 emit_label (label);
14906 LABEL_NUSES (label) = 1;
14911 rtx offset = force_reg (Pmode, const0_rtx);
14916 rtx label = ix86_expand_aligntest (count, 4, true);
14917 src = change_address (srcmem, SImode, srcptr);
14918 dest = change_address (destmem, SImode, destptr);
14919 emit_move_insn (dest, src);
14920 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14921 true, OPTAB_LIB_WIDEN);
14923 emit_move_insn (offset, tmp);
14924 emit_label (label);
14925 LABEL_NUSES (label) = 1;
14929 rtx label = ix86_expand_aligntest (count, 2, true);
14930 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14931 src = change_address (srcmem, HImode, tmp);
14932 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14933 dest = change_address (destmem, HImode, tmp);
14934 emit_move_insn (dest, src);
14935 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14936 true, OPTAB_LIB_WIDEN);
14938 emit_move_insn (offset, tmp);
14939 emit_label (label);
14940 LABEL_NUSES (label) = 1;
14944 rtx label = ix86_expand_aligntest (count, 1, true);
14945 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14946 src = change_address (srcmem, QImode, tmp);
14947 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14948 dest = change_address (destmem, QImode, tmp);
14949 emit_move_insn (dest, src);
14950 emit_label (label);
14951 LABEL_NUSES (label) = 1;
14956 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14958 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14959 rtx count, int max_size)
14962 expand_simple_binop (counter_mode (count), AND, count,
14963 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14964 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14965 gen_lowpart (QImode, value), count, QImode,
14969 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14971 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14975 if (CONST_INT_P (count))
14977 HOST_WIDE_INT countval = INTVAL (count);
14980 if ((countval & 0x10) && max_size > 16)
14984 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14985 emit_insn (gen_strset (destptr, dest, value));
14986 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14987 emit_insn (gen_strset (destptr, dest, value));
14990 gcc_unreachable ();
14993 if ((countval & 0x08) && max_size > 8)
14997 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14998 emit_insn (gen_strset (destptr, dest, value));
15002 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15003 emit_insn (gen_strset (destptr, dest, value));
15004 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15005 emit_insn (gen_strset (destptr, dest, value));
15009 if ((countval & 0x04) && max_size > 4)
15011 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15012 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15015 if ((countval & 0x02) && max_size > 2)
15017 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15018 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15021 if ((countval & 0x01) && max_size > 1)
15023 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15024 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15031 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15036 rtx label = ix86_expand_aligntest (count, 16, true);
15039 dest = change_address (destmem, DImode, destptr);
15040 emit_insn (gen_strset (destptr, dest, value));
15041 emit_insn (gen_strset (destptr, dest, value));
15045 dest = change_address (destmem, SImode, destptr);
15046 emit_insn (gen_strset (destptr, dest, value));
15047 emit_insn (gen_strset (destptr, dest, value));
15048 emit_insn (gen_strset (destptr, dest, value));
15049 emit_insn (gen_strset (destptr, dest, value));
15051 emit_label (label);
15052 LABEL_NUSES (label) = 1;
15056 rtx label = ix86_expand_aligntest (count, 8, true);
15059 dest = change_address (destmem, DImode, destptr);
15060 emit_insn (gen_strset (destptr, dest, value));
15064 dest = change_address (destmem, SImode, destptr);
15065 emit_insn (gen_strset (destptr, dest, value));
15066 emit_insn (gen_strset (destptr, dest, value));
15068 emit_label (label);
15069 LABEL_NUSES (label) = 1;
15073 rtx label = ix86_expand_aligntest (count, 4, true);
15074 dest = change_address (destmem, SImode, destptr);
15075 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15076 emit_label (label);
15077 LABEL_NUSES (label) = 1;
15081 rtx label = ix86_expand_aligntest (count, 2, true);
15082 dest = change_address (destmem, HImode, destptr);
15083 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15084 emit_label (label);
15085 LABEL_NUSES (label) = 1;
15089 rtx label = ix86_expand_aligntest (count, 1, true);
15090 dest = change_address (destmem, QImode, destptr);
15091 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15092 emit_label (label);
15093 LABEL_NUSES (label) = 1;
15097 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15098 DESIRED_ALIGNMENT. */
15100 expand_movmem_prologue (rtx destmem, rtx srcmem,
15101 rtx destptr, rtx srcptr, rtx count,
15102 int align, int desired_alignment)
15104 if (align <= 1 && desired_alignment > 1)
15106 rtx label = ix86_expand_aligntest (destptr, 1, false);
15107 srcmem = change_address (srcmem, QImode, srcptr);
15108 destmem = change_address (destmem, QImode, destptr);
15109 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15110 ix86_adjust_counter (count, 1);
15111 emit_label (label);
15112 LABEL_NUSES (label) = 1;
15114 if (align <= 2 && desired_alignment > 2)
15116 rtx label = ix86_expand_aligntest (destptr, 2, false);
15117 srcmem = change_address (srcmem, HImode, srcptr);
15118 destmem = change_address (destmem, HImode, destptr);
15119 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15120 ix86_adjust_counter (count, 2);
15121 emit_label (label);
15122 LABEL_NUSES (label) = 1;
15124 if (align <= 4 && desired_alignment > 4)
15126 rtx label = ix86_expand_aligntest (destptr, 4, false);
15127 srcmem = change_address (srcmem, SImode, srcptr);
15128 destmem = change_address (destmem, SImode, destptr);
15129 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15130 ix86_adjust_counter (count, 4);
15131 emit_label (label);
15132 LABEL_NUSES (label) = 1;
15134 gcc_assert (desired_alignment <= 8);
15137 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15138 DESIRED_ALIGNMENT. */
15140 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15141 int align, int desired_alignment)
15143 if (align <= 1 && desired_alignment > 1)
15145 rtx label = ix86_expand_aligntest (destptr, 1, false);
15146 destmem = change_address (destmem, QImode, destptr);
15147 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15148 ix86_adjust_counter (count, 1);
15149 emit_label (label);
15150 LABEL_NUSES (label) = 1;
15152 if (align <= 2 && desired_alignment > 2)
15154 rtx label = ix86_expand_aligntest (destptr, 2, false);
15155 destmem = change_address (destmem, HImode, destptr);
15156 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15157 ix86_adjust_counter (count, 2);
15158 emit_label (label);
15159 LABEL_NUSES (label) = 1;
15161 if (align <= 4 && desired_alignment > 4)
15163 rtx label = ix86_expand_aligntest (destptr, 4, false);
15164 destmem = change_address (destmem, SImode, destptr);
15165 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15166 ix86_adjust_counter (count, 4);
15167 emit_label (label);
15168 LABEL_NUSES (label) = 1;
15170 gcc_assert (desired_alignment <= 8);
15173 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15174 static enum stringop_alg
15175 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15176 int *dynamic_check)
15178 const struct stringop_algs * algs;
15179 /* Algorithms using the rep prefix want at least edi and ecx;
15180 additionally, memset wants eax and memcpy wants esi. Don't
15181 consider such algorithms if the user has appropriated those
15182 registers for their own purposes. */
15183 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15185 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15187 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15188 || (alg != rep_prefix_1_byte \
15189 && alg != rep_prefix_4_byte \
15190 && alg != rep_prefix_8_byte))
15192 *dynamic_check = -1;
15194 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15196 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15197 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15198 return stringop_alg;
15199 /* rep; movq or rep; movl is the smallest variant. */
15200 else if (optimize_size)
15202 if (!count || (count & 3))
15203 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15205 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15207 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15209 else if (expected_size != -1 && expected_size < 4)
15210 return loop_1_byte;
15211 else if (expected_size != -1)
15214 enum stringop_alg alg = libcall;
15215 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15217 /* We get here if the algorithms that were not libcall-based
15218 were rep-prefix based and we are unable to use rep prefixes
15219 based on global register usage. Break out of the loop and
15220 use the heuristic below. */
15221 if (algs->size[i].max == 0)
15223 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15225 enum stringop_alg candidate = algs->size[i].alg;
15227 if (candidate != libcall && ALG_USABLE_P (candidate))
15229 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15230 last non-libcall inline algorithm. */
15231 if (TARGET_INLINE_ALL_STRINGOPS)
15233 /* When the current size is best to be copied by a libcall,
15234 but we are still forced to inline, run the heuristic below
15235 that will pick code for medium sized blocks. */
15236 if (alg != libcall)
15240 else if (ALG_USABLE_P (candidate))
15244 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15246 /* When asked to inline the call anyway, try to pick meaningful choice.
15247 We look for maximal size of block that is faster to copy by hand and
15248 take blocks of at most of that size guessing that average size will
15249 be roughly half of the block.
15251 If this turns out to be bad, we might simply specify the preferred
15252 choice in ix86_costs. */
15253 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15254 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15257 enum stringop_alg alg;
15259 bool any_alg_usable_p = true;
15261 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15263 enum stringop_alg candidate = algs->size[i].alg;
15264 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15266 if (candidate != libcall && candidate
15267 && ALG_USABLE_P (candidate))
15268 max = algs->size[i].max;
15270 /* If there aren't any usable algorithms, then recursing on
15271 smaller sizes isn't going to find anything. Just return the
15272 simple byte-at-a-time copy loop. */
15273 if (!any_alg_usable_p)
15275 /* Pick something reasonable. */
15276 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15277 *dynamic_check = 128;
15278 return loop_1_byte;
15282 alg = decide_alg (count, max / 2, memset, dynamic_check);
15283 gcc_assert (*dynamic_check == -1);
15284 gcc_assert (alg != libcall);
15285 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15286 *dynamic_check = max;
15289 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15290 #undef ALG_USABLE_P
15293 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15294 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15296 decide_alignment (int align,
15297 enum stringop_alg alg,
15300 int desired_align = 0;
15304 gcc_unreachable ();
15306 case unrolled_loop:
15307 desired_align = GET_MODE_SIZE (Pmode);
15309 case rep_prefix_8_byte:
15312 case rep_prefix_4_byte:
15313 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15314 copying whole cacheline at once. */
15315 if (TARGET_PENTIUMPRO)
15320 case rep_prefix_1_byte:
15321 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15322 copying whole cacheline at once. */
15323 if (TARGET_PENTIUMPRO)
15337 if (desired_align < align)
15338 desired_align = align;
15339 if (expected_size != -1 && expected_size < 4)
15340 desired_align = align;
15341 return desired_align;
15344 /* Return the smallest power of 2 greater than VAL. */
15346 smallest_pow2_greater_than (int val)
15354 /* Expand string move (memcpy) operation. Use i386 string operations when
15355 profitable. expand_setmem contains similar code. The code depends upon
15356 architecture, block size and alignment, but always has the same
15359 1) Prologue guard: Conditional that jumps up to epilogues for small
15360 blocks that can be handled by epilogue alone. This is faster but
15361 also needed for correctness, since prologue assume the block is larger
15362 than the desired alignment.
15364 Optional dynamic check for size and libcall for large
15365 blocks is emitted here too, with -minline-stringops-dynamically.
15367 2) Prologue: copy first few bytes in order to get destination aligned
15368 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15369 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15370 We emit either a jump tree on power of two sized blocks, or a byte loop.
15372 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15373 with specified algorithm.
15375 4) Epilogue: code copying tail of the block that is too small to be
15376 handled by main body (or up to size guarded by prologue guard). */
15379 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15380 rtx expected_align_exp, rtx expected_size_exp)
15386 rtx jump_around_label = NULL;
15387 HOST_WIDE_INT align = 1;
15388 unsigned HOST_WIDE_INT count = 0;
15389 HOST_WIDE_INT expected_size = -1;
15390 int size_needed = 0, epilogue_size_needed;
15391 int desired_align = 0;
15392 enum stringop_alg alg;
15395 if (CONST_INT_P (align_exp))
15396 align = INTVAL (align_exp);
15397 /* i386 can do misaligned access on reasonably increased cost. */
15398 if (CONST_INT_P (expected_align_exp)
15399 && INTVAL (expected_align_exp) > align)
15400 align = INTVAL (expected_align_exp);
15401 if (CONST_INT_P (count_exp))
15402 count = expected_size = INTVAL (count_exp);
15403 if (CONST_INT_P (expected_size_exp) && count == 0)
15404 expected_size = INTVAL (expected_size_exp);
15406 /* Make sure we don't need to care about overflow later on. */
15407 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15410 /* Step 0: Decide on preferred algorithm, desired alignment and
15411 size of chunks to be copied by main loop. */
15413 alg = decide_alg (count, expected_size, false, &dynamic_check);
15414 desired_align = decide_alignment (align, alg, expected_size);
15416 if (!TARGET_ALIGN_STRINGOPS)
15417 align = desired_align;
15419 if (alg == libcall)
15421 gcc_assert (alg != no_stringop);
15423 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15424 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15425 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15430 gcc_unreachable ();
15432 size_needed = GET_MODE_SIZE (Pmode);
15434 case unrolled_loop:
15435 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15437 case rep_prefix_8_byte:
15440 case rep_prefix_4_byte:
15443 case rep_prefix_1_byte:
15449 epilogue_size_needed = size_needed;
15451 /* Step 1: Prologue guard. */
15453 /* Alignment code needs count to be in register. */
15454 if (CONST_INT_P (count_exp) && desired_align > align)
15455 count_exp = force_reg (counter_mode (count_exp), count_exp);
15456 gcc_assert (desired_align >= 1 && align >= 1);
15458 /* Ensure that alignment prologue won't copy past end of block. */
15459 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15461 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15462 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15463 Make sure it is power of 2. */
15464 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15466 if (CONST_INT_P (count_exp))
15468 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15473 label = gen_label_rtx ();
15474 emit_cmp_and_jump_insns (count_exp,
15475 GEN_INT (epilogue_size_needed),
15476 LTU, 0, counter_mode (count_exp), 1, label);
15477 if (expected_size == -1 || expected_size < epilogue_size_needed)
15478 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15480 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15484 /* Emit code to decide on runtime whether library call or inline should be
15486 if (dynamic_check != -1)
15488 if (CONST_INT_P (count_exp))
15490 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15492 emit_block_move_via_libcall (dst, src, count_exp, false);
15493 count_exp = const0_rtx;
15499 rtx hot_label = gen_label_rtx ();
15500 jump_around_label = gen_label_rtx ();
15501 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15502 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15503 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15504 emit_block_move_via_libcall (dst, src, count_exp, false);
15505 emit_jump (jump_around_label);
15506 emit_label (hot_label);
15510 /* Step 2: Alignment prologue. */
15512 if (desired_align > align)
15514 /* Except for the first move in epilogue, we no longer know
15515 constant offset in aliasing info. It don't seems to worth
15516 the pain to maintain it for the first move, so throw away
15518 src = change_address (src, BLKmode, srcreg);
15519 dst = change_address (dst, BLKmode, destreg);
15520 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15523 if (label && size_needed == 1)
15525 emit_label (label);
15526 LABEL_NUSES (label) = 1;
15530 /* Step 3: Main loop. */
15536 gcc_unreachable ();
15538 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15539 count_exp, QImode, 1, expected_size);
15542 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15543 count_exp, Pmode, 1, expected_size);
15545 case unrolled_loop:
15546 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15547 registers for 4 temporaries anyway. */
15548 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15549 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15552 case rep_prefix_8_byte:
15553 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15556 case rep_prefix_4_byte:
15557 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15560 case rep_prefix_1_byte:
15561 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15565 /* Adjust properly the offset of src and dest memory for aliasing. */
15566 if (CONST_INT_P (count_exp))
15568 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15569 (count / size_needed) * size_needed);
15570 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15571 (count / size_needed) * size_needed);
15575 src = change_address (src, BLKmode, srcreg);
15576 dst = change_address (dst, BLKmode, destreg);
15579 /* Step 4: Epilogue to copy the remaining bytes. */
15583 /* When the main loop is done, COUNT_EXP might hold original count,
15584 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15585 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15586 bytes. Compensate if needed. */
15588 if (size_needed < epilogue_size_needed)
15591 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15592 GEN_INT (size_needed - 1), count_exp, 1,
15594 if (tmp != count_exp)
15595 emit_move_insn (count_exp, tmp);
15597 emit_label (label);
15598 LABEL_NUSES (label) = 1;
15601 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15602 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15603 epilogue_size_needed);
15604 if (jump_around_label)
15605 emit_label (jump_around_label);
15609 /* Helper function for memcpy. For QImode value 0xXY produce
15610 0xXYXYXYXY of wide specified by MODE. This is essentially
15611 a * 0x10101010, but we can do slightly better than
15612 synth_mult by unwinding the sequence by hand on CPUs with
15615 promote_duplicated_reg (enum machine_mode mode, rtx val)
15617 enum machine_mode valmode = GET_MODE (val);
15619 int nops = mode == DImode ? 3 : 2;
15621 gcc_assert (mode == SImode || mode == DImode);
15622 if (val == const0_rtx)
15623 return copy_to_mode_reg (mode, const0_rtx);
15624 if (CONST_INT_P (val))
15626 HOST_WIDE_INT v = INTVAL (val) & 255;
15630 if (mode == DImode)
15631 v |= (v << 16) << 16;
15632 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15635 if (valmode == VOIDmode)
15637 if (valmode != QImode)
15638 val = gen_lowpart (QImode, val);
15639 if (mode == QImode)
15641 if (!TARGET_PARTIAL_REG_STALL)
15643 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15644 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15645 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15646 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15648 rtx reg = convert_modes (mode, QImode, val, true);
15649 tmp = promote_duplicated_reg (mode, const1_rtx);
15650 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15655 rtx reg = convert_modes (mode, QImode, val, true);
15657 if (!TARGET_PARTIAL_REG_STALL)
15658 if (mode == SImode)
15659 emit_insn (gen_movsi_insv_1 (reg, reg));
15661 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15664 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15665 NULL, 1, OPTAB_DIRECT);
15667 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15669 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15670 NULL, 1, OPTAB_DIRECT);
15671 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15672 if (mode == SImode)
15674 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15675 NULL, 1, OPTAB_DIRECT);
15676 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15681 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15682 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15683 alignment from ALIGN to DESIRED_ALIGN. */
15685 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15690 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15691 promoted_val = promote_duplicated_reg (DImode, val);
15692 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15693 promoted_val = promote_duplicated_reg (SImode, val);
15694 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15695 promoted_val = promote_duplicated_reg (HImode, val);
15697 promoted_val = val;
15699 return promoted_val;
15702 /* Expand string clear operation (bzero). Use i386 string operations when
15703 profitable. See expand_movmem comment for explanation of individual
15704 steps performed. */
15706 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15707 rtx expected_align_exp, rtx expected_size_exp)
15712 rtx jump_around_label = NULL;
15713 HOST_WIDE_INT align = 1;
15714 unsigned HOST_WIDE_INT count = 0;
15715 HOST_WIDE_INT expected_size = -1;
15716 int size_needed = 0, epilogue_size_needed;
15717 int desired_align = 0;
15718 enum stringop_alg alg;
15719 rtx promoted_val = NULL;
15720 bool force_loopy_epilogue = false;
15723 if (CONST_INT_P (align_exp))
15724 align = INTVAL (align_exp);
15725 /* i386 can do misaligned access on reasonably increased cost. */
15726 if (CONST_INT_P (expected_align_exp)
15727 && INTVAL (expected_align_exp) > align)
15728 align = INTVAL (expected_align_exp);
15729 if (CONST_INT_P (count_exp))
15730 count = expected_size = INTVAL (count_exp);
15731 if (CONST_INT_P (expected_size_exp) && count == 0)
15732 expected_size = INTVAL (expected_size_exp);
15734 /* Make sure we don't need to care about overflow later on. */
15735 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15738 /* Step 0: Decide on preferred algorithm, desired alignment and
15739 size of chunks to be copied by main loop. */
15741 alg = decide_alg (count, expected_size, true, &dynamic_check);
15742 desired_align = decide_alignment (align, alg, expected_size);
15744 if (!TARGET_ALIGN_STRINGOPS)
15745 align = desired_align;
15747 if (alg == libcall)
15749 gcc_assert (alg != no_stringop);
15751 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15752 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15757 gcc_unreachable ();
15759 size_needed = GET_MODE_SIZE (Pmode);
15761 case unrolled_loop:
15762 size_needed = GET_MODE_SIZE (Pmode) * 4;
15764 case rep_prefix_8_byte:
15767 case rep_prefix_4_byte:
15770 case rep_prefix_1_byte:
15775 epilogue_size_needed = size_needed;
15777 /* Step 1: Prologue guard. */
15779 /* Alignment code needs count to be in register. */
15780 if (CONST_INT_P (count_exp) && desired_align > align)
15782 enum machine_mode mode = SImode;
15783 if (TARGET_64BIT && (count & ~0xffffffff))
15785 count_exp = force_reg (mode, count_exp);
15787 /* Do the cheap promotion to allow better CSE across the
15788 main loop and epilogue (ie one load of the big constant in the
15789 front of all code. */
15790 if (CONST_INT_P (val_exp))
15791 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15792 desired_align, align);
15793 /* Ensure that alignment prologue won't copy past end of block. */
15794 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15796 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15797 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15798 Make sure it is power of 2. */
15799 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15801 /* To improve performance of small blocks, we jump around the VAL
15802 promoting mode. This mean that if the promoted VAL is not constant,
15803 we might not use it in the epilogue and have to use byte
15805 if (epilogue_size_needed > 2 && !promoted_val)
15806 force_loopy_epilogue = true;
15807 label = gen_label_rtx ();
15808 emit_cmp_and_jump_insns (count_exp,
15809 GEN_INT (epilogue_size_needed),
15810 LTU, 0, counter_mode (count_exp), 1, label);
15811 if (GET_CODE (count_exp) == CONST_INT)
15813 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15814 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15816 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15818 if (dynamic_check != -1)
15820 rtx hot_label = gen_label_rtx ();
15821 jump_around_label = gen_label_rtx ();
15822 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15823 LEU, 0, counter_mode (count_exp), 1, hot_label);
15824 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15825 set_storage_via_libcall (dst, count_exp, val_exp, false);
15826 emit_jump (jump_around_label);
15827 emit_label (hot_label);
15830 /* Step 2: Alignment prologue. */
15832 /* Do the expensive promotion once we branched off the small blocks. */
15834 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15835 desired_align, align);
15836 gcc_assert (desired_align >= 1 && align >= 1);
15838 if (desired_align > align)
15840 /* Except for the first move in epilogue, we no longer know
15841 constant offset in aliasing info. It don't seems to worth
15842 the pain to maintain it for the first move, so throw away
15844 dst = change_address (dst, BLKmode, destreg);
15845 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15848 if (label && size_needed == 1)
15850 emit_label (label);
15851 LABEL_NUSES (label) = 1;
15855 /* Step 3: Main loop. */
15861 gcc_unreachable ();
15863 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15864 count_exp, QImode, 1, expected_size);
15867 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15868 count_exp, Pmode, 1, expected_size);
15870 case unrolled_loop:
15871 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15872 count_exp, Pmode, 4, expected_size);
15874 case rep_prefix_8_byte:
15875 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15878 case rep_prefix_4_byte:
15879 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15882 case rep_prefix_1_byte:
15883 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15887 /* Adjust properly the offset of src and dest memory for aliasing. */
15888 if (CONST_INT_P (count_exp))
15889 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15890 (count / size_needed) * size_needed);
15892 dst = change_address (dst, BLKmode, destreg);
15894 /* Step 4: Epilogue to copy the remaining bytes. */
15898 /* When the main loop is done, COUNT_EXP might hold original count,
15899 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15900 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15901 bytes. Compensate if needed. */
15903 if (size_needed < desired_align - align)
15906 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15907 GEN_INT (size_needed - 1), count_exp, 1,
15909 size_needed = desired_align - align + 1;
15910 if (tmp != count_exp)
15911 emit_move_insn (count_exp, tmp);
15913 emit_label (label);
15914 LABEL_NUSES (label) = 1;
15916 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15918 if (force_loopy_epilogue)
15919 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15922 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15925 if (jump_around_label)
15926 emit_label (jump_around_label);
15930 /* Expand the appropriate insns for doing strlen if not just doing
15933 out = result, initialized with the start address
15934 align_rtx = alignment of the address.
15935 scratch = scratch register, initialized with the startaddress when
15936 not aligned, otherwise undefined
15938 This is just the body. It needs the initializations mentioned above and
15939 some address computing at the end. These things are done in i386.md. */
15942 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15946 rtx align_2_label = NULL_RTX;
15947 rtx align_3_label = NULL_RTX;
15948 rtx align_4_label = gen_label_rtx ();
15949 rtx end_0_label = gen_label_rtx ();
15951 rtx tmpreg = gen_reg_rtx (SImode);
15952 rtx scratch = gen_reg_rtx (SImode);
15956 if (CONST_INT_P (align_rtx))
15957 align = INTVAL (align_rtx);
15959 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15961 /* Is there a known alignment and is it less than 4? */
15964 rtx scratch1 = gen_reg_rtx (Pmode);
15965 emit_move_insn (scratch1, out);
15966 /* Is there a known alignment and is it not 2? */
15969 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15970 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15972 /* Leave just the 3 lower bits. */
15973 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15974 NULL_RTX, 0, OPTAB_WIDEN);
15976 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15977 Pmode, 1, align_4_label);
15978 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15979 Pmode, 1, align_2_label);
15980 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15981 Pmode, 1, align_3_label);
15985 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15986 check if is aligned to 4 - byte. */
15988 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
15989 NULL_RTX, 0, OPTAB_WIDEN);
15991 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15992 Pmode, 1, align_4_label);
15995 mem = change_address (src, QImode, out);
15997 /* Now compare the bytes. */
15999 /* Compare the first n unaligned byte on a byte per byte basis. */
16000 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16001 QImode, 1, end_0_label);
16003 /* Increment the address. */
16005 emit_insn (gen_adddi3 (out, out, const1_rtx));
16007 emit_insn (gen_addsi3 (out, out, const1_rtx));
16009 /* Not needed with an alignment of 2 */
16012 emit_label (align_2_label);
16014 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16018 emit_insn (gen_adddi3 (out, out, const1_rtx));
16020 emit_insn (gen_addsi3 (out, out, const1_rtx));
16022 emit_label (align_3_label);
16025 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16029 emit_insn (gen_adddi3 (out, out, const1_rtx));
16031 emit_insn (gen_addsi3 (out, out, const1_rtx));
16034 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16035 align this loop. It gives only huge programs, but does not help to
16037 emit_label (align_4_label);
16039 mem = change_address (src, SImode, out);
16040 emit_move_insn (scratch, mem);
16042 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
16044 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
16046 /* This formula yields a nonzero result iff one of the bytes is zero.
16047 This saves three branches inside loop and many cycles. */
16049 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16050 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16051 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16052 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16053 gen_int_mode (0x80808080, SImode)));
16054 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16059 rtx reg = gen_reg_rtx (SImode);
16060 rtx reg2 = gen_reg_rtx (Pmode);
16061 emit_move_insn (reg, tmpreg);
16062 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16064 /* If zero is not in the first two bytes, move two bytes forward. */
16065 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16066 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16067 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16068 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16069 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16072 /* Emit lea manually to avoid clobbering of flags. */
16073 emit_insn (gen_rtx_SET (SImode, reg2,
16074 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16076 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16077 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16078 emit_insn (gen_rtx_SET (VOIDmode, out,
16079 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16086 rtx end_2_label = gen_label_rtx ();
16087 /* Is zero in the first two bytes? */
16089 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16090 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16091 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16092 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16093 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16095 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16096 JUMP_LABEL (tmp) = end_2_label;
16098 /* Not in the first two. Move two bytes forward. */
16099 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16101 emit_insn (gen_adddi3 (out, out, const2_rtx));
16103 emit_insn (gen_addsi3 (out, out, const2_rtx));
16105 emit_label (end_2_label);
16109 /* Avoid branch in fixing the byte. */
16110 tmpreg = gen_lowpart (QImode, tmpreg);
16111 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16112 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16114 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
16116 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
16118 emit_label (end_0_label);
16121 /* Expand strlen. */
16124 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16126 rtx addr, scratch1, scratch2, scratch3, scratch4;
16128 /* The generic case of strlen expander is long. Avoid it's
16129 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16131 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16132 && !TARGET_INLINE_ALL_STRINGOPS
16134 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16137 addr = force_reg (Pmode, XEXP (src, 0));
16138 scratch1 = gen_reg_rtx (Pmode);
16140 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16143 /* Well it seems that some optimizer does not combine a call like
16144 foo(strlen(bar), strlen(bar));
16145 when the move and the subtraction is done here. It does calculate
16146 the length just once when these instructions are done inside of
16147 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16148 often used and I use one fewer register for the lifetime of
16149 output_strlen_unroll() this is better. */
16151 emit_move_insn (out, addr);
16153 ix86_expand_strlensi_unroll_1 (out, src, align);
16155 /* strlensi_unroll_1 returns the address of the zero at the end of
16156 the string, like memchr(), so compute the length by subtracting
16157 the start address. */
16159 emit_insn (gen_subdi3 (out, out, addr));
16161 emit_insn (gen_subsi3 (out, out, addr));
16167 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16168 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16171 scratch2 = gen_reg_rtx (Pmode);
16172 scratch3 = gen_reg_rtx (Pmode);
16173 scratch4 = force_reg (Pmode, constm1_rtx);
16175 emit_move_insn (scratch3, addr);
16176 eoschar = force_reg (QImode, eoschar);
16178 src = replace_equiv_address_nv (src, scratch3);
16180 /* If .md starts supporting :P, this can be done in .md. */
16181 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16182 scratch4), UNSPEC_SCAS);
16183 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16186 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16187 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16191 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16192 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16198 /* For given symbol (function) construct code to compute address of it's PLT
16199 entry in large x86-64 PIC model. */
16201 construct_plt_address (rtx symbol)
16203 rtx tmp = gen_reg_rtx (Pmode);
16204 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16206 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16207 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16209 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16210 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16215 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16216 rtx callarg2 ATTRIBUTE_UNUSED,
16217 rtx pop, int sibcall)
16219 rtx use = NULL, call;
16221 if (pop == const0_rtx)
16223 gcc_assert (!TARGET_64BIT || !pop);
16225 if (TARGET_MACHO && !TARGET_64BIT)
16228 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16229 fnaddr = machopic_indirect_call_target (fnaddr);
16234 /* Static functions and indirect calls don't need the pic register. */
16235 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16236 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16237 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16238 use_reg (&use, pic_offset_table_rtx);
16241 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16243 rtx al = gen_rtx_REG (QImode, AX_REG);
16244 emit_move_insn (al, callarg2);
16245 use_reg (&use, al);
16248 if (ix86_cmodel == CM_LARGE_PIC
16249 && GET_CODE (fnaddr) == MEM
16250 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16251 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16252 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16253 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16255 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16256 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16258 if (sibcall && TARGET_64BIT
16259 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16262 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16263 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16264 emit_move_insn (fnaddr, addr);
16265 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16268 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16270 call = gen_rtx_SET (VOIDmode, retval, call);
16273 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16274 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16275 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16278 call = emit_call_insn (call);
16280 CALL_INSN_FUNCTION_USAGE (call) = use;
16284 /* Clear stack slot assignments remembered from previous functions.
16285 This is called from INIT_EXPANDERS once before RTL is emitted for each
16288 static struct machine_function *
16289 ix86_init_machine_status (void)
16291 struct machine_function *f;
16293 f = GGC_CNEW (struct machine_function);
16294 f->use_fast_prologue_epilogue_nregs = -1;
16295 f->tls_descriptor_call_expanded_p = 0;
16300 /* Return a MEM corresponding to a stack slot with mode MODE.
16301 Allocate a new slot if necessary.
16303 The RTL for a function can have several slots available: N is
16304 which slot to use. */
16307 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16309 struct stack_local_entry *s;
16311 gcc_assert (n < MAX_386_STACK_LOCALS);
16313 /* Virtual slot is valid only before vregs are instantiated. */
16314 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16316 for (s = ix86_stack_locals; s; s = s->next)
16317 if (s->mode == mode && s->n == n)
16318 return copy_rtx (s->rtl);
16320 s = (struct stack_local_entry *)
16321 ggc_alloc (sizeof (struct stack_local_entry));
16324 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16326 s->next = ix86_stack_locals;
16327 ix86_stack_locals = s;
16331 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16333 static GTY(()) rtx ix86_tls_symbol;
16335 ix86_tls_get_addr (void)
16338 if (!ix86_tls_symbol)
16340 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16341 (TARGET_ANY_GNU_TLS
16343 ? "___tls_get_addr"
16344 : "__tls_get_addr");
16347 return ix86_tls_symbol;
16350 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16352 static GTY(()) rtx ix86_tls_module_base_symbol;
16354 ix86_tls_module_base (void)
16357 if (!ix86_tls_module_base_symbol)
16359 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16360 "_TLS_MODULE_BASE_");
16361 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16362 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16365 return ix86_tls_module_base_symbol;
16368 /* Calculate the length of the memory address in the instruction
16369 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16372 memory_address_length (rtx addr)
16374 struct ix86_address parts;
16375 rtx base, index, disp;
16379 if (GET_CODE (addr) == PRE_DEC
16380 || GET_CODE (addr) == POST_INC
16381 || GET_CODE (addr) == PRE_MODIFY
16382 || GET_CODE (addr) == POST_MODIFY)
16385 ok = ix86_decompose_address (addr, &parts);
16388 if (parts.base && GET_CODE (parts.base) == SUBREG)
16389 parts.base = SUBREG_REG (parts.base);
16390 if (parts.index && GET_CODE (parts.index) == SUBREG)
16391 parts.index = SUBREG_REG (parts.index);
16394 index = parts.index;
16399 - esp as the base always wants an index,
16400 - ebp as the base always wants a displacement. */
16402 /* Register Indirect. */
16403 if (base && !index && !disp)
16405 /* esp (for its index) and ebp (for its displacement) need
16406 the two-byte modrm form. */
16407 if (addr == stack_pointer_rtx
16408 || addr == arg_pointer_rtx
16409 || addr == frame_pointer_rtx
16410 || addr == hard_frame_pointer_rtx)
16414 /* Direct Addressing. */
16415 else if (disp && !base && !index)
16420 /* Find the length of the displacement constant. */
16423 if (base && satisfies_constraint_K (disp))
16428 /* ebp always wants a displacement. */
16429 else if (base == hard_frame_pointer_rtx)
16432 /* An index requires the two-byte modrm form.... */
16434 /* ...like esp, which always wants an index. */
16435 || base == stack_pointer_rtx
16436 || base == arg_pointer_rtx
16437 || base == frame_pointer_rtx)
16444 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16445 is set, expect that insn have 8bit immediate alternative. */
16447 ix86_attr_length_immediate_default (rtx insn, int shortform)
16451 extract_insn_cached (insn);
16452 for (i = recog_data.n_operands - 1; i >= 0; --i)
16453 if (CONSTANT_P (recog_data.operand[i]))
16456 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16460 switch (get_attr_mode (insn))
16471 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16476 fatal_insn ("unknown insn mode", insn);
16482 /* Compute default value for "length_address" attribute. */
16484 ix86_attr_length_address_default (rtx insn)
16488 if (get_attr_type (insn) == TYPE_LEA)
16490 rtx set = PATTERN (insn);
16492 if (GET_CODE (set) == PARALLEL)
16493 set = XVECEXP (set, 0, 0);
16495 gcc_assert (GET_CODE (set) == SET);
16497 return memory_address_length (SET_SRC (set));
16500 extract_insn_cached (insn);
16501 for (i = recog_data.n_operands - 1; i >= 0; --i)
16502 if (MEM_P (recog_data.operand[i]))
16504 return memory_address_length (XEXP (recog_data.operand[i], 0));
16510 /* Return the maximum number of instructions a cpu can issue. */
16513 ix86_issue_rate (void)
16517 case PROCESSOR_PENTIUM:
16521 case PROCESSOR_PENTIUMPRO:
16522 case PROCESSOR_PENTIUM4:
16523 case PROCESSOR_ATHLON:
16525 case PROCESSOR_AMDFAM10:
16526 case PROCESSOR_NOCONA:
16527 case PROCESSOR_GENERIC32:
16528 case PROCESSOR_GENERIC64:
16531 case PROCESSOR_CORE2:
16539 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16540 by DEP_INSN and nothing set by DEP_INSN. */
16543 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16547 /* Simplify the test for uninteresting insns. */
16548 if (insn_type != TYPE_SETCC
16549 && insn_type != TYPE_ICMOV
16550 && insn_type != TYPE_FCMOV
16551 && insn_type != TYPE_IBR)
16554 if ((set = single_set (dep_insn)) != 0)
16556 set = SET_DEST (set);
16559 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16560 && XVECLEN (PATTERN (dep_insn), 0) == 2
16561 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16562 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16564 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16565 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16570 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16573 /* This test is true if the dependent insn reads the flags but
16574 not any other potentially set register. */
16575 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16578 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16584 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16585 address with operands set by DEP_INSN. */
16588 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16592 if (insn_type == TYPE_LEA
16595 addr = PATTERN (insn);
16597 if (GET_CODE (addr) == PARALLEL)
16598 addr = XVECEXP (addr, 0, 0);
16600 gcc_assert (GET_CODE (addr) == SET);
16602 addr = SET_SRC (addr);
16607 extract_insn_cached (insn);
16608 for (i = recog_data.n_operands - 1; i >= 0; --i)
16609 if (MEM_P (recog_data.operand[i]))
16611 addr = XEXP (recog_data.operand[i], 0);
16618 return modified_in_p (addr, dep_insn);
16622 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16624 enum attr_type insn_type, dep_insn_type;
16625 enum attr_memory memory;
16627 int dep_insn_code_number;
16629 /* Anti and output dependencies have zero cost on all CPUs. */
16630 if (REG_NOTE_KIND (link) != 0)
16633 dep_insn_code_number = recog_memoized (dep_insn);
16635 /* If we can't recognize the insns, we can't really do anything. */
16636 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16639 insn_type = get_attr_type (insn);
16640 dep_insn_type = get_attr_type (dep_insn);
16644 case PROCESSOR_PENTIUM:
16645 /* Address Generation Interlock adds a cycle of latency. */
16646 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16649 /* ??? Compares pair with jump/setcc. */
16650 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16653 /* Floating point stores require value to be ready one cycle earlier. */
16654 if (insn_type == TYPE_FMOV
16655 && get_attr_memory (insn) == MEMORY_STORE
16656 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16660 case PROCESSOR_PENTIUMPRO:
16661 memory = get_attr_memory (insn);
16663 /* INT->FP conversion is expensive. */
16664 if (get_attr_fp_int_src (dep_insn))
16667 /* There is one cycle extra latency between an FP op and a store. */
16668 if (insn_type == TYPE_FMOV
16669 && (set = single_set (dep_insn)) != NULL_RTX
16670 && (set2 = single_set (insn)) != NULL_RTX
16671 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16672 && MEM_P (SET_DEST (set2)))
16675 /* Show ability of reorder buffer to hide latency of load by executing
16676 in parallel with previous instruction in case
16677 previous instruction is not needed to compute the address. */
16678 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16679 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16681 /* Claim moves to take one cycle, as core can issue one load
16682 at time and the next load can start cycle later. */
16683 if (dep_insn_type == TYPE_IMOV
16684 || dep_insn_type == TYPE_FMOV)
16692 memory = get_attr_memory (insn);
16694 /* The esp dependency is resolved before the instruction is really
16696 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16697 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16700 /* INT->FP conversion is expensive. */
16701 if (get_attr_fp_int_src (dep_insn))
16704 /* Show ability of reorder buffer to hide latency of load by executing
16705 in parallel with previous instruction in case
16706 previous instruction is not needed to compute the address. */
16707 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16708 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16710 /* Claim moves to take one cycle, as core can issue one load
16711 at time and the next load can start cycle later. */
16712 if (dep_insn_type == TYPE_IMOV
16713 || dep_insn_type == TYPE_FMOV)
16722 case PROCESSOR_ATHLON:
16724 case PROCESSOR_AMDFAM10:
16725 case PROCESSOR_GENERIC32:
16726 case PROCESSOR_GENERIC64:
16727 memory = get_attr_memory (insn);
16729 /* Show ability of reorder buffer to hide latency of load by executing
16730 in parallel with previous instruction in case
16731 previous instruction is not needed to compute the address. */
16732 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16733 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16735 enum attr_unit unit = get_attr_unit (insn);
16738 /* Because of the difference between the length of integer and
16739 floating unit pipeline preparation stages, the memory operands
16740 for floating point are cheaper.
16742 ??? For Athlon it the difference is most probably 2. */
16743 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16746 loadcost = TARGET_ATHLON ? 2 : 0;
16748 if (cost >= loadcost)
16761 /* How many alternative schedules to try. This should be as wide as the
16762 scheduling freedom in the DFA, but no wider. Making this value too
16763 large results extra work for the scheduler. */
16766 ia32_multipass_dfa_lookahead (void)
16770 case PROCESSOR_PENTIUM:
16773 case PROCESSOR_PENTIUMPRO:
16783 /* Compute the alignment given to a constant that is being placed in memory.
16784 EXP is the constant and ALIGN is the alignment that the object would
16786 The value of this function is used instead of that alignment to align
16790 ix86_constant_alignment (tree exp, int align)
16792 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
16793 || TREE_CODE (exp) == INTEGER_CST)
16795 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16797 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16800 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16801 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16802 return BITS_PER_WORD;
16807 /* Compute the alignment for a static variable.
16808 TYPE is the data type, and ALIGN is the alignment that
16809 the object would ordinarily have. The value of this function is used
16810 instead of that alignment to align the object. */
16813 ix86_data_alignment (tree type, int align)
16815 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16817 if (AGGREGATE_TYPE_P (type)
16818 && TYPE_SIZE (type)
16819 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16820 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16821 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16822 && align < max_align)
16825 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16826 to 16byte boundary. */
16829 if (AGGREGATE_TYPE_P (type)
16830 && TYPE_SIZE (type)
16831 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16832 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16833 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16837 if (TREE_CODE (type) == ARRAY_TYPE)
16839 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16841 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16844 else if (TREE_CODE (type) == COMPLEX_TYPE)
16847 if (TYPE_MODE (type) == DCmode && align < 64)
16849 if (TYPE_MODE (type) == XCmode && align < 128)
16852 else if ((TREE_CODE (type) == RECORD_TYPE
16853 || TREE_CODE (type) == UNION_TYPE
16854 || TREE_CODE (type) == QUAL_UNION_TYPE)
16855 && TYPE_FIELDS (type))
16857 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16859 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16862 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16863 || TREE_CODE (type) == INTEGER_TYPE)
16865 if (TYPE_MODE (type) == DFmode && align < 64)
16867 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16874 /* Compute the alignment for a local variable.
16875 TYPE is the data type, and ALIGN is the alignment that
16876 the object would ordinarily have. The value of this macro is used
16877 instead of that alignment to align the object. */
16880 ix86_local_alignment (tree type, int align)
16882 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16883 to 16byte boundary. */
16886 if (AGGREGATE_TYPE_P (type)
16887 && TYPE_SIZE (type)
16888 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16889 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16890 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16893 if (TREE_CODE (type) == ARRAY_TYPE)
16895 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16897 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16900 else if (TREE_CODE (type) == COMPLEX_TYPE)
16902 if (TYPE_MODE (type) == DCmode && align < 64)
16904 if (TYPE_MODE (type) == XCmode && align < 128)
16907 else if ((TREE_CODE (type) == RECORD_TYPE
16908 || TREE_CODE (type) == UNION_TYPE
16909 || TREE_CODE (type) == QUAL_UNION_TYPE)
16910 && TYPE_FIELDS (type))
16912 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16914 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16917 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16918 || TREE_CODE (type) == INTEGER_TYPE)
16921 if (TYPE_MODE (type) == DFmode && align < 64)
16923 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16929 /* Emit RTL insns to initialize the variable parts of a trampoline.
16930 FNADDR is an RTX for the address of the function's pure code.
16931 CXT is an RTX for the static chain value for the function. */
16933 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16937 /* Compute offset from the end of the jmp to the target function. */
16938 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16939 plus_constant (tramp, 10),
16940 NULL_RTX, 1, OPTAB_DIRECT);
16941 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16942 gen_int_mode (0xb9, QImode));
16943 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16944 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16945 gen_int_mode (0xe9, QImode));
16946 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16951 /* Try to load address using shorter movl instead of movabs.
16952 We may want to support movq for kernel mode, but kernel does not use
16953 trampolines at the moment. */
16954 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16956 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16957 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16958 gen_int_mode (0xbb41, HImode));
16959 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16960 gen_lowpart (SImode, fnaddr));
16965 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16966 gen_int_mode (0xbb49, HImode));
16967 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16971 /* Load static chain using movabs to r10. */
16972 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16973 gen_int_mode (0xba49, HImode));
16974 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16977 /* Jump to the r11 */
16978 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16979 gen_int_mode (0xff49, HImode));
16980 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16981 gen_int_mode (0xe3, QImode));
16983 gcc_assert (offset <= TRAMPOLINE_SIZE);
16986 #ifdef ENABLE_EXECUTE_STACK
16987 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
16988 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
16992 /* Codes for all the SSE/MMX builtins. */
16995 IX86_BUILTIN_ADDPS,
16996 IX86_BUILTIN_ADDSS,
16997 IX86_BUILTIN_DIVPS,
16998 IX86_BUILTIN_DIVSS,
16999 IX86_BUILTIN_MULPS,
17000 IX86_BUILTIN_MULSS,
17001 IX86_BUILTIN_SUBPS,
17002 IX86_BUILTIN_SUBSS,
17004 IX86_BUILTIN_CMPEQPS,
17005 IX86_BUILTIN_CMPLTPS,
17006 IX86_BUILTIN_CMPLEPS,
17007 IX86_BUILTIN_CMPGTPS,
17008 IX86_BUILTIN_CMPGEPS,
17009 IX86_BUILTIN_CMPNEQPS,
17010 IX86_BUILTIN_CMPNLTPS,
17011 IX86_BUILTIN_CMPNLEPS,
17012 IX86_BUILTIN_CMPNGTPS,
17013 IX86_BUILTIN_CMPNGEPS,
17014 IX86_BUILTIN_CMPORDPS,
17015 IX86_BUILTIN_CMPUNORDPS,
17016 IX86_BUILTIN_CMPEQSS,
17017 IX86_BUILTIN_CMPLTSS,
17018 IX86_BUILTIN_CMPLESS,
17019 IX86_BUILTIN_CMPNEQSS,
17020 IX86_BUILTIN_CMPNLTSS,
17021 IX86_BUILTIN_CMPNLESS,
17022 IX86_BUILTIN_CMPNGTSS,
17023 IX86_BUILTIN_CMPNGESS,
17024 IX86_BUILTIN_CMPORDSS,
17025 IX86_BUILTIN_CMPUNORDSS,
17027 IX86_BUILTIN_COMIEQSS,
17028 IX86_BUILTIN_COMILTSS,
17029 IX86_BUILTIN_COMILESS,
17030 IX86_BUILTIN_COMIGTSS,
17031 IX86_BUILTIN_COMIGESS,
17032 IX86_BUILTIN_COMINEQSS,
17033 IX86_BUILTIN_UCOMIEQSS,
17034 IX86_BUILTIN_UCOMILTSS,
17035 IX86_BUILTIN_UCOMILESS,
17036 IX86_BUILTIN_UCOMIGTSS,
17037 IX86_BUILTIN_UCOMIGESS,
17038 IX86_BUILTIN_UCOMINEQSS,
17040 IX86_BUILTIN_CVTPI2PS,
17041 IX86_BUILTIN_CVTPS2PI,
17042 IX86_BUILTIN_CVTSI2SS,
17043 IX86_BUILTIN_CVTSI642SS,
17044 IX86_BUILTIN_CVTSS2SI,
17045 IX86_BUILTIN_CVTSS2SI64,
17046 IX86_BUILTIN_CVTTPS2PI,
17047 IX86_BUILTIN_CVTTSS2SI,
17048 IX86_BUILTIN_CVTTSS2SI64,
17050 IX86_BUILTIN_MAXPS,
17051 IX86_BUILTIN_MAXSS,
17052 IX86_BUILTIN_MINPS,
17053 IX86_BUILTIN_MINSS,
17055 IX86_BUILTIN_LOADUPS,
17056 IX86_BUILTIN_STOREUPS,
17057 IX86_BUILTIN_MOVSS,
17059 IX86_BUILTIN_MOVHLPS,
17060 IX86_BUILTIN_MOVLHPS,
17061 IX86_BUILTIN_LOADHPS,
17062 IX86_BUILTIN_LOADLPS,
17063 IX86_BUILTIN_STOREHPS,
17064 IX86_BUILTIN_STORELPS,
17066 IX86_BUILTIN_MASKMOVQ,
17067 IX86_BUILTIN_MOVMSKPS,
17068 IX86_BUILTIN_PMOVMSKB,
17070 IX86_BUILTIN_MOVNTPS,
17071 IX86_BUILTIN_MOVNTQ,
17073 IX86_BUILTIN_LOADDQU,
17074 IX86_BUILTIN_STOREDQU,
17076 IX86_BUILTIN_PACKSSWB,
17077 IX86_BUILTIN_PACKSSDW,
17078 IX86_BUILTIN_PACKUSWB,
17080 IX86_BUILTIN_PADDB,
17081 IX86_BUILTIN_PADDW,
17082 IX86_BUILTIN_PADDD,
17083 IX86_BUILTIN_PADDQ,
17084 IX86_BUILTIN_PADDSB,
17085 IX86_BUILTIN_PADDSW,
17086 IX86_BUILTIN_PADDUSB,
17087 IX86_BUILTIN_PADDUSW,
17088 IX86_BUILTIN_PSUBB,
17089 IX86_BUILTIN_PSUBW,
17090 IX86_BUILTIN_PSUBD,
17091 IX86_BUILTIN_PSUBQ,
17092 IX86_BUILTIN_PSUBSB,
17093 IX86_BUILTIN_PSUBSW,
17094 IX86_BUILTIN_PSUBUSB,
17095 IX86_BUILTIN_PSUBUSW,
17098 IX86_BUILTIN_PANDN,
17102 IX86_BUILTIN_PAVGB,
17103 IX86_BUILTIN_PAVGW,
17105 IX86_BUILTIN_PCMPEQB,
17106 IX86_BUILTIN_PCMPEQW,
17107 IX86_BUILTIN_PCMPEQD,
17108 IX86_BUILTIN_PCMPGTB,
17109 IX86_BUILTIN_PCMPGTW,
17110 IX86_BUILTIN_PCMPGTD,
17112 IX86_BUILTIN_PMADDWD,
17114 IX86_BUILTIN_PMAXSW,
17115 IX86_BUILTIN_PMAXUB,
17116 IX86_BUILTIN_PMINSW,
17117 IX86_BUILTIN_PMINUB,
17119 IX86_BUILTIN_PMULHUW,
17120 IX86_BUILTIN_PMULHW,
17121 IX86_BUILTIN_PMULLW,
17123 IX86_BUILTIN_PSADBW,
17124 IX86_BUILTIN_PSHUFW,
17126 IX86_BUILTIN_PSLLW,
17127 IX86_BUILTIN_PSLLD,
17128 IX86_BUILTIN_PSLLQ,
17129 IX86_BUILTIN_PSRAW,
17130 IX86_BUILTIN_PSRAD,
17131 IX86_BUILTIN_PSRLW,
17132 IX86_BUILTIN_PSRLD,
17133 IX86_BUILTIN_PSRLQ,
17134 IX86_BUILTIN_PSLLWI,
17135 IX86_BUILTIN_PSLLDI,
17136 IX86_BUILTIN_PSLLQI,
17137 IX86_BUILTIN_PSRAWI,
17138 IX86_BUILTIN_PSRADI,
17139 IX86_BUILTIN_PSRLWI,
17140 IX86_BUILTIN_PSRLDI,
17141 IX86_BUILTIN_PSRLQI,
17143 IX86_BUILTIN_PUNPCKHBW,
17144 IX86_BUILTIN_PUNPCKHWD,
17145 IX86_BUILTIN_PUNPCKHDQ,
17146 IX86_BUILTIN_PUNPCKLBW,
17147 IX86_BUILTIN_PUNPCKLWD,
17148 IX86_BUILTIN_PUNPCKLDQ,
17150 IX86_BUILTIN_SHUFPS,
17152 IX86_BUILTIN_RCPPS,
17153 IX86_BUILTIN_RCPSS,
17154 IX86_BUILTIN_RSQRTPS,
17155 IX86_BUILTIN_RSQRTPS_NR,
17156 IX86_BUILTIN_RSQRTSS,
17157 IX86_BUILTIN_RSQRTF,
17158 IX86_BUILTIN_SQRTPS,
17159 IX86_BUILTIN_SQRTPS_NR,
17160 IX86_BUILTIN_SQRTSS,
17162 IX86_BUILTIN_UNPCKHPS,
17163 IX86_BUILTIN_UNPCKLPS,
17165 IX86_BUILTIN_ANDPS,
17166 IX86_BUILTIN_ANDNPS,
17168 IX86_BUILTIN_XORPS,
17171 IX86_BUILTIN_LDMXCSR,
17172 IX86_BUILTIN_STMXCSR,
17173 IX86_BUILTIN_SFENCE,
17175 /* 3DNow! Original */
17176 IX86_BUILTIN_FEMMS,
17177 IX86_BUILTIN_PAVGUSB,
17178 IX86_BUILTIN_PF2ID,
17179 IX86_BUILTIN_PFACC,
17180 IX86_BUILTIN_PFADD,
17181 IX86_BUILTIN_PFCMPEQ,
17182 IX86_BUILTIN_PFCMPGE,
17183 IX86_BUILTIN_PFCMPGT,
17184 IX86_BUILTIN_PFMAX,
17185 IX86_BUILTIN_PFMIN,
17186 IX86_BUILTIN_PFMUL,
17187 IX86_BUILTIN_PFRCP,
17188 IX86_BUILTIN_PFRCPIT1,
17189 IX86_BUILTIN_PFRCPIT2,
17190 IX86_BUILTIN_PFRSQIT1,
17191 IX86_BUILTIN_PFRSQRT,
17192 IX86_BUILTIN_PFSUB,
17193 IX86_BUILTIN_PFSUBR,
17194 IX86_BUILTIN_PI2FD,
17195 IX86_BUILTIN_PMULHRW,
17197 /* 3DNow! Athlon Extensions */
17198 IX86_BUILTIN_PF2IW,
17199 IX86_BUILTIN_PFNACC,
17200 IX86_BUILTIN_PFPNACC,
17201 IX86_BUILTIN_PI2FW,
17202 IX86_BUILTIN_PSWAPDSI,
17203 IX86_BUILTIN_PSWAPDSF,
17206 IX86_BUILTIN_ADDPD,
17207 IX86_BUILTIN_ADDSD,
17208 IX86_BUILTIN_DIVPD,
17209 IX86_BUILTIN_DIVSD,
17210 IX86_BUILTIN_MULPD,
17211 IX86_BUILTIN_MULSD,
17212 IX86_BUILTIN_SUBPD,
17213 IX86_BUILTIN_SUBSD,
17215 IX86_BUILTIN_CMPEQPD,
17216 IX86_BUILTIN_CMPLTPD,
17217 IX86_BUILTIN_CMPLEPD,
17218 IX86_BUILTIN_CMPGTPD,
17219 IX86_BUILTIN_CMPGEPD,
17220 IX86_BUILTIN_CMPNEQPD,
17221 IX86_BUILTIN_CMPNLTPD,
17222 IX86_BUILTIN_CMPNLEPD,
17223 IX86_BUILTIN_CMPNGTPD,
17224 IX86_BUILTIN_CMPNGEPD,
17225 IX86_BUILTIN_CMPORDPD,
17226 IX86_BUILTIN_CMPUNORDPD,
17227 IX86_BUILTIN_CMPEQSD,
17228 IX86_BUILTIN_CMPLTSD,
17229 IX86_BUILTIN_CMPLESD,
17230 IX86_BUILTIN_CMPNEQSD,
17231 IX86_BUILTIN_CMPNLTSD,
17232 IX86_BUILTIN_CMPNLESD,
17233 IX86_BUILTIN_CMPORDSD,
17234 IX86_BUILTIN_CMPUNORDSD,
17236 IX86_BUILTIN_COMIEQSD,
17237 IX86_BUILTIN_COMILTSD,
17238 IX86_BUILTIN_COMILESD,
17239 IX86_BUILTIN_COMIGTSD,
17240 IX86_BUILTIN_COMIGESD,
17241 IX86_BUILTIN_COMINEQSD,
17242 IX86_BUILTIN_UCOMIEQSD,
17243 IX86_BUILTIN_UCOMILTSD,
17244 IX86_BUILTIN_UCOMILESD,
17245 IX86_BUILTIN_UCOMIGTSD,
17246 IX86_BUILTIN_UCOMIGESD,
17247 IX86_BUILTIN_UCOMINEQSD,
17249 IX86_BUILTIN_MAXPD,
17250 IX86_BUILTIN_MAXSD,
17251 IX86_BUILTIN_MINPD,
17252 IX86_BUILTIN_MINSD,
17254 IX86_BUILTIN_ANDPD,
17255 IX86_BUILTIN_ANDNPD,
17257 IX86_BUILTIN_XORPD,
17259 IX86_BUILTIN_SQRTPD,
17260 IX86_BUILTIN_SQRTSD,
17262 IX86_BUILTIN_UNPCKHPD,
17263 IX86_BUILTIN_UNPCKLPD,
17265 IX86_BUILTIN_SHUFPD,
17267 IX86_BUILTIN_LOADUPD,
17268 IX86_BUILTIN_STOREUPD,
17269 IX86_BUILTIN_MOVSD,
17271 IX86_BUILTIN_LOADHPD,
17272 IX86_BUILTIN_LOADLPD,
17274 IX86_BUILTIN_CVTDQ2PD,
17275 IX86_BUILTIN_CVTDQ2PS,
17277 IX86_BUILTIN_CVTPD2DQ,
17278 IX86_BUILTIN_CVTPD2PI,
17279 IX86_BUILTIN_CVTPD2PS,
17280 IX86_BUILTIN_CVTTPD2DQ,
17281 IX86_BUILTIN_CVTTPD2PI,
17283 IX86_BUILTIN_CVTPI2PD,
17284 IX86_BUILTIN_CVTSI2SD,
17285 IX86_BUILTIN_CVTSI642SD,
17287 IX86_BUILTIN_CVTSD2SI,
17288 IX86_BUILTIN_CVTSD2SI64,
17289 IX86_BUILTIN_CVTSD2SS,
17290 IX86_BUILTIN_CVTSS2SD,
17291 IX86_BUILTIN_CVTTSD2SI,
17292 IX86_BUILTIN_CVTTSD2SI64,
17294 IX86_BUILTIN_CVTPS2DQ,
17295 IX86_BUILTIN_CVTPS2PD,
17296 IX86_BUILTIN_CVTTPS2DQ,
17298 IX86_BUILTIN_MOVNTI,
17299 IX86_BUILTIN_MOVNTPD,
17300 IX86_BUILTIN_MOVNTDQ,
17303 IX86_BUILTIN_MASKMOVDQU,
17304 IX86_BUILTIN_MOVMSKPD,
17305 IX86_BUILTIN_PMOVMSKB128,
17307 IX86_BUILTIN_PACKSSWB128,
17308 IX86_BUILTIN_PACKSSDW128,
17309 IX86_BUILTIN_PACKUSWB128,
17311 IX86_BUILTIN_PADDB128,
17312 IX86_BUILTIN_PADDW128,
17313 IX86_BUILTIN_PADDD128,
17314 IX86_BUILTIN_PADDQ128,
17315 IX86_BUILTIN_PADDSB128,
17316 IX86_BUILTIN_PADDSW128,
17317 IX86_BUILTIN_PADDUSB128,
17318 IX86_BUILTIN_PADDUSW128,
17319 IX86_BUILTIN_PSUBB128,
17320 IX86_BUILTIN_PSUBW128,
17321 IX86_BUILTIN_PSUBD128,
17322 IX86_BUILTIN_PSUBQ128,
17323 IX86_BUILTIN_PSUBSB128,
17324 IX86_BUILTIN_PSUBSW128,
17325 IX86_BUILTIN_PSUBUSB128,
17326 IX86_BUILTIN_PSUBUSW128,
17328 IX86_BUILTIN_PAND128,
17329 IX86_BUILTIN_PANDN128,
17330 IX86_BUILTIN_POR128,
17331 IX86_BUILTIN_PXOR128,
17333 IX86_BUILTIN_PAVGB128,
17334 IX86_BUILTIN_PAVGW128,
17336 IX86_BUILTIN_PCMPEQB128,
17337 IX86_BUILTIN_PCMPEQW128,
17338 IX86_BUILTIN_PCMPEQD128,
17339 IX86_BUILTIN_PCMPGTB128,
17340 IX86_BUILTIN_PCMPGTW128,
17341 IX86_BUILTIN_PCMPGTD128,
17343 IX86_BUILTIN_PMADDWD128,
17345 IX86_BUILTIN_PMAXSW128,
17346 IX86_BUILTIN_PMAXUB128,
17347 IX86_BUILTIN_PMINSW128,
17348 IX86_BUILTIN_PMINUB128,
17350 IX86_BUILTIN_PMULUDQ,
17351 IX86_BUILTIN_PMULUDQ128,
17352 IX86_BUILTIN_PMULHUW128,
17353 IX86_BUILTIN_PMULHW128,
17354 IX86_BUILTIN_PMULLW128,
17356 IX86_BUILTIN_PSADBW128,
17357 IX86_BUILTIN_PSHUFHW,
17358 IX86_BUILTIN_PSHUFLW,
17359 IX86_BUILTIN_PSHUFD,
17361 IX86_BUILTIN_PSLLDQI128,
17362 IX86_BUILTIN_PSLLWI128,
17363 IX86_BUILTIN_PSLLDI128,
17364 IX86_BUILTIN_PSLLQI128,
17365 IX86_BUILTIN_PSRAWI128,
17366 IX86_BUILTIN_PSRADI128,
17367 IX86_BUILTIN_PSRLDQI128,
17368 IX86_BUILTIN_PSRLWI128,
17369 IX86_BUILTIN_PSRLDI128,
17370 IX86_BUILTIN_PSRLQI128,
17372 IX86_BUILTIN_PSLLDQ128,
17373 IX86_BUILTIN_PSLLW128,
17374 IX86_BUILTIN_PSLLD128,
17375 IX86_BUILTIN_PSLLQ128,
17376 IX86_BUILTIN_PSRAW128,
17377 IX86_BUILTIN_PSRAD128,
17378 IX86_BUILTIN_PSRLW128,
17379 IX86_BUILTIN_PSRLD128,
17380 IX86_BUILTIN_PSRLQ128,
17382 IX86_BUILTIN_PUNPCKHBW128,
17383 IX86_BUILTIN_PUNPCKHWD128,
17384 IX86_BUILTIN_PUNPCKHDQ128,
17385 IX86_BUILTIN_PUNPCKHQDQ128,
17386 IX86_BUILTIN_PUNPCKLBW128,
17387 IX86_BUILTIN_PUNPCKLWD128,
17388 IX86_BUILTIN_PUNPCKLDQ128,
17389 IX86_BUILTIN_PUNPCKLQDQ128,
17391 IX86_BUILTIN_CLFLUSH,
17392 IX86_BUILTIN_MFENCE,
17393 IX86_BUILTIN_LFENCE,
17395 /* Prescott New Instructions. */
17396 IX86_BUILTIN_ADDSUBPS,
17397 IX86_BUILTIN_HADDPS,
17398 IX86_BUILTIN_HSUBPS,
17399 IX86_BUILTIN_MOVSHDUP,
17400 IX86_BUILTIN_MOVSLDUP,
17401 IX86_BUILTIN_ADDSUBPD,
17402 IX86_BUILTIN_HADDPD,
17403 IX86_BUILTIN_HSUBPD,
17404 IX86_BUILTIN_LDDQU,
17406 IX86_BUILTIN_MONITOR,
17407 IX86_BUILTIN_MWAIT,
17410 IX86_BUILTIN_PHADDW,
17411 IX86_BUILTIN_PHADDD,
17412 IX86_BUILTIN_PHADDSW,
17413 IX86_BUILTIN_PHSUBW,
17414 IX86_BUILTIN_PHSUBD,
17415 IX86_BUILTIN_PHSUBSW,
17416 IX86_BUILTIN_PMADDUBSW,
17417 IX86_BUILTIN_PMULHRSW,
17418 IX86_BUILTIN_PSHUFB,
17419 IX86_BUILTIN_PSIGNB,
17420 IX86_BUILTIN_PSIGNW,
17421 IX86_BUILTIN_PSIGND,
17422 IX86_BUILTIN_PALIGNR,
17423 IX86_BUILTIN_PABSB,
17424 IX86_BUILTIN_PABSW,
17425 IX86_BUILTIN_PABSD,
17427 IX86_BUILTIN_PHADDW128,
17428 IX86_BUILTIN_PHADDD128,
17429 IX86_BUILTIN_PHADDSW128,
17430 IX86_BUILTIN_PHSUBW128,
17431 IX86_BUILTIN_PHSUBD128,
17432 IX86_BUILTIN_PHSUBSW128,
17433 IX86_BUILTIN_PMADDUBSW128,
17434 IX86_BUILTIN_PMULHRSW128,
17435 IX86_BUILTIN_PSHUFB128,
17436 IX86_BUILTIN_PSIGNB128,
17437 IX86_BUILTIN_PSIGNW128,
17438 IX86_BUILTIN_PSIGND128,
17439 IX86_BUILTIN_PALIGNR128,
17440 IX86_BUILTIN_PABSB128,
17441 IX86_BUILTIN_PABSW128,
17442 IX86_BUILTIN_PABSD128,
17444 /* AMDFAM10 - SSE4A New Instructions. */
17445 IX86_BUILTIN_MOVNTSD,
17446 IX86_BUILTIN_MOVNTSS,
17447 IX86_BUILTIN_EXTRQI,
17448 IX86_BUILTIN_EXTRQ,
17449 IX86_BUILTIN_INSERTQI,
17450 IX86_BUILTIN_INSERTQ,
17453 IX86_BUILTIN_BLENDPD,
17454 IX86_BUILTIN_BLENDPS,
17455 IX86_BUILTIN_BLENDVPD,
17456 IX86_BUILTIN_BLENDVPS,
17457 IX86_BUILTIN_PBLENDVB128,
17458 IX86_BUILTIN_PBLENDW128,
17463 IX86_BUILTIN_INSERTPS128,
17465 IX86_BUILTIN_MOVNTDQA,
17466 IX86_BUILTIN_MPSADBW128,
17467 IX86_BUILTIN_PACKUSDW128,
17468 IX86_BUILTIN_PCMPEQQ,
17469 IX86_BUILTIN_PHMINPOSUW128,
17471 IX86_BUILTIN_PMAXSB128,
17472 IX86_BUILTIN_PMAXSD128,
17473 IX86_BUILTIN_PMAXUD128,
17474 IX86_BUILTIN_PMAXUW128,
17476 IX86_BUILTIN_PMINSB128,
17477 IX86_BUILTIN_PMINSD128,
17478 IX86_BUILTIN_PMINUD128,
17479 IX86_BUILTIN_PMINUW128,
17481 IX86_BUILTIN_PMOVSXBW128,
17482 IX86_BUILTIN_PMOVSXBD128,
17483 IX86_BUILTIN_PMOVSXBQ128,
17484 IX86_BUILTIN_PMOVSXWD128,
17485 IX86_BUILTIN_PMOVSXWQ128,
17486 IX86_BUILTIN_PMOVSXDQ128,
17488 IX86_BUILTIN_PMOVZXBW128,
17489 IX86_BUILTIN_PMOVZXBD128,
17490 IX86_BUILTIN_PMOVZXBQ128,
17491 IX86_BUILTIN_PMOVZXWD128,
17492 IX86_BUILTIN_PMOVZXWQ128,
17493 IX86_BUILTIN_PMOVZXDQ128,
17495 IX86_BUILTIN_PMULDQ128,
17496 IX86_BUILTIN_PMULLD128,
17498 IX86_BUILTIN_ROUNDPD,
17499 IX86_BUILTIN_ROUNDPS,
17500 IX86_BUILTIN_ROUNDSD,
17501 IX86_BUILTIN_ROUNDSS,
17503 IX86_BUILTIN_PTESTZ,
17504 IX86_BUILTIN_PTESTC,
17505 IX86_BUILTIN_PTESTNZC,
17507 IX86_BUILTIN_VEC_INIT_V2SI,
17508 IX86_BUILTIN_VEC_INIT_V4HI,
17509 IX86_BUILTIN_VEC_INIT_V8QI,
17510 IX86_BUILTIN_VEC_EXT_V2DF,
17511 IX86_BUILTIN_VEC_EXT_V2DI,
17512 IX86_BUILTIN_VEC_EXT_V4SF,
17513 IX86_BUILTIN_VEC_EXT_V4SI,
17514 IX86_BUILTIN_VEC_EXT_V8HI,
17515 IX86_BUILTIN_VEC_EXT_V2SI,
17516 IX86_BUILTIN_VEC_EXT_V4HI,
17517 IX86_BUILTIN_VEC_EXT_V16QI,
17518 IX86_BUILTIN_VEC_SET_V2DI,
17519 IX86_BUILTIN_VEC_SET_V4SF,
17520 IX86_BUILTIN_VEC_SET_V4SI,
17521 IX86_BUILTIN_VEC_SET_V8HI,
17522 IX86_BUILTIN_VEC_SET_V4HI,
17523 IX86_BUILTIN_VEC_SET_V16QI,
17525 IX86_BUILTIN_VEC_PACK_SFIX,
17528 IX86_BUILTIN_CRC32QI,
17529 IX86_BUILTIN_CRC32HI,
17530 IX86_BUILTIN_CRC32SI,
17531 IX86_BUILTIN_CRC32DI,
17533 IX86_BUILTIN_PCMPESTRI128,
17534 IX86_BUILTIN_PCMPESTRM128,
17535 IX86_BUILTIN_PCMPESTRA128,
17536 IX86_BUILTIN_PCMPESTRC128,
17537 IX86_BUILTIN_PCMPESTRO128,
17538 IX86_BUILTIN_PCMPESTRS128,
17539 IX86_BUILTIN_PCMPESTRZ128,
17540 IX86_BUILTIN_PCMPISTRI128,
17541 IX86_BUILTIN_PCMPISTRM128,
17542 IX86_BUILTIN_PCMPISTRA128,
17543 IX86_BUILTIN_PCMPISTRC128,
17544 IX86_BUILTIN_PCMPISTRO128,
17545 IX86_BUILTIN_PCMPISTRS128,
17546 IX86_BUILTIN_PCMPISTRZ128,
17548 IX86_BUILTIN_PCMPGTQ,
17550 /* TFmode support builtins. */
17552 IX86_BUILTIN_FABSQ,
17553 IX86_BUILTIN_COPYSIGNQ,
17555 /* SSE5 instructions */
17556 IX86_BUILTIN_FMADDSS,
17557 IX86_BUILTIN_FMADDSD,
17558 IX86_BUILTIN_FMADDPS,
17559 IX86_BUILTIN_FMADDPD,
17560 IX86_BUILTIN_FMSUBSS,
17561 IX86_BUILTIN_FMSUBSD,
17562 IX86_BUILTIN_FMSUBPS,
17563 IX86_BUILTIN_FMSUBPD,
17564 IX86_BUILTIN_FNMADDSS,
17565 IX86_BUILTIN_FNMADDSD,
17566 IX86_BUILTIN_FNMADDPS,
17567 IX86_BUILTIN_FNMADDPD,
17568 IX86_BUILTIN_FNMSUBSS,
17569 IX86_BUILTIN_FNMSUBSD,
17570 IX86_BUILTIN_FNMSUBPS,
17571 IX86_BUILTIN_FNMSUBPD,
17572 IX86_BUILTIN_PCMOV_V2DI,
17573 IX86_BUILTIN_PCMOV_V4SI,
17574 IX86_BUILTIN_PCMOV_V8HI,
17575 IX86_BUILTIN_PCMOV_V16QI,
17576 IX86_BUILTIN_PCMOV_V4SF,
17577 IX86_BUILTIN_PCMOV_V2DF,
17578 IX86_BUILTIN_PPERM,
17579 IX86_BUILTIN_PERMPS,
17580 IX86_BUILTIN_PERMPD,
17581 IX86_BUILTIN_PMACSSWW,
17582 IX86_BUILTIN_PMACSWW,
17583 IX86_BUILTIN_PMACSSWD,
17584 IX86_BUILTIN_PMACSWD,
17585 IX86_BUILTIN_PMACSSDD,
17586 IX86_BUILTIN_PMACSDD,
17587 IX86_BUILTIN_PMACSSDQL,
17588 IX86_BUILTIN_PMACSSDQH,
17589 IX86_BUILTIN_PMACSDQL,
17590 IX86_BUILTIN_PMACSDQH,
17591 IX86_BUILTIN_PMADCSSWD,
17592 IX86_BUILTIN_PMADCSWD,
17593 IX86_BUILTIN_PHADDBW,
17594 IX86_BUILTIN_PHADDBD,
17595 IX86_BUILTIN_PHADDBQ,
17596 IX86_BUILTIN_PHADDWD,
17597 IX86_BUILTIN_PHADDWQ,
17598 IX86_BUILTIN_PHADDDQ,
17599 IX86_BUILTIN_PHADDUBW,
17600 IX86_BUILTIN_PHADDUBD,
17601 IX86_BUILTIN_PHADDUBQ,
17602 IX86_BUILTIN_PHADDUWD,
17603 IX86_BUILTIN_PHADDUWQ,
17604 IX86_BUILTIN_PHADDUDQ,
17605 IX86_BUILTIN_PHSUBBW,
17606 IX86_BUILTIN_PHSUBWD,
17607 IX86_BUILTIN_PHSUBDQ,
17608 IX86_BUILTIN_PROTB,
17609 IX86_BUILTIN_PROTW,
17610 IX86_BUILTIN_PROTD,
17611 IX86_BUILTIN_PROTQ,
17612 IX86_BUILTIN_PROTB_IMM,
17613 IX86_BUILTIN_PROTW_IMM,
17614 IX86_BUILTIN_PROTD_IMM,
17615 IX86_BUILTIN_PROTQ_IMM,
17616 IX86_BUILTIN_PSHLB,
17617 IX86_BUILTIN_PSHLW,
17618 IX86_BUILTIN_PSHLD,
17619 IX86_BUILTIN_PSHLQ,
17620 IX86_BUILTIN_PSHAB,
17621 IX86_BUILTIN_PSHAW,
17622 IX86_BUILTIN_PSHAD,
17623 IX86_BUILTIN_PSHAQ,
17624 IX86_BUILTIN_FRCZSS,
17625 IX86_BUILTIN_FRCZSD,
17626 IX86_BUILTIN_FRCZPS,
17627 IX86_BUILTIN_FRCZPD,
17628 IX86_BUILTIN_CVTPH2PS,
17629 IX86_BUILTIN_CVTPS2PH,
17631 IX86_BUILTIN_COMEQSS,
17632 IX86_BUILTIN_COMNESS,
17633 IX86_BUILTIN_COMLTSS,
17634 IX86_BUILTIN_COMLESS,
17635 IX86_BUILTIN_COMGTSS,
17636 IX86_BUILTIN_COMGESS,
17637 IX86_BUILTIN_COMUEQSS,
17638 IX86_BUILTIN_COMUNESS,
17639 IX86_BUILTIN_COMULTSS,
17640 IX86_BUILTIN_COMULESS,
17641 IX86_BUILTIN_COMUGTSS,
17642 IX86_BUILTIN_COMUGESS,
17643 IX86_BUILTIN_COMORDSS,
17644 IX86_BUILTIN_COMUNORDSS,
17645 IX86_BUILTIN_COMFALSESS,
17646 IX86_BUILTIN_COMTRUESS,
17648 IX86_BUILTIN_COMEQSD,
17649 IX86_BUILTIN_COMNESD,
17650 IX86_BUILTIN_COMLTSD,
17651 IX86_BUILTIN_COMLESD,
17652 IX86_BUILTIN_COMGTSD,
17653 IX86_BUILTIN_COMGESD,
17654 IX86_BUILTIN_COMUEQSD,
17655 IX86_BUILTIN_COMUNESD,
17656 IX86_BUILTIN_COMULTSD,
17657 IX86_BUILTIN_COMULESD,
17658 IX86_BUILTIN_COMUGTSD,
17659 IX86_BUILTIN_COMUGESD,
17660 IX86_BUILTIN_COMORDSD,
17661 IX86_BUILTIN_COMUNORDSD,
17662 IX86_BUILTIN_COMFALSESD,
17663 IX86_BUILTIN_COMTRUESD,
17665 IX86_BUILTIN_COMEQPS,
17666 IX86_BUILTIN_COMNEPS,
17667 IX86_BUILTIN_COMLTPS,
17668 IX86_BUILTIN_COMLEPS,
17669 IX86_BUILTIN_COMGTPS,
17670 IX86_BUILTIN_COMGEPS,
17671 IX86_BUILTIN_COMUEQPS,
17672 IX86_BUILTIN_COMUNEPS,
17673 IX86_BUILTIN_COMULTPS,
17674 IX86_BUILTIN_COMULEPS,
17675 IX86_BUILTIN_COMUGTPS,
17676 IX86_BUILTIN_COMUGEPS,
17677 IX86_BUILTIN_COMORDPS,
17678 IX86_BUILTIN_COMUNORDPS,
17679 IX86_BUILTIN_COMFALSEPS,
17680 IX86_BUILTIN_COMTRUEPS,
17682 IX86_BUILTIN_COMEQPD,
17683 IX86_BUILTIN_COMNEPD,
17684 IX86_BUILTIN_COMLTPD,
17685 IX86_BUILTIN_COMLEPD,
17686 IX86_BUILTIN_COMGTPD,
17687 IX86_BUILTIN_COMGEPD,
17688 IX86_BUILTIN_COMUEQPD,
17689 IX86_BUILTIN_COMUNEPD,
17690 IX86_BUILTIN_COMULTPD,
17691 IX86_BUILTIN_COMULEPD,
17692 IX86_BUILTIN_COMUGTPD,
17693 IX86_BUILTIN_COMUGEPD,
17694 IX86_BUILTIN_COMORDPD,
17695 IX86_BUILTIN_COMUNORDPD,
17696 IX86_BUILTIN_COMFALSEPD,
17697 IX86_BUILTIN_COMTRUEPD,
17699 IX86_BUILTIN_PCOMEQUB,
17700 IX86_BUILTIN_PCOMNEUB,
17701 IX86_BUILTIN_PCOMLTUB,
17702 IX86_BUILTIN_PCOMLEUB,
17703 IX86_BUILTIN_PCOMGTUB,
17704 IX86_BUILTIN_PCOMGEUB,
17705 IX86_BUILTIN_PCOMFALSEUB,
17706 IX86_BUILTIN_PCOMTRUEUB,
17707 IX86_BUILTIN_PCOMEQUW,
17708 IX86_BUILTIN_PCOMNEUW,
17709 IX86_BUILTIN_PCOMLTUW,
17710 IX86_BUILTIN_PCOMLEUW,
17711 IX86_BUILTIN_PCOMGTUW,
17712 IX86_BUILTIN_PCOMGEUW,
17713 IX86_BUILTIN_PCOMFALSEUW,
17714 IX86_BUILTIN_PCOMTRUEUW,
17715 IX86_BUILTIN_PCOMEQUD,
17716 IX86_BUILTIN_PCOMNEUD,
17717 IX86_BUILTIN_PCOMLTUD,
17718 IX86_BUILTIN_PCOMLEUD,
17719 IX86_BUILTIN_PCOMGTUD,
17720 IX86_BUILTIN_PCOMGEUD,
17721 IX86_BUILTIN_PCOMFALSEUD,
17722 IX86_BUILTIN_PCOMTRUEUD,
17723 IX86_BUILTIN_PCOMEQUQ,
17724 IX86_BUILTIN_PCOMNEUQ,
17725 IX86_BUILTIN_PCOMLTUQ,
17726 IX86_BUILTIN_PCOMLEUQ,
17727 IX86_BUILTIN_PCOMGTUQ,
17728 IX86_BUILTIN_PCOMGEUQ,
17729 IX86_BUILTIN_PCOMFALSEUQ,
17730 IX86_BUILTIN_PCOMTRUEUQ,
17732 IX86_BUILTIN_PCOMEQB,
17733 IX86_BUILTIN_PCOMNEB,
17734 IX86_BUILTIN_PCOMLTB,
17735 IX86_BUILTIN_PCOMLEB,
17736 IX86_BUILTIN_PCOMGTB,
17737 IX86_BUILTIN_PCOMGEB,
17738 IX86_BUILTIN_PCOMFALSEB,
17739 IX86_BUILTIN_PCOMTRUEB,
17740 IX86_BUILTIN_PCOMEQW,
17741 IX86_BUILTIN_PCOMNEW,
17742 IX86_BUILTIN_PCOMLTW,
17743 IX86_BUILTIN_PCOMLEW,
17744 IX86_BUILTIN_PCOMGTW,
17745 IX86_BUILTIN_PCOMGEW,
17746 IX86_BUILTIN_PCOMFALSEW,
17747 IX86_BUILTIN_PCOMTRUEW,
17748 IX86_BUILTIN_PCOMEQD,
17749 IX86_BUILTIN_PCOMNED,
17750 IX86_BUILTIN_PCOMLTD,
17751 IX86_BUILTIN_PCOMLED,
17752 IX86_BUILTIN_PCOMGTD,
17753 IX86_BUILTIN_PCOMGED,
17754 IX86_BUILTIN_PCOMFALSED,
17755 IX86_BUILTIN_PCOMTRUED,
17756 IX86_BUILTIN_PCOMEQQ,
17757 IX86_BUILTIN_PCOMNEQ,
17758 IX86_BUILTIN_PCOMLTQ,
17759 IX86_BUILTIN_PCOMLEQ,
17760 IX86_BUILTIN_PCOMGTQ,
17761 IX86_BUILTIN_PCOMGEQ,
17762 IX86_BUILTIN_PCOMFALSEQ,
17763 IX86_BUILTIN_PCOMTRUEQ,
17768 /* Table for the ix86 builtin decls. */
17769 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17771 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17772 * if the target_flags include one of MASK. Stores the function decl
17773 * in the ix86_builtins array.
17774 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17777 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17779 tree decl = NULL_TREE;
17781 if (mask & ix86_isa_flags
17782 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17784 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17786 ix86_builtins[(int) code] = decl;
17792 /* Like def_builtin, but also marks the function decl "const". */
17795 def_builtin_const (int mask, const char *name, tree type,
17796 enum ix86_builtins code)
17798 tree decl = def_builtin (mask, name, type, code);
17800 TREE_READONLY (decl) = 1;
17804 /* Bits for builtin_description.flag. */
17806 /* Set when we don't support the comparison natively, and should
17807 swap_comparison in order to support it. */
17808 #define BUILTIN_DESC_SWAP_OPERANDS 1
17810 struct builtin_description
17812 const unsigned int mask;
17813 const enum insn_code icode;
17814 const char *const name;
17815 const enum ix86_builtins code;
17816 const enum rtx_code comparison;
17820 static const struct builtin_description bdesc_comi[] =
17822 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17823 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17824 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17825 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17828 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17829 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17848 static const struct builtin_description bdesc_ptest[] =
17851 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
17852 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
17853 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
17856 static const struct builtin_description bdesc_pcmpestr[] =
17859 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
17860 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
17861 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
17862 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
17863 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
17864 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
17865 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
17868 static const struct builtin_description bdesc_pcmpistr[] =
17871 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
17872 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
17873 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
17874 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
17875 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
17876 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
17877 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
17880 static const struct builtin_description bdesc_crc32[] =
17883 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
17884 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
17885 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
17886 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
17889 /* SSE builtins with 3 arguments and the last argument must be an immediate or xmm0. */
17890 static const struct builtin_description bdesc_sse_3arg[] =
17893 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, 0 },
17894 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, 0 },
17895 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, 0 },
17896 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, 0 },
17897 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, 0 },
17898 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, 0 },
17899 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, 0 },
17900 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, 0 },
17901 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, 0 },
17902 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, 0 },
17903 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, UNKNOWN, 0 },
17904 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, UNKNOWN, 0 },
17907 static const struct builtin_description bdesc_2arg[] =
17910 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
17911 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
17912 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
17913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
17914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
17915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
17916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
17917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
17919 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
17920 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
17921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
17922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
17923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
17924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
17925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
17926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
17927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
17928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
17931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
17932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
17933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
17934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
17935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
17936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
17937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
17938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
17942 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
17943 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
17944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
17945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
17947 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
17948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
17949 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
17950 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
17952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
17953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
17954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
17955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
17956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
17959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
17960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
17961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
17962 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
17963 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
17964 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
17965 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
17966 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
17968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
17969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
17970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
17971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
17972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
17973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
17974 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
17975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
17977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
17978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
17979 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
17981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
17982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
17983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
17984 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
17986 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
17987 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
17989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
17990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
17991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
17992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
17993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
17994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
17996 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
17997 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
17998 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
17999 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
18001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
18002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
18003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
18004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
18005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
18006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
18009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
18010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
18011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
18013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
18014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
18015 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
18017 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
18018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
18021 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
18022 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
18023 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
18024 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
18025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
18026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
18027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
18028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
18030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
18031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
18032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
18033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
18034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
18035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
18036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
18037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
18038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
18039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
18042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
18043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
18044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
18045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
18046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
18047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
18048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
18049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
18051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
18052 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
18053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
18054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
18056 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
18057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
18058 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
18059 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
18061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
18062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
18063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
18065 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, 0 },
18068 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
18069 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
18070 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
18071 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
18072 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
18073 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
18074 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
18075 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
18077 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
18078 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
18079 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
18080 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
18081 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
18082 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
18083 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
18084 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
18086 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
18087 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
18089 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
18090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
18091 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
18092 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
18094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
18095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
18097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
18098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
18099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
18100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
18101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
18102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
18104 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
18105 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
18106 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
18107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
18109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
18110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
18111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
18112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
18113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
18114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
18115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
18116 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
18118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
18119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
18120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
18122 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
18123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
18125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
18126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
18128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
18130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
18131 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
18132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
18133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
18136 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
18137 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
18138 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
18139 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
18140 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
18141 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
18144 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
18145 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
18146 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
18147 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
18148 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
18149 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
18150 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
18151 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
18152 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
18153 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
18154 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
18155 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
18156 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
18157 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
18158 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
18159 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
18160 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
18161 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
18162 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
18163 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
18164 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
18165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
18166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
18167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
18170 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
18171 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
18172 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
18173 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
18174 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
18175 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
18176 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
18177 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
18178 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
18179 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
18180 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
18181 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
18184 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
18187 static const struct builtin_description bdesc_1arg[] =
18190 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
18191 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
18193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
18194 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS_NR, UNKNOWN, 0 },
18195 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
18196 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, 0 },
18197 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
18199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
18200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, UNKNOWN, 0 },
18201 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, UNKNOWN, 0 },
18202 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, UNKNOWN, 0 },
18203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, UNKNOWN, 0 },
18204 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, 0 },
18207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, UNKNOWN, 0 },
18208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, UNKNOWN, 0 },
18210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, UNKNOWN, 0 },
18212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, UNKNOWN, 0 },
18213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, UNKNOWN, 0 },
18215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, UNKNOWN, 0 },
18216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, UNKNOWN, 0 },
18217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, UNKNOWN, 0 },
18218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, 0 },
18219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, UNKNOWN, 0 },
18221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, UNKNOWN, 0 },
18223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, UNKNOWN, 0 },
18224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, UNKNOWN, 0 },
18225 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, UNKNOWN, 0 },
18226 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, 0 },
18228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, UNKNOWN, 0 },
18229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, UNKNOWN, 0 },
18230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, 0 },
18233 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, 0 },
18234 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, 0 },
18237 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, 0 },
18238 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, 0 },
18239 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, 0 },
18240 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, 0 },
18241 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, 0 },
18242 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, 0 },
18245 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, UNKNOWN, 0 },
18246 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, UNKNOWN, 0 },
18247 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, 0 },
18248 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, UNKNOWN, 0 },
18249 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, 0 },
18250 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, 0 },
18251 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, UNKNOWN, 0 },
18252 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, UNKNOWN, 0 },
18253 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, 0 },
18254 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, UNKNOWN, 0 },
18255 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, 0 },
18256 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, 0 },
18257 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, 0 },
18259 /* Fake 1 arg builtins with a constant smaller than 8 bits as the 2nd arg. */
18260 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, UNKNOWN, 0 },
18261 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, UNKNOWN, 0 },
18265 enum multi_arg_type {
18275 MULTI_ARG_3_PERMPS,
18276 MULTI_ARG_3_PERMPD,
18283 MULTI_ARG_2_DI_IMM,
18284 MULTI_ARG_2_SI_IMM,
18285 MULTI_ARG_2_HI_IMM,
18286 MULTI_ARG_2_QI_IMM,
18287 MULTI_ARG_2_SF_CMP,
18288 MULTI_ARG_2_DF_CMP,
18289 MULTI_ARG_2_DI_CMP,
18290 MULTI_ARG_2_SI_CMP,
18291 MULTI_ARG_2_HI_CMP,
18292 MULTI_ARG_2_QI_CMP,
18315 static const struct builtin_description bdesc_multi_arg[] =
18317 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18318 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18319 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18320 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18321 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18322 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18323 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18324 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18325 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18326 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18327 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18328 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18329 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18330 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18331 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18332 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18333 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18334 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18335 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18336 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18337 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18338 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18339 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18340 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18341 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18342 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18343 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18344 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18345 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18346 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18347 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18348 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18349 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18350 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18351 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18352 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18353 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18354 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18355 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18356 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18357 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18358 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18359 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18360 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18361 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18362 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18363 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18364 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18365 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18366 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18367 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18368 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18369 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18370 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18371 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18372 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18373 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18374 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18375 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18376 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18377 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18378 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18379 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18380 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18381 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18382 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18383 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18384 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18385 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18386 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18387 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18388 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18389 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18390 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18391 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18393 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18394 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18395 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18396 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18397 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18398 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18399 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18400 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18401 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18402 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18403 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18404 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18405 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18406 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18407 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18408 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18410 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18411 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18412 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18413 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18414 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18415 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18416 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18417 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18418 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18419 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18420 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18421 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18422 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18423 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18424 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18425 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18428 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18429 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18430 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18431 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18432 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18433 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18434 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18435 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18436 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18437 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18438 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18439 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18440 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18441 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18442 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18444 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18445 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18446 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18447 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18448 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18449 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18450 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18451 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18452 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18453 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18454 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18455 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18456 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18457 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18458 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18459 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18461 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18462 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18463 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18464 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18465 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18466 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18467 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18469 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18470 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18471 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18472 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18473 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18474 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18475 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18477 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18478 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18479 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18480 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18481 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18482 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18483 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18488 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18491 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18496 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18499 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18553 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18554 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18557 ix86_init_mmx_sse_builtins (void)
18559 const struct builtin_description * d;
18562 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18563 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18564 tree V1DI_type_node
18565 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
18566 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18567 tree V2DI_type_node
18568 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18569 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18570 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18571 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18572 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
18573 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
18574 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
18576 tree pchar_type_node = build_pointer_type (char_type_node);
18577 tree pcchar_type_node = build_pointer_type (
18578 build_type_variant (char_type_node, 1, 0));
18579 tree pfloat_type_node = build_pointer_type (float_type_node);
18580 tree pcfloat_type_node = build_pointer_type (
18581 build_type_variant (float_type_node, 1, 0));
18582 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
18583 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
18584 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
18587 tree int_ftype_v4sf_v4sf
18588 = build_function_type_list (integer_type_node,
18589 V4SF_type_node, V4SF_type_node, NULL_TREE);
18590 tree v4si_ftype_v4sf_v4sf
18591 = build_function_type_list (V4SI_type_node,
18592 V4SF_type_node, V4SF_type_node, NULL_TREE);
18593 /* MMX/SSE/integer conversions. */
18594 tree int_ftype_v4sf
18595 = build_function_type_list (integer_type_node,
18596 V4SF_type_node, NULL_TREE);
18597 tree int64_ftype_v4sf
18598 = build_function_type_list (long_long_integer_type_node,
18599 V4SF_type_node, NULL_TREE);
18600 tree int_ftype_v8qi
18601 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
18602 tree v4sf_ftype_v4sf_int
18603 = build_function_type_list (V4SF_type_node,
18604 V4SF_type_node, integer_type_node, NULL_TREE);
18605 tree v4sf_ftype_v4sf_int64
18606 = build_function_type_list (V4SF_type_node,
18607 V4SF_type_node, long_long_integer_type_node,
18609 tree v4sf_ftype_v4sf_v2si
18610 = build_function_type_list (V4SF_type_node,
18611 V4SF_type_node, V2SI_type_node, NULL_TREE);
18613 /* Miscellaneous. */
18614 tree v8qi_ftype_v4hi_v4hi
18615 = build_function_type_list (V8QI_type_node,
18616 V4HI_type_node, V4HI_type_node, NULL_TREE);
18617 tree v4hi_ftype_v2si_v2si
18618 = build_function_type_list (V4HI_type_node,
18619 V2SI_type_node, V2SI_type_node, NULL_TREE);
18620 tree v4sf_ftype_v4sf_v4sf_int
18621 = build_function_type_list (V4SF_type_node,
18622 V4SF_type_node, V4SF_type_node,
18623 integer_type_node, NULL_TREE);
18624 tree v2si_ftype_v4hi_v4hi
18625 = build_function_type_list (V2SI_type_node,
18626 V4HI_type_node, V4HI_type_node, NULL_TREE);
18627 tree v4hi_ftype_v4hi_int
18628 = build_function_type_list (V4HI_type_node,
18629 V4HI_type_node, integer_type_node, NULL_TREE);
18630 tree v2si_ftype_v2si_int
18631 = build_function_type_list (V2SI_type_node,
18632 V2SI_type_node, integer_type_node, NULL_TREE);
18633 tree v1di_ftype_v1di_int
18634 = build_function_type_list (V1DI_type_node,
18635 V1DI_type_node, integer_type_node, NULL_TREE);
18637 tree void_ftype_void
18638 = build_function_type (void_type_node, void_list_node);
18639 tree void_ftype_unsigned
18640 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
18641 tree void_ftype_unsigned_unsigned
18642 = build_function_type_list (void_type_node, unsigned_type_node,
18643 unsigned_type_node, NULL_TREE);
18644 tree void_ftype_pcvoid_unsigned_unsigned
18645 = build_function_type_list (void_type_node, const_ptr_type_node,
18646 unsigned_type_node, unsigned_type_node,
18648 tree unsigned_ftype_void
18649 = build_function_type (unsigned_type_node, void_list_node);
18650 tree v2si_ftype_v4sf
18651 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
18652 /* Loads/stores. */
18653 tree void_ftype_v8qi_v8qi_pchar
18654 = build_function_type_list (void_type_node,
18655 V8QI_type_node, V8QI_type_node,
18656 pchar_type_node, NULL_TREE);
18657 tree v4sf_ftype_pcfloat
18658 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
18659 /* @@@ the type is bogus */
18660 tree v4sf_ftype_v4sf_pv2si
18661 = build_function_type_list (V4SF_type_node,
18662 V4SF_type_node, pv2si_type_node, NULL_TREE);
18663 tree void_ftype_pv2si_v4sf
18664 = build_function_type_list (void_type_node,
18665 pv2si_type_node, V4SF_type_node, NULL_TREE);
18666 tree void_ftype_pfloat_v4sf
18667 = build_function_type_list (void_type_node,
18668 pfloat_type_node, V4SF_type_node, NULL_TREE);
18669 tree void_ftype_pdi_di
18670 = build_function_type_list (void_type_node,
18671 pdi_type_node, long_long_unsigned_type_node,
18673 tree void_ftype_pv2di_v2di
18674 = build_function_type_list (void_type_node,
18675 pv2di_type_node, V2DI_type_node, NULL_TREE);
18676 /* Normal vector unops. */
18677 tree v4sf_ftype_v4sf
18678 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
18679 tree v16qi_ftype_v16qi
18680 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
18681 tree v8hi_ftype_v8hi
18682 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
18683 tree v4si_ftype_v4si
18684 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18685 tree v8qi_ftype_v8qi
18686 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
18687 tree v4hi_ftype_v4hi
18688 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
18690 /* Normal vector binops. */
18691 tree v4sf_ftype_v4sf_v4sf
18692 = build_function_type_list (V4SF_type_node,
18693 V4SF_type_node, V4SF_type_node, NULL_TREE);
18694 tree v8qi_ftype_v8qi_v8qi
18695 = build_function_type_list (V8QI_type_node,
18696 V8QI_type_node, V8QI_type_node, NULL_TREE);
18697 tree v4hi_ftype_v4hi_v4hi
18698 = build_function_type_list (V4HI_type_node,
18699 V4HI_type_node, V4HI_type_node, NULL_TREE);
18700 tree v2si_ftype_v2si_v2si
18701 = build_function_type_list (V2SI_type_node,
18702 V2SI_type_node, V2SI_type_node, NULL_TREE);
18703 tree v1di_ftype_v1di_v1di
18704 = build_function_type_list (V1DI_type_node,
18705 V1DI_type_node, V1DI_type_node, NULL_TREE);
18707 tree di_ftype_di_di_int
18708 = build_function_type_list (long_long_unsigned_type_node,
18709 long_long_unsigned_type_node,
18710 long_long_unsigned_type_node,
18711 integer_type_node, NULL_TREE);
18713 tree v2si_ftype_v2sf
18714 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
18715 tree v2sf_ftype_v2si
18716 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
18717 tree v2si_ftype_v2si
18718 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
18719 tree v2sf_ftype_v2sf
18720 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
18721 tree v2sf_ftype_v2sf_v2sf
18722 = build_function_type_list (V2SF_type_node,
18723 V2SF_type_node, V2SF_type_node, NULL_TREE);
18724 tree v2si_ftype_v2sf_v2sf
18725 = build_function_type_list (V2SI_type_node,
18726 V2SF_type_node, V2SF_type_node, NULL_TREE);
18727 tree pint_type_node = build_pointer_type (integer_type_node);
18728 tree pdouble_type_node = build_pointer_type (double_type_node);
18729 tree pcdouble_type_node = build_pointer_type (
18730 build_type_variant (double_type_node, 1, 0));
18731 tree int_ftype_v2df_v2df
18732 = build_function_type_list (integer_type_node,
18733 V2DF_type_node, V2DF_type_node, NULL_TREE);
18735 tree void_ftype_pcvoid
18736 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
18737 tree v4sf_ftype_v4si
18738 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
18739 tree v4si_ftype_v4sf
18740 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
18741 tree v2df_ftype_v4si
18742 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
18743 tree v4si_ftype_v2df
18744 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
18745 tree v4si_ftype_v2df_v2df
18746 = build_function_type_list (V4SI_type_node,
18747 V2DF_type_node, V2DF_type_node, NULL_TREE);
18748 tree v2si_ftype_v2df
18749 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
18750 tree v4sf_ftype_v2df
18751 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
18752 tree v2df_ftype_v2si
18753 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
18754 tree v2df_ftype_v4sf
18755 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
18756 tree int_ftype_v2df
18757 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
18758 tree int64_ftype_v2df
18759 = build_function_type_list (long_long_integer_type_node,
18760 V2DF_type_node, NULL_TREE);
18761 tree v2df_ftype_v2df_int
18762 = build_function_type_list (V2DF_type_node,
18763 V2DF_type_node, integer_type_node, NULL_TREE);
18764 tree v2df_ftype_v2df_int64
18765 = build_function_type_list (V2DF_type_node,
18766 V2DF_type_node, long_long_integer_type_node,
18768 tree v4sf_ftype_v4sf_v2df
18769 = build_function_type_list (V4SF_type_node,
18770 V4SF_type_node, V2DF_type_node, NULL_TREE);
18771 tree v2df_ftype_v2df_v4sf
18772 = build_function_type_list (V2DF_type_node,
18773 V2DF_type_node, V4SF_type_node, NULL_TREE);
18774 tree v2df_ftype_v2df_v2df_int
18775 = build_function_type_list (V2DF_type_node,
18776 V2DF_type_node, V2DF_type_node,
18779 tree v2df_ftype_v2df_pcdouble
18780 = build_function_type_list (V2DF_type_node,
18781 V2DF_type_node, pcdouble_type_node, NULL_TREE);
18782 tree void_ftype_pdouble_v2df
18783 = build_function_type_list (void_type_node,
18784 pdouble_type_node, V2DF_type_node, NULL_TREE);
18785 tree void_ftype_pint_int
18786 = build_function_type_list (void_type_node,
18787 pint_type_node, integer_type_node, NULL_TREE);
18788 tree void_ftype_v16qi_v16qi_pchar
18789 = build_function_type_list (void_type_node,
18790 V16QI_type_node, V16QI_type_node,
18791 pchar_type_node, NULL_TREE);
18792 tree v2df_ftype_pcdouble
18793 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
18794 tree v2df_ftype_v2df_v2df
18795 = build_function_type_list (V2DF_type_node,
18796 V2DF_type_node, V2DF_type_node, NULL_TREE);
18797 tree v16qi_ftype_v16qi_v16qi
18798 = build_function_type_list (V16QI_type_node,
18799 V16QI_type_node, V16QI_type_node, NULL_TREE);
18800 tree v8hi_ftype_v8hi_v8hi
18801 = build_function_type_list (V8HI_type_node,
18802 V8HI_type_node, V8HI_type_node, NULL_TREE);
18803 tree v4si_ftype_v4si_v4si
18804 = build_function_type_list (V4SI_type_node,
18805 V4SI_type_node, V4SI_type_node, NULL_TREE);
18806 tree v2di_ftype_v2di_v2di
18807 = build_function_type_list (V2DI_type_node,
18808 V2DI_type_node, V2DI_type_node, NULL_TREE);
18809 tree v2di_ftype_v2df_v2df
18810 = build_function_type_list (V2DI_type_node,
18811 V2DF_type_node, V2DF_type_node, NULL_TREE);
18812 tree v2df_ftype_v2df
18813 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
18814 tree v2di_ftype_v2di_int
18815 = build_function_type_list (V2DI_type_node,
18816 V2DI_type_node, integer_type_node, NULL_TREE);
18817 tree v2di_ftype_v2di_v2di_int
18818 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18819 V2DI_type_node, integer_type_node, NULL_TREE);
18820 tree v4si_ftype_v4si_int
18821 = build_function_type_list (V4SI_type_node,
18822 V4SI_type_node, integer_type_node, NULL_TREE);
18823 tree v8hi_ftype_v8hi_int
18824 = build_function_type_list (V8HI_type_node,
18825 V8HI_type_node, integer_type_node, NULL_TREE);
18826 tree v4si_ftype_v8hi_v8hi
18827 = build_function_type_list (V4SI_type_node,
18828 V8HI_type_node, V8HI_type_node, NULL_TREE);
18829 tree v1di_ftype_v8qi_v8qi
18830 = build_function_type_list (V1DI_type_node,
18831 V8QI_type_node, V8QI_type_node, NULL_TREE);
18832 tree v1di_ftype_v2si_v2si
18833 = build_function_type_list (V1DI_type_node,
18834 V2SI_type_node, V2SI_type_node, NULL_TREE);
18835 tree v2di_ftype_v16qi_v16qi
18836 = build_function_type_list (V2DI_type_node,
18837 V16QI_type_node, V16QI_type_node, NULL_TREE);
18838 tree v2di_ftype_v4si_v4si
18839 = build_function_type_list (V2DI_type_node,
18840 V4SI_type_node, V4SI_type_node, NULL_TREE);
18841 tree int_ftype_v16qi
18842 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
18843 tree v16qi_ftype_pcchar
18844 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
18845 tree void_ftype_pchar_v16qi
18846 = build_function_type_list (void_type_node,
18847 pchar_type_node, V16QI_type_node, NULL_TREE);
18849 tree v2di_ftype_v2di_unsigned_unsigned
18850 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18851 unsigned_type_node, unsigned_type_node,
18853 tree v2di_ftype_v2di_v2di_unsigned_unsigned
18854 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
18855 unsigned_type_node, unsigned_type_node,
18857 tree v2di_ftype_v2di_v16qi
18858 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
18860 tree v2df_ftype_v2df_v2df_v2df
18861 = build_function_type_list (V2DF_type_node,
18862 V2DF_type_node, V2DF_type_node,
18863 V2DF_type_node, NULL_TREE);
18864 tree v4sf_ftype_v4sf_v4sf_v4sf
18865 = build_function_type_list (V4SF_type_node,
18866 V4SF_type_node, V4SF_type_node,
18867 V4SF_type_node, NULL_TREE);
18868 tree v8hi_ftype_v16qi
18869 = build_function_type_list (V8HI_type_node, V16QI_type_node,
18871 tree v4si_ftype_v16qi
18872 = build_function_type_list (V4SI_type_node, V16QI_type_node,
18874 tree v2di_ftype_v16qi
18875 = build_function_type_list (V2DI_type_node, V16QI_type_node,
18877 tree v4si_ftype_v8hi
18878 = build_function_type_list (V4SI_type_node, V8HI_type_node,
18880 tree v2di_ftype_v8hi
18881 = build_function_type_list (V2DI_type_node, V8HI_type_node,
18883 tree v2di_ftype_v4si
18884 = build_function_type_list (V2DI_type_node, V4SI_type_node,
18886 tree v2di_ftype_pv2di
18887 = build_function_type_list (V2DI_type_node, pv2di_type_node,
18889 tree v16qi_ftype_v16qi_v16qi_int
18890 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18891 V16QI_type_node, integer_type_node,
18893 tree v16qi_ftype_v16qi_v16qi_v16qi
18894 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18895 V16QI_type_node, V16QI_type_node,
18897 tree v8hi_ftype_v8hi_v8hi_int
18898 = build_function_type_list (V8HI_type_node, V8HI_type_node,
18899 V8HI_type_node, integer_type_node,
18901 tree v4si_ftype_v4si_v4si_int
18902 = build_function_type_list (V4SI_type_node, V4SI_type_node,
18903 V4SI_type_node, integer_type_node,
18905 tree int_ftype_v2di_v2di
18906 = build_function_type_list (integer_type_node,
18907 V2DI_type_node, V2DI_type_node,
18909 tree int_ftype_v16qi_int_v16qi_int_int
18910 = build_function_type_list (integer_type_node,
18917 tree v16qi_ftype_v16qi_int_v16qi_int_int
18918 = build_function_type_list (V16QI_type_node,
18925 tree int_ftype_v16qi_v16qi_int
18926 = build_function_type_list (integer_type_node,
18932 /* SSE5 instructions */
18933 tree v2di_ftype_v2di_v2di_v2di
18934 = build_function_type_list (V2DI_type_node,
18940 tree v4si_ftype_v4si_v4si_v4si
18941 = build_function_type_list (V4SI_type_node,
18947 tree v4si_ftype_v4si_v4si_v2di
18948 = build_function_type_list (V4SI_type_node,
18954 tree v8hi_ftype_v8hi_v8hi_v8hi
18955 = build_function_type_list (V8HI_type_node,
18961 tree v8hi_ftype_v8hi_v8hi_v4si
18962 = build_function_type_list (V8HI_type_node,
18968 tree v2df_ftype_v2df_v2df_v16qi
18969 = build_function_type_list (V2DF_type_node,
18975 tree v4sf_ftype_v4sf_v4sf_v16qi
18976 = build_function_type_list (V4SF_type_node,
18982 tree v2di_ftype_v2di_si
18983 = build_function_type_list (V2DI_type_node,
18988 tree v4si_ftype_v4si_si
18989 = build_function_type_list (V4SI_type_node,
18994 tree v8hi_ftype_v8hi_si
18995 = build_function_type_list (V8HI_type_node,
19000 tree v16qi_ftype_v16qi_si
19001 = build_function_type_list (V16QI_type_node,
19005 tree v4sf_ftype_v4hi
19006 = build_function_type_list (V4SF_type_node,
19010 tree v4hi_ftype_v4sf
19011 = build_function_type_list (V4HI_type_node,
19015 tree v2di_ftype_v2di
19016 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19020 /* The __float80 type. */
19021 if (TYPE_MODE (long_double_type_node) == XFmode)
19022 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19026 /* The __float80 type. */
19027 tree float80_type_node = make_node (REAL_TYPE);
19029 TYPE_PRECISION (float80_type_node) = 80;
19030 layout_type (float80_type_node);
19031 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19037 tree float128_type_node = make_node (REAL_TYPE);
19039 TYPE_PRECISION (float128_type_node) = 128;
19040 layout_type (float128_type_node);
19041 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19044 /* TFmode support builtins. */
19045 ftype = build_function_type (float128_type_node,
19047 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19049 ftype = build_function_type_list (float128_type_node,
19050 float128_type_node,
19052 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19054 ftype = build_function_type_list (float128_type_node,
19055 float128_type_node,
19056 float128_type_node,
19058 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19061 /* Add all SSE builtins that are more or less simple operations on
19063 for (i = 0, d = bdesc_sse_3arg;
19064 i < ARRAY_SIZE (bdesc_sse_3arg);
19067 /* Use one of the operands; the target can have a different mode for
19068 mask-generating compares. */
19069 enum machine_mode mode;
19074 mode = insn_data[d->icode].operand[1].mode;
19079 type = v16qi_ftype_v16qi_v16qi_int;
19082 type = v8hi_ftype_v8hi_v8hi_int;
19085 type = v4si_ftype_v4si_v4si_int;
19088 type = v2di_ftype_v2di_v2di_int;
19091 type = v2df_ftype_v2df_v2df_int;
19094 type = v4sf_ftype_v4sf_v4sf_int;
19097 gcc_unreachable ();
19100 /* Override for variable blends. */
19103 case CODE_FOR_sse4_1_blendvpd:
19104 type = v2df_ftype_v2df_v2df_v2df;
19106 case CODE_FOR_sse4_1_blendvps:
19107 type = v4sf_ftype_v4sf_v4sf_v4sf;
19109 case CODE_FOR_sse4_1_pblendvb:
19110 type = v16qi_ftype_v16qi_v16qi_v16qi;
19116 def_builtin_const (d->mask, d->name, type, d->code);
19119 /* Add all builtins that are more or less simple operations on two
19121 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19123 /* Use one of the operands; the target can have a different mode for
19124 mask-generating compares. */
19125 enum machine_mode mode;
19130 mode = insn_data[d->icode].operand[1].mode;
19135 type = v16qi_ftype_v16qi_v16qi;
19138 type = v8hi_ftype_v8hi_v8hi;
19141 type = v4si_ftype_v4si_v4si;
19144 type = v2di_ftype_v2di_v2di;
19147 type = v2df_ftype_v2df_v2df;
19150 type = v4sf_ftype_v4sf_v4sf;
19153 type = v8qi_ftype_v8qi_v8qi;
19156 type = v4hi_ftype_v4hi_v4hi;
19159 type = v2si_ftype_v2si_v2si;
19162 type = v1di_ftype_v1di_v1di;
19166 gcc_unreachable ();
19169 /* Override for comparisons. */
19170 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19171 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
19172 type = v4si_ftype_v4sf_v4sf;
19174 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
19175 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19176 type = v2di_ftype_v2df_v2df;
19178 if (d->icode == CODE_FOR_vec_pack_sfix_v2df)
19179 type = v4si_ftype_v2df_v2df;
19181 def_builtin_const (d->mask, d->name, type, d->code);
19184 /* Add all builtins that are more or less simple operations on 1 operand. */
19185 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19187 enum machine_mode mode;
19192 mode = insn_data[d->icode].operand[1].mode;
19197 type = v16qi_ftype_v16qi;
19200 type = v8hi_ftype_v8hi;
19203 type = v4si_ftype_v4si;
19206 type = v2df_ftype_v2df;
19209 type = v4sf_ftype_v4sf;
19212 type = v8qi_ftype_v8qi;
19215 type = v4hi_ftype_v4hi;
19218 type = v2si_ftype_v2si;
19225 def_builtin_const (d->mask, d->name, type, d->code);
19228 /* pcmpestr[im] insns. */
19229 for (i = 0, d = bdesc_pcmpestr;
19230 i < ARRAY_SIZE (bdesc_pcmpestr);
19233 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19234 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19236 ftype = int_ftype_v16qi_int_v16qi_int_int;
19237 def_builtin_const (d->mask, d->name, ftype, d->code);
19240 /* pcmpistr[im] insns. */
19241 for (i = 0, d = bdesc_pcmpistr;
19242 i < ARRAY_SIZE (bdesc_pcmpistr);
19245 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19246 ftype = v16qi_ftype_v16qi_v16qi_int;
19248 ftype = int_ftype_v16qi_v16qi_int;
19249 def_builtin_const (d->mask, d->name, ftype, d->code);
19252 /* Add the remaining MMX insns with somewhat more complicated types. */
19253 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
19255 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSLLWI);
19256 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSLLDI);
19257 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSLLQI);
19258 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSLLW);
19259 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSLLD);
19260 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSLLQ);
19262 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRLWI);
19263 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRLDI);
19264 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSRLQI);
19265 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRLW);
19266 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRLD);
19267 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSRLQ);
19269 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrawi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRAWI);
19270 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psradi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRADI);
19271 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRAW);
19272 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRAD);
19274 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
19275 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
19277 /* comi/ucomi insns. */
19278 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19279 if (d->mask == OPTION_MASK_ISA_SSE2)
19280 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19282 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19285 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19286 def_builtin_const (d->mask, d->name, int_ftype_v2di_v2di, d->code);
19288 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
19289 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
19290 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
19292 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19293 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19294 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
19295 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
19296 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
19297 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
19298 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
19299 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
19300 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
19301 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
19302 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
19304 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19306 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
19307 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
19309 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
19310 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
19311 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
19312 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
19314 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
19315 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
19316 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
19317 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
19319 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
19321 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", v1di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
19323 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
19324 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
19325 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
19326 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS_NR);
19327 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
19328 ftype = build_function_type_list (float_type_node,
19331 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
19332 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
19333 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS_NR);
19334 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
19336 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
19338 /* Original 3DNow! */
19339 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
19340 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
19341 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
19342 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
19343 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
19344 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
19345 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
19346 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
19347 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
19348 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
19349 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
19350 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
19351 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
19352 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
19353 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
19354 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
19355 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
19356 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
19357 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
19358 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
19360 /* 3DNow! extension as used in the Athlon CPU. */
19361 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
19362 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
19363 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
19364 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
19365 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
19366 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
19369 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19371 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
19372 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
19374 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
19375 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
19377 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
19378 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
19379 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
19380 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
19381 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
19383 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
19384 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
19385 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
19386 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
19388 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
19389 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
19391 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
19393 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
19394 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
19396 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
19397 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
19398 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
19399 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
19400 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
19402 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
19404 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
19405 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
19406 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
19407 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
19409 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
19410 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
19411 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
19413 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
19414 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
19415 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
19416 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
19418 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19419 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
19420 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19422 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
19423 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
19425 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", v1di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
19426 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
19428 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
19429 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
19430 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
19431 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
19432 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
19433 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
19434 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
19436 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
19437 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
19438 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
19439 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
19440 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
19441 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
19442 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
19444 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
19445 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
19446 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
19447 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
19449 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
19451 /* Prescott New Instructions. */
19452 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19453 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19454 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
19457 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
19458 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
19461 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
19462 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
19463 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
19464 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
19465 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
19466 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
19467 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
19468 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
19469 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
19470 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
19471 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
19472 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
19473 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
19474 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
19476 /* SSE4.1 and SSE5 */
19477 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundpd", v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
19478 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundps", v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
19479 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundsd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
19480 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundss", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
19483 ftype = build_function_type_list (unsigned_type_node,
19484 unsigned_type_node,
19485 unsigned_char_type_node,
19487 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
19488 ftype = build_function_type_list (unsigned_type_node,
19489 unsigned_type_node,
19490 short_unsigned_type_node,
19492 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
19493 ftype = build_function_type_list (unsigned_type_node,
19494 unsigned_type_node,
19495 unsigned_type_node,
19497 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
19498 ftype = build_function_type_list (long_long_unsigned_type_node,
19499 long_long_unsigned_type_node,
19500 long_long_unsigned_type_node,
19502 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
19504 /* AMDFAM10 SSE4A New built-ins */
19505 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
19506 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
19507 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
19508 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
19509 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
19510 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
19512 /* Access to the vec_init patterns. */
19513 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19514 integer_type_node, NULL_TREE);
19515 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19517 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19518 short_integer_type_node,
19519 short_integer_type_node,
19520 short_integer_type_node, NULL_TREE);
19521 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19523 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19524 char_type_node, char_type_node,
19525 char_type_node, char_type_node,
19526 char_type_node, char_type_node,
19527 char_type_node, NULL_TREE);
19528 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19530 /* Access to the vec_extract patterns. */
19531 ftype = build_function_type_list (double_type_node, V2DF_type_node,
19532 integer_type_node, NULL_TREE);
19533 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
19535 ftype = build_function_type_list (long_long_integer_type_node,
19536 V2DI_type_node, integer_type_node,
19538 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
19540 ftype = build_function_type_list (float_type_node, V4SF_type_node,
19541 integer_type_node, NULL_TREE);
19542 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
19544 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
19545 integer_type_node, NULL_TREE);
19546 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
19548 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
19549 integer_type_node, NULL_TREE);
19550 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
19552 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
19553 integer_type_node, NULL_TREE);
19554 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
19556 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
19557 integer_type_node, NULL_TREE);
19558 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
19560 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
19561 integer_type_node, NULL_TREE);
19562 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
19564 /* Access to the vec_set patterns. */
19565 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
19567 integer_type_node, NULL_TREE);
19568 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
19570 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
19572 integer_type_node, NULL_TREE);
19573 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
19575 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
19577 integer_type_node, NULL_TREE);
19578 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
19580 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
19582 integer_type_node, NULL_TREE);
19583 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
19585 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
19587 integer_type_node, NULL_TREE);
19588 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
19590 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
19592 integer_type_node, NULL_TREE);
19593 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
19595 /* Add SSE5 multi-arg argument instructions */
19596 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
19598 tree mtype = NULL_TREE;
19603 switch ((enum multi_arg_type)d->flag)
19605 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
19606 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
19607 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
19608 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
19609 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
19610 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
19611 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
19612 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
19613 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
19614 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
19615 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
19616 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
19617 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
19618 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
19619 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
19620 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
19621 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
19622 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
19623 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
19624 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
19625 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
19626 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
19627 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
19628 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
19629 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
19630 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
19631 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
19632 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
19633 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
19634 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
19635 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
19636 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
19637 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
19638 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
19639 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
19640 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
19641 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
19642 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
19643 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
19644 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
19645 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
19646 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
19647 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
19648 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
19649 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
19650 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
19651 case MULTI_ARG_UNKNOWN:
19653 gcc_unreachable ();
19657 def_builtin_const (d->mask, d->name, mtype, d->code);
19662 ix86_init_builtins (void)
19665 ix86_init_mmx_sse_builtins ();
19668 /* Errors in the source file can cause expand_expr to return const0_rtx
19669 where we expect a vector. To avoid crashing, use one of the vector
19670 clear instructions. */
19672 safe_vector_operand (rtx x, enum machine_mode mode)
19674 if (x == const0_rtx)
19675 x = CONST0_RTX (mode);
19679 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
19680 4 operands. The third argument must be a constant smaller than 8
19684 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
19688 tree arg0 = CALL_EXPR_ARG (exp, 0);
19689 tree arg1 = CALL_EXPR_ARG (exp, 1);
19690 tree arg2 = CALL_EXPR_ARG (exp, 2);
19691 rtx op0 = expand_normal (arg0);
19692 rtx op1 = expand_normal (arg1);
19693 rtx op2 = expand_normal (arg2);
19694 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19695 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
19696 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
19697 enum machine_mode mode3 = insn_data[icode].operand[3].mode;
19699 if (VECTOR_MODE_P (mode1))
19700 op0 = safe_vector_operand (op0, mode1);
19701 if (VECTOR_MODE_P (mode2))
19702 op1 = safe_vector_operand (op1, mode2);
19703 if (VECTOR_MODE_P (mode3))
19704 op2 = safe_vector_operand (op2, mode3);
19708 || GET_MODE (target) != tmode
19709 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19710 target = gen_reg_rtx (tmode);
19712 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19713 op0 = copy_to_mode_reg (mode1, op0);
19714 if ((optimize && !register_operand (op1, mode2))
19715 || !(*insn_data[icode].operand[2].predicate) (op1, mode2))
19716 op1 = copy_to_mode_reg (mode2, op1);
19718 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19721 case CODE_FOR_sse4_1_blendvpd:
19722 case CODE_FOR_sse4_1_blendvps:
19723 case CODE_FOR_sse4_1_pblendvb:
19724 op2 = copy_to_mode_reg (mode3, op2);
19727 case CODE_FOR_sse4_1_roundsd:
19728 case CODE_FOR_sse4_1_roundss:
19729 error ("the third argument must be a 4-bit immediate");
19733 error ("the third argument must be an 8-bit immediate");
19737 pat = GEN_FCN (icode) (target, op0, op1, op2);
19744 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
19747 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
19750 tree arg0 = CALL_EXPR_ARG (exp, 0);
19751 tree arg1 = CALL_EXPR_ARG (exp, 1);
19752 rtx op0 = expand_normal (arg0);
19753 rtx op1 = expand_normal (arg1);
19754 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19755 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19756 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19760 || GET_MODE (target) != tmode
19761 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19762 target = gen_reg_rtx (tmode);
19764 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19765 op0 = copy_to_mode_reg (mode0, op0);
19766 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19768 op1 = copy_to_reg (op1);
19769 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
19772 pat = GEN_FCN (icode) (target, op0, op1);
19779 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
19782 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
19785 tree arg0 = CALL_EXPR_ARG (exp, 0);
19786 tree arg1 = CALL_EXPR_ARG (exp, 1);
19787 rtx op0 = expand_normal (arg0);
19788 rtx op1 = expand_normal (arg1);
19789 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19790 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19791 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19793 if (VECTOR_MODE_P (mode0))
19794 op0 = safe_vector_operand (op0, mode0);
19795 if (VECTOR_MODE_P (mode1))
19796 op1 = safe_vector_operand (op1, mode1);
19798 if (optimize || !target
19799 || GET_MODE (target) != tmode
19800 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19801 target = gen_reg_rtx (tmode);
19803 if (GET_MODE (op1) == SImode && mode1 == TImode)
19805 rtx x = gen_reg_rtx (V4SImode);
19806 emit_insn (gen_sse2_loadd (x, op1));
19807 op1 = gen_lowpart (TImode, x);
19810 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19811 op0 = copy_to_mode_reg (mode0, op0);
19812 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19813 op1 = copy_to_mode_reg (mode1, op1);
19815 /* ??? Using ix86_fixup_binary_operands is problematic when
19816 we've got mismatched modes. Fake it. */
19822 if (tmode == mode0 && tmode == mode1)
19824 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
19828 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
19830 op0 = force_reg (mode0, op0);
19831 op1 = force_reg (mode1, op1);
19832 target = gen_reg_rtx (tmode);
19835 pat = GEN_FCN (icode) (target, op0, op1);
19842 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
19845 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
19846 enum multi_arg_type m_type,
19847 enum insn_code sub_code)
19852 bool comparison_p = false;
19854 bool last_arg_constant = false;
19855 int num_memory = 0;
19858 enum machine_mode mode;
19861 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19865 case MULTI_ARG_3_SF:
19866 case MULTI_ARG_3_DF:
19867 case MULTI_ARG_3_DI:
19868 case MULTI_ARG_3_SI:
19869 case MULTI_ARG_3_SI_DI:
19870 case MULTI_ARG_3_HI:
19871 case MULTI_ARG_3_HI_SI:
19872 case MULTI_ARG_3_QI:
19873 case MULTI_ARG_3_PERMPS:
19874 case MULTI_ARG_3_PERMPD:
19878 case MULTI_ARG_2_SF:
19879 case MULTI_ARG_2_DF:
19880 case MULTI_ARG_2_DI:
19881 case MULTI_ARG_2_SI:
19882 case MULTI_ARG_2_HI:
19883 case MULTI_ARG_2_QI:
19887 case MULTI_ARG_2_DI_IMM:
19888 case MULTI_ARG_2_SI_IMM:
19889 case MULTI_ARG_2_HI_IMM:
19890 case MULTI_ARG_2_QI_IMM:
19892 last_arg_constant = true;
19895 case MULTI_ARG_1_SF:
19896 case MULTI_ARG_1_DF:
19897 case MULTI_ARG_1_DI:
19898 case MULTI_ARG_1_SI:
19899 case MULTI_ARG_1_HI:
19900 case MULTI_ARG_1_QI:
19901 case MULTI_ARG_1_SI_DI:
19902 case MULTI_ARG_1_HI_DI:
19903 case MULTI_ARG_1_HI_SI:
19904 case MULTI_ARG_1_QI_DI:
19905 case MULTI_ARG_1_QI_SI:
19906 case MULTI_ARG_1_QI_HI:
19907 case MULTI_ARG_1_PH2PS:
19908 case MULTI_ARG_1_PS2PH:
19912 case MULTI_ARG_2_SF_CMP:
19913 case MULTI_ARG_2_DF_CMP:
19914 case MULTI_ARG_2_DI_CMP:
19915 case MULTI_ARG_2_SI_CMP:
19916 case MULTI_ARG_2_HI_CMP:
19917 case MULTI_ARG_2_QI_CMP:
19919 comparison_p = true;
19922 case MULTI_ARG_2_SF_TF:
19923 case MULTI_ARG_2_DF_TF:
19924 case MULTI_ARG_2_DI_TF:
19925 case MULTI_ARG_2_SI_TF:
19926 case MULTI_ARG_2_HI_TF:
19927 case MULTI_ARG_2_QI_TF:
19932 case MULTI_ARG_UNKNOWN:
19934 gcc_unreachable ();
19937 if (optimize || !target
19938 || GET_MODE (target) != tmode
19939 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19940 target = gen_reg_rtx (tmode);
19942 gcc_assert (nargs <= 4);
19944 for (i = 0; i < nargs; i++)
19946 tree arg = CALL_EXPR_ARG (exp, i);
19947 rtx op = expand_normal (arg);
19948 int adjust = (comparison_p) ? 1 : 0;
19949 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
19951 if (last_arg_constant && i == nargs-1)
19953 if (GET_CODE (op) != CONST_INT)
19955 error ("last argument must be an immediate");
19956 return gen_reg_rtx (tmode);
19961 if (VECTOR_MODE_P (mode))
19962 op = safe_vector_operand (op, mode);
19964 /* If we aren't optimizing, only allow one memory operand to be
19966 if (memory_operand (op, mode))
19969 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
19972 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
19974 op = force_reg (mode, op);
19978 args[i].mode = mode;
19984 pat = GEN_FCN (icode) (target, args[0].op);
19989 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
19990 GEN_INT ((int)sub_code));
19991 else if (! comparison_p)
19992 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
19995 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
19999 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20004 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20008 gcc_unreachable ();
20018 /* Subroutine of ix86_expand_builtin to take care of stores. */
20021 ix86_expand_store_builtin (enum insn_code icode, tree exp)
20024 tree arg0 = CALL_EXPR_ARG (exp, 0);
20025 tree arg1 = CALL_EXPR_ARG (exp, 1);
20026 rtx op0 = expand_normal (arg0);
20027 rtx op1 = expand_normal (arg1);
20028 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
20029 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
20031 if (VECTOR_MODE_P (mode1))
20032 op1 = safe_vector_operand (op1, mode1);
20034 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20035 op1 = copy_to_mode_reg (mode1, op1);
20037 pat = GEN_FCN (icode) (op0, op1);
20043 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
20046 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
20047 rtx target, int do_load)
20050 tree arg0 = CALL_EXPR_ARG (exp, 0);
20051 rtx op0 = expand_normal (arg0);
20052 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20053 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20055 if (optimize || !target
20056 || GET_MODE (target) != tmode
20057 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20058 target = gen_reg_rtx (tmode);
20060 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20063 if (VECTOR_MODE_P (mode0))
20064 op0 = safe_vector_operand (op0, mode0);
20066 if ((optimize && !register_operand (op0, mode0))
20067 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20068 op0 = copy_to_mode_reg (mode0, op0);
20073 case CODE_FOR_sse4_1_roundpd:
20074 case CODE_FOR_sse4_1_roundps:
20076 tree arg1 = CALL_EXPR_ARG (exp, 1);
20077 rtx op1 = expand_normal (arg1);
20078 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20080 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
20082 error ("the second argument must be a 4-bit immediate");
20085 pat = GEN_FCN (icode) (target, op0, op1);
20089 pat = GEN_FCN (icode) (target, op0);
20099 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
20100 sqrtss, rsqrtss, rcpss. */
20103 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
20106 tree arg0 = CALL_EXPR_ARG (exp, 0);
20107 rtx op1, op0 = expand_normal (arg0);
20108 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20109 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20111 if (optimize || !target
20112 || GET_MODE (target) != tmode
20113 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20114 target = gen_reg_rtx (tmode);
20116 if (VECTOR_MODE_P (mode0))
20117 op0 = safe_vector_operand (op0, mode0);
20119 if ((optimize && !register_operand (op0, mode0))
20120 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20121 op0 = copy_to_mode_reg (mode0, op0);
20124 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20125 op1 = copy_to_mode_reg (mode0, op1);
20127 pat = GEN_FCN (icode) (target, op0, op1);
20134 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20137 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
20141 tree arg0 = CALL_EXPR_ARG (exp, 0);
20142 tree arg1 = CALL_EXPR_ARG (exp, 1);
20143 rtx op0 = expand_normal (arg0);
20144 rtx op1 = expand_normal (arg1);
20146 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20147 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20148 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20149 enum rtx_code comparison = d->comparison;
20151 if (VECTOR_MODE_P (mode0))
20152 op0 = safe_vector_operand (op0, mode0);
20153 if (VECTOR_MODE_P (mode1))
20154 op1 = safe_vector_operand (op1, mode1);
20156 /* Swap operands if we have a comparison that isn't available in
20158 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20160 rtx tmp = gen_reg_rtx (mode1);
20161 emit_move_insn (tmp, op1);
20166 if (optimize || !target
20167 || GET_MODE (target) != tmode
20168 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20169 target = gen_reg_rtx (tmode);
20171 if ((optimize && !register_operand (op0, mode0))
20172 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20173 op0 = copy_to_mode_reg (mode0, op0);
20174 if ((optimize && !register_operand (op1, mode1))
20175 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20176 op1 = copy_to_mode_reg (mode1, op1);
20178 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20179 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20186 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20189 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20193 tree arg0 = CALL_EXPR_ARG (exp, 0);
20194 tree arg1 = CALL_EXPR_ARG (exp, 1);
20195 rtx op0 = expand_normal (arg0);
20196 rtx op1 = expand_normal (arg1);
20197 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20198 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20199 enum rtx_code comparison = d->comparison;
20201 if (VECTOR_MODE_P (mode0))
20202 op0 = safe_vector_operand (op0, mode0);
20203 if (VECTOR_MODE_P (mode1))
20204 op1 = safe_vector_operand (op1, mode1);
20206 /* Swap operands if we have a comparison that isn't available in
20208 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20215 target = gen_reg_rtx (SImode);
20216 emit_move_insn (target, const0_rtx);
20217 target = gen_rtx_SUBREG (QImode, target, 0);
20219 if ((optimize && !register_operand (op0, mode0))
20220 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20221 op0 = copy_to_mode_reg (mode0, op0);
20222 if ((optimize && !register_operand (op1, mode1))
20223 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20224 op1 = copy_to_mode_reg (mode1, op1);
20226 pat = GEN_FCN (d->icode) (op0, op1);
20230 emit_insn (gen_rtx_SET (VOIDmode,
20231 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20232 gen_rtx_fmt_ee (comparison, QImode,
20236 return SUBREG_REG (target);
20239 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20242 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20246 tree arg0 = CALL_EXPR_ARG (exp, 0);
20247 tree arg1 = CALL_EXPR_ARG (exp, 1);
20248 rtx op0 = expand_normal (arg0);
20249 rtx op1 = expand_normal (arg1);
20250 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20251 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20252 enum rtx_code comparison = d->comparison;
20254 if (VECTOR_MODE_P (mode0))
20255 op0 = safe_vector_operand (op0, mode0);
20256 if (VECTOR_MODE_P (mode1))
20257 op1 = safe_vector_operand (op1, mode1);
20259 target = gen_reg_rtx (SImode);
20260 emit_move_insn (target, const0_rtx);
20261 target = gen_rtx_SUBREG (QImode, target, 0);
20263 if ((optimize && !register_operand (op0, mode0))
20264 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20265 op0 = copy_to_mode_reg (mode0, op0);
20266 if ((optimize && !register_operand (op1, mode1))
20267 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20268 op1 = copy_to_mode_reg (mode1, op1);
20270 pat = GEN_FCN (d->icode) (op0, op1);
20274 emit_insn (gen_rtx_SET (VOIDmode,
20275 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20276 gen_rtx_fmt_ee (comparison, QImode,
20280 return SUBREG_REG (target);
20283 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20286 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20287 tree exp, rtx target)
20290 tree arg0 = CALL_EXPR_ARG (exp, 0);
20291 tree arg1 = CALL_EXPR_ARG (exp, 1);
20292 tree arg2 = CALL_EXPR_ARG (exp, 2);
20293 tree arg3 = CALL_EXPR_ARG (exp, 3);
20294 tree arg4 = CALL_EXPR_ARG (exp, 4);
20295 rtx scratch0, scratch1;
20296 rtx op0 = expand_normal (arg0);
20297 rtx op1 = expand_normal (arg1);
20298 rtx op2 = expand_normal (arg2);
20299 rtx op3 = expand_normal (arg3);
20300 rtx op4 = expand_normal (arg4);
20301 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20303 tmode0 = insn_data[d->icode].operand[0].mode;
20304 tmode1 = insn_data[d->icode].operand[1].mode;
20305 modev2 = insn_data[d->icode].operand[2].mode;
20306 modei3 = insn_data[d->icode].operand[3].mode;
20307 modev4 = insn_data[d->icode].operand[4].mode;
20308 modei5 = insn_data[d->icode].operand[5].mode;
20309 modeimm = insn_data[d->icode].operand[6].mode;
20311 if (VECTOR_MODE_P (modev2))
20312 op0 = safe_vector_operand (op0, modev2);
20313 if (VECTOR_MODE_P (modev4))
20314 op2 = safe_vector_operand (op2, modev4);
20316 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20317 op0 = copy_to_mode_reg (modev2, op0);
20318 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20319 op1 = copy_to_mode_reg (modei3, op1);
20320 if ((optimize && !register_operand (op2, modev4))
20321 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20322 op2 = copy_to_mode_reg (modev4, op2);
20323 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20324 op3 = copy_to_mode_reg (modei5, op3);
20326 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20328 error ("the fifth argument must be a 8-bit immediate");
20332 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20334 if (optimize || !target
20335 || GET_MODE (target) != tmode0
20336 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20337 target = gen_reg_rtx (tmode0);
20339 scratch1 = gen_reg_rtx (tmode1);
20341 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20343 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20345 if (optimize || !target
20346 || GET_MODE (target) != tmode1
20347 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20348 target = gen_reg_rtx (tmode1);
20350 scratch0 = gen_reg_rtx (tmode0);
20352 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20356 gcc_assert (d->flag);
20358 scratch0 = gen_reg_rtx (tmode0);
20359 scratch1 = gen_reg_rtx (tmode1);
20361 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20371 target = gen_reg_rtx (SImode);
20372 emit_move_insn (target, const0_rtx);
20373 target = gen_rtx_SUBREG (QImode, target, 0);
20376 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20377 gen_rtx_fmt_ee (EQ, QImode,
20378 gen_rtx_REG ((enum machine_mode) d->flag,
20381 return SUBREG_REG (target);
20388 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20391 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20392 tree exp, rtx target)
20395 tree arg0 = CALL_EXPR_ARG (exp, 0);
20396 tree arg1 = CALL_EXPR_ARG (exp, 1);
20397 tree arg2 = CALL_EXPR_ARG (exp, 2);
20398 rtx scratch0, scratch1;
20399 rtx op0 = expand_normal (arg0);
20400 rtx op1 = expand_normal (arg1);
20401 rtx op2 = expand_normal (arg2);
20402 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20404 tmode0 = insn_data[d->icode].operand[0].mode;
20405 tmode1 = insn_data[d->icode].operand[1].mode;
20406 modev2 = insn_data[d->icode].operand[2].mode;
20407 modev3 = insn_data[d->icode].operand[3].mode;
20408 modeimm = insn_data[d->icode].operand[4].mode;
20410 if (VECTOR_MODE_P (modev2))
20411 op0 = safe_vector_operand (op0, modev2);
20412 if (VECTOR_MODE_P (modev3))
20413 op1 = safe_vector_operand (op1, modev3);
20415 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20416 op0 = copy_to_mode_reg (modev2, op0);
20417 if ((optimize && !register_operand (op1, modev3))
20418 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20419 op1 = copy_to_mode_reg (modev3, op1);
20421 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20423 error ("the third argument must be a 8-bit immediate");
20427 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20429 if (optimize || !target
20430 || GET_MODE (target) != tmode0
20431 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20432 target = gen_reg_rtx (tmode0);
20434 scratch1 = gen_reg_rtx (tmode1);
20436 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20438 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20440 if (optimize || !target
20441 || GET_MODE (target) != tmode1
20442 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20443 target = gen_reg_rtx (tmode1);
20445 scratch0 = gen_reg_rtx (tmode0);
20447 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20451 gcc_assert (d->flag);
20453 scratch0 = gen_reg_rtx (tmode0);
20454 scratch1 = gen_reg_rtx (tmode1);
20456 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20466 target = gen_reg_rtx (SImode);
20467 emit_move_insn (target, const0_rtx);
20468 target = gen_rtx_SUBREG (QImode, target, 0);
20471 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20472 gen_rtx_fmt_ee (EQ, QImode,
20473 gen_rtx_REG ((enum machine_mode) d->flag,
20476 return SUBREG_REG (target);
20482 /* Return the integer constant in ARG. Constrain it to be in the range
20483 of the subparts of VEC_TYPE; issue an error if not. */
20486 get_element_number (tree vec_type, tree arg)
20488 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
20490 if (!host_integerp (arg, 1)
20491 || (elt = tree_low_cst (arg, 1), elt > max))
20493 error ("selector must be an integer constant in the range 0..%wi", max);
20500 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20501 ix86_expand_vector_init. We DO have language-level syntax for this, in
20502 the form of (type){ init-list }. Except that since we can't place emms
20503 instructions from inside the compiler, we can't allow the use of MMX
20504 registers unless the user explicitly asks for it. So we do *not* define
20505 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
20506 we have builtins invoked by mmintrin.h that gives us license to emit
20507 these sorts of instructions. */
20510 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
20512 enum machine_mode tmode = TYPE_MODE (type);
20513 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
20514 int i, n_elt = GET_MODE_NUNITS (tmode);
20515 rtvec v = rtvec_alloc (n_elt);
20517 gcc_assert (VECTOR_MODE_P (tmode));
20518 gcc_assert (call_expr_nargs (exp) == n_elt);
20520 for (i = 0; i < n_elt; ++i)
20522 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
20523 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
20526 if (!target || !register_operand (target, tmode))
20527 target = gen_reg_rtx (tmode);
20529 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
20533 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20534 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
20535 had a language-level syntax for referencing vector elements. */
20538 ix86_expand_vec_ext_builtin (tree exp, rtx target)
20540 enum machine_mode tmode, mode0;
20545 arg0 = CALL_EXPR_ARG (exp, 0);
20546 arg1 = CALL_EXPR_ARG (exp, 1);
20548 op0 = expand_normal (arg0);
20549 elt = get_element_number (TREE_TYPE (arg0), arg1);
20551 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20552 mode0 = TYPE_MODE (TREE_TYPE (arg0));
20553 gcc_assert (VECTOR_MODE_P (mode0));
20555 op0 = force_reg (mode0, op0);
20557 if (optimize || !target || !register_operand (target, tmode))
20558 target = gen_reg_rtx (tmode);
20560 ix86_expand_vector_extract (true, target, op0, elt);
20565 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20566 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
20567 a language-level syntax for referencing vector elements. */
20570 ix86_expand_vec_set_builtin (tree exp)
20572 enum machine_mode tmode, mode1;
20573 tree arg0, arg1, arg2;
20575 rtx op0, op1, target;
20577 arg0 = CALL_EXPR_ARG (exp, 0);
20578 arg1 = CALL_EXPR_ARG (exp, 1);
20579 arg2 = CALL_EXPR_ARG (exp, 2);
20581 tmode = TYPE_MODE (TREE_TYPE (arg0));
20582 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20583 gcc_assert (VECTOR_MODE_P (tmode));
20585 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
20586 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
20587 elt = get_element_number (TREE_TYPE (arg0), arg2);
20589 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
20590 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
20592 op0 = force_reg (tmode, op0);
20593 op1 = force_reg (mode1, op1);
20595 /* OP0 is the source of these builtin functions and shouldn't be
20596 modified. Create a copy, use it and return it as target. */
20597 target = gen_reg_rtx (tmode);
20598 emit_move_insn (target, op0);
20599 ix86_expand_vector_set (true, target, op1, elt);
20604 /* Expand an expression EXP that calls a built-in function,
20605 with result going to TARGET if that's convenient
20606 (and in mode MODE if that's convenient).
20607 SUBTARGET may be used as the target for computing one of EXP's operands.
20608 IGNORE is nonzero if the value is to be ignored. */
20611 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
20612 enum machine_mode mode ATTRIBUTE_UNUSED,
20613 int ignore ATTRIBUTE_UNUSED)
20615 const struct builtin_description *d;
20617 enum insn_code icode;
20618 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
20619 tree arg0, arg1, arg2, arg3;
20620 rtx op0, op1, op2, op3, pat;
20621 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
20622 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
20626 case IX86_BUILTIN_EMMS:
20627 emit_insn (gen_mmx_emms ());
20630 case IX86_BUILTIN_SFENCE:
20631 emit_insn (gen_sse_sfence ());
20634 case IX86_BUILTIN_MASKMOVQ:
20635 case IX86_BUILTIN_MASKMOVDQU:
20636 icode = (fcode == IX86_BUILTIN_MASKMOVQ
20637 ? CODE_FOR_mmx_maskmovq
20638 : CODE_FOR_sse2_maskmovdqu);
20639 /* Note the arg order is different from the operand order. */
20640 arg1 = CALL_EXPR_ARG (exp, 0);
20641 arg2 = CALL_EXPR_ARG (exp, 1);
20642 arg0 = CALL_EXPR_ARG (exp, 2);
20643 op0 = expand_normal (arg0);
20644 op1 = expand_normal (arg1);
20645 op2 = expand_normal (arg2);
20646 mode0 = insn_data[icode].operand[0].mode;
20647 mode1 = insn_data[icode].operand[1].mode;
20648 mode2 = insn_data[icode].operand[2].mode;
20650 op0 = force_reg (Pmode, op0);
20651 op0 = gen_rtx_MEM (mode1, op0);
20653 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
20654 op0 = copy_to_mode_reg (mode0, op0);
20655 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
20656 op1 = copy_to_mode_reg (mode1, op1);
20657 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
20658 op2 = copy_to_mode_reg (mode2, op2);
20659 pat = GEN_FCN (icode) (op0, op1, op2);
20665 case IX86_BUILTIN_RSQRTF:
20666 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
20668 case IX86_BUILTIN_SQRTSS:
20669 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
20670 case IX86_BUILTIN_RSQRTSS:
20671 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
20672 case IX86_BUILTIN_RCPSS:
20673 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
20675 case IX86_BUILTIN_LOADUPS:
20676 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
20678 case IX86_BUILTIN_STOREUPS:
20679 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
20681 case IX86_BUILTIN_LOADHPS:
20682 case IX86_BUILTIN_LOADLPS:
20683 case IX86_BUILTIN_LOADHPD:
20684 case IX86_BUILTIN_LOADLPD:
20685 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
20686 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
20687 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
20688 : CODE_FOR_sse2_loadlpd);
20689 arg0 = CALL_EXPR_ARG (exp, 0);
20690 arg1 = CALL_EXPR_ARG (exp, 1);
20691 op0 = expand_normal (arg0);
20692 op1 = expand_normal (arg1);
20693 tmode = insn_data[icode].operand[0].mode;
20694 mode0 = insn_data[icode].operand[1].mode;
20695 mode1 = insn_data[icode].operand[2].mode;
20697 op0 = force_reg (mode0, op0);
20698 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
20699 if (optimize || target == 0
20700 || GET_MODE (target) != tmode
20701 || !register_operand (target, tmode))
20702 target = gen_reg_rtx (tmode);
20703 pat = GEN_FCN (icode) (target, op0, op1);
20709 case IX86_BUILTIN_STOREHPS:
20710 case IX86_BUILTIN_STORELPS:
20711 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
20712 : CODE_FOR_sse_storelps);
20713 arg0 = CALL_EXPR_ARG (exp, 0);
20714 arg1 = CALL_EXPR_ARG (exp, 1);
20715 op0 = expand_normal (arg0);
20716 op1 = expand_normal (arg1);
20717 mode0 = insn_data[icode].operand[0].mode;
20718 mode1 = insn_data[icode].operand[1].mode;
20720 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20721 op1 = force_reg (mode1, op1);
20723 pat = GEN_FCN (icode) (op0, op1);
20729 case IX86_BUILTIN_MOVNTPS:
20730 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
20731 case IX86_BUILTIN_MOVNTQ:
20732 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
20734 case IX86_BUILTIN_LDMXCSR:
20735 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
20736 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20737 emit_move_insn (target, op0);
20738 emit_insn (gen_sse_ldmxcsr (target));
20741 case IX86_BUILTIN_STMXCSR:
20742 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20743 emit_insn (gen_sse_stmxcsr (target));
20744 return copy_to_mode_reg (SImode, target);
20746 case IX86_BUILTIN_SHUFPS:
20747 case IX86_BUILTIN_SHUFPD:
20748 icode = (fcode == IX86_BUILTIN_SHUFPS
20749 ? CODE_FOR_sse_shufps
20750 : CODE_FOR_sse2_shufpd);
20751 arg0 = CALL_EXPR_ARG (exp, 0);
20752 arg1 = CALL_EXPR_ARG (exp, 1);
20753 arg2 = CALL_EXPR_ARG (exp, 2);
20754 op0 = expand_normal (arg0);
20755 op1 = expand_normal (arg1);
20756 op2 = expand_normal (arg2);
20757 tmode = insn_data[icode].operand[0].mode;
20758 mode0 = insn_data[icode].operand[1].mode;
20759 mode1 = insn_data[icode].operand[2].mode;
20760 mode2 = insn_data[icode].operand[3].mode;
20762 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20763 op0 = copy_to_mode_reg (mode0, op0);
20764 if ((optimize && !register_operand (op1, mode1))
20765 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
20766 op1 = copy_to_mode_reg (mode1, op1);
20767 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
20769 /* @@@ better error message */
20770 error ("mask must be an immediate");
20771 return gen_reg_rtx (tmode);
20773 if (optimize || target == 0
20774 || GET_MODE (target) != tmode
20775 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20776 target = gen_reg_rtx (tmode);
20777 pat = GEN_FCN (icode) (target, op0, op1, op2);
20783 case IX86_BUILTIN_PSHUFW:
20784 case IX86_BUILTIN_PSHUFD:
20785 case IX86_BUILTIN_PSHUFHW:
20786 case IX86_BUILTIN_PSHUFLW:
20787 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
20788 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
20789 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
20790 : CODE_FOR_mmx_pshufw);
20791 arg0 = CALL_EXPR_ARG (exp, 0);
20792 arg1 = CALL_EXPR_ARG (exp, 1);
20793 op0 = expand_normal (arg0);
20794 op1 = expand_normal (arg1);
20795 tmode = insn_data[icode].operand[0].mode;
20796 mode1 = insn_data[icode].operand[1].mode;
20797 mode2 = insn_data[icode].operand[2].mode;
20799 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20800 op0 = copy_to_mode_reg (mode1, op0);
20801 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20803 /* @@@ better error message */
20804 error ("mask must be an immediate");
20808 || GET_MODE (target) != tmode
20809 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20810 target = gen_reg_rtx (tmode);
20811 pat = GEN_FCN (icode) (target, op0, op1);
20817 case IX86_BUILTIN_PSLLW:
20818 case IX86_BUILTIN_PSLLWI:
20819 icode = CODE_FOR_mmx_ashlv4hi3;
20821 case IX86_BUILTIN_PSLLD:
20822 case IX86_BUILTIN_PSLLDI:
20823 icode = CODE_FOR_mmx_ashlv2si3;
20825 case IX86_BUILTIN_PSLLQ:
20826 case IX86_BUILTIN_PSLLQI:
20827 icode = CODE_FOR_mmx_ashlv1di3;
20829 case IX86_BUILTIN_PSRAW:
20830 case IX86_BUILTIN_PSRAWI:
20831 icode = CODE_FOR_mmx_ashrv4hi3;
20833 case IX86_BUILTIN_PSRAD:
20834 case IX86_BUILTIN_PSRADI:
20835 icode = CODE_FOR_mmx_ashrv2si3;
20837 case IX86_BUILTIN_PSRLW:
20838 case IX86_BUILTIN_PSRLWI:
20839 icode = CODE_FOR_mmx_lshrv4hi3;
20841 case IX86_BUILTIN_PSRLD:
20842 case IX86_BUILTIN_PSRLDI:
20843 icode = CODE_FOR_mmx_lshrv2si3;
20845 case IX86_BUILTIN_PSRLQ:
20846 case IX86_BUILTIN_PSRLQI:
20847 icode = CODE_FOR_mmx_lshrv1di3;
20850 case IX86_BUILTIN_PSLLW128:
20851 case IX86_BUILTIN_PSLLWI128:
20852 icode = CODE_FOR_ashlv8hi3;
20854 case IX86_BUILTIN_PSLLD128:
20855 case IX86_BUILTIN_PSLLDI128:
20856 icode = CODE_FOR_ashlv4si3;
20858 case IX86_BUILTIN_PSLLQ128:
20859 case IX86_BUILTIN_PSLLQI128:
20860 icode = CODE_FOR_ashlv2di3;
20862 case IX86_BUILTIN_PSRAW128:
20863 case IX86_BUILTIN_PSRAWI128:
20864 icode = CODE_FOR_ashrv8hi3;
20866 case IX86_BUILTIN_PSRAD128:
20867 case IX86_BUILTIN_PSRADI128:
20868 icode = CODE_FOR_ashrv4si3;
20870 case IX86_BUILTIN_PSRLW128:
20871 case IX86_BUILTIN_PSRLWI128:
20872 icode = CODE_FOR_lshrv8hi3;
20874 case IX86_BUILTIN_PSRLD128:
20875 case IX86_BUILTIN_PSRLDI128:
20876 icode = CODE_FOR_lshrv4si3;
20878 case IX86_BUILTIN_PSRLQ128:
20879 case IX86_BUILTIN_PSRLQI128:
20880 icode = CODE_FOR_lshrv2di3;
20883 arg0 = CALL_EXPR_ARG (exp, 0);
20884 arg1 = CALL_EXPR_ARG (exp, 1);
20885 op0 = expand_normal (arg0);
20886 op1 = expand_normal (arg1);
20888 tmode = insn_data[icode].operand[0].mode;
20889 mode1 = insn_data[icode].operand[1].mode;
20891 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20892 op0 = copy_to_reg (op0);
20894 if (!CONST_INT_P (op1))
20895 op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
20897 if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
20898 op1 = copy_to_reg (op1);
20900 target = gen_reg_rtx (tmode);
20901 pat = GEN_FCN (icode) (target, op0, op1);
20907 case IX86_BUILTIN_PSLLDQI128:
20908 case IX86_BUILTIN_PSRLDQI128:
20909 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
20910 : CODE_FOR_sse2_lshrti3);
20911 arg0 = CALL_EXPR_ARG (exp, 0);
20912 arg1 = CALL_EXPR_ARG (exp, 1);
20913 op0 = expand_normal (arg0);
20914 op1 = expand_normal (arg1);
20915 tmode = insn_data[icode].operand[0].mode;
20916 mode1 = insn_data[icode].operand[1].mode;
20917 mode2 = insn_data[icode].operand[2].mode;
20919 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20921 op0 = copy_to_reg (op0);
20922 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
20924 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20926 error ("shift must be an immediate");
20929 target = gen_reg_rtx (V2DImode);
20930 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
20937 case IX86_BUILTIN_FEMMS:
20938 emit_insn (gen_mmx_femms ());
20941 case IX86_BUILTIN_PAVGUSB:
20942 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
20944 case IX86_BUILTIN_PF2ID:
20945 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
20947 case IX86_BUILTIN_PFACC:
20948 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
20950 case IX86_BUILTIN_PFADD:
20951 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
20953 case IX86_BUILTIN_PFCMPEQ:
20954 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
20956 case IX86_BUILTIN_PFCMPGE:
20957 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
20959 case IX86_BUILTIN_PFCMPGT:
20960 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
20962 case IX86_BUILTIN_PFMAX:
20963 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
20965 case IX86_BUILTIN_PFMIN:
20966 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
20968 case IX86_BUILTIN_PFMUL:
20969 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
20971 case IX86_BUILTIN_PFRCP:
20972 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
20974 case IX86_BUILTIN_PFRCPIT1:
20975 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
20977 case IX86_BUILTIN_PFRCPIT2:
20978 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
20980 case IX86_BUILTIN_PFRSQIT1:
20981 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
20983 case IX86_BUILTIN_PFRSQRT:
20984 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
20986 case IX86_BUILTIN_PFSUB:
20987 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
20989 case IX86_BUILTIN_PFSUBR:
20990 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
20992 case IX86_BUILTIN_PI2FD:
20993 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
20995 case IX86_BUILTIN_PMULHRW:
20996 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
20998 case IX86_BUILTIN_PF2IW:
20999 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
21001 case IX86_BUILTIN_PFNACC:
21002 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
21004 case IX86_BUILTIN_PFPNACC:
21005 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
21007 case IX86_BUILTIN_PI2FW:
21008 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
21010 case IX86_BUILTIN_PSWAPDSI:
21011 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
21013 case IX86_BUILTIN_PSWAPDSF:
21014 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
21016 case IX86_BUILTIN_SQRTSD:
21017 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
21018 case IX86_BUILTIN_LOADUPD:
21019 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
21020 case IX86_BUILTIN_STOREUPD:
21021 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
21023 case IX86_BUILTIN_MFENCE:
21024 emit_insn (gen_sse2_mfence ());
21026 case IX86_BUILTIN_LFENCE:
21027 emit_insn (gen_sse2_lfence ());
21030 case IX86_BUILTIN_CLFLUSH:
21031 arg0 = CALL_EXPR_ARG (exp, 0);
21032 op0 = expand_normal (arg0);
21033 icode = CODE_FOR_sse2_clflush;
21034 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21035 op0 = copy_to_mode_reg (Pmode, op0);
21037 emit_insn (gen_sse2_clflush (op0));
21040 case IX86_BUILTIN_MOVNTPD:
21041 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
21042 case IX86_BUILTIN_MOVNTDQ:
21043 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
21044 case IX86_BUILTIN_MOVNTI:
21045 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
21047 case IX86_BUILTIN_LOADDQU:
21048 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
21049 case IX86_BUILTIN_STOREDQU:
21050 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
21052 case IX86_BUILTIN_MONITOR:
21053 arg0 = CALL_EXPR_ARG (exp, 0);
21054 arg1 = CALL_EXPR_ARG (exp, 1);
21055 arg2 = CALL_EXPR_ARG (exp, 2);
21056 op0 = expand_normal (arg0);
21057 op1 = expand_normal (arg1);
21058 op2 = expand_normal (arg2);
21060 op0 = copy_to_mode_reg (Pmode, op0);
21062 op1 = copy_to_mode_reg (SImode, op1);
21064 op2 = copy_to_mode_reg (SImode, op2);
21066 emit_insn (gen_sse3_monitor (op0, op1, op2));
21068 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
21071 case IX86_BUILTIN_MWAIT:
21072 arg0 = CALL_EXPR_ARG (exp, 0);
21073 arg1 = CALL_EXPR_ARG (exp, 1);
21074 op0 = expand_normal (arg0);
21075 op1 = expand_normal (arg1);
21077 op0 = copy_to_mode_reg (SImode, op0);
21079 op1 = copy_to_mode_reg (SImode, op1);
21080 emit_insn (gen_sse3_mwait (op0, op1));
21083 case IX86_BUILTIN_LDDQU:
21084 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
21087 case IX86_BUILTIN_PALIGNR:
21088 case IX86_BUILTIN_PALIGNR128:
21089 if (fcode == IX86_BUILTIN_PALIGNR)
21091 icode = CODE_FOR_ssse3_palignrdi;
21096 icode = CODE_FOR_ssse3_palignrti;
21099 arg0 = CALL_EXPR_ARG (exp, 0);
21100 arg1 = CALL_EXPR_ARG (exp, 1);
21101 arg2 = CALL_EXPR_ARG (exp, 2);
21102 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21103 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21104 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21105 tmode = insn_data[icode].operand[0].mode;
21106 mode1 = insn_data[icode].operand[1].mode;
21107 mode2 = insn_data[icode].operand[2].mode;
21108 mode3 = insn_data[icode].operand[3].mode;
21110 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21112 op0 = copy_to_reg (op0);
21113 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
21115 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21117 op1 = copy_to_reg (op1);
21118 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
21120 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21122 error ("shift must be an immediate");
21125 target = gen_reg_rtx (mode);
21126 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
21133 case IX86_BUILTIN_MOVNTDQA:
21134 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
21137 case IX86_BUILTIN_MOVNTSD:
21138 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
21140 case IX86_BUILTIN_MOVNTSS:
21141 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
21143 case IX86_BUILTIN_INSERTQ:
21144 case IX86_BUILTIN_EXTRQ:
21145 icode = (fcode == IX86_BUILTIN_EXTRQ
21146 ? CODE_FOR_sse4a_extrq
21147 : CODE_FOR_sse4a_insertq);
21148 arg0 = CALL_EXPR_ARG (exp, 0);
21149 arg1 = CALL_EXPR_ARG (exp, 1);
21150 op0 = expand_normal (arg0);
21151 op1 = expand_normal (arg1);
21152 tmode = insn_data[icode].operand[0].mode;
21153 mode1 = insn_data[icode].operand[1].mode;
21154 mode2 = insn_data[icode].operand[2].mode;
21155 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21156 op0 = copy_to_mode_reg (mode1, op0);
21157 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21158 op1 = copy_to_mode_reg (mode2, op1);
21159 if (optimize || target == 0
21160 || GET_MODE (target) != tmode
21161 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21162 target = gen_reg_rtx (tmode);
21163 pat = GEN_FCN (icode) (target, op0, op1);
21169 case IX86_BUILTIN_EXTRQI:
21170 icode = CODE_FOR_sse4a_extrqi;
21171 arg0 = CALL_EXPR_ARG (exp, 0);
21172 arg1 = CALL_EXPR_ARG (exp, 1);
21173 arg2 = CALL_EXPR_ARG (exp, 2);
21174 op0 = expand_normal (arg0);
21175 op1 = expand_normal (arg1);
21176 op2 = expand_normal (arg2);
21177 tmode = insn_data[icode].operand[0].mode;
21178 mode1 = insn_data[icode].operand[1].mode;
21179 mode2 = insn_data[icode].operand[2].mode;
21180 mode3 = insn_data[icode].operand[3].mode;
21181 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21182 op0 = copy_to_mode_reg (mode1, op0);
21183 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21185 error ("index mask must be an immediate");
21186 return gen_reg_rtx (tmode);
21188 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21190 error ("length mask must be an immediate");
21191 return gen_reg_rtx (tmode);
21193 if (optimize || target == 0
21194 || GET_MODE (target) != tmode
21195 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21196 target = gen_reg_rtx (tmode);
21197 pat = GEN_FCN (icode) (target, op0, op1, op2);
21203 case IX86_BUILTIN_INSERTQI:
21204 icode = CODE_FOR_sse4a_insertqi;
21205 arg0 = CALL_EXPR_ARG (exp, 0);
21206 arg1 = CALL_EXPR_ARG (exp, 1);
21207 arg2 = CALL_EXPR_ARG (exp, 2);
21208 arg3 = CALL_EXPR_ARG (exp, 3);
21209 op0 = expand_normal (arg0);
21210 op1 = expand_normal (arg1);
21211 op2 = expand_normal (arg2);
21212 op3 = expand_normal (arg3);
21213 tmode = insn_data[icode].operand[0].mode;
21214 mode1 = insn_data[icode].operand[1].mode;
21215 mode2 = insn_data[icode].operand[2].mode;
21216 mode3 = insn_data[icode].operand[3].mode;
21217 mode4 = insn_data[icode].operand[4].mode;
21219 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21220 op0 = copy_to_mode_reg (mode1, op0);
21222 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21223 op1 = copy_to_mode_reg (mode2, op1);
21225 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21227 error ("index mask must be an immediate");
21228 return gen_reg_rtx (tmode);
21230 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
21232 error ("length mask must be an immediate");
21233 return gen_reg_rtx (tmode);
21235 if (optimize || target == 0
21236 || GET_MODE (target) != tmode
21237 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21238 target = gen_reg_rtx (tmode);
21239 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
21245 case IX86_BUILTIN_VEC_INIT_V2SI:
21246 case IX86_BUILTIN_VEC_INIT_V4HI:
21247 case IX86_BUILTIN_VEC_INIT_V8QI:
21248 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21250 case IX86_BUILTIN_VEC_EXT_V2DF:
21251 case IX86_BUILTIN_VEC_EXT_V2DI:
21252 case IX86_BUILTIN_VEC_EXT_V4SF:
21253 case IX86_BUILTIN_VEC_EXT_V4SI:
21254 case IX86_BUILTIN_VEC_EXT_V8HI:
21255 case IX86_BUILTIN_VEC_EXT_V2SI:
21256 case IX86_BUILTIN_VEC_EXT_V4HI:
21257 case IX86_BUILTIN_VEC_EXT_V16QI:
21258 return ix86_expand_vec_ext_builtin (exp, target);
21260 case IX86_BUILTIN_VEC_SET_V2DI:
21261 case IX86_BUILTIN_VEC_SET_V4SF:
21262 case IX86_BUILTIN_VEC_SET_V4SI:
21263 case IX86_BUILTIN_VEC_SET_V8HI:
21264 case IX86_BUILTIN_VEC_SET_V4HI:
21265 case IX86_BUILTIN_VEC_SET_V16QI:
21266 return ix86_expand_vec_set_builtin (exp);
21268 case IX86_BUILTIN_INFQ:
21270 REAL_VALUE_TYPE inf;
21274 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21276 tmp = validize_mem (force_const_mem (mode, tmp));
21279 target = gen_reg_rtx (mode);
21281 emit_move_insn (target, tmp);
21285 case IX86_BUILTIN_FABSQ:
21286 return ix86_expand_unop_builtin (CODE_FOR_abstf2, exp, target, 0);
21288 case IX86_BUILTIN_COPYSIGNQ:
21289 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
21295 for (i = 0, d = bdesc_sse_3arg;
21296 i < ARRAY_SIZE (bdesc_sse_3arg);
21298 if (d->code == fcode)
21299 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
21302 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21303 if (d->code == fcode)
21305 /* Compares are treated specially. */
21306 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
21307 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
21308 || d->icode == CODE_FOR_sse2_maskcmpv2df3
21309 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
21310 return ix86_expand_sse_compare (d, exp, target);
21312 return ix86_expand_binop_builtin (d->icode, exp, target);
21315 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
21316 if (d->code == fcode)
21317 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
21319 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21320 if (d->code == fcode)
21321 return ix86_expand_sse_comi (d, exp, target);
21323 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
21324 if (d->code == fcode)
21325 return ix86_expand_sse_ptest (d, exp, target);
21327 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
21328 if (d->code == fcode)
21329 return ix86_expand_crc32 (d->icode, exp, target);
21331 for (i = 0, d = bdesc_pcmpestr;
21332 i < ARRAY_SIZE (bdesc_pcmpestr);
21334 if (d->code == fcode)
21335 return ix86_expand_sse_pcmpestr (d, exp, target);
21337 for (i = 0, d = bdesc_pcmpistr;
21338 i < ARRAY_SIZE (bdesc_pcmpistr);
21340 if (d->code == fcode)
21341 return ix86_expand_sse_pcmpistr (d, exp, target);
21343 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21344 if (d->code == fcode)
21345 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21346 (enum multi_arg_type)d->flag,
21349 gcc_unreachable ();
21352 /* Returns a function decl for a vectorized version of the builtin function
21353 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21354 if it is not available. */
21357 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21360 enum machine_mode in_mode, out_mode;
21363 if (TREE_CODE (type_out) != VECTOR_TYPE
21364 || TREE_CODE (type_in) != VECTOR_TYPE)
21367 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21368 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21369 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21370 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21374 case BUILT_IN_SQRT:
21375 if (out_mode == DFmode && out_n == 2
21376 && in_mode == DFmode && in_n == 2)
21377 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21380 case BUILT_IN_SQRTF:
21381 if (out_mode == SFmode && out_n == 4
21382 && in_mode == SFmode && in_n == 4)
21383 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21386 case BUILT_IN_LRINT:
21387 if (out_mode == SImode && out_n == 4
21388 && in_mode == DFmode && in_n == 2)
21389 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21392 case BUILT_IN_LRINTF:
21393 if (out_mode == SImode && out_n == 4
21394 && in_mode == SFmode && in_n == 4)
21395 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21402 /* Dispatch to a handler for a vectorization library. */
21403 if (ix86_veclib_handler)
21404 return (*ix86_veclib_handler)(fn, type_out, type_in);
21409 /* Handler for an ACML-style interface to a library with vectorized
21413 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21415 char name[20] = "__vr.._";
21416 tree fntype, new_fndecl, args;
21419 enum machine_mode el_mode, in_mode;
21422 /* The ACML is 64bits only and suitable for unsafe math only as
21423 it does not correctly support parts of IEEE with the required
21424 precision such as denormals. */
21426 || !flag_unsafe_math_optimizations)
21429 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21430 n = TYPE_VECTOR_SUBPARTS (type_out);
21431 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21432 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21433 if (el_mode != in_mode
21443 case BUILT_IN_LOG2:
21444 case BUILT_IN_LOG10:
21447 if (el_mode != DFmode
21452 case BUILT_IN_SINF:
21453 case BUILT_IN_COSF:
21454 case BUILT_IN_EXPF:
21455 case BUILT_IN_POWF:
21456 case BUILT_IN_LOGF:
21457 case BUILT_IN_LOG2F:
21458 case BUILT_IN_LOG10F:
21461 if (el_mode != SFmode
21470 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21471 sprintf (name + 7, "%s", bname+10);
21474 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21475 args = TREE_CHAIN (args))
21479 fntype = build_function_type_list (type_out, type_in, NULL);
21481 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21483 /* Build a function declaration for the vectorized function. */
21484 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21485 TREE_PUBLIC (new_fndecl) = 1;
21486 DECL_EXTERNAL (new_fndecl) = 1;
21487 DECL_IS_NOVOPS (new_fndecl) = 1;
21488 TREE_READONLY (new_fndecl) = 1;
21494 /* Returns a decl of a function that implements conversion of the
21495 input vector of type TYPE, or NULL_TREE if it is not available. */
21498 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21500 if (TREE_CODE (type) != VECTOR_TYPE)
21506 switch (TYPE_MODE (type))
21509 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21514 case FIX_TRUNC_EXPR:
21515 switch (TYPE_MODE (type))
21518 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21528 /* Returns a code for a target-specific builtin that implements
21529 reciprocal of the function, or NULL_TREE if not available. */
21532 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21533 bool sqrt ATTRIBUTE_UNUSED)
21535 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21536 && flag_finite_math_only && !flag_trapping_math
21537 && flag_unsafe_math_optimizations))
21541 /* Machine dependent builtins. */
21544 /* Vectorized version of sqrt to rsqrt conversion. */
21545 case IX86_BUILTIN_SQRTPS_NR:
21546 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21552 /* Normal builtins. */
21555 /* Sqrt to rsqrt conversion. */
21556 case BUILT_IN_SQRTF:
21557 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21564 /* Store OPERAND to the memory after reload is completed. This means
21565 that we can't easily use assign_stack_local. */
21567 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21571 gcc_assert (reload_completed);
21572 if (TARGET_RED_ZONE)
21574 result = gen_rtx_MEM (mode,
21575 gen_rtx_PLUS (Pmode,
21577 GEN_INT (-RED_ZONE_SIZE)));
21578 emit_move_insn (result, operand);
21580 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21586 operand = gen_lowpart (DImode, operand);
21590 gen_rtx_SET (VOIDmode,
21591 gen_rtx_MEM (DImode,
21592 gen_rtx_PRE_DEC (DImode,
21593 stack_pointer_rtx)),
21597 gcc_unreachable ();
21599 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21608 split_di (&operand, 1, operands, operands + 1);
21610 gen_rtx_SET (VOIDmode,
21611 gen_rtx_MEM (SImode,
21612 gen_rtx_PRE_DEC (Pmode,
21613 stack_pointer_rtx)),
21616 gen_rtx_SET (VOIDmode,
21617 gen_rtx_MEM (SImode,
21618 gen_rtx_PRE_DEC (Pmode,
21619 stack_pointer_rtx)),
21624 /* Store HImodes as SImodes. */
21625 operand = gen_lowpart (SImode, operand);
21629 gen_rtx_SET (VOIDmode,
21630 gen_rtx_MEM (GET_MODE (operand),
21631 gen_rtx_PRE_DEC (SImode,
21632 stack_pointer_rtx)),
21636 gcc_unreachable ();
21638 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21643 /* Free operand from the memory. */
21645 ix86_free_from_memory (enum machine_mode mode)
21647 if (!TARGET_RED_ZONE)
21651 if (mode == DImode || TARGET_64BIT)
21655 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21656 to pop or add instruction if registers are available. */
21657 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21658 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21663 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21664 QImode must go into class Q_REGS.
21665 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21666 movdf to do mem-to-mem moves through integer regs. */
21668 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
21670 enum machine_mode mode = GET_MODE (x);
21672 /* We're only allowed to return a subclass of CLASS. Many of the
21673 following checks fail for NO_REGS, so eliminate that early. */
21674 if (regclass == NO_REGS)
21677 /* All classes can load zeros. */
21678 if (x == CONST0_RTX (mode))
21681 /* Force constants into memory if we are loading a (nonzero) constant into
21682 an MMX or SSE register. This is because there are no MMX/SSE instructions
21683 to load from a constant. */
21685 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
21688 /* Prefer SSE regs only, if we can use them for math. */
21689 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
21690 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
21692 /* Floating-point constants need more complex checks. */
21693 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
21695 /* General regs can load everything. */
21696 if (reg_class_subset_p (regclass, GENERAL_REGS))
21699 /* Floats can load 0 and 1 plus some others. Note that we eliminated
21700 zero above. We only want to wind up preferring 80387 registers if
21701 we plan on doing computation with them. */
21703 && standard_80387_constant_p (x))
21705 /* Limit class to non-sse. */
21706 if (regclass == FLOAT_SSE_REGS)
21708 if (regclass == FP_TOP_SSE_REGS)
21710 if (regclass == FP_SECOND_SSE_REGS)
21711 return FP_SECOND_REG;
21712 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
21719 /* Generally when we see PLUS here, it's the function invariant
21720 (plus soft-fp const_int). Which can only be computed into general
21722 if (GET_CODE (x) == PLUS)
21723 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
21725 /* QImode constants are easy to load, but non-constant QImode data
21726 must go into Q_REGS. */
21727 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
21729 if (reg_class_subset_p (regclass, Q_REGS))
21731 if (reg_class_subset_p (Q_REGS, regclass))
21739 /* Discourage putting floating-point values in SSE registers unless
21740 SSE math is being used, and likewise for the 387 registers. */
21742 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
21744 enum machine_mode mode = GET_MODE (x);
21746 /* Restrict the output reload class to the register bank that we are doing
21747 math on. If we would like not to return a subset of CLASS, reject this
21748 alternative: if reload cannot do this, it will still use its choice. */
21749 mode = GET_MODE (x);
21750 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
21751 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
21753 if (X87_FLOAT_MODE_P (mode))
21755 if (regclass == FP_TOP_SSE_REGS)
21757 else if (regclass == FP_SECOND_SSE_REGS)
21758 return FP_SECOND_REG;
21760 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
21766 /* If we are copying between general and FP registers, we need a memory
21767 location. The same is true for SSE and MMX registers.
21769 To optimize register_move_cost performance, allow inline variant.
21771 The macro can't work reliably when one of the CLASSES is class containing
21772 registers from multiple units (SSE, MMX, integer). We avoid this by never
21773 combining those units in single alternative in the machine description.
21774 Ensure that this constraint holds to avoid unexpected surprises.
21776 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
21777 enforce these sanity checks. */
21780 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21781 enum machine_mode mode, int strict)
21783 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
21784 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
21785 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
21786 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
21787 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
21788 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
21790 gcc_assert (!strict);
21794 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
21797 /* ??? This is a lie. We do have moves between mmx/general, and for
21798 mmx/sse2. But by saying we need secondary memory we discourage the
21799 register allocator from using the mmx registers unless needed. */
21800 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
21803 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
21805 /* SSE1 doesn't have any direct moves from other classes. */
21809 /* If the target says that inter-unit moves are more expensive
21810 than moving through memory, then don't generate them. */
21811 if (!TARGET_INTER_UNIT_MOVES)
21814 /* Between SSE and general, we have moves no larger than word size. */
21815 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
21823 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21824 enum machine_mode mode, int strict)
21826 return inline_secondary_memory_needed (class1, class2, mode, strict);
21829 /* Return true if the registers in CLASS cannot represent the change from
21830 modes FROM to TO. */
21833 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
21834 enum reg_class regclass)
21839 /* x87 registers can't do subreg at all, as all values are reformatted
21840 to extended precision. */
21841 if (MAYBE_FLOAT_CLASS_P (regclass))
21844 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
21846 /* Vector registers do not support QI or HImode loads. If we don't
21847 disallow a change to these modes, reload will assume it's ok to
21848 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
21849 the vec_dupv4hi pattern. */
21850 if (GET_MODE_SIZE (from) < 4)
21853 /* Vector registers do not support subreg with nonzero offsets, which
21854 are otherwise valid for integer registers. Since we can't see
21855 whether we have a nonzero offset from here, prohibit all
21856 nonparadoxical subregs changing size. */
21857 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
21864 /* Return the cost of moving data of mode M between a
21865 register and memory. A value of 2 is the default; this cost is
21866 relative to those in `REGISTER_MOVE_COST'.
21868 This function is used extensively by register_move_cost that is used to
21869 build tables at startup. Make it inline in this case.
21870 When IN is 2, return maximum of in and out move cost.
21872 If moving between registers and memory is more expensive than
21873 between two registers, you should define this macro to express the
21876 Model also increased moving costs of QImode registers in non
21880 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
21884 if (FLOAT_CLASS_P (regclass))
21902 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
21903 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
21905 if (SSE_CLASS_P (regclass))
21908 switch (GET_MODE_SIZE (mode))
21923 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
21924 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
21926 if (MMX_CLASS_P (regclass))
21929 switch (GET_MODE_SIZE (mode))
21941 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
21942 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
21944 switch (GET_MODE_SIZE (mode))
21947 if (Q_CLASS_P (regclass) || TARGET_64BIT)
21950 return ix86_cost->int_store[0];
21951 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
21952 cost = ix86_cost->movzbl_load;
21954 cost = ix86_cost->int_load[0];
21956 return MAX (cost, ix86_cost->int_store[0]);
21962 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
21964 return ix86_cost->movzbl_load;
21966 return ix86_cost->int_store[0] + 4;
21971 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
21972 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
21974 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
21975 if (mode == TFmode)
21978 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
21980 cost = ix86_cost->int_load[2];
21982 cost = ix86_cost->int_store[2];
21983 return (cost * (((int) GET_MODE_SIZE (mode)
21984 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
21989 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
21991 return inline_memory_move_cost (mode, regclass, in);
21995 /* Return the cost of moving data from a register in class CLASS1 to
21996 one in class CLASS2.
21998 It is not required that the cost always equal 2 when FROM is the same as TO;
21999 on some machines it is expensive to move between registers if they are not
22000 general registers. */
22003 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22004 enum reg_class class2)
22006 /* In case we require secondary memory, compute cost of the store followed
22007 by load. In order to avoid bad register allocation choices, we need
22008 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22010 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22014 cost += inline_memory_move_cost (mode, class1, 2);
22015 cost += inline_memory_move_cost (mode, class2, 2);
22017 /* In case of copying from general_purpose_register we may emit multiple
22018 stores followed by single load causing memory size mismatch stall.
22019 Count this as arbitrarily high cost of 20. */
22020 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22023 /* In the case of FP/MMX moves, the registers actually overlap, and we
22024 have to switch modes in order to treat them differently. */
22025 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22026 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22032 /* Moves between SSE/MMX and integer unit are expensive. */
22033 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22034 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22036 /* ??? By keeping returned value relatively high, we limit the number
22037 of moves between integer and MMX/SSE registers for all targets.
22038 Additionally, high value prevents problem with x86_modes_tieable_p(),
22039 where integer modes in MMX/SSE registers are not tieable
22040 because of missing QImode and HImode moves to, from or between
22041 MMX/SSE registers. */
22042 return MAX (8, ix86_cost->mmxsse_to_integer);
22044 if (MAYBE_FLOAT_CLASS_P (class1))
22045 return ix86_cost->fp_move;
22046 if (MAYBE_SSE_CLASS_P (class1))
22047 return ix86_cost->sse_move;
22048 if (MAYBE_MMX_CLASS_P (class1))
22049 return ix86_cost->mmx_move;
22053 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22056 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22058 /* Flags and only flags can only hold CCmode values. */
22059 if (CC_REGNO_P (regno))
22060 return GET_MODE_CLASS (mode) == MODE_CC;
22061 if (GET_MODE_CLASS (mode) == MODE_CC
22062 || GET_MODE_CLASS (mode) == MODE_RANDOM
22063 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22065 if (FP_REGNO_P (regno))
22066 return VALID_FP_MODE_P (mode);
22067 if (SSE_REGNO_P (regno))
22069 /* We implement the move patterns for all vector modes into and
22070 out of SSE registers, even when no operation instructions
22072 return (VALID_SSE_REG_MODE (mode)
22073 || VALID_SSE2_REG_MODE (mode)
22074 || VALID_MMX_REG_MODE (mode)
22075 || VALID_MMX_REG_MODE_3DNOW (mode));
22077 if (MMX_REGNO_P (regno))
22079 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22080 so if the register is available at all, then we can move data of
22081 the given mode into or out of it. */
22082 return (VALID_MMX_REG_MODE (mode)
22083 || VALID_MMX_REG_MODE_3DNOW (mode));
22086 if (mode == QImode)
22088 /* Take care for QImode values - they can be in non-QI regs,
22089 but then they do cause partial register stalls. */
22090 if (regno < 4 || TARGET_64BIT)
22092 if (!TARGET_PARTIAL_REG_STALL)
22094 return reload_in_progress || reload_completed;
22096 /* We handle both integer and floats in the general purpose registers. */
22097 else if (VALID_INT_MODE_P (mode))
22099 else if (VALID_FP_MODE_P (mode))
22101 else if (VALID_DFP_MODE_P (mode))
22103 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22104 on to use that value in smaller contexts, this can easily force a
22105 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22106 supporting DImode, allow it. */
22107 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22113 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22114 tieable integer mode. */
22117 ix86_tieable_integer_mode_p (enum machine_mode mode)
22126 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22129 return TARGET_64BIT;
22136 /* Return true if MODE1 is accessible in a register that can hold MODE2
22137 without copying. That is, all register classes that can hold MODE2
22138 can also hold MODE1. */
22141 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22143 if (mode1 == mode2)
22146 if (ix86_tieable_integer_mode_p (mode1)
22147 && ix86_tieable_integer_mode_p (mode2))
22150 /* MODE2 being XFmode implies fp stack or general regs, which means we
22151 can tie any smaller floating point modes to it. Note that we do not
22152 tie this with TFmode. */
22153 if (mode2 == XFmode)
22154 return mode1 == SFmode || mode1 == DFmode;
22156 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22157 that we can tie it with SFmode. */
22158 if (mode2 == DFmode)
22159 return mode1 == SFmode;
22161 /* If MODE2 is only appropriate for an SSE register, then tie with
22162 any other mode acceptable to SSE registers. */
22163 if (GET_MODE_SIZE (mode2) == 16
22164 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22165 return (GET_MODE_SIZE (mode1) == 16
22166 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22168 /* If MODE2 is appropriate for an MMX register, then tie
22169 with any other mode acceptable to MMX registers. */
22170 if (GET_MODE_SIZE (mode2) == 8
22171 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22172 return (GET_MODE_SIZE (mode1) == 8
22173 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22178 /* Compute a (partial) cost for rtx X. Return true if the complete
22179 cost has been computed, and false if subexpressions should be
22180 scanned. In either case, *TOTAL contains the cost result. */
22183 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22185 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22186 enum machine_mode mode = GET_MODE (x);
22194 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22196 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22198 else if (flag_pic && SYMBOLIC_CONST (x)
22200 || (!GET_CODE (x) != LABEL_REF
22201 && (GET_CODE (x) != SYMBOL_REF
22202 || !SYMBOL_REF_LOCAL_P (x)))))
22209 if (mode == VOIDmode)
22212 switch (standard_80387_constant_p (x))
22217 default: /* Other constants */
22222 /* Start with (MEM (SYMBOL_REF)), since that's where
22223 it'll probably end up. Add a penalty for size. */
22224 *total = (COSTS_N_INSNS (1)
22225 + (flag_pic != 0 && !TARGET_64BIT)
22226 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22232 /* The zero extensions is often completely free on x86_64, so make
22233 it as cheap as possible. */
22234 if (TARGET_64BIT && mode == DImode
22235 && GET_MODE (XEXP (x, 0)) == SImode)
22237 else if (TARGET_ZERO_EXTEND_WITH_AND)
22238 *total = ix86_cost->add;
22240 *total = ix86_cost->movzx;
22244 *total = ix86_cost->movsx;
22248 if (CONST_INT_P (XEXP (x, 1))
22249 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22251 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22254 *total = ix86_cost->add;
22257 if ((value == 2 || value == 3)
22258 && ix86_cost->lea <= ix86_cost->shift_const)
22260 *total = ix86_cost->lea;
22270 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22272 if (CONST_INT_P (XEXP (x, 1)))
22274 if (INTVAL (XEXP (x, 1)) > 32)
22275 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22277 *total = ix86_cost->shift_const * 2;
22281 if (GET_CODE (XEXP (x, 1)) == AND)
22282 *total = ix86_cost->shift_var * 2;
22284 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22289 if (CONST_INT_P (XEXP (x, 1)))
22290 *total = ix86_cost->shift_const;
22292 *total = ix86_cost->shift_var;
22297 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22299 /* ??? SSE scalar cost should be used here. */
22300 *total = ix86_cost->fmul;
22303 else if (X87_FLOAT_MODE_P (mode))
22305 *total = ix86_cost->fmul;
22308 else if (FLOAT_MODE_P (mode))
22310 /* ??? SSE vector cost should be used here. */
22311 *total = ix86_cost->fmul;
22316 rtx op0 = XEXP (x, 0);
22317 rtx op1 = XEXP (x, 1);
22319 if (CONST_INT_P (XEXP (x, 1)))
22321 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22322 for (nbits = 0; value != 0; value &= value - 1)
22326 /* This is arbitrary. */
22329 /* Compute costs correctly for widening multiplication. */
22330 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22331 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22332 == GET_MODE_SIZE (mode))
22334 int is_mulwiden = 0;
22335 enum machine_mode inner_mode = GET_MODE (op0);
22337 if (GET_CODE (op0) == GET_CODE (op1))
22338 is_mulwiden = 1, op1 = XEXP (op1, 0);
22339 else if (CONST_INT_P (op1))
22341 if (GET_CODE (op0) == SIGN_EXTEND)
22342 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22345 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22349 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22352 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22353 + nbits * ix86_cost->mult_bit
22354 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22363 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22364 /* ??? SSE cost should be used here. */
22365 *total = ix86_cost->fdiv;
22366 else if (X87_FLOAT_MODE_P (mode))
22367 *total = ix86_cost->fdiv;
22368 else if (FLOAT_MODE_P (mode))
22369 /* ??? SSE vector cost should be used here. */
22370 *total = ix86_cost->fdiv;
22372 *total = ix86_cost->divide[MODE_INDEX (mode)];
22376 if (GET_MODE_CLASS (mode) == MODE_INT
22377 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22379 if (GET_CODE (XEXP (x, 0)) == PLUS
22380 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22381 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22382 && CONSTANT_P (XEXP (x, 1)))
22384 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22385 if (val == 2 || val == 4 || val == 8)
22387 *total = ix86_cost->lea;
22388 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22389 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22391 *total += rtx_cost (XEXP (x, 1), outer_code);
22395 else if (GET_CODE (XEXP (x, 0)) == MULT
22396 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22398 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22399 if (val == 2 || val == 4 || val == 8)
22401 *total = ix86_cost->lea;
22402 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22403 *total += rtx_cost (XEXP (x, 1), outer_code);
22407 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22409 *total = ix86_cost->lea;
22410 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22411 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22412 *total += rtx_cost (XEXP (x, 1), outer_code);
22419 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22421 /* ??? SSE cost should be used here. */
22422 *total = ix86_cost->fadd;
22425 else if (X87_FLOAT_MODE_P (mode))
22427 *total = ix86_cost->fadd;
22430 else if (FLOAT_MODE_P (mode))
22432 /* ??? SSE vector cost should be used here. */
22433 *total = ix86_cost->fadd;
22441 if (!TARGET_64BIT && mode == DImode)
22443 *total = (ix86_cost->add * 2
22444 + (rtx_cost (XEXP (x, 0), outer_code)
22445 << (GET_MODE (XEXP (x, 0)) != DImode))
22446 + (rtx_cost (XEXP (x, 1), outer_code)
22447 << (GET_MODE (XEXP (x, 1)) != DImode)));
22453 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22455 /* ??? SSE cost should be used here. */
22456 *total = ix86_cost->fchs;
22459 else if (X87_FLOAT_MODE_P (mode))
22461 *total = ix86_cost->fchs;
22464 else if (FLOAT_MODE_P (mode))
22466 /* ??? SSE vector cost should be used here. */
22467 *total = ix86_cost->fchs;
22473 if (!TARGET_64BIT && mode == DImode)
22474 *total = ix86_cost->add * 2;
22476 *total = ix86_cost->add;
22480 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22481 && XEXP (XEXP (x, 0), 1) == const1_rtx
22482 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22483 && XEXP (x, 1) == const0_rtx)
22485 /* This kind of construct is implemented using test[bwl].
22486 Treat it as if we had an AND. */
22487 *total = (ix86_cost->add
22488 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22489 + rtx_cost (const1_rtx, outer_code));
22495 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22500 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22501 /* ??? SSE cost should be used here. */
22502 *total = ix86_cost->fabs;
22503 else if (X87_FLOAT_MODE_P (mode))
22504 *total = ix86_cost->fabs;
22505 else if (FLOAT_MODE_P (mode))
22506 /* ??? SSE vector cost should be used here. */
22507 *total = ix86_cost->fabs;
22511 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22512 /* ??? SSE cost should be used here. */
22513 *total = ix86_cost->fsqrt;
22514 else if (X87_FLOAT_MODE_P (mode))
22515 *total = ix86_cost->fsqrt;
22516 else if (FLOAT_MODE_P (mode))
22517 /* ??? SSE vector cost should be used here. */
22518 *total = ix86_cost->fsqrt;
22522 if (XINT (x, 1) == UNSPEC_TP)
22533 static int current_machopic_label_num;
22535 /* Given a symbol name and its associated stub, write out the
22536 definition of the stub. */
22539 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22541 unsigned int length;
22542 char *binder_name, *symbol_name, lazy_ptr_name[32];
22543 int label = ++current_machopic_label_num;
22545 /* For 64-bit we shouldn't get here. */
22546 gcc_assert (!TARGET_64BIT);
22548 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22549 symb = (*targetm.strip_name_encoding) (symb);
22551 length = strlen (stub);
22552 binder_name = alloca (length + 32);
22553 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22555 length = strlen (symb);
22556 symbol_name = alloca (length + 32);
22557 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22559 sprintf (lazy_ptr_name, "L%d$lz", label);
22562 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22564 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22566 fprintf (file, "%s:\n", stub);
22567 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22571 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22572 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22573 fprintf (file, "\tjmp\t*%%edx\n");
22576 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22578 fprintf (file, "%s:\n", binder_name);
22582 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22583 fprintf (file, "\tpushl\t%%eax\n");
22586 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22588 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22590 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22591 fprintf (file, "%s:\n", lazy_ptr_name);
22592 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22593 fprintf (file, "\t.long %s\n", binder_name);
22597 darwin_x86_file_end (void)
22599 darwin_file_end ();
22602 #endif /* TARGET_MACHO */
22604 /* Order the registers for register allocator. */
22607 x86_order_regs_for_local_alloc (void)
22612 /* First allocate the local general purpose registers. */
22613 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22614 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22615 reg_alloc_order [pos++] = i;
22617 /* Global general purpose registers. */
22618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22619 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22620 reg_alloc_order [pos++] = i;
22622 /* x87 registers come first in case we are doing FP math
22624 if (!TARGET_SSE_MATH)
22625 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22626 reg_alloc_order [pos++] = i;
22628 /* SSE registers. */
22629 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22630 reg_alloc_order [pos++] = i;
22631 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22632 reg_alloc_order [pos++] = i;
22634 /* x87 registers. */
22635 if (TARGET_SSE_MATH)
22636 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22637 reg_alloc_order [pos++] = i;
22639 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22640 reg_alloc_order [pos++] = i;
22642 /* Initialize the rest of array as we do not allocate some registers
22644 while (pos < FIRST_PSEUDO_REGISTER)
22645 reg_alloc_order [pos++] = 0;
22648 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22649 struct attribute_spec.handler. */
22651 ix86_handle_struct_attribute (tree *node, tree name,
22652 tree args ATTRIBUTE_UNUSED,
22653 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22656 if (DECL_P (*node))
22658 if (TREE_CODE (*node) == TYPE_DECL)
22659 type = &TREE_TYPE (*node);
22664 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22665 || TREE_CODE (*type) == UNION_TYPE)))
22667 warning (OPT_Wattributes, "%qs attribute ignored",
22668 IDENTIFIER_POINTER (name));
22669 *no_add_attrs = true;
22672 else if ((is_attribute_p ("ms_struct", name)
22673 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
22674 || ((is_attribute_p ("gcc_struct", name)
22675 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
22677 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
22678 IDENTIFIER_POINTER (name));
22679 *no_add_attrs = true;
22686 ix86_ms_bitfield_layout_p (const_tree record_type)
22688 return (TARGET_MS_BITFIELD_LAYOUT &&
22689 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
22690 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
22693 /* Returns an expression indicating where the this parameter is
22694 located on entry to the FUNCTION. */
22697 x86_this_parameter (tree function)
22699 tree type = TREE_TYPE (function);
22700 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
22705 const int *parm_regs;
22707 if (TARGET_64BIT_MS_ABI)
22708 parm_regs = x86_64_ms_abi_int_parameter_registers;
22710 parm_regs = x86_64_int_parameter_registers;
22711 return gen_rtx_REG (DImode, parm_regs[aggr]);
22714 nregs = ix86_function_regparm (type, function);
22716 if (nregs > 0 && !stdarg_p (type))
22720 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
22721 regno = aggr ? DX_REG : CX_REG;
22729 return gen_rtx_MEM (SImode,
22730 plus_constant (stack_pointer_rtx, 4));
22733 return gen_rtx_REG (SImode, regno);
22736 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
22739 /* Determine whether x86_output_mi_thunk can succeed. */
22742 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
22743 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
22744 HOST_WIDE_INT vcall_offset, const_tree function)
22746 /* 64-bit can handle anything. */
22750 /* For 32-bit, everything's fine if we have one free register. */
22751 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
22754 /* Need a free register for vcall_offset. */
22758 /* Need a free register for GOT references. */
22759 if (flag_pic && !(*targetm.binds_local_p) (function))
22762 /* Otherwise ok. */
22766 /* Output the assembler code for a thunk function. THUNK_DECL is the
22767 declaration for the thunk function itself, FUNCTION is the decl for
22768 the target function. DELTA is an immediate constant offset to be
22769 added to THIS. If VCALL_OFFSET is nonzero, the word at
22770 *(*this + vcall_offset) should be added to THIS. */
22773 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
22774 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
22775 HOST_WIDE_INT vcall_offset, tree function)
22778 rtx this_param = x86_this_parameter (function);
22781 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
22782 pull it in now and let DELTA benefit. */
22783 if (REG_P (this_param))
22784 this_reg = this_param;
22785 else if (vcall_offset)
22787 /* Put the this parameter into %eax. */
22788 xops[0] = this_param;
22789 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
22790 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22793 this_reg = NULL_RTX;
22795 /* Adjust the this parameter by a fixed constant. */
22798 xops[0] = GEN_INT (delta);
22799 xops[1] = this_reg ? this_reg : this_param;
22802 if (!x86_64_general_operand (xops[0], DImode))
22804 tmp = gen_rtx_REG (DImode, R10_REG);
22806 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
22808 xops[1] = this_param;
22810 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22813 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22816 /* Adjust the this parameter by a value stored in the vtable. */
22820 tmp = gen_rtx_REG (DImode, R10_REG);
22823 int tmp_regno = CX_REG;
22824 if (lookup_attribute ("fastcall",
22825 TYPE_ATTRIBUTES (TREE_TYPE (function))))
22826 tmp_regno = AX_REG;
22827 tmp = gen_rtx_REG (SImode, tmp_regno);
22830 xops[0] = gen_rtx_MEM (Pmode, this_reg);
22833 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22835 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22837 /* Adjust the this parameter. */
22838 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
22839 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
22841 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
22842 xops[0] = GEN_INT (vcall_offset);
22844 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22845 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
22847 xops[1] = this_reg;
22849 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22851 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22854 /* If necessary, drop THIS back to its stack slot. */
22855 if (this_reg && this_reg != this_param)
22857 xops[0] = this_reg;
22858 xops[1] = this_param;
22859 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22862 xops[0] = XEXP (DECL_RTL (function), 0);
22865 if (!flag_pic || (*targetm.binds_local_p) (function))
22866 output_asm_insn ("jmp\t%P0", xops);
22867 /* All thunks should be in the same object as their target,
22868 and thus binds_local_p should be true. */
22869 else if (TARGET_64BIT_MS_ABI)
22870 gcc_unreachable ();
22873 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
22874 tmp = gen_rtx_CONST (Pmode, tmp);
22875 tmp = gen_rtx_MEM (QImode, tmp);
22877 output_asm_insn ("jmp\t%A0", xops);
22882 if (!flag_pic || (*targetm.binds_local_p) (function))
22883 output_asm_insn ("jmp\t%P0", xops);
22888 rtx sym_ref = XEXP (DECL_RTL (function), 0);
22889 tmp = (gen_rtx_SYMBOL_REF
22891 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
22892 tmp = gen_rtx_MEM (QImode, tmp);
22894 output_asm_insn ("jmp\t%0", xops);
22897 #endif /* TARGET_MACHO */
22899 tmp = gen_rtx_REG (SImode, CX_REG);
22900 output_set_got (tmp, NULL_RTX);
22903 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
22904 output_asm_insn ("jmp\t{*}%1", xops);
22910 x86_file_start (void)
22912 default_file_start ();
22914 darwin_file_start ();
22916 if (X86_FILE_START_VERSION_DIRECTIVE)
22917 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
22918 if (X86_FILE_START_FLTUSED)
22919 fputs ("\t.global\t__fltused\n", asm_out_file);
22920 if (ix86_asm_dialect == ASM_INTEL)
22921 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
22925 x86_field_alignment (tree field, int computed)
22927 enum machine_mode mode;
22928 tree type = TREE_TYPE (field);
22930 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
22932 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
22933 ? get_inner_array_type (type) : type);
22934 if (mode == DFmode || mode == DCmode
22935 || GET_MODE_CLASS (mode) == MODE_INT
22936 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
22937 return MIN (32, computed);
22941 /* Output assembler code to FILE to increment profiler label # LABELNO
22942 for profiling a function entry. */
22944 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
22948 #ifndef NO_PROFILE_COUNTERS
22949 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
22952 if (!TARGET_64BIT_MS_ABI && flag_pic)
22953 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
22955 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22959 #ifndef NO_PROFILE_COUNTERS
22960 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
22961 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
22963 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
22967 #ifndef NO_PROFILE_COUNTERS
22968 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
22969 PROFILE_COUNT_REGISTER);
22971 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22975 /* We don't have exact information about the insn sizes, but we may assume
22976 quite safely that we are informed about all 1 byte insns and memory
22977 address sizes. This is enough to eliminate unnecessary padding in
22981 min_insn_size (rtx insn)
22985 if (!INSN_P (insn) || !active_insn_p (insn))
22988 /* Discard alignments we've emit and jump instructions. */
22989 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
22990 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
22993 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
22994 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
22997 /* Important case - calls are always 5 bytes.
22998 It is common to have many calls in the row. */
23000 && symbolic_reference_mentioned_p (PATTERN (insn))
23001 && !SIBLING_CALL_P (insn))
23003 if (get_attr_length (insn) <= 1)
23006 /* For normal instructions we may rely on the sizes of addresses
23007 and the presence of symbol to require 4 bytes of encoding.
23008 This is not the case for jumps where references are PC relative. */
23009 if (!JUMP_P (insn))
23011 l = get_attr_length_address (insn);
23012 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23021 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23025 ix86_avoid_jump_misspredicts (void)
23027 rtx insn, start = get_insns ();
23028 int nbytes = 0, njumps = 0;
23031 /* Look for all minimal intervals of instructions containing 4 jumps.
23032 The intervals are bounded by START and INSN. NBYTES is the total
23033 size of instructions in the interval including INSN and not including
23034 START. When the NBYTES is smaller than 16 bytes, it is possible
23035 that the end of START and INSN ends up in the same 16byte page.
23037 The smallest offset in the page INSN can start is the case where START
23038 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23039 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23041 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23044 nbytes += min_insn_size (insn);
23046 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23047 INSN_UID (insn), min_insn_size (insn));
23049 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23050 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23058 start = NEXT_INSN (start);
23059 if ((JUMP_P (start)
23060 && GET_CODE (PATTERN (start)) != ADDR_VEC
23061 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23063 njumps--, isjump = 1;
23066 nbytes -= min_insn_size (start);
23068 gcc_assert (njumps >= 0);
23070 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23071 INSN_UID (start), INSN_UID (insn), nbytes);
23073 if (njumps == 3 && isjump && nbytes < 16)
23075 int padsize = 15 - nbytes + min_insn_size (insn);
23078 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23079 INSN_UID (insn), padsize);
23080 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23085 /* AMD Athlon works faster
23086 when RET is not destination of conditional jump or directly preceded
23087 by other jump instruction. We avoid the penalty by inserting NOP just
23088 before the RET instructions in such cases. */
23090 ix86_pad_returns (void)
23095 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23097 basic_block bb = e->src;
23098 rtx ret = BB_END (bb);
23100 bool replace = false;
23102 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23103 || !maybe_hot_bb_p (bb))
23105 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23106 if (active_insn_p (prev) || LABEL_P (prev))
23108 if (prev && LABEL_P (prev))
23113 FOR_EACH_EDGE (e, ei, bb->preds)
23114 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23115 && !(e->flags & EDGE_FALLTHRU))
23120 prev = prev_active_insn (ret);
23122 && ((JUMP_P (prev) && any_condjump_p (prev))
23125 /* Empty functions get branch mispredict even when the jump destination
23126 is not visible to us. */
23127 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23132 emit_insn_before (gen_return_internal_long (), ret);
23138 /* Implement machine specific optimizations. We implement padding of returns
23139 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23143 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23144 ix86_pad_returns ();
23145 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23146 ix86_avoid_jump_misspredicts ();
23149 /* Return nonzero when QImode register that must be represented via REX prefix
23152 x86_extended_QIreg_mentioned_p (rtx insn)
23155 extract_insn_cached (insn);
23156 for (i = 0; i < recog_data.n_operands; i++)
23157 if (REG_P (recog_data.operand[i])
23158 && REGNO (recog_data.operand[i]) >= 4)
23163 /* Return nonzero when P points to register encoded via REX prefix.
23164 Called via for_each_rtx. */
23166 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23168 unsigned int regno;
23171 regno = REGNO (*p);
23172 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23175 /* Return true when INSN mentions register that must be encoded using REX
23178 x86_extended_reg_mentioned_p (rtx insn)
23180 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23183 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23184 optabs would emit if we didn't have TFmode patterns. */
23187 x86_emit_floatuns (rtx operands[2])
23189 rtx neglab, donelab, i0, i1, f0, in, out;
23190 enum machine_mode mode, inmode;
23192 inmode = GET_MODE (operands[1]);
23193 gcc_assert (inmode == SImode || inmode == DImode);
23196 in = force_reg (inmode, operands[1]);
23197 mode = GET_MODE (out);
23198 neglab = gen_label_rtx ();
23199 donelab = gen_label_rtx ();
23200 f0 = gen_reg_rtx (mode);
23202 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23204 expand_float (out, in, 0);
23206 emit_jump_insn (gen_jump (donelab));
23209 emit_label (neglab);
23211 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23213 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23215 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23217 expand_float (f0, i0, 0);
23219 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23221 emit_label (donelab);
23224 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23225 with all elements equal to VAR. Return true if successful. */
23228 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23229 rtx target, rtx val)
23231 enum machine_mode smode, wsmode, wvmode;
23246 val = force_reg (GET_MODE_INNER (mode), val);
23247 x = gen_rtx_VEC_DUPLICATE (mode, val);
23248 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23254 if (TARGET_SSE || TARGET_3DNOW_A)
23256 val = gen_lowpart (SImode, val);
23257 x = gen_rtx_TRUNCATE (HImode, val);
23258 x = gen_rtx_VEC_DUPLICATE (mode, x);
23259 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23281 /* Extend HImode to SImode using a paradoxical SUBREG. */
23282 tmp1 = gen_reg_rtx (SImode);
23283 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23284 /* Insert the SImode value as low element of V4SImode vector. */
23285 tmp2 = gen_reg_rtx (V4SImode);
23286 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23287 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23288 CONST0_RTX (V4SImode),
23290 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23291 /* Cast the V4SImode vector back to a V8HImode vector. */
23292 tmp1 = gen_reg_rtx (V8HImode);
23293 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23294 /* Duplicate the low short through the whole low SImode word. */
23295 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23296 /* Cast the V8HImode vector back to a V4SImode vector. */
23297 tmp2 = gen_reg_rtx (V4SImode);
23298 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23299 /* Replicate the low element of the V4SImode vector. */
23300 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23301 /* Cast the V2SImode back to V8HImode, and store in target. */
23302 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23313 /* Extend QImode to SImode using a paradoxical SUBREG. */
23314 tmp1 = gen_reg_rtx (SImode);
23315 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23316 /* Insert the SImode value as low element of V4SImode vector. */
23317 tmp2 = gen_reg_rtx (V4SImode);
23318 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23319 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23320 CONST0_RTX (V4SImode),
23322 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23323 /* Cast the V4SImode vector back to a V16QImode vector. */
23324 tmp1 = gen_reg_rtx (V16QImode);
23325 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23326 /* Duplicate the low byte through the whole low SImode word. */
23327 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23328 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23329 /* Cast the V16QImode vector back to a V4SImode vector. */
23330 tmp2 = gen_reg_rtx (V4SImode);
23331 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23332 /* Replicate the low element of the V4SImode vector. */
23333 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23334 /* Cast the V2SImode back to V16QImode, and store in target. */
23335 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23343 /* Replicate the value once into the next wider mode and recurse. */
23344 val = convert_modes (wsmode, smode, val, true);
23345 x = expand_simple_binop (wsmode, ASHIFT, val,
23346 GEN_INT (GET_MODE_BITSIZE (smode)),
23347 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23348 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23350 x = gen_reg_rtx (wvmode);
23351 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23352 gcc_unreachable ();
23353 emit_move_insn (target, gen_lowpart (mode, x));
23361 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23362 whose ONE_VAR element is VAR, and other elements are zero. Return true
23366 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23367 rtx target, rtx var, int one_var)
23369 enum machine_mode vsimode;
23385 var = force_reg (GET_MODE_INNER (mode), var);
23386 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23387 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23392 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23393 new_target = gen_reg_rtx (mode);
23395 new_target = target;
23396 var = force_reg (GET_MODE_INNER (mode), var);
23397 x = gen_rtx_VEC_DUPLICATE (mode, var);
23398 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23399 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23402 /* We need to shuffle the value to the correct position, so
23403 create a new pseudo to store the intermediate result. */
23405 /* With SSE2, we can use the integer shuffle insns. */
23406 if (mode != V4SFmode && TARGET_SSE2)
23408 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23410 GEN_INT (one_var == 1 ? 0 : 1),
23411 GEN_INT (one_var == 2 ? 0 : 1),
23412 GEN_INT (one_var == 3 ? 0 : 1)));
23413 if (target != new_target)
23414 emit_move_insn (target, new_target);
23418 /* Otherwise convert the intermediate result to V4SFmode and
23419 use the SSE1 shuffle instructions. */
23420 if (mode != V4SFmode)
23422 tmp = gen_reg_rtx (V4SFmode);
23423 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23428 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23430 GEN_INT (one_var == 1 ? 0 : 1),
23431 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23432 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23434 if (mode != V4SFmode)
23435 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23436 else if (tmp != target)
23437 emit_move_insn (target, tmp);
23439 else if (target != new_target)
23440 emit_move_insn (target, new_target);
23445 vsimode = V4SImode;
23451 vsimode = V2SImode;
23457 /* Zero extend the variable element to SImode and recurse. */
23458 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23460 x = gen_reg_rtx (vsimode);
23461 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23463 gcc_unreachable ();
23465 emit_move_insn (target, gen_lowpart (mode, x));
23473 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23474 consisting of the values in VALS. It is known that all elements
23475 except ONE_VAR are constants. Return true if successful. */
23478 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23479 rtx target, rtx vals, int one_var)
23481 rtx var = XVECEXP (vals, 0, one_var);
23482 enum machine_mode wmode;
23485 const_vec = copy_rtx (vals);
23486 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23487 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23495 /* For the two element vectors, it's just as easy to use
23496 the general case. */
23512 /* There's no way to set one QImode entry easily. Combine
23513 the variable value with its adjacent constant value, and
23514 promote to an HImode set. */
23515 x = XVECEXP (vals, 0, one_var ^ 1);
23518 var = convert_modes (HImode, QImode, var, true);
23519 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23520 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23521 x = GEN_INT (INTVAL (x) & 0xff);
23525 var = convert_modes (HImode, QImode, var, true);
23526 x = gen_int_mode (INTVAL (x) << 8, HImode);
23528 if (x != const0_rtx)
23529 var = expand_simple_binop (HImode, IOR, var, x, var,
23530 1, OPTAB_LIB_WIDEN);
23532 x = gen_reg_rtx (wmode);
23533 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23534 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23536 emit_move_insn (target, gen_lowpart (mode, x));
23543 emit_move_insn (target, const_vec);
23544 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23548 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
23549 all values variable, and none identical. */
23552 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
23553 rtx target, rtx vals)
23555 enum machine_mode half_mode = GET_MODE_INNER (mode);
23556 rtx op0 = NULL, op1 = NULL;
23557 bool use_vec_concat = false;
23563 if (!mmx_ok && !TARGET_SSE)
23569 /* For the two element vectors, we always implement VEC_CONCAT. */
23570 op0 = XVECEXP (vals, 0, 0);
23571 op1 = XVECEXP (vals, 0, 1);
23572 use_vec_concat = true;
23576 half_mode = V2SFmode;
23579 half_mode = V2SImode;
23585 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
23586 Recurse to load the two halves. */
23588 op0 = gen_reg_rtx (half_mode);
23589 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
23590 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
23592 op1 = gen_reg_rtx (half_mode);
23593 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
23594 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
23596 use_vec_concat = true;
23607 gcc_unreachable ();
23610 if (use_vec_concat)
23612 if (!register_operand (op0, half_mode))
23613 op0 = force_reg (half_mode, op0);
23614 if (!register_operand (op1, half_mode))
23615 op1 = force_reg (half_mode, op1);
23617 emit_insn (gen_rtx_SET (VOIDmode, target,
23618 gen_rtx_VEC_CONCAT (mode, op0, op1)));
23622 int i, j, n_elts, n_words, n_elt_per_word;
23623 enum machine_mode inner_mode;
23624 rtx words[4], shift;
23626 inner_mode = GET_MODE_INNER (mode);
23627 n_elts = GET_MODE_NUNITS (mode);
23628 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
23629 n_elt_per_word = n_elts / n_words;
23630 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
23632 for (i = 0; i < n_words; ++i)
23634 rtx word = NULL_RTX;
23636 for (j = 0; j < n_elt_per_word; ++j)
23638 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
23639 elt = convert_modes (word_mode, inner_mode, elt, true);
23645 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
23646 word, 1, OPTAB_LIB_WIDEN);
23647 word = expand_simple_binop (word_mode, IOR, word, elt,
23648 word, 1, OPTAB_LIB_WIDEN);
23656 emit_move_insn (target, gen_lowpart (mode, words[0]));
23657 else if (n_words == 2)
23659 rtx tmp = gen_reg_rtx (mode);
23660 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
23661 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
23662 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
23663 emit_move_insn (target, tmp);
23665 else if (n_words == 4)
23667 rtx tmp = gen_reg_rtx (V4SImode);
23668 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
23669 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
23670 emit_move_insn (target, gen_lowpart (mode, tmp));
23673 gcc_unreachable ();
23677 /* Initialize vector TARGET via VALS. Suppress the use of MMX
23678 instructions unless MMX_OK is true. */
23681 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
23683 enum machine_mode mode = GET_MODE (target);
23684 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23685 int n_elts = GET_MODE_NUNITS (mode);
23686 int n_var = 0, one_var = -1;
23687 bool all_same = true, all_const_zero = true;
23691 for (i = 0; i < n_elts; ++i)
23693 x = XVECEXP (vals, 0, i);
23694 if (!(CONST_INT_P (x)
23695 || GET_CODE (x) == CONST_DOUBLE
23696 || GET_CODE (x) == CONST_FIXED))
23697 n_var++, one_var = i;
23698 else if (x != CONST0_RTX (inner_mode))
23699 all_const_zero = false;
23700 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
23704 /* Constants are best loaded from the constant pool. */
23707 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
23711 /* If all values are identical, broadcast the value. */
23713 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
23714 XVECEXP (vals, 0, 0)))
23717 /* Values where only one field is non-constant are best loaded from
23718 the pool and overwritten via move later. */
23722 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
23723 XVECEXP (vals, 0, one_var),
23727 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
23731 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
23735 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
23737 enum machine_mode mode = GET_MODE (target);
23738 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23739 bool use_vec_merge = false;
23748 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
23749 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
23751 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
23753 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
23754 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23760 use_vec_merge = TARGET_SSE4_1;
23768 /* For the two element vectors, we implement a VEC_CONCAT with
23769 the extraction of the other element. */
23771 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
23772 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
23775 op0 = val, op1 = tmp;
23777 op0 = tmp, op1 = val;
23779 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
23780 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23785 use_vec_merge = TARGET_SSE4_1;
23792 use_vec_merge = true;
23796 /* tmp = target = A B C D */
23797 tmp = copy_to_reg (target);
23798 /* target = A A B B */
23799 emit_insn (gen_sse_unpcklps (target, target, target));
23800 /* target = X A B B */
23801 ix86_expand_vector_set (false, target, val, 0);
23802 /* target = A X C D */
23803 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23804 GEN_INT (1), GEN_INT (0),
23805 GEN_INT (2+4), GEN_INT (3+4)));
23809 /* tmp = target = A B C D */
23810 tmp = copy_to_reg (target);
23811 /* tmp = X B C D */
23812 ix86_expand_vector_set (false, tmp, val, 0);
23813 /* target = A B X D */
23814 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23815 GEN_INT (0), GEN_INT (1),
23816 GEN_INT (0+4), GEN_INT (3+4)));
23820 /* tmp = target = A B C D */
23821 tmp = copy_to_reg (target);
23822 /* tmp = X B C D */
23823 ix86_expand_vector_set (false, tmp, val, 0);
23824 /* target = A B X D */
23825 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23826 GEN_INT (0), GEN_INT (1),
23827 GEN_INT (2+4), GEN_INT (0+4)));
23831 gcc_unreachable ();
23836 use_vec_merge = TARGET_SSE4_1;
23840 /* Element 0 handled by vec_merge below. */
23843 use_vec_merge = true;
23849 /* With SSE2, use integer shuffles to swap element 0 and ELT,
23850 store into element 0, then shuffle them back. */
23854 order[0] = GEN_INT (elt);
23855 order[1] = const1_rtx;
23856 order[2] = const2_rtx;
23857 order[3] = GEN_INT (3);
23858 order[elt] = const0_rtx;
23860 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23861 order[1], order[2], order[3]));
23863 ix86_expand_vector_set (false, target, val, 0);
23865 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23866 order[1], order[2], order[3]));
23870 /* For SSE1, we have to reuse the V4SF code. */
23871 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
23872 gen_lowpart (SFmode, val), elt);
23877 use_vec_merge = TARGET_SSE2;
23880 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
23884 use_vec_merge = TARGET_SSE4_1;
23894 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
23895 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
23896 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23900 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
23902 emit_move_insn (mem, target);
23904 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
23905 emit_move_insn (tmp, val);
23907 emit_move_insn (target, mem);
23912 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
23914 enum machine_mode mode = GET_MODE (vec);
23915 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23916 bool use_vec_extr = false;
23929 use_vec_extr = true;
23933 use_vec_extr = TARGET_SSE4_1;
23945 tmp = gen_reg_rtx (mode);
23946 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
23947 GEN_INT (elt), GEN_INT (elt),
23948 GEN_INT (elt+4), GEN_INT (elt+4)));
23952 tmp = gen_reg_rtx (mode);
23953 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
23957 gcc_unreachable ();
23960 use_vec_extr = true;
23965 use_vec_extr = TARGET_SSE4_1;
23979 tmp = gen_reg_rtx (mode);
23980 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
23981 GEN_INT (elt), GEN_INT (elt),
23982 GEN_INT (elt), GEN_INT (elt)));
23986 tmp = gen_reg_rtx (mode);
23987 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
23991 gcc_unreachable ();
23994 use_vec_extr = true;
23999 /* For SSE1, we have to reuse the V4SF code. */
24000 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24001 gen_lowpart (V4SFmode, vec), elt);
24007 use_vec_extr = TARGET_SSE2;
24010 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24014 use_vec_extr = TARGET_SSE4_1;
24018 /* ??? Could extract the appropriate HImode element and shift. */
24025 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24026 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24028 /* Let the rtl optimizers know about the zero extension performed. */
24029 if (inner_mode == QImode || inner_mode == HImode)
24031 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24032 target = gen_lowpart (SImode, target);
24035 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24039 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24041 emit_move_insn (mem, vec);
24043 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24044 emit_move_insn (target, tmp);
24048 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24049 pattern to reduce; DEST is the destination; IN is the input vector. */
24052 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24054 rtx tmp1, tmp2, tmp3;
24056 tmp1 = gen_reg_rtx (V4SFmode);
24057 tmp2 = gen_reg_rtx (V4SFmode);
24058 tmp3 = gen_reg_rtx (V4SFmode);
24060 emit_insn (gen_sse_movhlps (tmp1, in, in));
24061 emit_insn (fn (tmp2, tmp1, in));
24063 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24064 GEN_INT (1), GEN_INT (1),
24065 GEN_INT (1+4), GEN_INT (1+4)));
24066 emit_insn (fn (dest, tmp2, tmp3));
24069 /* Target hook for scalar_mode_supported_p. */
24071 ix86_scalar_mode_supported_p (enum machine_mode mode)
24073 if (DECIMAL_FLOAT_MODE_P (mode))
24075 else if (mode == TFmode)
24076 return TARGET_64BIT;
24078 return default_scalar_mode_supported_p (mode);
24081 /* Implements target hook vector_mode_supported_p. */
24083 ix86_vector_mode_supported_p (enum machine_mode mode)
24085 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24087 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24089 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24091 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24096 /* Target hook for c_mode_for_suffix. */
24097 static enum machine_mode
24098 ix86_c_mode_for_suffix (char suffix)
24100 if (TARGET_64BIT && suffix == 'q')
24102 if (TARGET_MMX && suffix == 'w')
24108 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24110 We do this in the new i386 backend to maintain source compatibility
24111 with the old cc0-based compiler. */
24114 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24115 tree inputs ATTRIBUTE_UNUSED,
24118 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24120 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24125 /* Implements target vector targetm.asm.encode_section_info. This
24126 is not used by netware. */
24128 static void ATTRIBUTE_UNUSED
24129 ix86_encode_section_info (tree decl, rtx rtl, int first)
24131 default_encode_section_info (decl, rtl, first);
24133 if (TREE_CODE (decl) == VAR_DECL
24134 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24135 && ix86_in_large_data_p (decl))
24136 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24139 /* Worker function for REVERSE_CONDITION. */
24142 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24144 return (mode != CCFPmode && mode != CCFPUmode
24145 ? reverse_condition (code)
24146 : reverse_condition_maybe_unordered (code));
24149 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24153 output_387_reg_move (rtx insn, rtx *operands)
24155 if (REG_P (operands[0]))
24157 if (REG_P (operands[1])
24158 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24160 if (REGNO (operands[0]) == FIRST_STACK_REG)
24161 return output_387_ffreep (operands, 0);
24162 return "fstp\t%y0";
24164 if (STACK_TOP_P (operands[0]))
24165 return "fld%z1\t%y1";
24168 else if (MEM_P (operands[0]))
24170 gcc_assert (REG_P (operands[1]));
24171 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24172 return "fstp%z0\t%y0";
24175 /* There is no non-popping store to memory for XFmode.
24176 So if we need one, follow the store with a load. */
24177 if (GET_MODE (operands[0]) == XFmode)
24178 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24180 return "fst%z0\t%y0";
24187 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24188 FP status register is set. */
24191 ix86_emit_fp_unordered_jump (rtx label)
24193 rtx reg = gen_reg_rtx (HImode);
24196 emit_insn (gen_x86_fnstsw_1 (reg));
24198 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24200 emit_insn (gen_x86_sahf_1 (reg));
24202 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24203 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24207 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24209 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24210 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24213 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24214 gen_rtx_LABEL_REF (VOIDmode, label),
24216 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24218 emit_jump_insn (temp);
24219 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24222 /* Output code to perform a log1p XFmode calculation. */
24224 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24226 rtx label1 = gen_label_rtx ();
24227 rtx label2 = gen_label_rtx ();
24229 rtx tmp = gen_reg_rtx (XFmode);
24230 rtx tmp2 = gen_reg_rtx (XFmode);
24232 emit_insn (gen_absxf2 (tmp, op1));
24233 emit_insn (gen_cmpxf (tmp,
24234 CONST_DOUBLE_FROM_REAL_VALUE (
24235 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24237 emit_jump_insn (gen_bge (label1));
24239 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24240 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24241 emit_jump (label2);
24243 emit_label (label1);
24244 emit_move_insn (tmp, CONST1_RTX (XFmode));
24245 emit_insn (gen_addxf3 (tmp, op1, tmp));
24246 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24247 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24249 emit_label (label2);
24252 /* Output code to perform a Newton-Rhapson approximation of a single precision
24253 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24255 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24257 rtx x0, x1, e0, e1, two;
24259 x0 = gen_reg_rtx (mode);
24260 e0 = gen_reg_rtx (mode);
24261 e1 = gen_reg_rtx (mode);
24262 x1 = gen_reg_rtx (mode);
24264 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24266 if (VECTOR_MODE_P (mode))
24267 two = ix86_build_const_vector (SFmode, true, two);
24269 two = force_reg (mode, two);
24271 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24273 /* x0 = rcp(b) estimate */
24274 emit_insn (gen_rtx_SET (VOIDmode, x0,
24275 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24278 emit_insn (gen_rtx_SET (VOIDmode, e0,
24279 gen_rtx_MULT (mode, x0, b)));
24281 emit_insn (gen_rtx_SET (VOIDmode, e1,
24282 gen_rtx_MINUS (mode, two, e0)));
24284 emit_insn (gen_rtx_SET (VOIDmode, x1,
24285 gen_rtx_MULT (mode, x0, e1)));
24287 emit_insn (gen_rtx_SET (VOIDmode, res,
24288 gen_rtx_MULT (mode, a, x1)));
24291 /* Output code to perform a Newton-Rhapson approximation of a
24292 single precision floating point [reciprocal] square root. */
24294 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24297 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24300 x0 = gen_reg_rtx (mode);
24301 e0 = gen_reg_rtx (mode);
24302 e1 = gen_reg_rtx (mode);
24303 e2 = gen_reg_rtx (mode);
24304 e3 = gen_reg_rtx (mode);
24306 real_arithmetic (&r, NEGATE_EXPR, &dconst3, NULL);
24307 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24309 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24310 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24312 if (VECTOR_MODE_P (mode))
24314 mthree = ix86_build_const_vector (SFmode, true, mthree);
24315 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24318 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24319 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24321 /* x0 = rsqrt(a) estimate */
24322 emit_insn (gen_rtx_SET (VOIDmode, x0,
24323 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24326 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24331 zero = gen_reg_rtx (mode);
24332 mask = gen_reg_rtx (mode);
24334 zero = force_reg (mode, CONST0_RTX(mode));
24335 emit_insn (gen_rtx_SET (VOIDmode, mask,
24336 gen_rtx_NE (mode, zero, a)));
24338 emit_insn (gen_rtx_SET (VOIDmode, x0,
24339 gen_rtx_AND (mode, x0, mask)));
24343 emit_insn (gen_rtx_SET (VOIDmode, e0,
24344 gen_rtx_MULT (mode, x0, a)));
24346 emit_insn (gen_rtx_SET (VOIDmode, e1,
24347 gen_rtx_MULT (mode, e0, x0)));
24350 mthree = force_reg (mode, mthree);
24351 emit_insn (gen_rtx_SET (VOIDmode, e2,
24352 gen_rtx_PLUS (mode, e1, mthree)));
24354 mhalf = force_reg (mode, mhalf);
24356 /* e3 = -.5 * x0 */
24357 emit_insn (gen_rtx_SET (VOIDmode, e3,
24358 gen_rtx_MULT (mode, x0, mhalf)));
24360 /* e3 = -.5 * e0 */
24361 emit_insn (gen_rtx_SET (VOIDmode, e3,
24362 gen_rtx_MULT (mode, e0, mhalf)));
24363 /* ret = e2 * e3 */
24364 emit_insn (gen_rtx_SET (VOIDmode, res,
24365 gen_rtx_MULT (mode, e2, e3)));
24368 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24370 static void ATTRIBUTE_UNUSED
24371 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24374 /* With Binutils 2.15, the "@unwind" marker must be specified on
24375 every occurrence of the ".eh_frame" section, not just the first
24378 && strcmp (name, ".eh_frame") == 0)
24380 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24381 flags & SECTION_WRITE ? "aw" : "a");
24384 default_elf_asm_named_section (name, flags, decl);
24387 /* Return the mangling of TYPE if it is an extended fundamental type. */
24389 static const char *
24390 ix86_mangle_type (const_tree type)
24392 type = TYPE_MAIN_VARIANT (type);
24394 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24395 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24398 switch (TYPE_MODE (type))
24401 /* __float128 is "g". */
24404 /* "long double" or __float80 is "e". */
24411 /* For 32-bit code we can save PIC register setup by using
24412 __stack_chk_fail_local hidden function instead of calling
24413 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24414 register, so it is better to call __stack_chk_fail directly. */
24417 ix86_stack_protect_fail (void)
24419 return TARGET_64BIT
24420 ? default_external_stack_protect_fail ()
24421 : default_hidden_stack_protect_fail ();
24424 /* Select a format to encode pointers in exception handling data. CODE
24425 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24426 true if the symbol may be affected by dynamic relocations.
24428 ??? All x86 object file formats are capable of representing this.
24429 After all, the relocation needed is the same as for the call insn.
24430 Whether or not a particular assembler allows us to enter such, I
24431 guess we'll have to see. */
24433 asm_preferred_eh_data_format (int code, int global)
24437 int type = DW_EH_PE_sdata8;
24439 || ix86_cmodel == CM_SMALL_PIC
24440 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24441 type = DW_EH_PE_sdata4;
24442 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24444 if (ix86_cmodel == CM_SMALL
24445 || (ix86_cmodel == CM_MEDIUM && code))
24446 return DW_EH_PE_udata4;
24447 return DW_EH_PE_absptr;
24450 /* Expand copysign from SIGN to the positive value ABS_VALUE
24451 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24454 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24456 enum machine_mode mode = GET_MODE (sign);
24457 rtx sgn = gen_reg_rtx (mode);
24458 if (mask == NULL_RTX)
24460 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24461 if (!VECTOR_MODE_P (mode))
24463 /* We need to generate a scalar mode mask in this case. */
24464 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24465 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24466 mask = gen_reg_rtx (mode);
24467 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24471 mask = gen_rtx_NOT (mode, mask);
24472 emit_insn (gen_rtx_SET (VOIDmode, sgn,
24473 gen_rtx_AND (mode, mask, sign)));
24474 emit_insn (gen_rtx_SET (VOIDmode, result,
24475 gen_rtx_IOR (mode, abs_value, sgn)));
24478 /* Expand fabs (OP0) and return a new rtx that holds the result. The
24479 mask for masking out the sign-bit is stored in *SMASK, if that is
24482 ix86_expand_sse_fabs (rtx op0, rtx *smask)
24484 enum machine_mode mode = GET_MODE (op0);
24487 xa = gen_reg_rtx (mode);
24488 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
24489 if (!VECTOR_MODE_P (mode))
24491 /* We need to generate a scalar mode mask in this case. */
24492 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24493 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24494 mask = gen_reg_rtx (mode);
24495 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24497 emit_insn (gen_rtx_SET (VOIDmode, xa,
24498 gen_rtx_AND (mode, op0, mask)));
24506 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
24507 swapping the operands if SWAP_OPERANDS is true. The expanded
24508 code is a forward jump to a newly created label in case the
24509 comparison is true. The generated label rtx is returned. */
24511 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
24512 bool swap_operands)
24523 label = gen_label_rtx ();
24524 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
24525 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24526 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
24527 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
24528 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
24529 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
24530 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
24531 JUMP_LABEL (tmp) = label;
24536 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
24537 using comparison code CODE. Operands are swapped for the comparison if
24538 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
24540 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
24541 bool swap_operands)
24543 enum machine_mode mode = GET_MODE (op0);
24544 rtx mask = gen_reg_rtx (mode);
24553 if (mode == DFmode)
24554 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
24555 gen_rtx_fmt_ee (code, mode, op0, op1)));
24557 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
24558 gen_rtx_fmt_ee (code, mode, op0, op1)));
24563 /* Generate and return a rtx of mode MODE for 2**n where n is the number
24564 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
24566 ix86_gen_TWO52 (enum machine_mode mode)
24568 REAL_VALUE_TYPE TWO52r;
24571 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
24572 TWO52 = const_double_from_real_value (TWO52r, mode);
24573 TWO52 = force_reg (mode, TWO52);
24578 /* Expand SSE sequence for computing lround from OP1 storing
24581 ix86_expand_lround (rtx op0, rtx op1)
24583 /* C code for the stuff we're doing below:
24584 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
24587 enum machine_mode mode = GET_MODE (op1);
24588 const struct real_format *fmt;
24589 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24592 /* load nextafter (0.5, 0.0) */
24593 fmt = REAL_MODE_FORMAT (mode);
24594 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24595 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24597 /* adj = copysign (0.5, op1) */
24598 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
24599 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
24601 /* adj = op1 + adj */
24602 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
24604 /* op0 = (imode)adj */
24605 expand_fix (op0, adj, 0);
24608 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
24611 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
24613 /* C code for the stuff we're doing below (for do_floor):
24615 xi -= (double)xi > op1 ? 1 : 0;
24618 enum machine_mode fmode = GET_MODE (op1);
24619 enum machine_mode imode = GET_MODE (op0);
24620 rtx ireg, freg, label, tmp;
24622 /* reg = (long)op1 */
24623 ireg = gen_reg_rtx (imode);
24624 expand_fix (ireg, op1, 0);
24626 /* freg = (double)reg */
24627 freg = gen_reg_rtx (fmode);
24628 expand_float (freg, ireg, 0);
24630 /* ireg = (freg > op1) ? ireg - 1 : ireg */
24631 label = ix86_expand_sse_compare_and_jump (UNLE,
24632 freg, op1, !do_floor);
24633 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
24634 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
24635 emit_move_insn (ireg, tmp);
24637 emit_label (label);
24638 LABEL_NUSES (label) = 1;
24640 emit_move_insn (op0, ireg);
24643 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
24644 result in OPERAND0. */
24646 ix86_expand_rint (rtx operand0, rtx operand1)
24648 /* C code for the stuff we're doing below:
24649 xa = fabs (operand1);
24650 if (!isless (xa, 2**52))
24652 xa = xa + 2**52 - 2**52;
24653 return copysign (xa, operand1);
24655 enum machine_mode mode = GET_MODE (operand0);
24656 rtx res, xa, label, TWO52, mask;
24658 res = gen_reg_rtx (mode);
24659 emit_move_insn (res, operand1);
24661 /* xa = abs (operand1) */
24662 xa = ix86_expand_sse_fabs (res, &mask);
24664 /* if (!isless (xa, TWO52)) goto label; */
24665 TWO52 = ix86_gen_TWO52 (mode);
24666 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24668 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24669 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24671 ix86_sse_copysign_to_positive (res, xa, res, mask);
24673 emit_label (label);
24674 LABEL_NUSES (label) = 1;
24676 emit_move_insn (operand0, res);
24679 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24682 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
24684 /* C code for the stuff we expand below.
24685 double xa = fabs (x), x2;
24686 if (!isless (xa, TWO52))
24688 xa = xa + TWO52 - TWO52;
24689 x2 = copysign (xa, x);
24698 enum machine_mode mode = GET_MODE (operand0);
24699 rtx xa, TWO52, tmp, label, one, res, mask;
24701 TWO52 = ix86_gen_TWO52 (mode);
24703 /* Temporary for holding the result, initialized to the input
24704 operand to ease control flow. */
24705 res = gen_reg_rtx (mode);
24706 emit_move_insn (res, operand1);
24708 /* xa = abs (operand1) */
24709 xa = ix86_expand_sse_fabs (res, &mask);
24711 /* if (!isless (xa, TWO52)) goto label; */
24712 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24714 /* xa = xa + TWO52 - TWO52; */
24715 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24716 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24718 /* xa = copysign (xa, operand1) */
24719 ix86_sse_copysign_to_positive (xa, xa, res, mask);
24721 /* generate 1.0 or -1.0 */
24722 one = force_reg (mode,
24723 const_double_from_real_value (do_floor
24724 ? dconst1 : dconstm1, mode));
24726 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24727 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24728 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24729 gen_rtx_AND (mode, one, tmp)));
24730 /* We always need to subtract here to preserve signed zero. */
24731 tmp = expand_simple_binop (mode, MINUS,
24732 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24733 emit_move_insn (res, tmp);
24735 emit_label (label);
24736 LABEL_NUSES (label) = 1;
24738 emit_move_insn (operand0, res);
24741 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24744 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
24746 /* C code for the stuff we expand below.
24747 double xa = fabs (x), x2;
24748 if (!isless (xa, TWO52))
24750 x2 = (double)(long)x;
24757 if (HONOR_SIGNED_ZEROS (mode))
24758 return copysign (x2, x);
24761 enum machine_mode mode = GET_MODE (operand0);
24762 rtx xa, xi, TWO52, tmp, label, one, res, mask;
24764 TWO52 = ix86_gen_TWO52 (mode);
24766 /* Temporary for holding the result, initialized to the input
24767 operand to ease control flow. */
24768 res = gen_reg_rtx (mode);
24769 emit_move_insn (res, operand1);
24771 /* xa = abs (operand1) */
24772 xa = ix86_expand_sse_fabs (res, &mask);
24774 /* if (!isless (xa, TWO52)) goto label; */
24775 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24777 /* xa = (double)(long)x */
24778 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24779 expand_fix (xi, res, 0);
24780 expand_float (xa, xi, 0);
24783 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24785 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24786 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24787 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24788 gen_rtx_AND (mode, one, tmp)));
24789 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
24790 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24791 emit_move_insn (res, tmp);
24793 if (HONOR_SIGNED_ZEROS (mode))
24794 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24796 emit_label (label);
24797 LABEL_NUSES (label) = 1;
24799 emit_move_insn (operand0, res);
24802 /* Expand SSE sequence for computing round from OPERAND1 storing
24803 into OPERAND0. Sequence that works without relying on DImode truncation
24804 via cvttsd2siq that is only available on 64bit targets. */
24806 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
24808 /* C code for the stuff we expand below.
24809 double xa = fabs (x), xa2, x2;
24810 if (!isless (xa, TWO52))
24812 Using the absolute value and copying back sign makes
24813 -0.0 -> -0.0 correct.
24814 xa2 = xa + TWO52 - TWO52;
24819 else if (dxa > 0.5)
24821 x2 = copysign (xa2, x);
24824 enum machine_mode mode = GET_MODE (operand0);
24825 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
24827 TWO52 = ix86_gen_TWO52 (mode);
24829 /* Temporary for holding the result, initialized to the input
24830 operand to ease control flow. */
24831 res = gen_reg_rtx (mode);
24832 emit_move_insn (res, operand1);
24834 /* xa = abs (operand1) */
24835 xa = ix86_expand_sse_fabs (res, &mask);
24837 /* if (!isless (xa, TWO52)) goto label; */
24838 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24840 /* xa2 = xa + TWO52 - TWO52; */
24841 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24842 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
24844 /* dxa = xa2 - xa; */
24845 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
24847 /* generate 0.5, 1.0 and -0.5 */
24848 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
24849 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
24850 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
24854 tmp = gen_reg_rtx (mode);
24855 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
24856 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
24857 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24858 gen_rtx_AND (mode, one, tmp)));
24859 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24860 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
24861 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
24862 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24863 gen_rtx_AND (mode, one, tmp)));
24864 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24866 /* res = copysign (xa2, operand1) */
24867 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
24869 emit_label (label);
24870 LABEL_NUSES (label) = 1;
24872 emit_move_insn (operand0, res);
24875 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24878 ix86_expand_trunc (rtx operand0, rtx operand1)
24880 /* C code for SSE variant we expand below.
24881 double xa = fabs (x), x2;
24882 if (!isless (xa, TWO52))
24884 x2 = (double)(long)x;
24885 if (HONOR_SIGNED_ZEROS (mode))
24886 return copysign (x2, x);
24889 enum machine_mode mode = GET_MODE (operand0);
24890 rtx xa, xi, TWO52, label, res, mask;
24892 TWO52 = ix86_gen_TWO52 (mode);
24894 /* Temporary for holding the result, initialized to the input
24895 operand to ease control flow. */
24896 res = gen_reg_rtx (mode);
24897 emit_move_insn (res, operand1);
24899 /* xa = abs (operand1) */
24900 xa = ix86_expand_sse_fabs (res, &mask);
24902 /* if (!isless (xa, TWO52)) goto label; */
24903 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24905 /* x = (double)(long)x */
24906 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24907 expand_fix (xi, res, 0);
24908 expand_float (res, xi, 0);
24910 if (HONOR_SIGNED_ZEROS (mode))
24911 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24913 emit_label (label);
24914 LABEL_NUSES (label) = 1;
24916 emit_move_insn (operand0, res);
24919 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24922 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
24924 enum machine_mode mode = GET_MODE (operand0);
24925 rtx xa, mask, TWO52, label, one, res, smask, tmp;
24927 /* C code for SSE variant we expand below.
24928 double xa = fabs (x), x2;
24929 if (!isless (xa, TWO52))
24931 xa2 = xa + TWO52 - TWO52;
24935 x2 = copysign (xa2, x);
24939 TWO52 = ix86_gen_TWO52 (mode);
24941 /* Temporary for holding the result, initialized to the input
24942 operand to ease control flow. */
24943 res = gen_reg_rtx (mode);
24944 emit_move_insn (res, operand1);
24946 /* xa = abs (operand1) */
24947 xa = ix86_expand_sse_fabs (res, &smask);
24949 /* if (!isless (xa, TWO52)) goto label; */
24950 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24952 /* res = xa + TWO52 - TWO52; */
24953 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24954 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
24955 emit_move_insn (res, tmp);
24958 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24960 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
24961 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
24962 emit_insn (gen_rtx_SET (VOIDmode, mask,
24963 gen_rtx_AND (mode, mask, one)));
24964 tmp = expand_simple_binop (mode, MINUS,
24965 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
24966 emit_move_insn (res, tmp);
24968 /* res = copysign (res, operand1) */
24969 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
24971 emit_label (label);
24972 LABEL_NUSES (label) = 1;
24974 emit_move_insn (operand0, res);
24977 /* Expand SSE sequence for computing round from OPERAND1 storing
24980 ix86_expand_round (rtx operand0, rtx operand1)
24982 /* C code for the stuff we're doing below:
24983 double xa = fabs (x);
24984 if (!isless (xa, TWO52))
24986 xa = (double)(long)(xa + nextafter (0.5, 0.0));
24987 return copysign (xa, x);
24989 enum machine_mode mode = GET_MODE (operand0);
24990 rtx res, TWO52, xa, label, xi, half, mask;
24991 const struct real_format *fmt;
24992 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24994 /* Temporary for holding the result, initialized to the input
24995 operand to ease control flow. */
24996 res = gen_reg_rtx (mode);
24997 emit_move_insn (res, operand1);
24999 TWO52 = ix86_gen_TWO52 (mode);
25000 xa = ix86_expand_sse_fabs (res, &mask);
25001 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25003 /* load nextafter (0.5, 0.0) */
25004 fmt = REAL_MODE_FORMAT (mode);
25005 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25006 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25008 /* xa = xa + 0.5 */
25009 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25010 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25012 /* xa = (double)(int64_t)xa */
25013 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25014 expand_fix (xi, xa, 0);
25015 expand_float (xa, xi, 0);
25017 /* res = copysign (xa, operand1) */
25018 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25020 emit_label (label);
25021 LABEL_NUSES (label) = 1;
25023 emit_move_insn (operand0, res);
25027 /* Validate whether a SSE5 instruction is valid or not.
25028 OPERANDS is the array of operands.
25029 NUM is the number of operands.
25030 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25031 NUM_MEMORY is the maximum number of memory operands to accept. */
25033 ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
25039 /* Count the number of memory arguments */
25042 for (i = 0; i < num; i++)
25044 enum machine_mode mode = GET_MODE (operands[i]);
25045 if (register_operand (operands[i], mode))
25048 else if (memory_operand (operands[i], mode))
25050 mem_mask |= (1 << i);
25056 rtx pattern = PATTERN (insn);
25058 /* allow 0 for pcmov */
25059 if (GET_CODE (pattern) != SET
25060 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25062 || operands[i] != CONST0_RTX (mode))
25067 /* If there were no memory operations, allow the insn */
25071 /* Do not allow the destination register to be a memory operand. */
25072 else if (mem_mask & (1 << 0))
25075 /* If there are too many memory operations, disallow the instruction. While
25076 the hardware only allows 1 memory reference, before register allocation
25077 for some insns, we allow two memory operations sometimes in order to allow
25078 code like the following to be optimized:
25080 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25082 or similar cases that are vectorized into using the fmaddss
25084 else if (mem_count > num_memory)
25087 /* Don't allow more than one memory operation if not optimizing. */
25088 else if (mem_count > 1 && !optimize)
25091 else if (num == 4 && mem_count == 1)
25093 /* formats (destination is the first argument), example fmaddss:
25094 xmm1, xmm1, xmm2, xmm3/mem
25095 xmm1, xmm1, xmm2/mem, xmm3
25096 xmm1, xmm2, xmm3/mem, xmm1
25097 xmm1, xmm2/mem, xmm3, xmm1 */
25099 return ((mem_mask == (1 << 1))
25100 || (mem_mask == (1 << 2))
25101 || (mem_mask == (1 << 3)));
25103 /* format, example pmacsdd:
25104 xmm1, xmm2, xmm3/mem, xmm1 */
25106 return (mem_mask == (1 << 2));
25109 else if (num == 4 && num_memory == 2)
25111 /* If there are two memory operations, we can load one of the memory ops
25112 into the destination register. This is for optimizing the
25113 multiply/add ops, which the combiner has optimized both the multiply
25114 and the add insns to have a memory operation. We have to be careful
25115 that the destination doesn't overlap with the inputs. */
25116 rtx op0 = operands[0];
25118 if (reg_mentioned_p (op0, operands[1])
25119 || reg_mentioned_p (op0, operands[2])
25120 || reg_mentioned_p (op0, operands[3]))
25123 /* formats (destination is the first argument), example fmaddss:
25124 xmm1, xmm1, xmm2, xmm3/mem
25125 xmm1, xmm1, xmm2/mem, xmm3
25126 xmm1, xmm2, xmm3/mem, xmm1
25127 xmm1, xmm2/mem, xmm3, xmm1
25129 For the oc0 case, we will load either operands[1] or operands[3] into
25130 operands[0], so any combination of 2 memory operands is ok. */
25134 /* format, example pmacsdd:
25135 xmm1, xmm2, xmm3/mem, xmm1
25137 For the integer multiply/add instructions be more restrictive and
25138 require operands[2] and operands[3] to be the memory operands. */
25140 return (mem_mask == ((1 << 2) | (1 << 3)));
25143 else if (num == 3 && num_memory == 1)
25145 /* formats, example protb:
25146 xmm1, xmm2, xmm3/mem
25147 xmm1, xmm2/mem, xmm3 */
25149 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25151 /* format, example comeq:
25152 xmm1, xmm2, xmm3/mem */
25154 return (mem_mask == (1 << 2));
25158 gcc_unreachable ();
25164 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25165 hardware will allow by using the destination register to load one of the
25166 memory operations. Presently this is used by the multiply/add routines to
25167 allow 2 memory references. */
25170 ix86_expand_sse5_multiple_memory (rtx operands[],
25172 enum machine_mode mode)
25174 rtx op0 = operands[0];
25176 || memory_operand (op0, mode)
25177 || reg_mentioned_p (op0, operands[1])
25178 || reg_mentioned_p (op0, operands[2])
25179 || reg_mentioned_p (op0, operands[3]))
25180 gcc_unreachable ();
25182 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25183 the destination register. */
25184 if (memory_operand (operands[1], mode))
25186 emit_move_insn (op0, operands[1]);
25189 else if (memory_operand (operands[3], mode))
25191 emit_move_insn (op0, operands[3]);
25195 gcc_unreachable ();
25201 /* Table of valid machine attributes. */
25202 static const struct attribute_spec ix86_attribute_table[] =
25204 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25205 /* Stdcall attribute says callee is responsible for popping arguments
25206 if they are not variable. */
25207 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25208 /* Fastcall attribute says callee is responsible for popping arguments
25209 if they are not variable. */
25210 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25211 /* Cdecl attribute says the callee is a normal C declaration */
25212 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25213 /* Regparm attribute specifies how many integer arguments are to be
25214 passed in registers. */
25215 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25216 /* Sseregparm attribute says we are using x86_64 calling conventions
25217 for FP arguments. */
25218 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25219 /* force_align_arg_pointer says this function realigns the stack at entry. */
25220 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25221 false, true, true, ix86_handle_cconv_attribute },
25222 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25223 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25224 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25225 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25227 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25228 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25229 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25230 SUBTARGET_ATTRIBUTE_TABLE,
25232 { NULL, 0, 0, false, false, false, NULL }
25235 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25237 x86_builtin_vectorization_cost (bool runtime_test)
25239 /* If the branch of the runtime test is taken - i.e. - the vectorized
25240 version is skipped - this incurs a misprediction cost (because the
25241 vectorized version is expected to be the fall-through). So we subtract
25242 the latency of a mispredicted branch from the costs that are incured
25243 when the vectorized version is executed.
25245 TODO: The values in individual target tables have to be tuned or new
25246 fields may be needed. For eg. on K8, the default branch path is the
25247 not-taken path. If the taken path is predicted correctly, the minimum
25248 penalty of going down the taken-path is 1 cycle. If the taken-path is
25249 not predicted correctly, then the minimum penalty is 10 cycles. */
25253 return (-(ix86_cost->cond_taken_branch_cost));
25259 /* Initialize the GCC target structure. */
25260 #undef TARGET_ATTRIBUTE_TABLE
25261 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25262 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25263 # undef TARGET_MERGE_DECL_ATTRIBUTES
25264 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25267 #undef TARGET_COMP_TYPE_ATTRIBUTES
25268 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25270 #undef TARGET_INIT_BUILTINS
25271 #define TARGET_INIT_BUILTINS ix86_init_builtins
25272 #undef TARGET_EXPAND_BUILTIN
25273 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25275 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25276 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25277 ix86_builtin_vectorized_function
25279 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25280 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25282 #undef TARGET_BUILTIN_RECIPROCAL
25283 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25285 #undef TARGET_ASM_FUNCTION_EPILOGUE
25286 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25288 #undef TARGET_ENCODE_SECTION_INFO
25289 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25290 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25292 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25295 #undef TARGET_ASM_OPEN_PAREN
25296 #define TARGET_ASM_OPEN_PAREN ""
25297 #undef TARGET_ASM_CLOSE_PAREN
25298 #define TARGET_ASM_CLOSE_PAREN ""
25300 #undef TARGET_ASM_ALIGNED_HI_OP
25301 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25302 #undef TARGET_ASM_ALIGNED_SI_OP
25303 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25305 #undef TARGET_ASM_ALIGNED_DI_OP
25306 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25309 #undef TARGET_ASM_UNALIGNED_HI_OP
25310 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25311 #undef TARGET_ASM_UNALIGNED_SI_OP
25312 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25313 #undef TARGET_ASM_UNALIGNED_DI_OP
25314 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25316 #undef TARGET_SCHED_ADJUST_COST
25317 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25318 #undef TARGET_SCHED_ISSUE_RATE
25319 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25320 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25321 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25322 ia32_multipass_dfa_lookahead
25324 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25325 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25328 #undef TARGET_HAVE_TLS
25329 #define TARGET_HAVE_TLS true
25331 #undef TARGET_CANNOT_FORCE_CONST_MEM
25332 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25333 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25334 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25336 #undef TARGET_DELEGITIMIZE_ADDRESS
25337 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25339 #undef TARGET_MS_BITFIELD_LAYOUT_P
25340 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25343 #undef TARGET_BINDS_LOCAL_P
25344 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25346 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25347 #undef TARGET_BINDS_LOCAL_P
25348 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25351 #undef TARGET_ASM_OUTPUT_MI_THUNK
25352 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25353 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25354 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25356 #undef TARGET_ASM_FILE_START
25357 #define TARGET_ASM_FILE_START x86_file_start
25359 #undef TARGET_DEFAULT_TARGET_FLAGS
25360 #define TARGET_DEFAULT_TARGET_FLAGS \
25362 | TARGET_SUBTARGET_DEFAULT \
25363 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25365 #undef TARGET_HANDLE_OPTION
25366 #define TARGET_HANDLE_OPTION ix86_handle_option
25368 #undef TARGET_RTX_COSTS
25369 #define TARGET_RTX_COSTS ix86_rtx_costs
25370 #undef TARGET_ADDRESS_COST
25371 #define TARGET_ADDRESS_COST ix86_address_cost
25373 #undef TARGET_FIXED_CONDITION_CODE_REGS
25374 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25375 #undef TARGET_CC_MODES_COMPATIBLE
25376 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25378 #undef TARGET_MACHINE_DEPENDENT_REORG
25379 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25381 #undef TARGET_BUILD_BUILTIN_VA_LIST
25382 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25384 #undef TARGET_EXPAND_BUILTIN_VA_START
25385 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
25387 #undef TARGET_MD_ASM_CLOBBERS
25388 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25390 #undef TARGET_PROMOTE_PROTOTYPES
25391 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25392 #undef TARGET_STRUCT_VALUE_RTX
25393 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25394 #undef TARGET_SETUP_INCOMING_VARARGS
25395 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25396 #undef TARGET_MUST_PASS_IN_STACK
25397 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25398 #undef TARGET_PASS_BY_REFERENCE
25399 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25400 #undef TARGET_INTERNAL_ARG_POINTER
25401 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25402 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25403 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25404 #undef TARGET_STRICT_ARGUMENT_NAMING
25405 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25407 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25408 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25410 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25411 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25413 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25414 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25416 #undef TARGET_C_MODE_FOR_SUFFIX
25417 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25420 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25421 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25424 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25425 #undef TARGET_INSERT_ATTRIBUTES
25426 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25429 #undef TARGET_MANGLE_TYPE
25430 #define TARGET_MANGLE_TYPE ix86_mangle_type
25432 #undef TARGET_STACK_PROTECT_FAIL
25433 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25435 #undef TARGET_FUNCTION_VALUE
25436 #define TARGET_FUNCTION_VALUE ix86_function_value
25438 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25439 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25441 struct gcc_target targetm = TARGET_INITIALIZER;
25443 #include "gt-i386.h"
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