1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs size_cost = { /* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of loading integer registers */
995 2, /* cost of moving MMX register */
996 {6, 6}, /* cost of loading MMX registers
997 in SImode and DImode */
998 {4, 4}, /* cost of storing MMX registers
999 in SImode and DImode */
1000 2, /* cost of moving SSE register */
1001 {6, 6, 6}, /* cost of loading SSE registers
1002 in SImode, DImode and TImode */
1003 {4, 4, 4}, /* cost of storing SSE registers
1004 in SImode, DImode and TImode */
1005 2, /* MMX or SSE register to integer */
1006 32, /* size of l1 cache. */
1007 2048, /* size of l2 cache. */
1008 128, /* size of prefetch block */
1009 8, /* number of parallel prefetches */
1010 3, /* Branch cost */
1011 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1012 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1013 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1014 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1015 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1016 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1017 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1018 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1019 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1020 {{libcall, {{8, loop}, {15, unrolled_loop},
1021 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1022 {libcall, {{24, loop}, {32, unrolled_loop},
1023 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1024 1, /* scalar_stmt_cost. */
1025 1, /* scalar load_cost. */
1026 1, /* scalar_store_cost. */
1027 1, /* vec_stmt_cost. */
1028 1, /* vec_to_scalar_cost. */
1029 1, /* scalar_to_vec_cost. */
1030 1, /* vec_align_load_cost. */
1031 2, /* vec_unalign_load_cost. */
1032 1, /* vec_store_cost. */
1033 3, /* cond_taken_branch_cost. */
1034 1, /* cond_not_taken_branch_cost. */
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1039 struct processor_costs generic64_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1045 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1046 COSTS_N_INSNS (1), /* variable shift costs */
1047 COSTS_N_INSNS (1), /* constant shift costs */
1048 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1049 COSTS_N_INSNS (4), /* HI */
1050 COSTS_N_INSNS (3), /* SI */
1051 COSTS_N_INSNS (4), /* DI */
1052 COSTS_N_INSNS (2)}, /* other */
1053 0, /* cost of multiply per each bit set */
1054 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1055 COSTS_N_INSNS (26), /* HI */
1056 COSTS_N_INSNS (42), /* SI */
1057 COSTS_N_INSNS (74), /* DI */
1058 COSTS_N_INSNS (74)}, /* other */
1059 COSTS_N_INSNS (1), /* cost of movsx */
1060 COSTS_N_INSNS (1), /* cost of movzx */
1061 8, /* "large" insn */
1062 17, /* MOVE_RATIO */
1063 4, /* cost for loading QImode using movzbl */
1064 {4, 4, 4}, /* cost of loading integer registers
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1067 {4, 4, 4}, /* cost of storing integer registers */
1068 4, /* cost of reg,reg fld/fst */
1069 {12, 12, 12}, /* cost of loading fp registers
1070 in SFmode, DFmode and XFmode */
1071 {6, 6, 8}, /* cost of storing fp registers
1072 in SFmode, DFmode and XFmode */
1073 2, /* cost of moving MMX register */
1074 {8, 8}, /* cost of loading MMX registers
1075 in SImode and DImode */
1076 {8, 8}, /* cost of storing MMX registers
1077 in SImode and DImode */
1078 2, /* cost of moving SSE register */
1079 {8, 8, 8}, /* cost of loading SSE registers
1080 in SImode, DImode and TImode */
1081 {8, 8, 8}, /* cost of storing SSE registers
1082 in SImode, DImode and TImode */
1083 5, /* MMX or SSE register to integer */
1084 32, /* size of l1 cache. */
1085 512, /* size of l2 cache. */
1086 64, /* size of prefetch block */
1087 6, /* number of parallel prefetches */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1090 3, /* Branch cost */
1091 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1092 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1093 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1094 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1095 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1096 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 1, /* scalar_stmt_cost. */
1102 1, /* scalar load_cost. */
1103 1, /* scalar_store_cost. */
1104 1, /* vec_stmt_cost. */
1105 1, /* vec_to_scalar_cost. */
1106 1, /* scalar_to_vec_cost. */
1107 1, /* vec_align_load_cost. */
1108 2, /* vec_unalign_load_cost. */
1109 1, /* vec_store_cost. */
1110 3, /* cond_taken_branch_cost. */
1111 1, /* cond_not_taken_branch_cost. */
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1116 struct processor_costs generic32_cost = {
1117 COSTS_N_INSNS (1), /* cost of an add instruction */
1118 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1119 COSTS_N_INSNS (1), /* variable shift costs */
1120 COSTS_N_INSNS (1), /* constant shift costs */
1121 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1122 COSTS_N_INSNS (4), /* HI */
1123 COSTS_N_INSNS (3), /* SI */
1124 COSTS_N_INSNS (4), /* DI */
1125 COSTS_N_INSNS (2)}, /* other */
1126 0, /* cost of multiply per each bit set */
1127 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1128 COSTS_N_INSNS (26), /* HI */
1129 COSTS_N_INSNS (42), /* SI */
1130 COSTS_N_INSNS (74), /* DI */
1131 COSTS_N_INSNS (74)}, /* other */
1132 COSTS_N_INSNS (1), /* cost of movsx */
1133 COSTS_N_INSNS (1), /* cost of movzx */
1134 8, /* "large" insn */
1135 17, /* MOVE_RATIO */
1136 4, /* cost for loading QImode using movzbl */
1137 {4, 4, 4}, /* cost of loading integer registers
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1140 {4, 4, 4}, /* cost of storing integer registers */
1141 4, /* cost of reg,reg fld/fst */
1142 {12, 12, 12}, /* cost of loading fp registers
1143 in SFmode, DFmode and XFmode */
1144 {6, 6, 8}, /* cost of storing fp registers
1145 in SFmode, DFmode and XFmode */
1146 2, /* cost of moving MMX register */
1147 {8, 8}, /* cost of loading MMX registers
1148 in SImode and DImode */
1149 {8, 8}, /* cost of storing MMX registers
1150 in SImode and DImode */
1151 2, /* cost of moving SSE register */
1152 {8, 8, 8}, /* cost of loading SSE registers
1153 in SImode, DImode and TImode */
1154 {8, 8, 8}, /* cost of storing SSE registers
1155 in SImode, DImode and TImode */
1156 5, /* MMX or SSE register to integer */
1157 32, /* size of l1 cache. */
1158 256, /* size of l2 cache. */
1159 64, /* size of prefetch block */
1160 6, /* number of parallel prefetches */
1161 3, /* Branch cost */
1162 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1163 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1164 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1165 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1166 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1167 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 1, /* scalar_stmt_cost. */
1173 1, /* scalar load_cost. */
1174 1, /* scalar_store_cost. */
1175 1, /* vec_stmt_cost. */
1176 1, /* vec_to_scalar_cost. */
1177 1, /* scalar_to_vec_cost. */
1178 1, /* vec_align_load_cost. */
1179 2, /* vec_unalign_load_cost. */
1180 1, /* vec_store_cost. */
1181 3, /* cond_taken_branch_cost. */
1182 1, /* cond_not_taken_branch_cost. */
1185 const struct processor_costs *ix86_cost = &pentium_cost;
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1213 unsigned char ix86_tune_features[X86_TUNE_LAST];
1215 /* Feature tests against the various tunings used to create ix86_tune_features
1216 based on the processor mask. */
1217 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1218 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1219 negatively, so enabling for Generic64 seems like good code size
1220 tradeoff. We can't enable it for 32bit generic because it does not
1221 work well with PPro base chips. */
1222 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1224 /* X86_TUNE_PUSH_MEMORY */
1225 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1226 | m_NOCONA | m_CORE2 | m_GENERIC,
1228 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1231 /* X86_TUNE_USE_BIT_TEST */
1234 /* X86_TUNE_UNROLL_STRLEN */
1235 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1237 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1238 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1240 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1241 on simulation result. But after P4 was made, no performance benefit
1242 was observed with branch hints. It also increases the code size.
1243 As a result, icc never generates branch hints. */
1246 /* X86_TUNE_DOUBLE_WITH_ADD */
1249 /* X86_TUNE_USE_SAHF */
1250 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1251 | m_NOCONA | m_CORE2 | m_GENERIC,
1253 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1254 partial dependencies. */
1255 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1256 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1258 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1259 register stalls on Generic32 compilation setting as well. However
1260 in current implementation the partial register stalls are not eliminated
1261 very well - they can be introduced via subregs synthesized by combine
1262 and can happen in caller/callee saving sequences. Because this option
1263 pays back little on PPro based chips and is in conflict with partial reg
1264 dependencies used by Athlon/P4 based chips, it is better to leave it off
1265 for generic32 for now. */
1268 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1269 m_CORE2 | m_GENERIC,
1271 /* X86_TUNE_USE_HIMODE_FIOP */
1272 m_386 | m_486 | m_K6_GEODE,
1274 /* X86_TUNE_USE_SIMODE_FIOP */
1275 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1277 /* X86_TUNE_USE_MOV0 */
1280 /* X86_TUNE_USE_CLTD */
1281 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1283 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1286 /* X86_TUNE_SPLIT_LONG_MOVES */
1289 /* X86_TUNE_READ_MODIFY_WRITE */
1292 /* X86_TUNE_READ_MODIFY */
1295 /* X86_TUNE_PROMOTE_QIMODE */
1296 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1297 | m_GENERIC /* | m_PENT4 ? */,
1299 /* X86_TUNE_FAST_PREFIX */
1300 ~(m_PENT | m_486 | m_386),
1302 /* X86_TUNE_SINGLE_STRINGOP */
1303 m_386 | m_PENT4 | m_NOCONA,
1305 /* X86_TUNE_QIMODE_MATH */
1308 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1309 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1310 might be considered for Generic32 if our scheme for avoiding partial
1311 stalls was more effective. */
1314 /* X86_TUNE_PROMOTE_QI_REGS */
1317 /* X86_TUNE_PROMOTE_HI_REGS */
1320 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1321 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_ADD_ESP_8 */
1324 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1325 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1327 /* X86_TUNE_SUB_ESP_4 */
1328 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1330 /* X86_TUNE_SUB_ESP_8 */
1331 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1332 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1334 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1335 for DFmode copies */
1336 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1337 | m_GENERIC | m_GEODE),
1339 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1340 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1342 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1343 conflict here in between PPro/Pentium4 based chips that thread 128bit
1344 SSE registers as single units versus K8 based chips that divide SSE
1345 registers to two 64bit halves. This knob promotes all store destinations
1346 to be 128bit to allow register renaming on 128bit SSE units, but usually
1347 results in one extra microop on 64bit SSE units. Experimental results
1348 shows that disabling this option on P4 brings over 20% SPECfp regression,
1349 while enabling it on K8 brings roughly 2.4% regression that can be partly
1350 masked by careful scheduling of moves. */
1351 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1353 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1356 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1357 are resolved on SSE register parts instead of whole registers, so we may
1358 maintain just lower part of scalar values in proper format leaving the
1359 upper part undefined. */
1362 /* X86_TUNE_SSE_TYPELESS_STORES */
1365 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1366 m_PPRO | m_PENT4 | m_NOCONA,
1368 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1369 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1371 /* X86_TUNE_PROLOGUE_USING_MOVE */
1372 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1374 /* X86_TUNE_EPILOGUE_USING_MOVE */
1375 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1377 /* X86_TUNE_SHIFT1 */
1380 /* X86_TUNE_USE_FFREEP */
1383 /* X86_TUNE_INTER_UNIT_MOVES */
1384 ~(m_AMD_MULTIPLE | m_GENERIC),
1386 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1389 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1390 than 4 branch instructions in the 16 byte window. */
1391 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1393 /* X86_TUNE_SCHEDULE */
1394 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1396 /* X86_TUNE_USE_BT */
1397 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1399 /* X86_TUNE_USE_INCDEC */
1400 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1402 /* X86_TUNE_PAD_RETURNS */
1403 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1405 /* X86_TUNE_EXT_80387_CONSTANTS */
1406 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1408 /* X86_TUNE_SHORTEN_X87_SSE */
1411 /* X86_TUNE_AVOID_VECTOR_DECODE */
1414 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1415 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1418 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1419 vector path on AMD machines. */
1420 m_K8 | m_GENERIC64 | m_AMDFAM10,
1422 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1424 m_K8 | m_GENERIC64 | m_AMDFAM10,
1426 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1430 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1431 but one byte longer. */
1434 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1435 operand that cannot be represented using a modRM byte. The XOR
1436 replacement is long decoded, so this split helps here as well. */
1439 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1440 from integer to FP. */
1443 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1444 with a subsequent conditional jump instruction into a single
1445 compare-and-branch uop. */
1449 /* Feature tests against the various architecture variations. */
1450 unsigned char ix86_arch_features[X86_ARCH_LAST];
1452 /* Feature tests against the various architecture variations, used to create
1453 ix86_arch_features based on the processor mask. */
1454 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1455 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1456 ~(m_386 | m_486 | m_PENT | m_K6),
1458 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1461 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1464 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1467 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1471 static const unsigned int x86_accumulate_outgoing_args
1472 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1474 static const unsigned int x86_arch_always_fancy_math_387
1475 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1476 | m_NOCONA | m_CORE2 | m_GENERIC;
1478 static enum stringop_alg stringop_alg = no_stringop;
1480 /* In case the average insn count for single function invocation is
1481 lower than this constant, emit fast (but longer) prologue and
1483 #define FAST_PROLOGUE_INSN_COUNT 20
1485 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1486 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1487 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1488 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1490 /* Array of the smallest class containing reg number REGNO, indexed by
1491 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1493 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1495 /* ax, dx, cx, bx */
1496 AREG, DREG, CREG, BREG,
1497 /* si, di, bp, sp */
1498 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1500 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1501 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1504 /* flags, fpsr, fpcr, frame */
1505 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1507 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1510 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1513 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1514 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1515 /* SSE REX registers */
1516 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1520 /* The "default" register map used in 32bit mode. */
1522 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1524 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1525 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1526 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1527 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1528 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1529 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1530 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1533 static int const x86_64_int_parameter_registers[6] =
1535 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1536 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1539 static int const x86_64_ms_abi_int_parameter_registers[4] =
1541 2 /*RCX*/, 1 /*RDX*/,
1542 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1545 static int const x86_64_int_return_registers[4] =
1547 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1550 /* The "default" register map used in 64bit mode. */
1551 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1553 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1554 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1555 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1556 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1557 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1558 8,9,10,11,12,13,14,15, /* extended integer registers */
1559 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1562 /* Define the register numbers to be used in Dwarf debugging information.
1563 The SVR4 reference port C compiler uses the following register numbers
1564 in its Dwarf output code:
1565 0 for %eax (gcc regno = 0)
1566 1 for %ecx (gcc regno = 2)
1567 2 for %edx (gcc regno = 1)
1568 3 for %ebx (gcc regno = 3)
1569 4 for %esp (gcc regno = 7)
1570 5 for %ebp (gcc regno = 6)
1571 6 for %esi (gcc regno = 4)
1572 7 for %edi (gcc regno = 5)
1573 The following three DWARF register numbers are never generated by
1574 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1575 believes these numbers have these meanings.
1576 8 for %eip (no gcc equivalent)
1577 9 for %eflags (gcc regno = 17)
1578 10 for %trapno (no gcc equivalent)
1579 It is not at all clear how we should number the FP stack registers
1580 for the x86 architecture. If the version of SDB on x86/svr4 were
1581 a bit less brain dead with respect to floating-point then we would
1582 have a precedent to follow with respect to DWARF register numbers
1583 for x86 FP registers, but the SDB on x86/svr4 is so completely
1584 broken with respect to FP registers that it is hardly worth thinking
1585 of it as something to strive for compatibility with.
1586 The version of x86/svr4 SDB I have at the moment does (partially)
1587 seem to believe that DWARF register number 11 is associated with
1588 the x86 register %st(0), but that's about all. Higher DWARF
1589 register numbers don't seem to be associated with anything in
1590 particular, and even for DWARF regno 11, SDB only seems to under-
1591 stand that it should say that a variable lives in %st(0) (when
1592 asked via an `=' command) if we said it was in DWARF regno 11,
1593 but SDB still prints garbage when asked for the value of the
1594 variable in question (via a `/' command).
1595 (Also note that the labels SDB prints for various FP stack regs
1596 when doing an `x' command are all wrong.)
1597 Note that these problems generally don't affect the native SVR4
1598 C compiler because it doesn't allow the use of -O with -g and
1599 because when it is *not* optimizing, it allocates a memory
1600 location for each floating-point variable, and the memory
1601 location is what gets described in the DWARF AT_location
1602 attribute for the variable in question.
1603 Regardless of the severe mental illness of the x86/svr4 SDB, we
1604 do something sensible here and we use the following DWARF
1605 register numbers. Note that these are all stack-top-relative
1607 11 for %st(0) (gcc regno = 8)
1608 12 for %st(1) (gcc regno = 9)
1609 13 for %st(2) (gcc regno = 10)
1610 14 for %st(3) (gcc regno = 11)
1611 15 for %st(4) (gcc regno = 12)
1612 16 for %st(5) (gcc regno = 13)
1613 17 for %st(6) (gcc regno = 14)
1614 18 for %st(7) (gcc regno = 15)
1616 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1618 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1619 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1620 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1621 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1622 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1623 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1624 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1627 /* Test and compare insns in i386.md store the information needed to
1628 generate branch and scc insns here. */
1630 rtx ix86_compare_op0 = NULL_RTX;
1631 rtx ix86_compare_op1 = NULL_RTX;
1632 rtx ix86_compare_emitted = NULL_RTX;
1634 /* Size of the register save area. */
1635 #define X86_64_VARARGS_SIZE (X86_64_REGPARM_MAX * UNITS_PER_WORD + X86_64_SSE_REGPARM_MAX * 16)
1637 /* Define the structure for the machine field in struct function. */
1639 struct stack_local_entry GTY(())
1641 unsigned short mode;
1644 struct stack_local_entry *next;
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1660 [va_arg registers] (
1661 > to_allocate <- FRAME_POINTER
1671 HOST_WIDE_INT frame;
1673 int outgoing_arguments_size;
1676 HOST_WIDE_INT to_allocate;
1677 /* The offsets relative to ARG_POINTER. */
1678 HOST_WIDE_INT frame_pointer_offset;
1679 HOST_WIDE_INT hard_frame_pointer_offset;
1680 HOST_WIDE_INT stack_pointer_offset;
1682 /* When save_regs_using_mov is set, emit prologue using
1683 move instead of push instructions. */
1684 bool save_regs_using_mov;
1687 /* Code model option. */
1688 enum cmodel ix86_cmodel;
1690 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1692 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1694 /* Which unit we are generating floating point math for. */
1695 enum fpmath_unit ix86_fpmath;
1697 /* Which cpu are we scheduling for. */
1698 enum processor_type ix86_tune;
1700 /* Which instruction set architecture to use. */
1701 enum processor_type ix86_arch;
1703 /* true if sse prefetch instruction is not NOOP. */
1704 int x86_prefetch_sse;
1706 /* ix86_regparm_string as a number */
1707 static int ix86_regparm;
1709 /* -mstackrealign option */
1710 extern int ix86_force_align_arg_pointer;
1711 static const char ix86_force_align_arg_pointer_string[]
1712 = "force_align_arg_pointer";
1714 static rtx (*ix86_gen_leave) (void);
1715 static rtx (*ix86_gen_pop1) (rtx);
1716 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1717 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1718 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1719 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1720 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1721 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1723 /* Preferred alignment for stack boundary in bits. */
1724 unsigned int ix86_preferred_stack_boundary;
1726 /* Alignment for incoming stack boundary in bits specified at
1728 static unsigned int ix86_user_incoming_stack_boundary;
1730 /* Default alignment for incoming stack boundary in bits. */
1731 static unsigned int ix86_default_incoming_stack_boundary;
1733 /* Alignment for incoming stack boundary in bits. */
1734 unsigned int ix86_incoming_stack_boundary;
1736 /* Values 1-5: see jump.c */
1737 int ix86_branch_cost;
1739 /* Calling abi specific va_list type nodes. */
1740 static GTY(()) tree sysv_va_list_type_node;
1741 static GTY(()) tree ms_va_list_type_node;
1743 /* Variables which are this size or smaller are put in the data/bss
1744 or ldata/lbss sections. */
1746 int ix86_section_threshold = 65536;
1748 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1749 char internal_label_prefix[16];
1750 int internal_label_prefix_len;
1752 /* Fence to use after loop using movnt. */
1755 /* Register class used for passing given 64bit part of the argument.
1756 These represent classes as documented by the PS ABI, with the exception
1757 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1758 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1760 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1761 whenever possible (upper half does contain padding). */
1762 enum x86_64_reg_class
1765 X86_64_INTEGER_CLASS,
1766 X86_64_INTEGERSI_CLASS,
1773 X86_64_COMPLEX_X87_CLASS,
1776 static const char * const x86_64_reg_class_name[] =
1778 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1779 "sseup", "x87", "x87up", "cplx87", "no"
1782 #define MAX_CLASSES 4
1784 /* Table of constants used by fldpi, fldln2, etc.... */
1785 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1786 static bool ext_80387_constants_init = 0;
1789 static struct machine_function * ix86_init_machine_status (void);
1790 static rtx ix86_function_value (const_tree, const_tree, bool);
1791 static int ix86_function_regparm (const_tree, const_tree);
1792 static void ix86_compute_frame_layout (struct ix86_frame *);
1793 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1796 enum ix86_function_specific_strings
1798 IX86_FUNCTION_SPECIFIC_ARCH,
1799 IX86_FUNCTION_SPECIFIC_TUNE,
1800 IX86_FUNCTION_SPECIFIC_FPMATH,
1801 IX86_FUNCTION_SPECIFIC_MAX
1804 static char *ix86_target_string (int, int, const char *, const char *,
1805 const char *, bool);
1806 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1807 static void ix86_function_specific_save (struct cl_target_option *);
1808 static void ix86_function_specific_restore (struct cl_target_option *);
1809 static void ix86_function_specific_print (FILE *, int,
1810 struct cl_target_option *);
1811 static bool ix86_valid_option_attribute_p (tree, tree, tree, int);
1812 static bool ix86_valid_option_attribute_inner_p (tree, char *[]);
1813 static bool ix86_can_inline_p (tree, tree);
1814 static void ix86_set_current_function (tree);
1817 /* The svr4 ABI for the i386 says that records and unions are returned
1819 #ifndef DEFAULT_PCC_STRUCT_RETURN
1820 #define DEFAULT_PCC_STRUCT_RETURN 1
1823 /* Whether -mtune= or -march= were specified */
1824 static int ix86_tune_defaulted;
1825 static int ix86_arch_specified;
1827 /* Bit flags that specify the ISA we are compiling for. */
1828 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1830 /* A mask of ix86_isa_flags that includes bit X if X
1831 was set or cleared on the command line. */
1832 static int ix86_isa_flags_explicit;
1834 /* Define a set of ISAs which are available when a given ISA is
1835 enabled. MMX and SSE ISAs are handled separately. */
1837 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1838 #define OPTION_MASK_ISA_3DNOW_SET \
1839 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1841 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1842 #define OPTION_MASK_ISA_SSE2_SET \
1843 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1844 #define OPTION_MASK_ISA_SSE3_SET \
1845 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1846 #define OPTION_MASK_ISA_SSSE3_SET \
1847 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1848 #define OPTION_MASK_ISA_SSE4_1_SET \
1849 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1850 #define OPTION_MASK_ISA_SSE4_2_SET \
1851 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1853 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1855 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1857 #define OPTION_MASK_ISA_SSE4A_SET \
1858 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1859 #define OPTION_MASK_ISA_SSE5_SET \
1860 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1862 /* AES and PCLMUL need SSE2 because they use xmm registers */
1863 #define OPTION_MASK_ISA_AES_SET \
1864 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1865 #define OPTION_MASK_ISA_PCLMUL_SET \
1866 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1868 #define OPTION_MASK_ISA_ABM_SET \
1869 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1870 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1871 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1872 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1874 /* Define a set of ISAs which aren't available when a given ISA is
1875 disabled. MMX and SSE ISAs are handled separately. */
1877 #define OPTION_MASK_ISA_MMX_UNSET \
1878 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1879 #define OPTION_MASK_ISA_3DNOW_UNSET \
1880 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1881 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1883 #define OPTION_MASK_ISA_SSE_UNSET \
1884 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1885 #define OPTION_MASK_ISA_SSE2_UNSET \
1886 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1887 #define OPTION_MASK_ISA_SSE3_UNSET \
1888 (OPTION_MASK_ISA_SSE3 \
1889 | OPTION_MASK_ISA_SSSE3_UNSET \
1890 | OPTION_MASK_ISA_SSE4A_UNSET )
1891 #define OPTION_MASK_ISA_SSSE3_UNSET \
1892 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1893 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1894 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1895 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1897 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1899 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1901 #define OPTION_MASK_ISA_SSE4A_UNSET \
1902 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1903 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1904 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1905 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1906 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1907 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1908 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1909 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1911 /* Vectorization library interface and handlers. */
1912 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1913 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1914 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1916 /* Processor target table, indexed by processor number */
1919 const struct processor_costs *cost; /* Processor costs */
1920 const int align_loop; /* Default alignments. */
1921 const int align_loop_max_skip;
1922 const int align_jump;
1923 const int align_jump_max_skip;
1924 const int align_func;
1927 static const struct ptt processor_target_table[PROCESSOR_max] =
1929 {&i386_cost, 4, 3, 4, 3, 4},
1930 {&i486_cost, 16, 15, 16, 15, 16},
1931 {&pentium_cost, 16, 7, 16, 7, 16},
1932 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1933 {&geode_cost, 0, 0, 0, 0, 0},
1934 {&k6_cost, 32, 7, 32, 7, 32},
1935 {&athlon_cost, 16, 7, 16, 7, 16},
1936 {&pentium4_cost, 0, 0, 0, 0, 0},
1937 {&k8_cost, 16, 7, 16, 7, 16},
1938 {&nocona_cost, 0, 0, 0, 0, 0},
1939 {&core2_cost, 16, 10, 16, 10, 16},
1940 {&generic32_cost, 16, 7, 16, 7, 16},
1941 {&generic64_cost, 16, 10, 16, 10, 16},
1942 {&amdfam10_cost, 32, 24, 32, 7, 32}
1945 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1970 /* Implement TARGET_HANDLE_OPTION. */
1973 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1980 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1981 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1985 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1986 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1993 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1994 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1998 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1999 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2009 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2010 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2014 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2015 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2022 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2023 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2027 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2028 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2035 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2036 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2040 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2041 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2048 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2049 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2053 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2054 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2061 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2062 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2066 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2067 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2074 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2075 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2079 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2080 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2085 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2086 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2090 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2091 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2097 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2098 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2102 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2103 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2110 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2111 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2115 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2116 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2123 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2124 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2128 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2203 /* Return a string the documents the current -m options. The caller is
2204 responsible for freeing the string. */
2207 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2208 const char *fpmath, bool add_nl_p)
2210 struct ix86_target_opts
2212 const char *option; /* option string */
2213 int mask; /* isa mask options */
2216 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2217 preceding options while match those first. */
2218 static struct ix86_target_opts isa_opts[] =
2220 { "-m64", OPTION_MASK_ISA_64BIT },
2221 { "-msse5", OPTION_MASK_ISA_SSE5 },
2222 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2223 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2224 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2225 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2226 { "-msse3", OPTION_MASK_ISA_SSE3 },
2227 { "-msse2", OPTION_MASK_ISA_SSE2 },
2228 { "-msse", OPTION_MASK_ISA_SSE },
2229 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2230 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2231 { "-mmmx", OPTION_MASK_ISA_MMX },
2232 { "-mabm", OPTION_MASK_ISA_ABM },
2233 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2234 { "-maes", OPTION_MASK_ISA_AES },
2235 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2239 static struct ix86_target_opts flag_opts[] =
2241 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2242 { "-m80387", MASK_80387 },
2243 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2244 { "-malign-double", MASK_ALIGN_DOUBLE },
2245 { "-mcld", MASK_CLD },
2246 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2247 { "-mieee-fp", MASK_IEEE_FP },
2248 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2249 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2250 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2251 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2252 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2253 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2254 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2255 { "-mno-red-zone", MASK_NO_RED_ZONE },
2256 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2257 { "-mrecip", MASK_RECIP },
2258 { "-mrtd", MASK_RTD },
2259 { "-msseregparm", MASK_SSEREGPARM },
2260 { "-mstack-arg-probe", MASK_STACK_PROBE },
2261 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2264 const char *opts[ (sizeof (isa_opts) / sizeof (isa_opts[0])
2265 + sizeof (flag_opts) / sizeof (flag_opts[0])
2269 char target_other[40];
2278 memset (opts, '\0', sizeof (opts));
2280 /* Add -march= option. */
2283 opts[num][0] = "-march=";
2284 opts[num++][1] = arch;
2287 /* Add -mtune= option. */
2290 opts[num][0] = "-mtune=";
2291 opts[num++][1] = tune;
2294 /* Pick out the options in isa options. */
2295 for (i = 0; i < sizeof (isa_opts) / sizeof (isa_opts[0]); i++)
2297 if ((isa & isa_opts[i].mask) != 0)
2299 opts[num++][0] = isa_opts[i].option;
2300 isa &= ~ isa_opts[i].mask;
2304 if (isa && add_nl_p)
2306 opts[num++][0] = isa_other;
2307 sprintf (isa_other, "(other isa: 0x%x)", isa);
2310 /* Add flag options. */
2311 for (i = 0; i < sizeof (flag_opts) / sizeof (flag_opts[0]); i++)
2313 if ((flags & flag_opts[i].mask) != 0)
2315 opts[num++][0] = flag_opts[i].option;
2316 flags &= ~ flag_opts[i].mask;
2320 if (flags && add_nl_p)
2322 opts[num++][0] = target_other;
2323 sprintf (target_other, "(other flags: 0x%x)", isa);
2326 /* Add -fpmath= option. */
2329 opts[num][0] = "-mfpmath=";
2330 opts[num++][1] = fpmath;
2337 gcc_assert (num < sizeof (opts) / sizeof (opts[0]));
2339 /* Size the string. */
2341 sep_len = (add_nl_p) ? 3 : 1;
2342 for (i = 0; i < num; i++)
2345 for (j = 0; j < 2; j++)
2347 len += strlen (opts[i][j]);
2350 /* Build the string. */
2351 ret = ptr = (char *) xmalloc (len);
2354 for (i = 0; i < num; i++)
2358 for (j = 0; j < 2; j++)
2359 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2366 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2374 for (j = 0; j < 2; j++)
2377 memcpy (ptr, opts[i][j], len2[j]);
2379 line_len += len2[j];
2384 gcc_assert (ret + len >= ptr);
2389 /* Function that is callable from the debugger to print the current
2392 ix86_debug_options (void)
2394 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2395 ix86_arch_string, ix86_tune_string,
2396 ix86_fpmath_string, true);
2400 fprintf (stderr, "%s\n\n", opts);
2404 fprintf (stderr, "<no options>\n\n");
2409 /* Sometimes certain combinations of command options do not make
2410 sense on a particular target machine. You can define a macro
2411 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2412 defined, is executed once just after all the command options have
2415 Don't use this macro to turn on various extra optimizations for
2416 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2419 override_options (bool main_args_p)
2422 unsigned int ix86_arch_mask, ix86_tune_mask;
2427 /* Comes from final.c -- no real reason to change it. */
2428 #define MAX_CODE_ALIGN 16
2436 PTA_PREFETCH_SSE = 1 << 4,
2438 PTA_3DNOW_A = 1 << 6,
2442 PTA_POPCNT = 1 << 10,
2444 PTA_SSE4A = 1 << 12,
2445 PTA_NO_SAHF = 1 << 13,
2446 PTA_SSE4_1 = 1 << 14,
2447 PTA_SSE4_2 = 1 << 15,
2450 PTA_PCLMUL = 1 << 18
2455 const char *const name; /* processor name or nickname. */
2456 const enum processor_type processor;
2457 const unsigned /*enum pta_flags*/ flags;
2459 const processor_alias_table[] =
2461 {"i386", PROCESSOR_I386, 0},
2462 {"i486", PROCESSOR_I486, 0},
2463 {"i586", PROCESSOR_PENTIUM, 0},
2464 {"pentium", PROCESSOR_PENTIUM, 0},
2465 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2466 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2467 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2468 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2469 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2470 {"i686", PROCESSOR_PENTIUMPRO, 0},
2471 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2472 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2473 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2474 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2475 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2476 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2477 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2478 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2479 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2480 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2481 | PTA_CX16 | PTA_NO_SAHF)},
2482 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2483 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2486 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2487 |PTA_PREFETCH_SSE)},
2488 {"k6", PROCESSOR_K6, PTA_MMX},
2489 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2490 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2491 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2492 | PTA_PREFETCH_SSE)},
2493 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2494 | PTA_PREFETCH_SSE)},
2495 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2497 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2499 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2501 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2502 | PTA_MMX | PTA_SSE | PTA_SSE2
2504 {"k8", PROCESSOR_K8, (PTA_64BIT
2505 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2506 | PTA_SSE | PTA_SSE2
2508 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2509 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2510 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2512 {"opteron", PROCESSOR_K8, (PTA_64BIT
2513 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2514 | PTA_SSE | PTA_SSE2
2516 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2517 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2518 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2520 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2521 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2522 | PTA_SSE | PTA_SSE2
2524 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2525 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2526 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2529 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2530 | PTA_SSE | PTA_SSE2
2532 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2533 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2534 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2536 | PTA_CX16 | PTA_ABM)},
2537 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2538 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2539 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2541 | PTA_CX16 | PTA_ABM)},
2542 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2543 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2546 int const pta_size = ARRAY_SIZE (processor_alias_table);
2548 /* Set up prefix/suffix so the error messages refer to either the command
2549 line argument, or the attribute(option). */
2558 prefix = "option(\"";
2563 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2564 SUBTARGET_OVERRIDE_OPTIONS;
2567 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2568 SUBSUBTARGET_OVERRIDE_OPTIONS;
2571 /* -fPIC is the default for x86_64. */
2572 if (TARGET_MACHO && TARGET_64BIT)
2575 /* Set the default values for switches whose default depends on TARGET_64BIT
2576 in case they weren't overwritten by command line options. */
2579 /* Mach-O doesn't support omitting the frame pointer for now. */
2580 if (flag_omit_frame_pointer == 2)
2581 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2582 if (flag_asynchronous_unwind_tables == 2)
2583 flag_asynchronous_unwind_tables = 1;
2584 if (flag_pcc_struct_return == 2)
2585 flag_pcc_struct_return = 0;
2589 if (flag_omit_frame_pointer == 2)
2590 flag_omit_frame_pointer = 0;
2591 if (flag_asynchronous_unwind_tables == 2)
2592 flag_asynchronous_unwind_tables = 0;
2593 if (flag_pcc_struct_return == 2)
2594 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2597 /* Need to check -mtune=generic first. */
2598 if (ix86_tune_string)
2600 if (!strcmp (ix86_tune_string, "generic")
2601 || !strcmp (ix86_tune_string, "i686")
2602 /* As special support for cross compilers we read -mtune=native
2603 as -mtune=generic. With native compilers we won't see the
2604 -mtune=native, as it was changed by the driver. */
2605 || !strcmp (ix86_tune_string, "native"))
2608 ix86_tune_string = "generic64";
2610 ix86_tune_string = "generic32";
2612 /* If this call is for setting the option attribute, allow the
2613 generic32/generic64 that was previously set. */
2614 else if (!main_args_p
2615 && (!strcmp (ix86_tune_string, "generic32")
2616 || !strcmp (ix86_tune_string, "generic64")))
2618 else if (!strncmp (ix86_tune_string, "generic", 7))
2619 error ("bad value (%s) for %stune=%s %s",
2620 ix86_tune_string, prefix, suffix, sw);
2624 if (ix86_arch_string)
2625 ix86_tune_string = ix86_arch_string;
2626 if (!ix86_tune_string)
2628 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2629 ix86_tune_defaulted = 1;
2632 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2633 need to use a sensible tune option. */
2634 if (!strcmp (ix86_tune_string, "generic")
2635 || !strcmp (ix86_tune_string, "x86-64")
2636 || !strcmp (ix86_tune_string, "i686"))
2639 ix86_tune_string = "generic64";
2641 ix86_tune_string = "generic32";
2644 if (ix86_stringop_string)
2646 if (!strcmp (ix86_stringop_string, "rep_byte"))
2647 stringop_alg = rep_prefix_1_byte;
2648 else if (!strcmp (ix86_stringop_string, "libcall"))
2649 stringop_alg = libcall;
2650 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2651 stringop_alg = rep_prefix_4_byte;
2652 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2653 stringop_alg = rep_prefix_8_byte;
2654 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2655 stringop_alg = loop_1_byte;
2656 else if (!strcmp (ix86_stringop_string, "loop"))
2657 stringop_alg = loop;
2658 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2659 stringop_alg = unrolled_loop;
2661 error ("bad value (%s) for %sstringop-strategy=%s %s",
2662 ix86_stringop_string, prefix, suffix, sw);
2664 if (!strcmp (ix86_tune_string, "x86-64"))
2665 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2666 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2667 prefix, suffix, prefix, suffix, prefix, suffix);
2669 if (!ix86_arch_string)
2670 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2672 ix86_arch_specified = 1;
2674 if (!strcmp (ix86_arch_string, "generic"))
2675 error ("generic CPU can be used only for %stune=%s %s",
2676 prefix, suffix, sw);
2677 if (!strncmp (ix86_arch_string, "generic", 7))
2678 error ("bad value (%s) for %sarch=%s %s",
2679 ix86_arch_string, prefix, suffix, sw);
2681 if (ix86_cmodel_string != 0)
2683 if (!strcmp (ix86_cmodel_string, "small"))
2684 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2685 else if (!strcmp (ix86_cmodel_string, "medium"))
2686 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2687 else if (!strcmp (ix86_cmodel_string, "large"))
2688 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2690 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2691 else if (!strcmp (ix86_cmodel_string, "32"))
2692 ix86_cmodel = CM_32;
2693 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2694 ix86_cmodel = CM_KERNEL;
2696 error ("bad value (%s) for %scmodel=%s %s",
2697 ix86_cmodel_string, prefix, suffix, sw);
2701 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2702 use of rip-relative addressing. This eliminates fixups that
2703 would otherwise be needed if this object is to be placed in a
2704 DLL, and is essentially just as efficient as direct addressing. */
2705 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2706 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2707 else if (TARGET_64BIT)
2708 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2710 ix86_cmodel = CM_32;
2712 if (ix86_asm_string != 0)
2715 && !strcmp (ix86_asm_string, "intel"))
2716 ix86_asm_dialect = ASM_INTEL;
2717 else if (!strcmp (ix86_asm_string, "att"))
2718 ix86_asm_dialect = ASM_ATT;
2720 error ("bad value (%s) for %sasm=%s %s",
2721 ix86_asm_string, prefix, suffix, sw);
2723 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2724 error ("code model %qs not supported in the %s bit mode",
2725 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2726 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2727 sorry ("%i-bit mode not compiled in",
2728 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2730 for (i = 0; i < pta_size; i++)
2731 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2733 ix86_arch = processor_alias_table[i].processor;
2734 /* Default cpu tuning to the architecture. */
2735 ix86_tune = ix86_arch;
2737 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2738 error ("CPU you selected does not support x86-64 "
2741 if (processor_alias_table[i].flags & PTA_MMX
2742 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2743 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2744 if (processor_alias_table[i].flags & PTA_3DNOW
2745 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2746 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2747 if (processor_alias_table[i].flags & PTA_3DNOW_A
2748 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2749 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2750 if (processor_alias_table[i].flags & PTA_SSE
2751 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2752 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2753 if (processor_alias_table[i].flags & PTA_SSE2
2754 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2755 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2756 if (processor_alias_table[i].flags & PTA_SSE3
2757 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2758 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2759 if (processor_alias_table[i].flags & PTA_SSSE3
2760 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2761 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2762 if (processor_alias_table[i].flags & PTA_SSE4_1
2763 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2764 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2765 if (processor_alias_table[i].flags & PTA_SSE4_2
2766 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2767 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2768 if (processor_alias_table[i].flags & PTA_SSE4A
2769 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2770 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2771 if (processor_alias_table[i].flags & PTA_SSE5
2772 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2773 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2774 if (processor_alias_table[i].flags & PTA_ABM
2775 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2776 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2777 if (processor_alias_table[i].flags & PTA_CX16
2778 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2779 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2780 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2782 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2783 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2785 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2786 if (processor_alias_table[i].flags & PTA_AES
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2788 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2789 if (processor_alias_table[i].flags & PTA_PCLMUL
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2791 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2792 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2793 x86_prefetch_sse = true;
2799 error ("bad value (%s) for %sarch=%s %s",
2800 ix86_arch_string, prefix, suffix, sw);
2802 ix86_arch_mask = 1u << ix86_arch;
2803 for (i = 0; i < X86_ARCH_LAST; ++i)
2804 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2806 for (i = 0; i < pta_size; i++)
2807 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2809 ix86_tune = processor_alias_table[i].processor;
2810 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2812 if (ix86_tune_defaulted)
2814 ix86_tune_string = "x86-64";
2815 for (i = 0; i < pta_size; i++)
2816 if (! strcmp (ix86_tune_string,
2817 processor_alias_table[i].name))
2819 ix86_tune = processor_alias_table[i].processor;
2822 error ("CPU you selected does not support x86-64 "
2825 /* Intel CPUs have always interpreted SSE prefetch instructions as
2826 NOPs; so, we can enable SSE prefetch instructions even when
2827 -mtune (rather than -march) points us to a processor that has them.
2828 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2829 higher processors. */
2831 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
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