1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static int ix86_function_regparm (const_tree, const_tree);
1883 static void ix86_compute_frame_layout (struct ix86_frame *);
1884 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1886 static void ix86_add_new_builtins (int);
1888 enum ix86_function_specific_strings
1890 IX86_FUNCTION_SPECIFIC_ARCH,
1891 IX86_FUNCTION_SPECIFIC_TUNE,
1892 IX86_FUNCTION_SPECIFIC_FPMATH,
1893 IX86_FUNCTION_SPECIFIC_MAX
1896 static char *ix86_target_string (int, int, const char *, const char *,
1897 const char *, bool);
1898 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1899 static void ix86_function_specific_save (struct cl_target_option *);
1900 static void ix86_function_specific_restore (struct cl_target_option *);
1901 static void ix86_function_specific_print (FILE *, int,
1902 struct cl_target_option *);
1903 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1904 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1905 static bool ix86_can_inline_p (tree, tree);
1906 static void ix86_set_current_function (tree);
1908 static enum calling_abi ix86_function_abi (const_tree);
1911 /* The svr4 ABI for the i386 says that records and unions are returned
1913 #ifndef DEFAULT_PCC_STRUCT_RETURN
1914 #define DEFAULT_PCC_STRUCT_RETURN 1
1917 /* Whether -mtune= or -march= were specified */
1918 static int ix86_tune_defaulted;
1919 static int ix86_arch_specified;
1921 /* Bit flags that specify the ISA we are compiling for. */
1922 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1924 /* A mask of ix86_isa_flags that includes bit X if X
1925 was set or cleared on the command line. */
1926 static int ix86_isa_flags_explicit;
1928 /* Define a set of ISAs which are available when a given ISA is
1929 enabled. MMX and SSE ISAs are handled separately. */
1931 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1932 #define OPTION_MASK_ISA_3DNOW_SET \
1933 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1935 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1936 #define OPTION_MASK_ISA_SSE2_SET \
1937 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1938 #define OPTION_MASK_ISA_SSE3_SET \
1939 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1940 #define OPTION_MASK_ISA_SSSE3_SET \
1941 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1942 #define OPTION_MASK_ISA_SSE4_1_SET \
1943 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_2_SET \
1945 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1946 #define OPTION_MASK_ISA_AVX_SET \
1947 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1948 #define OPTION_MASK_ISA_FMA_SET \
1949 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1951 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1953 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1955 #define OPTION_MASK_ISA_SSE4A_SET \
1956 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1958 /* AES and PCLMUL need SSE2 because they use xmm registers */
1959 #define OPTION_MASK_ISA_AES_SET \
1960 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1961 #define OPTION_MASK_ISA_PCLMUL_SET \
1962 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1964 #define OPTION_MASK_ISA_ABM_SET \
1965 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1967 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1968 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1969 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1970 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1971 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1973 /* Define a set of ISAs which aren't available when a given ISA is
1974 disabled. MMX and SSE ISAs are handled separately. */
1976 #define OPTION_MASK_ISA_MMX_UNSET \
1977 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1978 #define OPTION_MASK_ISA_3DNOW_UNSET \
1979 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1980 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1982 #define OPTION_MASK_ISA_SSE_UNSET \
1983 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1984 #define OPTION_MASK_ISA_SSE2_UNSET \
1985 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1986 #define OPTION_MASK_ISA_SSE3_UNSET \
1987 (OPTION_MASK_ISA_SSE3 \
1988 | OPTION_MASK_ISA_SSSE3_UNSET \
1989 | OPTION_MASK_ISA_SSE4A_UNSET )
1990 #define OPTION_MASK_ISA_SSSE3_UNSET \
1991 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1992 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1993 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1994 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1995 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1996 #define OPTION_MASK_ISA_AVX_UNSET \
1997 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1998 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2000 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2002 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2004 #define OPTION_MASK_ISA_SSE4A_UNSET \
2005 (OPTION_MASK_ISA_SSE4A)
2006 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2007 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2008 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2009 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2010 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2011 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2012 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2013 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2015 /* Vectorization library interface and handlers. */
2016 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2017 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2018 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2020 /* Processor target table, indexed by processor number */
2023 const struct processor_costs *cost; /* Processor costs */
2024 const int align_loop; /* Default alignments. */
2025 const int align_loop_max_skip;
2026 const int align_jump;
2027 const int align_jump_max_skip;
2028 const int align_func;
2031 static const struct ptt processor_target_table[PROCESSOR_max] =
2033 {&i386_cost, 4, 3, 4, 3, 4},
2034 {&i486_cost, 16, 15, 16, 15, 16},
2035 {&pentium_cost, 16, 7, 16, 7, 16},
2036 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2037 {&geode_cost, 0, 0, 0, 0, 0},
2038 {&k6_cost, 32, 7, 32, 7, 32},
2039 {&athlon_cost, 16, 7, 16, 7, 16},
2040 {&pentium4_cost, 0, 0, 0, 0, 0},
2041 {&k8_cost, 16, 7, 16, 7, 16},
2042 {&nocona_cost, 0, 0, 0, 0, 0},
2043 {&core2_cost, 16, 10, 16, 10, 16},
2044 {&generic32_cost, 16, 7, 16, 7, 16},
2045 {&generic64_cost, 16, 10, 16, 10, 16},
2046 {&amdfam10_cost, 32, 24, 32, 7, 32},
2047 {&atom_cost, 16, 7, 16, 7, 16}
2050 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2076 /* Implement TARGET_HANDLE_OPTION. */
2079 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2086 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2087 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2091 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2092 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2099 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2100 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2104 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2105 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2115 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2116 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2120 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2121 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2128 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2133 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2134 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2141 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2146 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2147 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2154 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2159 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2160 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2167 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2172 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2173 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2180 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2185 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2186 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2193 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2198 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2199 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2206 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2211 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2212 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2217 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2218 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2222 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2223 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2229 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2230 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2234 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2235 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2242 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2243 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2247 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2248 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2255 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2260 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2261 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2268 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2273 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2274 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2281 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2286 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2287 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2294 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2299 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2300 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2307 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2312 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2313 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2320 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2325 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2326 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2333 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2338 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2339 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2348 /* Return a string the documents the current -m options. The caller is
2349 responsible for freeing the string. */
2352 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2353 const char *fpmath, bool add_nl_p)
2355 struct ix86_target_opts
2357 const char *option; /* option string */
2358 int mask; /* isa mask options */
2361 /* This table is ordered so that options like -msse4.2 that imply
2362 preceding options while match those first. */
2363 static struct ix86_target_opts isa_opts[] =
2365 { "-m64", OPTION_MASK_ISA_64BIT },
2366 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2367 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2368 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2369 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2370 { "-msse3", OPTION_MASK_ISA_SSE3 },
2371 { "-msse2", OPTION_MASK_ISA_SSE2 },
2372 { "-msse", OPTION_MASK_ISA_SSE },
2373 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2374 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2375 { "-mmmx", OPTION_MASK_ISA_MMX },
2376 { "-mabm", OPTION_MASK_ISA_ABM },
2377 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2378 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2379 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2380 { "-maes", OPTION_MASK_ISA_AES },
2381 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2385 static struct ix86_target_opts flag_opts[] =
2387 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2388 { "-m80387", MASK_80387 },
2389 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2390 { "-malign-double", MASK_ALIGN_DOUBLE },
2391 { "-mcld", MASK_CLD },
2392 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2393 { "-mieee-fp", MASK_IEEE_FP },
2394 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2395 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2396 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2397 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2398 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2399 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2400 { "-mno-red-zone", MASK_NO_RED_ZONE },
2401 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2402 { "-mrecip", MASK_RECIP },
2403 { "-mrtd", MASK_RTD },
2404 { "-msseregparm", MASK_SSEREGPARM },
2405 { "-mstack-arg-probe", MASK_STACK_PROBE },
2406 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2409 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2412 char target_other[40];
2421 memset (opts, '\0', sizeof (opts));
2423 /* Add -march= option. */
2426 opts[num][0] = "-march=";
2427 opts[num++][1] = arch;
2430 /* Add -mtune= option. */
2433 opts[num][0] = "-mtune=";
2434 opts[num++][1] = tune;
2437 /* Pick out the options in isa options. */
2438 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2440 if ((isa & isa_opts[i].mask) != 0)
2442 opts[num++][0] = isa_opts[i].option;
2443 isa &= ~ isa_opts[i].mask;
2447 if (isa && add_nl_p)
2449 opts[num++][0] = isa_other;
2450 sprintf (isa_other, "(other isa: 0x%x)", isa);
2453 /* Add flag options. */
2454 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2456 if ((flags & flag_opts[i].mask) != 0)
2458 opts[num++][0] = flag_opts[i].option;
2459 flags &= ~ flag_opts[i].mask;
2463 if (flags && add_nl_p)
2465 opts[num++][0] = target_other;
2466 sprintf (target_other, "(other flags: 0x%x)", isa);
2469 /* Add -fpmath= option. */
2472 opts[num][0] = "-mfpmath=";
2473 opts[num++][1] = fpmath;
2480 gcc_assert (num < ARRAY_SIZE (opts));
2482 /* Size the string. */
2484 sep_len = (add_nl_p) ? 3 : 1;
2485 for (i = 0; i < num; i++)
2488 for (j = 0; j < 2; j++)
2490 len += strlen (opts[i][j]);
2493 /* Build the string. */
2494 ret = ptr = (char *) xmalloc (len);
2497 for (i = 0; i < num; i++)
2501 for (j = 0; j < 2; j++)
2502 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2509 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2517 for (j = 0; j < 2; j++)
2520 memcpy (ptr, opts[i][j], len2[j]);
2522 line_len += len2[j];
2527 gcc_assert (ret + len >= ptr);
2532 /* Function that is callable from the debugger to print the current
2535 ix86_debug_options (void)
2537 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2538 ix86_arch_string, ix86_tune_string,
2539 ix86_fpmath_string, true);
2543 fprintf (stderr, "%s\n\n", opts);
2547 fputs ("<no options>\n\n", stderr);
2552 /* Sometimes certain combinations of command options do not make
2553 sense on a particular target machine. You can define a macro
2554 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2555 defined, is executed once just after all the command options have
2558 Don't use this macro to turn on various extra optimizations for
2559 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2562 override_options (bool main_args_p)
2565 unsigned int ix86_arch_mask, ix86_tune_mask;
2570 /* Comes from final.c -- no real reason to change it. */
2571 #define MAX_CODE_ALIGN 16
2579 PTA_PREFETCH_SSE = 1 << 4,
2581 PTA_3DNOW_A = 1 << 6,
2585 PTA_POPCNT = 1 << 10,
2587 PTA_SSE4A = 1 << 12,
2588 PTA_NO_SAHF = 1 << 13,
2589 PTA_SSE4_1 = 1 << 14,
2590 PTA_SSE4_2 = 1 << 15,
2592 PTA_PCLMUL = 1 << 17,
2600 const char *const name; /* processor name or nickname. */
2601 const enum processor_type processor;
2602 const enum attr_cpu schedule;
2603 const unsigned /*enum pta_flags*/ flags;
2605 const processor_alias_table[] =
2607 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2608 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2609 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2610 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2611 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2612 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2613 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2614 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2615 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2616 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2617 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2618 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2619 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2621 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2623 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2624 PTA_MMX | PTA_SSE | PTA_SSE2},
2625 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2626 PTA_MMX |PTA_SSE | PTA_SSE2},
2627 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2628 PTA_MMX | PTA_SSE | PTA_SSE2},
2629 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2630 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2631 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2632 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2633 | PTA_CX16 | PTA_NO_SAHF},
2634 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2635 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2636 | PTA_SSSE3 | PTA_CX16},
2637 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2638 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2639 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2640 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2641 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2642 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2643 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2644 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2645 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2646 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2647 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2648 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2649 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2650 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2651 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2652 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2653 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2654 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2655 {"x86-64", PROCESSOR_K8, CPU_K8,
2656 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2657 {"k8", PROCESSOR_K8, CPU_K8,
2658 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2659 | PTA_SSE2 | PTA_NO_SAHF},
2660 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2661 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2662 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2663 {"opteron", PROCESSOR_K8, CPU_K8,
2664 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2665 | PTA_SSE2 | PTA_NO_SAHF},
2666 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2667 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2668 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2669 {"athlon64", PROCESSOR_K8, CPU_K8,
2670 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2671 | PTA_SSE2 | PTA_NO_SAHF},
2672 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2673 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2674 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2675 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2676 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2677 | PTA_SSE2 | PTA_NO_SAHF},
2678 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2679 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2680 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2681 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2682 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2683 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2684 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2685 0 /* flags are only used for -march switch. */ },
2686 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2687 PTA_64BIT /* flags are only used for -march switch. */ },
2690 int const pta_size = ARRAY_SIZE (processor_alias_table);
2692 /* Set up prefix/suffix so the error messages refer to either the command
2693 line argument, or the attribute(target). */
2702 prefix = "option(\"";
2707 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2708 SUBTARGET_OVERRIDE_OPTIONS;
2711 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2712 SUBSUBTARGET_OVERRIDE_OPTIONS;
2715 /* -fPIC is the default for x86_64. */
2716 if (TARGET_MACHO && TARGET_64BIT)
2719 /* Set the default values for switches whose default depends on TARGET_64BIT
2720 in case they weren't overwritten by command line options. */
2723 /* Mach-O doesn't support omitting the frame pointer for now. */
2724 if (flag_omit_frame_pointer == 2)
2725 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2726 if (flag_asynchronous_unwind_tables == 2)
2727 flag_asynchronous_unwind_tables = 1;
2728 if (flag_pcc_struct_return == 2)
2729 flag_pcc_struct_return = 0;
2733 if (flag_omit_frame_pointer == 2)
2734 flag_omit_frame_pointer = 0;
2735 if (flag_asynchronous_unwind_tables == 2)
2736 flag_asynchronous_unwind_tables = 0;
2737 if (flag_pcc_struct_return == 2)
2738 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2741 /* Need to check -mtune=generic first. */
2742 if (ix86_tune_string)
2744 if (!strcmp (ix86_tune_string, "generic")
2745 || !strcmp (ix86_tune_string, "i686")
2746 /* As special support for cross compilers we read -mtune=native
2747 as -mtune=generic. With native compilers we won't see the
2748 -mtune=native, as it was changed by the driver. */
2749 || !strcmp (ix86_tune_string, "native"))
2752 ix86_tune_string = "generic64";
2754 ix86_tune_string = "generic32";
2756 /* If this call is for setting the option attribute, allow the
2757 generic32/generic64 that was previously set. */
2758 else if (!main_args_p
2759 && (!strcmp (ix86_tune_string, "generic32")
2760 || !strcmp (ix86_tune_string, "generic64")))
2762 else if (!strncmp (ix86_tune_string, "generic", 7))
2763 error ("bad value (%s) for %stune=%s %s",
2764 ix86_tune_string, prefix, suffix, sw);
2768 if (ix86_arch_string)
2769 ix86_tune_string = ix86_arch_string;
2770 if (!ix86_tune_string)
2772 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2773 ix86_tune_defaulted = 1;
2776 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2777 need to use a sensible tune option. */
2778 if (!strcmp (ix86_tune_string, "generic")
2779 || !strcmp (ix86_tune_string, "x86-64")
2780 || !strcmp (ix86_tune_string, "i686"))
2783 ix86_tune_string = "generic64";
2785 ix86_tune_string = "generic32";
2788 if (ix86_stringop_string)
2790 if (!strcmp (ix86_stringop_string, "rep_byte"))
2791 stringop_alg = rep_prefix_1_byte;
2792 else if (!strcmp (ix86_stringop_string, "libcall"))
2793 stringop_alg = libcall;
2794 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2795 stringop_alg = rep_prefix_4_byte;
2796 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2798 /* rep; movq isn't available in 32-bit code. */
2799 stringop_alg = rep_prefix_8_byte;
2800 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2801 stringop_alg = loop_1_byte;
2802 else if (!strcmp (ix86_stringop_string, "loop"))
2803 stringop_alg = loop;
2804 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2805 stringop_alg = unrolled_loop;
2807 error ("bad value (%s) for %sstringop-strategy=%s %s",
2808 ix86_stringop_string, prefix, suffix, sw);
2810 if (!strcmp (ix86_tune_string, "x86-64"))
2811 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2812 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2813 prefix, suffix, prefix, suffix, prefix, suffix);
2815 if (!ix86_arch_string)
2816 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2818 ix86_arch_specified = 1;
2820 if (!strcmp (ix86_arch_string, "generic"))
2821 error ("generic CPU can be used only for %stune=%s %s",
2822 prefix, suffix, sw);
2823 if (!strncmp (ix86_arch_string, "generic", 7))
2824 error ("bad value (%s) for %sarch=%s %s",
2825 ix86_arch_string, prefix, suffix, sw);
2827 /* Validate -mabi= value. */
2828 if (ix86_abi_string)
2830 if (strcmp (ix86_abi_string, "sysv") == 0)
2831 ix86_abi = SYSV_ABI;
2832 else if (strcmp (ix86_abi_string, "ms") == 0)
2835 error ("unknown ABI (%s) for %sabi=%s %s",
2836 ix86_abi_string, prefix, suffix, sw);
2839 ix86_abi = DEFAULT_ABI;
2841 if (ix86_cmodel_string != 0)
2843 if (!strcmp (ix86_cmodel_string, "small"))
2844 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2845 else if (!strcmp (ix86_cmodel_string, "medium"))
2846 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2847 else if (!strcmp (ix86_cmodel_string, "large"))
2848 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2850 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2851 else if (!strcmp (ix86_cmodel_string, "32"))
2852 ix86_cmodel = CM_32;
2853 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2854 ix86_cmodel = CM_KERNEL;
2856 error ("bad value (%s) for %scmodel=%s %s",
2857 ix86_cmodel_string, prefix, suffix, sw);
2861 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2862 use of rip-relative addressing. This eliminates fixups that
2863 would otherwise be needed if this object is to be placed in a
2864 DLL, and is essentially just as efficient as direct addressing. */
2865 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2866 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2867 else if (TARGET_64BIT)
2868 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2870 ix86_cmodel = CM_32;
2872 if (ix86_asm_string != 0)
2875 && !strcmp (ix86_asm_string, "intel"))
2876 ix86_asm_dialect = ASM_INTEL;
2877 else if (!strcmp (ix86_asm_string, "att"))
2878 ix86_asm_dialect = ASM_ATT;
2880 error ("bad value (%s) for %sasm=%s %s",
2881 ix86_asm_string, prefix, suffix, sw);
2883 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2884 error ("code model %qs not supported in the %s bit mode",
2885 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2886 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2887 sorry ("%i-bit mode not compiled in",
2888 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2890 for (i = 0; i < pta_size; i++)
2891 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2893 ix86_schedule = processor_alias_table[i].schedule;
2894 ix86_arch = processor_alias_table[i].processor;
2895 /* Default cpu tuning to the architecture. */
2896 ix86_tune = ix86_arch;
2898 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2899 error ("CPU you selected does not support x86-64 "
2902 if (processor_alias_table[i].flags & PTA_MMX
2903 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2904 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2905 if (processor_alias_table[i].flags & PTA_3DNOW
2906 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2907 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2908 if (processor_alias_table[i].flags & PTA_3DNOW_A
2909 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2910 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2911 if (processor_alias_table[i].flags & PTA_SSE
2912 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2913 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2914 if (processor_alias_table[i].flags & PTA_SSE2
2915 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2916 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2917 if (processor_alias_table[i].flags & PTA_SSE3
2918 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2919 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2920 if (processor_alias_table[i].flags & PTA_SSSE3
2921 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2922 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2923 if (processor_alias_table[i].flags & PTA_SSE4_1
2924 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2925 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2926 if (processor_alias_table[i].flags & PTA_SSE4_2
2927 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2928 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2929 if (processor_alias_table[i].flags & PTA_AVX
2930 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2931 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2932 if (processor_alias_table[i].flags & PTA_FMA
2933 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2934 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2935 if (processor_alias_table[i].flags & PTA_SSE4A
2936 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2937 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2938 if (processor_alias_table[i].flags & PTA_ABM
2939 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2940 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2941 if (processor_alias_table[i].flags & PTA_CX16
2942 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2943 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2944 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2945 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2946 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2947 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2948 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2949 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2950 if (processor_alias_table[i].flags & PTA_MOVBE
2951 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2952 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2953 if (processor_alias_table[i].flags & PTA_AES
2954 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2955 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2956 if (processor_alias_table[i].flags & PTA_PCLMUL
2957 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2958 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2959 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2960 x86_prefetch_sse = true;
2966 error ("bad value (%s) for %sarch=%s %s",
2967 ix86_arch_string, prefix, suffix, sw);
2969 ix86_arch_mask = 1u << ix86_arch;
2970 for (i = 0; i < X86_ARCH_LAST; ++i)
2971 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2973 for (i = 0; i < pta_size; i++)
2974 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2976 ix86_schedule = processor_alias_table[i].schedule;
2977 ix86_tune = processor_alias_table[i].processor;
2978 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2980 if (ix86_tune_defaulted)
2982 ix86_tune_string = "x86-64";
2983 for (i = 0; i < pta_size; i++)
2984 if (! strcmp (ix86_tune_string,
2985 processor_alias_table[i].name))
2987 ix86_schedule = processor_alias_table[i].schedule;
2988 ix86_tune = processor_alias_table[i].processor;
2991 error ("CPU you selected does not support x86-64 "
2994 /* Intel CPUs have always interpreted SSE prefetch instructions as
2995 NOPs; so, we can enable SSE prefetch instructions even when
2996 -mtune (rather than -march) points us to a processor that has them.
2997 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2998 higher processors. */
3000 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3001 x86_prefetch_sse = true;
3005 error ("bad value (%s) for %stune=%s %s",
3006 ix86_tune_string, prefix, suffix, sw);
3008 ix86_tune_mask = 1u << ix86_tune;
3009 for (i = 0; i < X86_TUNE_LAST; ++i)
3010 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3013 ix86_cost = &ix86_size_cost;
3015 ix86_cost = processor_target_table[ix86_tune].cost;
3017 /* Arrange to set up i386_stack_locals for all functions. */
3018 init_machine_status = ix86_init_machine_status;
3020 /* Validate -mregparm= value. */
3021 if (ix86_regparm_string)
3024 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3025 i = atoi (ix86_regparm_string);
3026 if (i < 0 || i > REGPARM_MAX)
3027 error ("%sregparm=%d%s is not between 0 and %d",
3028 prefix, i, suffix, REGPARM_MAX);
3033 ix86_regparm = REGPARM_MAX;
3035 /* If the user has provided any of the -malign-* options,
3036 warn and use that value only if -falign-* is not set.
3037 Remove this code in GCC 3.2 or later. */
3038 if (ix86_align_loops_string)
3040 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3041 prefix, suffix, suffix);
3042 if (align_loops == 0)
3044 i = atoi (ix86_align_loops_string);
3045 if (i < 0 || i > MAX_CODE_ALIGN)
3046 error ("%salign-loops=%d%s is not between 0 and %d",
3047 prefix, i, suffix, MAX_CODE_ALIGN);
3049 align_loops = 1 << i;
3053 if (ix86_align_jumps_string)
3055 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3056 prefix, suffix, suffix);
3057 if (align_jumps == 0)
3059 i = atoi (ix86_align_jumps_string);
3060 if (i < 0 || i > MAX_CODE_ALIGN)
3061 error ("%salign-loops=%d%s is not between 0 and %d",
3062 prefix, i, suffix, MAX_CODE_ALIGN);
3064 align_jumps = 1 << i;
3068 if (ix86_align_funcs_string)
3070 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3071 prefix, suffix, suffix);
3072 if (align_functions == 0)
3074 i = atoi (ix86_align_funcs_string);
3075 if (i < 0 || i > MAX_CODE_ALIGN)
3076 error ("%salign-loops=%d%s is not between 0 and %d",
3077 prefix, i, suffix, MAX_CODE_ALIGN);
3079 align_functions = 1 << i;
3083 /* Default align_* from the processor table. */
3084 if (align_loops == 0)
3086 align_loops = processor_target_table[ix86_tune].align_loop;
3087 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3089 if (align_jumps == 0)
3091 align_jumps = processor_target_table[ix86_tune].align_jump;
3092 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3094 if (align_functions == 0)
3096 align_functions = processor_target_table[ix86_tune].align_func;
3099 /* Validate -mbranch-cost= value, or provide default. */
3100 ix86_branch_cost = ix86_cost->branch_cost;
3101 if (ix86_branch_cost_string)
3103 i = atoi (ix86_branch_cost_string);
3105 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3107 ix86_branch_cost = i;
3109 if (ix86_section_threshold_string)
3111 i = atoi (ix86_section_threshold_string);
3113 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3115 ix86_section_threshold = i;
3118 if (ix86_tls_dialect_string)
3120 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3121 ix86_tls_dialect = TLS_DIALECT_GNU;
3122 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3123 ix86_tls_dialect = TLS_DIALECT_GNU2;
3124 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3125 ix86_tls_dialect = TLS_DIALECT_SUN;
3127 error ("bad value (%s) for %stls-dialect=%s %s",
3128 ix86_tls_dialect_string, prefix, suffix, sw);
3131 if (ix87_precision_string)
3133 i = atoi (ix87_precision_string);
3134 if (i != 32 && i != 64 && i != 80)
3135 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3140 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3142 /* Enable by default the SSE and MMX builtins. Do allow the user to
3143 explicitly disable any of these. In particular, disabling SSE and
3144 MMX for kernel code is extremely useful. */
3145 if (!ix86_arch_specified)
3147 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3148 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3151 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3155 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3157 if (!ix86_arch_specified)
3159 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3161 /* i386 ABI does not specify red zone. It still makes sense to use it
3162 when programmer takes care to stack from being destroyed. */
3163 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3164 target_flags |= MASK_NO_RED_ZONE;
3167 /* Keep nonleaf frame pointers. */
3168 if (flag_omit_frame_pointer)
3169 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3170 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3171 flag_omit_frame_pointer = 1;
3173 /* If we're doing fast math, we don't care about comparison order
3174 wrt NaNs. This lets us use a shorter comparison sequence. */
3175 if (flag_finite_math_only)
3176 target_flags &= ~MASK_IEEE_FP;
3178 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3179 since the insns won't need emulation. */
3180 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3181 target_flags &= ~MASK_NO_FANCY_MATH_387;
3183 /* Likewise, if the target doesn't have a 387, or we've specified
3184 software floating point, don't use 387 inline intrinsics. */
3186 target_flags |= MASK_NO_FANCY_MATH_387;
3188 /* Turn on MMX builtins for -msse. */
3191 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3192 x86_prefetch_sse = true;
3195 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3196 if (TARGET_SSE4_2 || TARGET_ABM)
3197 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3199 /* Validate -mpreferred-stack-boundary= value or default it to
3200 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3201 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3202 if (ix86_preferred_stack_boundary_string)
3204 i = atoi (ix86_preferred_stack_boundary_string);
3205 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3206 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3207 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3209 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3212 /* Set the default value for -mstackrealign. */
3213 if (ix86_force_align_arg_pointer == -1)
3214 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3216 /* Validate -mincoming-stack-boundary= value or default it to
3217 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3218 if (ix86_force_align_arg_pointer)
3219 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3221 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3222 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3223 if (ix86_incoming_stack_boundary_string)
3225 i = atoi (ix86_incoming_stack_boundary_string);
3226 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3227 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3228 i, TARGET_64BIT ? 4 : 2);
3231 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3232 ix86_incoming_stack_boundary
3233 = ix86_user_incoming_stack_boundary;
3237 /* Accept -msseregparm only if at least SSE support is enabled. */
3238 if (TARGET_SSEREGPARM
3240 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3242 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3243 if (ix86_fpmath_string != 0)
3245 if (! strcmp (ix86_fpmath_string, "387"))
3246 ix86_fpmath = FPMATH_387;
3247 else if (! strcmp (ix86_fpmath_string, "sse"))
3251 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3252 ix86_fpmath = FPMATH_387;
3255 ix86_fpmath = FPMATH_SSE;
3257 else if (! strcmp (ix86_fpmath_string, "387,sse")
3258 || ! strcmp (ix86_fpmath_string, "387+sse")
3259 || ! strcmp (ix86_fpmath_string, "sse,387")
3260 || ! strcmp (ix86_fpmath_string, "sse+387")
3261 || ! strcmp (ix86_fpmath_string, "both"))
3265 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3266 ix86_fpmath = FPMATH_387;
3268 else if (!TARGET_80387)
3270 warning (0, "387 instruction set disabled, using SSE arithmetics");
3271 ix86_fpmath = FPMATH_SSE;
3274 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3277 error ("bad value (%s) for %sfpmath=%s %s",
3278 ix86_fpmath_string, prefix, suffix, sw);
3281 /* If the i387 is disabled, then do not return values in it. */
3283 target_flags &= ~MASK_FLOAT_RETURNS;
3285 /* Use external vectorized library in vectorizing intrinsics. */
3286 if (ix86_veclibabi_string)
3288 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3289 ix86_veclib_handler = ix86_veclibabi_svml;
3290 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3291 ix86_veclib_handler = ix86_veclibabi_acml;
3293 error ("unknown vectorization library ABI type (%s) for "
3294 "%sveclibabi=%s %s", ix86_veclibabi_string,
3295 prefix, suffix, sw);
3298 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3299 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3301 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3303 /* ??? Unwind info is not correct around the CFG unless either a frame
3304 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3305 unwind info generation to be aware of the CFG and propagating states
3307 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3308 || flag_exceptions || flag_non_call_exceptions)
3309 && flag_omit_frame_pointer
3310 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3312 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3313 warning (0, "unwind tables currently require either a frame pointer "
3314 "or %saccumulate-outgoing-args%s for correctness",
3316 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3319 /* If stack probes are required, the space used for large function
3320 arguments on the stack must also be probed, so enable
3321 -maccumulate-outgoing-args so this happens in the prologue. */
3322 if (TARGET_STACK_PROBE
3323 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3325 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3326 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3327 "for correctness", prefix, suffix);
3328 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3331 /* For sane SSE instruction set generation we need fcomi instruction.
3332 It is safe to enable all CMOVE instructions. */
3336 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3339 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3340 p = strchr (internal_label_prefix, 'X');
3341 internal_label_prefix_len = p - internal_label_prefix;
3345 /* When scheduling description is not available, disable scheduler pass
3346 so it won't slow down the compilation and make x87 code slower. */
3347 if (!TARGET_SCHEDULE)
3348 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3350 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3351 set_param_value ("simultaneous-prefetches",
3352 ix86_cost->simultaneous_prefetches);
3353 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3354 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3355 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3356 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3357 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3358 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3360 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3361 can be optimized to ap = __builtin_next_arg (0). */
3363 targetm.expand_builtin_va_start = NULL;
3367 ix86_gen_leave = gen_leave_rex64;
3368 ix86_gen_pop1 = gen_popdi1;
3369 ix86_gen_add3 = gen_adddi3;
3370 ix86_gen_sub3 = gen_subdi3;
3371 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3372 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3373 ix86_gen_monitor = gen_sse3_monitor64;
3374 ix86_gen_andsp = gen_anddi3;
3378 ix86_gen_leave = gen_leave;
3379 ix86_gen_pop1 = gen_popsi1;
3380 ix86_gen_add3 = gen_addsi3;
3381 ix86_gen_sub3 = gen_subsi3;
3382 ix86_gen_sub3_carry = gen_subsi3_carry;
3383 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3384 ix86_gen_monitor = gen_sse3_monitor;
3385 ix86_gen_andsp = gen_andsi3;
3389 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3391 target_flags |= MASK_CLD & ~target_flags_explicit;
3394 /* Save the initial options in case the user does function specific options */
3396 target_option_default_node = target_option_current_node
3397 = build_target_option_node ();
3400 /* Update register usage after having seen the compiler flags. */
3403 ix86_conditional_register_usage (void)
3408 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3410 if (fixed_regs[i] > 1)
3411 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3412 if (call_used_regs[i] > 1)
3413 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3416 /* The PIC register, if it exists, is fixed. */
3417 j = PIC_OFFSET_TABLE_REGNUM;
3418 if (j != INVALID_REGNUM)
3419 fixed_regs[j] = call_used_regs[j] = 1;
3421 /* The MS_ABI changes the set of call-used registers. */
3422 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3424 call_used_regs[SI_REG] = 0;
3425 call_used_regs[DI_REG] = 0;
3426 call_used_regs[XMM6_REG] = 0;
3427 call_used_regs[XMM7_REG] = 0;
3428 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3429 call_used_regs[i] = 0;
3432 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3433 other call-clobbered regs for 64-bit. */
3436 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3438 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3439 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3440 && call_used_regs[i])
3441 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3444 /* If MMX is disabled, squash the registers. */
3446 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3447 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3448 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3450 /* If SSE is disabled, squash the registers. */
3452 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3453 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3454 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3456 /* If the FPU is disabled, squash the registers. */
3457 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3459 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3460 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3462 /* If 32-bit, squash the 64-bit registers. */
3465 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3467 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3473 /* Save the current options */
3476 ix86_function_specific_save (struct cl_target_option *ptr)
3478 ptr->arch = ix86_arch;
3479 ptr->schedule = ix86_schedule;
3480 ptr->tune = ix86_tune;
3481 ptr->fpmath = ix86_fpmath;
3482 ptr->branch_cost = ix86_branch_cost;
3483 ptr->tune_defaulted = ix86_tune_defaulted;
3484 ptr->arch_specified = ix86_arch_specified;
3485 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3486 ptr->target_flags_explicit = target_flags_explicit;
3488 /* The fields are char but the variables are not; make sure the
3489 values fit in the fields. */
3490 gcc_assert (ptr->arch == ix86_arch);
3491 gcc_assert (ptr->schedule == ix86_schedule);
3492 gcc_assert (ptr->tune == ix86_tune);
3493 gcc_assert (ptr->fpmath == ix86_fpmath);
3494 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3497 /* Restore the current options */
3500 ix86_function_specific_restore (struct cl_target_option *ptr)
3502 enum processor_type old_tune = ix86_tune;
3503 enum processor_type old_arch = ix86_arch;
3504 unsigned int ix86_arch_mask, ix86_tune_mask;
3507 ix86_arch = (enum processor_type) ptr->arch;
3508 ix86_schedule = (enum attr_cpu) ptr->schedule;
3509 ix86_tune = (enum processor_type) ptr->tune;
3510 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3511 ix86_branch_cost = ptr->branch_cost;
3512 ix86_tune_defaulted = ptr->tune_defaulted;
3513 ix86_arch_specified = ptr->arch_specified;
3514 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3515 target_flags_explicit = ptr->target_flags_explicit;
3517 /* Recreate the arch feature tests if the arch changed */
3518 if (old_arch != ix86_arch)
3520 ix86_arch_mask = 1u << ix86_arch;
3521 for (i = 0; i < X86_ARCH_LAST; ++i)
3522 ix86_arch_features[i]
3523 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3526 /* Recreate the tune optimization tests */
3527 if (old_tune != ix86_tune)
3529 ix86_tune_mask = 1u << ix86_tune;
3530 for (i = 0; i < X86_TUNE_LAST; ++i)
3531 ix86_tune_features[i]
3532 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3536 /* Print the current options */
3539 ix86_function_specific_print (FILE *file, int indent,
3540 struct cl_target_option *ptr)
3543 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3544 NULL, NULL, NULL, false);
3546 fprintf (file, "%*sarch = %d (%s)\n",
3549 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3550 ? cpu_names[ptr->arch]
3553 fprintf (file, "%*stune = %d (%s)\n",
3556 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3557 ? cpu_names[ptr->tune]
3560 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3561 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3562 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3563 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3567 fprintf (file, "%*s%s\n", indent, "", target_string);
3568 free (target_string);
3573 /* Inner function to process the attribute((target(...))), take an argument and
3574 set the current options from the argument. If we have a list, recursively go
3578 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3583 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3584 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3585 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3586 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3601 enum ix86_opt_type type;
3606 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3607 IX86_ATTR_ISA ("abm", OPT_mabm),
3608 IX86_ATTR_ISA ("aes", OPT_maes),
3609 IX86_ATTR_ISA ("avx", OPT_mavx),
3610 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3611 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3612 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3613 IX86_ATTR_ISA ("sse", OPT_msse),
3614 IX86_ATTR_ISA ("sse2", OPT_msse2),
3615 IX86_ATTR_ISA ("sse3", OPT_msse3),
3616 IX86_ATTR_ISA ("sse4", OPT_msse4),
3617 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3618 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3619 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3620 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3622 /* string options */
3623 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3624 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3625 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3628 IX86_ATTR_YES ("cld",
3632 IX86_ATTR_NO ("fancy-math-387",
3633 OPT_mfancy_math_387,
3634 MASK_NO_FANCY_MATH_387),
3636 IX86_ATTR_YES ("ieee-fp",
3640 IX86_ATTR_YES ("inline-all-stringops",
3641 OPT_minline_all_stringops,
3642 MASK_INLINE_ALL_STRINGOPS),
3644 IX86_ATTR_YES ("inline-stringops-dynamically",
3645 OPT_minline_stringops_dynamically,
3646 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3648 IX86_ATTR_NO ("align-stringops",
3649 OPT_mno_align_stringops,
3650 MASK_NO_ALIGN_STRINGOPS),
3652 IX86_ATTR_YES ("recip",
3658 /* If this is a list, recurse to get the options. */
3659 if (TREE_CODE (args) == TREE_LIST)
3663 for (; args; args = TREE_CHAIN (args))
3664 if (TREE_VALUE (args)
3665 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3671 else if (TREE_CODE (args) != STRING_CST)
3674 /* Handle multiple arguments separated by commas. */
3675 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3677 while (next_optstr && *next_optstr != '\0')
3679 char *p = next_optstr;
3681 char *comma = strchr (next_optstr, ',');
3682 const char *opt_string;
3683 size_t len, opt_len;
3688 enum ix86_opt_type type = ix86_opt_unknown;
3694 len = comma - next_optstr;
3695 next_optstr = comma + 1;
3703 /* Recognize no-xxx. */
3704 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3713 /* Find the option. */
3716 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3718 type = attrs[i].type;
3719 opt_len = attrs[i].len;
3720 if (ch == attrs[i].string[0]
3721 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3722 && memcmp (p, attrs[i].string, opt_len) == 0)
3725 mask = attrs[i].mask;
3726 opt_string = attrs[i].string;
3731 /* Process the option. */
3734 error ("attribute(target(\"%s\")) is unknown", orig_p);
3738 else if (type == ix86_opt_isa)
3739 ix86_handle_option (opt, p, opt_set_p);
3741 else if (type == ix86_opt_yes || type == ix86_opt_no)
3743 if (type == ix86_opt_no)
3744 opt_set_p = !opt_set_p;
3747 target_flags |= mask;
3749 target_flags &= ~mask;
3752 else if (type == ix86_opt_str)
3756 error ("option(\"%s\") was already specified", opt_string);
3760 p_strings[opt] = xstrdup (p + opt_len);
3770 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3773 ix86_valid_target_attribute_tree (tree args)
3775 const char *orig_arch_string = ix86_arch_string;
3776 const char *orig_tune_string = ix86_tune_string;
3777 const char *orig_fpmath_string = ix86_fpmath_string;
3778 int orig_tune_defaulted = ix86_tune_defaulted;
3779 int orig_arch_specified = ix86_arch_specified;
3780 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3783 struct cl_target_option *def
3784 = TREE_TARGET_OPTION (target_option_default_node);
3786 /* Process each of the options on the chain. */
3787 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3790 /* If the changed options are different from the default, rerun override_options,
3791 and then save the options away. The string options are are attribute options,
3792 and will be undone when we copy the save structure. */
3793 if (ix86_isa_flags != def->ix86_isa_flags
3794 || target_flags != def->target_flags
3795 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3796 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3797 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3799 /* If we are using the default tune= or arch=, undo the string assigned,
3800 and use the default. */
3801 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3802 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3803 else if (!orig_arch_specified)
3804 ix86_arch_string = NULL;
3806 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3807 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3808 else if (orig_tune_defaulted)
3809 ix86_tune_string = NULL;
3811 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3812 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3813 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3814 else if (!TARGET_64BIT && TARGET_SSE)
3815 ix86_fpmath_string = "sse,387";
3817 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3818 override_options (false);
3820 /* Add any builtin functions with the new isa if any. */
3821 ix86_add_new_builtins (ix86_isa_flags);
3823 /* Save the current options unless we are validating options for
3825 t = build_target_option_node ();
3827 ix86_arch_string = orig_arch_string;
3828 ix86_tune_string = orig_tune_string;
3829 ix86_fpmath_string = orig_fpmath_string;
3831 /* Free up memory allocated to hold the strings */
3832 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3833 if (option_strings[i])
3834 free (option_strings[i]);
3840 /* Hook to validate attribute((target("string"))). */
3843 ix86_valid_target_attribute_p (tree fndecl,
3844 tree ARG_UNUSED (name),
3846 int ARG_UNUSED (flags))
3848 struct cl_target_option cur_target;
3850 tree old_optimize = build_optimization_node ();
3851 tree new_target, new_optimize;
3852 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3854 /* If the function changed the optimization levels as well as setting target
3855 options, start with the optimizations specified. */
3856 if (func_optimize && func_optimize != old_optimize)
3857 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3859 /* The target attributes may also change some optimization flags, so update
3860 the optimization options if necessary. */
3861 cl_target_option_save (&cur_target);
3862 new_target = ix86_valid_target_attribute_tree (args);
3863 new_optimize = build_optimization_node ();
3870 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3872 if (old_optimize != new_optimize)
3873 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3876 cl_target_option_restore (&cur_target);
3878 if (old_optimize != new_optimize)
3879 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3885 /* Hook to determine if one function can safely inline another. */
3888 ix86_can_inline_p (tree caller, tree callee)
3891 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3892 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3894 /* If callee has no option attributes, then it is ok to inline. */
3898 /* If caller has no option attributes, but callee does then it is not ok to
3900 else if (!caller_tree)
3905 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3906 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3908 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3909 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3911 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3912 != callee_opts->ix86_isa_flags)
3915 /* See if we have the same non-isa options. */
3916 else if (caller_opts->target_flags != callee_opts->target_flags)
3919 /* See if arch, tune, etc. are the same. */
3920 else if (caller_opts->arch != callee_opts->arch)
3923 else if (caller_opts->tune != callee_opts->tune)
3926 else if (caller_opts->fpmath != callee_opts->fpmath)
3929 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3940 /* Remember the last target of ix86_set_current_function. */
3941 static GTY(()) tree ix86_previous_fndecl;
3943 /* Establish appropriate back-end context for processing the function
3944 FNDECL. The argument might be NULL to indicate processing at top
3945 level, outside of any function scope. */
3947 ix86_set_current_function (tree fndecl)
3949 /* Only change the context if the function changes. This hook is called
3950 several times in the course of compiling a function, and we don't want to
3951 slow things down too much or call target_reinit when it isn't safe. */
3952 if (fndecl && fndecl != ix86_previous_fndecl)
3954 tree old_tree = (ix86_previous_fndecl
3955 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3958 tree new_tree = (fndecl
3959 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3962 ix86_previous_fndecl = fndecl;
3963 if (old_tree == new_tree)
3968 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3974 struct cl_target_option *def
3975 = TREE_TARGET_OPTION (target_option_current_node);
3977 cl_target_option_restore (def);
3984 /* Return true if this goes in large data/bss. */
3987 ix86_in_large_data_p (tree exp)
3989 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3992 /* Functions are never large data. */
3993 if (TREE_CODE (exp) == FUNCTION_DECL)
3996 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3998 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3999 if (strcmp (section, ".ldata") == 0
4000 || strcmp (section, ".lbss") == 0)
4006 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4008 /* If this is an incomplete type with size 0, then we can't put it
4009 in data because it might be too big when completed. */
4010 if (!size || size > ix86_section_threshold)
4017 /* Switch to the appropriate section for output of DECL.
4018 DECL is either a `VAR_DECL' node or a constant of some sort.
4019 RELOC indicates whether forming the initial value of DECL requires
4020 link-time relocations. */
4022 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4026 x86_64_elf_select_section (tree decl, int reloc,
4027 unsigned HOST_WIDE_INT align)
4029 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4030 && ix86_in_large_data_p (decl))
4032 const char *sname = NULL;
4033 unsigned int flags = SECTION_WRITE;
4034 switch (categorize_decl_for_section (decl, reloc))
4039 case SECCAT_DATA_REL:
4040 sname = ".ldata.rel";
4042 case SECCAT_DATA_REL_LOCAL:
4043 sname = ".ldata.rel.local";
4045 case SECCAT_DATA_REL_RO:
4046 sname = ".ldata.rel.ro";
4048 case SECCAT_DATA_REL_RO_LOCAL:
4049 sname = ".ldata.rel.ro.local";
4053 flags |= SECTION_BSS;
4056 case SECCAT_RODATA_MERGE_STR:
4057 case SECCAT_RODATA_MERGE_STR_INIT:
4058 case SECCAT_RODATA_MERGE_CONST:
4062 case SECCAT_SRODATA:
4069 /* We don't split these for medium model. Place them into
4070 default sections and hope for best. */
4072 case SECCAT_EMUTLS_VAR:
4073 case SECCAT_EMUTLS_TMPL:
4078 /* We might get called with string constants, but get_named_section
4079 doesn't like them as they are not DECLs. Also, we need to set
4080 flags in that case. */
4082 return get_section (sname, flags, NULL);
4083 return get_named_section (decl, sname, reloc);
4086 return default_elf_select_section (decl, reloc, align);
4089 /* Build up a unique section name, expressed as a
4090 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4091 RELOC indicates whether the initial value of EXP requires
4092 link-time relocations. */
4094 static void ATTRIBUTE_UNUSED
4095 x86_64_elf_unique_section (tree decl, int reloc)
4097 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4098 && ix86_in_large_data_p (decl))
4100 const char *prefix = NULL;
4101 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4102 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4104 switch (categorize_decl_for_section (decl, reloc))
4107 case SECCAT_DATA_REL:
4108 case SECCAT_DATA_REL_LOCAL:
4109 case SECCAT_DATA_REL_RO:
4110 case SECCAT_DATA_REL_RO_LOCAL:
4111 prefix = one_only ? ".ld" : ".ldata";
4114 prefix = one_only ? ".lb" : ".lbss";
4117 case SECCAT_RODATA_MERGE_STR:
4118 case SECCAT_RODATA_MERGE_STR_INIT:
4119 case SECCAT_RODATA_MERGE_CONST:
4120 prefix = one_only ? ".lr" : ".lrodata";
4122 case SECCAT_SRODATA:
4129 /* We don't split these for medium model. Place them into
4130 default sections and hope for best. */
4132 case SECCAT_EMUTLS_VAR:
4133 prefix = targetm.emutls.var_section;
4135 case SECCAT_EMUTLS_TMPL:
4136 prefix = targetm.emutls.tmpl_section;
4141 const char *name, *linkonce;
4144 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4145 name = targetm.strip_name_encoding (name);
4147 /* If we're using one_only, then there needs to be a .gnu.linkonce
4148 prefix to the section name. */
4149 linkonce = one_only ? ".gnu.linkonce" : "";
4151 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4153 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4157 default_unique_section (decl, reloc);
4160 #ifdef COMMON_ASM_OP
4161 /* This says how to output assembler code to declare an
4162 uninitialized external linkage data object.
4164 For medium model x86-64 we need to use .largecomm opcode for
4167 x86_elf_aligned_common (FILE *file,
4168 const char *name, unsigned HOST_WIDE_INT size,
4171 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4172 && size > (unsigned int)ix86_section_threshold)
4173 fputs (".largecomm\t", file);
4175 fputs (COMMON_ASM_OP, file);
4176 assemble_name (file, name);
4177 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4178 size, align / BITS_PER_UNIT);
4182 /* Utility function for targets to use in implementing
4183 ASM_OUTPUT_ALIGNED_BSS. */
4186 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4187 const char *name, unsigned HOST_WIDE_INT size,
4190 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4191 && size > (unsigned int)ix86_section_threshold)
4192 switch_to_section (get_named_section (decl, ".lbss", 0));
4194 switch_to_section (bss_section);
4195 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4196 #ifdef ASM_DECLARE_OBJECT_NAME
4197 last_assemble_variable_decl = decl;
4198 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4200 /* Standard thing is just output label for the object. */
4201 ASM_OUTPUT_LABEL (file, name);
4202 #endif /* ASM_DECLARE_OBJECT_NAME */
4203 ASM_OUTPUT_SKIP (file, size ? size : 1);
4207 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4209 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4210 make the problem with not enough registers even worse. */
4211 #ifdef INSN_SCHEDULING
4213 flag_schedule_insns = 0;
4217 /* The Darwin libraries never set errno, so we might as well
4218 avoid calling them when that's the only reason we would. */
4219 flag_errno_math = 0;
4221 /* The default values of these switches depend on the TARGET_64BIT
4222 that is not known at this moment. Mark these values with 2 and
4223 let user the to override these. In case there is no command line option
4224 specifying them, we will set the defaults in override_options. */
4226 flag_omit_frame_pointer = 2;
4227 flag_pcc_struct_return = 2;
4228 flag_asynchronous_unwind_tables = 2;
4229 flag_vect_cost_model = 1;
4230 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4231 SUBTARGET_OPTIMIZATION_OPTIONS;
4235 /* Decide whether we can make a sibling call to a function. DECL is the
4236 declaration of the function being targeted by the call and EXP is the
4237 CALL_EXPR representing the call. */
4240 ix86_function_ok_for_sibcall (tree decl, tree exp)
4242 tree type, decl_or_type;
4245 /* If we are generating position-independent code, we cannot sibcall
4246 optimize any indirect call, or a direct call to a global function,
4247 as the PLT requires %ebx be live. */
4248 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4251 /* If we need to align the outgoing stack, then sibcalling would
4252 unalign the stack, which may break the called function. */
4253 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4258 decl_or_type = decl;
4259 type = TREE_TYPE (decl);
4263 /* We're looking at the CALL_EXPR, we need the type of the function. */
4264 type = CALL_EXPR_FN (exp); /* pointer expression */
4265 type = TREE_TYPE (type); /* pointer type */
4266 type = TREE_TYPE (type); /* function type */
4267 decl_or_type = type;
4270 /* Check that the return value locations are the same. Like
4271 if we are returning floats on the 80387 register stack, we cannot
4272 make a sibcall from a function that doesn't return a float to a
4273 function that does or, conversely, from a function that does return
4274 a float to a function that doesn't; the necessary stack adjustment
4275 would not be executed. This is also the place we notice
4276 differences in the return value ABI. Note that it is ok for one
4277 of the functions to have void return type as long as the return
4278 value of the other is passed in a register. */
4279 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4280 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4282 if (STACK_REG_P (a) || STACK_REG_P (b))
4284 if (!rtx_equal_p (a, b))
4287 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4289 else if (!rtx_equal_p (a, b))
4294 /* The SYSV ABI has more call-clobbered registers;
4295 disallow sibcalls from MS to SYSV. */
4296 if (cfun->machine->call_abi == MS_ABI
4297 && ix86_function_type_abi (type) == SYSV_ABI)
4302 /* If this call is indirect, we'll need to be able to use a
4303 call-clobbered register for the address of the target function.
4304 Make sure that all such registers are not used for passing
4305 parameters. Note that DLLIMPORT functions are indirect. */
4307 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4309 if (ix86_function_regparm (type, NULL) >= 3)
4311 /* ??? Need to count the actual number of registers to be used,
4312 not the possible number of registers. Fix later. */
4318 /* Otherwise okay. That also includes certain types of indirect calls. */
4322 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4323 calling convention attributes;
4324 arguments as in struct attribute_spec.handler. */
4327 ix86_handle_cconv_attribute (tree *node, tree name,
4329 int flags ATTRIBUTE_UNUSED,
4332 if (TREE_CODE (*node) != FUNCTION_TYPE
4333 && TREE_CODE (*node) != METHOD_TYPE
4334 && TREE_CODE (*node) != FIELD_DECL
4335 && TREE_CODE (*node) != TYPE_DECL)
4337 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4339 *no_add_attrs = true;
4343 /* Can combine regparm with all attributes but fastcall. */
4344 if (is_attribute_p ("regparm", name))
4348 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4350 error ("fastcall and regparm attributes are not compatible");
4353 cst = TREE_VALUE (args);
4354 if (TREE_CODE (cst) != INTEGER_CST)
4356 warning (OPT_Wattributes,
4357 "%qE attribute requires an integer constant argument",
4359 *no_add_attrs = true;
4361 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4363 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4365 *no_add_attrs = true;
4373 /* Do not warn when emulating the MS ABI. */
4374 if (TREE_CODE (*node) != FUNCTION_TYPE
4375 || ix86_function_type_abi (*node) != MS_ABI)
4376 warning (OPT_Wattributes, "%qE attribute ignored",
4378 *no_add_attrs = true;
4382 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4383 if (is_attribute_p ("fastcall", name))
4385 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4387 error ("fastcall and cdecl attributes are not compatible");
4389 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4391 error ("fastcall and stdcall attributes are not compatible");
4393 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4395 error ("fastcall and regparm attributes are not compatible");
4399 /* Can combine stdcall with fastcall (redundant), regparm and
4401 else if (is_attribute_p ("stdcall", name))
4403 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4405 error ("stdcall and cdecl attributes are not compatible");
4407 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4409 error ("stdcall and fastcall attributes are not compatible");
4413 /* Can combine cdecl with regparm and sseregparm. */
4414 else if (is_attribute_p ("cdecl", name))
4416 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4418 error ("stdcall and cdecl attributes are not compatible");
4420 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4422 error ("fastcall and cdecl attributes are not compatible");
4426 /* Can combine sseregparm with all attributes. */
4431 /* Return 0 if the attributes for two types are incompatible, 1 if they
4432 are compatible, and 2 if they are nearly compatible (which causes a
4433 warning to be generated). */
4436 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4438 /* Check for mismatch of non-default calling convention. */
4439 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4441 if (TREE_CODE (type1) != FUNCTION_TYPE
4442 && TREE_CODE (type1) != METHOD_TYPE)
4445 /* Check for mismatched fastcall/regparm types. */
4446 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4447 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4448 || (ix86_function_regparm (type1, NULL)
4449 != ix86_function_regparm (type2, NULL)))
4452 /* Check for mismatched sseregparm types. */
4453 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4454 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4457 /* Check for mismatched return types (cdecl vs stdcall). */
4458 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4459 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4465 /* Return the regparm value for a function with the indicated TYPE and DECL.
4466 DECL may be NULL when calling function indirectly
4467 or considering a libcall. */
4470 ix86_function_regparm (const_tree type, const_tree decl)
4475 static bool error_issued;
4478 return (ix86_function_type_abi (type) == SYSV_ABI
4479 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4481 regparm = ix86_regparm;
4482 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4486 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4488 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4490 /* We can't use regparm(3) for nested functions because
4491 these pass static chain pointer in %ecx register. */
4492 if (!error_issued && regparm == 3
4493 && decl_function_context (decl)
4494 && !DECL_NO_STATIC_CHAIN (decl))
4496 error ("nested functions are limited to 2 register parameters");
4497 error_issued = true;
4505 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4508 /* Use register calling convention for local functions when possible. */
4510 && TREE_CODE (decl) == FUNCTION_DECL
4514 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4515 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4518 int local_regparm, globals = 0, regno;
4521 /* Make sure no regparm register is taken by a
4522 fixed register variable. */
4523 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4524 if (fixed_regs[local_regparm])
4527 /* We can't use regparm(3) for nested functions as these use
4528 static chain pointer in third argument. */
4529 if (local_regparm == 3
4530 && decl_function_context (decl)
4531 && !DECL_NO_STATIC_CHAIN (decl))
4534 /* If the function realigns its stackpointer, the prologue will
4535 clobber %ecx. If we've already generated code for the callee,
4536 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4537 scanning the attributes for the self-realigning property. */
4538 f = DECL_STRUCT_FUNCTION (decl);
4539 /* Since current internal arg pointer won't conflict with
4540 parameter passing regs, so no need to change stack
4541 realignment and adjust regparm number.
4543 Each fixed register usage increases register pressure,
4544 so less registers should be used for argument passing.
4545 This functionality can be overriden by an explicit
4547 for (regno = 0; regno <= DI_REG; regno++)
4548 if (fixed_regs[regno])
4552 = globals < local_regparm ? local_regparm - globals : 0;
4554 if (local_regparm > regparm)
4555 regparm = local_regparm;
4562 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4563 DFmode (2) arguments in SSE registers for a function with the
4564 indicated TYPE and DECL. DECL may be NULL when calling function
4565 indirectly or considering a libcall. Otherwise return 0. */
4568 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4570 gcc_assert (!TARGET_64BIT);
4572 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4573 by the sseregparm attribute. */
4574 if (TARGET_SSEREGPARM
4575 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4582 error ("Calling %qD with attribute sseregparm without "
4583 "SSE/SSE2 enabled", decl);
4585 error ("Calling %qT with attribute sseregparm without "
4586 "SSE/SSE2 enabled", type);
4594 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4595 (and DFmode for SSE2) arguments in SSE registers. */
4596 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4598 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4599 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4601 return TARGET_SSE2 ? 2 : 1;
4607 /* Return true if EAX is live at the start of the function. Used by
4608 ix86_expand_prologue to determine if we need special help before
4609 calling allocate_stack_worker. */
4612 ix86_eax_live_at_start_p (void)
4614 /* Cheat. Don't bother working forward from ix86_function_regparm
4615 to the function type to whether an actual argument is located in
4616 eax. Instead just look at cfg info, which is still close enough
4617 to correct at this point. This gives false positives for broken
4618 functions that might use uninitialized data that happens to be
4619 allocated in eax, but who cares? */
4620 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4623 /* Value is the number of bytes of arguments automatically
4624 popped when returning from a subroutine call.
4625 FUNDECL is the declaration node of the function (as a tree),
4626 FUNTYPE is the data type of the function (as a tree),
4627 or for a library call it is an identifier node for the subroutine name.
4628 SIZE is the number of bytes of arguments passed on the stack.
4630 On the 80386, the RTD insn may be used to pop them if the number
4631 of args is fixed, but if the number is variable then the caller
4632 must pop them all. RTD can't be used for library calls now
4633 because the library is compiled with the Unix compiler.
4634 Use of RTD is a selectable option, since it is incompatible with
4635 standard Unix calling sequences. If the option is not selected,
4636 the caller must always pop the args.
4638 The attribute stdcall is equivalent to RTD on a per module basis. */
4641 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4645 /* None of the 64-bit ABIs pop arguments. */
4649 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4651 /* Cdecl functions override -mrtd, and never pop the stack. */
4652 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4654 /* Stdcall and fastcall functions will pop the stack if not
4656 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4657 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4660 if (rtd && ! stdarg_p (funtype))
4664 /* Lose any fake structure return argument if it is passed on the stack. */
4665 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4666 && !KEEP_AGGREGATE_RETURN_POINTER)
4668 int nregs = ix86_function_regparm (funtype, fundecl);
4670 return GET_MODE_SIZE (Pmode);
4676 /* Argument support functions. */
4678 /* Return true when register may be used to pass function parameters. */
4680 ix86_function_arg_regno_p (int regno)
4683 const int *parm_regs;
4688 return (regno < REGPARM_MAX
4689 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4691 return (regno < REGPARM_MAX
4692 || (TARGET_MMX && MMX_REGNO_P (regno)
4693 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4694 || (TARGET_SSE && SSE_REGNO_P (regno)
4695 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4700 if (SSE_REGNO_P (regno) && TARGET_SSE)
4705 if (TARGET_SSE && SSE_REGNO_P (regno)
4706 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4710 /* TODO: The function should depend on current function ABI but
4711 builtins.c would need updating then. Therefore we use the
4714 /* RAX is used as hidden argument to va_arg functions. */
4715 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4718 if (ix86_abi == MS_ABI)
4719 parm_regs = x86_64_ms_abi_int_parameter_registers;
4721 parm_regs = x86_64_int_parameter_registers;
4722 for (i = 0; i < (ix86_abi == MS_ABI
4723 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4724 if (regno == parm_regs[i])
4729 /* Return if we do not know how to pass TYPE solely in registers. */
4732 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4734 if (must_pass_in_stack_var_size_or_pad (mode, type))
4737 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4738 The layout_type routine is crafty and tries to trick us into passing
4739 currently unsupported vector types on the stack by using TImode. */
4740 return (!TARGET_64BIT && mode == TImode
4741 && type && TREE_CODE (type) != VECTOR_TYPE);
4744 /* It returns the size, in bytes, of the area reserved for arguments passed
4745 in registers for the function represented by fndecl dependent to the used
4748 ix86_reg_parm_stack_space (const_tree fndecl)
4750 enum calling_abi call_abi = SYSV_ABI;
4751 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4752 call_abi = ix86_function_abi (fndecl);
4754 call_abi = ix86_function_type_abi (fndecl);
4755 if (call_abi == MS_ABI)
4760 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4763 ix86_function_type_abi (const_tree fntype)
4765 if (TARGET_64BIT && fntype != NULL)
4767 enum calling_abi abi = ix86_abi;
4768 if (abi == SYSV_ABI)
4770 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4773 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4780 static enum calling_abi
4781 ix86_function_abi (const_tree fndecl)
4785 return ix86_function_type_abi (TREE_TYPE (fndecl));
4788 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4791 ix86_cfun_abi (void)
4793 if (! cfun || ! TARGET_64BIT)
4795 return cfun->machine->call_abi;
4799 extern void init_regs (void);
4801 /* Implementation of call abi switching target hook. Specific to FNDECL
4802 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4803 for more details. */
4805 ix86_call_abi_override (const_tree fndecl)
4807 if (fndecl == NULL_TREE)
4808 cfun->machine->call_abi = ix86_abi;
4810 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4813 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4814 re-initialization of init_regs each time we switch function context since
4815 this is needed only during RTL expansion. */
4817 ix86_maybe_switch_abi (void)
4820 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4824 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4825 for a call to a function whose data type is FNTYPE.
4826 For a library call, FNTYPE is 0. */
4829 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4830 tree fntype, /* tree ptr for function decl */
4831 rtx libname, /* SYMBOL_REF of library name or 0 */
4834 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4835 memset (cum, 0, sizeof (*cum));
4838 cum->call_abi = ix86_function_abi (fndecl);
4840 cum->call_abi = ix86_function_type_abi (fntype);
4841 /* Set up the number of registers to use for passing arguments. */
4843 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4844 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4845 "or subtarget optimization implying it");
4846 cum->nregs = ix86_regparm;
4849 if (cum->call_abi != ix86_abi)
4850 cum->nregs = (ix86_abi != SYSV_ABI
4851 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4855 cum->sse_nregs = SSE_REGPARM_MAX;
4858 if (cum->call_abi != ix86_abi)
4859 cum->sse_nregs = (ix86_abi != SYSV_ABI
4860 ? X86_64_SSE_REGPARM_MAX
4861 : X86_64_MS_SSE_REGPARM_MAX);
4865 cum->mmx_nregs = MMX_REGPARM_MAX;
4866 cum->warn_avx = true;
4867 cum->warn_sse = true;
4868 cum->warn_mmx = true;
4870 /* Because type might mismatch in between caller and callee, we need to
4871 use actual type of function for local calls.
4872 FIXME: cgraph_analyze can be told to actually record if function uses
4873 va_start so for local functions maybe_vaarg can be made aggressive
4875 FIXME: once typesytem is fixed, we won't need this code anymore. */
4877 fntype = TREE_TYPE (fndecl);
4878 cum->maybe_vaarg = (fntype
4879 ? (!prototype_p (fntype) || stdarg_p (fntype))
4884 /* If there are variable arguments, then we won't pass anything
4885 in registers in 32-bit mode. */
4886 if (stdarg_p (fntype))
4897 /* Use ecx and edx registers if function has fastcall attribute,
4898 else look for regparm information. */
4901 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4907 cum->nregs = ix86_function_regparm (fntype, fndecl);
4910 /* Set up the number of SSE registers used for passing SFmode
4911 and DFmode arguments. Warn for mismatching ABI. */
4912 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4916 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4917 But in the case of vector types, it is some vector mode.
4919 When we have only some of our vector isa extensions enabled, then there
4920 are some modes for which vector_mode_supported_p is false. For these
4921 modes, the generic vector support in gcc will choose some non-vector mode
4922 in order to implement the type. By computing the natural mode, we'll
4923 select the proper ABI location for the operand and not depend on whatever
4924 the middle-end decides to do with these vector types.
4926 The midde-end can't deal with the vector types > 16 bytes. In this
4927 case, we return the original mode and warn ABI change if CUM isn't
4930 static enum machine_mode
4931 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4933 enum machine_mode mode = TYPE_MODE (type);
4935 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4937 HOST_WIDE_INT size = int_size_in_bytes (type);
4938 if ((size == 8 || size == 16 || size == 32)
4939 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4940 && TYPE_VECTOR_SUBPARTS (type) > 1)
4942 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4944 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4945 mode = MIN_MODE_VECTOR_FLOAT;
4947 mode = MIN_MODE_VECTOR_INT;
4949 /* Get the mode which has this inner mode and number of units. */
4950 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4951 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4952 && GET_MODE_INNER (mode) == innermode)
4954 if (size == 32 && !TARGET_AVX)
4956 static bool warnedavx;
4963 warning (0, "AVX vector argument without AVX "
4964 "enabled changes the ABI");
4966 return TYPE_MODE (type);
4979 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4980 this may not agree with the mode that the type system has chosen for the
4981 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4982 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4985 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4990 if (orig_mode != BLKmode)
4991 tmp = gen_rtx_REG (orig_mode, regno);
4994 tmp = gen_rtx_REG (mode, regno);
4995 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4996 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5002 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5003 of this code is to classify each 8bytes of incoming argument by the register
5004 class and assign registers accordingly. */
5006 /* Return the union class of CLASS1 and CLASS2.
5007 See the x86-64 PS ABI for details. */
5009 static enum x86_64_reg_class
5010 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5012 /* Rule #1: If both classes are equal, this is the resulting class. */
5013 if (class1 == class2)
5016 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5018 if (class1 == X86_64_NO_CLASS)
5020 if (class2 == X86_64_NO_CLASS)
5023 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5024 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5025 return X86_64_MEMORY_CLASS;
5027 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5028 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5029 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5030 return X86_64_INTEGERSI_CLASS;
5031 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5032 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5033 return X86_64_INTEGER_CLASS;
5035 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5037 if (class1 == X86_64_X87_CLASS
5038 || class1 == X86_64_X87UP_CLASS
5039 || class1 == X86_64_COMPLEX_X87_CLASS
5040 || class2 == X86_64_X87_CLASS
5041 || class2 == X86_64_X87UP_CLASS
5042 || class2 == X86_64_COMPLEX_X87_CLASS)
5043 return X86_64_MEMORY_CLASS;
5045 /* Rule #6: Otherwise class SSE is used. */
5046 return X86_64_SSE_CLASS;
5049 /* Classify the argument of type TYPE and mode MODE.
5050 CLASSES will be filled by the register class used to pass each word
5051 of the operand. The number of words is returned. In case the parameter
5052 should be passed in memory, 0 is returned. As a special case for zero
5053 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5055 BIT_OFFSET is used internally for handling records and specifies offset
5056 of the offset in bits modulo 256 to avoid overflow cases.
5058 See the x86-64 PS ABI for details.
5062 classify_argument (enum machine_mode mode, const_tree type,
5063 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5065 HOST_WIDE_INT bytes =
5066 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5067 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5069 /* Variable sized entities are always passed/returned in memory. */
5073 if (mode != VOIDmode
5074 && targetm.calls.must_pass_in_stack (mode, type))
5077 if (type && AGGREGATE_TYPE_P (type))
5081 enum x86_64_reg_class subclasses[MAX_CLASSES];
5083 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5087 for (i = 0; i < words; i++)
5088 classes[i] = X86_64_NO_CLASS;
5090 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5091 signalize memory class, so handle it as special case. */
5094 classes[0] = X86_64_NO_CLASS;
5098 /* Classify each field of record and merge classes. */
5099 switch (TREE_CODE (type))
5102 /* And now merge the fields of structure. */
5103 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5105 if (TREE_CODE (field) == FIELD_DECL)
5109 if (TREE_TYPE (field) == error_mark_node)
5112 /* Bitfields are always classified as integer. Handle them
5113 early, since later code would consider them to be
5114 misaligned integers. */
5115 if (DECL_BIT_FIELD (field))
5117 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5118 i < ((int_bit_position (field) + (bit_offset % 64))
5119 + tree_low_cst (DECL_SIZE (field), 0)
5122 merge_classes (X86_64_INTEGER_CLASS,
5129 type = TREE_TYPE (field);
5131 /* Flexible array member is ignored. */
5132 if (TYPE_MODE (type) == BLKmode
5133 && TREE_CODE (type) == ARRAY_TYPE
5134 && TYPE_SIZE (type) == NULL_TREE
5135 && TYPE_DOMAIN (type) != NULL_TREE
5136 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5141 if (!warned && warn_psabi)
5144 inform (input_location,
5145 "The ABI of passing struct with"
5146 " a flexible array member has"
5147 " changed in GCC 4.4");
5151 num = classify_argument (TYPE_MODE (type), type,
5153 (int_bit_position (field)
5154 + bit_offset) % 256);
5157 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5158 for (i = 0; i < num && (i + pos) < words; i++)
5160 merge_classes (subclasses[i], classes[i + pos]);
5167 /* Arrays are handled as small records. */
5170 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5171 TREE_TYPE (type), subclasses, bit_offset);
5175 /* The partial classes are now full classes. */
5176 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5177 subclasses[0] = X86_64_SSE_CLASS;
5178 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5179 && !((bit_offset % 64) == 0 && bytes == 4))
5180 subclasses[0] = X86_64_INTEGER_CLASS;
5182 for (i = 0; i < words; i++)
5183 classes[i] = subclasses[i % num];
5188 case QUAL_UNION_TYPE:
5189 /* Unions are similar to RECORD_TYPE but offset is always 0.
5191 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5193 if (TREE_CODE (field) == FIELD_DECL)
5197 if (TREE_TYPE (field) == error_mark_node)
5200 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5201 TREE_TYPE (field), subclasses,
5205 for (i = 0; i < num; i++)
5206 classes[i] = merge_classes (subclasses[i], classes[i]);
5217 /* When size > 16 bytes, if the first one isn't
5218 X86_64_SSE_CLASS or any other ones aren't
5219 X86_64_SSEUP_CLASS, everything should be passed in
5221 if (classes[0] != X86_64_SSE_CLASS)
5224 for (i = 1; i < words; i++)
5225 if (classes[i] != X86_64_SSEUP_CLASS)
5229 /* Final merger cleanup. */
5230 for (i = 0; i < words; i++)
5232 /* If one class is MEMORY, everything should be passed in
5234 if (classes[i] == X86_64_MEMORY_CLASS)
5237 /* The X86_64_SSEUP_CLASS should be always preceded by
5238 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5239 if (classes[i] == X86_64_SSEUP_CLASS
5240 && classes[i - 1] != X86_64_SSE_CLASS
5241 && classes[i - 1] != X86_64_SSEUP_CLASS)
5243 /* The first one should never be X86_64_SSEUP_CLASS. */
5244 gcc_assert (i != 0);
5245 classes[i] = X86_64_SSE_CLASS;
5248 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5249 everything should be passed in memory. */
5250 if (classes[i] == X86_64_X87UP_CLASS
5251 && (classes[i - 1] != X86_64_X87_CLASS))
5255 /* The first one should never be X86_64_X87UP_CLASS. */
5256 gcc_assert (i != 0);
5257 if (!warned && warn_psabi)
5260 inform (input_location,
5261 "The ABI of passing union with long double"
5262 " has changed in GCC 4.4");
5270 /* Compute alignment needed. We align all types to natural boundaries with
5271 exception of XFmode that is aligned to 64bits. */
5272 if (mode != VOIDmode && mode != BLKmode)
5274 int mode_alignment = GET_MODE_BITSIZE (mode);
5277 mode_alignment = 128;
5278 else if (mode == XCmode)
5279 mode_alignment = 256;
5280 if (COMPLEX_MODE_P (mode))
5281 mode_alignment /= 2;
5282 /* Misaligned fields are always returned in memory. */
5283 if (bit_offset % mode_alignment)
5287 /* for V1xx modes, just use the base mode */
5288 if (VECTOR_MODE_P (mode) && mode != V1DImode
5289 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5290 mode = GET_MODE_INNER (mode);
5292 /* Classification of atomic types. */
5297 classes[0] = X86_64_SSE_CLASS;
5300 classes[0] = X86_64_SSE_CLASS;
5301 classes[1] = X86_64_SSEUP_CLASS;
5311 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5315 classes[0] = X86_64_INTEGERSI_CLASS;
5318 else if (size <= 64)
5320 classes[0] = X86_64_INTEGER_CLASS;
5323 else if (size <= 64+32)
5325 classes[0] = X86_64_INTEGER_CLASS;
5326 classes[1] = X86_64_INTEGERSI_CLASS;
5329 else if (size <= 64+64)
5331 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5339 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5343 /* OImode shouldn't be used directly. */
5348 if (!(bit_offset % 64))
5349 classes[0] = X86_64_SSESF_CLASS;
5351 classes[0] = X86_64_SSE_CLASS;
5354 classes[0] = X86_64_SSEDF_CLASS;
5357 classes[0] = X86_64_X87_CLASS;
5358 classes[1] = X86_64_X87UP_CLASS;
5361 classes[0] = X86_64_SSE_CLASS;
5362 classes[1] = X86_64_SSEUP_CLASS;
5365 classes[0] = X86_64_SSE_CLASS;
5366 if (!(bit_offset % 64))
5372 if (!warned && warn_psabi)
5375 inform (input_location,
5376 "The ABI of passing structure with complex float"
5377 " member has changed in GCC 4.4");
5379 classes[1] = X86_64_SSESF_CLASS;
5383 classes[0] = X86_64_SSEDF_CLASS;
5384 classes[1] = X86_64_SSEDF_CLASS;
5387 classes[0] = X86_64_COMPLEX_X87_CLASS;
5390 /* This modes is larger than 16 bytes. */
5398 classes[0] = X86_64_SSE_CLASS;
5399 classes[1] = X86_64_SSEUP_CLASS;
5400 classes[2] = X86_64_SSEUP_CLASS;
5401 classes[3] = X86_64_SSEUP_CLASS;
5409 classes[0] = X86_64_SSE_CLASS;
5410 classes[1] = X86_64_SSEUP_CLASS;
5417 classes[0] = X86_64_SSE_CLASS;
5423 gcc_assert (VECTOR_MODE_P (mode));
5428 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5430 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5431 classes[0] = X86_64_INTEGERSI_CLASS;
5433 classes[0] = X86_64_INTEGER_CLASS;
5434 classes[1] = X86_64_INTEGER_CLASS;
5435 return 1 + (bytes > 8);
5439 /* Examine the argument and return set number of register required in each
5440 class. Return 0 iff parameter should be passed in memory. */
5442 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5443 int *int_nregs, int *sse_nregs)
5445 enum x86_64_reg_class regclass[MAX_CLASSES];
5446 int n = classify_argument (mode, type, regclass, 0);
5452 for (n--; n >= 0; n--)
5453 switch (regclass[n])
5455 case X86_64_INTEGER_CLASS:
5456 case X86_64_INTEGERSI_CLASS:
5459 case X86_64_SSE_CLASS:
5460 case X86_64_SSESF_CLASS:
5461 case X86_64_SSEDF_CLASS:
5464 case X86_64_NO_CLASS:
5465 case X86_64_SSEUP_CLASS:
5467 case X86_64_X87_CLASS:
5468 case X86_64_X87UP_CLASS:
5472 case X86_64_COMPLEX_X87_CLASS:
5473 return in_return ? 2 : 0;
5474 case X86_64_MEMORY_CLASS:
5480 /* Construct container for the argument used by GCC interface. See
5481 FUNCTION_ARG for the detailed description. */
5484 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5485 const_tree type, int in_return, int nintregs, int nsseregs,
5486 const int *intreg, int sse_regno)
5488 /* The following variables hold the static issued_error state. */
5489 static bool issued_sse_arg_error;
5490 static bool issued_sse_ret_error;
5491 static bool issued_x87_ret_error;
5493 enum machine_mode tmpmode;
5495 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5496 enum x86_64_reg_class regclass[MAX_CLASSES];
5500 int needed_sseregs, needed_intregs;
5501 rtx exp[MAX_CLASSES];
5504 n = classify_argument (mode, type, regclass, 0);
5507 if (!examine_argument (mode, type, in_return, &needed_intregs,
5510 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5513 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5514 some less clueful developer tries to use floating-point anyway. */
5515 if (needed_sseregs && !TARGET_SSE)
5519 if (!issued_sse_ret_error)
5521 error ("SSE register return with SSE disabled");
5522 issued_sse_ret_error = true;
5525 else if (!issued_sse_arg_error)
5527 error ("SSE register argument with SSE disabled");
5528 issued_sse_arg_error = true;
5533 /* Likewise, error if the ABI requires us to return values in the
5534 x87 registers and the user specified -mno-80387. */
5535 if (!TARGET_80387 && in_return)
5536 for (i = 0; i < n; i++)
5537 if (regclass[i] == X86_64_X87_CLASS
5538 || regclass[i] == X86_64_X87UP_CLASS
5539 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5541 if (!issued_x87_ret_error)
5543 error ("x87 register return with x87 disabled");
5544 issued_x87_ret_error = true;
5549 /* First construct simple cases. Avoid SCmode, since we want to use
5550 single register to pass this type. */
5551 if (n == 1 && mode != SCmode)
5552 switch (regclass[0])
5554 case X86_64_INTEGER_CLASS:
5555 case X86_64_INTEGERSI_CLASS:
5556 return gen_rtx_REG (mode, intreg[0]);
5557 case X86_64_SSE_CLASS:
5558 case X86_64_SSESF_CLASS:
5559 case X86_64_SSEDF_CLASS:
5560 if (mode != BLKmode)
5561 return gen_reg_or_parallel (mode, orig_mode,
5562 SSE_REGNO (sse_regno));
5564 case X86_64_X87_CLASS:
5565 case X86_64_COMPLEX_X87_CLASS:
5566 return gen_rtx_REG (mode, FIRST_STACK_REG);
5567 case X86_64_NO_CLASS:
5568 /* Zero sized array, struct or class. */
5573 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5574 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5575 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5577 && regclass[0] == X86_64_SSE_CLASS
5578 && regclass[1] == X86_64_SSEUP_CLASS
5579 && regclass[2] == X86_64_SSEUP_CLASS
5580 && regclass[3] == X86_64_SSEUP_CLASS
5582 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5585 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5586 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5587 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5588 && regclass[1] == X86_64_INTEGER_CLASS
5589 && (mode == CDImode || mode == TImode || mode == TFmode)
5590 && intreg[0] + 1 == intreg[1])
5591 return gen_rtx_REG (mode, intreg[0]);
5593 /* Otherwise figure out the entries of the PARALLEL. */
5594 for (i = 0; i < n; i++)
5598 switch (regclass[i])
5600 case X86_64_NO_CLASS:
5602 case X86_64_INTEGER_CLASS:
5603 case X86_64_INTEGERSI_CLASS:
5604 /* Merge TImodes on aligned occasions here too. */
5605 if (i * 8 + 8 > bytes)
5606 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5607 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5611 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5612 if (tmpmode == BLKmode)
5614 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5615 gen_rtx_REG (tmpmode, *intreg),
5619 case X86_64_SSESF_CLASS:
5620 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5621 gen_rtx_REG (SFmode,
5622 SSE_REGNO (sse_regno)),
5626 case X86_64_SSEDF_CLASS:
5627 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5628 gen_rtx_REG (DFmode,
5629 SSE_REGNO (sse_regno)),
5633 case X86_64_SSE_CLASS:
5641 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5651 && regclass[1] == X86_64_SSEUP_CLASS
5652 && regclass[2] == X86_64_SSEUP_CLASS
5653 && regclass[3] == X86_64_SSEUP_CLASS);
5660 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5661 gen_rtx_REG (tmpmode,
5662 SSE_REGNO (sse_regno)),
5671 /* Empty aligned struct, union or class. */
5675 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5676 for (i = 0; i < nexps; i++)
5677 XVECEXP (ret, 0, i) = exp [i];
5681 /* Update the data in CUM to advance over an argument of mode MODE
5682 and data type TYPE. (TYPE is null for libcalls where that information
5683 may not be available.) */
5686 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5687 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5703 cum->words += words;
5704 cum->nregs -= words;
5705 cum->regno += words;
5707 if (cum->nregs <= 0)
5715 /* OImode shouldn't be used directly. */
5719 if (cum->float_in_sse < 2)
5722 if (cum->float_in_sse < 1)
5739 if (!type || !AGGREGATE_TYPE_P (type))
5741 cum->sse_words += words;
5742 cum->sse_nregs -= 1;
5743 cum->sse_regno += 1;
5744 if (cum->sse_nregs <= 0)
5757 if (!type || !AGGREGATE_TYPE_P (type))
5759 cum->mmx_words += words;
5760 cum->mmx_nregs -= 1;
5761 cum->mmx_regno += 1;
5762 if (cum->mmx_nregs <= 0)
5773 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5774 tree type, HOST_WIDE_INT words, int named)
5776 int int_nregs, sse_nregs;
5778 /* Unnamed 256bit vector mode parameters are passed on stack. */
5779 if (!named && VALID_AVX256_REG_MODE (mode))
5782 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5783 cum->words += words;
5784 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5786 cum->nregs -= int_nregs;
5787 cum->sse_nregs -= sse_nregs;
5788 cum->regno += int_nregs;
5789 cum->sse_regno += sse_nregs;
5792 cum->words += words;
5796 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5797 HOST_WIDE_INT words)
5799 /* Otherwise, this should be passed indirect. */
5800 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5802 cum->words += words;
5811 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5812 tree type, int named)
5814 HOST_WIDE_INT bytes, words;
5816 if (mode == BLKmode)
5817 bytes = int_size_in_bytes (type);
5819 bytes = GET_MODE_SIZE (mode);
5820 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5823 mode = type_natural_mode (type, NULL);
5825 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5826 function_arg_advance_ms_64 (cum, bytes, words);
5827 else if (TARGET_64BIT)
5828 function_arg_advance_64 (cum, mode, type, words, named);
5830 function_arg_advance_32 (cum, mode, type, bytes, words);
5833 /* Define where to put the arguments to a function.
5834 Value is zero to push the argument on the stack,
5835 or a hard register in which to store the argument.
5837 MODE is the argument's machine mode.
5838 TYPE is the data type of the argument (as a tree).
5839 This is null for libcalls where that information may
5841 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5842 the preceding args and about the function being called.
5843 NAMED is nonzero if this argument is a named parameter
5844 (otherwise it is an extra parameter matching an ellipsis). */
5847 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5848 enum machine_mode orig_mode, tree type,
5849 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5851 static bool warnedsse, warnedmmx;
5853 /* Avoid the AL settings for the Unix64 ABI. */
5854 if (mode == VOIDmode)
5870 if (words <= cum->nregs)
5872 int regno = cum->regno;
5874 /* Fastcall allocates the first two DWORD (SImode) or
5875 smaller arguments to ECX and EDX if it isn't an
5881 || (type && AGGREGATE_TYPE_P (type)))
5884 /* ECX not EAX is the first allocated register. */
5885 if (regno == AX_REG)
5888 return gen_rtx_REG (mode, regno);
5893 if (cum->float_in_sse < 2)
5896 if (cum->float_in_sse < 1)
5900 /* In 32bit, we pass TImode in xmm registers. */
5907 if (!type || !AGGREGATE_TYPE_P (type))
5909 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5912 warning (0, "SSE vector argument without SSE enabled "
5916 return gen_reg_or_parallel (mode, orig_mode,
5917 cum->sse_regno + FIRST_SSE_REG);
5922 /* OImode shouldn't be used directly. */
5931 if (!type || !AGGREGATE_TYPE_P (type))
5934 return gen_reg_or_parallel (mode, orig_mode,
5935 cum->sse_regno + FIRST_SSE_REG);
5944 if (!type || !AGGREGATE_TYPE_P (type))
5946 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5949 warning (0, "MMX vector argument without MMX enabled "
5953 return gen_reg_or_parallel (mode, orig_mode,
5954 cum->mmx_regno + FIRST_MMX_REG);
5963 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5964 enum machine_mode orig_mode, tree type, int named)
5966 /* Handle a hidden AL argument containing number of registers
5967 for varargs x86-64 functions. */
5968 if (mode == VOIDmode)
5969 return GEN_INT (cum->maybe_vaarg
5970 ? (cum->sse_nregs < 0
5971 ? (cum->call_abi == ix86_abi
5973 : (ix86_abi != SYSV_ABI
5974 ? X86_64_SSE_REGPARM_MAX
5975 : X86_64_MS_SSE_REGPARM_MAX))
5990 /* Unnamed 256bit vector mode parameters are passed on stack. */
5996 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5998 &x86_64_int_parameter_registers [cum->regno],
6003 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6004 enum machine_mode orig_mode, int named,
6005 HOST_WIDE_INT bytes)
6009 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6010 We use value of -2 to specify that current function call is MSABI. */
6011 if (mode == VOIDmode)
6012 return GEN_INT (-2);
6014 /* If we've run out of registers, it goes on the stack. */
6015 if (cum->nregs == 0)
6018 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6020 /* Only floating point modes are passed in anything but integer regs. */
6021 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6024 regno = cum->regno + FIRST_SSE_REG;
6029 /* Unnamed floating parameters are passed in both the
6030 SSE and integer registers. */
6031 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6032 t2 = gen_rtx_REG (mode, regno);
6033 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6034 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6035 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6038 /* Handle aggregated types passed in register. */
6039 if (orig_mode == BLKmode)
6041 if (bytes > 0 && bytes <= 8)
6042 mode = (bytes > 4 ? DImode : SImode);
6043 if (mode == BLKmode)
6047 return gen_reg_or_parallel (mode, orig_mode, regno);
6051 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6052 tree type, int named)
6054 enum machine_mode mode = omode;
6055 HOST_WIDE_INT bytes, words;
6057 if (mode == BLKmode)
6058 bytes = int_size_in_bytes (type);
6060 bytes = GET_MODE_SIZE (mode);
6061 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6063 /* To simplify the code below, represent vector types with a vector mode
6064 even if MMX/SSE are not active. */
6065 if (type && TREE_CODE (type) == VECTOR_TYPE)
6066 mode = type_natural_mode (type, cum);
6068 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6069 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6070 else if (TARGET_64BIT)
6071 return function_arg_64 (cum, mode, omode, type, named);
6073 return function_arg_32 (cum, mode, omode, type, bytes, words);
6076 /* A C expression that indicates when an argument must be passed by
6077 reference. If nonzero for an argument, a copy of that argument is
6078 made in memory and a pointer to the argument is passed instead of
6079 the argument itself. The pointer is passed in whatever way is
6080 appropriate for passing a pointer to that type. */
6083 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6084 enum machine_mode mode ATTRIBUTE_UNUSED,
6085 const_tree type, bool named ATTRIBUTE_UNUSED)
6087 /* See Windows x64 Software Convention. */
6088 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6090 int msize = (int) GET_MODE_SIZE (mode);
6093 /* Arrays are passed by reference. */
6094 if (TREE_CODE (type) == ARRAY_TYPE)
6097 if (AGGREGATE_TYPE_P (type))
6099 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6100 are passed by reference. */
6101 msize = int_size_in_bytes (type);
6105 /* __m128 is passed by reference. */
6107 case 1: case 2: case 4: case 8:
6113 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6119 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6122 contains_aligned_value_p (tree type)
6124 enum machine_mode mode = TYPE_MODE (type);
6125 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6129 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6131 if (TYPE_ALIGN (type) < 128)
6134 if (AGGREGATE_TYPE_P (type))
6136 /* Walk the aggregates recursively. */
6137 switch (TREE_CODE (type))
6141 case QUAL_UNION_TYPE:
6145 /* Walk all the structure fields. */
6146 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6148 if (TREE_CODE (field) == FIELD_DECL
6149 && contains_aligned_value_p (TREE_TYPE (field)))
6156 /* Just for use if some languages passes arrays by value. */
6157 if (contains_aligned_value_p (TREE_TYPE (type)))
6168 /* Gives the alignment boundary, in bits, of an argument with the
6169 specified mode and type. */
6172 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6177 /* Since canonical type is used for call, we convert it to
6178 canonical type if needed. */
6179 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6180 type = TYPE_CANONICAL (type);
6181 align = TYPE_ALIGN (type);
6184 align = GET_MODE_ALIGNMENT (mode);
6185 if (align < PARM_BOUNDARY)
6186 align = PARM_BOUNDARY;
6187 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6188 natural boundaries. */
6189 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6191 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6192 make an exception for SSE modes since these require 128bit
6195 The handling here differs from field_alignment. ICC aligns MMX
6196 arguments to 4 byte boundaries, while structure fields are aligned
6197 to 8 byte boundaries. */
6200 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6201 align = PARM_BOUNDARY;
6205 if (!contains_aligned_value_p (type))
6206 align = PARM_BOUNDARY;
6209 if (align > BIGGEST_ALIGNMENT)
6210 align = BIGGEST_ALIGNMENT;
6214 /* Return true if N is a possible register number of function value. */
6217 ix86_function_value_regno_p (int regno)
6224 case FIRST_FLOAT_REG:
6225 /* TODO: The function should depend on current function ABI but
6226 builtins.c would need updating then. Therefore we use the
6228 if (TARGET_64BIT && ix86_abi == MS_ABI)
6230 return TARGET_FLOAT_RETURNS_IN_80387;
6236 if (TARGET_MACHO || TARGET_64BIT)
6244 /* Define how to find the value returned by a function.
6245 VALTYPE is the data type of the value (as a tree).
6246 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6247 otherwise, FUNC is 0. */
6250 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6251 const_tree fntype, const_tree fn)
6255 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6256 we normally prevent this case when mmx is not available. However
6257 some ABIs may require the result to be returned like DImode. */
6258 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6259 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6261 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6262 we prevent this case when sse is not available. However some ABIs
6263 may require the result to be returned like integer TImode. */
6264 else if (mode == TImode
6265 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6266 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6268 /* 32-byte vector modes in %ymm0. */
6269 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6270 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6272 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6273 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6274 regno = FIRST_FLOAT_REG;
6276 /* Most things go in %eax. */
6279 /* Override FP return register with %xmm0 for local functions when
6280 SSE math is enabled or for functions with sseregparm attribute. */
6281 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6283 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6284 if ((sse_level >= 1 && mode == SFmode)
6285 || (sse_level == 2 && mode == DFmode))
6286 regno = FIRST_SSE_REG;
6289 /* OImode shouldn't be used directly. */
6290 gcc_assert (mode != OImode);
6292 return gen_rtx_REG (orig_mode, regno);
6296 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6301 /* Handle libcalls, which don't provide a type node. */
6302 if (valtype == NULL)
6314 return gen_rtx_REG (mode, FIRST_SSE_REG);
6317 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6321 return gen_rtx_REG (mode, AX_REG);
6325 ret = construct_container (mode, orig_mode, valtype, 1,
6326 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6327 x86_64_int_return_registers, 0);
6329 /* For zero sized structures, construct_container returns NULL, but we
6330 need to keep rest of compiler happy by returning meaningful value. */
6332 ret = gen_rtx_REG (orig_mode, AX_REG);
6338 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6340 unsigned int regno = AX_REG;
6344 switch (GET_MODE_SIZE (mode))
6347 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6348 && !COMPLEX_MODE_P (mode))
6349 regno = FIRST_SSE_REG;
6353 if (mode == SFmode || mode == DFmode)
6354 regno = FIRST_SSE_REG;
6360 return gen_rtx_REG (orig_mode, regno);
6364 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6365 enum machine_mode orig_mode, enum machine_mode mode)
6367 const_tree fn, fntype;
6370 if (fntype_or_decl && DECL_P (fntype_or_decl))
6371 fn = fntype_or_decl;
6372 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6374 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6375 return function_value_ms_64 (orig_mode, mode);
6376 else if (TARGET_64BIT)
6377 return function_value_64 (orig_mode, mode, valtype);
6379 return function_value_32 (orig_mode, mode, fntype, fn);
6383 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6384 bool outgoing ATTRIBUTE_UNUSED)
6386 enum machine_mode mode, orig_mode;
6388 orig_mode = TYPE_MODE (valtype);
6389 mode = type_natural_mode (valtype, NULL);
6390 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6394 ix86_libcall_value (enum machine_mode mode)
6396 return ix86_function_value_1 (NULL, NULL, mode, mode);
6399 /* Return true iff type is returned in memory. */
6401 static int ATTRIBUTE_UNUSED
6402 return_in_memory_32 (const_tree type, enum machine_mode mode)
6406 if (mode == BLKmode)
6409 size = int_size_in_bytes (type);
6411 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6414 if (VECTOR_MODE_P (mode) || mode == TImode)
6416 /* User-created vectors small enough to fit in EAX. */
6420 /* MMX/3dNow values are returned in MM0,
6421 except when it doesn't exits. */
6423 return (TARGET_MMX ? 0 : 1);
6425 /* SSE values are returned in XMM0, except when it doesn't exist. */
6427 return (TARGET_SSE ? 0 : 1);
6429 /* AVX values are returned in YMM0, except when it doesn't exist. */
6431 return TARGET_AVX ? 0 : 1;
6440 /* OImode shouldn't be used directly. */
6441 gcc_assert (mode != OImode);
6446 static int ATTRIBUTE_UNUSED
6447 return_in_memory_64 (const_tree type, enum machine_mode mode)
6449 int needed_intregs, needed_sseregs;
6450 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6453 static int ATTRIBUTE_UNUSED
6454 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6456 HOST_WIDE_INT size = int_size_in_bytes (type);
6458 /* __m128 is returned in xmm0. */
6459 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6460 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6463 /* Otherwise, the size must be exactly in [1248]. */
6464 return (size != 1 && size != 2 && size != 4 && size != 8);
6468 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6470 #ifdef SUBTARGET_RETURN_IN_MEMORY
6471 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6473 const enum machine_mode mode = type_natural_mode (type, NULL);
6477 if (ix86_function_type_abi (fntype) == MS_ABI)
6478 return return_in_memory_ms_64 (type, mode);
6480 return return_in_memory_64 (type, mode);
6483 return return_in_memory_32 (type, mode);
6487 /* Return false iff TYPE is returned in memory. This version is used
6488 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6489 but differs notably in that when MMX is available, 8-byte vectors
6490 are returned in memory, rather than in MMX registers. */
6493 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6496 enum machine_mode mode = type_natural_mode (type, NULL);
6499 return return_in_memory_64 (type, mode);
6501 if (mode == BLKmode)
6504 size = int_size_in_bytes (type);
6506 if (VECTOR_MODE_P (mode))
6508 /* Return in memory only if MMX registers *are* available. This
6509 seems backwards, but it is consistent with the existing
6516 else if (mode == TImode)
6518 else if (mode == XFmode)
6524 /* When returning SSE vector types, we have a choice of either
6525 (1) being abi incompatible with a -march switch, or
6526 (2) generating an error.
6527 Given no good solution, I think the safest thing is one warning.
6528 The user won't be able to use -Werror, but....
6530 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6531 called in response to actually generating a caller or callee that
6532 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6533 via aggregate_value_p for general type probing from tree-ssa. */
6536 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6538 static bool warnedsse, warnedmmx;
6540 if (!TARGET_64BIT && type)
6542 /* Look at the return type of the function, not the function type. */
6543 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6545 if (!TARGET_SSE && !warnedsse)
6548 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6551 warning (0, "SSE vector return without SSE enabled "
6556 if (!TARGET_MMX && !warnedmmx)
6558 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6561 warning (0, "MMX vector return without MMX enabled "
6571 /* Create the va_list data type. */
6573 /* Returns the calling convention specific va_list date type.
6574 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6577 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6579 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6581 /* For i386 we use plain pointer to argument area. */
6582 if (!TARGET_64BIT || abi == MS_ABI)
6583 return build_pointer_type (char_type_node);
6585 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6586 type_decl = build_decl (BUILTINS_LOCATION,
6587 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6589 f_gpr = build_decl (BUILTINS_LOCATION,
6590 FIELD_DECL, get_identifier ("gp_offset"),
6591 unsigned_type_node);
6592 f_fpr = build_decl (BUILTINS_LOCATION,
6593 FIELD_DECL, get_identifier ("fp_offset"),
6594 unsigned_type_node);
6595 f_ovf = build_decl (BUILTINS_LOCATION,
6596 FIELD_DECL, get_identifier ("overflow_arg_area"),
6598 f_sav = build_decl (BUILTINS_LOCATION,
6599 FIELD_DECL, get_identifier ("reg_save_area"),
6602 va_list_gpr_counter_field = f_gpr;
6603 va_list_fpr_counter_field = f_fpr;
6605 DECL_FIELD_CONTEXT (f_gpr) = record;
6606 DECL_FIELD_CONTEXT (f_fpr) = record;
6607 DECL_FIELD_CONTEXT (f_ovf) = record;
6608 DECL_FIELD_CONTEXT (f_sav) = record;
6610 TREE_CHAIN (record) = type_decl;
6611 TYPE_NAME (record) = type_decl;
6612 TYPE_FIELDS (record) = f_gpr;
6613 TREE_CHAIN (f_gpr) = f_fpr;
6614 TREE_CHAIN (f_fpr) = f_ovf;
6615 TREE_CHAIN (f_ovf) = f_sav;
6617 layout_type (record);
6619 /* The correct type is an array type of one element. */
6620 return build_array_type (record, build_index_type (size_zero_node));
6623 /* Setup the builtin va_list data type and for 64-bit the additional
6624 calling convention specific va_list data types. */
6627 ix86_build_builtin_va_list (void)
6629 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6631 /* Initialize abi specific va_list builtin types. */
6635 if (ix86_abi == MS_ABI)
6637 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6638 if (TREE_CODE (t) != RECORD_TYPE)
6639 t = build_variant_type_copy (t);
6640 sysv_va_list_type_node = t;
6645 if (TREE_CODE (t) != RECORD_TYPE)
6646 t = build_variant_type_copy (t);
6647 sysv_va_list_type_node = t;
6649 if (ix86_abi != MS_ABI)
6651 t = ix86_build_builtin_va_list_abi (MS_ABI);
6652 if (TREE_CODE (t) != RECORD_TYPE)
6653 t = build_variant_type_copy (t);
6654 ms_va_list_type_node = t;
6659 if (TREE_CODE (t) != RECORD_TYPE)
6660 t = build_variant_type_copy (t);
6661 ms_va_list_type_node = t;
6668 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6671 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6680 int regparm = ix86_regparm;
6682 if (cum->call_abi != ix86_abi)
6683 regparm = (ix86_abi != SYSV_ABI
6684 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6686 /* GPR size of varargs save area. */
6687 if (cfun->va_list_gpr_size)
6688 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6690 ix86_varargs_gpr_size = 0;
6692 /* FPR size of varargs save area. We don't need it if we don't pass
6693 anything in SSE registers. */
6694 if (cum->sse_nregs && cfun->va_list_fpr_size)
6695 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6697 ix86_varargs_fpr_size = 0;
6699 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6702 save_area = frame_pointer_rtx;
6703 set = get_varargs_alias_set ();
6705 for (i = cum->regno;
6707 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6710 mem = gen_rtx_MEM (Pmode,
6711 plus_constant (save_area, i * UNITS_PER_WORD));
6712 MEM_NOTRAP_P (mem) = 1;
6713 set_mem_alias_set (mem, set);
6714 emit_move_insn (mem, gen_rtx_REG (Pmode,
6715 x86_64_int_parameter_registers[i]));
6718 if (ix86_varargs_fpr_size)
6720 /* Now emit code to save SSE registers. The AX parameter contains number
6721 of SSE parameter registers used to call this function. We use
6722 sse_prologue_save insn template that produces computed jump across
6723 SSE saves. We need some preparation work to get this working. */
6725 label = gen_label_rtx ();
6726 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6728 /* Compute address to jump to :
6729 label - eax*4 + nnamed_sse_arguments*4 Or
6730 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6731 tmp_reg = gen_reg_rtx (Pmode);
6732 nsse_reg = gen_reg_rtx (Pmode);
6733 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6734 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6735 gen_rtx_MULT (Pmode, nsse_reg,
6738 /* vmovaps is one byte longer than movaps. */
6740 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6741 gen_rtx_PLUS (Pmode, tmp_reg,
6747 gen_rtx_CONST (DImode,
6748 gen_rtx_PLUS (DImode,
6750 GEN_INT (cum->sse_regno
6751 * (TARGET_AVX ? 5 : 4)))));
6753 emit_move_insn (nsse_reg, label_ref);
6754 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6756 /* Compute address of memory block we save into. We always use pointer
6757 pointing 127 bytes after first byte to store - this is needed to keep
6758 instruction size limited by 4 bytes (5 bytes for AVX) with one
6759 byte displacement. */
6760 tmp_reg = gen_reg_rtx (Pmode);
6761 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6762 plus_constant (save_area,
6763 ix86_varargs_gpr_size + 127)));
6764 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6765 MEM_NOTRAP_P (mem) = 1;
6766 set_mem_alias_set (mem, set);
6767 set_mem_align (mem, BITS_PER_WORD);
6769 /* And finally do the dirty job! */
6770 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6771 GEN_INT (cum->sse_regno), label));
6776 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6778 alias_set_type set = get_varargs_alias_set ();
6781 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6785 mem = gen_rtx_MEM (Pmode,
6786 plus_constant (virtual_incoming_args_rtx,
6787 i * UNITS_PER_WORD));
6788 MEM_NOTRAP_P (mem) = 1;
6789 set_mem_alias_set (mem, set);
6791 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6792 emit_move_insn (mem, reg);
6797 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6798 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6801 CUMULATIVE_ARGS next_cum;
6804 /* This argument doesn't appear to be used anymore. Which is good,
6805 because the old code here didn't suppress rtl generation. */
6806 gcc_assert (!no_rtl);
6811 fntype = TREE_TYPE (current_function_decl);
6813 /* For varargs, we do not want to skip the dummy va_dcl argument.
6814 For stdargs, we do want to skip the last named argument. */
6816 if (stdarg_p (fntype))
6817 function_arg_advance (&next_cum, mode, type, 1);
6819 if (cum->call_abi == MS_ABI)
6820 setup_incoming_varargs_ms_64 (&next_cum);
6822 setup_incoming_varargs_64 (&next_cum);
6825 /* Checks if TYPE is of kind va_list char *. */
6828 is_va_list_char_pointer (tree type)
6832 /* For 32-bit it is always true. */
6835 canonic = ix86_canonical_va_list_type (type);
6836 return (canonic == ms_va_list_type_node
6837 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6840 /* Implement va_start. */
6843 ix86_va_start (tree valist, rtx nextarg)
6845 HOST_WIDE_INT words, n_gpr, n_fpr;
6846 tree f_gpr, f_fpr, f_ovf, f_sav;
6847 tree gpr, fpr, ovf, sav, t;
6850 /* Only 64bit target needs something special. */
6851 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6853 std_expand_builtin_va_start (valist, nextarg);
6857 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6858 f_fpr = TREE_CHAIN (f_gpr);
6859 f_ovf = TREE_CHAIN (f_fpr);
6860 f_sav = TREE_CHAIN (f_ovf);
6862 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6863 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6864 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6865 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6866 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6868 /* Count number of gp and fp argument registers used. */
6869 words = crtl->args.info.words;
6870 n_gpr = crtl->args.info.regno;
6871 n_fpr = crtl->args.info.sse_regno;
6873 if (cfun->va_list_gpr_size)
6875 type = TREE_TYPE (gpr);
6876 t = build2 (MODIFY_EXPR, type,
6877 gpr, build_int_cst (type, n_gpr * 8));
6878 TREE_SIDE_EFFECTS (t) = 1;
6879 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6882 if (TARGET_SSE && cfun->va_list_fpr_size)
6884 type = TREE_TYPE (fpr);
6885 t = build2 (MODIFY_EXPR, type, fpr,
6886 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6887 TREE_SIDE_EFFECTS (t) = 1;
6888 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6891 /* Find the overflow area. */
6892 type = TREE_TYPE (ovf);
6893 t = make_tree (type, crtl->args.internal_arg_pointer);
6895 t = build2 (POINTER_PLUS_EXPR, type, t,
6896 size_int (words * UNITS_PER_WORD));
6897 t = build2 (MODIFY_EXPR, type, ovf, t);
6898 TREE_SIDE_EFFECTS (t) = 1;
6899 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6901 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6903 /* Find the register save area.
6904 Prologue of the function save it right above stack frame. */
6905 type = TREE_TYPE (sav);
6906 t = make_tree (type, frame_pointer_rtx);
6907 if (!ix86_varargs_gpr_size)
6908 t = build2 (POINTER_PLUS_EXPR, type, t,
6909 size_int (-8 * X86_64_REGPARM_MAX));
6910 t = build2 (MODIFY_EXPR, type, sav, t);
6911 TREE_SIDE_EFFECTS (t) = 1;
6912 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6916 /* Implement va_arg. */
6919 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6922 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6923 tree f_gpr, f_fpr, f_ovf, f_sav;
6924 tree gpr, fpr, ovf, sav, t;
6926 tree lab_false, lab_over = NULL_TREE;
6931 enum machine_mode nat_mode;
6934 /* Only 64bit target needs something special. */
6935 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6936 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6938 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6939 f_fpr = TREE_CHAIN (f_gpr);
6940 f_ovf = TREE_CHAIN (f_fpr);
6941 f_sav = TREE_CHAIN (f_ovf);
6943 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6944 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6945 valist = build_va_arg_indirect_ref (valist);
6946 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6947 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6948 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6950 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6952 type = build_pointer_type (type);
6953 size = int_size_in_bytes (type);
6954 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6956 nat_mode = type_natural_mode (type, NULL);
6965 /* Unnamed 256bit vector mode parameters are passed on stack. */
6966 if (ix86_cfun_abi () == SYSV_ABI)
6973 container = construct_container (nat_mode, TYPE_MODE (type),
6974 type, 0, X86_64_REGPARM_MAX,
6975 X86_64_SSE_REGPARM_MAX, intreg,
6980 /* Pull the value out of the saved registers. */
6982 addr = create_tmp_var (ptr_type_node, "addr");
6986 int needed_intregs, needed_sseregs;
6988 tree int_addr, sse_addr;
6990 lab_false = create_artificial_label (UNKNOWN_LOCATION);
6991 lab_over = create_artificial_label (UNKNOWN_LOCATION);
6993 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6995 need_temp = (!REG_P (container)
6996 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6997 || TYPE_ALIGN (type) > 128));
6999 /* In case we are passing structure, verify that it is consecutive block
7000 on the register save area. If not we need to do moves. */
7001 if (!need_temp && !REG_P (container))
7003 /* Verify that all registers are strictly consecutive */
7004 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7008 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7010 rtx slot = XVECEXP (container, 0, i);
7011 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7012 || INTVAL (XEXP (slot, 1)) != i * 16)
7020 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7022 rtx slot = XVECEXP (container, 0, i);
7023 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7024 || INTVAL (XEXP (slot, 1)) != i * 8)
7036 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7037 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7040 /* First ensure that we fit completely in registers. */
7043 t = build_int_cst (TREE_TYPE (gpr),
7044 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7045 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7046 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7047 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7048 gimplify_and_add (t, pre_p);
7052 t = build_int_cst (TREE_TYPE (fpr),
7053 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7054 + X86_64_REGPARM_MAX * 8);
7055 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7056 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7057 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7058 gimplify_and_add (t, pre_p);
7061 /* Compute index to start of area used for integer regs. */
7064 /* int_addr = gpr + sav; */
7065 t = fold_convert (sizetype, gpr);
7066 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7067 gimplify_assign (int_addr, t, pre_p);
7071 /* sse_addr = fpr + sav; */
7072 t = fold_convert (sizetype, fpr);
7073 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7074 gimplify_assign (sse_addr, t, pre_p);
7079 tree temp = create_tmp_var (type, "va_arg_tmp");
7082 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7083 gimplify_assign (addr, t, pre_p);
7085 for (i = 0; i < XVECLEN (container, 0); i++)
7087 rtx slot = XVECEXP (container, 0, i);
7088 rtx reg = XEXP (slot, 0);
7089 enum machine_mode mode = GET_MODE (reg);
7090 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7091 tree addr_type = build_pointer_type (piece_type);
7092 tree daddr_type = build_pointer_type_for_mode (piece_type,
7096 tree dest_addr, dest;
7098 if (SSE_REGNO_P (REGNO (reg)))
7100 src_addr = sse_addr;
7101 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7105 src_addr = int_addr;
7106 src_offset = REGNO (reg) * 8;
7108 src_addr = fold_convert (addr_type, src_addr);
7109 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7110 size_int (src_offset));
7111 src = build_va_arg_indirect_ref (src_addr);
7113 dest_addr = fold_convert (daddr_type, addr);
7114 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7115 size_int (INTVAL (XEXP (slot, 1))));
7116 dest = build_va_arg_indirect_ref (dest_addr);
7118 gimplify_assign (dest, src, pre_p);
7124 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7125 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7126 gimplify_assign (gpr, t, pre_p);
7131 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7132 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7133 gimplify_assign (fpr, t, pre_p);
7136 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7138 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7141 /* ... otherwise out of the overflow area. */
7143 /* When we align parameter on stack for caller, if the parameter
7144 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7145 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7146 here with caller. */
7147 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7148 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7149 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7151 /* Care for on-stack alignment if needed. */
7152 if (arg_boundary <= 64
7153 || integer_zerop (TYPE_SIZE (type)))
7157 HOST_WIDE_INT align = arg_boundary / 8;
7158 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7159 size_int (align - 1));
7160 t = fold_convert (sizetype, t);
7161 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7163 t = fold_convert (TREE_TYPE (ovf), t);
7165 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7166 gimplify_assign (addr, t, pre_p);
7168 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7169 size_int (rsize * UNITS_PER_WORD));
7170 gimplify_assign (unshare_expr (ovf), t, pre_p);
7173 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7175 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7176 addr = fold_convert (ptrtype, addr);
7179 addr = build_va_arg_indirect_ref (addr);
7180 return build_va_arg_indirect_ref (addr);
7183 /* Return nonzero if OPNUM's MEM should be matched
7184 in movabs* patterns. */
7187 ix86_check_movabs (rtx insn, int opnum)
7191 set = PATTERN (insn);
7192 if (GET_CODE (set) == PARALLEL)
7193 set = XVECEXP (set, 0, 0);
7194 gcc_assert (GET_CODE (set) == SET);
7195 mem = XEXP (set, opnum);
7196 while (GET_CODE (mem) == SUBREG)
7197 mem = SUBREG_REG (mem);
7198 gcc_assert (MEM_P (mem));
7199 return (volatile_ok || !MEM_VOLATILE_P (mem));
7202 /* Initialize the table of extra 80387 mathematical constants. */
7205 init_ext_80387_constants (void)
7207 static const char * cst[5] =
7209 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7210 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7211 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7212 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7213 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7217 for (i = 0; i < 5; i++)
7219 real_from_string (&ext_80387_constants_table[i], cst[i]);
7220 /* Ensure each constant is rounded to XFmode precision. */
7221 real_convert (&ext_80387_constants_table[i],
7222 XFmode, &ext_80387_constants_table[i]);
7225 ext_80387_constants_init = 1;
7228 /* Return true if the constant is something that can be loaded with
7229 a special instruction. */
7232 standard_80387_constant_p (rtx x)
7234 enum machine_mode mode = GET_MODE (x);
7238 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7241 if (x == CONST0_RTX (mode))
7243 if (x == CONST1_RTX (mode))
7246 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7248 /* For XFmode constants, try to find a special 80387 instruction when
7249 optimizing for size or on those CPUs that benefit from them. */
7251 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7255 if (! ext_80387_constants_init)
7256 init_ext_80387_constants ();
7258 for (i = 0; i < 5; i++)
7259 if (real_identical (&r, &ext_80387_constants_table[i]))
7263 /* Load of the constant -0.0 or -1.0 will be split as
7264 fldz;fchs or fld1;fchs sequence. */
7265 if (real_isnegzero (&r))
7267 if (real_identical (&r, &dconstm1))
7273 /* Return the opcode of the special instruction to be used to load
7277 standard_80387_constant_opcode (rtx x)
7279 switch (standard_80387_constant_p (x))
7303 /* Return the CONST_DOUBLE representing the 80387 constant that is
7304 loaded by the specified special instruction. The argument IDX
7305 matches the return value from standard_80387_constant_p. */
7308 standard_80387_constant_rtx (int idx)
7312 if (! ext_80387_constants_init)
7313 init_ext_80387_constants ();
7329 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7333 /* Return 1 if X is all 0s and 2 if x is all 1s
7334 in supported SSE vector mode. */
7337 standard_sse_constant_p (rtx x)
7339 enum machine_mode mode = GET_MODE (x);
7341 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7343 if (vector_all_ones_operand (x, mode))
7359 /* Return the opcode of the special instruction to be used to load
7363 standard_sse_constant_opcode (rtx insn, rtx x)
7365 switch (standard_sse_constant_p (x))
7368 switch (get_attr_mode (insn))
7371 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7373 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7375 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7377 return "vxorps\t%x0, %x0, %x0";
7379 return "vxorpd\t%x0, %x0, %x0";
7381 return "vpxor\t%x0, %x0, %x0";
7386 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7393 /* Returns 1 if OP contains a symbol reference */
7396 symbolic_reference_mentioned_p (rtx op)
7401 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7404 fmt = GET_RTX_FORMAT (GET_CODE (op));
7405 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7411 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7412 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7416 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7423 /* Return 1 if it is appropriate to emit `ret' instructions in the
7424 body of a function. Do this only if the epilogue is simple, needing a
7425 couple of insns. Prior to reloading, we can't tell how many registers
7426 must be saved, so return 0 then. Return 0 if there is no frame
7427 marker to de-allocate. */
7430 ix86_can_use_return_insn_p (void)
7432 struct ix86_frame frame;
7434 if (! reload_completed || frame_pointer_needed)
7437 /* Don't allow more than 32 pop, since that's all we can do
7438 with one instruction. */
7439 if (crtl->args.pops_args
7440 && crtl->args.size >= 32768)
7443 ix86_compute_frame_layout (&frame);
7444 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7447 /* Value should be nonzero if functions must have frame pointers.
7448 Zero means the frame pointer need not be set up (and parms may
7449 be accessed via the stack pointer) in functions that seem suitable. */
7452 ix86_frame_pointer_required (void)
7454 /* If we accessed previous frames, then the generated code expects
7455 to be able to access the saved ebp value in our frame. */
7456 if (cfun->machine->accesses_prev_frame)
7459 /* Several x86 os'es need a frame pointer for other reasons,
7460 usually pertaining to setjmp. */
7461 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7464 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7465 the frame pointer by default. Turn it back on now if we've not
7466 got a leaf function. */
7467 if (TARGET_OMIT_LEAF_FRAME_POINTER
7468 && (!current_function_is_leaf
7469 || ix86_current_function_calls_tls_descriptor))
7478 /* Record that the current function accesses previous call frames. */
7481 ix86_setup_frame_addresses (void)
7483 cfun->machine->accesses_prev_frame = 1;
7486 #ifndef USE_HIDDEN_LINKONCE
7487 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7488 # define USE_HIDDEN_LINKONCE 1
7490 # define USE_HIDDEN_LINKONCE 0
7494 static int pic_labels_used;
7496 /* Fills in the label name that should be used for a pc thunk for
7497 the given register. */
7500 get_pc_thunk_name (char name[32], unsigned int regno)
7502 gcc_assert (!TARGET_64BIT);
7504 if (USE_HIDDEN_LINKONCE)
7505 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7507 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7511 /* This function generates code for -fpic that loads %ebx with
7512 the return address of the caller and then returns. */
7515 ix86_file_end (void)
7520 for (regno = 0; regno < 8; ++regno)
7524 if (! ((pic_labels_used >> regno) & 1))
7527 get_pc_thunk_name (name, regno);
7532 switch_to_section (darwin_sections[text_coal_section]);
7533 fputs ("\t.weak_definition\t", asm_out_file);
7534 assemble_name (asm_out_file, name);
7535 fputs ("\n\t.private_extern\t", asm_out_file);
7536 assemble_name (asm_out_file, name);
7537 fputs ("\n", asm_out_file);
7538 ASM_OUTPUT_LABEL (asm_out_file, name);
7542 if (USE_HIDDEN_LINKONCE)
7546 decl = build_decl (BUILTINS_LOCATION,
7547 FUNCTION_DECL, get_identifier (name),
7549 TREE_PUBLIC (decl) = 1;
7550 TREE_STATIC (decl) = 1;
7551 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7553 (*targetm.asm_out.unique_section) (decl, 0);
7554 switch_to_section (get_named_section (decl, NULL, 0));
7556 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7557 fputs ("\t.hidden\t", asm_out_file);
7558 assemble_name (asm_out_file, name);
7559 putc ('\n', asm_out_file);
7560 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7564 switch_to_section (text_section);
7565 ASM_OUTPUT_LABEL (asm_out_file, name);
7568 xops[0] = gen_rtx_REG (Pmode, regno);
7569 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7570 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7571 output_asm_insn ("ret", xops);
7574 if (NEED_INDICATE_EXEC_STACK)
7575 file_end_indicate_exec_stack ();
7578 /* Emit code for the SET_GOT patterns. */
7581 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7587 if (TARGET_VXWORKS_RTP && flag_pic)
7589 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7590 xops[2] = gen_rtx_MEM (Pmode,
7591 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7592 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7594 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7595 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7596 an unadorned address. */
7597 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7598 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7599 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7603 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7605 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7607 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7610 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7612 output_asm_insn ("call\t%a2", xops);
7615 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7616 is what will be referenced by the Mach-O PIC subsystem. */
7618 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7621 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7622 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7625 output_asm_insn ("pop%z0\t%0", xops);
7630 get_pc_thunk_name (name, REGNO (dest));
7631 pic_labels_used |= 1 << REGNO (dest);
7633 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7634 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7635 output_asm_insn ("call\t%X2", xops);
7636 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7637 is what will be referenced by the Mach-O PIC subsystem. */
7640 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7642 targetm.asm_out.internal_label (asm_out_file, "L",
7643 CODE_LABEL_NUMBER (label));
7650 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7651 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7653 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7658 /* Generate an "push" pattern for input ARG. */
7663 if (ix86_cfa_state->reg == stack_pointer_rtx)
7664 ix86_cfa_state->offset += UNITS_PER_WORD;
7666 return gen_rtx_SET (VOIDmode,
7668 gen_rtx_PRE_DEC (Pmode,
7669 stack_pointer_rtx)),
7673 /* Return >= 0 if there is an unused call-clobbered register available
7674 for the entire function. */
7677 ix86_select_alt_pic_regnum (void)
7679 if (current_function_is_leaf && !crtl->profile
7680 && !ix86_current_function_calls_tls_descriptor)
7683 /* Can't use the same register for both PIC and DRAP. */
7685 drap = REGNO (crtl->drap_reg);
7688 for (i = 2; i >= 0; --i)
7689 if (i != drap && !df_regs_ever_live_p (i))
7693 return INVALID_REGNUM;
7696 /* Return 1 if we need to save REGNO. */
7698 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7700 if (pic_offset_table_rtx
7701 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7702 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7704 || crtl->calls_eh_return
7705 || crtl->uses_const_pool))
7707 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7712 if (crtl->calls_eh_return && maybe_eh_return)
7717 unsigned test = EH_RETURN_DATA_REGNO (i);
7718 if (test == INVALID_REGNUM)
7725 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7728 return (df_regs_ever_live_p (regno)
7729 && !call_used_regs[regno]
7730 && !fixed_regs[regno]
7731 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7734 /* Return number of saved general prupose registers. */
7737 ix86_nsaved_regs (void)
7742 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7743 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7748 /* Return number of saved SSE registrers. */
7751 ix86_nsaved_sseregs (void)
7756 if (ix86_cfun_abi () != MS_ABI)
7758 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7759 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7764 /* Given FROM and TO register numbers, say whether this elimination is
7765 allowed. If stack alignment is needed, we can only replace argument
7766 pointer with hard frame pointer, or replace frame pointer with stack
7767 pointer. Otherwise, frame pointer elimination is automatically
7768 handled and all other eliminations are valid. */
7771 ix86_can_eliminate (const int from, const int to)
7773 if (stack_realign_fp)
7774 return ((from == ARG_POINTER_REGNUM
7775 && to == HARD_FRAME_POINTER_REGNUM)
7776 || (from == FRAME_POINTER_REGNUM
7777 && to == STACK_POINTER_REGNUM));
7779 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7782 /* Return the offset between two registers, one to be eliminated, and the other
7783 its replacement, at the start of a routine. */
7786 ix86_initial_elimination_offset (int from, int to)
7788 struct ix86_frame frame;
7789 ix86_compute_frame_layout (&frame);
7791 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7792 return frame.hard_frame_pointer_offset;
7793 else if (from == FRAME_POINTER_REGNUM
7794 && to == HARD_FRAME_POINTER_REGNUM)
7795 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7798 gcc_assert (to == STACK_POINTER_REGNUM);
7800 if (from == ARG_POINTER_REGNUM)
7801 return frame.stack_pointer_offset;
7803 gcc_assert (from == FRAME_POINTER_REGNUM);
7804 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7808 /* In a dynamically-aligned function, we can't know the offset from
7809 stack pointer to frame pointer, so we must ensure that setjmp
7810 eliminates fp against the hard fp (%ebp) rather than trying to
7811 index from %esp up to the top of the frame across a gap that is
7812 of unknown (at compile-time) size. */
7814 ix86_builtin_setjmp_frame_value (void)
7816 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7819 /* Fill structure ix86_frame about frame of currently computed function. */
7822 ix86_compute_frame_layout (struct ix86_frame *frame)
7824 HOST_WIDE_INT total_size;
7825 unsigned int stack_alignment_needed;
7826 HOST_WIDE_INT offset;
7827 unsigned int preferred_alignment;
7828 HOST_WIDE_INT size = get_frame_size ();
7830 frame->nregs = ix86_nsaved_regs ();
7831 frame->nsseregs = ix86_nsaved_sseregs ();
7834 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7835 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7837 /* MS ABI seem to require stack alignment to be always 16 except for function
7839 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7841 preferred_alignment = 16;
7842 stack_alignment_needed = 16;
7843 crtl->preferred_stack_boundary = 128;
7844 crtl->stack_alignment_needed = 128;
7847 gcc_assert (!size || stack_alignment_needed);
7848 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7849 gcc_assert (preferred_alignment <= stack_alignment_needed);
7851 /* During reload iteration the amount of registers saved can change.
7852 Recompute the value as needed. Do not recompute when amount of registers
7853 didn't change as reload does multiple calls to the function and does not
7854 expect the decision to change within single iteration. */
7855 if (!optimize_function_for_size_p (cfun)
7856 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7858 int count = frame->nregs;
7860 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7861 /* The fast prologue uses move instead of push to save registers. This
7862 is significantly longer, but also executes faster as modern hardware
7863 can execute the moves in parallel, but can't do that for push/pop.
7865 Be careful about choosing what prologue to emit: When function takes
7866 many instructions to execute we may use slow version as well as in
7867 case function is known to be outside hot spot (this is known with
7868 feedback only). Weight the size of function by number of registers
7869 to save as it is cheap to use one or two push instructions but very
7870 slow to use many of them. */
7872 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7873 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7874 || (flag_branch_probabilities
7875 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7876 cfun->machine->use_fast_prologue_epilogue = false;
7878 cfun->machine->use_fast_prologue_epilogue
7879 = !expensive_function_p (count);
7881 if (TARGET_PROLOGUE_USING_MOVE
7882 && cfun->machine->use_fast_prologue_epilogue)
7883 frame->save_regs_using_mov = true;
7885 frame->save_regs_using_mov = false;
7888 /* Skip return address and saved base pointer. */
7889 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7891 frame->hard_frame_pointer_offset = offset;
7893 /* Set offset to aligned because the realigned frame starts from
7895 if (stack_realign_fp)
7896 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7898 /* Register save area */
7899 offset += frame->nregs * UNITS_PER_WORD;
7901 /* Align SSE reg save area. */
7902 if (frame->nsseregs)
7903 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7905 frame->padding0 = 0;
7907 /* SSE register save area. */
7908 offset += frame->padding0 + frame->nsseregs * 16;
7911 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7912 offset += frame->va_arg_size;
7914 /* Align start of frame for local function. */
7915 frame->padding1 = ((offset + stack_alignment_needed - 1)
7916 & -stack_alignment_needed) - offset;
7918 offset += frame->padding1;
7920 /* Frame pointer points here. */
7921 frame->frame_pointer_offset = offset;
7925 /* Add outgoing arguments area. Can be skipped if we eliminated
7926 all the function calls as dead code.
7927 Skipping is however impossible when function calls alloca. Alloca
7928 expander assumes that last crtl->outgoing_args_size
7929 of stack frame are unused. */
7930 if (ACCUMULATE_OUTGOING_ARGS
7931 && (!current_function_is_leaf || cfun->calls_alloca
7932 || ix86_current_function_calls_tls_descriptor))
7934 offset += crtl->outgoing_args_size;
7935 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7938 frame->outgoing_arguments_size = 0;
7940 /* Align stack boundary. Only needed if we're calling another function
7942 if (!current_function_is_leaf || cfun->calls_alloca
7943 || ix86_current_function_calls_tls_descriptor)
7944 frame->padding2 = ((offset + preferred_alignment - 1)
7945 & -preferred_alignment) - offset;
7947 frame->padding2 = 0;
7949 offset += frame->padding2;
7951 /* We've reached end of stack frame. */
7952 frame->stack_pointer_offset = offset;
7954 /* Size prologue needs to allocate. */
7955 frame->to_allocate =
7956 (size + frame->padding1 + frame->padding2
7957 + frame->outgoing_arguments_size + frame->va_arg_size);
7959 if ((!frame->to_allocate && frame->nregs <= 1)
7960 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7961 frame->save_regs_using_mov = false;
7963 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7964 && current_function_sp_is_unchanging
7965 && current_function_is_leaf
7966 && !ix86_current_function_calls_tls_descriptor)
7968 frame->red_zone_size = frame->to_allocate;
7969 if (frame->save_regs_using_mov)
7970 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7971 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7972 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7975 frame->red_zone_size = 0;
7976 frame->to_allocate -= frame->red_zone_size;
7977 frame->stack_pointer_offset -= frame->red_zone_size;
7979 fprintf (stderr, "\n");
7980 fprintf (stderr, "size: %ld\n", (long)size);
7981 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7982 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7983 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7984 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7985 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7986 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7987 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7988 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7989 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7990 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7991 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7992 (long)frame->hard_frame_pointer_offset);
7993 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7994 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7995 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7996 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
8000 /* Emit code to save registers in the prologue. */
8003 ix86_emit_save_regs (void)
8008 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8009 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8011 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8012 RTX_FRAME_RELATED_P (insn) = 1;
8016 /* Emit code to save registers using MOV insns. First register
8017 is restored from POINTER + OFFSET. */
8019 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8024 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8025 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8027 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8029 gen_rtx_REG (Pmode, regno));
8030 RTX_FRAME_RELATED_P (insn) = 1;
8031 offset += UNITS_PER_WORD;
8035 /* Emit code to save registers using MOV insns. First register
8036 is restored from POINTER + OFFSET. */
8038 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8044 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8045 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8047 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8048 set_mem_align (mem, 128);
8049 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8050 RTX_FRAME_RELATED_P (insn) = 1;
8055 static GTY(()) rtx queued_cfa_restores;
8057 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8058 manipulation insn. Don't add it if the previously
8059 saved value will be left untouched within stack red-zone till return,
8060 as unwinders can find the same value in the register and
8064 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8067 && !TARGET_64BIT_MS_ABI
8068 && red_offset + RED_ZONE_SIZE >= 0
8069 && crtl->args.pops_args < 65536)
8074 add_reg_note (insn, REG_CFA_RESTORE, reg);
8075 RTX_FRAME_RELATED_P (insn) = 1;
8079 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8082 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8085 ix86_add_queued_cfa_restore_notes (rtx insn)
8088 if (!queued_cfa_restores)
8090 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8092 XEXP (last, 1) = REG_NOTES (insn);
8093 REG_NOTES (insn) = queued_cfa_restores;
8094 queued_cfa_restores = NULL_RTX;
8095 RTX_FRAME_RELATED_P (insn) = 1;
8098 /* Expand prologue or epilogue stack adjustment.
8099 The pattern exist to put a dependency on all ebp-based memory accesses.
8100 STYLE should be negative if instructions should be marked as frame related,
8101 zero if %r11 register is live and cannot be freely used and positive
8105 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8106 int style, bool set_cfa)
8111 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8112 else if (x86_64_immediate_operand (offset, DImode))
8113 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8117 /* r11 is used by indirect sibcall return as well, set before the
8118 epilogue and used after the epilogue. ATM indirect sibcall
8119 shouldn't be used together with huge frame sizes in one
8120 function because of the frame_size check in sibcall.c. */
8122 r11 = gen_rtx_REG (DImode, R11_REG);
8123 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8125 RTX_FRAME_RELATED_P (insn) = 1;
8126 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8131 ix86_add_queued_cfa_restore_notes (insn);
8137 gcc_assert (ix86_cfa_state->reg == src);
8138 ix86_cfa_state->offset += INTVAL (offset);
8139 ix86_cfa_state->reg = dest;
8141 r = gen_rtx_PLUS (Pmode, src, offset);
8142 r = gen_rtx_SET (VOIDmode, dest, r);
8143 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8144 RTX_FRAME_RELATED_P (insn) = 1;
8147 RTX_FRAME_RELATED_P (insn) = 1;
8150 /* Find an available register to be used as dynamic realign argument
8151 pointer regsiter. Such a register will be written in prologue and
8152 used in begin of body, so it must not be
8153 1. parameter passing register.
8155 We reuse static-chain register if it is available. Otherwise, we
8156 use DI for i386 and R13 for x86-64. We chose R13 since it has
8159 Return: the regno of chosen register. */
8162 find_drap_reg (void)
8164 tree decl = cfun->decl;
8168 /* Use R13 for nested function or function need static chain.
8169 Since function with tail call may use any caller-saved
8170 registers in epilogue, DRAP must not use caller-saved
8171 register in such case. */
8172 if ((decl_function_context (decl)
8173 && !DECL_NO_STATIC_CHAIN (decl))
8174 || crtl->tail_call_emit)
8181 /* Use DI for nested function or function need static chain.
8182 Since function with tail call may use any caller-saved
8183 registers in epilogue, DRAP must not use caller-saved
8184 register in such case. */
8185 if ((decl_function_context (decl)
8186 && !DECL_NO_STATIC_CHAIN (decl))
8187 || crtl->tail_call_emit)
8190 /* Reuse static chain register if it isn't used for parameter
8192 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8193 && !lookup_attribute ("fastcall",
8194 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8201 /* Update incoming stack boundary and estimated stack alignment. */
8204 ix86_update_stack_boundary (void)
8206 /* Prefer the one specified at command line. */
8207 ix86_incoming_stack_boundary
8208 = (ix86_user_incoming_stack_boundary
8209 ? ix86_user_incoming_stack_boundary
8210 : ix86_default_incoming_stack_boundary);
8212 /* Incoming stack alignment can be changed on individual functions
8213 via force_align_arg_pointer attribute. We use the smallest
8214 incoming stack boundary. */
8215 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8216 && lookup_attribute (ix86_force_align_arg_pointer_string,
8217 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8218 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8220 /* The incoming stack frame has to be aligned at least at
8221 parm_stack_boundary. */
8222 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8223 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8225 /* Stack at entrance of main is aligned by runtime. We use the
8226 smallest incoming stack boundary. */
8227 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8228 && DECL_NAME (current_function_decl)
8229 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8230 && DECL_FILE_SCOPE_P (current_function_decl))
8231 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8233 /* x86_64 vararg needs 16byte stack alignment for register save
8237 && crtl->stack_alignment_estimated < 128)
8238 crtl->stack_alignment_estimated = 128;
8241 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8242 needed or an rtx for DRAP otherwise. */
8245 ix86_get_drap_rtx (void)
8247 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8248 crtl->need_drap = true;
8250 if (stack_realign_drap)
8252 /* Assign DRAP to vDRAP and returns vDRAP */
8253 unsigned int regno = find_drap_reg ();
8258 arg_ptr = gen_rtx_REG (Pmode, regno);
8259 crtl->drap_reg = arg_ptr;
8262 drap_vreg = copy_to_reg (arg_ptr);
8266 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8267 RTX_FRAME_RELATED_P (insn) = 1;
8274 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8277 ix86_internal_arg_pointer (void)
8279 return virtual_incoming_args_rtx;
8282 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8283 to be generated in correct form. */
8285 ix86_finalize_stack_realign_flags (void)
8287 /* Check if stack realign is really needed after reload, and
8288 stores result in cfun */
8289 unsigned int incoming_stack_boundary
8290 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8291 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8292 unsigned int stack_realign = (incoming_stack_boundary
8293 < (current_function_is_leaf
8294 ? crtl->max_used_stack_slot_alignment
8295 : crtl->stack_alignment_needed));
8297 if (crtl->stack_realign_finalized)
8299 /* After stack_realign_needed is finalized, we can't no longer
8301 gcc_assert (crtl->stack_realign_needed == stack_realign);
8305 crtl->stack_realign_needed = stack_realign;
8306 crtl->stack_realign_finalized = true;
8310 /* Expand the prologue into a bunch of separate insns. */
8313 ix86_expand_prologue (void)
8317 struct ix86_frame frame;
8318 HOST_WIDE_INT allocate;
8320 ix86_finalize_stack_realign_flags ();
8322 /* DRAP should not coexist with stack_realign_fp */
8323 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8325 /* Initialize CFA state for before the prologue. */
8326 ix86_cfa_state->reg = stack_pointer_rtx;
8327 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8329 ix86_compute_frame_layout (&frame);
8331 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8332 of DRAP is needed and stack realignment is really needed after reload */
8333 if (crtl->drap_reg && crtl->stack_realign_needed)
8336 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8337 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8338 ? 0 : UNITS_PER_WORD);
8340 gcc_assert (stack_realign_drap);
8342 /* Grab the argument pointer. */
8343 x = plus_constant (stack_pointer_rtx,
8344 (UNITS_PER_WORD + param_ptr_offset));
8347 /* Only need to push parameter pointer reg if it is caller
8349 if (!call_used_regs[REGNO (crtl->drap_reg)])
8351 /* Push arg pointer reg */
8352 insn = emit_insn (gen_push (y));
8353 RTX_FRAME_RELATED_P (insn) = 1;
8356 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8357 RTX_FRAME_RELATED_P (insn) = 1;
8358 ix86_cfa_state->reg = crtl->drap_reg;
8360 /* Align the stack. */
8361 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8363 GEN_INT (-align_bytes)));
8364 RTX_FRAME_RELATED_P (insn) = 1;
8366 /* Replicate the return address on the stack so that return
8367 address can be reached via (argp - 1) slot. This is needed
8368 to implement macro RETURN_ADDR_RTX and intrinsic function
8369 expand_builtin_return_addr etc. */
8371 x = gen_frame_mem (Pmode,
8372 plus_constant (x, -UNITS_PER_WORD));
8373 insn = emit_insn (gen_push (x));
8374 RTX_FRAME_RELATED_P (insn) = 1;
8377 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8378 slower on all targets. Also sdb doesn't like it. */
8380 if (frame_pointer_needed)
8382 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8383 RTX_FRAME_RELATED_P (insn) = 1;
8385 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8386 RTX_FRAME_RELATED_P (insn) = 1;
8388 if (ix86_cfa_state->reg == stack_pointer_rtx)
8389 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8392 if (stack_realign_fp)
8394 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8395 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8397 /* Align the stack. */
8398 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8400 GEN_INT (-align_bytes)));
8401 RTX_FRAME_RELATED_P (insn) = 1;
8404 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8406 if (!frame.save_regs_using_mov)
8407 ix86_emit_save_regs ();
8409 allocate += frame.nregs * UNITS_PER_WORD;
8411 /* When using red zone we may start register saving before allocating
8412 the stack frame saving one cycle of the prologue. However I will
8413 avoid doing this if I am going to have to probe the stack since
8414 at least on x86_64 the stack probe can turn into a call that clobbers
8415 a red zone location */
8416 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8417 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8418 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8419 && !crtl->stack_realign_needed)
8420 ? hard_frame_pointer_rtx
8421 : stack_pointer_rtx,
8422 -frame.nregs * UNITS_PER_WORD);
8426 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8427 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8428 GEN_INT (-allocate), -1,
8429 ix86_cfa_state->reg == stack_pointer_rtx);
8432 /* Only valid for Win32. */
8433 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8437 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8439 if (cfun->machine->call_abi == MS_ABI)
8442 eax_live = ix86_eax_live_at_start_p ();
8446 emit_insn (gen_push (eax));
8447 allocate -= UNITS_PER_WORD;
8450 emit_move_insn (eax, GEN_INT (allocate));
8453 insn = gen_allocate_stack_worker_64 (eax, eax);
8455 insn = gen_allocate_stack_worker_32 (eax, eax);
8456 insn = emit_insn (insn);
8458 if (ix86_cfa_state->reg == stack_pointer_rtx)
8460 ix86_cfa_state->offset += allocate;
8461 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8462 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8463 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8464 RTX_FRAME_RELATED_P (insn) = 1;
8469 if (frame_pointer_needed)
8470 t = plus_constant (hard_frame_pointer_rtx,
8473 - frame.nregs * UNITS_PER_WORD);
8475 t = plus_constant (stack_pointer_rtx, allocate);
8476 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8480 if (frame.save_regs_using_mov
8481 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8482 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8484 if (!frame_pointer_needed
8485 || !frame.to_allocate
8486 || crtl->stack_realign_needed)
8487 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8489 + frame.nsseregs * 16 + frame.padding0);
8491 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8492 -frame.nregs * UNITS_PER_WORD);
8494 if (!frame_pointer_needed
8495 || !frame.to_allocate
8496 || crtl->stack_realign_needed)
8497 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8500 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8501 - frame.nregs * UNITS_PER_WORD
8502 - frame.nsseregs * 16
8505 pic_reg_used = false;
8506 if (pic_offset_table_rtx
8507 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8510 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8512 if (alt_pic_reg_used != INVALID_REGNUM)
8513 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8515 pic_reg_used = true;
8522 if (ix86_cmodel == CM_LARGE_PIC)
8524 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8525 rtx label = gen_label_rtx ();
8527 LABEL_PRESERVE_P (label) = 1;
8528 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8529 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8530 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8531 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8532 pic_offset_table_rtx, tmp_reg));
8535 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8538 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8541 /* In the pic_reg_used case, make sure that the got load isn't deleted
8542 when mcount needs it. Blockage to avoid call movement across mcount
8543 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8545 if (crtl->profile && pic_reg_used)
8546 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8548 if (crtl->drap_reg && !crtl->stack_realign_needed)
8550 /* vDRAP is setup but after reload it turns out stack realign
8551 isn't necessary, here we will emit prologue to setup DRAP
8552 without stack realign adjustment */
8553 int drap_bp_offset = UNITS_PER_WORD * 2;
8554 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8555 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8558 /* Prevent instructions from being scheduled into register save push
8559 sequence when access to the redzone area is done through frame pointer.
8560 The offset betweeh the frame pointer and the stack pointer is calculated
8561 relative to the value of the stack pointer at the end of the function
8562 prologue, and moving instructions that access redzone area via frame
8563 pointer inside push sequence violates this assumption. */
8564 if (frame_pointer_needed && frame.red_zone_size)
8565 emit_insn (gen_memory_blockage ());
8567 /* Emit cld instruction if stringops are used in the function. */
8568 if (TARGET_CLD && ix86_current_function_needs_cld)
8569 emit_insn (gen_cld ());
8572 /* Emit code to restore REG using a POP insn. */
8575 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8577 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8579 if (ix86_cfa_state->reg == crtl->drap_reg
8580 && REGNO (reg) == REGNO (crtl->drap_reg))
8582 /* Previously we'd represented the CFA as an expression
8583 like *(%ebp - 8). We've just popped that value from
8584 the stack, which means we need to reset the CFA to
8585 the drap register. This will remain until we restore
8586 the stack pointer. */
8587 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8588 RTX_FRAME_RELATED_P (insn) = 1;
8592 if (ix86_cfa_state->reg == stack_pointer_rtx)
8594 ix86_cfa_state->offset -= UNITS_PER_WORD;
8595 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8596 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8597 RTX_FRAME_RELATED_P (insn) = 1;
8600 /* When the frame pointer is the CFA, and we pop it, we are
8601 swapping back to the stack pointer as the CFA. This happens
8602 for stack frames that don't allocate other data, so we assume
8603 the stack pointer is now pointing at the return address, i.e.
8604 the function entry state, which makes the offset be 1 word. */
8605 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8606 && reg == hard_frame_pointer_rtx)
8608 ix86_cfa_state->reg = stack_pointer_rtx;
8609 ix86_cfa_state->offset = UNITS_PER_WORD;
8611 add_reg_note (insn, REG_CFA_DEF_CFA,
8612 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8613 GEN_INT (UNITS_PER_WORD)));
8614 RTX_FRAME_RELATED_P (insn) = 1;
8617 ix86_add_cfa_restore_note (insn, reg, red_offset);
8620 /* Emit code to restore saved registers using POP insns. */
8623 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8627 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8628 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8630 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8632 red_offset += UNITS_PER_WORD;
8636 /* Emit code and notes for the LEAVE instruction. */
8639 ix86_emit_leave (HOST_WIDE_INT red_offset)
8641 rtx insn = emit_insn (ix86_gen_leave ());
8643 ix86_add_queued_cfa_restore_notes (insn);
8645 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8647 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8648 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8649 RTX_FRAME_RELATED_P (insn) = 1;
8650 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8654 /* Emit code to restore saved registers using MOV insns. First register
8655 is restored from POINTER + OFFSET. */
8657 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8658 HOST_WIDE_INT red_offset,
8659 int maybe_eh_return)
8662 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8665 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8666 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8668 rtx reg = gen_rtx_REG (Pmode, regno);
8670 /* Ensure that adjust_address won't be forced to produce pointer
8671 out of range allowed by x86-64 instruction set. */
8672 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8676 r11 = gen_rtx_REG (DImode, R11_REG);
8677 emit_move_insn (r11, GEN_INT (offset));
8678 emit_insn (gen_adddi3 (r11, r11, pointer));
8679 base_address = gen_rtx_MEM (Pmode, r11);
8682 insn = emit_move_insn (reg,
8683 adjust_address (base_address, Pmode, offset));
8684 offset += UNITS_PER_WORD;
8686 if (ix86_cfa_state->reg == crtl->drap_reg
8687 && regno == REGNO (crtl->drap_reg))
8689 /* Previously we'd represented the CFA as an expression
8690 like *(%ebp - 8). We've just popped that value from
8691 the stack, which means we need to reset the CFA to
8692 the drap register. This will remain until we restore
8693 the stack pointer. */
8694 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8695 RTX_FRAME_RELATED_P (insn) = 1;
8698 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8700 red_offset += UNITS_PER_WORD;
8704 /* Emit code to restore saved registers using MOV insns. First register
8705 is restored from POINTER + OFFSET. */
8707 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8708 HOST_WIDE_INT red_offset,
8709 int maybe_eh_return)
8712 rtx base_address = gen_rtx_MEM (TImode, pointer);
8715 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8716 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8718 rtx reg = gen_rtx_REG (TImode, regno);
8720 /* Ensure that adjust_address won't be forced to produce pointer
8721 out of range allowed by x86-64 instruction set. */
8722 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8726 r11 = gen_rtx_REG (DImode, R11_REG);
8727 emit_move_insn (r11, GEN_INT (offset));
8728 emit_insn (gen_adddi3 (r11, r11, pointer));
8729 base_address = gen_rtx_MEM (TImode, r11);
8732 mem = adjust_address (base_address, TImode, offset);
8733 set_mem_align (mem, 128);
8734 insn = emit_move_insn (reg, mem);
8737 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8743 /* Restore function stack, frame, and registers. */
8746 ix86_expand_epilogue (int style)
8749 struct ix86_frame frame;
8750 HOST_WIDE_INT offset, red_offset;
8751 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8754 ix86_finalize_stack_realign_flags ();
8756 /* When stack is realigned, SP must be valid. */
8757 sp_valid = (!frame_pointer_needed
8758 || current_function_sp_is_unchanging
8759 || stack_realign_fp);
8761 ix86_compute_frame_layout (&frame);
8763 /* See the comment about red zone and frame
8764 pointer usage in ix86_expand_prologue. */
8765 if (frame_pointer_needed && frame.red_zone_size)
8766 emit_insn (gen_memory_blockage ());
8768 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8769 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8771 /* Calculate start of saved registers relative to ebp. Special care
8772 must be taken for the normal return case of a function using
8773 eh_return: the eax and edx registers are marked as saved, but not
8774 restored along this path. */
8775 offset = frame.nregs;
8776 if (crtl->calls_eh_return && style != 2)
8778 offset *= -UNITS_PER_WORD;
8779 offset -= frame.nsseregs * 16 + frame.padding0;
8781 /* Calculate start of saved registers relative to esp on entry of the
8782 function. When realigning stack, this needs to be the most negative
8783 value possible at runtime. */
8784 red_offset = offset;
8786 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8788 else if (stack_realign_fp)
8789 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8791 if (frame_pointer_needed)
8792 red_offset -= UNITS_PER_WORD;
8794 /* If we're only restoring one register and sp is not valid then
8795 using a move instruction to restore the register since it's
8796 less work than reloading sp and popping the register.
8798 The default code result in stack adjustment using add/lea instruction,
8799 while this code results in LEAVE instruction (or discrete equivalent),
8800 so it is profitable in some other cases as well. Especially when there
8801 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8802 and there is exactly one register to pop. This heuristic may need some
8803 tuning in future. */
8804 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8805 || (TARGET_EPILOGUE_USING_MOVE
8806 && cfun->machine->use_fast_prologue_epilogue
8807 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8808 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8809 && frame.to_allocate)
8810 || (frame_pointer_needed && TARGET_USE_LEAVE
8811 && cfun->machine->use_fast_prologue_epilogue
8812 && (frame.nregs + frame.nsseregs) == 1)
8813 || crtl->calls_eh_return)
8815 /* Restore registers. We can use ebp or esp to address the memory
8816 locations. If both are available, default to ebp, since offsets
8817 are known to be small. Only exception is esp pointing directly
8818 to the end of block of saved registers, where we may simplify
8821 If we are realigning stack with bp and sp, regs restore can't
8822 be addressed by bp. sp must be used instead. */
8824 if (!frame_pointer_needed
8825 || (sp_valid && !frame.to_allocate)
8826 || stack_realign_fp)
8828 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8829 frame.to_allocate, red_offset,
8831 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8833 + frame.nsseregs * 16
8836 + frame.nsseregs * 16
8837 + frame.padding0, style == 2);
8841 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8844 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8846 + frame.nsseregs * 16
8849 + frame.nsseregs * 16
8850 + frame.padding0, style == 2);
8853 red_offset -= offset;
8855 /* eh_return epilogues need %ecx added to the stack pointer. */
8858 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8860 /* Stack align doesn't work with eh_return. */
8861 gcc_assert (!crtl->stack_realign_needed);
8863 if (frame_pointer_needed)
8865 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8866 tmp = plus_constant (tmp, UNITS_PER_WORD);
8867 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8869 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8870 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8872 /* Note that we use SA as a temporary CFA, as the return
8873 address is at the proper place relative to it. We
8874 pretend this happens at the FP restore insn because
8875 prior to this insn the FP would be stored at the wrong
8876 offset relative to SA, and after this insn we have no
8877 other reasonable register to use for the CFA. We don't
8878 bother resetting the CFA to the SP for the duration of
8880 add_reg_note (tmp, REG_CFA_DEF_CFA,
8881 plus_constant (sa, UNITS_PER_WORD));
8882 ix86_add_queued_cfa_restore_notes (tmp);
8883 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8884 RTX_FRAME_RELATED_P (tmp) = 1;
8885 ix86_cfa_state->reg = sa;
8886 ix86_cfa_state->offset = UNITS_PER_WORD;
8888 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8889 const0_rtx, style, false);
8893 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8894 tmp = plus_constant (tmp, (frame.to_allocate
8895 + frame.nregs * UNITS_PER_WORD
8896 + frame.nsseregs * 16
8898 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8899 ix86_add_queued_cfa_restore_notes (tmp);
8901 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8902 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8904 ix86_cfa_state->offset = UNITS_PER_WORD;
8905 add_reg_note (tmp, REG_CFA_DEF_CFA,
8906 plus_constant (stack_pointer_rtx,
8908 RTX_FRAME_RELATED_P (tmp) = 1;
8912 else if (!frame_pointer_needed)
8913 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8914 GEN_INT (frame.to_allocate
8915 + frame.nregs * UNITS_PER_WORD
8916 + frame.nsseregs * 16
8918 style, !using_drap);
8919 /* If not an i386, mov & pop is faster than "leave". */
8920 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8921 || !cfun->machine->use_fast_prologue_epilogue)
8922 ix86_emit_leave (red_offset);
8925 pro_epilogue_adjust_stack (stack_pointer_rtx,
8926 hard_frame_pointer_rtx,
8927 const0_rtx, style, !using_drap);
8929 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
8934 /* First step is to deallocate the stack frame so that we can
8937 If we realign stack with frame pointer, then stack pointer
8938 won't be able to recover via lea $offset(%bp), %sp, because
8939 there is a padding area between bp and sp for realign.
8940 "add $to_allocate, %sp" must be used instead. */
8943 gcc_assert (frame_pointer_needed);
8944 gcc_assert (!stack_realign_fp);
8945 pro_epilogue_adjust_stack (stack_pointer_rtx,
8946 hard_frame_pointer_rtx,
8947 GEN_INT (offset), style, false);
8948 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8949 frame.to_allocate, red_offset,
8951 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8952 GEN_INT (frame.nsseregs * 16),
8955 else if (frame.to_allocate || frame.nsseregs)
8957 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8958 frame.to_allocate, red_offset,
8960 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8961 GEN_INT (frame.to_allocate
8962 + frame.nsseregs * 16
8963 + frame.padding0), style,
8964 !using_drap && !frame_pointer_needed);
8967 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
8969 red_offset -= offset;
8971 if (frame_pointer_needed)
8973 /* Leave results in shorter dependency chains on CPUs that are
8974 able to grok it fast. */
8975 if (TARGET_USE_LEAVE)
8976 ix86_emit_leave (red_offset);
8979 /* For stack realigned really happens, recover stack
8980 pointer to hard frame pointer is a must, if not using
8982 if (stack_realign_fp)
8983 pro_epilogue_adjust_stack (stack_pointer_rtx,
8984 hard_frame_pointer_rtx,
8985 const0_rtx, style, !using_drap);
8986 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
8994 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8995 ? 0 : UNITS_PER_WORD);
8998 gcc_assert (stack_realign_drap);
9000 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9002 GEN_INT (-(UNITS_PER_WORD
9003 + param_ptr_offset))));
9005 ix86_cfa_state->reg = stack_pointer_rtx;
9006 ix86_cfa_state->offset = UNITS_PER_WORD + param_ptr_offset;
9008 add_reg_note (insn, REG_CFA_DEF_CFA,
9009 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9010 GEN_INT (ix86_cfa_state->offset)));
9011 RTX_FRAME_RELATED_P (insn) = 1;
9013 if (param_ptr_offset)
9014 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9017 /* Sibcall epilogues don't want a return instruction. */
9020 *ix86_cfa_state = cfa_state_save;
9024 if (crtl->args.pops_args && crtl->args.size)
9026 rtx popc = GEN_INT (crtl->args.pops_args);
9028 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9029 address, do explicit add, and jump indirectly to the caller. */
9031 if (crtl->args.pops_args >= 65536)
9033 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9036 /* There is no "pascal" calling convention in any 64bit ABI. */
9037 gcc_assert (!TARGET_64BIT);
9039 insn = emit_insn (gen_popsi1 (ecx));
9040 ix86_cfa_state->offset -= UNITS_PER_WORD;
9042 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9043 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9044 add_reg_note (insn, REG_CFA_REGISTER,
9045 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9046 RTX_FRAME_RELATED_P (insn) = 1;
9048 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9050 emit_jump_insn (gen_return_indirect_internal (ecx));
9053 emit_jump_insn (gen_return_pop_internal (popc));
9056 emit_jump_insn (gen_return_internal ());
9058 /* Restore the state back to the state from the prologue,
9059 so that it's correct for the next epilogue. */
9060 *ix86_cfa_state = cfa_state_save;
9063 /* Reset from the function's potential modifications. */
9066 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9067 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9069 if (pic_offset_table_rtx)
9070 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9072 /* Mach-O doesn't support labels at the end of objects, so if
9073 it looks like we might want one, insert a NOP. */
9075 rtx insn = get_last_insn ();
9078 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9079 insn = PREV_INSN (insn);
9083 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9084 fputs ("\tnop\n", file);
9090 /* Extract the parts of an RTL expression that is a valid memory address
9091 for an instruction. Return 0 if the structure of the address is
9092 grossly off. Return -1 if the address contains ASHIFT, so it is not
9093 strictly valid, but still used for computing length of lea instruction. */
9096 ix86_decompose_address (rtx addr, struct ix86_address *out)
9098 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9099 rtx base_reg, index_reg;
9100 HOST_WIDE_INT scale = 1;
9101 rtx scale_rtx = NULL_RTX;
9103 enum ix86_address_seg seg = SEG_DEFAULT;
9105 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9107 else if (GET_CODE (addr) == PLUS)
9117 addends[n++] = XEXP (op, 1);
9120 while (GET_CODE (op) == PLUS);
9125 for (i = n; i >= 0; --i)
9128 switch (GET_CODE (op))
9133 index = XEXP (op, 0);
9134 scale_rtx = XEXP (op, 1);
9138 if (XINT (op, 1) == UNSPEC_TP
9139 && TARGET_TLS_DIRECT_SEG_REFS
9140 && seg == SEG_DEFAULT)
9141 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9170 else if (GET_CODE (addr) == MULT)
9172 index = XEXP (addr, 0); /* index*scale */
9173 scale_rtx = XEXP (addr, 1);
9175 else if (GET_CODE (addr) == ASHIFT)
9179 /* We're called for lea too, which implements ashift on occasion. */
9180 index = XEXP (addr, 0);
9181 tmp = XEXP (addr, 1);
9182 if (!CONST_INT_P (tmp))
9184 scale = INTVAL (tmp);
9185 if ((unsigned HOST_WIDE_INT) scale > 3)
9191 disp = addr; /* displacement */
9193 /* Extract the integral value of scale. */
9196 if (!CONST_INT_P (scale_rtx))
9198 scale = INTVAL (scale_rtx);
9201 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9202 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9204 /* Avoid useless 0 displacement. */
9205 if (disp == const0_rtx && (base || index))
9208 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9209 if (base_reg && index_reg && scale == 1
9210 && (index_reg == arg_pointer_rtx
9211 || index_reg == frame_pointer_rtx
9212 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9215 tmp = base, base = index, index = tmp;
9216 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9219 /* Special case: %ebp cannot be encoded as a base without a displacement.
9223 && (base_reg == hard_frame_pointer_rtx
9224 || base_reg == frame_pointer_rtx
9225 || base_reg == arg_pointer_rtx
9226 || (REG_P (base_reg)
9227 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9228 || REGNO (base_reg) == R13_REG))))
9231 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9232 Avoid this by transforming to [%esi+0].
9233 Reload calls address legitimization without cfun defined, so we need
9234 to test cfun for being non-NULL. */
9235 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9236 && base_reg && !index_reg && !disp
9238 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9241 /* Special case: encode reg+reg instead of reg*2. */
9242 if (!base && index && scale == 2)
9243 base = index, base_reg = index_reg, scale = 1;
9245 /* Special case: scaling cannot be encoded without base or displacement. */
9246 if (!base && !disp && index && scale != 1)
9258 /* Return cost of the memory address x.
9259 For i386, it is better to use a complex address than let gcc copy
9260 the address into a reg and make a new pseudo. But not if the address
9261 requires to two regs - that would mean more pseudos with longer
9264 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9266 struct ix86_address parts;
9268 int ok = ix86_decompose_address (x, &parts);
9272 if (parts.base && GET_CODE (parts.base) == SUBREG)
9273 parts.base = SUBREG_REG (parts.base);
9274 if (parts.index && GET_CODE (parts.index) == SUBREG)
9275 parts.index = SUBREG_REG (parts.index);
9277 /* Attempt to minimize number of registers in the address. */
9279 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9281 && (!REG_P (parts.index)
9282 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9286 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9288 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9289 && parts.base != parts.index)
9292 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9293 since it's predecode logic can't detect the length of instructions
9294 and it degenerates to vector decoded. Increase cost of such
9295 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9296 to split such addresses or even refuse such addresses at all.
9298 Following addressing modes are affected:
9303 The first and last case may be avoidable by explicitly coding the zero in
9304 memory address, but I don't have AMD-K6 machine handy to check this
9308 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9309 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9310 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9316 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9317 this is used for to form addresses to local data when -fPIC is in
9321 darwin_local_data_pic (rtx disp)
9323 return (GET_CODE (disp) == UNSPEC
9324 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9327 /* Determine if a given RTX is a valid constant. We already know this
9328 satisfies CONSTANT_P. */
9331 legitimate_constant_p (rtx x)
9333 switch (GET_CODE (x))
9338 if (GET_CODE (x) == PLUS)
9340 if (!CONST_INT_P (XEXP (x, 1)))
9345 if (TARGET_MACHO && darwin_local_data_pic (x))
9348 /* Only some unspecs are valid as "constants". */
9349 if (GET_CODE (x) == UNSPEC)
9350 switch (XINT (x, 1))
9355 return TARGET_64BIT;
9358 x = XVECEXP (x, 0, 0);
9359 return (GET_CODE (x) == SYMBOL_REF
9360 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9362 x = XVECEXP (x, 0, 0);
9363 return (GET_CODE (x) == SYMBOL_REF
9364 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9369 /* We must have drilled down to a symbol. */
9370 if (GET_CODE (x) == LABEL_REF)
9372 if (GET_CODE (x) != SYMBOL_REF)
9377 /* TLS symbols are never valid. */
9378 if (SYMBOL_REF_TLS_MODEL (x))
9381 /* DLLIMPORT symbols are never valid. */
9382 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9383 && SYMBOL_REF_DLLIMPORT_P (x))
9388 if (GET_MODE (x) == TImode
9389 && x != CONST0_RTX (TImode)
9395 if (!standard_sse_constant_p (x))
9402 /* Otherwise we handle everything else in the move patterns. */
9406 /* Determine if it's legal to put X into the constant pool. This
9407 is not possible for the address of thread-local symbols, which
9408 is checked above. */
9411 ix86_cannot_force_const_mem (rtx x)
9413 /* We can always put integral constants and vectors in memory. */
9414 switch (GET_CODE (x))
9424 return !legitimate_constant_p (x);
9428 /* Nonzero if the constant value X is a legitimate general operand
9429 when generating PIC code. It is given that flag_pic is on and
9430 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9433 legitimate_pic_operand_p (rtx x)
9437 switch (GET_CODE (x))
9440 inner = XEXP (x, 0);
9441 if (GET_CODE (inner) == PLUS
9442 && CONST_INT_P (XEXP (inner, 1)))
9443 inner = XEXP (inner, 0);
9445 /* Only some unspecs are valid as "constants". */
9446 if (GET_CODE (inner) == UNSPEC)
9447 switch (XINT (inner, 1))
9452 return TARGET_64BIT;
9454 x = XVECEXP (inner, 0, 0);
9455 return (GET_CODE (x) == SYMBOL_REF
9456 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9457 case UNSPEC_MACHOPIC_OFFSET:
9458 return legitimate_pic_address_disp_p (x);
9466 return legitimate_pic_address_disp_p (x);
9473 /* Determine if a given CONST RTX is a valid memory displacement
9477 legitimate_pic_address_disp_p (rtx disp)
9481 /* In 64bit mode we can allow direct addresses of symbols and labels
9482 when they are not dynamic symbols. */
9485 rtx op0 = disp, op1;
9487 switch (GET_CODE (disp))
9493 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9495 op0 = XEXP (XEXP (disp, 0), 0);
9496 op1 = XEXP (XEXP (disp, 0), 1);
9497 if (!CONST_INT_P (op1)
9498 || INTVAL (op1) >= 16*1024*1024
9499 || INTVAL (op1) < -16*1024*1024)
9501 if (GET_CODE (op0) == LABEL_REF)
9503 if (GET_CODE (op0) != SYMBOL_REF)
9508 /* TLS references should always be enclosed in UNSPEC. */
9509 if (SYMBOL_REF_TLS_MODEL (op0))
9511 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9512 && ix86_cmodel != CM_LARGE_PIC)
9520 if (GET_CODE (disp) != CONST)
9522 disp = XEXP (disp, 0);
9526 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9527 of GOT tables. We should not need these anyway. */
9528 if (GET_CODE (disp) != UNSPEC
9529 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9530 && XINT (disp, 1) != UNSPEC_GOTOFF
9531 && XINT (disp, 1) != UNSPEC_PLTOFF))
9534 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9535 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9541 if (GET_CODE (disp) == PLUS)
9543 if (!CONST_INT_P (XEXP (disp, 1)))
9545 disp = XEXP (disp, 0);
9549 if (TARGET_MACHO && darwin_local_data_pic (disp))
9552 if (GET_CODE (disp) != UNSPEC)
9555 switch (XINT (disp, 1))
9560 /* We need to check for both symbols and labels because VxWorks loads
9561 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9563 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9564 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9566 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9567 While ABI specify also 32bit relocation but we don't produce it in
9568 small PIC model at all. */
9569 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9570 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9572 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9574 case UNSPEC_GOTTPOFF:
9575 case UNSPEC_GOTNTPOFF:
9576 case UNSPEC_INDNTPOFF:
9579 disp = XVECEXP (disp, 0, 0);
9580 return (GET_CODE (disp) == SYMBOL_REF
9581 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9583 disp = XVECEXP (disp, 0, 0);
9584 return (GET_CODE (disp) == SYMBOL_REF
9585 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9587 disp = XVECEXP (disp, 0, 0);
9588 return (GET_CODE (disp) == SYMBOL_REF
9589 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9595 /* Recognizes RTL expressions that are valid memory addresses for an
9596 instruction. The MODE argument is the machine mode for the MEM
9597 expression that wants to use this address.
9599 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9600 convert common non-canonical forms to canonical form so that they will
9604 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9605 rtx addr, bool strict)
9607 struct ix86_address parts;
9608 rtx base, index, disp;
9609 HOST_WIDE_INT scale;
9610 const char *reason = NULL;
9611 rtx reason_rtx = NULL_RTX;
9613 if (ix86_decompose_address (addr, &parts) <= 0)
9615 reason = "decomposition failed";
9620 index = parts.index;
9622 scale = parts.scale;
9624 /* Validate base register.
9626 Don't allow SUBREG's that span more than a word here. It can lead to spill
9627 failures when the base is one word out of a two word structure, which is
9628 represented internally as a DImode int. */
9637 else if (GET_CODE (base) == SUBREG
9638 && REG_P (SUBREG_REG (base))
9639 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9641 reg = SUBREG_REG (base);
9644 reason = "base is not a register";
9648 if (GET_MODE (base) != Pmode)
9650 reason = "base is not in Pmode";
9654 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9655 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9657 reason = "base is not valid";
9662 /* Validate index register.
9664 Don't allow SUBREG's that span more than a word here -- same as above. */
9673 else if (GET_CODE (index) == SUBREG
9674 && REG_P (SUBREG_REG (index))
9675 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9677 reg = SUBREG_REG (index);
9680 reason = "index is not a register";
9684 if (GET_MODE (index) != Pmode)
9686 reason = "index is not in Pmode";
9690 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9691 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9693 reason = "index is not valid";
9698 /* Validate scale factor. */
9701 reason_rtx = GEN_INT (scale);
9704 reason = "scale without index";
9708 if (scale != 2 && scale != 4 && scale != 8)
9710 reason = "scale is not a valid multiplier";
9715 /* Validate displacement. */
9720 if (GET_CODE (disp) == CONST
9721 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9722 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9723 switch (XINT (XEXP (disp, 0), 1))
9725 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9726 used. While ABI specify also 32bit relocations, we don't produce
9727 them at all and use IP relative instead. */
9730 gcc_assert (flag_pic);
9732 goto is_legitimate_pic;
9733 reason = "64bit address unspec";
9736 case UNSPEC_GOTPCREL:
9737 gcc_assert (flag_pic);
9738 goto is_legitimate_pic;
9740 case UNSPEC_GOTTPOFF:
9741 case UNSPEC_GOTNTPOFF:
9742 case UNSPEC_INDNTPOFF:
9748 reason = "invalid address unspec";
9752 else if (SYMBOLIC_CONST (disp)
9756 && MACHOPIC_INDIRECT
9757 && !machopic_operand_p (disp)
9763 if (TARGET_64BIT && (index || base))
9765 /* foo@dtpoff(%rX) is ok. */
9766 if (GET_CODE (disp) != CONST
9767 || GET_CODE (XEXP (disp, 0)) != PLUS
9768 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9769 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9770 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9771 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9773 reason = "non-constant pic memory reference";
9777 else if (! legitimate_pic_address_disp_p (disp))
9779 reason = "displacement is an invalid pic construct";
9783 /* This code used to verify that a symbolic pic displacement
9784 includes the pic_offset_table_rtx register.
9786 While this is good idea, unfortunately these constructs may
9787 be created by "adds using lea" optimization for incorrect
9796 This code is nonsensical, but results in addressing
9797 GOT table with pic_offset_table_rtx base. We can't
9798 just refuse it easily, since it gets matched by
9799 "addsi3" pattern, that later gets split to lea in the
9800 case output register differs from input. While this
9801 can be handled by separate addsi pattern for this case
9802 that never results in lea, this seems to be easier and
9803 correct fix for crash to disable this test. */
9805 else if (GET_CODE (disp) != LABEL_REF
9806 && !CONST_INT_P (disp)
9807 && (GET_CODE (disp) != CONST
9808 || !legitimate_constant_p (disp))
9809 && (GET_CODE (disp) != SYMBOL_REF
9810 || !legitimate_constant_p (disp)))
9812 reason = "displacement is not constant";
9815 else if (TARGET_64BIT
9816 && !x86_64_immediate_operand (disp, VOIDmode))
9818 reason = "displacement is out of range";
9823 /* Everything looks valid. */
9830 /* Determine if a given RTX is a valid constant address. */
9833 constant_address_p (rtx x)
9835 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9838 /* Return a unique alias set for the GOT. */
9840 static alias_set_type
9841 ix86_GOT_alias_set (void)
9843 static alias_set_type set = -1;
9845 set = new_alias_set ();
9849 /* Return a legitimate reference for ORIG (an address) using the
9850 register REG. If REG is 0, a new pseudo is generated.
9852 There are two types of references that must be handled:
9854 1. Global data references must load the address from the GOT, via
9855 the PIC reg. An insn is emitted to do this load, and the reg is
9858 2. Static data references, constant pool addresses, and code labels
9859 compute the address as an offset from the GOT, whose base is in
9860 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9861 differentiate them from global data objects. The returned
9862 address is the PIC reg + an unspec constant.
9864 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9865 reg also appears in the address. */
9868 legitimize_pic_address (rtx orig, rtx reg)
9875 if (TARGET_MACHO && !TARGET_64BIT)
9878 reg = gen_reg_rtx (Pmode);
9879 /* Use the generic Mach-O PIC machinery. */
9880 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9884 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9886 else if (TARGET_64BIT
9887 && ix86_cmodel != CM_SMALL_PIC
9888 && gotoff_operand (addr, Pmode))
9891 /* This symbol may be referenced via a displacement from the PIC
9892 base address (@GOTOFF). */
9894 if (reload_in_progress)
9895 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9896 if (GET_CODE (addr) == CONST)
9897 addr = XEXP (addr, 0);
9898 if (GET_CODE (addr) == PLUS)
9900 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9902 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9905 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9906 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9908 tmpreg = gen_reg_rtx (Pmode);
9911 emit_move_insn (tmpreg, new_rtx);
9915 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9916 tmpreg, 1, OPTAB_DIRECT);
9919 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9921 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9923 /* This symbol may be referenced via a displacement from the PIC
9924 base address (@GOTOFF). */
9926 if (reload_in_progress)
9927 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9928 if (GET_CODE (addr) == CONST)
9929 addr = XEXP (addr, 0);
9930 if (GET_CODE (addr) == PLUS)
9932 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9934 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9937 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9938 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9939 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9943 emit_move_insn (reg, new_rtx);
9947 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9948 /* We can't use @GOTOFF for text labels on VxWorks;
9949 see gotoff_operand. */
9950 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9952 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9954 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9955 return legitimize_dllimport_symbol (addr, true);
9956 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9957 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9958 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9960 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9961 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9965 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9967 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9968 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9969 new_rtx = gen_const_mem (Pmode, new_rtx);
9970 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9973 reg = gen_reg_rtx (Pmode);
9974 /* Use directly gen_movsi, otherwise the address is loaded
9975 into register for CSE. We don't want to CSE this addresses,
9976 instead we CSE addresses from the GOT table, so skip this. */
9977 emit_insn (gen_movsi (reg, new_rtx));
9982 /* This symbol must be referenced via a load from the
9983 Global Offset Table (@GOT). */
9985 if (reload_in_progress)
9986 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9987 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9988 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9990 new_rtx = force_reg (Pmode, new_rtx);
9991 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9992 new_rtx = gen_const_mem (Pmode, new_rtx);
9993 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9996 reg = gen_reg_rtx (Pmode);
9997 emit_move_insn (reg, new_rtx);
10003 if (CONST_INT_P (addr)
10004 && !x86_64_immediate_operand (addr, VOIDmode))
10008 emit_move_insn (reg, addr);
10012 new_rtx = force_reg (Pmode, addr);
10014 else if (GET_CODE (addr) == CONST)
10016 addr = XEXP (addr, 0);
10018 /* We must match stuff we generate before. Assume the only
10019 unspecs that can get here are ours. Not that we could do
10020 anything with them anyway.... */
10021 if (GET_CODE (addr) == UNSPEC
10022 || (GET_CODE (addr) == PLUS
10023 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10025 gcc_assert (GET_CODE (addr) == PLUS);
10027 if (GET_CODE (addr) == PLUS)
10029 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10031 /* Check first to see if this is a constant offset from a @GOTOFF
10032 symbol reference. */
10033 if (gotoff_operand (op0, Pmode)
10034 && CONST_INT_P (op1))
10038 if (reload_in_progress)
10039 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10040 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10042 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10043 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10044 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10048 emit_move_insn (reg, new_rtx);
10054 if (INTVAL (op1) < -16*1024*1024
10055 || INTVAL (op1) >= 16*1024*1024)
10057 if (!x86_64_immediate_operand (op1, Pmode))
10058 op1 = force_reg (Pmode, op1);
10059 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10065 base = legitimize_pic_address (XEXP (addr, 0), reg);
10066 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10067 base == reg ? NULL_RTX : reg);
10069 if (CONST_INT_P (new_rtx))
10070 new_rtx = plus_constant (base, INTVAL (new_rtx));
10073 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10075 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10076 new_rtx = XEXP (new_rtx, 1);
10078 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10086 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10089 get_thread_pointer (int to_reg)
10093 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10097 reg = gen_reg_rtx (Pmode);
10098 insn = gen_rtx_SET (VOIDmode, reg, tp);
10099 insn = emit_insn (insn);
10104 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10105 false if we expect this to be used for a memory address and true if
10106 we expect to load the address into a register. */
10109 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10111 rtx dest, base, off, pic, tp;
10116 case TLS_MODEL_GLOBAL_DYNAMIC:
10117 dest = gen_reg_rtx (Pmode);
10118 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10120 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10122 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10125 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10126 insns = get_insns ();
10129 RTL_CONST_CALL_P (insns) = 1;
10130 emit_libcall_block (insns, dest, rax, x);
10132 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10133 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10135 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10137 if (TARGET_GNU2_TLS)
10139 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10141 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10145 case TLS_MODEL_LOCAL_DYNAMIC:
10146 base = gen_reg_rtx (Pmode);
10147 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10149 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10151 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10154 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10155 insns = get_insns ();
10158 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10159 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10160 RTL_CONST_CALL_P (insns) = 1;
10161 emit_libcall_block (insns, base, rax, note);
10163 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10164 emit_insn (gen_tls_local_dynamic_base_64 (base));
10166 emit_insn (gen_tls_local_dynamic_base_32 (base));
10168 if (TARGET_GNU2_TLS)
10170 rtx x = ix86_tls_module_base ();
10172 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10173 gen_rtx_MINUS (Pmode, x, tp));
10176 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10177 off = gen_rtx_CONST (Pmode, off);
10179 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10181 if (TARGET_GNU2_TLS)
10183 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10185 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10190 case TLS_MODEL_INITIAL_EXEC:
10194 type = UNSPEC_GOTNTPOFF;
10198 if (reload_in_progress)
10199 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10200 pic = pic_offset_table_rtx;
10201 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10203 else if (!TARGET_ANY_GNU_TLS)
10205 pic = gen_reg_rtx (Pmode);
10206 emit_insn (gen_set_got (pic));
10207 type = UNSPEC_GOTTPOFF;
10212 type = UNSPEC_INDNTPOFF;
10215 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10216 off = gen_rtx_CONST (Pmode, off);
10218 off = gen_rtx_PLUS (Pmode, pic, off);
10219 off = gen_const_mem (Pmode, off);
10220 set_mem_alias_set (off, ix86_GOT_alias_set ());
10222 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10224 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10225 off = force_reg (Pmode, off);
10226 return gen_rtx_PLUS (Pmode, base, off);
10230 base = get_thread_pointer (true);
10231 dest = gen_reg_rtx (Pmode);
10232 emit_insn (gen_subsi3 (dest, base, off));
10236 case TLS_MODEL_LOCAL_EXEC:
10237 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10238 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10239 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10240 off = gen_rtx_CONST (Pmode, off);
10242 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10244 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10245 return gen_rtx_PLUS (Pmode, base, off);
10249 base = get_thread_pointer (true);
10250 dest = gen_reg_rtx (Pmode);
10251 emit_insn (gen_subsi3 (dest, base, off));
10256 gcc_unreachable ();
10262 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10265 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10266 htab_t dllimport_map;
10269 get_dllimport_decl (tree decl)
10271 struct tree_map *h, in;
10274 const char *prefix;
10275 size_t namelen, prefixlen;
10280 if (!dllimport_map)
10281 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10283 in.hash = htab_hash_pointer (decl);
10284 in.base.from = decl;
10285 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10286 h = (struct tree_map *) *loc;
10290 *loc = h = GGC_NEW (struct tree_map);
10292 h->base.from = decl;
10293 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10294 VAR_DECL, NULL, ptr_type_node);
10295 DECL_ARTIFICIAL (to) = 1;
10296 DECL_IGNORED_P (to) = 1;
10297 DECL_EXTERNAL (to) = 1;
10298 TREE_READONLY (to) = 1;
10300 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10301 name = targetm.strip_name_encoding (name);
10302 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10303 ? "*__imp_" : "*__imp__";
10304 namelen = strlen (name);
10305 prefixlen = strlen (prefix);
10306 imp_name = (char *) alloca (namelen + prefixlen + 1);
10307 memcpy (imp_name, prefix, prefixlen);
10308 memcpy (imp_name + prefixlen, name, namelen + 1);
10310 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10311 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10312 SET_SYMBOL_REF_DECL (rtl, to);
10313 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10315 rtl = gen_const_mem (Pmode, rtl);
10316 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10318 SET_DECL_RTL (to, rtl);
10319 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10324 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10325 true if we require the result be a register. */
10328 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10333 gcc_assert (SYMBOL_REF_DECL (symbol));
10334 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10336 x = DECL_RTL (imp_decl);
10338 x = force_reg (Pmode, x);
10342 /* Try machine-dependent ways of modifying an illegitimate address
10343 to be legitimate. If we find one, return the new, valid address.
10344 This macro is used in only one place: `memory_address' in explow.c.
10346 OLDX is the address as it was before break_out_memory_refs was called.
10347 In some cases it is useful to look at this to decide what needs to be done.
10349 It is always safe for this macro to do nothing. It exists to recognize
10350 opportunities to optimize the output.
10352 For the 80386, we handle X+REG by loading X into a register R and
10353 using R+REG. R will go in a general reg and indexing will be used.
10354 However, if REG is a broken-out memory address or multiplication,
10355 nothing needs to be done because REG can certainly go in a general reg.
10357 When -fpic is used, special handling is needed for symbolic references.
10358 See comments by legitimize_pic_address in i386.c for details. */
10361 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10362 enum machine_mode mode)
10367 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10369 return legitimize_tls_address (x, (enum tls_model) log, false);
10370 if (GET_CODE (x) == CONST
10371 && GET_CODE (XEXP (x, 0)) == PLUS
10372 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10373 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10375 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10376 (enum tls_model) log, false);
10377 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10380 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10382 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10383 return legitimize_dllimport_symbol (x, true);
10384 if (GET_CODE (x) == CONST
10385 && GET_CODE (XEXP (x, 0)) == PLUS
10386 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10387 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10389 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10390 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10394 if (flag_pic && SYMBOLIC_CONST (x))
10395 return legitimize_pic_address (x, 0);
10397 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10398 if (GET_CODE (x) == ASHIFT
10399 && CONST_INT_P (XEXP (x, 1))
10400 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10403 log = INTVAL (XEXP (x, 1));
10404 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10405 GEN_INT (1 << log));
10408 if (GET_CODE (x) == PLUS)
10410 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10412 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10413 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10414 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10417 log = INTVAL (XEXP (XEXP (x, 0), 1));
10418 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10419 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10420 GEN_INT (1 << log));
10423 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10424 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10425 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10428 log = INTVAL (XEXP (XEXP (x, 1), 1));
10429 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10430 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10431 GEN_INT (1 << log));
10434 /* Put multiply first if it isn't already. */
10435 if (GET_CODE (XEXP (x, 1)) == MULT)
10437 rtx tmp = XEXP (x, 0);
10438 XEXP (x, 0) = XEXP (x, 1);
10443 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10444 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10445 created by virtual register instantiation, register elimination, and
10446 similar optimizations. */
10447 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10450 x = gen_rtx_PLUS (Pmode,
10451 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10452 XEXP (XEXP (x, 1), 0)),
10453 XEXP (XEXP (x, 1), 1));
10457 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10458 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10459 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10460 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10461 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10462 && CONSTANT_P (XEXP (x, 1)))
10465 rtx other = NULL_RTX;
10467 if (CONST_INT_P (XEXP (x, 1)))
10469 constant = XEXP (x, 1);
10470 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10472 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10474 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10475 other = XEXP (x, 1);
10483 x = gen_rtx_PLUS (Pmode,
10484 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10485 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10486 plus_constant (other, INTVAL (constant)));
10490 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10493 if (GET_CODE (XEXP (x, 0)) == MULT)
10496 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10499 if (GET_CODE (XEXP (x, 1)) == MULT)
10502 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10506 && REG_P (XEXP (x, 1))
10507 && REG_P (XEXP (x, 0)))
10510 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10513 x = legitimize_pic_address (x, 0);
10516 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10519 if (REG_P (XEXP (x, 0)))
10521 rtx temp = gen_reg_rtx (Pmode);
10522 rtx val = force_operand (XEXP (x, 1), temp);
10524 emit_move_insn (temp, val);
10526 XEXP (x, 1) = temp;
10530 else if (REG_P (XEXP (x, 1)))
10532 rtx temp = gen_reg_rtx (Pmode);
10533 rtx val = force_operand (XEXP (x, 0), temp);
10535 emit_move_insn (temp, val);
10537 XEXP (x, 0) = temp;
10545 /* Print an integer constant expression in assembler syntax. Addition
10546 and subtraction are the only arithmetic that may appear in these
10547 expressions. FILE is the stdio stream to write to, X is the rtx, and
10548 CODE is the operand print code from the output string. */
10551 output_pic_addr_const (FILE *file, rtx x, int code)
10555 switch (GET_CODE (x))
10558 gcc_assert (flag_pic);
10563 if (! TARGET_MACHO || TARGET_64BIT)
10564 output_addr_const (file, x);
10567 const char *name = XSTR (x, 0);
10569 /* Mark the decl as referenced so that cgraph will
10570 output the function. */
10571 if (SYMBOL_REF_DECL (x))
10572 mark_decl_referenced (SYMBOL_REF_DECL (x));
10575 if (MACHOPIC_INDIRECT
10576 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10577 name = machopic_indirection_name (x, /*stub_p=*/true);
10579 assemble_name (file, name);
10581 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10582 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10583 fputs ("@PLT", file);
10590 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10591 assemble_name (asm_out_file, buf);
10595 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10599 /* This used to output parentheses around the expression,
10600 but that does not work on the 386 (either ATT or BSD assembler). */
10601 output_pic_addr_const (file, XEXP (x, 0), code);
10605 if (GET_MODE (x) == VOIDmode)
10607 /* We can use %d if the number is <32 bits and positive. */
10608 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10609 fprintf (file, "0x%lx%08lx",
10610 (unsigned long) CONST_DOUBLE_HIGH (x),
10611 (unsigned long) CONST_DOUBLE_LOW (x));
10613 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10616 /* We can't handle floating point constants;
10617 PRINT_OPERAND must handle them. */
10618 output_operand_lossage ("floating constant misused");
10622 /* Some assemblers need integer constants to appear first. */
10623 if (CONST_INT_P (XEXP (x, 0)))
10625 output_pic_addr_const (file, XEXP (x, 0), code);
10627 output_pic_addr_const (file, XEXP (x, 1), code);
10631 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10632 output_pic_addr_const (file, XEXP (x, 1), code);
10634 output_pic_addr_const (file, XEXP (x, 0), code);
10640 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10641 output_pic_addr_const (file, XEXP (x, 0), code);
10643 output_pic_addr_const (file, XEXP (x, 1), code);
10645 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10649 gcc_assert (XVECLEN (x, 0) == 1);
10650 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10651 switch (XINT (x, 1))
10654 fputs ("@GOT", file);
10656 case UNSPEC_GOTOFF:
10657 fputs ("@GOTOFF", file);
10659 case UNSPEC_PLTOFF:
10660 fputs ("@PLTOFF", file);
10662 case UNSPEC_GOTPCREL:
10663 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10664 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10666 case UNSPEC_GOTTPOFF:
10667 /* FIXME: This might be @TPOFF in Sun ld too. */
10668 fputs ("@GOTTPOFF", file);
10671 fputs ("@TPOFF", file);
10673 case UNSPEC_NTPOFF:
10675 fputs ("@TPOFF", file);
10677 fputs ("@NTPOFF", file);
10679 case UNSPEC_DTPOFF:
10680 fputs ("@DTPOFF", file);
10682 case UNSPEC_GOTNTPOFF:
10684 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10685 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10687 fputs ("@GOTNTPOFF", file);
10689 case UNSPEC_INDNTPOFF:
10690 fputs ("@INDNTPOFF", file);
10693 case UNSPEC_MACHOPIC_OFFSET:
10695 machopic_output_function_base_name (file);
10699 output_operand_lossage ("invalid UNSPEC as operand");
10705 output_operand_lossage ("invalid expression as operand");
10709 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10710 We need to emit DTP-relative relocations. */
10712 static void ATTRIBUTE_UNUSED
10713 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10715 fputs (ASM_LONG, file);
10716 output_addr_const (file, x);
10717 fputs ("@DTPOFF", file);
10723 fputs (", 0", file);
10726 gcc_unreachable ();
10730 /* Return true if X is a representation of the PIC register. This copes
10731 with calls from ix86_find_base_term, where the register might have
10732 been replaced by a cselib value. */
10735 ix86_pic_register_p (rtx x)
10737 if (GET_CODE (x) == VALUE)
10738 return (pic_offset_table_rtx
10739 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10741 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10744 /* In the name of slightly smaller debug output, and to cater to
10745 general assembler lossage, recognize PIC+GOTOFF and turn it back
10746 into a direct symbol reference.
10748 On Darwin, this is necessary to avoid a crash, because Darwin
10749 has a different PIC label for each routine but the DWARF debugging
10750 information is not associated with any particular routine, so it's
10751 necessary to remove references to the PIC label from RTL stored by
10752 the DWARF output code. */
10755 ix86_delegitimize_address (rtx orig_x)
10758 /* reg_addend is NULL or a multiple of some register. */
10759 rtx reg_addend = NULL_RTX;
10760 /* const_addend is NULL or a const_int. */
10761 rtx const_addend = NULL_RTX;
10762 /* This is the result, or NULL. */
10763 rtx result = NULL_RTX;
10770 if (GET_CODE (x) != CONST
10771 || GET_CODE (XEXP (x, 0)) != UNSPEC
10772 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10773 || !MEM_P (orig_x))
10775 return XVECEXP (XEXP (x, 0), 0, 0);
10778 if (GET_CODE (x) != PLUS
10779 || GET_CODE (XEXP (x, 1)) != CONST)
10782 if (ix86_pic_register_p (XEXP (x, 0)))
10783 /* %ebx + GOT/GOTOFF */
10785 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10787 /* %ebx + %reg * scale + GOT/GOTOFF */
10788 reg_addend = XEXP (x, 0);
10789 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10790 reg_addend = XEXP (reg_addend, 1);
10791 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10792 reg_addend = XEXP (reg_addend, 0);
10795 if (!REG_P (reg_addend)
10796 && GET_CODE (reg_addend) != MULT
10797 && GET_CODE (reg_addend) != ASHIFT)
10803 x = XEXP (XEXP (x, 1), 0);
10804 if (GET_CODE (x) == PLUS
10805 && CONST_INT_P (XEXP (x, 1)))
10807 const_addend = XEXP (x, 1);
10811 if (GET_CODE (x) == UNSPEC
10812 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10813 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10814 result = XVECEXP (x, 0, 0);
10816 if (TARGET_MACHO && darwin_local_data_pic (x)
10817 && !MEM_P (orig_x))
10818 result = XVECEXP (x, 0, 0);
10824 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10826 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10830 /* If X is a machine specific address (i.e. a symbol or label being
10831 referenced as a displacement from the GOT implemented using an
10832 UNSPEC), then return the base term. Otherwise return X. */
10835 ix86_find_base_term (rtx x)
10841 if (GET_CODE (x) != CONST)
10843 term = XEXP (x, 0);
10844 if (GET_CODE (term) == PLUS
10845 && (CONST_INT_P (XEXP (term, 1))
10846 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10847 term = XEXP (term, 0);
10848 if (GET_CODE (term) != UNSPEC
10849 || XINT (term, 1) != UNSPEC_GOTPCREL)
10852 return XVECEXP (term, 0, 0);
10855 return ix86_delegitimize_address (x);
10859 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10860 int fp, FILE *file)
10862 const char *suffix;
10864 if (mode == CCFPmode || mode == CCFPUmode)
10866 code = ix86_fp_compare_code_to_integer (code);
10870 code = reverse_condition (code);
10921 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10925 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10926 Those same assemblers have the same but opposite lossage on cmov. */
10927 if (mode == CCmode)
10928 suffix = fp ? "nbe" : "a";
10929 else if (mode == CCCmode)
10932 gcc_unreachable ();
10948 gcc_unreachable ();
10952 gcc_assert (mode == CCmode || mode == CCCmode);
10969 gcc_unreachable ();
10973 /* ??? As above. */
10974 gcc_assert (mode == CCmode || mode == CCCmode);
10975 suffix = fp ? "nb" : "ae";
10978 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10982 /* ??? As above. */
10983 if (mode == CCmode)
10985 else if (mode == CCCmode)
10986 suffix = fp ? "nb" : "ae";
10988 gcc_unreachable ();
10991 suffix = fp ? "u" : "p";
10994 suffix = fp ? "nu" : "np";
10997 gcc_unreachable ();
10999 fputs (suffix, file);
11002 /* Print the name of register X to FILE based on its machine mode and number.
11003 If CODE is 'w', pretend the mode is HImode.
11004 If CODE is 'b', pretend the mode is QImode.
11005 If CODE is 'k', pretend the mode is SImode.
11006 If CODE is 'q', pretend the mode is DImode.
11007 If CODE is 'x', pretend the mode is V4SFmode.
11008 If CODE is 't', pretend the mode is V8SFmode.
11009 If CODE is 'h', pretend the reg is the 'high' byte register.
11010 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11011 If CODE is 'd', duplicate the operand for AVX instruction.
11015 print_reg (rtx x, int code, FILE *file)
11018 bool duplicated = code == 'd' && TARGET_AVX;
11020 gcc_assert (x == pc_rtx
11021 || (REGNO (x) != ARG_POINTER_REGNUM
11022 && REGNO (x) != FRAME_POINTER_REGNUM
11023 && REGNO (x) != FLAGS_REG
11024 && REGNO (x) != FPSR_REG
11025 && REGNO (x) != FPCR_REG));
11027 if (ASSEMBLER_DIALECT == ASM_ATT)
11032 gcc_assert (TARGET_64BIT);
11033 fputs ("rip", file);
11037 if (code == 'w' || MMX_REG_P (x))
11039 else if (code == 'b')
11041 else if (code == 'k')
11043 else if (code == 'q')
11045 else if (code == 'y')
11047 else if (code == 'h')
11049 else if (code == 'x')
11051 else if (code == 't')
11054 code = GET_MODE_SIZE (GET_MODE (x));
11056 /* Irritatingly, AMD extended registers use different naming convention
11057 from the normal registers. */
11058 if (REX_INT_REG_P (x))
11060 gcc_assert (TARGET_64BIT);
11064 error ("extended registers have no high halves");
11067 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11070 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11073 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11076 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11079 error ("unsupported operand size for extended register");
11089 if (STACK_TOP_P (x))
11098 if (! ANY_FP_REG_P (x))
11099 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11104 reg = hi_reg_name[REGNO (x)];
11107 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11109 reg = qi_reg_name[REGNO (x)];
11112 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11114 reg = qi_high_reg_name[REGNO (x)];
11119 gcc_assert (!duplicated);
11121 fputs (hi_reg_name[REGNO (x)] + 1, file);
11126 gcc_unreachable ();
11132 if (ASSEMBLER_DIALECT == ASM_ATT)
11133 fprintf (file, ", %%%s", reg);
11135 fprintf (file, ", %s", reg);
11139 /* Locate some local-dynamic symbol still in use by this function
11140 so that we can print its name in some tls_local_dynamic_base
11144 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11148 if (GET_CODE (x) == SYMBOL_REF
11149 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11151 cfun->machine->some_ld_name = XSTR (x, 0);
11158 static const char *
11159 get_some_local_dynamic_name (void)
11163 if (cfun->machine->some_ld_name)
11164 return cfun->machine->some_ld_name;
11166 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11168 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11169 return cfun->machine->some_ld_name;
11171 gcc_unreachable ();
11174 /* Meaning of CODE:
11175 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11176 C -- print opcode suffix for set/cmov insn.
11177 c -- like C, but print reversed condition
11178 E,e -- likewise, but for compare-and-branch fused insn.
11179 F,f -- likewise, but for floating-point.
11180 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11182 R -- print the prefix for register names.
11183 z -- print the opcode suffix for the size of the current operand.
11184 Z -- likewise, with special suffixes for x87 instructions.
11185 * -- print a star (in certain assembler syntax)
11186 A -- print an absolute memory reference.
11187 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11188 s -- print a shift double count, followed by the assemblers argument
11190 b -- print the QImode name of the register for the indicated operand.
11191 %b0 would print %al if operands[0] is reg 0.
11192 w -- likewise, print the HImode name of the register.
11193 k -- likewise, print the SImode name of the register.
11194 q -- likewise, print the DImode name of the register.
11195 x -- likewise, print the V4SFmode name of the register.
11196 t -- likewise, print the V8SFmode name of the register.
11197 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11198 y -- print "st(0)" instead of "st" as a register.
11199 d -- print duplicated register operand for AVX instruction.
11200 D -- print condition for SSE cmp instruction.
11201 P -- if PIC, print an @PLT suffix.
11202 X -- don't print any sort of PIC '@' suffix for a symbol.
11203 & -- print some in-use local-dynamic symbol name.
11204 H -- print a memory address offset by 8; used for sse high-parts
11205 + -- print a branch hint as 'cs' or 'ds' prefix
11206 ; -- print a semicolon (after prefixes due to bug in older gas).
11210 print_operand (FILE *file, rtx x, int code)
11217 if (ASSEMBLER_DIALECT == ASM_ATT)
11222 assemble_name (file, get_some_local_dynamic_name ());
11226 switch (ASSEMBLER_DIALECT)
11233 /* Intel syntax. For absolute addresses, registers should not
11234 be surrounded by braces. */
11238 PRINT_OPERAND (file, x, 0);
11245 gcc_unreachable ();
11248 PRINT_OPERAND (file, x, 0);
11253 if (ASSEMBLER_DIALECT == ASM_ATT)
11258 if (ASSEMBLER_DIALECT == ASM_ATT)
11263 if (ASSEMBLER_DIALECT == ASM_ATT)
11268 if (ASSEMBLER_DIALECT == ASM_ATT)
11273 if (ASSEMBLER_DIALECT == ASM_ATT)
11278 if (ASSEMBLER_DIALECT == ASM_ATT)
11283 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11285 /* Opcodes don't get size suffixes if using Intel opcodes. */
11286 if (ASSEMBLER_DIALECT == ASM_INTEL)
11289 switch (GET_MODE_SIZE (GET_MODE (x)))
11308 output_operand_lossage
11309 ("invalid operand size for operand code '%c'", code);
11314 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11316 (0, "non-integer operand used with operand code '%c'", code);
11320 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11321 if (ASSEMBLER_DIALECT == ASM_INTEL)
11324 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11326 switch (GET_MODE_SIZE (GET_MODE (x)))
11329 #ifdef HAVE_AS_IX86_FILDS
11339 #ifdef HAVE_AS_IX86_FILDQ
11342 fputs ("ll", file);
11350 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11352 /* 387 opcodes don't get size suffixes
11353 if the operands are registers. */
11354 if (STACK_REG_P (x))
11357 switch (GET_MODE_SIZE (GET_MODE (x)))
11378 output_operand_lossage
11379 ("invalid operand type used with operand code '%c'", code);
11383 output_operand_lossage
11384 ("invalid operand size for operand code '%c'", code);
11401 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11403 PRINT_OPERAND (file, x, 0);
11404 fputs (", ", file);
11409 /* Little bit of braindamage here. The SSE compare instructions
11410 does use completely different names for the comparisons that the
11411 fp conditional moves. */
11414 switch (GET_CODE (x))
11417 fputs ("eq", file);
11420 fputs ("eq_us", file);
11423 fputs ("lt", file);
11426 fputs ("nge", file);
11429 fputs ("le", file);
11432 fputs ("ngt", file);
11435 fputs ("unord", file);
11438 fputs ("neq", file);
11441 fputs ("neq_oq", file);
11444 fputs ("ge", file);
11447 fputs ("nlt", file);
11450 fputs ("gt", file);
11453 fputs ("nle", file);
11456 fputs ("ord", file);
11459 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11465 switch (GET_CODE (x))
11469 fputs ("eq", file);
11473 fputs ("lt", file);
11477 fputs ("le", file);
11480 fputs ("unord", file);
11484 fputs ("neq", file);
11488 fputs ("nlt", file);
11492 fputs ("nle", file);
11495 fputs ("ord", file);
11498 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11504 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11505 if (ASSEMBLER_DIALECT == ASM_ATT)
11507 switch (GET_MODE (x))
11509 case HImode: putc ('w', file); break;
11511 case SFmode: putc ('l', file); break;
11513 case DFmode: putc ('q', file); break;
11514 default: gcc_unreachable ();
11521 if (!COMPARISON_P (x))
11523 output_operand_lossage ("operand is neither a constant nor a "
11524 "condition code, invalid operand code "
11528 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11531 if (!COMPARISON_P (x))
11533 output_operand_lossage ("operand is neither a constant nor a "
11534 "condition code, invalid operand code "
11538 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11539 if (ASSEMBLER_DIALECT == ASM_ATT)
11542 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11545 /* Like above, but reverse condition */
11547 /* Check to see if argument to %c is really a constant
11548 and not a condition code which needs to be reversed. */
11549 if (!COMPARISON_P (x))
11551 output_operand_lossage ("operand is neither a constant nor a "
11552 "condition code, invalid operand "
11556 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11559 if (!COMPARISON_P (x))
11561 output_operand_lossage ("operand is neither a constant nor a "
11562 "condition code, invalid operand "
11566 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11567 if (ASSEMBLER_DIALECT == ASM_ATT)
11570 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11574 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11578 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11582 /* It doesn't actually matter what mode we use here, as we're
11583 only going to use this for printing. */
11584 x = adjust_address_nv (x, DImode, 8);
11592 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11595 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11598 int pred_val = INTVAL (XEXP (x, 0));
11600 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11601 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11603 int taken = pred_val > REG_BR_PROB_BASE / 2;
11604 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11606 /* Emit hints only in the case default branch prediction
11607 heuristics would fail. */
11608 if (taken != cputaken)
11610 /* We use 3e (DS) prefix for taken branches and
11611 2e (CS) prefix for not taken branches. */
11613 fputs ("ds ; ", file);
11615 fputs ("cs ; ", file);
11624 fputs (" ; ", file);
11631 output_operand_lossage ("invalid operand code '%c'", code);
11636 print_reg (x, code, file);
11638 else if (MEM_P (x))
11640 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11641 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11642 && GET_MODE (x) != BLKmode)
11645 switch (GET_MODE_SIZE (GET_MODE (x)))
11647 case 1: size = "BYTE"; break;
11648 case 2: size = "WORD"; break;
11649 case 4: size = "DWORD"; break;
11650 case 8: size = "QWORD"; break;
11651 case 12: size = "XWORD"; break;
11653 if (GET_MODE (x) == XFmode)
11659 gcc_unreachable ();
11662 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11665 else if (code == 'w')
11667 else if (code == 'k')
11670 fputs (size, file);
11671 fputs (" PTR ", file);
11675 /* Avoid (%rip) for call operands. */
11676 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11677 && !CONST_INT_P (x))
11678 output_addr_const (file, x);
11679 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11680 output_operand_lossage ("invalid constraints for operand");
11682 output_address (x);
11685 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11690 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11691 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11693 if (ASSEMBLER_DIALECT == ASM_ATT)
11695 fprintf (file, "0x%08lx", (long unsigned int) l);
11698 /* These float cases don't actually occur as immediate operands. */
11699 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11703 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11704 fputs (dstr, file);
11707 else if (GET_CODE (x) == CONST_DOUBLE
11708 && GET_MODE (x) == XFmode)
11712 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11713 fputs (dstr, file);
11718 /* We have patterns that allow zero sets of memory, for instance.
11719 In 64-bit mode, we should probably support all 8-byte vectors,
11720 since we can in fact encode that into an immediate. */
11721 if (GET_CODE (x) == CONST_VECTOR)
11723 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11729 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11731 if (ASSEMBLER_DIALECT == ASM_ATT)
11734 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11735 || GET_CODE (x) == LABEL_REF)
11737 if (ASSEMBLER_DIALECT == ASM_ATT)
11740 fputs ("OFFSET FLAT:", file);
11743 if (CONST_INT_P (x))
11744 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11746 output_pic_addr_const (file, x, code);
11748 output_addr_const (file, x);
11752 /* Print a memory operand whose address is ADDR. */
11755 print_operand_address (FILE *file, rtx addr)
11757 struct ix86_address parts;
11758 rtx base, index, disp;
11760 int ok = ix86_decompose_address (addr, &parts);
11765 index = parts.index;
11767 scale = parts.scale;
11775 if (ASSEMBLER_DIALECT == ASM_ATT)
11777 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11780 gcc_unreachable ();
11783 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11784 if (TARGET_64BIT && !base && !index)
11788 if (GET_CODE (disp) == CONST
11789 && GET_CODE (XEXP (disp, 0)) == PLUS
11790 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11791 symbol = XEXP (XEXP (disp, 0), 0);
11793 if (GET_CODE (symbol) == LABEL_REF
11794 || (GET_CODE (symbol) == SYMBOL_REF
11795 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11798 if (!base && !index)
11800 /* Displacement only requires special attention. */
11802 if (CONST_INT_P (disp))
11804 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11805 fputs ("ds:", file);
11806 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11809 output_pic_addr_const (file, disp, 0);
11811 output_addr_const (file, disp);
11815 if (ASSEMBLER_DIALECT == ASM_ATT)
11820 output_pic_addr_const (file, disp, 0);
11821 else if (GET_CODE (disp) == LABEL_REF)
11822 output_asm_label (disp);
11824 output_addr_const (file, disp);
11829 print_reg (base, 0, file);
11833 print_reg (index, 0, file);
11835 fprintf (file, ",%d", scale);
11841 rtx offset = NULL_RTX;
11845 /* Pull out the offset of a symbol; print any symbol itself. */
11846 if (GET_CODE (disp) == CONST
11847 && GET_CODE (XEXP (disp, 0)) == PLUS
11848 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11850 offset = XEXP (XEXP (disp, 0), 1);
11851 disp = gen_rtx_CONST (VOIDmode,
11852 XEXP (XEXP (disp, 0), 0));
11856 output_pic_addr_const (file, disp, 0);
11857 else if (GET_CODE (disp) == LABEL_REF)
11858 output_asm_label (disp);
11859 else if (CONST_INT_P (disp))
11862 output_addr_const (file, disp);
11868 print_reg (base, 0, file);
11871 if (INTVAL (offset) >= 0)
11873 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11877 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11884 print_reg (index, 0, file);
11886 fprintf (file, "*%d", scale);
11894 output_addr_const_extra (FILE *file, rtx x)
11898 if (GET_CODE (x) != UNSPEC)
11901 op = XVECEXP (x, 0, 0);
11902 switch (XINT (x, 1))
11904 case UNSPEC_GOTTPOFF:
11905 output_addr_const (file, op);
11906 /* FIXME: This might be @TPOFF in Sun ld. */
11907 fputs ("@GOTTPOFF", file);
11910 output_addr_const (file, op);
11911 fputs ("@TPOFF", file);
11913 case UNSPEC_NTPOFF:
11914 output_addr_const (file, op);
11916 fputs ("@TPOFF", file);
11918 fputs ("@NTPOFF", file);
11920 case UNSPEC_DTPOFF:
11921 output_addr_const (file, op);
11922 fputs ("@DTPOFF", file);
11924 case UNSPEC_GOTNTPOFF:
11925 output_addr_const (file, op);
11927 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11928 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11930 fputs ("@GOTNTPOFF", file);
11932 case UNSPEC_INDNTPOFF:
11933 output_addr_const (file, op);
11934 fputs ("@INDNTPOFF", file);
11937 case UNSPEC_MACHOPIC_OFFSET:
11938 output_addr_const (file, op);
11940 machopic_output_function_base_name (file);
11951 /* Split one or more DImode RTL references into pairs of SImode
11952 references. The RTL can be REG, offsettable MEM, integer constant, or
11953 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11954 split and "num" is its length. lo_half and hi_half are output arrays
11955 that parallel "operands". */
11958 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11962 rtx op = operands[num];
11964 /* simplify_subreg refuse to split volatile memory addresses,
11965 but we still have to handle it. */
11968 lo_half[num] = adjust_address (op, SImode, 0);
11969 hi_half[num] = adjust_address (op, SImode, 4);
11973 lo_half[num] = simplify_gen_subreg (SImode, op,
11974 GET_MODE (op) == VOIDmode
11975 ? DImode : GET_MODE (op), 0);
11976 hi_half[num] = simplify_gen_subreg (SImode, op,
11977 GET_MODE (op) == VOIDmode
11978 ? DImode : GET_MODE (op), 4);
11982 /* Split one or more TImode RTL references into pairs of DImode
11983 references. The RTL can be REG, offsettable MEM, integer constant, or
11984 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11985 split and "num" is its length. lo_half and hi_half are output arrays
11986 that parallel "operands". */
11989 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11993 rtx op = operands[num];
11995 /* simplify_subreg refuse to split volatile memory addresses, but we
11996 still have to handle it. */
11999 lo_half[num] = adjust_address (op, DImode, 0);
12000 hi_half[num] = adjust_address (op, DImode, 8);
12004 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12005 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12010 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12011 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12012 is the expression of the binary operation. The output may either be
12013 emitted here, or returned to the caller, like all output_* functions.
12015 There is no guarantee that the operands are the same mode, as they
12016 might be within FLOAT or FLOAT_EXTEND expressions. */
12018 #ifndef SYSV386_COMPAT
12019 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12020 wants to fix the assemblers because that causes incompatibility
12021 with gcc. No-one wants to fix gcc because that causes
12022 incompatibility with assemblers... You can use the option of
12023 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12024 #define SYSV386_COMPAT 1
12028 output_387_binary_op (rtx insn, rtx *operands)
12030 static char buf[40];
12033 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12035 #ifdef ENABLE_CHECKING
12036 /* Even if we do not want to check the inputs, this documents input
12037 constraints. Which helps in understanding the following code. */
12038 if (STACK_REG_P (operands[0])
12039 && ((REG_P (operands[1])
12040 && REGNO (operands[0]) == REGNO (operands[1])
12041 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12042 || (REG_P (operands[2])
12043 && REGNO (operands[0]) == REGNO (operands[2])
12044 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12045 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12048 gcc_assert (is_sse);
12051 switch (GET_CODE (operands[3]))
12054 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12055 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12063 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12064 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12072 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12073 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12081 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12082 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12090 gcc_unreachable ();
12097 strcpy (buf, ssep);
12098 if (GET_MODE (operands[0]) == SFmode)
12099 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12101 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12105 strcpy (buf, ssep + 1);
12106 if (GET_MODE (operands[0]) == SFmode)
12107 strcat (buf, "ss\t{%2, %0|%0, %2}");
12109 strcat (buf, "sd\t{%2, %0|%0, %2}");
12115 switch (GET_CODE (operands[3]))
12119 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12121 rtx temp = operands[2];
12122 operands[2] = operands[1];
12123 operands[1] = temp;
12126 /* know operands[0] == operands[1]. */
12128 if (MEM_P (operands[2]))
12134 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12136 if (STACK_TOP_P (operands[0]))
12137 /* How is it that we are storing to a dead operand[2]?
12138 Well, presumably operands[1] is dead too. We can't
12139 store the result to st(0) as st(0) gets popped on this
12140 instruction. Instead store to operands[2] (which I
12141 think has to be st(1)). st(1) will be popped later.
12142 gcc <= 2.8.1 didn't have this check and generated
12143 assembly code that the Unixware assembler rejected. */
12144 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12146 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12150 if (STACK_TOP_P (operands[0]))
12151 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12153 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12158 if (MEM_P (operands[1]))
12164 if (MEM_P (operands[2]))
12170 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12173 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12174 derived assemblers, confusingly reverse the direction of
12175 the operation for fsub{r} and fdiv{r} when the
12176 destination register is not st(0). The Intel assembler
12177 doesn't have this brain damage. Read !SYSV386_COMPAT to
12178 figure out what the hardware really does. */
12179 if (STACK_TOP_P (operands[0]))
12180 p = "{p\t%0, %2|rp\t%2, %0}";
12182 p = "{rp\t%2, %0|p\t%0, %2}";
12184 if (STACK_TOP_P (operands[0]))
12185 /* As above for fmul/fadd, we can't store to st(0). */
12186 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12188 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12193 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12196 if (STACK_TOP_P (operands[0]))
12197 p = "{rp\t%0, %1|p\t%1, %0}";
12199 p = "{p\t%1, %0|rp\t%0, %1}";
12201 if (STACK_TOP_P (operands[0]))
12202 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12204 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12209 if (STACK_TOP_P (operands[0]))
12211 if (STACK_TOP_P (operands[1]))
12212 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12214 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12217 else if (STACK_TOP_P (operands[1]))
12220 p = "{\t%1, %0|r\t%0, %1}";
12222 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12228 p = "{r\t%2, %0|\t%0, %2}";
12230 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12236 gcc_unreachable ();
12243 /* Return needed mode for entity in optimize_mode_switching pass. */
12246 ix86_mode_needed (int entity, rtx insn)
12248 enum attr_i387_cw mode;
12250 /* The mode UNINITIALIZED is used to store control word after a
12251 function call or ASM pattern. The mode ANY specify that function
12252 has no requirements on the control word and make no changes in the
12253 bits we are interested in. */
12256 || (NONJUMP_INSN_P (insn)
12257 && (asm_noperands (PATTERN (insn)) >= 0
12258 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12259 return I387_CW_UNINITIALIZED;
12261 if (recog_memoized (insn) < 0)
12262 return I387_CW_ANY;
12264 mode = get_attr_i387_cw (insn);
12269 if (mode == I387_CW_TRUNC)
12274 if (mode == I387_CW_FLOOR)
12279 if (mode == I387_CW_CEIL)
12284 if (mode == I387_CW_MASK_PM)
12289 gcc_unreachable ();
12292 return I387_CW_ANY;
12295 /* Output code to initialize control word copies used by trunc?f?i and
12296 rounding patterns. CURRENT_MODE is set to current control word,
12297 while NEW_MODE is set to new control word. */
12300 emit_i387_cw_initialization (int mode)
12302 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12305 enum ix86_stack_slot slot;
12307 rtx reg = gen_reg_rtx (HImode);
12309 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12310 emit_move_insn (reg, copy_rtx (stored_mode));
12312 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12313 || optimize_function_for_size_p (cfun))
12317 case I387_CW_TRUNC:
12318 /* round toward zero (truncate) */
12319 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12320 slot = SLOT_CW_TRUNC;
12323 case I387_CW_FLOOR:
12324 /* round down toward -oo */
12325 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12326 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12327 slot = SLOT_CW_FLOOR;
12331 /* round up toward +oo */
12332 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12333 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12334 slot = SLOT_CW_CEIL;
12337 case I387_CW_MASK_PM:
12338 /* mask precision exception for nearbyint() */
12339 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12340 slot = SLOT_CW_MASK_PM;
12344 gcc_unreachable ();
12351 case I387_CW_TRUNC:
12352 /* round toward zero (truncate) */
12353 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12354 slot = SLOT_CW_TRUNC;
12357 case I387_CW_FLOOR:
12358 /* round down toward -oo */
12359 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12360 slot = SLOT_CW_FLOOR;
12364 /* round up toward +oo */
12365 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12366 slot = SLOT_CW_CEIL;
12369 case I387_CW_MASK_PM:
12370 /* mask precision exception for nearbyint() */
12371 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12372 slot = SLOT_CW_MASK_PM;
12376 gcc_unreachable ();
12380 gcc_assert (slot < MAX_386_STACK_LOCALS);
12382 new_mode = assign_386_stack_local (HImode, slot);
12383 emit_move_insn (new_mode, reg);
12386 /* Output code for INSN to convert a float to a signed int. OPERANDS
12387 are the insn operands. The output may be [HSD]Imode and the input
12388 operand may be [SDX]Fmode. */
12391 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12393 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12394 int dimode_p = GET_MODE (operands[0]) == DImode;
12395 int round_mode = get_attr_i387_cw (insn);
12397 /* Jump through a hoop or two for DImode, since the hardware has no
12398 non-popping instruction. We used to do this a different way, but
12399 that was somewhat fragile and broke with post-reload splitters. */
12400 if ((dimode_p || fisttp) && !stack_top_dies)
12401 output_asm_insn ("fld\t%y1", operands);
12403 gcc_assert (STACK_TOP_P (operands[1]));
12404 gcc_assert (MEM_P (operands[0]));
12405 gcc_assert (GET_MODE (operands[1]) != TFmode);
12408 output_asm_insn ("fisttp%Z0\t%0", operands);
12411 if (round_mode != I387_CW_ANY)
12412 output_asm_insn ("fldcw\t%3", operands);
12413 if (stack_top_dies || dimode_p)
12414 output_asm_insn ("fistp%Z0\t%0", operands);
12416 output_asm_insn ("fist%Z0\t%0", operands);
12417 if (round_mode != I387_CW_ANY)
12418 output_asm_insn ("fldcw\t%2", operands);
12424 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12425 have the values zero or one, indicates the ffreep insn's operand
12426 from the OPERANDS array. */
12428 static const char *
12429 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12431 if (TARGET_USE_FFREEP)
12432 #ifdef HAVE_AS_IX86_FFREEP
12433 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12436 static char retval[32];
12437 int regno = REGNO (operands[opno]);
12439 gcc_assert (FP_REGNO_P (regno));
12441 regno -= FIRST_STACK_REG;
12443 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12448 return opno ? "fstp\t%y1" : "fstp\t%y0";
12452 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12453 should be used. UNORDERED_P is true when fucom should be used. */
12456 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12458 int stack_top_dies;
12459 rtx cmp_op0, cmp_op1;
12460 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12464 cmp_op0 = operands[0];
12465 cmp_op1 = operands[1];
12469 cmp_op0 = operands[1];
12470 cmp_op1 = operands[2];
12475 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12476 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12477 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12478 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12480 if (GET_MODE (operands[0]) == SFmode)
12482 return &ucomiss[TARGET_AVX ? 0 : 1];
12484 return &comiss[TARGET_AVX ? 0 : 1];
12487 return &ucomisd[TARGET_AVX ? 0 : 1];
12489 return &comisd[TARGET_AVX ? 0 : 1];
12492 gcc_assert (STACK_TOP_P (cmp_op0));
12494 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12496 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12498 if (stack_top_dies)
12500 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12501 return output_387_ffreep (operands, 1);
12504 return "ftst\n\tfnstsw\t%0";
12507 if (STACK_REG_P (cmp_op1)
12509 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12510 && REGNO (cmp_op1) != FIRST_STACK_REG)
12512 /* If both the top of the 387 stack dies, and the other operand
12513 is also a stack register that dies, then this must be a
12514 `fcompp' float compare */
12518 /* There is no double popping fcomi variant. Fortunately,
12519 eflags is immune from the fstp's cc clobbering. */
12521 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12523 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12524 return output_387_ffreep (operands, 0);
12529 return "fucompp\n\tfnstsw\t%0";
12531 return "fcompp\n\tfnstsw\t%0";
12536 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12538 static const char * const alt[16] =
12540 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12541 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12542 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12543 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12545 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12546 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12550 "fcomi\t{%y1, %0|%0, %y1}",
12551 "fcomip\t{%y1, %0|%0, %y1}",
12552 "fucomi\t{%y1, %0|%0, %y1}",
12553 "fucomip\t{%y1, %0|%0, %y1}",
12564 mask = eflags_p << 3;
12565 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12566 mask |= unordered_p << 1;
12567 mask |= stack_top_dies;
12569 gcc_assert (mask < 16);
12578 ix86_output_addr_vec_elt (FILE *file, int value)
12580 const char *directive = ASM_LONG;
12584 directive = ASM_QUAD;
12586 gcc_assert (!TARGET_64BIT);
12589 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12593 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12595 const char *directive = ASM_LONG;
12598 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12599 directive = ASM_QUAD;
12601 gcc_assert (!TARGET_64BIT);
12603 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12604 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12605 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12606 directive, value, rel);
12607 else if (HAVE_AS_GOTOFF_IN_DATA)
12608 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12610 else if (TARGET_MACHO)
12612 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12613 machopic_output_function_base_name (file);
12618 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12619 GOT_SYMBOL_NAME, value);
12622 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12626 ix86_expand_clear (rtx dest)
12630 /* We play register width games, which are only valid after reload. */
12631 gcc_assert (reload_completed);
12633 /* Avoid HImode and its attendant prefix byte. */
12634 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12635 dest = gen_rtx_REG (SImode, REGNO (dest));
12636 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12638 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12639 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12641 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12642 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12648 /* X is an unchanging MEM. If it is a constant pool reference, return
12649 the constant pool rtx, else NULL. */
12652 maybe_get_pool_constant (rtx x)
12654 x = ix86_delegitimize_address (XEXP (x, 0));
12656 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12657 return get_pool_constant (x);
12663 ix86_expand_move (enum machine_mode mode, rtx operands[])
12666 enum tls_model model;
12671 if (GET_CODE (op1) == SYMBOL_REF)
12673 model = SYMBOL_REF_TLS_MODEL (op1);
12676 op1 = legitimize_tls_address (op1, model, true);
12677 op1 = force_operand (op1, op0);
12681 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12682 && SYMBOL_REF_DLLIMPORT_P (op1))
12683 op1 = legitimize_dllimport_symbol (op1, false);
12685 else if (GET_CODE (op1) == CONST
12686 && GET_CODE (XEXP (op1, 0)) == PLUS
12687 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12689 rtx addend = XEXP (XEXP (op1, 0), 1);
12690 rtx symbol = XEXP (XEXP (op1, 0), 0);
12693 model = SYMBOL_REF_TLS_MODEL (symbol);
12695 tmp = legitimize_tls_address (symbol, model, true);
12696 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12697 && SYMBOL_REF_DLLIMPORT_P (symbol))
12698 tmp = legitimize_dllimport_symbol (symbol, true);
12702 tmp = force_operand (tmp, NULL);
12703 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12704 op0, 1, OPTAB_DIRECT);
12710 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12712 if (TARGET_MACHO && !TARGET_64BIT)
12717 rtx temp = ((reload_in_progress
12718 || ((op0 && REG_P (op0))
12720 ? op0 : gen_reg_rtx (Pmode));
12721 op1 = machopic_indirect_data_reference (op1, temp);
12722 op1 = machopic_legitimize_pic_address (op1, mode,
12723 temp == op1 ? 0 : temp);
12725 else if (MACHOPIC_INDIRECT)
12726 op1 = machopic_indirect_data_reference (op1, 0);
12734 op1 = force_reg (Pmode, op1);
12735 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12737 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12738 op1 = legitimize_pic_address (op1, reg);
12747 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12748 || !push_operand (op0, mode))
12750 op1 = force_reg (mode, op1);
12752 if (push_operand (op0, mode)
12753 && ! general_no_elim_operand (op1, mode))
12754 op1 = copy_to_mode_reg (mode, op1);
12756 /* Force large constants in 64bit compilation into register
12757 to get them CSEed. */
12758 if (can_create_pseudo_p ()
12759 && (mode == DImode) && TARGET_64BIT
12760 && immediate_operand (op1, mode)
12761 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12762 && !register_operand (op0, mode)
12764 op1 = copy_to_mode_reg (mode, op1);
12766 if (can_create_pseudo_p ()
12767 && FLOAT_MODE_P (mode)
12768 && GET_CODE (op1) == CONST_DOUBLE)
12770 /* If we are loading a floating point constant to a register,
12771 force the value to memory now, since we'll get better code
12772 out the back end. */
12774 op1 = validize_mem (force_const_mem (mode, op1));
12775 if (!register_operand (op0, mode))
12777 rtx temp = gen_reg_rtx (mode);
12778 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12779 emit_move_insn (op0, temp);
12785 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12789 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12791 rtx op0 = operands[0], op1 = operands[1];
12792 unsigned int align = GET_MODE_ALIGNMENT (mode);
12794 /* Force constants other than zero into memory. We do not know how
12795 the instructions used to build constants modify the upper 64 bits
12796 of the register, once we have that information we may be able
12797 to handle some of them more efficiently. */
12798 if (can_create_pseudo_p ()
12799 && register_operand (op0, mode)
12800 && (CONSTANT_P (op1)
12801 || (GET_CODE (op1) == SUBREG
12802 && CONSTANT_P (SUBREG_REG (op1))))
12803 && !standard_sse_constant_p (op1))
12804 op1 = validize_mem (force_const_mem (mode, op1));
12806 /* We need to check memory alignment for SSE mode since attribute
12807 can make operands unaligned. */
12808 if (can_create_pseudo_p ()
12809 && SSE_REG_MODE_P (mode)
12810 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12811 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12815 /* ix86_expand_vector_move_misalign() does not like constants ... */
12816 if (CONSTANT_P (op1)
12817 || (GET_CODE (op1) == SUBREG
12818 && CONSTANT_P (SUBREG_REG (op1))))
12819 op1 = validize_mem (force_const_mem (mode, op1));
12821 /* ... nor both arguments in memory. */
12822 if (!register_operand (op0, mode)
12823 && !register_operand (op1, mode))
12824 op1 = force_reg (mode, op1);
12826 tmp[0] = op0; tmp[1] = op1;
12827 ix86_expand_vector_move_misalign (mode, tmp);
12831 /* Make operand1 a register if it isn't already. */
12832 if (can_create_pseudo_p ()
12833 && !register_operand (op0, mode)
12834 && !register_operand (op1, mode))
12836 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12840 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12843 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12844 straight to ix86_expand_vector_move. */
12845 /* Code generation for scalar reg-reg moves of single and double precision data:
12846 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12850 if (x86_sse_partial_reg_dependency == true)
12855 Code generation for scalar loads of double precision data:
12856 if (x86_sse_split_regs == true)
12857 movlpd mem, reg (gas syntax)
12861 Code generation for unaligned packed loads of single precision data
12862 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12863 if (x86_sse_unaligned_move_optimal)
12866 if (x86_sse_partial_reg_dependency == true)
12878 Code generation for unaligned packed loads of double precision data
12879 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12880 if (x86_sse_unaligned_move_optimal)
12883 if (x86_sse_split_regs == true)
12896 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12905 switch (GET_MODE_CLASS (mode))
12907 case MODE_VECTOR_INT:
12909 switch (GET_MODE_SIZE (mode))
12912 op0 = gen_lowpart (V16QImode, op0);
12913 op1 = gen_lowpart (V16QImode, op1);
12914 emit_insn (gen_avx_movdqu (op0, op1));
12917 op0 = gen_lowpart (V32QImode, op0);
12918 op1 = gen_lowpart (V32QImode, op1);
12919 emit_insn (gen_avx_movdqu256 (op0, op1));
12922 gcc_unreachable ();
12925 case MODE_VECTOR_FLOAT:
12926 op0 = gen_lowpart (mode, op0);
12927 op1 = gen_lowpart (mode, op1);
12932 emit_insn (gen_avx_movups (op0, op1));
12935 emit_insn (gen_avx_movups256 (op0, op1));
12938 emit_insn (gen_avx_movupd (op0, op1));
12941 emit_insn (gen_avx_movupd256 (op0, op1));
12944 gcc_unreachable ();
12949 gcc_unreachable ();
12957 /* If we're optimizing for size, movups is the smallest. */
12958 if (optimize_insn_for_size_p ())
12960 op0 = gen_lowpart (V4SFmode, op0);
12961 op1 = gen_lowpart (V4SFmode, op1);
12962 emit_insn (gen_sse_movups (op0, op1));
12966 /* ??? If we have typed data, then it would appear that using
12967 movdqu is the only way to get unaligned data loaded with
12969 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12971 op0 = gen_lowpart (V16QImode, op0);
12972 op1 = gen_lowpart (V16QImode, op1);
12973 emit_insn (gen_sse2_movdqu (op0, op1));
12977 if (TARGET_SSE2 && mode == V2DFmode)
12981 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12983 op0 = gen_lowpart (V2DFmode, op0);
12984 op1 = gen_lowpart (V2DFmode, op1);
12985 emit_insn (gen_sse2_movupd (op0, op1));
12989 /* When SSE registers are split into halves, we can avoid
12990 writing to the top half twice. */
12991 if (TARGET_SSE_SPLIT_REGS)
12993 emit_clobber (op0);
12998 /* ??? Not sure about the best option for the Intel chips.
12999 The following would seem to satisfy; the register is
13000 entirely cleared, breaking the dependency chain. We
13001 then store to the upper half, with a dependency depth
13002 of one. A rumor has it that Intel recommends two movsd
13003 followed by an unpacklpd, but this is unconfirmed. And
13004 given that the dependency depth of the unpacklpd would
13005 still be one, I'm not sure why this would be better. */
13006 zero = CONST0_RTX (V2DFmode);
13009 m = adjust_address (op1, DFmode, 0);
13010 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13011 m = adjust_address (op1, DFmode, 8);
13012 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13016 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13018 op0 = gen_lowpart (V4SFmode, op0);
13019 op1 = gen_lowpart (V4SFmode, op1);
13020 emit_insn (gen_sse_movups (op0, op1));
13024 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13025 emit_move_insn (op0, CONST0_RTX (mode));
13027 emit_clobber (op0);
13029 if (mode != V4SFmode)
13030 op0 = gen_lowpart (V4SFmode, op0);
13031 m = adjust_address (op1, V2SFmode, 0);
13032 emit_insn (gen_sse_loadlps (op0, op0, m));
13033 m = adjust_address (op1, V2SFmode, 8);
13034 emit_insn (gen_sse_loadhps (op0, op0, m));
13037 else if (MEM_P (op0))
13039 /* If we're optimizing for size, movups is the smallest. */
13040 if (optimize_insn_for_size_p ())
13042 op0 = gen_lowpart (V4SFmode, op0);
13043 op1 = gen_lowpart (V4SFmode, op1);
13044 emit_insn (gen_sse_movups (op0, op1));
13048 /* ??? Similar to above, only less clear because of quote
13049 typeless stores unquote. */
13050 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13051 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13053 op0 = gen_lowpart (V16QImode, op0);
13054 op1 = gen_lowpart (V16QImode, op1);
13055 emit_insn (gen_sse2_movdqu (op0, op1));
13059 if (TARGET_SSE2 && mode == V2DFmode)
13061 m = adjust_address (op0, DFmode, 0);
13062 emit_insn (gen_sse2_storelpd (m, op1));
13063 m = adjust_address (op0, DFmode, 8);
13064 emit_insn (gen_sse2_storehpd (m, op1));
13068 if (mode != V4SFmode)
13069 op1 = gen_lowpart (V4SFmode, op1);
13070 m = adjust_address (op0, V2SFmode, 0);
13071 emit_insn (gen_sse_storelps (m, op1));
13072 m = adjust_address (op0, V2SFmode, 8);
13073 emit_insn (gen_sse_storehps (m, op1));
13077 gcc_unreachable ();
13080 /* Expand a push in MODE. This is some mode for which we do not support
13081 proper push instructions, at least from the registers that we expect
13082 the value to live in. */
13085 ix86_expand_push (enum machine_mode mode, rtx x)
13089 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13090 GEN_INT (-GET_MODE_SIZE (mode)),
13091 stack_pointer_rtx, 1, OPTAB_DIRECT);
13092 if (tmp != stack_pointer_rtx)
13093 emit_move_insn (stack_pointer_rtx, tmp);
13095 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13097 /* When we push an operand onto stack, it has to be aligned at least
13098 at the function argument boundary. However since we don't have
13099 the argument type, we can't determine the actual argument
13101 emit_move_insn (tmp, x);
13104 /* Helper function of ix86_fixup_binary_operands to canonicalize
13105 operand order. Returns true if the operands should be swapped. */
13108 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13111 rtx dst = operands[0];
13112 rtx src1 = operands[1];
13113 rtx src2 = operands[2];
13115 /* If the operation is not commutative, we can't do anything. */
13116 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13119 /* Highest priority is that src1 should match dst. */
13120 if (rtx_equal_p (dst, src1))
13122 if (rtx_equal_p (dst, src2))
13125 /* Next highest priority is that immediate constants come second. */
13126 if (immediate_operand (src2, mode))
13128 if (immediate_operand (src1, mode))
13131 /* Lowest priority is that memory references should come second. */
13141 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13142 destination to use for the operation. If different from the true
13143 destination in operands[0], a copy operation will be required. */
13146 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13149 rtx dst = operands[0];
13150 rtx src1 = operands[1];
13151 rtx src2 = operands[2];
13153 /* Canonicalize operand order. */
13154 if (ix86_swap_binary_operands_p (code, mode, operands))
13158 /* It is invalid to swap operands of different modes. */
13159 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13166 /* Both source operands cannot be in memory. */
13167 if (MEM_P (src1) && MEM_P (src2))
13169 /* Optimization: Only read from memory once. */
13170 if (rtx_equal_p (src1, src2))
13172 src2 = force_reg (mode, src2);
13176 src2 = force_reg (mode, src2);
13179 /* If the destination is memory, and we do not have matching source
13180 operands, do things in registers. */
13181 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13182 dst = gen_reg_rtx (mode);
13184 /* Source 1 cannot be a constant. */
13185 if (CONSTANT_P (src1))
13186 src1 = force_reg (mode, src1);
13188 /* Source 1 cannot be a non-matching memory. */
13189 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13190 src1 = force_reg (mode, src1);
13192 operands[1] = src1;
13193 operands[2] = src2;
13197 /* Similarly, but assume that the destination has already been
13198 set up properly. */
13201 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13202 enum machine_mode mode, rtx operands[])
13204 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13205 gcc_assert (dst == operands[0]);
13208 /* Attempt to expand a binary operator. Make the expansion closer to the
13209 actual machine, then just general_operand, which will allow 3 separate
13210 memory references (one output, two input) in a single insn. */
13213 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13216 rtx src1, src2, dst, op, clob;
13218 dst = ix86_fixup_binary_operands (code, mode, operands);
13219 src1 = operands[1];
13220 src2 = operands[2];
13222 /* Emit the instruction. */
13224 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13225 if (reload_in_progress)
13227 /* Reload doesn't know about the flags register, and doesn't know that
13228 it doesn't want to clobber it. We can only do this with PLUS. */
13229 gcc_assert (code == PLUS);
13234 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13235 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13238 /* Fix up the destination if needed. */
13239 if (dst != operands[0])
13240 emit_move_insn (operands[0], dst);
13243 /* Return TRUE or FALSE depending on whether the binary operator meets the
13244 appropriate constraints. */
13247 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13250 rtx dst = operands[0];
13251 rtx src1 = operands[1];
13252 rtx src2 = operands[2];
13254 /* Both source operands cannot be in memory. */
13255 if (MEM_P (src1) && MEM_P (src2))
13258 /* Canonicalize operand order for commutative operators. */
13259 if (ix86_swap_binary_operands_p (code, mode, operands))
13266 /* If the destination is memory, we must have a matching source operand. */
13267 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13270 /* Source 1 cannot be a constant. */
13271 if (CONSTANT_P (src1))
13274 /* Source 1 cannot be a non-matching memory. */
13275 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13281 /* Attempt to expand a unary operator. Make the expansion closer to the
13282 actual machine, then just general_operand, which will allow 2 separate
13283 memory references (one output, one input) in a single insn. */
13286 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13289 int matching_memory;
13290 rtx src, dst, op, clob;
13295 /* If the destination is memory, and we do not have matching source
13296 operands, do things in registers. */
13297 matching_memory = 0;
13300 if (rtx_equal_p (dst, src))
13301 matching_memory = 1;
13303 dst = gen_reg_rtx (mode);
13306 /* When source operand is memory, destination must match. */
13307 if (MEM_P (src) && !matching_memory)
13308 src = force_reg (mode, src);
13310 /* Emit the instruction. */
13312 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13313 if (reload_in_progress || code == NOT)
13315 /* Reload doesn't know about the flags register, and doesn't know that
13316 it doesn't want to clobber it. */
13317 gcc_assert (code == NOT);
13322 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13323 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13326 /* Fix up the destination if needed. */
13327 if (dst != operands[0])
13328 emit_move_insn (operands[0], dst);
13331 #define LEA_SEARCH_THRESHOLD 12
13333 /* Search backward for non-agu definition of register number REGNO1
13334 or register number REGNO2 in INSN's basic block until
13335 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13336 2. Reach BB boundary, or
13337 3. Reach agu definition.
13338 Returns the distance between the non-agu definition point and INSN.
13339 If no definition point, returns -1. */
13342 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13345 basic_block bb = BLOCK_FOR_INSN (insn);
13348 enum attr_type insn_type;
13350 if (insn != BB_HEAD (bb))
13352 rtx prev = PREV_INSN (insn);
13353 while (prev && distance < LEA_SEARCH_THRESHOLD)
13358 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13359 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13360 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13361 && (regno1 == DF_REF_REGNO (*def_rec)
13362 || regno2 == DF_REF_REGNO (*def_rec)))
13364 insn_type = get_attr_type (prev);
13365 if (insn_type != TYPE_LEA)
13369 if (prev == BB_HEAD (bb))
13371 prev = PREV_INSN (prev);
13375 if (distance < LEA_SEARCH_THRESHOLD)
13379 bool simple_loop = false;
13381 FOR_EACH_EDGE (e, ei, bb->preds)
13384 simple_loop = true;
13390 rtx prev = BB_END (bb);
13393 && distance < LEA_SEARCH_THRESHOLD)
13398 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13399 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13400 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13401 && (regno1 == DF_REF_REGNO (*def_rec)
13402 || regno2 == DF_REF_REGNO (*def_rec)))
13404 insn_type = get_attr_type (prev);
13405 if (insn_type != TYPE_LEA)
13409 prev = PREV_INSN (prev);
13417 /* get_attr_type may modify recog data. We want to make sure
13418 that recog data is valid for instruction INSN, on which
13419 distance_non_agu_define is called. INSN is unchanged here. */
13420 extract_insn_cached (insn);
13424 /* Return the distance between INSN and the next insn that uses
13425 register number REGNO0 in memory address. Return -1 if no such
13426 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13429 distance_agu_use (unsigned int regno0, rtx insn)
13431 basic_block bb = BLOCK_FOR_INSN (insn);
13436 if (insn != BB_END (bb))
13438 rtx next = NEXT_INSN (insn);
13439 while (next && distance < LEA_SEARCH_THRESHOLD)
13445 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13446 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13447 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13448 && regno0 == DF_REF_REGNO (*use_rec))
13450 /* Return DISTANCE if OP0 is used in memory
13451 address in NEXT. */
13455 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13456 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13457 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13458 && regno0 == DF_REF_REGNO (*def_rec))
13460 /* Return -1 if OP0 is set in NEXT. */
13464 if (next == BB_END (bb))
13466 next = NEXT_INSN (next);
13470 if (distance < LEA_SEARCH_THRESHOLD)
13474 bool simple_loop = false;
13476 FOR_EACH_EDGE (e, ei, bb->succs)
13479 simple_loop = true;
13485 rtx next = BB_HEAD (bb);
13488 && distance < LEA_SEARCH_THRESHOLD)
13494 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13495 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13496 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13497 && regno0 == DF_REF_REGNO (*use_rec))
13499 /* Return DISTANCE if OP0 is used in memory
13500 address in NEXT. */
13504 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13505 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13506 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13507 && regno0 == DF_REF_REGNO (*def_rec))
13509 /* Return -1 if OP0 is set in NEXT. */
13514 next = NEXT_INSN (next);
13522 /* Define this macro to tune LEA priority vs ADD, it take effect when
13523 there is a dilemma of choicing LEA or ADD
13524 Negative value: ADD is more preferred than LEA
13526 Positive value: LEA is more preferred than ADD*/
13527 #define IX86_LEA_PRIORITY 2
13529 /* Return true if it is ok to optimize an ADD operation to LEA
13530 operation to avoid flag register consumation. For the processors
13531 like ATOM, if the destination register of LEA holds an actual
13532 address which will be used soon, LEA is better and otherwise ADD
13536 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13537 rtx insn, rtx operands[])
13539 unsigned int regno0 = true_regnum (operands[0]);
13540 unsigned int regno1 = true_regnum (operands[1]);
13541 unsigned int regno2;
13543 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13544 return regno0 != regno1;
13546 regno2 = true_regnum (operands[2]);
13548 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13549 if (regno0 != regno1 && regno0 != regno2)
13553 int dist_define, dist_use;
13554 dist_define = distance_non_agu_define (regno1, regno2, insn);
13555 if (dist_define <= 0)
13558 /* If this insn has both backward non-agu dependence and forward
13559 agu dependence, the one with short distance take effect. */
13560 dist_use = distance_agu_use (regno0, insn);
13562 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13569 /* Return true if destination reg of SET_BODY is shift count of
13573 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13579 /* Retrieve destination of SET_BODY. */
13580 switch (GET_CODE (set_body))
13583 set_dest = SET_DEST (set_body);
13584 if (!set_dest || !REG_P (set_dest))
13588 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13589 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13597 /* Retrieve shift count of USE_BODY. */
13598 switch (GET_CODE (use_body))
13601 shift_rtx = XEXP (use_body, 1);
13604 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13605 if (ix86_dep_by_shift_count_body (set_body,
13606 XVECEXP (use_body, 0, i)))
13614 && (GET_CODE (shift_rtx) == ASHIFT
13615 || GET_CODE (shift_rtx) == LSHIFTRT
13616 || GET_CODE (shift_rtx) == ASHIFTRT
13617 || GET_CODE (shift_rtx) == ROTATE
13618 || GET_CODE (shift_rtx) == ROTATERT))
13620 rtx shift_count = XEXP (shift_rtx, 1);
13622 /* Return true if shift count is dest of SET_BODY. */
13623 if (REG_P (shift_count)
13624 && true_regnum (set_dest) == true_regnum (shift_count))
13631 /* Return true if destination reg of SET_INSN is shift count of
13635 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13637 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13638 PATTERN (use_insn));
13641 /* Return TRUE or FALSE depending on whether the unary operator meets the
13642 appropriate constraints. */
13645 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13646 enum machine_mode mode ATTRIBUTE_UNUSED,
13647 rtx operands[2] ATTRIBUTE_UNUSED)
13649 /* If one of operands is memory, source and destination must match. */
13650 if ((MEM_P (operands[0])
13651 || MEM_P (operands[1]))
13652 && ! rtx_equal_p (operands[0], operands[1]))
13657 /* Post-reload splitter for converting an SF or DFmode value in an
13658 SSE register into an unsigned SImode. */
13661 ix86_split_convert_uns_si_sse (rtx operands[])
13663 enum machine_mode vecmode;
13664 rtx value, large, zero_or_two31, input, two31, x;
13666 large = operands[1];
13667 zero_or_two31 = operands[2];
13668 input = operands[3];
13669 two31 = operands[4];
13670 vecmode = GET_MODE (large);
13671 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13673 /* Load up the value into the low element. We must ensure that the other
13674 elements are valid floats -- zero is the easiest such value. */
13677 if (vecmode == V4SFmode)
13678 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13680 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13684 input = gen_rtx_REG (vecmode, REGNO (input));
13685 emit_move_insn (value, CONST0_RTX (vecmode));
13686 if (vecmode == V4SFmode)
13687 emit_insn (gen_sse_movss (value, value, input));
13689 emit_insn (gen_sse2_movsd (value, value, input));
13692 emit_move_insn (large, two31);
13693 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13695 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13696 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13698 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13699 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13701 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13702 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13704 large = gen_rtx_REG (V4SImode, REGNO (large));
13705 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13707 x = gen_rtx_REG (V4SImode, REGNO (value));
13708 if (vecmode == V4SFmode)
13709 emit_insn (gen_sse2_cvttps2dq (x, value));
13711 emit_insn (gen_sse2_cvttpd2dq (x, value));
13714 emit_insn (gen_xorv4si3 (value, value, large));
13717 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13718 Expects the 64-bit DImode to be supplied in a pair of integral
13719 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13720 -mfpmath=sse, !optimize_size only. */
13723 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13725 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13726 rtx int_xmm, fp_xmm;
13727 rtx biases, exponents;
13730 int_xmm = gen_reg_rtx (V4SImode);
13731 if (TARGET_INTER_UNIT_MOVES)
13732 emit_insn (gen_movdi_to_sse (int_xmm, input));
13733 else if (TARGET_SSE_SPLIT_REGS)
13735 emit_clobber (int_xmm);
13736 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13740 x = gen_reg_rtx (V2DImode);
13741 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13742 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13745 x = gen_rtx_CONST_VECTOR (V4SImode,
13746 gen_rtvec (4, GEN_INT (0x43300000UL),
13747 GEN_INT (0x45300000UL),
13748 const0_rtx, const0_rtx));
13749 exponents = validize_mem (force_const_mem (V4SImode, x));
13751 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13752 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13754 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13755 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13756 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13757 (0x1.0p84 + double(fp_value_hi_xmm)).
13758 Note these exponents differ by 32. */
13760 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13762 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13763 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13764 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13765 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13766 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13767 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13768 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13769 biases = validize_mem (force_const_mem (V2DFmode, biases));
13770 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13772 /* Add the upper and lower DFmode values together. */
13774 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13777 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13778 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13779 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13782 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13785 /* Not used, but eases macroization of patterns. */
13787 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13788 rtx input ATTRIBUTE_UNUSED)
13790 gcc_unreachable ();
13793 /* Convert an unsigned SImode value into a DFmode. Only currently used
13794 for SSE, but applicable anywhere. */
13797 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13799 REAL_VALUE_TYPE TWO31r;
13802 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13803 NULL, 1, OPTAB_DIRECT);
13805 fp = gen_reg_rtx (DFmode);
13806 emit_insn (gen_floatsidf2 (fp, x));
13808 real_ldexp (&TWO31r, &dconst1, 31);
13809 x = const_double_from_real_value (TWO31r, DFmode);
13811 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13813 emit_move_insn (target, x);
13816 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13817 32-bit mode; otherwise we have a direct convert instruction. */
13820 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13822 REAL_VALUE_TYPE TWO32r;
13823 rtx fp_lo, fp_hi, x;
13825 fp_lo = gen_reg_rtx (DFmode);
13826 fp_hi = gen_reg_rtx (DFmode);
13828 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13830 real_ldexp (&TWO32r, &dconst1, 32);
13831 x = const_double_from_real_value (TWO32r, DFmode);
13832 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13834 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13836 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13839 emit_move_insn (target, x);
13842 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13843 For x86_32, -mfpmath=sse, !optimize_size only. */
13845 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13847 REAL_VALUE_TYPE ONE16r;
13848 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13850 real_ldexp (&ONE16r, &dconst1, 16);
13851 x = const_double_from_real_value (ONE16r, SFmode);
13852 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13853 NULL, 0, OPTAB_DIRECT);
13854 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13855 NULL, 0, OPTAB_DIRECT);
13856 fp_hi = gen_reg_rtx (SFmode);
13857 fp_lo = gen_reg_rtx (SFmode);
13858 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13859 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13860 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13862 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13864 if (!rtx_equal_p (target, fp_hi))
13865 emit_move_insn (target, fp_hi);
13868 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13869 then replicate the value for all elements of the vector
13873 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13880 v = gen_rtvec (4, value, value, value, value);
13881 return gen_rtx_CONST_VECTOR (V4SImode, v);
13885 v = gen_rtvec (2, value, value);
13886 return gen_rtx_CONST_VECTOR (V2DImode, v);
13890 v = gen_rtvec (4, value, value, value, value);
13892 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13893 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13894 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13898 v = gen_rtvec (2, value, value);
13900 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13901 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13904 gcc_unreachable ();
13908 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13909 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13910 for an SSE register. If VECT is true, then replicate the mask for
13911 all elements of the vector register. If INVERT is true, then create
13912 a mask excluding the sign bit. */
13915 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13917 enum machine_mode vec_mode, imode;
13918 HOST_WIDE_INT hi, lo;
13923 /* Find the sign bit, sign extended to 2*HWI. */
13929 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13930 lo = 0x80000000, hi = lo < 0;
13936 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13937 if (HOST_BITS_PER_WIDE_INT >= 64)
13938 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13940 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13945 vec_mode = VOIDmode;
13946 if (HOST_BITS_PER_WIDE_INT >= 64)
13949 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13956 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13960 lo = ~lo, hi = ~hi;
13966 mask = immed_double_const (lo, hi, imode);
13968 vec = gen_rtvec (2, v, mask);
13969 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13970 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13977 gcc_unreachable ();
13981 lo = ~lo, hi = ~hi;
13983 /* Force this value into the low part of a fp vector constant. */
13984 mask = immed_double_const (lo, hi, imode);
13985 mask = gen_lowpart (mode, mask);
13987 if (vec_mode == VOIDmode)
13988 return force_reg (mode, mask);
13990 v = ix86_build_const_vector (mode, vect, mask);
13991 return force_reg (vec_mode, v);
13994 /* Generate code for floating point ABS or NEG. */
13997 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14000 rtx mask, set, use, clob, dst, src;
14001 bool use_sse = false;
14002 bool vector_mode = VECTOR_MODE_P (mode);
14003 enum machine_mode elt_mode = mode;
14007 elt_mode = GET_MODE_INNER (mode);
14010 else if (mode == TFmode)
14012 else if (TARGET_SSE_MATH)
14013 use_sse = SSE_FLOAT_MODE_P (mode);
14015 /* NEG and ABS performed with SSE use bitwise mask operations.
14016 Create the appropriate mask now. */
14018 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14027 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14028 set = gen_rtx_SET (VOIDmode, dst, set);
14033 set = gen_rtx_fmt_e (code, mode, src);
14034 set = gen_rtx_SET (VOIDmode, dst, set);
14037 use = gen_rtx_USE (VOIDmode, mask);
14038 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14039 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14040 gen_rtvec (3, set, use, clob)));
14047 /* Expand a copysign operation. Special case operand 0 being a constant. */
14050 ix86_expand_copysign (rtx operands[])
14052 enum machine_mode mode;
14053 rtx dest, op0, op1, mask, nmask;
14055 dest = operands[0];
14059 mode = GET_MODE (dest);
14061 if (GET_CODE (op0) == CONST_DOUBLE)
14063 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14065 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14066 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14068 if (mode == SFmode || mode == DFmode)
14070 enum machine_mode vmode;
14072 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14074 if (op0 == CONST0_RTX (mode))
14075 op0 = CONST0_RTX (vmode);
14078 rtx v = ix86_build_const_vector (mode, false, op0);
14080 op0 = force_reg (vmode, v);
14083 else if (op0 != CONST0_RTX (mode))
14084 op0 = force_reg (mode, op0);
14086 mask = ix86_build_signbit_mask (mode, 0, 0);
14088 if (mode == SFmode)
14089 copysign_insn = gen_copysignsf3_const;
14090 else if (mode == DFmode)
14091 copysign_insn = gen_copysigndf3_const;
14093 copysign_insn = gen_copysigntf3_const;
14095 emit_insn (copysign_insn (dest, op0, op1, mask));
14099 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14101 nmask = ix86_build_signbit_mask (mode, 0, 1);
14102 mask = ix86_build_signbit_mask (mode, 0, 0);
14104 if (mode == SFmode)
14105 copysign_insn = gen_copysignsf3_var;
14106 else if (mode == DFmode)
14107 copysign_insn = gen_copysigndf3_var;
14109 copysign_insn = gen_copysigntf3_var;
14111 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14115 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14116 be a constant, and so has already been expanded into a vector constant. */
14119 ix86_split_copysign_const (rtx operands[])
14121 enum machine_mode mode, vmode;
14122 rtx dest, op0, op1, mask, x;
14124 dest = operands[0];
14127 mask = operands[3];
14129 mode = GET_MODE (dest);
14130 vmode = GET_MODE (mask);
14132 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14133 x = gen_rtx_AND (vmode, dest, mask);
14134 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14136 if (op0 != CONST0_RTX (vmode))
14138 x = gen_rtx_IOR (vmode, dest, op0);
14139 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14143 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14144 so we have to do two masks. */
14147 ix86_split_copysign_var (rtx operands[])
14149 enum machine_mode mode, vmode;
14150 rtx dest, scratch, op0, op1, mask, nmask, x;
14152 dest = operands[0];
14153 scratch = operands[1];
14156 nmask = operands[4];
14157 mask = operands[5];
14159 mode = GET_MODE (dest);
14160 vmode = GET_MODE (mask);
14162 if (rtx_equal_p (op0, op1))
14164 /* Shouldn't happen often (it's useless, obviously), but when it does
14165 we'd generate incorrect code if we continue below. */
14166 emit_move_insn (dest, op0);
14170 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14172 gcc_assert (REGNO (op1) == REGNO (scratch));
14174 x = gen_rtx_AND (vmode, scratch, mask);
14175 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14178 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14179 x = gen_rtx_NOT (vmode, dest);
14180 x = gen_rtx_AND (vmode, x, op0);
14181 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14185 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14187 x = gen_rtx_AND (vmode, scratch, mask);
14189 else /* alternative 2,4 */
14191 gcc_assert (REGNO (mask) == REGNO (scratch));
14192 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14193 x = gen_rtx_AND (vmode, scratch, op1);
14195 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14197 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14199 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14200 x = gen_rtx_AND (vmode, dest, nmask);
14202 else /* alternative 3,4 */
14204 gcc_assert (REGNO (nmask) == REGNO (dest));
14206 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14207 x = gen_rtx_AND (vmode, dest, op0);
14209 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14212 x = gen_rtx_IOR (vmode, dest, scratch);
14213 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14216 /* Return TRUE or FALSE depending on whether the first SET in INSN
14217 has source and destination with matching CC modes, and that the
14218 CC mode is at least as constrained as REQ_MODE. */
14221 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14224 enum machine_mode set_mode;
14226 set = PATTERN (insn);
14227 if (GET_CODE (set) == PARALLEL)
14228 set = XVECEXP (set, 0, 0);
14229 gcc_assert (GET_CODE (set) == SET);
14230 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14232 set_mode = GET_MODE (SET_DEST (set));
14236 if (req_mode != CCNOmode
14237 && (req_mode != CCmode
14238 || XEXP (SET_SRC (set), 1) != const0_rtx))
14242 if (req_mode == CCGCmode)
14246 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14250 if (req_mode == CCZmode)
14261 gcc_unreachable ();
14264 return (GET_MODE (SET_SRC (set)) == set_mode);
14267 /* Generate insn patterns to do an integer compare of OPERANDS. */
14270 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14272 enum machine_mode cmpmode;
14275 cmpmode = SELECT_CC_MODE (code, op0, op1);
14276 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14278 /* This is very simple, but making the interface the same as in the
14279 FP case makes the rest of the code easier. */
14280 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14281 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14283 /* Return the test that should be put into the flags user, i.e.
14284 the bcc, scc, or cmov instruction. */
14285 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14288 /* Figure out whether to use ordered or unordered fp comparisons.
14289 Return the appropriate mode to use. */
14292 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14294 /* ??? In order to make all comparisons reversible, we do all comparisons
14295 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14296 all forms trapping and nontrapping comparisons, we can make inequality
14297 comparisons trapping again, since it results in better code when using
14298 FCOM based compares. */
14299 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14303 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14305 enum machine_mode mode = GET_MODE (op0);
14307 if (SCALAR_FLOAT_MODE_P (mode))
14309 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14310 return ix86_fp_compare_mode (code);
14315 /* Only zero flag is needed. */
14316 case EQ: /* ZF=0 */
14317 case NE: /* ZF!=0 */
14319 /* Codes needing carry flag. */
14320 case GEU: /* CF=0 */
14321 case LTU: /* CF=1 */
14322 /* Detect overflow checks. They need just the carry flag. */
14323 if (GET_CODE (op0) == PLUS
14324 && rtx_equal_p (op1, XEXP (op0, 0)))
14328 case GTU: /* CF=0 & ZF=0 */
14329 case LEU: /* CF=1 | ZF=1 */
14330 /* Detect overflow checks. They need just the carry flag. */
14331 if (GET_CODE (op0) == MINUS
14332 && rtx_equal_p (op1, XEXP (op0, 0)))
14336 /* Codes possibly doable only with sign flag when
14337 comparing against zero. */
14338 case GE: /* SF=OF or SF=0 */
14339 case LT: /* SF<>OF or SF=1 */
14340 if (op1 == const0_rtx)
14343 /* For other cases Carry flag is not required. */
14345 /* Codes doable only with sign flag when comparing
14346 against zero, but we miss jump instruction for it
14347 so we need to use relational tests against overflow
14348 that thus needs to be zero. */
14349 case GT: /* ZF=0 & SF=OF */
14350 case LE: /* ZF=1 | SF<>OF */
14351 if (op1 == const0_rtx)
14355 /* strcmp pattern do (use flags) and combine may ask us for proper
14360 gcc_unreachable ();
14364 /* Return the fixed registers used for condition codes. */
14367 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14374 /* If two condition code modes are compatible, return a condition code
14375 mode which is compatible with both. Otherwise, return
14378 static enum machine_mode
14379 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14384 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14387 if ((m1 == CCGCmode && m2 == CCGOCmode)
14388 || (m1 == CCGOCmode && m2 == CCGCmode))
14394 gcc_unreachable ();
14424 /* These are only compatible with themselves, which we already
14431 /* Return a comparison we can do and that it is equivalent to
14432 swap_condition (code) apart possibly from orderedness.
14433 But, never change orderedness if TARGET_IEEE_FP, returning
14434 UNKNOWN in that case if necessary. */
14436 static enum rtx_code
14437 ix86_fp_swap_condition (enum rtx_code code)
14441 case GT: /* GTU - CF=0 & ZF=0 */
14442 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14443 case GE: /* GEU - CF=0 */
14444 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14445 case UNLT: /* LTU - CF=1 */
14446 return TARGET_IEEE_FP ? UNKNOWN : GT;
14447 case UNLE: /* LEU - CF=1 | ZF=1 */
14448 return TARGET_IEEE_FP ? UNKNOWN : GE;
14450 return swap_condition (code);
14454 /* Return cost of comparison CODE using the best strategy for performance.
14455 All following functions do use number of instructions as a cost metrics.
14456 In future this should be tweaked to compute bytes for optimize_size and
14457 take into account performance of various instructions on various CPUs. */
14460 ix86_fp_comparison_cost (enum rtx_code code)
14464 /* The cost of code using bit-twiddling on %ah. */
14481 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14485 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14488 gcc_unreachable ();
14491 switch (ix86_fp_comparison_strategy (code))
14493 case IX86_FPCMP_COMI:
14494 return arith_cost > 4 ? 3 : 2;
14495 case IX86_FPCMP_SAHF:
14496 return arith_cost > 4 ? 4 : 3;
14502 /* Return strategy to use for floating-point. We assume that fcomi is always
14503 preferrable where available, since that is also true when looking at size
14504 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14506 enum ix86_fpcmp_strategy
14507 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14509 /* Do fcomi/sahf based test when profitable. */
14512 return IX86_FPCMP_COMI;
14514 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14515 return IX86_FPCMP_SAHF;
14517 return IX86_FPCMP_ARITH;
14520 /* Swap, force into registers, or otherwise massage the two operands
14521 to a fp comparison. The operands are updated in place; the new
14522 comparison code is returned. */
14524 static enum rtx_code
14525 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14527 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14528 rtx op0 = *pop0, op1 = *pop1;
14529 enum machine_mode op_mode = GET_MODE (op0);
14530 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14532 /* All of the unordered compare instructions only work on registers.
14533 The same is true of the fcomi compare instructions. The XFmode
14534 compare instructions require registers except when comparing
14535 against zero or when converting operand 1 from fixed point to
14539 && (fpcmp_mode == CCFPUmode
14540 || (op_mode == XFmode
14541 && ! (standard_80387_constant_p (op0) == 1
14542 || standard_80387_constant_p (op1) == 1)
14543 && GET_CODE (op1) != FLOAT)
14544 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14546 op0 = force_reg (op_mode, op0);
14547 op1 = force_reg (op_mode, op1);
14551 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14552 things around if they appear profitable, otherwise force op0
14553 into a register. */
14555 if (standard_80387_constant_p (op0) == 0
14557 && ! (standard_80387_constant_p (op1) == 0
14560 enum rtx_code new_code = ix86_fp_swap_condition (code);
14561 if (new_code != UNKNOWN)
14564 tmp = op0, op0 = op1, op1 = tmp;
14570 op0 = force_reg (op_mode, op0);
14572 if (CONSTANT_P (op1))
14574 int tmp = standard_80387_constant_p (op1);
14576 op1 = validize_mem (force_const_mem (op_mode, op1));
14580 op1 = force_reg (op_mode, op1);
14583 op1 = force_reg (op_mode, op1);
14587 /* Try to rearrange the comparison to make it cheaper. */
14588 if (ix86_fp_comparison_cost (code)
14589 > ix86_fp_comparison_cost (swap_condition (code))
14590 && (REG_P (op1) || can_create_pseudo_p ()))
14593 tmp = op0, op0 = op1, op1 = tmp;
14594 code = swap_condition (code);
14596 op0 = force_reg (op_mode, op0);
14604 /* Convert comparison codes we use to represent FP comparison to integer
14605 code that will result in proper branch. Return UNKNOWN if no such code
14609 ix86_fp_compare_code_to_integer (enum rtx_code code)
14638 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14641 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14643 enum machine_mode fpcmp_mode, intcmp_mode;
14646 fpcmp_mode = ix86_fp_compare_mode (code);
14647 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14649 /* Do fcomi/sahf based test when profitable. */
14650 switch (ix86_fp_comparison_strategy (code))
14652 case IX86_FPCMP_COMI:
14653 intcmp_mode = fpcmp_mode;
14654 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14655 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14660 case IX86_FPCMP_SAHF:
14661 intcmp_mode = fpcmp_mode;
14662 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14663 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14667 scratch = gen_reg_rtx (HImode);
14668 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14669 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14672 case IX86_FPCMP_ARITH:
14673 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14674 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14675 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14677 scratch = gen_reg_rtx (HImode);
14678 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14680 /* In the unordered case, we have to check C2 for NaN's, which
14681 doesn't happen to work out to anything nice combination-wise.
14682 So do some bit twiddling on the value we've got in AH to come
14683 up with an appropriate set of condition codes. */
14685 intcmp_mode = CCNOmode;
14690 if (code == GT || !TARGET_IEEE_FP)
14692 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14697 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14698 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14699 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14700 intcmp_mode = CCmode;
14706 if (code == LT && TARGET_IEEE_FP)
14708 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14709 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14710 intcmp_mode = CCmode;
14715 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14721 if (code == GE || !TARGET_IEEE_FP)
14723 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14728 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14729 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14735 if (code == LE && TARGET_IEEE_FP)
14737 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14738 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14739 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14740 intcmp_mode = CCmode;
14745 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14751 if (code == EQ && TARGET_IEEE_FP)
14753 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14754 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14755 intcmp_mode = CCmode;
14760 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14766 if (code == NE && TARGET_IEEE_FP)
14768 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14769 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14775 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14781 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14785 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14790 gcc_unreachable ();
14798 /* Return the test that should be put into the flags user, i.e.
14799 the bcc, scc, or cmov instruction. */
14800 return gen_rtx_fmt_ee (code, VOIDmode,
14801 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14806 ix86_expand_compare (enum rtx_code code)
14809 op0 = ix86_compare_op0;
14810 op1 = ix86_compare_op1;
14812 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14813 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14815 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14817 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14818 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
14821 ret = ix86_expand_int_compare (code, op0, op1);
14827 ix86_expand_branch (enum rtx_code code, rtx label)
14831 switch (GET_MODE (ix86_compare_op0))
14840 tmp = ix86_expand_compare (code);
14841 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14842 gen_rtx_LABEL_REF (VOIDmode, label),
14844 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14851 /* Expand DImode branch into multiple compare+branch. */
14853 rtx lo[2], hi[2], label2;
14854 enum rtx_code code1, code2, code3;
14855 enum machine_mode submode;
14857 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14859 tmp = ix86_compare_op0;
14860 ix86_compare_op0 = ix86_compare_op1;
14861 ix86_compare_op1 = tmp;
14862 code = swap_condition (code);
14864 if (GET_MODE (ix86_compare_op0) == DImode)
14866 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14867 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14872 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14873 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14877 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14878 avoid two branches. This costs one extra insn, so disable when
14879 optimizing for size. */
14881 if ((code == EQ || code == NE)
14882 && (!optimize_insn_for_size_p ()
14883 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14888 if (hi[1] != const0_rtx)
14889 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14890 NULL_RTX, 0, OPTAB_WIDEN);
14893 if (lo[1] != const0_rtx)
14894 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14895 NULL_RTX, 0, OPTAB_WIDEN);
14897 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14898 NULL_RTX, 0, OPTAB_WIDEN);
14900 ix86_compare_op0 = tmp;
14901 ix86_compare_op1 = const0_rtx;
14902 ix86_expand_branch (code, label);
14906 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14907 op1 is a constant and the low word is zero, then we can just
14908 examine the high word. Similarly for low word -1 and
14909 less-or-equal-than or greater-than. */
14911 if (CONST_INT_P (hi[1]))
14914 case LT: case LTU: case GE: case GEU:
14915 if (lo[1] == const0_rtx)
14917 ix86_compare_op0 = hi[0];
14918 ix86_compare_op1 = hi[1];
14919 ix86_expand_branch (code, label);
14923 case LE: case LEU: case GT: case GTU:
14924 if (lo[1] == constm1_rtx)
14926 ix86_compare_op0 = hi[0];
14927 ix86_compare_op1 = hi[1];
14928 ix86_expand_branch (code, label);
14936 /* Otherwise, we need two or three jumps. */
14938 label2 = gen_label_rtx ();
14941 code2 = swap_condition (code);
14942 code3 = unsigned_condition (code);
14946 case LT: case GT: case LTU: case GTU:
14949 case LE: code1 = LT; code2 = GT; break;
14950 case GE: code1 = GT; code2 = LT; break;
14951 case LEU: code1 = LTU; code2 = GTU; break;
14952 case GEU: code1 = GTU; code2 = LTU; break;
14954 case EQ: code1 = UNKNOWN; code2 = NE; break;
14955 case NE: code2 = UNKNOWN; break;
14958 gcc_unreachable ();
14963 * if (hi(a) < hi(b)) goto true;
14964 * if (hi(a) > hi(b)) goto false;
14965 * if (lo(a) < lo(b)) goto true;
14969 ix86_compare_op0 = hi[0];
14970 ix86_compare_op1 = hi[1];
14972 if (code1 != UNKNOWN)
14973 ix86_expand_branch (code1, label);
14974 if (code2 != UNKNOWN)
14975 ix86_expand_branch (code2, label2);
14977 ix86_compare_op0 = lo[0];
14978 ix86_compare_op1 = lo[1];
14979 ix86_expand_branch (code3, label);
14981 if (code2 != UNKNOWN)
14982 emit_label (label2);
14987 /* If we have already emitted a compare insn, go straight to simple.
14988 ix86_expand_compare won't emit anything if ix86_compare_emitted
14990 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
14995 /* Split branch based on floating point condition. */
14997 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14998 rtx target1, rtx target2, rtx tmp, rtx pushed)
15003 if (target2 != pc_rtx)
15006 code = reverse_condition_maybe_unordered (code);
15011 condition = ix86_expand_fp_compare (code, op1, op2,
15014 /* Remove pushed operand from stack. */
15016 ix86_free_from_memory (GET_MODE (pushed));
15018 i = emit_jump_insn (gen_rtx_SET
15020 gen_rtx_IF_THEN_ELSE (VOIDmode,
15021 condition, target1, target2)));
15022 if (split_branch_probability >= 0)
15023 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15027 ix86_expand_setcc (enum rtx_code code, rtx dest)
15031 gcc_assert (GET_MODE (dest) == QImode);
15033 ret = ix86_expand_compare (code);
15034 PUT_MODE (ret, QImode);
15035 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15038 /* Expand comparison setting or clearing carry flag. Return true when
15039 successful and set pop for the operation. */
15041 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15043 enum machine_mode mode =
15044 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15046 /* Do not handle DImode compares that go through special path. */
15047 if (mode == (TARGET_64BIT ? TImode : DImode))
15050 if (SCALAR_FLOAT_MODE_P (mode))
15052 rtx compare_op, compare_seq;
15054 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15056 /* Shortcut: following common codes never translate
15057 into carry flag compares. */
15058 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15059 || code == ORDERED || code == UNORDERED)
15062 /* These comparisons require zero flag; swap operands so they won't. */
15063 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15064 && !TARGET_IEEE_FP)
15069 code = swap_condition (code);
15072 /* Try to expand the comparison and verify that we end up with
15073 carry flag based comparison. This fails to be true only when
15074 we decide to expand comparison using arithmetic that is not
15075 too common scenario. */
15077 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15078 compare_seq = get_insns ();
15081 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15082 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15083 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15085 code = GET_CODE (compare_op);
15087 if (code != LTU && code != GEU)
15090 emit_insn (compare_seq);
15095 if (!INTEGRAL_MODE_P (mode))
15104 /* Convert a==0 into (unsigned)a<1. */
15107 if (op1 != const0_rtx)
15110 code = (code == EQ ? LTU : GEU);
15113 /* Convert a>b into b<a or a>=b-1. */
15116 if (CONST_INT_P (op1))
15118 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15119 /* Bail out on overflow. We still can swap operands but that
15120 would force loading of the constant into register. */
15121 if (op1 == const0_rtx
15122 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15124 code = (code == GTU ? GEU : LTU);
15131 code = (code == GTU ? LTU : GEU);
15135 /* Convert a>=0 into (unsigned)a<0x80000000. */
15138 if (mode == DImode || op1 != const0_rtx)
15140 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15141 code = (code == LT ? GEU : LTU);
15145 if (mode == DImode || op1 != constm1_rtx)
15147 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15148 code = (code == LE ? GEU : LTU);
15154 /* Swapping operands may cause constant to appear as first operand. */
15155 if (!nonimmediate_operand (op0, VOIDmode))
15157 if (!can_create_pseudo_p ())
15159 op0 = force_reg (mode, op0);
15161 ix86_compare_op0 = op0;
15162 ix86_compare_op1 = op1;
15163 *pop = ix86_expand_compare (code);
15164 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15169 ix86_expand_int_movcc (rtx operands[])
15171 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15172 rtx compare_seq, compare_op;
15173 enum machine_mode mode = GET_MODE (operands[0]);
15174 bool sign_bit_compare_p = false;;
15177 ix86_compare_op0 = XEXP (operands[1], 0);
15178 ix86_compare_op1 = XEXP (operands[1], 1);
15179 compare_op = ix86_expand_compare (code);
15180 compare_seq = get_insns ();
15183 compare_code = GET_CODE (compare_op);
15185 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15186 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15187 sign_bit_compare_p = true;
15189 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15190 HImode insns, we'd be swallowed in word prefix ops. */
15192 if ((mode != HImode || TARGET_FAST_PREFIX)
15193 && (mode != (TARGET_64BIT ? TImode : DImode))
15194 && CONST_INT_P (operands[2])
15195 && CONST_INT_P (operands[3]))
15197 rtx out = operands[0];
15198 HOST_WIDE_INT ct = INTVAL (operands[2]);
15199 HOST_WIDE_INT cf = INTVAL (operands[3]);
15200 HOST_WIDE_INT diff;
15203 /* Sign bit compares are better done using shifts than we do by using
15205 if (sign_bit_compare_p
15206 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15207 ix86_compare_op1, &compare_op))
15209 /* Detect overlap between destination and compare sources. */
15212 if (!sign_bit_compare_p)
15214 bool fpcmp = false;
15216 compare_code = GET_CODE (compare_op);
15218 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15219 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15222 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15225 /* To simplify rest of code, restrict to the GEU case. */
15226 if (compare_code == LTU)
15228 HOST_WIDE_INT tmp = ct;
15231 compare_code = reverse_condition (compare_code);
15232 code = reverse_condition (code);
15237 PUT_CODE (compare_op,
15238 reverse_condition_maybe_unordered
15239 (GET_CODE (compare_op)));
15241 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15245 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15246 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15247 tmp = gen_reg_rtx (mode);
15249 if (mode == DImode)
15250 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15252 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15256 if (code == GT || code == GE)
15257 code = reverse_condition (code);
15260 HOST_WIDE_INT tmp = ct;
15265 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15266 ix86_compare_op1, VOIDmode, 0, -1);
15279 tmp = expand_simple_binop (mode, PLUS,
15281 copy_rtx (tmp), 1, OPTAB_DIRECT);
15292 tmp = expand_simple_binop (mode, IOR,
15294 copy_rtx (tmp), 1, OPTAB_DIRECT);
15296 else if (diff == -1 && ct)
15306 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15308 tmp = expand_simple_binop (mode, PLUS,
15309 copy_rtx (tmp), GEN_INT (cf),
15310 copy_rtx (tmp), 1, OPTAB_DIRECT);
15318 * andl cf - ct, dest
15328 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15331 tmp = expand_simple_binop (mode, AND,
15333 gen_int_mode (cf - ct, mode),
15334 copy_rtx (tmp), 1, OPTAB_DIRECT);
15336 tmp = expand_simple_binop (mode, PLUS,
15337 copy_rtx (tmp), GEN_INT (ct),
15338 copy_rtx (tmp), 1, OPTAB_DIRECT);
15341 if (!rtx_equal_p (tmp, out))
15342 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15344 return 1; /* DONE */
15349 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15352 tmp = ct, ct = cf, cf = tmp;
15355 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15357 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15359 /* We may be reversing unordered compare to normal compare, that
15360 is not valid in general (we may convert non-trapping condition
15361 to trapping one), however on i386 we currently emit all
15362 comparisons unordered. */
15363 compare_code = reverse_condition_maybe_unordered (compare_code);
15364 code = reverse_condition_maybe_unordered (code);
15368 compare_code = reverse_condition (compare_code);
15369 code = reverse_condition (code);
15373 compare_code = UNKNOWN;
15374 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15375 && CONST_INT_P (ix86_compare_op1))
15377 if (ix86_compare_op1 == const0_rtx
15378 && (code == LT || code == GE))
15379 compare_code = code;
15380 else if (ix86_compare_op1 == constm1_rtx)
15384 else if (code == GT)
15389 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15390 if (compare_code != UNKNOWN
15391 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15392 && (cf == -1 || ct == -1))
15394 /* If lea code below could be used, only optimize
15395 if it results in a 2 insn sequence. */
15397 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15398 || diff == 3 || diff == 5 || diff == 9)
15399 || (compare_code == LT && ct == -1)
15400 || (compare_code == GE && cf == -1))
15403 * notl op1 (if necessary)
15411 code = reverse_condition (code);
15414 out = emit_store_flag (out, code, ix86_compare_op0,
15415 ix86_compare_op1, VOIDmode, 0, -1);
15417 out = expand_simple_binop (mode, IOR,
15419 out, 1, OPTAB_DIRECT);
15420 if (out != operands[0])
15421 emit_move_insn (operands[0], out);
15423 return 1; /* DONE */
15428 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15429 || diff == 3 || diff == 5 || diff == 9)
15430 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15432 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15438 * lea cf(dest*(ct-cf)),dest
15442 * This also catches the degenerate setcc-only case.
15448 out = emit_store_flag (out, code, ix86_compare_op0,
15449 ix86_compare_op1, VOIDmode, 0, 1);
15452 /* On x86_64 the lea instruction operates on Pmode, so we need
15453 to get arithmetics done in proper mode to match. */
15455 tmp = copy_rtx (out);
15459 out1 = copy_rtx (out);
15460 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15464 tmp = gen_rtx_PLUS (mode, tmp, out1);
15470 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15473 if (!rtx_equal_p (tmp, out))
15476 out = force_operand (tmp, copy_rtx (out));
15478 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15480 if (!rtx_equal_p (out, operands[0]))
15481 emit_move_insn (operands[0], copy_rtx (out));
15483 return 1; /* DONE */
15487 * General case: Jumpful:
15488 * xorl dest,dest cmpl op1, op2
15489 * cmpl op1, op2 movl ct, dest
15490 * setcc dest jcc 1f
15491 * decl dest movl cf, dest
15492 * andl (cf-ct),dest 1:
15495 * Size 20. Size 14.
15497 * This is reasonably steep, but branch mispredict costs are
15498 * high on modern cpus, so consider failing only if optimizing
15502 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15503 && BRANCH_COST (optimize_insn_for_speed_p (),
15508 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15513 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15515 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15517 /* We may be reversing unordered compare to normal compare,
15518 that is not valid in general (we may convert non-trapping
15519 condition to trapping one), however on i386 we currently
15520 emit all comparisons unordered. */
15521 code = reverse_condition_maybe_unordered (code);
15525 code = reverse_condition (code);
15526 if (compare_code != UNKNOWN)
15527 compare_code = reverse_condition (compare_code);
15531 if (compare_code != UNKNOWN)
15533 /* notl op1 (if needed)
15538 For x < 0 (resp. x <= -1) there will be no notl,
15539 so if possible swap the constants to get rid of the
15541 True/false will be -1/0 while code below (store flag
15542 followed by decrement) is 0/-1, so the constants need
15543 to be exchanged once more. */
15545 if (compare_code == GE || !cf)
15547 code = reverse_condition (code);
15552 HOST_WIDE_INT tmp = cf;
15557 out = emit_store_flag (out, code, ix86_compare_op0,
15558 ix86_compare_op1, VOIDmode, 0, -1);
15562 out = emit_store_flag (out, code, ix86_compare_op0,
15563 ix86_compare_op1, VOIDmode, 0, 1);
15565 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15566 copy_rtx (out), 1, OPTAB_DIRECT);
15569 out = expand_simple_binop (mode, AND, copy_rtx (out),
15570 gen_int_mode (cf - ct, mode),
15571 copy_rtx (out), 1, OPTAB_DIRECT);
15573 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15574 copy_rtx (out), 1, OPTAB_DIRECT);
15575 if (!rtx_equal_p (out, operands[0]))
15576 emit_move_insn (operands[0], copy_rtx (out));
15578 return 1; /* DONE */
15582 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15584 /* Try a few things more with specific constants and a variable. */
15587 rtx var, orig_out, out, tmp;
15589 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15590 return 0; /* FAIL */
15592 /* If one of the two operands is an interesting constant, load a
15593 constant with the above and mask it in with a logical operation. */
15595 if (CONST_INT_P (operands[2]))
15598 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15599 operands[3] = constm1_rtx, op = and_optab;
15600 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15601 operands[3] = const0_rtx, op = ior_optab;
15603 return 0; /* FAIL */
15605 else if (CONST_INT_P (operands[3]))
15608 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15609 operands[2] = constm1_rtx, op = and_optab;
15610 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15611 operands[2] = const0_rtx, op = ior_optab;
15613 return 0; /* FAIL */
15616 return 0; /* FAIL */
15618 orig_out = operands[0];
15619 tmp = gen_reg_rtx (mode);
15622 /* Recurse to get the constant loaded. */
15623 if (ix86_expand_int_movcc (operands) == 0)
15624 return 0; /* FAIL */
15626 /* Mask in the interesting variable. */
15627 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15629 if (!rtx_equal_p (out, orig_out))
15630 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15632 return 1; /* DONE */
15636 * For comparison with above,
15646 if (! nonimmediate_operand (operands[2], mode))
15647 operands[2] = force_reg (mode, operands[2]);
15648 if (! nonimmediate_operand (operands[3], mode))
15649 operands[3] = force_reg (mode, operands[3]);
15651 if (! register_operand (operands[2], VOIDmode)
15653 || ! register_operand (operands[3], VOIDmode)))
15654 operands[2] = force_reg (mode, operands[2]);
15657 && ! register_operand (operands[3], VOIDmode))
15658 operands[3] = force_reg (mode, operands[3]);
15660 emit_insn (compare_seq);
15661 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15662 gen_rtx_IF_THEN_ELSE (mode,
15663 compare_op, operands[2],
15666 return 1; /* DONE */
15669 /* Swap, force into registers, or otherwise massage the two operands
15670 to an sse comparison with a mask result. Thus we differ a bit from
15671 ix86_prepare_fp_compare_args which expects to produce a flags result.
15673 The DEST operand exists to help determine whether to commute commutative
15674 operators. The POP0/POP1 operands are updated in place. The new
15675 comparison code is returned, or UNKNOWN if not implementable. */
15677 static enum rtx_code
15678 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15679 rtx *pop0, rtx *pop1)
15687 /* We have no LTGT as an operator. We could implement it with
15688 NE & ORDERED, but this requires an extra temporary. It's
15689 not clear that it's worth it. */
15696 /* These are supported directly. */
15703 /* For commutative operators, try to canonicalize the destination
15704 operand to be first in the comparison - this helps reload to
15705 avoid extra moves. */
15706 if (!dest || !rtx_equal_p (dest, *pop1))
15714 /* These are not supported directly. Swap the comparison operands
15715 to transform into something that is supported. */
15719 code = swap_condition (code);
15723 gcc_unreachable ();
15729 /* Detect conditional moves that exactly match min/max operational
15730 semantics. Note that this is IEEE safe, as long as we don't
15731 interchange the operands.
15733 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15734 and TRUE if the operation is successful and instructions are emitted. */
15737 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15738 rtx cmp_op1, rtx if_true, rtx if_false)
15740 enum machine_mode mode;
15746 else if (code == UNGE)
15749 if_true = if_false;
15755 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15757 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15762 mode = GET_MODE (dest);
15764 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15765 but MODE may be a vector mode and thus not appropriate. */
15766 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15768 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15771 if_true = force_reg (mode, if_true);
15772 v = gen_rtvec (2, if_true, if_false);
15773 tmp = gen_rtx_UNSPEC (mode, v, u);
15777 code = is_min ? SMIN : SMAX;
15778 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15781 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15785 /* Expand an sse vector comparison. Return the register with the result. */
15788 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15789 rtx op_true, rtx op_false)
15791 enum machine_mode mode = GET_MODE (dest);
15794 cmp_op0 = force_reg (mode, cmp_op0);
15795 if (!nonimmediate_operand (cmp_op1, mode))
15796 cmp_op1 = force_reg (mode, cmp_op1);
15799 || reg_overlap_mentioned_p (dest, op_true)
15800 || reg_overlap_mentioned_p (dest, op_false))
15801 dest = gen_reg_rtx (mode);
15803 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15804 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15809 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15810 operations. This is used for both scalar and vector conditional moves. */
15813 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15815 enum machine_mode mode = GET_MODE (dest);
15818 if (op_false == CONST0_RTX (mode))
15820 op_true = force_reg (mode, op_true);
15821 x = gen_rtx_AND (mode, cmp, op_true);
15822 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15824 else if (op_true == CONST0_RTX (mode))
15826 op_false = force_reg (mode, op_false);
15827 x = gen_rtx_NOT (mode, cmp);
15828 x = gen_rtx_AND (mode, x, op_false);
15829 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15833 op_true = force_reg (mode, op_true);
15834 op_false = force_reg (mode, op_false);
15836 t2 = gen_reg_rtx (mode);
15838 t3 = gen_reg_rtx (mode);
15842 x = gen_rtx_AND (mode, op_true, cmp);
15843 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15845 x = gen_rtx_NOT (mode, cmp);
15846 x = gen_rtx_AND (mode, x, op_false);
15847 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15849 x = gen_rtx_IOR (mode, t3, t2);
15850 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15854 /* Expand a floating-point conditional move. Return true if successful. */
15857 ix86_expand_fp_movcc (rtx operands[])
15859 enum machine_mode mode = GET_MODE (operands[0]);
15860 enum rtx_code code = GET_CODE (operands[1]);
15861 rtx tmp, compare_op;
15863 ix86_compare_op0 = XEXP (operands[1], 0);
15864 ix86_compare_op1 = XEXP (operands[1], 1);
15865 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15867 enum machine_mode cmode;
15869 /* Since we've no cmove for sse registers, don't force bad register
15870 allocation just to gain access to it. Deny movcc when the
15871 comparison mode doesn't match the move mode. */
15872 cmode = GET_MODE (ix86_compare_op0);
15873 if (cmode == VOIDmode)
15874 cmode = GET_MODE (ix86_compare_op1);
15878 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15880 &ix86_compare_op1);
15881 if (code == UNKNOWN)
15884 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15885 ix86_compare_op1, operands[2],
15889 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15890 ix86_compare_op1, operands[2], operands[3]);
15891 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15895 /* The floating point conditional move instructions don't directly
15896 support conditions resulting from a signed integer comparison. */
15898 compare_op = ix86_expand_compare (code);
15899 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15901 tmp = gen_reg_rtx (QImode);
15902 ix86_expand_setcc (code, tmp);
15904 ix86_compare_op0 = tmp;
15905 ix86_compare_op1 = const0_rtx;
15906 compare_op = ix86_expand_compare (code);
15909 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15910 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15911 operands[2], operands[3])));
15916 /* Expand a floating-point vector conditional move; a vcond operation
15917 rather than a movcc operation. */
15920 ix86_expand_fp_vcond (rtx operands[])
15922 enum rtx_code code = GET_CODE (operands[3]);
15925 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15926 &operands[4], &operands[5]);
15927 if (code == UNKNOWN)
15930 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15931 operands[5], operands[1], operands[2]))
15934 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15935 operands[1], operands[2]);
15936 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15940 /* Expand a signed/unsigned integral vector conditional move. */
15943 ix86_expand_int_vcond (rtx operands[])
15945 enum machine_mode mode = GET_MODE (operands[0]);
15946 enum rtx_code code = GET_CODE (operands[3]);
15947 bool negate = false;
15950 cop0 = operands[4];
15951 cop1 = operands[5];
15953 /* Canonicalize the comparison to EQ, GT, GTU. */
15964 code = reverse_condition (code);
15970 code = reverse_condition (code);
15976 code = swap_condition (code);
15977 x = cop0, cop0 = cop1, cop1 = x;
15981 gcc_unreachable ();
15984 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15985 if (mode == V2DImode)
15990 /* SSE4.1 supports EQ. */
15991 if (!TARGET_SSE4_1)
15997 /* SSE4.2 supports GT/GTU. */
15998 if (!TARGET_SSE4_2)
16003 gcc_unreachable ();
16007 /* Unsigned parallel compare is not supported by the hardware. Play some
16008 tricks to turn this into a signed comparison against 0. */
16011 cop0 = force_reg (mode, cop0);
16020 /* Perform a parallel modulo subtraction. */
16021 t1 = gen_reg_rtx (mode);
16022 emit_insn ((mode == V4SImode
16024 : gen_subv2di3) (t1, cop0, cop1));
16026 /* Extract the original sign bit of op0. */
16027 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16029 t2 = gen_reg_rtx (mode);
16030 emit_insn ((mode == V4SImode
16032 : gen_andv2di3) (t2, cop0, mask));
16034 /* XOR it back into the result of the subtraction. This results
16035 in the sign bit set iff we saw unsigned underflow. */
16036 x = gen_reg_rtx (mode);
16037 emit_insn ((mode == V4SImode
16039 : gen_xorv2di3) (x, t1, t2));
16047 /* Perform a parallel unsigned saturating subtraction. */
16048 x = gen_reg_rtx (mode);
16049 emit_insn (gen_rtx_SET (VOIDmode, x,
16050 gen_rtx_US_MINUS (mode, cop0, cop1)));
16057 gcc_unreachable ();
16061 cop1 = CONST0_RTX (mode);
16064 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16065 operands[1+negate], operands[2-negate]);
16067 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16068 operands[2-negate]);
16072 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16073 true if we should do zero extension, else sign extension. HIGH_P is
16074 true if we want the N/2 high elements, else the low elements. */
16077 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16079 enum machine_mode imode = GET_MODE (operands[1]);
16080 rtx (*unpack)(rtx, rtx, rtx);
16087 unpack = gen_vec_interleave_highv16qi;
16089 unpack = gen_vec_interleave_lowv16qi;
16093 unpack = gen_vec_interleave_highv8hi;
16095 unpack = gen_vec_interleave_lowv8hi;
16099 unpack = gen_vec_interleave_highv4si;
16101 unpack = gen_vec_interleave_lowv4si;
16104 gcc_unreachable ();
16107 dest = gen_lowpart (imode, operands[0]);
16110 se = force_reg (imode, CONST0_RTX (imode));
16112 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16113 operands[1], pc_rtx, pc_rtx);
16115 emit_insn (unpack (dest, operands[1], se));
16118 /* This function performs the same task as ix86_expand_sse_unpack,
16119 but with SSE4.1 instructions. */
16122 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16124 enum machine_mode imode = GET_MODE (operands[1]);
16125 rtx (*unpack)(rtx, rtx);
16132 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16134 unpack = gen_sse4_1_extendv8qiv8hi2;
16138 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16140 unpack = gen_sse4_1_extendv4hiv4si2;
16144 unpack = gen_sse4_1_zero_extendv2siv2di2;
16146 unpack = gen_sse4_1_extendv2siv2di2;
16149 gcc_unreachable ();
16152 dest = operands[0];
16155 /* Shift higher 8 bytes to lower 8 bytes. */
16156 src = gen_reg_rtx (imode);
16157 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16158 gen_lowpart (TImode, operands[1]),
16164 emit_insn (unpack (dest, src));
16167 /* Expand conditional increment or decrement using adb/sbb instructions.
16168 The default case using setcc followed by the conditional move can be
16169 done by generic code. */
16171 ix86_expand_int_addcc (rtx operands[])
16173 enum rtx_code code = GET_CODE (operands[1]);
16175 rtx val = const0_rtx;
16176 bool fpcmp = false;
16177 enum machine_mode mode = GET_MODE (operands[0]);
16179 ix86_compare_op0 = XEXP (operands[1], 0);
16180 ix86_compare_op1 = XEXP (operands[1], 1);
16181 if (operands[3] != const1_rtx
16182 && operands[3] != constm1_rtx)
16184 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16185 ix86_compare_op1, &compare_op))
16187 code = GET_CODE (compare_op);
16189 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16190 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16193 code = ix86_fp_compare_code_to_integer (code);
16200 PUT_CODE (compare_op,
16201 reverse_condition_maybe_unordered
16202 (GET_CODE (compare_op)));
16204 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16206 PUT_MODE (compare_op, mode);
16208 /* Construct either adc or sbb insn. */
16209 if ((code == LTU) == (operands[3] == constm1_rtx))
16211 switch (GET_MODE (operands[0]))
16214 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16217 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16220 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16223 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16226 gcc_unreachable ();
16231 switch (GET_MODE (operands[0]))
16234 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16237 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16240 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16243 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16246 gcc_unreachable ();
16249 return 1; /* DONE */
16253 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16254 works for floating pointer parameters and nonoffsetable memories.
16255 For pushes, it returns just stack offsets; the values will be saved
16256 in the right order. Maximally three parts are generated. */
16259 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16264 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16266 size = (GET_MODE_SIZE (mode) + 4) / 8;
16268 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16269 gcc_assert (size >= 2 && size <= 4);
16271 /* Optimize constant pool reference to immediates. This is used by fp
16272 moves, that force all constants to memory to allow combining. */
16273 if (MEM_P (operand) && MEM_READONLY_P (operand))
16275 rtx tmp = maybe_get_pool_constant (operand);
16280 if (MEM_P (operand) && !offsettable_memref_p (operand))
16282 /* The only non-offsetable memories we handle are pushes. */
16283 int ok = push_operand (operand, VOIDmode);
16287 operand = copy_rtx (operand);
16288 PUT_MODE (operand, Pmode);
16289 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16293 if (GET_CODE (operand) == CONST_VECTOR)
16295 enum machine_mode imode = int_mode_for_mode (mode);
16296 /* Caution: if we looked through a constant pool memory above,
16297 the operand may actually have a different mode now. That's
16298 ok, since we want to pun this all the way back to an integer. */
16299 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16300 gcc_assert (operand != NULL);
16306 if (mode == DImode)
16307 split_di (&operand, 1, &parts[0], &parts[1]);
16312 if (REG_P (operand))
16314 gcc_assert (reload_completed);
16315 for (i = 0; i < size; i++)
16316 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16318 else if (offsettable_memref_p (operand))
16320 operand = adjust_address (operand, SImode, 0);
16321 parts[0] = operand;
16322 for (i = 1; i < size; i++)
16323 parts[i] = adjust_address (operand, SImode, 4 * i);
16325 else if (GET_CODE (operand) == CONST_DOUBLE)
16330 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16334 real_to_target (l, &r, mode);
16335 parts[3] = gen_int_mode (l[3], SImode);
16336 parts[2] = gen_int_mode (l[2], SImode);
16339 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16340 parts[2] = gen_int_mode (l[2], SImode);
16343 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16346 gcc_unreachable ();
16348 parts[1] = gen_int_mode (l[1], SImode);
16349 parts[0] = gen_int_mode (l[0], SImode);
16352 gcc_unreachable ();
16357 if (mode == TImode)
16358 split_ti (&operand, 1, &parts[0], &parts[1]);
16359 if (mode == XFmode || mode == TFmode)
16361 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16362 if (REG_P (operand))
16364 gcc_assert (reload_completed);
16365 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16366 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16368 else if (offsettable_memref_p (operand))
16370 operand = adjust_address (operand, DImode, 0);
16371 parts[0] = operand;
16372 parts[1] = adjust_address (operand, upper_mode, 8);
16374 else if (GET_CODE (operand) == CONST_DOUBLE)
16379 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16380 real_to_target (l, &r, mode);
16382 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16383 if (HOST_BITS_PER_WIDE_INT >= 64)
16386 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16387 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16390 parts[0] = immed_double_const (l[0], l[1], DImode);
16392 if (upper_mode == SImode)
16393 parts[1] = gen_int_mode (l[2], SImode);
16394 else if (HOST_BITS_PER_WIDE_INT >= 64)
16397 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16398 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16401 parts[1] = immed_double_const (l[2], l[3], DImode);
16404 gcc_unreachable ();
16411 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16412 Return false when normal moves are needed; true when all required
16413 insns have been emitted. Operands 2-4 contain the input values
16414 int the correct order; operands 5-7 contain the output values. */
16417 ix86_split_long_move (rtx operands[])
16422 int collisions = 0;
16423 enum machine_mode mode = GET_MODE (operands[0]);
16424 bool collisionparts[4];
16426 /* The DFmode expanders may ask us to move double.
16427 For 64bit target this is single move. By hiding the fact
16428 here we simplify i386.md splitters. */
16429 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16431 /* Optimize constant pool reference to immediates. This is used by
16432 fp moves, that force all constants to memory to allow combining. */
16434 if (MEM_P (operands[1])
16435 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16436 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16437 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16438 if (push_operand (operands[0], VOIDmode))
16440 operands[0] = copy_rtx (operands[0]);
16441 PUT_MODE (operands[0], Pmode);
16444 operands[0] = gen_lowpart (DImode, operands[0]);
16445 operands[1] = gen_lowpart (DImode, operands[1]);
16446 emit_move_insn (operands[0], operands[1]);
16450 /* The only non-offsettable memory we handle is push. */
16451 if (push_operand (operands[0], VOIDmode))
16454 gcc_assert (!MEM_P (operands[0])
16455 || offsettable_memref_p (operands[0]));
16457 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16458 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16460 /* When emitting push, take care for source operands on the stack. */
16461 if (push && MEM_P (operands[1])
16462 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16464 rtx src_base = XEXP (part[1][nparts - 1], 0);
16466 /* Compensate for the stack decrement by 4. */
16467 if (!TARGET_64BIT && nparts == 3
16468 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16469 src_base = plus_constant (src_base, 4);
16471 /* src_base refers to the stack pointer and is
16472 automatically decreased by emitted push. */
16473 for (i = 0; i < nparts; i++)
16474 part[1][i] = change_address (part[1][i],
16475 GET_MODE (part[1][i]), src_base);
16478 /* We need to do copy in the right order in case an address register
16479 of the source overlaps the destination. */
16480 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16484 for (i = 0; i < nparts; i++)
16487 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16488 if (collisionparts[i])
16492 /* Collision in the middle part can be handled by reordering. */
16493 if (collisions == 1 && nparts == 3 && collisionparts [1])
16495 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16496 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16498 else if (collisions == 1
16500 && (collisionparts [1] || collisionparts [2]))
16502 if (collisionparts [1])
16504 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16505 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16509 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16510 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16514 /* If there are more collisions, we can't handle it by reordering.
16515 Do an lea to the last part and use only one colliding move. */
16516 else if (collisions > 1)
16522 base = part[0][nparts - 1];
16524 /* Handle the case when the last part isn't valid for lea.
16525 Happens in 64-bit mode storing the 12-byte XFmode. */
16526 if (GET_MODE (base) != Pmode)
16527 base = gen_rtx_REG (Pmode, REGNO (base));
16529 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16530 part[1][0] = replace_equiv_address (part[1][0], base);
16531 for (i = 1; i < nparts; i++)
16533 tmp = plus_constant (base, UNITS_PER_WORD * i);
16534 part[1][i] = replace_equiv_address (part[1][i], tmp);
16545 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16546 emit_insn (gen_addsi3 (stack_pointer_rtx,
16547 stack_pointer_rtx, GEN_INT (-4)));
16548 emit_move_insn (part[0][2], part[1][2]);
16550 else if (nparts == 4)
16552 emit_move_insn (part[0][3], part[1][3]);
16553 emit_move_insn (part[0][2], part[1][2]);
16558 /* In 64bit mode we don't have 32bit push available. In case this is
16559 register, it is OK - we will just use larger counterpart. We also
16560 retype memory - these comes from attempt to avoid REX prefix on
16561 moving of second half of TFmode value. */
16562 if (GET_MODE (part[1][1]) == SImode)
16564 switch (GET_CODE (part[1][1]))
16567 part[1][1] = adjust_address (part[1][1], DImode, 0);
16571 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16575 gcc_unreachable ();
16578 if (GET_MODE (part[1][0]) == SImode)
16579 part[1][0] = part[1][1];
16582 emit_move_insn (part[0][1], part[1][1]);
16583 emit_move_insn (part[0][0], part[1][0]);
16587 /* Choose correct order to not overwrite the source before it is copied. */
16588 if ((REG_P (part[0][0])
16589 && REG_P (part[1][1])
16590 && (REGNO (part[0][0]) == REGNO (part[1][1])
16592 && REGNO (part[0][0]) == REGNO (part[1][2]))
16594 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16596 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16598 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16600 operands[2 + i] = part[0][j];
16601 operands[6 + i] = part[1][j];
16606 for (i = 0; i < nparts; i++)
16608 operands[2 + i] = part[0][i];
16609 operands[6 + i] = part[1][i];
16613 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16614 if (optimize_insn_for_size_p ())
16616 for (j = 0; j < nparts - 1; j++)
16617 if (CONST_INT_P (operands[6 + j])
16618 && operands[6 + j] != const0_rtx
16619 && REG_P (operands[2 + j]))
16620 for (i = j; i < nparts - 1; i++)
16621 if (CONST_INT_P (operands[7 + i])
16622 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16623 operands[7 + i] = operands[2 + j];
16626 for (i = 0; i < nparts; i++)
16627 emit_move_insn (operands[2 + i], operands[6 + i]);
16632 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16633 left shift by a constant, either using a single shift or
16634 a sequence of add instructions. */
16637 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16641 emit_insn ((mode == DImode
16643 : gen_adddi3) (operand, operand, operand));
16645 else if (!optimize_insn_for_size_p ()
16646 && count * ix86_cost->add <= ix86_cost->shift_const)
16649 for (i=0; i<count; i++)
16651 emit_insn ((mode == DImode
16653 : gen_adddi3) (operand, operand, operand));
16657 emit_insn ((mode == DImode
16659 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16663 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16665 rtx low[2], high[2];
16667 const int single_width = mode == DImode ? 32 : 64;
16669 if (CONST_INT_P (operands[2]))
16671 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16672 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16674 if (count >= single_width)
16676 emit_move_insn (high[0], low[1]);
16677 emit_move_insn (low[0], const0_rtx);
16679 if (count > single_width)
16680 ix86_expand_ashl_const (high[0], count - single_width, mode);
16684 if (!rtx_equal_p (operands[0], operands[1]))
16685 emit_move_insn (operands[0], operands[1]);
16686 emit_insn ((mode == DImode
16688 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16689 ix86_expand_ashl_const (low[0], count, mode);
16694 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16696 if (operands[1] == const1_rtx)
16698 /* Assuming we've chosen a QImode capable registers, then 1 << N
16699 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16700 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16702 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16704 ix86_expand_clear (low[0]);
16705 ix86_expand_clear (high[0]);
16706 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16708 d = gen_lowpart (QImode, low[0]);
16709 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16710 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16711 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16713 d = gen_lowpart (QImode, high[0]);
16714 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16715 s = gen_rtx_NE (QImode, flags, const0_rtx);
16716 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16719 /* Otherwise, we can get the same results by manually performing
16720 a bit extract operation on bit 5/6, and then performing the two
16721 shifts. The two methods of getting 0/1 into low/high are exactly
16722 the same size. Avoiding the shift in the bit extract case helps
16723 pentium4 a bit; no one else seems to care much either way. */
16728 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16729 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16731 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16732 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16734 emit_insn ((mode == DImode
16736 : gen_lshrdi3) (high[0], high[0],
16737 GEN_INT (mode == DImode ? 5 : 6)));
16738 emit_insn ((mode == DImode
16740 : gen_anddi3) (high[0], high[0], const1_rtx));
16741 emit_move_insn (low[0], high[0]);
16742 emit_insn ((mode == DImode
16744 : gen_xordi3) (low[0], low[0], const1_rtx));
16747 emit_insn ((mode == DImode
16749 : gen_ashldi3) (low[0], low[0], operands[2]));
16750 emit_insn ((mode == DImode
16752 : gen_ashldi3) (high[0], high[0], operands[2]));
16756 if (operands[1] == constm1_rtx)
16758 /* For -1 << N, we can avoid the shld instruction, because we
16759 know that we're shifting 0...31/63 ones into a -1. */
16760 emit_move_insn (low[0], constm1_rtx);
16761 if (optimize_insn_for_size_p ())
16762 emit_move_insn (high[0], low[0]);
16764 emit_move_insn (high[0], constm1_rtx);
16768 if (!rtx_equal_p (operands[0], operands[1]))
16769 emit_move_insn (operands[0], operands[1]);
16771 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16772 emit_insn ((mode == DImode
16774 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16777 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16779 if (TARGET_CMOVE && scratch)
16781 ix86_expand_clear (scratch);
16782 emit_insn ((mode == DImode
16783 ? gen_x86_shift_adj_1
16784 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16788 emit_insn ((mode == DImode
16789 ? gen_x86_shift_adj_2
16790 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16794 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16796 rtx low[2], high[2];
16798 const int single_width = mode == DImode ? 32 : 64;
16800 if (CONST_INT_P (operands[2]))
16802 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16803 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16805 if (count == single_width * 2 - 1)
16807 emit_move_insn (high[0], high[1]);
16808 emit_insn ((mode == DImode
16810 : gen_ashrdi3) (high[0], high[0],
16811 GEN_INT (single_width - 1)));
16812 emit_move_insn (low[0], high[0]);
16815 else if (count >= single_width)
16817 emit_move_insn (low[0], high[1]);
16818 emit_move_insn (high[0], low[0]);
16819 emit_insn ((mode == DImode
16821 : gen_ashrdi3) (high[0], high[0],
16822 GEN_INT (single_width - 1)));
16823 if (count > single_width)
16824 emit_insn ((mode == DImode
16826 : gen_ashrdi3) (low[0], low[0],
16827 GEN_INT (count - single_width)));
16831 if (!rtx_equal_p (operands[0], operands[1]))
16832 emit_move_insn (operands[0], operands[1]);
16833 emit_insn ((mode == DImode
16835 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16836 emit_insn ((mode == DImode
16838 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16843 if (!rtx_equal_p (operands[0], operands[1]))
16844 emit_move_insn (operands[0], operands[1]);
16846 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16848 emit_insn ((mode == DImode
16850 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16851 emit_insn ((mode == DImode
16853 : gen_ashrdi3) (high[0], high[0], operands[2]));
16855 if (TARGET_CMOVE && scratch)
16857 emit_move_insn (scratch, high[0]);
16858 emit_insn ((mode == DImode
16860 : gen_ashrdi3) (scratch, scratch,
16861 GEN_INT (single_width - 1)));
16862 emit_insn ((mode == DImode
16863 ? gen_x86_shift_adj_1
16864 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16868 emit_insn ((mode == DImode
16869 ? gen_x86_shift_adj_3
16870 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16875 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16877 rtx low[2], high[2];
16879 const int single_width = mode == DImode ? 32 : 64;
16881 if (CONST_INT_P (operands[2]))
16883 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16884 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16886 if (count >= single_width)
16888 emit_move_insn (low[0], high[1]);
16889 ix86_expand_clear (high[0]);
16891 if (count > single_width)
16892 emit_insn ((mode == DImode
16894 : gen_lshrdi3) (low[0], low[0],
16895 GEN_INT (count - single_width)));
16899 if (!rtx_equal_p (operands[0], operands[1]))
16900 emit_move_insn (operands[0], operands[1]);
16901 emit_insn ((mode == DImode
16903 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16904 emit_insn ((mode == DImode
16906 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16911 if (!rtx_equal_p (operands[0], operands[1]))
16912 emit_move_insn (operands[0], operands[1]);
16914 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16916 emit_insn ((mode == DImode
16918 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16919 emit_insn ((mode == DImode
16921 : gen_lshrdi3) (high[0], high[0], operands[2]));
16923 /* Heh. By reversing the arguments, we can reuse this pattern. */
16924 if (TARGET_CMOVE && scratch)
16926 ix86_expand_clear (scratch);
16927 emit_insn ((mode == DImode
16928 ? gen_x86_shift_adj_1
16929 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16933 emit_insn ((mode == DImode
16934 ? gen_x86_shift_adj_2
16935 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16939 /* Predict just emitted jump instruction to be taken with probability PROB. */
16941 predict_jump (int prob)
16943 rtx insn = get_last_insn ();
16944 gcc_assert (JUMP_P (insn));
16945 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
16948 /* Helper function for the string operations below. Dest VARIABLE whether
16949 it is aligned to VALUE bytes. If true, jump to the label. */
16951 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16953 rtx label = gen_label_rtx ();
16954 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16955 if (GET_MODE (variable) == DImode)
16956 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16958 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16959 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16962 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16964 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16968 /* Adjust COUNTER by the VALUE. */
16970 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16972 if (GET_MODE (countreg) == DImode)
16973 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16975 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16978 /* Zero extend possibly SImode EXP to Pmode register. */
16980 ix86_zero_extend_to_Pmode (rtx exp)
16983 if (GET_MODE (exp) == VOIDmode)
16984 return force_reg (Pmode, exp);
16985 if (GET_MODE (exp) == Pmode)
16986 return copy_to_mode_reg (Pmode, exp);
16987 r = gen_reg_rtx (Pmode);
16988 emit_insn (gen_zero_extendsidi2 (r, exp));
16992 /* Divide COUNTREG by SCALE. */
16994 scale_counter (rtx countreg, int scale)
16997 rtx piece_size_mask;
17001 if (CONST_INT_P (countreg))
17002 return GEN_INT (INTVAL (countreg) / scale);
17003 gcc_assert (REG_P (countreg));
17005 piece_size_mask = GEN_INT (scale - 1);
17006 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17007 GEN_INT (exact_log2 (scale)),
17008 NULL, 1, OPTAB_DIRECT);
17012 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17013 DImode for constant loop counts. */
17015 static enum machine_mode
17016 counter_mode (rtx count_exp)
17018 if (GET_MODE (count_exp) != VOIDmode)
17019 return GET_MODE (count_exp);
17020 if (!CONST_INT_P (count_exp))
17022 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17027 /* When SRCPTR is non-NULL, output simple loop to move memory
17028 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17029 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17030 equivalent loop to set memory by VALUE (supposed to be in MODE).
17032 The size is rounded down to whole number of chunk size moved at once.
17033 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17037 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17038 rtx destptr, rtx srcptr, rtx value,
17039 rtx count, enum machine_mode mode, int unroll,
17042 rtx out_label, top_label, iter, tmp;
17043 enum machine_mode iter_mode = counter_mode (count);
17044 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17045 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17051 top_label = gen_label_rtx ();
17052 out_label = gen_label_rtx ();
17053 iter = gen_reg_rtx (iter_mode);
17055 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17056 NULL, 1, OPTAB_DIRECT);
17057 /* Those two should combine. */
17058 if (piece_size == const1_rtx)
17060 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17062 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17064 emit_move_insn (iter, const0_rtx);
17066 emit_label (top_label);
17068 tmp = convert_modes (Pmode, iter_mode, iter, true);
17069 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17070 destmem = change_address (destmem, mode, x_addr);
17074 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17075 srcmem = change_address (srcmem, mode, y_addr);
17077 /* When unrolling for chips that reorder memory reads and writes,
17078 we can save registers by using single temporary.
17079 Also using 4 temporaries is overkill in 32bit mode. */
17080 if (!TARGET_64BIT && 0)
17082 for (i = 0; i < unroll; i++)
17087 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17089 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17091 emit_move_insn (destmem, srcmem);
17097 gcc_assert (unroll <= 4);
17098 for (i = 0; i < unroll; i++)
17100 tmpreg[i] = gen_reg_rtx (mode);
17104 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17106 emit_move_insn (tmpreg[i], srcmem);
17108 for (i = 0; i < unroll; i++)
17113 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17115 emit_move_insn (destmem, tmpreg[i]);
17120 for (i = 0; i < unroll; i++)
17124 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17125 emit_move_insn (destmem, value);
17128 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17129 true, OPTAB_LIB_WIDEN);
17131 emit_move_insn (iter, tmp);
17133 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17135 if (expected_size != -1)
17137 expected_size /= GET_MODE_SIZE (mode) * unroll;
17138 if (expected_size == 0)
17140 else if (expected_size > REG_BR_PROB_BASE)
17141 predict_jump (REG_BR_PROB_BASE - 1);
17143 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17146 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17147 iter = ix86_zero_extend_to_Pmode (iter);
17148 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17149 true, OPTAB_LIB_WIDEN);
17150 if (tmp != destptr)
17151 emit_move_insn (destptr, tmp);
17154 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17155 true, OPTAB_LIB_WIDEN);
17157 emit_move_insn (srcptr, tmp);
17159 emit_label (out_label);
17162 /* Output "rep; mov" instruction.
17163 Arguments have same meaning as for previous function */
17165 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17166 rtx destptr, rtx srcptr,
17168 enum machine_mode mode)
17174 /* If the size is known, it is shorter to use rep movs. */
17175 if (mode == QImode && CONST_INT_P (count)
17176 && !(INTVAL (count) & 3))
17179 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17180 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17181 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17182 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17183 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17184 if (mode != QImode)
17186 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17187 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17188 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17189 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17190 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17191 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17195 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17196 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17198 if (CONST_INT_P (count))
17200 count = GEN_INT (INTVAL (count)
17201 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17202 destmem = shallow_copy_rtx (destmem);
17203 srcmem = shallow_copy_rtx (srcmem);
17204 set_mem_size (destmem, count);
17205 set_mem_size (srcmem, count);
17209 if (MEM_SIZE (destmem))
17210 set_mem_size (destmem, NULL_RTX);
17211 if (MEM_SIZE (srcmem))
17212 set_mem_size (srcmem, NULL_RTX);
17214 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17218 /* Output "rep; stos" instruction.
17219 Arguments have same meaning as for previous function */
17221 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17222 rtx count, enum machine_mode mode,
17228 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17229 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17230 value = force_reg (mode, gen_lowpart (mode, value));
17231 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17232 if (mode != QImode)
17234 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17235 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17236 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17239 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17240 if (orig_value == const0_rtx && CONST_INT_P (count))
17242 count = GEN_INT (INTVAL (count)
17243 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17244 destmem = shallow_copy_rtx (destmem);
17245 set_mem_size (destmem, count);
17247 else if (MEM_SIZE (destmem))
17248 set_mem_size (destmem, NULL_RTX);
17249 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17253 emit_strmov (rtx destmem, rtx srcmem,
17254 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17256 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17257 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17258 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17261 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17263 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17264 rtx destptr, rtx srcptr, rtx count, int max_size)
17267 if (CONST_INT_P (count))
17269 HOST_WIDE_INT countval = INTVAL (count);
17272 if ((countval & 0x10) && max_size > 16)
17276 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17277 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17280 gcc_unreachable ();
17283 if ((countval & 0x08) && max_size > 8)
17286 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17289 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17290 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17294 if ((countval & 0x04) && max_size > 4)
17296 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17299 if ((countval & 0x02) && max_size > 2)
17301 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17304 if ((countval & 0x01) && max_size > 1)
17306 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17313 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17314 count, 1, OPTAB_DIRECT);
17315 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17316 count, QImode, 1, 4);
17320 /* When there are stringops, we can cheaply increase dest and src pointers.
17321 Otherwise we save code size by maintaining offset (zero is readily
17322 available from preceding rep operation) and using x86 addressing modes.
17324 if (TARGET_SINGLE_STRINGOP)
17328 rtx label = ix86_expand_aligntest (count, 4, true);
17329 src = change_address (srcmem, SImode, srcptr);
17330 dest = change_address (destmem, SImode, destptr);
17331 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17332 emit_label (label);
17333 LABEL_NUSES (label) = 1;
17337 rtx label = ix86_expand_aligntest (count, 2, true);
17338 src = change_address (srcmem, HImode, srcptr);
17339 dest = change_address (destmem, HImode, destptr);
17340 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17341 emit_label (label);
17342 LABEL_NUSES (label) = 1;
17346 rtx label = ix86_expand_aligntest (count, 1, true);
17347 src = change_address (srcmem, QImode, srcptr);
17348 dest = change_address (destmem, QImode, destptr);
17349 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17350 emit_label (label);
17351 LABEL_NUSES (label) = 1;
17356 rtx offset = force_reg (Pmode, const0_rtx);
17361 rtx label = ix86_expand_aligntest (count, 4, true);
17362 src = change_address (srcmem, SImode, srcptr);
17363 dest = change_address (destmem, SImode, destptr);
17364 emit_move_insn (dest, src);
17365 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17366 true, OPTAB_LIB_WIDEN);
17368 emit_move_insn (offset, tmp);
17369 emit_label (label);
17370 LABEL_NUSES (label) = 1;
17374 rtx label = ix86_expand_aligntest (count, 2, true);
17375 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17376 src = change_address (srcmem, HImode, tmp);
17377 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17378 dest = change_address (destmem, HImode, tmp);
17379 emit_move_insn (dest, src);
17380 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17381 true, OPTAB_LIB_WIDEN);
17383 emit_move_insn (offset, tmp);
17384 emit_label (label);
17385 LABEL_NUSES (label) = 1;
17389 rtx label = ix86_expand_aligntest (count, 1, true);
17390 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17391 src = change_address (srcmem, QImode, tmp);
17392 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17393 dest = change_address (destmem, QImode, tmp);
17394 emit_move_insn (dest, src);
17395 emit_label (label);
17396 LABEL_NUSES (label) = 1;
17401 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17403 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17404 rtx count, int max_size)
17407 expand_simple_binop (counter_mode (count), AND, count,
17408 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17409 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17410 gen_lowpart (QImode, value), count, QImode,
17414 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17416 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17420 if (CONST_INT_P (count))
17422 HOST_WIDE_INT countval = INTVAL (count);
17425 if ((countval & 0x10) && max_size > 16)
17429 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17430 emit_insn (gen_strset (destptr, dest, value));
17431 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17432 emit_insn (gen_strset (destptr, dest, value));
17435 gcc_unreachable ();
17438 if ((countval & 0x08) && max_size > 8)
17442 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17443 emit_insn (gen_strset (destptr, dest, value));
17447 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17448 emit_insn (gen_strset (destptr, dest, value));
17449 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17450 emit_insn (gen_strset (destptr, dest, value));
17454 if ((countval & 0x04) && max_size > 4)
17456 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17457 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17460 if ((countval & 0x02) && max_size > 2)
17462 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17463 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17466 if ((countval & 0x01) && max_size > 1)
17468 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17469 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17476 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17481 rtx label = ix86_expand_aligntest (count, 16, true);
17484 dest = change_address (destmem, DImode, destptr);
17485 emit_insn (gen_strset (destptr, dest, value));
17486 emit_insn (gen_strset (destptr, dest, value));
17490 dest = change_address (destmem, SImode, destptr);
17491 emit_insn (gen_strset (destptr, dest, value));
17492 emit_insn (gen_strset (destptr, dest, value));
17493 emit_insn (gen_strset (destptr, dest, value));
17494 emit_insn (gen_strset (destptr, dest, value));
17496 emit_label (label);
17497 LABEL_NUSES (label) = 1;
17501 rtx label = ix86_expand_aligntest (count, 8, true);
17504 dest = change_address (destmem, DImode, destptr);
17505 emit_insn (gen_strset (destptr, dest, value));
17509 dest = change_address (destmem, SImode, destptr);
17510 emit_insn (gen_strset (destptr, dest, value));
17511 emit_insn (gen_strset (destptr, dest, value));
17513 emit_label (label);
17514 LABEL_NUSES (label) = 1;
17518 rtx label = ix86_expand_aligntest (count, 4, true);
17519 dest = change_address (destmem, SImode, destptr);
17520 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17521 emit_label (label);
17522 LABEL_NUSES (label) = 1;
17526 rtx label = ix86_expand_aligntest (count, 2, true);
17527 dest = change_address (destmem, HImode, destptr);
17528 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17529 emit_label (label);
17530 LABEL_NUSES (label) = 1;
17534 rtx label = ix86_expand_aligntest (count, 1, true);
17535 dest = change_address (destmem, QImode, destptr);
17536 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17537 emit_label (label);
17538 LABEL_NUSES (label) = 1;
17542 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17543 DESIRED_ALIGNMENT. */
17545 expand_movmem_prologue (rtx destmem, rtx srcmem,
17546 rtx destptr, rtx srcptr, rtx count,
17547 int align, int desired_alignment)
17549 if (align <= 1 && desired_alignment > 1)
17551 rtx label = ix86_expand_aligntest (destptr, 1, false);
17552 srcmem = change_address (srcmem, QImode, srcptr);
17553 destmem = change_address (destmem, QImode, destptr);
17554 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17555 ix86_adjust_counter (count, 1);
17556 emit_label (label);
17557 LABEL_NUSES (label) = 1;
17559 if (align <= 2 && desired_alignment > 2)
17561 rtx label = ix86_expand_aligntest (destptr, 2, false);
17562 srcmem = change_address (srcmem, HImode, srcptr);
17563 destmem = change_address (destmem, HImode, destptr);
17564 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17565 ix86_adjust_counter (count, 2);
17566 emit_label (label);
17567 LABEL_NUSES (label) = 1;
17569 if (align <= 4 && desired_alignment > 4)
17571 rtx label = ix86_expand_aligntest (destptr, 4, false);
17572 srcmem = change_address (srcmem, SImode, srcptr);
17573 destmem = change_address (destmem, SImode, destptr);
17574 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17575 ix86_adjust_counter (count, 4);
17576 emit_label (label);
17577 LABEL_NUSES (label) = 1;
17579 gcc_assert (desired_alignment <= 8);
17582 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17583 ALIGN_BYTES is how many bytes need to be copied. */
17585 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17586 int desired_align, int align_bytes)
17589 rtx src_size, dst_size;
17591 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17592 if (src_align_bytes >= 0)
17593 src_align_bytes = desired_align - src_align_bytes;
17594 src_size = MEM_SIZE (src);
17595 dst_size = MEM_SIZE (dst);
17596 if (align_bytes & 1)
17598 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17599 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17601 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17603 if (align_bytes & 2)
17605 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17606 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17607 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17608 set_mem_align (dst, 2 * BITS_PER_UNIT);
17609 if (src_align_bytes >= 0
17610 && (src_align_bytes & 1) == (align_bytes & 1)
17611 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17612 set_mem_align (src, 2 * BITS_PER_UNIT);
17614 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17616 if (align_bytes & 4)
17618 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17619 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17620 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17621 set_mem_align (dst, 4 * BITS_PER_UNIT);
17622 if (src_align_bytes >= 0)
17624 unsigned int src_align = 0;
17625 if ((src_align_bytes & 3) == (align_bytes & 3))
17627 else if ((src_align_bytes & 1) == (align_bytes & 1))
17629 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17630 set_mem_align (src, src_align * BITS_PER_UNIT);
17633 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17635 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17636 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17637 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17638 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17639 if (src_align_bytes >= 0)
17641 unsigned int src_align = 0;
17642 if ((src_align_bytes & 7) == (align_bytes & 7))
17644 else if ((src_align_bytes & 3) == (align_bytes & 3))
17646 else if ((src_align_bytes & 1) == (align_bytes & 1))
17648 if (src_align > (unsigned int) desired_align)
17649 src_align = desired_align;
17650 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17651 set_mem_align (src, src_align * BITS_PER_UNIT);
17654 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17656 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17661 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17662 DESIRED_ALIGNMENT. */
17664 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17665 int align, int desired_alignment)
17667 if (align <= 1 && desired_alignment > 1)
17669 rtx label = ix86_expand_aligntest (destptr, 1, false);
17670 destmem = change_address (destmem, QImode, destptr);
17671 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17672 ix86_adjust_counter (count, 1);
17673 emit_label (label);
17674 LABEL_NUSES (label) = 1;
17676 if (align <= 2 && desired_alignment > 2)
17678 rtx label = ix86_expand_aligntest (destptr, 2, false);
17679 destmem = change_address (destmem, HImode, destptr);
17680 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17681 ix86_adjust_counter (count, 2);
17682 emit_label (label);
17683 LABEL_NUSES (label) = 1;
17685 if (align <= 4 && desired_alignment > 4)
17687 rtx label = ix86_expand_aligntest (destptr, 4, false);
17688 destmem = change_address (destmem, SImode, destptr);
17689 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17690 ix86_adjust_counter (count, 4);
17691 emit_label (label);
17692 LABEL_NUSES (label) = 1;
17694 gcc_assert (desired_alignment <= 8);
17697 /* Set enough from DST to align DST known to by aligned by ALIGN to
17698 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17700 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17701 int desired_align, int align_bytes)
17704 rtx dst_size = MEM_SIZE (dst);
17705 if (align_bytes & 1)
17707 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17709 emit_insn (gen_strset (destreg, dst,
17710 gen_lowpart (QImode, value)));
17712 if (align_bytes & 2)
17714 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17715 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17716 set_mem_align (dst, 2 * BITS_PER_UNIT);
17718 emit_insn (gen_strset (destreg, dst,
17719 gen_lowpart (HImode, value)));
17721 if (align_bytes & 4)
17723 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17724 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17725 set_mem_align (dst, 4 * BITS_PER_UNIT);
17727 emit_insn (gen_strset (destreg, dst,
17728 gen_lowpart (SImode, value)));
17730 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17731 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17732 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17734 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17738 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17739 static enum stringop_alg
17740 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17741 int *dynamic_check)
17743 const struct stringop_algs * algs;
17744 bool optimize_for_speed;
17745 /* Algorithms using the rep prefix want at least edi and ecx;
17746 additionally, memset wants eax and memcpy wants esi. Don't
17747 consider such algorithms if the user has appropriated those
17748 registers for their own purposes. */
17749 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17751 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17753 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17754 || (alg != rep_prefix_1_byte \
17755 && alg != rep_prefix_4_byte \
17756 && alg != rep_prefix_8_byte))
17757 const struct processor_costs *cost;
17759 /* Even if the string operation call is cold, we still might spend a lot
17760 of time processing large blocks. */
17761 if (optimize_function_for_size_p (cfun)
17762 || (optimize_insn_for_size_p ()
17763 && expected_size != -1 && expected_size < 256))
17764 optimize_for_speed = false;
17766 optimize_for_speed = true;
17768 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17770 *dynamic_check = -1;
17772 algs = &cost->memset[TARGET_64BIT != 0];
17774 algs = &cost->memcpy[TARGET_64BIT != 0];
17775 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17776 return stringop_alg;
17777 /* rep; movq or rep; movl is the smallest variant. */
17778 else if (!optimize_for_speed)
17780 if (!count || (count & 3))
17781 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17783 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17785 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17787 else if (expected_size != -1 && expected_size < 4)
17788 return loop_1_byte;
17789 else if (expected_size != -1)
17792 enum stringop_alg alg = libcall;
17793 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17795 /* We get here if the algorithms that were not libcall-based
17796 were rep-prefix based and we are unable to use rep prefixes
17797 based on global register usage. Break out of the loop and
17798 use the heuristic below. */
17799 if (algs->size[i].max == 0)
17801 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17803 enum stringop_alg candidate = algs->size[i].alg;
17805 if (candidate != libcall && ALG_USABLE_P (candidate))
17807 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17808 last non-libcall inline algorithm. */
17809 if (TARGET_INLINE_ALL_STRINGOPS)
17811 /* When the current size is best to be copied by a libcall,
17812 but we are still forced to inline, run the heuristic below
17813 that will pick code for medium sized blocks. */
17814 if (alg != libcall)
17818 else if (ALG_USABLE_P (candidate))
17822 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17824 /* When asked to inline the call anyway, try to pick meaningful choice.
17825 We look for maximal size of block that is faster to copy by hand and
17826 take blocks of at most of that size guessing that average size will
17827 be roughly half of the block.
17829 If this turns out to be bad, we might simply specify the preferred
17830 choice in ix86_costs. */
17831 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17832 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17835 enum stringop_alg alg;
17837 bool any_alg_usable_p = true;
17839 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17841 enum stringop_alg candidate = algs->size[i].alg;
17842 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17844 if (candidate != libcall && candidate
17845 && ALG_USABLE_P (candidate))
17846 max = algs->size[i].max;
17848 /* If there aren't any usable algorithms, then recursing on
17849 smaller sizes isn't going to find anything. Just return the
17850 simple byte-at-a-time copy loop. */
17851 if (!any_alg_usable_p)
17853 /* Pick something reasonable. */
17854 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17855 *dynamic_check = 128;
17856 return loop_1_byte;
17860 alg = decide_alg (count, max / 2, memset, dynamic_check);
17861 gcc_assert (*dynamic_check == -1);
17862 gcc_assert (alg != libcall);
17863 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17864 *dynamic_check = max;
17867 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17868 #undef ALG_USABLE_P
17871 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17872 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17874 decide_alignment (int align,
17875 enum stringop_alg alg,
17878 int desired_align = 0;
17882 gcc_unreachable ();
17884 case unrolled_loop:
17885 desired_align = GET_MODE_SIZE (Pmode);
17887 case rep_prefix_8_byte:
17890 case rep_prefix_4_byte:
17891 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17892 copying whole cacheline at once. */
17893 if (TARGET_PENTIUMPRO)
17898 case rep_prefix_1_byte:
17899 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17900 copying whole cacheline at once. */
17901 if (TARGET_PENTIUMPRO)
17915 if (desired_align < align)
17916 desired_align = align;
17917 if (expected_size != -1 && expected_size < 4)
17918 desired_align = align;
17919 return desired_align;
17922 /* Return the smallest power of 2 greater than VAL. */
17924 smallest_pow2_greater_than (int val)
17932 /* Expand string move (memcpy) operation. Use i386 string operations when
17933 profitable. expand_setmem contains similar code. The code depends upon
17934 architecture, block size and alignment, but always has the same
17937 1) Prologue guard: Conditional that jumps up to epilogues for small
17938 blocks that can be handled by epilogue alone. This is faster but
17939 also needed for correctness, since prologue assume the block is larger
17940 than the desired alignment.
17942 Optional dynamic check for size and libcall for large
17943 blocks is emitted here too, with -minline-stringops-dynamically.
17945 2) Prologue: copy first few bytes in order to get destination aligned
17946 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17947 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17948 We emit either a jump tree on power of two sized blocks, or a byte loop.
17950 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17951 with specified algorithm.
17953 4) Epilogue: code copying tail of the block that is too small to be
17954 handled by main body (or up to size guarded by prologue guard). */
17957 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17958 rtx expected_align_exp, rtx expected_size_exp)
17964 rtx jump_around_label = NULL;
17965 HOST_WIDE_INT align = 1;
17966 unsigned HOST_WIDE_INT count = 0;
17967 HOST_WIDE_INT expected_size = -1;
17968 int size_needed = 0, epilogue_size_needed;
17969 int desired_align = 0, align_bytes = 0;
17970 enum stringop_alg alg;
17972 bool need_zero_guard = false;
17974 if (CONST_INT_P (align_exp))
17975 align = INTVAL (align_exp);
17976 /* i386 can do misaligned access on reasonably increased cost. */
17977 if (CONST_INT_P (expected_align_exp)
17978 && INTVAL (expected_align_exp) > align)
17979 align = INTVAL (expected_align_exp);
17980 /* ALIGN is the minimum of destination and source alignment, but we care here
17981 just about destination alignment. */
17982 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17983 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17985 if (CONST_INT_P (count_exp))
17986 count = expected_size = INTVAL (count_exp);
17987 if (CONST_INT_P (expected_size_exp) && count == 0)
17988 expected_size = INTVAL (expected_size_exp);
17990 /* Make sure we don't need to care about overflow later on. */
17991 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17994 /* Step 0: Decide on preferred algorithm, desired alignment and
17995 size of chunks to be copied by main loop. */
17997 alg = decide_alg (count, expected_size, false, &dynamic_check);
17998 desired_align = decide_alignment (align, alg, expected_size);
18000 if (!TARGET_ALIGN_STRINGOPS)
18001 align = desired_align;
18003 if (alg == libcall)
18005 gcc_assert (alg != no_stringop);
18007 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18008 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18009 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18014 gcc_unreachable ();
18016 need_zero_guard = true;
18017 size_needed = GET_MODE_SIZE (Pmode);
18019 case unrolled_loop:
18020 need_zero_guard = true;
18021 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18023 case rep_prefix_8_byte:
18026 case rep_prefix_4_byte:
18029 case rep_prefix_1_byte:
18033 need_zero_guard = true;
18038 epilogue_size_needed = size_needed;
18040 /* Step 1: Prologue guard. */
18042 /* Alignment code needs count to be in register. */
18043 if (CONST_INT_P (count_exp) && desired_align > align)
18045 if (INTVAL (count_exp) > desired_align
18046 && INTVAL (count_exp) > size_needed)
18049 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18050 if (align_bytes <= 0)
18053 align_bytes = desired_align - align_bytes;
18055 if (align_bytes == 0)
18056 count_exp = force_reg (counter_mode (count_exp), count_exp);
18058 gcc_assert (desired_align >= 1 && align >= 1);
18060 /* Ensure that alignment prologue won't copy past end of block. */
18061 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18063 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18064 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18065 Make sure it is power of 2. */
18066 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18070 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18072 /* If main algorithm works on QImode, no epilogue is needed.
18073 For small sizes just don't align anything. */
18074 if (size_needed == 1)
18075 desired_align = align;
18082 label = gen_label_rtx ();
18083 emit_cmp_and_jump_insns (count_exp,
18084 GEN_INT (epilogue_size_needed),
18085 LTU, 0, counter_mode (count_exp), 1, label);
18086 if (expected_size == -1 || expected_size < epilogue_size_needed)
18087 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18089 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18093 /* Emit code to decide on runtime whether library call or inline should be
18095 if (dynamic_check != -1)
18097 if (CONST_INT_P (count_exp))
18099 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18101 emit_block_move_via_libcall (dst, src, count_exp, false);
18102 count_exp = const0_rtx;
18108 rtx hot_label = gen_label_rtx ();
18109 jump_around_label = gen_label_rtx ();
18110 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18111 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18112 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18113 emit_block_move_via_libcall (dst, src, count_exp, false);
18114 emit_jump (jump_around_label);
18115 emit_label (hot_label);
18119 /* Step 2: Alignment prologue. */
18121 if (desired_align > align)
18123 if (align_bytes == 0)
18125 /* Except for the first move in epilogue, we no longer know
18126 constant offset in aliasing info. It don't seems to worth
18127 the pain to maintain it for the first move, so throw away
18129 src = change_address (src, BLKmode, srcreg);
18130 dst = change_address (dst, BLKmode, destreg);
18131 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18136 /* If we know how many bytes need to be stored before dst is
18137 sufficiently aligned, maintain aliasing info accurately. */
18138 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18139 desired_align, align_bytes);
18140 count_exp = plus_constant (count_exp, -align_bytes);
18141 count -= align_bytes;
18143 if (need_zero_guard
18144 && (count < (unsigned HOST_WIDE_INT) size_needed
18145 || (align_bytes == 0
18146 && count < ((unsigned HOST_WIDE_INT) size_needed
18147 + desired_align - align))))
18149 /* It is possible that we copied enough so the main loop will not
18151 gcc_assert (size_needed > 1);
18152 if (label == NULL_RTX)
18153 label = gen_label_rtx ();
18154 emit_cmp_and_jump_insns (count_exp,
18155 GEN_INT (size_needed),
18156 LTU, 0, counter_mode (count_exp), 1, label);
18157 if (expected_size == -1
18158 || expected_size < (desired_align - align) / 2 + size_needed)
18159 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18161 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18164 if (label && size_needed == 1)
18166 emit_label (label);
18167 LABEL_NUSES (label) = 1;
18169 epilogue_size_needed = 1;
18171 else if (label == NULL_RTX)
18172 epilogue_size_needed = size_needed;
18174 /* Step 3: Main loop. */
18180 gcc_unreachable ();
18182 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18183 count_exp, QImode, 1, expected_size);
18186 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18187 count_exp, Pmode, 1, expected_size);
18189 case unrolled_loop:
18190 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18191 registers for 4 temporaries anyway. */
18192 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18193 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18196 case rep_prefix_8_byte:
18197 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18200 case rep_prefix_4_byte:
18201 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18204 case rep_prefix_1_byte:
18205 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18209 /* Adjust properly the offset of src and dest memory for aliasing. */
18210 if (CONST_INT_P (count_exp))
18212 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18213 (count / size_needed) * size_needed);
18214 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18215 (count / size_needed) * size_needed);
18219 src = change_address (src, BLKmode, srcreg);
18220 dst = change_address (dst, BLKmode, destreg);
18223 /* Step 4: Epilogue to copy the remaining bytes. */
18227 /* When the main loop is done, COUNT_EXP might hold original count,
18228 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18229 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18230 bytes. Compensate if needed. */
18232 if (size_needed < epilogue_size_needed)
18235 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18236 GEN_INT (size_needed - 1), count_exp, 1,
18238 if (tmp != count_exp)
18239 emit_move_insn (count_exp, tmp);
18241 emit_label (label);
18242 LABEL_NUSES (label) = 1;
18245 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18246 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18247 epilogue_size_needed);
18248 if (jump_around_label)
18249 emit_label (jump_around_label);
18253 /* Helper function for memcpy. For QImode value 0xXY produce
18254 0xXYXYXYXY of wide specified by MODE. This is essentially
18255 a * 0x10101010, but we can do slightly better than
18256 synth_mult by unwinding the sequence by hand on CPUs with
18259 promote_duplicated_reg (enum machine_mode mode, rtx val)
18261 enum machine_mode valmode = GET_MODE (val);
18263 int nops = mode == DImode ? 3 : 2;
18265 gcc_assert (mode == SImode || mode == DImode);
18266 if (val == const0_rtx)
18267 return copy_to_mode_reg (mode, const0_rtx);
18268 if (CONST_INT_P (val))
18270 HOST_WIDE_INT v = INTVAL (val) & 255;
18274 if (mode == DImode)
18275 v |= (v << 16) << 16;
18276 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18279 if (valmode == VOIDmode)
18281 if (valmode != QImode)
18282 val = gen_lowpart (QImode, val);
18283 if (mode == QImode)
18285 if (!TARGET_PARTIAL_REG_STALL)
18287 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18288 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18289 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18290 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18292 rtx reg = convert_modes (mode, QImode, val, true);
18293 tmp = promote_duplicated_reg (mode, const1_rtx);
18294 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18299 rtx reg = convert_modes (mode, QImode, val, true);
18301 if (!TARGET_PARTIAL_REG_STALL)
18302 if (mode == SImode)
18303 emit_insn (gen_movsi_insv_1 (reg, reg));
18305 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18308 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18309 NULL, 1, OPTAB_DIRECT);
18311 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18313 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18314 NULL, 1, OPTAB_DIRECT);
18315 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18316 if (mode == SImode)
18318 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18319 NULL, 1, OPTAB_DIRECT);
18320 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18325 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18326 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18327 alignment from ALIGN to DESIRED_ALIGN. */
18329 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18334 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18335 promoted_val = promote_duplicated_reg (DImode, val);
18336 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18337 promoted_val = promote_duplicated_reg (SImode, val);
18338 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18339 promoted_val = promote_duplicated_reg (HImode, val);
18341 promoted_val = val;
18343 return promoted_val;
18346 /* Expand string clear operation (bzero). Use i386 string operations when
18347 profitable. See expand_movmem comment for explanation of individual
18348 steps performed. */
18350 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18351 rtx expected_align_exp, rtx expected_size_exp)
18356 rtx jump_around_label = NULL;
18357 HOST_WIDE_INT align = 1;
18358 unsigned HOST_WIDE_INT count = 0;
18359 HOST_WIDE_INT expected_size = -1;
18360 int size_needed = 0, epilogue_size_needed;
18361 int desired_align = 0, align_bytes = 0;
18362 enum stringop_alg alg;
18363 rtx promoted_val = NULL;
18364 bool force_loopy_epilogue = false;
18366 bool need_zero_guard = false;
18368 if (CONST_INT_P (align_exp))
18369 align = INTVAL (align_exp);
18370 /* i386 can do misaligned access on reasonably increased cost. */
18371 if (CONST_INT_P (expected_align_exp)
18372 && INTVAL (expected_align_exp) > align)
18373 align = INTVAL (expected_align_exp);
18374 if (CONST_INT_P (count_exp))
18375 count = expected_size = INTVAL (count_exp);
18376 if (CONST_INT_P (expected_size_exp) && count == 0)
18377 expected_size = INTVAL (expected_size_exp);
18379 /* Make sure we don't need to care about overflow later on. */
18380 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18383 /* Step 0: Decide on preferred algorithm, desired alignment and
18384 size of chunks to be copied by main loop. */
18386 alg = decide_alg (count, expected_size, true, &dynamic_check);
18387 desired_align = decide_alignment (align, alg, expected_size);
18389 if (!TARGET_ALIGN_STRINGOPS)
18390 align = desired_align;
18392 if (alg == libcall)
18394 gcc_assert (alg != no_stringop);
18396 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18397 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18402 gcc_unreachable ();
18404 need_zero_guard = true;
18405 size_needed = GET_MODE_SIZE (Pmode);
18407 case unrolled_loop:
18408 need_zero_guard = true;
18409 size_needed = GET_MODE_SIZE (Pmode) * 4;
18411 case rep_prefix_8_byte:
18414 case rep_prefix_4_byte:
18417 case rep_prefix_1_byte:
18421 need_zero_guard = true;
18425 epilogue_size_needed = size_needed;
18427 /* Step 1: Prologue guard. */
18429 /* Alignment code needs count to be in register. */
18430 if (CONST_INT_P (count_exp) && desired_align > align)
18432 if (INTVAL (count_exp) > desired_align
18433 && INTVAL (count_exp) > size_needed)
18436 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18437 if (align_bytes <= 0)
18440 align_bytes = desired_align - align_bytes;
18442 if (align_bytes == 0)
18444 enum machine_mode mode = SImode;
18445 if (TARGET_64BIT && (count & ~0xffffffff))
18447 count_exp = force_reg (mode, count_exp);
18450 /* Do the cheap promotion to allow better CSE across the
18451 main loop and epilogue (ie one load of the big constant in the
18452 front of all code. */
18453 if (CONST_INT_P (val_exp))
18454 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18455 desired_align, align);
18456 /* Ensure that alignment prologue won't copy past end of block. */
18457 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18459 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18460 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18461 Make sure it is power of 2. */
18462 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18464 /* To improve performance of small blocks, we jump around the VAL
18465 promoting mode. This mean that if the promoted VAL is not constant,
18466 we might not use it in the epilogue and have to use byte
18468 if (epilogue_size_needed > 2 && !promoted_val)
18469 force_loopy_epilogue = true;
18472 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18474 /* If main algorithm works on QImode, no epilogue is needed.
18475 For small sizes just don't align anything. */
18476 if (size_needed == 1)
18477 desired_align = align;
18484 label = gen_label_rtx ();
18485 emit_cmp_and_jump_insns (count_exp,
18486 GEN_INT (epilogue_size_needed),
18487 LTU, 0, counter_mode (count_exp), 1, label);
18488 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18489 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18491 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18494 if (dynamic_check != -1)
18496 rtx hot_label = gen_label_rtx ();
18497 jump_around_label = gen_label_rtx ();
18498 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18499 LEU, 0, counter_mode (count_exp), 1, hot_label);
18500 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18501 set_storage_via_libcall (dst, count_exp, val_exp, false);
18502 emit_jump (jump_around_label);
18503 emit_label (hot_label);
18506 /* Step 2: Alignment prologue. */
18508 /* Do the expensive promotion once we branched off the small blocks. */
18510 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18511 desired_align, align);
18512 gcc_assert (desired_align >= 1 && align >= 1);
18514 if (desired_align > align)
18516 if (align_bytes == 0)
18518 /* Except for the first move in epilogue, we no longer know
18519 constant offset in aliasing info. It don't seems to worth
18520 the pain to maintain it for the first move, so throw away
18522 dst = change_address (dst, BLKmode, destreg);
18523 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18528 /* If we know how many bytes need to be stored before dst is
18529 sufficiently aligned, maintain aliasing info accurately. */
18530 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18531 desired_align, align_bytes);
18532 count_exp = plus_constant (count_exp, -align_bytes);
18533 count -= align_bytes;
18535 if (need_zero_guard
18536 && (count < (unsigned HOST_WIDE_INT) size_needed
18537 || (align_bytes == 0
18538 && count < ((unsigned HOST_WIDE_INT) size_needed
18539 + desired_align - align))))
18541 /* It is possible that we copied enough so the main loop will not
18543 gcc_assert (size_needed > 1);
18544 if (label == NULL_RTX)
18545 label = gen_label_rtx ();
18546 emit_cmp_and_jump_insns (count_exp,
18547 GEN_INT (size_needed),
18548 LTU, 0, counter_mode (count_exp), 1, label);
18549 if (expected_size == -1
18550 || expected_size < (desired_align - align) / 2 + size_needed)
18551 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18553 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18556 if (label && size_needed == 1)
18558 emit_label (label);
18559 LABEL_NUSES (label) = 1;
18561 promoted_val = val_exp;
18562 epilogue_size_needed = 1;
18564 else if (label == NULL_RTX)
18565 epilogue_size_needed = size_needed;
18567 /* Step 3: Main loop. */
18573 gcc_unreachable ();
18575 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18576 count_exp, QImode, 1, expected_size);
18579 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18580 count_exp, Pmode, 1, expected_size);
18582 case unrolled_loop:
18583 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18584 count_exp, Pmode, 4, expected_size);
18586 case rep_prefix_8_byte:
18587 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18590 case rep_prefix_4_byte:
18591 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18594 case rep_prefix_1_byte:
18595 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18599 /* Adjust properly the offset of src and dest memory for aliasing. */
18600 if (CONST_INT_P (count_exp))
18601 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18602 (count / size_needed) * size_needed);
18604 dst = change_address (dst, BLKmode, destreg);
18606 /* Step 4: Epilogue to copy the remaining bytes. */
18610 /* When the main loop is done, COUNT_EXP might hold original count,
18611 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18612 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18613 bytes. Compensate if needed. */
18615 if (size_needed < epilogue_size_needed)
18618 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18619 GEN_INT (size_needed - 1), count_exp, 1,
18621 if (tmp != count_exp)
18622 emit_move_insn (count_exp, tmp);
18624 emit_label (label);
18625 LABEL_NUSES (label) = 1;
18628 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18630 if (force_loopy_epilogue)
18631 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18632 epilogue_size_needed);
18634 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18635 epilogue_size_needed);
18637 if (jump_around_label)
18638 emit_label (jump_around_label);
18642 /* Expand the appropriate insns for doing strlen if not just doing
18645 out = result, initialized with the start address
18646 align_rtx = alignment of the address.
18647 scratch = scratch register, initialized with the startaddress when
18648 not aligned, otherwise undefined
18650 This is just the body. It needs the initializations mentioned above and
18651 some address computing at the end. These things are done in i386.md. */
18654 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18658 rtx align_2_label = NULL_RTX;
18659 rtx align_3_label = NULL_RTX;
18660 rtx align_4_label = gen_label_rtx ();
18661 rtx end_0_label = gen_label_rtx ();
18663 rtx tmpreg = gen_reg_rtx (SImode);
18664 rtx scratch = gen_reg_rtx (SImode);
18668 if (CONST_INT_P (align_rtx))
18669 align = INTVAL (align_rtx);
18671 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18673 /* Is there a known alignment and is it less than 4? */
18676 rtx scratch1 = gen_reg_rtx (Pmode);
18677 emit_move_insn (scratch1, out);
18678 /* Is there a known alignment and is it not 2? */
18681 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18682 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18684 /* Leave just the 3 lower bits. */
18685 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18686 NULL_RTX, 0, OPTAB_WIDEN);
18688 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18689 Pmode, 1, align_4_label);
18690 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18691 Pmode, 1, align_2_label);
18692 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18693 Pmode, 1, align_3_label);
18697 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18698 check if is aligned to 4 - byte. */
18700 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18701 NULL_RTX, 0, OPTAB_WIDEN);
18703 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18704 Pmode, 1, align_4_label);
18707 mem = change_address (src, QImode, out);
18709 /* Now compare the bytes. */
18711 /* Compare the first n unaligned byte on a byte per byte basis. */
18712 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18713 QImode, 1, end_0_label);
18715 /* Increment the address. */
18716 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18718 /* Not needed with an alignment of 2 */
18721 emit_label (align_2_label);
18723 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18726 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18728 emit_label (align_3_label);
18731 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18734 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18737 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18738 align this loop. It gives only huge programs, but does not help to
18740 emit_label (align_4_label);
18742 mem = change_address (src, SImode, out);
18743 emit_move_insn (scratch, mem);
18744 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18746 /* This formula yields a nonzero result iff one of the bytes is zero.
18747 This saves three branches inside loop and many cycles. */
18749 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18750 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18751 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18752 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18753 gen_int_mode (0x80808080, SImode)));
18754 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18759 rtx reg = gen_reg_rtx (SImode);
18760 rtx reg2 = gen_reg_rtx (Pmode);
18761 emit_move_insn (reg, tmpreg);
18762 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18764 /* If zero is not in the first two bytes, move two bytes forward. */
18765 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18766 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18767 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18768 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18769 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18772 /* Emit lea manually to avoid clobbering of flags. */
18773 emit_insn (gen_rtx_SET (SImode, reg2,
18774 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18776 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18777 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18778 emit_insn (gen_rtx_SET (VOIDmode, out,
18779 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18786 rtx end_2_label = gen_label_rtx ();
18787 /* Is zero in the first two bytes? */
18789 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18790 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18791 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18792 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18793 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18795 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18796 JUMP_LABEL (tmp) = end_2_label;
18798 /* Not in the first two. Move two bytes forward. */
18799 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18800 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18802 emit_label (end_2_label);
18806 /* Avoid branch in fixing the byte. */
18807 tmpreg = gen_lowpart (QImode, tmpreg);
18808 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18809 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18810 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18812 emit_label (end_0_label);
18815 /* Expand strlen. */
18818 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18820 rtx addr, scratch1, scratch2, scratch3, scratch4;
18822 /* The generic case of strlen expander is long. Avoid it's
18823 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18825 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18826 && !TARGET_INLINE_ALL_STRINGOPS
18827 && !optimize_insn_for_size_p ()
18828 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18831 addr = force_reg (Pmode, XEXP (src, 0));
18832 scratch1 = gen_reg_rtx (Pmode);
18834 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18835 && !optimize_insn_for_size_p ())
18837 /* Well it seems that some optimizer does not combine a call like
18838 foo(strlen(bar), strlen(bar));
18839 when the move and the subtraction is done here. It does calculate
18840 the length just once when these instructions are done inside of
18841 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18842 often used and I use one fewer register for the lifetime of
18843 output_strlen_unroll() this is better. */
18845 emit_move_insn (out, addr);
18847 ix86_expand_strlensi_unroll_1 (out, src, align);
18849 /* strlensi_unroll_1 returns the address of the zero at the end of
18850 the string, like memchr(), so compute the length by subtracting
18851 the start address. */
18852 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18858 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18859 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18862 scratch2 = gen_reg_rtx (Pmode);
18863 scratch3 = gen_reg_rtx (Pmode);
18864 scratch4 = force_reg (Pmode, constm1_rtx);
18866 emit_move_insn (scratch3, addr);
18867 eoschar = force_reg (QImode, eoschar);
18869 src = replace_equiv_address_nv (src, scratch3);
18871 /* If .md starts supporting :P, this can be done in .md. */
18872 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18873 scratch4), UNSPEC_SCAS);
18874 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18875 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18876 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18881 /* For given symbol (function) construct code to compute address of it's PLT
18882 entry in large x86-64 PIC model. */
18884 construct_plt_address (rtx symbol)
18886 rtx tmp = gen_reg_rtx (Pmode);
18887 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18889 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18890 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18892 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18893 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18898 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18900 rtx pop, int sibcall)
18902 rtx use = NULL, call;
18904 if (pop == const0_rtx)
18906 gcc_assert (!TARGET_64BIT || !pop);
18908 if (TARGET_MACHO && !TARGET_64BIT)
18911 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18912 fnaddr = machopic_indirect_call_target (fnaddr);
18917 /* Static functions and indirect calls don't need the pic register. */
18918 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18919 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18920 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18921 use_reg (&use, pic_offset_table_rtx);
18924 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18926 rtx al = gen_rtx_REG (QImode, AX_REG);
18927 emit_move_insn (al, callarg2);
18928 use_reg (&use, al);
18931 if (ix86_cmodel == CM_LARGE_PIC
18933 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18934 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18935 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18937 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18938 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18940 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18941 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18944 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18946 call = gen_rtx_SET (VOIDmode, retval, call);
18949 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18950 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18951 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18954 && ix86_cfun_abi () == MS_ABI
18955 && (!callarg2 || INTVAL (callarg2) != -2))
18957 /* We need to represent that SI and DI registers are clobbered
18959 static int clobbered_registers[] = {
18960 XMM6_REG, XMM7_REG, XMM8_REG,
18961 XMM9_REG, XMM10_REG, XMM11_REG,
18962 XMM12_REG, XMM13_REG, XMM14_REG,
18963 XMM15_REG, SI_REG, DI_REG
18966 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18967 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18968 UNSPEC_MS_TO_SYSV_CALL);
18972 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18973 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18976 (SSE_REGNO_P (clobbered_registers[i])
18978 clobbered_registers[i]));
18980 call = gen_rtx_PARALLEL (VOIDmode,
18981 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18985 call = emit_call_insn (call);
18987 CALL_INSN_FUNCTION_USAGE (call) = use;
18991 /* Clear stack slot assignments remembered from previous functions.
18992 This is called from INIT_EXPANDERS once before RTL is emitted for each
18995 static struct machine_function *
18996 ix86_init_machine_status (void)
18998 struct machine_function *f;
19000 f = GGC_CNEW (struct machine_function);
19001 f->use_fast_prologue_epilogue_nregs = -1;
19002 f->tls_descriptor_call_expanded_p = 0;
19003 f->call_abi = ix86_abi;
19008 /* Return a MEM corresponding to a stack slot with mode MODE.
19009 Allocate a new slot if necessary.
19011 The RTL for a function can have several slots available: N is
19012 which slot to use. */
19015 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19017 struct stack_local_entry *s;
19019 gcc_assert (n < MAX_386_STACK_LOCALS);
19021 /* Virtual slot is valid only before vregs are instantiated. */
19022 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19024 for (s = ix86_stack_locals; s; s = s->next)
19025 if (s->mode == mode && s->n == n)
19026 return copy_rtx (s->rtl);
19028 s = (struct stack_local_entry *)
19029 ggc_alloc (sizeof (struct stack_local_entry));
19032 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19034 s->next = ix86_stack_locals;
19035 ix86_stack_locals = s;
19039 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19041 static GTY(()) rtx ix86_tls_symbol;
19043 ix86_tls_get_addr (void)
19046 if (!ix86_tls_symbol)
19048 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19049 (TARGET_ANY_GNU_TLS
19051 ? "___tls_get_addr"
19052 : "__tls_get_addr");
19055 return ix86_tls_symbol;
19058 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19060 static GTY(()) rtx ix86_tls_module_base_symbol;
19062 ix86_tls_module_base (void)
19065 if (!ix86_tls_module_base_symbol)
19067 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19068 "_TLS_MODULE_BASE_");
19069 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19070 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19073 return ix86_tls_module_base_symbol;
19076 /* Calculate the length of the memory address in the instruction
19077 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19080 memory_address_length (rtx addr)
19082 struct ix86_address parts;
19083 rtx base, index, disp;
19087 if (GET_CODE (addr) == PRE_DEC
19088 || GET_CODE (addr) == POST_INC
19089 || GET_CODE (addr) == PRE_MODIFY
19090 || GET_CODE (addr) == POST_MODIFY)
19093 ok = ix86_decompose_address (addr, &parts);
19096 if (parts.base && GET_CODE (parts.base) == SUBREG)
19097 parts.base = SUBREG_REG (parts.base);
19098 if (parts.index && GET_CODE (parts.index) == SUBREG)
19099 parts.index = SUBREG_REG (parts.index);
19102 index = parts.index;
19107 - esp as the base always wants an index,
19108 - ebp as the base always wants a displacement,
19109 - r12 as the base always wants an index,
19110 - r13 as the base always wants a displacement. */
19112 /* Register Indirect. */
19113 if (base && !index && !disp)
19115 /* esp (for its index) and ebp (for its displacement) need
19116 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19119 && (addr == arg_pointer_rtx
19120 || addr == frame_pointer_rtx
19121 || REGNO (addr) == SP_REG
19122 || REGNO (addr) == BP_REG
19123 || REGNO (addr) == R12_REG
19124 || REGNO (addr) == R13_REG))
19128 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19129 is not disp32, but disp32(%rip), so for disp32
19130 SIB byte is needed, unless print_operand_address
19131 optimizes it into disp32(%rip) or (%rip) is implied
19133 else if (disp && !base && !index)
19140 if (GET_CODE (disp) == CONST)
19141 symbol = XEXP (disp, 0);
19142 if (GET_CODE (symbol) == PLUS
19143 && CONST_INT_P (XEXP (symbol, 1)))
19144 symbol = XEXP (symbol, 0);
19146 if (GET_CODE (symbol) != LABEL_REF
19147 && (GET_CODE (symbol) != SYMBOL_REF
19148 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19149 && (GET_CODE (symbol) != UNSPEC
19150 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19151 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19158 /* Find the length of the displacement constant. */
19161 if (base && satisfies_constraint_K (disp))
19166 /* ebp always wants a displacement. Similarly r13. */
19167 else if (base && REG_P (base)
19168 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19171 /* An index requires the two-byte modrm form.... */
19173 /* ...like esp (or r12), which always wants an index. */
19174 || base == arg_pointer_rtx
19175 || base == frame_pointer_rtx
19176 || (base && REG_P (base)
19177 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19194 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19195 is set, expect that insn have 8bit immediate alternative. */
19197 ix86_attr_length_immediate_default (rtx insn, int shortform)
19201 extract_insn_cached (insn);
19202 for (i = recog_data.n_operands - 1; i >= 0; --i)
19203 if (CONSTANT_P (recog_data.operand[i]))
19205 enum attr_mode mode = get_attr_mode (insn);
19208 if (shortform && CONST_INT_P (recog_data.operand[i]))
19210 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19217 ival = trunc_int_for_mode (ival, HImode);
19220 ival = trunc_int_for_mode (ival, SImode);
19225 if (IN_RANGE (ival, -128, 127))
19242 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19247 fatal_insn ("unknown insn mode", insn);
19252 /* Compute default value for "length_address" attribute. */
19254 ix86_attr_length_address_default (rtx insn)
19258 if (get_attr_type (insn) == TYPE_LEA)
19260 rtx set = PATTERN (insn), addr;
19262 if (GET_CODE (set) == PARALLEL)
19263 set = XVECEXP (set, 0, 0);
19265 gcc_assert (GET_CODE (set) == SET);
19267 addr = SET_SRC (set);
19268 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19270 if (GET_CODE (addr) == ZERO_EXTEND)
19271 addr = XEXP (addr, 0);
19272 if (GET_CODE (addr) == SUBREG)
19273 addr = SUBREG_REG (addr);
19276 return memory_address_length (addr);
19279 extract_insn_cached (insn);
19280 for (i = recog_data.n_operands - 1; i >= 0; --i)
19281 if (MEM_P (recog_data.operand[i]))
19283 constrain_operands_cached (reload_completed);
19284 if (which_alternative != -1)
19286 const char *constraints = recog_data.constraints[i];
19287 int alt = which_alternative;
19289 while (*constraints == '=' || *constraints == '+')
19292 while (*constraints++ != ',')
19294 /* Skip ignored operands. */
19295 if (*constraints == 'X')
19298 return memory_address_length (XEXP (recog_data.operand[i], 0));
19303 /* Compute default value for "length_vex" attribute. It includes
19304 2 or 3 byte VEX prefix and 1 opcode byte. */
19307 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19312 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19313 byte VEX prefix. */
19314 if (!has_0f_opcode || has_vex_w)
19317 /* We can always use 2 byte VEX prefix in 32bit. */
19321 extract_insn_cached (insn);
19323 for (i = recog_data.n_operands - 1; i >= 0; --i)
19324 if (REG_P (recog_data.operand[i]))
19326 /* REX.W bit uses 3 byte VEX prefix. */
19327 if (GET_MODE (recog_data.operand[i]) == DImode
19328 && GENERAL_REG_P (recog_data.operand[i]))
19333 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19334 if (MEM_P (recog_data.operand[i])
19335 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19342 /* Return the maximum number of instructions a cpu can issue. */
19345 ix86_issue_rate (void)
19349 case PROCESSOR_PENTIUM:
19350 case PROCESSOR_ATOM:
19354 case PROCESSOR_PENTIUMPRO:
19355 case PROCESSOR_PENTIUM4:
19356 case PROCESSOR_ATHLON:
19358 case PROCESSOR_AMDFAM10:
19359 case PROCESSOR_NOCONA:
19360 case PROCESSOR_GENERIC32:
19361 case PROCESSOR_GENERIC64:
19364 case PROCESSOR_CORE2:
19372 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19373 by DEP_INSN and nothing set by DEP_INSN. */
19376 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19380 /* Simplify the test for uninteresting insns. */
19381 if (insn_type != TYPE_SETCC
19382 && insn_type != TYPE_ICMOV
19383 && insn_type != TYPE_FCMOV
19384 && insn_type != TYPE_IBR)
19387 if ((set = single_set (dep_insn)) != 0)
19389 set = SET_DEST (set);
19392 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19393 && XVECLEN (PATTERN (dep_insn), 0) == 2
19394 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19395 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19397 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19398 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19403 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19406 /* This test is true if the dependent insn reads the flags but
19407 not any other potentially set register. */
19408 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19411 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19417 /* Return true iff USE_INSN has a memory address with operands set by
19421 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19424 extract_insn_cached (use_insn);
19425 for (i = recog_data.n_operands - 1; i >= 0; --i)
19426 if (MEM_P (recog_data.operand[i]))
19428 rtx addr = XEXP (recog_data.operand[i], 0);
19429 return modified_in_p (addr, set_insn) != 0;
19435 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19437 enum attr_type insn_type, dep_insn_type;
19438 enum attr_memory memory;
19440 int dep_insn_code_number;
19442 /* Anti and output dependencies have zero cost on all CPUs. */
19443 if (REG_NOTE_KIND (link) != 0)
19446 dep_insn_code_number = recog_memoized (dep_insn);
19448 /* If we can't recognize the insns, we can't really do anything. */
19449 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19452 insn_type = get_attr_type (insn);
19453 dep_insn_type = get_attr_type (dep_insn);
19457 case PROCESSOR_PENTIUM:
19458 /* Address Generation Interlock adds a cycle of latency. */
19459 if (insn_type == TYPE_LEA)
19461 rtx addr = PATTERN (insn);
19463 if (GET_CODE (addr) == PARALLEL)
19464 addr = XVECEXP (addr, 0, 0);
19466 gcc_assert (GET_CODE (addr) == SET);
19468 addr = SET_SRC (addr);
19469 if (modified_in_p (addr, dep_insn))
19472 else if (ix86_agi_dependent (dep_insn, insn))
19475 /* ??? Compares pair with jump/setcc. */
19476 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19479 /* Floating point stores require value to be ready one cycle earlier. */
19480 if (insn_type == TYPE_FMOV
19481 && get_attr_memory (insn) == MEMORY_STORE
19482 && !ix86_agi_dependent (dep_insn, insn))
19486 case PROCESSOR_PENTIUMPRO:
19487 memory = get_attr_memory (insn);
19489 /* INT->FP conversion is expensive. */
19490 if (get_attr_fp_int_src (dep_insn))
19493 /* There is one cycle extra latency between an FP op and a store. */
19494 if (insn_type == TYPE_FMOV
19495 && (set = single_set (dep_insn)) != NULL_RTX
19496 && (set2 = single_set (insn)) != NULL_RTX
19497 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19498 && MEM_P (SET_DEST (set2)))
19501 /* Show ability of reorder buffer to hide latency of load by executing
19502 in parallel with previous instruction in case
19503 previous instruction is not needed to compute the address. */
19504 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19505 && !ix86_agi_dependent (dep_insn, insn))
19507 /* Claim moves to take one cycle, as core can issue one load
19508 at time and the next load can start cycle later. */
19509 if (dep_insn_type == TYPE_IMOV
19510 || dep_insn_type == TYPE_FMOV)
19518 memory = get_attr_memory (insn);
19520 /* The esp dependency is resolved before the instruction is really
19522 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19523 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19526 /* INT->FP conversion is expensive. */
19527 if (get_attr_fp_int_src (dep_insn))
19530 /* Show ability of reorder buffer to hide latency of load by executing
19531 in parallel with previous instruction in case
19532 previous instruction is not needed to compute the address. */
19533 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19534 && !ix86_agi_dependent (dep_insn, insn))
19536 /* Claim moves to take one cycle, as core can issue one load
19537 at time and the next load can start cycle later. */
19538 if (dep_insn_type == TYPE_IMOV
19539 || dep_insn_type == TYPE_FMOV)
19548 case PROCESSOR_ATHLON:
19550 case PROCESSOR_AMDFAM10:
19551 case PROCESSOR_ATOM:
19552 case PROCESSOR_GENERIC32:
19553 case PROCESSOR_GENERIC64:
19554 memory = get_attr_memory (insn);
19556 /* Show ability of reorder buffer to hide latency of load by executing
19557 in parallel with previous instruction in case
19558 previous instruction is not needed to compute the address. */
19559 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19560 && !ix86_agi_dependent (dep_insn, insn))
19562 enum attr_unit unit = get_attr_unit (insn);
19565 /* Because of the difference between the length of integer and
19566 floating unit pipeline preparation stages, the memory operands
19567 for floating point are cheaper.
19569 ??? For Athlon it the difference is most probably 2. */
19570 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19573 loadcost = TARGET_ATHLON ? 2 : 0;
19575 if (cost >= loadcost)
19588 /* How many alternative schedules to try. This should be as wide as the
19589 scheduling freedom in the DFA, but no wider. Making this value too
19590 large results extra work for the scheduler. */
19593 ia32_multipass_dfa_lookahead (void)
19597 case PROCESSOR_PENTIUM:
19600 case PROCESSOR_PENTIUMPRO:
19610 /* Compute the alignment given to a constant that is being placed in memory.
19611 EXP is the constant and ALIGN is the alignment that the object would
19613 The value of this function is used instead of that alignment to align
19617 ix86_constant_alignment (tree exp, int align)
19619 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19620 || TREE_CODE (exp) == INTEGER_CST)
19622 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19624 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19627 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19628 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19629 return BITS_PER_WORD;
19634 /* Compute the alignment for a static variable.
19635 TYPE is the data type, and ALIGN is the alignment that
19636 the object would ordinarily have. The value of this function is used
19637 instead of that alignment to align the object. */
19640 ix86_data_alignment (tree type, int align)
19642 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19644 if (AGGREGATE_TYPE_P (type)
19645 && TYPE_SIZE (type)
19646 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19647 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19648 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19649 && align < max_align)
19652 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19653 to 16byte boundary. */
19656 if (AGGREGATE_TYPE_P (type)
19657 && TYPE_SIZE (type)
19658 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19659 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19660 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19664 if (TREE_CODE (type) == ARRAY_TYPE)
19666 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19668 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19671 else if (TREE_CODE (type) == COMPLEX_TYPE)
19674 if (TYPE_MODE (type) == DCmode && align < 64)
19676 if ((TYPE_MODE (type) == XCmode
19677 || TYPE_MODE (type) == TCmode) && align < 128)
19680 else if ((TREE_CODE (type) == RECORD_TYPE
19681 || TREE_CODE (type) == UNION_TYPE
19682 || TREE_CODE (type) == QUAL_UNION_TYPE)
19683 && TYPE_FIELDS (type))
19685 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19687 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19690 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19691 || TREE_CODE (type) == INTEGER_TYPE)
19693 if (TYPE_MODE (type) == DFmode && align < 64)
19695 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19702 /* Compute the alignment for a local variable or a stack slot. EXP is
19703 the data type or decl itself, MODE is the widest mode available and
19704 ALIGN is the alignment that the object would ordinarily have. The
19705 value of this macro is used instead of that alignment to align the
19709 ix86_local_alignment (tree exp, enum machine_mode mode,
19710 unsigned int align)
19714 if (exp && DECL_P (exp))
19716 type = TREE_TYPE (exp);
19725 /* Don't do dynamic stack realignment for long long objects with
19726 -mpreferred-stack-boundary=2. */
19729 && ix86_preferred_stack_boundary < 64
19730 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19731 && (!type || !TYPE_USER_ALIGN (type))
19732 && (!decl || !DECL_USER_ALIGN (decl)))
19735 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19736 register in MODE. We will return the largest alignment of XF
19740 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19741 align = GET_MODE_ALIGNMENT (DFmode);
19745 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19746 to 16byte boundary. */
19749 if (AGGREGATE_TYPE_P (type)
19750 && TYPE_SIZE (type)
19751 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19752 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19753 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19756 if (TREE_CODE (type) == ARRAY_TYPE)
19758 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19760 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19763 else if (TREE_CODE (type) == COMPLEX_TYPE)
19765 if (TYPE_MODE (type) == DCmode && align < 64)
19767 if ((TYPE_MODE (type) == XCmode
19768 || TYPE_MODE (type) == TCmode) && align < 128)
19771 else if ((TREE_CODE (type) == RECORD_TYPE
19772 || TREE_CODE (type) == UNION_TYPE
19773 || TREE_CODE (type) == QUAL_UNION_TYPE)
19774 && TYPE_FIELDS (type))
19776 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19778 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19781 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19782 || TREE_CODE (type) == INTEGER_TYPE)
19785 if (TYPE_MODE (type) == DFmode && align < 64)
19787 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19793 /* Compute the minimum required alignment for dynamic stack realignment
19794 purposes for a local variable, parameter or a stack slot. EXP is
19795 the data type or decl itself, MODE is its mode and ALIGN is the
19796 alignment that the object would ordinarily have. */
19799 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19800 unsigned int align)
19804 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19807 if (exp && DECL_P (exp))
19809 type = TREE_TYPE (exp);
19818 /* Don't do dynamic stack realignment for long long objects with
19819 -mpreferred-stack-boundary=2. */
19820 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19821 && (!type || !TYPE_USER_ALIGN (type))
19822 && (!decl || !DECL_USER_ALIGN (decl)))
19828 /* Emit RTL insns to initialize the variable parts of a trampoline.
19829 FNADDR is an RTX for the address of the function's pure code.
19830 CXT is an RTX for the static chain value for the function. */
19832 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19836 /* Compute offset from the end of the jmp to the target function. */
19837 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19838 plus_constant (tramp, 10),
19839 NULL_RTX, 1, OPTAB_DIRECT);
19840 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19841 gen_int_mode (0xb9, QImode));
19842 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19843 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19844 gen_int_mode (0xe9, QImode));
19845 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19850 /* Try to load address using shorter movl instead of movabs.
19851 We may want to support movq for kernel mode, but kernel does not use
19852 trampolines at the moment. */
19853 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19855 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19856 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19857 gen_int_mode (0xbb41, HImode));
19858 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19859 gen_lowpart (SImode, fnaddr));
19864 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19865 gen_int_mode (0xbb49, HImode));
19866 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19870 /* Load static chain using movabs to r10. */
19871 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19872 gen_int_mode (0xba49, HImode));
19873 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19876 /* Jump to the r11 */
19877 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19878 gen_int_mode (0xff49, HImode));
19879 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19880 gen_int_mode (0xe3, QImode));
19882 gcc_assert (offset <= TRAMPOLINE_SIZE);
19885 #ifdef ENABLE_EXECUTE_STACK
19886 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19887 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19891 /* Codes for all the SSE/MMX builtins. */
19894 IX86_BUILTIN_ADDPS,
19895 IX86_BUILTIN_ADDSS,
19896 IX86_BUILTIN_DIVPS,
19897 IX86_BUILTIN_DIVSS,
19898 IX86_BUILTIN_MULPS,
19899 IX86_BUILTIN_MULSS,
19900 IX86_BUILTIN_SUBPS,
19901 IX86_BUILTIN_SUBSS,
19903 IX86_BUILTIN_CMPEQPS,
19904 IX86_BUILTIN_CMPLTPS,
19905 IX86_BUILTIN_CMPLEPS,
19906 IX86_BUILTIN_CMPGTPS,
19907 IX86_BUILTIN_CMPGEPS,
19908 IX86_BUILTIN_CMPNEQPS,
19909 IX86_BUILTIN_CMPNLTPS,
19910 IX86_BUILTIN_CMPNLEPS,
19911 IX86_BUILTIN_CMPNGTPS,
19912 IX86_BUILTIN_CMPNGEPS,
19913 IX86_BUILTIN_CMPORDPS,
19914 IX86_BUILTIN_CMPUNORDPS,
19915 IX86_BUILTIN_CMPEQSS,
19916 IX86_BUILTIN_CMPLTSS,
19917 IX86_BUILTIN_CMPLESS,
19918 IX86_BUILTIN_CMPNEQSS,
19919 IX86_BUILTIN_CMPNLTSS,
19920 IX86_BUILTIN_CMPNLESS,
19921 IX86_BUILTIN_CMPNGTSS,
19922 IX86_BUILTIN_CMPNGESS,
19923 IX86_BUILTIN_CMPORDSS,
19924 IX86_BUILTIN_CMPUNORDSS,
19926 IX86_BUILTIN_COMIEQSS,
19927 IX86_BUILTIN_COMILTSS,
19928 IX86_BUILTIN_COMILESS,
19929 IX86_BUILTIN_COMIGTSS,
19930 IX86_BUILTIN_COMIGESS,
19931 IX86_BUILTIN_COMINEQSS,
19932 IX86_BUILTIN_UCOMIEQSS,
19933 IX86_BUILTIN_UCOMILTSS,
19934 IX86_BUILTIN_UCOMILESS,
19935 IX86_BUILTIN_UCOMIGTSS,
19936 IX86_BUILTIN_UCOMIGESS,
19937 IX86_BUILTIN_UCOMINEQSS,
19939 IX86_BUILTIN_CVTPI2PS,
19940 IX86_BUILTIN_CVTPS2PI,
19941 IX86_BUILTIN_CVTSI2SS,
19942 IX86_BUILTIN_CVTSI642SS,
19943 IX86_BUILTIN_CVTSS2SI,
19944 IX86_BUILTIN_CVTSS2SI64,
19945 IX86_BUILTIN_CVTTPS2PI,
19946 IX86_BUILTIN_CVTTSS2SI,
19947 IX86_BUILTIN_CVTTSS2SI64,
19949 IX86_BUILTIN_MAXPS,
19950 IX86_BUILTIN_MAXSS,
19951 IX86_BUILTIN_MINPS,
19952 IX86_BUILTIN_MINSS,
19954 IX86_BUILTIN_LOADUPS,
19955 IX86_BUILTIN_STOREUPS,
19956 IX86_BUILTIN_MOVSS,
19958 IX86_BUILTIN_MOVHLPS,
19959 IX86_BUILTIN_MOVLHPS,
19960 IX86_BUILTIN_LOADHPS,
19961 IX86_BUILTIN_LOADLPS,
19962 IX86_BUILTIN_STOREHPS,
19963 IX86_BUILTIN_STORELPS,
19965 IX86_BUILTIN_MASKMOVQ,
19966 IX86_BUILTIN_MOVMSKPS,
19967 IX86_BUILTIN_PMOVMSKB,
19969 IX86_BUILTIN_MOVNTPS,
19970 IX86_BUILTIN_MOVNTQ,
19972 IX86_BUILTIN_LOADDQU,
19973 IX86_BUILTIN_STOREDQU,
19975 IX86_BUILTIN_PACKSSWB,
19976 IX86_BUILTIN_PACKSSDW,
19977 IX86_BUILTIN_PACKUSWB,
19979 IX86_BUILTIN_PADDB,
19980 IX86_BUILTIN_PADDW,
19981 IX86_BUILTIN_PADDD,
19982 IX86_BUILTIN_PADDQ,
19983 IX86_BUILTIN_PADDSB,
19984 IX86_BUILTIN_PADDSW,
19985 IX86_BUILTIN_PADDUSB,
19986 IX86_BUILTIN_PADDUSW,
19987 IX86_BUILTIN_PSUBB,
19988 IX86_BUILTIN_PSUBW,
19989 IX86_BUILTIN_PSUBD,
19990 IX86_BUILTIN_PSUBQ,
19991 IX86_BUILTIN_PSUBSB,
19992 IX86_BUILTIN_PSUBSW,
19993 IX86_BUILTIN_PSUBUSB,
19994 IX86_BUILTIN_PSUBUSW,
19997 IX86_BUILTIN_PANDN,
20001 IX86_BUILTIN_PAVGB,
20002 IX86_BUILTIN_PAVGW,
20004 IX86_BUILTIN_PCMPEQB,
20005 IX86_BUILTIN_PCMPEQW,
20006 IX86_BUILTIN_PCMPEQD,
20007 IX86_BUILTIN_PCMPGTB,
20008 IX86_BUILTIN_PCMPGTW,
20009 IX86_BUILTIN_PCMPGTD,
20011 IX86_BUILTIN_PMADDWD,
20013 IX86_BUILTIN_PMAXSW,
20014 IX86_BUILTIN_PMAXUB,
20015 IX86_BUILTIN_PMINSW,
20016 IX86_BUILTIN_PMINUB,
20018 IX86_BUILTIN_PMULHUW,
20019 IX86_BUILTIN_PMULHW,
20020 IX86_BUILTIN_PMULLW,
20022 IX86_BUILTIN_PSADBW,
20023 IX86_BUILTIN_PSHUFW,
20025 IX86_BUILTIN_PSLLW,
20026 IX86_BUILTIN_PSLLD,
20027 IX86_BUILTIN_PSLLQ,
20028 IX86_BUILTIN_PSRAW,
20029 IX86_BUILTIN_PSRAD,
20030 IX86_BUILTIN_PSRLW,
20031 IX86_BUILTIN_PSRLD,
20032 IX86_BUILTIN_PSRLQ,
20033 IX86_BUILTIN_PSLLWI,
20034 IX86_BUILTIN_PSLLDI,
20035 IX86_BUILTIN_PSLLQI,
20036 IX86_BUILTIN_PSRAWI,
20037 IX86_BUILTIN_PSRADI,
20038 IX86_BUILTIN_PSRLWI,
20039 IX86_BUILTIN_PSRLDI,
20040 IX86_BUILTIN_PSRLQI,
20042 IX86_BUILTIN_PUNPCKHBW,
20043 IX86_BUILTIN_PUNPCKHWD,
20044 IX86_BUILTIN_PUNPCKHDQ,
20045 IX86_BUILTIN_PUNPCKLBW,
20046 IX86_BUILTIN_PUNPCKLWD,
20047 IX86_BUILTIN_PUNPCKLDQ,
20049 IX86_BUILTIN_SHUFPS,
20051 IX86_BUILTIN_RCPPS,
20052 IX86_BUILTIN_RCPSS,
20053 IX86_BUILTIN_RSQRTPS,
20054 IX86_BUILTIN_RSQRTPS_NR,
20055 IX86_BUILTIN_RSQRTSS,
20056 IX86_BUILTIN_RSQRTF,
20057 IX86_BUILTIN_SQRTPS,
20058 IX86_BUILTIN_SQRTPS_NR,
20059 IX86_BUILTIN_SQRTSS,
20061 IX86_BUILTIN_UNPCKHPS,
20062 IX86_BUILTIN_UNPCKLPS,
20064 IX86_BUILTIN_ANDPS,
20065 IX86_BUILTIN_ANDNPS,
20067 IX86_BUILTIN_XORPS,
20070 IX86_BUILTIN_LDMXCSR,
20071 IX86_BUILTIN_STMXCSR,
20072 IX86_BUILTIN_SFENCE,
20074 /* 3DNow! Original */
20075 IX86_BUILTIN_FEMMS,
20076 IX86_BUILTIN_PAVGUSB,
20077 IX86_BUILTIN_PF2ID,
20078 IX86_BUILTIN_PFACC,
20079 IX86_BUILTIN_PFADD,
20080 IX86_BUILTIN_PFCMPEQ,
20081 IX86_BUILTIN_PFCMPGE,
20082 IX86_BUILTIN_PFCMPGT,
20083 IX86_BUILTIN_PFMAX,
20084 IX86_BUILTIN_PFMIN,
20085 IX86_BUILTIN_PFMUL,
20086 IX86_BUILTIN_PFRCP,
20087 IX86_BUILTIN_PFRCPIT1,
20088 IX86_BUILTIN_PFRCPIT2,
20089 IX86_BUILTIN_PFRSQIT1,
20090 IX86_BUILTIN_PFRSQRT,
20091 IX86_BUILTIN_PFSUB,
20092 IX86_BUILTIN_PFSUBR,
20093 IX86_BUILTIN_PI2FD,
20094 IX86_BUILTIN_PMULHRW,
20096 /* 3DNow! Athlon Extensions */
20097 IX86_BUILTIN_PF2IW,
20098 IX86_BUILTIN_PFNACC,
20099 IX86_BUILTIN_PFPNACC,
20100 IX86_BUILTIN_PI2FW,
20101 IX86_BUILTIN_PSWAPDSI,
20102 IX86_BUILTIN_PSWAPDSF,
20105 IX86_BUILTIN_ADDPD,
20106 IX86_BUILTIN_ADDSD,
20107 IX86_BUILTIN_DIVPD,
20108 IX86_BUILTIN_DIVSD,
20109 IX86_BUILTIN_MULPD,
20110 IX86_BUILTIN_MULSD,
20111 IX86_BUILTIN_SUBPD,
20112 IX86_BUILTIN_SUBSD,
20114 IX86_BUILTIN_CMPEQPD,
20115 IX86_BUILTIN_CMPLTPD,
20116 IX86_BUILTIN_CMPLEPD,
20117 IX86_BUILTIN_CMPGTPD,
20118 IX86_BUILTIN_CMPGEPD,
20119 IX86_BUILTIN_CMPNEQPD,
20120 IX86_BUILTIN_CMPNLTPD,
20121 IX86_BUILTIN_CMPNLEPD,
20122 IX86_BUILTIN_CMPNGTPD,
20123 IX86_BUILTIN_CMPNGEPD,
20124 IX86_BUILTIN_CMPORDPD,
20125 IX86_BUILTIN_CMPUNORDPD,
20126 IX86_BUILTIN_CMPEQSD,
20127 IX86_BUILTIN_CMPLTSD,
20128 IX86_BUILTIN_CMPLESD,
20129 IX86_BUILTIN_CMPNEQSD,
20130 IX86_BUILTIN_CMPNLTSD,
20131 IX86_BUILTIN_CMPNLESD,
20132 IX86_BUILTIN_CMPORDSD,
20133 IX86_BUILTIN_CMPUNORDSD,
20135 IX86_BUILTIN_COMIEQSD,
20136 IX86_BUILTIN_COMILTSD,
20137 IX86_BUILTIN_COMILESD,
20138 IX86_BUILTIN_COMIGTSD,
20139 IX86_BUILTIN_COMIGESD,
20140 IX86_BUILTIN_COMINEQSD,
20141 IX86_BUILTIN_UCOMIEQSD,
20142 IX86_BUILTIN_UCOMILTSD,
20143 IX86_BUILTIN_UCOMILESD,
20144 IX86_BUILTIN_UCOMIGTSD,
20145 IX86_BUILTIN_UCOMIGESD,
20146 IX86_BUILTIN_UCOMINEQSD,
20148 IX86_BUILTIN_MAXPD,
20149 IX86_BUILTIN_MAXSD,
20150 IX86_BUILTIN_MINPD,
20151 IX86_BUILTIN_MINSD,
20153 IX86_BUILTIN_ANDPD,
20154 IX86_BUILTIN_ANDNPD,
20156 IX86_BUILTIN_XORPD,
20158 IX86_BUILTIN_SQRTPD,
20159 IX86_BUILTIN_SQRTSD,
20161 IX86_BUILTIN_UNPCKHPD,
20162 IX86_BUILTIN_UNPCKLPD,
20164 IX86_BUILTIN_SHUFPD,
20166 IX86_BUILTIN_LOADUPD,
20167 IX86_BUILTIN_STOREUPD,
20168 IX86_BUILTIN_MOVSD,
20170 IX86_BUILTIN_LOADHPD,
20171 IX86_BUILTIN_LOADLPD,
20173 IX86_BUILTIN_CVTDQ2PD,
20174 IX86_BUILTIN_CVTDQ2PS,
20176 IX86_BUILTIN_CVTPD2DQ,
20177 IX86_BUILTIN_CVTPD2PI,
20178 IX86_BUILTIN_CVTPD2PS,
20179 IX86_BUILTIN_CVTTPD2DQ,
20180 IX86_BUILTIN_CVTTPD2PI,
20182 IX86_BUILTIN_CVTPI2PD,
20183 IX86_BUILTIN_CVTSI2SD,
20184 IX86_BUILTIN_CVTSI642SD,
20186 IX86_BUILTIN_CVTSD2SI,
20187 IX86_BUILTIN_CVTSD2SI64,
20188 IX86_BUILTIN_CVTSD2SS,
20189 IX86_BUILTIN_CVTSS2SD,
20190 IX86_BUILTIN_CVTTSD2SI,
20191 IX86_BUILTIN_CVTTSD2SI64,
20193 IX86_BUILTIN_CVTPS2DQ,
20194 IX86_BUILTIN_CVTPS2PD,
20195 IX86_BUILTIN_CVTTPS2DQ,
20197 IX86_BUILTIN_MOVNTI,
20198 IX86_BUILTIN_MOVNTPD,
20199 IX86_BUILTIN_MOVNTDQ,
20201 IX86_BUILTIN_MOVQ128,
20204 IX86_BUILTIN_MASKMOVDQU,
20205 IX86_BUILTIN_MOVMSKPD,
20206 IX86_BUILTIN_PMOVMSKB128,
20208 IX86_BUILTIN_PACKSSWB128,
20209 IX86_BUILTIN_PACKSSDW128,
20210 IX86_BUILTIN_PACKUSWB128,
20212 IX86_BUILTIN_PADDB128,
20213 IX86_BUILTIN_PADDW128,
20214 IX86_BUILTIN_PADDD128,
20215 IX86_BUILTIN_PADDQ128,
20216 IX86_BUILTIN_PADDSB128,
20217 IX86_BUILTIN_PADDSW128,
20218 IX86_BUILTIN_PADDUSB128,
20219 IX86_BUILTIN_PADDUSW128,
20220 IX86_BUILTIN_PSUBB128,
20221 IX86_BUILTIN_PSUBW128,
20222 IX86_BUILTIN_PSUBD128,
20223 IX86_BUILTIN_PSUBQ128,
20224 IX86_BUILTIN_PSUBSB128,
20225 IX86_BUILTIN_PSUBSW128,
20226 IX86_BUILTIN_PSUBUSB128,
20227 IX86_BUILTIN_PSUBUSW128,
20229 IX86_BUILTIN_PAND128,
20230 IX86_BUILTIN_PANDN128,
20231 IX86_BUILTIN_POR128,
20232 IX86_BUILTIN_PXOR128,
20234 IX86_BUILTIN_PAVGB128,
20235 IX86_BUILTIN_PAVGW128,
20237 IX86_BUILTIN_PCMPEQB128,
20238 IX86_BUILTIN_PCMPEQW128,
20239 IX86_BUILTIN_PCMPEQD128,
20240 IX86_BUILTIN_PCMPGTB128,
20241 IX86_BUILTIN_PCMPGTW128,
20242 IX86_BUILTIN_PCMPGTD128,
20244 IX86_BUILTIN_PMADDWD128,
20246 IX86_BUILTIN_PMAXSW128,
20247 IX86_BUILTIN_PMAXUB128,
20248 IX86_BUILTIN_PMINSW128,
20249 IX86_BUILTIN_PMINUB128,
20251 IX86_BUILTIN_PMULUDQ,
20252 IX86_BUILTIN_PMULUDQ128,
20253 IX86_BUILTIN_PMULHUW128,
20254 IX86_BUILTIN_PMULHW128,
20255 IX86_BUILTIN_PMULLW128,
20257 IX86_BUILTIN_PSADBW128,
20258 IX86_BUILTIN_PSHUFHW,
20259 IX86_BUILTIN_PSHUFLW,
20260 IX86_BUILTIN_PSHUFD,
20262 IX86_BUILTIN_PSLLDQI128,
20263 IX86_BUILTIN_PSLLWI128,
20264 IX86_BUILTIN_PSLLDI128,
20265 IX86_BUILTIN_PSLLQI128,
20266 IX86_BUILTIN_PSRAWI128,
20267 IX86_BUILTIN_PSRADI128,
20268 IX86_BUILTIN_PSRLDQI128,
20269 IX86_BUILTIN_PSRLWI128,
20270 IX86_BUILTIN_PSRLDI128,
20271 IX86_BUILTIN_PSRLQI128,
20273 IX86_BUILTIN_PSLLDQ128,
20274 IX86_BUILTIN_PSLLW128,
20275 IX86_BUILTIN_PSLLD128,
20276 IX86_BUILTIN_PSLLQ128,
20277 IX86_BUILTIN_PSRAW128,
20278 IX86_BUILTIN_PSRAD128,
20279 IX86_BUILTIN_PSRLW128,
20280 IX86_BUILTIN_PSRLD128,
20281 IX86_BUILTIN_PSRLQ128,
20283 IX86_BUILTIN_PUNPCKHBW128,
20284 IX86_BUILTIN_PUNPCKHWD128,
20285 IX86_BUILTIN_PUNPCKHDQ128,
20286 IX86_BUILTIN_PUNPCKHQDQ128,
20287 IX86_BUILTIN_PUNPCKLBW128,
20288 IX86_BUILTIN_PUNPCKLWD128,
20289 IX86_BUILTIN_PUNPCKLDQ128,
20290 IX86_BUILTIN_PUNPCKLQDQ128,
20292 IX86_BUILTIN_CLFLUSH,
20293 IX86_BUILTIN_MFENCE,
20294 IX86_BUILTIN_LFENCE,
20296 IX86_BUILTIN_BSRSI,
20297 IX86_BUILTIN_BSRDI,
20298 IX86_BUILTIN_RDPMC,
20299 IX86_BUILTIN_RDTSC,
20300 IX86_BUILTIN_RDTSCP,
20301 IX86_BUILTIN_ROLQI,
20302 IX86_BUILTIN_ROLHI,
20303 IX86_BUILTIN_RORQI,
20304 IX86_BUILTIN_RORHI,
20307 IX86_BUILTIN_ADDSUBPS,
20308 IX86_BUILTIN_HADDPS,
20309 IX86_BUILTIN_HSUBPS,
20310 IX86_BUILTIN_MOVSHDUP,
20311 IX86_BUILTIN_MOVSLDUP,
20312 IX86_BUILTIN_ADDSUBPD,
20313 IX86_BUILTIN_HADDPD,
20314 IX86_BUILTIN_HSUBPD,
20315 IX86_BUILTIN_LDDQU,
20317 IX86_BUILTIN_MONITOR,
20318 IX86_BUILTIN_MWAIT,
20321 IX86_BUILTIN_PHADDW,
20322 IX86_BUILTIN_PHADDD,
20323 IX86_BUILTIN_PHADDSW,
20324 IX86_BUILTIN_PHSUBW,
20325 IX86_BUILTIN_PHSUBD,
20326 IX86_BUILTIN_PHSUBSW,
20327 IX86_BUILTIN_PMADDUBSW,
20328 IX86_BUILTIN_PMULHRSW,
20329 IX86_BUILTIN_PSHUFB,
20330 IX86_BUILTIN_PSIGNB,
20331 IX86_BUILTIN_PSIGNW,
20332 IX86_BUILTIN_PSIGND,
20333 IX86_BUILTIN_PALIGNR,
20334 IX86_BUILTIN_PABSB,
20335 IX86_BUILTIN_PABSW,
20336 IX86_BUILTIN_PABSD,
20338 IX86_BUILTIN_PHADDW128,
20339 IX86_BUILTIN_PHADDD128,
20340 IX86_BUILTIN_PHADDSW128,
20341 IX86_BUILTIN_PHSUBW128,
20342 IX86_BUILTIN_PHSUBD128,
20343 IX86_BUILTIN_PHSUBSW128,
20344 IX86_BUILTIN_PMADDUBSW128,
20345 IX86_BUILTIN_PMULHRSW128,
20346 IX86_BUILTIN_PSHUFB128,
20347 IX86_BUILTIN_PSIGNB128,
20348 IX86_BUILTIN_PSIGNW128,
20349 IX86_BUILTIN_PSIGND128,
20350 IX86_BUILTIN_PALIGNR128,
20351 IX86_BUILTIN_PABSB128,
20352 IX86_BUILTIN_PABSW128,
20353 IX86_BUILTIN_PABSD128,
20355 /* AMDFAM10 - SSE4A New Instructions. */
20356 IX86_BUILTIN_MOVNTSD,
20357 IX86_BUILTIN_MOVNTSS,
20358 IX86_BUILTIN_EXTRQI,
20359 IX86_BUILTIN_EXTRQ,
20360 IX86_BUILTIN_INSERTQI,
20361 IX86_BUILTIN_INSERTQ,
20364 IX86_BUILTIN_BLENDPD,
20365 IX86_BUILTIN_BLENDPS,
20366 IX86_BUILTIN_BLENDVPD,
20367 IX86_BUILTIN_BLENDVPS,
20368 IX86_BUILTIN_PBLENDVB128,
20369 IX86_BUILTIN_PBLENDW128,
20374 IX86_BUILTIN_INSERTPS128,
20376 IX86_BUILTIN_MOVNTDQA,
20377 IX86_BUILTIN_MPSADBW128,
20378 IX86_BUILTIN_PACKUSDW128,
20379 IX86_BUILTIN_PCMPEQQ,
20380 IX86_BUILTIN_PHMINPOSUW128,
20382 IX86_BUILTIN_PMAXSB128,
20383 IX86_BUILTIN_PMAXSD128,
20384 IX86_BUILTIN_PMAXUD128,
20385 IX86_BUILTIN_PMAXUW128,
20387 IX86_BUILTIN_PMINSB128,
20388 IX86_BUILTIN_PMINSD128,
20389 IX86_BUILTIN_PMINUD128,
20390 IX86_BUILTIN_PMINUW128,
20392 IX86_BUILTIN_PMOVSXBW128,
20393 IX86_BUILTIN_PMOVSXBD128,
20394 IX86_BUILTIN_PMOVSXBQ128,
20395 IX86_BUILTIN_PMOVSXWD128,
20396 IX86_BUILTIN_PMOVSXWQ128,
20397 IX86_BUILTIN_PMOVSXDQ128,
20399 IX86_BUILTIN_PMOVZXBW128,
20400 IX86_BUILTIN_PMOVZXBD128,
20401 IX86_BUILTIN_PMOVZXBQ128,
20402 IX86_BUILTIN_PMOVZXWD128,
20403 IX86_BUILTIN_PMOVZXWQ128,
20404 IX86_BUILTIN_PMOVZXDQ128,
20406 IX86_BUILTIN_PMULDQ128,
20407 IX86_BUILTIN_PMULLD128,
20409 IX86_BUILTIN_ROUNDPD,
20410 IX86_BUILTIN_ROUNDPS,
20411 IX86_BUILTIN_ROUNDSD,
20412 IX86_BUILTIN_ROUNDSS,
20414 IX86_BUILTIN_PTESTZ,
20415 IX86_BUILTIN_PTESTC,
20416 IX86_BUILTIN_PTESTNZC,
20418 IX86_BUILTIN_VEC_INIT_V2SI,
20419 IX86_BUILTIN_VEC_INIT_V4HI,
20420 IX86_BUILTIN_VEC_INIT_V8QI,
20421 IX86_BUILTIN_VEC_EXT_V2DF,
20422 IX86_BUILTIN_VEC_EXT_V2DI,
20423 IX86_BUILTIN_VEC_EXT_V4SF,
20424 IX86_BUILTIN_VEC_EXT_V4SI,
20425 IX86_BUILTIN_VEC_EXT_V8HI,
20426 IX86_BUILTIN_VEC_EXT_V2SI,
20427 IX86_BUILTIN_VEC_EXT_V4HI,
20428 IX86_BUILTIN_VEC_EXT_V16QI,
20429 IX86_BUILTIN_VEC_SET_V2DI,
20430 IX86_BUILTIN_VEC_SET_V4SF,
20431 IX86_BUILTIN_VEC_SET_V4SI,
20432 IX86_BUILTIN_VEC_SET_V8HI,
20433 IX86_BUILTIN_VEC_SET_V4HI,
20434 IX86_BUILTIN_VEC_SET_V16QI,
20436 IX86_BUILTIN_VEC_PACK_SFIX,
20439 IX86_BUILTIN_CRC32QI,
20440 IX86_BUILTIN_CRC32HI,
20441 IX86_BUILTIN_CRC32SI,
20442 IX86_BUILTIN_CRC32DI,
20444 IX86_BUILTIN_PCMPESTRI128,
20445 IX86_BUILTIN_PCMPESTRM128,
20446 IX86_BUILTIN_PCMPESTRA128,
20447 IX86_BUILTIN_PCMPESTRC128,
20448 IX86_BUILTIN_PCMPESTRO128,
20449 IX86_BUILTIN_PCMPESTRS128,
20450 IX86_BUILTIN_PCMPESTRZ128,
20451 IX86_BUILTIN_PCMPISTRI128,
20452 IX86_BUILTIN_PCMPISTRM128,
20453 IX86_BUILTIN_PCMPISTRA128,
20454 IX86_BUILTIN_PCMPISTRC128,
20455 IX86_BUILTIN_PCMPISTRO128,
20456 IX86_BUILTIN_PCMPISTRS128,
20457 IX86_BUILTIN_PCMPISTRZ128,
20459 IX86_BUILTIN_PCMPGTQ,
20461 /* AES instructions */
20462 IX86_BUILTIN_AESENC128,
20463 IX86_BUILTIN_AESENCLAST128,
20464 IX86_BUILTIN_AESDEC128,
20465 IX86_BUILTIN_AESDECLAST128,
20466 IX86_BUILTIN_AESIMC128,
20467 IX86_BUILTIN_AESKEYGENASSIST128,
20469 /* PCLMUL instruction */
20470 IX86_BUILTIN_PCLMULQDQ128,
20473 IX86_BUILTIN_ADDPD256,
20474 IX86_BUILTIN_ADDPS256,
20475 IX86_BUILTIN_ADDSUBPD256,
20476 IX86_BUILTIN_ADDSUBPS256,
20477 IX86_BUILTIN_ANDPD256,
20478 IX86_BUILTIN_ANDPS256,
20479 IX86_BUILTIN_ANDNPD256,
20480 IX86_BUILTIN_ANDNPS256,
20481 IX86_BUILTIN_BLENDPD256,
20482 IX86_BUILTIN_BLENDPS256,
20483 IX86_BUILTIN_BLENDVPD256,
20484 IX86_BUILTIN_BLENDVPS256,
20485 IX86_BUILTIN_DIVPD256,
20486 IX86_BUILTIN_DIVPS256,
20487 IX86_BUILTIN_DPPS256,
20488 IX86_BUILTIN_HADDPD256,
20489 IX86_BUILTIN_HADDPS256,
20490 IX86_BUILTIN_HSUBPD256,
20491 IX86_BUILTIN_HSUBPS256,
20492 IX86_BUILTIN_MAXPD256,
20493 IX86_BUILTIN_MAXPS256,
20494 IX86_BUILTIN_MINPD256,
20495 IX86_BUILTIN_MINPS256,
20496 IX86_BUILTIN_MULPD256,
20497 IX86_BUILTIN_MULPS256,
20498 IX86_BUILTIN_ORPD256,
20499 IX86_BUILTIN_ORPS256,
20500 IX86_BUILTIN_SHUFPD256,
20501 IX86_BUILTIN_SHUFPS256,
20502 IX86_BUILTIN_SUBPD256,
20503 IX86_BUILTIN_SUBPS256,
20504 IX86_BUILTIN_XORPD256,
20505 IX86_BUILTIN_XORPS256,
20506 IX86_BUILTIN_CMPSD,
20507 IX86_BUILTIN_CMPSS,
20508 IX86_BUILTIN_CMPPD,
20509 IX86_BUILTIN_CMPPS,
20510 IX86_BUILTIN_CMPPD256,
20511 IX86_BUILTIN_CMPPS256,
20512 IX86_BUILTIN_CVTDQ2PD256,
20513 IX86_BUILTIN_CVTDQ2PS256,
20514 IX86_BUILTIN_CVTPD2PS256,
20515 IX86_BUILTIN_CVTPS2DQ256,
20516 IX86_BUILTIN_CVTPS2PD256,
20517 IX86_BUILTIN_CVTTPD2DQ256,
20518 IX86_BUILTIN_CVTPD2DQ256,
20519 IX86_BUILTIN_CVTTPS2DQ256,
20520 IX86_BUILTIN_EXTRACTF128PD256,
20521 IX86_BUILTIN_EXTRACTF128PS256,
20522 IX86_BUILTIN_EXTRACTF128SI256,
20523 IX86_BUILTIN_VZEROALL,
20524 IX86_BUILTIN_VZEROUPPER,
20525 IX86_BUILTIN_VZEROUPPER_REX64,
20526 IX86_BUILTIN_VPERMILVARPD,
20527 IX86_BUILTIN_VPERMILVARPS,
20528 IX86_BUILTIN_VPERMILVARPD256,
20529 IX86_BUILTIN_VPERMILVARPS256,
20530 IX86_BUILTIN_VPERMILPD,
20531 IX86_BUILTIN_VPERMILPS,
20532 IX86_BUILTIN_VPERMILPD256,
20533 IX86_BUILTIN_VPERMILPS256,
20534 IX86_BUILTIN_VPERM2F128PD256,
20535 IX86_BUILTIN_VPERM2F128PS256,
20536 IX86_BUILTIN_VPERM2F128SI256,
20537 IX86_BUILTIN_VBROADCASTSS,
20538 IX86_BUILTIN_VBROADCASTSD256,
20539 IX86_BUILTIN_VBROADCASTSS256,
20540 IX86_BUILTIN_VBROADCASTPD256,
20541 IX86_BUILTIN_VBROADCASTPS256,
20542 IX86_BUILTIN_VINSERTF128PD256,
20543 IX86_BUILTIN_VINSERTF128PS256,
20544 IX86_BUILTIN_VINSERTF128SI256,
20545 IX86_BUILTIN_LOADUPD256,
20546 IX86_BUILTIN_LOADUPS256,
20547 IX86_BUILTIN_STOREUPD256,
20548 IX86_BUILTIN_STOREUPS256,
20549 IX86_BUILTIN_LDDQU256,
20550 IX86_BUILTIN_MOVNTDQ256,
20551 IX86_BUILTIN_MOVNTPD256,
20552 IX86_BUILTIN_MOVNTPS256,
20553 IX86_BUILTIN_LOADDQU256,
20554 IX86_BUILTIN_STOREDQU256,
20555 IX86_BUILTIN_MASKLOADPD,
20556 IX86_BUILTIN_MASKLOADPS,
20557 IX86_BUILTIN_MASKSTOREPD,
20558 IX86_BUILTIN_MASKSTOREPS,
20559 IX86_BUILTIN_MASKLOADPD256,
20560 IX86_BUILTIN_MASKLOADPS256,
20561 IX86_BUILTIN_MASKSTOREPD256,
20562 IX86_BUILTIN_MASKSTOREPS256,
20563 IX86_BUILTIN_MOVSHDUP256,
20564 IX86_BUILTIN_MOVSLDUP256,
20565 IX86_BUILTIN_MOVDDUP256,
20567 IX86_BUILTIN_SQRTPD256,
20568 IX86_BUILTIN_SQRTPS256,
20569 IX86_BUILTIN_SQRTPS_NR256,
20570 IX86_BUILTIN_RSQRTPS256,
20571 IX86_BUILTIN_RSQRTPS_NR256,
20573 IX86_BUILTIN_RCPPS256,
20575 IX86_BUILTIN_ROUNDPD256,
20576 IX86_BUILTIN_ROUNDPS256,
20578 IX86_BUILTIN_UNPCKHPD256,
20579 IX86_BUILTIN_UNPCKLPD256,
20580 IX86_BUILTIN_UNPCKHPS256,
20581 IX86_BUILTIN_UNPCKLPS256,
20583 IX86_BUILTIN_SI256_SI,
20584 IX86_BUILTIN_PS256_PS,
20585 IX86_BUILTIN_PD256_PD,
20586 IX86_BUILTIN_SI_SI256,
20587 IX86_BUILTIN_PS_PS256,
20588 IX86_BUILTIN_PD_PD256,
20590 IX86_BUILTIN_VTESTZPD,
20591 IX86_BUILTIN_VTESTCPD,
20592 IX86_BUILTIN_VTESTNZCPD,
20593 IX86_BUILTIN_VTESTZPS,
20594 IX86_BUILTIN_VTESTCPS,
20595 IX86_BUILTIN_VTESTNZCPS,
20596 IX86_BUILTIN_VTESTZPD256,
20597 IX86_BUILTIN_VTESTCPD256,
20598 IX86_BUILTIN_VTESTNZCPD256,
20599 IX86_BUILTIN_VTESTZPS256,
20600 IX86_BUILTIN_VTESTCPS256,
20601 IX86_BUILTIN_VTESTNZCPS256,
20602 IX86_BUILTIN_PTESTZ256,
20603 IX86_BUILTIN_PTESTC256,
20604 IX86_BUILTIN_PTESTNZC256,
20606 IX86_BUILTIN_MOVMSKPD256,
20607 IX86_BUILTIN_MOVMSKPS256,
20609 /* TFmode support builtins. */
20611 IX86_BUILTIN_HUGE_VALQ,
20612 IX86_BUILTIN_FABSQ,
20613 IX86_BUILTIN_COPYSIGNQ,
20615 /* Vectorizer support builtins. */
20616 IX86_BUILTIN_CPYSGNPS,
20617 IX86_BUILTIN_CPYSGNPD,
20619 IX86_BUILTIN_CVTUDQ2PS,
20624 /* Table for the ix86 builtin decls. */
20625 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20627 /* Table of all of the builtin functions that are possible with different ISA's
20628 but are waiting to be built until a function is declared to use that
20630 struct GTY(()) builtin_isa {
20631 tree type; /* builtin type to use in the declaration */
20632 const char *name; /* function name */
20633 int isa; /* isa_flags this builtin is defined for */
20634 bool const_p; /* true if the declaration is constant */
20637 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20640 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20641 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20642 * function decl in the ix86_builtins array. Returns the function decl or
20643 * NULL_TREE, if the builtin was not added.
20645 * If the front end has a special hook for builtin functions, delay adding
20646 * builtin functions that aren't in the current ISA until the ISA is changed
20647 * with function specific optimization. Doing so, can save about 300K for the
20648 * default compiler. When the builtin is expanded, check at that time whether
20651 * If the front end doesn't have a special hook, record all builtins, even if
20652 * it isn't an instruction set in the current ISA in case the user uses
20653 * function specific options for a different ISA, so that we don't get scope
20654 * errors if a builtin is added in the middle of a function scope. */
20657 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20659 tree decl = NULL_TREE;
20661 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20663 ix86_builtins_isa[(int) code].isa = mask;
20665 if ((mask & ix86_isa_flags) != 0
20666 || (lang_hooks.builtin_function
20667 == lang_hooks.builtin_function_ext_scope))
20670 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20672 ix86_builtins[(int) code] = decl;
20673 ix86_builtins_isa[(int) code].type = NULL_TREE;
20677 ix86_builtins[(int) code] = NULL_TREE;
20678 ix86_builtins_isa[(int) code].const_p = false;
20679 ix86_builtins_isa[(int) code].type = type;
20680 ix86_builtins_isa[(int) code].name = name;
20687 /* Like def_builtin, but also marks the function decl "const". */
20690 def_builtin_const (int mask, const char *name, tree type,
20691 enum ix86_builtins code)
20693 tree decl = def_builtin (mask, name, type, code);
20695 TREE_READONLY (decl) = 1;
20697 ix86_builtins_isa[(int) code].const_p = true;
20702 /* Add any new builtin functions for a given ISA that may not have been
20703 declared. This saves a bit of space compared to adding all of the
20704 declarations to the tree, even if we didn't use them. */
20707 ix86_add_new_builtins (int isa)
20712 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20714 if ((ix86_builtins_isa[i].isa & isa) != 0
20715 && ix86_builtins_isa[i].type != NULL_TREE)
20717 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20718 ix86_builtins_isa[i].type,
20719 i, BUILT_IN_MD, NULL,
20722 ix86_builtins[i] = decl;
20723 ix86_builtins_isa[i].type = NULL_TREE;
20724 if (ix86_builtins_isa[i].const_p)
20725 TREE_READONLY (decl) = 1;
20730 /* Bits for builtin_description.flag. */
20732 /* Set when we don't support the comparison natively, and should
20733 swap_comparison in order to support it. */
20734 #define BUILTIN_DESC_SWAP_OPERANDS 1
20736 struct builtin_description
20738 const unsigned int mask;
20739 const enum insn_code icode;
20740 const char *const name;
20741 const enum ix86_builtins code;
20742 const enum rtx_code comparison;
20746 static const struct builtin_description bdesc_comi[] =
20748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20774 static const struct builtin_description bdesc_pcmpestr[] =
20777 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20778 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20779 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20780 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20781 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20782 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20783 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20786 static const struct builtin_description bdesc_pcmpistr[] =
20789 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20790 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20791 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20794 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20795 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20798 /* Special builtin types */
20799 enum ix86_special_builtin_type
20801 SPECIAL_FTYPE_UNKNOWN,
20804 UINT64_FTYPE_PUNSIGNED,
20805 V32QI_FTYPE_PCCHAR,
20806 V16QI_FTYPE_PCCHAR,
20808 V8SF_FTYPE_PCFLOAT,
20810 V4DF_FTYPE_PCDOUBLE,
20811 V4SF_FTYPE_PCFLOAT,
20812 V2DF_FTYPE_PCDOUBLE,
20813 V8SF_FTYPE_PCV8SF_V8SF,
20814 V4DF_FTYPE_PCV4DF_V4DF,
20815 V4SF_FTYPE_V4SF_PCV2SF,
20816 V4SF_FTYPE_PCV4SF_V4SF,
20817 V2DF_FTYPE_V2DF_PCDOUBLE,
20818 V2DF_FTYPE_PCV2DF_V2DF,
20820 VOID_FTYPE_PV2SF_V4SF,
20821 VOID_FTYPE_PV4DI_V4DI,
20822 VOID_FTYPE_PV2DI_V2DI,
20823 VOID_FTYPE_PCHAR_V32QI,
20824 VOID_FTYPE_PCHAR_V16QI,
20825 VOID_FTYPE_PFLOAT_V8SF,
20826 VOID_FTYPE_PFLOAT_V4SF,
20827 VOID_FTYPE_PDOUBLE_V4DF,
20828 VOID_FTYPE_PDOUBLE_V2DF,
20830 VOID_FTYPE_PINT_INT,
20831 VOID_FTYPE_PV8SF_V8SF_V8SF,
20832 VOID_FTYPE_PV4DF_V4DF_V4DF,
20833 VOID_FTYPE_PV4SF_V4SF_V4SF,
20834 VOID_FTYPE_PV2DF_V2DF_V2DF
20837 /* Builtin types */
20838 enum ix86_builtin_type
20841 FLOAT128_FTYPE_FLOAT128,
20843 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20844 INT_FTYPE_V8SF_V8SF_PTEST,
20845 INT_FTYPE_V4DI_V4DI_PTEST,
20846 INT_FTYPE_V4DF_V4DF_PTEST,
20847 INT_FTYPE_V4SF_V4SF_PTEST,
20848 INT_FTYPE_V2DI_V2DI_PTEST,
20849 INT_FTYPE_V2DF_V2DF_PTEST,
20884 V4SF_FTYPE_V4SF_VEC_MERGE,
20893 V2DF_FTYPE_V2DF_VEC_MERGE,
20904 V16QI_FTYPE_V16QI_V16QI,
20905 V16QI_FTYPE_V8HI_V8HI,
20906 V8QI_FTYPE_V8QI_V8QI,
20907 V8QI_FTYPE_V4HI_V4HI,
20908 V8HI_FTYPE_V8HI_V8HI,
20909 V8HI_FTYPE_V8HI_V8HI_COUNT,
20910 V8HI_FTYPE_V16QI_V16QI,
20911 V8HI_FTYPE_V4SI_V4SI,
20912 V8HI_FTYPE_V8HI_SI_COUNT,
20913 V8SF_FTYPE_V8SF_V8SF,
20914 V8SF_FTYPE_V8SF_V8SI,
20915 V4SI_FTYPE_V4SI_V4SI,
20916 V4SI_FTYPE_V4SI_V4SI_COUNT,
20917 V4SI_FTYPE_V8HI_V8HI,
20918 V4SI_FTYPE_V4SF_V4SF,
20919 V4SI_FTYPE_V2DF_V2DF,
20920 V4SI_FTYPE_V4SI_SI_COUNT,
20921 V4HI_FTYPE_V4HI_V4HI,
20922 V4HI_FTYPE_V4HI_V4HI_COUNT,
20923 V4HI_FTYPE_V8QI_V8QI,
20924 V4HI_FTYPE_V2SI_V2SI,
20925 V4HI_FTYPE_V4HI_SI_COUNT,
20926 V4DF_FTYPE_V4DF_V4DF,
20927 V4DF_FTYPE_V4DF_V4DI,
20928 V4SF_FTYPE_V4SF_V4SF,
20929 V4SF_FTYPE_V4SF_V4SF_SWAP,
20930 V4SF_FTYPE_V4SF_V4SI,
20931 V4SF_FTYPE_V4SF_V2SI,
20932 V4SF_FTYPE_V4SF_V2DF,
20933 V4SF_FTYPE_V4SF_DI,
20934 V4SF_FTYPE_V4SF_SI,
20935 V2DI_FTYPE_V2DI_V2DI,
20936 V2DI_FTYPE_V2DI_V2DI_COUNT,
20937 V2DI_FTYPE_V16QI_V16QI,
20938 V2DI_FTYPE_V4SI_V4SI,
20939 V2DI_FTYPE_V2DI_V16QI,
20940 V2DI_FTYPE_V2DF_V2DF,
20941 V2DI_FTYPE_V2DI_SI_COUNT,
20942 V2SI_FTYPE_V2SI_V2SI,
20943 V2SI_FTYPE_V2SI_V2SI_COUNT,
20944 V2SI_FTYPE_V4HI_V4HI,
20945 V2SI_FTYPE_V2SF_V2SF,
20946 V2SI_FTYPE_V2SI_SI_COUNT,
20947 V2DF_FTYPE_V2DF_V2DF,
20948 V2DF_FTYPE_V2DF_V2DF_SWAP,
20949 V2DF_FTYPE_V2DF_V4SF,
20950 V2DF_FTYPE_V2DF_V2DI,
20951 V2DF_FTYPE_V2DF_DI,
20952 V2DF_FTYPE_V2DF_SI,
20953 V2SF_FTYPE_V2SF_V2SF,
20954 V1DI_FTYPE_V1DI_V1DI,
20955 V1DI_FTYPE_V1DI_V1DI_COUNT,
20956 V1DI_FTYPE_V8QI_V8QI,
20957 V1DI_FTYPE_V2SI_V2SI,
20958 V1DI_FTYPE_V1DI_SI_COUNT,
20959 UINT64_FTYPE_UINT64_UINT64,
20960 UINT_FTYPE_UINT_UINT,
20961 UINT_FTYPE_UINT_USHORT,
20962 UINT_FTYPE_UINT_UCHAR,
20963 UINT16_FTYPE_UINT16_INT,
20964 UINT8_FTYPE_UINT8_INT,
20965 V8HI_FTYPE_V8HI_INT,
20966 V4SI_FTYPE_V4SI_INT,
20967 V4HI_FTYPE_V4HI_INT,
20968 V8SF_FTYPE_V8SF_INT,
20969 V4SI_FTYPE_V8SI_INT,
20970 V4SF_FTYPE_V8SF_INT,
20971 V2DF_FTYPE_V4DF_INT,
20972 V4DF_FTYPE_V4DF_INT,
20973 V4SF_FTYPE_V4SF_INT,
20974 V2DI_FTYPE_V2DI_INT,
20975 V2DI2TI_FTYPE_V2DI_INT,
20976 V2DF_FTYPE_V2DF_INT,
20977 V16QI_FTYPE_V16QI_V16QI_V16QI,
20978 V8SF_FTYPE_V8SF_V8SF_V8SF,
20979 V4DF_FTYPE_V4DF_V4DF_V4DF,
20980 V4SF_FTYPE_V4SF_V4SF_V4SF,
20981 V2DF_FTYPE_V2DF_V2DF_V2DF,
20982 V16QI_FTYPE_V16QI_V16QI_INT,
20983 V8SI_FTYPE_V8SI_V8SI_INT,
20984 V8SI_FTYPE_V8SI_V4SI_INT,
20985 V8HI_FTYPE_V8HI_V8HI_INT,
20986 V8SF_FTYPE_V8SF_V8SF_INT,
20987 V8SF_FTYPE_V8SF_V4SF_INT,
20988 V4SI_FTYPE_V4SI_V4SI_INT,
20989 V4DF_FTYPE_V4DF_V4DF_INT,
20990 V4DF_FTYPE_V4DF_V2DF_INT,
20991 V4SF_FTYPE_V4SF_V4SF_INT,
20992 V2DI_FTYPE_V2DI_V2DI_INT,
20993 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20994 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20995 V2DF_FTYPE_V2DF_V2DF_INT,
20996 V2DI_FTYPE_V2DI_UINT_UINT,
20997 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21000 /* Special builtins with variable number of arguments. */
21001 static const struct builtin_description bdesc_special_args[] =
21003 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21004 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21010 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21022 /* SSE or 3DNow!A */
21023 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21024 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21029 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21041 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21047 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21048 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21053 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21083 /* Builtins with variable number of arguments. */
21084 static const struct builtin_description bdesc_args[] =
21086 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21087 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21088 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21089 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21090 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21091 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21092 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21096 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21097 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21098 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21099 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21103 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21105 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21106 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21108 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21109 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21159 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21160 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21161 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21162 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21164 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21165 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21166 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21167 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21168 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21169 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21170 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21171 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21172 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21173 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21174 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21175 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21176 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21177 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21178 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21181 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21182 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21183 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21184 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21185 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21186 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21191 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21192 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21193 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21195 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21196 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21197 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21198 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21200 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21202 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21204 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21205 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21206 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21236 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21237 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21241 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21243 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21244 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21246 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21256 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21258 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21260 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21262 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21264 /* SSE MMX or 3Dnow!A */
21265 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21266 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21267 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21269 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21270 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21271 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21272 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21274 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21275 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21277 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21299 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21300 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21307 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21308 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21309 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21337 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21341 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21343 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21344 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21346 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21354 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21356 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21357 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21359 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21370 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21375 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21378 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21390 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21391 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21392 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21408 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21417 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21421 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21422 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21423 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21424 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21425 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21426 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21427 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21430 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21431 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21432 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21433 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21434 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21435 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21437 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21438 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21439 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21440 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21448 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21449 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21451 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21454 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21455 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21458 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21459 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21461 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21462 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21463 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21464 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21465 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21466 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21469 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21470 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21471 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21472 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21473 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21474 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21476 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21477 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21478 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21479 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21480 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21481 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21482 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21483 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21484 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21485 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21486 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21506 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21507 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21508 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21509 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21510 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21511 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21512 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21513 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21514 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21515 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21517 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21518 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21519 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21520 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21521 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21522 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21523 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21545 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21546 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21547 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21548 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21550 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21551 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21552 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21555 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21556 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21557 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21558 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21559 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21562 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21563 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21564 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21565 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21568 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21569 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21571 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21572 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21573 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21574 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21577 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21594 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21595 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21596 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21597 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21598 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21599 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21600 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21601 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21602 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21603 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21604 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21605 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21651 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21653 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21655 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21695 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21696 in the current target ISA to allow the user to compile particular modules
21697 with different target specific options that differ from the command line
21700 ix86_init_mmx_sse_builtins (void)
21702 const struct builtin_description * d;
21705 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21706 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21707 tree V1DI_type_node
21708 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21709 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21710 tree V2DI_type_node
21711 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21712 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21713 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21714 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21715 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21716 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21717 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21719 tree pchar_type_node = build_pointer_type (char_type_node);
21720 tree pcchar_type_node
21721 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21722 tree pfloat_type_node = build_pointer_type (float_type_node);
21723 tree pcfloat_type_node
21724 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21725 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21726 tree pcv2sf_type_node
21727 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21728 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21729 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21732 tree int_ftype_v4sf_v4sf
21733 = build_function_type_list (integer_type_node,
21734 V4SF_type_node, V4SF_type_node, NULL_TREE);
21735 tree v4si_ftype_v4sf_v4sf
21736 = build_function_type_list (V4SI_type_node,
21737 V4SF_type_node, V4SF_type_node, NULL_TREE);
21738 /* MMX/SSE/integer conversions. */
21739 tree int_ftype_v4sf
21740 = build_function_type_list (integer_type_node,
21741 V4SF_type_node, NULL_TREE);
21742 tree int64_ftype_v4sf
21743 = build_function_type_list (long_long_integer_type_node,
21744 V4SF_type_node, NULL_TREE);
21745 tree int_ftype_v8qi
21746 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21747 tree v4sf_ftype_v4sf_int
21748 = build_function_type_list (V4SF_type_node,
21749 V4SF_type_node, integer_type_node, NULL_TREE);
21750 tree v4sf_ftype_v4sf_int64
21751 = build_function_type_list (V4SF_type_node,
21752 V4SF_type_node, long_long_integer_type_node,
21754 tree v4sf_ftype_v4sf_v2si
21755 = build_function_type_list (V4SF_type_node,
21756 V4SF_type_node, V2SI_type_node, NULL_TREE);
21758 /* Miscellaneous. */
21759 tree v8qi_ftype_v4hi_v4hi
21760 = build_function_type_list (V8QI_type_node,
21761 V4HI_type_node, V4HI_type_node, NULL_TREE);
21762 tree v4hi_ftype_v2si_v2si
21763 = build_function_type_list (V4HI_type_node,
21764 V2SI_type_node, V2SI_type_node, NULL_TREE);
21765 tree v4sf_ftype_v4sf_v4sf_int
21766 = build_function_type_list (V4SF_type_node,
21767 V4SF_type_node, V4SF_type_node,
21768 integer_type_node, NULL_TREE);
21769 tree v2si_ftype_v4hi_v4hi
21770 = build_function_type_list (V2SI_type_node,
21771 V4HI_type_node, V4HI_type_node, NULL_TREE);
21772 tree v4hi_ftype_v4hi_int
21773 = build_function_type_list (V4HI_type_node,
21774 V4HI_type_node, integer_type_node, NULL_TREE);
21775 tree v2si_ftype_v2si_int
21776 = build_function_type_list (V2SI_type_node,
21777 V2SI_type_node, integer_type_node, NULL_TREE);
21778 tree v1di_ftype_v1di_int
21779 = build_function_type_list (V1DI_type_node,
21780 V1DI_type_node, integer_type_node, NULL_TREE);
21782 tree void_ftype_void
21783 = build_function_type (void_type_node, void_list_node);
21784 tree void_ftype_unsigned
21785 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21786 tree void_ftype_unsigned_unsigned
21787 = build_function_type_list (void_type_node, unsigned_type_node,
21788 unsigned_type_node, NULL_TREE);
21789 tree void_ftype_pcvoid_unsigned_unsigned
21790 = build_function_type_list (void_type_node, const_ptr_type_node,
21791 unsigned_type_node, unsigned_type_node,
21793 tree unsigned_ftype_void
21794 = build_function_type (unsigned_type_node, void_list_node);
21795 tree v2si_ftype_v4sf
21796 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21797 /* Loads/stores. */
21798 tree void_ftype_v8qi_v8qi_pchar
21799 = build_function_type_list (void_type_node,
21800 V8QI_type_node, V8QI_type_node,
21801 pchar_type_node, NULL_TREE);
21802 tree v4sf_ftype_pcfloat
21803 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21804 tree v4sf_ftype_v4sf_pcv2sf
21805 = build_function_type_list (V4SF_type_node,
21806 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21807 tree void_ftype_pv2sf_v4sf
21808 = build_function_type_list (void_type_node,
21809 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21810 tree void_ftype_pfloat_v4sf
21811 = build_function_type_list (void_type_node,
21812 pfloat_type_node, V4SF_type_node, NULL_TREE);
21813 tree void_ftype_pdi_di
21814 = build_function_type_list (void_type_node,
21815 pdi_type_node, long_long_unsigned_type_node,
21817 tree void_ftype_pv2di_v2di
21818 = build_function_type_list (void_type_node,
21819 pv2di_type_node, V2DI_type_node, NULL_TREE);
21820 /* Normal vector unops. */
21821 tree v4sf_ftype_v4sf
21822 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21823 tree v16qi_ftype_v16qi
21824 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21825 tree v8hi_ftype_v8hi
21826 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21827 tree v4si_ftype_v4si
21828 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21829 tree v8qi_ftype_v8qi
21830 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21831 tree v4hi_ftype_v4hi
21832 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21834 /* Normal vector binops. */
21835 tree v4sf_ftype_v4sf_v4sf
21836 = build_function_type_list (V4SF_type_node,
21837 V4SF_type_node, V4SF_type_node, NULL_TREE);
21838 tree v8qi_ftype_v8qi_v8qi
21839 = build_function_type_list (V8QI_type_node,
21840 V8QI_type_node, V8QI_type_node, NULL_TREE);
21841 tree v4hi_ftype_v4hi_v4hi
21842 = build_function_type_list (V4HI_type_node,
21843 V4HI_type_node, V4HI_type_node, NULL_TREE);
21844 tree v2si_ftype_v2si_v2si
21845 = build_function_type_list (V2SI_type_node,
21846 V2SI_type_node, V2SI_type_node, NULL_TREE);
21847 tree v1di_ftype_v1di_v1di
21848 = build_function_type_list (V1DI_type_node,
21849 V1DI_type_node, V1DI_type_node, NULL_TREE);
21850 tree v1di_ftype_v1di_v1di_int
21851 = build_function_type_list (V1DI_type_node,
21852 V1DI_type_node, V1DI_type_node,
21853 integer_type_node, NULL_TREE);
21854 tree v2si_ftype_v2sf
21855 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21856 tree v2sf_ftype_v2si
21857 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21858 tree v2si_ftype_v2si
21859 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21860 tree v2sf_ftype_v2sf
21861 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21862 tree v2sf_ftype_v2sf_v2sf
21863 = build_function_type_list (V2SF_type_node,
21864 V2SF_type_node, V2SF_type_node, NULL_TREE);
21865 tree v2si_ftype_v2sf_v2sf
21866 = build_function_type_list (V2SI_type_node,
21867 V2SF_type_node, V2SF_type_node, NULL_TREE);
21868 tree pint_type_node = build_pointer_type (integer_type_node);
21869 tree pdouble_type_node = build_pointer_type (double_type_node);
21870 tree pcdouble_type_node = build_pointer_type (
21871 build_type_variant (double_type_node, 1, 0));
21872 tree int_ftype_v2df_v2df
21873 = build_function_type_list (integer_type_node,
21874 V2DF_type_node, V2DF_type_node, NULL_TREE);
21876 tree void_ftype_pcvoid
21877 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21878 tree v4sf_ftype_v4si
21879 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21880 tree v4si_ftype_v4sf
21881 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21882 tree v2df_ftype_v4si
21883 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21884 tree v4si_ftype_v2df
21885 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21886 tree v4si_ftype_v2df_v2df
21887 = build_function_type_list (V4SI_type_node,
21888 V2DF_type_node, V2DF_type_node, NULL_TREE);
21889 tree v2si_ftype_v2df
21890 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21891 tree v4sf_ftype_v2df
21892 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21893 tree v2df_ftype_v2si
21894 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21895 tree v2df_ftype_v4sf
21896 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21897 tree int_ftype_v2df
21898 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21899 tree int64_ftype_v2df
21900 = build_function_type_list (long_long_integer_type_node,
21901 V2DF_type_node, NULL_TREE);
21902 tree v2df_ftype_v2df_int
21903 = build_function_type_list (V2DF_type_node,
21904 V2DF_type_node, integer_type_node, NULL_TREE);
21905 tree v2df_ftype_v2df_int64
21906 = build_function_type_list (V2DF_type_node,
21907 V2DF_type_node, long_long_integer_type_node,
21909 tree v4sf_ftype_v4sf_v2df
21910 = build_function_type_list (V4SF_type_node,
21911 V4SF_type_node, V2DF_type_node, NULL_TREE);
21912 tree v2df_ftype_v2df_v4sf
21913 = build_function_type_list (V2DF_type_node,
21914 V2DF_type_node, V4SF_type_node, NULL_TREE);
21915 tree v2df_ftype_v2df_v2df_int
21916 = build_function_type_list (V2DF_type_node,
21917 V2DF_type_node, V2DF_type_node,
21920 tree v2df_ftype_v2df_pcdouble
21921 = build_function_type_list (V2DF_type_node,
21922 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21923 tree void_ftype_pdouble_v2df
21924 = build_function_type_list (void_type_node,
21925 pdouble_type_node, V2DF_type_node, NULL_TREE);
21926 tree void_ftype_pint_int
21927 = build_function_type_list (void_type_node,
21928 pint_type_node, integer_type_node, NULL_TREE);
21929 tree void_ftype_v16qi_v16qi_pchar
21930 = build_function_type_list (void_type_node,
21931 V16QI_type_node, V16QI_type_node,
21932 pchar_type_node, NULL_TREE);
21933 tree v2df_ftype_pcdouble
21934 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21935 tree v2df_ftype_v2df_v2df
21936 = build_function_type_list (V2DF_type_node,
21937 V2DF_type_node, V2DF_type_node, NULL_TREE);
21938 tree v16qi_ftype_v16qi_v16qi
21939 = build_function_type_list (V16QI_type_node,
21940 V16QI_type_node, V16QI_type_node, NULL_TREE);
21941 tree v8hi_ftype_v8hi_v8hi
21942 = build_function_type_list (V8HI_type_node,
21943 V8HI_type_node, V8HI_type_node, NULL_TREE);
21944 tree v4si_ftype_v4si_v4si
21945 = build_function_type_list (V4SI_type_node,
21946 V4SI_type_node, V4SI_type_node, NULL_TREE);
21947 tree v2di_ftype_v2di_v2di
21948 = build_function_type_list (V2DI_type_node,
21949 V2DI_type_node, V2DI_type_node, NULL_TREE);
21950 tree v2di_ftype_v2df_v2df
21951 = build_function_type_list (V2DI_type_node,
21952 V2DF_type_node, V2DF_type_node, NULL_TREE);
21953 tree v2df_ftype_v2df
21954 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
21955 tree v2di_ftype_v2di_int
21956 = build_function_type_list (V2DI_type_node,
21957 V2DI_type_node, integer_type_node, NULL_TREE);
21958 tree v2di_ftype_v2di_v2di_int
21959 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21960 V2DI_type_node, integer_type_node, NULL_TREE);
21961 tree v4si_ftype_v4si_int
21962 = build_function_type_list (V4SI_type_node,
21963 V4SI_type_node, integer_type_node, NULL_TREE);
21964 tree v8hi_ftype_v8hi_int
21965 = build_function_type_list (V8HI_type_node,
21966 V8HI_type_node, integer_type_node, NULL_TREE);
21967 tree v4si_ftype_v8hi_v8hi
21968 = build_function_type_list (V4SI_type_node,
21969 V8HI_type_node, V8HI_type_node, NULL_TREE);
21970 tree v1di_ftype_v8qi_v8qi
21971 = build_function_type_list (V1DI_type_node,
21972 V8QI_type_node, V8QI_type_node, NULL_TREE);
21973 tree v1di_ftype_v2si_v2si
21974 = build_function_type_list (V1DI_type_node,
21975 V2SI_type_node, V2SI_type_node, NULL_TREE);
21976 tree v2di_ftype_v16qi_v16qi
21977 = build_function_type_list (V2DI_type_node,
21978 V16QI_type_node, V16QI_type_node, NULL_TREE);
21979 tree v2di_ftype_v4si_v4si
21980 = build_function_type_list (V2DI_type_node,
21981 V4SI_type_node, V4SI_type_node, NULL_TREE);
21982 tree int_ftype_v16qi
21983 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
21984 tree v16qi_ftype_pcchar
21985 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
21986 tree void_ftype_pchar_v16qi
21987 = build_function_type_list (void_type_node,
21988 pchar_type_node, V16QI_type_node, NULL_TREE);
21990 tree v2di_ftype_v2di_unsigned_unsigned
21991 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21992 unsigned_type_node, unsigned_type_node,
21994 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21995 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
21996 unsigned_type_node, unsigned_type_node,
21998 tree v2di_ftype_v2di_v16qi
21999 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22001 tree v2df_ftype_v2df_v2df_v2df
22002 = build_function_type_list (V2DF_type_node,
22003 V2DF_type_node, V2DF_type_node,
22004 V2DF_type_node, NULL_TREE);
22005 tree v4sf_ftype_v4sf_v4sf_v4sf
22006 = build_function_type_list (V4SF_type_node,
22007 V4SF_type_node, V4SF_type_node,
22008 V4SF_type_node, NULL_TREE);
22009 tree v8hi_ftype_v16qi
22010 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22012 tree v4si_ftype_v16qi
22013 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22015 tree v2di_ftype_v16qi
22016 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22018 tree v4si_ftype_v8hi
22019 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22021 tree v2di_ftype_v8hi
22022 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22024 tree v2di_ftype_v4si
22025 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22027 tree v2di_ftype_pv2di
22028 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22030 tree v16qi_ftype_v16qi_v16qi_int
22031 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22032 V16QI_type_node, integer_type_node,
22034 tree v16qi_ftype_v16qi_v16qi_v16qi
22035 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22036 V16QI_type_node, V16QI_type_node,
22038 tree v8hi_ftype_v8hi_v8hi_int
22039 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22040 V8HI_type_node, integer_type_node,
22042 tree v4si_ftype_v4si_v4si_int
22043 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22044 V4SI_type_node, integer_type_node,
22046 tree int_ftype_v2di_v2di
22047 = build_function_type_list (integer_type_node,
22048 V2DI_type_node, V2DI_type_node,
22050 tree int_ftype_v16qi_int_v16qi_int_int
22051 = build_function_type_list (integer_type_node,
22058 tree v16qi_ftype_v16qi_int_v16qi_int_int
22059 = build_function_type_list (V16QI_type_node,
22066 tree int_ftype_v16qi_v16qi_int
22067 = build_function_type_list (integer_type_node,
22074 tree v2di_ftype_v2di
22075 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22077 tree v16qi_ftype_v8hi_v8hi
22078 = build_function_type_list (V16QI_type_node,
22079 V8HI_type_node, V8HI_type_node,
22081 tree v8hi_ftype_v4si_v4si
22082 = build_function_type_list (V8HI_type_node,
22083 V4SI_type_node, V4SI_type_node,
22085 tree v8hi_ftype_v16qi_v16qi
22086 = build_function_type_list (V8HI_type_node,
22087 V16QI_type_node, V16QI_type_node,
22089 tree v4hi_ftype_v8qi_v8qi
22090 = build_function_type_list (V4HI_type_node,
22091 V8QI_type_node, V8QI_type_node,
22093 tree unsigned_ftype_unsigned_uchar
22094 = build_function_type_list (unsigned_type_node,
22095 unsigned_type_node,
22096 unsigned_char_type_node,
22098 tree unsigned_ftype_unsigned_ushort
22099 = build_function_type_list (unsigned_type_node,
22100 unsigned_type_node,
22101 short_unsigned_type_node,
22103 tree unsigned_ftype_unsigned_unsigned
22104 = build_function_type_list (unsigned_type_node,
22105 unsigned_type_node,
22106 unsigned_type_node,
22108 tree uint64_ftype_uint64_uint64
22109 = build_function_type_list (long_long_unsigned_type_node,
22110 long_long_unsigned_type_node,
22111 long_long_unsigned_type_node,
22113 tree float_ftype_float
22114 = build_function_type_list (float_type_node,
22119 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22121 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22123 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22125 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22127 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22129 tree v8sf_ftype_v8sf
22130 = build_function_type_list (V8SF_type_node,
22133 tree v8si_ftype_v8sf
22134 = build_function_type_list (V8SI_type_node,
22137 tree v8sf_ftype_v8si
22138 = build_function_type_list (V8SF_type_node,
22141 tree v4si_ftype_v4df
22142 = build_function_type_list (V4SI_type_node,
22145 tree v4df_ftype_v4df
22146 = build_function_type_list (V4DF_type_node,
22149 tree v4df_ftype_v4si
22150 = build_function_type_list (V4DF_type_node,
22153 tree v4df_ftype_v4sf
22154 = build_function_type_list (V4DF_type_node,
22157 tree v4sf_ftype_v4df
22158 = build_function_type_list (V4SF_type_node,
22161 tree v8sf_ftype_v8sf_v8sf
22162 = build_function_type_list (V8SF_type_node,
22163 V8SF_type_node, V8SF_type_node,
22165 tree v4df_ftype_v4df_v4df
22166 = build_function_type_list (V4DF_type_node,
22167 V4DF_type_node, V4DF_type_node,
22169 tree v8sf_ftype_v8sf_int
22170 = build_function_type_list (V8SF_type_node,
22171 V8SF_type_node, integer_type_node,
22173 tree v4si_ftype_v8si_int
22174 = build_function_type_list (V4SI_type_node,
22175 V8SI_type_node, integer_type_node,
22177 tree v4df_ftype_v4df_int
22178 = build_function_type_list (V4DF_type_node,
22179 V4DF_type_node, integer_type_node,
22181 tree v4sf_ftype_v8sf_int
22182 = build_function_type_list (V4SF_type_node,
22183 V8SF_type_node, integer_type_node,
22185 tree v2df_ftype_v4df_int
22186 = build_function_type_list (V2DF_type_node,
22187 V4DF_type_node, integer_type_node,
22189 tree v8sf_ftype_v8sf_v8sf_int
22190 = build_function_type_list (V8SF_type_node,
22191 V8SF_type_node, V8SF_type_node,
22194 tree v8sf_ftype_v8sf_v8sf_v8sf
22195 = build_function_type_list (V8SF_type_node,
22196 V8SF_type_node, V8SF_type_node,
22199 tree v4df_ftype_v4df_v4df_v4df
22200 = build_function_type_list (V4DF_type_node,
22201 V4DF_type_node, V4DF_type_node,
22204 tree v8si_ftype_v8si_v8si_int
22205 = build_function_type_list (V8SI_type_node,
22206 V8SI_type_node, V8SI_type_node,
22209 tree v4df_ftype_v4df_v4df_int
22210 = build_function_type_list (V4DF_type_node,
22211 V4DF_type_node, V4DF_type_node,
22214 tree v8sf_ftype_pcfloat
22215 = build_function_type_list (V8SF_type_node,
22218 tree v4df_ftype_pcdouble
22219 = build_function_type_list (V4DF_type_node,
22220 pcdouble_type_node,
22222 tree pcv4sf_type_node
22223 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22224 tree pcv2df_type_node
22225 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22226 tree v8sf_ftype_pcv4sf
22227 = build_function_type_list (V8SF_type_node,
22230 tree v4df_ftype_pcv2df
22231 = build_function_type_list (V4DF_type_node,
22234 tree v32qi_ftype_pcchar
22235 = build_function_type_list (V32QI_type_node,
22238 tree void_ftype_pchar_v32qi
22239 = build_function_type_list (void_type_node,
22240 pchar_type_node, V32QI_type_node,
22242 tree v8si_ftype_v8si_v4si_int
22243 = build_function_type_list (V8SI_type_node,
22244 V8SI_type_node, V4SI_type_node,
22247 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22248 tree void_ftype_pv4di_v4di
22249 = build_function_type_list (void_type_node,
22250 pv4di_type_node, V4DI_type_node,
22252 tree v8sf_ftype_v8sf_v4sf_int
22253 = build_function_type_list (V8SF_type_node,
22254 V8SF_type_node, V4SF_type_node,
22257 tree v4df_ftype_v4df_v2df_int
22258 = build_function_type_list (V4DF_type_node,
22259 V4DF_type_node, V2DF_type_node,
22262 tree void_ftype_pfloat_v8sf
22263 = build_function_type_list (void_type_node,
22264 pfloat_type_node, V8SF_type_node,
22266 tree void_ftype_pdouble_v4df
22267 = build_function_type_list (void_type_node,
22268 pdouble_type_node, V4DF_type_node,
22270 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22271 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22272 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22273 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22274 tree pcv8sf_type_node
22275 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22276 tree pcv4df_type_node
22277 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22278 tree v8sf_ftype_pcv8sf_v8sf
22279 = build_function_type_list (V8SF_type_node,
22280 pcv8sf_type_node, V8SF_type_node,
22282 tree v4df_ftype_pcv4df_v4df
22283 = build_function_type_list (V4DF_type_node,
22284 pcv4df_type_node, V4DF_type_node,
22286 tree v4sf_ftype_pcv4sf_v4sf
22287 = build_function_type_list (V4SF_type_node,
22288 pcv4sf_type_node, V4SF_type_node,
22290 tree v2df_ftype_pcv2df_v2df
22291 = build_function_type_list (V2DF_type_node,
22292 pcv2df_type_node, V2DF_type_node,
22294 tree void_ftype_pv8sf_v8sf_v8sf
22295 = build_function_type_list (void_type_node,
22296 pv8sf_type_node, V8SF_type_node,
22299 tree void_ftype_pv4df_v4df_v4df
22300 = build_function_type_list (void_type_node,
22301 pv4df_type_node, V4DF_type_node,
22304 tree void_ftype_pv4sf_v4sf_v4sf
22305 = build_function_type_list (void_type_node,
22306 pv4sf_type_node, V4SF_type_node,
22309 tree void_ftype_pv2df_v2df_v2df
22310 = build_function_type_list (void_type_node,
22311 pv2df_type_node, V2DF_type_node,
22314 tree v4df_ftype_v2df
22315 = build_function_type_list (V4DF_type_node,
22318 tree v8sf_ftype_v4sf
22319 = build_function_type_list (V8SF_type_node,
22322 tree v8si_ftype_v4si
22323 = build_function_type_list (V8SI_type_node,
22326 tree v2df_ftype_v4df
22327 = build_function_type_list (V2DF_type_node,
22330 tree v4sf_ftype_v8sf
22331 = build_function_type_list (V4SF_type_node,
22334 tree v4si_ftype_v8si
22335 = build_function_type_list (V4SI_type_node,
22338 tree int_ftype_v4df
22339 = build_function_type_list (integer_type_node,
22342 tree int_ftype_v8sf
22343 = build_function_type_list (integer_type_node,
22346 tree int_ftype_v8sf_v8sf
22347 = build_function_type_list (integer_type_node,
22348 V8SF_type_node, V8SF_type_node,
22350 tree int_ftype_v4di_v4di
22351 = build_function_type_list (integer_type_node,
22352 V4DI_type_node, V4DI_type_node,
22354 tree int_ftype_v4df_v4df
22355 = build_function_type_list (integer_type_node,
22356 V4DF_type_node, V4DF_type_node,
22358 tree v8sf_ftype_v8sf_v8si
22359 = build_function_type_list (V8SF_type_node,
22360 V8SF_type_node, V8SI_type_node,
22362 tree v4df_ftype_v4df_v4di
22363 = build_function_type_list (V4DF_type_node,
22364 V4DF_type_node, V4DI_type_node,
22366 tree v4sf_ftype_v4sf_v4si
22367 = build_function_type_list (V4SF_type_node,
22368 V4SF_type_node, V4SI_type_node, NULL_TREE);
22369 tree v2df_ftype_v2df_v2di
22370 = build_function_type_list (V2DF_type_node,
22371 V2DF_type_node, V2DI_type_node, NULL_TREE);
22373 /* Integer intrinsics. */
22374 tree uint64_ftype_void
22375 = build_function_type (long_long_unsigned_type_node,
22378 = build_function_type_list (integer_type_node,
22379 integer_type_node, NULL_TREE);
22380 tree int64_ftype_int64
22381 = build_function_type_list (long_long_integer_type_node,
22382 long_long_integer_type_node,
22384 tree uint64_ftype_int
22385 = build_function_type_list (long_long_unsigned_type_node,
22386 integer_type_node, NULL_TREE);
22387 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
22388 tree uint64_ftype_punsigned
22389 = build_function_type_list (long_long_unsigned_type_node,
22390 punsigned_type_node, NULL_TREE);
22391 tree ushort_ftype_ushort_int
22392 = build_function_type_list (short_unsigned_type_node,
22393 short_unsigned_type_node,
22396 tree uchar_ftype_uchar_int
22397 = build_function_type_list (unsigned_char_type_node,
22398 unsigned_char_type_node,
22404 /* Add all special builtins with variable number of operands. */
22405 for (i = 0, d = bdesc_special_args;
22406 i < ARRAY_SIZE (bdesc_special_args);
22414 switch ((enum ix86_special_builtin_type) d->flag)
22416 case VOID_FTYPE_VOID:
22417 type = void_ftype_void;
22419 case UINT64_FTYPE_VOID:
22420 type = uint64_ftype_void;
22422 case UINT64_FTYPE_PUNSIGNED:
22423 type = uint64_ftype_punsigned;
22425 case V32QI_FTYPE_PCCHAR:
22426 type = v32qi_ftype_pcchar;
22428 case V16QI_FTYPE_PCCHAR:
22429 type = v16qi_ftype_pcchar;
22431 case V8SF_FTYPE_PCV4SF:
22432 type = v8sf_ftype_pcv4sf;
22434 case V8SF_FTYPE_PCFLOAT:
22435 type = v8sf_ftype_pcfloat;
22437 case V4DF_FTYPE_PCV2DF:
22438 type = v4df_ftype_pcv2df;
22440 case V4DF_FTYPE_PCDOUBLE:
22441 type = v4df_ftype_pcdouble;
22443 case V4SF_FTYPE_PCFLOAT:
22444 type = v4sf_ftype_pcfloat;
22446 case V2DI_FTYPE_PV2DI:
22447 type = v2di_ftype_pv2di;
22449 case V2DF_FTYPE_PCDOUBLE:
22450 type = v2df_ftype_pcdouble;
22452 case V8SF_FTYPE_PCV8SF_V8SF:
22453 type = v8sf_ftype_pcv8sf_v8sf;
22455 case V4DF_FTYPE_PCV4DF_V4DF:
22456 type = v4df_ftype_pcv4df_v4df;
22458 case V4SF_FTYPE_V4SF_PCV2SF:
22459 type = v4sf_ftype_v4sf_pcv2sf;
22461 case V4SF_FTYPE_PCV4SF_V4SF:
22462 type = v4sf_ftype_pcv4sf_v4sf;
22464 case V2DF_FTYPE_V2DF_PCDOUBLE:
22465 type = v2df_ftype_v2df_pcdouble;
22467 case V2DF_FTYPE_PCV2DF_V2DF:
22468 type = v2df_ftype_pcv2df_v2df;
22470 case VOID_FTYPE_PV2SF_V4SF:
22471 type = void_ftype_pv2sf_v4sf;
22473 case VOID_FTYPE_PV4DI_V4DI:
22474 type = void_ftype_pv4di_v4di;
22476 case VOID_FTYPE_PV2DI_V2DI:
22477 type = void_ftype_pv2di_v2di;
22479 case VOID_FTYPE_PCHAR_V32QI:
22480 type = void_ftype_pchar_v32qi;
22482 case VOID_FTYPE_PCHAR_V16QI:
22483 type = void_ftype_pchar_v16qi;
22485 case VOID_FTYPE_PFLOAT_V8SF:
22486 type = void_ftype_pfloat_v8sf;
22488 case VOID_FTYPE_PFLOAT_V4SF:
22489 type = void_ftype_pfloat_v4sf;
22491 case VOID_FTYPE_PDOUBLE_V4DF:
22492 type = void_ftype_pdouble_v4df;
22494 case VOID_FTYPE_PDOUBLE_V2DF:
22495 type = void_ftype_pdouble_v2df;
22497 case VOID_FTYPE_PDI_DI:
22498 type = void_ftype_pdi_di;
22500 case VOID_FTYPE_PINT_INT:
22501 type = void_ftype_pint_int;
22503 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22504 type = void_ftype_pv8sf_v8sf_v8sf;
22506 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22507 type = void_ftype_pv4df_v4df_v4df;
22509 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22510 type = void_ftype_pv4sf_v4sf_v4sf;
22512 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22513 type = void_ftype_pv2df_v2df_v2df;
22516 gcc_unreachable ();
22519 def_builtin (d->mask, d->name, type, d->code);
22522 /* Add all builtins with variable number of operands. */
22523 for (i = 0, d = bdesc_args;
22524 i < ARRAY_SIZE (bdesc_args);
22532 switch ((enum ix86_builtin_type) d->flag)
22534 case FLOAT_FTYPE_FLOAT:
22535 type = float_ftype_float;
22537 case INT_FTYPE_V8SF_V8SF_PTEST:
22538 type = int_ftype_v8sf_v8sf;
22540 case INT_FTYPE_V4DI_V4DI_PTEST:
22541 type = int_ftype_v4di_v4di;
22543 case INT_FTYPE_V4DF_V4DF_PTEST:
22544 type = int_ftype_v4df_v4df;
22546 case INT_FTYPE_V4SF_V4SF_PTEST:
22547 type = int_ftype_v4sf_v4sf;
22549 case INT_FTYPE_V2DI_V2DI_PTEST:
22550 type = int_ftype_v2di_v2di;
22552 case INT_FTYPE_V2DF_V2DF_PTEST:
22553 type = int_ftype_v2df_v2df;
22555 case INT_FTYPE_INT:
22556 type = int_ftype_int;
22558 case UINT64_FTYPE_INT:
22559 type = uint64_ftype_int;
22561 case INT64_FTYPE_INT64:
22562 type = int64_ftype_int64;
22564 case INT64_FTYPE_V4SF:
22565 type = int64_ftype_v4sf;
22567 case INT64_FTYPE_V2DF:
22568 type = int64_ftype_v2df;
22570 case INT_FTYPE_V16QI:
22571 type = int_ftype_v16qi;
22573 case INT_FTYPE_V8QI:
22574 type = int_ftype_v8qi;
22576 case INT_FTYPE_V8SF:
22577 type = int_ftype_v8sf;
22579 case INT_FTYPE_V4DF:
22580 type = int_ftype_v4df;
22582 case INT_FTYPE_V4SF:
22583 type = int_ftype_v4sf;
22585 case INT_FTYPE_V2DF:
22586 type = int_ftype_v2df;
22588 case V16QI_FTYPE_V16QI:
22589 type = v16qi_ftype_v16qi;
22591 case V8SI_FTYPE_V8SF:
22592 type = v8si_ftype_v8sf;
22594 case V8SI_FTYPE_V4SI:
22595 type = v8si_ftype_v4si;
22597 case V8HI_FTYPE_V8HI:
22598 type = v8hi_ftype_v8hi;
22600 case V8HI_FTYPE_V16QI:
22601 type = v8hi_ftype_v16qi;
22603 case V8QI_FTYPE_V8QI:
22604 type = v8qi_ftype_v8qi;
22606 case V8SF_FTYPE_V8SF:
22607 type = v8sf_ftype_v8sf;
22609 case V8SF_FTYPE_V8SI:
22610 type = v8sf_ftype_v8si;
22612 case V8SF_FTYPE_V4SF:
22613 type = v8sf_ftype_v4sf;
22615 case V4SI_FTYPE_V4DF:
22616 type = v4si_ftype_v4df;
22618 case V4SI_FTYPE_V4SI:
22619 type = v4si_ftype_v4si;
22621 case V4SI_FTYPE_V16QI:
22622 type = v4si_ftype_v16qi;
22624 case V4SI_FTYPE_V8SI:
22625 type = v4si_ftype_v8si;
22627 case V4SI_FTYPE_V8HI:
22628 type = v4si_ftype_v8hi;
22630 case V4SI_FTYPE_V4SF:
22631 type = v4si_ftype_v4sf;
22633 case V4SI_FTYPE_V2DF:
22634 type = v4si_ftype_v2df;
22636 case V4HI_FTYPE_V4HI:
22637 type = v4hi_ftype_v4hi;
22639 case V4DF_FTYPE_V4DF:
22640 type = v4df_ftype_v4df;
22642 case V4DF_FTYPE_V4SI:
22643 type = v4df_ftype_v4si;
22645 case V4DF_FTYPE_V4SF:
22646 type = v4df_ftype_v4sf;
22648 case V4DF_FTYPE_V2DF:
22649 type = v4df_ftype_v2df;
22651 case V4SF_FTYPE_V4SF:
22652 case V4SF_FTYPE_V4SF_VEC_MERGE:
22653 type = v4sf_ftype_v4sf;
22655 case V4SF_FTYPE_V8SF:
22656 type = v4sf_ftype_v8sf;
22658 case V4SF_FTYPE_V4SI:
22659 type = v4sf_ftype_v4si;
22661 case V4SF_FTYPE_V4DF:
22662 type = v4sf_ftype_v4df;
22664 case V4SF_FTYPE_V2DF:
22665 type = v4sf_ftype_v2df;
22667 case V2DI_FTYPE_V2DI:
22668 type = v2di_ftype_v2di;
22670 case V2DI_FTYPE_V16QI:
22671 type = v2di_ftype_v16qi;
22673 case V2DI_FTYPE_V8HI:
22674 type = v2di_ftype_v8hi;
22676 case V2DI_FTYPE_V4SI:
22677 type = v2di_ftype_v4si;
22679 case V2SI_FTYPE_V2SI:
22680 type = v2si_ftype_v2si;
22682 case V2SI_FTYPE_V4SF:
22683 type = v2si_ftype_v4sf;
22685 case V2SI_FTYPE_V2DF:
22686 type = v2si_ftype_v2df;
22688 case V2SI_FTYPE_V2SF:
22689 type = v2si_ftype_v2sf;
22691 case V2DF_FTYPE_V4DF:
22692 type = v2df_ftype_v4df;
22694 case V2DF_FTYPE_V4SF:
22695 type = v2df_ftype_v4sf;
22697 case V2DF_FTYPE_V2DF:
22698 case V2DF_FTYPE_V2DF_VEC_MERGE:
22699 type = v2df_ftype_v2df;
22701 case V2DF_FTYPE_V2SI:
22702 type = v2df_ftype_v2si;
22704 case V2DF_FTYPE_V4SI:
22705 type = v2df_ftype_v4si;
22707 case V2SF_FTYPE_V2SF:
22708 type = v2sf_ftype_v2sf;
22710 case V2SF_FTYPE_V2SI:
22711 type = v2sf_ftype_v2si;
22713 case V16QI_FTYPE_V16QI_V16QI:
22714 type = v16qi_ftype_v16qi_v16qi;
22716 case V16QI_FTYPE_V8HI_V8HI:
22717 type = v16qi_ftype_v8hi_v8hi;
22719 case V8QI_FTYPE_V8QI_V8QI:
22720 type = v8qi_ftype_v8qi_v8qi;
22722 case V8QI_FTYPE_V4HI_V4HI:
22723 type = v8qi_ftype_v4hi_v4hi;
22725 case V8HI_FTYPE_V8HI_V8HI:
22726 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22727 type = v8hi_ftype_v8hi_v8hi;
22729 case V8HI_FTYPE_V16QI_V16QI:
22730 type = v8hi_ftype_v16qi_v16qi;
22732 case V8HI_FTYPE_V4SI_V4SI:
22733 type = v8hi_ftype_v4si_v4si;
22735 case V8HI_FTYPE_V8HI_SI_COUNT:
22736 type = v8hi_ftype_v8hi_int;
22738 case V8SF_FTYPE_V8SF_V8SF:
22739 type = v8sf_ftype_v8sf_v8sf;
22741 case V8SF_FTYPE_V8SF_V8SI:
22742 type = v8sf_ftype_v8sf_v8si;
22744 case V4SI_FTYPE_V4SI_V4SI:
22745 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22746 type = v4si_ftype_v4si_v4si;
22748 case V4SI_FTYPE_V8HI_V8HI:
22749 type = v4si_ftype_v8hi_v8hi;
22751 case V4SI_FTYPE_V4SF_V4SF:
22752 type = v4si_ftype_v4sf_v4sf;
22754 case V4SI_FTYPE_V2DF_V2DF:
22755 type = v4si_ftype_v2df_v2df;
22757 case V4SI_FTYPE_V4SI_SI_COUNT:
22758 type = v4si_ftype_v4si_int;
22760 case V4HI_FTYPE_V4HI_V4HI:
22761 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22762 type = v4hi_ftype_v4hi_v4hi;
22764 case V4HI_FTYPE_V8QI_V8QI:
22765 type = v4hi_ftype_v8qi_v8qi;
22767 case V4HI_FTYPE_V2SI_V2SI:
22768 type = v4hi_ftype_v2si_v2si;
22770 case V4HI_FTYPE_V4HI_SI_COUNT:
22771 type = v4hi_ftype_v4hi_int;
22773 case V4DF_FTYPE_V4DF_V4DF:
22774 type = v4df_ftype_v4df_v4df;
22776 case V4DF_FTYPE_V4DF_V4DI:
22777 type = v4df_ftype_v4df_v4di;
22779 case V4SF_FTYPE_V4SF_V4SF:
22780 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22781 type = v4sf_ftype_v4sf_v4sf;
22783 case V4SF_FTYPE_V4SF_V4SI:
22784 type = v4sf_ftype_v4sf_v4si;
22786 case V4SF_FTYPE_V4SF_V2SI:
22787 type = v4sf_ftype_v4sf_v2si;
22789 case V4SF_FTYPE_V4SF_V2DF:
22790 type = v4sf_ftype_v4sf_v2df;
22792 case V4SF_FTYPE_V4SF_DI:
22793 type = v4sf_ftype_v4sf_int64;
22795 case V4SF_FTYPE_V4SF_SI:
22796 type = v4sf_ftype_v4sf_int;
22798 case V2DI_FTYPE_V2DI_V2DI:
22799 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22800 type = v2di_ftype_v2di_v2di;
22802 case V2DI_FTYPE_V16QI_V16QI:
22803 type = v2di_ftype_v16qi_v16qi;
22805 case V2DI_FTYPE_V4SI_V4SI:
22806 type = v2di_ftype_v4si_v4si;
22808 case V2DI_FTYPE_V2DI_V16QI:
22809 type = v2di_ftype_v2di_v16qi;
22811 case V2DI_FTYPE_V2DF_V2DF:
22812 type = v2di_ftype_v2df_v2df;
22814 case V2DI_FTYPE_V2DI_SI_COUNT:
22815 type = v2di_ftype_v2di_int;
22817 case V2SI_FTYPE_V2SI_V2SI:
22818 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22819 type = v2si_ftype_v2si_v2si;
22821 case V2SI_FTYPE_V4HI_V4HI:
22822 type = v2si_ftype_v4hi_v4hi;
22824 case V2SI_FTYPE_V2SF_V2SF:
22825 type = v2si_ftype_v2sf_v2sf;
22827 case V2SI_FTYPE_V2SI_SI_COUNT:
22828 type = v2si_ftype_v2si_int;
22830 case V2DF_FTYPE_V2DF_V2DF:
22831 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22832 type = v2df_ftype_v2df_v2df;
22834 case V2DF_FTYPE_V2DF_V4SF:
22835 type = v2df_ftype_v2df_v4sf;
22837 case V2DF_FTYPE_V2DF_V2DI:
22838 type = v2df_ftype_v2df_v2di;
22840 case V2DF_FTYPE_V2DF_DI:
22841 type = v2df_ftype_v2df_int64;
22843 case V2DF_FTYPE_V2DF_SI:
22844 type = v2df_ftype_v2df_int;
22846 case V2SF_FTYPE_V2SF_V2SF:
22847 type = v2sf_ftype_v2sf_v2sf;
22849 case V1DI_FTYPE_V1DI_V1DI:
22850 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22851 type = v1di_ftype_v1di_v1di;
22853 case V1DI_FTYPE_V8QI_V8QI:
22854 type = v1di_ftype_v8qi_v8qi;
22856 case V1DI_FTYPE_V2SI_V2SI:
22857 type = v1di_ftype_v2si_v2si;
22859 case V1DI_FTYPE_V1DI_SI_COUNT:
22860 type = v1di_ftype_v1di_int;
22862 case UINT64_FTYPE_UINT64_UINT64:
22863 type = uint64_ftype_uint64_uint64;
22865 case UINT_FTYPE_UINT_UINT:
22866 type = unsigned_ftype_unsigned_unsigned;
22868 case UINT_FTYPE_UINT_USHORT:
22869 type = unsigned_ftype_unsigned_ushort;
22871 case UINT_FTYPE_UINT_UCHAR:
22872 type = unsigned_ftype_unsigned_uchar;
22874 case UINT16_FTYPE_UINT16_INT:
22875 type = ushort_ftype_ushort_int;
22877 case UINT8_FTYPE_UINT8_INT:
22878 type = uchar_ftype_uchar_int;
22880 case V8HI_FTYPE_V8HI_INT:
22881 type = v8hi_ftype_v8hi_int;
22883 case V8SF_FTYPE_V8SF_INT:
22884 type = v8sf_ftype_v8sf_int;
22886 case V4SI_FTYPE_V4SI_INT:
22887 type = v4si_ftype_v4si_int;
22889 case V4SI_FTYPE_V8SI_INT:
22890 type = v4si_ftype_v8si_int;
22892 case V4HI_FTYPE_V4HI_INT:
22893 type = v4hi_ftype_v4hi_int;
22895 case V4DF_FTYPE_V4DF_INT:
22896 type = v4df_ftype_v4df_int;
22898 case V4SF_FTYPE_V4SF_INT:
22899 type = v4sf_ftype_v4sf_int;
22901 case V4SF_FTYPE_V8SF_INT:
22902 type = v4sf_ftype_v8sf_int;
22904 case V2DI_FTYPE_V2DI_INT:
22905 case V2DI2TI_FTYPE_V2DI_INT:
22906 type = v2di_ftype_v2di_int;
22908 case V2DF_FTYPE_V2DF_INT:
22909 type = v2df_ftype_v2df_int;
22911 case V2DF_FTYPE_V4DF_INT:
22912 type = v2df_ftype_v4df_int;
22914 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22915 type = v16qi_ftype_v16qi_v16qi_v16qi;
22917 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22918 type = v8sf_ftype_v8sf_v8sf_v8sf;
22920 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22921 type = v4df_ftype_v4df_v4df_v4df;
22923 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22924 type = v4sf_ftype_v4sf_v4sf_v4sf;
22926 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22927 type = v2df_ftype_v2df_v2df_v2df;
22929 case V16QI_FTYPE_V16QI_V16QI_INT:
22930 type = v16qi_ftype_v16qi_v16qi_int;
22932 case V8SI_FTYPE_V8SI_V8SI_INT:
22933 type = v8si_ftype_v8si_v8si_int;
22935 case V8SI_FTYPE_V8SI_V4SI_INT:
22936 type = v8si_ftype_v8si_v4si_int;
22938 case V8HI_FTYPE_V8HI_V8HI_INT:
22939 type = v8hi_ftype_v8hi_v8hi_int;
22941 case V8SF_FTYPE_V8SF_V8SF_INT:
22942 type = v8sf_ftype_v8sf_v8sf_int;
22944 case V8SF_FTYPE_V8SF_V4SF_INT:
22945 type = v8sf_ftype_v8sf_v4sf_int;
22947 case V4SI_FTYPE_V4SI_V4SI_INT:
22948 type = v4si_ftype_v4si_v4si_int;
22950 case V4DF_FTYPE_V4DF_V4DF_INT:
22951 type = v4df_ftype_v4df_v4df_int;
22953 case V4DF_FTYPE_V4DF_V2DF_INT:
22954 type = v4df_ftype_v4df_v2df_int;
22956 case V4SF_FTYPE_V4SF_V4SF_INT:
22957 type = v4sf_ftype_v4sf_v4sf_int;
22959 case V2DI_FTYPE_V2DI_V2DI_INT:
22960 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
22961 type = v2di_ftype_v2di_v2di_int;
22963 case V2DF_FTYPE_V2DF_V2DF_INT:
22964 type = v2df_ftype_v2df_v2df_int;
22966 case V2DI_FTYPE_V2DI_UINT_UINT:
22967 type = v2di_ftype_v2di_unsigned_unsigned;
22969 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
22970 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
22972 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
22973 type = v1di_ftype_v1di_v1di_int;
22976 gcc_unreachable ();
22979 def_builtin_const (d->mask, d->name, type, d->code);
22982 /* pcmpestr[im] insns. */
22983 for (i = 0, d = bdesc_pcmpestr;
22984 i < ARRAY_SIZE (bdesc_pcmpestr);
22987 if (d->code == IX86_BUILTIN_PCMPESTRM128)
22988 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
22990 ftype = int_ftype_v16qi_int_v16qi_int_int;
22991 def_builtin_const (d->mask, d->name, ftype, d->code);
22994 /* pcmpistr[im] insns. */
22995 for (i = 0, d = bdesc_pcmpistr;
22996 i < ARRAY_SIZE (bdesc_pcmpistr);
22999 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23000 ftype = v16qi_ftype_v16qi_v16qi_int;
23002 ftype = int_ftype_v16qi_v16qi_int;
23003 def_builtin_const (d->mask, d->name, ftype, d->code);
23006 /* comi/ucomi insns. */
23007 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23008 if (d->mask == OPTION_MASK_ISA_SSE2)
23009 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23011 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23014 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23015 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23017 /* SSE or 3DNow!A */
23018 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23021 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23023 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23024 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23027 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23028 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23031 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23032 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23033 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23034 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23035 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23036 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23039 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23042 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23043 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23045 /* Access to the vec_init patterns. */
23046 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23047 integer_type_node, NULL_TREE);
23048 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23050 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23051 short_integer_type_node,
23052 short_integer_type_node,
23053 short_integer_type_node, NULL_TREE);
23054 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23056 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23057 char_type_node, char_type_node,
23058 char_type_node, char_type_node,
23059 char_type_node, char_type_node,
23060 char_type_node, NULL_TREE);
23061 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23063 /* Access to the vec_extract patterns. */
23064 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23065 integer_type_node, NULL_TREE);
23066 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23068 ftype = build_function_type_list (long_long_integer_type_node,
23069 V2DI_type_node, integer_type_node,
23071 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23073 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23074 integer_type_node, NULL_TREE);
23075 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23077 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23078 integer_type_node, NULL_TREE);
23079 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23081 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23082 integer_type_node, NULL_TREE);
23083 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23085 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23086 integer_type_node, NULL_TREE);
23087 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23089 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23090 integer_type_node, NULL_TREE);
23091 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23093 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23094 integer_type_node, NULL_TREE);
23095 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23097 /* Access to the vec_set patterns. */
23098 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23100 integer_type_node, NULL_TREE);
23101 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23103 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23105 integer_type_node, NULL_TREE);
23106 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23108 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23110 integer_type_node, NULL_TREE);
23111 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23113 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23115 integer_type_node, NULL_TREE);
23116 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23118 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23120 integer_type_node, NULL_TREE);
23121 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23123 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23125 integer_type_node, NULL_TREE);
23126 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23129 /* Internal method for ix86_init_builtins. */
23132 ix86_init_builtins_va_builtins_abi (void)
23134 tree ms_va_ref, sysv_va_ref;
23135 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23136 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23137 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23138 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23142 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23143 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23144 ms_va_ref = build_reference_type (ms_va_list_type_node);
23146 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23149 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23150 fnvoid_va_start_ms =
23151 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23152 fnvoid_va_end_sysv =
23153 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23154 fnvoid_va_start_sysv =
23155 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23157 fnvoid_va_copy_ms =
23158 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23160 fnvoid_va_copy_sysv =
23161 build_function_type_list (void_type_node, sysv_va_ref,
23162 sysv_va_ref, NULL_TREE);
23164 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23165 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23166 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23167 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23168 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23169 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23170 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23171 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23172 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23173 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23174 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23175 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23179 ix86_init_builtins (void)
23181 tree float128_type_node = make_node (REAL_TYPE);
23184 /* The __float80 type. */
23185 if (TYPE_MODE (long_double_type_node) == XFmode)
23186 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23190 /* The __float80 type. */
23191 tree float80_type_node = make_node (REAL_TYPE);
23193 TYPE_PRECISION (float80_type_node) = 80;
23194 layout_type (float80_type_node);
23195 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23199 /* The __float128 type. */
23200 TYPE_PRECISION (float128_type_node) = 128;
23201 layout_type (float128_type_node);
23202 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23205 /* TFmode support builtins. */
23206 ftype = build_function_type (float128_type_node, void_list_node);
23207 decl = add_builtin_function ("__builtin_infq", ftype,
23208 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23210 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23212 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23213 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23215 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23217 /* We will expand them to normal call if SSE2 isn't available since
23218 they are used by libgcc. */
23219 ftype = build_function_type_list (float128_type_node,
23220 float128_type_node,
23222 decl = add_builtin_function ("__builtin_fabsq", ftype,
23223 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23224 "__fabstf2", NULL_TREE);
23225 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23226 TREE_READONLY (decl) = 1;
23228 ftype = build_function_type_list (float128_type_node,
23229 float128_type_node,
23230 float128_type_node,
23232 decl = add_builtin_function ("__builtin_copysignq", ftype,
23233 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23234 "__copysigntf3", NULL_TREE);
23235 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23236 TREE_READONLY (decl) = 1;
23238 ix86_init_mmx_sse_builtins ();
23240 ix86_init_builtins_va_builtins_abi ();
23243 /* Errors in the source file can cause expand_expr to return const0_rtx
23244 where we expect a vector. To avoid crashing, use one of the vector
23245 clear instructions. */
23247 safe_vector_operand (rtx x, enum machine_mode mode)
23249 if (x == const0_rtx)
23250 x = CONST0_RTX (mode);
23254 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23257 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23260 tree arg0 = CALL_EXPR_ARG (exp, 0);
23261 tree arg1 = CALL_EXPR_ARG (exp, 1);
23262 rtx op0 = expand_normal (arg0);
23263 rtx op1 = expand_normal (arg1);
23264 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23265 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23266 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23268 if (VECTOR_MODE_P (mode0))
23269 op0 = safe_vector_operand (op0, mode0);
23270 if (VECTOR_MODE_P (mode1))
23271 op1 = safe_vector_operand (op1, mode1);
23273 if (optimize || !target
23274 || GET_MODE (target) != tmode
23275 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23276 target = gen_reg_rtx (tmode);
23278 if (GET_MODE (op1) == SImode && mode1 == TImode)
23280 rtx x = gen_reg_rtx (V4SImode);
23281 emit_insn (gen_sse2_loadd (x, op1));
23282 op1 = gen_lowpart (TImode, x);
23285 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23286 op0 = copy_to_mode_reg (mode0, op0);
23287 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23288 op1 = copy_to_mode_reg (mode1, op1);
23290 pat = GEN_FCN (icode) (target, op0, op1);
23299 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23300 insns with vec_merge. */
23303 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23307 tree arg0 = CALL_EXPR_ARG (exp, 0);
23308 rtx op1, op0 = expand_normal (arg0);
23309 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23310 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23312 if (optimize || !target
23313 || GET_MODE (target) != tmode
23314 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23315 target = gen_reg_rtx (tmode);
23317 if (VECTOR_MODE_P (mode0))
23318 op0 = safe_vector_operand (op0, mode0);
23320 if ((optimize && !register_operand (op0, mode0))
23321 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23322 op0 = copy_to_mode_reg (mode0, op0);
23325 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23326 op1 = copy_to_mode_reg (mode0, op1);
23328 pat = GEN_FCN (icode) (target, op0, op1);
23335 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23338 ix86_expand_sse_compare (const struct builtin_description *d,
23339 tree exp, rtx target, bool swap)
23342 tree arg0 = CALL_EXPR_ARG (exp, 0);
23343 tree arg1 = CALL_EXPR_ARG (exp, 1);
23344 rtx op0 = expand_normal (arg0);
23345 rtx op1 = expand_normal (arg1);
23347 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23348 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23349 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23350 enum rtx_code comparison = d->comparison;
23352 if (VECTOR_MODE_P (mode0))
23353 op0 = safe_vector_operand (op0, mode0);
23354 if (VECTOR_MODE_P (mode1))
23355 op1 = safe_vector_operand (op1, mode1);
23357 /* Swap operands if we have a comparison that isn't available in
23361 rtx tmp = gen_reg_rtx (mode1);
23362 emit_move_insn (tmp, op1);
23367 if (optimize || !target
23368 || GET_MODE (target) != tmode
23369 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23370 target = gen_reg_rtx (tmode);
23372 if ((optimize && !register_operand (op0, mode0))
23373 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23374 op0 = copy_to_mode_reg (mode0, op0);
23375 if ((optimize && !register_operand (op1, mode1))
23376 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23377 op1 = copy_to_mode_reg (mode1, op1);
23379 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23380 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23387 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23390 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23394 tree arg0 = CALL_EXPR_ARG (exp, 0);
23395 tree arg1 = CALL_EXPR_ARG (exp, 1);
23396 rtx op0 = expand_normal (arg0);
23397 rtx op1 = expand_normal (arg1);
23398 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23399 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23400 enum rtx_code comparison = d->comparison;
23402 if (VECTOR_MODE_P (mode0))
23403 op0 = safe_vector_operand (op0, mode0);
23404 if (VECTOR_MODE_P (mode1))
23405 op1 = safe_vector_operand (op1, mode1);
23407 /* Swap operands if we have a comparison that isn't available in
23409 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23416 target = gen_reg_rtx (SImode);
23417 emit_move_insn (target, const0_rtx);
23418 target = gen_rtx_SUBREG (QImode, target, 0);
23420 if ((optimize && !register_operand (op0, mode0))
23421 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23422 op0 = copy_to_mode_reg (mode0, op0);
23423 if ((optimize && !register_operand (op1, mode1))
23424 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23425 op1 = copy_to_mode_reg (mode1, op1);
23427 pat = GEN_FCN (d->icode) (op0, op1);
23431 emit_insn (gen_rtx_SET (VOIDmode,
23432 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23433 gen_rtx_fmt_ee (comparison, QImode,
23437 return SUBREG_REG (target);
23440 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23443 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23447 tree arg0 = CALL_EXPR_ARG (exp, 0);
23448 tree arg1 = CALL_EXPR_ARG (exp, 1);
23449 rtx op0 = expand_normal (arg0);
23450 rtx op1 = expand_normal (arg1);
23451 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23452 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23453 enum rtx_code comparison = d->comparison;
23455 if (VECTOR_MODE_P (mode0))
23456 op0 = safe_vector_operand (op0, mode0);
23457 if (VECTOR_MODE_P (mode1))
23458 op1 = safe_vector_operand (op1, mode1);
23460 target = gen_reg_rtx (SImode);
23461 emit_move_insn (target, const0_rtx);
23462 target = gen_rtx_SUBREG (QImode, target, 0);
23464 if ((optimize && !register_operand (op0, mode0))
23465 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23466 op0 = copy_to_mode_reg (mode0, op0);
23467 if ((optimize && !register_operand (op1, mode1))
23468 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23469 op1 = copy_to_mode_reg (mode1, op1);
23471 pat = GEN_FCN (d->icode) (op0, op1);
23475 emit_insn (gen_rtx_SET (VOIDmode,
23476 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23477 gen_rtx_fmt_ee (comparison, QImode,
23481 return SUBREG_REG (target);
23484 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23487 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23488 tree exp, rtx target)
23491 tree arg0 = CALL_EXPR_ARG (exp, 0);
23492 tree arg1 = CALL_EXPR_ARG (exp, 1);
23493 tree arg2 = CALL_EXPR_ARG (exp, 2);
23494 tree arg3 = CALL_EXPR_ARG (exp, 3);
23495 tree arg4 = CALL_EXPR_ARG (exp, 4);
23496 rtx scratch0, scratch1;
23497 rtx op0 = expand_normal (arg0);
23498 rtx op1 = expand_normal (arg1);
23499 rtx op2 = expand_normal (arg2);
23500 rtx op3 = expand_normal (arg3);
23501 rtx op4 = expand_normal (arg4);
23502 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23504 tmode0 = insn_data[d->icode].operand[0].mode;
23505 tmode1 = insn_data[d->icode].operand[1].mode;
23506 modev2 = insn_data[d->icode].operand[2].mode;
23507 modei3 = insn_data[d->icode].operand[3].mode;
23508 modev4 = insn_data[d->icode].operand[4].mode;
23509 modei5 = insn_data[d->icode].operand[5].mode;
23510 modeimm = insn_data[d->icode].operand[6].mode;
23512 if (VECTOR_MODE_P (modev2))
23513 op0 = safe_vector_operand (op0, modev2);
23514 if (VECTOR_MODE_P (modev4))
23515 op2 = safe_vector_operand (op2, modev4);
23517 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23518 op0 = copy_to_mode_reg (modev2, op0);
23519 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23520 op1 = copy_to_mode_reg (modei3, op1);
23521 if ((optimize && !register_operand (op2, modev4))
23522 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23523 op2 = copy_to_mode_reg (modev4, op2);
23524 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23525 op3 = copy_to_mode_reg (modei5, op3);
23527 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23529 error ("the fifth argument must be a 8-bit immediate");
23533 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23535 if (optimize || !target
23536 || GET_MODE (target) != tmode0
23537 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23538 target = gen_reg_rtx (tmode0);
23540 scratch1 = gen_reg_rtx (tmode1);
23542 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23544 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23546 if (optimize || !target
23547 || GET_MODE (target) != tmode1
23548 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23549 target = gen_reg_rtx (tmode1);
23551 scratch0 = gen_reg_rtx (tmode0);
23553 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23557 gcc_assert (d->flag);
23559 scratch0 = gen_reg_rtx (tmode0);
23560 scratch1 = gen_reg_rtx (tmode1);
23562 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23572 target = gen_reg_rtx (SImode);
23573 emit_move_insn (target, const0_rtx);
23574 target = gen_rtx_SUBREG (QImode, target, 0);
23577 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23578 gen_rtx_fmt_ee (EQ, QImode,
23579 gen_rtx_REG ((enum machine_mode) d->flag,
23582 return SUBREG_REG (target);
23589 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23592 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23593 tree exp, rtx target)
23596 tree arg0 = CALL_EXPR_ARG (exp, 0);
23597 tree arg1 = CALL_EXPR_ARG (exp, 1);
23598 tree arg2 = CALL_EXPR_ARG (exp, 2);
23599 rtx scratch0, scratch1;
23600 rtx op0 = expand_normal (arg0);
23601 rtx op1 = expand_normal (arg1);
23602 rtx op2 = expand_normal (arg2);
23603 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23605 tmode0 = insn_data[d->icode].operand[0].mode;
23606 tmode1 = insn_data[d->icode].operand[1].mode;
23607 modev2 = insn_data[d->icode].operand[2].mode;
23608 modev3 = insn_data[d->icode].operand[3].mode;
23609 modeimm = insn_data[d->icode].operand[4].mode;
23611 if (VECTOR_MODE_P (modev2))
23612 op0 = safe_vector_operand (op0, modev2);
23613 if (VECTOR_MODE_P (modev3))
23614 op1 = safe_vector_operand (op1, modev3);
23616 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23617 op0 = copy_to_mode_reg (modev2, op0);
23618 if ((optimize && !register_operand (op1, modev3))
23619 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23620 op1 = copy_to_mode_reg (modev3, op1);
23622 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23624 error ("the third argument must be a 8-bit immediate");
23628 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23630 if (optimize || !target
23631 || GET_MODE (target) != tmode0
23632 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23633 target = gen_reg_rtx (tmode0);
23635 scratch1 = gen_reg_rtx (tmode1);
23637 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23639 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23641 if (optimize || !target
23642 || GET_MODE (target) != tmode1
23643 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23644 target = gen_reg_rtx (tmode1);
23646 scratch0 = gen_reg_rtx (tmode0);
23648 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23652 gcc_assert (d->flag);
23654 scratch0 = gen_reg_rtx (tmode0);
23655 scratch1 = gen_reg_rtx (tmode1);
23657 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23667 target = gen_reg_rtx (SImode);
23668 emit_move_insn (target, const0_rtx);
23669 target = gen_rtx_SUBREG (QImode, target, 0);
23672 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23673 gen_rtx_fmt_ee (EQ, QImode,
23674 gen_rtx_REG ((enum machine_mode) d->flag,
23677 return SUBREG_REG (target);
23683 /* Subroutine of ix86_expand_builtin to take care of insns with
23684 variable number of operands. */
23687 ix86_expand_args_builtin (const struct builtin_description *d,
23688 tree exp, rtx target)
23690 rtx pat, real_target;
23691 unsigned int i, nargs;
23692 unsigned int nargs_constant = 0;
23693 int num_memory = 0;
23697 enum machine_mode mode;
23699 bool last_arg_count = false;
23700 enum insn_code icode = d->icode;
23701 const struct insn_data *insn_p = &insn_data[icode];
23702 enum machine_mode tmode = insn_p->operand[0].mode;
23703 enum machine_mode rmode = VOIDmode;
23705 enum rtx_code comparison = d->comparison;
23707 switch ((enum ix86_builtin_type) d->flag)
23709 case INT_FTYPE_V8SF_V8SF_PTEST:
23710 case INT_FTYPE_V4DI_V4DI_PTEST:
23711 case INT_FTYPE_V4DF_V4DF_PTEST:
23712 case INT_FTYPE_V4SF_V4SF_PTEST:
23713 case INT_FTYPE_V2DI_V2DI_PTEST:
23714 case INT_FTYPE_V2DF_V2DF_PTEST:
23715 return ix86_expand_sse_ptest (d, exp, target);
23716 case FLOAT128_FTYPE_FLOAT128:
23717 case FLOAT_FTYPE_FLOAT:
23718 case INT_FTYPE_INT:
23719 case UINT64_FTYPE_INT:
23720 case INT64_FTYPE_INT64:
23721 case INT64_FTYPE_V4SF:
23722 case INT64_FTYPE_V2DF:
23723 case INT_FTYPE_V16QI:
23724 case INT_FTYPE_V8QI:
23725 case INT_FTYPE_V8SF:
23726 case INT_FTYPE_V4DF:
23727 case INT_FTYPE_V4SF:
23728 case INT_FTYPE_V2DF:
23729 case V16QI_FTYPE_V16QI:
23730 case V8SI_FTYPE_V8SF:
23731 case V8SI_FTYPE_V4SI:
23732 case V8HI_FTYPE_V8HI:
23733 case V8HI_FTYPE_V16QI:
23734 case V8QI_FTYPE_V8QI:
23735 case V8SF_FTYPE_V8SF:
23736 case V8SF_FTYPE_V8SI:
23737 case V8SF_FTYPE_V4SF:
23738 case V4SI_FTYPE_V4SI:
23739 case V4SI_FTYPE_V16QI:
23740 case V4SI_FTYPE_V4SF:
23741 case V4SI_FTYPE_V8SI:
23742 case V4SI_FTYPE_V8HI:
23743 case V4SI_FTYPE_V4DF:
23744 case V4SI_FTYPE_V2DF:
23745 case V4HI_FTYPE_V4HI:
23746 case V4DF_FTYPE_V4DF:
23747 case V4DF_FTYPE_V4SI:
23748 case V4DF_FTYPE_V4SF:
23749 case V4DF_FTYPE_V2DF:
23750 case V4SF_FTYPE_V4SF:
23751 case V4SF_FTYPE_V4SI:
23752 case V4SF_FTYPE_V8SF:
23753 case V4SF_FTYPE_V4DF:
23754 case V4SF_FTYPE_V2DF:
23755 case V2DI_FTYPE_V2DI:
23756 case V2DI_FTYPE_V16QI:
23757 case V2DI_FTYPE_V8HI:
23758 case V2DI_FTYPE_V4SI:
23759 case V2DF_FTYPE_V2DF:
23760 case V2DF_FTYPE_V4SI:
23761 case V2DF_FTYPE_V4DF:
23762 case V2DF_FTYPE_V4SF:
23763 case V2DF_FTYPE_V2SI:
23764 case V2SI_FTYPE_V2SI:
23765 case V2SI_FTYPE_V4SF:
23766 case V2SI_FTYPE_V2SF:
23767 case V2SI_FTYPE_V2DF:
23768 case V2SF_FTYPE_V2SF:
23769 case V2SF_FTYPE_V2SI:
23772 case V4SF_FTYPE_V4SF_VEC_MERGE:
23773 case V2DF_FTYPE_V2DF_VEC_MERGE:
23774 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
23775 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
23776 case V16QI_FTYPE_V16QI_V16QI:
23777 case V16QI_FTYPE_V8HI_V8HI:
23778 case V8QI_FTYPE_V8QI_V8QI:
23779 case V8QI_FTYPE_V4HI_V4HI:
23780 case V8HI_FTYPE_V8HI_V8HI:
23781 case V8HI_FTYPE_V16QI_V16QI:
23782 case V8HI_FTYPE_V4SI_V4SI:
23783 case V8SF_FTYPE_V8SF_V8SF:
23784 case V8SF_FTYPE_V8SF_V8SI:
23785 case V4SI_FTYPE_V4SI_V4SI:
23786 case V4SI_FTYPE_V8HI_V8HI:
23787 case V4SI_FTYPE_V4SF_V4SF:
23788 case V4SI_FTYPE_V2DF_V2DF:
23789 case V4HI_FTYPE_V4HI_V4HI:
23790 case V4HI_FTYPE_V8QI_V8QI:
23791 case V4HI_FTYPE_V2SI_V2SI:
23792 case V4DF_FTYPE_V4DF_V4DF:
23793 case V4DF_FTYPE_V4DF_V4DI:
23794 case V4SF_FTYPE_V4SF_V4SF:
23795 case V4SF_FTYPE_V4SF_V4SI:
23796 case V4SF_FTYPE_V4SF_V2SI:
23797 case V4SF_FTYPE_V4SF_V2DF:
23798 case V4SF_FTYPE_V4SF_DI:
23799 case V4SF_FTYPE_V4SF_SI:
23800 case V2DI_FTYPE_V2DI_V2DI:
23801 case V2DI_FTYPE_V16QI_V16QI:
23802 case V2DI_FTYPE_V4SI_V4SI:
23803 case V2DI_FTYPE_V2DI_V16QI:
23804 case V2DI_FTYPE_V2DF_V2DF:
23805 case V2SI_FTYPE_V2SI_V2SI:
23806 case V2SI_FTYPE_V4HI_V4HI:
23807 case V2SI_FTYPE_V2SF_V2SF:
23808 case V2DF_FTYPE_V2DF_V2DF:
23809 case V2DF_FTYPE_V2DF_V4SF:
23810 case V2DF_FTYPE_V2DF_V2DI:
23811 case V2DF_FTYPE_V2DF_DI:
23812 case V2DF_FTYPE_V2DF_SI:
23813 case V2SF_FTYPE_V2SF_V2SF:
23814 case V1DI_FTYPE_V1DI_V1DI:
23815 case V1DI_FTYPE_V8QI_V8QI:
23816 case V1DI_FTYPE_V2SI_V2SI:
23817 if (comparison == UNKNOWN)
23818 return ix86_expand_binop_builtin (icode, exp, target);
23821 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23822 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23823 gcc_assert (comparison != UNKNOWN);
23827 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23828 case V8HI_FTYPE_V8HI_SI_COUNT:
23829 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23830 case V4SI_FTYPE_V4SI_SI_COUNT:
23831 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23832 case V4HI_FTYPE_V4HI_SI_COUNT:
23833 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23834 case V2DI_FTYPE_V2DI_SI_COUNT:
23835 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23836 case V2SI_FTYPE_V2SI_SI_COUNT:
23837 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23838 case V1DI_FTYPE_V1DI_SI_COUNT:
23840 last_arg_count = true;
23842 case UINT64_FTYPE_UINT64_UINT64:
23843 case UINT_FTYPE_UINT_UINT:
23844 case UINT_FTYPE_UINT_USHORT:
23845 case UINT_FTYPE_UINT_UCHAR:
23846 case UINT16_FTYPE_UINT16_INT:
23847 case UINT8_FTYPE_UINT8_INT:
23850 case V2DI2TI_FTYPE_V2DI_INT:
23853 nargs_constant = 1;
23855 case V8HI_FTYPE_V8HI_INT:
23856 case V8SF_FTYPE_V8SF_INT:
23857 case V4SI_FTYPE_V4SI_INT:
23858 case V4SI_FTYPE_V8SI_INT:
23859 case V4HI_FTYPE_V4HI_INT:
23860 case V4DF_FTYPE_V4DF_INT:
23861 case V4SF_FTYPE_V4SF_INT:
23862 case V4SF_FTYPE_V8SF_INT:
23863 case V2DI_FTYPE_V2DI_INT:
23864 case V2DF_FTYPE_V2DF_INT:
23865 case V2DF_FTYPE_V4DF_INT:
23867 nargs_constant = 1;
23869 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23870 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23871 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23872 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23873 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23876 case V16QI_FTYPE_V16QI_V16QI_INT:
23877 case V8HI_FTYPE_V8HI_V8HI_INT:
23878 case V8SI_FTYPE_V8SI_V8SI_INT:
23879 case V8SI_FTYPE_V8SI_V4SI_INT:
23880 case V8SF_FTYPE_V8SF_V8SF_INT:
23881 case V8SF_FTYPE_V8SF_V4SF_INT:
23882 case V4SI_FTYPE_V4SI_V4SI_INT:
23883 case V4DF_FTYPE_V4DF_V4DF_INT:
23884 case V4DF_FTYPE_V4DF_V2DF_INT:
23885 case V4SF_FTYPE_V4SF_V4SF_INT:
23886 case V2DI_FTYPE_V2DI_V2DI_INT:
23887 case V2DF_FTYPE_V2DF_V2DF_INT:
23889 nargs_constant = 1;
23891 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23894 nargs_constant = 1;
23896 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23899 nargs_constant = 1;
23901 case V2DI_FTYPE_V2DI_UINT_UINT:
23903 nargs_constant = 2;
23905 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23907 nargs_constant = 2;
23910 gcc_unreachable ();
23913 gcc_assert (nargs <= ARRAY_SIZE (args));
23915 if (comparison != UNKNOWN)
23917 gcc_assert (nargs == 2);
23918 return ix86_expand_sse_compare (d, exp, target, swap);
23921 if (rmode == VOIDmode || rmode == tmode)
23925 || GET_MODE (target) != tmode
23926 || ! (*insn_p->operand[0].predicate) (target, tmode))
23927 target = gen_reg_rtx (tmode);
23928 real_target = target;
23932 target = gen_reg_rtx (rmode);
23933 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
23936 for (i = 0; i < nargs; i++)
23938 tree arg = CALL_EXPR_ARG (exp, i);
23939 rtx op = expand_normal (arg);
23940 enum machine_mode mode = insn_p->operand[i + 1].mode;
23941 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
23943 if (last_arg_count && (i + 1) == nargs)
23945 /* SIMD shift insns take either an 8-bit immediate or
23946 register as count. But builtin functions take int as
23947 count. If count doesn't match, we put it in register. */
23950 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
23951 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
23952 op = copy_to_reg (op);
23955 else if ((nargs - i) <= nargs_constant)
23960 case CODE_FOR_sse4_1_roundpd:
23961 case CODE_FOR_sse4_1_roundps:
23962 case CODE_FOR_sse4_1_roundsd:
23963 case CODE_FOR_sse4_1_roundss:
23964 case CODE_FOR_sse4_1_blendps:
23965 case CODE_FOR_avx_blendpd256:
23966 case CODE_FOR_avx_vpermilv4df:
23967 case CODE_FOR_avx_roundpd256:
23968 case CODE_FOR_avx_roundps256:
23969 error ("the last argument must be a 4-bit immediate");
23972 case CODE_FOR_sse4_1_blendpd:
23973 case CODE_FOR_avx_vpermilv2df:
23974 error ("the last argument must be a 2-bit immediate");
23977 case CODE_FOR_avx_vextractf128v4df:
23978 case CODE_FOR_avx_vextractf128v8sf:
23979 case CODE_FOR_avx_vextractf128v8si:
23980 case CODE_FOR_avx_vinsertf128v4df:
23981 case CODE_FOR_avx_vinsertf128v8sf:
23982 case CODE_FOR_avx_vinsertf128v8si:
23983 error ("the last argument must be a 1-bit immediate");
23986 case CODE_FOR_avx_cmpsdv2df3:
23987 case CODE_FOR_avx_cmpssv4sf3:
23988 case CODE_FOR_avx_cmppdv2df3:
23989 case CODE_FOR_avx_cmppsv4sf3:
23990 case CODE_FOR_avx_cmppdv4df3:
23991 case CODE_FOR_avx_cmppsv8sf3:
23992 error ("the last argument must be a 5-bit immediate");
23996 switch (nargs_constant)
23999 if ((nargs - i) == nargs_constant)
24001 error ("the next to last argument must be an 8-bit immediate");
24005 error ("the last argument must be an 8-bit immediate");
24008 gcc_unreachable ();
24015 if (VECTOR_MODE_P (mode))
24016 op = safe_vector_operand (op, mode);
24018 /* If we aren't optimizing, only allow one memory operand to
24020 if (memory_operand (op, mode))
24023 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24025 if (optimize || !match || num_memory > 1)
24026 op = copy_to_mode_reg (mode, op);
24030 op = copy_to_reg (op);
24031 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24036 args[i].mode = mode;
24042 pat = GEN_FCN (icode) (real_target, args[0].op);
24045 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24048 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24052 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24053 args[2].op, args[3].op);
24056 gcc_unreachable ();
24066 /* Subroutine of ix86_expand_builtin to take care of special insns
24067 with variable number of operands. */
24070 ix86_expand_special_args_builtin (const struct builtin_description *d,
24071 tree exp, rtx target)
24075 unsigned int i, nargs, arg_adjust, memory;
24079 enum machine_mode mode;
24081 enum insn_code icode = d->icode;
24082 bool last_arg_constant = false;
24083 const struct insn_data *insn_p = &insn_data[icode];
24084 enum machine_mode tmode = insn_p->operand[0].mode;
24085 enum { load, store } klass;
24087 switch ((enum ix86_special_builtin_type) d->flag)
24089 case VOID_FTYPE_VOID:
24090 emit_insn (GEN_FCN (icode) (target));
24092 case UINT64_FTYPE_VOID:
24097 case UINT64_FTYPE_PUNSIGNED:
24098 case V2DI_FTYPE_PV2DI:
24099 case V32QI_FTYPE_PCCHAR:
24100 case V16QI_FTYPE_PCCHAR:
24101 case V8SF_FTYPE_PCV4SF:
24102 case V8SF_FTYPE_PCFLOAT:
24103 case V4SF_FTYPE_PCFLOAT:
24104 case V4DF_FTYPE_PCV2DF:
24105 case V4DF_FTYPE_PCDOUBLE:
24106 case V2DF_FTYPE_PCDOUBLE:
24111 case VOID_FTYPE_PV2SF_V4SF:
24112 case VOID_FTYPE_PV4DI_V4DI:
24113 case VOID_FTYPE_PV2DI_V2DI:
24114 case VOID_FTYPE_PCHAR_V32QI:
24115 case VOID_FTYPE_PCHAR_V16QI:
24116 case VOID_FTYPE_PFLOAT_V8SF:
24117 case VOID_FTYPE_PFLOAT_V4SF:
24118 case VOID_FTYPE_PDOUBLE_V4DF:
24119 case VOID_FTYPE_PDOUBLE_V2DF:
24120 case VOID_FTYPE_PDI_DI:
24121 case VOID_FTYPE_PINT_INT:
24124 /* Reserve memory operand for target. */
24125 memory = ARRAY_SIZE (args);
24127 case V4SF_FTYPE_V4SF_PCV2SF:
24128 case V2DF_FTYPE_V2DF_PCDOUBLE:
24133 case V8SF_FTYPE_PCV8SF_V8SF:
24134 case V4DF_FTYPE_PCV4DF_V4DF:
24135 case V4SF_FTYPE_PCV4SF_V4SF:
24136 case V2DF_FTYPE_PCV2DF_V2DF:
24141 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24142 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24143 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24144 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24147 /* Reserve memory operand for target. */
24148 memory = ARRAY_SIZE (args);
24151 gcc_unreachable ();
24154 gcc_assert (nargs <= ARRAY_SIZE (args));
24156 if (klass == store)
24158 arg = CALL_EXPR_ARG (exp, 0);
24159 op = expand_normal (arg);
24160 gcc_assert (target == 0);
24161 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24169 || GET_MODE (target) != tmode
24170 || ! (*insn_p->operand[0].predicate) (target, tmode))
24171 target = gen_reg_rtx (tmode);
24174 for (i = 0; i < nargs; i++)
24176 enum machine_mode mode = insn_p->operand[i + 1].mode;
24179 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24180 op = expand_normal (arg);
24181 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24183 if (last_arg_constant && (i + 1) == nargs)
24189 error ("the last argument must be an 8-bit immediate");
24197 /* This must be the memory operand. */
24198 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24199 gcc_assert (GET_MODE (op) == mode
24200 || GET_MODE (op) == VOIDmode);
24204 /* This must be register. */
24205 if (VECTOR_MODE_P (mode))
24206 op = safe_vector_operand (op, mode);
24208 gcc_assert (GET_MODE (op) == mode
24209 || GET_MODE (op) == VOIDmode);
24210 op = copy_to_mode_reg (mode, op);
24215 args[i].mode = mode;
24221 pat = GEN_FCN (icode) (target);
24224 pat = GEN_FCN (icode) (target, args[0].op);
24227 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24230 gcc_unreachable ();
24236 return klass == store ? 0 : target;
24239 /* Return the integer constant in ARG. Constrain it to be in the range
24240 of the subparts of VEC_TYPE; issue an error if not. */
24243 get_element_number (tree vec_type, tree arg)
24245 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24247 if (!host_integerp (arg, 1)
24248 || (elt = tree_low_cst (arg, 1), elt > max))
24250 error ("selector must be an integer constant in the range 0..%wi", max);
24257 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24258 ix86_expand_vector_init. We DO have language-level syntax for this, in
24259 the form of (type){ init-list }. Except that since we can't place emms
24260 instructions from inside the compiler, we can't allow the use of MMX
24261 registers unless the user explicitly asks for it. So we do *not* define
24262 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24263 we have builtins invoked by mmintrin.h that gives us license to emit
24264 these sorts of instructions. */
24267 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24269 enum machine_mode tmode = TYPE_MODE (type);
24270 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24271 int i, n_elt = GET_MODE_NUNITS (tmode);
24272 rtvec v = rtvec_alloc (n_elt);
24274 gcc_assert (VECTOR_MODE_P (tmode));
24275 gcc_assert (call_expr_nargs (exp) == n_elt);
24277 for (i = 0; i < n_elt; ++i)
24279 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24280 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24283 if (!target || !register_operand (target, tmode))
24284 target = gen_reg_rtx (tmode);
24286 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24290 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24291 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24292 had a language-level syntax for referencing vector elements. */
24295 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24297 enum machine_mode tmode, mode0;
24302 arg0 = CALL_EXPR_ARG (exp, 0);
24303 arg1 = CALL_EXPR_ARG (exp, 1);
24305 op0 = expand_normal (arg0);
24306 elt = get_element_number (TREE_TYPE (arg0), arg1);
24308 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24309 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24310 gcc_assert (VECTOR_MODE_P (mode0));
24312 op0 = force_reg (mode0, op0);
24314 if (optimize || !target || !register_operand (target, tmode))
24315 target = gen_reg_rtx (tmode);
24317 ix86_expand_vector_extract (true, target, op0, elt);
24322 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24323 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24324 a language-level syntax for referencing vector elements. */
24327 ix86_expand_vec_set_builtin (tree exp)
24329 enum machine_mode tmode, mode1;
24330 tree arg0, arg1, arg2;
24332 rtx op0, op1, target;
24334 arg0 = CALL_EXPR_ARG (exp, 0);
24335 arg1 = CALL_EXPR_ARG (exp, 1);
24336 arg2 = CALL_EXPR_ARG (exp, 2);
24338 tmode = TYPE_MODE (TREE_TYPE (arg0));
24339 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24340 gcc_assert (VECTOR_MODE_P (tmode));
24342 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24343 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24344 elt = get_element_number (TREE_TYPE (arg0), arg2);
24346 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24347 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24349 op0 = force_reg (tmode, op0);
24350 op1 = force_reg (mode1, op1);
24352 /* OP0 is the source of these builtin functions and shouldn't be
24353 modified. Create a copy, use it and return it as target. */
24354 target = gen_reg_rtx (tmode);
24355 emit_move_insn (target, op0);
24356 ix86_expand_vector_set (true, target, op1, elt);
24361 /* Expand an expression EXP that calls a built-in function,
24362 with result going to TARGET if that's convenient
24363 (and in mode MODE if that's convenient).
24364 SUBTARGET may be used as the target for computing one of EXP's operands.
24365 IGNORE is nonzero if the value is to be ignored. */
24368 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24369 enum machine_mode mode ATTRIBUTE_UNUSED,
24370 int ignore ATTRIBUTE_UNUSED)
24372 const struct builtin_description *d;
24374 enum insn_code icode;
24375 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24376 tree arg0, arg1, arg2;
24377 rtx op0, op1, op2, pat;
24378 enum machine_mode mode0, mode1, mode2;
24379 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24381 /* Determine whether the builtin function is available under the current ISA.
24382 Originally the builtin was not created if it wasn't applicable to the
24383 current ISA based on the command line switches. With function specific
24384 options, we need to check in the context of the function making the call
24385 whether it is supported. */
24386 if (ix86_builtins_isa[fcode].isa
24387 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24389 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24390 NULL, NULL, false);
24393 error ("%qE needs unknown isa option", fndecl);
24396 gcc_assert (opts != NULL);
24397 error ("%qE needs isa option %s", fndecl, opts);
24405 case IX86_BUILTIN_MASKMOVQ:
24406 case IX86_BUILTIN_MASKMOVDQU:
24407 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24408 ? CODE_FOR_mmx_maskmovq
24409 : CODE_FOR_sse2_maskmovdqu);
24410 /* Note the arg order is different from the operand order. */
24411 arg1 = CALL_EXPR_ARG (exp, 0);
24412 arg2 = CALL_EXPR_ARG (exp, 1);
24413 arg0 = CALL_EXPR_ARG (exp, 2);
24414 op0 = expand_normal (arg0);
24415 op1 = expand_normal (arg1);
24416 op2 = expand_normal (arg2);
24417 mode0 = insn_data[icode].operand[0].mode;
24418 mode1 = insn_data[icode].operand[1].mode;
24419 mode2 = insn_data[icode].operand[2].mode;
24421 op0 = force_reg (Pmode, op0);
24422 op0 = gen_rtx_MEM (mode1, op0);
24424 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24425 op0 = copy_to_mode_reg (mode0, op0);
24426 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24427 op1 = copy_to_mode_reg (mode1, op1);
24428 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24429 op2 = copy_to_mode_reg (mode2, op2);
24430 pat = GEN_FCN (icode) (op0, op1, op2);
24436 case IX86_BUILTIN_LDMXCSR:
24437 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24438 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24439 emit_move_insn (target, op0);
24440 emit_insn (gen_sse_ldmxcsr (target));
24443 case IX86_BUILTIN_STMXCSR:
24444 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24445 emit_insn (gen_sse_stmxcsr (target));
24446 return copy_to_mode_reg (SImode, target);
24448 case IX86_BUILTIN_CLFLUSH:
24449 arg0 = CALL_EXPR_ARG (exp, 0);
24450 op0 = expand_normal (arg0);
24451 icode = CODE_FOR_sse2_clflush;
24452 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24453 op0 = copy_to_mode_reg (Pmode, op0);
24455 emit_insn (gen_sse2_clflush (op0));
24458 case IX86_BUILTIN_MONITOR:
24459 arg0 = CALL_EXPR_ARG (exp, 0);
24460 arg1 = CALL_EXPR_ARG (exp, 1);
24461 arg2 = CALL_EXPR_ARG (exp, 2);
24462 op0 = expand_normal (arg0);
24463 op1 = expand_normal (arg1);
24464 op2 = expand_normal (arg2);
24466 op0 = copy_to_mode_reg (Pmode, op0);
24468 op1 = copy_to_mode_reg (SImode, op1);
24470 op2 = copy_to_mode_reg (SImode, op2);
24471 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24474 case IX86_BUILTIN_MWAIT:
24475 arg0 = CALL_EXPR_ARG (exp, 0);
24476 arg1 = CALL_EXPR_ARG (exp, 1);
24477 op0 = expand_normal (arg0);
24478 op1 = expand_normal (arg1);
24480 op0 = copy_to_mode_reg (SImode, op0);
24482 op1 = copy_to_mode_reg (SImode, op1);
24483 emit_insn (gen_sse3_mwait (op0, op1));
24486 case IX86_BUILTIN_VEC_INIT_V2SI:
24487 case IX86_BUILTIN_VEC_INIT_V4HI:
24488 case IX86_BUILTIN_VEC_INIT_V8QI:
24489 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24491 case IX86_BUILTIN_VEC_EXT_V2DF:
24492 case IX86_BUILTIN_VEC_EXT_V2DI:
24493 case IX86_BUILTIN_VEC_EXT_V4SF:
24494 case IX86_BUILTIN_VEC_EXT_V4SI:
24495 case IX86_BUILTIN_VEC_EXT_V8HI:
24496 case IX86_BUILTIN_VEC_EXT_V2SI:
24497 case IX86_BUILTIN_VEC_EXT_V4HI:
24498 case IX86_BUILTIN_VEC_EXT_V16QI:
24499 return ix86_expand_vec_ext_builtin (exp, target);
24501 case IX86_BUILTIN_VEC_SET_V2DI:
24502 case IX86_BUILTIN_VEC_SET_V4SF:
24503 case IX86_BUILTIN_VEC_SET_V4SI:
24504 case IX86_BUILTIN_VEC_SET_V8HI:
24505 case IX86_BUILTIN_VEC_SET_V4HI:
24506 case IX86_BUILTIN_VEC_SET_V16QI:
24507 return ix86_expand_vec_set_builtin (exp);
24509 case IX86_BUILTIN_INFQ:
24510 case IX86_BUILTIN_HUGE_VALQ:
24512 REAL_VALUE_TYPE inf;
24516 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24518 tmp = validize_mem (force_const_mem (mode, tmp));
24521 target = gen_reg_rtx (mode);
24523 emit_move_insn (target, tmp);
24531 for (i = 0, d = bdesc_special_args;
24532 i < ARRAY_SIZE (bdesc_special_args);
24534 if (d->code == fcode)
24535 return ix86_expand_special_args_builtin (d, exp, target);
24537 for (i = 0, d = bdesc_args;
24538 i < ARRAY_SIZE (bdesc_args);
24540 if (d->code == fcode)
24543 case IX86_BUILTIN_FABSQ:
24544 case IX86_BUILTIN_COPYSIGNQ:
24546 /* Emit a normal call if SSE2 isn't available. */
24547 return expand_call (exp, target, ignore);
24549 return ix86_expand_args_builtin (d, exp, target);
24552 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24553 if (d->code == fcode)
24554 return ix86_expand_sse_comi (d, exp, target);
24556 for (i = 0, d = bdesc_pcmpestr;
24557 i < ARRAY_SIZE (bdesc_pcmpestr);
24559 if (d->code == fcode)
24560 return ix86_expand_sse_pcmpestr (d, exp, target);
24562 for (i = 0, d = bdesc_pcmpistr;
24563 i < ARRAY_SIZE (bdesc_pcmpistr);
24565 if (d->code == fcode)
24566 return ix86_expand_sse_pcmpistr (d, exp, target);
24568 gcc_unreachable ();
24571 /* Returns a function decl for a vectorized version of the builtin function
24572 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24573 if it is not available. */
24576 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24579 enum machine_mode in_mode, out_mode;
24582 if (TREE_CODE (type_out) != VECTOR_TYPE
24583 || TREE_CODE (type_in) != VECTOR_TYPE)
24586 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24587 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24588 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24589 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24593 case BUILT_IN_SQRT:
24594 if (out_mode == DFmode && out_n == 2
24595 && in_mode == DFmode && in_n == 2)
24596 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24599 case BUILT_IN_SQRTF:
24600 if (out_mode == SFmode && out_n == 4
24601 && in_mode == SFmode && in_n == 4)
24602 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24605 case BUILT_IN_LRINT:
24606 if (out_mode == SImode && out_n == 4
24607 && in_mode == DFmode && in_n == 2)
24608 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24611 case BUILT_IN_LRINTF:
24612 if (out_mode == SImode && out_n == 4
24613 && in_mode == SFmode && in_n == 4)
24614 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24617 case BUILT_IN_COPYSIGN:
24618 if (out_mode == DFmode && out_n == 2
24619 && in_mode == DFmode && in_n == 2)
24620 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
24623 case BUILT_IN_COPYSIGNF:
24624 if (out_mode == SFmode && out_n == 4
24625 && in_mode == SFmode && in_n == 4)
24626 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
24633 /* Dispatch to a handler for a vectorization library. */
24634 if (ix86_veclib_handler)
24635 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
24641 /* Handler for an SVML-style interface to
24642 a library with vectorized intrinsics. */
24645 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24648 tree fntype, new_fndecl, args;
24651 enum machine_mode el_mode, in_mode;
24654 /* The SVML is suitable for unsafe math only. */
24655 if (!flag_unsafe_math_optimizations)
24658 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24659 n = TYPE_VECTOR_SUBPARTS (type_out);
24660 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24661 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24662 if (el_mode != in_mode
24670 case BUILT_IN_LOG10:
24672 case BUILT_IN_TANH:
24674 case BUILT_IN_ATAN:
24675 case BUILT_IN_ATAN2:
24676 case BUILT_IN_ATANH:
24677 case BUILT_IN_CBRT:
24678 case BUILT_IN_SINH:
24680 case BUILT_IN_ASINH:
24681 case BUILT_IN_ASIN:
24682 case BUILT_IN_COSH:
24684 case BUILT_IN_ACOSH:
24685 case BUILT_IN_ACOS:
24686 if (el_mode != DFmode || n != 2)
24690 case BUILT_IN_EXPF:
24691 case BUILT_IN_LOGF:
24692 case BUILT_IN_LOG10F:
24693 case BUILT_IN_POWF:
24694 case BUILT_IN_TANHF:
24695 case BUILT_IN_TANF:
24696 case BUILT_IN_ATANF:
24697 case BUILT_IN_ATAN2F:
24698 case BUILT_IN_ATANHF:
24699 case BUILT_IN_CBRTF:
24700 case BUILT_IN_SINHF:
24701 case BUILT_IN_SINF:
24702 case BUILT_IN_ASINHF:
24703 case BUILT_IN_ASINF:
24704 case BUILT_IN_COSHF:
24705 case BUILT_IN_COSF:
24706 case BUILT_IN_ACOSHF:
24707 case BUILT_IN_ACOSF:
24708 if (el_mode != SFmode || n != 4)
24716 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24718 if (fn == BUILT_IN_LOGF)
24719 strcpy (name, "vmlsLn4");
24720 else if (fn == BUILT_IN_LOG)
24721 strcpy (name, "vmldLn2");
24724 sprintf (name, "vmls%s", bname+10);
24725 name[strlen (name)-1] = '4';
24728 sprintf (name, "vmld%s2", bname+10);
24730 /* Convert to uppercase. */
24734 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24735 args = TREE_CHAIN (args))
24739 fntype = build_function_type_list (type_out, type_in, NULL);
24741 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24743 /* Build a function declaration for the vectorized function. */
24744 new_fndecl = build_decl (BUILTINS_LOCATION,
24745 FUNCTION_DECL, get_identifier (name), fntype);
24746 TREE_PUBLIC (new_fndecl) = 1;
24747 DECL_EXTERNAL (new_fndecl) = 1;
24748 DECL_IS_NOVOPS (new_fndecl) = 1;
24749 TREE_READONLY (new_fndecl) = 1;
24754 /* Handler for an ACML-style interface to
24755 a library with vectorized intrinsics. */
24758 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
24760 char name[20] = "__vr.._";
24761 tree fntype, new_fndecl, args;
24764 enum machine_mode el_mode, in_mode;
24767 /* The ACML is 64bits only and suitable for unsafe math only as
24768 it does not correctly support parts of IEEE with the required
24769 precision such as denormals. */
24771 || !flag_unsafe_math_optimizations)
24774 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24775 n = TYPE_VECTOR_SUBPARTS (type_out);
24776 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24777 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24778 if (el_mode != in_mode
24788 case BUILT_IN_LOG2:
24789 case BUILT_IN_LOG10:
24792 if (el_mode != DFmode
24797 case BUILT_IN_SINF:
24798 case BUILT_IN_COSF:
24799 case BUILT_IN_EXPF:
24800 case BUILT_IN_POWF:
24801 case BUILT_IN_LOGF:
24802 case BUILT_IN_LOG2F:
24803 case BUILT_IN_LOG10F:
24806 if (el_mode != SFmode
24815 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24816 sprintf (name + 7, "%s", bname+10);
24819 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24820 args = TREE_CHAIN (args))
24824 fntype = build_function_type_list (type_out, type_in, NULL);
24826 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24828 /* Build a function declaration for the vectorized function. */
24829 new_fndecl = build_decl (BUILTINS_LOCATION,
24830 FUNCTION_DECL, get_identifier (name), fntype);
24831 TREE_PUBLIC (new_fndecl) = 1;
24832 DECL_EXTERNAL (new_fndecl) = 1;
24833 DECL_IS_NOVOPS (new_fndecl) = 1;
24834 TREE_READONLY (new_fndecl) = 1;
24840 /* Returns a decl of a function that implements conversion of an integer vector
24841 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24842 side of the conversion.
24843 Return NULL_TREE if it is not available. */
24846 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
24848 if (TREE_CODE (type) != VECTOR_TYPE)
24854 switch (TYPE_MODE (type))
24857 return TYPE_UNSIGNED (type)
24858 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
24859 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
24864 case FIX_TRUNC_EXPR:
24865 switch (TYPE_MODE (type))
24868 return TYPE_UNSIGNED (type)
24870 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
24880 /* Returns a code for a target-specific builtin that implements
24881 reciprocal of the function, or NULL_TREE if not available. */
24884 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
24885 bool sqrt ATTRIBUTE_UNUSED)
24887 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
24888 && flag_finite_math_only && !flag_trapping_math
24889 && flag_unsafe_math_optimizations))
24893 /* Machine dependent builtins. */
24896 /* Vectorized version of sqrt to rsqrt conversion. */
24897 case IX86_BUILTIN_SQRTPS_NR:
24898 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
24904 /* Normal builtins. */
24907 /* Sqrt to rsqrt conversion. */
24908 case BUILT_IN_SQRTF:
24909 return ix86_builtins[IX86_BUILTIN_RSQRTF];
24916 /* Store OPERAND to the memory after reload is completed. This means
24917 that we can't easily use assign_stack_local. */
24919 ix86_force_to_memory (enum machine_mode mode, rtx operand)
24923 gcc_assert (reload_completed);
24924 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
24926 result = gen_rtx_MEM (mode,
24927 gen_rtx_PLUS (Pmode,
24929 GEN_INT (-RED_ZONE_SIZE)));
24930 emit_move_insn (result, operand);
24932 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
24938 operand = gen_lowpart (DImode, operand);
24942 gen_rtx_SET (VOIDmode,
24943 gen_rtx_MEM (DImode,
24944 gen_rtx_PRE_DEC (DImode,
24945 stack_pointer_rtx)),
24949 gcc_unreachable ();
24951 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24960 split_di (&operand, 1, operands, operands + 1);
24962 gen_rtx_SET (VOIDmode,
24963 gen_rtx_MEM (SImode,
24964 gen_rtx_PRE_DEC (Pmode,
24965 stack_pointer_rtx)),
24968 gen_rtx_SET (VOIDmode,
24969 gen_rtx_MEM (SImode,
24970 gen_rtx_PRE_DEC (Pmode,
24971 stack_pointer_rtx)),
24976 /* Store HImodes as SImodes. */
24977 operand = gen_lowpart (SImode, operand);
24981 gen_rtx_SET (VOIDmode,
24982 gen_rtx_MEM (GET_MODE (operand),
24983 gen_rtx_PRE_DEC (SImode,
24984 stack_pointer_rtx)),
24988 gcc_unreachable ();
24990 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24995 /* Free operand from the memory. */
24997 ix86_free_from_memory (enum machine_mode mode)
24999 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25003 if (mode == DImode || TARGET_64BIT)
25007 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25008 to pop or add instruction if registers are available. */
25009 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25010 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25015 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25016 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25018 static const enum reg_class *
25019 i386_ira_cover_classes (void)
25021 static const enum reg_class sse_fpmath_classes[] = {
25022 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
25024 static const enum reg_class no_sse_fpmath_classes[] = {
25025 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
25028 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
25031 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25032 QImode must go into class Q_REGS.
25033 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25034 movdf to do mem-to-mem moves through integer regs. */
25036 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25038 enum machine_mode mode = GET_MODE (x);
25040 /* We're only allowed to return a subclass of CLASS. Many of the
25041 following checks fail for NO_REGS, so eliminate that early. */
25042 if (regclass == NO_REGS)
25045 /* All classes can load zeros. */
25046 if (x == CONST0_RTX (mode))
25049 /* Force constants into memory if we are loading a (nonzero) constant into
25050 an MMX or SSE register. This is because there are no MMX/SSE instructions
25051 to load from a constant. */
25053 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25056 /* Prefer SSE regs only, if we can use them for math. */
25057 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25058 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25060 /* Floating-point constants need more complex checks. */
25061 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25063 /* General regs can load everything. */
25064 if (reg_class_subset_p (regclass, GENERAL_REGS))
25067 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25068 zero above. We only want to wind up preferring 80387 registers if
25069 we plan on doing computation with them. */
25071 && standard_80387_constant_p (x))
25073 /* Limit class to non-sse. */
25074 if (regclass == FLOAT_SSE_REGS)
25076 if (regclass == FP_TOP_SSE_REGS)
25078 if (regclass == FP_SECOND_SSE_REGS)
25079 return FP_SECOND_REG;
25080 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25087 /* Generally when we see PLUS here, it's the function invariant
25088 (plus soft-fp const_int). Which can only be computed into general
25090 if (GET_CODE (x) == PLUS)
25091 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25093 /* QImode constants are easy to load, but non-constant QImode data
25094 must go into Q_REGS. */
25095 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25097 if (reg_class_subset_p (regclass, Q_REGS))
25099 if (reg_class_subset_p (Q_REGS, regclass))
25107 /* Discourage putting floating-point values in SSE registers unless
25108 SSE math is being used, and likewise for the 387 registers. */
25110 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25112 enum machine_mode mode = GET_MODE (x);
25114 /* Restrict the output reload class to the register bank that we are doing
25115 math on. If we would like not to return a subset of CLASS, reject this
25116 alternative: if reload cannot do this, it will still use its choice. */
25117 mode = GET_MODE (x);
25118 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25119 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25121 if (X87_FLOAT_MODE_P (mode))
25123 if (regclass == FP_TOP_SSE_REGS)
25125 else if (regclass == FP_SECOND_SSE_REGS)
25126 return FP_SECOND_REG;
25128 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25134 static enum reg_class
25135 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25136 enum machine_mode mode,
25137 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25139 /* QImode spills from non-QI registers require
25140 intermediate register on 32bit targets. */
25141 if (!in_p && mode == QImode && !TARGET_64BIT
25142 && (rclass == GENERAL_REGS
25143 || rclass == LEGACY_REGS
25144 || rclass == INDEX_REGS))
25153 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25154 regno = true_regnum (x);
25156 /* Return Q_REGS if the operand is in memory. */
25164 /* If we are copying between general and FP registers, we need a memory
25165 location. The same is true for SSE and MMX registers.
25167 To optimize register_move_cost performance, allow inline variant.
25169 The macro can't work reliably when one of the CLASSES is class containing
25170 registers from multiple units (SSE, MMX, integer). We avoid this by never
25171 combining those units in single alternative in the machine description.
25172 Ensure that this constraint holds to avoid unexpected surprises.
25174 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25175 enforce these sanity checks. */
25178 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25179 enum machine_mode mode, int strict)
25181 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25182 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25183 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25184 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25185 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25186 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25188 gcc_assert (!strict);
25192 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25195 /* ??? This is a lie. We do have moves between mmx/general, and for
25196 mmx/sse2. But by saying we need secondary memory we discourage the
25197 register allocator from using the mmx registers unless needed. */
25198 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25201 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25203 /* SSE1 doesn't have any direct moves from other classes. */
25207 /* If the target says that inter-unit moves are more expensive
25208 than moving through memory, then don't generate them. */
25209 if (!TARGET_INTER_UNIT_MOVES)
25212 /* Between SSE and general, we have moves no larger than word size. */
25213 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25221 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25222 enum machine_mode mode, int strict)
25224 return inline_secondary_memory_needed (class1, class2, mode, strict);
25227 /* Return true if the registers in CLASS cannot represent the change from
25228 modes FROM to TO. */
25231 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25232 enum reg_class regclass)
25237 /* x87 registers can't do subreg at all, as all values are reformatted
25238 to extended precision. */
25239 if (MAYBE_FLOAT_CLASS_P (regclass))
25242 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25244 /* Vector registers do not support QI or HImode loads. If we don't
25245 disallow a change to these modes, reload will assume it's ok to
25246 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25247 the vec_dupv4hi pattern. */
25248 if (GET_MODE_SIZE (from) < 4)
25251 /* Vector registers do not support subreg with nonzero offsets, which
25252 are otherwise valid for integer registers. Since we can't see
25253 whether we have a nonzero offset from here, prohibit all
25254 nonparadoxical subregs changing size. */
25255 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25262 /* Return the cost of moving data of mode M between a
25263 register and memory. A value of 2 is the default; this cost is
25264 relative to those in `REGISTER_MOVE_COST'.
25266 This function is used extensively by register_move_cost that is used to
25267 build tables at startup. Make it inline in this case.
25268 When IN is 2, return maximum of in and out move cost.
25270 If moving between registers and memory is more expensive than
25271 between two registers, you should define this macro to express the
25274 Model also increased moving costs of QImode registers in non
25278 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25282 if (FLOAT_CLASS_P (regclass))
25300 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25301 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25303 if (SSE_CLASS_P (regclass))
25306 switch (GET_MODE_SIZE (mode))
25321 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25322 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25324 if (MMX_CLASS_P (regclass))
25327 switch (GET_MODE_SIZE (mode))
25339 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25340 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25342 switch (GET_MODE_SIZE (mode))
25345 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25348 return ix86_cost->int_store[0];
25349 if (TARGET_PARTIAL_REG_DEPENDENCY
25350 && optimize_function_for_speed_p (cfun))
25351 cost = ix86_cost->movzbl_load;
25353 cost = ix86_cost->int_load[0];
25355 return MAX (cost, ix86_cost->int_store[0]);
25361 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25363 return ix86_cost->movzbl_load;
25365 return ix86_cost->int_store[0] + 4;
25370 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25371 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25373 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25374 if (mode == TFmode)
25377 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25379 cost = ix86_cost->int_load[2];
25381 cost = ix86_cost->int_store[2];
25382 return (cost * (((int) GET_MODE_SIZE (mode)
25383 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25388 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25390 return inline_memory_move_cost (mode, regclass, in);
25394 /* Return the cost of moving data from a register in class CLASS1 to
25395 one in class CLASS2.
25397 It is not required that the cost always equal 2 when FROM is the same as TO;
25398 on some machines it is expensive to move between registers if they are not
25399 general registers. */
25402 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25403 enum reg_class class2)
25405 /* In case we require secondary memory, compute cost of the store followed
25406 by load. In order to avoid bad register allocation choices, we need
25407 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25409 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25413 cost += inline_memory_move_cost (mode, class1, 2);
25414 cost += inline_memory_move_cost (mode, class2, 2);
25416 /* In case of copying from general_purpose_register we may emit multiple
25417 stores followed by single load causing memory size mismatch stall.
25418 Count this as arbitrarily high cost of 20. */
25419 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25422 /* In the case of FP/MMX moves, the registers actually overlap, and we
25423 have to switch modes in order to treat them differently. */
25424 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25425 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25431 /* Moves between SSE/MMX and integer unit are expensive. */
25432 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25433 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25435 /* ??? By keeping returned value relatively high, we limit the number
25436 of moves between integer and MMX/SSE registers for all targets.
25437 Additionally, high value prevents problem with x86_modes_tieable_p(),
25438 where integer modes in MMX/SSE registers are not tieable
25439 because of missing QImode and HImode moves to, from or between
25440 MMX/SSE registers. */
25441 return MAX (8, ix86_cost->mmxsse_to_integer);
25443 if (MAYBE_FLOAT_CLASS_P (class1))
25444 return ix86_cost->fp_move;
25445 if (MAYBE_SSE_CLASS_P (class1))
25446 return ix86_cost->sse_move;
25447 if (MAYBE_MMX_CLASS_P (class1))
25448 return ix86_cost->mmx_move;
25452 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25455 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25457 /* Flags and only flags can only hold CCmode values. */
25458 if (CC_REGNO_P (regno))
25459 return GET_MODE_CLASS (mode) == MODE_CC;
25460 if (GET_MODE_CLASS (mode) == MODE_CC
25461 || GET_MODE_CLASS (mode) == MODE_RANDOM
25462 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25464 if (FP_REGNO_P (regno))
25465 return VALID_FP_MODE_P (mode);
25466 if (SSE_REGNO_P (regno))
25468 /* We implement the move patterns for all vector modes into and
25469 out of SSE registers, even when no operation instructions
25470 are available. OImode move is available only when AVX is
25472 return ((TARGET_AVX && mode == OImode)
25473 || VALID_AVX256_REG_MODE (mode)
25474 || VALID_SSE_REG_MODE (mode)
25475 || VALID_SSE2_REG_MODE (mode)
25476 || VALID_MMX_REG_MODE (mode)
25477 || VALID_MMX_REG_MODE_3DNOW (mode));
25479 if (MMX_REGNO_P (regno))
25481 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25482 so if the register is available at all, then we can move data of
25483 the given mode into or out of it. */
25484 return (VALID_MMX_REG_MODE (mode)
25485 || VALID_MMX_REG_MODE_3DNOW (mode));
25488 if (mode == QImode)
25490 /* Take care for QImode values - they can be in non-QI regs,
25491 but then they do cause partial register stalls. */
25492 if (regno <= BX_REG || TARGET_64BIT)
25494 if (!TARGET_PARTIAL_REG_STALL)
25496 return reload_in_progress || reload_completed;
25498 /* We handle both integer and floats in the general purpose registers. */
25499 else if (VALID_INT_MODE_P (mode))
25501 else if (VALID_FP_MODE_P (mode))
25503 else if (VALID_DFP_MODE_P (mode))
25505 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25506 on to use that value in smaller contexts, this can easily force a
25507 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25508 supporting DImode, allow it. */
25509 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25515 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25516 tieable integer mode. */
25519 ix86_tieable_integer_mode_p (enum machine_mode mode)
25528 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25531 return TARGET_64BIT;
25538 /* Return true if MODE1 is accessible in a register that can hold MODE2
25539 without copying. That is, all register classes that can hold MODE2
25540 can also hold MODE1. */
25543 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25545 if (mode1 == mode2)
25548 if (ix86_tieable_integer_mode_p (mode1)
25549 && ix86_tieable_integer_mode_p (mode2))
25552 /* MODE2 being XFmode implies fp stack or general regs, which means we
25553 can tie any smaller floating point modes to it. Note that we do not
25554 tie this with TFmode. */
25555 if (mode2 == XFmode)
25556 return mode1 == SFmode || mode1 == DFmode;
25558 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25559 that we can tie it with SFmode. */
25560 if (mode2 == DFmode)
25561 return mode1 == SFmode;
25563 /* If MODE2 is only appropriate for an SSE register, then tie with
25564 any other mode acceptable to SSE registers. */
25565 if (GET_MODE_SIZE (mode2) == 16
25566 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25567 return (GET_MODE_SIZE (mode1) == 16
25568 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25570 /* If MODE2 is appropriate for an MMX register, then tie
25571 with any other mode acceptable to MMX registers. */
25572 if (GET_MODE_SIZE (mode2) == 8
25573 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25574 return (GET_MODE_SIZE (mode1) == 8
25575 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25580 /* Compute a (partial) cost for rtx X. Return true if the complete
25581 cost has been computed, and false if subexpressions should be
25582 scanned. In either case, *TOTAL contains the cost result. */
25585 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25587 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25588 enum machine_mode mode = GET_MODE (x);
25589 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25597 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25599 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25601 else if (flag_pic && SYMBOLIC_CONST (x)
25603 || (!GET_CODE (x) != LABEL_REF
25604 && (GET_CODE (x) != SYMBOL_REF
25605 || !SYMBOL_REF_LOCAL_P (x)))))
25612 if (mode == VOIDmode)
25615 switch (standard_80387_constant_p (x))
25620 default: /* Other constants */
25625 /* Start with (MEM (SYMBOL_REF)), since that's where
25626 it'll probably end up. Add a penalty for size. */
25627 *total = (COSTS_N_INSNS (1)
25628 + (flag_pic != 0 && !TARGET_64BIT)
25629 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25635 /* The zero extensions is often completely free on x86_64, so make
25636 it as cheap as possible. */
25637 if (TARGET_64BIT && mode == DImode
25638 && GET_MODE (XEXP (x, 0)) == SImode)
25640 else if (TARGET_ZERO_EXTEND_WITH_AND)
25641 *total = cost->add;
25643 *total = cost->movzx;
25647 *total = cost->movsx;
25651 if (CONST_INT_P (XEXP (x, 1))
25652 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25654 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25657 *total = cost->add;
25660 if ((value == 2 || value == 3)
25661 && cost->lea <= cost->shift_const)
25663 *total = cost->lea;
25673 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25675 if (CONST_INT_P (XEXP (x, 1)))
25677 if (INTVAL (XEXP (x, 1)) > 32)
25678 *total = cost->shift_const + COSTS_N_INSNS (2);
25680 *total = cost->shift_const * 2;
25684 if (GET_CODE (XEXP (x, 1)) == AND)
25685 *total = cost->shift_var * 2;
25687 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25692 if (CONST_INT_P (XEXP (x, 1)))
25693 *total = cost->shift_const;
25695 *total = cost->shift_var;
25700 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25702 /* ??? SSE scalar cost should be used here. */
25703 *total = cost->fmul;
25706 else if (X87_FLOAT_MODE_P (mode))
25708 *total = cost->fmul;
25711 else if (FLOAT_MODE_P (mode))
25713 /* ??? SSE vector cost should be used here. */
25714 *total = cost->fmul;
25719 rtx op0 = XEXP (x, 0);
25720 rtx op1 = XEXP (x, 1);
25722 if (CONST_INT_P (XEXP (x, 1)))
25724 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25725 for (nbits = 0; value != 0; value &= value - 1)
25729 /* This is arbitrary. */
25732 /* Compute costs correctly for widening multiplication. */
25733 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25734 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25735 == GET_MODE_SIZE (mode))
25737 int is_mulwiden = 0;
25738 enum machine_mode inner_mode = GET_MODE (op0);
25740 if (GET_CODE (op0) == GET_CODE (op1))
25741 is_mulwiden = 1, op1 = XEXP (op1, 0);
25742 else if (CONST_INT_P (op1))
25744 if (GET_CODE (op0) == SIGN_EXTEND)
25745 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25748 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
25752 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
25755 *total = (cost->mult_init[MODE_INDEX (mode)]
25756 + nbits * cost->mult_bit
25757 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
25766 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25767 /* ??? SSE cost should be used here. */
25768 *total = cost->fdiv;
25769 else if (X87_FLOAT_MODE_P (mode))
25770 *total = cost->fdiv;
25771 else if (FLOAT_MODE_P (mode))
25772 /* ??? SSE vector cost should be used here. */
25773 *total = cost->fdiv;
25775 *total = cost->divide[MODE_INDEX (mode)];
25779 if (GET_MODE_CLASS (mode) == MODE_INT
25780 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
25782 if (GET_CODE (XEXP (x, 0)) == PLUS
25783 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
25784 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
25785 && CONSTANT_P (XEXP (x, 1)))
25787 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
25788 if (val == 2 || val == 4 || val == 8)
25790 *total = cost->lea;
25791 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25792 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
25793 outer_code, speed);
25794 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25798 else if (GET_CODE (XEXP (x, 0)) == MULT
25799 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
25801 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
25802 if (val == 2 || val == 4 || val == 8)
25804 *total = cost->lea;
25805 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25806 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25810 else if (GET_CODE (XEXP (x, 0)) == PLUS)
25812 *total = cost->lea;
25813 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25814 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25815 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25822 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25824 /* ??? SSE cost should be used here. */
25825 *total = cost->fadd;
25828 else if (X87_FLOAT_MODE_P (mode))
25830 *total = cost->fadd;
25833 else if (FLOAT_MODE_P (mode))
25835 /* ??? SSE vector cost should be used here. */
25836 *total = cost->fadd;
25844 if (!TARGET_64BIT && mode == DImode)
25846 *total = (cost->add * 2
25847 + (rtx_cost (XEXP (x, 0), outer_code, speed)
25848 << (GET_MODE (XEXP (x, 0)) != DImode))
25849 + (rtx_cost (XEXP (x, 1), outer_code, speed)
25850 << (GET_MODE (XEXP (x, 1)) != DImode)));
25856 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25858 /* ??? SSE cost should be used here. */
25859 *total = cost->fchs;
25862 else if (X87_FLOAT_MODE_P (mode))
25864 *total = cost->fchs;
25867 else if (FLOAT_MODE_P (mode))
25869 /* ??? SSE vector cost should be used here. */
25870 *total = cost->fchs;
25876 if (!TARGET_64BIT && mode == DImode)
25877 *total = cost->add * 2;
25879 *total = cost->add;
25883 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
25884 && XEXP (XEXP (x, 0), 1) == const1_rtx
25885 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
25886 && XEXP (x, 1) == const0_rtx)
25888 /* This kind of construct is implemented using test[bwl].
25889 Treat it as if we had an AND. */
25890 *total = (cost->add
25891 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
25892 + rtx_cost (const1_rtx, outer_code, speed));
25898 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
25903 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25904 /* ??? SSE cost should be used here. */
25905 *total = cost->fabs;
25906 else if (X87_FLOAT_MODE_P (mode))
25907 *total = cost->fabs;
25908 else if (FLOAT_MODE_P (mode))
25909 /* ??? SSE vector cost should be used here. */
25910 *total = cost->fabs;
25914 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25915 /* ??? SSE cost should be used here. */
25916 *total = cost->fsqrt;
25917 else if (X87_FLOAT_MODE_P (mode))
25918 *total = cost->fsqrt;
25919 else if (FLOAT_MODE_P (mode))
25920 /* ??? SSE vector cost should be used here. */
25921 *total = cost->fsqrt;
25925 if (XINT (x, 1) == UNSPEC_TP)
25936 static int current_machopic_label_num;
25938 /* Given a symbol name and its associated stub, write out the
25939 definition of the stub. */
25942 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25944 unsigned int length;
25945 char *binder_name, *symbol_name, lazy_ptr_name[32];
25946 int label = ++current_machopic_label_num;
25948 /* For 64-bit we shouldn't get here. */
25949 gcc_assert (!TARGET_64BIT);
25951 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25952 symb = (*targetm.strip_name_encoding) (symb);
25954 length = strlen (stub);
25955 binder_name = XALLOCAVEC (char, length + 32);
25956 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
25958 length = strlen (symb);
25959 symbol_name = XALLOCAVEC (char, length + 32);
25960 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25962 sprintf (lazy_ptr_name, "L%d$lz", label);
25965 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
25967 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
25969 fprintf (file, "%s:\n", stub);
25970 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25974 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
25975 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
25976 fprintf (file, "\tjmp\t*%%edx\n");
25979 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
25981 fprintf (file, "%s:\n", binder_name);
25985 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
25986 fputs ("\tpushl\t%eax\n", file);
25989 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
25991 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
25993 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25994 fprintf (file, "%s:\n", lazy_ptr_name);
25995 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25996 fprintf (file, ASM_LONG "%s\n", binder_name);
26000 darwin_x86_file_end (void)
26002 darwin_file_end ();
26005 #endif /* TARGET_MACHO */
26007 /* Order the registers for register allocator. */
26010 x86_order_regs_for_local_alloc (void)
26015 /* First allocate the local general purpose registers. */
26016 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26017 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26018 reg_alloc_order [pos++] = i;
26020 /* Global general purpose registers. */
26021 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26022 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26023 reg_alloc_order [pos++] = i;
26025 /* x87 registers come first in case we are doing FP math
26027 if (!TARGET_SSE_MATH)
26028 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26029 reg_alloc_order [pos++] = i;
26031 /* SSE registers. */
26032 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26033 reg_alloc_order [pos++] = i;
26034 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26035 reg_alloc_order [pos++] = i;
26037 /* x87 registers. */
26038 if (TARGET_SSE_MATH)
26039 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26040 reg_alloc_order [pos++] = i;
26042 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26043 reg_alloc_order [pos++] = i;
26045 /* Initialize the rest of array as we do not allocate some registers
26047 while (pos < FIRST_PSEUDO_REGISTER)
26048 reg_alloc_order [pos++] = 0;
26051 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26052 struct attribute_spec.handler. */
26054 ix86_handle_abi_attribute (tree *node, tree name,
26055 tree args ATTRIBUTE_UNUSED,
26056 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26058 if (TREE_CODE (*node) != FUNCTION_TYPE
26059 && TREE_CODE (*node) != METHOD_TYPE
26060 && TREE_CODE (*node) != FIELD_DECL
26061 && TREE_CODE (*node) != TYPE_DECL)
26063 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26065 *no_add_attrs = true;
26070 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26072 *no_add_attrs = true;
26076 /* Can combine regparm with all attributes but fastcall. */
26077 if (is_attribute_p ("ms_abi", name))
26079 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26081 error ("ms_abi and sysv_abi attributes are not compatible");
26086 else if (is_attribute_p ("sysv_abi", name))
26088 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26090 error ("ms_abi and sysv_abi attributes are not compatible");
26099 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26100 struct attribute_spec.handler. */
26102 ix86_handle_struct_attribute (tree *node, tree name,
26103 tree args ATTRIBUTE_UNUSED,
26104 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26107 if (DECL_P (*node))
26109 if (TREE_CODE (*node) == TYPE_DECL)
26110 type = &TREE_TYPE (*node);
26115 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26116 || TREE_CODE (*type) == UNION_TYPE)))
26118 warning (OPT_Wattributes, "%qE attribute ignored",
26120 *no_add_attrs = true;
26123 else if ((is_attribute_p ("ms_struct", name)
26124 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26125 || ((is_attribute_p ("gcc_struct", name)
26126 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26128 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26130 *no_add_attrs = true;
26137 ix86_ms_bitfield_layout_p (const_tree record_type)
26139 return (TARGET_MS_BITFIELD_LAYOUT &&
26140 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26141 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26144 /* Returns an expression indicating where the this parameter is
26145 located on entry to the FUNCTION. */
26148 x86_this_parameter (tree function)
26150 tree type = TREE_TYPE (function);
26151 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26156 const int *parm_regs;
26158 if (ix86_function_type_abi (type) == MS_ABI)
26159 parm_regs = x86_64_ms_abi_int_parameter_registers;
26161 parm_regs = x86_64_int_parameter_registers;
26162 return gen_rtx_REG (DImode, parm_regs[aggr]);
26165 nregs = ix86_function_regparm (type, function);
26167 if (nregs > 0 && !stdarg_p (type))
26171 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26172 regno = aggr ? DX_REG : CX_REG;
26180 return gen_rtx_MEM (SImode,
26181 plus_constant (stack_pointer_rtx, 4));
26184 return gen_rtx_REG (SImode, regno);
26187 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26190 /* Determine whether x86_output_mi_thunk can succeed. */
26193 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26194 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26195 HOST_WIDE_INT vcall_offset, const_tree function)
26197 /* 64-bit can handle anything. */
26201 /* For 32-bit, everything's fine if we have one free register. */
26202 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26205 /* Need a free register for vcall_offset. */
26209 /* Need a free register for GOT references. */
26210 if (flag_pic && !(*targetm.binds_local_p) (function))
26213 /* Otherwise ok. */
26217 /* Output the assembler code for a thunk function. THUNK_DECL is the
26218 declaration for the thunk function itself, FUNCTION is the decl for
26219 the target function. DELTA is an immediate constant offset to be
26220 added to THIS. If VCALL_OFFSET is nonzero, the word at
26221 *(*this + vcall_offset) should be added to THIS. */
26224 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26225 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26226 HOST_WIDE_INT vcall_offset, tree function)
26229 rtx this_param = x86_this_parameter (function);
26232 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26233 pull it in now and let DELTA benefit. */
26234 if (REG_P (this_param))
26235 this_reg = this_param;
26236 else if (vcall_offset)
26238 /* Put the this parameter into %eax. */
26239 xops[0] = this_param;
26240 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26241 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26244 this_reg = NULL_RTX;
26246 /* Adjust the this parameter by a fixed constant. */
26249 xops[0] = GEN_INT (delta);
26250 xops[1] = this_reg ? this_reg : this_param;
26253 if (!x86_64_general_operand (xops[0], DImode))
26255 tmp = gen_rtx_REG (DImode, R10_REG);
26257 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26259 xops[1] = this_param;
26261 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26264 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26267 /* Adjust the this parameter by a value stored in the vtable. */
26271 tmp = gen_rtx_REG (DImode, R10_REG);
26274 int tmp_regno = CX_REG;
26275 if (lookup_attribute ("fastcall",
26276 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26277 tmp_regno = AX_REG;
26278 tmp = gen_rtx_REG (SImode, tmp_regno);
26281 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26283 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26285 /* Adjust the this parameter. */
26286 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26287 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26289 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26290 xops[0] = GEN_INT (vcall_offset);
26292 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26293 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26295 xops[1] = this_reg;
26296 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26299 /* If necessary, drop THIS back to its stack slot. */
26300 if (this_reg && this_reg != this_param)
26302 xops[0] = this_reg;
26303 xops[1] = this_param;
26304 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26307 xops[0] = XEXP (DECL_RTL (function), 0);
26310 if (!flag_pic || (*targetm.binds_local_p) (function))
26311 output_asm_insn ("jmp\t%P0", xops);
26312 /* All thunks should be in the same object as their target,
26313 and thus binds_local_p should be true. */
26314 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26315 gcc_unreachable ();
26318 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26319 tmp = gen_rtx_CONST (Pmode, tmp);
26320 tmp = gen_rtx_MEM (QImode, tmp);
26322 output_asm_insn ("jmp\t%A0", xops);
26327 if (!flag_pic || (*targetm.binds_local_p) (function))
26328 output_asm_insn ("jmp\t%P0", xops);
26333 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26334 tmp = (gen_rtx_SYMBOL_REF
26336 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26337 tmp = gen_rtx_MEM (QImode, tmp);
26339 output_asm_insn ("jmp\t%0", xops);
26342 #endif /* TARGET_MACHO */
26344 tmp = gen_rtx_REG (SImode, CX_REG);
26345 output_set_got (tmp, NULL_RTX);
26348 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26349 output_asm_insn ("jmp\t{*}%1", xops);
26355 x86_file_start (void)
26357 default_file_start ();
26359 darwin_file_start ();
26361 if (X86_FILE_START_VERSION_DIRECTIVE)
26362 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26363 if (X86_FILE_START_FLTUSED)
26364 fputs ("\t.global\t__fltused\n", asm_out_file);
26365 if (ix86_asm_dialect == ASM_INTEL)
26366 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26370 x86_field_alignment (tree field, int computed)
26372 enum machine_mode mode;
26373 tree type = TREE_TYPE (field);
26375 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26377 mode = TYPE_MODE (strip_array_types (type));
26378 if (mode == DFmode || mode == DCmode
26379 || GET_MODE_CLASS (mode) == MODE_INT
26380 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26381 return MIN (32, computed);
26385 /* Output assembler code to FILE to increment profiler label # LABELNO
26386 for profiling a function entry. */
26388 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26392 #ifndef NO_PROFILE_COUNTERS
26393 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
26396 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26397 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
26399 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26403 #ifndef NO_PROFILE_COUNTERS
26404 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
26407 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
26411 #ifndef NO_PROFILE_COUNTERS
26412 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
26415 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26419 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26420 /* We don't have exact information about the insn sizes, but we may assume
26421 quite safely that we are informed about all 1 byte insns and memory
26422 address sizes. This is enough to eliminate unnecessary padding in
26426 min_insn_size (rtx insn)
26430 if (!INSN_P (insn) || !active_insn_p (insn))
26433 /* Discard alignments we've emit and jump instructions. */
26434 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26435 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26437 if (JUMP_TABLE_DATA_P (insn))
26440 /* Important case - calls are always 5 bytes.
26441 It is common to have many calls in the row. */
26443 && symbolic_reference_mentioned_p (PATTERN (insn))
26444 && !SIBLING_CALL_P (insn))
26446 len = get_attr_length (insn);
26450 /* For normal instructions we rely on get_attr_length being exact,
26451 with a few exceptions. */
26452 if (!JUMP_P (insn))
26454 enum attr_type type = get_attr_type (insn);
26459 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
26460 || asm_noperands (PATTERN (insn)) >= 0)
26467 /* Otherwise trust get_attr_length. */
26471 l = get_attr_length_address (insn);
26472 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26481 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26485 ix86_avoid_jump_mispredicts (void)
26487 rtx insn, start = get_insns ();
26488 int nbytes = 0, njumps = 0;
26491 /* Look for all minimal intervals of instructions containing 4 jumps.
26492 The intervals are bounded by START and INSN. NBYTES is the total
26493 size of instructions in the interval including INSN and not including
26494 START. When the NBYTES is smaller than 16 bytes, it is possible
26495 that the end of START and INSN ends up in the same 16byte page.
26497 The smallest offset in the page INSN can start is the case where START
26498 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26499 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26501 for (insn = start; insn; insn = NEXT_INSN (insn))
26505 if (LABEL_P (insn))
26507 int align = label_to_alignment (insn);
26508 int max_skip = label_to_max_skip (insn);
26512 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26513 already in the current 16 byte page, because otherwise
26514 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26515 bytes to reach 16 byte boundary. */
26517 || (align <= 3 && max_skip != (1 << align) - 1))
26520 fprintf (dump_file, "Label %i with max_skip %i\n",
26521 INSN_UID (insn), max_skip);
26524 while (nbytes + max_skip >= 16)
26526 start = NEXT_INSN (start);
26527 if ((JUMP_P (start)
26528 && GET_CODE (PATTERN (start)) != ADDR_VEC
26529 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26531 njumps--, isjump = 1;
26534 nbytes -= min_insn_size (start);
26540 min_size = min_insn_size (insn);
26541 nbytes += min_size;
26543 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
26544 INSN_UID (insn), min_size);
26546 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26547 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26555 start = NEXT_INSN (start);
26556 if ((JUMP_P (start)
26557 && GET_CODE (PATTERN (start)) != ADDR_VEC
26558 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26560 njumps--, isjump = 1;
26563 nbytes -= min_insn_size (start);
26565 gcc_assert (njumps >= 0);
26567 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26568 INSN_UID (start), INSN_UID (insn), nbytes);
26570 if (njumps == 3 && isjump && nbytes < 16)
26572 int padsize = 15 - nbytes + min_insn_size (insn);
26575 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26576 INSN_UID (insn), padsize);
26577 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
26583 /* AMD Athlon works faster
26584 when RET is not destination of conditional jump or directly preceded
26585 by other jump instruction. We avoid the penalty by inserting NOP just
26586 before the RET instructions in such cases. */
26588 ix86_pad_returns (void)
26593 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26595 basic_block bb = e->src;
26596 rtx ret = BB_END (bb);
26598 bool replace = false;
26600 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26601 || optimize_bb_for_size_p (bb))
26603 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26604 if (active_insn_p (prev) || LABEL_P (prev))
26606 if (prev && LABEL_P (prev))
26611 FOR_EACH_EDGE (e, ei, bb->preds)
26612 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26613 && !(e->flags & EDGE_FALLTHRU))
26618 prev = prev_active_insn (ret);
26620 && ((JUMP_P (prev) && any_condjump_p (prev))
26623 /* Empty functions get branch mispredict even when the jump destination
26624 is not visible to us. */
26625 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26630 emit_jump_insn_before (gen_return_internal_long (), ret);
26636 /* Implement machine specific optimizations. We implement padding of returns
26637 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26641 if (optimize && optimize_function_for_speed_p (cfun))
26643 if (TARGET_PAD_RETURNS)
26644 ix86_pad_returns ();
26645 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26646 if (TARGET_FOUR_JUMP_LIMIT)
26647 ix86_avoid_jump_mispredicts ();
26652 /* Return nonzero when QImode register that must be represented via REX prefix
26655 x86_extended_QIreg_mentioned_p (rtx insn)
26658 extract_insn_cached (insn);
26659 for (i = 0; i < recog_data.n_operands; i++)
26660 if (REG_P (recog_data.operand[i])
26661 && REGNO (recog_data.operand[i]) > BX_REG)
26666 /* Return nonzero when P points to register encoded via REX prefix.
26667 Called via for_each_rtx. */
26669 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26671 unsigned int regno;
26674 regno = REGNO (*p);
26675 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26678 /* Return true when INSN mentions register that must be encoded using REX
26681 x86_extended_reg_mentioned_p (rtx insn)
26683 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26684 extended_reg_mentioned_1, NULL);
26687 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26688 optabs would emit if we didn't have TFmode patterns. */
26691 x86_emit_floatuns (rtx operands[2])
26693 rtx neglab, donelab, i0, i1, f0, in, out;
26694 enum machine_mode mode, inmode;
26696 inmode = GET_MODE (operands[1]);
26697 gcc_assert (inmode == SImode || inmode == DImode);
26700 in = force_reg (inmode, operands[1]);
26701 mode = GET_MODE (out);
26702 neglab = gen_label_rtx ();
26703 donelab = gen_label_rtx ();
26704 f0 = gen_reg_rtx (mode);
26706 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26708 expand_float (out, in, 0);
26710 emit_jump_insn (gen_jump (donelab));
26713 emit_label (neglab);
26715 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26717 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26719 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26721 expand_float (f0, i0, 0);
26723 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26725 emit_label (donelab);
26728 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26729 with all elements equal to VAR. Return true if successful. */
26732 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26733 rtx target, rtx val)
26735 enum machine_mode hmode, smode, wsmode, wvmode;
26750 val = force_reg (GET_MODE_INNER (mode), val);
26751 x = gen_rtx_VEC_DUPLICATE (mode, val);
26752 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26758 if (TARGET_SSE || TARGET_3DNOW_A)
26760 val = gen_lowpart (SImode, val);
26761 x = gen_rtx_TRUNCATE (HImode, val);
26762 x = gen_rtx_VEC_DUPLICATE (mode, x);
26763 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26785 /* Extend HImode to SImode using a paradoxical SUBREG. */
26786 tmp1 = gen_reg_rtx (SImode);
26787 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26788 /* Insert the SImode value as low element of V4SImode vector. */
26789 tmp2 = gen_reg_rtx (V4SImode);
26790 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26791 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26792 CONST0_RTX (V4SImode),
26794 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26795 /* Cast the V4SImode vector back to a V8HImode vector. */
26796 tmp1 = gen_reg_rtx (V8HImode);
26797 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26798 /* Duplicate the low short through the whole low SImode word. */
26799 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26800 /* Cast the V8HImode vector back to a V4SImode vector. */
26801 tmp2 = gen_reg_rtx (V4SImode);
26802 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26803 /* Replicate the low element of the V4SImode vector. */
26804 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26805 /* Cast the V2SImode back to V8HImode, and store in target. */
26806 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
26817 /* Extend QImode to SImode using a paradoxical SUBREG. */
26818 tmp1 = gen_reg_rtx (SImode);
26819 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26820 /* Insert the SImode value as low element of V4SImode vector. */
26821 tmp2 = gen_reg_rtx (V4SImode);
26822 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26823 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26824 CONST0_RTX (V4SImode),
26826 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26827 /* Cast the V4SImode vector back to a V16QImode vector. */
26828 tmp1 = gen_reg_rtx (V16QImode);
26829 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
26830 /* Duplicate the low byte through the whole low SImode word. */
26831 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26832 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26833 /* Cast the V16QImode vector back to a V4SImode vector. */
26834 tmp2 = gen_reg_rtx (V4SImode);
26835 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26836 /* Replicate the low element of the V4SImode vector. */
26837 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26838 /* Cast the V2SImode back to V16QImode, and store in target. */
26839 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
26847 /* Replicate the value once into the next wider mode and recurse. */
26848 val = convert_modes (wsmode, smode, val, true);
26849 x = expand_simple_binop (wsmode, ASHIFT, val,
26850 GEN_INT (GET_MODE_BITSIZE (smode)),
26851 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26852 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
26854 x = gen_reg_rtx (wvmode);
26855 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
26856 gcc_unreachable ();
26857 emit_move_insn (target, gen_lowpart (mode, x));
26880 rtx tmp = gen_reg_rtx (hmode);
26881 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
26882 emit_insn (gen_rtx_SET (VOIDmode, target,
26883 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
26892 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26893 whose ONE_VAR element is VAR, and other elements are zero. Return true
26897 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
26898 rtx target, rtx var, int one_var)
26900 enum machine_mode vsimode;
26903 bool use_vector_set = false;
26908 /* For SSE4.1, we normally use vector set. But if the second
26909 element is zero and inter-unit moves are OK, we use movq
26911 use_vector_set = (TARGET_64BIT
26913 && !(TARGET_INTER_UNIT_MOVES
26919 use_vector_set = TARGET_SSE4_1;
26922 use_vector_set = TARGET_SSE2;
26925 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
26932 use_vector_set = TARGET_AVX;
26935 /* Use ix86_expand_vector_set in 64bit mode only. */
26936 use_vector_set = TARGET_AVX && TARGET_64BIT;
26942 if (use_vector_set)
26944 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
26945 var = force_reg (GET_MODE_INNER (mode), var);
26946 ix86_expand_vector_set (mmx_ok, target, var, one_var);
26962 var = force_reg (GET_MODE_INNER (mode), var);
26963 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
26964 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26969 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
26970 new_target = gen_reg_rtx (mode);
26972 new_target = target;
26973 var = force_reg (GET_MODE_INNER (mode), var);
26974 x = gen_rtx_VEC_DUPLICATE (mode, var);
26975 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
26976 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
26979 /* We need to shuffle the value to the correct position, so
26980 create a new pseudo to store the intermediate result. */
26982 /* With SSE2, we can use the integer shuffle insns. */
26983 if (mode != V4SFmode && TARGET_SSE2)
26985 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
26987 GEN_INT (one_var == 1 ? 0 : 1),
26988 GEN_INT (one_var == 2 ? 0 : 1),
26989 GEN_INT (one_var == 3 ? 0 : 1)));
26990 if (target != new_target)
26991 emit_move_insn (target, new_target);
26995 /* Otherwise convert the intermediate result to V4SFmode and
26996 use the SSE1 shuffle instructions. */
26997 if (mode != V4SFmode)
26999 tmp = gen_reg_rtx (V4SFmode);
27000 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27005 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27007 GEN_INT (one_var == 1 ? 0 : 1),
27008 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27009 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27011 if (mode != V4SFmode)
27012 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27013 else if (tmp != target)
27014 emit_move_insn (target, tmp);
27016 else if (target != new_target)
27017 emit_move_insn (target, new_target);
27022 vsimode = V4SImode;
27028 vsimode = V2SImode;
27034 /* Zero extend the variable element to SImode and recurse. */
27035 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27037 x = gen_reg_rtx (vsimode);
27038 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27040 gcc_unreachable ();
27042 emit_move_insn (target, gen_lowpart (mode, x));
27050 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27051 consisting of the values in VALS. It is known that all elements
27052 except ONE_VAR are constants. Return true if successful. */
27055 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27056 rtx target, rtx vals, int one_var)
27058 rtx var = XVECEXP (vals, 0, one_var);
27059 enum machine_mode wmode;
27062 const_vec = copy_rtx (vals);
27063 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27064 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27072 /* For the two element vectors, it's just as easy to use
27073 the general case. */
27077 /* Use ix86_expand_vector_set in 64bit mode only. */
27100 /* There's no way to set one QImode entry easily. Combine
27101 the variable value with its adjacent constant value, and
27102 promote to an HImode set. */
27103 x = XVECEXP (vals, 0, one_var ^ 1);
27106 var = convert_modes (HImode, QImode, var, true);
27107 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27108 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27109 x = GEN_INT (INTVAL (x) & 0xff);
27113 var = convert_modes (HImode, QImode, var, true);
27114 x = gen_int_mode (INTVAL (x) << 8, HImode);
27116 if (x != const0_rtx)
27117 var = expand_simple_binop (HImode, IOR, var, x, var,
27118 1, OPTAB_LIB_WIDEN);
27120 x = gen_reg_rtx (wmode);
27121 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27122 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27124 emit_move_insn (target, gen_lowpart (mode, x));
27131 emit_move_insn (target, const_vec);
27132 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27136 /* A subroutine of ix86_expand_vector_init_general. Use vector
27137 concatenate to handle the most general case: all values variable,
27138 and none identical. */
27141 ix86_expand_vector_init_concat (enum machine_mode mode,
27142 rtx target, rtx *ops, int n)
27144 enum machine_mode cmode, hmode = VOIDmode;
27145 rtx first[8], second[4];
27185 gcc_unreachable ();
27188 if (!register_operand (ops[1], cmode))
27189 ops[1] = force_reg (cmode, ops[1]);
27190 if (!register_operand (ops[0], cmode))
27191 ops[0] = force_reg (cmode, ops[0]);
27192 emit_insn (gen_rtx_SET (VOIDmode, target,
27193 gen_rtx_VEC_CONCAT (mode, ops[0],
27213 gcc_unreachable ();
27229 gcc_unreachable ();
27234 /* FIXME: We process inputs backward to help RA. PR 36222. */
27237 for (; i > 0; i -= 2, j--)
27239 first[j] = gen_reg_rtx (cmode);
27240 v = gen_rtvec (2, ops[i - 1], ops[i]);
27241 ix86_expand_vector_init (false, first[j],
27242 gen_rtx_PARALLEL (cmode, v));
27248 gcc_assert (hmode != VOIDmode);
27249 for (i = j = 0; i < n; i += 2, j++)
27251 second[j] = gen_reg_rtx (hmode);
27252 ix86_expand_vector_init_concat (hmode, second [j],
27256 ix86_expand_vector_init_concat (mode, target, second, n);
27259 ix86_expand_vector_init_concat (mode, target, first, n);
27263 gcc_unreachable ();
27267 /* A subroutine of ix86_expand_vector_init_general. Use vector
27268 interleave to handle the most general case: all values variable,
27269 and none identical. */
27272 ix86_expand_vector_init_interleave (enum machine_mode mode,
27273 rtx target, rtx *ops, int n)
27275 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27278 rtx (*gen_load_even) (rtx, rtx, rtx);
27279 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27280 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27285 gen_load_even = gen_vec_setv8hi;
27286 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27287 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27288 inner_mode = HImode;
27289 first_imode = V4SImode;
27290 second_imode = V2DImode;
27291 third_imode = VOIDmode;
27294 gen_load_even = gen_vec_setv16qi;
27295 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27296 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27297 inner_mode = QImode;
27298 first_imode = V8HImode;
27299 second_imode = V4SImode;
27300 third_imode = V2DImode;
27303 gcc_unreachable ();
27306 for (i = 0; i < n; i++)
27308 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27309 op0 = gen_reg_rtx (SImode);
27310 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27312 /* Insert the SImode value as low element of V4SImode vector. */
27313 op1 = gen_reg_rtx (V4SImode);
27314 op0 = gen_rtx_VEC_MERGE (V4SImode,
27315 gen_rtx_VEC_DUPLICATE (V4SImode,
27317 CONST0_RTX (V4SImode),
27319 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27321 /* Cast the V4SImode vector back to a vector in orignal mode. */
27322 op0 = gen_reg_rtx (mode);
27323 emit_move_insn (op0, gen_lowpart (mode, op1));
27325 /* Load even elements into the second positon. */
27326 emit_insn ((*gen_load_even) (op0,
27327 force_reg (inner_mode,
27331 /* Cast vector to FIRST_IMODE vector. */
27332 ops[i] = gen_reg_rtx (first_imode);
27333 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27336 /* Interleave low FIRST_IMODE vectors. */
27337 for (i = j = 0; i < n; i += 2, j++)
27339 op0 = gen_reg_rtx (first_imode);
27340 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27342 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27343 ops[j] = gen_reg_rtx (second_imode);
27344 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27347 /* Interleave low SECOND_IMODE vectors. */
27348 switch (second_imode)
27351 for (i = j = 0; i < n / 2; i += 2, j++)
27353 op0 = gen_reg_rtx (second_imode);
27354 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27357 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27359 ops[j] = gen_reg_rtx (third_imode);
27360 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27362 second_imode = V2DImode;
27363 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27367 op0 = gen_reg_rtx (second_imode);
27368 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27371 /* Cast the SECOND_IMODE vector back to a vector on original
27373 emit_insn (gen_rtx_SET (VOIDmode, target,
27374 gen_lowpart (mode, op0)));
27378 gcc_unreachable ();
27382 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27383 all values variable, and none identical. */
27386 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27387 rtx target, rtx vals)
27389 rtx ops[32], op0, op1;
27390 enum machine_mode half_mode = VOIDmode;
27397 if (!mmx_ok && !TARGET_SSE)
27409 n = GET_MODE_NUNITS (mode);
27410 for (i = 0; i < n; i++)
27411 ops[i] = XVECEXP (vals, 0, i);
27412 ix86_expand_vector_init_concat (mode, target, ops, n);
27416 half_mode = V16QImode;
27420 half_mode = V8HImode;
27424 n = GET_MODE_NUNITS (mode);
27425 for (i = 0; i < n; i++)
27426 ops[i] = XVECEXP (vals, 0, i);
27427 op0 = gen_reg_rtx (half_mode);
27428 op1 = gen_reg_rtx (half_mode);
27429 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27431 ix86_expand_vector_init_interleave (half_mode, op1,
27432 &ops [n >> 1], n >> 2);
27433 emit_insn (gen_rtx_SET (VOIDmode, target,
27434 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27438 if (!TARGET_SSE4_1)
27446 /* Don't use ix86_expand_vector_init_interleave if we can't
27447 move from GPR to SSE register directly. */
27448 if (!TARGET_INTER_UNIT_MOVES)
27451 n = GET_MODE_NUNITS (mode);
27452 for (i = 0; i < n; i++)
27453 ops[i] = XVECEXP (vals, 0, i);
27454 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27462 gcc_unreachable ();
27466 int i, j, n_elts, n_words, n_elt_per_word;
27467 enum machine_mode inner_mode;
27468 rtx words[4], shift;
27470 inner_mode = GET_MODE_INNER (mode);
27471 n_elts = GET_MODE_NUNITS (mode);
27472 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27473 n_elt_per_word = n_elts / n_words;
27474 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27476 for (i = 0; i < n_words; ++i)
27478 rtx word = NULL_RTX;
27480 for (j = 0; j < n_elt_per_word; ++j)
27482 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27483 elt = convert_modes (word_mode, inner_mode, elt, true);
27489 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27490 word, 1, OPTAB_LIB_WIDEN);
27491 word = expand_simple_binop (word_mode, IOR, word, elt,
27492 word, 1, OPTAB_LIB_WIDEN);
27500 emit_move_insn (target, gen_lowpart (mode, words[0]));
27501 else if (n_words == 2)
27503 rtx tmp = gen_reg_rtx (mode);
27504 emit_clobber (tmp);
27505 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27506 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27507 emit_move_insn (target, tmp);
27509 else if (n_words == 4)
27511 rtx tmp = gen_reg_rtx (V4SImode);
27512 gcc_assert (word_mode == SImode);
27513 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27514 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27515 emit_move_insn (target, gen_lowpart (mode, tmp));
27518 gcc_unreachable ();
27522 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27523 instructions unless MMX_OK is true. */
27526 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27528 enum machine_mode mode = GET_MODE (target);
27529 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27530 int n_elts = GET_MODE_NUNITS (mode);
27531 int n_var = 0, one_var = -1;
27532 bool all_same = true, all_const_zero = true;
27536 for (i = 0; i < n_elts; ++i)
27538 x = XVECEXP (vals, 0, i);
27539 if (!(CONST_INT_P (x)
27540 || GET_CODE (x) == CONST_DOUBLE
27541 || GET_CODE (x) == CONST_FIXED))
27542 n_var++, one_var = i;
27543 else if (x != CONST0_RTX (inner_mode))
27544 all_const_zero = false;
27545 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27549 /* Constants are best loaded from the constant pool. */
27552 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27556 /* If all values are identical, broadcast the value. */
27558 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27559 XVECEXP (vals, 0, 0)))
27562 /* Values where only one field is non-constant are best loaded from
27563 the pool and overwritten via move later. */
27567 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27568 XVECEXP (vals, 0, one_var),
27572 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27576 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27580 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27582 enum machine_mode mode = GET_MODE (target);
27583 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27584 enum machine_mode half_mode;
27585 bool use_vec_merge = false;
27587 static rtx (*gen_extract[6][2]) (rtx, rtx)
27589 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27590 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27591 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27592 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27593 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27594 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27596 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27598 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27599 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27600 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27601 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27602 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27603 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27613 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27614 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27616 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27618 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27619 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27625 use_vec_merge = TARGET_SSE4_1;
27633 /* For the two element vectors, we implement a VEC_CONCAT with
27634 the extraction of the other element. */
27636 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27637 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27640 op0 = val, op1 = tmp;
27642 op0 = tmp, op1 = val;
27644 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27645 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27650 use_vec_merge = TARGET_SSE4_1;
27657 use_vec_merge = true;
27661 /* tmp = target = A B C D */
27662 tmp = copy_to_reg (target);
27663 /* target = A A B B */
27664 emit_insn (gen_sse_unpcklps (target, target, target));
27665 /* target = X A B B */
27666 ix86_expand_vector_set (false, target, val, 0);
27667 /* target = A X C D */
27668 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27669 const1_rtx, const0_rtx,
27670 GEN_INT (2+4), GEN_INT (3+4)));
27674 /* tmp = target = A B C D */
27675 tmp = copy_to_reg (target);
27676 /* tmp = X B C D */
27677 ix86_expand_vector_set (false, tmp, val, 0);
27678 /* target = A B X D */
27679 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27680 const0_rtx, const1_rtx,
27681 GEN_INT (0+4), GEN_INT (3+4)));
27685 /* tmp = target = A B C D */
27686 tmp = copy_to_reg (target);
27687 /* tmp = X B C D */
27688 ix86_expand_vector_set (false, tmp, val, 0);
27689 /* target = A B X D */
27690 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27691 const0_rtx, const1_rtx,
27692 GEN_INT (2+4), GEN_INT (0+4)));
27696 gcc_unreachable ();
27701 use_vec_merge = TARGET_SSE4_1;
27705 /* Element 0 handled by vec_merge below. */
27708 use_vec_merge = true;
27714 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27715 store into element 0, then shuffle them back. */
27719 order[0] = GEN_INT (elt);
27720 order[1] = const1_rtx;
27721 order[2] = const2_rtx;
27722 order[3] = GEN_INT (3);
27723 order[elt] = const0_rtx;
27725 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27726 order[1], order[2], order[3]));
27728 ix86_expand_vector_set (false, target, val, 0);
27730 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27731 order[1], order[2], order[3]));
27735 /* For SSE1, we have to reuse the V4SF code. */
27736 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27737 gen_lowpart (SFmode, val), elt);
27742 use_vec_merge = TARGET_SSE2;
27745 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27749 use_vec_merge = TARGET_SSE4_1;
27756 half_mode = V16QImode;
27762 half_mode = V8HImode;
27768 half_mode = V4SImode;
27774 half_mode = V2DImode;
27780 half_mode = V4SFmode;
27786 half_mode = V2DFmode;
27792 /* Compute offset. */
27796 gcc_assert (i <= 1);
27798 /* Extract the half. */
27799 tmp = gen_reg_rtx (half_mode);
27800 emit_insn ((*gen_extract[j][i]) (tmp, target));
27802 /* Put val in tmp at elt. */
27803 ix86_expand_vector_set (false, tmp, val, elt);
27806 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
27815 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
27816 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
27817 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27821 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27823 emit_move_insn (mem, target);
27825 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27826 emit_move_insn (tmp, val);
27828 emit_move_insn (target, mem);
27833 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
27835 enum machine_mode mode = GET_MODE (vec);
27836 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27837 bool use_vec_extr = false;
27850 use_vec_extr = true;
27854 use_vec_extr = TARGET_SSE4_1;
27866 tmp = gen_reg_rtx (mode);
27867 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
27868 GEN_INT (elt), GEN_INT (elt),
27869 GEN_INT (elt+4), GEN_INT (elt+4)));
27873 tmp = gen_reg_rtx (mode);
27874 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
27878 gcc_unreachable ();
27881 use_vec_extr = true;
27886 use_vec_extr = TARGET_SSE4_1;
27900 tmp = gen_reg_rtx (mode);
27901 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
27902 GEN_INT (elt), GEN_INT (elt),
27903 GEN_INT (elt), GEN_INT (elt)));
27907 tmp = gen_reg_rtx (mode);
27908 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
27912 gcc_unreachable ();
27915 use_vec_extr = true;
27920 /* For SSE1, we have to reuse the V4SF code. */
27921 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
27922 gen_lowpart (V4SFmode, vec), elt);
27928 use_vec_extr = TARGET_SSE2;
27931 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27935 use_vec_extr = TARGET_SSE4_1;
27939 /* ??? Could extract the appropriate HImode element and shift. */
27946 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
27947 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
27949 /* Let the rtl optimizers know about the zero extension performed. */
27950 if (inner_mode == QImode || inner_mode == HImode)
27952 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
27953 target = gen_lowpart (SImode, target);
27956 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27960 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27962 emit_move_insn (mem, vec);
27964 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27965 emit_move_insn (target, tmp);
27969 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27970 pattern to reduce; DEST is the destination; IN is the input vector. */
27973 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
27975 rtx tmp1, tmp2, tmp3;
27977 tmp1 = gen_reg_rtx (V4SFmode);
27978 tmp2 = gen_reg_rtx (V4SFmode);
27979 tmp3 = gen_reg_rtx (V4SFmode);
27981 emit_insn (gen_sse_movhlps (tmp1, in, in));
27982 emit_insn (fn (tmp2, tmp1, in));
27984 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
27985 const1_rtx, const1_rtx,
27986 GEN_INT (1+4), GEN_INT (1+4)));
27987 emit_insn (fn (dest, tmp2, tmp3));
27990 /* Target hook for scalar_mode_supported_p. */
27992 ix86_scalar_mode_supported_p (enum machine_mode mode)
27994 if (DECIMAL_FLOAT_MODE_P (mode))
27996 else if (mode == TFmode)
27999 return default_scalar_mode_supported_p (mode);
28002 /* Implements target hook vector_mode_supported_p. */
28004 ix86_vector_mode_supported_p (enum machine_mode mode)
28006 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28008 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28010 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28012 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28014 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28019 /* Target hook for c_mode_for_suffix. */
28020 static enum machine_mode
28021 ix86_c_mode_for_suffix (char suffix)
28031 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28033 We do this in the new i386 backend to maintain source compatibility
28034 with the old cc0-based compiler. */
28037 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28038 tree inputs ATTRIBUTE_UNUSED,
28041 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28043 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28048 /* Implements target vector targetm.asm.encode_section_info. This
28049 is not used by netware. */
28051 static void ATTRIBUTE_UNUSED
28052 ix86_encode_section_info (tree decl, rtx rtl, int first)
28054 default_encode_section_info (decl, rtl, first);
28056 if (TREE_CODE (decl) == VAR_DECL
28057 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28058 && ix86_in_large_data_p (decl))
28059 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28062 /* Worker function for REVERSE_CONDITION. */
28065 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28067 return (mode != CCFPmode && mode != CCFPUmode
28068 ? reverse_condition (code)
28069 : reverse_condition_maybe_unordered (code));
28072 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28076 output_387_reg_move (rtx insn, rtx *operands)
28078 if (REG_P (operands[0]))
28080 if (REG_P (operands[1])
28081 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28083 if (REGNO (operands[0]) == FIRST_STACK_REG)
28084 return output_387_ffreep (operands, 0);
28085 return "fstp\t%y0";
28087 if (STACK_TOP_P (operands[0]))
28088 return "fld%Z1\t%y1";
28091 else if (MEM_P (operands[0]))
28093 gcc_assert (REG_P (operands[1]));
28094 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28095 return "fstp%Z0\t%y0";
28098 /* There is no non-popping store to memory for XFmode.
28099 So if we need one, follow the store with a load. */
28100 if (GET_MODE (operands[0]) == XFmode)
28101 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28103 return "fst%Z0\t%y0";
28110 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28111 FP status register is set. */
28114 ix86_emit_fp_unordered_jump (rtx label)
28116 rtx reg = gen_reg_rtx (HImode);
28119 emit_insn (gen_x86_fnstsw_1 (reg));
28121 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28123 emit_insn (gen_x86_sahf_1 (reg));
28125 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28126 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28130 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28132 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28133 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28136 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28137 gen_rtx_LABEL_REF (VOIDmode, label),
28139 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28141 emit_jump_insn (temp);
28142 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28145 /* Output code to perform a log1p XFmode calculation. */
28147 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28149 rtx label1 = gen_label_rtx ();
28150 rtx label2 = gen_label_rtx ();
28152 rtx tmp = gen_reg_rtx (XFmode);
28153 rtx tmp2 = gen_reg_rtx (XFmode);
28156 emit_insn (gen_absxf2 (tmp, op1));
28157 test = gen_rtx_GE (VOIDmode, tmp,
28158 CONST_DOUBLE_FROM_REAL_VALUE (
28159 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28161 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28163 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28164 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28165 emit_jump (label2);
28167 emit_label (label1);
28168 emit_move_insn (tmp, CONST1_RTX (XFmode));
28169 emit_insn (gen_addxf3 (tmp, op1, tmp));
28170 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28171 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28173 emit_label (label2);
28176 /* Output code to perform a Newton-Rhapson approximation of a single precision
28177 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28179 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28181 rtx x0, x1, e0, e1, two;
28183 x0 = gen_reg_rtx (mode);
28184 e0 = gen_reg_rtx (mode);
28185 e1 = gen_reg_rtx (mode);
28186 x1 = gen_reg_rtx (mode);
28188 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28190 if (VECTOR_MODE_P (mode))
28191 two = ix86_build_const_vector (SFmode, true, two);
28193 two = force_reg (mode, two);
28195 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28197 /* x0 = rcp(b) estimate */
28198 emit_insn (gen_rtx_SET (VOIDmode, x0,
28199 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28202 emit_insn (gen_rtx_SET (VOIDmode, e0,
28203 gen_rtx_MULT (mode, x0, b)));
28205 emit_insn (gen_rtx_SET (VOIDmode, e1,
28206 gen_rtx_MINUS (mode, two, e0)));
28208 emit_insn (gen_rtx_SET (VOIDmode, x1,
28209 gen_rtx_MULT (mode, x0, e1)));
28211 emit_insn (gen_rtx_SET (VOIDmode, res,
28212 gen_rtx_MULT (mode, a, x1)));
28215 /* Output code to perform a Newton-Rhapson approximation of a
28216 single precision floating point [reciprocal] square root. */
28218 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28221 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28224 x0 = gen_reg_rtx (mode);
28225 e0 = gen_reg_rtx (mode);
28226 e1 = gen_reg_rtx (mode);
28227 e2 = gen_reg_rtx (mode);
28228 e3 = gen_reg_rtx (mode);
28230 real_from_integer (&r, VOIDmode, -3, -1, 0);
28231 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28233 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28234 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28236 if (VECTOR_MODE_P (mode))
28238 mthree = ix86_build_const_vector (SFmode, true, mthree);
28239 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28242 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28243 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28245 /* x0 = rsqrt(a) estimate */
28246 emit_insn (gen_rtx_SET (VOIDmode, x0,
28247 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28250 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28255 zero = gen_reg_rtx (mode);
28256 mask = gen_reg_rtx (mode);
28258 zero = force_reg (mode, CONST0_RTX(mode));
28259 emit_insn (gen_rtx_SET (VOIDmode, mask,
28260 gen_rtx_NE (mode, zero, a)));
28262 emit_insn (gen_rtx_SET (VOIDmode, x0,
28263 gen_rtx_AND (mode, x0, mask)));
28267 emit_insn (gen_rtx_SET (VOIDmode, e0,
28268 gen_rtx_MULT (mode, x0, a)));
28270 emit_insn (gen_rtx_SET (VOIDmode, e1,
28271 gen_rtx_MULT (mode, e0, x0)));
28274 mthree = force_reg (mode, mthree);
28275 emit_insn (gen_rtx_SET (VOIDmode, e2,
28276 gen_rtx_PLUS (mode, e1, mthree)));
28278 mhalf = force_reg (mode, mhalf);
28280 /* e3 = -.5 * x0 */
28281 emit_insn (gen_rtx_SET (VOIDmode, e3,
28282 gen_rtx_MULT (mode, x0, mhalf)));
28284 /* e3 = -.5 * e0 */
28285 emit_insn (gen_rtx_SET (VOIDmode, e3,
28286 gen_rtx_MULT (mode, e0, mhalf)));
28287 /* ret = e2 * e3 */
28288 emit_insn (gen_rtx_SET (VOIDmode, res,
28289 gen_rtx_MULT (mode, e2, e3)));
28292 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28294 static void ATTRIBUTE_UNUSED
28295 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28298 /* With Binutils 2.15, the "@unwind" marker must be specified on
28299 every occurrence of the ".eh_frame" section, not just the first
28302 && strcmp (name, ".eh_frame") == 0)
28304 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28305 flags & SECTION_WRITE ? "aw" : "a");
28308 default_elf_asm_named_section (name, flags, decl);
28311 /* Return the mangling of TYPE if it is an extended fundamental type. */
28313 static const char *
28314 ix86_mangle_type (const_tree type)
28316 type = TYPE_MAIN_VARIANT (type);
28318 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28319 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28322 switch (TYPE_MODE (type))
28325 /* __float128 is "g". */
28328 /* "long double" or __float80 is "e". */
28335 /* For 32-bit code we can save PIC register setup by using
28336 __stack_chk_fail_local hidden function instead of calling
28337 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28338 register, so it is better to call __stack_chk_fail directly. */
28341 ix86_stack_protect_fail (void)
28343 return TARGET_64BIT
28344 ? default_external_stack_protect_fail ()
28345 : default_hidden_stack_protect_fail ();
28348 /* Select a format to encode pointers in exception handling data. CODE
28349 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28350 true if the symbol may be affected by dynamic relocations.
28352 ??? All x86 object file formats are capable of representing this.
28353 After all, the relocation needed is the same as for the call insn.
28354 Whether or not a particular assembler allows us to enter such, I
28355 guess we'll have to see. */
28357 asm_preferred_eh_data_format (int code, int global)
28361 int type = DW_EH_PE_sdata8;
28363 || ix86_cmodel == CM_SMALL_PIC
28364 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28365 type = DW_EH_PE_sdata4;
28366 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28368 if (ix86_cmodel == CM_SMALL
28369 || (ix86_cmodel == CM_MEDIUM && code))
28370 return DW_EH_PE_udata4;
28371 return DW_EH_PE_absptr;
28374 /* Expand copysign from SIGN to the positive value ABS_VALUE
28375 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28378 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28380 enum machine_mode mode = GET_MODE (sign);
28381 rtx sgn = gen_reg_rtx (mode);
28382 if (mask == NULL_RTX)
28384 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28385 if (!VECTOR_MODE_P (mode))
28387 /* We need to generate a scalar mode mask in this case. */
28388 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28389 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28390 mask = gen_reg_rtx (mode);
28391 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28395 mask = gen_rtx_NOT (mode, mask);
28396 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28397 gen_rtx_AND (mode, mask, sign)));
28398 emit_insn (gen_rtx_SET (VOIDmode, result,
28399 gen_rtx_IOR (mode, abs_value, sgn)));
28402 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28403 mask for masking out the sign-bit is stored in *SMASK, if that is
28406 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28408 enum machine_mode mode = GET_MODE (op0);
28411 xa = gen_reg_rtx (mode);
28412 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28413 if (!VECTOR_MODE_P (mode))
28415 /* We need to generate a scalar mode mask in this case. */
28416 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28417 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28418 mask = gen_reg_rtx (mode);
28419 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28421 emit_insn (gen_rtx_SET (VOIDmode, xa,
28422 gen_rtx_AND (mode, op0, mask)));
28430 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28431 swapping the operands if SWAP_OPERANDS is true. The expanded
28432 code is a forward jump to a newly created label in case the
28433 comparison is true. The generated label rtx is returned. */
28435 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28436 bool swap_operands)
28447 label = gen_label_rtx ();
28448 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28449 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28450 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28451 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28452 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28453 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28454 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28455 JUMP_LABEL (tmp) = label;
28460 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28461 using comparison code CODE. Operands are swapped for the comparison if
28462 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28464 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28465 bool swap_operands)
28467 enum machine_mode mode = GET_MODE (op0);
28468 rtx mask = gen_reg_rtx (mode);
28477 if (mode == DFmode)
28478 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28479 gen_rtx_fmt_ee (code, mode, op0, op1)));
28481 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28482 gen_rtx_fmt_ee (code, mode, op0, op1)));
28487 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28488 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28490 ix86_gen_TWO52 (enum machine_mode mode)
28492 REAL_VALUE_TYPE TWO52r;
28495 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28496 TWO52 = const_double_from_real_value (TWO52r, mode);
28497 TWO52 = force_reg (mode, TWO52);
28502 /* Expand SSE sequence for computing lround from OP1 storing
28505 ix86_expand_lround (rtx op0, rtx op1)
28507 /* C code for the stuff we're doing below:
28508 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28511 enum machine_mode mode = GET_MODE (op1);
28512 const struct real_format *fmt;
28513 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28516 /* load nextafter (0.5, 0.0) */
28517 fmt = REAL_MODE_FORMAT (mode);
28518 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28519 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28521 /* adj = copysign (0.5, op1) */
28522 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28523 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28525 /* adj = op1 + adj */
28526 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28528 /* op0 = (imode)adj */
28529 expand_fix (op0, adj, 0);
28532 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28535 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28537 /* C code for the stuff we're doing below (for do_floor):
28539 xi -= (double)xi > op1 ? 1 : 0;
28542 enum machine_mode fmode = GET_MODE (op1);
28543 enum machine_mode imode = GET_MODE (op0);
28544 rtx ireg, freg, label, tmp;
28546 /* reg = (long)op1 */
28547 ireg = gen_reg_rtx (imode);
28548 expand_fix (ireg, op1, 0);
28550 /* freg = (double)reg */
28551 freg = gen_reg_rtx (fmode);
28552 expand_float (freg, ireg, 0);
28554 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28555 label = ix86_expand_sse_compare_and_jump (UNLE,
28556 freg, op1, !do_floor);
28557 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28558 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28559 emit_move_insn (ireg, tmp);
28561 emit_label (label);
28562 LABEL_NUSES (label) = 1;
28564 emit_move_insn (op0, ireg);
28567 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28568 result in OPERAND0. */
28570 ix86_expand_rint (rtx operand0, rtx operand1)
28572 /* C code for the stuff we're doing below:
28573 xa = fabs (operand1);
28574 if (!isless (xa, 2**52))
28576 xa = xa + 2**52 - 2**52;
28577 return copysign (xa, operand1);
28579 enum machine_mode mode = GET_MODE (operand0);
28580 rtx res, xa, label, TWO52, mask;
28582 res = gen_reg_rtx (mode);
28583 emit_move_insn (res, operand1);
28585 /* xa = abs (operand1) */
28586 xa = ix86_expand_sse_fabs (res, &mask);
28588 /* if (!isless (xa, TWO52)) goto label; */
28589 TWO52 = ix86_gen_TWO52 (mode);
28590 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28592 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28593 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28595 ix86_sse_copysign_to_positive (res, xa, res, mask);
28597 emit_label (label);
28598 LABEL_NUSES (label) = 1;
28600 emit_move_insn (operand0, res);
28603 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28606 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28608 /* C code for the stuff we expand below.
28609 double xa = fabs (x), x2;
28610 if (!isless (xa, TWO52))
28612 xa = xa + TWO52 - TWO52;
28613 x2 = copysign (xa, x);
28622 enum machine_mode mode = GET_MODE (operand0);
28623 rtx xa, TWO52, tmp, label, one, res, mask;
28625 TWO52 = ix86_gen_TWO52 (mode);
28627 /* Temporary for holding the result, initialized to the input
28628 operand to ease control flow. */
28629 res = gen_reg_rtx (mode);
28630 emit_move_insn (res, operand1);
28632 /* xa = abs (operand1) */
28633 xa = ix86_expand_sse_fabs (res, &mask);
28635 /* if (!isless (xa, TWO52)) goto label; */
28636 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28638 /* xa = xa + TWO52 - TWO52; */
28639 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28640 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28642 /* xa = copysign (xa, operand1) */
28643 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28645 /* generate 1.0 or -1.0 */
28646 one = force_reg (mode,
28647 const_double_from_real_value (do_floor
28648 ? dconst1 : dconstm1, mode));
28650 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28651 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28652 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28653 gen_rtx_AND (mode, one, tmp)));
28654 /* We always need to subtract here to preserve signed zero. */
28655 tmp = expand_simple_binop (mode, MINUS,
28656 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28657 emit_move_insn (res, tmp);
28659 emit_label (label);
28660 LABEL_NUSES (label) = 1;
28662 emit_move_insn (operand0, res);
28665 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28668 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28670 /* C code for the stuff we expand below.
28671 double xa = fabs (x), x2;
28672 if (!isless (xa, TWO52))
28674 x2 = (double)(long)x;
28681 if (HONOR_SIGNED_ZEROS (mode))
28682 return copysign (x2, x);
28685 enum machine_mode mode = GET_MODE (operand0);
28686 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28688 TWO52 = ix86_gen_TWO52 (mode);
28690 /* Temporary for holding the result, initialized to the input
28691 operand to ease control flow. */
28692 res = gen_reg_rtx (mode);
28693 emit_move_insn (res, operand1);
28695 /* xa = abs (operand1) */
28696 xa = ix86_expand_sse_fabs (res, &mask);
28698 /* if (!isless (xa, TWO52)) goto label; */
28699 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28701 /* xa = (double)(long)x */
28702 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28703 expand_fix (xi, res, 0);
28704 expand_float (xa, xi, 0);
28707 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28709 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28710 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28711 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28712 gen_rtx_AND (mode, one, tmp)));
28713 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28714 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28715 emit_move_insn (res, tmp);
28717 if (HONOR_SIGNED_ZEROS (mode))
28718 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28720 emit_label (label);
28721 LABEL_NUSES (label) = 1;
28723 emit_move_insn (operand0, res);
28726 /* Expand SSE sequence for computing round from OPERAND1 storing
28727 into OPERAND0. Sequence that works without relying on DImode truncation
28728 via cvttsd2siq that is only available on 64bit targets. */
28730 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28732 /* C code for the stuff we expand below.
28733 double xa = fabs (x), xa2, x2;
28734 if (!isless (xa, TWO52))
28736 Using the absolute value and copying back sign makes
28737 -0.0 -> -0.0 correct.
28738 xa2 = xa + TWO52 - TWO52;
28743 else if (dxa > 0.5)
28745 x2 = copysign (xa2, x);
28748 enum machine_mode mode = GET_MODE (operand0);
28749 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28751 TWO52 = ix86_gen_TWO52 (mode);
28753 /* Temporary for holding the result, initialized to the input
28754 operand to ease control flow. */
28755 res = gen_reg_rtx (mode);
28756 emit_move_insn (res, operand1);
28758 /* xa = abs (operand1) */
28759 xa = ix86_expand_sse_fabs (res, &mask);
28761 /* if (!isless (xa, TWO52)) goto label; */
28762 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28764 /* xa2 = xa + TWO52 - TWO52; */
28765 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28766 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28768 /* dxa = xa2 - xa; */
28769 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28771 /* generate 0.5, 1.0 and -0.5 */
28772 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28773 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28774 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28778 tmp = gen_reg_rtx (mode);
28779 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28780 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28781 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28782 gen_rtx_AND (mode, one, tmp)));
28783 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28784 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28785 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28786 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28787 gen_rtx_AND (mode, one, tmp)));
28788 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28790 /* res = copysign (xa2, operand1) */
28791 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28793 emit_label (label);
28794 LABEL_NUSES (label) = 1;
28796 emit_move_insn (operand0, res);
28799 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28802 ix86_expand_trunc (rtx operand0, rtx operand1)
28804 /* C code for SSE variant we expand below.
28805 double xa = fabs (x), x2;
28806 if (!isless (xa, TWO52))
28808 x2 = (double)(long)x;
28809 if (HONOR_SIGNED_ZEROS (mode))
28810 return copysign (x2, x);
28813 enum machine_mode mode = GET_MODE (operand0);
28814 rtx xa, xi, TWO52, label, res, mask;
28816 TWO52 = ix86_gen_TWO52 (mode);
28818 /* Temporary for holding the result, initialized to the input
28819 operand to ease control flow. */
28820 res = gen_reg_rtx (mode);
28821 emit_move_insn (res, operand1);
28823 /* xa = abs (operand1) */
28824 xa = ix86_expand_sse_fabs (res, &mask);
28826 /* if (!isless (xa, TWO52)) goto label; */
28827 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28829 /* x = (double)(long)x */
28830 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28831 expand_fix (xi, res, 0);
28832 expand_float (res, xi, 0);
28834 if (HONOR_SIGNED_ZEROS (mode))
28835 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28837 emit_label (label);
28838 LABEL_NUSES (label) = 1;
28840 emit_move_insn (operand0, res);
28843 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28846 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
28848 enum machine_mode mode = GET_MODE (operand0);
28849 rtx xa, mask, TWO52, label, one, res, smask, tmp;
28851 /* C code for SSE variant we expand below.
28852 double xa = fabs (x), x2;
28853 if (!isless (xa, TWO52))
28855 xa2 = xa + TWO52 - TWO52;
28859 x2 = copysign (xa2, x);
28863 TWO52 = ix86_gen_TWO52 (mode);
28865 /* Temporary for holding the result, initialized to the input
28866 operand to ease control flow. */
28867 res = gen_reg_rtx (mode);
28868 emit_move_insn (res, operand1);
28870 /* xa = abs (operand1) */
28871 xa = ix86_expand_sse_fabs (res, &smask);
28873 /* if (!isless (xa, TWO52)) goto label; */
28874 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28876 /* res = xa + TWO52 - TWO52; */
28877 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28878 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
28879 emit_move_insn (res, tmp);
28882 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28884 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28885 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
28886 emit_insn (gen_rtx_SET (VOIDmode, mask,
28887 gen_rtx_AND (mode, mask, one)));
28888 tmp = expand_simple_binop (mode, MINUS,
28889 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
28890 emit_move_insn (res, tmp);
28892 /* res = copysign (res, operand1) */
28893 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
28895 emit_label (label);
28896 LABEL_NUSES (label) = 1;
28898 emit_move_insn (operand0, res);
28901 /* Expand SSE sequence for computing round from OPERAND1 storing
28904 ix86_expand_round (rtx operand0, rtx operand1)
28906 /* C code for the stuff we're doing below:
28907 double xa = fabs (x);
28908 if (!isless (xa, TWO52))
28910 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28911 return copysign (xa, x);
28913 enum machine_mode mode = GET_MODE (operand0);
28914 rtx res, TWO52, xa, label, xi, half, mask;
28915 const struct real_format *fmt;
28916 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28918 /* Temporary for holding the result, initialized to the input
28919 operand to ease control flow. */
28920 res = gen_reg_rtx (mode);
28921 emit_move_insn (res, operand1);
28923 TWO52 = ix86_gen_TWO52 (mode);
28924 xa = ix86_expand_sse_fabs (res, &mask);
28925 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28927 /* load nextafter (0.5, 0.0) */
28928 fmt = REAL_MODE_FORMAT (mode);
28929 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28930 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28932 /* xa = xa + 0.5 */
28933 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
28934 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
28936 /* xa = (double)(int64_t)xa */
28937 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28938 expand_fix (xi, xa, 0);
28939 expand_float (xa, xi, 0);
28941 /* res = copysign (xa, operand1) */
28942 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
28944 emit_label (label);
28945 LABEL_NUSES (label) = 1;
28947 emit_move_insn (operand0, res);
28950 /* Table of valid machine attributes. */
28951 static const struct attribute_spec ix86_attribute_table[] =
28953 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28954 /* Stdcall attribute says callee is responsible for popping arguments
28955 if they are not variable. */
28956 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28957 /* Fastcall attribute says callee is responsible for popping arguments
28958 if they are not variable. */
28959 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28960 /* Cdecl attribute says the callee is a normal C declaration */
28961 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28962 /* Regparm attribute specifies how many integer arguments are to be
28963 passed in registers. */
28964 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
28965 /* Sseregparm attribute says we are using x86_64 calling conventions
28966 for FP arguments. */
28967 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28968 /* force_align_arg_pointer says this function realigns the stack at entry. */
28969 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
28970 false, true, true, ix86_handle_cconv_attribute },
28971 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28972 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
28973 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
28974 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
28976 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28977 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28978 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28979 SUBTARGET_ATTRIBUTE_TABLE,
28981 /* ms_abi and sysv_abi calling convention function attributes. */
28982 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28983 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28985 { NULL, 0, 0, false, false, false, NULL }
28988 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28990 x86_builtin_vectorization_cost (bool runtime_test)
28992 /* If the branch of the runtime test is taken - i.e. - the vectorized
28993 version is skipped - this incurs a misprediction cost (because the
28994 vectorized version is expected to be the fall-through). So we subtract
28995 the latency of a mispredicted branch from the costs that are incured
28996 when the vectorized version is executed.
28998 TODO: The values in individual target tables have to be tuned or new
28999 fields may be needed. For eg. on K8, the default branch path is the
29000 not-taken path. If the taken path is predicted correctly, the minimum
29001 penalty of going down the taken-path is 1 cycle. If the taken-path is
29002 not predicted correctly, then the minimum penalty is 10 cycles. */
29006 return (-(ix86_cost->cond_taken_branch_cost));
29012 /* This function returns the calling abi specific va_list type node.
29013 It returns the FNDECL specific va_list type. */
29016 ix86_fn_abi_va_list (tree fndecl)
29019 return va_list_type_node;
29020 gcc_assert (fndecl != NULL_TREE);
29022 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29023 return ms_va_list_type_node;
29025 return sysv_va_list_type_node;
29028 /* Returns the canonical va_list type specified by TYPE. If there
29029 is no valid TYPE provided, it return NULL_TREE. */
29032 ix86_canonical_va_list_type (tree type)
29036 /* Resolve references and pointers to va_list type. */
29037 if (INDIRECT_REF_P (type))
29038 type = TREE_TYPE (type);
29039 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29040 type = TREE_TYPE (type);
29044 wtype = va_list_type_node;
29045 gcc_assert (wtype != NULL_TREE);
29047 if (TREE_CODE (wtype) == ARRAY_TYPE)
29049 /* If va_list is an array type, the argument may have decayed
29050 to a pointer type, e.g. by being passed to another function.
29051 In that case, unwrap both types so that we can compare the
29052 underlying records. */
29053 if (TREE_CODE (htype) == ARRAY_TYPE
29054 || POINTER_TYPE_P (htype))
29056 wtype = TREE_TYPE (wtype);
29057 htype = TREE_TYPE (htype);
29060 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29061 return va_list_type_node;
29062 wtype = sysv_va_list_type_node;
29063 gcc_assert (wtype != NULL_TREE);
29065 if (TREE_CODE (wtype) == ARRAY_TYPE)
29067 /* If va_list is an array type, the argument may have decayed
29068 to a pointer type, e.g. by being passed to another function.
29069 In that case, unwrap both types so that we can compare the
29070 underlying records. */
29071 if (TREE_CODE (htype) == ARRAY_TYPE
29072 || POINTER_TYPE_P (htype))
29074 wtype = TREE_TYPE (wtype);
29075 htype = TREE_TYPE (htype);
29078 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29079 return sysv_va_list_type_node;
29080 wtype = ms_va_list_type_node;
29081 gcc_assert (wtype != NULL_TREE);
29083 if (TREE_CODE (wtype) == ARRAY_TYPE)
29085 /* If va_list is an array type, the argument may have decayed
29086 to a pointer type, e.g. by being passed to another function.
29087 In that case, unwrap both types so that we can compare the
29088 underlying records. */
29089 if (TREE_CODE (htype) == ARRAY_TYPE
29090 || POINTER_TYPE_P (htype))
29092 wtype = TREE_TYPE (wtype);
29093 htype = TREE_TYPE (htype);
29096 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29097 return ms_va_list_type_node;
29100 return std_canonical_va_list_type (type);
29103 /* Iterate through the target-specific builtin types for va_list.
29104 IDX denotes the iterator, *PTREE is set to the result type of
29105 the va_list builtin, and *PNAME to its internal type.
29106 Returns zero if there is no element for this index, otherwise
29107 IDX should be increased upon the next call.
29108 Note, do not iterate a base builtin's name like __builtin_va_list.
29109 Used from c_common_nodes_and_builtins. */
29112 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29118 *ptree = ms_va_list_type_node;
29119 *pname = "__builtin_ms_va_list";
29122 *ptree = sysv_va_list_type_node;
29123 *pname = "__builtin_sysv_va_list";
29131 /* Initialize the GCC target structure. */
29132 #undef TARGET_RETURN_IN_MEMORY
29133 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29135 #undef TARGET_LEGITIMIZE_ADDRESS
29136 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
29138 #undef TARGET_ATTRIBUTE_TABLE
29139 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29140 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29141 # undef TARGET_MERGE_DECL_ATTRIBUTES
29142 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29145 #undef TARGET_COMP_TYPE_ATTRIBUTES
29146 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29148 #undef TARGET_INIT_BUILTINS
29149 #define TARGET_INIT_BUILTINS ix86_init_builtins
29150 #undef TARGET_EXPAND_BUILTIN
29151 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29153 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29154 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29155 ix86_builtin_vectorized_function
29157 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29158 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29160 #undef TARGET_BUILTIN_RECIPROCAL
29161 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29163 #undef TARGET_ASM_FUNCTION_EPILOGUE
29164 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29166 #undef TARGET_ENCODE_SECTION_INFO
29167 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29168 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29170 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29173 #undef TARGET_ASM_OPEN_PAREN
29174 #define TARGET_ASM_OPEN_PAREN ""
29175 #undef TARGET_ASM_CLOSE_PAREN
29176 #define TARGET_ASM_CLOSE_PAREN ""
29178 #undef TARGET_ASM_BYTE_OP
29179 #define TARGET_ASM_BYTE_OP ASM_BYTE
29181 #undef TARGET_ASM_ALIGNED_HI_OP
29182 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29183 #undef TARGET_ASM_ALIGNED_SI_OP
29184 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29186 #undef TARGET_ASM_ALIGNED_DI_OP
29187 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29190 #undef TARGET_ASM_UNALIGNED_HI_OP
29191 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29192 #undef TARGET_ASM_UNALIGNED_SI_OP
29193 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29194 #undef TARGET_ASM_UNALIGNED_DI_OP
29195 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29197 #undef TARGET_SCHED_ADJUST_COST
29198 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29199 #undef TARGET_SCHED_ISSUE_RATE
29200 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29201 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29202 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29203 ia32_multipass_dfa_lookahead
29205 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29206 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29209 #undef TARGET_HAVE_TLS
29210 #define TARGET_HAVE_TLS true
29212 #undef TARGET_CANNOT_FORCE_CONST_MEM
29213 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29214 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29215 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29217 #undef TARGET_DELEGITIMIZE_ADDRESS
29218 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29220 #undef TARGET_MS_BITFIELD_LAYOUT_P
29221 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29224 #undef TARGET_BINDS_LOCAL_P
29225 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29227 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29228 #undef TARGET_BINDS_LOCAL_P
29229 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29232 #undef TARGET_ASM_OUTPUT_MI_THUNK
29233 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29234 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29235 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29237 #undef TARGET_ASM_FILE_START
29238 #define TARGET_ASM_FILE_START x86_file_start
29240 #undef TARGET_DEFAULT_TARGET_FLAGS
29241 #define TARGET_DEFAULT_TARGET_FLAGS \
29243 | TARGET_SUBTARGET_DEFAULT \
29244 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29246 #undef TARGET_HANDLE_OPTION
29247 #define TARGET_HANDLE_OPTION ix86_handle_option
29249 #undef TARGET_RTX_COSTS
29250 #define TARGET_RTX_COSTS ix86_rtx_costs
29251 #undef TARGET_ADDRESS_COST
29252 #define TARGET_ADDRESS_COST ix86_address_cost
29254 #undef TARGET_FIXED_CONDITION_CODE_REGS
29255 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29256 #undef TARGET_CC_MODES_COMPATIBLE
29257 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29259 #undef TARGET_MACHINE_DEPENDENT_REORG
29260 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29262 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29263 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29265 #undef TARGET_BUILD_BUILTIN_VA_LIST
29266 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29268 #undef TARGET_FN_ABI_VA_LIST
29269 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29271 #undef TARGET_CANONICAL_VA_LIST_TYPE
29272 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29274 #undef TARGET_EXPAND_BUILTIN_VA_START
29275 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29277 #undef TARGET_MD_ASM_CLOBBERS
29278 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29280 #undef TARGET_PROMOTE_PROTOTYPES
29281 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29282 #undef TARGET_STRUCT_VALUE_RTX
29283 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29284 #undef TARGET_SETUP_INCOMING_VARARGS
29285 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29286 #undef TARGET_MUST_PASS_IN_STACK
29287 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29288 #undef TARGET_PASS_BY_REFERENCE
29289 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29290 #undef TARGET_INTERNAL_ARG_POINTER
29291 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29292 #undef TARGET_UPDATE_STACK_BOUNDARY
29293 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29294 #undef TARGET_GET_DRAP_RTX
29295 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29296 #undef TARGET_STRICT_ARGUMENT_NAMING
29297 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29299 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29300 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29302 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29303 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29305 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29306 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29308 #undef TARGET_C_MODE_FOR_SUFFIX
29309 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29312 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29313 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29316 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29317 #undef TARGET_INSERT_ATTRIBUTES
29318 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29321 #undef TARGET_MANGLE_TYPE
29322 #define TARGET_MANGLE_TYPE ix86_mangle_type
29324 #undef TARGET_STACK_PROTECT_FAIL
29325 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29327 #undef TARGET_FUNCTION_VALUE
29328 #define TARGET_FUNCTION_VALUE ix86_function_value
29330 #undef TARGET_SECONDARY_RELOAD
29331 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29333 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29334 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29336 #undef TARGET_SET_CURRENT_FUNCTION
29337 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29339 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29340 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29342 #undef TARGET_OPTION_SAVE
29343 #define TARGET_OPTION_SAVE ix86_function_specific_save
29345 #undef TARGET_OPTION_RESTORE
29346 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29348 #undef TARGET_OPTION_PRINT
29349 #define TARGET_OPTION_PRINT ix86_function_specific_print
29351 #undef TARGET_CAN_INLINE_P
29352 #define TARGET_CAN_INLINE_P ix86_can_inline_p
29354 #undef TARGET_EXPAND_TO_RTL_HOOK
29355 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29357 #undef TARGET_LEGITIMATE_ADDRESS_P
29358 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
29360 #undef TARGET_IRA_COVER_CLASSES
29361 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
29363 #undef TARGET_FRAME_POINTER_REQUIRED
29364 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
29366 #undef TARGET_CAN_ELIMINATE
29367 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
29369 struct gcc_target targetm = TARGET_INITIALIZER;
29371 #include "gt-i386.h"