1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static int ix86_function_regparm (const_tree, const_tree);
1883 static void ix86_compute_frame_layout (struct ix86_frame *);
1884 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1886 static void ix86_add_new_builtins (int);
1888 enum ix86_function_specific_strings
1890 IX86_FUNCTION_SPECIFIC_ARCH,
1891 IX86_FUNCTION_SPECIFIC_TUNE,
1892 IX86_FUNCTION_SPECIFIC_FPMATH,
1893 IX86_FUNCTION_SPECIFIC_MAX
1896 static char *ix86_target_string (int, int, const char *, const char *,
1897 const char *, bool);
1898 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1899 static void ix86_function_specific_save (struct cl_target_option *);
1900 static void ix86_function_specific_restore (struct cl_target_option *);
1901 static void ix86_function_specific_print (FILE *, int,
1902 struct cl_target_option *);
1903 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1904 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1905 static bool ix86_can_inline_p (tree, tree);
1906 static void ix86_set_current_function (tree);
1908 static enum calling_abi ix86_function_abi (const_tree);
1911 /* The svr4 ABI for the i386 says that records and unions are returned
1913 #ifndef DEFAULT_PCC_STRUCT_RETURN
1914 #define DEFAULT_PCC_STRUCT_RETURN 1
1917 /* Whether -mtune= or -march= were specified */
1918 static int ix86_tune_defaulted;
1919 static int ix86_arch_specified;
1921 /* Bit flags that specify the ISA we are compiling for. */
1922 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1924 /* A mask of ix86_isa_flags that includes bit X if X
1925 was set or cleared on the command line. */
1926 static int ix86_isa_flags_explicit;
1928 /* Define a set of ISAs which are available when a given ISA is
1929 enabled. MMX and SSE ISAs are handled separately. */
1931 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1932 #define OPTION_MASK_ISA_3DNOW_SET \
1933 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1935 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1936 #define OPTION_MASK_ISA_SSE2_SET \
1937 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1938 #define OPTION_MASK_ISA_SSE3_SET \
1939 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1940 #define OPTION_MASK_ISA_SSSE3_SET \
1941 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1942 #define OPTION_MASK_ISA_SSE4_1_SET \
1943 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_2_SET \
1945 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1946 #define OPTION_MASK_ISA_AVX_SET \
1947 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1948 #define OPTION_MASK_ISA_FMA_SET \
1949 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1951 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1953 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1955 #define OPTION_MASK_ISA_SSE4A_SET \
1956 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1957 #define OPTION_MASK_ISA_SSE5_SET \
1958 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1960 /* AES and PCLMUL need SSE2 because they use xmm registers */
1961 #define OPTION_MASK_ISA_AES_SET \
1962 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1963 #define OPTION_MASK_ISA_PCLMUL_SET \
1964 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1966 #define OPTION_MASK_ISA_ABM_SET \
1967 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1969 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1970 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1971 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1972 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1974 /* Define a set of ISAs which aren't available when a given ISA is
1975 disabled. MMX and SSE ISAs are handled separately. */
1977 #define OPTION_MASK_ISA_MMX_UNSET \
1978 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1979 #define OPTION_MASK_ISA_3DNOW_UNSET \
1980 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1981 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1983 #define OPTION_MASK_ISA_SSE_UNSET \
1984 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1985 #define OPTION_MASK_ISA_SSE2_UNSET \
1986 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1987 #define OPTION_MASK_ISA_SSE3_UNSET \
1988 (OPTION_MASK_ISA_SSE3 \
1989 | OPTION_MASK_ISA_SSSE3_UNSET \
1990 | OPTION_MASK_ISA_SSE4A_UNSET )
1991 #define OPTION_MASK_ISA_SSSE3_UNSET \
1992 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1993 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1994 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1995 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1996 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1997 #define OPTION_MASK_ISA_AVX_UNSET \
1998 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1999 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2001 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2003 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2005 #define OPTION_MASK_ISA_SSE4A_UNSET \
2006 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
2007 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
2008 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2009 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2010 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2011 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2012 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2013 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2014 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2016 /* Vectorization library interface and handlers. */
2017 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2018 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2019 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2021 /* Processor target table, indexed by processor number */
2024 const struct processor_costs *cost; /* Processor costs */
2025 const int align_loop; /* Default alignments. */
2026 const int align_loop_max_skip;
2027 const int align_jump;
2028 const int align_jump_max_skip;
2029 const int align_func;
2032 static const struct ptt processor_target_table[PROCESSOR_max] =
2034 {&i386_cost, 4, 3, 4, 3, 4},
2035 {&i486_cost, 16, 15, 16, 15, 16},
2036 {&pentium_cost, 16, 7, 16, 7, 16},
2037 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2038 {&geode_cost, 0, 0, 0, 0, 0},
2039 {&k6_cost, 32, 7, 32, 7, 32},
2040 {&athlon_cost, 16, 7, 16, 7, 16},
2041 {&pentium4_cost, 0, 0, 0, 0, 0},
2042 {&k8_cost, 16, 7, 16, 7, 16},
2043 {&nocona_cost, 0, 0, 0, 0, 0},
2044 {&core2_cost, 16, 10, 16, 10, 16},
2045 {&generic32_cost, 16, 7, 16, 7, 16},
2046 {&generic64_cost, 16, 10, 16, 10, 16},
2047 {&amdfam10_cost, 32, 24, 32, 7, 32},
2048 {&atom_cost, 16, 7, 16, 7, 16}
2051 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2077 /* Implement TARGET_HANDLE_OPTION. */
2080 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2087 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2088 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2092 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2093 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2100 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2101 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2105 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2106 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2116 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2117 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2121 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2122 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2129 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2130 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2134 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2135 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2142 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2147 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2148 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2155 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2160 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2161 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2168 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2173 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2174 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2181 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2186 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2187 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2194 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2199 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2200 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2207 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2212 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2213 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2218 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2219 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2223 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2224 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2230 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2231 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2235 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2236 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2243 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2244 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2248 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2249 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2256 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2257 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2261 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2262 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2269 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2270 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2274 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2275 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2282 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2283 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2287 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2288 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2295 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2296 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2300 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2301 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2308 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2309 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2313 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2314 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2321 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2322 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2326 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2327 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2334 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2335 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2339 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2340 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2349 /* Return a string the documents the current -m options. The caller is
2350 responsible for freeing the string. */
2353 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2354 const char *fpmath, bool add_nl_p)
2356 struct ix86_target_opts
2358 const char *option; /* option string */
2359 int mask; /* isa mask options */
2362 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2363 preceding options while match those first. */
2364 static struct ix86_target_opts isa_opts[] =
2366 { "-m64", OPTION_MASK_ISA_64BIT },
2367 { "-msse5", OPTION_MASK_ISA_SSE5 },
2368 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2369 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2370 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2371 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2372 { "-msse3", OPTION_MASK_ISA_SSE3 },
2373 { "-msse2", OPTION_MASK_ISA_SSE2 },
2374 { "-msse", OPTION_MASK_ISA_SSE },
2375 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2376 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2377 { "-mmmx", OPTION_MASK_ISA_MMX },
2378 { "-mabm", OPTION_MASK_ISA_ABM },
2379 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2380 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2381 { "-maes", OPTION_MASK_ISA_AES },
2382 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2386 static struct ix86_target_opts flag_opts[] =
2388 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2389 { "-m80387", MASK_80387 },
2390 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2391 { "-malign-double", MASK_ALIGN_DOUBLE },
2392 { "-mcld", MASK_CLD },
2393 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2394 { "-mieee-fp", MASK_IEEE_FP },
2395 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2396 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2397 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2398 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2399 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2400 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2401 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2402 { "-mno-red-zone", MASK_NO_RED_ZONE },
2403 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2404 { "-mrecip", MASK_RECIP },
2405 { "-mrtd", MASK_RTD },
2406 { "-msseregparm", MASK_SSEREGPARM },
2407 { "-mstack-arg-probe", MASK_STACK_PROBE },
2408 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2411 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2414 char target_other[40];
2423 memset (opts, '\0', sizeof (opts));
2425 /* Add -march= option. */
2428 opts[num][0] = "-march=";
2429 opts[num++][1] = arch;
2432 /* Add -mtune= option. */
2435 opts[num][0] = "-mtune=";
2436 opts[num++][1] = tune;
2439 /* Pick out the options in isa options. */
2440 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2442 if ((isa & isa_opts[i].mask) != 0)
2444 opts[num++][0] = isa_opts[i].option;
2445 isa &= ~ isa_opts[i].mask;
2449 if (isa && add_nl_p)
2451 opts[num++][0] = isa_other;
2452 sprintf (isa_other, "(other isa: 0x%x)", isa);
2455 /* Add flag options. */
2456 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2458 if ((flags & flag_opts[i].mask) != 0)
2460 opts[num++][0] = flag_opts[i].option;
2461 flags &= ~ flag_opts[i].mask;
2465 if (flags && add_nl_p)
2467 opts[num++][0] = target_other;
2468 sprintf (target_other, "(other flags: 0x%x)", isa);
2471 /* Add -fpmath= option. */
2474 opts[num][0] = "-mfpmath=";
2475 opts[num++][1] = fpmath;
2482 gcc_assert (num < ARRAY_SIZE (opts));
2484 /* Size the string. */
2486 sep_len = (add_nl_p) ? 3 : 1;
2487 for (i = 0; i < num; i++)
2490 for (j = 0; j < 2; j++)
2492 len += strlen (opts[i][j]);
2495 /* Build the string. */
2496 ret = ptr = (char *) xmalloc (len);
2499 for (i = 0; i < num; i++)
2503 for (j = 0; j < 2; j++)
2504 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2511 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2519 for (j = 0; j < 2; j++)
2522 memcpy (ptr, opts[i][j], len2[j]);
2524 line_len += len2[j];
2529 gcc_assert (ret + len >= ptr);
2534 /* Function that is callable from the debugger to print the current
2537 ix86_debug_options (void)
2539 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2540 ix86_arch_string, ix86_tune_string,
2541 ix86_fpmath_string, true);
2545 fprintf (stderr, "%s\n\n", opts);
2549 fprintf (stderr, "<no options>\n\n");
2554 /* Sometimes certain combinations of command options do not make
2555 sense on a particular target machine. You can define a macro
2556 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2557 defined, is executed once just after all the command options have
2560 Don't use this macro to turn on various extra optimizations for
2561 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2564 override_options (bool main_args_p)
2567 unsigned int ix86_arch_mask, ix86_tune_mask;
2572 /* Comes from final.c -- no real reason to change it. */
2573 #define MAX_CODE_ALIGN 16
2581 PTA_PREFETCH_SSE = 1 << 4,
2583 PTA_3DNOW_A = 1 << 6,
2587 PTA_POPCNT = 1 << 10,
2589 PTA_SSE4A = 1 << 12,
2590 PTA_NO_SAHF = 1 << 13,
2591 PTA_SSE4_1 = 1 << 14,
2592 PTA_SSE4_2 = 1 << 15,
2595 PTA_PCLMUL = 1 << 18,
2603 const char *const name; /* processor name or nickname. */
2604 const enum processor_type processor;
2605 const enum attr_cpu schedule;
2606 const unsigned /*enum pta_flags*/ flags;
2608 const processor_alias_table[] =
2610 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2611 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2612 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2613 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2614 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2615 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2616 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2617 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2618 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2619 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2620 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2621 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2622 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2624 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2626 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2627 PTA_MMX | PTA_SSE | PTA_SSE2},
2628 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2629 PTA_MMX |PTA_SSE | PTA_SSE2},
2630 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2631 PTA_MMX | PTA_SSE | PTA_SSE2},
2632 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2633 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2634 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2635 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2636 | PTA_CX16 | PTA_NO_SAHF},
2637 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2638 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2639 | PTA_SSSE3 | PTA_CX16},
2640 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2641 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2642 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2643 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2644 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2645 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2646 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2647 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2648 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2649 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2650 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2651 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2652 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2653 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2654 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2655 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2656 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2657 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2658 {"x86-64", PROCESSOR_K8, CPU_K8,
2659 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2660 {"k8", PROCESSOR_K8, CPU_K8,
2661 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2662 | PTA_SSE2 | PTA_NO_SAHF},
2663 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2664 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2665 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2666 {"opteron", PROCESSOR_K8, CPU_K8,
2667 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2668 | PTA_SSE2 | PTA_NO_SAHF},
2669 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2670 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2671 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2672 {"athlon64", PROCESSOR_K8, CPU_K8,
2673 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2674 | PTA_SSE2 | PTA_NO_SAHF},
2675 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2676 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2677 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2678 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2679 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2680 | PTA_SSE2 | PTA_NO_SAHF},
2681 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2682 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2683 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2684 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2685 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2686 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2687 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2688 0 /* flags are only used for -march switch. */ },
2689 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2690 PTA_64BIT /* flags are only used for -march switch. */ },
2693 int const pta_size = ARRAY_SIZE (processor_alias_table);
2695 /* Set up prefix/suffix so the error messages refer to either the command
2696 line argument, or the attribute(target). */
2705 prefix = "option(\"";
2710 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2711 SUBTARGET_OVERRIDE_OPTIONS;
2714 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2715 SUBSUBTARGET_OVERRIDE_OPTIONS;
2718 /* -fPIC is the default for x86_64. */
2719 if (TARGET_MACHO && TARGET_64BIT)
2722 /* Set the default values for switches whose default depends on TARGET_64BIT
2723 in case they weren't overwritten by command line options. */
2726 /* Mach-O doesn't support omitting the frame pointer for now. */
2727 if (flag_omit_frame_pointer == 2)
2728 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2729 if (flag_asynchronous_unwind_tables == 2)
2730 flag_asynchronous_unwind_tables = 1;
2731 if (flag_pcc_struct_return == 2)
2732 flag_pcc_struct_return = 0;
2736 if (flag_omit_frame_pointer == 2)
2737 flag_omit_frame_pointer = 0;
2738 if (flag_asynchronous_unwind_tables == 2)
2739 flag_asynchronous_unwind_tables = 0;
2740 if (flag_pcc_struct_return == 2)
2741 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2744 /* Need to check -mtune=generic first. */
2745 if (ix86_tune_string)
2747 if (!strcmp (ix86_tune_string, "generic")
2748 || !strcmp (ix86_tune_string, "i686")
2749 /* As special support for cross compilers we read -mtune=native
2750 as -mtune=generic. With native compilers we won't see the
2751 -mtune=native, as it was changed by the driver. */
2752 || !strcmp (ix86_tune_string, "native"))
2755 ix86_tune_string = "generic64";
2757 ix86_tune_string = "generic32";
2759 /* If this call is for setting the option attribute, allow the
2760 generic32/generic64 that was previously set. */
2761 else if (!main_args_p
2762 && (!strcmp (ix86_tune_string, "generic32")
2763 || !strcmp (ix86_tune_string, "generic64")))
2765 else if (!strncmp (ix86_tune_string, "generic", 7))
2766 error ("bad value (%s) for %stune=%s %s",
2767 ix86_tune_string, prefix, suffix, sw);
2771 if (ix86_arch_string)
2772 ix86_tune_string = ix86_arch_string;
2773 if (!ix86_tune_string)
2775 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2776 ix86_tune_defaulted = 1;
2779 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2780 need to use a sensible tune option. */
2781 if (!strcmp (ix86_tune_string, "generic")
2782 || !strcmp (ix86_tune_string, "x86-64")
2783 || !strcmp (ix86_tune_string, "i686"))
2786 ix86_tune_string = "generic64";
2788 ix86_tune_string = "generic32";
2791 if (ix86_stringop_string)
2793 if (!strcmp (ix86_stringop_string, "rep_byte"))
2794 stringop_alg = rep_prefix_1_byte;
2795 else if (!strcmp (ix86_stringop_string, "libcall"))
2796 stringop_alg = libcall;
2797 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2798 stringop_alg = rep_prefix_4_byte;
2799 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2801 /* rep; movq isn't available in 32-bit code. */
2802 stringop_alg = rep_prefix_8_byte;
2803 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2804 stringop_alg = loop_1_byte;
2805 else if (!strcmp (ix86_stringop_string, "loop"))
2806 stringop_alg = loop;
2807 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2808 stringop_alg = unrolled_loop;
2810 error ("bad value (%s) for %sstringop-strategy=%s %s",
2811 ix86_stringop_string, prefix, suffix, sw);
2813 if (!strcmp (ix86_tune_string, "x86-64"))
2814 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2815 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2816 prefix, suffix, prefix, suffix, prefix, suffix);
2818 if (!ix86_arch_string)
2819 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2821 ix86_arch_specified = 1;
2823 if (!strcmp (ix86_arch_string, "generic"))
2824 error ("generic CPU can be used only for %stune=%s %s",
2825 prefix, suffix, sw);
2826 if (!strncmp (ix86_arch_string, "generic", 7))
2827 error ("bad value (%s) for %sarch=%s %s",
2828 ix86_arch_string, prefix, suffix, sw);
2830 /* Validate -mabi= value. */
2831 if (ix86_abi_string)
2833 if (strcmp (ix86_abi_string, "sysv") == 0)
2834 ix86_abi = SYSV_ABI;
2835 else if (strcmp (ix86_abi_string, "ms") == 0)
2838 error ("unknown ABI (%s) for %sabi=%s %s",
2839 ix86_abi_string, prefix, suffix, sw);
2842 ix86_abi = DEFAULT_ABI;
2844 if (ix86_cmodel_string != 0)
2846 if (!strcmp (ix86_cmodel_string, "small"))
2847 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2848 else if (!strcmp (ix86_cmodel_string, "medium"))
2849 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2850 else if (!strcmp (ix86_cmodel_string, "large"))
2851 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2853 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2854 else if (!strcmp (ix86_cmodel_string, "32"))
2855 ix86_cmodel = CM_32;
2856 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2857 ix86_cmodel = CM_KERNEL;
2859 error ("bad value (%s) for %scmodel=%s %s",
2860 ix86_cmodel_string, prefix, suffix, sw);
2864 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2865 use of rip-relative addressing. This eliminates fixups that
2866 would otherwise be needed if this object is to be placed in a
2867 DLL, and is essentially just as efficient as direct addressing. */
2868 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2869 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2870 else if (TARGET_64BIT)
2871 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2873 ix86_cmodel = CM_32;
2875 if (ix86_asm_string != 0)
2878 && !strcmp (ix86_asm_string, "intel"))
2879 ix86_asm_dialect = ASM_INTEL;
2880 else if (!strcmp (ix86_asm_string, "att"))
2881 ix86_asm_dialect = ASM_ATT;
2883 error ("bad value (%s) for %sasm=%s %s",
2884 ix86_asm_string, prefix, suffix, sw);
2886 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2887 error ("code model %qs not supported in the %s bit mode",
2888 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2889 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2890 sorry ("%i-bit mode not compiled in",
2891 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2893 for (i = 0; i < pta_size; i++)
2894 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2896 ix86_schedule = processor_alias_table[i].schedule;
2897 ix86_arch = processor_alias_table[i].processor;
2898 /* Default cpu tuning to the architecture. */
2899 ix86_tune = ix86_arch;
2901 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2902 error ("CPU you selected does not support x86-64 "
2905 if (processor_alias_table[i].flags & PTA_MMX
2906 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2907 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2908 if (processor_alias_table[i].flags & PTA_3DNOW
2909 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2910 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2911 if (processor_alias_table[i].flags & PTA_3DNOW_A
2912 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2913 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2914 if (processor_alias_table[i].flags & PTA_SSE
2915 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2916 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2917 if (processor_alias_table[i].flags & PTA_SSE2
2918 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2919 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2920 if (processor_alias_table[i].flags & PTA_SSE3
2921 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2922 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2923 if (processor_alias_table[i].flags & PTA_SSSE3
2924 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2925 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2926 if (processor_alias_table[i].flags & PTA_SSE4_1
2927 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2928 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2929 if (processor_alias_table[i].flags & PTA_SSE4_2
2930 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2931 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2932 if (processor_alias_table[i].flags & PTA_AVX
2933 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2934 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2935 if (processor_alias_table[i].flags & PTA_FMA
2936 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2937 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2938 if (processor_alias_table[i].flags & PTA_SSE4A
2939 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2940 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2941 if (processor_alias_table[i].flags & PTA_SSE5
2942 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2943 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2944 if (processor_alias_table[i].flags & PTA_ABM
2945 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2946 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2947 if (processor_alias_table[i].flags & PTA_CX16
2948 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2949 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2950 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2951 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2952 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2953 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2954 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2955 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2956 if (processor_alias_table[i].flags & PTA_MOVBE
2957 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2958 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2959 if (processor_alias_table[i].flags & PTA_AES
2960 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2961 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2962 if (processor_alias_table[i].flags & PTA_PCLMUL
2963 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2964 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2965 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2966 x86_prefetch_sse = true;
2972 error ("bad value (%s) for %sarch=%s %s",
2973 ix86_arch_string, prefix, suffix, sw);
2975 ix86_arch_mask = 1u << ix86_arch;
2976 for (i = 0; i < X86_ARCH_LAST; ++i)
2977 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2979 for (i = 0; i < pta_size; i++)
2980 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2982 ix86_schedule = processor_alias_table[i].schedule;
2983 ix86_tune = processor_alias_table[i].processor;
2984 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2986 if (ix86_tune_defaulted)
2988 ix86_tune_string = "x86-64";
2989 for (i = 0; i < pta_size; i++)
2990 if (! strcmp (ix86_tune_string,
2991 processor_alias_table[i].name))
2993 ix86_schedule = processor_alias_table[i].schedule;
2994 ix86_tune = processor_alias_table[i].processor;
2997 error ("CPU you selected does not support x86-64 "
3000 /* Intel CPUs have always interpreted SSE prefetch instructions as
3001 NOPs; so, we can enable SSE prefetch instructions even when
3002 -mtune (rather than -march) points us to a processor that has them.
3003 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3004 higher processors. */
3006 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3007 x86_prefetch_sse = true;
3011 error ("bad value (%s) for %stune=%s %s",
3012 ix86_tune_string, prefix, suffix, sw);
3014 ix86_tune_mask = 1u << ix86_tune;
3015 for (i = 0; i < X86_TUNE_LAST; ++i)
3016 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3019 ix86_cost = &ix86_size_cost;
3021 ix86_cost = processor_target_table[ix86_tune].cost;
3023 /* Arrange to set up i386_stack_locals for all functions. */
3024 init_machine_status = ix86_init_machine_status;
3026 /* Validate -mregparm= value. */
3027 if (ix86_regparm_string)
3030 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3031 i = atoi (ix86_regparm_string);
3032 if (i < 0 || i > REGPARM_MAX)
3033 error ("%sregparm=%d%s is not between 0 and %d",
3034 prefix, i, suffix, REGPARM_MAX);
3039 ix86_regparm = REGPARM_MAX;
3041 /* If the user has provided any of the -malign-* options,
3042 warn and use that value only if -falign-* is not set.
3043 Remove this code in GCC 3.2 or later. */
3044 if (ix86_align_loops_string)
3046 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3047 prefix, suffix, suffix);
3048 if (align_loops == 0)
3050 i = atoi (ix86_align_loops_string);
3051 if (i < 0 || i > MAX_CODE_ALIGN)
3052 error ("%salign-loops=%d%s is not between 0 and %d",
3053 prefix, i, suffix, MAX_CODE_ALIGN);
3055 align_loops = 1 << i;
3059 if (ix86_align_jumps_string)
3061 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3062 prefix, suffix, suffix);
3063 if (align_jumps == 0)
3065 i = atoi (ix86_align_jumps_string);
3066 if (i < 0 || i > MAX_CODE_ALIGN)
3067 error ("%salign-loops=%d%s is not between 0 and %d",
3068 prefix, i, suffix, MAX_CODE_ALIGN);
3070 align_jumps = 1 << i;
3074 if (ix86_align_funcs_string)
3076 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3077 prefix, suffix, suffix);
3078 if (align_functions == 0)
3080 i = atoi (ix86_align_funcs_string);
3081 if (i < 0 || i > MAX_CODE_ALIGN)
3082 error ("%salign-loops=%d%s is not between 0 and %d",
3083 prefix, i, suffix, MAX_CODE_ALIGN);
3085 align_functions = 1 << i;
3089 /* Default align_* from the processor table. */
3090 if (align_loops == 0)
3092 align_loops = processor_target_table[ix86_tune].align_loop;
3093 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3095 if (align_jumps == 0)
3097 align_jumps = processor_target_table[ix86_tune].align_jump;
3098 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3100 if (align_functions == 0)
3102 align_functions = processor_target_table[ix86_tune].align_func;
3105 /* Validate -mbranch-cost= value, or provide default. */
3106 ix86_branch_cost = ix86_cost->branch_cost;
3107 if (ix86_branch_cost_string)
3109 i = atoi (ix86_branch_cost_string);
3111 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3113 ix86_branch_cost = i;
3115 if (ix86_section_threshold_string)
3117 i = atoi (ix86_section_threshold_string);
3119 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3121 ix86_section_threshold = i;
3124 if (ix86_tls_dialect_string)
3126 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3127 ix86_tls_dialect = TLS_DIALECT_GNU;
3128 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3129 ix86_tls_dialect = TLS_DIALECT_GNU2;
3130 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3131 ix86_tls_dialect = TLS_DIALECT_SUN;
3133 error ("bad value (%s) for %stls-dialect=%s %s",
3134 ix86_tls_dialect_string, prefix, suffix, sw);
3137 if (ix87_precision_string)
3139 i = atoi (ix87_precision_string);
3140 if (i != 32 && i != 64 && i != 80)
3141 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3146 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3148 /* Enable by default the SSE and MMX builtins. Do allow the user to
3149 explicitly disable any of these. In particular, disabling SSE and
3150 MMX for kernel code is extremely useful. */
3151 if (!ix86_arch_specified)
3153 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3154 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3157 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3161 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3163 if (!ix86_arch_specified)
3165 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3167 /* i386 ABI does not specify red zone. It still makes sense to use it
3168 when programmer takes care to stack from being destroyed. */
3169 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3170 target_flags |= MASK_NO_RED_ZONE;
3173 /* Keep nonleaf frame pointers. */
3174 if (flag_omit_frame_pointer)
3175 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3176 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3177 flag_omit_frame_pointer = 1;
3179 /* If we're doing fast math, we don't care about comparison order
3180 wrt NaNs. This lets us use a shorter comparison sequence. */
3181 if (flag_finite_math_only)
3182 target_flags &= ~MASK_IEEE_FP;
3184 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3185 since the insns won't need emulation. */
3186 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3187 target_flags &= ~MASK_NO_FANCY_MATH_387;
3189 /* Likewise, if the target doesn't have a 387, or we've specified
3190 software floating point, don't use 387 inline intrinsics. */
3192 target_flags |= MASK_NO_FANCY_MATH_387;
3194 /* Turn on MMX builtins for -msse. */
3197 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3198 x86_prefetch_sse = true;
3201 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3202 if (TARGET_SSE4_2 || TARGET_ABM)
3203 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3205 /* Validate -mpreferred-stack-boundary= value or default it to
3206 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3207 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3208 if (ix86_preferred_stack_boundary_string)
3210 i = atoi (ix86_preferred_stack_boundary_string);
3211 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3212 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3213 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3215 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3218 /* Set the default value for -mstackrealign. */
3219 if (ix86_force_align_arg_pointer == -1)
3220 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3222 /* Validate -mincoming-stack-boundary= value or default it to
3223 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3224 if (ix86_force_align_arg_pointer)
3225 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3227 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3228 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3229 if (ix86_incoming_stack_boundary_string)
3231 i = atoi (ix86_incoming_stack_boundary_string);
3232 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3233 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3234 i, TARGET_64BIT ? 4 : 2);
3237 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3238 ix86_incoming_stack_boundary
3239 = ix86_user_incoming_stack_boundary;
3243 /* Accept -msseregparm only if at least SSE support is enabled. */
3244 if (TARGET_SSEREGPARM
3246 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3248 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3249 if (ix86_fpmath_string != 0)
3251 if (! strcmp (ix86_fpmath_string, "387"))
3252 ix86_fpmath = FPMATH_387;
3253 else if (! strcmp (ix86_fpmath_string, "sse"))
3257 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3258 ix86_fpmath = FPMATH_387;
3261 ix86_fpmath = FPMATH_SSE;
3263 else if (! strcmp (ix86_fpmath_string, "387,sse")
3264 || ! strcmp (ix86_fpmath_string, "387+sse")
3265 || ! strcmp (ix86_fpmath_string, "sse,387")
3266 || ! strcmp (ix86_fpmath_string, "sse+387")
3267 || ! strcmp (ix86_fpmath_string, "both"))
3271 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3272 ix86_fpmath = FPMATH_387;
3274 else if (!TARGET_80387)
3276 warning (0, "387 instruction set disabled, using SSE arithmetics");
3277 ix86_fpmath = FPMATH_SSE;
3280 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3283 error ("bad value (%s) for %sfpmath=%s %s",
3284 ix86_fpmath_string, prefix, suffix, sw);
3287 /* If the i387 is disabled, then do not return values in it. */
3289 target_flags &= ~MASK_FLOAT_RETURNS;
3291 /* Use external vectorized library in vectorizing intrinsics. */
3292 if (ix86_veclibabi_string)
3294 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3295 ix86_veclib_handler = ix86_veclibabi_svml;
3296 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3297 ix86_veclib_handler = ix86_veclibabi_acml;
3299 error ("unknown vectorization library ABI type (%s) for "
3300 "%sveclibabi=%s %s", ix86_veclibabi_string,
3301 prefix, suffix, sw);
3304 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3305 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3307 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3309 /* ??? Unwind info is not correct around the CFG unless either a frame
3310 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3311 unwind info generation to be aware of the CFG and propagating states
3313 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3314 || flag_exceptions || flag_non_call_exceptions)
3315 && flag_omit_frame_pointer
3316 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3318 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3319 warning (0, "unwind tables currently require either a frame pointer "
3320 "or %saccumulate-outgoing-args%s for correctness",
3322 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3325 /* If stack probes are required, the space used for large function
3326 arguments on the stack must also be probed, so enable
3327 -maccumulate-outgoing-args so this happens in the prologue. */
3328 if (TARGET_STACK_PROBE
3329 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3331 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3332 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3333 "for correctness", prefix, suffix);
3334 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3337 /* For sane SSE instruction set generation we need fcomi instruction.
3338 It is safe to enable all CMOVE instructions. */
3342 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3345 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3346 p = strchr (internal_label_prefix, 'X');
3347 internal_label_prefix_len = p - internal_label_prefix;
3351 /* When scheduling description is not available, disable scheduler pass
3352 so it won't slow down the compilation and make x87 code slower. */
3353 if (!TARGET_SCHEDULE)
3354 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3356 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3357 set_param_value ("simultaneous-prefetches",
3358 ix86_cost->simultaneous_prefetches);
3359 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3360 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3361 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3362 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3363 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3364 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3366 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3367 can be optimized to ap = __builtin_next_arg (0). */
3369 targetm.expand_builtin_va_start = NULL;
3373 ix86_gen_leave = gen_leave_rex64;
3374 ix86_gen_pop1 = gen_popdi1;
3375 ix86_gen_add3 = gen_adddi3;
3376 ix86_gen_sub3 = gen_subdi3;
3377 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3378 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3379 ix86_gen_monitor = gen_sse3_monitor64;
3380 ix86_gen_andsp = gen_anddi3;
3384 ix86_gen_leave = gen_leave;
3385 ix86_gen_pop1 = gen_popsi1;
3386 ix86_gen_add3 = gen_addsi3;
3387 ix86_gen_sub3 = gen_subsi3;
3388 ix86_gen_sub3_carry = gen_subsi3_carry;
3389 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3390 ix86_gen_monitor = gen_sse3_monitor;
3391 ix86_gen_andsp = gen_andsi3;
3395 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3397 target_flags |= MASK_CLD & ~target_flags_explicit;
3400 /* Save the initial options in case the user does function specific options */
3402 target_option_default_node = target_option_current_node
3403 = build_target_option_node ();
3406 /* Save the current options */
3409 ix86_function_specific_save (struct cl_target_option *ptr)
3411 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3412 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3413 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3414 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3415 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3417 ptr->arch = ix86_arch;
3418 ptr->schedule = ix86_schedule;
3419 ptr->tune = ix86_tune;
3420 ptr->fpmath = ix86_fpmath;
3421 ptr->branch_cost = ix86_branch_cost;
3422 ptr->tune_defaulted = ix86_tune_defaulted;
3423 ptr->arch_specified = ix86_arch_specified;
3424 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3425 ptr->target_flags_explicit = target_flags_explicit;
3428 /* Restore the current options */
3431 ix86_function_specific_restore (struct cl_target_option *ptr)
3433 enum processor_type old_tune = ix86_tune;
3434 enum processor_type old_arch = ix86_arch;
3435 unsigned int ix86_arch_mask, ix86_tune_mask;
3438 ix86_arch = (enum processor_type) ptr->arch;
3439 ix86_schedule = (enum attr_cpu) ptr->schedule;
3440 ix86_tune = (enum processor_type) ptr->tune;
3441 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3442 ix86_branch_cost = ptr->branch_cost;
3443 ix86_tune_defaulted = ptr->tune_defaulted;
3444 ix86_arch_specified = ptr->arch_specified;
3445 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3446 target_flags_explicit = ptr->target_flags_explicit;
3448 /* Recreate the arch feature tests if the arch changed */
3449 if (old_arch != ix86_arch)
3451 ix86_arch_mask = 1u << ix86_arch;
3452 for (i = 0; i < X86_ARCH_LAST; ++i)
3453 ix86_arch_features[i]
3454 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3457 /* Recreate the tune optimization tests */
3458 if (old_tune != ix86_tune)
3460 ix86_tune_mask = 1u << ix86_tune;
3461 for (i = 0; i < X86_TUNE_LAST; ++i)
3462 ix86_tune_features[i]
3463 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3467 /* Print the current options */
3470 ix86_function_specific_print (FILE *file, int indent,
3471 struct cl_target_option *ptr)
3474 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3475 NULL, NULL, NULL, false);
3477 fprintf (file, "%*sarch = %d (%s)\n",
3480 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3481 ? cpu_names[ptr->arch]
3484 fprintf (file, "%*stune = %d (%s)\n",
3487 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3488 ? cpu_names[ptr->tune]
3491 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3492 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3493 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3494 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3498 fprintf (file, "%*s%s\n", indent, "", target_string);
3499 free (target_string);
3504 /* Inner function to process the attribute((target(...))), take an argument and
3505 set the current options from the argument. If we have a list, recursively go
3509 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3514 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3515 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3516 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3517 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3532 enum ix86_opt_type type;
3537 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3538 IX86_ATTR_ISA ("abm", OPT_mabm),
3539 IX86_ATTR_ISA ("aes", OPT_maes),
3540 IX86_ATTR_ISA ("avx", OPT_mavx),
3541 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3542 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3543 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3544 IX86_ATTR_ISA ("sse", OPT_msse),
3545 IX86_ATTR_ISA ("sse2", OPT_msse2),
3546 IX86_ATTR_ISA ("sse3", OPT_msse3),
3547 IX86_ATTR_ISA ("sse4", OPT_msse4),
3548 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3549 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3550 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3551 IX86_ATTR_ISA ("sse5", OPT_msse5),
3552 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3554 /* string options */
3555 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3556 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3557 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3560 IX86_ATTR_YES ("cld",
3564 IX86_ATTR_NO ("fancy-math-387",
3565 OPT_mfancy_math_387,
3566 MASK_NO_FANCY_MATH_387),
3568 IX86_ATTR_NO ("fused-madd",
3570 MASK_NO_FUSED_MADD),
3572 IX86_ATTR_YES ("ieee-fp",
3576 IX86_ATTR_YES ("inline-all-stringops",
3577 OPT_minline_all_stringops,
3578 MASK_INLINE_ALL_STRINGOPS),
3580 IX86_ATTR_YES ("inline-stringops-dynamically",
3581 OPT_minline_stringops_dynamically,
3582 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3584 IX86_ATTR_NO ("align-stringops",
3585 OPT_mno_align_stringops,
3586 MASK_NO_ALIGN_STRINGOPS),
3588 IX86_ATTR_YES ("recip",
3594 /* If this is a list, recurse to get the options. */
3595 if (TREE_CODE (args) == TREE_LIST)
3599 for (; args; args = TREE_CHAIN (args))
3600 if (TREE_VALUE (args)
3601 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3607 else if (TREE_CODE (args) != STRING_CST)
3610 /* Handle multiple arguments separated by commas. */
3611 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3613 while (next_optstr && *next_optstr != '\0')
3615 char *p = next_optstr;
3617 char *comma = strchr (next_optstr, ',');
3618 const char *opt_string;
3619 size_t len, opt_len;
3624 enum ix86_opt_type type = ix86_opt_unknown;
3630 len = comma - next_optstr;
3631 next_optstr = comma + 1;
3639 /* Recognize no-xxx. */
3640 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3649 /* Find the option. */
3652 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3654 type = attrs[i].type;
3655 opt_len = attrs[i].len;
3656 if (ch == attrs[i].string[0]
3657 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3658 && memcmp (p, attrs[i].string, opt_len) == 0)
3661 mask = attrs[i].mask;
3662 opt_string = attrs[i].string;
3667 /* Process the option. */
3670 error ("attribute(target(\"%s\")) is unknown", orig_p);
3674 else if (type == ix86_opt_isa)
3675 ix86_handle_option (opt, p, opt_set_p);
3677 else if (type == ix86_opt_yes || type == ix86_opt_no)
3679 if (type == ix86_opt_no)
3680 opt_set_p = !opt_set_p;
3683 target_flags |= mask;
3685 target_flags &= ~mask;
3688 else if (type == ix86_opt_str)
3692 error ("option(\"%s\") was already specified", opt_string);
3696 p_strings[opt] = xstrdup (p + opt_len);
3706 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3709 ix86_valid_target_attribute_tree (tree args)
3711 const char *orig_arch_string = ix86_arch_string;
3712 const char *orig_tune_string = ix86_tune_string;
3713 const char *orig_fpmath_string = ix86_fpmath_string;
3714 int orig_tune_defaulted = ix86_tune_defaulted;
3715 int orig_arch_specified = ix86_arch_specified;
3716 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3719 struct cl_target_option *def
3720 = TREE_TARGET_OPTION (target_option_default_node);
3722 /* Process each of the options on the chain. */
3723 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3726 /* If the changed options are different from the default, rerun override_options,
3727 and then save the options away. The string options are are attribute options,
3728 and will be undone when we copy the save structure. */
3729 if (ix86_isa_flags != def->ix86_isa_flags
3730 || target_flags != def->target_flags
3731 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3732 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3733 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3735 /* If we are using the default tune= or arch=, undo the string assigned,
3736 and use the default. */
3737 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3738 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3739 else if (!orig_arch_specified)
3740 ix86_arch_string = NULL;
3742 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3743 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3744 else if (orig_tune_defaulted)
3745 ix86_tune_string = NULL;
3747 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3748 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3749 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3750 else if (!TARGET_64BIT && TARGET_SSE)
3751 ix86_fpmath_string = "sse,387";
3753 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3754 override_options (false);
3756 /* Add any builtin functions with the new isa if any. */
3757 ix86_add_new_builtins (ix86_isa_flags);
3759 /* Save the current options unless we are validating options for
3761 t = build_target_option_node ();
3763 ix86_arch_string = orig_arch_string;
3764 ix86_tune_string = orig_tune_string;
3765 ix86_fpmath_string = orig_fpmath_string;
3767 /* Free up memory allocated to hold the strings */
3768 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3769 if (option_strings[i])
3770 free (option_strings[i]);
3776 /* Hook to validate attribute((target("string"))). */
3779 ix86_valid_target_attribute_p (tree fndecl,
3780 tree ARG_UNUSED (name),
3782 int ARG_UNUSED (flags))
3784 struct cl_target_option cur_target;
3786 tree old_optimize = build_optimization_node ();
3787 tree new_target, new_optimize;
3788 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3790 /* If the function changed the optimization levels as well as setting target
3791 options, start with the optimizations specified. */
3792 if (func_optimize && func_optimize != old_optimize)
3793 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3795 /* The target attributes may also change some optimization flags, so update
3796 the optimization options if necessary. */
3797 cl_target_option_save (&cur_target);
3798 new_target = ix86_valid_target_attribute_tree (args);
3799 new_optimize = build_optimization_node ();
3806 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3808 if (old_optimize != new_optimize)
3809 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3812 cl_target_option_restore (&cur_target);
3814 if (old_optimize != new_optimize)
3815 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3821 /* Hook to determine if one function can safely inline another. */
3824 ix86_can_inline_p (tree caller, tree callee)
3827 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3828 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3830 /* If callee has no option attributes, then it is ok to inline. */
3834 /* If caller has no option attributes, but callee does then it is not ok to
3836 else if (!caller_tree)
3841 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3842 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3844 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3845 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3847 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3848 != callee_opts->ix86_isa_flags)
3851 /* See if we have the same non-isa options. */
3852 else if (caller_opts->target_flags != callee_opts->target_flags)
3855 /* See if arch, tune, etc. are the same. */
3856 else if (caller_opts->arch != callee_opts->arch)
3859 else if (caller_opts->tune != callee_opts->tune)
3862 else if (caller_opts->fpmath != callee_opts->fpmath)
3865 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3876 /* Remember the last target of ix86_set_current_function. */
3877 static GTY(()) tree ix86_previous_fndecl;
3879 /* Establish appropriate back-end context for processing the function
3880 FNDECL. The argument might be NULL to indicate processing at top
3881 level, outside of any function scope. */
3883 ix86_set_current_function (tree fndecl)
3885 /* Only change the context if the function changes. This hook is called
3886 several times in the course of compiling a function, and we don't want to
3887 slow things down too much or call target_reinit when it isn't safe. */
3888 if (fndecl && fndecl != ix86_previous_fndecl)
3890 tree old_tree = (ix86_previous_fndecl
3891 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3894 tree new_tree = (fndecl
3895 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3898 ix86_previous_fndecl = fndecl;
3899 if (old_tree == new_tree)
3904 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3910 struct cl_target_option *def
3911 = TREE_TARGET_OPTION (target_option_current_node);
3913 cl_target_option_restore (def);
3920 /* Return true if this goes in large data/bss. */
3923 ix86_in_large_data_p (tree exp)
3925 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3928 /* Functions are never large data. */
3929 if (TREE_CODE (exp) == FUNCTION_DECL)
3932 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3934 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3935 if (strcmp (section, ".ldata") == 0
3936 || strcmp (section, ".lbss") == 0)
3942 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3944 /* If this is an incomplete type with size 0, then we can't put it
3945 in data because it might be too big when completed. */
3946 if (!size || size > ix86_section_threshold)
3953 /* Switch to the appropriate section for output of DECL.
3954 DECL is either a `VAR_DECL' node or a constant of some sort.
3955 RELOC indicates whether forming the initial value of DECL requires
3956 link-time relocations. */
3958 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3962 x86_64_elf_select_section (tree decl, int reloc,
3963 unsigned HOST_WIDE_INT align)
3965 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3966 && ix86_in_large_data_p (decl))
3968 const char *sname = NULL;
3969 unsigned int flags = SECTION_WRITE;
3970 switch (categorize_decl_for_section (decl, reloc))
3975 case SECCAT_DATA_REL:
3976 sname = ".ldata.rel";
3978 case SECCAT_DATA_REL_LOCAL:
3979 sname = ".ldata.rel.local";
3981 case SECCAT_DATA_REL_RO:
3982 sname = ".ldata.rel.ro";
3984 case SECCAT_DATA_REL_RO_LOCAL:
3985 sname = ".ldata.rel.ro.local";
3989 flags |= SECTION_BSS;
3992 case SECCAT_RODATA_MERGE_STR:
3993 case SECCAT_RODATA_MERGE_STR_INIT:
3994 case SECCAT_RODATA_MERGE_CONST:
3998 case SECCAT_SRODATA:
4005 /* We don't split these for medium model. Place them into
4006 default sections and hope for best. */
4008 case SECCAT_EMUTLS_VAR:
4009 case SECCAT_EMUTLS_TMPL:
4014 /* We might get called with string constants, but get_named_section
4015 doesn't like them as they are not DECLs. Also, we need to set
4016 flags in that case. */
4018 return get_section (sname, flags, NULL);
4019 return get_named_section (decl, sname, reloc);
4022 return default_elf_select_section (decl, reloc, align);
4025 /* Build up a unique section name, expressed as a
4026 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4027 RELOC indicates whether the initial value of EXP requires
4028 link-time relocations. */
4030 static void ATTRIBUTE_UNUSED
4031 x86_64_elf_unique_section (tree decl, int reloc)
4033 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4034 && ix86_in_large_data_p (decl))
4036 const char *prefix = NULL;
4037 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4038 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4040 switch (categorize_decl_for_section (decl, reloc))
4043 case SECCAT_DATA_REL:
4044 case SECCAT_DATA_REL_LOCAL:
4045 case SECCAT_DATA_REL_RO:
4046 case SECCAT_DATA_REL_RO_LOCAL:
4047 prefix = one_only ? ".ld" : ".ldata";
4050 prefix = one_only ? ".lb" : ".lbss";
4053 case SECCAT_RODATA_MERGE_STR:
4054 case SECCAT_RODATA_MERGE_STR_INIT:
4055 case SECCAT_RODATA_MERGE_CONST:
4056 prefix = one_only ? ".lr" : ".lrodata";
4058 case SECCAT_SRODATA:
4065 /* We don't split these for medium model. Place them into
4066 default sections and hope for best. */
4068 case SECCAT_EMUTLS_VAR:
4069 prefix = targetm.emutls.var_section;
4071 case SECCAT_EMUTLS_TMPL:
4072 prefix = targetm.emutls.tmpl_section;
4077 const char *name, *linkonce;
4080 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4081 name = targetm.strip_name_encoding (name);
4083 /* If we're using one_only, then there needs to be a .gnu.linkonce
4084 prefix to the section name. */
4085 linkonce = one_only ? ".gnu.linkonce" : "";
4087 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4089 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4093 default_unique_section (decl, reloc);
4096 #ifdef COMMON_ASM_OP
4097 /* This says how to output assembler code to declare an
4098 uninitialized external linkage data object.
4100 For medium model x86-64 we need to use .largecomm opcode for
4103 x86_elf_aligned_common (FILE *file,
4104 const char *name, unsigned HOST_WIDE_INT size,
4107 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4108 && size > (unsigned int)ix86_section_threshold)
4109 fprintf (file, ".largecomm\t");
4111 fprintf (file, "%s", COMMON_ASM_OP);
4112 assemble_name (file, name);
4113 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4114 size, align / BITS_PER_UNIT);
4118 /* Utility function for targets to use in implementing
4119 ASM_OUTPUT_ALIGNED_BSS. */
4122 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4123 const char *name, unsigned HOST_WIDE_INT size,
4126 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4127 && size > (unsigned int)ix86_section_threshold)
4128 switch_to_section (get_named_section (decl, ".lbss", 0));
4130 switch_to_section (bss_section);
4131 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4132 #ifdef ASM_DECLARE_OBJECT_NAME
4133 last_assemble_variable_decl = decl;
4134 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4136 /* Standard thing is just output label for the object. */
4137 ASM_OUTPUT_LABEL (file, name);
4138 #endif /* ASM_DECLARE_OBJECT_NAME */
4139 ASM_OUTPUT_SKIP (file, size ? size : 1);
4143 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4145 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4146 make the problem with not enough registers even worse. */
4147 #ifdef INSN_SCHEDULING
4149 flag_schedule_insns = 0;
4153 /* The Darwin libraries never set errno, so we might as well
4154 avoid calling them when that's the only reason we would. */
4155 flag_errno_math = 0;
4157 /* The default values of these switches depend on the TARGET_64BIT
4158 that is not known at this moment. Mark these values with 2 and
4159 let user the to override these. In case there is no command line option
4160 specifying them, we will set the defaults in override_options. */
4162 flag_omit_frame_pointer = 2;
4163 flag_pcc_struct_return = 2;
4164 flag_asynchronous_unwind_tables = 2;
4165 flag_vect_cost_model = 1;
4166 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4167 SUBTARGET_OPTIMIZATION_OPTIONS;
4171 /* Decide whether we can make a sibling call to a function. DECL is the
4172 declaration of the function being targeted by the call and EXP is the
4173 CALL_EXPR representing the call. */
4176 ix86_function_ok_for_sibcall (tree decl, tree exp)
4181 /* If we are generating position-independent code, we cannot sibcall
4182 optimize any indirect call, or a direct call to a global function,
4183 as the PLT requires %ebx be live. */
4184 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4191 func = TREE_TYPE (CALL_EXPR_FN (exp));
4192 if (POINTER_TYPE_P (func))
4193 func = TREE_TYPE (func);
4196 /* Check that the return value locations are the same. Like
4197 if we are returning floats on the 80387 register stack, we cannot
4198 make a sibcall from a function that doesn't return a float to a
4199 function that does or, conversely, from a function that does return
4200 a float to a function that doesn't; the necessary stack adjustment
4201 would not be executed. This is also the place we notice
4202 differences in the return value ABI. Note that it is ok for one
4203 of the functions to have void return type as long as the return
4204 value of the other is passed in a register. */
4205 a = ix86_function_value (TREE_TYPE (exp), func, false);
4206 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4208 if (STACK_REG_P (a) || STACK_REG_P (b))
4210 if (!rtx_equal_p (a, b))
4213 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4215 else if (!rtx_equal_p (a, b))
4218 /* If this call is indirect, we'll need to be able to use a call-clobbered
4219 register for the address of the target function. Make sure that all
4220 such registers are not used for passing parameters. */
4221 if (!decl && !TARGET_64BIT)
4225 /* We're looking at the CALL_EXPR, we need the type of the function. */
4226 type = CALL_EXPR_FN (exp); /* pointer expression */
4227 type = TREE_TYPE (type); /* pointer type */
4228 type = TREE_TYPE (type); /* function type */
4230 if (ix86_function_regparm (type, NULL) >= 3)
4232 /* ??? Need to count the actual number of registers to be used,
4233 not the possible number of registers. Fix later. */
4238 /* Dllimport'd functions are also called indirectly. */
4239 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4241 && decl && DECL_DLLIMPORT_P (decl)
4242 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4245 /* If we need to align the outgoing stack, then sibcalling would
4246 unalign the stack, which may break the called function. */
4247 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4250 /* Otherwise okay. That also includes certain types of indirect calls. */
4254 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4255 calling convention attributes;
4256 arguments as in struct attribute_spec.handler. */
4259 ix86_handle_cconv_attribute (tree *node, tree name,
4261 int flags ATTRIBUTE_UNUSED,
4264 if (TREE_CODE (*node) != FUNCTION_TYPE
4265 && TREE_CODE (*node) != METHOD_TYPE
4266 && TREE_CODE (*node) != FIELD_DECL
4267 && TREE_CODE (*node) != TYPE_DECL)
4269 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4271 *no_add_attrs = true;
4275 /* Can combine regparm with all attributes but fastcall. */
4276 if (is_attribute_p ("regparm", name))
4280 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4282 error ("fastcall and regparm attributes are not compatible");
4285 cst = TREE_VALUE (args);
4286 if (TREE_CODE (cst) != INTEGER_CST)
4288 warning (OPT_Wattributes,
4289 "%qE attribute requires an integer constant argument",
4291 *no_add_attrs = true;
4293 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4295 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4297 *no_add_attrs = true;
4305 /* Do not warn when emulating the MS ABI. */
4306 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4307 warning (OPT_Wattributes, "%qE attribute ignored",
4309 *no_add_attrs = true;
4313 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4314 if (is_attribute_p ("fastcall", name))
4316 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4318 error ("fastcall and cdecl attributes are not compatible");
4320 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4322 error ("fastcall and stdcall attributes are not compatible");
4324 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4326 error ("fastcall and regparm attributes are not compatible");
4330 /* Can combine stdcall with fastcall (redundant), regparm and
4332 else if (is_attribute_p ("stdcall", name))
4334 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4336 error ("stdcall and cdecl attributes are not compatible");
4338 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4340 error ("stdcall and fastcall attributes are not compatible");
4344 /* Can combine cdecl with regparm and sseregparm. */
4345 else if (is_attribute_p ("cdecl", name))
4347 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4349 error ("stdcall and cdecl attributes are not compatible");
4351 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4353 error ("fastcall and cdecl attributes are not compatible");
4357 /* Can combine sseregparm with all attributes. */
4362 /* Return 0 if the attributes for two types are incompatible, 1 if they
4363 are compatible, and 2 if they are nearly compatible (which causes a
4364 warning to be generated). */
4367 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4369 /* Check for mismatch of non-default calling convention. */
4370 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4372 if (TREE_CODE (type1) != FUNCTION_TYPE
4373 && TREE_CODE (type1) != METHOD_TYPE)
4376 /* Check for mismatched fastcall/regparm types. */
4377 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4378 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4379 || (ix86_function_regparm (type1, NULL)
4380 != ix86_function_regparm (type2, NULL)))
4383 /* Check for mismatched sseregparm types. */
4384 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4385 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4388 /* Check for mismatched return types (cdecl vs stdcall). */
4389 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4390 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4396 /* Return the regparm value for a function with the indicated TYPE and DECL.
4397 DECL may be NULL when calling function indirectly
4398 or considering a libcall. */
4401 ix86_function_regparm (const_tree type, const_tree decl)
4406 static bool error_issued;
4409 return (ix86_function_type_abi (type) == SYSV_ABI
4410 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4412 regparm = ix86_regparm;
4413 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4417 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4419 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4421 /* We can't use regparm(3) for nested functions because
4422 these pass static chain pointer in %ecx register. */
4423 if (!error_issued && regparm == 3
4424 && decl_function_context (decl)
4425 && !DECL_NO_STATIC_CHAIN (decl))
4427 error ("nested functions are limited to 2 register parameters");
4428 error_issued = true;
4436 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4439 /* Use register calling convention for local functions when possible. */
4441 && TREE_CODE (decl) == FUNCTION_DECL
4445 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4446 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4449 int local_regparm, globals = 0, regno;
4452 /* Make sure no regparm register is taken by a
4453 fixed register variable. */
4454 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4455 if (fixed_regs[local_regparm])
4458 /* We can't use regparm(3) for nested functions as these use
4459 static chain pointer in third argument. */
4460 if (local_regparm == 3
4461 && decl_function_context (decl)
4462 && !DECL_NO_STATIC_CHAIN (decl))
4465 /* If the function realigns its stackpointer, the prologue will
4466 clobber %ecx. If we've already generated code for the callee,
4467 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4468 scanning the attributes for the self-realigning property. */
4469 f = DECL_STRUCT_FUNCTION (decl);
4470 /* Since current internal arg pointer won't conflict with
4471 parameter passing regs, so no need to change stack
4472 realignment and adjust regparm number.
4474 Each fixed register usage increases register pressure,
4475 so less registers should be used for argument passing.
4476 This functionality can be overriden by an explicit
4478 for (regno = 0; regno <= DI_REG; regno++)
4479 if (fixed_regs[regno])
4483 = globals < local_regparm ? local_regparm - globals : 0;
4485 if (local_regparm > regparm)
4486 regparm = local_regparm;
4493 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4494 DFmode (2) arguments in SSE registers for a function with the
4495 indicated TYPE and DECL. DECL may be NULL when calling function
4496 indirectly or considering a libcall. Otherwise return 0. */
4499 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4501 gcc_assert (!TARGET_64BIT);
4503 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4504 by the sseregparm attribute. */
4505 if (TARGET_SSEREGPARM
4506 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4513 error ("Calling %qD with attribute sseregparm without "
4514 "SSE/SSE2 enabled", decl);
4516 error ("Calling %qT with attribute sseregparm without "
4517 "SSE/SSE2 enabled", type);
4525 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4526 (and DFmode for SSE2) arguments in SSE registers. */
4527 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4529 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4530 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4532 return TARGET_SSE2 ? 2 : 1;
4538 /* Return true if EAX is live at the start of the function. Used by
4539 ix86_expand_prologue to determine if we need special help before
4540 calling allocate_stack_worker. */
4543 ix86_eax_live_at_start_p (void)
4545 /* Cheat. Don't bother working forward from ix86_function_regparm
4546 to the function type to whether an actual argument is located in
4547 eax. Instead just look at cfg info, which is still close enough
4548 to correct at this point. This gives false positives for broken
4549 functions that might use uninitialized data that happens to be
4550 allocated in eax, but who cares? */
4551 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4554 /* Value is the number of bytes of arguments automatically
4555 popped when returning from a subroutine call.
4556 FUNDECL is the declaration node of the function (as a tree),
4557 FUNTYPE is the data type of the function (as a tree),
4558 or for a library call it is an identifier node for the subroutine name.
4559 SIZE is the number of bytes of arguments passed on the stack.
4561 On the 80386, the RTD insn may be used to pop them if the number
4562 of args is fixed, but if the number is variable then the caller
4563 must pop them all. RTD can't be used for library calls now
4564 because the library is compiled with the Unix compiler.
4565 Use of RTD is a selectable option, since it is incompatible with
4566 standard Unix calling sequences. If the option is not selected,
4567 the caller must always pop the args.
4569 The attribute stdcall is equivalent to RTD on a per module basis. */
4572 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4576 /* None of the 64-bit ABIs pop arguments. */
4580 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4582 /* Cdecl functions override -mrtd, and never pop the stack. */
4583 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4585 /* Stdcall and fastcall functions will pop the stack if not
4587 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4588 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4591 if (rtd && ! stdarg_p (funtype))
4595 /* Lose any fake structure return argument if it is passed on the stack. */
4596 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4597 && !KEEP_AGGREGATE_RETURN_POINTER)
4599 int nregs = ix86_function_regparm (funtype, fundecl);
4601 return GET_MODE_SIZE (Pmode);
4607 /* Argument support functions. */
4609 /* Return true when register may be used to pass function parameters. */
4611 ix86_function_arg_regno_p (int regno)
4614 const int *parm_regs;
4619 return (regno < REGPARM_MAX
4620 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4622 return (regno < REGPARM_MAX
4623 || (TARGET_MMX && MMX_REGNO_P (regno)
4624 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4625 || (TARGET_SSE && SSE_REGNO_P (regno)
4626 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4631 if (SSE_REGNO_P (regno) && TARGET_SSE)
4636 if (TARGET_SSE && SSE_REGNO_P (regno)
4637 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4641 /* TODO: The function should depend on current function ABI but
4642 builtins.c would need updating then. Therefore we use the
4645 /* RAX is used as hidden argument to va_arg functions. */
4646 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4649 if (ix86_abi == MS_ABI)
4650 parm_regs = x86_64_ms_abi_int_parameter_registers;
4652 parm_regs = x86_64_int_parameter_registers;
4653 for (i = 0; i < (ix86_abi == MS_ABI ? X64_REGPARM_MAX
4654 : X86_64_REGPARM_MAX); i++)
4655 if (regno == parm_regs[i])
4660 /* Return if we do not know how to pass TYPE solely in registers. */
4663 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4665 if (must_pass_in_stack_var_size_or_pad (mode, type))
4668 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4669 The layout_type routine is crafty and tries to trick us into passing
4670 currently unsupported vector types on the stack by using TImode. */
4671 return (!TARGET_64BIT && mode == TImode
4672 && type && TREE_CODE (type) != VECTOR_TYPE);
4675 /* It returns the size, in bytes, of the area reserved for arguments passed
4676 in registers for the function represented by fndecl dependent to the used
4679 ix86_reg_parm_stack_space (const_tree fndecl)
4681 enum calling_abi call_abi = SYSV_ABI;
4682 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4683 call_abi = ix86_function_abi (fndecl);
4685 call_abi = ix86_function_type_abi (fndecl);
4686 if (call_abi == MS_ABI)
4691 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4694 ix86_function_type_abi (const_tree fntype)
4696 if (TARGET_64BIT && fntype != NULL)
4698 enum calling_abi abi = ix86_abi;
4699 if (abi == SYSV_ABI)
4701 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4704 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4711 static enum calling_abi
4712 ix86_function_abi (const_tree fndecl)
4716 return ix86_function_type_abi (TREE_TYPE (fndecl));
4719 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4722 ix86_cfun_abi (void)
4724 if (! cfun || ! TARGET_64BIT)
4726 return cfun->machine->call_abi;
4730 extern void init_regs (void);
4732 /* Implementation of call abi switching target hook. Specific to FNDECL
4733 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4734 for more details. */
4736 ix86_call_abi_override (const_tree fndecl)
4738 if (fndecl == NULL_TREE)
4739 cfun->machine->call_abi = ix86_abi;
4741 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4744 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4745 re-initialization of init_regs each time we switch function context since
4746 this is needed only during RTL expansion. */
4748 ix86_maybe_switch_abi (void)
4751 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4755 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4756 for a call to a function whose data type is FNTYPE.
4757 For a library call, FNTYPE is 0. */
4760 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4761 tree fntype, /* tree ptr for function decl */
4762 rtx libname, /* SYMBOL_REF of library name or 0 */
4765 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4766 memset (cum, 0, sizeof (*cum));
4769 cum->call_abi = ix86_function_abi (fndecl);
4771 cum->call_abi = ix86_function_type_abi (fntype);
4772 /* Set up the number of registers to use for passing arguments. */
4774 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4775 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4776 cum->nregs = ix86_regparm;
4779 if (cum->call_abi != ix86_abi)
4780 cum->nregs = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX
4785 cum->sse_nregs = SSE_REGPARM_MAX;
4788 if (cum->call_abi != ix86_abi)
4789 cum->sse_nregs = ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4790 : X64_SSE_REGPARM_MAX;
4794 cum->mmx_nregs = MMX_REGPARM_MAX;
4795 cum->warn_avx = true;
4796 cum->warn_sse = true;
4797 cum->warn_mmx = true;
4799 /* Because type might mismatch in between caller and callee, we need to
4800 use actual type of function for local calls.
4801 FIXME: cgraph_analyze can be told to actually record if function uses
4802 va_start so for local functions maybe_vaarg can be made aggressive
4804 FIXME: once typesytem is fixed, we won't need this code anymore. */
4806 fntype = TREE_TYPE (fndecl);
4807 cum->maybe_vaarg = (fntype
4808 ? (!prototype_p (fntype) || stdarg_p (fntype))
4813 /* If there are variable arguments, then we won't pass anything
4814 in registers in 32-bit mode. */
4815 if (stdarg_p (fntype))
4826 /* Use ecx and edx registers if function has fastcall attribute,
4827 else look for regparm information. */
4830 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4836 cum->nregs = ix86_function_regparm (fntype, fndecl);
4839 /* Set up the number of SSE registers used for passing SFmode
4840 and DFmode arguments. Warn for mismatching ABI. */
4841 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4845 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4846 But in the case of vector types, it is some vector mode.
4848 When we have only some of our vector isa extensions enabled, then there
4849 are some modes for which vector_mode_supported_p is false. For these
4850 modes, the generic vector support in gcc will choose some non-vector mode
4851 in order to implement the type. By computing the natural mode, we'll
4852 select the proper ABI location for the operand and not depend on whatever
4853 the middle-end decides to do with these vector types.
4855 The midde-end can't deal with the vector types > 16 bytes. In this
4856 case, we return the original mode and warn ABI change if CUM isn't
4859 static enum machine_mode
4860 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4862 enum machine_mode mode = TYPE_MODE (type);
4864 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4866 HOST_WIDE_INT size = int_size_in_bytes (type);
4867 if ((size == 8 || size == 16 || size == 32)
4868 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4869 && TYPE_VECTOR_SUBPARTS (type) > 1)
4871 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4873 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4874 mode = MIN_MODE_VECTOR_FLOAT;
4876 mode = MIN_MODE_VECTOR_INT;
4878 /* Get the mode which has this inner mode and number of units. */
4879 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4880 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4881 && GET_MODE_INNER (mode) == innermode)
4883 if (size == 32 && !TARGET_AVX)
4885 static bool warnedavx;
4892 warning (0, "AVX vector argument without AVX "
4893 "enabled changes the ABI");
4895 return TYPE_MODE (type);
4908 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4909 this may not agree with the mode that the type system has chosen for the
4910 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4911 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4914 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4919 if (orig_mode != BLKmode)
4920 tmp = gen_rtx_REG (orig_mode, regno);
4923 tmp = gen_rtx_REG (mode, regno);
4924 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4925 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4931 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4932 of this code is to classify each 8bytes of incoming argument by the register
4933 class and assign registers accordingly. */
4935 /* Return the union class of CLASS1 and CLASS2.
4936 See the x86-64 PS ABI for details. */
4938 static enum x86_64_reg_class
4939 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4941 /* Rule #1: If both classes are equal, this is the resulting class. */
4942 if (class1 == class2)
4945 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4947 if (class1 == X86_64_NO_CLASS)
4949 if (class2 == X86_64_NO_CLASS)
4952 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4953 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4954 return X86_64_MEMORY_CLASS;
4956 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4957 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4958 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4959 return X86_64_INTEGERSI_CLASS;
4960 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4961 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4962 return X86_64_INTEGER_CLASS;
4964 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4966 if (class1 == X86_64_X87_CLASS
4967 || class1 == X86_64_X87UP_CLASS
4968 || class1 == X86_64_COMPLEX_X87_CLASS
4969 || class2 == X86_64_X87_CLASS
4970 || class2 == X86_64_X87UP_CLASS
4971 || class2 == X86_64_COMPLEX_X87_CLASS)
4972 return X86_64_MEMORY_CLASS;
4974 /* Rule #6: Otherwise class SSE is used. */
4975 return X86_64_SSE_CLASS;
4978 /* Classify the argument of type TYPE and mode MODE.
4979 CLASSES will be filled by the register class used to pass each word
4980 of the operand. The number of words is returned. In case the parameter
4981 should be passed in memory, 0 is returned. As a special case for zero
4982 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4984 BIT_OFFSET is used internally for handling records and specifies offset
4985 of the offset in bits modulo 256 to avoid overflow cases.
4987 See the x86-64 PS ABI for details.
4991 classify_argument (enum machine_mode mode, const_tree type,
4992 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4994 HOST_WIDE_INT bytes =
4995 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4996 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4998 /* Variable sized entities are always passed/returned in memory. */
5002 if (mode != VOIDmode
5003 && targetm.calls.must_pass_in_stack (mode, type))
5006 if (type && AGGREGATE_TYPE_P (type))
5010 enum x86_64_reg_class subclasses[MAX_CLASSES];
5012 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5016 for (i = 0; i < words; i++)
5017 classes[i] = X86_64_NO_CLASS;
5019 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5020 signalize memory class, so handle it as special case. */
5023 classes[0] = X86_64_NO_CLASS;
5027 /* Classify each field of record and merge classes. */
5028 switch (TREE_CODE (type))
5031 /* And now merge the fields of structure. */
5032 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5034 if (TREE_CODE (field) == FIELD_DECL)
5038 if (TREE_TYPE (field) == error_mark_node)
5041 /* Bitfields are always classified as integer. Handle them
5042 early, since later code would consider them to be
5043 misaligned integers. */
5044 if (DECL_BIT_FIELD (field))
5046 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5047 i < ((int_bit_position (field) + (bit_offset % 64))
5048 + tree_low_cst (DECL_SIZE (field), 0)
5051 merge_classes (X86_64_INTEGER_CLASS,
5058 type = TREE_TYPE (field);
5060 /* Flexible array member is ignored. */
5061 if (TYPE_MODE (type) == BLKmode
5062 && TREE_CODE (type) == ARRAY_TYPE
5063 && TYPE_SIZE (type) == NULL_TREE
5064 && TYPE_DOMAIN (type) != NULL_TREE
5065 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5070 if (!warned && warn_psabi)
5073 inform (input_location,
5074 "The ABI of passing struct with"
5075 " a flexible array member has"
5076 " changed in GCC 4.4");
5080 num = classify_argument (TYPE_MODE (type), type,
5082 (int_bit_position (field)
5083 + bit_offset) % 256);
5086 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5087 for (i = 0; i < num && (i + pos) < words; i++)
5089 merge_classes (subclasses[i], classes[i + pos]);
5096 /* Arrays are handled as small records. */
5099 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5100 TREE_TYPE (type), subclasses, bit_offset);
5104 /* The partial classes are now full classes. */
5105 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5106 subclasses[0] = X86_64_SSE_CLASS;
5107 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5108 && !((bit_offset % 64) == 0 && bytes == 4))
5109 subclasses[0] = X86_64_INTEGER_CLASS;
5111 for (i = 0; i < words; i++)
5112 classes[i] = subclasses[i % num];
5117 case QUAL_UNION_TYPE:
5118 /* Unions are similar to RECORD_TYPE but offset is always 0.
5120 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5122 if (TREE_CODE (field) == FIELD_DECL)
5126 if (TREE_TYPE (field) == error_mark_node)
5129 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5130 TREE_TYPE (field), subclasses,
5134 for (i = 0; i < num; i++)
5135 classes[i] = merge_classes (subclasses[i], classes[i]);
5146 /* When size > 16 bytes, if the first one isn't
5147 X86_64_SSE_CLASS or any other ones aren't
5148 X86_64_SSEUP_CLASS, everything should be passed in
5150 if (classes[0] != X86_64_SSE_CLASS)
5153 for (i = 1; i < words; i++)
5154 if (classes[i] != X86_64_SSEUP_CLASS)
5158 /* Final merger cleanup. */
5159 for (i = 0; i < words; i++)
5161 /* If one class is MEMORY, everything should be passed in
5163 if (classes[i] == X86_64_MEMORY_CLASS)
5166 /* The X86_64_SSEUP_CLASS should be always preceded by
5167 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5168 if (classes[i] == X86_64_SSEUP_CLASS
5169 && classes[i - 1] != X86_64_SSE_CLASS
5170 && classes[i - 1] != X86_64_SSEUP_CLASS)
5172 /* The first one should never be X86_64_SSEUP_CLASS. */
5173 gcc_assert (i != 0);
5174 classes[i] = X86_64_SSE_CLASS;
5177 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5178 everything should be passed in memory. */
5179 if (classes[i] == X86_64_X87UP_CLASS
5180 && (classes[i - 1] != X86_64_X87_CLASS))
5184 /* The first one should never be X86_64_X87UP_CLASS. */
5185 gcc_assert (i != 0);
5186 if (!warned && warn_psabi)
5189 inform (input_location,
5190 "The ABI of passing union with long double"
5191 " has changed in GCC 4.4");
5199 /* Compute alignment needed. We align all types to natural boundaries with
5200 exception of XFmode that is aligned to 64bits. */
5201 if (mode != VOIDmode && mode != BLKmode)
5203 int mode_alignment = GET_MODE_BITSIZE (mode);
5206 mode_alignment = 128;
5207 else if (mode == XCmode)
5208 mode_alignment = 256;
5209 if (COMPLEX_MODE_P (mode))
5210 mode_alignment /= 2;
5211 /* Misaligned fields are always returned in memory. */
5212 if (bit_offset % mode_alignment)
5216 /* for V1xx modes, just use the base mode */
5217 if (VECTOR_MODE_P (mode) && mode != V1DImode
5218 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5219 mode = GET_MODE_INNER (mode);
5221 /* Classification of atomic types. */
5226 classes[0] = X86_64_SSE_CLASS;
5229 classes[0] = X86_64_SSE_CLASS;
5230 classes[1] = X86_64_SSEUP_CLASS;
5240 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5244 classes[0] = X86_64_INTEGERSI_CLASS;
5247 else if (size <= 64)
5249 classes[0] = X86_64_INTEGER_CLASS;
5252 else if (size <= 64+32)
5254 classes[0] = X86_64_INTEGER_CLASS;
5255 classes[1] = X86_64_INTEGERSI_CLASS;
5258 else if (size <= 64+64)
5260 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5268 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5272 /* OImode shouldn't be used directly. */
5277 if (!(bit_offset % 64))
5278 classes[0] = X86_64_SSESF_CLASS;
5280 classes[0] = X86_64_SSE_CLASS;
5283 classes[0] = X86_64_SSEDF_CLASS;
5286 classes[0] = X86_64_X87_CLASS;
5287 classes[1] = X86_64_X87UP_CLASS;
5290 classes[0] = X86_64_SSE_CLASS;
5291 classes[1] = X86_64_SSEUP_CLASS;
5294 classes[0] = X86_64_SSE_CLASS;
5295 if (!(bit_offset % 64))
5301 if (!warned && warn_psabi)
5304 inform (input_location,
5305 "The ABI of passing structure with complex float"
5306 " member has changed in GCC 4.4");
5308 classes[1] = X86_64_SSESF_CLASS;
5312 classes[0] = X86_64_SSEDF_CLASS;
5313 classes[1] = X86_64_SSEDF_CLASS;
5316 classes[0] = X86_64_COMPLEX_X87_CLASS;
5319 /* This modes is larger than 16 bytes. */
5327 classes[0] = X86_64_SSE_CLASS;
5328 classes[1] = X86_64_SSEUP_CLASS;
5329 classes[2] = X86_64_SSEUP_CLASS;
5330 classes[3] = X86_64_SSEUP_CLASS;
5338 classes[0] = X86_64_SSE_CLASS;
5339 classes[1] = X86_64_SSEUP_CLASS;
5346 classes[0] = X86_64_SSE_CLASS;
5352 gcc_assert (VECTOR_MODE_P (mode));
5357 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5359 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5360 classes[0] = X86_64_INTEGERSI_CLASS;
5362 classes[0] = X86_64_INTEGER_CLASS;
5363 classes[1] = X86_64_INTEGER_CLASS;
5364 return 1 + (bytes > 8);
5368 /* Examine the argument and return set number of register required in each
5369 class. Return 0 iff parameter should be passed in memory. */
5371 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5372 int *int_nregs, int *sse_nregs)
5374 enum x86_64_reg_class regclass[MAX_CLASSES];
5375 int n = classify_argument (mode, type, regclass, 0);
5381 for (n--; n >= 0; n--)
5382 switch (regclass[n])
5384 case X86_64_INTEGER_CLASS:
5385 case X86_64_INTEGERSI_CLASS:
5388 case X86_64_SSE_CLASS:
5389 case X86_64_SSESF_CLASS:
5390 case X86_64_SSEDF_CLASS:
5393 case X86_64_NO_CLASS:
5394 case X86_64_SSEUP_CLASS:
5396 case X86_64_X87_CLASS:
5397 case X86_64_X87UP_CLASS:
5401 case X86_64_COMPLEX_X87_CLASS:
5402 return in_return ? 2 : 0;
5403 case X86_64_MEMORY_CLASS:
5409 /* Construct container for the argument used by GCC interface. See
5410 FUNCTION_ARG for the detailed description. */
5413 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5414 const_tree type, int in_return, int nintregs, int nsseregs,
5415 const int *intreg, int sse_regno)
5417 /* The following variables hold the static issued_error state. */
5418 static bool issued_sse_arg_error;
5419 static bool issued_sse_ret_error;
5420 static bool issued_x87_ret_error;
5422 enum machine_mode tmpmode;
5424 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5425 enum x86_64_reg_class regclass[MAX_CLASSES];
5429 int needed_sseregs, needed_intregs;
5430 rtx exp[MAX_CLASSES];
5433 n = classify_argument (mode, type, regclass, 0);
5436 if (!examine_argument (mode, type, in_return, &needed_intregs,
5439 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5442 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5443 some less clueful developer tries to use floating-point anyway. */
5444 if (needed_sseregs && !TARGET_SSE)
5448 if (!issued_sse_ret_error)
5450 error ("SSE register return with SSE disabled");
5451 issued_sse_ret_error = true;
5454 else if (!issued_sse_arg_error)
5456 error ("SSE register argument with SSE disabled");
5457 issued_sse_arg_error = true;
5462 /* Likewise, error if the ABI requires us to return values in the
5463 x87 registers and the user specified -mno-80387. */
5464 if (!TARGET_80387 && in_return)
5465 for (i = 0; i < n; i++)
5466 if (regclass[i] == X86_64_X87_CLASS
5467 || regclass[i] == X86_64_X87UP_CLASS
5468 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5470 if (!issued_x87_ret_error)
5472 error ("x87 register return with x87 disabled");
5473 issued_x87_ret_error = true;
5478 /* First construct simple cases. Avoid SCmode, since we want to use
5479 single register to pass this type. */
5480 if (n == 1 && mode != SCmode)
5481 switch (regclass[0])
5483 case X86_64_INTEGER_CLASS:
5484 case X86_64_INTEGERSI_CLASS:
5485 return gen_rtx_REG (mode, intreg[0]);
5486 case X86_64_SSE_CLASS:
5487 case X86_64_SSESF_CLASS:
5488 case X86_64_SSEDF_CLASS:
5489 if (mode != BLKmode)
5490 return gen_reg_or_parallel (mode, orig_mode,
5491 SSE_REGNO (sse_regno));
5493 case X86_64_X87_CLASS:
5494 case X86_64_COMPLEX_X87_CLASS:
5495 return gen_rtx_REG (mode, FIRST_STACK_REG);
5496 case X86_64_NO_CLASS:
5497 /* Zero sized array, struct or class. */
5502 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5503 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5504 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5506 && regclass[0] == X86_64_SSE_CLASS
5507 && regclass[1] == X86_64_SSEUP_CLASS
5508 && regclass[2] == X86_64_SSEUP_CLASS
5509 && regclass[3] == X86_64_SSEUP_CLASS
5511 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5514 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5515 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5516 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5517 && regclass[1] == X86_64_INTEGER_CLASS
5518 && (mode == CDImode || mode == TImode || mode == TFmode)
5519 && intreg[0] + 1 == intreg[1])
5520 return gen_rtx_REG (mode, intreg[0]);
5522 /* Otherwise figure out the entries of the PARALLEL. */
5523 for (i = 0; i < n; i++)
5527 switch (regclass[i])
5529 case X86_64_NO_CLASS:
5531 case X86_64_INTEGER_CLASS:
5532 case X86_64_INTEGERSI_CLASS:
5533 /* Merge TImodes on aligned occasions here too. */
5534 if (i * 8 + 8 > bytes)
5535 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5536 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5540 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5541 if (tmpmode == BLKmode)
5543 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5544 gen_rtx_REG (tmpmode, *intreg),
5548 case X86_64_SSESF_CLASS:
5549 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5550 gen_rtx_REG (SFmode,
5551 SSE_REGNO (sse_regno)),
5555 case X86_64_SSEDF_CLASS:
5556 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5557 gen_rtx_REG (DFmode,
5558 SSE_REGNO (sse_regno)),
5562 case X86_64_SSE_CLASS:
5570 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5580 && regclass[1] == X86_64_SSEUP_CLASS
5581 && regclass[2] == X86_64_SSEUP_CLASS
5582 && regclass[3] == X86_64_SSEUP_CLASS);
5589 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5590 gen_rtx_REG (tmpmode,
5591 SSE_REGNO (sse_regno)),
5600 /* Empty aligned struct, union or class. */
5604 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5605 for (i = 0; i < nexps; i++)
5606 XVECEXP (ret, 0, i) = exp [i];
5610 /* Update the data in CUM to advance over an argument of mode MODE
5611 and data type TYPE. (TYPE is null for libcalls where that information
5612 may not be available.) */
5615 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5616 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5632 cum->words += words;
5633 cum->nregs -= words;
5634 cum->regno += words;
5636 if (cum->nregs <= 0)
5644 /* OImode shouldn't be used directly. */
5648 if (cum->float_in_sse < 2)
5651 if (cum->float_in_sse < 1)
5668 if (!type || !AGGREGATE_TYPE_P (type))
5670 cum->sse_words += words;
5671 cum->sse_nregs -= 1;
5672 cum->sse_regno += 1;
5673 if (cum->sse_nregs <= 0)
5686 if (!type || !AGGREGATE_TYPE_P (type))
5688 cum->mmx_words += words;
5689 cum->mmx_nregs -= 1;
5690 cum->mmx_regno += 1;
5691 if (cum->mmx_nregs <= 0)
5702 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5703 tree type, HOST_WIDE_INT words, int named)
5705 int int_nregs, sse_nregs;
5707 /* Unnamed 256bit vector mode parameters are passed on stack. */
5708 if (!named && VALID_AVX256_REG_MODE (mode))
5711 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5712 cum->words += words;
5713 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5715 cum->nregs -= int_nregs;
5716 cum->sse_nregs -= sse_nregs;
5717 cum->regno += int_nregs;
5718 cum->sse_regno += sse_nregs;
5721 cum->words += words;
5725 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5726 HOST_WIDE_INT words)
5728 /* Otherwise, this should be passed indirect. */
5729 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5731 cum->words += words;
5740 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5741 tree type, int named)
5743 HOST_WIDE_INT bytes, words;
5745 if (mode == BLKmode)
5746 bytes = int_size_in_bytes (type);
5748 bytes = GET_MODE_SIZE (mode);
5749 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5752 mode = type_natural_mode (type, NULL);
5754 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5755 function_arg_advance_ms_64 (cum, bytes, words);
5756 else if (TARGET_64BIT)
5757 function_arg_advance_64 (cum, mode, type, words, named);
5759 function_arg_advance_32 (cum, mode, type, bytes, words);
5762 /* Define where to put the arguments to a function.
5763 Value is zero to push the argument on the stack,
5764 or a hard register in which to store the argument.
5766 MODE is the argument's machine mode.
5767 TYPE is the data type of the argument (as a tree).
5768 This is null for libcalls where that information may
5770 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5771 the preceding args and about the function being called.
5772 NAMED is nonzero if this argument is a named parameter
5773 (otherwise it is an extra parameter matching an ellipsis). */
5776 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5777 enum machine_mode orig_mode, tree type,
5778 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5780 static bool warnedsse, warnedmmx;
5782 /* Avoid the AL settings for the Unix64 ABI. */
5783 if (mode == VOIDmode)
5799 if (words <= cum->nregs)
5801 int regno = cum->regno;
5803 /* Fastcall allocates the first two DWORD (SImode) or
5804 smaller arguments to ECX and EDX if it isn't an
5810 || (type && AGGREGATE_TYPE_P (type)))
5813 /* ECX not EAX is the first allocated register. */
5814 if (regno == AX_REG)
5817 return gen_rtx_REG (mode, regno);
5822 if (cum->float_in_sse < 2)
5825 if (cum->float_in_sse < 1)
5829 /* In 32bit, we pass TImode in xmm registers. */
5836 if (!type || !AGGREGATE_TYPE_P (type))
5838 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5841 warning (0, "SSE vector argument without SSE enabled "
5845 return gen_reg_or_parallel (mode, orig_mode,
5846 cum->sse_regno + FIRST_SSE_REG);
5851 /* OImode shouldn't be used directly. */
5860 if (!type || !AGGREGATE_TYPE_P (type))
5863 return gen_reg_or_parallel (mode, orig_mode,
5864 cum->sse_regno + FIRST_SSE_REG);
5873 if (!type || !AGGREGATE_TYPE_P (type))
5875 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5878 warning (0, "MMX vector argument without MMX enabled "
5882 return gen_reg_or_parallel (mode, orig_mode,
5883 cum->mmx_regno + FIRST_MMX_REG);
5892 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5893 enum machine_mode orig_mode, tree type, int named)
5895 /* Handle a hidden AL argument containing number of registers
5896 for varargs x86-64 functions. */
5897 if (mode == VOIDmode)
5898 return GEN_INT (cum->maybe_vaarg
5899 ? (cum->sse_nregs < 0
5900 ? (cum->call_abi == ix86_abi
5902 : (ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5903 : X64_SSE_REGPARM_MAX))
5918 /* Unnamed 256bit vector mode parameters are passed on stack. */
5924 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5926 &x86_64_int_parameter_registers [cum->regno],
5931 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5932 enum machine_mode orig_mode, int named,
5933 HOST_WIDE_INT bytes)
5937 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5938 We use value of -2 to specify that current function call is MSABI. */
5939 if (mode == VOIDmode)
5940 return GEN_INT (-2);
5942 /* If we've run out of registers, it goes on the stack. */
5943 if (cum->nregs == 0)
5946 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5948 /* Only floating point modes are passed in anything but integer regs. */
5949 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5952 regno = cum->regno + FIRST_SSE_REG;
5957 /* Unnamed floating parameters are passed in both the
5958 SSE and integer registers. */
5959 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5960 t2 = gen_rtx_REG (mode, regno);
5961 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5962 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5963 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5966 /* Handle aggregated types passed in register. */
5967 if (orig_mode == BLKmode)
5969 if (bytes > 0 && bytes <= 8)
5970 mode = (bytes > 4 ? DImode : SImode);
5971 if (mode == BLKmode)
5975 return gen_reg_or_parallel (mode, orig_mode, regno);
5979 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5980 tree type, int named)
5982 enum machine_mode mode = omode;
5983 HOST_WIDE_INT bytes, words;
5985 if (mode == BLKmode)
5986 bytes = int_size_in_bytes (type);
5988 bytes = GET_MODE_SIZE (mode);
5989 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5991 /* To simplify the code below, represent vector types with a vector mode
5992 even if MMX/SSE are not active. */
5993 if (type && TREE_CODE (type) == VECTOR_TYPE)
5994 mode = type_natural_mode (type, cum);
5996 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5997 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5998 else if (TARGET_64BIT)
5999 return function_arg_64 (cum, mode, omode, type, named);
6001 return function_arg_32 (cum, mode, omode, type, bytes, words);
6004 /* A C expression that indicates when an argument must be passed by
6005 reference. If nonzero for an argument, a copy of that argument is
6006 made in memory and a pointer to the argument is passed instead of
6007 the argument itself. The pointer is passed in whatever way is
6008 appropriate for passing a pointer to that type. */
6011 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6012 enum machine_mode mode ATTRIBUTE_UNUSED,
6013 const_tree type, bool named ATTRIBUTE_UNUSED)
6015 /* See Windows x64 Software Convention. */
6016 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6018 int msize = (int) GET_MODE_SIZE (mode);
6021 /* Arrays are passed by reference. */
6022 if (TREE_CODE (type) == ARRAY_TYPE)
6025 if (AGGREGATE_TYPE_P (type))
6027 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6028 are passed by reference. */
6029 msize = int_size_in_bytes (type);
6033 /* __m128 is passed by reference. */
6035 case 1: case 2: case 4: case 8:
6041 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6047 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6050 contains_aligned_value_p (tree type)
6052 enum machine_mode mode = TYPE_MODE (type);
6053 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6057 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6059 if (TYPE_ALIGN (type) < 128)
6062 if (AGGREGATE_TYPE_P (type))
6064 /* Walk the aggregates recursively. */
6065 switch (TREE_CODE (type))
6069 case QUAL_UNION_TYPE:
6073 /* Walk all the structure fields. */
6074 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6076 if (TREE_CODE (field) == FIELD_DECL
6077 && contains_aligned_value_p (TREE_TYPE (field)))
6084 /* Just for use if some languages passes arrays by value. */
6085 if (contains_aligned_value_p (TREE_TYPE (type)))
6096 /* Gives the alignment boundary, in bits, of an argument with the
6097 specified mode and type. */
6100 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6105 /* Since canonical type is used for call, we convert it to
6106 canonical type if needed. */
6107 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6108 type = TYPE_CANONICAL (type);
6109 align = TYPE_ALIGN (type);
6112 align = GET_MODE_ALIGNMENT (mode);
6113 if (align < PARM_BOUNDARY)
6114 align = PARM_BOUNDARY;
6115 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6116 natural boundaries. */
6117 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6119 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6120 make an exception for SSE modes since these require 128bit
6123 The handling here differs from field_alignment. ICC aligns MMX
6124 arguments to 4 byte boundaries, while structure fields are aligned
6125 to 8 byte boundaries. */
6128 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6129 align = PARM_BOUNDARY;
6133 if (!contains_aligned_value_p (type))
6134 align = PARM_BOUNDARY;
6137 if (align > BIGGEST_ALIGNMENT)
6138 align = BIGGEST_ALIGNMENT;
6142 /* Return true if N is a possible register number of function value. */
6145 ix86_function_value_regno_p (int regno)
6152 case FIRST_FLOAT_REG:
6153 /* TODO: The function should depend on current function ABI but
6154 builtins.c would need updating then. Therefore we use the
6156 if (TARGET_64BIT && ix86_abi == MS_ABI)
6158 return TARGET_FLOAT_RETURNS_IN_80387;
6164 if (TARGET_MACHO || TARGET_64BIT)
6172 /* Define how to find the value returned by a function.
6173 VALTYPE is the data type of the value (as a tree).
6174 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6175 otherwise, FUNC is 0. */
6178 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6179 const_tree fntype, const_tree fn)
6183 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6184 we normally prevent this case when mmx is not available. However
6185 some ABIs may require the result to be returned like DImode. */
6186 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6187 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6189 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6190 we prevent this case when sse is not available. However some ABIs
6191 may require the result to be returned like integer TImode. */
6192 else if (mode == TImode
6193 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6194 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6196 /* 32-byte vector modes in %ymm0. */
6197 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6198 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6200 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6201 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6202 regno = FIRST_FLOAT_REG;
6204 /* Most things go in %eax. */
6207 /* Override FP return register with %xmm0 for local functions when
6208 SSE math is enabled or for functions with sseregparm attribute. */
6209 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6211 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6212 if ((sse_level >= 1 && mode == SFmode)
6213 || (sse_level == 2 && mode == DFmode))
6214 regno = FIRST_SSE_REG;
6217 /* OImode shouldn't be used directly. */
6218 gcc_assert (mode != OImode);
6220 return gen_rtx_REG (orig_mode, regno);
6224 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6229 /* Handle libcalls, which don't provide a type node. */
6230 if (valtype == NULL)
6242 return gen_rtx_REG (mode, FIRST_SSE_REG);
6245 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6249 return gen_rtx_REG (mode, AX_REG);
6253 ret = construct_container (mode, orig_mode, valtype, 1,
6254 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6255 x86_64_int_return_registers, 0);
6257 /* For zero sized structures, construct_container returns NULL, but we
6258 need to keep rest of compiler happy by returning meaningful value. */
6260 ret = gen_rtx_REG (orig_mode, AX_REG);
6266 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6268 unsigned int regno = AX_REG;
6272 switch (GET_MODE_SIZE (mode))
6275 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6276 && !COMPLEX_MODE_P (mode))
6277 regno = FIRST_SSE_REG;
6281 if (mode == SFmode || mode == DFmode)
6282 regno = FIRST_SSE_REG;
6288 return gen_rtx_REG (orig_mode, regno);
6292 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6293 enum machine_mode orig_mode, enum machine_mode mode)
6295 const_tree fn, fntype;
6298 if (fntype_or_decl && DECL_P (fntype_or_decl))
6299 fn = fntype_or_decl;
6300 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6302 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6303 return function_value_ms_64 (orig_mode, mode);
6304 else if (TARGET_64BIT)
6305 return function_value_64 (orig_mode, mode, valtype);
6307 return function_value_32 (orig_mode, mode, fntype, fn);
6311 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6312 bool outgoing ATTRIBUTE_UNUSED)
6314 enum machine_mode mode, orig_mode;
6316 orig_mode = TYPE_MODE (valtype);
6317 mode = type_natural_mode (valtype, NULL);
6318 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6322 ix86_libcall_value (enum machine_mode mode)
6324 return ix86_function_value_1 (NULL, NULL, mode, mode);
6327 /* Return true iff type is returned in memory. */
6329 static int ATTRIBUTE_UNUSED
6330 return_in_memory_32 (const_tree type, enum machine_mode mode)
6334 if (mode == BLKmode)
6337 size = int_size_in_bytes (type);
6339 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6342 if (VECTOR_MODE_P (mode) || mode == TImode)
6344 /* User-created vectors small enough to fit in EAX. */
6348 /* MMX/3dNow values are returned in MM0,
6349 except when it doesn't exits. */
6351 return (TARGET_MMX ? 0 : 1);
6353 /* SSE values are returned in XMM0, except when it doesn't exist. */
6355 return (TARGET_SSE ? 0 : 1);
6357 /* AVX values are returned in YMM0, except when it doesn't exist. */
6359 return TARGET_AVX ? 0 : 1;
6368 /* OImode shouldn't be used directly. */
6369 gcc_assert (mode != OImode);
6374 static int ATTRIBUTE_UNUSED
6375 return_in_memory_64 (const_tree type, enum machine_mode mode)
6377 int needed_intregs, needed_sseregs;
6378 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6381 static int ATTRIBUTE_UNUSED
6382 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6384 HOST_WIDE_INT size = int_size_in_bytes (type);
6386 /* __m128 is returned in xmm0. */
6387 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6388 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6391 /* Otherwise, the size must be exactly in [1248]. */
6392 return (size != 1 && size != 2 && size != 4 && size != 8);
6396 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6398 #ifdef SUBTARGET_RETURN_IN_MEMORY
6399 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6401 const enum machine_mode mode = type_natural_mode (type, NULL);
6405 if (ix86_function_type_abi (fntype) == MS_ABI)
6406 return return_in_memory_ms_64 (type, mode);
6408 return return_in_memory_64 (type, mode);
6411 return return_in_memory_32 (type, mode);
6415 /* Return false iff TYPE is returned in memory. This version is used
6416 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6417 but differs notably in that when MMX is available, 8-byte vectors
6418 are returned in memory, rather than in MMX registers. */
6421 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6424 enum machine_mode mode = type_natural_mode (type, NULL);
6427 return return_in_memory_64 (type, mode);
6429 if (mode == BLKmode)
6432 size = int_size_in_bytes (type);
6434 if (VECTOR_MODE_P (mode))
6436 /* Return in memory only if MMX registers *are* available. This
6437 seems backwards, but it is consistent with the existing
6444 else if (mode == TImode)
6446 else if (mode == XFmode)
6452 /* When returning SSE vector types, we have a choice of either
6453 (1) being abi incompatible with a -march switch, or
6454 (2) generating an error.
6455 Given no good solution, I think the safest thing is one warning.
6456 The user won't be able to use -Werror, but....
6458 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6459 called in response to actually generating a caller or callee that
6460 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6461 via aggregate_value_p for general type probing from tree-ssa. */
6464 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6466 static bool warnedsse, warnedmmx;
6468 if (!TARGET_64BIT && type)
6470 /* Look at the return type of the function, not the function type. */
6471 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6473 if (!TARGET_SSE && !warnedsse)
6476 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6479 warning (0, "SSE vector return without SSE enabled "
6484 if (!TARGET_MMX && !warnedmmx)
6486 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6489 warning (0, "MMX vector return without MMX enabled "
6499 /* Create the va_list data type. */
6501 /* Returns the calling convention specific va_list date type.
6502 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6505 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6507 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6509 /* For i386 we use plain pointer to argument area. */
6510 if (!TARGET_64BIT || abi == MS_ABI)
6511 return build_pointer_type (char_type_node);
6513 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6514 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6516 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6517 unsigned_type_node);
6518 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6519 unsigned_type_node);
6520 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6522 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6525 va_list_gpr_counter_field = f_gpr;
6526 va_list_fpr_counter_field = f_fpr;
6528 DECL_FIELD_CONTEXT (f_gpr) = record;
6529 DECL_FIELD_CONTEXT (f_fpr) = record;
6530 DECL_FIELD_CONTEXT (f_ovf) = record;
6531 DECL_FIELD_CONTEXT (f_sav) = record;
6533 TREE_CHAIN (record) = type_decl;
6534 TYPE_NAME (record) = type_decl;
6535 TYPE_FIELDS (record) = f_gpr;
6536 TREE_CHAIN (f_gpr) = f_fpr;
6537 TREE_CHAIN (f_fpr) = f_ovf;
6538 TREE_CHAIN (f_ovf) = f_sav;
6540 layout_type (record);
6542 /* The correct type is an array type of one element. */
6543 return build_array_type (record, build_index_type (size_zero_node));
6546 /* Setup the builtin va_list data type and for 64-bit the additional
6547 calling convention specific va_list data types. */
6550 ix86_build_builtin_va_list (void)
6552 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6554 /* Initialize abi specific va_list builtin types. */
6558 if (ix86_abi == MS_ABI)
6560 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6561 if (TREE_CODE (t) != RECORD_TYPE)
6562 t = build_variant_type_copy (t);
6563 sysv_va_list_type_node = t;
6568 if (TREE_CODE (t) != RECORD_TYPE)
6569 t = build_variant_type_copy (t);
6570 sysv_va_list_type_node = t;
6572 if (ix86_abi != MS_ABI)
6574 t = ix86_build_builtin_va_list_abi (MS_ABI);
6575 if (TREE_CODE (t) != RECORD_TYPE)
6576 t = build_variant_type_copy (t);
6577 ms_va_list_type_node = t;
6582 if (TREE_CODE (t) != RECORD_TYPE)
6583 t = build_variant_type_copy (t);
6584 ms_va_list_type_node = t;
6591 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6594 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6603 int regparm = ix86_regparm;
6605 if (cum->call_abi != ix86_abi)
6606 regparm = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6608 /* GPR size of varargs save area. */
6609 if (cfun->va_list_gpr_size)
6610 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6612 ix86_varargs_gpr_size = 0;
6614 /* FPR size of varargs save area. We don't need it if we don't pass
6615 anything in SSE registers. */
6616 if (cum->sse_nregs && cfun->va_list_fpr_size)
6617 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6619 ix86_varargs_fpr_size = 0;
6621 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6624 save_area = frame_pointer_rtx;
6625 set = get_varargs_alias_set ();
6627 for (i = cum->regno;
6629 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6632 mem = gen_rtx_MEM (Pmode,
6633 plus_constant (save_area, i * UNITS_PER_WORD));
6634 MEM_NOTRAP_P (mem) = 1;
6635 set_mem_alias_set (mem, set);
6636 emit_move_insn (mem, gen_rtx_REG (Pmode,
6637 x86_64_int_parameter_registers[i]));
6640 if (ix86_varargs_fpr_size)
6642 /* Now emit code to save SSE registers. The AX parameter contains number
6643 of SSE parameter registers used to call this function. We use
6644 sse_prologue_save insn template that produces computed jump across
6645 SSE saves. We need some preparation work to get this working. */
6647 label = gen_label_rtx ();
6648 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6650 /* Compute address to jump to :
6651 label - eax*4 + nnamed_sse_arguments*4 Or
6652 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6653 tmp_reg = gen_reg_rtx (Pmode);
6654 nsse_reg = gen_reg_rtx (Pmode);
6655 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6656 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6657 gen_rtx_MULT (Pmode, nsse_reg,
6660 /* vmovaps is one byte longer than movaps. */
6662 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6663 gen_rtx_PLUS (Pmode, tmp_reg,
6669 gen_rtx_CONST (DImode,
6670 gen_rtx_PLUS (DImode,
6672 GEN_INT (cum->sse_regno
6673 * (TARGET_AVX ? 5 : 4)))));
6675 emit_move_insn (nsse_reg, label_ref);
6676 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6678 /* Compute address of memory block we save into. We always use pointer
6679 pointing 127 bytes after first byte to store - this is needed to keep
6680 instruction size limited by 4 bytes (5 bytes for AVX) with one
6681 byte displacement. */
6682 tmp_reg = gen_reg_rtx (Pmode);
6683 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6684 plus_constant (save_area,
6685 ix86_varargs_gpr_size + 127)));
6686 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6687 MEM_NOTRAP_P (mem) = 1;
6688 set_mem_alias_set (mem, set);
6689 set_mem_align (mem, BITS_PER_WORD);
6691 /* And finally do the dirty job! */
6692 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6693 GEN_INT (cum->sse_regno), label));
6698 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6700 alias_set_type set = get_varargs_alias_set ();
6703 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6707 mem = gen_rtx_MEM (Pmode,
6708 plus_constant (virtual_incoming_args_rtx,
6709 i * UNITS_PER_WORD));
6710 MEM_NOTRAP_P (mem) = 1;
6711 set_mem_alias_set (mem, set);
6713 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6714 emit_move_insn (mem, reg);
6719 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6720 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6723 CUMULATIVE_ARGS next_cum;
6726 /* This argument doesn't appear to be used anymore. Which is good,
6727 because the old code here didn't suppress rtl generation. */
6728 gcc_assert (!no_rtl);
6733 fntype = TREE_TYPE (current_function_decl);
6735 /* For varargs, we do not want to skip the dummy va_dcl argument.
6736 For stdargs, we do want to skip the last named argument. */
6738 if (stdarg_p (fntype))
6739 function_arg_advance (&next_cum, mode, type, 1);
6741 if (cum->call_abi == MS_ABI)
6742 setup_incoming_varargs_ms_64 (&next_cum);
6744 setup_incoming_varargs_64 (&next_cum);
6747 /* Checks if TYPE is of kind va_list char *. */
6750 is_va_list_char_pointer (tree type)
6754 /* For 32-bit it is always true. */
6757 canonic = ix86_canonical_va_list_type (type);
6758 return (canonic == ms_va_list_type_node
6759 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6762 /* Implement va_start. */
6765 ix86_va_start (tree valist, rtx nextarg)
6767 HOST_WIDE_INT words, n_gpr, n_fpr;
6768 tree f_gpr, f_fpr, f_ovf, f_sav;
6769 tree gpr, fpr, ovf, sav, t;
6772 /* Only 64bit target needs something special. */
6773 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6775 std_expand_builtin_va_start (valist, nextarg);
6779 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6780 f_fpr = TREE_CHAIN (f_gpr);
6781 f_ovf = TREE_CHAIN (f_fpr);
6782 f_sav = TREE_CHAIN (f_ovf);
6784 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6785 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6786 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6787 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6788 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6790 /* Count number of gp and fp argument registers used. */
6791 words = crtl->args.info.words;
6792 n_gpr = crtl->args.info.regno;
6793 n_fpr = crtl->args.info.sse_regno;
6795 if (cfun->va_list_gpr_size)
6797 type = TREE_TYPE (gpr);
6798 t = build2 (MODIFY_EXPR, type,
6799 gpr, build_int_cst (type, n_gpr * 8));
6800 TREE_SIDE_EFFECTS (t) = 1;
6801 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6804 if (TARGET_SSE && cfun->va_list_fpr_size)
6806 type = TREE_TYPE (fpr);
6807 t = build2 (MODIFY_EXPR, type, fpr,
6808 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6809 TREE_SIDE_EFFECTS (t) = 1;
6810 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6813 /* Find the overflow area. */
6814 type = TREE_TYPE (ovf);
6815 t = make_tree (type, crtl->args.internal_arg_pointer);
6817 t = build2 (POINTER_PLUS_EXPR, type, t,
6818 size_int (words * UNITS_PER_WORD));
6819 t = build2 (MODIFY_EXPR, type, ovf, t);
6820 TREE_SIDE_EFFECTS (t) = 1;
6821 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6823 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6825 /* Find the register save area.
6826 Prologue of the function save it right above stack frame. */
6827 type = TREE_TYPE (sav);
6828 t = make_tree (type, frame_pointer_rtx);
6829 if (!ix86_varargs_gpr_size)
6830 t = build2 (POINTER_PLUS_EXPR, type, t,
6831 size_int (-8 * X86_64_REGPARM_MAX));
6832 t = build2 (MODIFY_EXPR, type, sav, t);
6833 TREE_SIDE_EFFECTS (t) = 1;
6834 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6838 /* Implement va_arg. */
6841 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6844 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6845 tree f_gpr, f_fpr, f_ovf, f_sav;
6846 tree gpr, fpr, ovf, sav, t;
6848 tree lab_false, lab_over = NULL_TREE;
6853 enum machine_mode nat_mode;
6856 /* Only 64bit target needs something special. */
6857 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6858 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6860 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6861 f_fpr = TREE_CHAIN (f_gpr);
6862 f_ovf = TREE_CHAIN (f_fpr);
6863 f_sav = TREE_CHAIN (f_ovf);
6865 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6866 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6867 valist = build_va_arg_indirect_ref (valist);
6868 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6869 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6870 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6872 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6874 type = build_pointer_type (type);
6875 size = int_size_in_bytes (type);
6876 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6878 nat_mode = type_natural_mode (type, NULL);
6887 /* Unnamed 256bit vector mode parameters are passed on stack. */
6888 if (ix86_cfun_abi () == SYSV_ABI)
6895 container = construct_container (nat_mode, TYPE_MODE (type),
6896 type, 0, X86_64_REGPARM_MAX,
6897 X86_64_SSE_REGPARM_MAX, intreg,
6902 /* Pull the value out of the saved registers. */
6904 addr = create_tmp_var (ptr_type_node, "addr");
6905 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6909 int needed_intregs, needed_sseregs;
6911 tree int_addr, sse_addr;
6913 lab_false = create_artificial_label ();
6914 lab_over = create_artificial_label ();
6916 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6918 need_temp = (!REG_P (container)
6919 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6920 || TYPE_ALIGN (type) > 128));
6922 /* In case we are passing structure, verify that it is consecutive block
6923 on the register save area. If not we need to do moves. */
6924 if (!need_temp && !REG_P (container))
6926 /* Verify that all registers are strictly consecutive */
6927 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6931 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6933 rtx slot = XVECEXP (container, 0, i);
6934 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6935 || INTVAL (XEXP (slot, 1)) != i * 16)
6943 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6945 rtx slot = XVECEXP (container, 0, i);
6946 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6947 || INTVAL (XEXP (slot, 1)) != i * 8)
6959 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6960 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6961 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6962 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6965 /* First ensure that we fit completely in registers. */
6968 t = build_int_cst (TREE_TYPE (gpr),
6969 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6970 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6971 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6972 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6973 gimplify_and_add (t, pre_p);
6977 t = build_int_cst (TREE_TYPE (fpr),
6978 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6979 + X86_64_REGPARM_MAX * 8);
6980 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6981 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6982 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6983 gimplify_and_add (t, pre_p);
6986 /* Compute index to start of area used for integer regs. */
6989 /* int_addr = gpr + sav; */
6990 t = fold_convert (sizetype, gpr);
6991 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6992 gimplify_assign (int_addr, t, pre_p);
6996 /* sse_addr = fpr + sav; */
6997 t = fold_convert (sizetype, fpr);
6998 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6999 gimplify_assign (sse_addr, t, pre_p);
7004 tree temp = create_tmp_var (type, "va_arg_tmp");
7007 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7008 gimplify_assign (addr, t, pre_p);
7010 for (i = 0; i < XVECLEN (container, 0); i++)
7012 rtx slot = XVECEXP (container, 0, i);
7013 rtx reg = XEXP (slot, 0);
7014 enum machine_mode mode = GET_MODE (reg);
7015 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7016 tree addr_type = build_pointer_type (piece_type);
7017 tree daddr_type = build_pointer_type_for_mode (piece_type,
7021 tree dest_addr, dest;
7023 if (SSE_REGNO_P (REGNO (reg)))
7025 src_addr = sse_addr;
7026 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7030 src_addr = int_addr;
7031 src_offset = REGNO (reg) * 8;
7033 src_addr = fold_convert (addr_type, src_addr);
7034 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7035 size_int (src_offset));
7036 src = build_va_arg_indirect_ref (src_addr);
7038 dest_addr = fold_convert (daddr_type, addr);
7039 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7040 size_int (INTVAL (XEXP (slot, 1))));
7041 dest = build_va_arg_indirect_ref (dest_addr);
7043 gimplify_assign (dest, src, pre_p);
7049 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7050 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7051 gimplify_assign (gpr, t, pre_p);
7056 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7057 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7058 gimplify_assign (fpr, t, pre_p);
7061 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7063 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7066 /* ... otherwise out of the overflow area. */
7068 /* When we align parameter on stack for caller, if the parameter
7069 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7070 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7071 here with caller. */
7072 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7073 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7074 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7076 /* Care for on-stack alignment if needed. */
7077 if (arg_boundary <= 64
7078 || integer_zerop (TYPE_SIZE (type)))
7082 HOST_WIDE_INT align = arg_boundary / 8;
7083 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7084 size_int (align - 1));
7085 t = fold_convert (sizetype, t);
7086 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7088 t = fold_convert (TREE_TYPE (ovf), t);
7090 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7091 gimplify_assign (addr, t, pre_p);
7093 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7094 size_int (rsize * UNITS_PER_WORD));
7095 gimplify_assign (unshare_expr (ovf), t, pre_p);
7098 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7100 ptrtype = build_pointer_type (type);
7101 addr = fold_convert (ptrtype, addr);
7104 addr = build_va_arg_indirect_ref (addr);
7105 return build_va_arg_indirect_ref (addr);
7108 /* Return nonzero if OPNUM's MEM should be matched
7109 in movabs* patterns. */
7112 ix86_check_movabs (rtx insn, int opnum)
7116 set = PATTERN (insn);
7117 if (GET_CODE (set) == PARALLEL)
7118 set = XVECEXP (set, 0, 0);
7119 gcc_assert (GET_CODE (set) == SET);
7120 mem = XEXP (set, opnum);
7121 while (GET_CODE (mem) == SUBREG)
7122 mem = SUBREG_REG (mem);
7123 gcc_assert (MEM_P (mem));
7124 return (volatile_ok || !MEM_VOLATILE_P (mem));
7127 /* Initialize the table of extra 80387 mathematical constants. */
7130 init_ext_80387_constants (void)
7132 static const char * cst[5] =
7134 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7135 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7136 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7137 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7138 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7142 for (i = 0; i < 5; i++)
7144 real_from_string (&ext_80387_constants_table[i], cst[i]);
7145 /* Ensure each constant is rounded to XFmode precision. */
7146 real_convert (&ext_80387_constants_table[i],
7147 XFmode, &ext_80387_constants_table[i]);
7150 ext_80387_constants_init = 1;
7153 /* Return true if the constant is something that can be loaded with
7154 a special instruction. */
7157 standard_80387_constant_p (rtx x)
7159 enum machine_mode mode = GET_MODE (x);
7163 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7166 if (x == CONST0_RTX (mode))
7168 if (x == CONST1_RTX (mode))
7171 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7173 /* For XFmode constants, try to find a special 80387 instruction when
7174 optimizing for size or on those CPUs that benefit from them. */
7176 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7180 if (! ext_80387_constants_init)
7181 init_ext_80387_constants ();
7183 for (i = 0; i < 5; i++)
7184 if (real_identical (&r, &ext_80387_constants_table[i]))
7188 /* Load of the constant -0.0 or -1.0 will be split as
7189 fldz;fchs or fld1;fchs sequence. */
7190 if (real_isnegzero (&r))
7192 if (real_identical (&r, &dconstm1))
7198 /* Return the opcode of the special instruction to be used to load
7202 standard_80387_constant_opcode (rtx x)
7204 switch (standard_80387_constant_p (x))
7228 /* Return the CONST_DOUBLE representing the 80387 constant that is
7229 loaded by the specified special instruction. The argument IDX
7230 matches the return value from standard_80387_constant_p. */
7233 standard_80387_constant_rtx (int idx)
7237 if (! ext_80387_constants_init)
7238 init_ext_80387_constants ();
7254 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7258 /* Return 1 if mode is a valid mode for sse. */
7260 standard_sse_mode_p (enum machine_mode mode)
7277 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7278 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7279 modes and AVX is enabled. */
7282 standard_sse_constant_p (rtx x)
7284 enum machine_mode mode = GET_MODE (x);
7286 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7288 if (vector_all_ones_operand (x, mode))
7290 if (standard_sse_mode_p (mode))
7291 return TARGET_SSE2 ? 2 : -2;
7292 else if (VALID_AVX256_REG_MODE (mode))
7293 return TARGET_AVX ? 3 : -3;
7299 /* Return the opcode of the special instruction to be used to load
7303 standard_sse_constant_opcode (rtx insn, rtx x)
7305 switch (standard_sse_constant_p (x))
7308 switch (get_attr_mode (insn))
7311 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7313 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7315 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7317 return "vxorps\t%x0, %x0, %x0";
7319 return "vxorpd\t%x0, %x0, %x0";
7321 return "vpxor\t%x0, %x0, %x0";
7327 switch (get_attr_mode (insn))
7332 return "vpcmpeqd\t%0, %0, %0";
7338 return "pcmpeqd\t%0, %0";
7343 /* Returns 1 if OP contains a symbol reference */
7346 symbolic_reference_mentioned_p (rtx op)
7351 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7354 fmt = GET_RTX_FORMAT (GET_CODE (op));
7355 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7361 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7362 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7366 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7373 /* Return 1 if it is appropriate to emit `ret' instructions in the
7374 body of a function. Do this only if the epilogue is simple, needing a
7375 couple of insns. Prior to reloading, we can't tell how many registers
7376 must be saved, so return 0 then. Return 0 if there is no frame
7377 marker to de-allocate. */
7380 ix86_can_use_return_insn_p (void)
7382 struct ix86_frame frame;
7384 if (! reload_completed || frame_pointer_needed)
7387 /* Don't allow more than 32 pop, since that's all we can do
7388 with one instruction. */
7389 if (crtl->args.pops_args
7390 && crtl->args.size >= 32768)
7393 ix86_compute_frame_layout (&frame);
7394 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7397 /* Value should be nonzero if functions must have frame pointers.
7398 Zero means the frame pointer need not be set up (and parms may
7399 be accessed via the stack pointer) in functions that seem suitable. */
7402 ix86_frame_pointer_required (void)
7404 /* If we accessed previous frames, then the generated code expects
7405 to be able to access the saved ebp value in our frame. */
7406 if (cfun->machine->accesses_prev_frame)
7409 /* Several x86 os'es need a frame pointer for other reasons,
7410 usually pertaining to setjmp. */
7411 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7414 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7415 the frame pointer by default. Turn it back on now if we've not
7416 got a leaf function. */
7417 if (TARGET_OMIT_LEAF_FRAME_POINTER
7418 && (!current_function_is_leaf
7419 || ix86_current_function_calls_tls_descriptor))
7428 /* Record that the current function accesses previous call frames. */
7431 ix86_setup_frame_addresses (void)
7433 cfun->machine->accesses_prev_frame = 1;
7436 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7437 # define USE_HIDDEN_LINKONCE 1
7439 # define USE_HIDDEN_LINKONCE 0
7442 static int pic_labels_used;
7444 /* Fills in the label name that should be used for a pc thunk for
7445 the given register. */
7448 get_pc_thunk_name (char name[32], unsigned int regno)
7450 gcc_assert (!TARGET_64BIT);
7452 if (USE_HIDDEN_LINKONCE)
7453 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7455 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7459 /* This function generates code for -fpic that loads %ebx with
7460 the return address of the caller and then returns. */
7463 ix86_file_end (void)
7468 for (regno = 0; regno < 8; ++regno)
7472 if (! ((pic_labels_used >> regno) & 1))
7475 get_pc_thunk_name (name, regno);
7480 switch_to_section (darwin_sections[text_coal_section]);
7481 fputs ("\t.weak_definition\t", asm_out_file);
7482 assemble_name (asm_out_file, name);
7483 fputs ("\n\t.private_extern\t", asm_out_file);
7484 assemble_name (asm_out_file, name);
7485 fputs ("\n", asm_out_file);
7486 ASM_OUTPUT_LABEL (asm_out_file, name);
7490 if (USE_HIDDEN_LINKONCE)
7494 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7496 TREE_PUBLIC (decl) = 1;
7497 TREE_STATIC (decl) = 1;
7498 DECL_ONE_ONLY (decl) = 1;
7500 (*targetm.asm_out.unique_section) (decl, 0);
7501 switch_to_section (get_named_section (decl, NULL, 0));
7503 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7504 fputs ("\t.hidden\t", asm_out_file);
7505 assemble_name (asm_out_file, name);
7506 fputc ('\n', asm_out_file);
7507 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7511 switch_to_section (text_section);
7512 ASM_OUTPUT_LABEL (asm_out_file, name);
7515 xops[0] = gen_rtx_REG (Pmode, regno);
7516 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7517 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7518 output_asm_insn ("ret", xops);
7521 if (NEED_INDICATE_EXEC_STACK)
7522 file_end_indicate_exec_stack ();
7525 /* Emit code for the SET_GOT patterns. */
7528 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7534 if (TARGET_VXWORKS_RTP && flag_pic)
7536 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7537 xops[2] = gen_rtx_MEM (Pmode,
7538 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7539 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7541 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7542 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7543 an unadorned address. */
7544 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7545 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7546 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7550 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7552 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7554 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7557 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7559 output_asm_insn ("call\t%a2", xops);
7562 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7563 is what will be referenced by the Mach-O PIC subsystem. */
7565 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7568 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7569 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7572 output_asm_insn ("pop%z0\t%0", xops);
7577 get_pc_thunk_name (name, REGNO (dest));
7578 pic_labels_used |= 1 << REGNO (dest);
7580 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7581 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7582 output_asm_insn ("call\t%X2", xops);
7583 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7584 is what will be referenced by the Mach-O PIC subsystem. */
7587 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7589 targetm.asm_out.internal_label (asm_out_file, "L",
7590 CODE_LABEL_NUMBER (label));
7597 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7598 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7600 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7605 /* Generate an "push" pattern for input ARG. */
7610 return gen_rtx_SET (VOIDmode,
7612 gen_rtx_PRE_DEC (Pmode,
7613 stack_pointer_rtx)),
7617 /* Return >= 0 if there is an unused call-clobbered register available
7618 for the entire function. */
7621 ix86_select_alt_pic_regnum (void)
7623 if (current_function_is_leaf && !crtl->profile
7624 && !ix86_current_function_calls_tls_descriptor)
7627 /* Can't use the same register for both PIC and DRAP. */
7629 drap = REGNO (crtl->drap_reg);
7632 for (i = 2; i >= 0; --i)
7633 if (i != drap && !df_regs_ever_live_p (i))
7637 return INVALID_REGNUM;
7640 /* Return 1 if we need to save REGNO. */
7642 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7644 if (pic_offset_table_rtx
7645 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7646 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7648 || crtl->calls_eh_return
7649 || crtl->uses_const_pool))
7651 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7656 if (crtl->calls_eh_return && maybe_eh_return)
7661 unsigned test = EH_RETURN_DATA_REGNO (i);
7662 if (test == INVALID_REGNUM)
7670 && regno == REGNO (crtl->drap_reg))
7673 return (df_regs_ever_live_p (regno)
7674 && !call_used_regs[regno]
7675 && !fixed_regs[regno]
7676 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7679 /* Return number of saved general prupose registers. */
7682 ix86_nsaved_regs (void)
7687 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7688 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7693 /* Return number of saved SSE registrers. */
7696 ix86_nsaved_sseregs (void)
7701 if (ix86_cfun_abi () != MS_ABI)
7703 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7704 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7709 /* Given FROM and TO register numbers, say whether this elimination is
7710 allowed. If stack alignment is needed, we can only replace argument
7711 pointer with hard frame pointer, or replace frame pointer with stack
7712 pointer. Otherwise, frame pointer elimination is automatically
7713 handled and all other eliminations are valid. */
7716 ix86_can_eliminate (int from, int to)
7718 if (stack_realign_fp)
7719 return ((from == ARG_POINTER_REGNUM
7720 && to == HARD_FRAME_POINTER_REGNUM)
7721 || (from == FRAME_POINTER_REGNUM
7722 && to == STACK_POINTER_REGNUM));
7724 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7727 /* Return the offset between two registers, one to be eliminated, and the other
7728 its replacement, at the start of a routine. */
7731 ix86_initial_elimination_offset (int from, int to)
7733 struct ix86_frame frame;
7734 ix86_compute_frame_layout (&frame);
7736 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7737 return frame.hard_frame_pointer_offset;
7738 else if (from == FRAME_POINTER_REGNUM
7739 && to == HARD_FRAME_POINTER_REGNUM)
7740 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7743 gcc_assert (to == STACK_POINTER_REGNUM);
7745 if (from == ARG_POINTER_REGNUM)
7746 return frame.stack_pointer_offset;
7748 gcc_assert (from == FRAME_POINTER_REGNUM);
7749 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7753 /* In a dynamically-aligned function, we can't know the offset from
7754 stack pointer to frame pointer, so we must ensure that setjmp
7755 eliminates fp against the hard fp (%ebp) rather than trying to
7756 index from %esp up to the top of the frame across a gap that is
7757 of unknown (at compile-time) size. */
7759 ix86_builtin_setjmp_frame_value (void)
7761 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7764 /* Fill structure ix86_frame about frame of currently computed function. */
7767 ix86_compute_frame_layout (struct ix86_frame *frame)
7769 HOST_WIDE_INT total_size;
7770 unsigned int stack_alignment_needed;
7771 HOST_WIDE_INT offset;
7772 unsigned int preferred_alignment;
7773 HOST_WIDE_INT size = get_frame_size ();
7775 frame->nregs = ix86_nsaved_regs ();
7776 frame->nsseregs = ix86_nsaved_sseregs ();
7779 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7780 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7782 /* MS ABI seem to require stack alignment to be always 16 except for function
7784 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7786 preferred_alignment = 16;
7787 stack_alignment_needed = 16;
7788 crtl->preferred_stack_boundary = 128;
7789 crtl->stack_alignment_needed = 128;
7792 gcc_assert (!size || stack_alignment_needed);
7793 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7794 gcc_assert (preferred_alignment <= stack_alignment_needed);
7796 /* During reload iteration the amount of registers saved can change.
7797 Recompute the value as needed. Do not recompute when amount of registers
7798 didn't change as reload does multiple calls to the function and does not
7799 expect the decision to change within single iteration. */
7800 if (!optimize_function_for_size_p (cfun)
7801 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7803 int count = frame->nregs;
7805 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7806 /* The fast prologue uses move instead of push to save registers. This
7807 is significantly longer, but also executes faster as modern hardware
7808 can execute the moves in parallel, but can't do that for push/pop.
7810 Be careful about choosing what prologue to emit: When function takes
7811 many instructions to execute we may use slow version as well as in
7812 case function is known to be outside hot spot (this is known with
7813 feedback only). Weight the size of function by number of registers
7814 to save as it is cheap to use one or two push instructions but very
7815 slow to use many of them. */
7817 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7818 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7819 || (flag_branch_probabilities
7820 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7821 cfun->machine->use_fast_prologue_epilogue = false;
7823 cfun->machine->use_fast_prologue_epilogue
7824 = !expensive_function_p (count);
7826 if (TARGET_PROLOGUE_USING_MOVE
7827 && cfun->machine->use_fast_prologue_epilogue)
7828 frame->save_regs_using_mov = true;
7830 frame->save_regs_using_mov = false;
7833 /* Skip return address and saved base pointer. */
7834 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7836 frame->hard_frame_pointer_offset = offset;
7838 /* Set offset to aligned because the realigned frame starts from
7840 if (stack_realign_fp)
7841 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7843 /* Register save area */
7844 offset += frame->nregs * UNITS_PER_WORD;
7846 /* Align SSE reg save area. */
7847 if (frame->nsseregs)
7848 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7850 frame->padding0 = 0;
7852 /* SSE register save area. */
7853 offset += frame->padding0 + frame->nsseregs * 16;
7856 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7857 offset += frame->va_arg_size;
7859 /* Align start of frame for local function. */
7860 frame->padding1 = ((offset + stack_alignment_needed - 1)
7861 & -stack_alignment_needed) - offset;
7863 offset += frame->padding1;
7865 /* Frame pointer points here. */
7866 frame->frame_pointer_offset = offset;
7870 /* Add outgoing arguments area. Can be skipped if we eliminated
7871 all the function calls as dead code.
7872 Skipping is however impossible when function calls alloca. Alloca
7873 expander assumes that last crtl->outgoing_args_size
7874 of stack frame are unused. */
7875 if (ACCUMULATE_OUTGOING_ARGS
7876 && (!current_function_is_leaf || cfun->calls_alloca
7877 || ix86_current_function_calls_tls_descriptor))
7879 offset += crtl->outgoing_args_size;
7880 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7883 frame->outgoing_arguments_size = 0;
7885 /* Align stack boundary. Only needed if we're calling another function
7887 if (!current_function_is_leaf || cfun->calls_alloca
7888 || ix86_current_function_calls_tls_descriptor)
7889 frame->padding2 = ((offset + preferred_alignment - 1)
7890 & -preferred_alignment) - offset;
7892 frame->padding2 = 0;
7894 offset += frame->padding2;
7896 /* We've reached end of stack frame. */
7897 frame->stack_pointer_offset = offset;
7899 /* Size prologue needs to allocate. */
7900 frame->to_allocate =
7901 (size + frame->padding1 + frame->padding2
7902 + frame->outgoing_arguments_size + frame->va_arg_size);
7904 if ((!frame->to_allocate && frame->nregs <= 1)
7905 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7906 frame->save_regs_using_mov = false;
7908 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7909 && current_function_is_leaf
7910 && !ix86_current_function_calls_tls_descriptor)
7912 frame->red_zone_size = frame->to_allocate;
7913 if (frame->save_regs_using_mov)
7914 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7915 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7916 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7919 frame->red_zone_size = 0;
7920 frame->to_allocate -= frame->red_zone_size;
7921 frame->stack_pointer_offset -= frame->red_zone_size;
7923 fprintf (stderr, "\n");
7924 fprintf (stderr, "size: %ld\n", (long)size);
7925 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7926 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7927 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7928 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7929 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7930 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7931 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7932 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7933 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7934 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7935 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7936 (long)frame->hard_frame_pointer_offset);
7937 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7938 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7939 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7940 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7944 /* Emit code to save registers in the prologue. */
7947 ix86_emit_save_regs (void)
7952 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7953 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7955 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7956 RTX_FRAME_RELATED_P (insn) = 1;
7960 /* Emit code to save registers using MOV insns. First register
7961 is restored from POINTER + OFFSET. */
7963 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7968 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7969 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7971 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7973 gen_rtx_REG (Pmode, regno));
7974 RTX_FRAME_RELATED_P (insn) = 1;
7975 offset += UNITS_PER_WORD;
7979 /* Emit code to save registers using MOV insns. First register
7980 is restored from POINTER + OFFSET. */
7982 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7988 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7989 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7991 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7992 set_mem_align (mem, 128);
7993 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7994 RTX_FRAME_RELATED_P (insn) = 1;
7999 /* Expand prologue or epilogue stack adjustment.
8000 The pattern exist to put a dependency on all ebp-based memory accesses.
8001 STYLE should be negative if instructions should be marked as frame related,
8002 zero if %r11 register is live and cannot be freely used and positive
8006 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
8011 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8012 else if (x86_64_immediate_operand (offset, DImode))
8013 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8017 /* r11 is used by indirect sibcall return as well, set before the
8018 epilogue and used after the epilogue. ATM indirect sibcall
8019 shouldn't be used together with huge frame sizes in one
8020 function because of the frame_size check in sibcall.c. */
8022 r11 = gen_rtx_REG (DImode, R11_REG);
8023 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8025 RTX_FRAME_RELATED_P (insn) = 1;
8026 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8030 RTX_FRAME_RELATED_P (insn) = 1;
8033 /* Find an available register to be used as dynamic realign argument
8034 pointer regsiter. Such a register will be written in prologue and
8035 used in begin of body, so it must not be
8036 1. parameter passing register.
8038 We reuse static-chain register if it is available. Otherwise, we
8039 use DI for i386 and R13 for x86-64. We chose R13 since it has
8042 Return: the regno of chosen register. */
8045 find_drap_reg (void)
8047 tree decl = cfun->decl;
8051 /* Use R13 for nested function or function need static chain.
8052 Since function with tail call may use any caller-saved
8053 registers in epilogue, DRAP must not use caller-saved
8054 register in such case. */
8055 if ((decl_function_context (decl)
8056 && !DECL_NO_STATIC_CHAIN (decl))
8057 || crtl->tail_call_emit)
8064 /* Use DI for nested function or function need static chain.
8065 Since function with tail call may use any caller-saved
8066 registers in epilogue, DRAP must not use caller-saved
8067 register in such case. */
8068 if ((decl_function_context (decl)
8069 && !DECL_NO_STATIC_CHAIN (decl))
8070 || crtl->tail_call_emit)
8073 /* Reuse static chain register if it isn't used for parameter
8075 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8076 && !lookup_attribute ("fastcall",
8077 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8084 /* Update incoming stack boundary and estimated stack alignment. */
8087 ix86_update_stack_boundary (void)
8089 /* Prefer the one specified at command line. */
8090 ix86_incoming_stack_boundary
8091 = (ix86_user_incoming_stack_boundary
8092 ? ix86_user_incoming_stack_boundary
8093 : ix86_default_incoming_stack_boundary);
8095 /* Incoming stack alignment can be changed on individual functions
8096 via force_align_arg_pointer attribute. We use the smallest
8097 incoming stack boundary. */
8098 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8099 && lookup_attribute (ix86_force_align_arg_pointer_string,
8100 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8101 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8103 /* The incoming stack frame has to be aligned at least at
8104 parm_stack_boundary. */
8105 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8106 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8108 /* Stack at entrance of main is aligned by runtime. We use the
8109 smallest incoming stack boundary. */
8110 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8111 && DECL_NAME (current_function_decl)
8112 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8113 && DECL_FILE_SCOPE_P (current_function_decl))
8114 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8116 /* x86_64 vararg needs 16byte stack alignment for register save
8120 && crtl->stack_alignment_estimated < 128)
8121 crtl->stack_alignment_estimated = 128;
8124 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8125 needed or an rtx for DRAP otherwise. */
8128 ix86_get_drap_rtx (void)
8130 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8131 crtl->need_drap = true;
8133 if (stack_realign_drap)
8135 /* Assign DRAP to vDRAP and returns vDRAP */
8136 unsigned int regno = find_drap_reg ();
8141 arg_ptr = gen_rtx_REG (Pmode, regno);
8142 crtl->drap_reg = arg_ptr;
8145 drap_vreg = copy_to_reg (arg_ptr);
8149 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8150 RTX_FRAME_RELATED_P (insn) = 1;
8157 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8160 ix86_internal_arg_pointer (void)
8162 return virtual_incoming_args_rtx;
8165 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8166 This is called from dwarf2out.c to emit call frame instructions
8167 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8169 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8171 rtx unspec = SET_SRC (pattern);
8172 gcc_assert (GET_CODE (unspec) == UNSPEC);
8176 case UNSPEC_REG_SAVE:
8177 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8178 SET_DEST (pattern));
8180 case UNSPEC_DEF_CFA:
8181 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8182 INTVAL (XVECEXP (unspec, 0, 0)));
8189 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8190 to be generated in correct form. */
8192 ix86_finalize_stack_realign_flags (void)
8194 /* Check if stack realign is really needed after reload, and
8195 stores result in cfun */
8196 unsigned int incoming_stack_boundary
8197 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8198 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8199 unsigned int stack_realign = (incoming_stack_boundary
8200 < (current_function_is_leaf
8201 ? crtl->max_used_stack_slot_alignment
8202 : crtl->stack_alignment_needed));
8204 if (crtl->stack_realign_finalized)
8206 /* After stack_realign_needed is finalized, we can't no longer
8208 gcc_assert (crtl->stack_realign_needed == stack_realign);
8212 crtl->stack_realign_needed = stack_realign;
8213 crtl->stack_realign_finalized = true;
8217 /* Expand the prologue into a bunch of separate insns. */
8220 ix86_expand_prologue (void)
8224 struct ix86_frame frame;
8225 HOST_WIDE_INT allocate;
8227 ix86_finalize_stack_realign_flags ();
8229 /* DRAP should not coexist with stack_realign_fp */
8230 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8232 ix86_compute_frame_layout (&frame);
8234 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8235 of DRAP is needed and stack realignment is really needed after reload */
8236 if (crtl->drap_reg && crtl->stack_realign_needed)
8239 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8240 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8241 ? 0 : UNITS_PER_WORD);
8243 gcc_assert (stack_realign_drap);
8245 /* Grab the argument pointer. */
8246 x = plus_constant (stack_pointer_rtx,
8247 (UNITS_PER_WORD + param_ptr_offset));
8250 /* Only need to push parameter pointer reg if it is caller
8252 if (!call_used_regs[REGNO (crtl->drap_reg)])
8254 /* Push arg pointer reg */
8255 insn = emit_insn (gen_push (y));
8256 RTX_FRAME_RELATED_P (insn) = 1;
8259 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8260 RTX_FRAME_RELATED_P (insn) = 1;
8262 /* Align the stack. */
8263 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8265 GEN_INT (-align_bytes)));
8266 RTX_FRAME_RELATED_P (insn) = 1;
8268 /* Replicate the return address on the stack so that return
8269 address can be reached via (argp - 1) slot. This is needed
8270 to implement macro RETURN_ADDR_RTX and intrinsic function
8271 expand_builtin_return_addr etc. */
8273 x = gen_frame_mem (Pmode,
8274 plus_constant (x, -UNITS_PER_WORD));
8275 insn = emit_insn (gen_push (x));
8276 RTX_FRAME_RELATED_P (insn) = 1;
8279 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8280 slower on all targets. Also sdb doesn't like it. */
8282 if (frame_pointer_needed)
8284 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8285 RTX_FRAME_RELATED_P (insn) = 1;
8287 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8288 RTX_FRAME_RELATED_P (insn) = 1;
8291 if (stack_realign_fp)
8293 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8294 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8296 /* Align the stack. */
8297 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8299 GEN_INT (-align_bytes)));
8300 RTX_FRAME_RELATED_P (insn) = 1;
8303 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8305 if (!frame.save_regs_using_mov)
8306 ix86_emit_save_regs ();
8308 allocate += frame.nregs * UNITS_PER_WORD;
8310 /* When using red zone we may start register saving before allocating
8311 the stack frame saving one cycle of the prologue. However I will
8312 avoid doing this if I am going to have to probe the stack since
8313 at least on x86_64 the stack probe can turn into a call that clobbers
8314 a red zone location */
8315 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8316 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8317 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8318 && !crtl->stack_realign_needed)
8319 ? hard_frame_pointer_rtx
8320 : stack_pointer_rtx,
8321 -frame.nregs * UNITS_PER_WORD);
8325 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8326 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8327 GEN_INT (-allocate), -1);
8330 /* Only valid for Win32. */
8331 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8335 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8337 if (cfun->machine->call_abi == MS_ABI)
8340 eax_live = ix86_eax_live_at_start_p ();
8344 emit_insn (gen_push (eax));
8345 allocate -= UNITS_PER_WORD;
8348 emit_move_insn (eax, GEN_INT (allocate));
8351 insn = gen_allocate_stack_worker_64 (eax, eax);
8353 insn = gen_allocate_stack_worker_32 (eax, eax);
8354 insn = emit_insn (insn);
8355 RTX_FRAME_RELATED_P (insn) = 1;
8356 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8357 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8358 add_reg_note (insn, REG_FRAME_RELATED_EXPR, t);
8362 if (frame_pointer_needed)
8363 t = plus_constant (hard_frame_pointer_rtx,
8366 - frame.nregs * UNITS_PER_WORD);
8368 t = plus_constant (stack_pointer_rtx, allocate);
8369 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8373 if (frame.save_regs_using_mov
8374 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8375 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8377 if (!frame_pointer_needed
8378 || !frame.to_allocate
8379 || crtl->stack_realign_needed)
8380 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8382 + frame.nsseregs * 16 + frame.padding0);
8384 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8385 -frame.nregs * UNITS_PER_WORD);
8387 if (!frame_pointer_needed
8388 || !frame.to_allocate
8389 || crtl->stack_realign_needed)
8390 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8393 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8394 - frame.nregs * UNITS_PER_WORD
8395 - frame.nsseregs * 16
8398 pic_reg_used = false;
8399 if (pic_offset_table_rtx
8400 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8403 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8405 if (alt_pic_reg_used != INVALID_REGNUM)
8406 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8408 pic_reg_used = true;
8415 if (ix86_cmodel == CM_LARGE_PIC)
8417 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8418 rtx label = gen_label_rtx ();
8420 LABEL_PRESERVE_P (label) = 1;
8421 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8422 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8423 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8424 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8425 pic_offset_table_rtx, tmp_reg));
8428 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8431 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8434 /* In the pic_reg_used case, make sure that the got load isn't deleted
8435 when mcount needs it. Blockage to avoid call movement across mcount
8436 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8438 if (crtl->profile && pic_reg_used)
8439 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8441 if (crtl->drap_reg && !crtl->stack_realign_needed)
8443 /* vDRAP is setup but after reload it turns out stack realign
8444 isn't necessary, here we will emit prologue to setup DRAP
8445 without stack realign adjustment */
8446 int drap_bp_offset = UNITS_PER_WORD * 2;
8447 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8448 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8451 /* Prevent instructions from being scheduled into register save push
8452 sequence when access to the redzone area is done through frame pointer.
8453 The offset betweeh the frame pointer and the stack pointer is calculated
8454 relative to the value of the stack pointer at the end of the function
8455 prologue, and moving instructions that access redzone area via frame
8456 pointer inside push sequence violates this assumption. */
8457 if (frame_pointer_needed && frame.red_zone_size)
8458 emit_insn (gen_memory_blockage ());
8460 /* Emit cld instruction if stringops are used in the function. */
8461 if (TARGET_CLD && ix86_current_function_needs_cld)
8462 emit_insn (gen_cld ());
8465 /* Emit code to restore saved registers using MOV insns. First register
8466 is restored from POINTER + OFFSET. */
8468 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8469 int maybe_eh_return)
8472 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8474 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8475 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8477 /* Ensure that adjust_address won't be forced to produce pointer
8478 out of range allowed by x86-64 instruction set. */
8479 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8483 r11 = gen_rtx_REG (DImode, R11_REG);
8484 emit_move_insn (r11, GEN_INT (offset));
8485 emit_insn (gen_adddi3 (r11, r11, pointer));
8486 base_address = gen_rtx_MEM (Pmode, r11);
8489 emit_move_insn (gen_rtx_REG (Pmode, regno),
8490 adjust_address (base_address, Pmode, offset));
8491 offset += UNITS_PER_WORD;
8495 /* Emit code to restore saved registers using MOV insns. First register
8496 is restored from POINTER + OFFSET. */
8498 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8499 int maybe_eh_return)
8502 rtx base_address = gen_rtx_MEM (TImode, pointer);
8505 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8506 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8508 /* Ensure that adjust_address won't be forced to produce pointer
8509 out of range allowed by x86-64 instruction set. */
8510 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8514 r11 = gen_rtx_REG (DImode, R11_REG);
8515 emit_move_insn (r11, GEN_INT (offset));
8516 emit_insn (gen_adddi3 (r11, r11, pointer));
8517 base_address = gen_rtx_MEM (TImode, r11);
8520 mem = adjust_address (base_address, TImode, offset);
8521 set_mem_align (mem, 128);
8522 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8527 /* Restore function stack, frame, and registers. */
8530 ix86_expand_epilogue (int style)
8534 struct ix86_frame frame;
8535 HOST_WIDE_INT offset;
8537 ix86_finalize_stack_realign_flags ();
8539 /* When stack is realigned, SP must be valid. */
8540 sp_valid = (!frame_pointer_needed
8541 || current_function_sp_is_unchanging
8542 || stack_realign_fp);
8544 ix86_compute_frame_layout (&frame);
8546 /* See the comment about red zone and frame
8547 pointer usage in ix86_expand_prologue. */
8548 if (frame_pointer_needed && frame.red_zone_size)
8549 emit_insn (gen_memory_blockage ());
8551 /* Calculate start of saved registers relative to ebp. Special care
8552 must be taken for the normal return case of a function using
8553 eh_return: the eax and edx registers are marked as saved, but not
8554 restored along this path. */
8555 offset = frame.nregs;
8556 if (crtl->calls_eh_return && style != 2)
8558 offset *= -UNITS_PER_WORD;
8559 offset -= frame.nsseregs * 16 + frame.padding0;
8561 /* If we're only restoring one register and sp is not valid then
8562 using a move instruction to restore the register since it's
8563 less work than reloading sp and popping the register.
8565 The default code result in stack adjustment using add/lea instruction,
8566 while this code results in LEAVE instruction (or discrete equivalent),
8567 so it is profitable in some other cases as well. Especially when there
8568 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8569 and there is exactly one register to pop. This heuristic may need some
8570 tuning in future. */
8571 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8572 || (TARGET_EPILOGUE_USING_MOVE
8573 && cfun->machine->use_fast_prologue_epilogue
8574 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8575 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8576 || (frame_pointer_needed && TARGET_USE_LEAVE
8577 && cfun->machine->use_fast_prologue_epilogue
8578 && (frame.nregs + frame.nsseregs) == 1)
8579 || crtl->calls_eh_return)
8581 /* Restore registers. We can use ebp or esp to address the memory
8582 locations. If both are available, default to ebp, since offsets
8583 are known to be small. Only exception is esp pointing directly
8584 to the end of block of saved registers, where we may simplify
8587 If we are realigning stack with bp and sp, regs restore can't
8588 be addressed by bp. sp must be used instead. */
8590 if (!frame_pointer_needed
8591 || (sp_valid && !frame.to_allocate)
8592 || stack_realign_fp)
8594 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8595 frame.to_allocate, style == 2);
8596 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8598 + frame.nsseregs * 16
8599 + frame.padding0, style == 2);
8603 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8604 offset, style == 2);
8605 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8607 + frame.nsseregs * 16
8608 + frame.padding0, style == 2);
8611 /* eh_return epilogues need %ecx added to the stack pointer. */
8614 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8616 /* Stack align doesn't work with eh_return. */
8617 gcc_assert (!crtl->stack_realign_needed);
8619 if (frame_pointer_needed)
8621 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8622 tmp = plus_constant (tmp, UNITS_PER_WORD);
8623 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8625 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8626 emit_move_insn (hard_frame_pointer_rtx, tmp);
8628 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8633 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8634 tmp = plus_constant (tmp, (frame.to_allocate
8635 + frame.nregs * UNITS_PER_WORD
8636 + frame.nsseregs * 16
8638 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8641 else if (!frame_pointer_needed)
8642 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8643 GEN_INT (frame.to_allocate
8644 + frame.nregs * UNITS_PER_WORD
8645 + frame.nsseregs * 16
8648 /* If not an i386, mov & pop is faster than "leave". */
8649 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8650 || !cfun->machine->use_fast_prologue_epilogue)
8651 emit_insn ((*ix86_gen_leave) ());
8654 pro_epilogue_adjust_stack (stack_pointer_rtx,
8655 hard_frame_pointer_rtx,
8658 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8663 /* First step is to deallocate the stack frame so that we can
8666 If we realign stack with frame pointer, then stack pointer
8667 won't be able to recover via lea $offset(%bp), %sp, because
8668 there is a padding area between bp and sp for realign.
8669 "add $to_allocate, %sp" must be used instead. */
8672 gcc_assert (frame_pointer_needed);
8673 gcc_assert (!stack_realign_fp);
8674 pro_epilogue_adjust_stack (stack_pointer_rtx,
8675 hard_frame_pointer_rtx,
8676 GEN_INT (offset), style);
8677 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8678 frame.to_allocate, style == 2);
8679 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8680 GEN_INT (frame.nsseregs * 16), style);
8682 else if (frame.to_allocate || frame.nsseregs)
8684 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8687 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8688 GEN_INT (frame.to_allocate
8689 + frame.nsseregs * 16
8690 + frame.padding0), style);
8693 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8694 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8695 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8696 if (frame_pointer_needed)
8698 /* Leave results in shorter dependency chains on CPUs that are
8699 able to grok it fast. */
8700 if (TARGET_USE_LEAVE)
8701 emit_insn ((*ix86_gen_leave) ());
8704 /* For stack realigned really happens, recover stack
8705 pointer to hard frame pointer is a must, if not using
8707 if (stack_realign_fp)
8708 pro_epilogue_adjust_stack (stack_pointer_rtx,
8709 hard_frame_pointer_rtx,
8711 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8716 if (crtl->drap_reg && crtl->stack_realign_needed)
8718 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8719 ? 0 : UNITS_PER_WORD);
8720 gcc_assert (stack_realign_drap);
8721 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8723 GEN_INT (-(UNITS_PER_WORD
8724 + param_ptr_offset))));
8725 if (!call_used_regs[REGNO (crtl->drap_reg)])
8726 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8730 /* Sibcall epilogues don't want a return instruction. */
8734 if (crtl->args.pops_args && crtl->args.size)
8736 rtx popc = GEN_INT (crtl->args.pops_args);
8738 /* i386 can only pop 64K bytes. If asked to pop more, pop
8739 return address, do explicit add, and jump indirectly to the
8742 if (crtl->args.pops_args >= 65536)
8744 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8746 /* There is no "pascal" calling convention in any 64bit ABI. */
8747 gcc_assert (!TARGET_64BIT);
8749 emit_insn (gen_popsi1 (ecx));
8750 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8751 emit_jump_insn (gen_return_indirect_internal (ecx));
8754 emit_jump_insn (gen_return_pop_internal (popc));
8757 emit_jump_insn (gen_return_internal ());
8760 /* Reset from the function's potential modifications. */
8763 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8764 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8766 if (pic_offset_table_rtx)
8767 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8769 /* Mach-O doesn't support labels at the end of objects, so if
8770 it looks like we might want one, insert a NOP. */
8772 rtx insn = get_last_insn ();
8775 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8776 insn = PREV_INSN (insn);
8780 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8781 fputs ("\tnop\n", file);
8787 /* Extract the parts of an RTL expression that is a valid memory address
8788 for an instruction. Return 0 if the structure of the address is
8789 grossly off. Return -1 if the address contains ASHIFT, so it is not
8790 strictly valid, but still used for computing length of lea instruction. */
8793 ix86_decompose_address (rtx addr, struct ix86_address *out)
8795 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8796 rtx base_reg, index_reg;
8797 HOST_WIDE_INT scale = 1;
8798 rtx scale_rtx = NULL_RTX;
8800 enum ix86_address_seg seg = SEG_DEFAULT;
8802 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8804 else if (GET_CODE (addr) == PLUS)
8814 addends[n++] = XEXP (op, 1);
8817 while (GET_CODE (op) == PLUS);
8822 for (i = n; i >= 0; --i)
8825 switch (GET_CODE (op))
8830 index = XEXP (op, 0);
8831 scale_rtx = XEXP (op, 1);
8835 if (XINT (op, 1) == UNSPEC_TP
8836 && TARGET_TLS_DIRECT_SEG_REFS
8837 && seg == SEG_DEFAULT)
8838 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8867 else if (GET_CODE (addr) == MULT)
8869 index = XEXP (addr, 0); /* index*scale */
8870 scale_rtx = XEXP (addr, 1);
8872 else if (GET_CODE (addr) == ASHIFT)
8876 /* We're called for lea too, which implements ashift on occasion. */
8877 index = XEXP (addr, 0);
8878 tmp = XEXP (addr, 1);
8879 if (!CONST_INT_P (tmp))
8881 scale = INTVAL (tmp);
8882 if ((unsigned HOST_WIDE_INT) scale > 3)
8888 disp = addr; /* displacement */
8890 /* Extract the integral value of scale. */
8893 if (!CONST_INT_P (scale_rtx))
8895 scale = INTVAL (scale_rtx);
8898 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8899 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8901 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8902 if (base_reg && index_reg && scale == 1
8903 && (index_reg == arg_pointer_rtx
8904 || index_reg == frame_pointer_rtx
8905 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8908 tmp = base, base = index, index = tmp;
8909 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8912 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8913 if ((base_reg == hard_frame_pointer_rtx
8914 || base_reg == frame_pointer_rtx
8915 || base_reg == arg_pointer_rtx) && !disp)
8918 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8919 Avoid this by transforming to [%esi+0].
8920 Reload calls address legitimization without cfun defined, so we need
8921 to test cfun for being non-NULL. */
8922 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8923 && base_reg && !index_reg && !disp
8925 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8928 /* Special case: encode reg+reg instead of reg*2. */
8929 if (!base && index && scale && scale == 2)
8930 base = index, base_reg = index_reg, scale = 1;
8932 /* Special case: scaling cannot be encoded without base or displacement. */
8933 if (!base && !disp && index && scale != 1)
8945 /* Return cost of the memory address x.
8946 For i386, it is better to use a complex address than let gcc copy
8947 the address into a reg and make a new pseudo. But not if the address
8948 requires to two regs - that would mean more pseudos with longer
8951 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8953 struct ix86_address parts;
8955 int ok = ix86_decompose_address (x, &parts);
8959 if (parts.base && GET_CODE (parts.base) == SUBREG)
8960 parts.base = SUBREG_REG (parts.base);
8961 if (parts.index && GET_CODE (parts.index) == SUBREG)
8962 parts.index = SUBREG_REG (parts.index);
8964 /* Attempt to minimize number of registers in the address. */
8966 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8968 && (!REG_P (parts.index)
8969 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8973 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8975 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8976 && parts.base != parts.index)
8979 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8980 since it's predecode logic can't detect the length of instructions
8981 and it degenerates to vector decoded. Increase cost of such
8982 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8983 to split such addresses or even refuse such addresses at all.
8985 Following addressing modes are affected:
8990 The first and last case may be avoidable by explicitly coding the zero in
8991 memory address, but I don't have AMD-K6 machine handy to check this
8995 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8996 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8997 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9003 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9004 this is used for to form addresses to local data when -fPIC is in
9008 darwin_local_data_pic (rtx disp)
9010 return (GET_CODE (disp) == UNSPEC
9011 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9014 /* Determine if a given RTX is a valid constant. We already know this
9015 satisfies CONSTANT_P. */
9018 legitimate_constant_p (rtx x)
9020 switch (GET_CODE (x))
9025 if (GET_CODE (x) == PLUS)
9027 if (!CONST_INT_P (XEXP (x, 1)))
9032 if (TARGET_MACHO && darwin_local_data_pic (x))
9035 /* Only some unspecs are valid as "constants". */
9036 if (GET_CODE (x) == UNSPEC)
9037 switch (XINT (x, 1))
9042 return TARGET_64BIT;
9045 x = XVECEXP (x, 0, 0);
9046 return (GET_CODE (x) == SYMBOL_REF
9047 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9049 x = XVECEXP (x, 0, 0);
9050 return (GET_CODE (x) == SYMBOL_REF
9051 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9056 /* We must have drilled down to a symbol. */
9057 if (GET_CODE (x) == LABEL_REF)
9059 if (GET_CODE (x) != SYMBOL_REF)
9064 /* TLS symbols are never valid. */
9065 if (SYMBOL_REF_TLS_MODEL (x))
9068 /* DLLIMPORT symbols are never valid. */
9069 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9070 && SYMBOL_REF_DLLIMPORT_P (x))
9075 if (GET_MODE (x) == TImode
9076 && x != CONST0_RTX (TImode)
9082 if (!standard_sse_constant_p (x))
9089 /* Otherwise we handle everything else in the move patterns. */
9093 /* Determine if it's legal to put X into the constant pool. This
9094 is not possible for the address of thread-local symbols, which
9095 is checked above. */
9098 ix86_cannot_force_const_mem (rtx x)
9100 /* We can always put integral constants and vectors in memory. */
9101 switch (GET_CODE (x))
9111 return !legitimate_constant_p (x);
9115 /* Nonzero if the constant value X is a legitimate general operand
9116 when generating PIC code. It is given that flag_pic is on and
9117 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9120 legitimate_pic_operand_p (rtx x)
9124 switch (GET_CODE (x))
9127 inner = XEXP (x, 0);
9128 if (GET_CODE (inner) == PLUS
9129 && CONST_INT_P (XEXP (inner, 1)))
9130 inner = XEXP (inner, 0);
9132 /* Only some unspecs are valid as "constants". */
9133 if (GET_CODE (inner) == UNSPEC)
9134 switch (XINT (inner, 1))
9139 return TARGET_64BIT;
9141 x = XVECEXP (inner, 0, 0);
9142 return (GET_CODE (x) == SYMBOL_REF
9143 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9144 case UNSPEC_MACHOPIC_OFFSET:
9145 return legitimate_pic_address_disp_p (x);
9153 return legitimate_pic_address_disp_p (x);
9160 /* Determine if a given CONST RTX is a valid memory displacement
9164 legitimate_pic_address_disp_p (rtx disp)
9168 /* In 64bit mode we can allow direct addresses of symbols and labels
9169 when they are not dynamic symbols. */
9172 rtx op0 = disp, op1;
9174 switch (GET_CODE (disp))
9180 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9182 op0 = XEXP (XEXP (disp, 0), 0);
9183 op1 = XEXP (XEXP (disp, 0), 1);
9184 if (!CONST_INT_P (op1)
9185 || INTVAL (op1) >= 16*1024*1024
9186 || INTVAL (op1) < -16*1024*1024)
9188 if (GET_CODE (op0) == LABEL_REF)
9190 if (GET_CODE (op0) != SYMBOL_REF)
9195 /* TLS references should always be enclosed in UNSPEC. */
9196 if (SYMBOL_REF_TLS_MODEL (op0))
9198 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9199 && ix86_cmodel != CM_LARGE_PIC)
9207 if (GET_CODE (disp) != CONST)
9209 disp = XEXP (disp, 0);
9213 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9214 of GOT tables. We should not need these anyway. */
9215 if (GET_CODE (disp) != UNSPEC
9216 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9217 && XINT (disp, 1) != UNSPEC_GOTOFF
9218 && XINT (disp, 1) != UNSPEC_PLTOFF))
9221 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9222 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9228 if (GET_CODE (disp) == PLUS)
9230 if (!CONST_INT_P (XEXP (disp, 1)))
9232 disp = XEXP (disp, 0);
9236 if (TARGET_MACHO && darwin_local_data_pic (disp))
9239 if (GET_CODE (disp) != UNSPEC)
9242 switch (XINT (disp, 1))
9247 /* We need to check for both symbols and labels because VxWorks loads
9248 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9250 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9251 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9253 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9254 While ABI specify also 32bit relocation but we don't produce it in
9255 small PIC model at all. */
9256 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9257 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9259 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9261 case UNSPEC_GOTTPOFF:
9262 case UNSPEC_GOTNTPOFF:
9263 case UNSPEC_INDNTPOFF:
9266 disp = XVECEXP (disp, 0, 0);
9267 return (GET_CODE (disp) == SYMBOL_REF
9268 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9270 disp = XVECEXP (disp, 0, 0);
9271 return (GET_CODE (disp) == SYMBOL_REF
9272 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9274 disp = XVECEXP (disp, 0, 0);
9275 return (GET_CODE (disp) == SYMBOL_REF
9276 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9282 /* Recognizes RTL expressions that are valid memory addresses for an
9283 instruction. The MODE argument is the machine mode for the MEM
9284 expression that wants to use this address.
9286 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9287 convert common non-canonical forms to canonical form so that they will
9291 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9292 rtx addr, bool strict)
9294 struct ix86_address parts;
9295 rtx base, index, disp;
9296 HOST_WIDE_INT scale;
9297 const char *reason = NULL;
9298 rtx reason_rtx = NULL_RTX;
9300 if (ix86_decompose_address (addr, &parts) <= 0)
9302 reason = "decomposition failed";
9307 index = parts.index;
9309 scale = parts.scale;
9311 /* Validate base register.
9313 Don't allow SUBREG's that span more than a word here. It can lead to spill
9314 failures when the base is one word out of a two word structure, which is
9315 represented internally as a DImode int. */
9324 else if (GET_CODE (base) == SUBREG
9325 && REG_P (SUBREG_REG (base))
9326 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9328 reg = SUBREG_REG (base);
9331 reason = "base is not a register";
9335 if (GET_MODE (base) != Pmode)
9337 reason = "base is not in Pmode";
9341 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9342 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9344 reason = "base is not valid";
9349 /* Validate index register.
9351 Don't allow SUBREG's that span more than a word here -- same as above. */
9360 else if (GET_CODE (index) == SUBREG
9361 && REG_P (SUBREG_REG (index))
9362 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9364 reg = SUBREG_REG (index);
9367 reason = "index is not a register";
9371 if (GET_MODE (index) != Pmode)
9373 reason = "index is not in Pmode";
9377 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9378 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9380 reason = "index is not valid";
9385 /* Validate scale factor. */
9388 reason_rtx = GEN_INT (scale);
9391 reason = "scale without index";
9395 if (scale != 2 && scale != 4 && scale != 8)
9397 reason = "scale is not a valid multiplier";
9402 /* Validate displacement. */
9407 if (GET_CODE (disp) == CONST
9408 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9409 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9410 switch (XINT (XEXP (disp, 0), 1))
9412 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9413 used. While ABI specify also 32bit relocations, we don't produce
9414 them at all and use IP relative instead. */
9417 gcc_assert (flag_pic);
9419 goto is_legitimate_pic;
9420 reason = "64bit address unspec";
9423 case UNSPEC_GOTPCREL:
9424 gcc_assert (flag_pic);
9425 goto is_legitimate_pic;
9427 case UNSPEC_GOTTPOFF:
9428 case UNSPEC_GOTNTPOFF:
9429 case UNSPEC_INDNTPOFF:
9435 reason = "invalid address unspec";
9439 else if (SYMBOLIC_CONST (disp)
9443 && MACHOPIC_INDIRECT
9444 && !machopic_operand_p (disp)
9450 if (TARGET_64BIT && (index || base))
9452 /* foo@dtpoff(%rX) is ok. */
9453 if (GET_CODE (disp) != CONST
9454 || GET_CODE (XEXP (disp, 0)) != PLUS
9455 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9456 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9457 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9458 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9460 reason = "non-constant pic memory reference";
9464 else if (! legitimate_pic_address_disp_p (disp))
9466 reason = "displacement is an invalid pic construct";
9470 /* This code used to verify that a symbolic pic displacement
9471 includes the pic_offset_table_rtx register.
9473 While this is good idea, unfortunately these constructs may
9474 be created by "adds using lea" optimization for incorrect
9483 This code is nonsensical, but results in addressing
9484 GOT table with pic_offset_table_rtx base. We can't
9485 just refuse it easily, since it gets matched by
9486 "addsi3" pattern, that later gets split to lea in the
9487 case output register differs from input. While this
9488 can be handled by separate addsi pattern for this case
9489 that never results in lea, this seems to be easier and
9490 correct fix for crash to disable this test. */
9492 else if (GET_CODE (disp) != LABEL_REF
9493 && !CONST_INT_P (disp)
9494 && (GET_CODE (disp) != CONST
9495 || !legitimate_constant_p (disp))
9496 && (GET_CODE (disp) != SYMBOL_REF
9497 || !legitimate_constant_p (disp)))
9499 reason = "displacement is not constant";
9502 else if (TARGET_64BIT
9503 && !x86_64_immediate_operand (disp, VOIDmode))
9505 reason = "displacement is out of range";
9510 /* Everything looks valid. */
9517 /* Determine if a given RTX is a valid constant address. */
9520 constant_address_p (rtx x)
9522 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9525 /* Return a unique alias set for the GOT. */
9527 static alias_set_type
9528 ix86_GOT_alias_set (void)
9530 static alias_set_type set = -1;
9532 set = new_alias_set ();
9536 /* Return a legitimate reference for ORIG (an address) using the
9537 register REG. If REG is 0, a new pseudo is generated.
9539 There are two types of references that must be handled:
9541 1. Global data references must load the address from the GOT, via
9542 the PIC reg. An insn is emitted to do this load, and the reg is
9545 2. Static data references, constant pool addresses, and code labels
9546 compute the address as an offset from the GOT, whose base is in
9547 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9548 differentiate them from global data objects. The returned
9549 address is the PIC reg + an unspec constant.
9551 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9552 reg also appears in the address. */
9555 legitimize_pic_address (rtx orig, rtx reg)
9562 if (TARGET_MACHO && !TARGET_64BIT)
9565 reg = gen_reg_rtx (Pmode);
9566 /* Use the generic Mach-O PIC machinery. */
9567 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9571 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9573 else if (TARGET_64BIT
9574 && ix86_cmodel != CM_SMALL_PIC
9575 && gotoff_operand (addr, Pmode))
9578 /* This symbol may be referenced via a displacement from the PIC
9579 base address (@GOTOFF). */
9581 if (reload_in_progress)
9582 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9583 if (GET_CODE (addr) == CONST)
9584 addr = XEXP (addr, 0);
9585 if (GET_CODE (addr) == PLUS)
9587 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9589 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9592 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9593 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9595 tmpreg = gen_reg_rtx (Pmode);
9598 emit_move_insn (tmpreg, new_rtx);
9602 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9603 tmpreg, 1, OPTAB_DIRECT);
9606 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9608 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9610 /* This symbol may be referenced via a displacement from the PIC
9611 base address (@GOTOFF). */
9613 if (reload_in_progress)
9614 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9615 if (GET_CODE (addr) == CONST)
9616 addr = XEXP (addr, 0);
9617 if (GET_CODE (addr) == PLUS)
9619 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9621 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9624 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9625 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9626 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9630 emit_move_insn (reg, new_rtx);
9634 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9635 /* We can't use @GOTOFF for text labels on VxWorks;
9636 see gotoff_operand. */
9637 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9639 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9641 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9642 return legitimize_dllimport_symbol (addr, true);
9643 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9644 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9645 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9647 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9648 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9652 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9654 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9655 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9656 new_rtx = gen_const_mem (Pmode, new_rtx);
9657 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9660 reg = gen_reg_rtx (Pmode);
9661 /* Use directly gen_movsi, otherwise the address is loaded
9662 into register for CSE. We don't want to CSE this addresses,
9663 instead we CSE addresses from the GOT table, so skip this. */
9664 emit_insn (gen_movsi (reg, new_rtx));
9669 /* This symbol must be referenced via a load from the
9670 Global Offset Table (@GOT). */
9672 if (reload_in_progress)
9673 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9674 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9675 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9677 new_rtx = force_reg (Pmode, new_rtx);
9678 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9679 new_rtx = gen_const_mem (Pmode, new_rtx);
9680 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9683 reg = gen_reg_rtx (Pmode);
9684 emit_move_insn (reg, new_rtx);
9690 if (CONST_INT_P (addr)
9691 && !x86_64_immediate_operand (addr, VOIDmode))
9695 emit_move_insn (reg, addr);
9699 new_rtx = force_reg (Pmode, addr);
9701 else if (GET_CODE (addr) == CONST)
9703 addr = XEXP (addr, 0);
9705 /* We must match stuff we generate before. Assume the only
9706 unspecs that can get here are ours. Not that we could do
9707 anything with them anyway.... */
9708 if (GET_CODE (addr) == UNSPEC
9709 || (GET_CODE (addr) == PLUS
9710 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9712 gcc_assert (GET_CODE (addr) == PLUS);
9714 if (GET_CODE (addr) == PLUS)
9716 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9718 /* Check first to see if this is a constant offset from a @GOTOFF
9719 symbol reference. */
9720 if (gotoff_operand (op0, Pmode)
9721 && CONST_INT_P (op1))
9725 if (reload_in_progress)
9726 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9727 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9729 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9730 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9731 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9735 emit_move_insn (reg, new_rtx);
9741 if (INTVAL (op1) < -16*1024*1024
9742 || INTVAL (op1) >= 16*1024*1024)
9744 if (!x86_64_immediate_operand (op1, Pmode))
9745 op1 = force_reg (Pmode, op1);
9746 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9752 base = legitimize_pic_address (XEXP (addr, 0), reg);
9753 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9754 base == reg ? NULL_RTX : reg);
9756 if (CONST_INT_P (new_rtx))
9757 new_rtx = plus_constant (base, INTVAL (new_rtx));
9760 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9762 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9763 new_rtx = XEXP (new_rtx, 1);
9765 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9773 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9776 get_thread_pointer (int to_reg)
9780 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9784 reg = gen_reg_rtx (Pmode);
9785 insn = gen_rtx_SET (VOIDmode, reg, tp);
9786 insn = emit_insn (insn);
9791 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
9792 false if we expect this to be used for a memory address and true if
9793 we expect to load the address into a register. */
9796 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9798 rtx dest, base, off, pic, tp;
9803 case TLS_MODEL_GLOBAL_DYNAMIC:
9804 dest = gen_reg_rtx (Pmode);
9805 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9807 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9809 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9812 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9813 insns = get_insns ();
9816 RTL_CONST_CALL_P (insns) = 1;
9817 emit_libcall_block (insns, dest, rax, x);
9819 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9820 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9822 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9824 if (TARGET_GNU2_TLS)
9826 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9828 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9832 case TLS_MODEL_LOCAL_DYNAMIC:
9833 base = gen_reg_rtx (Pmode);
9834 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9836 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9838 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9841 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9842 insns = get_insns ();
9845 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9846 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9847 RTL_CONST_CALL_P (insns) = 1;
9848 emit_libcall_block (insns, base, rax, note);
9850 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9851 emit_insn (gen_tls_local_dynamic_base_64 (base));
9853 emit_insn (gen_tls_local_dynamic_base_32 (base));
9855 if (TARGET_GNU2_TLS)
9857 rtx x = ix86_tls_module_base ();
9859 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9860 gen_rtx_MINUS (Pmode, x, tp));
9863 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9864 off = gen_rtx_CONST (Pmode, off);
9866 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9868 if (TARGET_GNU2_TLS)
9870 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9872 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9877 case TLS_MODEL_INITIAL_EXEC:
9881 type = UNSPEC_GOTNTPOFF;
9885 if (reload_in_progress)
9886 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9887 pic = pic_offset_table_rtx;
9888 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9890 else if (!TARGET_ANY_GNU_TLS)
9892 pic = gen_reg_rtx (Pmode);
9893 emit_insn (gen_set_got (pic));
9894 type = UNSPEC_GOTTPOFF;
9899 type = UNSPEC_INDNTPOFF;
9902 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9903 off = gen_rtx_CONST (Pmode, off);
9905 off = gen_rtx_PLUS (Pmode, pic, off);
9906 off = gen_const_mem (Pmode, off);
9907 set_mem_alias_set (off, ix86_GOT_alias_set ());
9909 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9911 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9912 off = force_reg (Pmode, off);
9913 return gen_rtx_PLUS (Pmode, base, off);
9917 base = get_thread_pointer (true);
9918 dest = gen_reg_rtx (Pmode);
9919 emit_insn (gen_subsi3 (dest, base, off));
9923 case TLS_MODEL_LOCAL_EXEC:
9924 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9925 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9926 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9927 off = gen_rtx_CONST (Pmode, off);
9929 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9931 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9932 return gen_rtx_PLUS (Pmode, base, off);
9936 base = get_thread_pointer (true);
9937 dest = gen_reg_rtx (Pmode);
9938 emit_insn (gen_subsi3 (dest, base, off));
9949 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9952 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9953 htab_t dllimport_map;
9956 get_dllimport_decl (tree decl)
9958 struct tree_map *h, in;
9962 size_t namelen, prefixlen;
9968 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9970 in.hash = htab_hash_pointer (decl);
9971 in.base.from = decl;
9972 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9973 h = (struct tree_map *) *loc;
9977 *loc = h = GGC_NEW (struct tree_map);
9979 h->base.from = decl;
9980 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9981 DECL_ARTIFICIAL (to) = 1;
9982 DECL_IGNORED_P (to) = 1;
9983 DECL_EXTERNAL (to) = 1;
9984 TREE_READONLY (to) = 1;
9986 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9987 name = targetm.strip_name_encoding (name);
9988 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9989 ? "*__imp_" : "*__imp__";
9990 namelen = strlen (name);
9991 prefixlen = strlen (prefix);
9992 imp_name = (char *) alloca (namelen + prefixlen + 1);
9993 memcpy (imp_name, prefix, prefixlen);
9994 memcpy (imp_name + prefixlen, name, namelen + 1);
9996 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9997 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9998 SET_SYMBOL_REF_DECL (rtl, to);
9999 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10001 rtl = gen_const_mem (Pmode, rtl);
10002 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10004 SET_DECL_RTL (to, rtl);
10005 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10010 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10011 true if we require the result be a register. */
10014 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10019 gcc_assert (SYMBOL_REF_DECL (symbol));
10020 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10022 x = DECL_RTL (imp_decl);
10024 x = force_reg (Pmode, x);
10028 /* Try machine-dependent ways of modifying an illegitimate address
10029 to be legitimate. If we find one, return the new, valid address.
10030 This macro is used in only one place: `memory_address' in explow.c.
10032 OLDX is the address as it was before break_out_memory_refs was called.
10033 In some cases it is useful to look at this to decide what needs to be done.
10035 It is always safe for this macro to do nothing. It exists to recognize
10036 opportunities to optimize the output.
10038 For the 80386, we handle X+REG by loading X into a register R and
10039 using R+REG. R will go in a general reg and indexing will be used.
10040 However, if REG is a broken-out memory address or multiplication,
10041 nothing needs to be done because REG can certainly go in a general reg.
10043 When -fpic is used, special handling is needed for symbolic references.
10044 See comments by legitimize_pic_address in i386.c for details. */
10047 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10048 enum machine_mode mode)
10053 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10055 return legitimize_tls_address (x, (enum tls_model) log, false);
10056 if (GET_CODE (x) == CONST
10057 && GET_CODE (XEXP (x, 0)) == PLUS
10058 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10059 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10061 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10062 (enum tls_model) log, false);
10063 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10066 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10068 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10069 return legitimize_dllimport_symbol (x, true);
10070 if (GET_CODE (x) == CONST
10071 && GET_CODE (XEXP (x, 0)) == PLUS
10072 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10073 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10075 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10076 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10080 if (flag_pic && SYMBOLIC_CONST (x))
10081 return legitimize_pic_address (x, 0);
10083 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10084 if (GET_CODE (x) == ASHIFT
10085 && CONST_INT_P (XEXP (x, 1))
10086 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10089 log = INTVAL (XEXP (x, 1));
10090 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10091 GEN_INT (1 << log));
10094 if (GET_CODE (x) == PLUS)
10096 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10098 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10099 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10100 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10103 log = INTVAL (XEXP (XEXP (x, 0), 1));
10104 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10105 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10106 GEN_INT (1 << log));
10109 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10110 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10111 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10114 log = INTVAL (XEXP (XEXP (x, 1), 1));
10115 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10116 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10117 GEN_INT (1 << log));
10120 /* Put multiply first if it isn't already. */
10121 if (GET_CODE (XEXP (x, 1)) == MULT)
10123 rtx tmp = XEXP (x, 0);
10124 XEXP (x, 0) = XEXP (x, 1);
10129 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10130 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10131 created by virtual register instantiation, register elimination, and
10132 similar optimizations. */
10133 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10136 x = gen_rtx_PLUS (Pmode,
10137 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10138 XEXP (XEXP (x, 1), 0)),
10139 XEXP (XEXP (x, 1), 1));
10143 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10144 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10145 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10146 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10147 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10148 && CONSTANT_P (XEXP (x, 1)))
10151 rtx other = NULL_RTX;
10153 if (CONST_INT_P (XEXP (x, 1)))
10155 constant = XEXP (x, 1);
10156 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10158 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10160 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10161 other = XEXP (x, 1);
10169 x = gen_rtx_PLUS (Pmode,
10170 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10171 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10172 plus_constant (other, INTVAL (constant)));
10176 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10179 if (GET_CODE (XEXP (x, 0)) == MULT)
10182 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10185 if (GET_CODE (XEXP (x, 1)) == MULT)
10188 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10192 && REG_P (XEXP (x, 1))
10193 && REG_P (XEXP (x, 0)))
10196 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10199 x = legitimize_pic_address (x, 0);
10202 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10205 if (REG_P (XEXP (x, 0)))
10207 rtx temp = gen_reg_rtx (Pmode);
10208 rtx val = force_operand (XEXP (x, 1), temp);
10210 emit_move_insn (temp, val);
10212 XEXP (x, 1) = temp;
10216 else if (REG_P (XEXP (x, 1)))
10218 rtx temp = gen_reg_rtx (Pmode);
10219 rtx val = force_operand (XEXP (x, 0), temp);
10221 emit_move_insn (temp, val);
10223 XEXP (x, 0) = temp;
10231 /* Print an integer constant expression in assembler syntax. Addition
10232 and subtraction are the only arithmetic that may appear in these
10233 expressions. FILE is the stdio stream to write to, X is the rtx, and
10234 CODE is the operand print code from the output string. */
10237 output_pic_addr_const (FILE *file, rtx x, int code)
10241 switch (GET_CODE (x))
10244 gcc_assert (flag_pic);
10249 if (! TARGET_MACHO || TARGET_64BIT)
10250 output_addr_const (file, x);
10253 const char *name = XSTR (x, 0);
10255 /* Mark the decl as referenced so that cgraph will
10256 output the function. */
10257 if (SYMBOL_REF_DECL (x))
10258 mark_decl_referenced (SYMBOL_REF_DECL (x));
10261 if (MACHOPIC_INDIRECT
10262 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10263 name = machopic_indirection_name (x, /*stub_p=*/true);
10265 assemble_name (file, name);
10267 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10268 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10269 fputs ("@PLT", file);
10276 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10277 assemble_name (asm_out_file, buf);
10281 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10285 /* This used to output parentheses around the expression,
10286 but that does not work on the 386 (either ATT or BSD assembler). */
10287 output_pic_addr_const (file, XEXP (x, 0), code);
10291 if (GET_MODE (x) == VOIDmode)
10293 /* We can use %d if the number is <32 bits and positive. */
10294 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10295 fprintf (file, "0x%lx%08lx",
10296 (unsigned long) CONST_DOUBLE_HIGH (x),
10297 (unsigned long) CONST_DOUBLE_LOW (x));
10299 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10302 /* We can't handle floating point constants;
10303 PRINT_OPERAND must handle them. */
10304 output_operand_lossage ("floating constant misused");
10308 /* Some assemblers need integer constants to appear first. */
10309 if (CONST_INT_P (XEXP (x, 0)))
10311 output_pic_addr_const (file, XEXP (x, 0), code);
10313 output_pic_addr_const (file, XEXP (x, 1), code);
10317 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10318 output_pic_addr_const (file, XEXP (x, 1), code);
10320 output_pic_addr_const (file, XEXP (x, 0), code);
10326 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10327 output_pic_addr_const (file, XEXP (x, 0), code);
10329 output_pic_addr_const (file, XEXP (x, 1), code);
10331 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10335 gcc_assert (XVECLEN (x, 0) == 1);
10336 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10337 switch (XINT (x, 1))
10340 fputs ("@GOT", file);
10342 case UNSPEC_GOTOFF:
10343 fputs ("@GOTOFF", file);
10345 case UNSPEC_PLTOFF:
10346 fputs ("@PLTOFF", file);
10348 case UNSPEC_GOTPCREL:
10349 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10350 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10352 case UNSPEC_GOTTPOFF:
10353 /* FIXME: This might be @TPOFF in Sun ld too. */
10354 fputs ("@GOTTPOFF", file);
10357 fputs ("@TPOFF", file);
10359 case UNSPEC_NTPOFF:
10361 fputs ("@TPOFF", file);
10363 fputs ("@NTPOFF", file);
10365 case UNSPEC_DTPOFF:
10366 fputs ("@DTPOFF", file);
10368 case UNSPEC_GOTNTPOFF:
10370 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10371 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10373 fputs ("@GOTNTPOFF", file);
10375 case UNSPEC_INDNTPOFF:
10376 fputs ("@INDNTPOFF", file);
10379 case UNSPEC_MACHOPIC_OFFSET:
10381 machopic_output_function_base_name (file);
10385 output_operand_lossage ("invalid UNSPEC as operand");
10391 output_operand_lossage ("invalid expression as operand");
10395 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10396 We need to emit DTP-relative relocations. */
10398 static void ATTRIBUTE_UNUSED
10399 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10401 fputs (ASM_LONG, file);
10402 output_addr_const (file, x);
10403 fputs ("@DTPOFF", file);
10409 fputs (", 0", file);
10412 gcc_unreachable ();
10416 /* Return true if X is a representation of the PIC register. This copes
10417 with calls from ix86_find_base_term, where the register might have
10418 been replaced by a cselib value. */
10421 ix86_pic_register_p (rtx x)
10423 if (GET_CODE (x) == VALUE)
10424 return (pic_offset_table_rtx
10425 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10427 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10430 /* In the name of slightly smaller debug output, and to cater to
10431 general assembler lossage, recognize PIC+GOTOFF and turn it back
10432 into a direct symbol reference.
10434 On Darwin, this is necessary to avoid a crash, because Darwin
10435 has a different PIC label for each routine but the DWARF debugging
10436 information is not associated with any particular routine, so it's
10437 necessary to remove references to the PIC label from RTL stored by
10438 the DWARF output code. */
10441 ix86_delegitimize_address (rtx orig_x)
10444 /* reg_addend is NULL or a multiple of some register. */
10445 rtx reg_addend = NULL_RTX;
10446 /* const_addend is NULL or a const_int. */
10447 rtx const_addend = NULL_RTX;
10448 /* This is the result, or NULL. */
10449 rtx result = NULL_RTX;
10456 if (GET_CODE (x) != CONST
10457 || GET_CODE (XEXP (x, 0)) != UNSPEC
10458 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10459 || !MEM_P (orig_x))
10461 return XVECEXP (XEXP (x, 0), 0, 0);
10464 if (GET_CODE (x) != PLUS
10465 || GET_CODE (XEXP (x, 1)) != CONST)
10468 if (ix86_pic_register_p (XEXP (x, 0)))
10469 /* %ebx + GOT/GOTOFF */
10471 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10473 /* %ebx + %reg * scale + GOT/GOTOFF */
10474 reg_addend = XEXP (x, 0);
10475 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10476 reg_addend = XEXP (reg_addend, 1);
10477 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10478 reg_addend = XEXP (reg_addend, 0);
10481 if (!REG_P (reg_addend)
10482 && GET_CODE (reg_addend) != MULT
10483 && GET_CODE (reg_addend) != ASHIFT)
10489 x = XEXP (XEXP (x, 1), 0);
10490 if (GET_CODE (x) == PLUS
10491 && CONST_INT_P (XEXP (x, 1)))
10493 const_addend = XEXP (x, 1);
10497 if (GET_CODE (x) == UNSPEC
10498 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10499 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10500 result = XVECEXP (x, 0, 0);
10502 if (TARGET_MACHO && darwin_local_data_pic (x)
10503 && !MEM_P (orig_x))
10504 result = XVECEXP (x, 0, 0);
10510 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10512 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10516 /* If X is a machine specific address (i.e. a symbol or label being
10517 referenced as a displacement from the GOT implemented using an
10518 UNSPEC), then return the base term. Otherwise return X. */
10521 ix86_find_base_term (rtx x)
10527 if (GET_CODE (x) != CONST)
10529 term = XEXP (x, 0);
10530 if (GET_CODE (term) == PLUS
10531 && (CONST_INT_P (XEXP (term, 1))
10532 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10533 term = XEXP (term, 0);
10534 if (GET_CODE (term) != UNSPEC
10535 || XINT (term, 1) != UNSPEC_GOTPCREL)
10538 return XVECEXP (term, 0, 0);
10541 return ix86_delegitimize_address (x);
10545 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10546 int fp, FILE *file)
10548 const char *suffix;
10550 if (mode == CCFPmode || mode == CCFPUmode)
10552 enum rtx_code second_code, bypass_code;
10553 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10554 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10555 code = ix86_fp_compare_code_to_integer (code);
10559 code = reverse_condition (code);
10610 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10614 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10615 Those same assemblers have the same but opposite lossage on cmov. */
10616 if (mode == CCmode)
10617 suffix = fp ? "nbe" : "a";
10618 else if (mode == CCCmode)
10621 gcc_unreachable ();
10637 gcc_unreachable ();
10641 gcc_assert (mode == CCmode || mode == CCCmode);
10658 gcc_unreachable ();
10662 /* ??? As above. */
10663 gcc_assert (mode == CCmode || mode == CCCmode);
10664 suffix = fp ? "nb" : "ae";
10667 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10671 /* ??? As above. */
10672 if (mode == CCmode)
10674 else if (mode == CCCmode)
10675 suffix = fp ? "nb" : "ae";
10677 gcc_unreachable ();
10680 suffix = fp ? "u" : "p";
10683 suffix = fp ? "nu" : "np";
10686 gcc_unreachable ();
10688 fputs (suffix, file);
10691 /* Print the name of register X to FILE based on its machine mode and number.
10692 If CODE is 'w', pretend the mode is HImode.
10693 If CODE is 'b', pretend the mode is QImode.
10694 If CODE is 'k', pretend the mode is SImode.
10695 If CODE is 'q', pretend the mode is DImode.
10696 If CODE is 'x', pretend the mode is V4SFmode.
10697 If CODE is 't', pretend the mode is V8SFmode.
10698 If CODE is 'h', pretend the reg is the 'high' byte register.
10699 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10700 If CODE is 'd', duplicate the operand for AVX instruction.
10704 print_reg (rtx x, int code, FILE *file)
10707 bool duplicated = code == 'd' && TARGET_AVX;
10709 gcc_assert (x == pc_rtx
10710 || (REGNO (x) != ARG_POINTER_REGNUM
10711 && REGNO (x) != FRAME_POINTER_REGNUM
10712 && REGNO (x) != FLAGS_REG
10713 && REGNO (x) != FPSR_REG
10714 && REGNO (x) != FPCR_REG));
10716 if (ASSEMBLER_DIALECT == ASM_ATT)
10721 gcc_assert (TARGET_64BIT);
10722 fputs ("rip", file);
10726 if (code == 'w' || MMX_REG_P (x))
10728 else if (code == 'b')
10730 else if (code == 'k')
10732 else if (code == 'q')
10734 else if (code == 'y')
10736 else if (code == 'h')
10738 else if (code == 'x')
10740 else if (code == 't')
10743 code = GET_MODE_SIZE (GET_MODE (x));
10745 /* Irritatingly, AMD extended registers use different naming convention
10746 from the normal registers. */
10747 if (REX_INT_REG_P (x))
10749 gcc_assert (TARGET_64BIT);
10753 error ("extended registers have no high halves");
10756 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10759 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10762 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10765 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10768 error ("unsupported operand size for extended register");
10778 if (STACK_TOP_P (x))
10787 if (! ANY_FP_REG_P (x))
10788 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10793 reg = hi_reg_name[REGNO (x)];
10796 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10798 reg = qi_reg_name[REGNO (x)];
10801 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10803 reg = qi_high_reg_name[REGNO (x)];
10808 gcc_assert (!duplicated);
10810 fputs (hi_reg_name[REGNO (x)] + 1, file);
10815 gcc_unreachable ();
10821 if (ASSEMBLER_DIALECT == ASM_ATT)
10822 fprintf (file, ", %%%s", reg);
10824 fprintf (file, ", %s", reg);
10828 /* Locate some local-dynamic symbol still in use by this function
10829 so that we can print its name in some tls_local_dynamic_base
10833 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10837 if (GET_CODE (x) == SYMBOL_REF
10838 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10840 cfun->machine->some_ld_name = XSTR (x, 0);
10847 static const char *
10848 get_some_local_dynamic_name (void)
10852 if (cfun->machine->some_ld_name)
10853 return cfun->machine->some_ld_name;
10855 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10857 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10858 return cfun->machine->some_ld_name;
10860 gcc_unreachable ();
10863 /* Meaning of CODE:
10864 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10865 C -- print opcode suffix for set/cmov insn.
10866 c -- like C, but print reversed condition
10867 E,e -- likewise, but for compare-and-branch fused insn.
10868 F,f -- likewise, but for floating-point.
10869 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10871 R -- print the prefix for register names.
10872 z -- print the opcode suffix for the size of the current operand.
10873 Z -- likewise, with special suffixes for x87 instructions.
10874 * -- print a star (in certain assembler syntax)
10875 A -- print an absolute memory reference.
10876 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10877 s -- print a shift double count, followed by the assemblers argument
10879 b -- print the QImode name of the register for the indicated operand.
10880 %b0 would print %al if operands[0] is reg 0.
10881 w -- likewise, print the HImode name of the register.
10882 k -- likewise, print the SImode name of the register.
10883 q -- likewise, print the DImode name of the register.
10884 x -- likewise, print the V4SFmode name of the register.
10885 t -- likewise, print the V8SFmode name of the register.
10886 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10887 y -- print "st(0)" instead of "st" as a register.
10888 d -- print duplicated register operand for AVX instruction.
10889 D -- print condition for SSE cmp instruction.
10890 P -- if PIC, print an @PLT suffix.
10891 X -- don't print any sort of PIC '@' suffix for a symbol.
10892 & -- print some in-use local-dynamic symbol name.
10893 H -- print a memory address offset by 8; used for sse high-parts
10894 Y -- print condition for SSE5 com* instruction.
10895 + -- print a branch hint as 'cs' or 'ds' prefix
10896 ; -- print a semicolon (after prefixes due to bug in older gas).
10900 print_operand (FILE *file, rtx x, int code)
10907 if (ASSEMBLER_DIALECT == ASM_ATT)
10912 assemble_name (file, get_some_local_dynamic_name ());
10916 switch (ASSEMBLER_DIALECT)
10923 /* Intel syntax. For absolute addresses, registers should not
10924 be surrounded by braces. */
10928 PRINT_OPERAND (file, x, 0);
10935 gcc_unreachable ();
10938 PRINT_OPERAND (file, x, 0);
10943 if (ASSEMBLER_DIALECT == ASM_ATT)
10948 if (ASSEMBLER_DIALECT == ASM_ATT)
10953 if (ASSEMBLER_DIALECT == ASM_ATT)
10958 if (ASSEMBLER_DIALECT == ASM_ATT)
10963 if (ASSEMBLER_DIALECT == ASM_ATT)
10968 if (ASSEMBLER_DIALECT == ASM_ATT)
10973 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10975 /* Opcodes don't get size suffixes if using Intel opcodes. */
10976 if (ASSEMBLER_DIALECT == ASM_INTEL)
10979 switch (GET_MODE_SIZE (GET_MODE (x)))
10998 output_operand_lossage
10999 ("invalid operand size for operand code '%c'", code);
11004 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11006 (0, "non-integer operand used with operand code '%c'", code);
11010 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11011 if (ASSEMBLER_DIALECT == ASM_INTEL)
11014 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11016 switch (GET_MODE_SIZE (GET_MODE (x)))
11019 #ifdef HAVE_AS_IX86_FILDS
11029 #ifdef HAVE_AS_IX86_FILDQ
11032 fputs ("ll", file);
11040 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11042 /* 387 opcodes don't get size suffixes
11043 if the operands are registers. */
11044 if (STACK_REG_P (x))
11047 switch (GET_MODE_SIZE (GET_MODE (x)))
11068 output_operand_lossage
11069 ("invalid operand type used with operand code '%c'", code);
11073 output_operand_lossage
11074 ("invalid operand size for operand code '%c'", code);
11091 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11093 PRINT_OPERAND (file, x, 0);
11094 fputs (", ", file);
11099 /* Little bit of braindamage here. The SSE compare instructions
11100 does use completely different names for the comparisons that the
11101 fp conditional moves. */
11104 switch (GET_CODE (x))
11107 fputs ("eq", file);
11110 fputs ("eq_us", file);
11113 fputs ("lt", file);
11116 fputs ("nge", file);
11119 fputs ("le", file);
11122 fputs ("ngt", file);
11125 fputs ("unord", file);
11128 fputs ("neq", file);
11131 fputs ("neq_oq", file);
11134 fputs ("ge", file);
11137 fputs ("nlt", file);
11140 fputs ("gt", file);
11143 fputs ("nle", file);
11146 fputs ("ord", file);
11149 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11155 switch (GET_CODE (x))
11159 fputs ("eq", file);
11163 fputs ("lt", file);
11167 fputs ("le", file);
11170 fputs ("unord", file);
11174 fputs ("neq", file);
11178 fputs ("nlt", file);
11182 fputs ("nle", file);
11185 fputs ("ord", file);
11188 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11194 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11195 if (ASSEMBLER_DIALECT == ASM_ATT)
11197 switch (GET_MODE (x))
11199 case HImode: putc ('w', file); break;
11201 case SFmode: putc ('l', file); break;
11203 case DFmode: putc ('q', file); break;
11204 default: gcc_unreachable ();
11211 if (!COMPARISON_P (x))
11213 output_operand_lossage ("operand is neither a constant nor a "
11214 "condition code, invalid operand code "
11218 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11221 if (!COMPARISON_P (x))
11223 output_operand_lossage ("operand is neither a constant nor a "
11224 "condition code, invalid operand code "
11228 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11229 if (ASSEMBLER_DIALECT == ASM_ATT)
11232 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11235 /* Like above, but reverse condition */
11237 /* Check to see if argument to %c is really a constant
11238 and not a condition code which needs to be reversed. */
11239 if (!COMPARISON_P (x))
11241 output_operand_lossage ("operand is neither a constant nor a "
11242 "condition code, invalid operand "
11246 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11249 if (!COMPARISON_P (x))
11251 output_operand_lossage ("operand is neither a constant nor a "
11252 "condition code, invalid operand "
11256 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11257 if (ASSEMBLER_DIALECT == ASM_ATT)
11260 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11264 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11268 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11272 /* It doesn't actually matter what mode we use here, as we're
11273 only going to use this for printing. */
11274 x = adjust_address_nv (x, DImode, 8);
11282 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11285 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11288 int pred_val = INTVAL (XEXP (x, 0));
11290 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11291 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11293 int taken = pred_val > REG_BR_PROB_BASE / 2;
11294 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11296 /* Emit hints only in the case default branch prediction
11297 heuristics would fail. */
11298 if (taken != cputaken)
11300 /* We use 3e (DS) prefix for taken branches and
11301 2e (CS) prefix for not taken branches. */
11303 fputs ("ds ; ", file);
11305 fputs ("cs ; ", file);
11313 switch (GET_CODE (x))
11316 fputs ("neq", file);
11319 fputs ("eq", file);
11323 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11327 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11331 fputs ("le", file);
11335 fputs ("lt", file);
11338 fputs ("unord", file);
11341 fputs ("ord", file);
11344 fputs ("ueq", file);
11347 fputs ("nlt", file);
11350 fputs ("nle", file);
11353 fputs ("ule", file);
11356 fputs ("ult", file);
11359 fputs ("une", file);
11362 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11369 fputs (" ; ", file);
11376 output_operand_lossage ("invalid operand code '%c'", code);
11381 print_reg (x, code, file);
11383 else if (MEM_P (x))
11385 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11386 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11387 && GET_MODE (x) != BLKmode)
11390 switch (GET_MODE_SIZE (GET_MODE (x)))
11392 case 1: size = "BYTE"; break;
11393 case 2: size = "WORD"; break;
11394 case 4: size = "DWORD"; break;
11395 case 8: size = "QWORD"; break;
11396 case 12: size = "XWORD"; break;
11398 if (GET_MODE (x) == XFmode)
11404 gcc_unreachable ();
11407 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11410 else if (code == 'w')
11412 else if (code == 'k')
11415 fputs (size, file);
11416 fputs (" PTR ", file);
11420 /* Avoid (%rip) for call operands. */
11421 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11422 && !CONST_INT_P (x))
11423 output_addr_const (file, x);
11424 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11425 output_operand_lossage ("invalid constraints for operand");
11427 output_address (x);
11430 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11435 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11436 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11438 if (ASSEMBLER_DIALECT == ASM_ATT)
11440 fprintf (file, "0x%08lx", (long unsigned int) l);
11443 /* These float cases don't actually occur as immediate operands. */
11444 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11448 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11449 fprintf (file, "%s", dstr);
11452 else if (GET_CODE (x) == CONST_DOUBLE
11453 && GET_MODE (x) == XFmode)
11457 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11458 fprintf (file, "%s", dstr);
11463 /* We have patterns that allow zero sets of memory, for instance.
11464 In 64-bit mode, we should probably support all 8-byte vectors,
11465 since we can in fact encode that into an immediate. */
11466 if (GET_CODE (x) == CONST_VECTOR)
11468 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11474 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11476 if (ASSEMBLER_DIALECT == ASM_ATT)
11479 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11480 || GET_CODE (x) == LABEL_REF)
11482 if (ASSEMBLER_DIALECT == ASM_ATT)
11485 fputs ("OFFSET FLAT:", file);
11488 if (CONST_INT_P (x))
11489 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11491 output_pic_addr_const (file, x, code);
11493 output_addr_const (file, x);
11497 /* Print a memory operand whose address is ADDR. */
11500 print_operand_address (FILE *file, rtx addr)
11502 struct ix86_address parts;
11503 rtx base, index, disp;
11505 int ok = ix86_decompose_address (addr, &parts);
11510 index = parts.index;
11512 scale = parts.scale;
11520 if (ASSEMBLER_DIALECT == ASM_ATT)
11522 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11525 gcc_unreachable ();
11528 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11529 if (TARGET_64BIT && !base && !index)
11533 if (GET_CODE (disp) == CONST
11534 && GET_CODE (XEXP (disp, 0)) == PLUS
11535 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11536 symbol = XEXP (XEXP (disp, 0), 0);
11538 if (GET_CODE (symbol) == LABEL_REF
11539 || (GET_CODE (symbol) == SYMBOL_REF
11540 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11543 if (!base && !index)
11545 /* Displacement only requires special attention. */
11547 if (CONST_INT_P (disp))
11549 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11550 fputs ("ds:", file);
11551 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11554 output_pic_addr_const (file, disp, 0);
11556 output_addr_const (file, disp);
11560 if (ASSEMBLER_DIALECT == ASM_ATT)
11565 output_pic_addr_const (file, disp, 0);
11566 else if (GET_CODE (disp) == LABEL_REF)
11567 output_asm_label (disp);
11569 output_addr_const (file, disp);
11574 print_reg (base, 0, file);
11578 print_reg (index, 0, file);
11580 fprintf (file, ",%d", scale);
11586 rtx offset = NULL_RTX;
11590 /* Pull out the offset of a symbol; print any symbol itself. */
11591 if (GET_CODE (disp) == CONST
11592 && GET_CODE (XEXP (disp, 0)) == PLUS
11593 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11595 offset = XEXP (XEXP (disp, 0), 1);
11596 disp = gen_rtx_CONST (VOIDmode,
11597 XEXP (XEXP (disp, 0), 0));
11601 output_pic_addr_const (file, disp, 0);
11602 else if (GET_CODE (disp) == LABEL_REF)
11603 output_asm_label (disp);
11604 else if (CONST_INT_P (disp))
11607 output_addr_const (file, disp);
11613 print_reg (base, 0, file);
11616 if (INTVAL (offset) >= 0)
11618 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11622 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11629 print_reg (index, 0, file);
11631 fprintf (file, "*%d", scale);
11639 output_addr_const_extra (FILE *file, rtx x)
11643 if (GET_CODE (x) != UNSPEC)
11646 op = XVECEXP (x, 0, 0);
11647 switch (XINT (x, 1))
11649 case UNSPEC_GOTTPOFF:
11650 output_addr_const (file, op);
11651 /* FIXME: This might be @TPOFF in Sun ld. */
11652 fputs ("@GOTTPOFF", file);
11655 output_addr_const (file, op);
11656 fputs ("@TPOFF", file);
11658 case UNSPEC_NTPOFF:
11659 output_addr_const (file, op);
11661 fputs ("@TPOFF", file);
11663 fputs ("@NTPOFF", file);
11665 case UNSPEC_DTPOFF:
11666 output_addr_const (file, op);
11667 fputs ("@DTPOFF", file);
11669 case UNSPEC_GOTNTPOFF:
11670 output_addr_const (file, op);
11672 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11673 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11675 fputs ("@GOTNTPOFF", file);
11677 case UNSPEC_INDNTPOFF:
11678 output_addr_const (file, op);
11679 fputs ("@INDNTPOFF", file);
11682 case UNSPEC_MACHOPIC_OFFSET:
11683 output_addr_const (file, op);
11685 machopic_output_function_base_name (file);
11696 /* Split one or more DImode RTL references into pairs of SImode
11697 references. The RTL can be REG, offsettable MEM, integer constant, or
11698 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11699 split and "num" is its length. lo_half and hi_half are output arrays
11700 that parallel "operands". */
11703 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11707 rtx op = operands[num];
11709 /* simplify_subreg refuse to split volatile memory addresses,
11710 but we still have to handle it. */
11713 lo_half[num] = adjust_address (op, SImode, 0);
11714 hi_half[num] = adjust_address (op, SImode, 4);
11718 lo_half[num] = simplify_gen_subreg (SImode, op,
11719 GET_MODE (op) == VOIDmode
11720 ? DImode : GET_MODE (op), 0);
11721 hi_half[num] = simplify_gen_subreg (SImode, op,
11722 GET_MODE (op) == VOIDmode
11723 ? DImode : GET_MODE (op), 4);
11727 /* Split one or more TImode RTL references into pairs of DImode
11728 references. The RTL can be REG, offsettable MEM, integer constant, or
11729 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11730 split and "num" is its length. lo_half and hi_half are output arrays
11731 that parallel "operands". */
11734 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11738 rtx op = operands[num];
11740 /* simplify_subreg refuse to split volatile memory addresses, but we
11741 still have to handle it. */
11744 lo_half[num] = adjust_address (op, DImode, 0);
11745 hi_half[num] = adjust_address (op, DImode, 8);
11749 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11750 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11755 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11756 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11757 is the expression of the binary operation. The output may either be
11758 emitted here, or returned to the caller, like all output_* functions.
11760 There is no guarantee that the operands are the same mode, as they
11761 might be within FLOAT or FLOAT_EXTEND expressions. */
11763 #ifndef SYSV386_COMPAT
11764 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11765 wants to fix the assemblers because that causes incompatibility
11766 with gcc. No-one wants to fix gcc because that causes
11767 incompatibility with assemblers... You can use the option of
11768 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11769 #define SYSV386_COMPAT 1
11773 output_387_binary_op (rtx insn, rtx *operands)
11775 static char buf[40];
11778 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11780 #ifdef ENABLE_CHECKING
11781 /* Even if we do not want to check the inputs, this documents input
11782 constraints. Which helps in understanding the following code. */
11783 if (STACK_REG_P (operands[0])
11784 && ((REG_P (operands[1])
11785 && REGNO (operands[0]) == REGNO (operands[1])
11786 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11787 || (REG_P (operands[2])
11788 && REGNO (operands[0]) == REGNO (operands[2])
11789 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11790 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11793 gcc_assert (is_sse);
11796 switch (GET_CODE (operands[3]))
11799 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11800 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11808 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11809 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11817 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11818 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11826 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11827 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11835 gcc_unreachable ();
11842 strcpy (buf, ssep);
11843 if (GET_MODE (operands[0]) == SFmode)
11844 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11846 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11850 strcpy (buf, ssep + 1);
11851 if (GET_MODE (operands[0]) == SFmode)
11852 strcat (buf, "ss\t{%2, %0|%0, %2}");
11854 strcat (buf, "sd\t{%2, %0|%0, %2}");
11860 switch (GET_CODE (operands[3]))
11864 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11866 rtx temp = operands[2];
11867 operands[2] = operands[1];
11868 operands[1] = temp;
11871 /* know operands[0] == operands[1]. */
11873 if (MEM_P (operands[2]))
11879 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11881 if (STACK_TOP_P (operands[0]))
11882 /* How is it that we are storing to a dead operand[2]?
11883 Well, presumably operands[1] is dead too. We can't
11884 store the result to st(0) as st(0) gets popped on this
11885 instruction. Instead store to operands[2] (which I
11886 think has to be st(1)). st(1) will be popped later.
11887 gcc <= 2.8.1 didn't have this check and generated
11888 assembly code that the Unixware assembler rejected. */
11889 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11891 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11895 if (STACK_TOP_P (operands[0]))
11896 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11898 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11903 if (MEM_P (operands[1]))
11909 if (MEM_P (operands[2]))
11915 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11918 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11919 derived assemblers, confusingly reverse the direction of
11920 the operation for fsub{r} and fdiv{r} when the
11921 destination register is not st(0). The Intel assembler
11922 doesn't have this brain damage. Read !SYSV386_COMPAT to
11923 figure out what the hardware really does. */
11924 if (STACK_TOP_P (operands[0]))
11925 p = "{p\t%0, %2|rp\t%2, %0}";
11927 p = "{rp\t%2, %0|p\t%0, %2}";
11929 if (STACK_TOP_P (operands[0]))
11930 /* As above for fmul/fadd, we can't store to st(0). */
11931 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11933 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11938 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11941 if (STACK_TOP_P (operands[0]))
11942 p = "{rp\t%0, %1|p\t%1, %0}";
11944 p = "{p\t%1, %0|rp\t%0, %1}";
11946 if (STACK_TOP_P (operands[0]))
11947 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11949 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11954 if (STACK_TOP_P (operands[0]))
11956 if (STACK_TOP_P (operands[1]))
11957 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11959 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11962 else if (STACK_TOP_P (operands[1]))
11965 p = "{\t%1, %0|r\t%0, %1}";
11967 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11973 p = "{r\t%2, %0|\t%0, %2}";
11975 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11981 gcc_unreachable ();
11988 /* Return needed mode for entity in optimize_mode_switching pass. */
11991 ix86_mode_needed (int entity, rtx insn)
11993 enum attr_i387_cw mode;
11995 /* The mode UNINITIALIZED is used to store control word after a
11996 function call or ASM pattern. The mode ANY specify that function
11997 has no requirements on the control word and make no changes in the
11998 bits we are interested in. */
12001 || (NONJUMP_INSN_P (insn)
12002 && (asm_noperands (PATTERN (insn)) >= 0
12003 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12004 return I387_CW_UNINITIALIZED;
12006 if (recog_memoized (insn) < 0)
12007 return I387_CW_ANY;
12009 mode = get_attr_i387_cw (insn);
12014 if (mode == I387_CW_TRUNC)
12019 if (mode == I387_CW_FLOOR)
12024 if (mode == I387_CW_CEIL)
12029 if (mode == I387_CW_MASK_PM)
12034 gcc_unreachable ();
12037 return I387_CW_ANY;
12040 /* Output code to initialize control word copies used by trunc?f?i and
12041 rounding patterns. CURRENT_MODE is set to current control word,
12042 while NEW_MODE is set to new control word. */
12045 emit_i387_cw_initialization (int mode)
12047 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12050 enum ix86_stack_slot slot;
12052 rtx reg = gen_reg_rtx (HImode);
12054 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12055 emit_move_insn (reg, copy_rtx (stored_mode));
12057 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12058 || optimize_function_for_size_p (cfun))
12062 case I387_CW_TRUNC:
12063 /* round toward zero (truncate) */
12064 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12065 slot = SLOT_CW_TRUNC;
12068 case I387_CW_FLOOR:
12069 /* round down toward -oo */
12070 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12071 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12072 slot = SLOT_CW_FLOOR;
12076 /* round up toward +oo */
12077 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12078 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12079 slot = SLOT_CW_CEIL;
12082 case I387_CW_MASK_PM:
12083 /* mask precision exception for nearbyint() */
12084 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12085 slot = SLOT_CW_MASK_PM;
12089 gcc_unreachable ();
12096 case I387_CW_TRUNC:
12097 /* round toward zero (truncate) */
12098 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12099 slot = SLOT_CW_TRUNC;
12102 case I387_CW_FLOOR:
12103 /* round down toward -oo */
12104 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12105 slot = SLOT_CW_FLOOR;
12109 /* round up toward +oo */
12110 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12111 slot = SLOT_CW_CEIL;
12114 case I387_CW_MASK_PM:
12115 /* mask precision exception for nearbyint() */
12116 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12117 slot = SLOT_CW_MASK_PM;
12121 gcc_unreachable ();
12125 gcc_assert (slot < MAX_386_STACK_LOCALS);
12127 new_mode = assign_386_stack_local (HImode, slot);
12128 emit_move_insn (new_mode, reg);
12131 /* Output code for INSN to convert a float to a signed int. OPERANDS
12132 are the insn operands. The output may be [HSD]Imode and the input
12133 operand may be [SDX]Fmode. */
12136 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12138 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12139 int dimode_p = GET_MODE (operands[0]) == DImode;
12140 int round_mode = get_attr_i387_cw (insn);
12142 /* Jump through a hoop or two for DImode, since the hardware has no
12143 non-popping instruction. We used to do this a different way, but
12144 that was somewhat fragile and broke with post-reload splitters. */
12145 if ((dimode_p || fisttp) && !stack_top_dies)
12146 output_asm_insn ("fld\t%y1", operands);
12148 gcc_assert (STACK_TOP_P (operands[1]));
12149 gcc_assert (MEM_P (operands[0]));
12150 gcc_assert (GET_MODE (operands[1]) != TFmode);
12153 output_asm_insn ("fisttp%Z0\t%0", operands);
12156 if (round_mode != I387_CW_ANY)
12157 output_asm_insn ("fldcw\t%3", operands);
12158 if (stack_top_dies || dimode_p)
12159 output_asm_insn ("fistp%Z0\t%0", operands);
12161 output_asm_insn ("fist%Z0\t%0", operands);
12162 if (round_mode != I387_CW_ANY)
12163 output_asm_insn ("fldcw\t%2", operands);
12169 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12170 have the values zero or one, indicates the ffreep insn's operand
12171 from the OPERANDS array. */
12173 static const char *
12174 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12176 if (TARGET_USE_FFREEP)
12177 #if HAVE_AS_IX86_FFREEP
12178 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12181 static char retval[] = ".word\t0xc_df";
12182 int regno = REGNO (operands[opno]);
12184 gcc_assert (FP_REGNO_P (regno));
12186 retval[9] = '0' + (regno - FIRST_STACK_REG);
12191 return opno ? "fstp\t%y1" : "fstp\t%y0";
12195 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12196 should be used. UNORDERED_P is true when fucom should be used. */
12199 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12201 int stack_top_dies;
12202 rtx cmp_op0, cmp_op1;
12203 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12207 cmp_op0 = operands[0];
12208 cmp_op1 = operands[1];
12212 cmp_op0 = operands[1];
12213 cmp_op1 = operands[2];
12218 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12219 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12220 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12221 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12223 if (GET_MODE (operands[0]) == SFmode)
12225 return &ucomiss[TARGET_AVX ? 0 : 1];
12227 return &comiss[TARGET_AVX ? 0 : 1];
12230 return &ucomisd[TARGET_AVX ? 0 : 1];
12232 return &comisd[TARGET_AVX ? 0 : 1];
12235 gcc_assert (STACK_TOP_P (cmp_op0));
12237 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12239 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12241 if (stack_top_dies)
12243 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12244 return output_387_ffreep (operands, 1);
12247 return "ftst\n\tfnstsw\t%0";
12250 if (STACK_REG_P (cmp_op1)
12252 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12253 && REGNO (cmp_op1) != FIRST_STACK_REG)
12255 /* If both the top of the 387 stack dies, and the other operand
12256 is also a stack register that dies, then this must be a
12257 `fcompp' float compare */
12261 /* There is no double popping fcomi variant. Fortunately,
12262 eflags is immune from the fstp's cc clobbering. */
12264 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12266 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12267 return output_387_ffreep (operands, 0);
12272 return "fucompp\n\tfnstsw\t%0";
12274 return "fcompp\n\tfnstsw\t%0";
12279 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12281 static const char * const alt[16] =
12283 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12284 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12285 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12286 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12288 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12289 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12293 "fcomi\t{%y1, %0|%0, %y1}",
12294 "fcomip\t{%y1, %0|%0, %y1}",
12295 "fucomi\t{%y1, %0|%0, %y1}",
12296 "fucomip\t{%y1, %0|%0, %y1}",
12307 mask = eflags_p << 3;
12308 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12309 mask |= unordered_p << 1;
12310 mask |= stack_top_dies;
12312 gcc_assert (mask < 16);
12321 ix86_output_addr_vec_elt (FILE *file, int value)
12323 const char *directive = ASM_LONG;
12327 directive = ASM_QUAD;
12329 gcc_assert (!TARGET_64BIT);
12332 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12336 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12338 const char *directive = ASM_LONG;
12341 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12342 directive = ASM_QUAD;
12344 gcc_assert (!TARGET_64BIT);
12346 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12347 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12348 fprintf (file, "%s%s%d-%s%d\n",
12349 directive, LPREFIX, value, LPREFIX, rel);
12350 else if (HAVE_AS_GOTOFF_IN_DATA)
12351 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12353 else if (TARGET_MACHO)
12355 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12356 machopic_output_function_base_name (file);
12357 fprintf(file, "\n");
12361 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12362 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12365 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12369 ix86_expand_clear (rtx dest)
12373 /* We play register width games, which are only valid after reload. */
12374 gcc_assert (reload_completed);
12376 /* Avoid HImode and its attendant prefix byte. */
12377 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12378 dest = gen_rtx_REG (SImode, REGNO (dest));
12379 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12381 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12382 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12384 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12385 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12391 /* X is an unchanging MEM. If it is a constant pool reference, return
12392 the constant pool rtx, else NULL. */
12395 maybe_get_pool_constant (rtx x)
12397 x = ix86_delegitimize_address (XEXP (x, 0));
12399 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12400 return get_pool_constant (x);
12406 ix86_expand_move (enum machine_mode mode, rtx operands[])
12409 enum tls_model model;
12414 if (GET_CODE (op1) == SYMBOL_REF)
12416 model = SYMBOL_REF_TLS_MODEL (op1);
12419 op1 = legitimize_tls_address (op1, model, true);
12420 op1 = force_operand (op1, op0);
12424 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12425 && SYMBOL_REF_DLLIMPORT_P (op1))
12426 op1 = legitimize_dllimport_symbol (op1, false);
12428 else if (GET_CODE (op1) == CONST
12429 && GET_CODE (XEXP (op1, 0)) == PLUS
12430 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12432 rtx addend = XEXP (XEXP (op1, 0), 1);
12433 rtx symbol = XEXP (XEXP (op1, 0), 0);
12436 model = SYMBOL_REF_TLS_MODEL (symbol);
12438 tmp = legitimize_tls_address (symbol, model, true);
12439 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12440 && SYMBOL_REF_DLLIMPORT_P (symbol))
12441 tmp = legitimize_dllimport_symbol (symbol, true);
12445 tmp = force_operand (tmp, NULL);
12446 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12447 op0, 1, OPTAB_DIRECT);
12453 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12455 if (TARGET_MACHO && !TARGET_64BIT)
12460 rtx temp = ((reload_in_progress
12461 || ((op0 && REG_P (op0))
12463 ? op0 : gen_reg_rtx (Pmode));
12464 op1 = machopic_indirect_data_reference (op1, temp);
12465 op1 = machopic_legitimize_pic_address (op1, mode,
12466 temp == op1 ? 0 : temp);
12468 else if (MACHOPIC_INDIRECT)
12469 op1 = machopic_indirect_data_reference (op1, 0);
12477 op1 = force_reg (Pmode, op1);
12478 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12480 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12481 op1 = legitimize_pic_address (op1, reg);
12490 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12491 || !push_operand (op0, mode))
12493 op1 = force_reg (mode, op1);
12495 if (push_operand (op0, mode)
12496 && ! general_no_elim_operand (op1, mode))
12497 op1 = copy_to_mode_reg (mode, op1);
12499 /* Force large constants in 64bit compilation into register
12500 to get them CSEed. */
12501 if (can_create_pseudo_p ()
12502 && (mode == DImode) && TARGET_64BIT
12503 && immediate_operand (op1, mode)
12504 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12505 && !register_operand (op0, mode)
12507 op1 = copy_to_mode_reg (mode, op1);
12509 if (can_create_pseudo_p ()
12510 && FLOAT_MODE_P (mode)
12511 && GET_CODE (op1) == CONST_DOUBLE)
12513 /* If we are loading a floating point constant to a register,
12514 force the value to memory now, since we'll get better code
12515 out the back end. */
12517 op1 = validize_mem (force_const_mem (mode, op1));
12518 if (!register_operand (op0, mode))
12520 rtx temp = gen_reg_rtx (mode);
12521 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12522 emit_move_insn (op0, temp);
12528 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12532 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12534 rtx op0 = operands[0], op1 = operands[1];
12535 unsigned int align = GET_MODE_ALIGNMENT (mode);
12537 /* Force constants other than zero into memory. We do not know how
12538 the instructions used to build constants modify the upper 64 bits
12539 of the register, once we have that information we may be able
12540 to handle some of them more efficiently. */
12541 if (can_create_pseudo_p ()
12542 && register_operand (op0, mode)
12543 && (CONSTANT_P (op1)
12544 || (GET_CODE (op1) == SUBREG
12545 && CONSTANT_P (SUBREG_REG (op1))))
12546 && standard_sse_constant_p (op1) <= 0)
12547 op1 = validize_mem (force_const_mem (mode, op1));
12549 /* We need to check memory alignment for SSE mode since attribute
12550 can make operands unaligned. */
12551 if (can_create_pseudo_p ()
12552 && SSE_REG_MODE_P (mode)
12553 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12554 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12558 /* ix86_expand_vector_move_misalign() does not like constants ... */
12559 if (CONSTANT_P (op1)
12560 || (GET_CODE (op1) == SUBREG
12561 && CONSTANT_P (SUBREG_REG (op1))))
12562 op1 = validize_mem (force_const_mem (mode, op1));
12564 /* ... nor both arguments in memory. */
12565 if (!register_operand (op0, mode)
12566 && !register_operand (op1, mode))
12567 op1 = force_reg (mode, op1);
12569 tmp[0] = op0; tmp[1] = op1;
12570 ix86_expand_vector_move_misalign (mode, tmp);
12574 /* Make operand1 a register if it isn't already. */
12575 if (can_create_pseudo_p ()
12576 && !register_operand (op0, mode)
12577 && !register_operand (op1, mode))
12579 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12583 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12586 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12587 straight to ix86_expand_vector_move. */
12588 /* Code generation for scalar reg-reg moves of single and double precision data:
12589 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12593 if (x86_sse_partial_reg_dependency == true)
12598 Code generation for scalar loads of double precision data:
12599 if (x86_sse_split_regs == true)
12600 movlpd mem, reg (gas syntax)
12604 Code generation for unaligned packed loads of single precision data
12605 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12606 if (x86_sse_unaligned_move_optimal)
12609 if (x86_sse_partial_reg_dependency == true)
12621 Code generation for unaligned packed loads of double precision data
12622 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12623 if (x86_sse_unaligned_move_optimal)
12626 if (x86_sse_split_regs == true)
12639 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12648 switch (GET_MODE_CLASS (mode))
12650 case MODE_VECTOR_INT:
12652 switch (GET_MODE_SIZE (mode))
12655 op0 = gen_lowpart (V16QImode, op0);
12656 op1 = gen_lowpart (V16QImode, op1);
12657 emit_insn (gen_avx_movdqu (op0, op1));
12660 op0 = gen_lowpart (V32QImode, op0);
12661 op1 = gen_lowpart (V32QImode, op1);
12662 emit_insn (gen_avx_movdqu256 (op0, op1));
12665 gcc_unreachable ();
12668 case MODE_VECTOR_FLOAT:
12669 op0 = gen_lowpart (mode, op0);
12670 op1 = gen_lowpart (mode, op1);
12675 emit_insn (gen_avx_movups (op0, op1));
12678 emit_insn (gen_avx_movups256 (op0, op1));
12681 emit_insn (gen_avx_movupd (op0, op1));
12684 emit_insn (gen_avx_movupd256 (op0, op1));
12687 gcc_unreachable ();
12692 gcc_unreachable ();
12700 /* If we're optimizing for size, movups is the smallest. */
12701 if (optimize_insn_for_size_p ())
12703 op0 = gen_lowpart (V4SFmode, op0);
12704 op1 = gen_lowpart (V4SFmode, op1);
12705 emit_insn (gen_sse_movups (op0, op1));
12709 /* ??? If we have typed data, then it would appear that using
12710 movdqu is the only way to get unaligned data loaded with
12712 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12714 op0 = gen_lowpart (V16QImode, op0);
12715 op1 = gen_lowpart (V16QImode, op1);
12716 emit_insn (gen_sse2_movdqu (op0, op1));
12720 if (TARGET_SSE2 && mode == V2DFmode)
12724 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12726 op0 = gen_lowpart (V2DFmode, op0);
12727 op1 = gen_lowpart (V2DFmode, op1);
12728 emit_insn (gen_sse2_movupd (op0, op1));
12732 /* When SSE registers are split into halves, we can avoid
12733 writing to the top half twice. */
12734 if (TARGET_SSE_SPLIT_REGS)
12736 emit_clobber (op0);
12741 /* ??? Not sure about the best option for the Intel chips.
12742 The following would seem to satisfy; the register is
12743 entirely cleared, breaking the dependency chain. We
12744 then store to the upper half, with a dependency depth
12745 of one. A rumor has it that Intel recommends two movsd
12746 followed by an unpacklpd, but this is unconfirmed. And
12747 given that the dependency depth of the unpacklpd would
12748 still be one, I'm not sure why this would be better. */
12749 zero = CONST0_RTX (V2DFmode);
12752 m = adjust_address (op1, DFmode, 0);
12753 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12754 m = adjust_address (op1, DFmode, 8);
12755 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12759 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12761 op0 = gen_lowpart (V4SFmode, op0);
12762 op1 = gen_lowpart (V4SFmode, op1);
12763 emit_insn (gen_sse_movups (op0, op1));
12767 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12768 emit_move_insn (op0, CONST0_RTX (mode));
12770 emit_clobber (op0);
12772 if (mode != V4SFmode)
12773 op0 = gen_lowpart (V4SFmode, op0);
12774 m = adjust_address (op1, V2SFmode, 0);
12775 emit_insn (gen_sse_loadlps (op0, op0, m));
12776 m = adjust_address (op1, V2SFmode, 8);
12777 emit_insn (gen_sse_loadhps (op0, op0, m));
12780 else if (MEM_P (op0))
12782 /* If we're optimizing for size, movups is the smallest. */
12783 if (optimize_insn_for_size_p ())
12785 op0 = gen_lowpart (V4SFmode, op0);
12786 op1 = gen_lowpart (V4SFmode, op1);
12787 emit_insn (gen_sse_movups (op0, op1));
12791 /* ??? Similar to above, only less clear because of quote
12792 typeless stores unquote. */
12793 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12794 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12796 op0 = gen_lowpart (V16QImode, op0);
12797 op1 = gen_lowpart (V16QImode, op1);
12798 emit_insn (gen_sse2_movdqu (op0, op1));
12802 if (TARGET_SSE2 && mode == V2DFmode)
12804 m = adjust_address (op0, DFmode, 0);
12805 emit_insn (gen_sse2_storelpd (m, op1));
12806 m = adjust_address (op0, DFmode, 8);
12807 emit_insn (gen_sse2_storehpd (m, op1));
12811 if (mode != V4SFmode)
12812 op1 = gen_lowpart (V4SFmode, op1);
12813 m = adjust_address (op0, V2SFmode, 0);
12814 emit_insn (gen_sse_storelps (m, op1));
12815 m = adjust_address (op0, V2SFmode, 8);
12816 emit_insn (gen_sse_storehps (m, op1));
12820 gcc_unreachable ();
12823 /* Expand a push in MODE. This is some mode for which we do not support
12824 proper push instructions, at least from the registers that we expect
12825 the value to live in. */
12828 ix86_expand_push (enum machine_mode mode, rtx x)
12832 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12833 GEN_INT (-GET_MODE_SIZE (mode)),
12834 stack_pointer_rtx, 1, OPTAB_DIRECT);
12835 if (tmp != stack_pointer_rtx)
12836 emit_move_insn (stack_pointer_rtx, tmp);
12838 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12840 /* When we push an operand onto stack, it has to be aligned at least
12841 at the function argument boundary. However since we don't have
12842 the argument type, we can't determine the actual argument
12844 emit_move_insn (tmp, x);
12847 /* Helper function of ix86_fixup_binary_operands to canonicalize
12848 operand order. Returns true if the operands should be swapped. */
12851 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12854 rtx dst = operands[0];
12855 rtx src1 = operands[1];
12856 rtx src2 = operands[2];
12858 /* If the operation is not commutative, we can't do anything. */
12859 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12862 /* Highest priority is that src1 should match dst. */
12863 if (rtx_equal_p (dst, src1))
12865 if (rtx_equal_p (dst, src2))
12868 /* Next highest priority is that immediate constants come second. */
12869 if (immediate_operand (src2, mode))
12871 if (immediate_operand (src1, mode))
12874 /* Lowest priority is that memory references should come second. */
12884 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12885 destination to use for the operation. If different from the true
12886 destination in operands[0], a copy operation will be required. */
12889 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12892 rtx dst = operands[0];
12893 rtx src1 = operands[1];
12894 rtx src2 = operands[2];
12896 /* Canonicalize operand order. */
12897 if (ix86_swap_binary_operands_p (code, mode, operands))
12901 /* It is invalid to swap operands of different modes. */
12902 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12909 /* Both source operands cannot be in memory. */
12910 if (MEM_P (src1) && MEM_P (src2))
12912 /* Optimization: Only read from memory once. */
12913 if (rtx_equal_p (src1, src2))
12915 src2 = force_reg (mode, src2);
12919 src2 = force_reg (mode, src2);
12922 /* If the destination is memory, and we do not have matching source
12923 operands, do things in registers. */
12924 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12925 dst = gen_reg_rtx (mode);
12927 /* Source 1 cannot be a constant. */
12928 if (CONSTANT_P (src1))
12929 src1 = force_reg (mode, src1);
12931 /* Source 1 cannot be a non-matching memory. */
12932 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12933 src1 = force_reg (mode, src1);
12935 operands[1] = src1;
12936 operands[2] = src2;
12940 /* Similarly, but assume that the destination has already been
12941 set up properly. */
12944 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12945 enum machine_mode mode, rtx operands[])
12947 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12948 gcc_assert (dst == operands[0]);
12951 /* Attempt to expand a binary operator. Make the expansion closer to the
12952 actual machine, then just general_operand, which will allow 3 separate
12953 memory references (one output, two input) in a single insn. */
12956 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12959 rtx src1, src2, dst, op, clob;
12961 dst = ix86_fixup_binary_operands (code, mode, operands);
12962 src1 = operands[1];
12963 src2 = operands[2];
12965 /* Emit the instruction. */
12967 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12968 if (reload_in_progress)
12970 /* Reload doesn't know about the flags register, and doesn't know that
12971 it doesn't want to clobber it. We can only do this with PLUS. */
12972 gcc_assert (code == PLUS);
12977 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12978 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12981 /* Fix up the destination if needed. */
12982 if (dst != operands[0])
12983 emit_move_insn (operands[0], dst);
12986 /* Return TRUE or FALSE depending on whether the binary operator meets the
12987 appropriate constraints. */
12990 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12993 rtx dst = operands[0];
12994 rtx src1 = operands[1];
12995 rtx src2 = operands[2];
12997 /* Both source operands cannot be in memory. */
12998 if (MEM_P (src1) && MEM_P (src2))
13001 /* Canonicalize operand order for commutative operators. */
13002 if (ix86_swap_binary_operands_p (code, mode, operands))
13009 /* If the destination is memory, we must have a matching source operand. */
13010 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13013 /* Source 1 cannot be a constant. */
13014 if (CONSTANT_P (src1))
13017 /* Source 1 cannot be a non-matching memory. */
13018 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13024 /* Attempt to expand a unary operator. Make the expansion closer to the
13025 actual machine, then just general_operand, which will allow 2 separate
13026 memory references (one output, one input) in a single insn. */
13029 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13032 int matching_memory;
13033 rtx src, dst, op, clob;
13038 /* If the destination is memory, and we do not have matching source
13039 operands, do things in registers. */
13040 matching_memory = 0;
13043 if (rtx_equal_p (dst, src))
13044 matching_memory = 1;
13046 dst = gen_reg_rtx (mode);
13049 /* When source operand is memory, destination must match. */
13050 if (MEM_P (src) && !matching_memory)
13051 src = force_reg (mode, src);
13053 /* Emit the instruction. */
13055 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13056 if (reload_in_progress || code == NOT)
13058 /* Reload doesn't know about the flags register, and doesn't know that
13059 it doesn't want to clobber it. */
13060 gcc_assert (code == NOT);
13065 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13066 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13069 /* Fix up the destination if needed. */
13070 if (dst != operands[0])
13071 emit_move_insn (operands[0], dst);
13074 #define LEA_SEARCH_THRESHOLD 12
13076 /* Search backward for non-agu definition of register number REGNO1
13077 or register number REGNO2 in INSN's basic block until
13078 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13079 2. Reach BB boundary, or
13080 3. Reach agu definition.
13081 Returns the distance between the non-agu definition point and INSN.
13082 If no definition point, returns -1. */
13085 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13088 basic_block bb = BLOCK_FOR_INSN (insn);
13091 enum attr_type insn_type;
13093 if (insn != BB_HEAD (bb))
13095 rtx prev = PREV_INSN (insn);
13096 while (prev && distance < LEA_SEARCH_THRESHOLD)
13101 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13102 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13103 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13104 && (regno1 == DF_REF_REGNO (*def_rec)
13105 || regno2 == DF_REF_REGNO (*def_rec)))
13107 insn_type = get_attr_type (prev);
13108 if (insn_type != TYPE_LEA)
13112 if (prev == BB_HEAD (bb))
13114 prev = PREV_INSN (prev);
13118 if (distance < LEA_SEARCH_THRESHOLD)
13122 bool simple_loop = false;
13124 FOR_EACH_EDGE (e, ei, bb->preds)
13127 simple_loop = true;
13133 rtx prev = BB_END (bb);
13136 && distance < LEA_SEARCH_THRESHOLD)
13141 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13142 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13143 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13144 && (regno1 == DF_REF_REGNO (*def_rec)
13145 || regno2 == DF_REF_REGNO (*def_rec)))
13147 insn_type = get_attr_type (prev);
13148 if (insn_type != TYPE_LEA)
13152 prev = PREV_INSN (prev);
13160 /* get_attr_type may modify recog data. We want to make sure
13161 that recog data is valid for instruction INSN, on which
13162 distance_non_agu_define is called. INSN is unchanged here. */
13163 extract_insn_cached (insn);
13167 /* Return the distance between INSN and the next insn that uses
13168 register number REGNO0 in memory address. Return -1 if no such
13169 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13172 distance_agu_use (unsigned int regno0, rtx insn)
13174 basic_block bb = BLOCK_FOR_INSN (insn);
13179 if (insn != BB_END (bb))
13181 rtx next = NEXT_INSN (insn);
13182 while (next && distance < LEA_SEARCH_THRESHOLD)
13188 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13189 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13190 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13191 && regno0 == DF_REF_REGNO (*use_rec))
13193 /* Return DISTANCE if OP0 is used in memory
13194 address in NEXT. */
13198 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13199 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13200 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13201 && regno0 == DF_REF_REGNO (*def_rec))
13203 /* Return -1 if OP0 is set in NEXT. */
13207 if (next == BB_END (bb))
13209 next = NEXT_INSN (next);
13213 if (distance < LEA_SEARCH_THRESHOLD)
13217 bool simple_loop = false;
13219 FOR_EACH_EDGE (e, ei, bb->succs)
13222 simple_loop = true;
13228 rtx next = BB_HEAD (bb);
13231 && distance < LEA_SEARCH_THRESHOLD)
13237 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13238 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13239 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13240 && regno0 == DF_REF_REGNO (*use_rec))
13242 /* Return DISTANCE if OP0 is used in memory
13243 address in NEXT. */
13247 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13248 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13249 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13250 && regno0 == DF_REF_REGNO (*def_rec))
13252 /* Return -1 if OP0 is set in NEXT. */
13257 next = NEXT_INSN (next);
13265 /* Define this macro to tune LEA priority vs ADD, it take effect when
13266 there is a dilemma of choicing LEA or ADD
13267 Negative value: ADD is more preferred than LEA
13269 Positive value: LEA is more preferred than ADD*/
13270 #define IX86_LEA_PRIORITY 2
13272 /* Return true if it is ok to optimize an ADD operation to LEA
13273 operation to avoid flag register consumation. For the processors
13274 like ATOM, if the destination register of LEA holds an actual
13275 address which will be used soon, LEA is better and otherwise ADD
13279 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13280 rtx insn, rtx operands[])
13282 unsigned int regno0 = true_regnum (operands[0]);
13283 unsigned int regno1 = true_regnum (operands[1]);
13284 unsigned int regno2;
13286 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13287 return regno0 != regno1;
13289 regno2 = true_regnum (operands[2]);
13291 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13292 if (regno0 != regno1 && regno0 != regno2)
13296 int dist_define, dist_use;
13297 dist_define = distance_non_agu_define (regno1, regno2, insn);
13298 if (dist_define <= 0)
13301 /* If this insn has both backward non-agu dependence and forward
13302 agu dependence, the one with short distance take effect. */
13303 dist_use = distance_agu_use (regno0, insn);
13305 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13312 /* Return true if destination reg of SET_BODY is shift count of
13316 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13322 /* Retrieve destination of SET_BODY. */
13323 switch (GET_CODE (set_body))
13326 set_dest = SET_DEST (set_body);
13327 if (!set_dest || !REG_P (set_dest))
13331 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13332 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13340 /* Retrieve shift count of USE_BODY. */
13341 switch (GET_CODE (use_body))
13344 shift_rtx = XEXP (use_body, 1);
13347 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13348 if (ix86_dep_by_shift_count_body (set_body,
13349 XVECEXP (use_body, 0, i)))
13357 && (GET_CODE (shift_rtx) == ASHIFT
13358 || GET_CODE (shift_rtx) == LSHIFTRT
13359 || GET_CODE (shift_rtx) == ASHIFTRT
13360 || GET_CODE (shift_rtx) == ROTATE
13361 || GET_CODE (shift_rtx) == ROTATERT))
13363 rtx shift_count = XEXP (shift_rtx, 1);
13365 /* Return true if shift count is dest of SET_BODY. */
13366 if (REG_P (shift_count)
13367 && true_regnum (set_dest) == true_regnum (shift_count))
13374 /* Return true if destination reg of SET_INSN is shift count of
13378 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13380 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13381 PATTERN (use_insn));
13384 /* Return TRUE or FALSE depending on whether the unary operator meets the
13385 appropriate constraints. */
13388 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13389 enum machine_mode mode ATTRIBUTE_UNUSED,
13390 rtx operands[2] ATTRIBUTE_UNUSED)
13392 /* If one of operands is memory, source and destination must match. */
13393 if ((MEM_P (operands[0])
13394 || MEM_P (operands[1]))
13395 && ! rtx_equal_p (operands[0], operands[1]))
13400 /* Post-reload splitter for converting an SF or DFmode value in an
13401 SSE register into an unsigned SImode. */
13404 ix86_split_convert_uns_si_sse (rtx operands[])
13406 enum machine_mode vecmode;
13407 rtx value, large, zero_or_two31, input, two31, x;
13409 large = operands[1];
13410 zero_or_two31 = operands[2];
13411 input = operands[3];
13412 two31 = operands[4];
13413 vecmode = GET_MODE (large);
13414 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13416 /* Load up the value into the low element. We must ensure that the other
13417 elements are valid floats -- zero is the easiest such value. */
13420 if (vecmode == V4SFmode)
13421 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13423 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13427 input = gen_rtx_REG (vecmode, REGNO (input));
13428 emit_move_insn (value, CONST0_RTX (vecmode));
13429 if (vecmode == V4SFmode)
13430 emit_insn (gen_sse_movss (value, value, input));
13432 emit_insn (gen_sse2_movsd (value, value, input));
13435 emit_move_insn (large, two31);
13436 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13438 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13439 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13441 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13442 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13444 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13445 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13447 large = gen_rtx_REG (V4SImode, REGNO (large));
13448 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13450 x = gen_rtx_REG (V4SImode, REGNO (value));
13451 if (vecmode == V4SFmode)
13452 emit_insn (gen_sse2_cvttps2dq (x, value));
13454 emit_insn (gen_sse2_cvttpd2dq (x, value));
13457 emit_insn (gen_xorv4si3 (value, value, large));
13460 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13461 Expects the 64-bit DImode to be supplied in a pair of integral
13462 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13463 -mfpmath=sse, !optimize_size only. */
13466 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13468 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13469 rtx int_xmm, fp_xmm;
13470 rtx biases, exponents;
13473 int_xmm = gen_reg_rtx (V4SImode);
13474 if (TARGET_INTER_UNIT_MOVES)
13475 emit_insn (gen_movdi_to_sse (int_xmm, input));
13476 else if (TARGET_SSE_SPLIT_REGS)
13478 emit_clobber (int_xmm);
13479 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13483 x = gen_reg_rtx (V2DImode);
13484 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13485 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13488 x = gen_rtx_CONST_VECTOR (V4SImode,
13489 gen_rtvec (4, GEN_INT (0x43300000UL),
13490 GEN_INT (0x45300000UL),
13491 const0_rtx, const0_rtx));
13492 exponents = validize_mem (force_const_mem (V4SImode, x));
13494 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13495 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13497 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13498 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13499 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13500 (0x1.0p84 + double(fp_value_hi_xmm)).
13501 Note these exponents differ by 32. */
13503 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13505 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13506 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13507 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13508 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13509 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13510 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13511 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13512 biases = validize_mem (force_const_mem (V2DFmode, biases));
13513 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13515 /* Add the upper and lower DFmode values together. */
13517 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13520 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13521 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13522 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13525 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13528 /* Not used, but eases macroization of patterns. */
13530 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13531 rtx input ATTRIBUTE_UNUSED)
13533 gcc_unreachable ();
13536 /* Convert an unsigned SImode value into a DFmode. Only currently used
13537 for SSE, but applicable anywhere. */
13540 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13542 REAL_VALUE_TYPE TWO31r;
13545 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13546 NULL, 1, OPTAB_DIRECT);
13548 fp = gen_reg_rtx (DFmode);
13549 emit_insn (gen_floatsidf2 (fp, x));
13551 real_ldexp (&TWO31r, &dconst1, 31);
13552 x = const_double_from_real_value (TWO31r, DFmode);
13554 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13556 emit_move_insn (target, x);
13559 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13560 32-bit mode; otherwise we have a direct convert instruction. */
13563 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13565 REAL_VALUE_TYPE TWO32r;
13566 rtx fp_lo, fp_hi, x;
13568 fp_lo = gen_reg_rtx (DFmode);
13569 fp_hi = gen_reg_rtx (DFmode);
13571 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13573 real_ldexp (&TWO32r, &dconst1, 32);
13574 x = const_double_from_real_value (TWO32r, DFmode);
13575 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13577 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13579 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13582 emit_move_insn (target, x);
13585 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13586 For x86_32, -mfpmath=sse, !optimize_size only. */
13588 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13590 REAL_VALUE_TYPE ONE16r;
13591 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13593 real_ldexp (&ONE16r, &dconst1, 16);
13594 x = const_double_from_real_value (ONE16r, SFmode);
13595 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13596 NULL, 0, OPTAB_DIRECT);
13597 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13598 NULL, 0, OPTAB_DIRECT);
13599 fp_hi = gen_reg_rtx (SFmode);
13600 fp_lo = gen_reg_rtx (SFmode);
13601 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13602 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13603 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13605 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13607 if (!rtx_equal_p (target, fp_hi))
13608 emit_move_insn (target, fp_hi);
13611 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13612 then replicate the value for all elements of the vector
13616 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13623 v = gen_rtvec (4, value, value, value, value);
13624 return gen_rtx_CONST_VECTOR (V4SImode, v);
13628 v = gen_rtvec (2, value, value);
13629 return gen_rtx_CONST_VECTOR (V2DImode, v);
13633 v = gen_rtvec (4, value, value, value, value);
13635 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13636 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13637 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13641 v = gen_rtvec (2, value, value);
13643 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13644 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13647 gcc_unreachable ();
13651 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13652 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13653 for an SSE register. If VECT is true, then replicate the mask for
13654 all elements of the vector register. If INVERT is true, then create
13655 a mask excluding the sign bit. */
13658 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13660 enum machine_mode vec_mode, imode;
13661 HOST_WIDE_INT hi, lo;
13666 /* Find the sign bit, sign extended to 2*HWI. */
13672 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13673 lo = 0x80000000, hi = lo < 0;
13679 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13680 if (HOST_BITS_PER_WIDE_INT >= 64)
13681 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13683 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13688 vec_mode = VOIDmode;
13689 if (HOST_BITS_PER_WIDE_INT >= 64)
13692 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13699 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13703 lo = ~lo, hi = ~hi;
13709 mask = immed_double_const (lo, hi, imode);
13711 vec = gen_rtvec (2, v, mask);
13712 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13713 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13720 gcc_unreachable ();
13724 lo = ~lo, hi = ~hi;
13726 /* Force this value into the low part of a fp vector constant. */
13727 mask = immed_double_const (lo, hi, imode);
13728 mask = gen_lowpart (mode, mask);
13730 if (vec_mode == VOIDmode)
13731 return force_reg (mode, mask);
13733 v = ix86_build_const_vector (mode, vect, mask);
13734 return force_reg (vec_mode, v);
13737 /* Generate code for floating point ABS or NEG. */
13740 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13743 rtx mask, set, use, clob, dst, src;
13744 bool use_sse = false;
13745 bool vector_mode = VECTOR_MODE_P (mode);
13746 enum machine_mode elt_mode = mode;
13750 elt_mode = GET_MODE_INNER (mode);
13753 else if (mode == TFmode)
13755 else if (TARGET_SSE_MATH)
13756 use_sse = SSE_FLOAT_MODE_P (mode);
13758 /* NEG and ABS performed with SSE use bitwise mask operations.
13759 Create the appropriate mask now. */
13761 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13770 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13771 set = gen_rtx_SET (VOIDmode, dst, set);
13776 set = gen_rtx_fmt_e (code, mode, src);
13777 set = gen_rtx_SET (VOIDmode, dst, set);
13780 use = gen_rtx_USE (VOIDmode, mask);
13781 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13782 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13783 gen_rtvec (3, set, use, clob)));
13790 /* Expand a copysign operation. Special case operand 0 being a constant. */
13793 ix86_expand_copysign (rtx operands[])
13795 enum machine_mode mode;
13796 rtx dest, op0, op1, mask, nmask;
13798 dest = operands[0];
13802 mode = GET_MODE (dest);
13804 if (GET_CODE (op0) == CONST_DOUBLE)
13806 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13808 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13809 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13811 if (mode == SFmode || mode == DFmode)
13813 enum machine_mode vmode;
13815 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13817 if (op0 == CONST0_RTX (mode))
13818 op0 = CONST0_RTX (vmode);
13823 if (mode == SFmode)
13824 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13825 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13827 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13829 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13832 else if (op0 != CONST0_RTX (mode))
13833 op0 = force_reg (mode, op0);
13835 mask = ix86_build_signbit_mask (mode, 0, 0);
13837 if (mode == SFmode)
13838 copysign_insn = gen_copysignsf3_const;
13839 else if (mode == DFmode)
13840 copysign_insn = gen_copysigndf3_const;
13842 copysign_insn = gen_copysigntf3_const;
13844 emit_insn (copysign_insn (dest, op0, op1, mask));
13848 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13850 nmask = ix86_build_signbit_mask (mode, 0, 1);
13851 mask = ix86_build_signbit_mask (mode, 0, 0);
13853 if (mode == SFmode)
13854 copysign_insn = gen_copysignsf3_var;
13855 else if (mode == DFmode)
13856 copysign_insn = gen_copysigndf3_var;
13858 copysign_insn = gen_copysigntf3_var;
13860 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13864 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13865 be a constant, and so has already been expanded into a vector constant. */
13868 ix86_split_copysign_const (rtx operands[])
13870 enum machine_mode mode, vmode;
13871 rtx dest, op0, op1, mask, x;
13873 dest = operands[0];
13876 mask = operands[3];
13878 mode = GET_MODE (dest);
13879 vmode = GET_MODE (mask);
13881 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13882 x = gen_rtx_AND (vmode, dest, mask);
13883 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13885 if (op0 != CONST0_RTX (vmode))
13887 x = gen_rtx_IOR (vmode, dest, op0);
13888 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13892 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13893 so we have to do two masks. */
13896 ix86_split_copysign_var (rtx operands[])
13898 enum machine_mode mode, vmode;
13899 rtx dest, scratch, op0, op1, mask, nmask, x;
13901 dest = operands[0];
13902 scratch = operands[1];
13905 nmask = operands[4];
13906 mask = operands[5];
13908 mode = GET_MODE (dest);
13909 vmode = GET_MODE (mask);
13911 if (rtx_equal_p (op0, op1))
13913 /* Shouldn't happen often (it's useless, obviously), but when it does
13914 we'd generate incorrect code if we continue below. */
13915 emit_move_insn (dest, op0);
13919 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13921 gcc_assert (REGNO (op1) == REGNO (scratch));
13923 x = gen_rtx_AND (vmode, scratch, mask);
13924 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13927 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13928 x = gen_rtx_NOT (vmode, dest);
13929 x = gen_rtx_AND (vmode, x, op0);
13930 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13934 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13936 x = gen_rtx_AND (vmode, scratch, mask);
13938 else /* alternative 2,4 */
13940 gcc_assert (REGNO (mask) == REGNO (scratch));
13941 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13942 x = gen_rtx_AND (vmode, scratch, op1);
13944 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13946 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13948 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13949 x = gen_rtx_AND (vmode, dest, nmask);
13951 else /* alternative 3,4 */
13953 gcc_assert (REGNO (nmask) == REGNO (dest));
13955 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13956 x = gen_rtx_AND (vmode, dest, op0);
13958 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13961 x = gen_rtx_IOR (vmode, dest, scratch);
13962 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13965 /* Return TRUE or FALSE depending on whether the first SET in INSN
13966 has source and destination with matching CC modes, and that the
13967 CC mode is at least as constrained as REQ_MODE. */
13970 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13973 enum machine_mode set_mode;
13975 set = PATTERN (insn);
13976 if (GET_CODE (set) == PARALLEL)
13977 set = XVECEXP (set, 0, 0);
13978 gcc_assert (GET_CODE (set) == SET);
13979 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13981 set_mode = GET_MODE (SET_DEST (set));
13985 if (req_mode != CCNOmode
13986 && (req_mode != CCmode
13987 || XEXP (SET_SRC (set), 1) != const0_rtx))
13991 if (req_mode == CCGCmode)
13995 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13999 if (req_mode == CCZmode)
14010 gcc_unreachable ();
14013 return (GET_MODE (SET_SRC (set)) == set_mode);
14016 /* Generate insn patterns to do an integer compare of OPERANDS. */
14019 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14021 enum machine_mode cmpmode;
14024 cmpmode = SELECT_CC_MODE (code, op0, op1);
14025 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14027 /* This is very simple, but making the interface the same as in the
14028 FP case makes the rest of the code easier. */
14029 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14030 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14032 /* Return the test that should be put into the flags user, i.e.
14033 the bcc, scc, or cmov instruction. */
14034 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14037 /* Figure out whether to use ordered or unordered fp comparisons.
14038 Return the appropriate mode to use. */
14041 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14043 /* ??? In order to make all comparisons reversible, we do all comparisons
14044 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14045 all forms trapping and nontrapping comparisons, we can make inequality
14046 comparisons trapping again, since it results in better code when using
14047 FCOM based compares. */
14048 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14052 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14054 enum machine_mode mode = GET_MODE (op0);
14056 if (SCALAR_FLOAT_MODE_P (mode))
14058 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14059 return ix86_fp_compare_mode (code);
14064 /* Only zero flag is needed. */
14065 case EQ: /* ZF=0 */
14066 case NE: /* ZF!=0 */
14068 /* Codes needing carry flag. */
14069 case GEU: /* CF=0 */
14070 case LTU: /* CF=1 */
14071 /* Detect overflow checks. They need just the carry flag. */
14072 if (GET_CODE (op0) == PLUS
14073 && rtx_equal_p (op1, XEXP (op0, 0)))
14077 case GTU: /* CF=0 & ZF=0 */
14078 case LEU: /* CF=1 | ZF=1 */
14079 /* Detect overflow checks. They need just the carry flag. */
14080 if (GET_CODE (op0) == MINUS
14081 && rtx_equal_p (op1, XEXP (op0, 0)))
14085 /* Codes possibly doable only with sign flag when
14086 comparing against zero. */
14087 case GE: /* SF=OF or SF=0 */
14088 case LT: /* SF<>OF or SF=1 */
14089 if (op1 == const0_rtx)
14092 /* For other cases Carry flag is not required. */
14094 /* Codes doable only with sign flag when comparing
14095 against zero, but we miss jump instruction for it
14096 so we need to use relational tests against overflow
14097 that thus needs to be zero. */
14098 case GT: /* ZF=0 & SF=OF */
14099 case LE: /* ZF=1 | SF<>OF */
14100 if (op1 == const0_rtx)
14104 /* strcmp pattern do (use flags) and combine may ask us for proper
14109 gcc_unreachable ();
14113 /* Return the fixed registers used for condition codes. */
14116 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14123 /* If two condition code modes are compatible, return a condition code
14124 mode which is compatible with both. Otherwise, return
14127 static enum machine_mode
14128 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14133 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14136 if ((m1 == CCGCmode && m2 == CCGOCmode)
14137 || (m1 == CCGOCmode && m2 == CCGCmode))
14143 gcc_unreachable ();
14173 /* These are only compatible with themselves, which we already
14179 /* Split comparison code CODE into comparisons we can do using branch
14180 instructions. BYPASS_CODE is comparison code for branch that will
14181 branch around FIRST_CODE and SECOND_CODE. If some of branches
14182 is not required, set value to UNKNOWN.
14183 We never require more than two branches. */
14186 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
14187 enum rtx_code *first_code,
14188 enum rtx_code *second_code)
14190 *first_code = code;
14191 *bypass_code = UNKNOWN;
14192 *second_code = UNKNOWN;
14194 /* The fcomi comparison sets flags as follows:
14204 case GT: /* GTU - CF=0 & ZF=0 */
14205 case GE: /* GEU - CF=0 */
14206 case ORDERED: /* PF=0 */
14207 case UNORDERED: /* PF=1 */
14208 case UNEQ: /* EQ - ZF=1 */
14209 case UNLT: /* LTU - CF=1 */
14210 case UNLE: /* LEU - CF=1 | ZF=1 */
14211 case LTGT: /* EQ - ZF=0 */
14213 case LT: /* LTU - CF=1 - fails on unordered */
14214 *first_code = UNLT;
14215 *bypass_code = UNORDERED;
14217 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
14218 *first_code = UNLE;
14219 *bypass_code = UNORDERED;
14221 case EQ: /* EQ - ZF=1 - fails on unordered */
14222 *first_code = UNEQ;
14223 *bypass_code = UNORDERED;
14225 case NE: /* NE - ZF=0 - fails on unordered */
14226 *first_code = LTGT;
14227 *second_code = UNORDERED;
14229 case UNGE: /* GEU - CF=0 - fails on unordered */
14231 *second_code = UNORDERED;
14233 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
14235 *second_code = UNORDERED;
14238 gcc_unreachable ();
14240 if (!TARGET_IEEE_FP)
14242 *second_code = UNKNOWN;
14243 *bypass_code = UNKNOWN;
14247 /* Return cost of comparison done fcom + arithmetics operations on AX.
14248 All following functions do use number of instructions as a cost metrics.
14249 In future this should be tweaked to compute bytes for optimize_size and
14250 take into account performance of various instructions on various CPUs. */
14252 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
14254 if (!TARGET_IEEE_FP)
14256 /* The cost of code output by ix86_expand_fp_compare. */
14280 gcc_unreachable ();
14284 /* Return cost of comparison done using fcomi operation.
14285 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14287 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
14289 enum rtx_code bypass_code, first_code, second_code;
14290 /* Return arbitrarily high cost when instruction is not supported - this
14291 prevents gcc from using it. */
14294 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14295 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
14298 /* Return cost of comparison done using sahf operation.
14299 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14301 ix86_fp_comparison_sahf_cost (enum rtx_code code)
14303 enum rtx_code bypass_code, first_code, second_code;
14304 /* Return arbitrarily high cost when instruction is not preferred - this
14305 avoids gcc from using it. */
14306 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
14308 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14309 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
14312 /* Compute cost of the comparison done using any method.
14313 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14315 ix86_fp_comparison_cost (enum rtx_code code)
14317 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
14320 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
14321 sahf_cost = ix86_fp_comparison_sahf_cost (code);
14323 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
14324 if (min > sahf_cost)
14326 if (min > fcomi_cost)
14331 /* Return true if we should use an FCOMI instruction for this
14335 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
14337 enum rtx_code swapped_code = swap_condition (code);
14339 return ((ix86_fp_comparison_cost (code)
14340 == ix86_fp_comparison_fcomi_cost (code))
14341 || (ix86_fp_comparison_cost (swapped_code)
14342 == ix86_fp_comparison_fcomi_cost (swapped_code)));
14345 /* Swap, force into registers, or otherwise massage the two operands
14346 to a fp comparison. The operands are updated in place; the new
14347 comparison code is returned. */
14349 static enum rtx_code
14350 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14352 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14353 rtx op0 = *pop0, op1 = *pop1;
14354 enum machine_mode op_mode = GET_MODE (op0);
14355 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14357 /* All of the unordered compare instructions only work on registers.
14358 The same is true of the fcomi compare instructions. The XFmode
14359 compare instructions require registers except when comparing
14360 against zero or when converting operand 1 from fixed point to
14364 && (fpcmp_mode == CCFPUmode
14365 || (op_mode == XFmode
14366 && ! (standard_80387_constant_p (op0) == 1
14367 || standard_80387_constant_p (op1) == 1)
14368 && GET_CODE (op1) != FLOAT)
14369 || ix86_use_fcomi_compare (code)))
14371 op0 = force_reg (op_mode, op0);
14372 op1 = force_reg (op_mode, op1);
14376 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14377 things around if they appear profitable, otherwise force op0
14378 into a register. */
14380 if (standard_80387_constant_p (op0) == 0
14382 && ! (standard_80387_constant_p (op1) == 0
14386 tmp = op0, op0 = op1, op1 = tmp;
14387 code = swap_condition (code);
14391 op0 = force_reg (op_mode, op0);
14393 if (CONSTANT_P (op1))
14395 int tmp = standard_80387_constant_p (op1);
14397 op1 = validize_mem (force_const_mem (op_mode, op1));
14401 op1 = force_reg (op_mode, op1);
14404 op1 = force_reg (op_mode, op1);
14408 /* Try to rearrange the comparison to make it cheaper. */
14409 if (ix86_fp_comparison_cost (code)
14410 > ix86_fp_comparison_cost (swap_condition (code))
14411 && (REG_P (op1) || can_create_pseudo_p ()))
14414 tmp = op0, op0 = op1, op1 = tmp;
14415 code = swap_condition (code);
14417 op0 = force_reg (op_mode, op0);
14425 /* Convert comparison codes we use to represent FP comparison to integer
14426 code that will result in proper branch. Return UNKNOWN if no such code
14430 ix86_fp_compare_code_to_integer (enum rtx_code code)
14459 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14462 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
14463 rtx *second_test, rtx *bypass_test)
14465 enum machine_mode fpcmp_mode, intcmp_mode;
14467 int cost = ix86_fp_comparison_cost (code);
14468 enum rtx_code bypass_code, first_code, second_code;
14470 fpcmp_mode = ix86_fp_compare_mode (code);
14471 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14474 *second_test = NULL_RTX;
14476 *bypass_test = NULL_RTX;
14478 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14480 /* Do fcomi/sahf based test when profitable. */
14481 if (ix86_fp_comparison_arithmetics_cost (code) > cost
14482 && (bypass_code == UNKNOWN || bypass_test)
14483 && (second_code == UNKNOWN || second_test))
14485 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14486 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14492 gcc_assert (TARGET_SAHF);
14495 scratch = gen_reg_rtx (HImode);
14496 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14498 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14501 /* The FP codes work out to act like unsigned. */
14502 intcmp_mode = fpcmp_mode;
14504 if (bypass_code != UNKNOWN)
14505 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14506 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14508 if (second_code != UNKNOWN)
14509 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14510 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14515 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14516 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14517 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14519 scratch = gen_reg_rtx (HImode);
14520 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14522 /* In the unordered case, we have to check C2 for NaN's, which
14523 doesn't happen to work out to anything nice combination-wise.
14524 So do some bit twiddling on the value we've got in AH to come
14525 up with an appropriate set of condition codes. */
14527 intcmp_mode = CCNOmode;
14532 if (code == GT || !TARGET_IEEE_FP)
14534 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14539 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14540 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14541 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14542 intcmp_mode = CCmode;
14548 if (code == LT && TARGET_IEEE_FP)
14550 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14551 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14552 intcmp_mode = CCmode;
14557 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14563 if (code == GE || !TARGET_IEEE_FP)
14565 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14570 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14571 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14578 if (code == LE && TARGET_IEEE_FP)
14580 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14581 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14582 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14583 intcmp_mode = CCmode;
14588 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14594 if (code == EQ && TARGET_IEEE_FP)
14596 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14597 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14598 intcmp_mode = CCmode;
14603 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14610 if (code == NE && TARGET_IEEE_FP)
14612 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14613 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14619 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14625 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14629 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14634 gcc_unreachable ();
14638 /* Return the test that should be put into the flags user, i.e.
14639 the bcc, scc, or cmov instruction. */
14640 return gen_rtx_fmt_ee (code, VOIDmode,
14641 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14646 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14649 op0 = ix86_compare_op0;
14650 op1 = ix86_compare_op1;
14653 *second_test = NULL_RTX;
14655 *bypass_test = NULL_RTX;
14657 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14658 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14660 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14662 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14663 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14664 second_test, bypass_test);
14667 ret = ix86_expand_int_compare (code, op0, op1);
14672 /* Return true if the CODE will result in nontrivial jump sequence. */
14674 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14676 enum rtx_code bypass_code, first_code, second_code;
14679 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14680 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14684 ix86_expand_branch (enum rtx_code code, rtx label)
14688 switch (GET_MODE (ix86_compare_op0))
14694 tmp = ix86_expand_compare (code, NULL, NULL);
14695 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14696 gen_rtx_LABEL_REF (VOIDmode, label),
14698 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14707 enum rtx_code bypass_code, first_code, second_code;
14709 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14710 &ix86_compare_op1);
14712 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14714 /* Check whether we will use the natural sequence with one jump. If
14715 so, we can expand jump early. Otherwise delay expansion by
14716 creating compound insn to not confuse optimizers. */
14717 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14719 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14720 gen_rtx_LABEL_REF (VOIDmode, label),
14721 pc_rtx, NULL_RTX, NULL_RTX);
14725 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14726 ix86_compare_op0, ix86_compare_op1);
14727 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14728 gen_rtx_LABEL_REF (VOIDmode, label),
14730 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14732 use_fcomi = ix86_use_fcomi_compare (code);
14733 vec = rtvec_alloc (3 + !use_fcomi);
14734 RTVEC_ELT (vec, 0) = tmp;
14736 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14738 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14741 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14743 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14752 /* Expand DImode branch into multiple compare+branch. */
14754 rtx lo[2], hi[2], label2;
14755 enum rtx_code code1, code2, code3;
14756 enum machine_mode submode;
14758 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14760 tmp = ix86_compare_op0;
14761 ix86_compare_op0 = ix86_compare_op1;
14762 ix86_compare_op1 = tmp;
14763 code = swap_condition (code);
14765 if (GET_MODE (ix86_compare_op0) == DImode)
14767 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14768 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14773 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14774 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14778 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14779 avoid two branches. This costs one extra insn, so disable when
14780 optimizing for size. */
14782 if ((code == EQ || code == NE)
14783 && (!optimize_insn_for_size_p ()
14784 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14789 if (hi[1] != const0_rtx)
14790 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14791 NULL_RTX, 0, OPTAB_WIDEN);
14794 if (lo[1] != const0_rtx)
14795 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14796 NULL_RTX, 0, OPTAB_WIDEN);
14798 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14799 NULL_RTX, 0, OPTAB_WIDEN);
14801 ix86_compare_op0 = tmp;
14802 ix86_compare_op1 = const0_rtx;
14803 ix86_expand_branch (code, label);
14807 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14808 op1 is a constant and the low word is zero, then we can just
14809 examine the high word. Similarly for low word -1 and
14810 less-or-equal-than or greater-than. */
14812 if (CONST_INT_P (hi[1]))
14815 case LT: case LTU: case GE: case GEU:
14816 if (lo[1] == const0_rtx)
14818 ix86_compare_op0 = hi[0];
14819 ix86_compare_op1 = hi[1];
14820 ix86_expand_branch (code, label);
14824 case LE: case LEU: case GT: case GTU:
14825 if (lo[1] == constm1_rtx)
14827 ix86_compare_op0 = hi[0];
14828 ix86_compare_op1 = hi[1];
14829 ix86_expand_branch (code, label);
14837 /* Otherwise, we need two or three jumps. */
14839 label2 = gen_label_rtx ();
14842 code2 = swap_condition (code);
14843 code3 = unsigned_condition (code);
14847 case LT: case GT: case LTU: case GTU:
14850 case LE: code1 = LT; code2 = GT; break;
14851 case GE: code1 = GT; code2 = LT; break;
14852 case LEU: code1 = LTU; code2 = GTU; break;
14853 case GEU: code1 = GTU; code2 = LTU; break;
14855 case EQ: code1 = UNKNOWN; code2 = NE; break;
14856 case NE: code2 = UNKNOWN; break;
14859 gcc_unreachable ();
14864 * if (hi(a) < hi(b)) goto true;
14865 * if (hi(a) > hi(b)) goto false;
14866 * if (lo(a) < lo(b)) goto true;
14870 ix86_compare_op0 = hi[0];
14871 ix86_compare_op1 = hi[1];
14873 if (code1 != UNKNOWN)
14874 ix86_expand_branch (code1, label);
14875 if (code2 != UNKNOWN)
14876 ix86_expand_branch (code2, label2);
14878 ix86_compare_op0 = lo[0];
14879 ix86_compare_op1 = lo[1];
14880 ix86_expand_branch (code3, label);
14882 if (code2 != UNKNOWN)
14883 emit_label (label2);
14888 /* If we have already emitted a compare insn, go straight to simple.
14889 ix86_expand_compare won't emit anything if ix86_compare_emitted
14891 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
14896 /* Split branch based on floating point condition. */
14898 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14899 rtx target1, rtx target2, rtx tmp, rtx pushed)
14901 rtx second, bypass;
14902 rtx label = NULL_RTX;
14904 int bypass_probability = -1, second_probability = -1, probability = -1;
14907 if (target2 != pc_rtx)
14910 code = reverse_condition_maybe_unordered (code);
14915 condition = ix86_expand_fp_compare (code, op1, op2,
14916 tmp, &second, &bypass);
14918 /* Remove pushed operand from stack. */
14920 ix86_free_from_memory (GET_MODE (pushed));
14922 if (split_branch_probability >= 0)
14924 /* Distribute the probabilities across the jumps.
14925 Assume the BYPASS and SECOND to be always test
14927 probability = split_branch_probability;
14929 /* Value of 1 is low enough to make no need for probability
14930 to be updated. Later we may run some experiments and see
14931 if unordered values are more frequent in practice. */
14933 bypass_probability = 1;
14935 second_probability = 1;
14937 if (bypass != NULL_RTX)
14939 label = gen_label_rtx ();
14940 i = emit_jump_insn (gen_rtx_SET
14942 gen_rtx_IF_THEN_ELSE (VOIDmode,
14944 gen_rtx_LABEL_REF (VOIDmode,
14947 if (bypass_probability >= 0)
14948 add_reg_note (i, REG_BR_PROB, GEN_INT (bypass_probability));
14950 i = emit_jump_insn (gen_rtx_SET
14952 gen_rtx_IF_THEN_ELSE (VOIDmode,
14953 condition, target1, target2)));
14954 if (probability >= 0)
14955 add_reg_note (i, REG_BR_PROB, GEN_INT (probability));
14956 if (second != NULL_RTX)
14958 i = emit_jump_insn (gen_rtx_SET
14960 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14962 if (second_probability >= 0)
14963 add_reg_note (i, REG_BR_PROB, GEN_INT (second_probability));
14965 if (label != NULL_RTX)
14966 emit_label (label);
14970 ix86_expand_setcc (enum rtx_code code, rtx dest)
14972 rtx ret, tmp, tmpreg, equiv;
14973 rtx second_test, bypass_test;
14975 gcc_assert (GET_MODE (dest) == QImode);
14977 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14978 PUT_MODE (ret, QImode);
14983 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14984 if (bypass_test || second_test)
14986 rtx test = second_test;
14988 rtx tmp2 = gen_reg_rtx (QImode);
14991 gcc_assert (!second_test);
14992 test = bypass_test;
14994 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14996 PUT_MODE (test, QImode);
14997 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
15000 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
15002 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
15005 /* Attach a REG_EQUAL note describing the comparison result. */
15006 if (ix86_compare_op0 && ix86_compare_op1)
15008 equiv = simplify_gen_relational (code, QImode,
15009 GET_MODE (ix86_compare_op0),
15010 ix86_compare_op0, ix86_compare_op1);
15011 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
15015 /* Expand comparison setting or clearing carry flag. Return true when
15016 successful and set pop for the operation. */
15018 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15020 enum machine_mode mode =
15021 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15023 /* Do not handle DImode compares that go through special path. */
15024 if (mode == (TARGET_64BIT ? TImode : DImode))
15027 if (SCALAR_FLOAT_MODE_P (mode))
15029 rtx second_test = NULL, bypass_test = NULL;
15030 rtx compare_op, compare_seq;
15032 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15034 /* Shortcut: following common codes never translate
15035 into carry flag compares. */
15036 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15037 || code == ORDERED || code == UNORDERED)
15040 /* These comparisons require zero flag; swap operands so they won't. */
15041 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15042 && !TARGET_IEEE_FP)
15047 code = swap_condition (code);
15050 /* Try to expand the comparison and verify that we end up with
15051 carry flag based comparison. This fails to be true only when
15052 we decide to expand comparison using arithmetic that is not
15053 too common scenario. */
15055 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
15056 &second_test, &bypass_test);
15057 compare_seq = get_insns ();
15060 if (second_test || bypass_test)
15063 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15064 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15065 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15067 code = GET_CODE (compare_op);
15069 if (code != LTU && code != GEU)
15072 emit_insn (compare_seq);
15077 if (!INTEGRAL_MODE_P (mode))
15086 /* Convert a==0 into (unsigned)a<1. */
15089 if (op1 != const0_rtx)
15092 code = (code == EQ ? LTU : GEU);
15095 /* Convert a>b into b<a or a>=b-1. */
15098 if (CONST_INT_P (op1))
15100 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15101 /* Bail out on overflow. We still can swap operands but that
15102 would force loading of the constant into register. */
15103 if (op1 == const0_rtx
15104 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15106 code = (code == GTU ? GEU : LTU);
15113 code = (code == GTU ? LTU : GEU);
15117 /* Convert a>=0 into (unsigned)a<0x80000000. */
15120 if (mode == DImode || op1 != const0_rtx)
15122 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15123 code = (code == LT ? GEU : LTU);
15127 if (mode == DImode || op1 != constm1_rtx)
15129 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15130 code = (code == LE ? GEU : LTU);
15136 /* Swapping operands may cause constant to appear as first operand. */
15137 if (!nonimmediate_operand (op0, VOIDmode))
15139 if (!can_create_pseudo_p ())
15141 op0 = force_reg (mode, op0);
15143 ix86_compare_op0 = op0;
15144 ix86_compare_op1 = op1;
15145 *pop = ix86_expand_compare (code, NULL, NULL);
15146 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15151 ix86_expand_int_movcc (rtx operands[])
15153 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15154 rtx compare_seq, compare_op;
15155 rtx second_test, bypass_test;
15156 enum machine_mode mode = GET_MODE (operands[0]);
15157 bool sign_bit_compare_p = false;;
15160 ix86_compare_op0 = XEXP (operands[1], 0);
15161 ix86_compare_op1 = XEXP (operands[1], 1);
15162 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15163 compare_seq = get_insns ();
15166 compare_code = GET_CODE (compare_op);
15168 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15169 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15170 sign_bit_compare_p = true;
15172 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15173 HImode insns, we'd be swallowed in word prefix ops. */
15175 if ((mode != HImode || TARGET_FAST_PREFIX)
15176 && (mode != (TARGET_64BIT ? TImode : DImode))
15177 && CONST_INT_P (operands[2])
15178 && CONST_INT_P (operands[3]))
15180 rtx out = operands[0];
15181 HOST_WIDE_INT ct = INTVAL (operands[2]);
15182 HOST_WIDE_INT cf = INTVAL (operands[3]);
15183 HOST_WIDE_INT diff;
15186 /* Sign bit compares are better done using shifts than we do by using
15188 if (sign_bit_compare_p
15189 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15190 ix86_compare_op1, &compare_op))
15192 /* Detect overlap between destination and compare sources. */
15195 if (!sign_bit_compare_p)
15197 bool fpcmp = false;
15199 compare_code = GET_CODE (compare_op);
15201 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15202 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15205 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15208 /* To simplify rest of code, restrict to the GEU case. */
15209 if (compare_code == LTU)
15211 HOST_WIDE_INT tmp = ct;
15214 compare_code = reverse_condition (compare_code);
15215 code = reverse_condition (code);
15220 PUT_CODE (compare_op,
15221 reverse_condition_maybe_unordered
15222 (GET_CODE (compare_op)));
15224 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15228 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15229 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15230 tmp = gen_reg_rtx (mode);
15232 if (mode == DImode)
15233 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15235 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15239 if (code == GT || code == GE)
15240 code = reverse_condition (code);
15243 HOST_WIDE_INT tmp = ct;
15248 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15249 ix86_compare_op1, VOIDmode, 0, -1);
15262 tmp = expand_simple_binop (mode, PLUS,
15264 copy_rtx (tmp), 1, OPTAB_DIRECT);
15275 tmp = expand_simple_binop (mode, IOR,
15277 copy_rtx (tmp), 1, OPTAB_DIRECT);
15279 else if (diff == -1 && ct)
15289 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15291 tmp = expand_simple_binop (mode, PLUS,
15292 copy_rtx (tmp), GEN_INT (cf),
15293 copy_rtx (tmp), 1, OPTAB_DIRECT);
15301 * andl cf - ct, dest
15311 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15314 tmp = expand_simple_binop (mode, AND,
15316 gen_int_mode (cf - ct, mode),
15317 copy_rtx (tmp), 1, OPTAB_DIRECT);
15319 tmp = expand_simple_binop (mode, PLUS,
15320 copy_rtx (tmp), GEN_INT (ct),
15321 copy_rtx (tmp), 1, OPTAB_DIRECT);
15324 if (!rtx_equal_p (tmp, out))
15325 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15327 return 1; /* DONE */
15332 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15335 tmp = ct, ct = cf, cf = tmp;
15338 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15340 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15342 /* We may be reversing unordered compare to normal compare, that
15343 is not valid in general (we may convert non-trapping condition
15344 to trapping one), however on i386 we currently emit all
15345 comparisons unordered. */
15346 compare_code = reverse_condition_maybe_unordered (compare_code);
15347 code = reverse_condition_maybe_unordered (code);
15351 compare_code = reverse_condition (compare_code);
15352 code = reverse_condition (code);
15356 compare_code = UNKNOWN;
15357 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15358 && CONST_INT_P (ix86_compare_op1))
15360 if (ix86_compare_op1 == const0_rtx
15361 && (code == LT || code == GE))
15362 compare_code = code;
15363 else if (ix86_compare_op1 == constm1_rtx)
15367 else if (code == GT)
15372 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15373 if (compare_code != UNKNOWN
15374 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15375 && (cf == -1 || ct == -1))
15377 /* If lea code below could be used, only optimize
15378 if it results in a 2 insn sequence. */
15380 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15381 || diff == 3 || diff == 5 || diff == 9)
15382 || (compare_code == LT && ct == -1)
15383 || (compare_code == GE && cf == -1))
15386 * notl op1 (if necessary)
15394 code = reverse_condition (code);
15397 out = emit_store_flag (out, code, ix86_compare_op0,
15398 ix86_compare_op1, VOIDmode, 0, -1);
15400 out = expand_simple_binop (mode, IOR,
15402 out, 1, OPTAB_DIRECT);
15403 if (out != operands[0])
15404 emit_move_insn (operands[0], out);
15406 return 1; /* DONE */
15411 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15412 || diff == 3 || diff == 5 || diff == 9)
15413 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15415 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15421 * lea cf(dest*(ct-cf)),dest
15425 * This also catches the degenerate setcc-only case.
15431 out = emit_store_flag (out, code, ix86_compare_op0,
15432 ix86_compare_op1, VOIDmode, 0, 1);
15435 /* On x86_64 the lea instruction operates on Pmode, so we need
15436 to get arithmetics done in proper mode to match. */
15438 tmp = copy_rtx (out);
15442 out1 = copy_rtx (out);
15443 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15447 tmp = gen_rtx_PLUS (mode, tmp, out1);
15453 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15456 if (!rtx_equal_p (tmp, out))
15459 out = force_operand (tmp, copy_rtx (out));
15461 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15463 if (!rtx_equal_p (out, operands[0]))
15464 emit_move_insn (operands[0], copy_rtx (out));
15466 return 1; /* DONE */
15470 * General case: Jumpful:
15471 * xorl dest,dest cmpl op1, op2
15472 * cmpl op1, op2 movl ct, dest
15473 * setcc dest jcc 1f
15474 * decl dest movl cf, dest
15475 * andl (cf-ct),dest 1:
15478 * Size 20. Size 14.
15480 * This is reasonably steep, but branch mispredict costs are
15481 * high on modern cpus, so consider failing only if optimizing
15485 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15486 && BRANCH_COST (optimize_insn_for_speed_p (),
15491 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15496 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15498 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15500 /* We may be reversing unordered compare to normal compare,
15501 that is not valid in general (we may convert non-trapping
15502 condition to trapping one), however on i386 we currently
15503 emit all comparisons unordered. */
15504 code = reverse_condition_maybe_unordered (code);
15508 code = reverse_condition (code);
15509 if (compare_code != UNKNOWN)
15510 compare_code = reverse_condition (compare_code);
15514 if (compare_code != UNKNOWN)
15516 /* notl op1 (if needed)
15521 For x < 0 (resp. x <= -1) there will be no notl,
15522 so if possible swap the constants to get rid of the
15524 True/false will be -1/0 while code below (store flag
15525 followed by decrement) is 0/-1, so the constants need
15526 to be exchanged once more. */
15528 if (compare_code == GE || !cf)
15530 code = reverse_condition (code);
15535 HOST_WIDE_INT tmp = cf;
15540 out = emit_store_flag (out, code, ix86_compare_op0,
15541 ix86_compare_op1, VOIDmode, 0, -1);
15545 out = emit_store_flag (out, code, ix86_compare_op0,
15546 ix86_compare_op1, VOIDmode, 0, 1);
15548 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15549 copy_rtx (out), 1, OPTAB_DIRECT);
15552 out = expand_simple_binop (mode, AND, copy_rtx (out),
15553 gen_int_mode (cf - ct, mode),
15554 copy_rtx (out), 1, OPTAB_DIRECT);
15556 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15557 copy_rtx (out), 1, OPTAB_DIRECT);
15558 if (!rtx_equal_p (out, operands[0]))
15559 emit_move_insn (operands[0], copy_rtx (out));
15561 return 1; /* DONE */
15565 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15567 /* Try a few things more with specific constants and a variable. */
15570 rtx var, orig_out, out, tmp;
15572 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15573 return 0; /* FAIL */
15575 /* If one of the two operands is an interesting constant, load a
15576 constant with the above and mask it in with a logical operation. */
15578 if (CONST_INT_P (operands[2]))
15581 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15582 operands[3] = constm1_rtx, op = and_optab;
15583 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15584 operands[3] = const0_rtx, op = ior_optab;
15586 return 0; /* FAIL */
15588 else if (CONST_INT_P (operands[3]))
15591 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15592 operands[2] = constm1_rtx, op = and_optab;
15593 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15594 operands[2] = const0_rtx, op = ior_optab;
15596 return 0; /* FAIL */
15599 return 0; /* FAIL */
15601 orig_out = operands[0];
15602 tmp = gen_reg_rtx (mode);
15605 /* Recurse to get the constant loaded. */
15606 if (ix86_expand_int_movcc (operands) == 0)
15607 return 0; /* FAIL */
15609 /* Mask in the interesting variable. */
15610 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15612 if (!rtx_equal_p (out, orig_out))
15613 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15615 return 1; /* DONE */
15619 * For comparison with above,
15629 if (! nonimmediate_operand (operands[2], mode))
15630 operands[2] = force_reg (mode, operands[2]);
15631 if (! nonimmediate_operand (operands[3], mode))
15632 operands[3] = force_reg (mode, operands[3]);
15634 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15636 rtx tmp = gen_reg_rtx (mode);
15637 emit_move_insn (tmp, operands[3]);
15640 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15642 rtx tmp = gen_reg_rtx (mode);
15643 emit_move_insn (tmp, operands[2]);
15647 if (! register_operand (operands[2], VOIDmode)
15649 || ! register_operand (operands[3], VOIDmode)))
15650 operands[2] = force_reg (mode, operands[2]);
15653 && ! register_operand (operands[3], VOIDmode))
15654 operands[3] = force_reg (mode, operands[3]);
15656 emit_insn (compare_seq);
15657 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15658 gen_rtx_IF_THEN_ELSE (mode,
15659 compare_op, operands[2],
15662 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15663 gen_rtx_IF_THEN_ELSE (mode,
15665 copy_rtx (operands[3]),
15666 copy_rtx (operands[0]))));
15668 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15669 gen_rtx_IF_THEN_ELSE (mode,
15671 copy_rtx (operands[2]),
15672 copy_rtx (operands[0]))));
15674 return 1; /* DONE */
15677 /* Swap, force into registers, or otherwise massage the two operands
15678 to an sse comparison with a mask result. Thus we differ a bit from
15679 ix86_prepare_fp_compare_args which expects to produce a flags result.
15681 The DEST operand exists to help determine whether to commute commutative
15682 operators. The POP0/POP1 operands are updated in place. The new
15683 comparison code is returned, or UNKNOWN if not implementable. */
15685 static enum rtx_code
15686 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15687 rtx *pop0, rtx *pop1)
15695 /* We have no LTGT as an operator. We could implement it with
15696 NE & ORDERED, but this requires an extra temporary. It's
15697 not clear that it's worth it. */
15704 /* These are supported directly. */
15711 /* For commutative operators, try to canonicalize the destination
15712 operand to be first in the comparison - this helps reload to
15713 avoid extra moves. */
15714 if (!dest || !rtx_equal_p (dest, *pop1))
15722 /* These are not supported directly. Swap the comparison operands
15723 to transform into something that is supported. */
15727 code = swap_condition (code);
15731 gcc_unreachable ();
15737 /* Detect conditional moves that exactly match min/max operational
15738 semantics. Note that this is IEEE safe, as long as we don't
15739 interchange the operands.
15741 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15742 and TRUE if the operation is successful and instructions are emitted. */
15745 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15746 rtx cmp_op1, rtx if_true, rtx if_false)
15748 enum machine_mode mode;
15754 else if (code == UNGE)
15757 if_true = if_false;
15763 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15765 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15770 mode = GET_MODE (dest);
15772 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15773 but MODE may be a vector mode and thus not appropriate. */
15774 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15776 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15779 if_true = force_reg (mode, if_true);
15780 v = gen_rtvec (2, if_true, if_false);
15781 tmp = gen_rtx_UNSPEC (mode, v, u);
15785 code = is_min ? SMIN : SMAX;
15786 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15789 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15793 /* Expand an sse vector comparison. Return the register with the result. */
15796 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15797 rtx op_true, rtx op_false)
15799 enum machine_mode mode = GET_MODE (dest);
15802 cmp_op0 = force_reg (mode, cmp_op0);
15803 if (!nonimmediate_operand (cmp_op1, mode))
15804 cmp_op1 = force_reg (mode, cmp_op1);
15807 || reg_overlap_mentioned_p (dest, op_true)
15808 || reg_overlap_mentioned_p (dest, op_false))
15809 dest = gen_reg_rtx (mode);
15811 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15812 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15817 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15818 operations. This is used for both scalar and vector conditional moves. */
15821 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15823 enum machine_mode mode = GET_MODE (dest);
15826 if (op_false == CONST0_RTX (mode))
15828 op_true = force_reg (mode, op_true);
15829 x = gen_rtx_AND (mode, cmp, op_true);
15830 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15832 else if (op_true == CONST0_RTX (mode))
15834 op_false = force_reg (mode, op_false);
15835 x = gen_rtx_NOT (mode, cmp);
15836 x = gen_rtx_AND (mode, x, op_false);
15837 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15839 else if (TARGET_SSE5)
15841 rtx pcmov = gen_rtx_SET (mode, dest,
15842 gen_rtx_IF_THEN_ELSE (mode, cmp,
15849 op_true = force_reg (mode, op_true);
15850 op_false = force_reg (mode, op_false);
15852 t2 = gen_reg_rtx (mode);
15854 t3 = gen_reg_rtx (mode);
15858 x = gen_rtx_AND (mode, op_true, cmp);
15859 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15861 x = gen_rtx_NOT (mode, cmp);
15862 x = gen_rtx_AND (mode, x, op_false);
15863 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15865 x = gen_rtx_IOR (mode, t3, t2);
15866 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15870 /* Expand a floating-point conditional move. Return true if successful. */
15873 ix86_expand_fp_movcc (rtx operands[])
15875 enum machine_mode mode = GET_MODE (operands[0]);
15876 enum rtx_code code = GET_CODE (operands[1]);
15877 rtx tmp, compare_op, second_test, bypass_test;
15879 ix86_compare_op0 = XEXP (operands[1], 0);
15880 ix86_compare_op1 = XEXP (operands[1], 1);
15881 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15883 enum machine_mode cmode;
15885 /* Since we've no cmove for sse registers, don't force bad register
15886 allocation just to gain access to it. Deny movcc when the
15887 comparison mode doesn't match the move mode. */
15888 cmode = GET_MODE (ix86_compare_op0);
15889 if (cmode == VOIDmode)
15890 cmode = GET_MODE (ix86_compare_op1);
15894 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15896 &ix86_compare_op1);
15897 if (code == UNKNOWN)
15900 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15901 ix86_compare_op1, operands[2],
15905 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15906 ix86_compare_op1, operands[2], operands[3]);
15907 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15911 /* The floating point conditional move instructions don't directly
15912 support conditions resulting from a signed integer comparison. */
15914 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15916 /* The floating point conditional move instructions don't directly
15917 support signed integer comparisons. */
15919 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15921 gcc_assert (!second_test && !bypass_test);
15922 tmp = gen_reg_rtx (QImode);
15923 ix86_expand_setcc (code, tmp);
15925 ix86_compare_op0 = tmp;
15926 ix86_compare_op1 = const0_rtx;
15927 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15929 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15931 tmp = gen_reg_rtx (mode);
15932 emit_move_insn (tmp, operands[3]);
15935 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15937 tmp = gen_reg_rtx (mode);
15938 emit_move_insn (tmp, operands[2]);
15942 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15943 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15944 operands[2], operands[3])));
15946 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15947 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15948 operands[3], operands[0])));
15950 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15951 gen_rtx_IF_THEN_ELSE (mode, second_test,
15952 operands[2], operands[0])));
15957 /* Expand a floating-point vector conditional move; a vcond operation
15958 rather than a movcc operation. */
15961 ix86_expand_fp_vcond (rtx operands[])
15963 enum rtx_code code = GET_CODE (operands[3]);
15966 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15967 &operands[4], &operands[5]);
15968 if (code == UNKNOWN)
15971 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15972 operands[5], operands[1], operands[2]))
15975 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15976 operands[1], operands[2]);
15977 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15981 /* Expand a signed/unsigned integral vector conditional move. */
15984 ix86_expand_int_vcond (rtx operands[])
15986 enum machine_mode mode = GET_MODE (operands[0]);
15987 enum rtx_code code = GET_CODE (operands[3]);
15988 bool negate = false;
15991 cop0 = operands[4];
15992 cop1 = operands[5];
15994 /* SSE5 supports all of the comparisons on all vector int types. */
15997 /* Canonicalize the comparison to EQ, GT, GTU. */
16008 code = reverse_condition (code);
16014 code = reverse_condition (code);
16020 code = swap_condition (code);
16021 x = cop0, cop0 = cop1, cop1 = x;
16025 gcc_unreachable ();
16028 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16029 if (mode == V2DImode)
16034 /* SSE4.1 supports EQ. */
16035 if (!TARGET_SSE4_1)
16041 /* SSE4.2 supports GT/GTU. */
16042 if (!TARGET_SSE4_2)
16047 gcc_unreachable ();
16051 /* Unsigned parallel compare is not supported by the hardware. Play some
16052 tricks to turn this into a signed comparison against 0. */
16055 cop0 = force_reg (mode, cop0);
16064 /* Perform a parallel modulo subtraction. */
16065 t1 = gen_reg_rtx (mode);
16066 emit_insn ((mode == V4SImode
16068 : gen_subv2di3) (t1, cop0, cop1));
16070 /* Extract the original sign bit of op0. */
16071 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16073 t2 = gen_reg_rtx (mode);
16074 emit_insn ((mode == V4SImode
16076 : gen_andv2di3) (t2, cop0, mask));
16078 /* XOR it back into the result of the subtraction. This results
16079 in the sign bit set iff we saw unsigned underflow. */
16080 x = gen_reg_rtx (mode);
16081 emit_insn ((mode == V4SImode
16083 : gen_xorv2di3) (x, t1, t2));
16091 /* Perform a parallel unsigned saturating subtraction. */
16092 x = gen_reg_rtx (mode);
16093 emit_insn (gen_rtx_SET (VOIDmode, x,
16094 gen_rtx_US_MINUS (mode, cop0, cop1)));
16101 gcc_unreachable ();
16105 cop1 = CONST0_RTX (mode);
16109 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16110 operands[1+negate], operands[2-negate]);
16112 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16113 operands[2-negate]);
16117 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16118 true if we should do zero extension, else sign extension. HIGH_P is
16119 true if we want the N/2 high elements, else the low elements. */
16122 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16124 enum machine_mode imode = GET_MODE (operands[1]);
16125 rtx (*unpack)(rtx, rtx, rtx);
16132 unpack = gen_vec_interleave_highv16qi;
16134 unpack = gen_vec_interleave_lowv16qi;
16138 unpack = gen_vec_interleave_highv8hi;
16140 unpack = gen_vec_interleave_lowv8hi;
16144 unpack = gen_vec_interleave_highv4si;
16146 unpack = gen_vec_interleave_lowv4si;
16149 gcc_unreachable ();
16152 dest = gen_lowpart (imode, operands[0]);
16155 se = force_reg (imode, CONST0_RTX (imode));
16157 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16158 operands[1], pc_rtx, pc_rtx);
16160 emit_insn (unpack (dest, operands[1], se));
16163 /* This function performs the same task as ix86_expand_sse_unpack,
16164 but with SSE4.1 instructions. */
16167 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16169 enum machine_mode imode = GET_MODE (operands[1]);
16170 rtx (*unpack)(rtx, rtx);
16177 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16179 unpack = gen_sse4_1_extendv8qiv8hi2;
16183 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16185 unpack = gen_sse4_1_extendv4hiv4si2;
16189 unpack = gen_sse4_1_zero_extendv2siv2di2;
16191 unpack = gen_sse4_1_extendv2siv2di2;
16194 gcc_unreachable ();
16197 dest = operands[0];
16200 /* Shift higher 8 bytes to lower 8 bytes. */
16201 src = gen_reg_rtx (imode);
16202 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16203 gen_lowpart (TImode, operands[1]),
16209 emit_insn (unpack (dest, src));
16212 /* This function performs the same task as ix86_expand_sse_unpack,
16213 but with sse5 instructions. */
16216 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16218 enum machine_mode imode = GET_MODE (operands[1]);
16219 int pperm_bytes[16];
16221 int h = (high_p) ? 8 : 0;
16224 rtvec v = rtvec_alloc (16);
16227 rtx op0 = operands[0], op1 = operands[1];
16232 vs = rtvec_alloc (8);
16233 h2 = (high_p) ? 8 : 0;
16234 for (i = 0; i < 8; i++)
16236 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
16237 pperm_bytes[2*i+1] = ((unsigned_p)
16239 : PPERM_SIGN | PPERM_SRC2 | i | h);
16242 for (i = 0; i < 16; i++)
16243 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16245 for (i = 0; i < 8; i++)
16246 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16248 p = gen_rtx_PARALLEL (VOIDmode, vs);
16249 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16251 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
16253 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
16257 vs = rtvec_alloc (4);
16258 h2 = (high_p) ? 4 : 0;
16259 for (i = 0; i < 4; i++)
16261 sign_extend = ((unsigned_p)
16263 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
16264 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
16265 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
16266 pperm_bytes[4*i+2] = sign_extend;
16267 pperm_bytes[4*i+3] = sign_extend;
16270 for (i = 0; i < 16; i++)
16271 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16273 for (i = 0; i < 4; i++)
16274 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16276 p = gen_rtx_PARALLEL (VOIDmode, vs);
16277 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16279 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
16281 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
16285 vs = rtvec_alloc (2);
16286 h2 = (high_p) ? 2 : 0;
16287 for (i = 0; i < 2; i++)
16289 sign_extend = ((unsigned_p)
16291 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
16292 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
16293 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
16294 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
16295 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
16296 pperm_bytes[8*i+4] = sign_extend;
16297 pperm_bytes[8*i+5] = sign_extend;
16298 pperm_bytes[8*i+6] = sign_extend;
16299 pperm_bytes[8*i+7] = sign_extend;
16302 for (i = 0; i < 16; i++)
16303 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16305 for (i = 0; i < 2; i++)
16306 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16308 p = gen_rtx_PARALLEL (VOIDmode, vs);
16309 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16311 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
16313 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
16317 gcc_unreachable ();
16323 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
16324 next narrower integer vector type */
16326 ix86_expand_sse5_pack (rtx operands[3])
16328 enum machine_mode imode = GET_MODE (operands[0]);
16329 int pperm_bytes[16];
16331 rtvec v = rtvec_alloc (16);
16333 rtx op0 = operands[0];
16334 rtx op1 = operands[1];
16335 rtx op2 = operands[2];
16340 for (i = 0; i < 8; i++)
16342 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
16343 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
16346 for (i = 0; i < 16; i++)
16347 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16349 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16350 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
16354 for (i = 0; i < 4; i++)
16356 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
16357 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
16358 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
16359 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
16362 for (i = 0; i < 16; i++)
16363 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16365 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16366 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
16370 for (i = 0; i < 2; i++)
16372 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
16373 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
16374 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
16375 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
16376 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
16377 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
16378 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
16379 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
16382 for (i = 0; i < 16; i++)
16383 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16385 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16386 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
16390 gcc_unreachable ();
16396 /* Expand conditional increment or decrement using adb/sbb instructions.
16397 The default case using setcc followed by the conditional move can be
16398 done by generic code. */
16400 ix86_expand_int_addcc (rtx operands[])
16402 enum rtx_code code = GET_CODE (operands[1]);
16404 rtx val = const0_rtx;
16405 bool fpcmp = false;
16406 enum machine_mode mode = GET_MODE (operands[0]);
16408 ix86_compare_op0 = XEXP (operands[1], 0);
16409 ix86_compare_op1 = XEXP (operands[1], 1);
16410 if (operands[3] != const1_rtx
16411 && operands[3] != constm1_rtx)
16413 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16414 ix86_compare_op1, &compare_op))
16416 code = GET_CODE (compare_op);
16418 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16419 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16422 code = ix86_fp_compare_code_to_integer (code);
16429 PUT_CODE (compare_op,
16430 reverse_condition_maybe_unordered
16431 (GET_CODE (compare_op)));
16433 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16435 PUT_MODE (compare_op, mode);
16437 /* Construct either adc or sbb insn. */
16438 if ((code == LTU) == (operands[3] == constm1_rtx))
16440 switch (GET_MODE (operands[0]))
16443 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16446 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16449 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16452 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16455 gcc_unreachable ();
16460 switch (GET_MODE (operands[0]))
16463 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16466 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16469 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16472 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16475 gcc_unreachable ();
16478 return 1; /* DONE */
16482 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16483 works for floating pointer parameters and nonoffsetable memories.
16484 For pushes, it returns just stack offsets; the values will be saved
16485 in the right order. Maximally three parts are generated. */
16488 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16493 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16495 size = (GET_MODE_SIZE (mode) + 4) / 8;
16497 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16498 gcc_assert (size >= 2 && size <= 4);
16500 /* Optimize constant pool reference to immediates. This is used by fp
16501 moves, that force all constants to memory to allow combining. */
16502 if (MEM_P (operand) && MEM_READONLY_P (operand))
16504 rtx tmp = maybe_get_pool_constant (operand);
16509 if (MEM_P (operand) && !offsettable_memref_p (operand))
16511 /* The only non-offsetable memories we handle are pushes. */
16512 int ok = push_operand (operand, VOIDmode);
16516 operand = copy_rtx (operand);
16517 PUT_MODE (operand, Pmode);
16518 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16522 if (GET_CODE (operand) == CONST_VECTOR)
16524 enum machine_mode imode = int_mode_for_mode (mode);
16525 /* Caution: if we looked through a constant pool memory above,
16526 the operand may actually have a different mode now. That's
16527 ok, since we want to pun this all the way back to an integer. */
16528 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16529 gcc_assert (operand != NULL);
16535 if (mode == DImode)
16536 split_di (&operand, 1, &parts[0], &parts[1]);
16541 if (REG_P (operand))
16543 gcc_assert (reload_completed);
16544 for (i = 0; i < size; i++)
16545 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16547 else if (offsettable_memref_p (operand))
16549 operand = adjust_address (operand, SImode, 0);
16550 parts[0] = operand;
16551 for (i = 1; i < size; i++)
16552 parts[i] = adjust_address (operand, SImode, 4 * i);
16554 else if (GET_CODE (operand) == CONST_DOUBLE)
16559 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16563 real_to_target (l, &r, mode);
16564 parts[3] = gen_int_mode (l[3], SImode);
16565 parts[2] = gen_int_mode (l[2], SImode);
16568 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16569 parts[2] = gen_int_mode (l[2], SImode);
16572 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16575 gcc_unreachable ();
16577 parts[1] = gen_int_mode (l[1], SImode);
16578 parts[0] = gen_int_mode (l[0], SImode);
16581 gcc_unreachable ();
16586 if (mode == TImode)
16587 split_ti (&operand, 1, &parts[0], &parts[1]);
16588 if (mode == XFmode || mode == TFmode)
16590 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16591 if (REG_P (operand))
16593 gcc_assert (reload_completed);
16594 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16595 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16597 else if (offsettable_memref_p (operand))
16599 operand = adjust_address (operand, DImode, 0);
16600 parts[0] = operand;
16601 parts[1] = adjust_address (operand, upper_mode, 8);
16603 else if (GET_CODE (operand) == CONST_DOUBLE)
16608 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16609 real_to_target (l, &r, mode);
16611 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16612 if (HOST_BITS_PER_WIDE_INT >= 64)
16615 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16616 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16619 parts[0] = immed_double_const (l[0], l[1], DImode);
16621 if (upper_mode == SImode)
16622 parts[1] = gen_int_mode (l[2], SImode);
16623 else if (HOST_BITS_PER_WIDE_INT >= 64)
16626 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16627 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16630 parts[1] = immed_double_const (l[2], l[3], DImode);
16633 gcc_unreachable ();
16640 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16641 Return false when normal moves are needed; true when all required
16642 insns have been emitted. Operands 2-4 contain the input values
16643 int the correct order; operands 5-7 contain the output values. */
16646 ix86_split_long_move (rtx operands[])
16651 int collisions = 0;
16652 enum machine_mode mode = GET_MODE (operands[0]);
16653 bool collisionparts[4];
16655 /* The DFmode expanders may ask us to move double.
16656 For 64bit target this is single move. By hiding the fact
16657 here we simplify i386.md splitters. */
16658 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16660 /* Optimize constant pool reference to immediates. This is used by
16661 fp moves, that force all constants to memory to allow combining. */
16663 if (MEM_P (operands[1])
16664 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16665 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16666 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16667 if (push_operand (operands[0], VOIDmode))
16669 operands[0] = copy_rtx (operands[0]);
16670 PUT_MODE (operands[0], Pmode);
16673 operands[0] = gen_lowpart (DImode, operands[0]);
16674 operands[1] = gen_lowpart (DImode, operands[1]);
16675 emit_move_insn (operands[0], operands[1]);
16679 /* The only non-offsettable memory we handle is push. */
16680 if (push_operand (operands[0], VOIDmode))
16683 gcc_assert (!MEM_P (operands[0])
16684 || offsettable_memref_p (operands[0]));
16686 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16687 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16689 /* When emitting push, take care for source operands on the stack. */
16690 if (push && MEM_P (operands[1])
16691 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16692 for (i = 0; i < nparts - 1; i++)
16693 part[1][i] = change_address (part[1][i],
16694 GET_MODE (part[1][i]),
16695 XEXP (part[1][i + 1], 0));
16697 /* We need to do copy in the right order in case an address register
16698 of the source overlaps the destination. */
16699 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16703 for (i = 0; i < nparts; i++)
16706 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16707 if (collisionparts[i])
16711 /* Collision in the middle part can be handled by reordering. */
16712 if (collisions == 1 && nparts == 3 && collisionparts [1])
16714 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16715 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16717 else if (collisions == 1
16719 && (collisionparts [1] || collisionparts [2]))
16721 if (collisionparts [1])
16723 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16724 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16728 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16729 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16733 /* If there are more collisions, we can't handle it by reordering.
16734 Do an lea to the last part and use only one colliding move. */
16735 else if (collisions > 1)
16741 base = part[0][nparts - 1];
16743 /* Handle the case when the last part isn't valid for lea.
16744 Happens in 64-bit mode storing the 12-byte XFmode. */
16745 if (GET_MODE (base) != Pmode)
16746 base = gen_rtx_REG (Pmode, REGNO (base));
16748 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16749 part[1][0] = replace_equiv_address (part[1][0], base);
16750 for (i = 1; i < nparts; i++)
16752 tmp = plus_constant (base, UNITS_PER_WORD * i);
16753 part[1][i] = replace_equiv_address (part[1][i], tmp);
16764 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16765 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16766 emit_move_insn (part[0][2], part[1][2]);
16768 else if (nparts == 4)
16770 emit_move_insn (part[0][3], part[1][3]);
16771 emit_move_insn (part[0][2], part[1][2]);
16776 /* In 64bit mode we don't have 32bit push available. In case this is
16777 register, it is OK - we will just use larger counterpart. We also
16778 retype memory - these comes from attempt to avoid REX prefix on
16779 moving of second half of TFmode value. */
16780 if (GET_MODE (part[1][1]) == SImode)
16782 switch (GET_CODE (part[1][1]))
16785 part[1][1] = adjust_address (part[1][1], DImode, 0);
16789 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16793 gcc_unreachable ();
16796 if (GET_MODE (part[1][0]) == SImode)
16797 part[1][0] = part[1][1];
16800 emit_move_insn (part[0][1], part[1][1]);
16801 emit_move_insn (part[0][0], part[1][0]);
16805 /* Choose correct order to not overwrite the source before it is copied. */
16806 if ((REG_P (part[0][0])
16807 && REG_P (part[1][1])
16808 && (REGNO (part[0][0]) == REGNO (part[1][1])
16810 && REGNO (part[0][0]) == REGNO (part[1][2]))
16812 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16814 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16816 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16818 operands[2 + i] = part[0][j];
16819 operands[6 + i] = part[1][j];
16824 for (i = 0; i < nparts; i++)
16826 operands[2 + i] = part[0][i];
16827 operands[6 + i] = part[1][i];
16831 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16832 if (optimize_insn_for_size_p ())
16834 for (j = 0; j < nparts - 1; j++)
16835 if (CONST_INT_P (operands[6 + j])
16836 && operands[6 + j] != const0_rtx
16837 && REG_P (operands[2 + j]))
16838 for (i = j; i < nparts - 1; i++)
16839 if (CONST_INT_P (operands[7 + i])
16840 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16841 operands[7 + i] = operands[2 + j];
16844 for (i = 0; i < nparts; i++)
16845 emit_move_insn (operands[2 + i], operands[6 + i]);
16850 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16851 left shift by a constant, either using a single shift or
16852 a sequence of add instructions. */
16855 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16859 emit_insn ((mode == DImode
16861 : gen_adddi3) (operand, operand, operand));
16863 else if (!optimize_insn_for_size_p ()
16864 && count * ix86_cost->add <= ix86_cost->shift_const)
16867 for (i=0; i<count; i++)
16869 emit_insn ((mode == DImode
16871 : gen_adddi3) (operand, operand, operand));
16875 emit_insn ((mode == DImode
16877 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16881 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16883 rtx low[2], high[2];
16885 const int single_width = mode == DImode ? 32 : 64;
16887 if (CONST_INT_P (operands[2]))
16889 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16890 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16892 if (count >= single_width)
16894 emit_move_insn (high[0], low[1]);
16895 emit_move_insn (low[0], const0_rtx);
16897 if (count > single_width)
16898 ix86_expand_ashl_const (high[0], count - single_width, mode);
16902 if (!rtx_equal_p (operands[0], operands[1]))
16903 emit_move_insn (operands[0], operands[1]);
16904 emit_insn ((mode == DImode
16906 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16907 ix86_expand_ashl_const (low[0], count, mode);
16912 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16914 if (operands[1] == const1_rtx)
16916 /* Assuming we've chosen a QImode capable registers, then 1 << N
16917 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16918 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16920 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16922 ix86_expand_clear (low[0]);
16923 ix86_expand_clear (high[0]);
16924 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16926 d = gen_lowpart (QImode, low[0]);
16927 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16928 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16929 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16931 d = gen_lowpart (QImode, high[0]);
16932 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16933 s = gen_rtx_NE (QImode, flags, const0_rtx);
16934 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16937 /* Otherwise, we can get the same results by manually performing
16938 a bit extract operation on bit 5/6, and then performing the two
16939 shifts. The two methods of getting 0/1 into low/high are exactly
16940 the same size. Avoiding the shift in the bit extract case helps
16941 pentium4 a bit; no one else seems to care much either way. */
16946 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16947 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16949 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16950 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16952 emit_insn ((mode == DImode
16954 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16955 emit_insn ((mode == DImode
16957 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16958 emit_move_insn (low[0], high[0]);
16959 emit_insn ((mode == DImode
16961 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16964 emit_insn ((mode == DImode
16966 : gen_ashldi3) (low[0], low[0], operands[2]));
16967 emit_insn ((mode == DImode
16969 : gen_ashldi3) (high[0], high[0], operands[2]));
16973 if (operands[1] == constm1_rtx)
16975 /* For -1 << N, we can avoid the shld instruction, because we
16976 know that we're shifting 0...31/63 ones into a -1. */
16977 emit_move_insn (low[0], constm1_rtx);
16978 if (optimize_insn_for_size_p ())
16979 emit_move_insn (high[0], low[0]);
16981 emit_move_insn (high[0], constm1_rtx);
16985 if (!rtx_equal_p (operands[0], operands[1]))
16986 emit_move_insn (operands[0], operands[1]);
16988 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16989 emit_insn ((mode == DImode
16991 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16994 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16996 if (TARGET_CMOVE && scratch)
16998 ix86_expand_clear (scratch);
16999 emit_insn ((mode == DImode
17000 ? gen_x86_shift_adj_1
17001 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
17005 emit_insn ((mode == DImode
17006 ? gen_x86_shift_adj_2
17007 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
17011 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
17013 rtx low[2], high[2];
17015 const int single_width = mode == DImode ? 32 : 64;
17017 if (CONST_INT_P (operands[2]))
17019 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17020 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17022 if (count == single_width * 2 - 1)
17024 emit_move_insn (high[0], high[1]);
17025 emit_insn ((mode == DImode
17027 : gen_ashrdi3) (high[0], high[0],
17028 GEN_INT (single_width - 1)));
17029 emit_move_insn (low[0], high[0]);
17032 else if (count >= single_width)
17034 emit_move_insn (low[0], high[1]);
17035 emit_move_insn (high[0], low[0]);
17036 emit_insn ((mode == DImode
17038 : gen_ashrdi3) (high[0], high[0],
17039 GEN_INT (single_width - 1)));
17040 if (count > single_width)
17041 emit_insn ((mode == DImode
17043 : gen_ashrdi3) (low[0], low[0],
17044 GEN_INT (count - single_width)));
17048 if (!rtx_equal_p (operands[0], operands[1]))
17049 emit_move_insn (operands[0], operands[1]);
17050 emit_insn ((mode == DImode
17052 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17053 emit_insn ((mode == DImode
17055 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
17060 if (!rtx_equal_p (operands[0], operands[1]))
17061 emit_move_insn (operands[0], operands[1]);
17063 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17065 emit_insn ((mode == DImode
17067 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17068 emit_insn ((mode == DImode
17070 : gen_ashrdi3) (high[0], high[0], operands[2]));
17072 if (TARGET_CMOVE && scratch)
17074 emit_move_insn (scratch, high[0]);
17075 emit_insn ((mode == DImode
17077 : gen_ashrdi3) (scratch, scratch,
17078 GEN_INT (single_width - 1)));
17079 emit_insn ((mode == DImode
17080 ? gen_x86_shift_adj_1
17081 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17085 emit_insn ((mode == DImode
17086 ? gen_x86_shift_adj_3
17087 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
17092 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
17094 rtx low[2], high[2];
17096 const int single_width = mode == DImode ? 32 : 64;
17098 if (CONST_INT_P (operands[2]))
17100 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17101 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17103 if (count >= single_width)
17105 emit_move_insn (low[0], high[1]);
17106 ix86_expand_clear (high[0]);
17108 if (count > single_width)
17109 emit_insn ((mode == DImode
17111 : gen_lshrdi3) (low[0], low[0],
17112 GEN_INT (count - single_width)));
17116 if (!rtx_equal_p (operands[0], operands[1]))
17117 emit_move_insn (operands[0], operands[1]);
17118 emit_insn ((mode == DImode
17120 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17121 emit_insn ((mode == DImode
17123 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
17128 if (!rtx_equal_p (operands[0], operands[1]))
17129 emit_move_insn (operands[0], operands[1]);
17131 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17133 emit_insn ((mode == DImode
17135 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17136 emit_insn ((mode == DImode
17138 : gen_lshrdi3) (high[0], high[0], operands[2]));
17140 /* Heh. By reversing the arguments, we can reuse this pattern. */
17141 if (TARGET_CMOVE && scratch)
17143 ix86_expand_clear (scratch);
17144 emit_insn ((mode == DImode
17145 ? gen_x86_shift_adj_1
17146 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17150 emit_insn ((mode == DImode
17151 ? gen_x86_shift_adj_2
17152 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17156 /* Predict just emitted jump instruction to be taken with probability PROB. */
17158 predict_jump (int prob)
17160 rtx insn = get_last_insn ();
17161 gcc_assert (JUMP_P (insn));
17162 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17165 /* Helper function for the string operations below. Dest VARIABLE whether
17166 it is aligned to VALUE bytes. If true, jump to the label. */
17168 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17170 rtx label = gen_label_rtx ();
17171 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17172 if (GET_MODE (variable) == DImode)
17173 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17175 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17176 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17179 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17181 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17185 /* Adjust COUNTER by the VALUE. */
17187 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17189 if (GET_MODE (countreg) == DImode)
17190 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17192 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17195 /* Zero extend possibly SImode EXP to Pmode register. */
17197 ix86_zero_extend_to_Pmode (rtx exp)
17200 if (GET_MODE (exp) == VOIDmode)
17201 return force_reg (Pmode, exp);
17202 if (GET_MODE (exp) == Pmode)
17203 return copy_to_mode_reg (Pmode, exp);
17204 r = gen_reg_rtx (Pmode);
17205 emit_insn (gen_zero_extendsidi2 (r, exp));
17209 /* Divide COUNTREG by SCALE. */
17211 scale_counter (rtx countreg, int scale)
17214 rtx piece_size_mask;
17218 if (CONST_INT_P (countreg))
17219 return GEN_INT (INTVAL (countreg) / scale);
17220 gcc_assert (REG_P (countreg));
17222 piece_size_mask = GEN_INT (scale - 1);
17223 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17224 GEN_INT (exact_log2 (scale)),
17225 NULL, 1, OPTAB_DIRECT);
17229 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17230 DImode for constant loop counts. */
17232 static enum machine_mode
17233 counter_mode (rtx count_exp)
17235 if (GET_MODE (count_exp) != VOIDmode)
17236 return GET_MODE (count_exp);
17237 if (!CONST_INT_P (count_exp))
17239 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17244 /* When SRCPTR is non-NULL, output simple loop to move memory
17245 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17246 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17247 equivalent loop to set memory by VALUE (supposed to be in MODE).
17249 The size is rounded down to whole number of chunk size moved at once.
17250 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17254 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17255 rtx destptr, rtx srcptr, rtx value,
17256 rtx count, enum machine_mode mode, int unroll,
17259 rtx out_label, top_label, iter, tmp;
17260 enum machine_mode iter_mode = counter_mode (count);
17261 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17262 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17268 top_label = gen_label_rtx ();
17269 out_label = gen_label_rtx ();
17270 iter = gen_reg_rtx (iter_mode);
17272 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17273 NULL, 1, OPTAB_DIRECT);
17274 /* Those two should combine. */
17275 if (piece_size == const1_rtx)
17277 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17279 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17281 emit_move_insn (iter, const0_rtx);
17283 emit_label (top_label);
17285 tmp = convert_modes (Pmode, iter_mode, iter, true);
17286 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17287 destmem = change_address (destmem, mode, x_addr);
17291 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17292 srcmem = change_address (srcmem, mode, y_addr);
17294 /* When unrolling for chips that reorder memory reads and writes,
17295 we can save registers by using single temporary.
17296 Also using 4 temporaries is overkill in 32bit mode. */
17297 if (!TARGET_64BIT && 0)
17299 for (i = 0; i < unroll; i++)
17304 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17306 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17308 emit_move_insn (destmem, srcmem);
17314 gcc_assert (unroll <= 4);
17315 for (i = 0; i < unroll; i++)
17317 tmpreg[i] = gen_reg_rtx (mode);
17321 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17323 emit_move_insn (tmpreg[i], srcmem);
17325 for (i = 0; i < unroll; i++)
17330 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17332 emit_move_insn (destmem, tmpreg[i]);
17337 for (i = 0; i < unroll; i++)
17341 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17342 emit_move_insn (destmem, value);
17345 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17346 true, OPTAB_LIB_WIDEN);
17348 emit_move_insn (iter, tmp);
17350 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17352 if (expected_size != -1)
17354 expected_size /= GET_MODE_SIZE (mode) * unroll;
17355 if (expected_size == 0)
17357 else if (expected_size > REG_BR_PROB_BASE)
17358 predict_jump (REG_BR_PROB_BASE - 1);
17360 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17363 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17364 iter = ix86_zero_extend_to_Pmode (iter);
17365 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17366 true, OPTAB_LIB_WIDEN);
17367 if (tmp != destptr)
17368 emit_move_insn (destptr, tmp);
17371 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17372 true, OPTAB_LIB_WIDEN);
17374 emit_move_insn (srcptr, tmp);
17376 emit_label (out_label);
17379 /* Output "rep; mov" instruction.
17380 Arguments have same meaning as for previous function */
17382 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17383 rtx destptr, rtx srcptr,
17385 enum machine_mode mode)
17391 /* If the size is known, it is shorter to use rep movs. */
17392 if (mode == QImode && CONST_INT_P (count)
17393 && !(INTVAL (count) & 3))
17396 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17397 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17398 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17399 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17400 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17401 if (mode != QImode)
17403 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17404 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17405 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17406 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17407 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17408 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17412 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17413 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17415 if (CONST_INT_P (count))
17417 count = GEN_INT (INTVAL (count)
17418 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17419 destmem = shallow_copy_rtx (destmem);
17420 srcmem = shallow_copy_rtx (srcmem);
17421 set_mem_size (destmem, count);
17422 set_mem_size (srcmem, count);
17426 if (MEM_SIZE (destmem))
17427 set_mem_size (destmem, NULL_RTX);
17428 if (MEM_SIZE (srcmem))
17429 set_mem_size (srcmem, NULL_RTX);
17431 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17435 /* Output "rep; stos" instruction.
17436 Arguments have same meaning as for previous function */
17438 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17439 rtx count, enum machine_mode mode,
17445 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17446 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17447 value = force_reg (mode, gen_lowpart (mode, value));
17448 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17449 if (mode != QImode)
17451 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17452 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17453 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17456 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17457 if (orig_value == const0_rtx && CONST_INT_P (count))
17459 count = GEN_INT (INTVAL (count)
17460 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17461 destmem = shallow_copy_rtx (destmem);
17462 set_mem_size (destmem, count);
17464 else if (MEM_SIZE (destmem))
17465 set_mem_size (destmem, NULL_RTX);
17466 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17470 emit_strmov (rtx destmem, rtx srcmem,
17471 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17473 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17474 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17475 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17478 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17480 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17481 rtx destptr, rtx srcptr, rtx count, int max_size)
17484 if (CONST_INT_P (count))
17486 HOST_WIDE_INT countval = INTVAL (count);
17489 if ((countval & 0x10) && max_size > 16)
17493 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17494 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17497 gcc_unreachable ();
17500 if ((countval & 0x08) && max_size > 8)
17503 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17506 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17507 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17511 if ((countval & 0x04) && max_size > 4)
17513 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17516 if ((countval & 0x02) && max_size > 2)
17518 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17521 if ((countval & 0x01) && max_size > 1)
17523 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17530 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17531 count, 1, OPTAB_DIRECT);
17532 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17533 count, QImode, 1, 4);
17537 /* When there are stringops, we can cheaply increase dest and src pointers.
17538 Otherwise we save code size by maintaining offset (zero is readily
17539 available from preceding rep operation) and using x86 addressing modes.
17541 if (TARGET_SINGLE_STRINGOP)
17545 rtx label = ix86_expand_aligntest (count, 4, true);
17546 src = change_address (srcmem, SImode, srcptr);
17547 dest = change_address (destmem, SImode, destptr);
17548 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17549 emit_label (label);
17550 LABEL_NUSES (label) = 1;
17554 rtx label = ix86_expand_aligntest (count, 2, true);
17555 src = change_address (srcmem, HImode, srcptr);
17556 dest = change_address (destmem, HImode, destptr);
17557 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17558 emit_label (label);
17559 LABEL_NUSES (label) = 1;
17563 rtx label = ix86_expand_aligntest (count, 1, true);
17564 src = change_address (srcmem, QImode, srcptr);
17565 dest = change_address (destmem, QImode, destptr);
17566 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17567 emit_label (label);
17568 LABEL_NUSES (label) = 1;
17573 rtx offset = force_reg (Pmode, const0_rtx);
17578 rtx label = ix86_expand_aligntest (count, 4, true);
17579 src = change_address (srcmem, SImode, srcptr);
17580 dest = change_address (destmem, SImode, destptr);
17581 emit_move_insn (dest, src);
17582 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17583 true, OPTAB_LIB_WIDEN);
17585 emit_move_insn (offset, tmp);
17586 emit_label (label);
17587 LABEL_NUSES (label) = 1;
17591 rtx label = ix86_expand_aligntest (count, 2, true);
17592 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17593 src = change_address (srcmem, HImode, tmp);
17594 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17595 dest = change_address (destmem, HImode, tmp);
17596 emit_move_insn (dest, src);
17597 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17598 true, OPTAB_LIB_WIDEN);
17600 emit_move_insn (offset, tmp);
17601 emit_label (label);
17602 LABEL_NUSES (label) = 1;
17606 rtx label = ix86_expand_aligntest (count, 1, true);
17607 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17608 src = change_address (srcmem, QImode, tmp);
17609 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17610 dest = change_address (destmem, QImode, tmp);
17611 emit_move_insn (dest, src);
17612 emit_label (label);
17613 LABEL_NUSES (label) = 1;
17618 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17620 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17621 rtx count, int max_size)
17624 expand_simple_binop (counter_mode (count), AND, count,
17625 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17626 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17627 gen_lowpart (QImode, value), count, QImode,
17631 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17633 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17637 if (CONST_INT_P (count))
17639 HOST_WIDE_INT countval = INTVAL (count);
17642 if ((countval & 0x10) && max_size > 16)
17646 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17647 emit_insn (gen_strset (destptr, dest, value));
17648 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17649 emit_insn (gen_strset (destptr, dest, value));
17652 gcc_unreachable ();
17655 if ((countval & 0x08) && max_size > 8)
17659 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17660 emit_insn (gen_strset (destptr, dest, value));
17664 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17665 emit_insn (gen_strset (destptr, dest, value));
17666 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17667 emit_insn (gen_strset (destptr, dest, value));
17671 if ((countval & 0x04) && max_size > 4)
17673 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17674 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17677 if ((countval & 0x02) && max_size > 2)
17679 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17680 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17683 if ((countval & 0x01) && max_size > 1)
17685 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17686 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17693 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17698 rtx label = ix86_expand_aligntest (count, 16, true);
17701 dest = change_address (destmem, DImode, destptr);
17702 emit_insn (gen_strset (destptr, dest, value));
17703 emit_insn (gen_strset (destptr, dest, value));
17707 dest = change_address (destmem, SImode, destptr);
17708 emit_insn (gen_strset (destptr, dest, value));
17709 emit_insn (gen_strset (destptr, dest, value));
17710 emit_insn (gen_strset (destptr, dest, value));
17711 emit_insn (gen_strset (destptr, dest, value));
17713 emit_label (label);
17714 LABEL_NUSES (label) = 1;
17718 rtx label = ix86_expand_aligntest (count, 8, true);
17721 dest = change_address (destmem, DImode, destptr);
17722 emit_insn (gen_strset (destptr, dest, value));
17726 dest = change_address (destmem, SImode, destptr);
17727 emit_insn (gen_strset (destptr, dest, value));
17728 emit_insn (gen_strset (destptr, dest, value));
17730 emit_label (label);
17731 LABEL_NUSES (label) = 1;
17735 rtx label = ix86_expand_aligntest (count, 4, true);
17736 dest = change_address (destmem, SImode, destptr);
17737 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17738 emit_label (label);
17739 LABEL_NUSES (label) = 1;
17743 rtx label = ix86_expand_aligntest (count, 2, true);
17744 dest = change_address (destmem, HImode, destptr);
17745 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17746 emit_label (label);
17747 LABEL_NUSES (label) = 1;
17751 rtx label = ix86_expand_aligntest (count, 1, true);
17752 dest = change_address (destmem, QImode, destptr);
17753 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17754 emit_label (label);
17755 LABEL_NUSES (label) = 1;
17759 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17760 DESIRED_ALIGNMENT. */
17762 expand_movmem_prologue (rtx destmem, rtx srcmem,
17763 rtx destptr, rtx srcptr, rtx count,
17764 int align, int desired_alignment)
17766 if (align <= 1 && desired_alignment > 1)
17768 rtx label = ix86_expand_aligntest (destptr, 1, false);
17769 srcmem = change_address (srcmem, QImode, srcptr);
17770 destmem = change_address (destmem, QImode, destptr);
17771 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17772 ix86_adjust_counter (count, 1);
17773 emit_label (label);
17774 LABEL_NUSES (label) = 1;
17776 if (align <= 2 && desired_alignment > 2)
17778 rtx label = ix86_expand_aligntest (destptr, 2, false);
17779 srcmem = change_address (srcmem, HImode, srcptr);
17780 destmem = change_address (destmem, HImode, destptr);
17781 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17782 ix86_adjust_counter (count, 2);
17783 emit_label (label);
17784 LABEL_NUSES (label) = 1;
17786 if (align <= 4 && desired_alignment > 4)
17788 rtx label = ix86_expand_aligntest (destptr, 4, false);
17789 srcmem = change_address (srcmem, SImode, srcptr);
17790 destmem = change_address (destmem, SImode, destptr);
17791 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17792 ix86_adjust_counter (count, 4);
17793 emit_label (label);
17794 LABEL_NUSES (label) = 1;
17796 gcc_assert (desired_alignment <= 8);
17799 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17800 ALIGN_BYTES is how many bytes need to be copied. */
17802 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17803 int desired_align, int align_bytes)
17806 rtx src_size, dst_size;
17808 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17809 if (src_align_bytes >= 0)
17810 src_align_bytes = desired_align - src_align_bytes;
17811 src_size = MEM_SIZE (src);
17812 dst_size = MEM_SIZE (dst);
17813 if (align_bytes & 1)
17815 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17816 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17818 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17820 if (align_bytes & 2)
17822 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17823 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17824 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17825 set_mem_align (dst, 2 * BITS_PER_UNIT);
17826 if (src_align_bytes >= 0
17827 && (src_align_bytes & 1) == (align_bytes & 1)
17828 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17829 set_mem_align (src, 2 * BITS_PER_UNIT);
17831 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17833 if (align_bytes & 4)
17835 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17836 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17837 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17838 set_mem_align (dst, 4 * BITS_PER_UNIT);
17839 if (src_align_bytes >= 0)
17841 unsigned int src_align = 0;
17842 if ((src_align_bytes & 3) == (align_bytes & 3))
17844 else if ((src_align_bytes & 1) == (align_bytes & 1))
17846 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17847 set_mem_align (src, src_align * BITS_PER_UNIT);
17850 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17852 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17853 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17854 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17855 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17856 if (src_align_bytes >= 0)
17858 unsigned int src_align = 0;
17859 if ((src_align_bytes & 7) == (align_bytes & 7))
17861 else if ((src_align_bytes & 3) == (align_bytes & 3))
17863 else if ((src_align_bytes & 1) == (align_bytes & 1))
17865 if (src_align > (unsigned int) desired_align)
17866 src_align = desired_align;
17867 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17868 set_mem_align (src, src_align * BITS_PER_UNIT);
17871 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17873 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17878 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17879 DESIRED_ALIGNMENT. */
17881 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17882 int align, int desired_alignment)
17884 if (align <= 1 && desired_alignment > 1)
17886 rtx label = ix86_expand_aligntest (destptr, 1, false);
17887 destmem = change_address (destmem, QImode, destptr);
17888 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17889 ix86_adjust_counter (count, 1);
17890 emit_label (label);
17891 LABEL_NUSES (label) = 1;
17893 if (align <= 2 && desired_alignment > 2)
17895 rtx label = ix86_expand_aligntest (destptr, 2, false);
17896 destmem = change_address (destmem, HImode, destptr);
17897 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17898 ix86_adjust_counter (count, 2);
17899 emit_label (label);
17900 LABEL_NUSES (label) = 1;
17902 if (align <= 4 && desired_alignment > 4)
17904 rtx label = ix86_expand_aligntest (destptr, 4, false);
17905 destmem = change_address (destmem, SImode, destptr);
17906 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17907 ix86_adjust_counter (count, 4);
17908 emit_label (label);
17909 LABEL_NUSES (label) = 1;
17911 gcc_assert (desired_alignment <= 8);
17914 /* Set enough from DST to align DST known to by aligned by ALIGN to
17915 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17917 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17918 int desired_align, int align_bytes)
17921 rtx dst_size = MEM_SIZE (dst);
17922 if (align_bytes & 1)
17924 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17926 emit_insn (gen_strset (destreg, dst,
17927 gen_lowpart (QImode, value)));
17929 if (align_bytes & 2)
17931 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17932 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17933 set_mem_align (dst, 2 * BITS_PER_UNIT);
17935 emit_insn (gen_strset (destreg, dst,
17936 gen_lowpart (HImode, value)));
17938 if (align_bytes & 4)
17940 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17941 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17942 set_mem_align (dst, 4 * BITS_PER_UNIT);
17944 emit_insn (gen_strset (destreg, dst,
17945 gen_lowpart (SImode, value)));
17947 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17948 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17949 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17951 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17955 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17956 static enum stringop_alg
17957 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17958 int *dynamic_check)
17960 const struct stringop_algs * algs;
17961 bool optimize_for_speed;
17962 /* Algorithms using the rep prefix want at least edi and ecx;
17963 additionally, memset wants eax and memcpy wants esi. Don't
17964 consider such algorithms if the user has appropriated those
17965 registers for their own purposes. */
17966 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17968 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17970 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17971 || (alg != rep_prefix_1_byte \
17972 && alg != rep_prefix_4_byte \
17973 && alg != rep_prefix_8_byte))
17974 const struct processor_costs *cost;
17976 /* Even if the string operation call is cold, we still might spend a lot
17977 of time processing large blocks. */
17978 if (optimize_function_for_size_p (cfun)
17979 || (optimize_insn_for_size_p ()
17980 && expected_size != -1 && expected_size < 256))
17981 optimize_for_speed = false;
17983 optimize_for_speed = true;
17985 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17987 *dynamic_check = -1;
17989 algs = &cost->memset[TARGET_64BIT != 0];
17991 algs = &cost->memcpy[TARGET_64BIT != 0];
17992 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17993 return stringop_alg;
17994 /* rep; movq or rep; movl is the smallest variant. */
17995 else if (!optimize_for_speed)
17997 if (!count || (count & 3))
17998 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
18000 return rep_prefix_usable ? rep_prefix_4_byte : loop;
18002 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18004 else if (expected_size != -1 && expected_size < 4)
18005 return loop_1_byte;
18006 else if (expected_size != -1)
18009 enum stringop_alg alg = libcall;
18010 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18012 /* We get here if the algorithms that were not libcall-based
18013 were rep-prefix based and we are unable to use rep prefixes
18014 based on global register usage. Break out of the loop and
18015 use the heuristic below. */
18016 if (algs->size[i].max == 0)
18018 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
18020 enum stringop_alg candidate = algs->size[i].alg;
18022 if (candidate != libcall && ALG_USABLE_P (candidate))
18024 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18025 last non-libcall inline algorithm. */
18026 if (TARGET_INLINE_ALL_STRINGOPS)
18028 /* When the current size is best to be copied by a libcall,
18029 but we are still forced to inline, run the heuristic below
18030 that will pick code for medium sized blocks. */
18031 if (alg != libcall)
18035 else if (ALG_USABLE_P (candidate))
18039 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
18041 /* When asked to inline the call anyway, try to pick meaningful choice.
18042 We look for maximal size of block that is faster to copy by hand and
18043 take blocks of at most of that size guessing that average size will
18044 be roughly half of the block.
18046 If this turns out to be bad, we might simply specify the preferred
18047 choice in ix86_costs. */
18048 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18049 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
18052 enum stringop_alg alg;
18054 bool any_alg_usable_p = true;
18056 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18058 enum stringop_alg candidate = algs->size[i].alg;
18059 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
18061 if (candidate != libcall && candidate
18062 && ALG_USABLE_P (candidate))
18063 max = algs->size[i].max;
18065 /* If there aren't any usable algorithms, then recursing on
18066 smaller sizes isn't going to find anything. Just return the
18067 simple byte-at-a-time copy loop. */
18068 if (!any_alg_usable_p)
18070 /* Pick something reasonable. */
18071 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18072 *dynamic_check = 128;
18073 return loop_1_byte;
18077 alg = decide_alg (count, max / 2, memset, dynamic_check);
18078 gcc_assert (*dynamic_check == -1);
18079 gcc_assert (alg != libcall);
18080 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18081 *dynamic_check = max;
18084 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
18085 #undef ALG_USABLE_P
18088 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18089 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18091 decide_alignment (int align,
18092 enum stringop_alg alg,
18095 int desired_align = 0;
18099 gcc_unreachable ();
18101 case unrolled_loop:
18102 desired_align = GET_MODE_SIZE (Pmode);
18104 case rep_prefix_8_byte:
18107 case rep_prefix_4_byte:
18108 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18109 copying whole cacheline at once. */
18110 if (TARGET_PENTIUMPRO)
18115 case rep_prefix_1_byte:
18116 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18117 copying whole cacheline at once. */
18118 if (TARGET_PENTIUMPRO)
18132 if (desired_align < align)
18133 desired_align = align;
18134 if (expected_size != -1 && expected_size < 4)
18135 desired_align = align;
18136 return desired_align;
18139 /* Return the smallest power of 2 greater than VAL. */
18141 smallest_pow2_greater_than (int val)
18149 /* Expand string move (memcpy) operation. Use i386 string operations when
18150 profitable. expand_setmem contains similar code. The code depends upon
18151 architecture, block size and alignment, but always has the same
18154 1) Prologue guard: Conditional that jumps up to epilogues for small
18155 blocks that can be handled by epilogue alone. This is faster but
18156 also needed for correctness, since prologue assume the block is larger
18157 than the desired alignment.
18159 Optional dynamic check for size and libcall for large
18160 blocks is emitted here too, with -minline-stringops-dynamically.
18162 2) Prologue: copy first few bytes in order to get destination aligned
18163 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18164 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18165 We emit either a jump tree on power of two sized blocks, or a byte loop.
18167 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18168 with specified algorithm.
18170 4) Epilogue: code copying tail of the block that is too small to be
18171 handled by main body (or up to size guarded by prologue guard). */
18174 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18175 rtx expected_align_exp, rtx expected_size_exp)
18181 rtx jump_around_label = NULL;
18182 HOST_WIDE_INT align = 1;
18183 unsigned HOST_WIDE_INT count = 0;
18184 HOST_WIDE_INT expected_size = -1;
18185 int size_needed = 0, epilogue_size_needed;
18186 int desired_align = 0, align_bytes = 0;
18187 enum stringop_alg alg;
18189 bool need_zero_guard = false;
18191 if (CONST_INT_P (align_exp))
18192 align = INTVAL (align_exp);
18193 /* i386 can do misaligned access on reasonably increased cost. */
18194 if (CONST_INT_P (expected_align_exp)
18195 && INTVAL (expected_align_exp) > align)
18196 align = INTVAL (expected_align_exp);
18197 /* ALIGN is the minimum of destination and source alignment, but we care here
18198 just about destination alignment. */
18199 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18200 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18202 if (CONST_INT_P (count_exp))
18203 count = expected_size = INTVAL (count_exp);
18204 if (CONST_INT_P (expected_size_exp) && count == 0)
18205 expected_size = INTVAL (expected_size_exp);
18207 /* Make sure we don't need to care about overflow later on. */
18208 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18211 /* Step 0: Decide on preferred algorithm, desired alignment and
18212 size of chunks to be copied by main loop. */
18214 alg = decide_alg (count, expected_size, false, &dynamic_check);
18215 desired_align = decide_alignment (align, alg, expected_size);
18217 if (!TARGET_ALIGN_STRINGOPS)
18218 align = desired_align;
18220 if (alg == libcall)
18222 gcc_assert (alg != no_stringop);
18224 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18225 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18226 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18231 gcc_unreachable ();
18233 need_zero_guard = true;
18234 size_needed = GET_MODE_SIZE (Pmode);
18236 case unrolled_loop:
18237 need_zero_guard = true;
18238 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18240 case rep_prefix_8_byte:
18243 case rep_prefix_4_byte:
18246 case rep_prefix_1_byte:
18250 need_zero_guard = true;
18255 epilogue_size_needed = size_needed;
18257 /* Step 1: Prologue guard. */
18259 /* Alignment code needs count to be in register. */
18260 if (CONST_INT_P (count_exp) && desired_align > align)
18262 if (INTVAL (count_exp) > desired_align
18263 && INTVAL (count_exp) > size_needed)
18266 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18267 if (align_bytes <= 0)
18270 align_bytes = desired_align - align_bytes;
18272 if (align_bytes == 0)
18273 count_exp = force_reg (counter_mode (count_exp), count_exp);
18275 gcc_assert (desired_align >= 1 && align >= 1);
18277 /* Ensure that alignment prologue won't copy past end of block. */
18278 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18280 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18281 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18282 Make sure it is power of 2. */
18283 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18287 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18289 /* If main algorithm works on QImode, no epilogue is needed.
18290 For small sizes just don't align anything. */
18291 if (size_needed == 1)
18292 desired_align = align;
18299 label = gen_label_rtx ();
18300 emit_cmp_and_jump_insns (count_exp,
18301 GEN_INT (epilogue_size_needed),
18302 LTU, 0, counter_mode (count_exp), 1, label);
18303 if (expected_size == -1 || expected_size < epilogue_size_needed)
18304 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18306 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18310 /* Emit code to decide on runtime whether library call or inline should be
18312 if (dynamic_check != -1)
18314 if (CONST_INT_P (count_exp))
18316 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18318 emit_block_move_via_libcall (dst, src, count_exp, false);
18319 count_exp = const0_rtx;
18325 rtx hot_label = gen_label_rtx ();
18326 jump_around_label = gen_label_rtx ();
18327 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18328 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18329 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18330 emit_block_move_via_libcall (dst, src, count_exp, false);
18331 emit_jump (jump_around_label);
18332 emit_label (hot_label);
18336 /* Step 2: Alignment prologue. */
18338 if (desired_align > align)
18340 if (align_bytes == 0)
18342 /* Except for the first move in epilogue, we no longer know
18343 constant offset in aliasing info. It don't seems to worth
18344 the pain to maintain it for the first move, so throw away
18346 src = change_address (src, BLKmode, srcreg);
18347 dst = change_address (dst, BLKmode, destreg);
18348 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18353 /* If we know how many bytes need to be stored before dst is
18354 sufficiently aligned, maintain aliasing info accurately. */
18355 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18356 desired_align, align_bytes);
18357 count_exp = plus_constant (count_exp, -align_bytes);
18358 count -= align_bytes;
18360 if (need_zero_guard
18361 && (count < (unsigned HOST_WIDE_INT) size_needed
18362 || (align_bytes == 0
18363 && count < ((unsigned HOST_WIDE_INT) size_needed
18364 + desired_align - align))))
18366 /* It is possible that we copied enough so the main loop will not
18368 gcc_assert (size_needed > 1);
18369 if (label == NULL_RTX)
18370 label = gen_label_rtx ();
18371 emit_cmp_and_jump_insns (count_exp,
18372 GEN_INT (size_needed),
18373 LTU, 0, counter_mode (count_exp), 1, label);
18374 if (expected_size == -1
18375 || expected_size < (desired_align - align) / 2 + size_needed)
18376 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18378 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18381 if (label && size_needed == 1)
18383 emit_label (label);
18384 LABEL_NUSES (label) = 1;
18386 epilogue_size_needed = 1;
18388 else if (label == NULL_RTX)
18389 epilogue_size_needed = size_needed;
18391 /* Step 3: Main loop. */
18397 gcc_unreachable ();
18399 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18400 count_exp, QImode, 1, expected_size);
18403 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18404 count_exp, Pmode, 1, expected_size);
18406 case unrolled_loop:
18407 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18408 registers for 4 temporaries anyway. */
18409 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18410 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18413 case rep_prefix_8_byte:
18414 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18417 case rep_prefix_4_byte:
18418 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18421 case rep_prefix_1_byte:
18422 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18426 /* Adjust properly the offset of src and dest memory for aliasing. */
18427 if (CONST_INT_P (count_exp))
18429 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18430 (count / size_needed) * size_needed);
18431 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18432 (count / size_needed) * size_needed);
18436 src = change_address (src, BLKmode, srcreg);
18437 dst = change_address (dst, BLKmode, destreg);
18440 /* Step 4: Epilogue to copy the remaining bytes. */
18444 /* When the main loop is done, COUNT_EXP might hold original count,
18445 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18446 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18447 bytes. Compensate if needed. */
18449 if (size_needed < epilogue_size_needed)
18452 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18453 GEN_INT (size_needed - 1), count_exp, 1,
18455 if (tmp != count_exp)
18456 emit_move_insn (count_exp, tmp);
18458 emit_label (label);
18459 LABEL_NUSES (label) = 1;
18462 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18463 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18464 epilogue_size_needed);
18465 if (jump_around_label)
18466 emit_label (jump_around_label);
18470 /* Helper function for memcpy. For QImode value 0xXY produce
18471 0xXYXYXYXY of wide specified by MODE. This is essentially
18472 a * 0x10101010, but we can do slightly better than
18473 synth_mult by unwinding the sequence by hand on CPUs with
18476 promote_duplicated_reg (enum machine_mode mode, rtx val)
18478 enum machine_mode valmode = GET_MODE (val);
18480 int nops = mode == DImode ? 3 : 2;
18482 gcc_assert (mode == SImode || mode == DImode);
18483 if (val == const0_rtx)
18484 return copy_to_mode_reg (mode, const0_rtx);
18485 if (CONST_INT_P (val))
18487 HOST_WIDE_INT v = INTVAL (val) & 255;
18491 if (mode == DImode)
18492 v |= (v << 16) << 16;
18493 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18496 if (valmode == VOIDmode)
18498 if (valmode != QImode)
18499 val = gen_lowpart (QImode, val);
18500 if (mode == QImode)
18502 if (!TARGET_PARTIAL_REG_STALL)
18504 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18505 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18506 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18507 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18509 rtx reg = convert_modes (mode, QImode, val, true);
18510 tmp = promote_duplicated_reg (mode, const1_rtx);
18511 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18516 rtx reg = convert_modes (mode, QImode, val, true);
18518 if (!TARGET_PARTIAL_REG_STALL)
18519 if (mode == SImode)
18520 emit_insn (gen_movsi_insv_1 (reg, reg));
18522 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18525 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18526 NULL, 1, OPTAB_DIRECT);
18528 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18530 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18531 NULL, 1, OPTAB_DIRECT);
18532 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18533 if (mode == SImode)
18535 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18536 NULL, 1, OPTAB_DIRECT);
18537 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18542 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18543 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18544 alignment from ALIGN to DESIRED_ALIGN. */
18546 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18551 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18552 promoted_val = promote_duplicated_reg (DImode, val);
18553 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18554 promoted_val = promote_duplicated_reg (SImode, val);
18555 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18556 promoted_val = promote_duplicated_reg (HImode, val);
18558 promoted_val = val;
18560 return promoted_val;
18563 /* Expand string clear operation (bzero). Use i386 string operations when
18564 profitable. See expand_movmem comment for explanation of individual
18565 steps performed. */
18567 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18568 rtx expected_align_exp, rtx expected_size_exp)
18573 rtx jump_around_label = NULL;
18574 HOST_WIDE_INT align = 1;
18575 unsigned HOST_WIDE_INT count = 0;
18576 HOST_WIDE_INT expected_size = -1;
18577 int size_needed = 0, epilogue_size_needed;
18578 int desired_align = 0, align_bytes = 0;
18579 enum stringop_alg alg;
18580 rtx promoted_val = NULL;
18581 bool force_loopy_epilogue = false;
18583 bool need_zero_guard = false;
18585 if (CONST_INT_P (align_exp))
18586 align = INTVAL (align_exp);
18587 /* i386 can do misaligned access on reasonably increased cost. */
18588 if (CONST_INT_P (expected_align_exp)
18589 && INTVAL (expected_align_exp) > align)
18590 align = INTVAL (expected_align_exp);
18591 if (CONST_INT_P (count_exp))
18592 count = expected_size = INTVAL (count_exp);
18593 if (CONST_INT_P (expected_size_exp) && count == 0)
18594 expected_size = INTVAL (expected_size_exp);
18596 /* Make sure we don't need to care about overflow later on. */
18597 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18600 /* Step 0: Decide on preferred algorithm, desired alignment and
18601 size of chunks to be copied by main loop. */
18603 alg = decide_alg (count, expected_size, true, &dynamic_check);
18604 desired_align = decide_alignment (align, alg, expected_size);
18606 if (!TARGET_ALIGN_STRINGOPS)
18607 align = desired_align;
18609 if (alg == libcall)
18611 gcc_assert (alg != no_stringop);
18613 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18614 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18619 gcc_unreachable ();
18621 need_zero_guard = true;
18622 size_needed = GET_MODE_SIZE (Pmode);
18624 case unrolled_loop:
18625 need_zero_guard = true;
18626 size_needed = GET_MODE_SIZE (Pmode) * 4;
18628 case rep_prefix_8_byte:
18631 case rep_prefix_4_byte:
18634 case rep_prefix_1_byte:
18638 need_zero_guard = true;
18642 epilogue_size_needed = size_needed;
18644 /* Step 1: Prologue guard. */
18646 /* Alignment code needs count to be in register. */
18647 if (CONST_INT_P (count_exp) && desired_align > align)
18649 if (INTVAL (count_exp) > desired_align
18650 && INTVAL (count_exp) > size_needed)
18653 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18654 if (align_bytes <= 0)
18657 align_bytes = desired_align - align_bytes;
18659 if (align_bytes == 0)
18661 enum machine_mode mode = SImode;
18662 if (TARGET_64BIT && (count & ~0xffffffff))
18664 count_exp = force_reg (mode, count_exp);
18667 /* Do the cheap promotion to allow better CSE across the
18668 main loop and epilogue (ie one load of the big constant in the
18669 front of all code. */
18670 if (CONST_INT_P (val_exp))
18671 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18672 desired_align, align);
18673 /* Ensure that alignment prologue won't copy past end of block. */
18674 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18676 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18677 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18678 Make sure it is power of 2. */
18679 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18681 /* To improve performance of small blocks, we jump around the VAL
18682 promoting mode. This mean that if the promoted VAL is not constant,
18683 we might not use it in the epilogue and have to use byte
18685 if (epilogue_size_needed > 2 && !promoted_val)
18686 force_loopy_epilogue = true;
18689 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18691 /* If main algorithm works on QImode, no epilogue is needed.
18692 For small sizes just don't align anything. */
18693 if (size_needed == 1)
18694 desired_align = align;
18701 label = gen_label_rtx ();
18702 emit_cmp_and_jump_insns (count_exp,
18703 GEN_INT (epilogue_size_needed),
18704 LTU, 0, counter_mode (count_exp), 1, label);
18705 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18706 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18708 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18711 if (dynamic_check != -1)
18713 rtx hot_label = gen_label_rtx ();
18714 jump_around_label = gen_label_rtx ();
18715 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18716 LEU, 0, counter_mode (count_exp), 1, hot_label);
18717 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18718 set_storage_via_libcall (dst, count_exp, val_exp, false);
18719 emit_jump (jump_around_label);
18720 emit_label (hot_label);
18723 /* Step 2: Alignment prologue. */
18725 /* Do the expensive promotion once we branched off the small blocks. */
18727 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18728 desired_align, align);
18729 gcc_assert (desired_align >= 1 && align >= 1);
18731 if (desired_align > align)
18733 if (align_bytes == 0)
18735 /* Except for the first move in epilogue, we no longer know
18736 constant offset in aliasing info. It don't seems to worth
18737 the pain to maintain it for the first move, so throw away
18739 dst = change_address (dst, BLKmode, destreg);
18740 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18745 /* If we know how many bytes need to be stored before dst is
18746 sufficiently aligned, maintain aliasing info accurately. */
18747 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18748 desired_align, align_bytes);
18749 count_exp = plus_constant (count_exp, -align_bytes);
18750 count -= align_bytes;
18752 if (need_zero_guard
18753 && (count < (unsigned HOST_WIDE_INT) size_needed
18754 || (align_bytes == 0
18755 && count < ((unsigned HOST_WIDE_INT) size_needed
18756 + desired_align - align))))
18758 /* It is possible that we copied enough so the main loop will not
18760 gcc_assert (size_needed > 1);
18761 if (label == NULL_RTX)
18762 label = gen_label_rtx ();
18763 emit_cmp_and_jump_insns (count_exp,
18764 GEN_INT (size_needed),
18765 LTU, 0, counter_mode (count_exp), 1, label);
18766 if (expected_size == -1
18767 || expected_size < (desired_align - align) / 2 + size_needed)
18768 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18770 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18773 if (label && size_needed == 1)
18775 emit_label (label);
18776 LABEL_NUSES (label) = 1;
18778 promoted_val = val_exp;
18779 epilogue_size_needed = 1;
18781 else if (label == NULL_RTX)
18782 epilogue_size_needed = size_needed;
18784 /* Step 3: Main loop. */
18790 gcc_unreachable ();
18792 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18793 count_exp, QImode, 1, expected_size);
18796 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18797 count_exp, Pmode, 1, expected_size);
18799 case unrolled_loop:
18800 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18801 count_exp, Pmode, 4, expected_size);
18803 case rep_prefix_8_byte:
18804 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18807 case rep_prefix_4_byte:
18808 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18811 case rep_prefix_1_byte:
18812 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18816 /* Adjust properly the offset of src and dest memory for aliasing. */
18817 if (CONST_INT_P (count_exp))
18818 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18819 (count / size_needed) * size_needed);
18821 dst = change_address (dst, BLKmode, destreg);
18823 /* Step 4: Epilogue to copy the remaining bytes. */
18827 /* When the main loop is done, COUNT_EXP might hold original count,
18828 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18829 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18830 bytes. Compensate if needed. */
18832 if (size_needed < epilogue_size_needed)
18835 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18836 GEN_INT (size_needed - 1), count_exp, 1,
18838 if (tmp != count_exp)
18839 emit_move_insn (count_exp, tmp);
18841 emit_label (label);
18842 LABEL_NUSES (label) = 1;
18845 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18847 if (force_loopy_epilogue)
18848 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18849 epilogue_size_needed);
18851 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18852 epilogue_size_needed);
18854 if (jump_around_label)
18855 emit_label (jump_around_label);
18859 /* Expand the appropriate insns for doing strlen if not just doing
18862 out = result, initialized with the start address
18863 align_rtx = alignment of the address.
18864 scratch = scratch register, initialized with the startaddress when
18865 not aligned, otherwise undefined
18867 This is just the body. It needs the initializations mentioned above and
18868 some address computing at the end. These things are done in i386.md. */
18871 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18875 rtx align_2_label = NULL_RTX;
18876 rtx align_3_label = NULL_RTX;
18877 rtx align_4_label = gen_label_rtx ();
18878 rtx end_0_label = gen_label_rtx ();
18880 rtx tmpreg = gen_reg_rtx (SImode);
18881 rtx scratch = gen_reg_rtx (SImode);
18885 if (CONST_INT_P (align_rtx))
18886 align = INTVAL (align_rtx);
18888 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18890 /* Is there a known alignment and is it less than 4? */
18893 rtx scratch1 = gen_reg_rtx (Pmode);
18894 emit_move_insn (scratch1, out);
18895 /* Is there a known alignment and is it not 2? */
18898 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18899 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18901 /* Leave just the 3 lower bits. */
18902 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18903 NULL_RTX, 0, OPTAB_WIDEN);
18905 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18906 Pmode, 1, align_4_label);
18907 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18908 Pmode, 1, align_2_label);
18909 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18910 Pmode, 1, align_3_label);
18914 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18915 check if is aligned to 4 - byte. */
18917 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18918 NULL_RTX, 0, OPTAB_WIDEN);
18920 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18921 Pmode, 1, align_4_label);
18924 mem = change_address (src, QImode, out);
18926 /* Now compare the bytes. */
18928 /* Compare the first n unaligned byte on a byte per byte basis. */
18929 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18930 QImode, 1, end_0_label);
18932 /* Increment the address. */
18933 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18935 /* Not needed with an alignment of 2 */
18938 emit_label (align_2_label);
18940 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18943 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18945 emit_label (align_3_label);
18948 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18951 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18954 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18955 align this loop. It gives only huge programs, but does not help to
18957 emit_label (align_4_label);
18959 mem = change_address (src, SImode, out);
18960 emit_move_insn (scratch, mem);
18961 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18963 /* This formula yields a nonzero result iff one of the bytes is zero.
18964 This saves three branches inside loop and many cycles. */
18966 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18967 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18968 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18969 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18970 gen_int_mode (0x80808080, SImode)));
18971 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18976 rtx reg = gen_reg_rtx (SImode);
18977 rtx reg2 = gen_reg_rtx (Pmode);
18978 emit_move_insn (reg, tmpreg);
18979 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18981 /* If zero is not in the first two bytes, move two bytes forward. */
18982 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18983 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18984 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18985 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18986 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18989 /* Emit lea manually to avoid clobbering of flags. */
18990 emit_insn (gen_rtx_SET (SImode, reg2,
18991 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18993 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18994 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18995 emit_insn (gen_rtx_SET (VOIDmode, out,
18996 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
19003 rtx end_2_label = gen_label_rtx ();
19004 /* Is zero in the first two bytes? */
19006 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
19007 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19008 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
19009 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
19010 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
19012 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
19013 JUMP_LABEL (tmp) = end_2_label;
19015 /* Not in the first two. Move two bytes forward. */
19016 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
19017 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
19019 emit_label (end_2_label);
19023 /* Avoid branch in fixing the byte. */
19024 tmpreg = gen_lowpart (QImode, tmpreg);
19025 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
19026 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
19027 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
19029 emit_label (end_0_label);
19032 /* Expand strlen. */
19035 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
19037 rtx addr, scratch1, scratch2, scratch3, scratch4;
19039 /* The generic case of strlen expander is long. Avoid it's
19040 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19042 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19043 && !TARGET_INLINE_ALL_STRINGOPS
19044 && !optimize_insn_for_size_p ()
19045 && (!CONST_INT_P (align) || INTVAL (align) < 4))
19048 addr = force_reg (Pmode, XEXP (src, 0));
19049 scratch1 = gen_reg_rtx (Pmode);
19051 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19052 && !optimize_insn_for_size_p ())
19054 /* Well it seems that some optimizer does not combine a call like
19055 foo(strlen(bar), strlen(bar));
19056 when the move and the subtraction is done here. It does calculate
19057 the length just once when these instructions are done inside of
19058 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19059 often used and I use one fewer register for the lifetime of
19060 output_strlen_unroll() this is better. */
19062 emit_move_insn (out, addr);
19064 ix86_expand_strlensi_unroll_1 (out, src, align);
19066 /* strlensi_unroll_1 returns the address of the zero at the end of
19067 the string, like memchr(), so compute the length by subtracting
19068 the start address. */
19069 emit_insn ((*ix86_gen_sub3) (out, out, addr));
19075 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19076 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
19079 scratch2 = gen_reg_rtx (Pmode);
19080 scratch3 = gen_reg_rtx (Pmode);
19081 scratch4 = force_reg (Pmode, constm1_rtx);
19083 emit_move_insn (scratch3, addr);
19084 eoschar = force_reg (QImode, eoschar);
19086 src = replace_equiv_address_nv (src, scratch3);
19088 /* If .md starts supporting :P, this can be done in .md. */
19089 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
19090 scratch4), UNSPEC_SCAS);
19091 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
19092 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
19093 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
19098 /* For given symbol (function) construct code to compute address of it's PLT
19099 entry in large x86-64 PIC model. */
19101 construct_plt_address (rtx symbol)
19103 rtx tmp = gen_reg_rtx (Pmode);
19104 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
19106 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
19107 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
19109 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
19110 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
19115 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
19117 rtx pop, int sibcall)
19119 rtx use = NULL, call;
19121 if (pop == const0_rtx)
19123 gcc_assert (!TARGET_64BIT || !pop);
19125 if (TARGET_MACHO && !TARGET_64BIT)
19128 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
19129 fnaddr = machopic_indirect_call_target (fnaddr);
19134 /* Static functions and indirect calls don't need the pic register. */
19135 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
19136 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19137 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
19138 use_reg (&use, pic_offset_table_rtx);
19141 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
19143 rtx al = gen_rtx_REG (QImode, AX_REG);
19144 emit_move_insn (al, callarg2);
19145 use_reg (&use, al);
19148 if (ix86_cmodel == CM_LARGE_PIC
19150 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19151 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
19152 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19153 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
19155 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19156 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19158 if (sibcall && TARGET_64BIT
19159 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
19162 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19163 fnaddr = gen_rtx_REG (Pmode, R11_REG);
19164 emit_move_insn (fnaddr, addr);
19165 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19168 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19170 call = gen_rtx_SET (VOIDmode, retval, call);
19173 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19174 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19175 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19178 && ix86_cfun_abi () == MS_ABI
19179 && (!callarg2 || INTVAL (callarg2) != -2))
19181 /* We need to represent that SI and DI registers are clobbered
19183 static int clobbered_registers[] = {
19184 XMM6_REG, XMM7_REG, XMM8_REG,
19185 XMM9_REG, XMM10_REG, XMM11_REG,
19186 XMM12_REG, XMM13_REG, XMM14_REG,
19187 XMM15_REG, SI_REG, DI_REG
19190 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19191 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19192 UNSPEC_MS_TO_SYSV_CALL);
19196 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19197 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19200 (SSE_REGNO_P (clobbered_registers[i])
19202 clobbered_registers[i]));
19204 call = gen_rtx_PARALLEL (VOIDmode,
19205 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19209 call = emit_call_insn (call);
19211 CALL_INSN_FUNCTION_USAGE (call) = use;
19215 /* Clear stack slot assignments remembered from previous functions.
19216 This is called from INIT_EXPANDERS once before RTL is emitted for each
19219 static struct machine_function *
19220 ix86_init_machine_status (void)
19222 struct machine_function *f;
19224 f = GGC_CNEW (struct machine_function);
19225 f->use_fast_prologue_epilogue_nregs = -1;
19226 f->tls_descriptor_call_expanded_p = 0;
19227 f->call_abi = ix86_abi;
19232 /* Return a MEM corresponding to a stack slot with mode MODE.
19233 Allocate a new slot if necessary.
19235 The RTL for a function can have several slots available: N is
19236 which slot to use. */
19239 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19241 struct stack_local_entry *s;
19243 gcc_assert (n < MAX_386_STACK_LOCALS);
19245 /* Virtual slot is valid only before vregs are instantiated. */
19246 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19248 for (s = ix86_stack_locals; s; s = s->next)
19249 if (s->mode == mode && s->n == n)
19250 return copy_rtx (s->rtl);
19252 s = (struct stack_local_entry *)
19253 ggc_alloc (sizeof (struct stack_local_entry));
19256 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19258 s->next = ix86_stack_locals;
19259 ix86_stack_locals = s;
19263 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19265 static GTY(()) rtx ix86_tls_symbol;
19267 ix86_tls_get_addr (void)
19270 if (!ix86_tls_symbol)
19272 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19273 (TARGET_ANY_GNU_TLS
19275 ? "___tls_get_addr"
19276 : "__tls_get_addr");
19279 return ix86_tls_symbol;
19282 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19284 static GTY(()) rtx ix86_tls_module_base_symbol;
19286 ix86_tls_module_base (void)
19289 if (!ix86_tls_module_base_symbol)
19291 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19292 "_TLS_MODULE_BASE_");
19293 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19294 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19297 return ix86_tls_module_base_symbol;
19300 /* Calculate the length of the memory address in the instruction
19301 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19304 memory_address_length (rtx addr)
19306 struct ix86_address parts;
19307 rtx base, index, disp;
19311 if (GET_CODE (addr) == PRE_DEC
19312 || GET_CODE (addr) == POST_INC
19313 || GET_CODE (addr) == PRE_MODIFY
19314 || GET_CODE (addr) == POST_MODIFY)
19317 ok = ix86_decompose_address (addr, &parts);
19320 if (parts.base && GET_CODE (parts.base) == SUBREG)
19321 parts.base = SUBREG_REG (parts.base);
19322 if (parts.index && GET_CODE (parts.index) == SUBREG)
19323 parts.index = SUBREG_REG (parts.index);
19326 index = parts.index;
19331 - esp as the base always wants an index,
19332 - ebp as the base always wants a displacement,
19333 - r12 as the base always wants an index,
19334 - r13 as the base always wants a displacement. */
19336 /* Register Indirect. */
19337 if (base && !index && !disp)
19339 /* esp (for its index) and ebp (for its displacement) need
19340 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19343 && (addr == arg_pointer_rtx
19344 || addr == frame_pointer_rtx
19345 || REGNO (addr) == SP_REG
19346 || REGNO (addr) == BP_REG
19347 || REGNO (addr) == R12_REG
19348 || REGNO (addr) == R13_REG))
19352 /* Direct Addressing. */
19353 else if (disp && !base && !index)
19358 /* Find the length of the displacement constant. */
19361 if (base && satisfies_constraint_K (disp))
19366 /* ebp always wants a displacement. Similarly r13. */
19367 else if (REG_P (base)
19368 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19371 /* An index requires the two-byte modrm form.... */
19373 /* ...like esp (or r12), which always wants an index. */
19374 || base == arg_pointer_rtx
19375 || base == frame_pointer_rtx
19377 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19384 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19385 is set, expect that insn have 8bit immediate alternative. */
19387 ix86_attr_length_immediate_default (rtx insn, int shortform)
19391 extract_insn_cached (insn);
19392 for (i = recog_data.n_operands - 1; i >= 0; --i)
19393 if (CONSTANT_P (recog_data.operand[i]))
19396 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
19400 switch (get_attr_mode (insn))
19411 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19416 fatal_insn ("unknown insn mode", insn);
19422 /* Compute default value for "length_address" attribute. */
19424 ix86_attr_length_address_default (rtx insn)
19428 if (get_attr_type (insn) == TYPE_LEA)
19430 rtx set = PATTERN (insn), addr;
19432 if (GET_CODE (set) == PARALLEL)
19433 set = XVECEXP (set, 0, 0);
19435 gcc_assert (GET_CODE (set) == SET);
19437 addr = SET_SRC (set);
19438 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19440 if (GET_CODE (addr) == ZERO_EXTEND)
19441 addr = XEXP (addr, 0);
19442 if (GET_CODE (addr) == SUBREG)
19443 addr = SUBREG_REG (addr);
19446 return memory_address_length (addr);
19449 extract_insn_cached (insn);
19450 for (i = recog_data.n_operands - 1; i >= 0; --i)
19451 if (MEM_P (recog_data.operand[i]))
19453 return memory_address_length (XEXP (recog_data.operand[i], 0));
19459 /* Compute default value for "length_vex" attribute. It includes
19460 2 or 3 byte VEX prefix and 1 opcode byte. */
19463 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19468 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19469 byte VEX prefix. */
19470 if (!has_0f_opcode || has_vex_w)
19473 /* We can always use 2 byte VEX prefix in 32bit. */
19477 extract_insn_cached (insn);
19479 for (i = recog_data.n_operands - 1; i >= 0; --i)
19480 if (REG_P (recog_data.operand[i]))
19482 /* REX.W bit uses 3 byte VEX prefix. */
19483 if (GET_MODE (recog_data.operand[i]) == DImode)
19488 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19489 if (MEM_P (recog_data.operand[i])
19490 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19497 /* Return the maximum number of instructions a cpu can issue. */
19500 ix86_issue_rate (void)
19504 case PROCESSOR_PENTIUM:
19505 case PROCESSOR_ATOM:
19509 case PROCESSOR_PENTIUMPRO:
19510 case PROCESSOR_PENTIUM4:
19511 case PROCESSOR_ATHLON:
19513 case PROCESSOR_AMDFAM10:
19514 case PROCESSOR_NOCONA:
19515 case PROCESSOR_GENERIC32:
19516 case PROCESSOR_GENERIC64:
19519 case PROCESSOR_CORE2:
19527 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19528 by DEP_INSN and nothing set by DEP_INSN. */
19531 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19535 /* Simplify the test for uninteresting insns. */
19536 if (insn_type != TYPE_SETCC
19537 && insn_type != TYPE_ICMOV
19538 && insn_type != TYPE_FCMOV
19539 && insn_type != TYPE_IBR)
19542 if ((set = single_set (dep_insn)) != 0)
19544 set = SET_DEST (set);
19547 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19548 && XVECLEN (PATTERN (dep_insn), 0) == 2
19549 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19550 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19552 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19553 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19558 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19561 /* This test is true if the dependent insn reads the flags but
19562 not any other potentially set register. */
19563 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19566 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19572 /* Return true iff USE_INSN has a memory address with operands set by
19576 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19579 extract_insn_cached (use_insn);
19580 for (i = recog_data.n_operands - 1; i >= 0; --i)
19581 if (MEM_P (recog_data.operand[i]))
19583 rtx addr = XEXP (recog_data.operand[i], 0);
19584 return modified_in_p (addr, set_insn) != 0;
19590 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19592 enum attr_type insn_type, dep_insn_type;
19593 enum attr_memory memory;
19595 int dep_insn_code_number;
19597 /* Anti and output dependencies have zero cost on all CPUs. */
19598 if (REG_NOTE_KIND (link) != 0)
19601 dep_insn_code_number = recog_memoized (dep_insn);
19603 /* If we can't recognize the insns, we can't really do anything. */
19604 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19607 insn_type = get_attr_type (insn);
19608 dep_insn_type = get_attr_type (dep_insn);
19612 case PROCESSOR_PENTIUM:
19613 /* Address Generation Interlock adds a cycle of latency. */
19614 if (insn_type == TYPE_LEA)
19616 rtx addr = PATTERN (insn);
19618 if (GET_CODE (addr) == PARALLEL)
19619 addr = XVECEXP (addr, 0, 0);
19621 gcc_assert (GET_CODE (addr) == SET);
19623 addr = SET_SRC (addr);
19624 if (modified_in_p (addr, dep_insn))
19627 else if (ix86_agi_dependent (dep_insn, insn))
19630 /* ??? Compares pair with jump/setcc. */
19631 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19634 /* Floating point stores require value to be ready one cycle earlier. */
19635 if (insn_type == TYPE_FMOV
19636 && get_attr_memory (insn) == MEMORY_STORE
19637 && !ix86_agi_dependent (dep_insn, insn))
19641 case PROCESSOR_PENTIUMPRO:
19642 memory = get_attr_memory (insn);
19644 /* INT->FP conversion is expensive. */
19645 if (get_attr_fp_int_src (dep_insn))
19648 /* There is one cycle extra latency between an FP op and a store. */
19649 if (insn_type == TYPE_FMOV
19650 && (set = single_set (dep_insn)) != NULL_RTX
19651 && (set2 = single_set (insn)) != NULL_RTX
19652 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19653 && MEM_P (SET_DEST (set2)))
19656 /* Show ability of reorder buffer to hide latency of load by executing
19657 in parallel with previous instruction in case
19658 previous instruction is not needed to compute the address. */
19659 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19660 && !ix86_agi_dependent (dep_insn, insn))
19662 /* Claim moves to take one cycle, as core can issue one load
19663 at time and the next load can start cycle later. */
19664 if (dep_insn_type == TYPE_IMOV
19665 || dep_insn_type == TYPE_FMOV)
19673 memory = get_attr_memory (insn);
19675 /* The esp dependency is resolved before the instruction is really
19677 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19678 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19681 /* INT->FP conversion is expensive. */
19682 if (get_attr_fp_int_src (dep_insn))
19685 /* Show ability of reorder buffer to hide latency of load by executing
19686 in parallel with previous instruction in case
19687 previous instruction is not needed to compute the address. */
19688 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19689 && !ix86_agi_dependent (dep_insn, insn))
19691 /* Claim moves to take one cycle, as core can issue one load
19692 at time and the next load can start cycle later. */
19693 if (dep_insn_type == TYPE_IMOV
19694 || dep_insn_type == TYPE_FMOV)
19703 case PROCESSOR_ATHLON:
19705 case PROCESSOR_AMDFAM10:
19706 case PROCESSOR_ATOM:
19707 case PROCESSOR_GENERIC32:
19708 case PROCESSOR_GENERIC64:
19709 memory = get_attr_memory (insn);
19711 /* Show ability of reorder buffer to hide latency of load by executing
19712 in parallel with previous instruction in case
19713 previous instruction is not needed to compute the address. */
19714 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19715 && !ix86_agi_dependent (dep_insn, insn))
19717 enum attr_unit unit = get_attr_unit (insn);
19720 /* Because of the difference between the length of integer and
19721 floating unit pipeline preparation stages, the memory operands
19722 for floating point are cheaper.
19724 ??? For Athlon it the difference is most probably 2. */
19725 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19728 loadcost = TARGET_ATHLON ? 2 : 0;
19730 if (cost >= loadcost)
19743 /* How many alternative schedules to try. This should be as wide as the
19744 scheduling freedom in the DFA, but no wider. Making this value too
19745 large results extra work for the scheduler. */
19748 ia32_multipass_dfa_lookahead (void)
19752 case PROCESSOR_PENTIUM:
19755 case PROCESSOR_PENTIUMPRO:
19765 /* Compute the alignment given to a constant that is being placed in memory.
19766 EXP is the constant and ALIGN is the alignment that the object would
19768 The value of this function is used instead of that alignment to align
19772 ix86_constant_alignment (tree exp, int align)
19774 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19775 || TREE_CODE (exp) == INTEGER_CST)
19777 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19779 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19782 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19783 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19784 return BITS_PER_WORD;
19789 /* Compute the alignment for a static variable.
19790 TYPE is the data type, and ALIGN is the alignment that
19791 the object would ordinarily have. The value of this function is used
19792 instead of that alignment to align the object. */
19795 ix86_data_alignment (tree type, int align)
19797 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19799 if (AGGREGATE_TYPE_P (type)
19800 && TYPE_SIZE (type)
19801 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19802 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19803 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19804 && align < max_align)
19807 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19808 to 16byte boundary. */
19811 if (AGGREGATE_TYPE_P (type)
19812 && TYPE_SIZE (type)
19813 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19814 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19815 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19819 if (TREE_CODE (type) == ARRAY_TYPE)
19821 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19823 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19826 else if (TREE_CODE (type) == COMPLEX_TYPE)
19829 if (TYPE_MODE (type) == DCmode && align < 64)
19831 if ((TYPE_MODE (type) == XCmode
19832 || TYPE_MODE (type) == TCmode) && align < 128)
19835 else if ((TREE_CODE (type) == RECORD_TYPE
19836 || TREE_CODE (type) == UNION_TYPE
19837 || TREE_CODE (type) == QUAL_UNION_TYPE)
19838 && TYPE_FIELDS (type))
19840 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19842 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19845 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19846 || TREE_CODE (type) == INTEGER_TYPE)
19848 if (TYPE_MODE (type) == DFmode && align < 64)
19850 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19857 /* Compute the alignment for a local variable or a stack slot. EXP is
19858 the data type or decl itself, MODE is the widest mode available and
19859 ALIGN is the alignment that the object would ordinarily have. The
19860 value of this macro is used instead of that alignment to align the
19864 ix86_local_alignment (tree exp, enum machine_mode mode,
19865 unsigned int align)
19869 if (exp && DECL_P (exp))
19871 type = TREE_TYPE (exp);
19880 /* Don't do dynamic stack realignment for long long objects with
19881 -mpreferred-stack-boundary=2. */
19884 && ix86_preferred_stack_boundary < 64
19885 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19886 && (!type || !TYPE_USER_ALIGN (type))
19887 && (!decl || !DECL_USER_ALIGN (decl)))
19890 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19891 register in MODE. We will return the largest alignment of XF
19895 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19896 align = GET_MODE_ALIGNMENT (DFmode);
19900 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19901 to 16byte boundary. */
19904 if (AGGREGATE_TYPE_P (type)
19905 && TYPE_SIZE (type)
19906 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19907 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19908 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19911 if (TREE_CODE (type) == ARRAY_TYPE)
19913 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19915 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19918 else if (TREE_CODE (type) == COMPLEX_TYPE)
19920 if (TYPE_MODE (type) == DCmode && align < 64)
19922 if ((TYPE_MODE (type) == XCmode
19923 || TYPE_MODE (type) == TCmode) && align < 128)
19926 else if ((TREE_CODE (type) == RECORD_TYPE
19927 || TREE_CODE (type) == UNION_TYPE
19928 || TREE_CODE (type) == QUAL_UNION_TYPE)
19929 && TYPE_FIELDS (type))
19931 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19933 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19936 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19937 || TREE_CODE (type) == INTEGER_TYPE)
19940 if (TYPE_MODE (type) == DFmode && align < 64)
19942 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19948 /* Emit RTL insns to initialize the variable parts of a trampoline.
19949 FNADDR is an RTX for the address of the function's pure code.
19950 CXT is an RTX for the static chain value for the function. */
19952 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19956 /* Compute offset from the end of the jmp to the target function. */
19957 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19958 plus_constant (tramp, 10),
19959 NULL_RTX, 1, OPTAB_DIRECT);
19960 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19961 gen_int_mode (0xb9, QImode));
19962 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19963 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19964 gen_int_mode (0xe9, QImode));
19965 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19970 /* Try to load address using shorter movl instead of movabs.
19971 We may want to support movq for kernel mode, but kernel does not use
19972 trampolines at the moment. */
19973 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19975 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19976 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19977 gen_int_mode (0xbb41, HImode));
19978 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19979 gen_lowpart (SImode, fnaddr));
19984 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19985 gen_int_mode (0xbb49, HImode));
19986 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19990 /* Load static chain using movabs to r10. */
19991 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19992 gen_int_mode (0xba49, HImode));
19993 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19996 /* Jump to the r11 */
19997 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19998 gen_int_mode (0xff49, HImode));
19999 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
20000 gen_int_mode (0xe3, QImode));
20002 gcc_assert (offset <= TRAMPOLINE_SIZE);
20005 #ifdef ENABLE_EXECUTE_STACK
20006 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20007 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
20011 /* Codes for all the SSE/MMX builtins. */
20014 IX86_BUILTIN_ADDPS,
20015 IX86_BUILTIN_ADDSS,
20016 IX86_BUILTIN_DIVPS,
20017 IX86_BUILTIN_DIVSS,
20018 IX86_BUILTIN_MULPS,
20019 IX86_BUILTIN_MULSS,
20020 IX86_BUILTIN_SUBPS,
20021 IX86_BUILTIN_SUBSS,
20023 IX86_BUILTIN_CMPEQPS,
20024 IX86_BUILTIN_CMPLTPS,
20025 IX86_BUILTIN_CMPLEPS,
20026 IX86_BUILTIN_CMPGTPS,
20027 IX86_BUILTIN_CMPGEPS,
20028 IX86_BUILTIN_CMPNEQPS,
20029 IX86_BUILTIN_CMPNLTPS,
20030 IX86_BUILTIN_CMPNLEPS,
20031 IX86_BUILTIN_CMPNGTPS,
20032 IX86_BUILTIN_CMPNGEPS,
20033 IX86_BUILTIN_CMPORDPS,
20034 IX86_BUILTIN_CMPUNORDPS,
20035 IX86_BUILTIN_CMPEQSS,
20036 IX86_BUILTIN_CMPLTSS,
20037 IX86_BUILTIN_CMPLESS,
20038 IX86_BUILTIN_CMPNEQSS,
20039 IX86_BUILTIN_CMPNLTSS,
20040 IX86_BUILTIN_CMPNLESS,
20041 IX86_BUILTIN_CMPNGTSS,
20042 IX86_BUILTIN_CMPNGESS,
20043 IX86_BUILTIN_CMPORDSS,
20044 IX86_BUILTIN_CMPUNORDSS,
20046 IX86_BUILTIN_COMIEQSS,
20047 IX86_BUILTIN_COMILTSS,
20048 IX86_BUILTIN_COMILESS,
20049 IX86_BUILTIN_COMIGTSS,
20050 IX86_BUILTIN_COMIGESS,
20051 IX86_BUILTIN_COMINEQSS,
20052 IX86_BUILTIN_UCOMIEQSS,
20053 IX86_BUILTIN_UCOMILTSS,
20054 IX86_BUILTIN_UCOMILESS,
20055 IX86_BUILTIN_UCOMIGTSS,
20056 IX86_BUILTIN_UCOMIGESS,
20057 IX86_BUILTIN_UCOMINEQSS,
20059 IX86_BUILTIN_CVTPI2PS,
20060 IX86_BUILTIN_CVTPS2PI,
20061 IX86_BUILTIN_CVTSI2SS,
20062 IX86_BUILTIN_CVTSI642SS,
20063 IX86_BUILTIN_CVTSS2SI,
20064 IX86_BUILTIN_CVTSS2SI64,
20065 IX86_BUILTIN_CVTTPS2PI,
20066 IX86_BUILTIN_CVTTSS2SI,
20067 IX86_BUILTIN_CVTTSS2SI64,
20069 IX86_BUILTIN_MAXPS,
20070 IX86_BUILTIN_MAXSS,
20071 IX86_BUILTIN_MINPS,
20072 IX86_BUILTIN_MINSS,
20074 IX86_BUILTIN_LOADUPS,
20075 IX86_BUILTIN_STOREUPS,
20076 IX86_BUILTIN_MOVSS,
20078 IX86_BUILTIN_MOVHLPS,
20079 IX86_BUILTIN_MOVLHPS,
20080 IX86_BUILTIN_LOADHPS,
20081 IX86_BUILTIN_LOADLPS,
20082 IX86_BUILTIN_STOREHPS,
20083 IX86_BUILTIN_STORELPS,
20085 IX86_BUILTIN_MASKMOVQ,
20086 IX86_BUILTIN_MOVMSKPS,
20087 IX86_BUILTIN_PMOVMSKB,
20089 IX86_BUILTIN_MOVNTPS,
20090 IX86_BUILTIN_MOVNTQ,
20092 IX86_BUILTIN_LOADDQU,
20093 IX86_BUILTIN_STOREDQU,
20095 IX86_BUILTIN_PACKSSWB,
20096 IX86_BUILTIN_PACKSSDW,
20097 IX86_BUILTIN_PACKUSWB,
20099 IX86_BUILTIN_PADDB,
20100 IX86_BUILTIN_PADDW,
20101 IX86_BUILTIN_PADDD,
20102 IX86_BUILTIN_PADDQ,
20103 IX86_BUILTIN_PADDSB,
20104 IX86_BUILTIN_PADDSW,
20105 IX86_BUILTIN_PADDUSB,
20106 IX86_BUILTIN_PADDUSW,
20107 IX86_BUILTIN_PSUBB,
20108 IX86_BUILTIN_PSUBW,
20109 IX86_BUILTIN_PSUBD,
20110 IX86_BUILTIN_PSUBQ,
20111 IX86_BUILTIN_PSUBSB,
20112 IX86_BUILTIN_PSUBSW,
20113 IX86_BUILTIN_PSUBUSB,
20114 IX86_BUILTIN_PSUBUSW,
20117 IX86_BUILTIN_PANDN,
20121 IX86_BUILTIN_PAVGB,
20122 IX86_BUILTIN_PAVGW,
20124 IX86_BUILTIN_PCMPEQB,
20125 IX86_BUILTIN_PCMPEQW,
20126 IX86_BUILTIN_PCMPEQD,
20127 IX86_BUILTIN_PCMPGTB,
20128 IX86_BUILTIN_PCMPGTW,
20129 IX86_BUILTIN_PCMPGTD,
20131 IX86_BUILTIN_PMADDWD,
20133 IX86_BUILTIN_PMAXSW,
20134 IX86_BUILTIN_PMAXUB,
20135 IX86_BUILTIN_PMINSW,
20136 IX86_BUILTIN_PMINUB,
20138 IX86_BUILTIN_PMULHUW,
20139 IX86_BUILTIN_PMULHW,
20140 IX86_BUILTIN_PMULLW,
20142 IX86_BUILTIN_PSADBW,
20143 IX86_BUILTIN_PSHUFW,
20145 IX86_BUILTIN_PSLLW,
20146 IX86_BUILTIN_PSLLD,
20147 IX86_BUILTIN_PSLLQ,
20148 IX86_BUILTIN_PSRAW,
20149 IX86_BUILTIN_PSRAD,
20150 IX86_BUILTIN_PSRLW,
20151 IX86_BUILTIN_PSRLD,
20152 IX86_BUILTIN_PSRLQ,
20153 IX86_BUILTIN_PSLLWI,
20154 IX86_BUILTIN_PSLLDI,
20155 IX86_BUILTIN_PSLLQI,
20156 IX86_BUILTIN_PSRAWI,
20157 IX86_BUILTIN_PSRADI,
20158 IX86_BUILTIN_PSRLWI,
20159 IX86_BUILTIN_PSRLDI,
20160 IX86_BUILTIN_PSRLQI,
20162 IX86_BUILTIN_PUNPCKHBW,
20163 IX86_BUILTIN_PUNPCKHWD,
20164 IX86_BUILTIN_PUNPCKHDQ,
20165 IX86_BUILTIN_PUNPCKLBW,
20166 IX86_BUILTIN_PUNPCKLWD,
20167 IX86_BUILTIN_PUNPCKLDQ,
20169 IX86_BUILTIN_SHUFPS,
20171 IX86_BUILTIN_RCPPS,
20172 IX86_BUILTIN_RCPSS,
20173 IX86_BUILTIN_RSQRTPS,
20174 IX86_BUILTIN_RSQRTPS_NR,
20175 IX86_BUILTIN_RSQRTSS,
20176 IX86_BUILTIN_RSQRTF,
20177 IX86_BUILTIN_SQRTPS,
20178 IX86_BUILTIN_SQRTPS_NR,
20179 IX86_BUILTIN_SQRTSS,
20181 IX86_BUILTIN_UNPCKHPS,
20182 IX86_BUILTIN_UNPCKLPS,
20184 IX86_BUILTIN_ANDPS,
20185 IX86_BUILTIN_ANDNPS,
20187 IX86_BUILTIN_XORPS,
20190 IX86_BUILTIN_LDMXCSR,
20191 IX86_BUILTIN_STMXCSR,
20192 IX86_BUILTIN_SFENCE,
20194 /* 3DNow! Original */
20195 IX86_BUILTIN_FEMMS,
20196 IX86_BUILTIN_PAVGUSB,
20197 IX86_BUILTIN_PF2ID,
20198 IX86_BUILTIN_PFACC,
20199 IX86_BUILTIN_PFADD,
20200 IX86_BUILTIN_PFCMPEQ,
20201 IX86_BUILTIN_PFCMPGE,
20202 IX86_BUILTIN_PFCMPGT,
20203 IX86_BUILTIN_PFMAX,
20204 IX86_BUILTIN_PFMIN,
20205 IX86_BUILTIN_PFMUL,
20206 IX86_BUILTIN_PFRCP,
20207 IX86_BUILTIN_PFRCPIT1,
20208 IX86_BUILTIN_PFRCPIT2,
20209 IX86_BUILTIN_PFRSQIT1,
20210 IX86_BUILTIN_PFRSQRT,
20211 IX86_BUILTIN_PFSUB,
20212 IX86_BUILTIN_PFSUBR,
20213 IX86_BUILTIN_PI2FD,
20214 IX86_BUILTIN_PMULHRW,
20216 /* 3DNow! Athlon Extensions */
20217 IX86_BUILTIN_PF2IW,
20218 IX86_BUILTIN_PFNACC,
20219 IX86_BUILTIN_PFPNACC,
20220 IX86_BUILTIN_PI2FW,
20221 IX86_BUILTIN_PSWAPDSI,
20222 IX86_BUILTIN_PSWAPDSF,
20225 IX86_BUILTIN_ADDPD,
20226 IX86_BUILTIN_ADDSD,
20227 IX86_BUILTIN_DIVPD,
20228 IX86_BUILTIN_DIVSD,
20229 IX86_BUILTIN_MULPD,
20230 IX86_BUILTIN_MULSD,
20231 IX86_BUILTIN_SUBPD,
20232 IX86_BUILTIN_SUBSD,
20234 IX86_BUILTIN_CMPEQPD,
20235 IX86_BUILTIN_CMPLTPD,
20236 IX86_BUILTIN_CMPLEPD,
20237 IX86_BUILTIN_CMPGTPD,
20238 IX86_BUILTIN_CMPGEPD,
20239 IX86_BUILTIN_CMPNEQPD,
20240 IX86_BUILTIN_CMPNLTPD,
20241 IX86_BUILTIN_CMPNLEPD,
20242 IX86_BUILTIN_CMPNGTPD,
20243 IX86_BUILTIN_CMPNGEPD,
20244 IX86_BUILTIN_CMPORDPD,
20245 IX86_BUILTIN_CMPUNORDPD,
20246 IX86_BUILTIN_CMPEQSD,
20247 IX86_BUILTIN_CMPLTSD,
20248 IX86_BUILTIN_CMPLESD,
20249 IX86_BUILTIN_CMPNEQSD,
20250 IX86_BUILTIN_CMPNLTSD,
20251 IX86_BUILTIN_CMPNLESD,
20252 IX86_BUILTIN_CMPORDSD,
20253 IX86_BUILTIN_CMPUNORDSD,
20255 IX86_BUILTIN_COMIEQSD,
20256 IX86_BUILTIN_COMILTSD,
20257 IX86_BUILTIN_COMILESD,
20258 IX86_BUILTIN_COMIGTSD,
20259 IX86_BUILTIN_COMIGESD,
20260 IX86_BUILTIN_COMINEQSD,
20261 IX86_BUILTIN_UCOMIEQSD,
20262 IX86_BUILTIN_UCOMILTSD,
20263 IX86_BUILTIN_UCOMILESD,
20264 IX86_BUILTIN_UCOMIGTSD,
20265 IX86_BUILTIN_UCOMIGESD,
20266 IX86_BUILTIN_UCOMINEQSD,
20268 IX86_BUILTIN_MAXPD,
20269 IX86_BUILTIN_MAXSD,
20270 IX86_BUILTIN_MINPD,
20271 IX86_BUILTIN_MINSD,
20273 IX86_BUILTIN_ANDPD,
20274 IX86_BUILTIN_ANDNPD,
20276 IX86_BUILTIN_XORPD,
20278 IX86_BUILTIN_SQRTPD,
20279 IX86_BUILTIN_SQRTSD,
20281 IX86_BUILTIN_UNPCKHPD,
20282 IX86_BUILTIN_UNPCKLPD,
20284 IX86_BUILTIN_SHUFPD,
20286 IX86_BUILTIN_LOADUPD,
20287 IX86_BUILTIN_STOREUPD,
20288 IX86_BUILTIN_MOVSD,
20290 IX86_BUILTIN_LOADHPD,
20291 IX86_BUILTIN_LOADLPD,
20293 IX86_BUILTIN_CVTDQ2PD,
20294 IX86_BUILTIN_CVTDQ2PS,
20296 IX86_BUILTIN_CVTPD2DQ,
20297 IX86_BUILTIN_CVTPD2PI,
20298 IX86_BUILTIN_CVTPD2PS,
20299 IX86_BUILTIN_CVTTPD2DQ,
20300 IX86_BUILTIN_CVTTPD2PI,
20302 IX86_BUILTIN_CVTPI2PD,
20303 IX86_BUILTIN_CVTSI2SD,
20304 IX86_BUILTIN_CVTSI642SD,
20306 IX86_BUILTIN_CVTSD2SI,
20307 IX86_BUILTIN_CVTSD2SI64,
20308 IX86_BUILTIN_CVTSD2SS,
20309 IX86_BUILTIN_CVTSS2SD,
20310 IX86_BUILTIN_CVTTSD2SI,
20311 IX86_BUILTIN_CVTTSD2SI64,
20313 IX86_BUILTIN_CVTPS2DQ,
20314 IX86_BUILTIN_CVTPS2PD,
20315 IX86_BUILTIN_CVTTPS2DQ,
20317 IX86_BUILTIN_MOVNTI,
20318 IX86_BUILTIN_MOVNTPD,
20319 IX86_BUILTIN_MOVNTDQ,
20321 IX86_BUILTIN_MOVQ128,
20324 IX86_BUILTIN_MASKMOVDQU,
20325 IX86_BUILTIN_MOVMSKPD,
20326 IX86_BUILTIN_PMOVMSKB128,
20328 IX86_BUILTIN_PACKSSWB128,
20329 IX86_BUILTIN_PACKSSDW128,
20330 IX86_BUILTIN_PACKUSWB128,
20332 IX86_BUILTIN_PADDB128,
20333 IX86_BUILTIN_PADDW128,
20334 IX86_BUILTIN_PADDD128,
20335 IX86_BUILTIN_PADDQ128,
20336 IX86_BUILTIN_PADDSB128,
20337 IX86_BUILTIN_PADDSW128,
20338 IX86_BUILTIN_PADDUSB128,
20339 IX86_BUILTIN_PADDUSW128,
20340 IX86_BUILTIN_PSUBB128,
20341 IX86_BUILTIN_PSUBW128,
20342 IX86_BUILTIN_PSUBD128,
20343 IX86_BUILTIN_PSUBQ128,
20344 IX86_BUILTIN_PSUBSB128,
20345 IX86_BUILTIN_PSUBSW128,
20346 IX86_BUILTIN_PSUBUSB128,
20347 IX86_BUILTIN_PSUBUSW128,
20349 IX86_BUILTIN_PAND128,
20350 IX86_BUILTIN_PANDN128,
20351 IX86_BUILTIN_POR128,
20352 IX86_BUILTIN_PXOR128,
20354 IX86_BUILTIN_PAVGB128,
20355 IX86_BUILTIN_PAVGW128,
20357 IX86_BUILTIN_PCMPEQB128,
20358 IX86_BUILTIN_PCMPEQW128,
20359 IX86_BUILTIN_PCMPEQD128,
20360 IX86_BUILTIN_PCMPGTB128,
20361 IX86_BUILTIN_PCMPGTW128,
20362 IX86_BUILTIN_PCMPGTD128,
20364 IX86_BUILTIN_PMADDWD128,
20366 IX86_BUILTIN_PMAXSW128,
20367 IX86_BUILTIN_PMAXUB128,
20368 IX86_BUILTIN_PMINSW128,
20369 IX86_BUILTIN_PMINUB128,
20371 IX86_BUILTIN_PMULUDQ,
20372 IX86_BUILTIN_PMULUDQ128,
20373 IX86_BUILTIN_PMULHUW128,
20374 IX86_BUILTIN_PMULHW128,
20375 IX86_BUILTIN_PMULLW128,
20377 IX86_BUILTIN_PSADBW128,
20378 IX86_BUILTIN_PSHUFHW,
20379 IX86_BUILTIN_PSHUFLW,
20380 IX86_BUILTIN_PSHUFD,
20382 IX86_BUILTIN_PSLLDQI128,
20383 IX86_BUILTIN_PSLLWI128,
20384 IX86_BUILTIN_PSLLDI128,
20385 IX86_BUILTIN_PSLLQI128,
20386 IX86_BUILTIN_PSRAWI128,
20387 IX86_BUILTIN_PSRADI128,
20388 IX86_BUILTIN_PSRLDQI128,
20389 IX86_BUILTIN_PSRLWI128,
20390 IX86_BUILTIN_PSRLDI128,
20391 IX86_BUILTIN_PSRLQI128,
20393 IX86_BUILTIN_PSLLDQ128,
20394 IX86_BUILTIN_PSLLW128,
20395 IX86_BUILTIN_PSLLD128,
20396 IX86_BUILTIN_PSLLQ128,
20397 IX86_BUILTIN_PSRAW128,
20398 IX86_BUILTIN_PSRAD128,
20399 IX86_BUILTIN_PSRLW128,
20400 IX86_BUILTIN_PSRLD128,
20401 IX86_BUILTIN_PSRLQ128,
20403 IX86_BUILTIN_PUNPCKHBW128,
20404 IX86_BUILTIN_PUNPCKHWD128,
20405 IX86_BUILTIN_PUNPCKHDQ128,
20406 IX86_BUILTIN_PUNPCKHQDQ128,
20407 IX86_BUILTIN_PUNPCKLBW128,
20408 IX86_BUILTIN_PUNPCKLWD128,
20409 IX86_BUILTIN_PUNPCKLDQ128,
20410 IX86_BUILTIN_PUNPCKLQDQ128,
20412 IX86_BUILTIN_CLFLUSH,
20413 IX86_BUILTIN_MFENCE,
20414 IX86_BUILTIN_LFENCE,
20417 IX86_BUILTIN_ADDSUBPS,
20418 IX86_BUILTIN_HADDPS,
20419 IX86_BUILTIN_HSUBPS,
20420 IX86_BUILTIN_MOVSHDUP,
20421 IX86_BUILTIN_MOVSLDUP,
20422 IX86_BUILTIN_ADDSUBPD,
20423 IX86_BUILTIN_HADDPD,
20424 IX86_BUILTIN_HSUBPD,
20425 IX86_BUILTIN_LDDQU,
20427 IX86_BUILTIN_MONITOR,
20428 IX86_BUILTIN_MWAIT,
20431 IX86_BUILTIN_PHADDW,
20432 IX86_BUILTIN_PHADDD,
20433 IX86_BUILTIN_PHADDSW,
20434 IX86_BUILTIN_PHSUBW,
20435 IX86_BUILTIN_PHSUBD,
20436 IX86_BUILTIN_PHSUBSW,
20437 IX86_BUILTIN_PMADDUBSW,
20438 IX86_BUILTIN_PMULHRSW,
20439 IX86_BUILTIN_PSHUFB,
20440 IX86_BUILTIN_PSIGNB,
20441 IX86_BUILTIN_PSIGNW,
20442 IX86_BUILTIN_PSIGND,
20443 IX86_BUILTIN_PALIGNR,
20444 IX86_BUILTIN_PABSB,
20445 IX86_BUILTIN_PABSW,
20446 IX86_BUILTIN_PABSD,
20448 IX86_BUILTIN_PHADDW128,
20449 IX86_BUILTIN_PHADDD128,
20450 IX86_BUILTIN_PHADDSW128,
20451 IX86_BUILTIN_PHSUBW128,
20452 IX86_BUILTIN_PHSUBD128,
20453 IX86_BUILTIN_PHSUBSW128,
20454 IX86_BUILTIN_PMADDUBSW128,
20455 IX86_BUILTIN_PMULHRSW128,
20456 IX86_BUILTIN_PSHUFB128,
20457 IX86_BUILTIN_PSIGNB128,
20458 IX86_BUILTIN_PSIGNW128,
20459 IX86_BUILTIN_PSIGND128,
20460 IX86_BUILTIN_PALIGNR128,
20461 IX86_BUILTIN_PABSB128,
20462 IX86_BUILTIN_PABSW128,
20463 IX86_BUILTIN_PABSD128,
20465 /* AMDFAM10 - SSE4A New Instructions. */
20466 IX86_BUILTIN_MOVNTSD,
20467 IX86_BUILTIN_MOVNTSS,
20468 IX86_BUILTIN_EXTRQI,
20469 IX86_BUILTIN_EXTRQ,
20470 IX86_BUILTIN_INSERTQI,
20471 IX86_BUILTIN_INSERTQ,
20474 IX86_BUILTIN_BLENDPD,
20475 IX86_BUILTIN_BLENDPS,
20476 IX86_BUILTIN_BLENDVPD,
20477 IX86_BUILTIN_BLENDVPS,
20478 IX86_BUILTIN_PBLENDVB128,
20479 IX86_BUILTIN_PBLENDW128,
20484 IX86_BUILTIN_INSERTPS128,
20486 IX86_BUILTIN_MOVNTDQA,
20487 IX86_BUILTIN_MPSADBW128,
20488 IX86_BUILTIN_PACKUSDW128,
20489 IX86_BUILTIN_PCMPEQQ,
20490 IX86_BUILTIN_PHMINPOSUW128,
20492 IX86_BUILTIN_PMAXSB128,
20493 IX86_BUILTIN_PMAXSD128,
20494 IX86_BUILTIN_PMAXUD128,
20495 IX86_BUILTIN_PMAXUW128,
20497 IX86_BUILTIN_PMINSB128,
20498 IX86_BUILTIN_PMINSD128,
20499 IX86_BUILTIN_PMINUD128,
20500 IX86_BUILTIN_PMINUW128,
20502 IX86_BUILTIN_PMOVSXBW128,
20503 IX86_BUILTIN_PMOVSXBD128,
20504 IX86_BUILTIN_PMOVSXBQ128,
20505 IX86_BUILTIN_PMOVSXWD128,
20506 IX86_BUILTIN_PMOVSXWQ128,
20507 IX86_BUILTIN_PMOVSXDQ128,
20509 IX86_BUILTIN_PMOVZXBW128,
20510 IX86_BUILTIN_PMOVZXBD128,
20511 IX86_BUILTIN_PMOVZXBQ128,
20512 IX86_BUILTIN_PMOVZXWD128,
20513 IX86_BUILTIN_PMOVZXWQ128,
20514 IX86_BUILTIN_PMOVZXDQ128,
20516 IX86_BUILTIN_PMULDQ128,
20517 IX86_BUILTIN_PMULLD128,
20519 IX86_BUILTIN_ROUNDPD,
20520 IX86_BUILTIN_ROUNDPS,
20521 IX86_BUILTIN_ROUNDSD,
20522 IX86_BUILTIN_ROUNDSS,
20524 IX86_BUILTIN_PTESTZ,
20525 IX86_BUILTIN_PTESTC,
20526 IX86_BUILTIN_PTESTNZC,
20528 IX86_BUILTIN_VEC_INIT_V2SI,
20529 IX86_BUILTIN_VEC_INIT_V4HI,
20530 IX86_BUILTIN_VEC_INIT_V8QI,
20531 IX86_BUILTIN_VEC_EXT_V2DF,
20532 IX86_BUILTIN_VEC_EXT_V2DI,
20533 IX86_BUILTIN_VEC_EXT_V4SF,
20534 IX86_BUILTIN_VEC_EXT_V4SI,
20535 IX86_BUILTIN_VEC_EXT_V8HI,
20536 IX86_BUILTIN_VEC_EXT_V2SI,
20537 IX86_BUILTIN_VEC_EXT_V4HI,
20538 IX86_BUILTIN_VEC_EXT_V16QI,
20539 IX86_BUILTIN_VEC_SET_V2DI,
20540 IX86_BUILTIN_VEC_SET_V4SF,
20541 IX86_BUILTIN_VEC_SET_V4SI,
20542 IX86_BUILTIN_VEC_SET_V8HI,
20543 IX86_BUILTIN_VEC_SET_V4HI,
20544 IX86_BUILTIN_VEC_SET_V16QI,
20546 IX86_BUILTIN_VEC_PACK_SFIX,
20549 IX86_BUILTIN_CRC32QI,
20550 IX86_BUILTIN_CRC32HI,
20551 IX86_BUILTIN_CRC32SI,
20552 IX86_BUILTIN_CRC32DI,
20554 IX86_BUILTIN_PCMPESTRI128,
20555 IX86_BUILTIN_PCMPESTRM128,
20556 IX86_BUILTIN_PCMPESTRA128,
20557 IX86_BUILTIN_PCMPESTRC128,
20558 IX86_BUILTIN_PCMPESTRO128,
20559 IX86_BUILTIN_PCMPESTRS128,
20560 IX86_BUILTIN_PCMPESTRZ128,
20561 IX86_BUILTIN_PCMPISTRI128,
20562 IX86_BUILTIN_PCMPISTRM128,
20563 IX86_BUILTIN_PCMPISTRA128,
20564 IX86_BUILTIN_PCMPISTRC128,
20565 IX86_BUILTIN_PCMPISTRO128,
20566 IX86_BUILTIN_PCMPISTRS128,
20567 IX86_BUILTIN_PCMPISTRZ128,
20569 IX86_BUILTIN_PCMPGTQ,
20571 /* AES instructions */
20572 IX86_BUILTIN_AESENC128,
20573 IX86_BUILTIN_AESENCLAST128,
20574 IX86_BUILTIN_AESDEC128,
20575 IX86_BUILTIN_AESDECLAST128,
20576 IX86_BUILTIN_AESIMC128,
20577 IX86_BUILTIN_AESKEYGENASSIST128,
20579 /* PCLMUL instruction */
20580 IX86_BUILTIN_PCLMULQDQ128,
20583 IX86_BUILTIN_ADDPD256,
20584 IX86_BUILTIN_ADDPS256,
20585 IX86_BUILTIN_ADDSUBPD256,
20586 IX86_BUILTIN_ADDSUBPS256,
20587 IX86_BUILTIN_ANDPD256,
20588 IX86_BUILTIN_ANDPS256,
20589 IX86_BUILTIN_ANDNPD256,
20590 IX86_BUILTIN_ANDNPS256,
20591 IX86_BUILTIN_BLENDPD256,
20592 IX86_BUILTIN_BLENDPS256,
20593 IX86_BUILTIN_BLENDVPD256,
20594 IX86_BUILTIN_BLENDVPS256,
20595 IX86_BUILTIN_DIVPD256,
20596 IX86_BUILTIN_DIVPS256,
20597 IX86_BUILTIN_DPPS256,
20598 IX86_BUILTIN_HADDPD256,
20599 IX86_BUILTIN_HADDPS256,
20600 IX86_BUILTIN_HSUBPD256,
20601 IX86_BUILTIN_HSUBPS256,
20602 IX86_BUILTIN_MAXPD256,
20603 IX86_BUILTIN_MAXPS256,
20604 IX86_BUILTIN_MINPD256,
20605 IX86_BUILTIN_MINPS256,
20606 IX86_BUILTIN_MULPD256,
20607 IX86_BUILTIN_MULPS256,
20608 IX86_BUILTIN_ORPD256,
20609 IX86_BUILTIN_ORPS256,
20610 IX86_BUILTIN_SHUFPD256,
20611 IX86_BUILTIN_SHUFPS256,
20612 IX86_BUILTIN_SUBPD256,
20613 IX86_BUILTIN_SUBPS256,
20614 IX86_BUILTIN_XORPD256,
20615 IX86_BUILTIN_XORPS256,
20616 IX86_BUILTIN_CMPSD,
20617 IX86_BUILTIN_CMPSS,
20618 IX86_BUILTIN_CMPPD,
20619 IX86_BUILTIN_CMPPS,
20620 IX86_BUILTIN_CMPPD256,
20621 IX86_BUILTIN_CMPPS256,
20622 IX86_BUILTIN_CVTDQ2PD256,
20623 IX86_BUILTIN_CVTDQ2PS256,
20624 IX86_BUILTIN_CVTPD2PS256,
20625 IX86_BUILTIN_CVTPS2DQ256,
20626 IX86_BUILTIN_CVTPS2PD256,
20627 IX86_BUILTIN_CVTTPD2DQ256,
20628 IX86_BUILTIN_CVTPD2DQ256,
20629 IX86_BUILTIN_CVTTPS2DQ256,
20630 IX86_BUILTIN_EXTRACTF128PD256,
20631 IX86_BUILTIN_EXTRACTF128PS256,
20632 IX86_BUILTIN_EXTRACTF128SI256,
20633 IX86_BUILTIN_VZEROALL,
20634 IX86_BUILTIN_VZEROUPPER,
20635 IX86_BUILTIN_VZEROUPPER_REX64,
20636 IX86_BUILTIN_VPERMILVARPD,
20637 IX86_BUILTIN_VPERMILVARPS,
20638 IX86_BUILTIN_VPERMILVARPD256,
20639 IX86_BUILTIN_VPERMILVARPS256,
20640 IX86_BUILTIN_VPERMILPD,
20641 IX86_BUILTIN_VPERMILPS,
20642 IX86_BUILTIN_VPERMILPD256,
20643 IX86_BUILTIN_VPERMILPS256,
20644 IX86_BUILTIN_VPERM2F128PD256,
20645 IX86_BUILTIN_VPERM2F128PS256,
20646 IX86_BUILTIN_VPERM2F128SI256,
20647 IX86_BUILTIN_VBROADCASTSS,
20648 IX86_BUILTIN_VBROADCASTSD256,
20649 IX86_BUILTIN_VBROADCASTSS256,
20650 IX86_BUILTIN_VBROADCASTPD256,
20651 IX86_BUILTIN_VBROADCASTPS256,
20652 IX86_BUILTIN_VINSERTF128PD256,
20653 IX86_BUILTIN_VINSERTF128PS256,
20654 IX86_BUILTIN_VINSERTF128SI256,
20655 IX86_BUILTIN_LOADUPD256,
20656 IX86_BUILTIN_LOADUPS256,
20657 IX86_BUILTIN_STOREUPD256,
20658 IX86_BUILTIN_STOREUPS256,
20659 IX86_BUILTIN_LDDQU256,
20660 IX86_BUILTIN_MOVNTDQ256,
20661 IX86_BUILTIN_MOVNTPD256,
20662 IX86_BUILTIN_MOVNTPS256,
20663 IX86_BUILTIN_LOADDQU256,
20664 IX86_BUILTIN_STOREDQU256,
20665 IX86_BUILTIN_MASKLOADPD,
20666 IX86_BUILTIN_MASKLOADPS,
20667 IX86_BUILTIN_MASKSTOREPD,
20668 IX86_BUILTIN_MASKSTOREPS,
20669 IX86_BUILTIN_MASKLOADPD256,
20670 IX86_BUILTIN_MASKLOADPS256,
20671 IX86_BUILTIN_MASKSTOREPD256,
20672 IX86_BUILTIN_MASKSTOREPS256,
20673 IX86_BUILTIN_MOVSHDUP256,
20674 IX86_BUILTIN_MOVSLDUP256,
20675 IX86_BUILTIN_MOVDDUP256,
20677 IX86_BUILTIN_SQRTPD256,
20678 IX86_BUILTIN_SQRTPS256,
20679 IX86_BUILTIN_SQRTPS_NR256,
20680 IX86_BUILTIN_RSQRTPS256,
20681 IX86_BUILTIN_RSQRTPS_NR256,
20683 IX86_BUILTIN_RCPPS256,
20685 IX86_BUILTIN_ROUNDPD256,
20686 IX86_BUILTIN_ROUNDPS256,
20688 IX86_BUILTIN_UNPCKHPD256,
20689 IX86_BUILTIN_UNPCKLPD256,
20690 IX86_BUILTIN_UNPCKHPS256,
20691 IX86_BUILTIN_UNPCKLPS256,
20693 IX86_BUILTIN_SI256_SI,
20694 IX86_BUILTIN_PS256_PS,
20695 IX86_BUILTIN_PD256_PD,
20696 IX86_BUILTIN_SI_SI256,
20697 IX86_BUILTIN_PS_PS256,
20698 IX86_BUILTIN_PD_PD256,
20700 IX86_BUILTIN_VTESTZPD,
20701 IX86_BUILTIN_VTESTCPD,
20702 IX86_BUILTIN_VTESTNZCPD,
20703 IX86_BUILTIN_VTESTZPS,
20704 IX86_BUILTIN_VTESTCPS,
20705 IX86_BUILTIN_VTESTNZCPS,
20706 IX86_BUILTIN_VTESTZPD256,
20707 IX86_BUILTIN_VTESTCPD256,
20708 IX86_BUILTIN_VTESTNZCPD256,
20709 IX86_BUILTIN_VTESTZPS256,
20710 IX86_BUILTIN_VTESTCPS256,
20711 IX86_BUILTIN_VTESTNZCPS256,
20712 IX86_BUILTIN_PTESTZ256,
20713 IX86_BUILTIN_PTESTC256,
20714 IX86_BUILTIN_PTESTNZC256,
20716 IX86_BUILTIN_MOVMSKPD256,
20717 IX86_BUILTIN_MOVMSKPS256,
20719 /* TFmode support builtins. */
20721 IX86_BUILTIN_HUGE_VALQ,
20722 IX86_BUILTIN_FABSQ,
20723 IX86_BUILTIN_COPYSIGNQ,
20725 /* SSE5 instructions */
20726 IX86_BUILTIN_FMADDSS,
20727 IX86_BUILTIN_FMADDSD,
20728 IX86_BUILTIN_FMADDPS,
20729 IX86_BUILTIN_FMADDPD,
20730 IX86_BUILTIN_FMSUBSS,
20731 IX86_BUILTIN_FMSUBSD,
20732 IX86_BUILTIN_FMSUBPS,
20733 IX86_BUILTIN_FMSUBPD,
20734 IX86_BUILTIN_FNMADDSS,
20735 IX86_BUILTIN_FNMADDSD,
20736 IX86_BUILTIN_FNMADDPS,
20737 IX86_BUILTIN_FNMADDPD,
20738 IX86_BUILTIN_FNMSUBSS,
20739 IX86_BUILTIN_FNMSUBSD,
20740 IX86_BUILTIN_FNMSUBPS,
20741 IX86_BUILTIN_FNMSUBPD,
20742 IX86_BUILTIN_PCMOV,
20743 IX86_BUILTIN_PCMOV_V2DI,
20744 IX86_BUILTIN_PCMOV_V4SI,
20745 IX86_BUILTIN_PCMOV_V8HI,
20746 IX86_BUILTIN_PCMOV_V16QI,
20747 IX86_BUILTIN_PCMOV_V4SF,
20748 IX86_BUILTIN_PCMOV_V2DF,
20749 IX86_BUILTIN_PPERM,
20750 IX86_BUILTIN_PERMPS,
20751 IX86_BUILTIN_PERMPD,
20752 IX86_BUILTIN_PMACSSWW,
20753 IX86_BUILTIN_PMACSWW,
20754 IX86_BUILTIN_PMACSSWD,
20755 IX86_BUILTIN_PMACSWD,
20756 IX86_BUILTIN_PMACSSDD,
20757 IX86_BUILTIN_PMACSDD,
20758 IX86_BUILTIN_PMACSSDQL,
20759 IX86_BUILTIN_PMACSSDQH,
20760 IX86_BUILTIN_PMACSDQL,
20761 IX86_BUILTIN_PMACSDQH,
20762 IX86_BUILTIN_PMADCSSWD,
20763 IX86_BUILTIN_PMADCSWD,
20764 IX86_BUILTIN_PHADDBW,
20765 IX86_BUILTIN_PHADDBD,
20766 IX86_BUILTIN_PHADDBQ,
20767 IX86_BUILTIN_PHADDWD,
20768 IX86_BUILTIN_PHADDWQ,
20769 IX86_BUILTIN_PHADDDQ,
20770 IX86_BUILTIN_PHADDUBW,
20771 IX86_BUILTIN_PHADDUBD,
20772 IX86_BUILTIN_PHADDUBQ,
20773 IX86_BUILTIN_PHADDUWD,
20774 IX86_BUILTIN_PHADDUWQ,
20775 IX86_BUILTIN_PHADDUDQ,
20776 IX86_BUILTIN_PHSUBBW,
20777 IX86_BUILTIN_PHSUBWD,
20778 IX86_BUILTIN_PHSUBDQ,
20779 IX86_BUILTIN_PROTB,
20780 IX86_BUILTIN_PROTW,
20781 IX86_BUILTIN_PROTD,
20782 IX86_BUILTIN_PROTQ,
20783 IX86_BUILTIN_PROTB_IMM,
20784 IX86_BUILTIN_PROTW_IMM,
20785 IX86_BUILTIN_PROTD_IMM,
20786 IX86_BUILTIN_PROTQ_IMM,
20787 IX86_BUILTIN_PSHLB,
20788 IX86_BUILTIN_PSHLW,
20789 IX86_BUILTIN_PSHLD,
20790 IX86_BUILTIN_PSHLQ,
20791 IX86_BUILTIN_PSHAB,
20792 IX86_BUILTIN_PSHAW,
20793 IX86_BUILTIN_PSHAD,
20794 IX86_BUILTIN_PSHAQ,
20795 IX86_BUILTIN_FRCZSS,
20796 IX86_BUILTIN_FRCZSD,
20797 IX86_BUILTIN_FRCZPS,
20798 IX86_BUILTIN_FRCZPD,
20799 IX86_BUILTIN_CVTPH2PS,
20800 IX86_BUILTIN_CVTPS2PH,
20802 IX86_BUILTIN_COMEQSS,
20803 IX86_BUILTIN_COMNESS,
20804 IX86_BUILTIN_COMLTSS,
20805 IX86_BUILTIN_COMLESS,
20806 IX86_BUILTIN_COMGTSS,
20807 IX86_BUILTIN_COMGESS,
20808 IX86_BUILTIN_COMUEQSS,
20809 IX86_BUILTIN_COMUNESS,
20810 IX86_BUILTIN_COMULTSS,
20811 IX86_BUILTIN_COMULESS,
20812 IX86_BUILTIN_COMUGTSS,
20813 IX86_BUILTIN_COMUGESS,
20814 IX86_BUILTIN_COMORDSS,
20815 IX86_BUILTIN_COMUNORDSS,
20816 IX86_BUILTIN_COMFALSESS,
20817 IX86_BUILTIN_COMTRUESS,
20819 IX86_BUILTIN_COMEQSD,
20820 IX86_BUILTIN_COMNESD,
20821 IX86_BUILTIN_COMLTSD,
20822 IX86_BUILTIN_COMLESD,
20823 IX86_BUILTIN_COMGTSD,
20824 IX86_BUILTIN_COMGESD,
20825 IX86_BUILTIN_COMUEQSD,
20826 IX86_BUILTIN_COMUNESD,
20827 IX86_BUILTIN_COMULTSD,
20828 IX86_BUILTIN_COMULESD,
20829 IX86_BUILTIN_COMUGTSD,
20830 IX86_BUILTIN_COMUGESD,
20831 IX86_BUILTIN_COMORDSD,
20832 IX86_BUILTIN_COMUNORDSD,
20833 IX86_BUILTIN_COMFALSESD,
20834 IX86_BUILTIN_COMTRUESD,
20836 IX86_BUILTIN_COMEQPS,
20837 IX86_BUILTIN_COMNEPS,
20838 IX86_BUILTIN_COMLTPS,
20839 IX86_BUILTIN_COMLEPS,
20840 IX86_BUILTIN_COMGTPS,
20841 IX86_BUILTIN_COMGEPS,
20842 IX86_BUILTIN_COMUEQPS,
20843 IX86_BUILTIN_COMUNEPS,
20844 IX86_BUILTIN_COMULTPS,
20845 IX86_BUILTIN_COMULEPS,
20846 IX86_BUILTIN_COMUGTPS,
20847 IX86_BUILTIN_COMUGEPS,
20848 IX86_BUILTIN_COMORDPS,
20849 IX86_BUILTIN_COMUNORDPS,
20850 IX86_BUILTIN_COMFALSEPS,
20851 IX86_BUILTIN_COMTRUEPS,
20853 IX86_BUILTIN_COMEQPD,
20854 IX86_BUILTIN_COMNEPD,
20855 IX86_BUILTIN_COMLTPD,
20856 IX86_BUILTIN_COMLEPD,
20857 IX86_BUILTIN_COMGTPD,
20858 IX86_BUILTIN_COMGEPD,
20859 IX86_BUILTIN_COMUEQPD,
20860 IX86_BUILTIN_COMUNEPD,
20861 IX86_BUILTIN_COMULTPD,
20862 IX86_BUILTIN_COMULEPD,
20863 IX86_BUILTIN_COMUGTPD,
20864 IX86_BUILTIN_COMUGEPD,
20865 IX86_BUILTIN_COMORDPD,
20866 IX86_BUILTIN_COMUNORDPD,
20867 IX86_BUILTIN_COMFALSEPD,
20868 IX86_BUILTIN_COMTRUEPD,
20870 IX86_BUILTIN_PCOMEQUB,
20871 IX86_BUILTIN_PCOMNEUB,
20872 IX86_BUILTIN_PCOMLTUB,
20873 IX86_BUILTIN_PCOMLEUB,
20874 IX86_BUILTIN_PCOMGTUB,
20875 IX86_BUILTIN_PCOMGEUB,
20876 IX86_BUILTIN_PCOMFALSEUB,
20877 IX86_BUILTIN_PCOMTRUEUB,
20878 IX86_BUILTIN_PCOMEQUW,
20879 IX86_BUILTIN_PCOMNEUW,
20880 IX86_BUILTIN_PCOMLTUW,
20881 IX86_BUILTIN_PCOMLEUW,
20882 IX86_BUILTIN_PCOMGTUW,
20883 IX86_BUILTIN_PCOMGEUW,
20884 IX86_BUILTIN_PCOMFALSEUW,
20885 IX86_BUILTIN_PCOMTRUEUW,
20886 IX86_BUILTIN_PCOMEQUD,
20887 IX86_BUILTIN_PCOMNEUD,
20888 IX86_BUILTIN_PCOMLTUD,
20889 IX86_BUILTIN_PCOMLEUD,
20890 IX86_BUILTIN_PCOMGTUD,
20891 IX86_BUILTIN_PCOMGEUD,
20892 IX86_BUILTIN_PCOMFALSEUD,
20893 IX86_BUILTIN_PCOMTRUEUD,
20894 IX86_BUILTIN_PCOMEQUQ,
20895 IX86_BUILTIN_PCOMNEUQ,
20896 IX86_BUILTIN_PCOMLTUQ,
20897 IX86_BUILTIN_PCOMLEUQ,
20898 IX86_BUILTIN_PCOMGTUQ,
20899 IX86_BUILTIN_PCOMGEUQ,
20900 IX86_BUILTIN_PCOMFALSEUQ,
20901 IX86_BUILTIN_PCOMTRUEUQ,
20903 IX86_BUILTIN_PCOMEQB,
20904 IX86_BUILTIN_PCOMNEB,
20905 IX86_BUILTIN_PCOMLTB,
20906 IX86_BUILTIN_PCOMLEB,
20907 IX86_BUILTIN_PCOMGTB,
20908 IX86_BUILTIN_PCOMGEB,
20909 IX86_BUILTIN_PCOMFALSEB,
20910 IX86_BUILTIN_PCOMTRUEB,
20911 IX86_BUILTIN_PCOMEQW,
20912 IX86_BUILTIN_PCOMNEW,
20913 IX86_BUILTIN_PCOMLTW,
20914 IX86_BUILTIN_PCOMLEW,
20915 IX86_BUILTIN_PCOMGTW,
20916 IX86_BUILTIN_PCOMGEW,
20917 IX86_BUILTIN_PCOMFALSEW,
20918 IX86_BUILTIN_PCOMTRUEW,
20919 IX86_BUILTIN_PCOMEQD,
20920 IX86_BUILTIN_PCOMNED,
20921 IX86_BUILTIN_PCOMLTD,
20922 IX86_BUILTIN_PCOMLED,
20923 IX86_BUILTIN_PCOMGTD,
20924 IX86_BUILTIN_PCOMGED,
20925 IX86_BUILTIN_PCOMFALSED,
20926 IX86_BUILTIN_PCOMTRUED,
20927 IX86_BUILTIN_PCOMEQQ,
20928 IX86_BUILTIN_PCOMNEQ,
20929 IX86_BUILTIN_PCOMLTQ,
20930 IX86_BUILTIN_PCOMLEQ,
20931 IX86_BUILTIN_PCOMGTQ,
20932 IX86_BUILTIN_PCOMGEQ,
20933 IX86_BUILTIN_PCOMFALSEQ,
20934 IX86_BUILTIN_PCOMTRUEQ,
20939 /* Table for the ix86 builtin decls. */
20940 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20942 /* Table of all of the builtin functions that are possible with different ISA's
20943 but are waiting to be built until a function is declared to use that
20945 struct GTY(()) builtin_isa {
20946 tree type; /* builtin type to use in the declaration */
20947 const char *name; /* function name */
20948 int isa; /* isa_flags this builtin is defined for */
20949 bool const_p; /* true if the declaration is constant */
20952 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20955 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20956 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20957 * function decl in the ix86_builtins array. Returns the function decl or
20958 * NULL_TREE, if the builtin was not added.
20960 * If the front end has a special hook for builtin functions, delay adding
20961 * builtin functions that aren't in the current ISA until the ISA is changed
20962 * with function specific optimization. Doing so, can save about 300K for the
20963 * default compiler. When the builtin is expanded, check at that time whether
20966 * If the front end doesn't have a special hook, record all builtins, even if
20967 * it isn't an instruction set in the current ISA in case the user uses
20968 * function specific options for a different ISA, so that we don't get scope
20969 * errors if a builtin is added in the middle of a function scope. */
20972 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20974 tree decl = NULL_TREE;
20976 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20978 ix86_builtins_isa[(int) code].isa = mask;
20980 if ((mask & ix86_isa_flags) != 0
20981 || (lang_hooks.builtin_function
20982 == lang_hooks.builtin_function_ext_scope))
20985 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20987 ix86_builtins[(int) code] = decl;
20988 ix86_builtins_isa[(int) code].type = NULL_TREE;
20992 ix86_builtins[(int) code] = NULL_TREE;
20993 ix86_builtins_isa[(int) code].const_p = false;
20994 ix86_builtins_isa[(int) code].type = type;
20995 ix86_builtins_isa[(int) code].name = name;
21002 /* Like def_builtin, but also marks the function decl "const". */
21005 def_builtin_const (int mask, const char *name, tree type,
21006 enum ix86_builtins code)
21008 tree decl = def_builtin (mask, name, type, code);
21010 TREE_READONLY (decl) = 1;
21012 ix86_builtins_isa[(int) code].const_p = true;
21017 /* Add any new builtin functions for a given ISA that may not have been
21018 declared. This saves a bit of space compared to adding all of the
21019 declarations to the tree, even if we didn't use them. */
21022 ix86_add_new_builtins (int isa)
21027 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
21029 if ((ix86_builtins_isa[i].isa & isa) != 0
21030 && ix86_builtins_isa[i].type != NULL_TREE)
21032 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
21033 ix86_builtins_isa[i].type,
21034 i, BUILT_IN_MD, NULL,
21037 ix86_builtins[i] = decl;
21038 ix86_builtins_isa[i].type = NULL_TREE;
21039 if (ix86_builtins_isa[i].const_p)
21040 TREE_READONLY (decl) = 1;
21045 /* Bits for builtin_description.flag. */
21047 /* Set when we don't support the comparison natively, and should
21048 swap_comparison in order to support it. */
21049 #define BUILTIN_DESC_SWAP_OPERANDS 1
21051 struct builtin_description
21053 const unsigned int mask;
21054 const enum insn_code icode;
21055 const char *const name;
21056 const enum ix86_builtins code;
21057 const enum rtx_code comparison;
21061 static const struct builtin_description bdesc_comi[] =
21063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21065 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21068 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21069 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21070 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21089 static const struct builtin_description bdesc_pcmpestr[] =
21092 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21093 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21094 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21095 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21096 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21097 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21098 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21101 static const struct builtin_description bdesc_pcmpistr[] =
21104 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21105 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21106 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21107 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21108 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21109 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21110 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21113 /* Special builtin types */
21114 enum ix86_special_builtin_type
21116 SPECIAL_FTYPE_UNKNOWN,
21118 V32QI_FTYPE_PCCHAR,
21119 V16QI_FTYPE_PCCHAR,
21121 V8SF_FTYPE_PCFLOAT,
21123 V4DF_FTYPE_PCDOUBLE,
21124 V4SF_FTYPE_PCFLOAT,
21125 V2DF_FTYPE_PCDOUBLE,
21126 V8SF_FTYPE_PCV8SF_V8SF,
21127 V4DF_FTYPE_PCV4DF_V4DF,
21128 V4SF_FTYPE_V4SF_PCV2SF,
21129 V4SF_FTYPE_PCV4SF_V4SF,
21130 V2DF_FTYPE_V2DF_PCDOUBLE,
21131 V2DF_FTYPE_PCV2DF_V2DF,
21133 VOID_FTYPE_PV2SF_V4SF,
21134 VOID_FTYPE_PV4DI_V4DI,
21135 VOID_FTYPE_PV2DI_V2DI,
21136 VOID_FTYPE_PCHAR_V32QI,
21137 VOID_FTYPE_PCHAR_V16QI,
21138 VOID_FTYPE_PFLOAT_V8SF,
21139 VOID_FTYPE_PFLOAT_V4SF,
21140 VOID_FTYPE_PDOUBLE_V4DF,
21141 VOID_FTYPE_PDOUBLE_V2DF,
21143 VOID_FTYPE_PINT_INT,
21144 VOID_FTYPE_PV8SF_V8SF_V8SF,
21145 VOID_FTYPE_PV4DF_V4DF_V4DF,
21146 VOID_FTYPE_PV4SF_V4SF_V4SF,
21147 VOID_FTYPE_PV2DF_V2DF_V2DF
21150 /* Builtin types */
21151 enum ix86_builtin_type
21154 FLOAT128_FTYPE_FLOAT128,
21156 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21157 INT_FTYPE_V8SF_V8SF_PTEST,
21158 INT_FTYPE_V4DI_V4DI_PTEST,
21159 INT_FTYPE_V4DF_V4DF_PTEST,
21160 INT_FTYPE_V4SF_V4SF_PTEST,
21161 INT_FTYPE_V2DI_V2DI_PTEST,
21162 INT_FTYPE_V2DF_V2DF_PTEST,
21194 V4SF_FTYPE_V4SF_VEC_MERGE,
21203 V2DF_FTYPE_V2DF_VEC_MERGE,
21214 V16QI_FTYPE_V16QI_V16QI,
21215 V16QI_FTYPE_V8HI_V8HI,
21216 V8QI_FTYPE_V8QI_V8QI,
21217 V8QI_FTYPE_V4HI_V4HI,
21218 V8HI_FTYPE_V8HI_V8HI,
21219 V8HI_FTYPE_V8HI_V8HI_COUNT,
21220 V8HI_FTYPE_V16QI_V16QI,
21221 V8HI_FTYPE_V4SI_V4SI,
21222 V8HI_FTYPE_V8HI_SI_COUNT,
21223 V8SF_FTYPE_V8SF_V8SF,
21224 V8SF_FTYPE_V8SF_V8SI,
21225 V4SI_FTYPE_V4SI_V4SI,
21226 V4SI_FTYPE_V4SI_V4SI_COUNT,
21227 V4SI_FTYPE_V8HI_V8HI,
21228 V4SI_FTYPE_V4SF_V4SF,
21229 V4SI_FTYPE_V2DF_V2DF,
21230 V4SI_FTYPE_V4SI_SI_COUNT,
21231 V4HI_FTYPE_V4HI_V4HI,
21232 V4HI_FTYPE_V4HI_V4HI_COUNT,
21233 V4HI_FTYPE_V8QI_V8QI,
21234 V4HI_FTYPE_V2SI_V2SI,
21235 V4HI_FTYPE_V4HI_SI_COUNT,
21236 V4DF_FTYPE_V4DF_V4DF,
21237 V4DF_FTYPE_V4DF_V4DI,
21238 V4SF_FTYPE_V4SF_V4SF,
21239 V4SF_FTYPE_V4SF_V4SF_SWAP,
21240 V4SF_FTYPE_V4SF_V4SI,
21241 V4SF_FTYPE_V4SF_V2SI,
21242 V4SF_FTYPE_V4SF_V2DF,
21243 V4SF_FTYPE_V4SF_DI,
21244 V4SF_FTYPE_V4SF_SI,
21245 V2DI_FTYPE_V2DI_V2DI,
21246 V2DI_FTYPE_V2DI_V2DI_COUNT,
21247 V2DI_FTYPE_V16QI_V16QI,
21248 V2DI_FTYPE_V4SI_V4SI,
21249 V2DI_FTYPE_V2DI_V16QI,
21250 V2DI_FTYPE_V2DF_V2DF,
21251 V2DI_FTYPE_V2DI_SI_COUNT,
21252 V2SI_FTYPE_V2SI_V2SI,
21253 V2SI_FTYPE_V2SI_V2SI_COUNT,
21254 V2SI_FTYPE_V4HI_V4HI,
21255 V2SI_FTYPE_V2SF_V2SF,
21256 V2SI_FTYPE_V2SI_SI_COUNT,
21257 V2DF_FTYPE_V2DF_V2DF,
21258 V2DF_FTYPE_V2DF_V2DF_SWAP,
21259 V2DF_FTYPE_V2DF_V4SF,
21260 V2DF_FTYPE_V2DF_V2DI,
21261 V2DF_FTYPE_V2DF_DI,
21262 V2DF_FTYPE_V2DF_SI,
21263 V2SF_FTYPE_V2SF_V2SF,
21264 V1DI_FTYPE_V1DI_V1DI,
21265 V1DI_FTYPE_V1DI_V1DI_COUNT,
21266 V1DI_FTYPE_V8QI_V8QI,
21267 V1DI_FTYPE_V2SI_V2SI,
21268 V1DI_FTYPE_V1DI_SI_COUNT,
21269 UINT64_FTYPE_UINT64_UINT64,
21270 UINT_FTYPE_UINT_UINT,
21271 UINT_FTYPE_UINT_USHORT,
21272 UINT_FTYPE_UINT_UCHAR,
21273 V8HI_FTYPE_V8HI_INT,
21274 V4SI_FTYPE_V4SI_INT,
21275 V4HI_FTYPE_V4HI_INT,
21276 V8SF_FTYPE_V8SF_INT,
21277 V4SI_FTYPE_V8SI_INT,
21278 V4SF_FTYPE_V8SF_INT,
21279 V2DF_FTYPE_V4DF_INT,
21280 V4DF_FTYPE_V4DF_INT,
21281 V4SF_FTYPE_V4SF_INT,
21282 V2DI_FTYPE_V2DI_INT,
21283 V2DI2TI_FTYPE_V2DI_INT,
21284 V2DF_FTYPE_V2DF_INT,
21285 V16QI_FTYPE_V16QI_V16QI_V16QI,
21286 V8SF_FTYPE_V8SF_V8SF_V8SF,
21287 V4DF_FTYPE_V4DF_V4DF_V4DF,
21288 V4SF_FTYPE_V4SF_V4SF_V4SF,
21289 V2DF_FTYPE_V2DF_V2DF_V2DF,
21290 V16QI_FTYPE_V16QI_V16QI_INT,
21291 V8SI_FTYPE_V8SI_V8SI_INT,
21292 V8SI_FTYPE_V8SI_V4SI_INT,
21293 V8HI_FTYPE_V8HI_V8HI_INT,
21294 V8SF_FTYPE_V8SF_V8SF_INT,
21295 V8SF_FTYPE_V8SF_V4SF_INT,
21296 V4SI_FTYPE_V4SI_V4SI_INT,
21297 V4DF_FTYPE_V4DF_V4DF_INT,
21298 V4DF_FTYPE_V4DF_V2DF_INT,
21299 V4SF_FTYPE_V4SF_V4SF_INT,
21300 V2DI_FTYPE_V2DI_V2DI_INT,
21301 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21302 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21303 V2DF_FTYPE_V2DF_V2DF_INT,
21304 V2DI_FTYPE_V2DI_UINT_UINT,
21305 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21308 /* Special builtins with variable number of arguments. */
21309 static const struct builtin_description bdesc_special_args[] =
21312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21315 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21318 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21320 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21323 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21327 /* SSE or 3DNow!A */
21328 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21329 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21346 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21349 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21352 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21353 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21356 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21357 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21358 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21364 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21374 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21378 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21379 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21384 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21388 /* Builtins with variable number of arguments. */
21389 static const struct builtin_description bdesc_args[] =
21392 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21393 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21394 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21395 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21396 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21397 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21399 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21400 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21401 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21402 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21403 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21404 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21405 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21406 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21408 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21409 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21411 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21412 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21413 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21414 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21416 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21417 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21418 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21419 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21420 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21421 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21423 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21424 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21425 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21426 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21427 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21428 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21430 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21431 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21432 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21434 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21436 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21437 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21438 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21439 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21440 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21441 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21443 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21444 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21445 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21446 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21447 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21448 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21450 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21451 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21452 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21453 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21456 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21457 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21458 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21459 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21461 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21462 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21463 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21464 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21465 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21466 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21467 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21468 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21469 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21470 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21471 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21472 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21473 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21474 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21475 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21478 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21479 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21480 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21481 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21482 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21483 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21486 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21487 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21488 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21489 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21490 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21491 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21492 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21493 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21494 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21495 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21496 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21497 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21499 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21501 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21502 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21503 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21504 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21505 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21506 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21507 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21508 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21510 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21511 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21512 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21513 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21514 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21515 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21516 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21517 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21519 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21520 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21521 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21522 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21523 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21524 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21525 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21526 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21527 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21528 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21529 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21530 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21531 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21533 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21534 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21536 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21538 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21539 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21540 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21541 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21543 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21544 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21545 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21546 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21547 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21549 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21550 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21551 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21553 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21555 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21557 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21559 /* SSE MMX or 3Dnow!A */
21560 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21561 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21562 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21564 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21565 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21566 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21567 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21569 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21570 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21572 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21587 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21593 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21594 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21597 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21598 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21600 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21601 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21602 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21603 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21607 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21618 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21619 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21623 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21625 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21626 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21628 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21630 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21631 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21632 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21633 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21635 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21636 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21637 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21638 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21640 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21641 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21642 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21644 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21646 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21647 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21648 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21649 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21650 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21651 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21652 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21653 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21655 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21656 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21657 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21660 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21664 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21665 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21667 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21668 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21669 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21670 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21672 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21673 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21675 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21676 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21677 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21678 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21679 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21680 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21682 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21683 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21684 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21687 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21688 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21692 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21700 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21701 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21708 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21709 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21711 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21714 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21715 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21716 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21717 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21718 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21719 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21722 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21723 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21724 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21725 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21726 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21727 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21729 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21730 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21731 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21732 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21734 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21740 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21741 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21746 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21747 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21750 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21751 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21753 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21754 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21755 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21756 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21757 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21758 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21761 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21762 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21763 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21764 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21765 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21766 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21768 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21769 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21770 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21771 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21772 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21773 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21774 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21775 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21776 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21777 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21778 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21779 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21780 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21781 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21782 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21783 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21784 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21785 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21786 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21787 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21788 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21789 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21790 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21791 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21794 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21795 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21798 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21799 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21800 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21801 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21802 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21803 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21804 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21805 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21806 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21807 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21809 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21810 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21811 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21812 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21813 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21814 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21815 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21816 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21817 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21818 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21819 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21820 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21821 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21823 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21824 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21825 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21826 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21827 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21828 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21829 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21830 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21831 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21832 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21833 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21834 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21836 /* SSE4.1 and SSE5 */
21837 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21838 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21839 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21840 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21842 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21843 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21844 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21847 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21848 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21849 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21850 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21851 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21854 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21855 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21856 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21857 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21860 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21861 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21864 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21866 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21869 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21872 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21873 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21876 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21877 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21880 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21881 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21886 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21887 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21888 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21889 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21890 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21891 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21892 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21893 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21894 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21895 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21896 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21897 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21922 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21923 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21926 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21927 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21932 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21934 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21939 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21940 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21941 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21943 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21944 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21945 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21946 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21947 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21949 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21951 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21952 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21954 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21955 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21956 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21957 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21959 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21960 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21961 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21962 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21963 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21964 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21966 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21967 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21968 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21969 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21970 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21971 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21972 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21973 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21974 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21975 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21976 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21977 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21978 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21979 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21980 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21982 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21983 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21987 enum multi_arg_type {
21997 MULTI_ARG_3_PERMPS,
21998 MULTI_ARG_3_PERMPD,
22005 MULTI_ARG_2_DI_IMM,
22006 MULTI_ARG_2_SI_IMM,
22007 MULTI_ARG_2_HI_IMM,
22008 MULTI_ARG_2_QI_IMM,
22009 MULTI_ARG_2_SF_CMP,
22010 MULTI_ARG_2_DF_CMP,
22011 MULTI_ARG_2_DI_CMP,
22012 MULTI_ARG_2_SI_CMP,
22013 MULTI_ARG_2_HI_CMP,
22014 MULTI_ARG_2_QI_CMP,
22037 static const struct builtin_description bdesc_multi_arg[] =
22039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22040 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22054 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22057 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22059 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22063 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, UNKNOWN, (int)MULTI_ARG_3_PERMPS },
22064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, UNKNOWN, (int)MULTI_ARG_3_PERMPD },
22065 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22072 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22073 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22074 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22076 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22081 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22082 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22083 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22084 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22085 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22086 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22087 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22088 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22089 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22090 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22091 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22092 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22093 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22094 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22095 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22096 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22097 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int)MULTI_ARG_1_PH2PS },
22098 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int)MULTI_ARG_1_PS2PH },
22099 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22100 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22101 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22102 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22103 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22104 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22105 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22106 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22107 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22108 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22109 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22110 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22111 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22112 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22113 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22115 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
22116 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
22117 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
22118 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
22119 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
22120 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
22121 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
22122 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
22123 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22124 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22125 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
22126 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
22127 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
22128 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
22129 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
22130 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
22132 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
22133 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
22134 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
22135 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
22136 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
22137 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
22138 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
22139 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
22140 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22141 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22142 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
22143 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
22144 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
22145 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
22146 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
22147 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
22149 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
22150 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
22151 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
22152 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
22153 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
22154 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
22155 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
22156 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
22157 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22158 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22159 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
22160 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
22161 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
22162 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
22163 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
22164 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
22166 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
22167 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
22168 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
22169 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
22170 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
22171 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
22172 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
22173 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
22174 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22175 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22176 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
22177 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
22178 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
22179 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
22180 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
22181 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
22183 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22184 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22185 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22186 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22187 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22188 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22189 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22191 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22192 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22193 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22194 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22195 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22196 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22197 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22199 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22200 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22201 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22202 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22203 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22204 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22205 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22207 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22208 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22209 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22210 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22211 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22212 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22213 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22215 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22216 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22217 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22218 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22219 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22220 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22221 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22223 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22224 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22225 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22226 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22227 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22228 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22229 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22231 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22232 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22233 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22234 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22235 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22236 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22237 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22239 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22240 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22241 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22242 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22243 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22244 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22245 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22247 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
22248 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
22249 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
22250 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
22251 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
22252 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
22253 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
22254 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
22256 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22257 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22258 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22259 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22260 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22261 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22262 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22263 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22265 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22266 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22267 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22268 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22269 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22270 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22271 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22272 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22275 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22276 in the current target ISA to allow the user to compile particular modules
22277 with different target specific options that differ from the command line
22280 ix86_init_mmx_sse_builtins (void)
22282 const struct builtin_description * d;
22285 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
22286 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
22287 tree V1DI_type_node
22288 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
22289 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
22290 tree V2DI_type_node
22291 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
22292 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
22293 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
22294 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
22295 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
22296 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
22297 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
22299 tree pchar_type_node = build_pointer_type (char_type_node);
22300 tree pcchar_type_node
22301 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
22302 tree pfloat_type_node = build_pointer_type (float_type_node);
22303 tree pcfloat_type_node
22304 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
22305 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
22306 tree pcv2sf_type_node
22307 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
22308 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
22309 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
22312 tree int_ftype_v4sf_v4sf
22313 = build_function_type_list (integer_type_node,
22314 V4SF_type_node, V4SF_type_node, NULL_TREE);
22315 tree v4si_ftype_v4sf_v4sf
22316 = build_function_type_list (V4SI_type_node,
22317 V4SF_type_node, V4SF_type_node, NULL_TREE);
22318 /* MMX/SSE/integer conversions. */
22319 tree int_ftype_v4sf
22320 = build_function_type_list (integer_type_node,
22321 V4SF_type_node, NULL_TREE);
22322 tree int64_ftype_v4sf
22323 = build_function_type_list (long_long_integer_type_node,
22324 V4SF_type_node, NULL_TREE);
22325 tree int_ftype_v8qi
22326 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22327 tree v4sf_ftype_v4sf_int
22328 = build_function_type_list (V4SF_type_node,
22329 V4SF_type_node, integer_type_node, NULL_TREE);
22330 tree v4sf_ftype_v4sf_int64
22331 = build_function_type_list (V4SF_type_node,
22332 V4SF_type_node, long_long_integer_type_node,
22334 tree v4sf_ftype_v4sf_v2si
22335 = build_function_type_list (V4SF_type_node,
22336 V4SF_type_node, V2SI_type_node, NULL_TREE);
22338 /* Miscellaneous. */
22339 tree v8qi_ftype_v4hi_v4hi
22340 = build_function_type_list (V8QI_type_node,
22341 V4HI_type_node, V4HI_type_node, NULL_TREE);
22342 tree v4hi_ftype_v2si_v2si
22343 = build_function_type_list (V4HI_type_node,
22344 V2SI_type_node, V2SI_type_node, NULL_TREE);
22345 tree v4sf_ftype_v4sf_v4sf_int
22346 = build_function_type_list (V4SF_type_node,
22347 V4SF_type_node, V4SF_type_node,
22348 integer_type_node, NULL_TREE);
22349 tree v2si_ftype_v4hi_v4hi
22350 = build_function_type_list (V2SI_type_node,
22351 V4HI_type_node, V4HI_type_node, NULL_TREE);
22352 tree v4hi_ftype_v4hi_int
22353 = build_function_type_list (V4HI_type_node,
22354 V4HI_type_node, integer_type_node, NULL_TREE);
22355 tree v2si_ftype_v2si_int
22356 = build_function_type_list (V2SI_type_node,
22357 V2SI_type_node, integer_type_node, NULL_TREE);
22358 tree v1di_ftype_v1di_int
22359 = build_function_type_list (V1DI_type_node,
22360 V1DI_type_node, integer_type_node, NULL_TREE);
22362 tree void_ftype_void
22363 = build_function_type (void_type_node, void_list_node);
22364 tree void_ftype_unsigned
22365 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22366 tree void_ftype_unsigned_unsigned
22367 = build_function_type_list (void_type_node, unsigned_type_node,
22368 unsigned_type_node, NULL_TREE);
22369 tree void_ftype_pcvoid_unsigned_unsigned
22370 = build_function_type_list (void_type_node, const_ptr_type_node,
22371 unsigned_type_node, unsigned_type_node,
22373 tree unsigned_ftype_void
22374 = build_function_type (unsigned_type_node, void_list_node);
22375 tree v2si_ftype_v4sf
22376 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22377 /* Loads/stores. */
22378 tree void_ftype_v8qi_v8qi_pchar
22379 = build_function_type_list (void_type_node,
22380 V8QI_type_node, V8QI_type_node,
22381 pchar_type_node, NULL_TREE);
22382 tree v4sf_ftype_pcfloat
22383 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22384 tree v4sf_ftype_v4sf_pcv2sf
22385 = build_function_type_list (V4SF_type_node,
22386 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22387 tree void_ftype_pv2sf_v4sf
22388 = build_function_type_list (void_type_node,
22389 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22390 tree void_ftype_pfloat_v4sf
22391 = build_function_type_list (void_type_node,
22392 pfloat_type_node, V4SF_type_node, NULL_TREE);
22393 tree void_ftype_pdi_di
22394 = build_function_type_list (void_type_node,
22395 pdi_type_node, long_long_unsigned_type_node,
22397 tree void_ftype_pv2di_v2di
22398 = build_function_type_list (void_type_node,
22399 pv2di_type_node, V2DI_type_node, NULL_TREE);
22400 /* Normal vector unops. */
22401 tree v4sf_ftype_v4sf
22402 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22403 tree v16qi_ftype_v16qi
22404 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22405 tree v8hi_ftype_v8hi
22406 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22407 tree v4si_ftype_v4si
22408 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22409 tree v8qi_ftype_v8qi
22410 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22411 tree v4hi_ftype_v4hi
22412 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22414 /* Normal vector binops. */
22415 tree v4sf_ftype_v4sf_v4sf
22416 = build_function_type_list (V4SF_type_node,
22417 V4SF_type_node, V4SF_type_node, NULL_TREE);
22418 tree v8qi_ftype_v8qi_v8qi
22419 = build_function_type_list (V8QI_type_node,
22420 V8QI_type_node, V8QI_type_node, NULL_TREE);
22421 tree v4hi_ftype_v4hi_v4hi
22422 = build_function_type_list (V4HI_type_node,
22423 V4HI_type_node, V4HI_type_node, NULL_TREE);
22424 tree v2si_ftype_v2si_v2si
22425 = build_function_type_list (V2SI_type_node,
22426 V2SI_type_node, V2SI_type_node, NULL_TREE);
22427 tree v1di_ftype_v1di_v1di
22428 = build_function_type_list (V1DI_type_node,
22429 V1DI_type_node, V1DI_type_node, NULL_TREE);
22430 tree v1di_ftype_v1di_v1di_int
22431 = build_function_type_list (V1DI_type_node,
22432 V1DI_type_node, V1DI_type_node,
22433 integer_type_node, NULL_TREE);
22434 tree v2si_ftype_v2sf
22435 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22436 tree v2sf_ftype_v2si
22437 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22438 tree v2si_ftype_v2si
22439 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22440 tree v2sf_ftype_v2sf
22441 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22442 tree v2sf_ftype_v2sf_v2sf
22443 = build_function_type_list (V2SF_type_node,
22444 V2SF_type_node, V2SF_type_node, NULL_TREE);
22445 tree v2si_ftype_v2sf_v2sf
22446 = build_function_type_list (V2SI_type_node,
22447 V2SF_type_node, V2SF_type_node, NULL_TREE);
22448 tree pint_type_node = build_pointer_type (integer_type_node);
22449 tree pdouble_type_node = build_pointer_type (double_type_node);
22450 tree pcdouble_type_node = build_pointer_type (
22451 build_type_variant (double_type_node, 1, 0));
22452 tree int_ftype_v2df_v2df
22453 = build_function_type_list (integer_type_node,
22454 V2DF_type_node, V2DF_type_node, NULL_TREE);
22456 tree void_ftype_pcvoid
22457 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22458 tree v4sf_ftype_v4si
22459 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22460 tree v4si_ftype_v4sf
22461 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22462 tree v2df_ftype_v4si
22463 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22464 tree v4si_ftype_v2df
22465 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22466 tree v4si_ftype_v2df_v2df
22467 = build_function_type_list (V4SI_type_node,
22468 V2DF_type_node, V2DF_type_node, NULL_TREE);
22469 tree v2si_ftype_v2df
22470 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22471 tree v4sf_ftype_v2df
22472 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22473 tree v2df_ftype_v2si
22474 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22475 tree v2df_ftype_v4sf
22476 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22477 tree int_ftype_v2df
22478 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22479 tree int64_ftype_v2df
22480 = build_function_type_list (long_long_integer_type_node,
22481 V2DF_type_node, NULL_TREE);
22482 tree v2df_ftype_v2df_int
22483 = build_function_type_list (V2DF_type_node,
22484 V2DF_type_node, integer_type_node, NULL_TREE);
22485 tree v2df_ftype_v2df_int64
22486 = build_function_type_list (V2DF_type_node,
22487 V2DF_type_node, long_long_integer_type_node,
22489 tree v4sf_ftype_v4sf_v2df
22490 = build_function_type_list (V4SF_type_node,
22491 V4SF_type_node, V2DF_type_node, NULL_TREE);
22492 tree v2df_ftype_v2df_v4sf
22493 = build_function_type_list (V2DF_type_node,
22494 V2DF_type_node, V4SF_type_node, NULL_TREE);
22495 tree v2df_ftype_v2df_v2df_int
22496 = build_function_type_list (V2DF_type_node,
22497 V2DF_type_node, V2DF_type_node,
22500 tree v2df_ftype_v2df_pcdouble
22501 = build_function_type_list (V2DF_type_node,
22502 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22503 tree void_ftype_pdouble_v2df
22504 = build_function_type_list (void_type_node,
22505 pdouble_type_node, V2DF_type_node, NULL_TREE);
22506 tree void_ftype_pint_int
22507 = build_function_type_list (void_type_node,
22508 pint_type_node, integer_type_node, NULL_TREE);
22509 tree void_ftype_v16qi_v16qi_pchar
22510 = build_function_type_list (void_type_node,
22511 V16QI_type_node, V16QI_type_node,
22512 pchar_type_node, NULL_TREE);
22513 tree v2df_ftype_pcdouble
22514 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22515 tree v2df_ftype_v2df_v2df
22516 = build_function_type_list (V2DF_type_node,
22517 V2DF_type_node, V2DF_type_node, NULL_TREE);
22518 tree v16qi_ftype_v16qi_v16qi
22519 = build_function_type_list (V16QI_type_node,
22520 V16QI_type_node, V16QI_type_node, NULL_TREE);
22521 tree v8hi_ftype_v8hi_v8hi
22522 = build_function_type_list (V8HI_type_node,
22523 V8HI_type_node, V8HI_type_node, NULL_TREE);
22524 tree v4si_ftype_v4si_v4si
22525 = build_function_type_list (V4SI_type_node,
22526 V4SI_type_node, V4SI_type_node, NULL_TREE);
22527 tree v2di_ftype_v2di_v2di
22528 = build_function_type_list (V2DI_type_node,
22529 V2DI_type_node, V2DI_type_node, NULL_TREE);
22530 tree v2di_ftype_v2df_v2df
22531 = build_function_type_list (V2DI_type_node,
22532 V2DF_type_node, V2DF_type_node, NULL_TREE);
22533 tree v2df_ftype_v2df
22534 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22535 tree v2di_ftype_v2di_int
22536 = build_function_type_list (V2DI_type_node,
22537 V2DI_type_node, integer_type_node, NULL_TREE);
22538 tree v2di_ftype_v2di_v2di_int
22539 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22540 V2DI_type_node, integer_type_node, NULL_TREE);
22541 tree v4si_ftype_v4si_int
22542 = build_function_type_list (V4SI_type_node,
22543 V4SI_type_node, integer_type_node, NULL_TREE);
22544 tree v8hi_ftype_v8hi_int
22545 = build_function_type_list (V8HI_type_node,
22546 V8HI_type_node, integer_type_node, NULL_TREE);
22547 tree v4si_ftype_v8hi_v8hi
22548 = build_function_type_list (V4SI_type_node,
22549 V8HI_type_node, V8HI_type_node, NULL_TREE);
22550 tree v1di_ftype_v8qi_v8qi
22551 = build_function_type_list (V1DI_type_node,
22552 V8QI_type_node, V8QI_type_node, NULL_TREE);
22553 tree v1di_ftype_v2si_v2si
22554 = build_function_type_list (V1DI_type_node,
22555 V2SI_type_node, V2SI_type_node, NULL_TREE);
22556 tree v2di_ftype_v16qi_v16qi
22557 = build_function_type_list (V2DI_type_node,
22558 V16QI_type_node, V16QI_type_node, NULL_TREE);
22559 tree v2di_ftype_v4si_v4si
22560 = build_function_type_list (V2DI_type_node,
22561 V4SI_type_node, V4SI_type_node, NULL_TREE);
22562 tree int_ftype_v16qi
22563 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22564 tree v16qi_ftype_pcchar
22565 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22566 tree void_ftype_pchar_v16qi
22567 = build_function_type_list (void_type_node,
22568 pchar_type_node, V16QI_type_node, NULL_TREE);
22570 tree v2di_ftype_v2di_unsigned_unsigned
22571 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22572 unsigned_type_node, unsigned_type_node,
22574 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22575 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22576 unsigned_type_node, unsigned_type_node,
22578 tree v2di_ftype_v2di_v16qi
22579 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22581 tree v2df_ftype_v2df_v2df_v2df
22582 = build_function_type_list (V2DF_type_node,
22583 V2DF_type_node, V2DF_type_node,
22584 V2DF_type_node, NULL_TREE);
22585 tree v4sf_ftype_v4sf_v4sf_v4sf
22586 = build_function_type_list (V4SF_type_node,
22587 V4SF_type_node, V4SF_type_node,
22588 V4SF_type_node, NULL_TREE);
22589 tree v8hi_ftype_v16qi
22590 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22592 tree v4si_ftype_v16qi
22593 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22595 tree v2di_ftype_v16qi
22596 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22598 tree v4si_ftype_v8hi
22599 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22601 tree v2di_ftype_v8hi
22602 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22604 tree v2di_ftype_v4si
22605 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22607 tree v2di_ftype_pv2di
22608 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22610 tree v16qi_ftype_v16qi_v16qi_int
22611 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22612 V16QI_type_node, integer_type_node,
22614 tree v16qi_ftype_v16qi_v16qi_v16qi
22615 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22616 V16QI_type_node, V16QI_type_node,
22618 tree v8hi_ftype_v8hi_v8hi_int
22619 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22620 V8HI_type_node, integer_type_node,
22622 tree v4si_ftype_v4si_v4si_int
22623 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22624 V4SI_type_node, integer_type_node,
22626 tree int_ftype_v2di_v2di
22627 = build_function_type_list (integer_type_node,
22628 V2DI_type_node, V2DI_type_node,
22630 tree int_ftype_v16qi_int_v16qi_int_int
22631 = build_function_type_list (integer_type_node,
22638 tree v16qi_ftype_v16qi_int_v16qi_int_int
22639 = build_function_type_list (V16QI_type_node,
22646 tree int_ftype_v16qi_v16qi_int
22647 = build_function_type_list (integer_type_node,
22653 /* SSE5 instructions */
22654 tree v2di_ftype_v2di_v2di_v2di
22655 = build_function_type_list (V2DI_type_node,
22661 tree v4si_ftype_v4si_v4si_v4si
22662 = build_function_type_list (V4SI_type_node,
22668 tree v4si_ftype_v4si_v4si_v2di
22669 = build_function_type_list (V4SI_type_node,
22675 tree v8hi_ftype_v8hi_v8hi_v8hi
22676 = build_function_type_list (V8HI_type_node,
22682 tree v8hi_ftype_v8hi_v8hi_v4si
22683 = build_function_type_list (V8HI_type_node,
22689 tree v2df_ftype_v2df_v2df_v16qi
22690 = build_function_type_list (V2DF_type_node,
22696 tree v4sf_ftype_v4sf_v4sf_v16qi
22697 = build_function_type_list (V4SF_type_node,
22703 tree v2di_ftype_v2di_si
22704 = build_function_type_list (V2DI_type_node,
22709 tree v4si_ftype_v4si_si
22710 = build_function_type_list (V4SI_type_node,
22715 tree v8hi_ftype_v8hi_si
22716 = build_function_type_list (V8HI_type_node,
22721 tree v16qi_ftype_v16qi_si
22722 = build_function_type_list (V16QI_type_node,
22726 tree v4sf_ftype_v4hi
22727 = build_function_type_list (V4SF_type_node,
22731 tree v4hi_ftype_v4sf
22732 = build_function_type_list (V4HI_type_node,
22736 tree v2di_ftype_v2di
22737 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22739 tree v16qi_ftype_v8hi_v8hi
22740 = build_function_type_list (V16QI_type_node,
22741 V8HI_type_node, V8HI_type_node,
22743 tree v8hi_ftype_v4si_v4si
22744 = build_function_type_list (V8HI_type_node,
22745 V4SI_type_node, V4SI_type_node,
22747 tree v8hi_ftype_v16qi_v16qi
22748 = build_function_type_list (V8HI_type_node,
22749 V16QI_type_node, V16QI_type_node,
22751 tree v4hi_ftype_v8qi_v8qi
22752 = build_function_type_list (V4HI_type_node,
22753 V8QI_type_node, V8QI_type_node,
22755 tree unsigned_ftype_unsigned_uchar
22756 = build_function_type_list (unsigned_type_node,
22757 unsigned_type_node,
22758 unsigned_char_type_node,
22760 tree unsigned_ftype_unsigned_ushort
22761 = build_function_type_list (unsigned_type_node,
22762 unsigned_type_node,
22763 short_unsigned_type_node,
22765 tree unsigned_ftype_unsigned_unsigned
22766 = build_function_type_list (unsigned_type_node,
22767 unsigned_type_node,
22768 unsigned_type_node,
22770 tree uint64_ftype_uint64_uint64
22771 = build_function_type_list (long_long_unsigned_type_node,
22772 long_long_unsigned_type_node,
22773 long_long_unsigned_type_node,
22775 tree float_ftype_float
22776 = build_function_type_list (float_type_node,
22781 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22783 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22785 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22787 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22789 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22791 tree v8sf_ftype_v8sf
22792 = build_function_type_list (V8SF_type_node,
22795 tree v8si_ftype_v8sf
22796 = build_function_type_list (V8SI_type_node,
22799 tree v8sf_ftype_v8si
22800 = build_function_type_list (V8SF_type_node,
22803 tree v4si_ftype_v4df
22804 = build_function_type_list (V4SI_type_node,
22807 tree v4df_ftype_v4df
22808 = build_function_type_list (V4DF_type_node,
22811 tree v4df_ftype_v4si
22812 = build_function_type_list (V4DF_type_node,
22815 tree v4df_ftype_v4sf
22816 = build_function_type_list (V4DF_type_node,
22819 tree v4sf_ftype_v4df
22820 = build_function_type_list (V4SF_type_node,
22823 tree v8sf_ftype_v8sf_v8sf
22824 = build_function_type_list (V8SF_type_node,
22825 V8SF_type_node, V8SF_type_node,
22827 tree v4df_ftype_v4df_v4df
22828 = build_function_type_list (V4DF_type_node,
22829 V4DF_type_node, V4DF_type_node,
22831 tree v8sf_ftype_v8sf_int
22832 = build_function_type_list (V8SF_type_node,
22833 V8SF_type_node, integer_type_node,
22835 tree v4si_ftype_v8si_int
22836 = build_function_type_list (V4SI_type_node,
22837 V8SI_type_node, integer_type_node,
22839 tree v4df_ftype_v4df_int
22840 = build_function_type_list (V4DF_type_node,
22841 V4DF_type_node, integer_type_node,
22843 tree v4sf_ftype_v8sf_int
22844 = build_function_type_list (V4SF_type_node,
22845 V8SF_type_node, integer_type_node,
22847 tree v2df_ftype_v4df_int
22848 = build_function_type_list (V2DF_type_node,
22849 V4DF_type_node, integer_type_node,
22851 tree v8sf_ftype_v8sf_v8sf_int
22852 = build_function_type_list (V8SF_type_node,
22853 V8SF_type_node, V8SF_type_node,
22856 tree v8sf_ftype_v8sf_v8sf_v8sf
22857 = build_function_type_list (V8SF_type_node,
22858 V8SF_type_node, V8SF_type_node,
22861 tree v4df_ftype_v4df_v4df_v4df
22862 = build_function_type_list (V4DF_type_node,
22863 V4DF_type_node, V4DF_type_node,
22866 tree v8si_ftype_v8si_v8si_int
22867 = build_function_type_list (V8SI_type_node,
22868 V8SI_type_node, V8SI_type_node,
22871 tree v4df_ftype_v4df_v4df_int
22872 = build_function_type_list (V4DF_type_node,
22873 V4DF_type_node, V4DF_type_node,
22876 tree v8sf_ftype_pcfloat
22877 = build_function_type_list (V8SF_type_node,
22880 tree v4df_ftype_pcdouble
22881 = build_function_type_list (V4DF_type_node,
22882 pcdouble_type_node,
22884 tree pcv4sf_type_node
22885 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22886 tree pcv2df_type_node
22887 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22888 tree v8sf_ftype_pcv4sf
22889 = build_function_type_list (V8SF_type_node,
22892 tree v4df_ftype_pcv2df
22893 = build_function_type_list (V4DF_type_node,
22896 tree v32qi_ftype_pcchar
22897 = build_function_type_list (V32QI_type_node,
22900 tree void_ftype_pchar_v32qi
22901 = build_function_type_list (void_type_node,
22902 pchar_type_node, V32QI_type_node,
22904 tree v8si_ftype_v8si_v4si_int
22905 = build_function_type_list (V8SI_type_node,
22906 V8SI_type_node, V4SI_type_node,
22909 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22910 tree void_ftype_pv4di_v4di
22911 = build_function_type_list (void_type_node,
22912 pv4di_type_node, V4DI_type_node,
22914 tree v8sf_ftype_v8sf_v4sf_int
22915 = build_function_type_list (V8SF_type_node,
22916 V8SF_type_node, V4SF_type_node,
22919 tree v4df_ftype_v4df_v2df_int
22920 = build_function_type_list (V4DF_type_node,
22921 V4DF_type_node, V2DF_type_node,
22924 tree void_ftype_pfloat_v8sf
22925 = build_function_type_list (void_type_node,
22926 pfloat_type_node, V8SF_type_node,
22928 tree void_ftype_pdouble_v4df
22929 = build_function_type_list (void_type_node,
22930 pdouble_type_node, V4DF_type_node,
22932 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22933 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22934 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22935 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22936 tree pcv8sf_type_node
22937 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22938 tree pcv4df_type_node
22939 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22940 tree v8sf_ftype_pcv8sf_v8sf
22941 = build_function_type_list (V8SF_type_node,
22942 pcv8sf_type_node, V8SF_type_node,
22944 tree v4df_ftype_pcv4df_v4df
22945 = build_function_type_list (V4DF_type_node,
22946 pcv4df_type_node, V4DF_type_node,
22948 tree v4sf_ftype_pcv4sf_v4sf
22949 = build_function_type_list (V4SF_type_node,
22950 pcv4sf_type_node, V4SF_type_node,
22952 tree v2df_ftype_pcv2df_v2df
22953 = build_function_type_list (V2DF_type_node,
22954 pcv2df_type_node, V2DF_type_node,
22956 tree void_ftype_pv8sf_v8sf_v8sf
22957 = build_function_type_list (void_type_node,
22958 pv8sf_type_node, V8SF_type_node,
22961 tree void_ftype_pv4df_v4df_v4df
22962 = build_function_type_list (void_type_node,
22963 pv4df_type_node, V4DF_type_node,
22966 tree void_ftype_pv4sf_v4sf_v4sf
22967 = build_function_type_list (void_type_node,
22968 pv4sf_type_node, V4SF_type_node,
22971 tree void_ftype_pv2df_v2df_v2df
22972 = build_function_type_list (void_type_node,
22973 pv2df_type_node, V2DF_type_node,
22976 tree v4df_ftype_v2df
22977 = build_function_type_list (V4DF_type_node,
22980 tree v8sf_ftype_v4sf
22981 = build_function_type_list (V8SF_type_node,
22984 tree v8si_ftype_v4si
22985 = build_function_type_list (V8SI_type_node,
22988 tree v2df_ftype_v4df
22989 = build_function_type_list (V2DF_type_node,
22992 tree v4sf_ftype_v8sf
22993 = build_function_type_list (V4SF_type_node,
22996 tree v4si_ftype_v8si
22997 = build_function_type_list (V4SI_type_node,
23000 tree int_ftype_v4df
23001 = build_function_type_list (integer_type_node,
23004 tree int_ftype_v8sf
23005 = build_function_type_list (integer_type_node,
23008 tree int_ftype_v8sf_v8sf
23009 = build_function_type_list (integer_type_node,
23010 V8SF_type_node, V8SF_type_node,
23012 tree int_ftype_v4di_v4di
23013 = build_function_type_list (integer_type_node,
23014 V4DI_type_node, V4DI_type_node,
23016 tree int_ftype_v4df_v4df
23017 = build_function_type_list (integer_type_node,
23018 V4DF_type_node, V4DF_type_node,
23020 tree v8sf_ftype_v8sf_v8si
23021 = build_function_type_list (V8SF_type_node,
23022 V8SF_type_node, V8SI_type_node,
23024 tree v4df_ftype_v4df_v4di
23025 = build_function_type_list (V4DF_type_node,
23026 V4DF_type_node, V4DI_type_node,
23028 tree v4sf_ftype_v4sf_v4si
23029 = build_function_type_list (V4SF_type_node,
23030 V4SF_type_node, V4SI_type_node, NULL_TREE);
23031 tree v2df_ftype_v2df_v2di
23032 = build_function_type_list (V2DF_type_node,
23033 V2DF_type_node, V2DI_type_node, NULL_TREE);
23037 /* Add all special builtins with variable number of operands. */
23038 for (i = 0, d = bdesc_special_args;
23039 i < ARRAY_SIZE (bdesc_special_args);
23047 switch ((enum ix86_special_builtin_type) d->flag)
23049 case VOID_FTYPE_VOID:
23050 type = void_ftype_void;
23052 case V32QI_FTYPE_PCCHAR:
23053 type = v32qi_ftype_pcchar;
23055 case V16QI_FTYPE_PCCHAR:
23056 type = v16qi_ftype_pcchar;
23058 case V8SF_FTYPE_PCV4SF:
23059 type = v8sf_ftype_pcv4sf;
23061 case V8SF_FTYPE_PCFLOAT:
23062 type = v8sf_ftype_pcfloat;
23064 case V4DF_FTYPE_PCV2DF:
23065 type = v4df_ftype_pcv2df;
23067 case V4DF_FTYPE_PCDOUBLE:
23068 type = v4df_ftype_pcdouble;
23070 case V4SF_FTYPE_PCFLOAT:
23071 type = v4sf_ftype_pcfloat;
23073 case V2DI_FTYPE_PV2DI:
23074 type = v2di_ftype_pv2di;
23076 case V2DF_FTYPE_PCDOUBLE:
23077 type = v2df_ftype_pcdouble;
23079 case V8SF_FTYPE_PCV8SF_V8SF:
23080 type = v8sf_ftype_pcv8sf_v8sf;
23082 case V4DF_FTYPE_PCV4DF_V4DF:
23083 type = v4df_ftype_pcv4df_v4df;
23085 case V4SF_FTYPE_V4SF_PCV2SF:
23086 type = v4sf_ftype_v4sf_pcv2sf;
23088 case V4SF_FTYPE_PCV4SF_V4SF:
23089 type = v4sf_ftype_pcv4sf_v4sf;
23091 case V2DF_FTYPE_V2DF_PCDOUBLE:
23092 type = v2df_ftype_v2df_pcdouble;
23094 case V2DF_FTYPE_PCV2DF_V2DF:
23095 type = v2df_ftype_pcv2df_v2df;
23097 case VOID_FTYPE_PV2SF_V4SF:
23098 type = void_ftype_pv2sf_v4sf;
23100 case VOID_FTYPE_PV4DI_V4DI:
23101 type = void_ftype_pv4di_v4di;
23103 case VOID_FTYPE_PV2DI_V2DI:
23104 type = void_ftype_pv2di_v2di;
23106 case VOID_FTYPE_PCHAR_V32QI:
23107 type = void_ftype_pchar_v32qi;
23109 case VOID_FTYPE_PCHAR_V16QI:
23110 type = void_ftype_pchar_v16qi;
23112 case VOID_FTYPE_PFLOAT_V8SF:
23113 type = void_ftype_pfloat_v8sf;
23115 case VOID_FTYPE_PFLOAT_V4SF:
23116 type = void_ftype_pfloat_v4sf;
23118 case VOID_FTYPE_PDOUBLE_V4DF:
23119 type = void_ftype_pdouble_v4df;
23121 case VOID_FTYPE_PDOUBLE_V2DF:
23122 type = void_ftype_pdouble_v2df;
23124 case VOID_FTYPE_PDI_DI:
23125 type = void_ftype_pdi_di;
23127 case VOID_FTYPE_PINT_INT:
23128 type = void_ftype_pint_int;
23130 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23131 type = void_ftype_pv8sf_v8sf_v8sf;
23133 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23134 type = void_ftype_pv4df_v4df_v4df;
23136 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23137 type = void_ftype_pv4sf_v4sf_v4sf;
23139 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23140 type = void_ftype_pv2df_v2df_v2df;
23143 gcc_unreachable ();
23146 def_builtin (d->mask, d->name, type, d->code);
23149 /* Add all builtins with variable number of operands. */
23150 for (i = 0, d = bdesc_args;
23151 i < ARRAY_SIZE (bdesc_args);
23159 switch ((enum ix86_builtin_type) d->flag)
23161 case FLOAT_FTYPE_FLOAT:
23162 type = float_ftype_float;
23164 case INT_FTYPE_V8SF_V8SF_PTEST:
23165 type = int_ftype_v8sf_v8sf;
23167 case INT_FTYPE_V4DI_V4DI_PTEST:
23168 type = int_ftype_v4di_v4di;
23170 case INT_FTYPE_V4DF_V4DF_PTEST:
23171 type = int_ftype_v4df_v4df;
23173 case INT_FTYPE_V4SF_V4SF_PTEST:
23174 type = int_ftype_v4sf_v4sf;
23176 case INT_FTYPE_V2DI_V2DI_PTEST:
23177 type = int_ftype_v2di_v2di;
23179 case INT_FTYPE_V2DF_V2DF_PTEST:
23180 type = int_ftype_v2df_v2df;
23182 case INT64_FTYPE_V4SF:
23183 type = int64_ftype_v4sf;
23185 case INT64_FTYPE_V2DF:
23186 type = int64_ftype_v2df;
23188 case INT_FTYPE_V16QI:
23189 type = int_ftype_v16qi;
23191 case INT_FTYPE_V8QI:
23192 type = int_ftype_v8qi;
23194 case INT_FTYPE_V8SF:
23195 type = int_ftype_v8sf;
23197 case INT_FTYPE_V4DF:
23198 type = int_ftype_v4df;
23200 case INT_FTYPE_V4SF:
23201 type = int_ftype_v4sf;
23203 case INT_FTYPE_V2DF:
23204 type = int_ftype_v2df;
23206 case V16QI_FTYPE_V16QI:
23207 type = v16qi_ftype_v16qi;
23209 case V8SI_FTYPE_V8SF:
23210 type = v8si_ftype_v8sf;
23212 case V8SI_FTYPE_V4SI:
23213 type = v8si_ftype_v4si;
23215 case V8HI_FTYPE_V8HI:
23216 type = v8hi_ftype_v8hi;
23218 case V8HI_FTYPE_V16QI:
23219 type = v8hi_ftype_v16qi;
23221 case V8QI_FTYPE_V8QI:
23222 type = v8qi_ftype_v8qi;
23224 case V8SF_FTYPE_V8SF:
23225 type = v8sf_ftype_v8sf;
23227 case V8SF_FTYPE_V8SI:
23228 type = v8sf_ftype_v8si;
23230 case V8SF_FTYPE_V4SF:
23231 type = v8sf_ftype_v4sf;
23233 case V4SI_FTYPE_V4DF:
23234 type = v4si_ftype_v4df;
23236 case V4SI_FTYPE_V4SI:
23237 type = v4si_ftype_v4si;
23239 case V4SI_FTYPE_V16QI:
23240 type = v4si_ftype_v16qi;
23242 case V4SI_FTYPE_V8SI:
23243 type = v4si_ftype_v8si;
23245 case V4SI_FTYPE_V8HI:
23246 type = v4si_ftype_v8hi;
23248 case V4SI_FTYPE_V4SF:
23249 type = v4si_ftype_v4sf;
23251 case V4SI_FTYPE_V2DF:
23252 type = v4si_ftype_v2df;
23254 case V4HI_FTYPE_V4HI:
23255 type = v4hi_ftype_v4hi;
23257 case V4DF_FTYPE_V4DF:
23258 type = v4df_ftype_v4df;
23260 case V4DF_FTYPE_V4SI:
23261 type = v4df_ftype_v4si;
23263 case V4DF_FTYPE_V4SF:
23264 type = v4df_ftype_v4sf;
23266 case V4DF_FTYPE_V2DF:
23267 type = v4df_ftype_v2df;
23269 case V4SF_FTYPE_V4SF:
23270 case V4SF_FTYPE_V4SF_VEC_MERGE:
23271 type = v4sf_ftype_v4sf;
23273 case V4SF_FTYPE_V8SF:
23274 type = v4sf_ftype_v8sf;
23276 case V4SF_FTYPE_V4SI:
23277 type = v4sf_ftype_v4si;
23279 case V4SF_FTYPE_V4DF:
23280 type = v4sf_ftype_v4df;
23282 case V4SF_FTYPE_V2DF:
23283 type = v4sf_ftype_v2df;
23285 case V2DI_FTYPE_V2DI:
23286 type = v2di_ftype_v2di;
23288 case V2DI_FTYPE_V16QI:
23289 type = v2di_ftype_v16qi;
23291 case V2DI_FTYPE_V8HI:
23292 type = v2di_ftype_v8hi;
23294 case V2DI_FTYPE_V4SI:
23295 type = v2di_ftype_v4si;
23297 case V2SI_FTYPE_V2SI:
23298 type = v2si_ftype_v2si;
23300 case V2SI_FTYPE_V4SF:
23301 type = v2si_ftype_v4sf;
23303 case V2SI_FTYPE_V2DF:
23304 type = v2si_ftype_v2df;
23306 case V2SI_FTYPE_V2SF:
23307 type = v2si_ftype_v2sf;
23309 case V2DF_FTYPE_V4DF:
23310 type = v2df_ftype_v4df;
23312 case V2DF_FTYPE_V4SF:
23313 type = v2df_ftype_v4sf;
23315 case V2DF_FTYPE_V2DF:
23316 case V2DF_FTYPE_V2DF_VEC_MERGE:
23317 type = v2df_ftype_v2df;
23319 case V2DF_FTYPE_V2SI:
23320 type = v2df_ftype_v2si;
23322 case V2DF_FTYPE_V4SI:
23323 type = v2df_ftype_v4si;
23325 case V2SF_FTYPE_V2SF:
23326 type = v2sf_ftype_v2sf;
23328 case V2SF_FTYPE_V2SI:
23329 type = v2sf_ftype_v2si;
23331 case V16QI_FTYPE_V16QI_V16QI:
23332 type = v16qi_ftype_v16qi_v16qi;
23334 case V16QI_FTYPE_V8HI_V8HI:
23335 type = v16qi_ftype_v8hi_v8hi;
23337 case V8QI_FTYPE_V8QI_V8QI:
23338 type = v8qi_ftype_v8qi_v8qi;
23340 case V8QI_FTYPE_V4HI_V4HI:
23341 type = v8qi_ftype_v4hi_v4hi;
23343 case V8HI_FTYPE_V8HI_V8HI:
23344 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23345 type = v8hi_ftype_v8hi_v8hi;
23347 case V8HI_FTYPE_V16QI_V16QI:
23348 type = v8hi_ftype_v16qi_v16qi;
23350 case V8HI_FTYPE_V4SI_V4SI:
23351 type = v8hi_ftype_v4si_v4si;
23353 case V8HI_FTYPE_V8HI_SI_COUNT:
23354 type = v8hi_ftype_v8hi_int;
23356 case V8SF_FTYPE_V8SF_V8SF:
23357 type = v8sf_ftype_v8sf_v8sf;
23359 case V8SF_FTYPE_V8SF_V8SI:
23360 type = v8sf_ftype_v8sf_v8si;
23362 case V4SI_FTYPE_V4SI_V4SI:
23363 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23364 type = v4si_ftype_v4si_v4si;
23366 case V4SI_FTYPE_V8HI_V8HI:
23367 type = v4si_ftype_v8hi_v8hi;
23369 case V4SI_FTYPE_V4SF_V4SF:
23370 type = v4si_ftype_v4sf_v4sf;
23372 case V4SI_FTYPE_V2DF_V2DF:
23373 type = v4si_ftype_v2df_v2df;
23375 case V4SI_FTYPE_V4SI_SI_COUNT:
23376 type = v4si_ftype_v4si_int;
23378 case V4HI_FTYPE_V4HI_V4HI:
23379 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23380 type = v4hi_ftype_v4hi_v4hi;
23382 case V4HI_FTYPE_V8QI_V8QI:
23383 type = v4hi_ftype_v8qi_v8qi;
23385 case V4HI_FTYPE_V2SI_V2SI:
23386 type = v4hi_ftype_v2si_v2si;
23388 case V4HI_FTYPE_V4HI_SI_COUNT:
23389 type = v4hi_ftype_v4hi_int;
23391 case V4DF_FTYPE_V4DF_V4DF:
23392 type = v4df_ftype_v4df_v4df;
23394 case V4DF_FTYPE_V4DF_V4DI:
23395 type = v4df_ftype_v4df_v4di;
23397 case V4SF_FTYPE_V4SF_V4SF:
23398 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23399 type = v4sf_ftype_v4sf_v4sf;
23401 case V4SF_FTYPE_V4SF_V4SI:
23402 type = v4sf_ftype_v4sf_v4si;
23404 case V4SF_FTYPE_V4SF_V2SI:
23405 type = v4sf_ftype_v4sf_v2si;
23407 case V4SF_FTYPE_V4SF_V2DF:
23408 type = v4sf_ftype_v4sf_v2df;
23410 case V4SF_FTYPE_V4SF_DI:
23411 type = v4sf_ftype_v4sf_int64;
23413 case V4SF_FTYPE_V4SF_SI:
23414 type = v4sf_ftype_v4sf_int;
23416 case V2DI_FTYPE_V2DI_V2DI:
23417 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23418 type = v2di_ftype_v2di_v2di;
23420 case V2DI_FTYPE_V16QI_V16QI:
23421 type = v2di_ftype_v16qi_v16qi;
23423 case V2DI_FTYPE_V4SI_V4SI:
23424 type = v2di_ftype_v4si_v4si;
23426 case V2DI_FTYPE_V2DI_V16QI:
23427 type = v2di_ftype_v2di_v16qi;
23429 case V2DI_FTYPE_V2DF_V2DF:
23430 type = v2di_ftype_v2df_v2df;
23432 case V2DI_FTYPE_V2DI_SI_COUNT:
23433 type = v2di_ftype_v2di_int;
23435 case V2SI_FTYPE_V2SI_V2SI:
23436 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23437 type = v2si_ftype_v2si_v2si;
23439 case V2SI_FTYPE_V4HI_V4HI:
23440 type = v2si_ftype_v4hi_v4hi;
23442 case V2SI_FTYPE_V2SF_V2SF:
23443 type = v2si_ftype_v2sf_v2sf;
23445 case V2SI_FTYPE_V2SI_SI_COUNT:
23446 type = v2si_ftype_v2si_int;
23448 case V2DF_FTYPE_V2DF_V2DF:
23449 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23450 type = v2df_ftype_v2df_v2df;
23452 case V2DF_FTYPE_V2DF_V4SF:
23453 type = v2df_ftype_v2df_v4sf;
23455 case V2DF_FTYPE_V2DF_V2DI:
23456 type = v2df_ftype_v2df_v2di;
23458 case V2DF_FTYPE_V2DF_DI:
23459 type = v2df_ftype_v2df_int64;
23461 case V2DF_FTYPE_V2DF_SI:
23462 type = v2df_ftype_v2df_int;
23464 case V2SF_FTYPE_V2SF_V2SF:
23465 type = v2sf_ftype_v2sf_v2sf;
23467 case V1DI_FTYPE_V1DI_V1DI:
23468 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23469 type = v1di_ftype_v1di_v1di;
23471 case V1DI_FTYPE_V8QI_V8QI:
23472 type = v1di_ftype_v8qi_v8qi;
23474 case V1DI_FTYPE_V2SI_V2SI:
23475 type = v1di_ftype_v2si_v2si;
23477 case V1DI_FTYPE_V1DI_SI_COUNT:
23478 type = v1di_ftype_v1di_int;
23480 case UINT64_FTYPE_UINT64_UINT64:
23481 type = uint64_ftype_uint64_uint64;
23483 case UINT_FTYPE_UINT_UINT:
23484 type = unsigned_ftype_unsigned_unsigned;
23486 case UINT_FTYPE_UINT_USHORT:
23487 type = unsigned_ftype_unsigned_ushort;
23489 case UINT_FTYPE_UINT_UCHAR:
23490 type = unsigned_ftype_unsigned_uchar;
23492 case V8HI_FTYPE_V8HI_INT:
23493 type = v8hi_ftype_v8hi_int;
23495 case V8SF_FTYPE_V8SF_INT:
23496 type = v8sf_ftype_v8sf_int;
23498 case V4SI_FTYPE_V4SI_INT:
23499 type = v4si_ftype_v4si_int;
23501 case V4SI_FTYPE_V8SI_INT:
23502 type = v4si_ftype_v8si_int;
23504 case V4HI_FTYPE_V4HI_INT:
23505 type = v4hi_ftype_v4hi_int;
23507 case V4DF_FTYPE_V4DF_INT:
23508 type = v4df_ftype_v4df_int;
23510 case V4SF_FTYPE_V4SF_INT:
23511 type = v4sf_ftype_v4sf_int;
23513 case V4SF_FTYPE_V8SF_INT:
23514 type = v4sf_ftype_v8sf_int;
23516 case V2DI_FTYPE_V2DI_INT:
23517 case V2DI2TI_FTYPE_V2DI_INT:
23518 type = v2di_ftype_v2di_int;
23520 case V2DF_FTYPE_V2DF_INT:
23521 type = v2df_ftype_v2df_int;
23523 case V2DF_FTYPE_V4DF_INT:
23524 type = v2df_ftype_v4df_int;
23526 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23527 type = v16qi_ftype_v16qi_v16qi_v16qi;
23529 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23530 type = v8sf_ftype_v8sf_v8sf_v8sf;
23532 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23533 type = v4df_ftype_v4df_v4df_v4df;
23535 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23536 type = v4sf_ftype_v4sf_v4sf_v4sf;
23538 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23539 type = v2df_ftype_v2df_v2df_v2df;
23541 case V16QI_FTYPE_V16QI_V16QI_INT:
23542 type = v16qi_ftype_v16qi_v16qi_int;
23544 case V8SI_FTYPE_V8SI_V8SI_INT:
23545 type = v8si_ftype_v8si_v8si_int;
23547 case V8SI_FTYPE_V8SI_V4SI_INT:
23548 type = v8si_ftype_v8si_v4si_int;
23550 case V8HI_FTYPE_V8HI_V8HI_INT:
23551 type = v8hi_ftype_v8hi_v8hi_int;
23553 case V8SF_FTYPE_V8SF_V8SF_INT:
23554 type = v8sf_ftype_v8sf_v8sf_int;
23556 case V8SF_FTYPE_V8SF_V4SF_INT:
23557 type = v8sf_ftype_v8sf_v4sf_int;
23559 case V4SI_FTYPE_V4SI_V4SI_INT:
23560 type = v4si_ftype_v4si_v4si_int;
23562 case V4DF_FTYPE_V4DF_V4DF_INT:
23563 type = v4df_ftype_v4df_v4df_int;
23565 case V4DF_FTYPE_V4DF_V2DF_INT:
23566 type = v4df_ftype_v4df_v2df_int;
23568 case V4SF_FTYPE_V4SF_V4SF_INT:
23569 type = v4sf_ftype_v4sf_v4sf_int;
23571 case V2DI_FTYPE_V2DI_V2DI_INT:
23572 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23573 type = v2di_ftype_v2di_v2di_int;
23575 case V2DF_FTYPE_V2DF_V2DF_INT:
23576 type = v2df_ftype_v2df_v2df_int;
23578 case V2DI_FTYPE_V2DI_UINT_UINT:
23579 type = v2di_ftype_v2di_unsigned_unsigned;
23581 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23582 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23584 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23585 type = v1di_ftype_v1di_v1di_int;
23588 gcc_unreachable ();
23591 def_builtin_const (d->mask, d->name, type, d->code);
23594 /* pcmpestr[im] insns. */
23595 for (i = 0, d = bdesc_pcmpestr;
23596 i < ARRAY_SIZE (bdesc_pcmpestr);
23599 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23600 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23602 ftype = int_ftype_v16qi_int_v16qi_int_int;
23603 def_builtin_const (d->mask, d->name, ftype, d->code);
23606 /* pcmpistr[im] insns. */
23607 for (i = 0, d = bdesc_pcmpistr;
23608 i < ARRAY_SIZE (bdesc_pcmpistr);
23611 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23612 ftype = v16qi_ftype_v16qi_v16qi_int;
23614 ftype = int_ftype_v16qi_v16qi_int;
23615 def_builtin_const (d->mask, d->name, ftype, d->code);
23618 /* comi/ucomi insns. */
23619 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23620 if (d->mask == OPTION_MASK_ISA_SSE2)
23621 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23623 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23626 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23627 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23629 /* SSE or 3DNow!A */
23630 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23633 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23635 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23636 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23639 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23640 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23643 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23644 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23645 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23646 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23647 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23648 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23651 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23654 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23655 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23657 /* Access to the vec_init patterns. */
23658 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23659 integer_type_node, NULL_TREE);
23660 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23662 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23663 short_integer_type_node,
23664 short_integer_type_node,
23665 short_integer_type_node, NULL_TREE);
23666 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23668 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23669 char_type_node, char_type_node,
23670 char_type_node, char_type_node,
23671 char_type_node, char_type_node,
23672 char_type_node, NULL_TREE);
23673 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23675 /* Access to the vec_extract patterns. */
23676 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23677 integer_type_node, NULL_TREE);
23678 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23680 ftype = build_function_type_list (long_long_integer_type_node,
23681 V2DI_type_node, integer_type_node,
23683 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23685 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23686 integer_type_node, NULL_TREE);
23687 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23689 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23690 integer_type_node, NULL_TREE);
23691 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23693 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23694 integer_type_node, NULL_TREE);
23695 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23697 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23698 integer_type_node, NULL_TREE);
23699 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23701 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23702 integer_type_node, NULL_TREE);
23703 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23705 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23706 integer_type_node, NULL_TREE);
23707 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23709 /* Access to the vec_set patterns. */
23710 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23712 integer_type_node, NULL_TREE);
23713 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23715 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23717 integer_type_node, NULL_TREE);
23718 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23720 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23722 integer_type_node, NULL_TREE);
23723 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23725 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23727 integer_type_node, NULL_TREE);
23728 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23730 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23732 integer_type_node, NULL_TREE);
23733 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23735 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23737 integer_type_node, NULL_TREE);
23738 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23740 /* Add SSE5 multi-arg argument instructions */
23741 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23743 tree mtype = NULL_TREE;
23748 switch ((enum multi_arg_type)d->flag)
23750 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23751 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23752 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23753 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23754 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23755 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23756 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23757 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23758 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23759 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23760 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23761 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23762 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23763 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23764 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23765 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23766 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23767 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23768 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23769 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23770 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23771 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23772 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23773 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23774 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23775 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23776 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23777 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23778 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23779 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23780 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23781 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23782 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23783 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23784 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23785 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23786 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23787 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23788 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23789 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23790 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23791 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23792 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23793 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23794 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23795 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23796 case MULTI_ARG_UNKNOWN:
23798 gcc_unreachable ();
23802 def_builtin_const (d->mask, d->name, mtype, d->code);
23806 /* Internal method for ix86_init_builtins. */
23809 ix86_init_builtins_va_builtins_abi (void)
23811 tree ms_va_ref, sysv_va_ref;
23812 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23813 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23814 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23815 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23819 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23820 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23821 ms_va_ref = build_reference_type (ms_va_list_type_node);
23823 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23826 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23827 fnvoid_va_start_ms =
23828 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23829 fnvoid_va_end_sysv =
23830 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23831 fnvoid_va_start_sysv =
23832 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23834 fnvoid_va_copy_ms =
23835 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23837 fnvoid_va_copy_sysv =
23838 build_function_type_list (void_type_node, sysv_va_ref,
23839 sysv_va_ref, NULL_TREE);
23841 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23842 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23843 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23844 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23845 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23846 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23847 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23848 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23849 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23850 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23851 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23852 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23856 ix86_init_builtins (void)
23858 tree float128_type_node = make_node (REAL_TYPE);
23861 /* The __float80 type. */
23862 if (TYPE_MODE (long_double_type_node) == XFmode)
23863 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23867 /* The __float80 type. */
23868 tree float80_type_node = make_node (REAL_TYPE);
23870 TYPE_PRECISION (float80_type_node) = 80;
23871 layout_type (float80_type_node);
23872 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23876 /* The __float128 type. */
23877 TYPE_PRECISION (float128_type_node) = 128;
23878 layout_type (float128_type_node);
23879 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23882 /* TFmode support builtins. */
23883 ftype = build_function_type (float128_type_node, void_list_node);
23884 decl = add_builtin_function ("__builtin_infq", ftype,
23885 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23887 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23889 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23890 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23892 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23894 /* We will expand them to normal call if SSE2 isn't available since
23895 they are used by libgcc. */
23896 ftype = build_function_type_list (float128_type_node,
23897 float128_type_node,
23899 decl = add_builtin_function ("__builtin_fabsq", ftype,
23900 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23901 "__fabstf2", NULL_TREE);
23902 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23903 TREE_READONLY (decl) = 1;
23905 ftype = build_function_type_list (float128_type_node,
23906 float128_type_node,
23907 float128_type_node,
23909 decl = add_builtin_function ("__builtin_copysignq", ftype,
23910 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23911 "__copysigntf3", NULL_TREE);
23912 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23913 TREE_READONLY (decl) = 1;
23915 ix86_init_mmx_sse_builtins ();
23917 ix86_init_builtins_va_builtins_abi ();
23920 /* Errors in the source file can cause expand_expr to return const0_rtx
23921 where we expect a vector. To avoid crashing, use one of the vector
23922 clear instructions. */
23924 safe_vector_operand (rtx x, enum machine_mode mode)
23926 if (x == const0_rtx)
23927 x = CONST0_RTX (mode);
23931 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23934 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23937 tree arg0 = CALL_EXPR_ARG (exp, 0);
23938 tree arg1 = CALL_EXPR_ARG (exp, 1);
23939 rtx op0 = expand_normal (arg0);
23940 rtx op1 = expand_normal (arg1);
23941 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23942 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23943 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23945 if (VECTOR_MODE_P (mode0))
23946 op0 = safe_vector_operand (op0, mode0);
23947 if (VECTOR_MODE_P (mode1))
23948 op1 = safe_vector_operand (op1, mode1);
23950 if (optimize || !target
23951 || GET_MODE (target) != tmode
23952 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23953 target = gen_reg_rtx (tmode);
23955 if (GET_MODE (op1) == SImode && mode1 == TImode)
23957 rtx x = gen_reg_rtx (V4SImode);
23958 emit_insn (gen_sse2_loadd (x, op1));
23959 op1 = gen_lowpart (TImode, x);
23962 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23963 op0 = copy_to_mode_reg (mode0, op0);
23964 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23965 op1 = copy_to_mode_reg (mode1, op1);
23967 pat = GEN_FCN (icode) (target, op0, op1);
23976 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23979 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23980 enum multi_arg_type m_type,
23981 enum rtx_code sub_code)
23986 bool comparison_p = false;
23988 bool last_arg_constant = false;
23989 int num_memory = 0;
23992 enum machine_mode mode;
23995 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23999 case MULTI_ARG_3_SF:
24000 case MULTI_ARG_3_DF:
24001 case MULTI_ARG_3_DI:
24002 case MULTI_ARG_3_SI:
24003 case MULTI_ARG_3_SI_DI:
24004 case MULTI_ARG_3_HI:
24005 case MULTI_ARG_3_HI_SI:
24006 case MULTI_ARG_3_QI:
24007 case MULTI_ARG_3_PERMPS:
24008 case MULTI_ARG_3_PERMPD:
24012 case MULTI_ARG_2_SF:
24013 case MULTI_ARG_2_DF:
24014 case MULTI_ARG_2_DI:
24015 case MULTI_ARG_2_SI:
24016 case MULTI_ARG_2_HI:
24017 case MULTI_ARG_2_QI:
24021 case MULTI_ARG_2_DI_IMM:
24022 case MULTI_ARG_2_SI_IMM:
24023 case MULTI_ARG_2_HI_IMM:
24024 case MULTI_ARG_2_QI_IMM:
24026 last_arg_constant = true;
24029 case MULTI_ARG_1_SF:
24030 case MULTI_ARG_1_DF:
24031 case MULTI_ARG_1_DI:
24032 case MULTI_ARG_1_SI:
24033 case MULTI_ARG_1_HI:
24034 case MULTI_ARG_1_QI:
24035 case MULTI_ARG_1_SI_DI:
24036 case MULTI_ARG_1_HI_DI:
24037 case MULTI_ARG_1_HI_SI:
24038 case MULTI_ARG_1_QI_DI:
24039 case MULTI_ARG_1_QI_SI:
24040 case MULTI_ARG_1_QI_HI:
24041 case MULTI_ARG_1_PH2PS:
24042 case MULTI_ARG_1_PS2PH:
24046 case MULTI_ARG_2_SF_CMP:
24047 case MULTI_ARG_2_DF_CMP:
24048 case MULTI_ARG_2_DI_CMP:
24049 case MULTI_ARG_2_SI_CMP:
24050 case MULTI_ARG_2_HI_CMP:
24051 case MULTI_ARG_2_QI_CMP:
24053 comparison_p = true;
24056 case MULTI_ARG_2_SF_TF:
24057 case MULTI_ARG_2_DF_TF:
24058 case MULTI_ARG_2_DI_TF:
24059 case MULTI_ARG_2_SI_TF:
24060 case MULTI_ARG_2_HI_TF:
24061 case MULTI_ARG_2_QI_TF:
24066 case MULTI_ARG_UNKNOWN:
24068 gcc_unreachable ();
24071 if (optimize || !target
24072 || GET_MODE (target) != tmode
24073 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24074 target = gen_reg_rtx (tmode);
24076 gcc_assert (nargs <= 4);
24078 for (i = 0; i < nargs; i++)
24080 tree arg = CALL_EXPR_ARG (exp, i);
24081 rtx op = expand_normal (arg);
24082 int adjust = (comparison_p) ? 1 : 0;
24083 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
24085 if (last_arg_constant && i == nargs-1)
24087 if (!CONST_INT_P (op))
24089 error ("last argument must be an immediate");
24090 return gen_reg_rtx (tmode);
24095 if (VECTOR_MODE_P (mode))
24096 op = safe_vector_operand (op, mode);
24098 /* If we aren't optimizing, only allow one memory operand to be
24100 if (memory_operand (op, mode))
24103 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
24106 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
24108 op = force_reg (mode, op);
24112 args[i].mode = mode;
24118 pat = GEN_FCN (icode) (target, args[0].op);
24123 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
24124 GEN_INT ((int)sub_code));
24125 else if (! comparison_p)
24126 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24129 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
24133 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
24138 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
24142 gcc_unreachable ();
24152 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24153 insns with vec_merge. */
24156 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
24160 tree arg0 = CALL_EXPR_ARG (exp, 0);
24161 rtx op1, op0 = expand_normal (arg0);
24162 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24163 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24165 if (optimize || !target
24166 || GET_MODE (target) != tmode
24167 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24168 target = gen_reg_rtx (tmode);
24170 if (VECTOR_MODE_P (mode0))
24171 op0 = safe_vector_operand (op0, mode0);
24173 if ((optimize && !register_operand (op0, mode0))
24174 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
24175 op0 = copy_to_mode_reg (mode0, op0);
24178 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
24179 op1 = copy_to_mode_reg (mode0, op1);
24181 pat = GEN_FCN (icode) (target, op0, op1);
24188 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24191 ix86_expand_sse_compare (const struct builtin_description *d,
24192 tree exp, rtx target, bool swap)
24195 tree arg0 = CALL_EXPR_ARG (exp, 0);
24196 tree arg1 = CALL_EXPR_ARG (exp, 1);
24197 rtx op0 = expand_normal (arg0);
24198 rtx op1 = expand_normal (arg1);
24200 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
24201 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
24202 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
24203 enum rtx_code comparison = d->comparison;
24205 if (VECTOR_MODE_P (mode0))
24206 op0 = safe_vector_operand (op0, mode0);
24207 if (VECTOR_MODE_P (mode1))
24208 op1 = safe_vector_operand (op1, mode1);
24210 /* Swap operands if we have a comparison that isn't available in
24214 rtx tmp = gen_reg_rtx (mode1);
24215 emit_move_insn (tmp, op1);
24220 if (optimize || !target
24221 || GET_MODE (target) != tmode
24222 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
24223 target = gen_reg_rtx (tmode);
24225 if ((optimize && !register_operand (op0, mode0))
24226 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
24227 op0 = copy_to_mode_reg (mode0, op0);
24228 if ((optimize && !register_operand (op1, mode1))
24229 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
24230 op1 = copy_to_mode_reg (mode1, op1);
24232 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
24233 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
24240 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24243 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
24247 tree arg0 = CALL_EXPR_ARG (exp, 0);
24248 tree arg1 = CALL_EXPR_ARG (exp, 1);
24249 rtx op0 = expand_normal (arg0);
24250 rtx op1 = expand_normal (arg1);
24251 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24252 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24253 enum rtx_code comparison = d->comparison;
24255 if (VECTOR_MODE_P (mode0))
24256 op0 = safe_vector_operand (op0, mode0);
24257 if (VECTOR_MODE_P (mode1))
24258 op1 = safe_vector_operand (op1, mode1);
24260 /* Swap operands if we have a comparison that isn't available in
24262 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
24269 target = gen_reg_rtx (SImode);
24270 emit_move_insn (target, const0_rtx);
24271 target = gen_rtx_SUBREG (QImode, target, 0);
24273 if ((optimize && !register_operand (op0, mode0))
24274 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24275 op0 = copy_to_mode_reg (mode0, op0);
24276 if ((optimize && !register_operand (op1, mode1))
24277 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24278 op1 = copy_to_mode_reg (mode1, op1);
24280 pat = GEN_FCN (d->icode) (op0, op1);
24284 emit_insn (gen_rtx_SET (VOIDmode,
24285 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24286 gen_rtx_fmt_ee (comparison, QImode,
24290 return SUBREG_REG (target);
24293 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24296 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
24300 tree arg0 = CALL_EXPR_ARG (exp, 0);
24301 tree arg1 = CALL_EXPR_ARG (exp, 1);
24302 rtx op0 = expand_normal (arg0);
24303 rtx op1 = expand_normal (arg1);
24304 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24305 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24306 enum rtx_code comparison = d->comparison;
24308 if (VECTOR_MODE_P (mode0))
24309 op0 = safe_vector_operand (op0, mode0);
24310 if (VECTOR_MODE_P (mode1))
24311 op1 = safe_vector_operand (op1, mode1);
24313 target = gen_reg_rtx (SImode);
24314 emit_move_insn (target, const0_rtx);
24315 target = gen_rtx_SUBREG (QImode, target, 0);
24317 if ((optimize && !register_operand (op0, mode0))
24318 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24319 op0 = copy_to_mode_reg (mode0, op0);
24320 if ((optimize && !register_operand (op1, mode1))
24321 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24322 op1 = copy_to_mode_reg (mode1, op1);
24324 pat = GEN_FCN (d->icode) (op0, op1);
24328 emit_insn (gen_rtx_SET (VOIDmode,
24329 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24330 gen_rtx_fmt_ee (comparison, QImode,
24334 return SUBREG_REG (target);
24337 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24340 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24341 tree exp, rtx target)
24344 tree arg0 = CALL_EXPR_ARG (exp, 0);
24345 tree arg1 = CALL_EXPR_ARG (exp, 1);
24346 tree arg2 = CALL_EXPR_ARG (exp, 2);
24347 tree arg3 = CALL_EXPR_ARG (exp, 3);
24348 tree arg4 = CALL_EXPR_ARG (exp, 4);
24349 rtx scratch0, scratch1;
24350 rtx op0 = expand_normal (arg0);
24351 rtx op1 = expand_normal (arg1);
24352 rtx op2 = expand_normal (arg2);
24353 rtx op3 = expand_normal (arg3);
24354 rtx op4 = expand_normal (arg4);
24355 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24357 tmode0 = insn_data[d->icode].operand[0].mode;
24358 tmode1 = insn_data[d->icode].operand[1].mode;
24359 modev2 = insn_data[d->icode].operand[2].mode;
24360 modei3 = insn_data[d->icode].operand[3].mode;
24361 modev4 = insn_data[d->icode].operand[4].mode;
24362 modei5 = insn_data[d->icode].operand[5].mode;
24363 modeimm = insn_data[d->icode].operand[6].mode;
24365 if (VECTOR_MODE_P (modev2))
24366 op0 = safe_vector_operand (op0, modev2);
24367 if (VECTOR_MODE_P (modev4))
24368 op2 = safe_vector_operand (op2, modev4);
24370 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24371 op0 = copy_to_mode_reg (modev2, op0);
24372 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24373 op1 = copy_to_mode_reg (modei3, op1);
24374 if ((optimize && !register_operand (op2, modev4))
24375 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24376 op2 = copy_to_mode_reg (modev4, op2);
24377 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24378 op3 = copy_to_mode_reg (modei5, op3);
24380 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24382 error ("the fifth argument must be a 8-bit immediate");
24386 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24388 if (optimize || !target
24389 || GET_MODE (target) != tmode0
24390 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24391 target = gen_reg_rtx (tmode0);
24393 scratch1 = gen_reg_rtx (tmode1);
24395 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24397 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24399 if (optimize || !target
24400 || GET_MODE (target) != tmode1
24401 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24402 target = gen_reg_rtx (tmode1);
24404 scratch0 = gen_reg_rtx (tmode0);
24406 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24410 gcc_assert (d->flag);
24412 scratch0 = gen_reg_rtx (tmode0);
24413 scratch1 = gen_reg_rtx (tmode1);
24415 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24425 target = gen_reg_rtx (SImode);
24426 emit_move_insn (target, const0_rtx);
24427 target = gen_rtx_SUBREG (QImode, target, 0);
24430 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24431 gen_rtx_fmt_ee (EQ, QImode,
24432 gen_rtx_REG ((enum machine_mode) d->flag,
24435 return SUBREG_REG (target);
24442 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24445 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24446 tree exp, rtx target)
24449 tree arg0 = CALL_EXPR_ARG (exp, 0);
24450 tree arg1 = CALL_EXPR_ARG (exp, 1);
24451 tree arg2 = CALL_EXPR_ARG (exp, 2);
24452 rtx scratch0, scratch1;
24453 rtx op0 = expand_normal (arg0);
24454 rtx op1 = expand_normal (arg1);
24455 rtx op2 = expand_normal (arg2);
24456 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24458 tmode0 = insn_data[d->icode].operand[0].mode;
24459 tmode1 = insn_data[d->icode].operand[1].mode;
24460 modev2 = insn_data[d->icode].operand[2].mode;
24461 modev3 = insn_data[d->icode].operand[3].mode;
24462 modeimm = insn_data[d->icode].operand[4].mode;
24464 if (VECTOR_MODE_P (modev2))
24465 op0 = safe_vector_operand (op0, modev2);
24466 if (VECTOR_MODE_P (modev3))
24467 op1 = safe_vector_operand (op1, modev3);
24469 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24470 op0 = copy_to_mode_reg (modev2, op0);
24471 if ((optimize && !register_operand (op1, modev3))
24472 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24473 op1 = copy_to_mode_reg (modev3, op1);
24475 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24477 error ("the third argument must be a 8-bit immediate");
24481 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24483 if (optimize || !target
24484 || GET_MODE (target) != tmode0
24485 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24486 target = gen_reg_rtx (tmode0);
24488 scratch1 = gen_reg_rtx (tmode1);
24490 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24492 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24494 if (optimize || !target
24495 || GET_MODE (target) != tmode1
24496 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24497 target = gen_reg_rtx (tmode1);
24499 scratch0 = gen_reg_rtx (tmode0);
24501 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24505 gcc_assert (d->flag);
24507 scratch0 = gen_reg_rtx (tmode0);
24508 scratch1 = gen_reg_rtx (tmode1);
24510 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24520 target = gen_reg_rtx (SImode);
24521 emit_move_insn (target, const0_rtx);
24522 target = gen_rtx_SUBREG (QImode, target, 0);
24525 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24526 gen_rtx_fmt_ee (EQ, QImode,
24527 gen_rtx_REG ((enum machine_mode) d->flag,
24530 return SUBREG_REG (target);
24536 /* Subroutine of ix86_expand_builtin to take care of insns with
24537 variable number of operands. */
24540 ix86_expand_args_builtin (const struct builtin_description *d,
24541 tree exp, rtx target)
24543 rtx pat, real_target;
24544 unsigned int i, nargs;
24545 unsigned int nargs_constant = 0;
24546 int num_memory = 0;
24550 enum machine_mode mode;
24552 bool last_arg_count = false;
24553 enum insn_code icode = d->icode;
24554 const struct insn_data *insn_p = &insn_data[icode];
24555 enum machine_mode tmode = insn_p->operand[0].mode;
24556 enum machine_mode rmode = VOIDmode;
24558 enum rtx_code comparison = d->comparison;
24560 switch ((enum ix86_builtin_type) d->flag)
24562 case INT_FTYPE_V8SF_V8SF_PTEST:
24563 case INT_FTYPE_V4DI_V4DI_PTEST:
24564 case INT_FTYPE_V4DF_V4DF_PTEST:
24565 case INT_FTYPE_V4SF_V4SF_PTEST:
24566 case INT_FTYPE_V2DI_V2DI_PTEST:
24567 case INT_FTYPE_V2DF_V2DF_PTEST:
24568 return ix86_expand_sse_ptest (d, exp, target);
24569 case FLOAT128_FTYPE_FLOAT128:
24570 case FLOAT_FTYPE_FLOAT:
24571 case INT64_FTYPE_V4SF:
24572 case INT64_FTYPE_V2DF:
24573 case INT_FTYPE_V16QI:
24574 case INT_FTYPE_V8QI:
24575 case INT_FTYPE_V8SF:
24576 case INT_FTYPE_V4DF:
24577 case INT_FTYPE_V4SF:
24578 case INT_FTYPE_V2DF:
24579 case V16QI_FTYPE_V16QI:
24580 case V8SI_FTYPE_V8SF:
24581 case V8SI_FTYPE_V4SI:
24582 case V8HI_FTYPE_V8HI:
24583 case V8HI_FTYPE_V16QI:
24584 case V8QI_FTYPE_V8QI:
24585 case V8SF_FTYPE_V8SF:
24586 case V8SF_FTYPE_V8SI:
24587 case V8SF_FTYPE_V4SF:
24588 case V4SI_FTYPE_V4SI:
24589 case V4SI_FTYPE_V16QI:
24590 case V4SI_FTYPE_V4SF:
24591 case V4SI_FTYPE_V8SI:
24592 case V4SI_FTYPE_V8HI:
24593 case V4SI_FTYPE_V4DF:
24594 case V4SI_FTYPE_V2DF:
24595 case V4HI_FTYPE_V4HI:
24596 case V4DF_FTYPE_V4DF:
24597 case V4DF_FTYPE_V4SI:
24598 case V4DF_FTYPE_V4SF:
24599 case V4DF_FTYPE_V2DF:
24600 case V4SF_FTYPE_V4SF:
24601 case V4SF_FTYPE_V4SI:
24602 case V4SF_FTYPE_V8SF:
24603 case V4SF_FTYPE_V4DF:
24604 case V4SF_FTYPE_V2DF:
24605 case V2DI_FTYPE_V2DI:
24606 case V2DI_FTYPE_V16QI:
24607 case V2DI_FTYPE_V8HI:
24608 case V2DI_FTYPE_V4SI:
24609 case V2DF_FTYPE_V2DF:
24610 case V2DF_FTYPE_V4SI:
24611 case V2DF_FTYPE_V4DF:
24612 case V2DF_FTYPE_V4SF:
24613 case V2DF_FTYPE_V2SI:
24614 case V2SI_FTYPE_V2SI:
24615 case V2SI_FTYPE_V4SF:
24616 case V2SI_FTYPE_V2SF:
24617 case V2SI_FTYPE_V2DF:
24618 case V2SF_FTYPE_V2SF:
24619 case V2SF_FTYPE_V2SI:
24622 case V4SF_FTYPE_V4SF_VEC_MERGE:
24623 case V2DF_FTYPE_V2DF_VEC_MERGE:
24624 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24625 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24626 case V16QI_FTYPE_V16QI_V16QI:
24627 case V16QI_FTYPE_V8HI_V8HI:
24628 case V8QI_FTYPE_V8QI_V8QI:
24629 case V8QI_FTYPE_V4HI_V4HI:
24630 case V8HI_FTYPE_V8HI_V8HI:
24631 case V8HI_FTYPE_V16QI_V16QI:
24632 case V8HI_FTYPE_V4SI_V4SI:
24633 case V8SF_FTYPE_V8SF_V8SF:
24634 case V8SF_FTYPE_V8SF_V8SI:
24635 case V4SI_FTYPE_V4SI_V4SI:
24636 case V4SI_FTYPE_V8HI_V8HI:
24637 case V4SI_FTYPE_V4SF_V4SF:
24638 case V4SI_FTYPE_V2DF_V2DF:
24639 case V4HI_FTYPE_V4HI_V4HI:
24640 case V4HI_FTYPE_V8QI_V8QI:
24641 case V4HI_FTYPE_V2SI_V2SI:
24642 case V4DF_FTYPE_V4DF_V4DF:
24643 case V4DF_FTYPE_V4DF_V4DI:
24644 case V4SF_FTYPE_V4SF_V4SF:
24645 case V4SF_FTYPE_V4SF_V4SI:
24646 case V4SF_FTYPE_V4SF_V2SI:
24647 case V4SF_FTYPE_V4SF_V2DF:
24648 case V4SF_FTYPE_V4SF_DI:
24649 case V4SF_FTYPE_V4SF_SI:
24650 case V2DI_FTYPE_V2DI_V2DI:
24651 case V2DI_FTYPE_V16QI_V16QI:
24652 case V2DI_FTYPE_V4SI_V4SI:
24653 case V2DI_FTYPE_V2DI_V16QI:
24654 case V2DI_FTYPE_V2DF_V2DF:
24655 case V2SI_FTYPE_V2SI_V2SI:
24656 case V2SI_FTYPE_V4HI_V4HI:
24657 case V2SI_FTYPE_V2SF_V2SF:
24658 case V2DF_FTYPE_V2DF_V2DF:
24659 case V2DF_FTYPE_V2DF_V4SF:
24660 case V2DF_FTYPE_V2DF_V2DI:
24661 case V2DF_FTYPE_V2DF_DI:
24662 case V2DF_FTYPE_V2DF_SI:
24663 case V2SF_FTYPE_V2SF_V2SF:
24664 case V1DI_FTYPE_V1DI_V1DI:
24665 case V1DI_FTYPE_V8QI_V8QI:
24666 case V1DI_FTYPE_V2SI_V2SI:
24667 if (comparison == UNKNOWN)
24668 return ix86_expand_binop_builtin (icode, exp, target);
24671 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24672 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24673 gcc_assert (comparison != UNKNOWN);
24677 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24678 case V8HI_FTYPE_V8HI_SI_COUNT:
24679 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24680 case V4SI_FTYPE_V4SI_SI_COUNT:
24681 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24682 case V4HI_FTYPE_V4HI_SI_COUNT:
24683 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24684 case V2DI_FTYPE_V2DI_SI_COUNT:
24685 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24686 case V2SI_FTYPE_V2SI_SI_COUNT:
24687 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24688 case V1DI_FTYPE_V1DI_SI_COUNT:
24690 last_arg_count = true;
24692 case UINT64_FTYPE_UINT64_UINT64:
24693 case UINT_FTYPE_UINT_UINT:
24694 case UINT_FTYPE_UINT_USHORT:
24695 case UINT_FTYPE_UINT_UCHAR:
24698 case V2DI2TI_FTYPE_V2DI_INT:
24701 nargs_constant = 1;
24703 case V8HI_FTYPE_V8HI_INT:
24704 case V8SF_FTYPE_V8SF_INT:
24705 case V4SI_FTYPE_V4SI_INT:
24706 case V4SI_FTYPE_V8SI_INT:
24707 case V4HI_FTYPE_V4HI_INT:
24708 case V4DF_FTYPE_V4DF_INT:
24709 case V4SF_FTYPE_V4SF_INT:
24710 case V4SF_FTYPE_V8SF_INT:
24711 case V2DI_FTYPE_V2DI_INT:
24712 case V2DF_FTYPE_V2DF_INT:
24713 case V2DF_FTYPE_V4DF_INT:
24715 nargs_constant = 1;
24717 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24718 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24719 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24720 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24721 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24724 case V16QI_FTYPE_V16QI_V16QI_INT:
24725 case V8HI_FTYPE_V8HI_V8HI_INT:
24726 case V8SI_FTYPE_V8SI_V8SI_INT:
24727 case V8SI_FTYPE_V8SI_V4SI_INT:
24728 case V8SF_FTYPE_V8SF_V8SF_INT:
24729 case V8SF_FTYPE_V8SF_V4SF_INT:
24730 case V4SI_FTYPE_V4SI_V4SI_INT:
24731 case V4DF_FTYPE_V4DF_V4DF_INT:
24732 case V4DF_FTYPE_V4DF_V2DF_INT:
24733 case V4SF_FTYPE_V4SF_V4SF_INT:
24734 case V2DI_FTYPE_V2DI_V2DI_INT:
24735 case V2DF_FTYPE_V2DF_V2DF_INT:
24737 nargs_constant = 1;
24739 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24742 nargs_constant = 1;
24744 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24747 nargs_constant = 1;
24749 case V2DI_FTYPE_V2DI_UINT_UINT:
24751 nargs_constant = 2;
24753 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24755 nargs_constant = 2;
24758 gcc_unreachable ();
24761 gcc_assert (nargs <= ARRAY_SIZE (args));
24763 if (comparison != UNKNOWN)
24765 gcc_assert (nargs == 2);
24766 return ix86_expand_sse_compare (d, exp, target, swap);
24769 if (rmode == VOIDmode || rmode == tmode)
24773 || GET_MODE (target) != tmode
24774 || ! (*insn_p->operand[0].predicate) (target, tmode))
24775 target = gen_reg_rtx (tmode);
24776 real_target = target;
24780 target = gen_reg_rtx (rmode);
24781 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24784 for (i = 0; i < nargs; i++)
24786 tree arg = CALL_EXPR_ARG (exp, i);
24787 rtx op = expand_normal (arg);
24788 enum machine_mode mode = insn_p->operand[i + 1].mode;
24789 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24791 if (last_arg_count && (i + 1) == nargs)
24793 /* SIMD shift insns take either an 8-bit immediate or
24794 register as count. But builtin functions take int as
24795 count. If count doesn't match, we put it in register. */
24798 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24799 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24800 op = copy_to_reg (op);
24803 else if ((nargs - i) <= nargs_constant)
24808 case CODE_FOR_sse4_1_roundpd:
24809 case CODE_FOR_sse4_1_roundps:
24810 case CODE_FOR_sse4_1_roundsd:
24811 case CODE_FOR_sse4_1_roundss:
24812 case CODE_FOR_sse4_1_blendps:
24813 case CODE_FOR_avx_blendpd256:
24814 case CODE_FOR_avx_vpermilv4df:
24815 case CODE_FOR_avx_roundpd256:
24816 case CODE_FOR_avx_roundps256:
24817 error ("the last argument must be a 4-bit immediate");
24820 case CODE_FOR_sse4_1_blendpd:
24821 case CODE_FOR_avx_vpermilv2df:
24822 error ("the last argument must be a 2-bit immediate");
24825 case CODE_FOR_avx_vextractf128v4df:
24826 case CODE_FOR_avx_vextractf128v8sf:
24827 case CODE_FOR_avx_vextractf128v8si:
24828 case CODE_FOR_avx_vinsertf128v4df:
24829 case CODE_FOR_avx_vinsertf128v8sf:
24830 case CODE_FOR_avx_vinsertf128v8si:
24831 error ("the last argument must be a 1-bit immediate");
24834 case CODE_FOR_avx_cmpsdv2df3:
24835 case CODE_FOR_avx_cmpssv4sf3:
24836 case CODE_FOR_avx_cmppdv2df3:
24837 case CODE_FOR_avx_cmppsv4sf3:
24838 case CODE_FOR_avx_cmppdv4df3:
24839 case CODE_FOR_avx_cmppsv8sf3:
24840 error ("the last argument must be a 5-bit immediate");
24844 switch (nargs_constant)
24847 if ((nargs - i) == nargs_constant)
24849 error ("the next to last argument must be an 8-bit immediate");
24853 error ("the last argument must be an 8-bit immediate");
24856 gcc_unreachable ();
24863 if (VECTOR_MODE_P (mode))
24864 op = safe_vector_operand (op, mode);
24866 /* If we aren't optimizing, only allow one memory operand to
24868 if (memory_operand (op, mode))
24871 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24873 if (optimize || !match || num_memory > 1)
24874 op = copy_to_mode_reg (mode, op);
24878 op = copy_to_reg (op);
24879 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24884 args[i].mode = mode;
24890 pat = GEN_FCN (icode) (real_target, args[0].op);
24893 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24896 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24900 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24901 args[2].op, args[3].op);
24904 gcc_unreachable ();
24914 /* Subroutine of ix86_expand_builtin to take care of special insns
24915 with variable number of operands. */
24918 ix86_expand_special_args_builtin (const struct builtin_description *d,
24919 tree exp, rtx target)
24923 unsigned int i, nargs, arg_adjust, memory;
24927 enum machine_mode mode;
24929 enum insn_code icode = d->icode;
24930 bool last_arg_constant = false;
24931 const struct insn_data *insn_p = &insn_data[icode];
24932 enum machine_mode tmode = insn_p->operand[0].mode;
24933 enum { load, store } klass;
24935 switch ((enum ix86_special_builtin_type) d->flag)
24937 case VOID_FTYPE_VOID:
24938 emit_insn (GEN_FCN (icode) (target));
24940 case V2DI_FTYPE_PV2DI:
24941 case V32QI_FTYPE_PCCHAR:
24942 case V16QI_FTYPE_PCCHAR:
24943 case V8SF_FTYPE_PCV4SF:
24944 case V8SF_FTYPE_PCFLOAT:
24945 case V4SF_FTYPE_PCFLOAT:
24946 case V4DF_FTYPE_PCV2DF:
24947 case V4DF_FTYPE_PCDOUBLE:
24948 case V2DF_FTYPE_PCDOUBLE:
24953 case VOID_FTYPE_PV2SF_V4SF:
24954 case VOID_FTYPE_PV4DI_V4DI:
24955 case VOID_FTYPE_PV2DI_V2DI:
24956 case VOID_FTYPE_PCHAR_V32QI:
24957 case VOID_FTYPE_PCHAR_V16QI:
24958 case VOID_FTYPE_PFLOAT_V8SF:
24959 case VOID_FTYPE_PFLOAT_V4SF:
24960 case VOID_FTYPE_PDOUBLE_V4DF:
24961 case VOID_FTYPE_PDOUBLE_V2DF:
24962 case VOID_FTYPE_PDI_DI:
24963 case VOID_FTYPE_PINT_INT:
24966 /* Reserve memory operand for target. */
24967 memory = ARRAY_SIZE (args);
24969 case V4SF_FTYPE_V4SF_PCV2SF:
24970 case V2DF_FTYPE_V2DF_PCDOUBLE:
24975 case V8SF_FTYPE_PCV8SF_V8SF:
24976 case V4DF_FTYPE_PCV4DF_V4DF:
24977 case V4SF_FTYPE_PCV4SF_V4SF:
24978 case V2DF_FTYPE_PCV2DF_V2DF:
24983 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24984 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24985 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24986 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24989 /* Reserve memory operand for target. */
24990 memory = ARRAY_SIZE (args);
24993 gcc_unreachable ();
24996 gcc_assert (nargs <= ARRAY_SIZE (args));
24998 if (klass == store)
25000 arg = CALL_EXPR_ARG (exp, 0);
25001 op = expand_normal (arg);
25002 gcc_assert (target == 0);
25003 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
25011 || GET_MODE (target) != tmode
25012 || ! (*insn_p->operand[0].predicate) (target, tmode))
25013 target = gen_reg_rtx (tmode);
25016 for (i = 0; i < nargs; i++)
25018 enum machine_mode mode = insn_p->operand[i + 1].mode;
25021 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
25022 op = expand_normal (arg);
25023 match = (*insn_p->operand[i + 1].predicate) (op, mode);
25025 if (last_arg_constant && (i + 1) == nargs)
25031 error ("the last argument must be an 8-bit immediate");
25039 /* This must be the memory operand. */
25040 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
25041 gcc_assert (GET_MODE (op) == mode
25042 || GET_MODE (op) == VOIDmode);
25046 /* This must be register. */
25047 if (VECTOR_MODE_P (mode))
25048 op = safe_vector_operand (op, mode);
25050 gcc_assert (GET_MODE (op) == mode
25051 || GET_MODE (op) == VOIDmode);
25052 op = copy_to_mode_reg (mode, op);
25057 args[i].mode = mode;
25063 pat = GEN_FCN (icode) (target, args[0].op);
25066 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
25069 gcc_unreachable ();
25075 return klass == store ? 0 : target;
25078 /* Return the integer constant in ARG. Constrain it to be in the range
25079 of the subparts of VEC_TYPE; issue an error if not. */
25082 get_element_number (tree vec_type, tree arg)
25084 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
25086 if (!host_integerp (arg, 1)
25087 || (elt = tree_low_cst (arg, 1), elt > max))
25089 error ("selector must be an integer constant in the range 0..%wi", max);
25096 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25097 ix86_expand_vector_init. We DO have language-level syntax for this, in
25098 the form of (type){ init-list }. Except that since we can't place emms
25099 instructions from inside the compiler, we can't allow the use of MMX
25100 registers unless the user explicitly asks for it. So we do *not* define
25101 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25102 we have builtins invoked by mmintrin.h that gives us license to emit
25103 these sorts of instructions. */
25106 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
25108 enum machine_mode tmode = TYPE_MODE (type);
25109 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
25110 int i, n_elt = GET_MODE_NUNITS (tmode);
25111 rtvec v = rtvec_alloc (n_elt);
25113 gcc_assert (VECTOR_MODE_P (tmode));
25114 gcc_assert (call_expr_nargs (exp) == n_elt);
25116 for (i = 0; i < n_elt; ++i)
25118 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
25119 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
25122 if (!target || !register_operand (target, tmode))
25123 target = gen_reg_rtx (tmode);
25125 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
25129 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25130 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25131 had a language-level syntax for referencing vector elements. */
25134 ix86_expand_vec_ext_builtin (tree exp, rtx target)
25136 enum machine_mode tmode, mode0;
25141 arg0 = CALL_EXPR_ARG (exp, 0);
25142 arg1 = CALL_EXPR_ARG (exp, 1);
25144 op0 = expand_normal (arg0);
25145 elt = get_element_number (TREE_TYPE (arg0), arg1);
25147 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25148 mode0 = TYPE_MODE (TREE_TYPE (arg0));
25149 gcc_assert (VECTOR_MODE_P (mode0));
25151 op0 = force_reg (mode0, op0);
25153 if (optimize || !target || !register_operand (target, tmode))
25154 target = gen_reg_rtx (tmode);
25156 ix86_expand_vector_extract (true, target, op0, elt);
25161 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25162 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25163 a language-level syntax for referencing vector elements. */
25166 ix86_expand_vec_set_builtin (tree exp)
25168 enum machine_mode tmode, mode1;
25169 tree arg0, arg1, arg2;
25171 rtx op0, op1, target;
25173 arg0 = CALL_EXPR_ARG (exp, 0);
25174 arg1 = CALL_EXPR_ARG (exp, 1);
25175 arg2 = CALL_EXPR_ARG (exp, 2);
25177 tmode = TYPE_MODE (TREE_TYPE (arg0));
25178 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25179 gcc_assert (VECTOR_MODE_P (tmode));
25181 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
25182 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
25183 elt = get_element_number (TREE_TYPE (arg0), arg2);
25185 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
25186 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
25188 op0 = force_reg (tmode, op0);
25189 op1 = force_reg (mode1, op1);
25191 /* OP0 is the source of these builtin functions and shouldn't be
25192 modified. Create a copy, use it and return it as target. */
25193 target = gen_reg_rtx (tmode);
25194 emit_move_insn (target, op0);
25195 ix86_expand_vector_set (true, target, op1, elt);
25200 /* Expand an expression EXP that calls a built-in function,
25201 with result going to TARGET if that's convenient
25202 (and in mode MODE if that's convenient).
25203 SUBTARGET may be used as the target for computing one of EXP's operands.
25204 IGNORE is nonzero if the value is to be ignored. */
25207 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
25208 enum machine_mode mode ATTRIBUTE_UNUSED,
25209 int ignore ATTRIBUTE_UNUSED)
25211 const struct builtin_description *d;
25213 enum insn_code icode;
25214 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
25215 tree arg0, arg1, arg2;
25216 rtx op0, op1, op2, pat;
25217 enum machine_mode mode0, mode1, mode2;
25218 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
25220 /* Determine whether the builtin function is available under the current ISA.
25221 Originally the builtin was not created if it wasn't applicable to the
25222 current ISA based on the command line switches. With function specific
25223 options, we need to check in the context of the function making the call
25224 whether it is supported. */
25225 if (ix86_builtins_isa[fcode].isa
25226 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
25228 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
25229 NULL, NULL, false);
25232 error ("%qE needs unknown isa option", fndecl);
25235 gcc_assert (opts != NULL);
25236 error ("%qE needs isa option %s", fndecl, opts);
25244 case IX86_BUILTIN_MASKMOVQ:
25245 case IX86_BUILTIN_MASKMOVDQU:
25246 icode = (fcode == IX86_BUILTIN_MASKMOVQ
25247 ? CODE_FOR_mmx_maskmovq
25248 : CODE_FOR_sse2_maskmovdqu);
25249 /* Note the arg order is different from the operand order. */
25250 arg1 = CALL_EXPR_ARG (exp, 0);
25251 arg2 = CALL_EXPR_ARG (exp, 1);
25252 arg0 = CALL_EXPR_ARG (exp, 2);
25253 op0 = expand_normal (arg0);
25254 op1 = expand_normal (arg1);
25255 op2 = expand_normal (arg2);
25256 mode0 = insn_data[icode].operand[0].mode;
25257 mode1 = insn_data[icode].operand[1].mode;
25258 mode2 = insn_data[icode].operand[2].mode;
25260 op0 = force_reg (Pmode, op0);
25261 op0 = gen_rtx_MEM (mode1, op0);
25263 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
25264 op0 = copy_to_mode_reg (mode0, op0);
25265 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
25266 op1 = copy_to_mode_reg (mode1, op1);
25267 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
25268 op2 = copy_to_mode_reg (mode2, op2);
25269 pat = GEN_FCN (icode) (op0, op1, op2);
25275 case IX86_BUILTIN_LDMXCSR:
25276 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
25277 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25278 emit_move_insn (target, op0);
25279 emit_insn (gen_sse_ldmxcsr (target));
25282 case IX86_BUILTIN_STMXCSR:
25283 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25284 emit_insn (gen_sse_stmxcsr (target));
25285 return copy_to_mode_reg (SImode, target);
25287 case IX86_BUILTIN_CLFLUSH:
25288 arg0 = CALL_EXPR_ARG (exp, 0);
25289 op0 = expand_normal (arg0);
25290 icode = CODE_FOR_sse2_clflush;
25291 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
25292 op0 = copy_to_mode_reg (Pmode, op0);
25294 emit_insn (gen_sse2_clflush (op0));
25297 case IX86_BUILTIN_MONITOR:
25298 arg0 = CALL_EXPR_ARG (exp, 0);
25299 arg1 = CALL_EXPR_ARG (exp, 1);
25300 arg2 = CALL_EXPR_ARG (exp, 2);
25301 op0 = expand_normal (arg0);
25302 op1 = expand_normal (arg1);
25303 op2 = expand_normal (arg2);
25305 op0 = copy_to_mode_reg (Pmode, op0);
25307 op1 = copy_to_mode_reg (SImode, op1);
25309 op2 = copy_to_mode_reg (SImode, op2);
25310 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
25313 case IX86_BUILTIN_MWAIT:
25314 arg0 = CALL_EXPR_ARG (exp, 0);
25315 arg1 = CALL_EXPR_ARG (exp, 1);
25316 op0 = expand_normal (arg0);
25317 op1 = expand_normal (arg1);
25319 op0 = copy_to_mode_reg (SImode, op0);
25321 op1 = copy_to_mode_reg (SImode, op1);
25322 emit_insn (gen_sse3_mwait (op0, op1));
25325 case IX86_BUILTIN_VEC_INIT_V2SI:
25326 case IX86_BUILTIN_VEC_INIT_V4HI:
25327 case IX86_BUILTIN_VEC_INIT_V8QI:
25328 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25330 case IX86_BUILTIN_VEC_EXT_V2DF:
25331 case IX86_BUILTIN_VEC_EXT_V2DI:
25332 case IX86_BUILTIN_VEC_EXT_V4SF:
25333 case IX86_BUILTIN_VEC_EXT_V4SI:
25334 case IX86_BUILTIN_VEC_EXT_V8HI:
25335 case IX86_BUILTIN_VEC_EXT_V2SI:
25336 case IX86_BUILTIN_VEC_EXT_V4HI:
25337 case IX86_BUILTIN_VEC_EXT_V16QI:
25338 return ix86_expand_vec_ext_builtin (exp, target);
25340 case IX86_BUILTIN_VEC_SET_V2DI:
25341 case IX86_BUILTIN_VEC_SET_V4SF:
25342 case IX86_BUILTIN_VEC_SET_V4SI:
25343 case IX86_BUILTIN_VEC_SET_V8HI:
25344 case IX86_BUILTIN_VEC_SET_V4HI:
25345 case IX86_BUILTIN_VEC_SET_V16QI:
25346 return ix86_expand_vec_set_builtin (exp);
25348 case IX86_BUILTIN_INFQ:
25349 case IX86_BUILTIN_HUGE_VALQ:
25351 REAL_VALUE_TYPE inf;
25355 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25357 tmp = validize_mem (force_const_mem (mode, tmp));
25360 target = gen_reg_rtx (mode);
25362 emit_move_insn (target, tmp);
25370 for (i = 0, d = bdesc_special_args;
25371 i < ARRAY_SIZE (bdesc_special_args);
25373 if (d->code == fcode)
25374 return ix86_expand_special_args_builtin (d, exp, target);
25376 for (i = 0, d = bdesc_args;
25377 i < ARRAY_SIZE (bdesc_args);
25379 if (d->code == fcode)
25382 case IX86_BUILTIN_FABSQ:
25383 case IX86_BUILTIN_COPYSIGNQ:
25385 /* Emit a normal call if SSE2 isn't available. */
25386 return expand_call (exp, target, ignore);
25388 return ix86_expand_args_builtin (d, exp, target);
25391 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25392 if (d->code == fcode)
25393 return ix86_expand_sse_comi (d, exp, target);
25395 for (i = 0, d = bdesc_pcmpestr;
25396 i < ARRAY_SIZE (bdesc_pcmpestr);
25398 if (d->code == fcode)
25399 return ix86_expand_sse_pcmpestr (d, exp, target);
25401 for (i = 0, d = bdesc_pcmpistr;
25402 i < ARRAY_SIZE (bdesc_pcmpistr);
25404 if (d->code == fcode)
25405 return ix86_expand_sse_pcmpistr (d, exp, target);
25407 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25408 if (d->code == fcode)
25409 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25410 (enum multi_arg_type)d->flag,
25413 gcc_unreachable ();
25416 /* Returns a function decl for a vectorized version of the builtin function
25417 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25418 if it is not available. */
25421 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25424 enum machine_mode in_mode, out_mode;
25427 if (TREE_CODE (type_out) != VECTOR_TYPE
25428 || TREE_CODE (type_in) != VECTOR_TYPE)
25431 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25432 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25433 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25434 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25438 case BUILT_IN_SQRT:
25439 if (out_mode == DFmode && out_n == 2
25440 && in_mode == DFmode && in_n == 2)
25441 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25444 case BUILT_IN_SQRTF:
25445 if (out_mode == SFmode && out_n == 4
25446 && in_mode == SFmode && in_n == 4)
25447 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25450 case BUILT_IN_LRINT:
25451 if (out_mode == SImode && out_n == 4
25452 && in_mode == DFmode && in_n == 2)
25453 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25456 case BUILT_IN_LRINTF:
25457 if (out_mode == SImode && out_n == 4
25458 && in_mode == SFmode && in_n == 4)
25459 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25466 /* Dispatch to a handler for a vectorization library. */
25467 if (ix86_veclib_handler)
25468 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25474 /* Handler for an SVML-style interface to
25475 a library with vectorized intrinsics. */
25478 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25481 tree fntype, new_fndecl, args;
25484 enum machine_mode el_mode, in_mode;
25487 /* The SVML is suitable for unsafe math only. */
25488 if (!flag_unsafe_math_optimizations)
25491 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25492 n = TYPE_VECTOR_SUBPARTS (type_out);
25493 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25494 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25495 if (el_mode != in_mode
25503 case BUILT_IN_LOG10:
25505 case BUILT_IN_TANH:
25507 case BUILT_IN_ATAN:
25508 case BUILT_IN_ATAN2:
25509 case BUILT_IN_ATANH:
25510 case BUILT_IN_CBRT:
25511 case BUILT_IN_SINH:
25513 case BUILT_IN_ASINH:
25514 case BUILT_IN_ASIN:
25515 case BUILT_IN_COSH:
25517 case BUILT_IN_ACOSH:
25518 case BUILT_IN_ACOS:
25519 if (el_mode != DFmode || n != 2)
25523 case BUILT_IN_EXPF:
25524 case BUILT_IN_LOGF:
25525 case BUILT_IN_LOG10F:
25526 case BUILT_IN_POWF:
25527 case BUILT_IN_TANHF:
25528 case BUILT_IN_TANF:
25529 case BUILT_IN_ATANF:
25530 case BUILT_IN_ATAN2F:
25531 case BUILT_IN_ATANHF:
25532 case BUILT_IN_CBRTF:
25533 case BUILT_IN_SINHF:
25534 case BUILT_IN_SINF:
25535 case BUILT_IN_ASINHF:
25536 case BUILT_IN_ASINF:
25537 case BUILT_IN_COSHF:
25538 case BUILT_IN_COSF:
25539 case BUILT_IN_ACOSHF:
25540 case BUILT_IN_ACOSF:
25541 if (el_mode != SFmode || n != 4)
25549 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25551 if (fn == BUILT_IN_LOGF)
25552 strcpy (name, "vmlsLn4");
25553 else if (fn == BUILT_IN_LOG)
25554 strcpy (name, "vmldLn2");
25557 sprintf (name, "vmls%s", bname+10);
25558 name[strlen (name)-1] = '4';
25561 sprintf (name, "vmld%s2", bname+10);
25563 /* Convert to uppercase. */
25567 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25568 args = TREE_CHAIN (args))
25572 fntype = build_function_type_list (type_out, type_in, NULL);
25574 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25576 /* Build a function declaration for the vectorized function. */
25577 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25578 TREE_PUBLIC (new_fndecl) = 1;
25579 DECL_EXTERNAL (new_fndecl) = 1;
25580 DECL_IS_NOVOPS (new_fndecl) = 1;
25581 TREE_READONLY (new_fndecl) = 1;
25586 /* Handler for an ACML-style interface to
25587 a library with vectorized intrinsics. */
25590 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25592 char name[20] = "__vr.._";
25593 tree fntype, new_fndecl, args;
25596 enum machine_mode el_mode, in_mode;
25599 /* The ACML is 64bits only and suitable for unsafe math only as
25600 it does not correctly support parts of IEEE with the required
25601 precision such as denormals. */
25603 || !flag_unsafe_math_optimizations)
25606 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25607 n = TYPE_VECTOR_SUBPARTS (type_out);
25608 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25609 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25610 if (el_mode != in_mode
25620 case BUILT_IN_LOG2:
25621 case BUILT_IN_LOG10:
25624 if (el_mode != DFmode
25629 case BUILT_IN_SINF:
25630 case BUILT_IN_COSF:
25631 case BUILT_IN_EXPF:
25632 case BUILT_IN_POWF:
25633 case BUILT_IN_LOGF:
25634 case BUILT_IN_LOG2F:
25635 case BUILT_IN_LOG10F:
25638 if (el_mode != SFmode
25647 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25648 sprintf (name + 7, "%s", bname+10);
25651 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25652 args = TREE_CHAIN (args))
25656 fntype = build_function_type_list (type_out, type_in, NULL);
25658 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25660 /* Build a function declaration for the vectorized function. */
25661 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25662 TREE_PUBLIC (new_fndecl) = 1;
25663 DECL_EXTERNAL (new_fndecl) = 1;
25664 DECL_IS_NOVOPS (new_fndecl) = 1;
25665 TREE_READONLY (new_fndecl) = 1;
25671 /* Returns a decl of a function that implements conversion of an integer vector
25672 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25673 side of the conversion.
25674 Return NULL_TREE if it is not available. */
25677 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25679 if (TREE_CODE (type) != VECTOR_TYPE
25680 /* There are only conversions from/to signed integers. */
25681 || TYPE_UNSIGNED (TREE_TYPE (type)))
25687 switch (TYPE_MODE (type))
25690 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25695 case FIX_TRUNC_EXPR:
25696 switch (TYPE_MODE (type))
25699 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25709 /* Returns a code for a target-specific builtin that implements
25710 reciprocal of the function, or NULL_TREE if not available. */
25713 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25714 bool sqrt ATTRIBUTE_UNUSED)
25716 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25717 && flag_finite_math_only && !flag_trapping_math
25718 && flag_unsafe_math_optimizations))
25722 /* Machine dependent builtins. */
25725 /* Vectorized version of sqrt to rsqrt conversion. */
25726 case IX86_BUILTIN_SQRTPS_NR:
25727 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25733 /* Normal builtins. */
25736 /* Sqrt to rsqrt conversion. */
25737 case BUILT_IN_SQRTF:
25738 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25745 /* Store OPERAND to the memory after reload is completed. This means
25746 that we can't easily use assign_stack_local. */
25748 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25752 gcc_assert (reload_completed);
25753 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25755 result = gen_rtx_MEM (mode,
25756 gen_rtx_PLUS (Pmode,
25758 GEN_INT (-RED_ZONE_SIZE)));
25759 emit_move_insn (result, operand);
25761 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25767 operand = gen_lowpart (DImode, operand);
25771 gen_rtx_SET (VOIDmode,
25772 gen_rtx_MEM (DImode,
25773 gen_rtx_PRE_DEC (DImode,
25774 stack_pointer_rtx)),
25778 gcc_unreachable ();
25780 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25789 split_di (&operand, 1, operands, operands + 1);
25791 gen_rtx_SET (VOIDmode,
25792 gen_rtx_MEM (SImode,
25793 gen_rtx_PRE_DEC (Pmode,
25794 stack_pointer_rtx)),
25797 gen_rtx_SET (VOIDmode,
25798 gen_rtx_MEM (SImode,
25799 gen_rtx_PRE_DEC (Pmode,
25800 stack_pointer_rtx)),
25805 /* Store HImodes as SImodes. */
25806 operand = gen_lowpart (SImode, operand);
25810 gen_rtx_SET (VOIDmode,
25811 gen_rtx_MEM (GET_MODE (operand),
25812 gen_rtx_PRE_DEC (SImode,
25813 stack_pointer_rtx)),
25817 gcc_unreachable ();
25819 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25824 /* Free operand from the memory. */
25826 ix86_free_from_memory (enum machine_mode mode)
25828 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25832 if (mode == DImode || TARGET_64BIT)
25836 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25837 to pop or add instruction if registers are available. */
25838 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25839 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25844 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25845 QImode must go into class Q_REGS.
25846 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25847 movdf to do mem-to-mem moves through integer regs. */
25849 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25851 enum machine_mode mode = GET_MODE (x);
25853 /* We're only allowed to return a subclass of CLASS. Many of the
25854 following checks fail for NO_REGS, so eliminate that early. */
25855 if (regclass == NO_REGS)
25858 /* All classes can load zeros. */
25859 if (x == CONST0_RTX (mode))
25862 /* Force constants into memory if we are loading a (nonzero) constant into
25863 an MMX or SSE register. This is because there are no MMX/SSE instructions
25864 to load from a constant. */
25866 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25869 /* Prefer SSE regs only, if we can use them for math. */
25870 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25871 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25873 /* Floating-point constants need more complex checks. */
25874 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25876 /* General regs can load everything. */
25877 if (reg_class_subset_p (regclass, GENERAL_REGS))
25880 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25881 zero above. We only want to wind up preferring 80387 registers if
25882 we plan on doing computation with them. */
25884 && standard_80387_constant_p (x))
25886 /* Limit class to non-sse. */
25887 if (regclass == FLOAT_SSE_REGS)
25889 if (regclass == FP_TOP_SSE_REGS)
25891 if (regclass == FP_SECOND_SSE_REGS)
25892 return FP_SECOND_REG;
25893 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25900 /* Generally when we see PLUS here, it's the function invariant
25901 (plus soft-fp const_int). Which can only be computed into general
25903 if (GET_CODE (x) == PLUS)
25904 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25906 /* QImode constants are easy to load, but non-constant QImode data
25907 must go into Q_REGS. */
25908 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25910 if (reg_class_subset_p (regclass, Q_REGS))
25912 if (reg_class_subset_p (Q_REGS, regclass))
25920 /* Discourage putting floating-point values in SSE registers unless
25921 SSE math is being used, and likewise for the 387 registers. */
25923 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25925 enum machine_mode mode = GET_MODE (x);
25927 /* Restrict the output reload class to the register bank that we are doing
25928 math on. If we would like not to return a subset of CLASS, reject this
25929 alternative: if reload cannot do this, it will still use its choice. */
25930 mode = GET_MODE (x);
25931 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25932 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25934 if (X87_FLOAT_MODE_P (mode))
25936 if (regclass == FP_TOP_SSE_REGS)
25938 else if (regclass == FP_SECOND_SSE_REGS)
25939 return FP_SECOND_REG;
25941 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25947 static enum reg_class
25948 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25949 enum machine_mode mode,
25950 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25952 /* QImode spills from non-QI registers require
25953 intermediate register on 32bit targets. */
25954 if (!in_p && mode == QImode && !TARGET_64BIT
25955 && (rclass == GENERAL_REGS
25956 || rclass == LEGACY_REGS
25957 || rclass == INDEX_REGS))
25966 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25967 regno = true_regnum (x);
25969 /* Return Q_REGS if the operand is in memory. */
25977 /* If we are copying between general and FP registers, we need a memory
25978 location. The same is true for SSE and MMX registers.
25980 To optimize register_move_cost performance, allow inline variant.
25982 The macro can't work reliably when one of the CLASSES is class containing
25983 registers from multiple units (SSE, MMX, integer). We avoid this by never
25984 combining those units in single alternative in the machine description.
25985 Ensure that this constraint holds to avoid unexpected surprises.
25987 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25988 enforce these sanity checks. */
25991 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25992 enum machine_mode mode, int strict)
25994 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25995 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25996 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25997 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25998 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25999 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
26001 gcc_assert (!strict);
26005 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
26008 /* ??? This is a lie. We do have moves between mmx/general, and for
26009 mmx/sse2. But by saying we need secondary memory we discourage the
26010 register allocator from using the mmx registers unless needed. */
26011 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
26014 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26016 /* SSE1 doesn't have any direct moves from other classes. */
26020 /* If the target says that inter-unit moves are more expensive
26021 than moving through memory, then don't generate them. */
26022 if (!TARGET_INTER_UNIT_MOVES)
26025 /* Between SSE and general, we have moves no larger than word size. */
26026 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
26034 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26035 enum machine_mode mode, int strict)
26037 return inline_secondary_memory_needed (class1, class2, mode, strict);
26040 /* Return true if the registers in CLASS cannot represent the change from
26041 modes FROM to TO. */
26044 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
26045 enum reg_class regclass)
26050 /* x87 registers can't do subreg at all, as all values are reformatted
26051 to extended precision. */
26052 if (MAYBE_FLOAT_CLASS_P (regclass))
26055 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
26057 /* Vector registers do not support QI or HImode loads. If we don't
26058 disallow a change to these modes, reload will assume it's ok to
26059 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26060 the vec_dupv4hi pattern. */
26061 if (GET_MODE_SIZE (from) < 4)
26064 /* Vector registers do not support subreg with nonzero offsets, which
26065 are otherwise valid for integer registers. Since we can't see
26066 whether we have a nonzero offset from here, prohibit all
26067 nonparadoxical subregs changing size. */
26068 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
26075 /* Return the cost of moving data of mode M between a
26076 register and memory. A value of 2 is the default; this cost is
26077 relative to those in `REGISTER_MOVE_COST'.
26079 This function is used extensively by register_move_cost that is used to
26080 build tables at startup. Make it inline in this case.
26081 When IN is 2, return maximum of in and out move cost.
26083 If moving between registers and memory is more expensive than
26084 between two registers, you should define this macro to express the
26087 Model also increased moving costs of QImode registers in non
26091 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
26095 if (FLOAT_CLASS_P (regclass))
26113 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
26114 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
26116 if (SSE_CLASS_P (regclass))
26119 switch (GET_MODE_SIZE (mode))
26134 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
26135 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
26137 if (MMX_CLASS_P (regclass))
26140 switch (GET_MODE_SIZE (mode))
26152 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
26153 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
26155 switch (GET_MODE_SIZE (mode))
26158 if (Q_CLASS_P (regclass) || TARGET_64BIT)
26161 return ix86_cost->int_store[0];
26162 if (TARGET_PARTIAL_REG_DEPENDENCY
26163 && optimize_function_for_speed_p (cfun))
26164 cost = ix86_cost->movzbl_load;
26166 cost = ix86_cost->int_load[0];
26168 return MAX (cost, ix86_cost->int_store[0]);
26174 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
26176 return ix86_cost->movzbl_load;
26178 return ix86_cost->int_store[0] + 4;
26183 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
26184 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
26186 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26187 if (mode == TFmode)
26190 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
26192 cost = ix86_cost->int_load[2];
26194 cost = ix86_cost->int_store[2];
26195 return (cost * (((int) GET_MODE_SIZE (mode)
26196 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
26201 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
26203 return inline_memory_move_cost (mode, regclass, in);
26207 /* Return the cost of moving data from a register in class CLASS1 to
26208 one in class CLASS2.
26210 It is not required that the cost always equal 2 when FROM is the same as TO;
26211 on some machines it is expensive to move between registers if they are not
26212 general registers. */
26215 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
26216 enum reg_class class2)
26218 /* In case we require secondary memory, compute cost of the store followed
26219 by load. In order to avoid bad register allocation choices, we need
26220 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
26222 if (inline_secondary_memory_needed (class1, class2, mode, 0))
26226 cost += inline_memory_move_cost (mode, class1, 2);
26227 cost += inline_memory_move_cost (mode, class2, 2);
26229 /* In case of copying from general_purpose_register we may emit multiple
26230 stores followed by single load causing memory size mismatch stall.
26231 Count this as arbitrarily high cost of 20. */
26232 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
26235 /* In the case of FP/MMX moves, the registers actually overlap, and we
26236 have to switch modes in order to treat them differently. */
26237 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
26238 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
26244 /* Moves between SSE/MMX and integer unit are expensive. */
26245 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
26246 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26248 /* ??? By keeping returned value relatively high, we limit the number
26249 of moves between integer and MMX/SSE registers for all targets.
26250 Additionally, high value prevents problem with x86_modes_tieable_p(),
26251 where integer modes in MMX/SSE registers are not tieable
26252 because of missing QImode and HImode moves to, from or between
26253 MMX/SSE registers. */
26254 return MAX (8, ix86_cost->mmxsse_to_integer);
26256 if (MAYBE_FLOAT_CLASS_P (class1))
26257 return ix86_cost->fp_move;
26258 if (MAYBE_SSE_CLASS_P (class1))
26259 return ix86_cost->sse_move;
26260 if (MAYBE_MMX_CLASS_P (class1))
26261 return ix86_cost->mmx_move;
26265 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
26268 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
26270 /* Flags and only flags can only hold CCmode values. */
26271 if (CC_REGNO_P (regno))
26272 return GET_MODE_CLASS (mode) == MODE_CC;
26273 if (GET_MODE_CLASS (mode) == MODE_CC
26274 || GET_MODE_CLASS (mode) == MODE_RANDOM
26275 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
26277 if (FP_REGNO_P (regno))
26278 return VALID_FP_MODE_P (mode);
26279 if (SSE_REGNO_P (regno))
26281 /* We implement the move patterns for all vector modes into and
26282 out of SSE registers, even when no operation instructions
26283 are available. OImode move is available only when AVX is
26285 return ((TARGET_AVX && mode == OImode)
26286 || VALID_AVX256_REG_MODE (mode)
26287 || VALID_SSE_REG_MODE (mode)
26288 || VALID_SSE2_REG_MODE (mode)
26289 || VALID_MMX_REG_MODE (mode)
26290 || VALID_MMX_REG_MODE_3DNOW (mode));
26292 if (MMX_REGNO_P (regno))
26294 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26295 so if the register is available at all, then we can move data of
26296 the given mode into or out of it. */
26297 return (VALID_MMX_REG_MODE (mode)
26298 || VALID_MMX_REG_MODE_3DNOW (mode));
26301 if (mode == QImode)
26303 /* Take care for QImode values - they can be in non-QI regs,
26304 but then they do cause partial register stalls. */
26305 if (regno <= BX_REG || TARGET_64BIT)
26307 if (!TARGET_PARTIAL_REG_STALL)
26309 return reload_in_progress || reload_completed;
26311 /* We handle both integer and floats in the general purpose registers. */
26312 else if (VALID_INT_MODE_P (mode))
26314 else if (VALID_FP_MODE_P (mode))
26316 else if (VALID_DFP_MODE_P (mode))
26318 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26319 on to use that value in smaller contexts, this can easily force a
26320 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26321 supporting DImode, allow it. */
26322 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26328 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26329 tieable integer mode. */
26332 ix86_tieable_integer_mode_p (enum machine_mode mode)
26341 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26344 return TARGET_64BIT;
26351 /* Return true if MODE1 is accessible in a register that can hold MODE2
26352 without copying. That is, all register classes that can hold MODE2
26353 can also hold MODE1. */
26356 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26358 if (mode1 == mode2)
26361 if (ix86_tieable_integer_mode_p (mode1)
26362 && ix86_tieable_integer_mode_p (mode2))
26365 /* MODE2 being XFmode implies fp stack or general regs, which means we
26366 can tie any smaller floating point modes to it. Note that we do not
26367 tie this with TFmode. */
26368 if (mode2 == XFmode)
26369 return mode1 == SFmode || mode1 == DFmode;
26371 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26372 that we can tie it with SFmode. */
26373 if (mode2 == DFmode)
26374 return mode1 == SFmode;
26376 /* If MODE2 is only appropriate for an SSE register, then tie with
26377 any other mode acceptable to SSE registers. */
26378 if (GET_MODE_SIZE (mode2) == 16
26379 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26380 return (GET_MODE_SIZE (mode1) == 16
26381 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26383 /* If MODE2 is appropriate for an MMX register, then tie
26384 with any other mode acceptable to MMX registers. */
26385 if (GET_MODE_SIZE (mode2) == 8
26386 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26387 return (GET_MODE_SIZE (mode1) == 8
26388 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26393 /* Compute a (partial) cost for rtx X. Return true if the complete
26394 cost has been computed, and false if subexpressions should be
26395 scanned. In either case, *TOTAL contains the cost result. */
26398 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26400 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26401 enum machine_mode mode = GET_MODE (x);
26402 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26410 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26412 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26414 else if (flag_pic && SYMBOLIC_CONST (x)
26416 || (!GET_CODE (x) != LABEL_REF
26417 && (GET_CODE (x) != SYMBOL_REF
26418 || !SYMBOL_REF_LOCAL_P (x)))))
26425 if (mode == VOIDmode)
26428 switch (standard_80387_constant_p (x))
26433 default: /* Other constants */
26438 /* Start with (MEM (SYMBOL_REF)), since that's where
26439 it'll probably end up. Add a penalty for size. */
26440 *total = (COSTS_N_INSNS (1)
26441 + (flag_pic != 0 && !TARGET_64BIT)
26442 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26448 /* The zero extensions is often completely free on x86_64, so make
26449 it as cheap as possible. */
26450 if (TARGET_64BIT && mode == DImode
26451 && GET_MODE (XEXP (x, 0)) == SImode)
26453 else if (TARGET_ZERO_EXTEND_WITH_AND)
26454 *total = cost->add;
26456 *total = cost->movzx;
26460 *total = cost->movsx;
26464 if (CONST_INT_P (XEXP (x, 1))
26465 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26467 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26470 *total = cost->add;
26473 if ((value == 2 || value == 3)
26474 && cost->lea <= cost->shift_const)
26476 *total = cost->lea;
26486 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26488 if (CONST_INT_P (XEXP (x, 1)))
26490 if (INTVAL (XEXP (x, 1)) > 32)
26491 *total = cost->shift_const + COSTS_N_INSNS (2);
26493 *total = cost->shift_const * 2;
26497 if (GET_CODE (XEXP (x, 1)) == AND)
26498 *total = cost->shift_var * 2;
26500 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26505 if (CONST_INT_P (XEXP (x, 1)))
26506 *total = cost->shift_const;
26508 *total = cost->shift_var;
26513 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26515 /* ??? SSE scalar cost should be used here. */
26516 *total = cost->fmul;
26519 else if (X87_FLOAT_MODE_P (mode))
26521 *total = cost->fmul;
26524 else if (FLOAT_MODE_P (mode))
26526 /* ??? SSE vector cost should be used here. */
26527 *total = cost->fmul;
26532 rtx op0 = XEXP (x, 0);
26533 rtx op1 = XEXP (x, 1);
26535 if (CONST_INT_P (XEXP (x, 1)))
26537 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26538 for (nbits = 0; value != 0; value &= value - 1)
26542 /* This is arbitrary. */
26545 /* Compute costs correctly for widening multiplication. */
26546 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26547 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26548 == GET_MODE_SIZE (mode))
26550 int is_mulwiden = 0;
26551 enum machine_mode inner_mode = GET_MODE (op0);
26553 if (GET_CODE (op0) == GET_CODE (op1))
26554 is_mulwiden = 1, op1 = XEXP (op1, 0);
26555 else if (CONST_INT_P (op1))
26557 if (GET_CODE (op0) == SIGN_EXTEND)
26558 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26561 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26565 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26568 *total = (cost->mult_init[MODE_INDEX (mode)]
26569 + nbits * cost->mult_bit
26570 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26579 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26580 /* ??? SSE cost should be used here. */
26581 *total = cost->fdiv;
26582 else if (X87_FLOAT_MODE_P (mode))
26583 *total = cost->fdiv;
26584 else if (FLOAT_MODE_P (mode))
26585 /* ??? SSE vector cost should be used here. */
26586 *total = cost->fdiv;
26588 *total = cost->divide[MODE_INDEX (mode)];
26592 if (GET_MODE_CLASS (mode) == MODE_INT
26593 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26595 if (GET_CODE (XEXP (x, 0)) == PLUS
26596 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26597 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26598 && CONSTANT_P (XEXP (x, 1)))
26600 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26601 if (val == 2 || val == 4 || val == 8)
26603 *total = cost->lea;
26604 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26605 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26606 outer_code, speed);
26607 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26611 else if (GET_CODE (XEXP (x, 0)) == MULT
26612 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26614 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26615 if (val == 2 || val == 4 || val == 8)
26617 *total = cost->lea;
26618 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26619 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26623 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26625 *total = cost->lea;
26626 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26627 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26628 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26635 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26637 /* ??? SSE cost should be used here. */
26638 *total = cost->fadd;
26641 else if (X87_FLOAT_MODE_P (mode))
26643 *total = cost->fadd;
26646 else if (FLOAT_MODE_P (mode))
26648 /* ??? SSE vector cost should be used here. */
26649 *total = cost->fadd;
26657 if (!TARGET_64BIT && mode == DImode)
26659 *total = (cost->add * 2
26660 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26661 << (GET_MODE (XEXP (x, 0)) != DImode))
26662 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26663 << (GET_MODE (XEXP (x, 1)) != DImode)));
26669 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26671 /* ??? SSE cost should be used here. */
26672 *total = cost->fchs;
26675 else if (X87_FLOAT_MODE_P (mode))
26677 *total = cost->fchs;
26680 else if (FLOAT_MODE_P (mode))
26682 /* ??? SSE vector cost should be used here. */
26683 *total = cost->fchs;
26689 if (!TARGET_64BIT && mode == DImode)
26690 *total = cost->add * 2;
26692 *total = cost->add;
26696 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26697 && XEXP (XEXP (x, 0), 1) == const1_rtx
26698 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26699 && XEXP (x, 1) == const0_rtx)
26701 /* This kind of construct is implemented using test[bwl].
26702 Treat it as if we had an AND. */
26703 *total = (cost->add
26704 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26705 + rtx_cost (const1_rtx, outer_code, speed));
26711 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26716 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26717 /* ??? SSE cost should be used here. */
26718 *total = cost->fabs;
26719 else if (X87_FLOAT_MODE_P (mode))
26720 *total = cost->fabs;
26721 else if (FLOAT_MODE_P (mode))
26722 /* ??? SSE vector cost should be used here. */
26723 *total = cost->fabs;
26727 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26728 /* ??? SSE cost should be used here. */
26729 *total = cost->fsqrt;
26730 else if (X87_FLOAT_MODE_P (mode))
26731 *total = cost->fsqrt;
26732 else if (FLOAT_MODE_P (mode))
26733 /* ??? SSE vector cost should be used here. */
26734 *total = cost->fsqrt;
26738 if (XINT (x, 1) == UNSPEC_TP)
26749 static int current_machopic_label_num;
26751 /* Given a symbol name and its associated stub, write out the
26752 definition of the stub. */
26755 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26757 unsigned int length;
26758 char *binder_name, *symbol_name, lazy_ptr_name[32];
26759 int label = ++current_machopic_label_num;
26761 /* For 64-bit we shouldn't get here. */
26762 gcc_assert (!TARGET_64BIT);
26764 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26765 symb = (*targetm.strip_name_encoding) (symb);
26767 length = strlen (stub);
26768 binder_name = XALLOCAVEC (char, length + 32);
26769 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26771 length = strlen (symb);
26772 symbol_name = XALLOCAVEC (char, length + 32);
26773 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26775 sprintf (lazy_ptr_name, "L%d$lz", label);
26778 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26780 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26782 fprintf (file, "%s:\n", stub);
26783 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26787 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26788 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26789 fprintf (file, "\tjmp\t*%%edx\n");
26792 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26794 fprintf (file, "%s:\n", binder_name);
26798 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26799 fprintf (file, "\tpushl\t%%eax\n");
26802 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26804 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26806 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26807 fprintf (file, "%s:\n", lazy_ptr_name);
26808 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26809 fprintf (file, "\t.long %s\n", binder_name);
26813 darwin_x86_file_end (void)
26815 darwin_file_end ();
26818 #endif /* TARGET_MACHO */
26820 /* Order the registers for register allocator. */
26823 x86_order_regs_for_local_alloc (void)
26828 /* First allocate the local general purpose registers. */
26829 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26830 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26831 reg_alloc_order [pos++] = i;
26833 /* Global general purpose registers. */
26834 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26835 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26836 reg_alloc_order [pos++] = i;
26838 /* x87 registers come first in case we are doing FP math
26840 if (!TARGET_SSE_MATH)
26841 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26842 reg_alloc_order [pos++] = i;
26844 /* SSE registers. */
26845 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26846 reg_alloc_order [pos++] = i;
26847 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26848 reg_alloc_order [pos++] = i;
26850 /* x87 registers. */
26851 if (TARGET_SSE_MATH)
26852 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26853 reg_alloc_order [pos++] = i;
26855 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26856 reg_alloc_order [pos++] = i;
26858 /* Initialize the rest of array as we do not allocate some registers
26860 while (pos < FIRST_PSEUDO_REGISTER)
26861 reg_alloc_order [pos++] = 0;
26864 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26865 struct attribute_spec.handler. */
26867 ix86_handle_abi_attribute (tree *node, tree name,
26868 tree args ATTRIBUTE_UNUSED,
26869 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26871 if (TREE_CODE (*node) != FUNCTION_TYPE
26872 && TREE_CODE (*node) != METHOD_TYPE
26873 && TREE_CODE (*node) != FIELD_DECL
26874 && TREE_CODE (*node) != TYPE_DECL)
26876 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26878 *no_add_attrs = true;
26883 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26885 *no_add_attrs = true;
26889 /* Can combine regparm with all attributes but fastcall. */
26890 if (is_attribute_p ("ms_abi", name))
26892 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26894 error ("ms_abi and sysv_abi attributes are not compatible");
26899 else if (is_attribute_p ("sysv_abi", name))
26901 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26903 error ("ms_abi and sysv_abi attributes are not compatible");
26912 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26913 struct attribute_spec.handler. */
26915 ix86_handle_struct_attribute (tree *node, tree name,
26916 tree args ATTRIBUTE_UNUSED,
26917 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26920 if (DECL_P (*node))
26922 if (TREE_CODE (*node) == TYPE_DECL)
26923 type = &TREE_TYPE (*node);
26928 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26929 || TREE_CODE (*type) == UNION_TYPE)))
26931 warning (OPT_Wattributes, "%qE attribute ignored",
26933 *no_add_attrs = true;
26936 else if ((is_attribute_p ("ms_struct", name)
26937 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26938 || ((is_attribute_p ("gcc_struct", name)
26939 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26941 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26943 *no_add_attrs = true;
26950 ix86_ms_bitfield_layout_p (const_tree record_type)
26952 return (TARGET_MS_BITFIELD_LAYOUT &&
26953 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26954 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26957 /* Returns an expression indicating where the this parameter is
26958 located on entry to the FUNCTION. */
26961 x86_this_parameter (tree function)
26963 tree type = TREE_TYPE (function);
26964 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26969 const int *parm_regs;
26971 if (ix86_function_type_abi (type) == MS_ABI)
26972 parm_regs = x86_64_ms_abi_int_parameter_registers;
26974 parm_regs = x86_64_int_parameter_registers;
26975 return gen_rtx_REG (DImode, parm_regs[aggr]);
26978 nregs = ix86_function_regparm (type, function);
26980 if (nregs > 0 && !stdarg_p (type))
26984 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26985 regno = aggr ? DX_REG : CX_REG;
26993 return gen_rtx_MEM (SImode,
26994 plus_constant (stack_pointer_rtx, 4));
26997 return gen_rtx_REG (SImode, regno);
27000 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
27003 /* Determine whether x86_output_mi_thunk can succeed. */
27006 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
27007 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27008 HOST_WIDE_INT vcall_offset, const_tree function)
27010 /* 64-bit can handle anything. */
27014 /* For 32-bit, everything's fine if we have one free register. */
27015 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
27018 /* Need a free register for vcall_offset. */
27022 /* Need a free register for GOT references. */
27023 if (flag_pic && !(*targetm.binds_local_p) (function))
27026 /* Otherwise ok. */
27030 /* Output the assembler code for a thunk function. THUNK_DECL is the
27031 declaration for the thunk function itself, FUNCTION is the decl for
27032 the target function. DELTA is an immediate constant offset to be
27033 added to THIS. If VCALL_OFFSET is nonzero, the word at
27034 *(*this + vcall_offset) should be added to THIS. */
27037 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
27038 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
27039 HOST_WIDE_INT vcall_offset, tree function)
27042 rtx this_param = x86_this_parameter (function);
27045 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27046 pull it in now and let DELTA benefit. */
27047 if (REG_P (this_param))
27048 this_reg = this_param;
27049 else if (vcall_offset)
27051 /* Put the this parameter into %eax. */
27052 xops[0] = this_param;
27053 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
27054 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27057 this_reg = NULL_RTX;
27059 /* Adjust the this parameter by a fixed constant. */
27062 xops[0] = GEN_INT (delta);
27063 xops[1] = this_reg ? this_reg : this_param;
27066 if (!x86_64_general_operand (xops[0], DImode))
27068 tmp = gen_rtx_REG (DImode, R10_REG);
27070 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
27072 xops[1] = this_param;
27074 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
27077 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
27080 /* Adjust the this parameter by a value stored in the vtable. */
27084 tmp = gen_rtx_REG (DImode, R10_REG);
27087 int tmp_regno = CX_REG;
27088 if (lookup_attribute ("fastcall",
27089 TYPE_ATTRIBUTES (TREE_TYPE (function))))
27090 tmp_regno = AX_REG;
27091 tmp = gen_rtx_REG (SImode, tmp_regno);
27094 xops[0] = gen_rtx_MEM (Pmode, this_reg);
27096 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27098 /* Adjust the this parameter. */
27099 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
27100 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
27102 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
27103 xops[0] = GEN_INT (vcall_offset);
27105 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
27106 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
27108 xops[1] = this_reg;
27109 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
27112 /* If necessary, drop THIS back to its stack slot. */
27113 if (this_reg && this_reg != this_param)
27115 xops[0] = this_reg;
27116 xops[1] = this_param;
27117 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27120 xops[0] = XEXP (DECL_RTL (function), 0);
27123 if (!flag_pic || (*targetm.binds_local_p) (function))
27124 output_asm_insn ("jmp\t%P0", xops);
27125 /* All thunks should be in the same object as their target,
27126 and thus binds_local_p should be true. */
27127 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
27128 gcc_unreachable ();
27131 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
27132 tmp = gen_rtx_CONST (Pmode, tmp);
27133 tmp = gen_rtx_MEM (QImode, tmp);
27135 output_asm_insn ("jmp\t%A0", xops);
27140 if (!flag_pic || (*targetm.binds_local_p) (function))
27141 output_asm_insn ("jmp\t%P0", xops);
27146 rtx sym_ref = XEXP (DECL_RTL (function), 0);
27147 tmp = (gen_rtx_SYMBOL_REF
27149 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
27150 tmp = gen_rtx_MEM (QImode, tmp);
27152 output_asm_insn ("jmp\t%0", xops);
27155 #endif /* TARGET_MACHO */
27157 tmp = gen_rtx_REG (SImode, CX_REG);
27158 output_set_got (tmp, NULL_RTX);
27161 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
27162 output_asm_insn ("jmp\t{*}%1", xops);
27168 x86_file_start (void)
27170 default_file_start ();
27172 darwin_file_start ();
27174 if (X86_FILE_START_VERSION_DIRECTIVE)
27175 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
27176 if (X86_FILE_START_FLTUSED)
27177 fputs ("\t.global\t__fltused\n", asm_out_file);
27178 if (ix86_asm_dialect == ASM_INTEL)
27179 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
27183 x86_field_alignment (tree field, int computed)
27185 enum machine_mode mode;
27186 tree type = TREE_TYPE (field);
27188 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
27190 mode = TYPE_MODE (strip_array_types (type));
27191 if (mode == DFmode || mode == DCmode
27192 || GET_MODE_CLASS (mode) == MODE_INT
27193 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
27194 return MIN (32, computed);
27198 /* Output assembler code to FILE to increment profiler label # LABELNO
27199 for profiling a function entry. */
27201 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
27205 #ifndef NO_PROFILE_COUNTERS
27206 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
27209 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
27210 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
27212 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
27216 #ifndef NO_PROFILE_COUNTERS
27217 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
27218 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
27220 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
27224 #ifndef NO_PROFILE_COUNTERS
27225 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
27226 PROFILE_COUNT_REGISTER);
27228 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
27232 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27233 /* We don't have exact information about the insn sizes, but we may assume
27234 quite safely that we are informed about all 1 byte insns and memory
27235 address sizes. This is enough to eliminate unnecessary padding in
27239 min_insn_size (rtx insn)
27243 if (!INSN_P (insn) || !active_insn_p (insn))
27246 /* Discard alignments we've emit and jump instructions. */
27247 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
27248 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
27250 if (JUMP_TABLE_DATA_P(insn))
27253 /* Important case - calls are always 5 bytes.
27254 It is common to have many calls in the row. */
27256 && symbolic_reference_mentioned_p (PATTERN (insn))
27257 && !SIBLING_CALL_P (insn))
27259 if (get_attr_length (insn) <= 1)
27262 /* For normal instructions we may rely on the sizes of addresses
27263 and the presence of symbol to require 4 bytes of encoding.
27264 This is not the case for jumps where references are PC relative. */
27265 if (!JUMP_P (insn))
27267 l = get_attr_length_address (insn);
27268 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
27277 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
27281 ix86_avoid_jump_mispredicts (void)
27283 rtx insn, start = get_insns ();
27284 int nbytes = 0, njumps = 0;
27287 /* Look for all minimal intervals of instructions containing 4 jumps.
27288 The intervals are bounded by START and INSN. NBYTES is the total
27289 size of instructions in the interval including INSN and not including
27290 START. When the NBYTES is smaller than 16 bytes, it is possible
27291 that the end of START and INSN ends up in the same 16byte page.
27293 The smallest offset in the page INSN can start is the case where START
27294 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27295 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
27297 for (insn = start; insn; insn = NEXT_INSN (insn))
27301 if (LABEL_P (insn))
27303 int align = label_to_alignment (insn);
27304 int max_skip = label_to_max_skip (insn);
27308 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
27309 already in the current 16 byte page, because otherwise
27310 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
27311 bytes to reach 16 byte boundary. */
27313 || (align <= 3 && max_skip != (1 << align) - 1))
27316 fprintf (dump_file, "Label %i with max_skip %i\n",
27317 INSN_UID (insn), max_skip);
27320 while (nbytes + max_skip >= 16)
27322 start = NEXT_INSN (start);
27323 if ((JUMP_P (start)
27324 && GET_CODE (PATTERN (start)) != ADDR_VEC
27325 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27327 njumps--, isjump = 1;
27330 nbytes -= min_insn_size (start);
27336 min_size = min_insn_size (insn);
27337 nbytes += min_size;
27339 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
27340 INSN_UID (insn), min_size);
27342 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27343 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27351 start = NEXT_INSN (start);
27352 if ((JUMP_P (start)
27353 && GET_CODE (PATTERN (start)) != ADDR_VEC
27354 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27356 njumps--, isjump = 1;
27359 nbytes -= min_insn_size (start);
27361 gcc_assert (njumps >= 0);
27363 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27364 INSN_UID (start), INSN_UID (insn), nbytes);
27366 if (njumps == 3 && isjump && nbytes < 16)
27368 int padsize = 15 - nbytes + min_insn_size (insn);
27371 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27372 INSN_UID (insn), padsize);
27373 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27379 /* AMD Athlon works faster
27380 when RET is not destination of conditional jump or directly preceded
27381 by other jump instruction. We avoid the penalty by inserting NOP just
27382 before the RET instructions in such cases. */
27384 ix86_pad_returns (void)
27389 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27391 basic_block bb = e->src;
27392 rtx ret = BB_END (bb);
27394 bool replace = false;
27396 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27397 || optimize_bb_for_size_p (bb))
27399 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27400 if (active_insn_p (prev) || LABEL_P (prev))
27402 if (prev && LABEL_P (prev))
27407 FOR_EACH_EDGE (e, ei, bb->preds)
27408 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27409 && !(e->flags & EDGE_FALLTHRU))
27414 prev = prev_active_insn (ret);
27416 && ((JUMP_P (prev) && any_condjump_p (prev))
27419 /* Empty functions get branch mispredict even when the jump destination
27420 is not visible to us. */
27421 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27426 emit_insn_before (gen_return_internal_long (), ret);
27432 /* Implement machine specific optimizations. We implement padding of returns
27433 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27437 if (optimize && optimize_function_for_speed_p (cfun))
27439 if (TARGET_PAD_RETURNS)
27440 ix86_pad_returns ();
27441 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27442 if (TARGET_FOUR_JUMP_LIMIT)
27443 ix86_avoid_jump_mispredicts ();
27448 /* Return nonzero when QImode register that must be represented via REX prefix
27451 x86_extended_QIreg_mentioned_p (rtx insn)
27454 extract_insn_cached (insn);
27455 for (i = 0; i < recog_data.n_operands; i++)
27456 if (REG_P (recog_data.operand[i])
27457 && REGNO (recog_data.operand[i]) > BX_REG)
27462 /* Return nonzero when P points to register encoded via REX prefix.
27463 Called via for_each_rtx. */
27465 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27467 unsigned int regno;
27470 regno = REGNO (*p);
27471 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27474 /* Return true when INSN mentions register that must be encoded using REX
27477 x86_extended_reg_mentioned_p (rtx insn)
27479 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27480 extended_reg_mentioned_1, NULL);
27483 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27484 optabs would emit if we didn't have TFmode patterns. */
27487 x86_emit_floatuns (rtx operands[2])
27489 rtx neglab, donelab, i0, i1, f0, in, out;
27490 enum machine_mode mode, inmode;
27492 inmode = GET_MODE (operands[1]);
27493 gcc_assert (inmode == SImode || inmode == DImode);
27496 in = force_reg (inmode, operands[1]);
27497 mode = GET_MODE (out);
27498 neglab = gen_label_rtx ();
27499 donelab = gen_label_rtx ();
27500 f0 = gen_reg_rtx (mode);
27502 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27504 expand_float (out, in, 0);
27506 emit_jump_insn (gen_jump (donelab));
27509 emit_label (neglab);
27511 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27513 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27515 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27517 expand_float (f0, i0, 0);
27519 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27521 emit_label (donelab);
27524 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27525 with all elements equal to VAR. Return true if successful. */
27528 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27529 rtx target, rtx val)
27531 enum machine_mode hmode, smode, wsmode, wvmode;
27546 val = force_reg (GET_MODE_INNER (mode), val);
27547 x = gen_rtx_VEC_DUPLICATE (mode, val);
27548 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27554 if (TARGET_SSE || TARGET_3DNOW_A)
27556 val = gen_lowpart (SImode, val);
27557 x = gen_rtx_TRUNCATE (HImode, val);
27558 x = gen_rtx_VEC_DUPLICATE (mode, x);
27559 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27581 /* Extend HImode to SImode using a paradoxical SUBREG. */
27582 tmp1 = gen_reg_rtx (SImode);
27583 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27584 /* Insert the SImode value as low element of V4SImode vector. */
27585 tmp2 = gen_reg_rtx (V4SImode);
27586 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27587 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27588 CONST0_RTX (V4SImode),
27590 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27591 /* Cast the V4SImode vector back to a V8HImode vector. */
27592 tmp1 = gen_reg_rtx (V8HImode);
27593 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27594 /* Duplicate the low short through the whole low SImode word. */
27595 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27596 /* Cast the V8HImode vector back to a V4SImode vector. */
27597 tmp2 = gen_reg_rtx (V4SImode);
27598 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27599 /* Replicate the low element of the V4SImode vector. */
27600 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27601 /* Cast the V2SImode back to V8HImode, and store in target. */
27602 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27613 /* Extend QImode to SImode using a paradoxical SUBREG. */
27614 tmp1 = gen_reg_rtx (SImode);
27615 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27616 /* Insert the SImode value as low element of V4SImode vector. */
27617 tmp2 = gen_reg_rtx (V4SImode);
27618 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27619 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27620 CONST0_RTX (V4SImode),
27622 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27623 /* Cast the V4SImode vector back to a V16QImode vector. */
27624 tmp1 = gen_reg_rtx (V16QImode);
27625 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27626 /* Duplicate the low byte through the whole low SImode word. */
27627 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27628 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27629 /* Cast the V16QImode vector back to a V4SImode vector. */
27630 tmp2 = gen_reg_rtx (V4SImode);
27631 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27632 /* Replicate the low element of the V4SImode vector. */
27633 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27634 /* Cast the V2SImode back to V16QImode, and store in target. */
27635 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27643 /* Replicate the value once into the next wider mode and recurse. */
27644 val = convert_modes (wsmode, smode, val, true);
27645 x = expand_simple_binop (wsmode, ASHIFT, val,
27646 GEN_INT (GET_MODE_BITSIZE (smode)),
27647 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27648 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27650 x = gen_reg_rtx (wvmode);
27651 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27652 gcc_unreachable ();
27653 emit_move_insn (target, gen_lowpart (mode, x));
27676 rtx tmp = gen_reg_rtx (hmode);
27677 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27678 emit_insn (gen_rtx_SET (VOIDmode, target,
27679 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27688 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27689 whose ONE_VAR element is VAR, and other elements are zero. Return true
27693 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27694 rtx target, rtx var, int one_var)
27696 enum machine_mode vsimode;
27699 bool use_vector_set = false;
27704 /* For SSE4.1, we normally use vector set. But if the second
27705 element is zero and inter-unit moves are OK, we use movq
27707 use_vector_set = (TARGET_64BIT
27709 && !(TARGET_INTER_UNIT_MOVES
27715 use_vector_set = TARGET_SSE4_1;
27718 use_vector_set = TARGET_SSE2;
27721 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27728 use_vector_set = TARGET_AVX;
27731 /* Use ix86_expand_vector_set in 64bit mode only. */
27732 use_vector_set = TARGET_AVX && TARGET_64BIT;
27738 if (use_vector_set)
27740 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27741 var = force_reg (GET_MODE_INNER (mode), var);
27742 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27758 var = force_reg (GET_MODE_INNER (mode), var);
27759 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27760 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27765 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27766 new_target = gen_reg_rtx (mode);
27768 new_target = target;
27769 var = force_reg (GET_MODE_INNER (mode), var);
27770 x = gen_rtx_VEC_DUPLICATE (mode, var);
27771 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27772 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27775 /* We need to shuffle the value to the correct position, so
27776 create a new pseudo to store the intermediate result. */
27778 /* With SSE2, we can use the integer shuffle insns. */
27779 if (mode != V4SFmode && TARGET_SSE2)
27781 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27783 GEN_INT (one_var == 1 ? 0 : 1),
27784 GEN_INT (one_var == 2 ? 0 : 1),
27785 GEN_INT (one_var == 3 ? 0 : 1)));
27786 if (target != new_target)
27787 emit_move_insn (target, new_target);
27791 /* Otherwise convert the intermediate result to V4SFmode and
27792 use the SSE1 shuffle instructions. */
27793 if (mode != V4SFmode)
27795 tmp = gen_reg_rtx (V4SFmode);
27796 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27801 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27803 GEN_INT (one_var == 1 ? 0 : 1),
27804 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27805 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27807 if (mode != V4SFmode)
27808 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27809 else if (tmp != target)
27810 emit_move_insn (target, tmp);
27812 else if (target != new_target)
27813 emit_move_insn (target, new_target);
27818 vsimode = V4SImode;
27824 vsimode = V2SImode;
27830 /* Zero extend the variable element to SImode and recurse. */
27831 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27833 x = gen_reg_rtx (vsimode);
27834 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27836 gcc_unreachable ();
27838 emit_move_insn (target, gen_lowpart (mode, x));
27846 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27847 consisting of the values in VALS. It is known that all elements
27848 except ONE_VAR are constants. Return true if successful. */
27851 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27852 rtx target, rtx vals, int one_var)
27854 rtx var = XVECEXP (vals, 0, one_var);
27855 enum machine_mode wmode;
27858 const_vec = copy_rtx (vals);
27859 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27860 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27868 /* For the two element vectors, it's just as easy to use
27869 the general case. */
27873 /* Use ix86_expand_vector_set in 64bit mode only. */
27896 /* There's no way to set one QImode entry easily. Combine
27897 the variable value with its adjacent constant value, and
27898 promote to an HImode set. */
27899 x = XVECEXP (vals, 0, one_var ^ 1);
27902 var = convert_modes (HImode, QImode, var, true);
27903 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27904 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27905 x = GEN_INT (INTVAL (x) & 0xff);
27909 var = convert_modes (HImode, QImode, var, true);
27910 x = gen_int_mode (INTVAL (x) << 8, HImode);
27912 if (x != const0_rtx)
27913 var = expand_simple_binop (HImode, IOR, var, x, var,
27914 1, OPTAB_LIB_WIDEN);
27916 x = gen_reg_rtx (wmode);
27917 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27918 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27920 emit_move_insn (target, gen_lowpart (mode, x));
27927 emit_move_insn (target, const_vec);
27928 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27932 /* A subroutine of ix86_expand_vector_init_general. Use vector
27933 concatenate to handle the most general case: all values variable,
27934 and none identical. */
27937 ix86_expand_vector_init_concat (enum machine_mode mode,
27938 rtx target, rtx *ops, int n)
27940 enum machine_mode cmode, hmode = VOIDmode;
27941 rtx first[8], second[4];
27981 gcc_unreachable ();
27984 if (!register_operand (ops[1], cmode))
27985 ops[1] = force_reg (cmode, ops[1]);
27986 if (!register_operand (ops[0], cmode))
27987 ops[0] = force_reg (cmode, ops[0]);
27988 emit_insn (gen_rtx_SET (VOIDmode, target,
27989 gen_rtx_VEC_CONCAT (mode, ops[0],
28009 gcc_unreachable ();
28025 gcc_unreachable ();
28030 /* FIXME: We process inputs backward to help RA. PR 36222. */
28033 for (; i > 0; i -= 2, j--)
28035 first[j] = gen_reg_rtx (cmode);
28036 v = gen_rtvec (2, ops[i - 1], ops[i]);
28037 ix86_expand_vector_init (false, first[j],
28038 gen_rtx_PARALLEL (cmode, v));
28044 gcc_assert (hmode != VOIDmode);
28045 for (i = j = 0; i < n; i += 2, j++)
28047 second[j] = gen_reg_rtx (hmode);
28048 ix86_expand_vector_init_concat (hmode, second [j],
28052 ix86_expand_vector_init_concat (mode, target, second, n);
28055 ix86_expand_vector_init_concat (mode, target, first, n);
28059 gcc_unreachable ();
28063 /* A subroutine of ix86_expand_vector_init_general. Use vector
28064 interleave to handle the most general case: all values variable,
28065 and none identical. */
28068 ix86_expand_vector_init_interleave (enum machine_mode mode,
28069 rtx target, rtx *ops, int n)
28071 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
28074 rtx (*gen_load_even) (rtx, rtx, rtx);
28075 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
28076 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
28081 gen_load_even = gen_vec_setv8hi;
28082 gen_interleave_first_low = gen_vec_interleave_lowv4si;
28083 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28084 inner_mode = HImode;
28085 first_imode = V4SImode;
28086 second_imode = V2DImode;
28087 third_imode = VOIDmode;
28090 gen_load_even = gen_vec_setv16qi;
28091 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
28092 gen_interleave_second_low = gen_vec_interleave_lowv4si;
28093 inner_mode = QImode;
28094 first_imode = V8HImode;
28095 second_imode = V4SImode;
28096 third_imode = V2DImode;
28099 gcc_unreachable ();
28102 for (i = 0; i < n; i++)
28104 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
28105 op0 = gen_reg_rtx (SImode);
28106 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
28108 /* Insert the SImode value as low element of V4SImode vector. */
28109 op1 = gen_reg_rtx (V4SImode);
28110 op0 = gen_rtx_VEC_MERGE (V4SImode,
28111 gen_rtx_VEC_DUPLICATE (V4SImode,
28113 CONST0_RTX (V4SImode),
28115 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
28117 /* Cast the V4SImode vector back to a vector in orignal mode. */
28118 op0 = gen_reg_rtx (mode);
28119 emit_move_insn (op0, gen_lowpart (mode, op1));
28121 /* Load even elements into the second positon. */
28122 emit_insn ((*gen_load_even) (op0,
28123 force_reg (inner_mode,
28127 /* Cast vector to FIRST_IMODE vector. */
28128 ops[i] = gen_reg_rtx (first_imode);
28129 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
28132 /* Interleave low FIRST_IMODE vectors. */
28133 for (i = j = 0; i < n; i += 2, j++)
28135 op0 = gen_reg_rtx (first_imode);
28136 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
28138 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
28139 ops[j] = gen_reg_rtx (second_imode);
28140 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
28143 /* Interleave low SECOND_IMODE vectors. */
28144 switch (second_imode)
28147 for (i = j = 0; i < n / 2; i += 2, j++)
28149 op0 = gen_reg_rtx (second_imode);
28150 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
28153 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
28155 ops[j] = gen_reg_rtx (third_imode);
28156 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
28158 second_imode = V2DImode;
28159 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28163 op0 = gen_reg_rtx (second_imode);
28164 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
28167 /* Cast the SECOND_IMODE vector back to a vector on original
28169 emit_insn (gen_rtx_SET (VOIDmode, target,
28170 gen_lowpart (mode, op0)));
28174 gcc_unreachable ();
28178 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
28179 all values variable, and none identical. */
28182 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
28183 rtx target, rtx vals)
28185 rtx ops[32], op0, op1;
28186 enum machine_mode half_mode = VOIDmode;
28193 if (!mmx_ok && !TARGET_SSE)
28205 n = GET_MODE_NUNITS (mode);
28206 for (i = 0; i < n; i++)
28207 ops[i] = XVECEXP (vals, 0, i);
28208 ix86_expand_vector_init_concat (mode, target, ops, n);
28212 half_mode = V16QImode;
28216 half_mode = V8HImode;
28220 n = GET_MODE_NUNITS (mode);
28221 for (i = 0; i < n; i++)
28222 ops[i] = XVECEXP (vals, 0, i);
28223 op0 = gen_reg_rtx (half_mode);
28224 op1 = gen_reg_rtx (half_mode);
28225 ix86_expand_vector_init_interleave (half_mode, op0, ops,
28227 ix86_expand_vector_init_interleave (half_mode, op1,
28228 &ops [n >> 1], n >> 2);
28229 emit_insn (gen_rtx_SET (VOIDmode, target,
28230 gen_rtx_VEC_CONCAT (mode, op0, op1)));
28234 if (!TARGET_SSE4_1)
28242 /* Don't use ix86_expand_vector_init_interleave if we can't
28243 move from GPR to SSE register directly. */
28244 if (!TARGET_INTER_UNIT_MOVES)
28247 n = GET_MODE_NUNITS (mode);
28248 for (i = 0; i < n; i++)
28249 ops[i] = XVECEXP (vals, 0, i);
28250 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
28258 gcc_unreachable ();
28262 int i, j, n_elts, n_words, n_elt_per_word;
28263 enum machine_mode inner_mode;
28264 rtx words[4], shift;
28266 inner_mode = GET_MODE_INNER (mode);
28267 n_elts = GET_MODE_NUNITS (mode);
28268 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
28269 n_elt_per_word = n_elts / n_words;
28270 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
28272 for (i = 0; i < n_words; ++i)
28274 rtx word = NULL_RTX;
28276 for (j = 0; j < n_elt_per_word; ++j)
28278 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
28279 elt = convert_modes (word_mode, inner_mode, elt, true);
28285 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
28286 word, 1, OPTAB_LIB_WIDEN);
28287 word = expand_simple_binop (word_mode, IOR, word, elt,
28288 word, 1, OPTAB_LIB_WIDEN);
28296 emit_move_insn (target, gen_lowpart (mode, words[0]));
28297 else if (n_words == 2)
28299 rtx tmp = gen_reg_rtx (mode);
28300 emit_clobber (tmp);
28301 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
28302 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
28303 emit_move_insn (target, tmp);
28305 else if (n_words == 4)
28307 rtx tmp = gen_reg_rtx (V4SImode);
28308 gcc_assert (word_mode == SImode);
28309 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
28310 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
28311 emit_move_insn (target, gen_lowpart (mode, tmp));
28314 gcc_unreachable ();
28318 /* Initialize vector TARGET via VALS. Suppress the use of MMX
28319 instructions unless MMX_OK is true. */
28322 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28324 enum machine_mode mode = GET_MODE (target);
28325 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28326 int n_elts = GET_MODE_NUNITS (mode);
28327 int n_var = 0, one_var = -1;
28328 bool all_same = true, all_const_zero = true;
28332 for (i = 0; i < n_elts; ++i)
28334 x = XVECEXP (vals, 0, i);
28335 if (!(CONST_INT_P (x)
28336 || GET_CODE (x) == CONST_DOUBLE
28337 || GET_CODE (x) == CONST_FIXED))
28338 n_var++, one_var = i;
28339 else if (x != CONST0_RTX (inner_mode))
28340 all_const_zero = false;
28341 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28345 /* Constants are best loaded from the constant pool. */
28348 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28352 /* If all values are identical, broadcast the value. */
28354 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28355 XVECEXP (vals, 0, 0)))
28358 /* Values where only one field is non-constant are best loaded from
28359 the pool and overwritten via move later. */
28363 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28364 XVECEXP (vals, 0, one_var),
28368 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28372 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28376 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28378 enum machine_mode mode = GET_MODE (target);
28379 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28380 enum machine_mode half_mode;
28381 bool use_vec_merge = false;
28383 static rtx (*gen_extract[6][2]) (rtx, rtx)
28385 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28386 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28387 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28388 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28389 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28390 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28392 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28394 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28395 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28396 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28397 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28398 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28399 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28409 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28410 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28412 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28414 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28415 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28421 use_vec_merge = TARGET_SSE4_1;
28429 /* For the two element vectors, we implement a VEC_CONCAT with
28430 the extraction of the other element. */
28432 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28433 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28436 op0 = val, op1 = tmp;
28438 op0 = tmp, op1 = val;
28440 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28441 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28446 use_vec_merge = TARGET_SSE4_1;
28453 use_vec_merge = true;
28457 /* tmp = target = A B C D */
28458 tmp = copy_to_reg (target);
28459 /* target = A A B B */
28460 emit_insn (gen_sse_unpcklps (target, target, target));
28461 /* target = X A B B */
28462 ix86_expand_vector_set (false, target, val, 0);
28463 /* target = A X C D */
28464 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28465 GEN_INT (1), GEN_INT (0),
28466 GEN_INT (2+4), GEN_INT (3+4)));
28470 /* tmp = target = A B C D */
28471 tmp = copy_to_reg (target);
28472 /* tmp = X B C D */
28473 ix86_expand_vector_set (false, tmp, val, 0);
28474 /* target = A B X D */
28475 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28476 GEN_INT (0), GEN_INT (1),
28477 GEN_INT (0+4), GEN_INT (3+4)));
28481 /* tmp = target = A B C D */
28482 tmp = copy_to_reg (target);
28483 /* tmp = X B C D */
28484 ix86_expand_vector_set (false, tmp, val, 0);
28485 /* target = A B X D */
28486 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28487 GEN_INT (0), GEN_INT (1),
28488 GEN_INT (2+4), GEN_INT (0+4)));
28492 gcc_unreachable ();
28497 use_vec_merge = TARGET_SSE4_1;
28501 /* Element 0 handled by vec_merge below. */
28504 use_vec_merge = true;
28510 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28511 store into element 0, then shuffle them back. */
28515 order[0] = GEN_INT (elt);
28516 order[1] = const1_rtx;
28517 order[2] = const2_rtx;
28518 order[3] = GEN_INT (3);
28519 order[elt] = const0_rtx;
28521 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28522 order[1], order[2], order[3]));
28524 ix86_expand_vector_set (false, target, val, 0);
28526 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28527 order[1], order[2], order[3]));
28531 /* For SSE1, we have to reuse the V4SF code. */
28532 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28533 gen_lowpart (SFmode, val), elt);
28538 use_vec_merge = TARGET_SSE2;
28541 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28545 use_vec_merge = TARGET_SSE4_1;
28552 half_mode = V16QImode;
28558 half_mode = V8HImode;
28564 half_mode = V4SImode;
28570 half_mode = V2DImode;
28576 half_mode = V4SFmode;
28582 half_mode = V2DFmode;
28588 /* Compute offset. */
28592 gcc_assert (i <= 1);
28594 /* Extract the half. */
28595 tmp = gen_reg_rtx (half_mode);
28596 emit_insn ((*gen_extract[j][i]) (tmp, target));
28598 /* Put val in tmp at elt. */
28599 ix86_expand_vector_set (false, tmp, val, elt);
28602 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28611 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28612 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28613 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28617 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28619 emit_move_insn (mem, target);
28621 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28622 emit_move_insn (tmp, val);
28624 emit_move_insn (target, mem);
28629 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28631 enum machine_mode mode = GET_MODE (vec);
28632 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28633 bool use_vec_extr = false;
28646 use_vec_extr = true;
28650 use_vec_extr = TARGET_SSE4_1;
28662 tmp = gen_reg_rtx (mode);
28663 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28664 GEN_INT (elt), GEN_INT (elt),
28665 GEN_INT (elt+4), GEN_INT (elt+4)));
28669 tmp = gen_reg_rtx (mode);
28670 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28674 gcc_unreachable ();
28677 use_vec_extr = true;
28682 use_vec_extr = TARGET_SSE4_1;
28696 tmp = gen_reg_rtx (mode);
28697 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28698 GEN_INT (elt), GEN_INT (elt),
28699 GEN_INT (elt), GEN_INT (elt)));
28703 tmp = gen_reg_rtx (mode);
28704 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28708 gcc_unreachable ();
28711 use_vec_extr = true;
28716 /* For SSE1, we have to reuse the V4SF code. */
28717 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28718 gen_lowpart (V4SFmode, vec), elt);
28724 use_vec_extr = TARGET_SSE2;
28727 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28731 use_vec_extr = TARGET_SSE4_1;
28735 /* ??? Could extract the appropriate HImode element and shift. */
28742 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28743 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28745 /* Let the rtl optimizers know about the zero extension performed. */
28746 if (inner_mode == QImode || inner_mode == HImode)
28748 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28749 target = gen_lowpart (SImode, target);
28752 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28756 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28758 emit_move_insn (mem, vec);
28760 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28761 emit_move_insn (target, tmp);
28765 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28766 pattern to reduce; DEST is the destination; IN is the input vector. */
28769 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28771 rtx tmp1, tmp2, tmp3;
28773 tmp1 = gen_reg_rtx (V4SFmode);
28774 tmp2 = gen_reg_rtx (V4SFmode);
28775 tmp3 = gen_reg_rtx (V4SFmode);
28777 emit_insn (gen_sse_movhlps (tmp1, in, in));
28778 emit_insn (fn (tmp2, tmp1, in));
28780 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28781 GEN_INT (1), GEN_INT (1),
28782 GEN_INT (1+4), GEN_INT (1+4)));
28783 emit_insn (fn (dest, tmp2, tmp3));
28786 /* Target hook for scalar_mode_supported_p. */
28788 ix86_scalar_mode_supported_p (enum machine_mode mode)
28790 if (DECIMAL_FLOAT_MODE_P (mode))
28792 else if (mode == TFmode)
28795 return default_scalar_mode_supported_p (mode);
28798 /* Implements target hook vector_mode_supported_p. */
28800 ix86_vector_mode_supported_p (enum machine_mode mode)
28802 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28804 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28806 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28808 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28810 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28815 /* Target hook for c_mode_for_suffix. */
28816 static enum machine_mode
28817 ix86_c_mode_for_suffix (char suffix)
28827 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28829 We do this in the new i386 backend to maintain source compatibility
28830 with the old cc0-based compiler. */
28833 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28834 tree inputs ATTRIBUTE_UNUSED,
28837 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28839 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28844 /* Implements target vector targetm.asm.encode_section_info. This
28845 is not used by netware. */
28847 static void ATTRIBUTE_UNUSED
28848 ix86_encode_section_info (tree decl, rtx rtl, int first)
28850 default_encode_section_info (decl, rtl, first);
28852 if (TREE_CODE (decl) == VAR_DECL
28853 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28854 && ix86_in_large_data_p (decl))
28855 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28858 /* Worker function for REVERSE_CONDITION. */
28861 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28863 return (mode != CCFPmode && mode != CCFPUmode
28864 ? reverse_condition (code)
28865 : reverse_condition_maybe_unordered (code));
28868 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28872 output_387_reg_move (rtx insn, rtx *operands)
28874 if (REG_P (operands[0]))
28876 if (REG_P (operands[1])
28877 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28879 if (REGNO (operands[0]) == FIRST_STACK_REG)
28880 return output_387_ffreep (operands, 0);
28881 return "fstp\t%y0";
28883 if (STACK_TOP_P (operands[0]))
28884 return "fld%Z1\t%y1";
28887 else if (MEM_P (operands[0]))
28889 gcc_assert (REG_P (operands[1]));
28890 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28891 return "fstp%Z0\t%y0";
28894 /* There is no non-popping store to memory for XFmode.
28895 So if we need one, follow the store with a load. */
28896 if (GET_MODE (operands[0]) == XFmode)
28897 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28899 return "fst%Z0\t%y0";
28906 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28907 FP status register is set. */
28910 ix86_emit_fp_unordered_jump (rtx label)
28912 rtx reg = gen_reg_rtx (HImode);
28915 emit_insn (gen_x86_fnstsw_1 (reg));
28917 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28919 emit_insn (gen_x86_sahf_1 (reg));
28921 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28922 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28926 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28928 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28929 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28932 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28933 gen_rtx_LABEL_REF (VOIDmode, label),
28935 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28937 emit_jump_insn (temp);
28938 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28941 /* Output code to perform a log1p XFmode calculation. */
28943 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28945 rtx label1 = gen_label_rtx ();
28946 rtx label2 = gen_label_rtx ();
28948 rtx tmp = gen_reg_rtx (XFmode);
28949 rtx tmp2 = gen_reg_rtx (XFmode);
28952 emit_insn (gen_absxf2 (tmp, op1));
28953 test = gen_rtx_GE (VOIDmode, tmp,
28954 CONST_DOUBLE_FROM_REAL_VALUE (
28955 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28957 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28959 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28960 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28961 emit_jump (label2);
28963 emit_label (label1);
28964 emit_move_insn (tmp, CONST1_RTX (XFmode));
28965 emit_insn (gen_addxf3 (tmp, op1, tmp));
28966 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28967 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28969 emit_label (label2);
28972 /* Output code to perform a Newton-Rhapson approximation of a single precision
28973 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28975 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28977 rtx x0, x1, e0, e1, two;
28979 x0 = gen_reg_rtx (mode);
28980 e0 = gen_reg_rtx (mode);
28981 e1 = gen_reg_rtx (mode);
28982 x1 = gen_reg_rtx (mode);
28984 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28986 if (VECTOR_MODE_P (mode))
28987 two = ix86_build_const_vector (SFmode, true, two);
28989 two = force_reg (mode, two);
28991 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28993 /* x0 = rcp(b) estimate */
28994 emit_insn (gen_rtx_SET (VOIDmode, x0,
28995 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28998 emit_insn (gen_rtx_SET (VOIDmode, e0,
28999 gen_rtx_MULT (mode, x0, b)));
29001 emit_insn (gen_rtx_SET (VOIDmode, e1,
29002 gen_rtx_MINUS (mode, two, e0)));
29004 emit_insn (gen_rtx_SET (VOIDmode, x1,
29005 gen_rtx_MULT (mode, x0, e1)));
29007 emit_insn (gen_rtx_SET (VOIDmode, res,
29008 gen_rtx_MULT (mode, a, x1)));
29011 /* Output code to perform a Newton-Rhapson approximation of a
29012 single precision floating point [reciprocal] square root. */
29014 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
29017 rtx x0, e0, e1, e2, e3, mthree, mhalf;
29020 x0 = gen_reg_rtx (mode);
29021 e0 = gen_reg_rtx (mode);
29022 e1 = gen_reg_rtx (mode);
29023 e2 = gen_reg_rtx (mode);
29024 e3 = gen_reg_rtx (mode);
29026 real_from_integer (&r, VOIDmode, -3, -1, 0);
29027 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29029 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
29030 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29032 if (VECTOR_MODE_P (mode))
29034 mthree = ix86_build_const_vector (SFmode, true, mthree);
29035 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
29038 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
29039 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
29041 /* x0 = rsqrt(a) estimate */
29042 emit_insn (gen_rtx_SET (VOIDmode, x0,
29043 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
29046 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
29051 zero = gen_reg_rtx (mode);
29052 mask = gen_reg_rtx (mode);
29054 zero = force_reg (mode, CONST0_RTX(mode));
29055 emit_insn (gen_rtx_SET (VOIDmode, mask,
29056 gen_rtx_NE (mode, zero, a)));
29058 emit_insn (gen_rtx_SET (VOIDmode, x0,
29059 gen_rtx_AND (mode, x0, mask)));
29063 emit_insn (gen_rtx_SET (VOIDmode, e0,
29064 gen_rtx_MULT (mode, x0, a)));
29066 emit_insn (gen_rtx_SET (VOIDmode, e1,
29067 gen_rtx_MULT (mode, e0, x0)));
29070 mthree = force_reg (mode, mthree);
29071 emit_insn (gen_rtx_SET (VOIDmode, e2,
29072 gen_rtx_PLUS (mode, e1, mthree)));
29074 mhalf = force_reg (mode, mhalf);
29076 /* e3 = -.5 * x0 */
29077 emit_insn (gen_rtx_SET (VOIDmode, e3,
29078 gen_rtx_MULT (mode, x0, mhalf)));
29080 /* e3 = -.5 * e0 */
29081 emit_insn (gen_rtx_SET (VOIDmode, e3,
29082 gen_rtx_MULT (mode, e0, mhalf)));
29083 /* ret = e2 * e3 */
29084 emit_insn (gen_rtx_SET (VOIDmode, res,
29085 gen_rtx_MULT (mode, e2, e3)));
29088 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
29090 static void ATTRIBUTE_UNUSED
29091 i386_solaris_elf_named_section (const char *name, unsigned int flags,
29094 /* With Binutils 2.15, the "@unwind" marker must be specified on
29095 every occurrence of the ".eh_frame" section, not just the first
29098 && strcmp (name, ".eh_frame") == 0)
29100 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
29101 flags & SECTION_WRITE ? "aw" : "a");
29104 default_elf_asm_named_section (name, flags, decl);
29107 /* Return the mangling of TYPE if it is an extended fundamental type. */
29109 static const char *
29110 ix86_mangle_type (const_tree type)
29112 type = TYPE_MAIN_VARIANT (type);
29114 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
29115 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
29118 switch (TYPE_MODE (type))
29121 /* __float128 is "g". */
29124 /* "long double" or __float80 is "e". */
29131 /* For 32-bit code we can save PIC register setup by using
29132 __stack_chk_fail_local hidden function instead of calling
29133 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
29134 register, so it is better to call __stack_chk_fail directly. */
29137 ix86_stack_protect_fail (void)
29139 return TARGET_64BIT
29140 ? default_external_stack_protect_fail ()
29141 : default_hidden_stack_protect_fail ();
29144 /* Select a format to encode pointers in exception handling data. CODE
29145 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
29146 true if the symbol may be affected by dynamic relocations.
29148 ??? All x86 object file formats are capable of representing this.
29149 After all, the relocation needed is the same as for the call insn.
29150 Whether or not a particular assembler allows us to enter such, I
29151 guess we'll have to see. */
29153 asm_preferred_eh_data_format (int code, int global)
29157 int type = DW_EH_PE_sdata8;
29159 || ix86_cmodel == CM_SMALL_PIC
29160 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
29161 type = DW_EH_PE_sdata4;
29162 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
29164 if (ix86_cmodel == CM_SMALL
29165 || (ix86_cmodel == CM_MEDIUM && code))
29166 return DW_EH_PE_udata4;
29167 return DW_EH_PE_absptr;
29170 /* Expand copysign from SIGN to the positive value ABS_VALUE
29171 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
29174 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
29176 enum machine_mode mode = GET_MODE (sign);
29177 rtx sgn = gen_reg_rtx (mode);
29178 if (mask == NULL_RTX)
29180 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
29181 if (!VECTOR_MODE_P (mode))
29183 /* We need to generate a scalar mode mask in this case. */
29184 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29185 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29186 mask = gen_reg_rtx (mode);
29187 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29191 mask = gen_rtx_NOT (mode, mask);
29192 emit_insn (gen_rtx_SET (VOIDmode, sgn,
29193 gen_rtx_AND (mode, mask, sign)));
29194 emit_insn (gen_rtx_SET (VOIDmode, result,
29195 gen_rtx_IOR (mode, abs_value, sgn)));
29198 /* Expand fabs (OP0) and return a new rtx that holds the result. The
29199 mask for masking out the sign-bit is stored in *SMASK, if that is
29202 ix86_expand_sse_fabs (rtx op0, rtx *smask)
29204 enum machine_mode mode = GET_MODE (op0);
29207 xa = gen_reg_rtx (mode);
29208 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
29209 if (!VECTOR_MODE_P (mode))
29211 /* We need to generate a scalar mode mask in this case. */
29212 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29213 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29214 mask = gen_reg_rtx (mode);
29215 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29217 emit_insn (gen_rtx_SET (VOIDmode, xa,
29218 gen_rtx_AND (mode, op0, mask)));
29226 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
29227 swapping the operands if SWAP_OPERANDS is true. The expanded
29228 code is a forward jump to a newly created label in case the
29229 comparison is true. The generated label rtx is returned. */
29231 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
29232 bool swap_operands)
29243 label = gen_label_rtx ();
29244 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
29245 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29246 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
29247 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
29248 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
29249 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
29250 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
29251 JUMP_LABEL (tmp) = label;
29256 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
29257 using comparison code CODE. Operands are swapped for the comparison if
29258 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
29260 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
29261 bool swap_operands)
29263 enum machine_mode mode = GET_MODE (op0);
29264 rtx mask = gen_reg_rtx (mode);
29273 if (mode == DFmode)
29274 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
29275 gen_rtx_fmt_ee (code, mode, op0, op1)));
29277 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
29278 gen_rtx_fmt_ee (code, mode, op0, op1)));
29283 /* Generate and return a rtx of mode MODE for 2**n where n is the number
29284 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
29286 ix86_gen_TWO52 (enum machine_mode mode)
29288 REAL_VALUE_TYPE TWO52r;
29291 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
29292 TWO52 = const_double_from_real_value (TWO52r, mode);
29293 TWO52 = force_reg (mode, TWO52);
29298 /* Expand SSE sequence for computing lround from OP1 storing
29301 ix86_expand_lround (rtx op0, rtx op1)
29303 /* C code for the stuff we're doing below:
29304 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
29307 enum machine_mode mode = GET_MODE (op1);
29308 const struct real_format *fmt;
29309 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29312 /* load nextafter (0.5, 0.0) */
29313 fmt = REAL_MODE_FORMAT (mode);
29314 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29315 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29317 /* adj = copysign (0.5, op1) */
29318 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
29319 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29321 /* adj = op1 + adj */
29322 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29324 /* op0 = (imode)adj */
29325 expand_fix (op0, adj, 0);
29328 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29331 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29333 /* C code for the stuff we're doing below (for do_floor):
29335 xi -= (double)xi > op1 ? 1 : 0;
29338 enum machine_mode fmode = GET_MODE (op1);
29339 enum machine_mode imode = GET_MODE (op0);
29340 rtx ireg, freg, label, tmp;
29342 /* reg = (long)op1 */
29343 ireg = gen_reg_rtx (imode);
29344 expand_fix (ireg, op1, 0);
29346 /* freg = (double)reg */
29347 freg = gen_reg_rtx (fmode);
29348 expand_float (freg, ireg, 0);
29350 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29351 label = ix86_expand_sse_compare_and_jump (UNLE,
29352 freg, op1, !do_floor);
29353 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29354 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29355 emit_move_insn (ireg, tmp);
29357 emit_label (label);
29358 LABEL_NUSES (label) = 1;
29360 emit_move_insn (op0, ireg);
29363 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29364 result in OPERAND0. */
29366 ix86_expand_rint (rtx operand0, rtx operand1)
29368 /* C code for the stuff we're doing below:
29369 xa = fabs (operand1);
29370 if (!isless (xa, 2**52))
29372 xa = xa + 2**52 - 2**52;
29373 return copysign (xa, operand1);
29375 enum machine_mode mode = GET_MODE (operand0);
29376 rtx res, xa, label, TWO52, mask;
29378 res = gen_reg_rtx (mode);
29379 emit_move_insn (res, operand1);
29381 /* xa = abs (operand1) */
29382 xa = ix86_expand_sse_fabs (res, &mask);
29384 /* if (!isless (xa, TWO52)) goto label; */
29385 TWO52 = ix86_gen_TWO52 (mode);
29386 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29388 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29389 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29391 ix86_sse_copysign_to_positive (res, xa, res, mask);
29393 emit_label (label);
29394 LABEL_NUSES (label) = 1;
29396 emit_move_insn (operand0, res);
29399 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29402 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29404 /* C code for the stuff we expand below.
29405 double xa = fabs (x), x2;
29406 if (!isless (xa, TWO52))
29408 xa = xa + TWO52 - TWO52;
29409 x2 = copysign (xa, x);
29418 enum machine_mode mode = GET_MODE (operand0);
29419 rtx xa, TWO52, tmp, label, one, res, mask;
29421 TWO52 = ix86_gen_TWO52 (mode);
29423 /* Temporary for holding the result, initialized to the input
29424 operand to ease control flow. */
29425 res = gen_reg_rtx (mode);
29426 emit_move_insn (res, operand1);
29428 /* xa = abs (operand1) */
29429 xa = ix86_expand_sse_fabs (res, &mask);
29431 /* if (!isless (xa, TWO52)) goto label; */
29432 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29434 /* xa = xa + TWO52 - TWO52; */
29435 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29436 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29438 /* xa = copysign (xa, operand1) */
29439 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29441 /* generate 1.0 or -1.0 */
29442 one = force_reg (mode,
29443 const_double_from_real_value (do_floor
29444 ? dconst1 : dconstm1, mode));
29446 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29447 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29448 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29449 gen_rtx_AND (mode, one, tmp)));
29450 /* We always need to subtract here to preserve signed zero. */
29451 tmp = expand_simple_binop (mode, MINUS,
29452 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29453 emit_move_insn (res, tmp);
29455 emit_label (label);
29456 LABEL_NUSES (label) = 1;
29458 emit_move_insn (operand0, res);
29461 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29464 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29466 /* C code for the stuff we expand below.
29467 double xa = fabs (x), x2;
29468 if (!isless (xa, TWO52))
29470 x2 = (double)(long)x;
29477 if (HONOR_SIGNED_ZEROS (mode))
29478 return copysign (x2, x);
29481 enum machine_mode mode = GET_MODE (operand0);
29482 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29484 TWO52 = ix86_gen_TWO52 (mode);
29486 /* Temporary for holding the result, initialized to the input
29487 operand to ease control flow. */
29488 res = gen_reg_rtx (mode);
29489 emit_move_insn (res, operand1);
29491 /* xa = abs (operand1) */
29492 xa = ix86_expand_sse_fabs (res, &mask);
29494 /* if (!isless (xa, TWO52)) goto label; */
29495 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29497 /* xa = (double)(long)x */
29498 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29499 expand_fix (xi, res, 0);
29500 expand_float (xa, xi, 0);
29503 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29505 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29506 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29507 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29508 gen_rtx_AND (mode, one, tmp)));
29509 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29510 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29511 emit_move_insn (res, tmp);
29513 if (HONOR_SIGNED_ZEROS (mode))
29514 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29516 emit_label (label);
29517 LABEL_NUSES (label) = 1;
29519 emit_move_insn (operand0, res);
29522 /* Expand SSE sequence for computing round from OPERAND1 storing
29523 into OPERAND0. Sequence that works without relying on DImode truncation
29524 via cvttsd2siq that is only available on 64bit targets. */
29526 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29528 /* C code for the stuff we expand below.
29529 double xa = fabs (x), xa2, x2;
29530 if (!isless (xa, TWO52))
29532 Using the absolute value and copying back sign makes
29533 -0.0 -> -0.0 correct.
29534 xa2 = xa + TWO52 - TWO52;
29539 else if (dxa > 0.5)
29541 x2 = copysign (xa2, x);
29544 enum machine_mode mode = GET_MODE (operand0);
29545 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29547 TWO52 = ix86_gen_TWO52 (mode);
29549 /* Temporary for holding the result, initialized to the input
29550 operand to ease control flow. */
29551 res = gen_reg_rtx (mode);
29552 emit_move_insn (res, operand1);
29554 /* xa = abs (operand1) */
29555 xa = ix86_expand_sse_fabs (res, &mask);
29557 /* if (!isless (xa, TWO52)) goto label; */
29558 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29560 /* xa2 = xa + TWO52 - TWO52; */
29561 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29562 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29564 /* dxa = xa2 - xa; */
29565 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29567 /* generate 0.5, 1.0 and -0.5 */
29568 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29569 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29570 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29574 tmp = gen_reg_rtx (mode);
29575 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29576 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29577 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29578 gen_rtx_AND (mode, one, tmp)));
29579 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29580 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29581 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29582 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29583 gen_rtx_AND (mode, one, tmp)));
29584 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29586 /* res = copysign (xa2, operand1) */
29587 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29589 emit_label (label);
29590 LABEL_NUSES (label) = 1;
29592 emit_move_insn (operand0, res);
29595 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29598 ix86_expand_trunc (rtx operand0, rtx operand1)
29600 /* C code for SSE variant we expand below.
29601 double xa = fabs (x), x2;
29602 if (!isless (xa, TWO52))
29604 x2 = (double)(long)x;
29605 if (HONOR_SIGNED_ZEROS (mode))
29606 return copysign (x2, x);
29609 enum machine_mode mode = GET_MODE (operand0);
29610 rtx xa, xi, TWO52, label, res, mask;
29612 TWO52 = ix86_gen_TWO52 (mode);
29614 /* Temporary for holding the result, initialized to the input
29615 operand to ease control flow. */
29616 res = gen_reg_rtx (mode);
29617 emit_move_insn (res, operand1);
29619 /* xa = abs (operand1) */
29620 xa = ix86_expand_sse_fabs (res, &mask);
29622 /* if (!isless (xa, TWO52)) goto label; */
29623 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29625 /* x = (double)(long)x */
29626 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29627 expand_fix (xi, res, 0);
29628 expand_float (res, xi, 0);
29630 if (HONOR_SIGNED_ZEROS (mode))
29631 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29633 emit_label (label);
29634 LABEL_NUSES (label) = 1;
29636 emit_move_insn (operand0, res);
29639 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29642 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29644 enum machine_mode mode = GET_MODE (operand0);
29645 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29647 /* C code for SSE variant we expand below.
29648 double xa = fabs (x), x2;
29649 if (!isless (xa, TWO52))
29651 xa2 = xa + TWO52 - TWO52;
29655 x2 = copysign (xa2, x);
29659 TWO52 = ix86_gen_TWO52 (mode);
29661 /* Temporary for holding the result, initialized to the input
29662 operand to ease control flow. */
29663 res = gen_reg_rtx (mode);
29664 emit_move_insn (res, operand1);
29666 /* xa = abs (operand1) */
29667 xa = ix86_expand_sse_fabs (res, &smask);
29669 /* if (!isless (xa, TWO52)) goto label; */
29670 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29672 /* res = xa + TWO52 - TWO52; */
29673 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29674 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29675 emit_move_insn (res, tmp);
29678 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29680 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29681 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29682 emit_insn (gen_rtx_SET (VOIDmode, mask,
29683 gen_rtx_AND (mode, mask, one)));
29684 tmp = expand_simple_binop (mode, MINUS,
29685 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29686 emit_move_insn (res, tmp);
29688 /* res = copysign (res, operand1) */
29689 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29691 emit_label (label);
29692 LABEL_NUSES (label) = 1;
29694 emit_move_insn (operand0, res);
29697 /* Expand SSE sequence for computing round from OPERAND1 storing
29700 ix86_expand_round (rtx operand0, rtx operand1)
29702 /* C code for the stuff we're doing below:
29703 double xa = fabs (x);
29704 if (!isless (xa, TWO52))
29706 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29707 return copysign (xa, x);
29709 enum machine_mode mode = GET_MODE (operand0);
29710 rtx res, TWO52, xa, label, xi, half, mask;
29711 const struct real_format *fmt;
29712 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29714 /* Temporary for holding the result, initialized to the input
29715 operand to ease control flow. */
29716 res = gen_reg_rtx (mode);
29717 emit_move_insn (res, operand1);
29719 TWO52 = ix86_gen_TWO52 (mode);
29720 xa = ix86_expand_sse_fabs (res, &mask);
29721 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29723 /* load nextafter (0.5, 0.0) */
29724 fmt = REAL_MODE_FORMAT (mode);
29725 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29726 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29728 /* xa = xa + 0.5 */
29729 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29730 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29732 /* xa = (double)(int64_t)xa */
29733 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29734 expand_fix (xi, xa, 0);
29735 expand_float (xa, xi, 0);
29737 /* res = copysign (xa, operand1) */
29738 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29740 emit_label (label);
29741 LABEL_NUSES (label) = 1;
29743 emit_move_insn (operand0, res);
29747 /* Validate whether a SSE5 instruction is valid or not.
29748 OPERANDS is the array of operands.
29749 NUM is the number of operands.
29750 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29751 NUM_MEMORY is the maximum number of memory operands to accept.
29752 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29755 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29756 bool uses_oc0, int num_memory, bool commutative)
29762 /* Count the number of memory arguments */
29765 for (i = 0; i < num; i++)
29767 enum machine_mode mode = GET_MODE (operands[i]);
29768 if (register_operand (operands[i], mode))
29771 else if (memory_operand (operands[i], mode))
29773 mem_mask |= (1 << i);
29779 rtx pattern = PATTERN (insn);
29781 /* allow 0 for pcmov */
29782 if (GET_CODE (pattern) != SET
29783 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29785 || operands[i] != CONST0_RTX (mode))
29790 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29791 a memory operation. */
29792 if (num_memory < 0)
29794 num_memory = -num_memory;
29795 if ((mem_mask & (1 << (num-1))) != 0)
29797 mem_mask &= ~(1 << (num-1));
29802 /* If there were no memory operations, allow the insn */
29806 /* Do not allow the destination register to be a memory operand. */
29807 else if (mem_mask & (1 << 0))
29810 /* If there are too many memory operations, disallow the instruction. While
29811 the hardware only allows 1 memory reference, before register allocation
29812 for some insns, we allow two memory operations sometimes in order to allow
29813 code like the following to be optimized:
29815 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29817 or similar cases that are vectorized into using the fmaddss
29819 else if (mem_count > num_memory)
29822 /* Don't allow more than one memory operation if not optimizing. */
29823 else if (mem_count > 1 && !optimize)
29826 else if (num == 4 && mem_count == 1)
29828 /* formats (destination is the first argument), example fmaddss:
29829 xmm1, xmm1, xmm2, xmm3/mem
29830 xmm1, xmm1, xmm2/mem, xmm3
29831 xmm1, xmm2, xmm3/mem, xmm1
29832 xmm1, xmm2/mem, xmm3, xmm1 */
29834 return ((mem_mask == (1 << 1))
29835 || (mem_mask == (1 << 2))
29836 || (mem_mask == (1 << 3)));
29838 /* format, example pmacsdd:
29839 xmm1, xmm2, xmm3/mem, xmm1 */
29841 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29843 return (mem_mask == (1 << 2));
29846 else if (num == 4 && num_memory == 2)
29848 /* If there are two memory operations, we can load one of the memory ops
29849 into the destination register. This is for optimizing the
29850 multiply/add ops, which the combiner has optimized both the multiply
29851 and the add insns to have a memory operation. We have to be careful
29852 that the destination doesn't overlap with the inputs. */
29853 rtx op0 = operands[0];
29855 if (reg_mentioned_p (op0, operands[1])
29856 || reg_mentioned_p (op0, operands[2])
29857 || reg_mentioned_p (op0, operands[3]))
29860 /* formats (destination is the first argument), example fmaddss:
29861 xmm1, xmm1, xmm2, xmm3/mem
29862 xmm1, xmm1, xmm2/mem, xmm3
29863 xmm1, xmm2, xmm3/mem, xmm1
29864 xmm1, xmm2/mem, xmm3, xmm1
29866 For the oc0 case, we will load either operands[1] or operands[3] into
29867 operands[0], so any combination of 2 memory operands is ok. */
29871 /* format, example pmacsdd:
29872 xmm1, xmm2, xmm3/mem, xmm1
29874 For the integer multiply/add instructions be more restrictive and
29875 require operands[2] and operands[3] to be the memory operands. */
29877 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29879 return (mem_mask == ((1 << 2) | (1 << 3)));
29882 else if (num == 3 && num_memory == 1)
29884 /* formats, example protb:
29885 xmm1, xmm2, xmm3/mem
29886 xmm1, xmm2/mem, xmm3 */
29888 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29890 /* format, example comeq:
29891 xmm1, xmm2, xmm3/mem */
29893 return (mem_mask == (1 << 2));
29897 gcc_unreachable ();
29903 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29904 hardware will allow by using the destination register to load one of the
29905 memory operations. Presently this is used by the multiply/add routines to
29906 allow 2 memory references. */
29909 ix86_expand_sse5_multiple_memory (rtx operands[],
29911 enum machine_mode mode)
29913 rtx op0 = operands[0];
29915 || memory_operand (op0, mode)
29916 || reg_mentioned_p (op0, operands[1])
29917 || reg_mentioned_p (op0, operands[2])
29918 || reg_mentioned_p (op0, operands[3]))
29919 gcc_unreachable ();
29921 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29922 the destination register. */
29923 if (memory_operand (operands[1], mode))
29925 emit_move_insn (op0, operands[1]);
29928 else if (memory_operand (operands[3], mode))
29930 emit_move_insn (op0, operands[3]);
29934 gcc_unreachable ();
29940 /* Table of valid machine attributes. */
29941 static const struct attribute_spec ix86_attribute_table[] =
29943 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29944 /* Stdcall attribute says callee is responsible for popping arguments
29945 if they are not variable. */
29946 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29947 /* Fastcall attribute says callee is responsible for popping arguments
29948 if they are not variable. */
29949 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29950 /* Cdecl attribute says the callee is a normal C declaration */
29951 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29952 /* Regparm attribute specifies how many integer arguments are to be
29953 passed in registers. */
29954 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29955 /* Sseregparm attribute says we are using x86_64 calling conventions
29956 for FP arguments. */
29957 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29958 /* force_align_arg_pointer says this function realigns the stack at entry. */
29959 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29960 false, true, true, ix86_handle_cconv_attribute },
29961 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29962 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29963 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29964 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29966 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29967 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29968 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29969 SUBTARGET_ATTRIBUTE_TABLE,
29971 /* ms_abi and sysv_abi calling convention function attributes. */
29972 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29973 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29975 { NULL, 0, 0, false, false, false, NULL }
29978 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29980 x86_builtin_vectorization_cost (bool runtime_test)
29982 /* If the branch of the runtime test is taken - i.e. - the vectorized
29983 version is skipped - this incurs a misprediction cost (because the
29984 vectorized version is expected to be the fall-through). So we subtract
29985 the latency of a mispredicted branch from the costs that are incured
29986 when the vectorized version is executed.
29988 TODO: The values in individual target tables have to be tuned or new
29989 fields may be needed. For eg. on K8, the default branch path is the
29990 not-taken path. If the taken path is predicted correctly, the minimum
29991 penalty of going down the taken-path is 1 cycle. If the taken-path is
29992 not predicted correctly, then the minimum penalty is 10 cycles. */
29996 return (-(ix86_cost->cond_taken_branch_cost));
30002 /* This function returns the calling abi specific va_list type node.
30003 It returns the FNDECL specific va_list type. */
30006 ix86_fn_abi_va_list (tree fndecl)
30009 return va_list_type_node;
30010 gcc_assert (fndecl != NULL_TREE);
30012 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
30013 return ms_va_list_type_node;
30015 return sysv_va_list_type_node;
30018 /* Returns the canonical va_list type specified by TYPE. If there
30019 is no valid TYPE provided, it return NULL_TREE. */
30022 ix86_canonical_va_list_type (tree type)
30026 /* Resolve references and pointers to va_list type. */
30027 if (INDIRECT_REF_P (type))
30028 type = TREE_TYPE (type);
30029 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
30030 type = TREE_TYPE (type);
30034 wtype = va_list_type_node;
30035 gcc_assert (wtype != NULL_TREE);
30037 if (TREE_CODE (wtype) == ARRAY_TYPE)
30039 /* If va_list is an array type, the argument may have decayed
30040 to a pointer type, e.g. by being passed to another function.
30041 In that case, unwrap both types so that we can compare the
30042 underlying records. */
30043 if (TREE_CODE (htype) == ARRAY_TYPE
30044 || POINTER_TYPE_P (htype))
30046 wtype = TREE_TYPE (wtype);
30047 htype = TREE_TYPE (htype);
30050 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30051 return va_list_type_node;
30052 wtype = sysv_va_list_type_node;
30053 gcc_assert (wtype != NULL_TREE);
30055 if (TREE_CODE (wtype) == ARRAY_TYPE)
30057 /* If va_list is an array type, the argument may have decayed
30058 to a pointer type, e.g. by being passed to another function.
30059 In that case, unwrap both types so that we can compare the
30060 underlying records. */
30061 if (TREE_CODE (htype) == ARRAY_TYPE
30062 || POINTER_TYPE_P (htype))
30064 wtype = TREE_TYPE (wtype);
30065 htype = TREE_TYPE (htype);
30068 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30069 return sysv_va_list_type_node;
30070 wtype = ms_va_list_type_node;
30071 gcc_assert (wtype != NULL_TREE);
30073 if (TREE_CODE (wtype) == ARRAY_TYPE)
30075 /* If va_list is an array type, the argument may have decayed
30076 to a pointer type, e.g. by being passed to another function.
30077 In that case, unwrap both types so that we can compare the
30078 underlying records. */
30079 if (TREE_CODE (htype) == ARRAY_TYPE
30080 || POINTER_TYPE_P (htype))
30082 wtype = TREE_TYPE (wtype);
30083 htype = TREE_TYPE (htype);
30086 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30087 return ms_va_list_type_node;
30090 return std_canonical_va_list_type (type);
30093 /* Iterate through the target-specific builtin types for va_list.
30094 IDX denotes the iterator, *PTREE is set to the result type of
30095 the va_list builtin, and *PNAME to its internal type.
30096 Returns zero if there is no element for this index, otherwise
30097 IDX should be increased upon the next call.
30098 Note, do not iterate a base builtin's name like __builtin_va_list.
30099 Used from c_common_nodes_and_builtins. */
30102 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
30108 *ptree = ms_va_list_type_node;
30109 *pname = "__builtin_ms_va_list";
30112 *ptree = sysv_va_list_type_node;
30113 *pname = "__builtin_sysv_va_list";
30121 /* Initialize the GCC target structure. */
30122 #undef TARGET_RETURN_IN_MEMORY
30123 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30125 #undef TARGET_LEGITIMIZE_ADDRESS
30126 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30128 #undef TARGET_ATTRIBUTE_TABLE
30129 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30130 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30131 # undef TARGET_MERGE_DECL_ATTRIBUTES
30132 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30135 #undef TARGET_COMP_TYPE_ATTRIBUTES
30136 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30138 #undef TARGET_INIT_BUILTINS
30139 #define TARGET_INIT_BUILTINS ix86_init_builtins
30140 #undef TARGET_EXPAND_BUILTIN
30141 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30143 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30144 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30145 ix86_builtin_vectorized_function
30147 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30148 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30150 #undef TARGET_BUILTIN_RECIPROCAL
30151 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30153 #undef TARGET_ASM_FUNCTION_EPILOGUE
30154 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30156 #undef TARGET_ENCODE_SECTION_INFO
30157 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30158 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30160 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30163 #undef TARGET_ASM_OPEN_PAREN
30164 #define TARGET_ASM_OPEN_PAREN ""
30165 #undef TARGET_ASM_CLOSE_PAREN
30166 #define TARGET_ASM_CLOSE_PAREN ""
30168 #undef TARGET_ASM_ALIGNED_HI_OP
30169 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30170 #undef TARGET_ASM_ALIGNED_SI_OP
30171 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30173 #undef TARGET_ASM_ALIGNED_DI_OP
30174 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30177 #undef TARGET_ASM_UNALIGNED_HI_OP
30178 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30179 #undef TARGET_ASM_UNALIGNED_SI_OP
30180 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30181 #undef TARGET_ASM_UNALIGNED_DI_OP
30182 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30184 #undef TARGET_SCHED_ADJUST_COST
30185 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30186 #undef TARGET_SCHED_ISSUE_RATE
30187 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30188 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30189 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30190 ia32_multipass_dfa_lookahead
30192 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30193 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30196 #undef TARGET_HAVE_TLS
30197 #define TARGET_HAVE_TLS true
30199 #undef TARGET_CANNOT_FORCE_CONST_MEM
30200 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30201 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30202 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30204 #undef TARGET_DELEGITIMIZE_ADDRESS
30205 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30207 #undef TARGET_MS_BITFIELD_LAYOUT_P
30208 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30211 #undef TARGET_BINDS_LOCAL_P
30212 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30214 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30215 #undef TARGET_BINDS_LOCAL_P
30216 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30219 #undef TARGET_ASM_OUTPUT_MI_THUNK
30220 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30221 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30222 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30224 #undef TARGET_ASM_FILE_START
30225 #define TARGET_ASM_FILE_START x86_file_start
30227 #undef TARGET_DEFAULT_TARGET_FLAGS
30228 #define TARGET_DEFAULT_TARGET_FLAGS \
30230 | TARGET_SUBTARGET_DEFAULT \
30231 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
30233 #undef TARGET_HANDLE_OPTION
30234 #define TARGET_HANDLE_OPTION ix86_handle_option
30236 #undef TARGET_RTX_COSTS
30237 #define TARGET_RTX_COSTS ix86_rtx_costs
30238 #undef TARGET_ADDRESS_COST
30239 #define TARGET_ADDRESS_COST ix86_address_cost
30241 #undef TARGET_FIXED_CONDITION_CODE_REGS
30242 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30243 #undef TARGET_CC_MODES_COMPATIBLE
30244 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30246 #undef TARGET_MACHINE_DEPENDENT_REORG
30247 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30249 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30250 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30252 #undef TARGET_BUILD_BUILTIN_VA_LIST
30253 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30255 #undef TARGET_FN_ABI_VA_LIST
30256 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30258 #undef TARGET_CANONICAL_VA_LIST_TYPE
30259 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30261 #undef TARGET_EXPAND_BUILTIN_VA_START
30262 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30264 #undef TARGET_MD_ASM_CLOBBERS
30265 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30267 #undef TARGET_PROMOTE_PROTOTYPES
30268 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30269 #undef TARGET_STRUCT_VALUE_RTX
30270 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30271 #undef TARGET_SETUP_INCOMING_VARARGS
30272 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30273 #undef TARGET_MUST_PASS_IN_STACK
30274 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30275 #undef TARGET_PASS_BY_REFERENCE
30276 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30277 #undef TARGET_INTERNAL_ARG_POINTER
30278 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30279 #undef TARGET_UPDATE_STACK_BOUNDARY
30280 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30281 #undef TARGET_GET_DRAP_RTX
30282 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30283 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
30284 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
30285 #undef TARGET_STRICT_ARGUMENT_NAMING
30286 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30288 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30289 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30291 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30292 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30294 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30295 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30297 #undef TARGET_C_MODE_FOR_SUFFIX
30298 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30301 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30302 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30305 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30306 #undef TARGET_INSERT_ATTRIBUTES
30307 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30310 #undef TARGET_MANGLE_TYPE
30311 #define TARGET_MANGLE_TYPE ix86_mangle_type
30313 #undef TARGET_STACK_PROTECT_FAIL
30314 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30316 #undef TARGET_FUNCTION_VALUE
30317 #define TARGET_FUNCTION_VALUE ix86_function_value
30319 #undef TARGET_SECONDARY_RELOAD
30320 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30322 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30323 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30325 #undef TARGET_SET_CURRENT_FUNCTION
30326 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30328 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30329 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30331 #undef TARGET_OPTION_SAVE
30332 #define TARGET_OPTION_SAVE ix86_function_specific_save
30334 #undef TARGET_OPTION_RESTORE
30335 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30337 #undef TARGET_OPTION_PRINT
30338 #define TARGET_OPTION_PRINT ix86_function_specific_print
30340 #undef TARGET_OPTION_CAN_INLINE_P
30341 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
30343 #undef TARGET_EXPAND_TO_RTL_HOOK
30344 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30346 #undef TARGET_LEGITIMATE_ADDRESS_P
30347 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30349 struct gcc_target targetm = TARGET_INITIALIZER;
30351 #include "gt-i386.h"
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