1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #include "tm-constrs.h"
54 #ifndef CHECK_STACK_LIMIT
55 #define CHECK_STACK_LIMIT (-1)
58 /* Return index of given mode in mult and division cost tables. */
59 #define MODE_INDEX(mode) \
60 ((mode) == QImode ? 0 \
61 : (mode) == HImode ? 1 \
62 : (mode) == SImode ? 2 \
63 : (mode) == DImode ? 3 \
66 /* Processor costs (relative to an add) */
67 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
68 #define COSTS_N_BYTES(N) ((N) * 2)
71 struct processor_costs size_cost = { /* costs for tunning for size */
72 COSTS_N_BYTES (2), /* cost of an add instruction */
73 COSTS_N_BYTES (3), /* cost of a lea instruction */
74 COSTS_N_BYTES (2), /* variable shift costs */
75 COSTS_N_BYTES (3), /* constant shift costs */
76 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
77 COSTS_N_BYTES (3), /* HI */
78 COSTS_N_BYTES (3), /* SI */
79 COSTS_N_BYTES (3), /* DI */
80 COSTS_N_BYTES (5)}, /* other */
81 0, /* cost of multiply per each bit set */
82 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
83 COSTS_N_BYTES (3), /* HI */
84 COSTS_N_BYTES (3), /* SI */
85 COSTS_N_BYTES (3), /* DI */
86 COSTS_N_BYTES (5)}, /* other */
87 COSTS_N_BYTES (3), /* cost of movsx */
88 COSTS_N_BYTES (3), /* cost of movzx */
91 2, /* cost for loading QImode using movzbl */
92 {2, 2, 2}, /* cost of loading integer registers
93 in QImode, HImode and SImode.
94 Relative to reg-reg move (2). */
95 {2, 2, 2}, /* cost of storing integer registers */
96 2, /* cost of reg,reg fld/fst */
97 {2, 2, 2}, /* cost of loading fp registers
98 in SFmode, DFmode and XFmode */
99 {2, 2, 2}, /* cost of storing fp registers
100 in SFmode, DFmode and XFmode */
101 3, /* cost of moving MMX register */
102 {3, 3}, /* cost of loading MMX registers
103 in SImode and DImode */
104 {3, 3}, /* cost of storing MMX registers
105 in SImode and DImode */
106 3, /* cost of moving SSE register */
107 {3, 3, 3}, /* cost of loading SSE registers
108 in SImode, DImode and TImode */
109 {3, 3, 3}, /* cost of storing SSE registers
110 in SImode, DImode and TImode */
111 3, /* MMX or SSE register to integer */
112 0, /* size of prefetch block */
113 0, /* number of parallel prefetches */
115 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
116 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
117 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
118 COSTS_N_BYTES (2), /* cost of FABS instruction. */
119 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
120 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
123 /* Processor costs (relative to an add) */
125 struct processor_costs i386_cost = { /* 386 specific costs */
126 COSTS_N_INSNS (1), /* cost of an add instruction */
127 COSTS_N_INSNS (1), /* cost of a lea instruction */
128 COSTS_N_INSNS (3), /* variable shift costs */
129 COSTS_N_INSNS (2), /* constant shift costs */
130 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
131 COSTS_N_INSNS (6), /* HI */
132 COSTS_N_INSNS (6), /* SI */
133 COSTS_N_INSNS (6), /* DI */
134 COSTS_N_INSNS (6)}, /* other */
135 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
136 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
137 COSTS_N_INSNS (23), /* HI */
138 COSTS_N_INSNS (23), /* SI */
139 COSTS_N_INSNS (23), /* DI */
140 COSTS_N_INSNS (23)}, /* other */
141 COSTS_N_INSNS (3), /* cost of movsx */
142 COSTS_N_INSNS (2), /* cost of movzx */
143 15, /* "large" insn */
145 4, /* cost for loading QImode using movzbl */
146 {2, 4, 2}, /* cost of loading integer registers
147 in QImode, HImode and SImode.
148 Relative to reg-reg move (2). */
149 {2, 4, 2}, /* cost of storing integer registers */
150 2, /* cost of reg,reg fld/fst */
151 {8, 8, 8}, /* cost of loading fp registers
152 in SFmode, DFmode and XFmode */
153 {8, 8, 8}, /* cost of storing fp registers
154 in SFmode, DFmode and XFmode */
155 2, /* cost of moving MMX register */
156 {4, 8}, /* cost of loading MMX registers
157 in SImode and DImode */
158 {4, 8}, /* cost of storing MMX registers
159 in SImode and DImode */
160 2, /* cost of moving SSE register */
161 {4, 8, 16}, /* cost of loading SSE registers
162 in SImode, DImode and TImode */
163 {4, 8, 16}, /* cost of storing SSE registers
164 in SImode, DImode and TImode */
165 3, /* MMX or SSE register to integer */
166 0, /* size of prefetch block */
167 0, /* number of parallel prefetches */
169 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
170 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
171 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
172 COSTS_N_INSNS (22), /* cost of FABS instruction. */
173 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
174 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
178 struct processor_costs i486_cost = { /* 486 specific costs */
179 COSTS_N_INSNS (1), /* cost of an add instruction */
180 COSTS_N_INSNS (1), /* cost of a lea instruction */
181 COSTS_N_INSNS (3), /* variable shift costs */
182 COSTS_N_INSNS (2), /* constant shift costs */
183 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
184 COSTS_N_INSNS (12), /* HI */
185 COSTS_N_INSNS (12), /* SI */
186 COSTS_N_INSNS (12), /* DI */
187 COSTS_N_INSNS (12)}, /* other */
188 1, /* cost of multiply per each bit set */
189 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
190 COSTS_N_INSNS (40), /* HI */
191 COSTS_N_INSNS (40), /* SI */
192 COSTS_N_INSNS (40), /* DI */
193 COSTS_N_INSNS (40)}, /* other */
194 COSTS_N_INSNS (3), /* cost of movsx */
195 COSTS_N_INSNS (2), /* cost of movzx */
196 15, /* "large" insn */
198 4, /* cost for loading QImode using movzbl */
199 {2, 4, 2}, /* cost of loading integer registers
200 in QImode, HImode and SImode.
201 Relative to reg-reg move (2). */
202 {2, 4, 2}, /* cost of storing integer registers */
203 2, /* cost of reg,reg fld/fst */
204 {8, 8, 8}, /* cost of loading fp registers
205 in SFmode, DFmode and XFmode */
206 {8, 8, 8}, /* cost of storing fp registers
207 in SFmode, DFmode and XFmode */
208 2, /* cost of moving MMX register */
209 {4, 8}, /* cost of loading MMX registers
210 in SImode and DImode */
211 {4, 8}, /* cost of storing MMX registers
212 in SImode and DImode */
213 2, /* cost of moving SSE register */
214 {4, 8, 16}, /* cost of loading SSE registers
215 in SImode, DImode and TImode */
216 {4, 8, 16}, /* cost of storing SSE registers
217 in SImode, DImode and TImode */
218 3, /* MMX or SSE register to integer */
219 0, /* size of prefetch block */
220 0, /* number of parallel prefetches */
222 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
223 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
224 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
225 COSTS_N_INSNS (3), /* cost of FABS instruction. */
226 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
227 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
231 struct processor_costs pentium_cost = {
232 COSTS_N_INSNS (1), /* cost of an add instruction */
233 COSTS_N_INSNS (1), /* cost of a lea instruction */
234 COSTS_N_INSNS (4), /* variable shift costs */
235 COSTS_N_INSNS (1), /* constant shift costs */
236 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
237 COSTS_N_INSNS (11), /* HI */
238 COSTS_N_INSNS (11), /* SI */
239 COSTS_N_INSNS (11), /* DI */
240 COSTS_N_INSNS (11)}, /* other */
241 0, /* cost of multiply per each bit set */
242 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
243 COSTS_N_INSNS (25), /* HI */
244 COSTS_N_INSNS (25), /* SI */
245 COSTS_N_INSNS (25), /* DI */
246 COSTS_N_INSNS (25)}, /* other */
247 COSTS_N_INSNS (3), /* cost of movsx */
248 COSTS_N_INSNS (2), /* cost of movzx */
249 8, /* "large" insn */
251 6, /* cost for loading QImode using movzbl */
252 {2, 4, 2}, /* cost of loading integer registers
253 in QImode, HImode and SImode.
254 Relative to reg-reg move (2). */
255 {2, 4, 2}, /* cost of storing integer registers */
256 2, /* cost of reg,reg fld/fst */
257 {2, 2, 6}, /* cost of loading fp registers
258 in SFmode, DFmode and XFmode */
259 {4, 4, 6}, /* cost of storing fp registers
260 in SFmode, DFmode and XFmode */
261 8, /* cost of moving MMX register */
262 {8, 8}, /* cost of loading MMX registers
263 in SImode and DImode */
264 {8, 8}, /* cost of storing MMX registers
265 in SImode and DImode */
266 2, /* cost of moving SSE register */
267 {4, 8, 16}, /* cost of loading SSE registers
268 in SImode, DImode and TImode */
269 {4, 8, 16}, /* cost of storing SSE registers
270 in SImode, DImode and TImode */
271 3, /* MMX or SSE register to integer */
272 0, /* size of prefetch block */
273 0, /* number of parallel prefetches */
275 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
276 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
277 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
278 COSTS_N_INSNS (1), /* cost of FABS instruction. */
279 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
280 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
284 struct processor_costs pentiumpro_cost = {
285 COSTS_N_INSNS (1), /* cost of an add instruction */
286 COSTS_N_INSNS (1), /* cost of a lea instruction */
287 COSTS_N_INSNS (1), /* variable shift costs */
288 COSTS_N_INSNS (1), /* constant shift costs */
289 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
290 COSTS_N_INSNS (4), /* HI */
291 COSTS_N_INSNS (4), /* SI */
292 COSTS_N_INSNS (4), /* DI */
293 COSTS_N_INSNS (4)}, /* other */
294 0, /* cost of multiply per each bit set */
295 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
296 COSTS_N_INSNS (17), /* HI */
297 COSTS_N_INSNS (17), /* SI */
298 COSTS_N_INSNS (17), /* DI */
299 COSTS_N_INSNS (17)}, /* other */
300 COSTS_N_INSNS (1), /* cost of movsx */
301 COSTS_N_INSNS (1), /* cost of movzx */
302 8, /* "large" insn */
304 2, /* cost for loading QImode using movzbl */
305 {4, 4, 4}, /* cost of loading integer registers
306 in QImode, HImode and SImode.
307 Relative to reg-reg move (2). */
308 {2, 2, 2}, /* cost of storing integer registers */
309 2, /* cost of reg,reg fld/fst */
310 {2, 2, 6}, /* cost of loading fp registers
311 in SFmode, DFmode and XFmode */
312 {4, 4, 6}, /* cost of storing fp registers
313 in SFmode, DFmode and XFmode */
314 2, /* cost of moving MMX register */
315 {2, 2}, /* cost of loading MMX registers
316 in SImode and DImode */
317 {2, 2}, /* cost of storing MMX registers
318 in SImode and DImode */
319 2, /* cost of moving SSE register */
320 {2, 2, 8}, /* cost of loading SSE registers
321 in SImode, DImode and TImode */
322 {2, 2, 8}, /* cost of storing SSE registers
323 in SImode, DImode and TImode */
324 3, /* MMX or SSE register to integer */
325 32, /* size of prefetch block */
326 6, /* number of parallel prefetches */
328 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
329 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
330 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
331 COSTS_N_INSNS (2), /* cost of FABS instruction. */
332 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
333 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
337 struct processor_costs k6_cost = {
338 COSTS_N_INSNS (1), /* cost of an add instruction */
339 COSTS_N_INSNS (2), /* cost of a lea instruction */
340 COSTS_N_INSNS (1), /* variable shift costs */
341 COSTS_N_INSNS (1), /* constant shift costs */
342 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
343 COSTS_N_INSNS (3), /* HI */
344 COSTS_N_INSNS (3), /* SI */
345 COSTS_N_INSNS (3), /* DI */
346 COSTS_N_INSNS (3)}, /* other */
347 0, /* cost of multiply per each bit set */
348 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
349 COSTS_N_INSNS (18), /* HI */
350 COSTS_N_INSNS (18), /* SI */
351 COSTS_N_INSNS (18), /* DI */
352 COSTS_N_INSNS (18)}, /* other */
353 COSTS_N_INSNS (2), /* cost of movsx */
354 COSTS_N_INSNS (2), /* cost of movzx */
355 8, /* "large" insn */
357 3, /* cost for loading QImode using movzbl */
358 {4, 5, 4}, /* cost of loading integer registers
359 in QImode, HImode and SImode.
360 Relative to reg-reg move (2). */
361 {2, 3, 2}, /* cost of storing integer registers */
362 4, /* cost of reg,reg fld/fst */
363 {6, 6, 6}, /* cost of loading fp registers
364 in SFmode, DFmode and XFmode */
365 {4, 4, 4}, /* cost of storing fp registers
366 in SFmode, DFmode and XFmode */
367 2, /* cost of moving MMX register */
368 {2, 2}, /* cost of loading MMX registers
369 in SImode and DImode */
370 {2, 2}, /* cost of storing MMX registers
371 in SImode and DImode */
372 2, /* cost of moving SSE register */
373 {2, 2, 8}, /* cost of loading SSE registers
374 in SImode, DImode and TImode */
375 {2, 2, 8}, /* cost of storing SSE registers
376 in SImode, DImode and TImode */
377 6, /* MMX or SSE register to integer */
378 32, /* size of prefetch block */
379 1, /* number of parallel prefetches */
381 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
382 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
383 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
384 COSTS_N_INSNS (2), /* cost of FABS instruction. */
385 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
386 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
390 struct processor_costs athlon_cost = {
391 COSTS_N_INSNS (1), /* cost of an add instruction */
392 COSTS_N_INSNS (2), /* cost of a lea instruction */
393 COSTS_N_INSNS (1), /* variable shift costs */
394 COSTS_N_INSNS (1), /* constant shift costs */
395 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
396 COSTS_N_INSNS (5), /* HI */
397 COSTS_N_INSNS (5), /* SI */
398 COSTS_N_INSNS (5), /* DI */
399 COSTS_N_INSNS (5)}, /* other */
400 0, /* cost of multiply per each bit set */
401 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
402 COSTS_N_INSNS (26), /* HI */
403 COSTS_N_INSNS (42), /* SI */
404 COSTS_N_INSNS (74), /* DI */
405 COSTS_N_INSNS (74)}, /* other */
406 COSTS_N_INSNS (1), /* cost of movsx */
407 COSTS_N_INSNS (1), /* cost of movzx */
408 8, /* "large" insn */
410 4, /* cost for loading QImode using movzbl */
411 {3, 4, 3}, /* cost of loading integer registers
412 in QImode, HImode and SImode.
413 Relative to reg-reg move (2). */
414 {3, 4, 3}, /* cost of storing integer registers */
415 4, /* cost of reg,reg fld/fst */
416 {4, 4, 12}, /* cost of loading fp registers
417 in SFmode, DFmode and XFmode */
418 {6, 6, 8}, /* cost of storing fp registers
419 in SFmode, DFmode and XFmode */
420 2, /* cost of moving MMX register */
421 {4, 4}, /* cost of loading MMX registers
422 in SImode and DImode */
423 {4, 4}, /* cost of storing MMX registers
424 in SImode and DImode */
425 2, /* cost of moving SSE register */
426 {4, 4, 6}, /* cost of loading SSE registers
427 in SImode, DImode and TImode */
428 {4, 4, 5}, /* cost of storing SSE registers
429 in SImode, DImode and TImode */
430 5, /* MMX or SSE register to integer */
431 64, /* size of prefetch block */
432 6, /* number of parallel prefetches */
434 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
435 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
436 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
437 COSTS_N_INSNS (2), /* cost of FABS instruction. */
438 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
439 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
443 struct processor_costs k8_cost = {
444 COSTS_N_INSNS (1), /* cost of an add instruction */
445 COSTS_N_INSNS (2), /* cost of a lea instruction */
446 COSTS_N_INSNS (1), /* variable shift costs */
447 COSTS_N_INSNS (1), /* constant shift costs */
448 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
449 COSTS_N_INSNS (4), /* HI */
450 COSTS_N_INSNS (3), /* SI */
451 COSTS_N_INSNS (4), /* DI */
452 COSTS_N_INSNS (5)}, /* other */
453 0, /* cost of multiply per each bit set */
454 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
455 COSTS_N_INSNS (26), /* HI */
456 COSTS_N_INSNS (42), /* SI */
457 COSTS_N_INSNS (74), /* DI */
458 COSTS_N_INSNS (74)}, /* other */
459 COSTS_N_INSNS (1), /* cost of movsx */
460 COSTS_N_INSNS (1), /* cost of movzx */
461 8, /* "large" insn */
463 4, /* cost for loading QImode using movzbl */
464 {3, 4, 3}, /* cost of loading integer registers
465 in QImode, HImode and SImode.
466 Relative to reg-reg move (2). */
467 {3, 4, 3}, /* cost of storing integer registers */
468 4, /* cost of reg,reg fld/fst */
469 {4, 4, 12}, /* cost of loading fp registers
470 in SFmode, DFmode and XFmode */
471 {6, 6, 8}, /* cost of storing fp registers
472 in SFmode, DFmode and XFmode */
473 2, /* cost of moving MMX register */
474 {3, 3}, /* cost of loading MMX registers
475 in SImode and DImode */
476 {4, 4}, /* cost of storing MMX registers
477 in SImode and DImode */
478 2, /* cost of moving SSE register */
479 {4, 3, 6}, /* cost of loading SSE registers
480 in SImode, DImode and TImode */
481 {4, 4, 5}, /* cost of storing SSE registers
482 in SImode, DImode and TImode */
483 5, /* MMX or SSE register to integer */
484 64, /* size of prefetch block */
485 6, /* number of parallel prefetches */
487 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (2), /* cost of FABS instruction. */
491 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
496 struct processor_costs pentium4_cost = {
497 COSTS_N_INSNS (1), /* cost of an add instruction */
498 COSTS_N_INSNS (3), /* cost of a lea instruction */
499 COSTS_N_INSNS (4), /* variable shift costs */
500 COSTS_N_INSNS (4), /* constant shift costs */
501 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
502 COSTS_N_INSNS (15), /* HI */
503 COSTS_N_INSNS (15), /* SI */
504 COSTS_N_INSNS (15), /* DI */
505 COSTS_N_INSNS (15)}, /* other */
506 0, /* cost of multiply per each bit set */
507 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
508 COSTS_N_INSNS (56), /* HI */
509 COSTS_N_INSNS (56), /* SI */
510 COSTS_N_INSNS (56), /* DI */
511 COSTS_N_INSNS (56)}, /* other */
512 COSTS_N_INSNS (1), /* cost of movsx */
513 COSTS_N_INSNS (1), /* cost of movzx */
514 16, /* "large" insn */
516 2, /* cost for loading QImode using movzbl */
517 {4, 5, 4}, /* cost of loading integer registers
518 in QImode, HImode and SImode.
519 Relative to reg-reg move (2). */
520 {2, 3, 2}, /* cost of storing integer registers */
521 2, /* cost of reg,reg fld/fst */
522 {2, 2, 6}, /* cost of loading fp registers
523 in SFmode, DFmode and XFmode */
524 {4, 4, 6}, /* cost of storing fp registers
525 in SFmode, DFmode and XFmode */
526 2, /* cost of moving MMX register */
527 {2, 2}, /* cost of loading MMX registers
528 in SImode and DImode */
529 {2, 2}, /* cost of storing MMX registers
530 in SImode and DImode */
531 12, /* cost of moving SSE register */
532 {12, 12, 12}, /* cost of loading SSE registers
533 in SImode, DImode and TImode */
534 {2, 2, 8}, /* cost of storing SSE registers
535 in SImode, DImode and TImode */
536 10, /* MMX or SSE register to integer */
537 64, /* size of prefetch block */
538 6, /* number of parallel prefetches */
540 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
541 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
542 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
543 COSTS_N_INSNS (2), /* cost of FABS instruction. */
544 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
545 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
549 struct processor_costs nocona_cost = {
550 COSTS_N_INSNS (1), /* cost of an add instruction */
551 COSTS_N_INSNS (1), /* cost of a lea instruction */
552 COSTS_N_INSNS (1), /* variable shift costs */
553 COSTS_N_INSNS (1), /* constant shift costs */
554 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
555 COSTS_N_INSNS (10), /* HI */
556 COSTS_N_INSNS (10), /* SI */
557 COSTS_N_INSNS (10), /* DI */
558 COSTS_N_INSNS (10)}, /* other */
559 0, /* cost of multiply per each bit set */
560 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
561 COSTS_N_INSNS (66), /* HI */
562 COSTS_N_INSNS (66), /* SI */
563 COSTS_N_INSNS (66), /* DI */
564 COSTS_N_INSNS (66)}, /* other */
565 COSTS_N_INSNS (1), /* cost of movsx */
566 COSTS_N_INSNS (1), /* cost of movzx */
567 16, /* "large" insn */
569 4, /* cost for loading QImode using movzbl */
570 {4, 4, 4}, /* cost of loading integer registers
571 in QImode, HImode and SImode.
572 Relative to reg-reg move (2). */
573 {4, 4, 4}, /* cost of storing integer registers */
574 3, /* cost of reg,reg fld/fst */
575 {12, 12, 12}, /* cost of loading fp registers
576 in SFmode, DFmode and XFmode */
577 {4, 4, 4}, /* cost of storing fp registers
578 in SFmode, DFmode and XFmode */
579 6, /* cost of moving MMX register */
580 {12, 12}, /* cost of loading MMX registers
581 in SImode and DImode */
582 {12, 12}, /* cost of storing MMX registers
583 in SImode and DImode */
584 6, /* cost of moving SSE register */
585 {12, 12, 12}, /* cost of loading SSE registers
586 in SImode, DImode and TImode */
587 {12, 12, 12}, /* cost of storing SSE registers
588 in SImode, DImode and TImode */
589 8, /* MMX or SSE register to integer */
590 128, /* size of prefetch block */
591 8, /* number of parallel prefetches */
593 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
594 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
595 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
596 COSTS_N_INSNS (3), /* cost of FABS instruction. */
597 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
598 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
601 /* Generic64 should produce code tuned for Nocona and K8. */
603 struct processor_costs generic64_cost = {
604 COSTS_N_INSNS (1), /* cost of an add instruction */
605 /* On all chips taken into consideration lea is 2 cycles and more. With
606 this cost however our current implementation of synth_mult results in
607 use of unnecessary temporary registers causing regression on several
608 SPECfp benchmarks. */
609 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
610 COSTS_N_INSNS (1), /* variable shift costs */
611 COSTS_N_INSNS (1), /* constant shift costs */
612 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
613 COSTS_N_INSNS (4), /* HI */
614 COSTS_N_INSNS (3), /* SI */
615 COSTS_N_INSNS (4), /* DI */
616 COSTS_N_INSNS (2)}, /* other */
617 0, /* cost of multiply per each bit set */
618 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
619 COSTS_N_INSNS (26), /* HI */
620 COSTS_N_INSNS (42), /* SI */
621 COSTS_N_INSNS (74), /* DI */
622 COSTS_N_INSNS (74)}, /* other */
623 COSTS_N_INSNS (1), /* cost of movsx */
624 COSTS_N_INSNS (1), /* cost of movzx */
625 8, /* "large" insn */
627 4, /* cost for loading QImode using movzbl */
628 {4, 4, 4}, /* cost of loading integer registers
629 in QImode, HImode and SImode.
630 Relative to reg-reg move (2). */
631 {4, 4, 4}, /* cost of storing integer registers */
632 4, /* cost of reg,reg fld/fst */
633 {12, 12, 12}, /* cost of loading fp registers
634 in SFmode, DFmode and XFmode */
635 {6, 6, 8}, /* cost of storing fp registers
636 in SFmode, DFmode and XFmode */
637 2, /* cost of moving MMX register */
638 {8, 8}, /* cost of loading MMX registers
639 in SImode and DImode */
640 {8, 8}, /* cost of storing MMX registers
641 in SImode and DImode */
642 2, /* cost of moving SSE register */
643 {8, 8, 8}, /* cost of loading SSE registers
644 in SImode, DImode and TImode */
645 {8, 8, 8}, /* cost of storing SSE registers
646 in SImode, DImode and TImode */
647 5, /* MMX or SSE register to integer */
648 64, /* size of prefetch block */
649 6, /* number of parallel prefetches */
650 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
651 is increased to perhaps more appropriate value of 5. */
653 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
654 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
655 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
656 COSTS_N_INSNS (8), /* cost of FABS instruction. */
657 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
658 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
661 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
663 struct processor_costs generic32_cost = {
664 COSTS_N_INSNS (1), /* cost of an add instruction */
665 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
666 COSTS_N_INSNS (1), /* variable shift costs */
667 COSTS_N_INSNS (1), /* constant shift costs */
668 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
669 COSTS_N_INSNS (4), /* HI */
670 COSTS_N_INSNS (3), /* SI */
671 COSTS_N_INSNS (4), /* DI */
672 COSTS_N_INSNS (2)}, /* other */
673 0, /* cost of multiply per each bit set */
674 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
675 COSTS_N_INSNS (26), /* HI */
676 COSTS_N_INSNS (42), /* SI */
677 COSTS_N_INSNS (74), /* DI */
678 COSTS_N_INSNS (74)}, /* other */
679 COSTS_N_INSNS (1), /* cost of movsx */
680 COSTS_N_INSNS (1), /* cost of movzx */
681 8, /* "large" insn */
683 4, /* cost for loading QImode using movzbl */
684 {4, 4, 4}, /* cost of loading integer registers
685 in QImode, HImode and SImode.
686 Relative to reg-reg move (2). */
687 {4, 4, 4}, /* cost of storing integer registers */
688 4, /* cost of reg,reg fld/fst */
689 {12, 12, 12}, /* cost of loading fp registers
690 in SFmode, DFmode and XFmode */
691 {6, 6, 8}, /* cost of storing fp registers
692 in SFmode, DFmode and XFmode */
693 2, /* cost of moving MMX register */
694 {8, 8}, /* cost of loading MMX registers
695 in SImode and DImode */
696 {8, 8}, /* cost of storing MMX registers
697 in SImode and DImode */
698 2, /* cost of moving SSE register */
699 {8, 8, 8}, /* cost of loading SSE registers
700 in SImode, DImode and TImode */
701 {8, 8, 8}, /* cost of storing SSE registers
702 in SImode, DImode and TImode */
703 5, /* MMX or SSE register to integer */
704 64, /* size of prefetch block */
705 6, /* number of parallel prefetches */
707 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (8), /* cost of FABS instruction. */
711 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
715 const struct processor_costs *ix86_cost = &pentium_cost;
717 /* Processor feature/optimization bitmasks. */
718 #define m_386 (1<<PROCESSOR_I386)
719 #define m_486 (1<<PROCESSOR_I486)
720 #define m_PENT (1<<PROCESSOR_PENTIUM)
721 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
722 #define m_K6 (1<<PROCESSOR_K6)
723 #define m_ATHLON (1<<PROCESSOR_ATHLON)
724 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
725 #define m_K8 (1<<PROCESSOR_K8)
726 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
727 #define m_NOCONA (1<<PROCESSOR_NOCONA)
728 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
729 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
730 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
732 /* Generic instruction choice should be common subset of supported CPUs
733 (PPro/PENT4/NOCONA/Athlon/K8). */
735 /* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
736 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
737 generic because it is not working well with PPro base chips. */
738 const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64;
739 const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
740 const int x86_zero_extend_with_and = m_486 | m_PENT;
741 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */;
742 const int x86_double_with_add = ~m_386;
743 const int x86_use_bit_test = m_386;
744 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
745 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
746 const int x86_fisttp = m_NOCONA;
747 const int x86_3dnow_a = m_ATHLON_K8;
748 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
749 /* Branch hints were put in P4 based on simulation result. But
750 after P4 was made, no performance benefit was observed with
751 branch hints. It also increases the code size. As the result,
752 icc never generates branch hints. */
753 const int x86_branch_hints = 0;
754 const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
755 /* We probably ought to watch for partial register stalls on Generic32
756 compilation setting as well. However in current implementation the
757 partial register stalls are not eliminated very well - they can
758 be introduced via subregs synthesized by combine and can happen
759 in caller/callee saving sequences.
760 Because this option pays back little on PPro based chips and is in conflict
761 with partial reg. dependencies used by Athlon/P4 based chips, it is better
762 to leave it off for generic32 for now. */
763 const int x86_partial_reg_stall = m_PPRO;
764 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
765 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
766 const int x86_use_mov0 = m_K6;
767 const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC);
768 const int x86_read_modify_write = ~m_PENT;
769 const int x86_read_modify = ~(m_PENT | m_PPRO);
770 const int x86_split_long_moves = m_PPRO;
771 const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */
772 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
773 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
774 const int x86_qimode_math = ~(0);
775 const int x86_promote_qi_regs = 0;
776 /* On PPro this flag is meant to avoid partial register stalls. Just like
777 the x86_partial_reg_stall this option might be considered for Generic32
778 if our scheme for avoiding partial stalls was more effective. */
779 const int x86_himode_math = ~(m_PPRO);
780 const int x86_promote_hi_regs = m_PPRO;
781 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC;
782 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
783 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC;
784 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
785 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC);
786 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
787 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
788 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
789 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
790 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
791 const int x86_shift1 = ~m_486;
792 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
793 /* In Generic model we have an conflict here in between PPro/Pentium4 based chips
794 that thread 128bit SSE registers as single units versus K8 based chips that
795 divide SSE registers to two 64bit halves.
796 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
797 to allow register renaming on 128bit SSE units, but usually results in one
798 extra microop on 64bit SSE units. Experimental results shows that disabling
799 this option on P4 brings over 20% SPECfp regression, while enabling it on
800 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
802 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
803 /* Set for machines where the type and dependencies are resolved on SSE
804 register parts instead of whole registers, so we may maintain just
805 lower part of scalar values in proper format leaving the upper part
807 const int x86_sse_split_regs = m_ATHLON_K8;
808 const int x86_sse_typeless_stores = m_ATHLON_K8;
809 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
810 const int x86_use_ffreep = m_ATHLON_K8;
811 const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
812 const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC);
814 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
815 integer data in xmm registers. Which results in pretty abysmal code. */
816 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
818 const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
819 /* Some CPU cores are not able to predict more than 4 branch instructions in
820 the 16 byte window. */
821 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
822 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC;
823 const int x86_use_bt = m_ATHLON_K8;
824 /* Compare and exchange was added for 80486. */
825 const int x86_cmpxchg = ~m_386;
826 /* Compare and exchange 8 bytes was added for pentium. */
827 const int x86_cmpxchg8b = ~(m_386 | m_486);
828 /* Compare and exchange 16 bytes was added for nocona. */
829 const int x86_cmpxchg16b = m_NOCONA;
830 /* Exchange and add was added for 80486. */
831 const int x86_xadd = ~m_386;
832 const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC;
834 /* In case the average insn count for single function invocation is
835 lower than this constant, emit fast (but longer) prologue and
837 #define FAST_PROLOGUE_INSN_COUNT 20
839 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
840 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
841 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
842 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
844 /* Array of the smallest class containing reg number REGNO, indexed by
845 REGNO. Used by REGNO_REG_CLASS in i386.h. */
847 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
850 AREG, DREG, CREG, BREG,
852 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
854 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
855 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
858 /* flags, fpsr, dirflag, frame */
859 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
860 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
862 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
864 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
865 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
866 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
870 /* The "default" register map used in 32bit mode. */
872 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
874 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
875 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
876 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
877 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
878 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
879 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
880 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
883 static int const x86_64_int_parameter_registers[6] =
885 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
886 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
889 static int const x86_64_int_return_registers[4] =
891 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
894 /* The "default" register map used in 64bit mode. */
895 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
897 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
898 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
899 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
900 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
901 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
902 8,9,10,11,12,13,14,15, /* extended integer registers */
903 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
906 /* Define the register numbers to be used in Dwarf debugging information.
907 The SVR4 reference port C compiler uses the following register numbers
908 in its Dwarf output code:
909 0 for %eax (gcc regno = 0)
910 1 for %ecx (gcc regno = 2)
911 2 for %edx (gcc regno = 1)
912 3 for %ebx (gcc regno = 3)
913 4 for %esp (gcc regno = 7)
914 5 for %ebp (gcc regno = 6)
915 6 for %esi (gcc regno = 4)
916 7 for %edi (gcc regno = 5)
917 The following three DWARF register numbers are never generated by
918 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
919 believes these numbers have these meanings.
920 8 for %eip (no gcc equivalent)
921 9 for %eflags (gcc regno = 17)
922 10 for %trapno (no gcc equivalent)
923 It is not at all clear how we should number the FP stack registers
924 for the x86 architecture. If the version of SDB on x86/svr4 were
925 a bit less brain dead with respect to floating-point then we would
926 have a precedent to follow with respect to DWARF register numbers
927 for x86 FP registers, but the SDB on x86/svr4 is so completely
928 broken with respect to FP registers that it is hardly worth thinking
929 of it as something to strive for compatibility with.
930 The version of x86/svr4 SDB I have at the moment does (partially)
931 seem to believe that DWARF register number 11 is associated with
932 the x86 register %st(0), but that's about all. Higher DWARF
933 register numbers don't seem to be associated with anything in
934 particular, and even for DWARF regno 11, SDB only seems to under-
935 stand that it should say that a variable lives in %st(0) (when
936 asked via an `=' command) if we said it was in DWARF regno 11,
937 but SDB still prints garbage when asked for the value of the
938 variable in question (via a `/' command).
939 (Also note that the labels SDB prints for various FP stack regs
940 when doing an `x' command are all wrong.)
941 Note that these problems generally don't affect the native SVR4
942 C compiler because it doesn't allow the use of -O with -g and
943 because when it is *not* optimizing, it allocates a memory
944 location for each floating-point variable, and the memory
945 location is what gets described in the DWARF AT_location
946 attribute for the variable in question.
947 Regardless of the severe mental illness of the x86/svr4 SDB, we
948 do something sensible here and we use the following DWARF
949 register numbers. Note that these are all stack-top-relative
951 11 for %st(0) (gcc regno = 8)
952 12 for %st(1) (gcc regno = 9)
953 13 for %st(2) (gcc regno = 10)
954 14 for %st(3) (gcc regno = 11)
955 15 for %st(4) (gcc regno = 12)
956 16 for %st(5) (gcc regno = 13)
957 17 for %st(6) (gcc regno = 14)
958 18 for %st(7) (gcc regno = 15)
960 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
962 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
963 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
964 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
965 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
966 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
967 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
968 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
971 /* Test and compare insns in i386.md store the information needed to
972 generate branch and scc insns here. */
974 rtx ix86_compare_op0 = NULL_RTX;
975 rtx ix86_compare_op1 = NULL_RTX;
976 rtx ix86_compare_emitted = NULL_RTX;
978 /* Size of the register save area. */
979 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
981 /* Define the structure for the machine field in struct function. */
983 struct stack_local_entry GTY(())
988 struct stack_local_entry *next;
991 /* Structure describing stack frame layout.
992 Stack grows downward:
998 saved frame pointer if frame_pointer_needed
999 <- HARD_FRAME_POINTER
1004 [va_arg registers] (
1005 > to_allocate <- FRAME_POINTER
1015 HOST_WIDE_INT frame;
1017 int outgoing_arguments_size;
1020 HOST_WIDE_INT to_allocate;
1021 /* The offsets relative to ARG_POINTER. */
1022 HOST_WIDE_INT frame_pointer_offset;
1023 HOST_WIDE_INT hard_frame_pointer_offset;
1024 HOST_WIDE_INT stack_pointer_offset;
1026 /* When save_regs_using_mov is set, emit prologue using
1027 move instead of push instructions. */
1028 bool save_regs_using_mov;
1031 /* Code model option. */
1032 enum cmodel ix86_cmodel;
1034 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1036 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1038 /* Which unit we are generating floating point math for. */
1039 enum fpmath_unit ix86_fpmath;
1041 /* Which cpu are we scheduling for. */
1042 enum processor_type ix86_tune;
1043 /* Which instruction set architecture to use. */
1044 enum processor_type ix86_arch;
1046 /* true if sse prefetch instruction is not NOOP. */
1047 int x86_prefetch_sse;
1049 /* ix86_regparm_string as a number */
1050 static int ix86_regparm;
1052 /* -mstackrealign option */
1053 extern int ix86_force_align_arg_pointer;
1054 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1056 /* Preferred alignment for stack boundary in bits. */
1057 unsigned int ix86_preferred_stack_boundary;
1059 /* Values 1-5: see jump.c */
1060 int ix86_branch_cost;
1062 /* Variables which are this size or smaller are put in the data/bss
1063 or ldata/lbss sections. */
1065 int ix86_section_threshold = 65536;
1067 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1068 char internal_label_prefix[16];
1069 int internal_label_prefix_len;
1071 static bool ix86_handle_option (size_t, const char *, int);
1072 static void output_pic_addr_const (FILE *, rtx, int);
1073 static void put_condition_code (enum rtx_code, enum machine_mode,
1075 static const char *get_some_local_dynamic_name (void);
1076 static int get_some_local_dynamic_name_1 (rtx *, void *);
1077 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
1078 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
1080 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
1081 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
1083 static rtx get_thread_pointer (int);
1084 static rtx legitimize_tls_address (rtx, enum tls_model, int);
1085 static void get_pc_thunk_name (char [32], unsigned int);
1086 static rtx gen_push (rtx);
1087 static int ix86_flags_dependent (rtx, rtx, enum attr_type);
1088 static int ix86_agi_dependent (rtx, rtx, enum attr_type);
1089 static struct machine_function * ix86_init_machine_status (void);
1090 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
1091 static int ix86_nsaved_regs (void);
1092 static void ix86_emit_save_regs (void);
1093 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
1094 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
1095 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
1096 static HOST_WIDE_INT ix86_GOT_alias_set (void);
1097 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
1098 static rtx ix86_expand_aligntest (rtx, int);
1099 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
1100 static int ix86_issue_rate (void);
1101 static int ix86_adjust_cost (rtx, rtx, rtx, int);
1102 static int ia32_multipass_dfa_lookahead (void);
1103 static void ix86_init_mmx_sse_builtins (void);
1104 static rtx x86_this_parameter (tree);
1105 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
1106 HOST_WIDE_INT, tree);
1107 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
1108 static void x86_file_start (void);
1109 static void ix86_reorg (void);
1110 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
1111 static tree ix86_build_builtin_va_list (void);
1112 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
1114 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
1115 static bool ix86_scalar_mode_supported_p (enum machine_mode);
1116 static bool ix86_vector_mode_supported_p (enum machine_mode);
1118 static int ix86_address_cost (rtx);
1119 static bool ix86_cannot_force_const_mem (rtx);
1120 static rtx ix86_delegitimize_address (rtx);
1122 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1124 struct builtin_description;
1125 static rtx ix86_expand_sse_comi (const struct builtin_description *,
1127 static rtx ix86_expand_sse_compare (const struct builtin_description *,
1129 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
1130 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
1131 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
1132 static rtx ix86_expand_store_builtin (enum insn_code, tree);
1133 static rtx safe_vector_operand (rtx, enum machine_mode);
1134 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
1135 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
1136 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
1137 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
1138 static int ix86_fp_comparison_cost (enum rtx_code code);
1139 static unsigned int ix86_select_alt_pic_regnum (void);
1140 static int ix86_save_reg (unsigned int, int);
1141 static void ix86_compute_frame_layout (struct ix86_frame *);
1142 static int ix86_comp_type_attributes (tree, tree);
1143 static int ix86_function_regparm (tree, tree);
1144 const struct attribute_spec ix86_attribute_table[];
1145 static bool ix86_function_ok_for_sibcall (tree, tree);
1146 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
1147 static int ix86_value_regno (enum machine_mode, tree, tree);
1148 static bool contains_128bit_aligned_vector_p (tree);
1149 static rtx ix86_struct_value_rtx (tree, int);
1150 static bool ix86_ms_bitfield_layout_p (tree);
1151 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
1152 static int extended_reg_mentioned_1 (rtx *, void *);
1153 static bool ix86_rtx_costs (rtx, int, int, int *);
1154 static int min_insn_size (rtx);
1155 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
1156 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
1157 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
1159 static void ix86_init_builtins (void);
1160 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1161 static const char *ix86_mangle_fundamental_type (tree);
1162 static tree ix86_stack_protect_fail (void);
1163 static rtx ix86_internal_arg_pointer (void);
1164 static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
1166 /* This function is only used on Solaris. */
1167 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
1170 /* Register class used for passing given 64bit part of the argument.
1171 These represent classes as documented by the PS ABI, with the exception
1172 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1173 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1175 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1176 whenever possible (upper half does contain padding).
1178 enum x86_64_reg_class
1181 X86_64_INTEGER_CLASS,
1182 X86_64_INTEGERSI_CLASS,
1189 X86_64_COMPLEX_X87_CLASS,
1192 static const char * const x86_64_reg_class_name[] = {
1193 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1194 "sseup", "x87", "x87up", "cplx87", "no"
1197 #define MAX_CLASSES 4
1199 /* Table of constants used by fldpi, fldln2, etc.... */
1200 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1201 static bool ext_80387_constants_init = 0;
1202 static void init_ext_80387_constants (void);
1203 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
1204 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
1205 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
1206 static section *x86_64_elf_select_section (tree decl, int reloc,
1207 unsigned HOST_WIDE_INT align)
1210 /* Initialize the GCC target structure. */
1211 #undef TARGET_ATTRIBUTE_TABLE
1212 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
1213 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1214 # undef TARGET_MERGE_DECL_ATTRIBUTES
1215 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
1218 #undef TARGET_COMP_TYPE_ATTRIBUTES
1219 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
1221 #undef TARGET_INIT_BUILTINS
1222 #define TARGET_INIT_BUILTINS ix86_init_builtins
1223 #undef TARGET_EXPAND_BUILTIN
1224 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
1226 #undef TARGET_ASM_FUNCTION_EPILOGUE
1227 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
1229 #undef TARGET_ENCODE_SECTION_INFO
1230 #ifndef SUBTARGET_ENCODE_SECTION_INFO
1231 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
1233 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
1236 #undef TARGET_ASM_OPEN_PAREN
1237 #define TARGET_ASM_OPEN_PAREN ""
1238 #undef TARGET_ASM_CLOSE_PAREN
1239 #define TARGET_ASM_CLOSE_PAREN ""
1241 #undef TARGET_ASM_ALIGNED_HI_OP
1242 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
1243 #undef TARGET_ASM_ALIGNED_SI_OP
1244 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1246 #undef TARGET_ASM_ALIGNED_DI_OP
1247 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1250 #undef TARGET_ASM_UNALIGNED_HI_OP
1251 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1252 #undef TARGET_ASM_UNALIGNED_SI_OP
1253 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1254 #undef TARGET_ASM_UNALIGNED_DI_OP
1255 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1257 #undef TARGET_SCHED_ADJUST_COST
1258 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1259 #undef TARGET_SCHED_ISSUE_RATE
1260 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1261 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1262 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1263 ia32_multipass_dfa_lookahead
1265 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1266 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1269 #undef TARGET_HAVE_TLS
1270 #define TARGET_HAVE_TLS true
1272 #undef TARGET_CANNOT_FORCE_CONST_MEM
1273 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1274 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1275 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
1277 #undef TARGET_DELEGITIMIZE_ADDRESS
1278 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1280 #undef TARGET_MS_BITFIELD_LAYOUT_P
1281 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1284 #undef TARGET_BINDS_LOCAL_P
1285 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1288 #undef TARGET_ASM_OUTPUT_MI_THUNK
1289 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1290 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1291 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1293 #undef TARGET_ASM_FILE_START
1294 #define TARGET_ASM_FILE_START x86_file_start
1296 #undef TARGET_DEFAULT_TARGET_FLAGS
1297 #define TARGET_DEFAULT_TARGET_FLAGS \
1299 | TARGET_64BIT_DEFAULT \
1300 | TARGET_SUBTARGET_DEFAULT \
1301 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1303 #undef TARGET_HANDLE_OPTION
1304 #define TARGET_HANDLE_OPTION ix86_handle_option
1306 #undef TARGET_RTX_COSTS
1307 #define TARGET_RTX_COSTS ix86_rtx_costs
1308 #undef TARGET_ADDRESS_COST
1309 #define TARGET_ADDRESS_COST ix86_address_cost
1311 #undef TARGET_FIXED_CONDITION_CODE_REGS
1312 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1313 #undef TARGET_CC_MODES_COMPATIBLE
1314 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1316 #undef TARGET_MACHINE_DEPENDENT_REORG
1317 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1319 #undef TARGET_BUILD_BUILTIN_VA_LIST
1320 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1322 #undef TARGET_MD_ASM_CLOBBERS
1323 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1325 #undef TARGET_PROMOTE_PROTOTYPES
1326 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1327 #undef TARGET_STRUCT_VALUE_RTX
1328 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1329 #undef TARGET_SETUP_INCOMING_VARARGS
1330 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1331 #undef TARGET_MUST_PASS_IN_STACK
1332 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1333 #undef TARGET_PASS_BY_REFERENCE
1334 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1335 #undef TARGET_INTERNAL_ARG_POINTER
1336 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1337 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1338 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1340 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1341 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1343 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1344 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
1346 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1347 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1350 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1351 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1354 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1355 #undef TARGET_INSERT_ATTRIBUTES
1356 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1359 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1360 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1362 #undef TARGET_STACK_PROTECT_FAIL
1363 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1365 #undef TARGET_FUNCTION_VALUE
1366 #define TARGET_FUNCTION_VALUE ix86_function_value
1368 struct gcc_target targetm = TARGET_INITIALIZER;
1371 /* The svr4 ABI for the i386 says that records and unions are returned
1373 #ifndef DEFAULT_PCC_STRUCT_RETURN
1374 #define DEFAULT_PCC_STRUCT_RETURN 1
1377 /* Implement TARGET_HANDLE_OPTION. */
1380 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1387 target_flags &= ~MASK_3DNOW_A;
1388 target_flags_explicit |= MASK_3DNOW_A;
1395 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1396 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1403 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1404 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1411 target_flags &= ~MASK_SSE3;
1412 target_flags_explicit |= MASK_SSE3;
1421 /* Sometimes certain combinations of command options do not make
1422 sense on a particular target machine. You can define a macro
1423 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1424 defined, is executed once just after all the command options have
1427 Don't use this macro to turn on various extra optimizations for
1428 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1431 override_options (void)
1434 int ix86_tune_defaulted = 0;
1436 /* Comes from final.c -- no real reason to change it. */
1437 #define MAX_CODE_ALIGN 16
1441 const struct processor_costs *cost; /* Processor costs */
1442 const int target_enable; /* Target flags to enable. */
1443 const int target_disable; /* Target flags to disable. */
1444 const int align_loop; /* Default alignments. */
1445 const int align_loop_max_skip;
1446 const int align_jump;
1447 const int align_jump_max_skip;
1448 const int align_func;
1450 const processor_target_table[PROCESSOR_max] =
1452 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1453 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1454 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1455 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1456 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1457 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1458 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1459 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1460 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1461 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1462 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1465 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1468 const char *const name; /* processor name or nickname. */
1469 const enum processor_type processor;
1470 const enum pta_flags
1476 PTA_PREFETCH_SSE = 16,
1482 const processor_alias_table[] =
1484 {"i386", PROCESSOR_I386, 0},
1485 {"i486", PROCESSOR_I486, 0},
1486 {"i586", PROCESSOR_PENTIUM, 0},
1487 {"pentium", PROCESSOR_PENTIUM, 0},
1488 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1489 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1490 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1491 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1492 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1493 {"i686", PROCESSOR_PENTIUMPRO, 0},
1494 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1495 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1496 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1497 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1498 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1499 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1500 | PTA_MMX | PTA_PREFETCH_SSE},
1501 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1502 | PTA_MMX | PTA_PREFETCH_SSE},
1503 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1504 | PTA_MMX | PTA_PREFETCH_SSE},
1505 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1506 | PTA_MMX | PTA_PREFETCH_SSE},
1507 {"k6", PROCESSOR_K6, PTA_MMX},
1508 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1509 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1510 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1512 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1513 | PTA_3DNOW | PTA_3DNOW_A},
1514 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1515 | PTA_3DNOW_A | PTA_SSE},
1516 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1517 | PTA_3DNOW_A | PTA_SSE},
1518 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1519 | PTA_3DNOW_A | PTA_SSE},
1520 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1521 | PTA_SSE | PTA_SSE2 },
1522 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1523 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1524 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1525 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1526 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1527 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1528 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1529 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1530 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1531 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1534 int const pta_size = ARRAY_SIZE (processor_alias_table);
1536 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1537 SUBTARGET_OVERRIDE_OPTIONS;
1540 /* Set the default values for switches whose default depends on TARGET_64BIT
1541 in case they weren't overwritten by command line options. */
1544 if (flag_omit_frame_pointer == 2)
1545 flag_omit_frame_pointer = 1;
1546 if (flag_asynchronous_unwind_tables == 2)
1547 flag_asynchronous_unwind_tables = 1;
1548 if (flag_pcc_struct_return == 2)
1549 flag_pcc_struct_return = 0;
1553 if (flag_omit_frame_pointer == 2)
1554 flag_omit_frame_pointer = 0;
1555 if (flag_asynchronous_unwind_tables == 2)
1556 flag_asynchronous_unwind_tables = 0;
1557 if (flag_pcc_struct_return == 2)
1558 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1561 /* Need to check -mtune=generic first. */
1562 if (ix86_tune_string)
1564 if (!strcmp (ix86_tune_string, "generic")
1565 || !strcmp (ix86_tune_string, "i686")
1566 /* As special support for cross compilers we read -mtune=native
1567 as -mtune=generic. With native compilers we won't see the
1568 -mtune=native, as it was changed by the driver. */
1569 || !strcmp (ix86_tune_string, "native"))
1572 ix86_tune_string = "generic64";
1574 ix86_tune_string = "generic32";
1576 else if (!strncmp (ix86_tune_string, "generic", 7))
1577 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1581 if (ix86_arch_string)
1582 ix86_tune_string = ix86_arch_string;
1583 if (!ix86_tune_string)
1585 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1586 ix86_tune_defaulted = 1;
1589 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1590 need to use a sensible tune option. */
1591 if (!strcmp (ix86_tune_string, "generic")
1592 || !strcmp (ix86_tune_string, "x86-64")
1593 || !strcmp (ix86_tune_string, "i686"))
1596 ix86_tune_string = "generic64";
1598 ix86_tune_string = "generic32";
1601 if (!strcmp (ix86_tune_string, "x86-64"))
1602 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
1603 "-mtune=generic instead as appropriate.");
1605 if (!ix86_arch_string)
1606 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1607 if (!strcmp (ix86_arch_string, "generic"))
1608 error ("generic CPU can be used only for -mtune= switch");
1609 if (!strncmp (ix86_arch_string, "generic", 7))
1610 error ("bad value (%s) for -march= switch", ix86_arch_string);
1612 if (ix86_cmodel_string != 0)
1614 if (!strcmp (ix86_cmodel_string, "small"))
1615 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1616 else if (!strcmp (ix86_cmodel_string, "medium"))
1617 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1619 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1620 else if (!strcmp (ix86_cmodel_string, "32"))
1621 ix86_cmodel = CM_32;
1622 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1623 ix86_cmodel = CM_KERNEL;
1624 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1625 ix86_cmodel = CM_LARGE;
1627 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1631 ix86_cmodel = CM_32;
1633 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1635 if (ix86_asm_string != 0)
1638 && !strcmp (ix86_asm_string, "intel"))
1639 ix86_asm_dialect = ASM_INTEL;
1640 else if (!strcmp (ix86_asm_string, "att"))
1641 ix86_asm_dialect = ASM_ATT;
1643 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1645 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1646 error ("code model %qs not supported in the %s bit mode",
1647 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1648 if (ix86_cmodel == CM_LARGE)
1649 sorry ("code model %<large%> not supported yet");
1650 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1651 sorry ("%i-bit mode not compiled in",
1652 (target_flags & MASK_64BIT) ? 64 : 32);
1654 for (i = 0; i < pta_size; i++)
1655 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1657 ix86_arch = processor_alias_table[i].processor;
1658 /* Default cpu tuning to the architecture. */
1659 ix86_tune = ix86_arch;
1660 if (processor_alias_table[i].flags & PTA_MMX
1661 && !(target_flags_explicit & MASK_MMX))
1662 target_flags |= MASK_MMX;
1663 if (processor_alias_table[i].flags & PTA_3DNOW
1664 && !(target_flags_explicit & MASK_3DNOW))
1665 target_flags |= MASK_3DNOW;
1666 if (processor_alias_table[i].flags & PTA_3DNOW_A
1667 && !(target_flags_explicit & MASK_3DNOW_A))
1668 target_flags |= MASK_3DNOW_A;
1669 if (processor_alias_table[i].flags & PTA_SSE
1670 && !(target_flags_explicit & MASK_SSE))
1671 target_flags |= MASK_SSE;
1672 if (processor_alias_table[i].flags & PTA_SSE2
1673 && !(target_flags_explicit & MASK_SSE2))
1674 target_flags |= MASK_SSE2;
1675 if (processor_alias_table[i].flags & PTA_SSE3
1676 && !(target_flags_explicit & MASK_SSE3))
1677 target_flags |= MASK_SSE3;
1678 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1679 x86_prefetch_sse = true;
1680 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1681 error ("CPU you selected does not support x86-64 "
1687 error ("bad value (%s) for -march= switch", ix86_arch_string);
1689 for (i = 0; i < pta_size; i++)
1690 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1692 ix86_tune = processor_alias_table[i].processor;
1693 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1695 if (ix86_tune_defaulted)
1697 ix86_tune_string = "x86-64";
1698 for (i = 0; i < pta_size; i++)
1699 if (! strcmp (ix86_tune_string,
1700 processor_alias_table[i].name))
1702 ix86_tune = processor_alias_table[i].processor;
1705 error ("CPU you selected does not support x86-64 "
1708 /* Intel CPUs have always interpreted SSE prefetch instructions as
1709 NOPs; so, we can enable SSE prefetch instructions even when
1710 -mtune (rather than -march) points us to a processor that has them.
1711 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1712 higher processors. */
1713 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1714 x86_prefetch_sse = true;
1718 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1721 ix86_cost = &size_cost;
1723 ix86_cost = processor_target_table[ix86_tune].cost;
1724 target_flags |= processor_target_table[ix86_tune].target_enable;
1725 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1727 /* Arrange to set up i386_stack_locals for all functions. */
1728 init_machine_status = ix86_init_machine_status;
1730 /* Validate -mregparm= value. */
1731 if (ix86_regparm_string)
1733 i = atoi (ix86_regparm_string);
1734 if (i < 0 || i > REGPARM_MAX)
1735 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1741 ix86_regparm = REGPARM_MAX;
1743 /* If the user has provided any of the -malign-* options,
1744 warn and use that value only if -falign-* is not set.
1745 Remove this code in GCC 3.2 or later. */
1746 if (ix86_align_loops_string)
1748 warning (0, "-malign-loops is obsolete, use -falign-loops");
1749 if (align_loops == 0)
1751 i = atoi (ix86_align_loops_string);
1752 if (i < 0 || i > MAX_CODE_ALIGN)
1753 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1755 align_loops = 1 << i;
1759 if (ix86_align_jumps_string)
1761 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1762 if (align_jumps == 0)
1764 i = atoi (ix86_align_jumps_string);
1765 if (i < 0 || i > MAX_CODE_ALIGN)
1766 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1768 align_jumps = 1 << i;
1772 if (ix86_align_funcs_string)
1774 warning (0, "-malign-functions is obsolete, use -falign-functions");
1775 if (align_functions == 0)
1777 i = atoi (ix86_align_funcs_string);
1778 if (i < 0 || i > MAX_CODE_ALIGN)
1779 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1781 align_functions = 1 << i;
1785 /* Default align_* from the processor table. */
1786 if (align_loops == 0)
1788 align_loops = processor_target_table[ix86_tune].align_loop;
1789 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
1791 if (align_jumps == 0)
1793 align_jumps = processor_target_table[ix86_tune].align_jump;
1794 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
1796 if (align_functions == 0)
1798 align_functions = processor_target_table[ix86_tune].align_func;
1801 /* Validate -mpreferred-stack-boundary= value, or provide default.
1802 The default of 128 bits is for Pentium III's SSE __m128, but we
1803 don't want additional code to keep the stack aligned when
1804 optimizing for code size. */
1805 ix86_preferred_stack_boundary = ((TARGET_64BIT || TARGET_MACHO || !optimize_size)
1807 if (ix86_preferred_stack_boundary_string)
1809 i = atoi (ix86_preferred_stack_boundary_string);
1810 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
1811 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
1812 TARGET_64BIT ? 4 : 2);
1814 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
1817 /* Validate -mbranch-cost= value, or provide default. */
1818 ix86_branch_cost = ix86_cost->branch_cost;
1819 if (ix86_branch_cost_string)
1821 i = atoi (ix86_branch_cost_string);
1823 error ("-mbranch-cost=%d is not between 0 and 5", i);
1825 ix86_branch_cost = i;
1827 if (ix86_section_threshold_string)
1829 i = atoi (ix86_section_threshold_string);
1831 error ("-mlarge-data-threshold=%d is negative", i);
1833 ix86_section_threshold = i;
1836 if (ix86_tls_dialect_string)
1838 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
1839 ix86_tls_dialect = TLS_DIALECT_GNU;
1840 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
1841 ix86_tls_dialect = TLS_DIALECT_GNU2;
1842 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
1843 ix86_tls_dialect = TLS_DIALECT_SUN;
1845 error ("bad value (%s) for -mtls-dialect= switch",
1846 ix86_tls_dialect_string);
1849 /* Keep nonleaf frame pointers. */
1850 if (flag_omit_frame_pointer)
1851 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
1852 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
1853 flag_omit_frame_pointer = 1;
1855 /* If we're doing fast math, we don't care about comparison order
1856 wrt NaNs. This lets us use a shorter comparison sequence. */
1857 if (flag_unsafe_math_optimizations)
1858 target_flags &= ~MASK_IEEE_FP;
1860 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1861 since the insns won't need emulation. */
1862 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1863 target_flags &= ~MASK_NO_FANCY_MATH_387;
1865 /* Likewise, if the target doesn't have a 387, or we've specified
1866 software floating point, don't use 387 inline intrinsics. */
1868 target_flags |= MASK_NO_FANCY_MATH_387;
1870 /* Turn on SSE2 builtins for -msse3. */
1872 target_flags |= MASK_SSE2;
1874 /* Turn on SSE builtins for -msse2. */
1876 target_flags |= MASK_SSE;
1878 /* Turn on MMX builtins for -msse. */
1881 target_flags |= MASK_MMX & ~target_flags_explicit;
1882 x86_prefetch_sse = true;
1885 /* Turn on MMX builtins for 3Dnow. */
1887 target_flags |= MASK_MMX;
1891 if (TARGET_ALIGN_DOUBLE)
1892 error ("-malign-double makes no sense in the 64bit mode");
1894 error ("-mrtd calling convention not supported in the 64bit mode");
1896 /* Enable by default the SSE and MMX builtins. Do allow the user to
1897 explicitly disable any of these. In particular, disabling SSE and
1898 MMX for kernel code is extremely useful. */
1900 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
1901 & ~target_flags_explicit);
1905 /* i386 ABI does not specify red zone. It still makes sense to use it
1906 when programmer takes care to stack from being destroyed. */
1907 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
1908 target_flags |= MASK_NO_RED_ZONE;
1911 /* Accept -msseregparm only if at least SSE support is enabled. */
1912 if (TARGET_SSEREGPARM
1914 error ("-msseregparm used without SSE enabled");
1916 ix86_fpmath = TARGET_FPMATH_DEFAULT;
1918 if (ix86_fpmath_string != 0)
1920 if (! strcmp (ix86_fpmath_string, "387"))
1921 ix86_fpmath = FPMATH_387;
1922 else if (! strcmp (ix86_fpmath_string, "sse"))
1926 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1927 ix86_fpmath = FPMATH_387;
1930 ix86_fpmath = FPMATH_SSE;
1932 else if (! strcmp (ix86_fpmath_string, "387,sse")
1933 || ! strcmp (ix86_fpmath_string, "sse,387"))
1937 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1938 ix86_fpmath = FPMATH_387;
1940 else if (!TARGET_80387)
1942 warning (0, "387 instruction set disabled, using SSE arithmetics");
1943 ix86_fpmath = FPMATH_SSE;
1946 ix86_fpmath = FPMATH_SSE | FPMATH_387;
1949 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
1952 /* If the i387 is disabled, then do not return values in it. */
1954 target_flags &= ~MASK_FLOAT_RETURNS;
1956 if ((x86_accumulate_outgoing_args & TUNEMASK)
1957 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1959 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1961 /* ??? Unwind info is not correct around the CFG unless either a frame
1962 pointer is present or M_A_O_A is set. Fixing this requires rewriting
1963 unwind info generation to be aware of the CFG and propagating states
1965 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
1966 || flag_exceptions || flag_non_call_exceptions)
1967 && flag_omit_frame_pointer
1968 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
1970 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1971 warning (0, "unwind tables currently require either a frame pointer "
1972 "or -maccumulate-outgoing-args for correctness");
1973 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1976 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1979 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
1980 p = strchr (internal_label_prefix, 'X');
1981 internal_label_prefix_len = p - internal_label_prefix;
1985 /* When scheduling description is not available, disable scheduler pass
1986 so it won't slow down the compilation and make x87 code slower. */
1987 if (!TARGET_SCHEDULE)
1988 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
1991 /* switch to the appropriate section for output of DECL.
1992 DECL is either a `VAR_DECL' node or a constant of some sort.
1993 RELOC indicates whether forming the initial value of DECL requires
1994 link-time relocations. */
1997 x86_64_elf_select_section (tree decl, int reloc,
1998 unsigned HOST_WIDE_INT align)
2000 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2001 && ix86_in_large_data_p (decl))
2003 const char *sname = NULL;
2004 unsigned int flags = SECTION_WRITE;
2005 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2010 case SECCAT_DATA_REL:
2011 sname = ".ldata.rel";
2013 case SECCAT_DATA_REL_LOCAL:
2014 sname = ".ldata.rel.local";
2016 case SECCAT_DATA_REL_RO:
2017 sname = ".ldata.rel.ro";
2019 case SECCAT_DATA_REL_RO_LOCAL:
2020 sname = ".ldata.rel.ro.local";
2024 flags |= SECTION_BSS;
2027 case SECCAT_RODATA_MERGE_STR:
2028 case SECCAT_RODATA_MERGE_STR_INIT:
2029 case SECCAT_RODATA_MERGE_CONST:
2033 case SECCAT_SRODATA:
2040 /* We don't split these for medium model. Place them into
2041 default sections and hope for best. */
2046 /* We might get called with string constants, but get_named_section
2047 doesn't like them as they are not DECLs. Also, we need to set
2048 flags in that case. */
2050 return get_section (sname, flags, NULL);
2051 return get_named_section (decl, sname, reloc);
2054 return default_elf_select_section (decl, reloc, align);
2057 /* Build up a unique section name, expressed as a
2058 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2059 RELOC indicates whether the initial value of EXP requires
2060 link-time relocations. */
2063 x86_64_elf_unique_section (tree decl, int reloc)
2065 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2066 && ix86_in_large_data_p (decl))
2068 const char *prefix = NULL;
2069 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2070 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2072 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2075 case SECCAT_DATA_REL:
2076 case SECCAT_DATA_REL_LOCAL:
2077 case SECCAT_DATA_REL_RO:
2078 case SECCAT_DATA_REL_RO_LOCAL:
2079 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2082 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2085 case SECCAT_RODATA_MERGE_STR:
2086 case SECCAT_RODATA_MERGE_STR_INIT:
2087 case SECCAT_RODATA_MERGE_CONST:
2088 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2090 case SECCAT_SRODATA:
2097 /* We don't split these for medium model. Place them into
2098 default sections and hope for best. */
2106 plen = strlen (prefix);
2108 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2109 name = targetm.strip_name_encoding (name);
2110 nlen = strlen (name);
2112 string = alloca (nlen + plen + 1);
2113 memcpy (string, prefix, plen);
2114 memcpy (string + plen, name, nlen + 1);
2116 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2120 default_unique_section (decl, reloc);
2123 #ifdef COMMON_ASM_OP
2124 /* This says how to output assembler code to declare an
2125 uninitialized external linkage data object.
2127 For medium model x86-64 we need to use .largecomm opcode for
2130 x86_elf_aligned_common (FILE *file,
2131 const char *name, unsigned HOST_WIDE_INT size,
2134 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2135 && size > (unsigned int)ix86_section_threshold)
2136 fprintf (file, ".largecomm\t");
2138 fprintf (file, "%s", COMMON_ASM_OP);
2139 assemble_name (file, name);
2140 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2141 size, align / BITS_PER_UNIT);
2144 /* Utility function for targets to use in implementing
2145 ASM_OUTPUT_ALIGNED_BSS. */
2148 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2149 const char *name, unsigned HOST_WIDE_INT size,
2152 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2153 && size > (unsigned int)ix86_section_threshold)
2154 switch_to_section (get_named_section (decl, ".lbss", 0));
2156 switch_to_section (bss_section);
2157 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2158 #ifdef ASM_DECLARE_OBJECT_NAME
2159 last_assemble_variable_decl = decl;
2160 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2162 /* Standard thing is just output label for the object. */
2163 ASM_OUTPUT_LABEL (file, name);
2164 #endif /* ASM_DECLARE_OBJECT_NAME */
2165 ASM_OUTPUT_SKIP (file, size ? size : 1);
2170 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2172 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2173 make the problem with not enough registers even worse. */
2174 #ifdef INSN_SCHEDULING
2176 flag_schedule_insns = 0;
2180 /* The Darwin libraries never set errno, so we might as well
2181 avoid calling them when that's the only reason we would. */
2182 flag_errno_math = 0;
2184 /* The default values of these switches depend on the TARGET_64BIT
2185 that is not known at this moment. Mark these values with 2 and
2186 let user the to override these. In case there is no command line option
2187 specifying them, we will set the defaults in override_options. */
2189 flag_omit_frame_pointer = 2;
2190 flag_pcc_struct_return = 2;
2191 flag_asynchronous_unwind_tables = 2;
2192 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2193 SUBTARGET_OPTIMIZATION_OPTIONS;
2197 /* Table of valid machine attributes. */
2198 const struct attribute_spec ix86_attribute_table[] =
2200 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2201 /* Stdcall attribute says callee is responsible for popping arguments
2202 if they are not variable. */
2203 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2204 /* Fastcall attribute says callee is responsible for popping arguments
2205 if they are not variable. */
2206 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2207 /* Cdecl attribute says the callee is a normal C declaration */
2208 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2209 /* Regparm attribute specifies how many integer arguments are to be
2210 passed in registers. */
2211 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
2212 /* Sseregparm attribute says we are using x86_64 calling conventions
2213 for FP arguments. */
2214 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2215 /* force_align_arg_pointer says this function realigns the stack at entry. */
2216 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
2217 false, true, true, ix86_handle_cconv_attribute },
2218 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2219 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2220 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2221 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
2223 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2224 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2225 #ifdef SUBTARGET_ATTRIBUTE_TABLE
2226 SUBTARGET_ATTRIBUTE_TABLE,
2228 { NULL, 0, 0, false, false, false, NULL }
2231 /* Decide whether we can make a sibling call to a function. DECL is the
2232 declaration of the function being targeted by the call and EXP is the
2233 CALL_EXPR representing the call. */
2236 ix86_function_ok_for_sibcall (tree decl, tree exp)
2241 /* If we are generating position-independent code, we cannot sibcall
2242 optimize any indirect call, or a direct call to a global function,
2243 as the PLT requires %ebx be live. */
2244 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2251 func = TREE_TYPE (TREE_OPERAND (exp, 0));
2252 if (POINTER_TYPE_P (func))
2253 func = TREE_TYPE (func);
2256 /* Check that the return value locations are the same. Like
2257 if we are returning floats on the 80387 register stack, we cannot
2258 make a sibcall from a function that doesn't return a float to a
2259 function that does or, conversely, from a function that does return
2260 a float to a function that doesn't; the necessary stack adjustment
2261 would not be executed. This is also the place we notice
2262 differences in the return value ABI. Note that it is ok for one
2263 of the functions to have void return type as long as the return
2264 value of the other is passed in a register. */
2265 a = ix86_function_value (TREE_TYPE (exp), func, false);
2266 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2268 if (STACK_REG_P (a) || STACK_REG_P (b))
2270 if (!rtx_equal_p (a, b))
2273 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2275 else if (!rtx_equal_p (a, b))
2278 /* If this call is indirect, we'll need to be able to use a call-clobbered
2279 register for the address of the target function. Make sure that all
2280 such registers are not used for passing parameters. */
2281 if (!decl && !TARGET_64BIT)
2285 /* We're looking at the CALL_EXPR, we need the type of the function. */
2286 type = TREE_OPERAND (exp, 0); /* pointer expression */
2287 type = TREE_TYPE (type); /* pointer type */
2288 type = TREE_TYPE (type); /* function type */
2290 if (ix86_function_regparm (type, NULL) >= 3)
2292 /* ??? Need to count the actual number of registers to be used,
2293 not the possible number of registers. Fix later. */
2298 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2299 /* Dllimport'd functions are also called indirectly. */
2300 if (decl && DECL_DLLIMPORT_P (decl)
2301 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2305 /* If we forced aligned the stack, then sibcalling would unalign the
2306 stack, which may break the called function. */
2307 if (cfun->machine->force_align_arg_pointer)
2310 /* Otherwise okay. That also includes certain types of indirect calls. */
2314 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2315 calling convention attributes;
2316 arguments as in struct attribute_spec.handler. */
2319 ix86_handle_cconv_attribute (tree *node, tree name,
2321 int flags ATTRIBUTE_UNUSED,
2324 if (TREE_CODE (*node) != FUNCTION_TYPE
2325 && TREE_CODE (*node) != METHOD_TYPE
2326 && TREE_CODE (*node) != FIELD_DECL
2327 && TREE_CODE (*node) != TYPE_DECL)
2329 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2330 IDENTIFIER_POINTER (name));
2331 *no_add_attrs = true;
2335 /* Can combine regparm with all attributes but fastcall. */
2336 if (is_attribute_p ("regparm", name))
2340 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2342 error ("fastcall and regparm attributes are not compatible");
2345 cst = TREE_VALUE (args);
2346 if (TREE_CODE (cst) != INTEGER_CST)
2348 warning (OPT_Wattributes,
2349 "%qs attribute requires an integer constant argument",
2350 IDENTIFIER_POINTER (name));
2351 *no_add_attrs = true;
2353 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2355 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2356 IDENTIFIER_POINTER (name), REGPARM_MAX);
2357 *no_add_attrs = true;
2361 && lookup_attribute (ix86_force_align_arg_pointer_string,
2362 TYPE_ATTRIBUTES (*node))
2363 && compare_tree_int (cst, REGPARM_MAX-1))
2365 error ("%s functions limited to %d register parameters",
2366 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
2374 warning (OPT_Wattributes, "%qs attribute ignored",
2375 IDENTIFIER_POINTER (name));
2376 *no_add_attrs = true;
2380 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2381 if (is_attribute_p ("fastcall", name))
2383 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2385 error ("fastcall and cdecl attributes are not compatible");
2387 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2389 error ("fastcall and stdcall attributes are not compatible");
2391 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2393 error ("fastcall and regparm attributes are not compatible");
2397 /* Can combine stdcall with fastcall (redundant), regparm and
2399 else if (is_attribute_p ("stdcall", name))
2401 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2403 error ("stdcall and cdecl attributes are not compatible");
2405 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2407 error ("stdcall and fastcall attributes are not compatible");
2411 /* Can combine cdecl with regparm and sseregparm. */
2412 else if (is_attribute_p ("cdecl", name))
2414 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2416 error ("stdcall and cdecl attributes are not compatible");
2418 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2420 error ("fastcall and cdecl attributes are not compatible");
2424 /* Can combine sseregparm with all attributes. */
2429 /* Return 0 if the attributes for two types are incompatible, 1 if they
2430 are compatible, and 2 if they are nearly compatible (which causes a
2431 warning to be generated). */
2434 ix86_comp_type_attributes (tree type1, tree type2)
2436 /* Check for mismatch of non-default calling convention. */
2437 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2439 if (TREE_CODE (type1) != FUNCTION_TYPE)
2442 /* Check for mismatched fastcall/regparm types. */
2443 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2444 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2445 || (ix86_function_regparm (type1, NULL)
2446 != ix86_function_regparm (type2, NULL)))
2449 /* Check for mismatched sseregparm types. */
2450 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2451 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2454 /* Check for mismatched return types (cdecl vs stdcall). */
2455 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2456 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2462 /* Return the regparm value for a function with the indicated TYPE and DECL.
2463 DECL may be NULL when calling function indirectly
2464 or considering a libcall. */
2467 ix86_function_regparm (tree type, tree decl)
2470 int regparm = ix86_regparm;
2471 bool user_convention = false;
2475 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2478 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2479 user_convention = true;
2482 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2485 user_convention = true;
2488 /* Use register calling convention for local functions when possible. */
2489 if (!TARGET_64BIT && !user_convention && decl
2490 && flag_unit_at_a_time && !profile_flag)
2492 struct cgraph_local_info *i = cgraph_local_info (decl);
2495 int local_regparm, globals = 0, regno;
2497 /* Make sure no regparm register is taken by a global register
2499 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2500 if (global_regs[local_regparm])
2502 /* We can't use regparm(3) for nested functions as these use
2503 static chain pointer in third argument. */
2504 if (local_regparm == 3
2505 && decl_function_context (decl)
2506 && !DECL_NO_STATIC_CHAIN (decl))
2508 /* If the function realigns its stackpointer, the
2509 prologue will clobber %ecx. If we've already
2510 generated code for the callee, the callee
2511 DECL_STRUCT_FUNCTION is gone, so we fall back to
2512 scanning the attributes for the self-realigning
2514 if ((DECL_STRUCT_FUNCTION (decl)
2515 && DECL_STRUCT_FUNCTION (decl)->machine->force_align_arg_pointer)
2516 || (!DECL_STRUCT_FUNCTION (decl)
2517 && lookup_attribute (ix86_force_align_arg_pointer_string,
2518 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
2520 /* Each global register variable increases register preassure,
2521 so the more global reg vars there are, the smaller regparm
2522 optimization use, unless requested by the user explicitly. */
2523 for (regno = 0; regno < 6; regno++)
2524 if (global_regs[regno])
2527 = globals < local_regparm ? local_regparm - globals : 0;
2529 if (local_regparm > regparm)
2530 regparm = local_regparm;
2537 /* Return 1 or 2, if we can pass up to 8 SFmode (1) and DFmode (2) arguments
2538 in SSE registers for a function with the indicated TYPE and DECL.
2539 DECL may be NULL when calling function indirectly
2540 or considering a libcall. Otherwise return 0. */
2543 ix86_function_sseregparm (tree type, tree decl)
2545 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2546 by the sseregparm attribute. */
2547 if (TARGET_SSEREGPARM
2549 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2554 error ("Calling %qD with attribute sseregparm without "
2555 "SSE/SSE2 enabled", decl);
2557 error ("Calling %qT with attribute sseregparm without "
2558 "SSE/SSE2 enabled", type);
2565 /* For local functions, pass SFmode (and DFmode for SSE2) arguments
2566 in SSE registers even for 32-bit mode and not just 3, but up to
2567 8 SSE arguments in registers. */
2568 if (!TARGET_64BIT && decl
2569 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2571 struct cgraph_local_info *i = cgraph_local_info (decl);
2573 return TARGET_SSE2 ? 2 : 1;
2579 /* Return true if EAX is live at the start of the function. Used by
2580 ix86_expand_prologue to determine if we need special help before
2581 calling allocate_stack_worker. */
2584 ix86_eax_live_at_start_p (void)
2586 /* Cheat. Don't bother working forward from ix86_function_regparm
2587 to the function type to whether an actual argument is located in
2588 eax. Instead just look at cfg info, which is still close enough
2589 to correct at this point. This gives false positives for broken
2590 functions that might use uninitialized data that happens to be
2591 allocated in eax, but who cares? */
2592 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2595 /* Value is the number of bytes of arguments automatically
2596 popped when returning from a subroutine call.
2597 FUNDECL is the declaration node of the function (as a tree),
2598 FUNTYPE is the data type of the function (as a tree),
2599 or for a library call it is an identifier node for the subroutine name.
2600 SIZE is the number of bytes of arguments passed on the stack.
2602 On the 80386, the RTD insn may be used to pop them if the number
2603 of args is fixed, but if the number is variable then the caller
2604 must pop them all. RTD can't be used for library calls now
2605 because the library is compiled with the Unix compiler.
2606 Use of RTD is a selectable option, since it is incompatible with
2607 standard Unix calling sequences. If the option is not selected,
2608 the caller must always pop the args.
2610 The attribute stdcall is equivalent to RTD on a per module basis. */
2613 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2615 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2617 /* Cdecl functions override -mrtd, and never pop the stack. */
2618 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2620 /* Stdcall and fastcall functions will pop the stack if not
2622 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2623 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2627 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2628 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2629 == void_type_node)))
2633 /* Lose any fake structure return argument if it is passed on the stack. */
2634 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2636 && !KEEP_AGGREGATE_RETURN_POINTER)
2638 int nregs = ix86_function_regparm (funtype, fundecl);
2641 return GET_MODE_SIZE (Pmode);
2647 /* Argument support functions. */
2649 /* Return true when register may be used to pass function parameters. */
2651 ix86_function_arg_regno_p (int regno)
2655 return (regno < REGPARM_MAX
2656 || (TARGET_MMX && MMX_REGNO_P (regno)
2657 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2658 || (TARGET_SSE && SSE_REGNO_P (regno)
2659 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2661 if (TARGET_SSE && SSE_REGNO_P (regno)
2662 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2664 /* RAX is used as hidden argument to va_arg functions. */
2667 for (i = 0; i < REGPARM_MAX; i++)
2668 if (regno == x86_64_int_parameter_registers[i])
2673 /* Return if we do not know how to pass TYPE solely in registers. */
2676 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2678 if (must_pass_in_stack_var_size_or_pad (mode, type))
2681 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2682 The layout_type routine is crafty and tries to trick us into passing
2683 currently unsupported vector types on the stack by using TImode. */
2684 return (!TARGET_64BIT && mode == TImode
2685 && type && TREE_CODE (type) != VECTOR_TYPE);
2688 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2689 for a call to a function whose data type is FNTYPE.
2690 For a library call, FNTYPE is 0. */
2693 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2694 tree fntype, /* tree ptr for function decl */
2695 rtx libname, /* SYMBOL_REF of library name or 0 */
2698 static CUMULATIVE_ARGS zero_cum;
2699 tree param, next_param;
2701 if (TARGET_DEBUG_ARG)
2703 fprintf (stderr, "\ninit_cumulative_args (");
2705 fprintf (stderr, "fntype code = %s, ret code = %s",
2706 tree_code_name[(int) TREE_CODE (fntype)],
2707 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
2709 fprintf (stderr, "no fntype");
2712 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
2717 /* Set up the number of registers to use for passing arguments. */
2718 cum->nregs = ix86_regparm;
2720 cum->sse_nregs = SSE_REGPARM_MAX;
2722 cum->mmx_nregs = MMX_REGPARM_MAX;
2723 cum->warn_sse = true;
2724 cum->warn_mmx = true;
2725 cum->maybe_vaarg = false;
2727 /* Use ecx and edx registers if function has fastcall attribute,
2728 else look for regparm information. */
2729 if (fntype && !TARGET_64BIT)
2731 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
2737 cum->nregs = ix86_function_regparm (fntype, fndecl);
2740 /* Set up the number of SSE registers used for passing SFmode
2741 and DFmode arguments. Warn for mismatching ABI. */
2742 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
2744 /* Determine if this function has variable arguments. This is
2745 indicated by the last argument being 'void_type_mode' if there
2746 are no variable arguments. If there are variable arguments, then
2747 we won't pass anything in registers in 32-bit mode. */
2749 if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
2751 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2752 param != 0; param = next_param)
2754 next_param = TREE_CHAIN (param);
2755 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
2765 cum->float_in_sse = 0;
2767 cum->maybe_vaarg = true;
2771 if ((!fntype && !libname)
2772 || (fntype && !TYPE_ARG_TYPES (fntype)))
2773 cum->maybe_vaarg = true;
2775 if (TARGET_DEBUG_ARG)
2776 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
2781 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
2782 But in the case of vector types, it is some vector mode.
2784 When we have only some of our vector isa extensions enabled, then there
2785 are some modes for which vector_mode_supported_p is false. For these
2786 modes, the generic vector support in gcc will choose some non-vector mode
2787 in order to implement the type. By computing the natural mode, we'll
2788 select the proper ABI location for the operand and not depend on whatever
2789 the middle-end decides to do with these vector types. */
2791 static enum machine_mode
2792 type_natural_mode (tree type)
2794 enum machine_mode mode = TYPE_MODE (type);
2796 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
2798 HOST_WIDE_INT size = int_size_in_bytes (type);
2799 if ((size == 8 || size == 16)
2800 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
2801 && TYPE_VECTOR_SUBPARTS (type) > 1)
2803 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
2805 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
2806 mode = MIN_MODE_VECTOR_FLOAT;
2808 mode = MIN_MODE_VECTOR_INT;
2810 /* Get the mode which has this inner mode and number of units. */
2811 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
2812 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
2813 && GET_MODE_INNER (mode) == innermode)
2823 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
2824 this may not agree with the mode that the type system has chosen for the
2825 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
2826 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
2829 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
2834 if (orig_mode != BLKmode)
2835 tmp = gen_rtx_REG (orig_mode, regno);
2838 tmp = gen_rtx_REG (mode, regno);
2839 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
2840 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
2846 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2847 of this code is to classify each 8bytes of incoming argument by the register
2848 class and assign registers accordingly. */
2850 /* Return the union class of CLASS1 and CLASS2.
2851 See the x86-64 PS ABI for details. */
2853 static enum x86_64_reg_class
2854 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
2856 /* Rule #1: If both classes are equal, this is the resulting class. */
2857 if (class1 == class2)
2860 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2862 if (class1 == X86_64_NO_CLASS)
2864 if (class2 == X86_64_NO_CLASS)
2867 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2868 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
2869 return X86_64_MEMORY_CLASS;
2871 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2872 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
2873 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
2874 return X86_64_INTEGERSI_CLASS;
2875 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
2876 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
2877 return X86_64_INTEGER_CLASS;
2879 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
2881 if (class1 == X86_64_X87_CLASS
2882 || class1 == X86_64_X87UP_CLASS
2883 || class1 == X86_64_COMPLEX_X87_CLASS
2884 || class2 == X86_64_X87_CLASS
2885 || class2 == X86_64_X87UP_CLASS
2886 || class2 == X86_64_COMPLEX_X87_CLASS)
2887 return X86_64_MEMORY_CLASS;
2889 /* Rule #6: Otherwise class SSE is used. */
2890 return X86_64_SSE_CLASS;
2893 /* Classify the argument of type TYPE and mode MODE.
2894 CLASSES will be filled by the register class used to pass each word
2895 of the operand. The number of words is returned. In case the parameter
2896 should be passed in memory, 0 is returned. As a special case for zero
2897 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2899 BIT_OFFSET is used internally for handling records and specifies offset
2900 of the offset in bits modulo 256 to avoid overflow cases.
2902 See the x86-64 PS ABI for details.
2906 classify_argument (enum machine_mode mode, tree type,
2907 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
2909 HOST_WIDE_INT bytes =
2910 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2911 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2913 /* Variable sized entities are always passed/returned in memory. */
2917 if (mode != VOIDmode
2918 && targetm.calls.must_pass_in_stack (mode, type))
2921 if (type && AGGREGATE_TYPE_P (type))
2925 enum x86_64_reg_class subclasses[MAX_CLASSES];
2927 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2931 for (i = 0; i < words; i++)
2932 classes[i] = X86_64_NO_CLASS;
2934 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2935 signalize memory class, so handle it as special case. */
2938 classes[0] = X86_64_NO_CLASS;
2942 /* Classify each field of record and merge classes. */
2943 switch (TREE_CODE (type))
2946 /* For classes first merge in the field of the subclasses. */
2947 if (TYPE_BINFO (type))
2949 tree binfo, base_binfo;
2952 for (binfo = TYPE_BINFO (type), basenum = 0;
2953 BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
2956 int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
2957 tree type = BINFO_TYPE (base_binfo);
2959 num = classify_argument (TYPE_MODE (type),
2961 (offset + bit_offset) % 256);
2964 for (i = 0; i < num; i++)
2966 int pos = (offset + (bit_offset % 64)) / 8 / 8;
2968 merge_classes (subclasses[i], classes[i + pos]);
2972 /* And now merge the fields of structure. */
2973 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2975 if (TREE_CODE (field) == FIELD_DECL)
2979 if (TREE_TYPE (field) == error_mark_node)
2982 /* Bitfields are always classified as integer. Handle them
2983 early, since later code would consider them to be
2984 misaligned integers. */
2985 if (DECL_BIT_FIELD (field))
2987 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2988 i < ((int_bit_position (field) + (bit_offset % 64))
2989 + tree_low_cst (DECL_SIZE (field), 0)
2992 merge_classes (X86_64_INTEGER_CLASS,
2997 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2998 TREE_TYPE (field), subclasses,
2999 (int_bit_position (field)
3000 + bit_offset) % 256);
3003 for (i = 0; i < num; i++)
3006 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3008 merge_classes (subclasses[i], classes[i + pos]);
3016 /* Arrays are handled as small records. */
3019 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3020 TREE_TYPE (type), subclasses, bit_offset);
3024 /* The partial classes are now full classes. */
3025 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3026 subclasses[0] = X86_64_SSE_CLASS;
3027 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3028 subclasses[0] = X86_64_INTEGER_CLASS;
3030 for (i = 0; i < words; i++)
3031 classes[i] = subclasses[i % num];
3036 case QUAL_UNION_TYPE:
3037 /* Unions are similar to RECORD_TYPE but offset is always 0.
3040 /* Unions are not derived. */
3041 gcc_assert (!TYPE_BINFO (type)
3042 || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type)));
3043 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3045 if (TREE_CODE (field) == FIELD_DECL)
3048 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3049 TREE_TYPE (field), subclasses,
3053 for (i = 0; i < num; i++)
3054 classes[i] = merge_classes (subclasses[i], classes[i]);
3063 /* Final merger cleanup. */
3064 for (i = 0; i < words; i++)
3066 /* If one class is MEMORY, everything should be passed in
3068 if (classes[i] == X86_64_MEMORY_CLASS)
3071 /* The X86_64_SSEUP_CLASS should be always preceded by
3072 X86_64_SSE_CLASS. */
3073 if (classes[i] == X86_64_SSEUP_CLASS
3074 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3075 classes[i] = X86_64_SSE_CLASS;
3077 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3078 if (classes[i] == X86_64_X87UP_CLASS
3079 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3080 classes[i] = X86_64_SSE_CLASS;
3085 /* Compute alignment needed. We align all types to natural boundaries with
3086 exception of XFmode that is aligned to 64bits. */
3087 if (mode != VOIDmode && mode != BLKmode)
3089 int mode_alignment = GET_MODE_BITSIZE (mode);
3092 mode_alignment = 128;
3093 else if (mode == XCmode)
3094 mode_alignment = 256;
3095 if (COMPLEX_MODE_P (mode))
3096 mode_alignment /= 2;
3097 /* Misaligned fields are always returned in memory. */
3098 if (bit_offset % mode_alignment)
3102 /* for V1xx modes, just use the base mode */
3103 if (VECTOR_MODE_P (mode)
3104 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3105 mode = GET_MODE_INNER (mode);
3107 /* Classification of atomic types. */
3112 classes[0] = X86_64_SSE_CLASS;
3115 classes[0] = X86_64_SSE_CLASS;
3116 classes[1] = X86_64_SSEUP_CLASS;
3125 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3126 classes[0] = X86_64_INTEGERSI_CLASS;
3128 classes[0] = X86_64_INTEGER_CLASS;
3132 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3137 if (!(bit_offset % 64))
3138 classes[0] = X86_64_SSESF_CLASS;
3140 classes[0] = X86_64_SSE_CLASS;
3143 classes[0] = X86_64_SSEDF_CLASS;
3146 classes[0] = X86_64_X87_CLASS;
3147 classes[1] = X86_64_X87UP_CLASS;
3150 classes[0] = X86_64_SSE_CLASS;
3151 classes[1] = X86_64_SSEUP_CLASS;
3154 classes[0] = X86_64_SSE_CLASS;
3157 classes[0] = X86_64_SSEDF_CLASS;
3158 classes[1] = X86_64_SSEDF_CLASS;
3161 classes[0] = X86_64_COMPLEX_X87_CLASS;
3164 /* This modes is larger than 16 bytes. */
3172 classes[0] = X86_64_SSE_CLASS;
3173 classes[1] = X86_64_SSEUP_CLASS;
3179 classes[0] = X86_64_SSE_CLASS;
3185 gcc_assert (VECTOR_MODE_P (mode));
3190 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3192 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3193 classes[0] = X86_64_INTEGERSI_CLASS;
3195 classes[0] = X86_64_INTEGER_CLASS;
3196 classes[1] = X86_64_INTEGER_CLASS;
3197 return 1 + (bytes > 8);
3201 /* Examine the argument and return set number of register required in each
3202 class. Return 0 iff parameter should be passed in memory. */
3204 examine_argument (enum machine_mode mode, tree type, int in_return,
3205 int *int_nregs, int *sse_nregs)
3207 enum x86_64_reg_class class[MAX_CLASSES];
3208 int n = classify_argument (mode, type, class, 0);
3214 for (n--; n >= 0; n--)
3217 case X86_64_INTEGER_CLASS:
3218 case X86_64_INTEGERSI_CLASS:
3221 case X86_64_SSE_CLASS:
3222 case X86_64_SSESF_CLASS:
3223 case X86_64_SSEDF_CLASS:
3226 case X86_64_NO_CLASS:
3227 case X86_64_SSEUP_CLASS:
3229 case X86_64_X87_CLASS:
3230 case X86_64_X87UP_CLASS:
3234 case X86_64_COMPLEX_X87_CLASS:
3235 return in_return ? 2 : 0;
3236 case X86_64_MEMORY_CLASS:
3242 /* Construct container for the argument used by GCC interface. See
3243 FUNCTION_ARG for the detailed description. */
3246 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3247 tree type, int in_return, int nintregs, int nsseregs,
3248 const int *intreg, int sse_regno)
3250 enum machine_mode tmpmode;
3252 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3253 enum x86_64_reg_class class[MAX_CLASSES];
3257 int needed_sseregs, needed_intregs;
3258 rtx exp[MAX_CLASSES];
3261 n = classify_argument (mode, type, class, 0);
3262 if (TARGET_DEBUG_ARG)
3265 fprintf (stderr, "Memory class\n");
3268 fprintf (stderr, "Classes:");
3269 for (i = 0; i < n; i++)
3271 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
3273 fprintf (stderr, "\n");
3278 if (!examine_argument (mode, type, in_return, &needed_intregs,
3281 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3284 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3285 some less clueful developer tries to use floating-point anyway. */
3286 if (needed_sseregs && !TARGET_SSE)
3288 static bool issued_error;
3291 issued_error = true;
3293 error ("SSE register return with SSE disabled");
3295 error ("SSE register argument with SSE disabled");
3300 /* First construct simple cases. Avoid SCmode, since we want to use
3301 single register to pass this type. */
3302 if (n == 1 && mode != SCmode)
3305 case X86_64_INTEGER_CLASS:
3306 case X86_64_INTEGERSI_CLASS:
3307 return gen_rtx_REG (mode, intreg[0]);
3308 case X86_64_SSE_CLASS:
3309 case X86_64_SSESF_CLASS:
3310 case X86_64_SSEDF_CLASS:
3311 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3312 case X86_64_X87_CLASS:
3313 case X86_64_COMPLEX_X87_CLASS:
3314 return gen_rtx_REG (mode, FIRST_STACK_REG);
3315 case X86_64_NO_CLASS:
3316 /* Zero sized array, struct or class. */
3321 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
3323 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3325 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
3326 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3327 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
3328 && class[1] == X86_64_INTEGER_CLASS
3329 && (mode == CDImode || mode == TImode || mode == TFmode)
3330 && intreg[0] + 1 == intreg[1])
3331 return gen_rtx_REG (mode, intreg[0]);
3333 /* Otherwise figure out the entries of the PARALLEL. */
3334 for (i = 0; i < n; i++)
3338 case X86_64_NO_CLASS:
3340 case X86_64_INTEGER_CLASS:
3341 case X86_64_INTEGERSI_CLASS:
3342 /* Merge TImodes on aligned occasions here too. */
3343 if (i * 8 + 8 > bytes)
3344 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3345 else if (class[i] == X86_64_INTEGERSI_CLASS)
3349 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3350 if (tmpmode == BLKmode)
3352 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3353 gen_rtx_REG (tmpmode, *intreg),
3357 case X86_64_SSESF_CLASS:
3358 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3359 gen_rtx_REG (SFmode,
3360 SSE_REGNO (sse_regno)),
3364 case X86_64_SSEDF_CLASS:
3365 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3366 gen_rtx_REG (DFmode,
3367 SSE_REGNO (sse_regno)),
3371 case X86_64_SSE_CLASS:
3372 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3376 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3377 gen_rtx_REG (tmpmode,
3378 SSE_REGNO (sse_regno)),
3380 if (tmpmode == TImode)
3389 /* Empty aligned struct, union or class. */
3393 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3394 for (i = 0; i < nexps; i++)
3395 XVECEXP (ret, 0, i) = exp [i];
3399 /* Update the data in CUM to advance over an argument
3400 of mode MODE and data type TYPE.
3401 (TYPE is null for libcalls where that information may not be available.) */
3404 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3405 tree type, int named)
3408 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3409 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3412 mode = type_natural_mode (type);
3414 if (TARGET_DEBUG_ARG)
3415 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3416 "mode=%s, named=%d)\n\n",
3417 words, cum->words, cum->nregs, cum->sse_nregs,
3418 GET_MODE_NAME (mode), named);
3422 int int_nregs, sse_nregs;
3423 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3424 cum->words += words;
3425 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3427 cum->nregs -= int_nregs;
3428 cum->sse_nregs -= sse_nregs;
3429 cum->regno += int_nregs;
3430 cum->sse_regno += sse_nregs;
3433 cum->words += words;
3451 cum->words += words;
3452 cum->nregs -= words;
3453 cum->regno += words;
3455 if (cum->nregs <= 0)
3463 if (cum->float_in_sse < 2)
3466 if (cum->float_in_sse < 1)
3477 if (!type || !AGGREGATE_TYPE_P (type))
3479 cum->sse_words += words;
3480 cum->sse_nregs -= 1;
3481 cum->sse_regno += 1;
3482 if (cum->sse_nregs <= 0)
3494 if (!type || !AGGREGATE_TYPE_P (type))
3496 cum->mmx_words += words;
3497 cum->mmx_nregs -= 1;
3498 cum->mmx_regno += 1;
3499 if (cum->mmx_nregs <= 0)
3510 /* Define where to put the arguments to a function.
3511 Value is zero to push the argument on the stack,
3512 or a hard register in which to store the argument.
3514 MODE is the argument's machine mode.
3515 TYPE is the data type of the argument (as a tree).
3516 This is null for libcalls where that information may
3518 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3519 the preceding args and about the function being called.
3520 NAMED is nonzero if this argument is a named parameter
3521 (otherwise it is an extra parameter matching an ellipsis). */
3524 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3525 tree type, int named)
3527 enum machine_mode mode = orig_mode;
3530 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3531 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3532 static bool warnedsse, warnedmmx;
3534 /* To simplify the code below, represent vector types with a vector mode
3535 even if MMX/SSE are not active. */
3536 if (type && TREE_CODE (type) == VECTOR_TYPE)
3537 mode = type_natural_mode (type);
3539 /* Handle a hidden AL argument containing number of registers for varargs
3540 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3542 if (mode == VOIDmode)
3545 return GEN_INT (cum->maybe_vaarg
3546 ? (cum->sse_nregs < 0
3554 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3556 &x86_64_int_parameter_registers [cum->regno],
3561 /* For now, pass fp/complex values on the stack. */
3573 if (words <= cum->nregs)
3575 int regno = cum->regno;
3577 /* Fastcall allocates the first two DWORD (SImode) or
3578 smaller arguments to ECX and EDX. */
3581 if (mode == BLKmode || mode == DImode)
3584 /* ECX not EAX is the first allocated register. */
3588 ret = gen_rtx_REG (mode, regno);
3592 if (cum->float_in_sse < 2)
3595 if (cum->float_in_sse < 1)
3605 if (!type || !AGGREGATE_TYPE_P (type))
3607 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3610 warning (0, "SSE vector argument without SSE enabled "
3614 ret = gen_reg_or_parallel (mode, orig_mode,
3615 cum->sse_regno + FIRST_SSE_REG);
3622 if (!type || !AGGREGATE_TYPE_P (type))
3624 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3627 warning (0, "MMX vector argument without MMX enabled "
3631 ret = gen_reg_or_parallel (mode, orig_mode,
3632 cum->mmx_regno + FIRST_MMX_REG);
3637 if (TARGET_DEBUG_ARG)
3640 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3641 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
3644 print_simple_rtl (stderr, ret);
3646 fprintf (stderr, ", stack");
3648 fprintf (stderr, " )\n");
3654 /* A C expression that indicates when an argument must be passed by
3655 reference. If nonzero for an argument, a copy of that argument is
3656 made in memory and a pointer to the argument is passed instead of
3657 the argument itself. The pointer is passed in whatever way is
3658 appropriate for passing a pointer to that type. */
3661 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3662 enum machine_mode mode ATTRIBUTE_UNUSED,
3663 tree type, bool named ATTRIBUTE_UNUSED)
3668 if (type && int_size_in_bytes (type) == -1)
3670 if (TARGET_DEBUG_ARG)
3671 fprintf (stderr, "function_arg_pass_by_reference\n");
3678 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
3679 ABI. Only called if TARGET_SSE. */
3681 contains_128bit_aligned_vector_p (tree type)
3683 enum machine_mode mode = TYPE_MODE (type);
3684 if (SSE_REG_MODE_P (mode)
3685 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
3687 if (TYPE_ALIGN (type) < 128)
3690 if (AGGREGATE_TYPE_P (type))
3692 /* Walk the aggregates recursively. */
3693 switch (TREE_CODE (type))
3697 case QUAL_UNION_TYPE:
3701 if (TYPE_BINFO (type))
3703 tree binfo, base_binfo;
3706 for (binfo = TYPE_BINFO (type), i = 0;
3707 BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
3708 if (contains_128bit_aligned_vector_p
3709 (BINFO_TYPE (base_binfo)))
3712 /* And now merge the fields of structure. */
3713 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3715 if (TREE_CODE (field) == FIELD_DECL
3716 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
3723 /* Just for use if some languages passes arrays by value. */
3724 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
3735 /* Gives the alignment boundary, in bits, of an argument with the
3736 specified mode and type. */
3739 ix86_function_arg_boundary (enum machine_mode mode, tree type)
3743 align = TYPE_ALIGN (type);
3745 align = GET_MODE_ALIGNMENT (mode);
3746 if (align < PARM_BOUNDARY)
3747 align = PARM_BOUNDARY;
3750 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
3751 make an exception for SSE modes since these require 128bit
3754 The handling here differs from field_alignment. ICC aligns MMX
3755 arguments to 4 byte boundaries, while structure fields are aligned
3756 to 8 byte boundaries. */
3758 align = PARM_BOUNDARY;
3761 if (!SSE_REG_MODE_P (mode))
3762 align = PARM_BOUNDARY;
3766 if (!contains_128bit_aligned_vector_p (type))
3767 align = PARM_BOUNDARY;
3775 /* Return true if N is a possible register number of function value. */
3777 ix86_function_value_regno_p (int regno)
3780 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
3781 || (regno == FIRST_SSE_REG && TARGET_SSE))
3785 && (regno == FIRST_MMX_REG && TARGET_MMX))
3791 /* Define how to find the value returned by a function.
3792 VALTYPE is the data type of the value (as a tree).
3793 If the precise function being called is known, FUNC is its FUNCTION_DECL;
3794 otherwise, FUNC is 0. */
3796 ix86_function_value (tree valtype, tree fntype_or_decl,
3797 bool outgoing ATTRIBUTE_UNUSED)
3799 enum machine_mode natmode = type_natural_mode (valtype);
3803 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
3804 1, REGPARM_MAX, SSE_REGPARM_MAX,
3805 x86_64_int_return_registers, 0);
3806 /* For zero sized structures, construct_container return NULL, but we
3807 need to keep rest of compiler happy by returning meaningful value. */
3809 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
3814 tree fn = NULL_TREE, fntype;
3816 && DECL_P (fntype_or_decl))
3817 fn = fntype_or_decl;
3818 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
3819 return gen_rtx_REG (TYPE_MODE (valtype),
3820 ix86_value_regno (natmode, fn, fntype));
3824 /* Return true iff type is returned in memory. */
3826 ix86_return_in_memory (tree type)
3828 int needed_intregs, needed_sseregs, size;
3829 enum machine_mode mode = type_natural_mode (type);
3832 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
3834 if (mode == BLKmode)
3837 size = int_size_in_bytes (type);
3839 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
3842 if (VECTOR_MODE_P (mode) || mode == TImode)
3844 /* User-created vectors small enough to fit in EAX. */
3848 /* MMX/3dNow values are returned in MM0,
3849 except when it doesn't exits. */
3851 return (TARGET_MMX ? 0 : 1);
3853 /* SSE values are returned in XMM0, except when it doesn't exist. */
3855 return (TARGET_SSE ? 0 : 1);
3869 /* When returning SSE vector types, we have a choice of either
3870 (1) being abi incompatible with a -march switch, or
3871 (2) generating an error.
3872 Given no good solution, I think the safest thing is one warning.
3873 The user won't be able to use -Werror, but....
3875 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3876 called in response to actually generating a caller or callee that
3877 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3878 via aggregate_value_p for general type probing from tree-ssa. */
3881 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
3883 static bool warnedsse, warnedmmx;
3887 /* Look at the return type of the function, not the function type. */
3888 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
3890 if (!TARGET_SSE && !warnedsse)
3893 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3896 warning (0, "SSE vector return without SSE enabled "
3901 if (!TARGET_MMX && !warnedmmx)
3903 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
3906 warning (0, "MMX vector return without MMX enabled "
3915 /* Define how to find the value returned by a library function
3916 assuming the value has mode MODE. */
3918 ix86_libcall_value (enum machine_mode mode)
3932 return gen_rtx_REG (mode, FIRST_SSE_REG);
3935 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
3939 return gen_rtx_REG (mode, 0);
3943 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
3946 /* Given a mode, return the register to use for a return value. */
3949 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
3951 gcc_assert (!TARGET_64BIT);
3953 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
3954 we prevent this case when mmx is not available. */
3955 if ((VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8))
3956 return FIRST_MMX_REG;
3958 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3959 we prevent this case when sse is not available. */
3960 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3961 return FIRST_SSE_REG;
3963 /* Decimal floating point values can go in %eax, unlike other float modes. */
3964 if (DECIMAL_FLOAT_MODE_P (mode))
3967 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
3968 if (!SCALAR_FLOAT_MODE_P (mode) || !TARGET_FLOAT_RETURNS_IN_80387)
3971 /* Floating point return values in %st(0), except for local functions when
3972 SSE math is enabled or for functions with sseregparm attribute. */
3973 if ((func || fntype)
3974 && (mode == SFmode || mode == DFmode))
3976 int sse_level = ix86_function_sseregparm (fntype, func);
3977 if ((sse_level >= 1 && mode == SFmode)
3978 || (sse_level == 2 && mode == DFmode))
3979 return FIRST_SSE_REG;
3982 return FIRST_FLOAT_REG;
3985 /* Create the va_list data type. */
3988 ix86_build_builtin_va_list (void)
3990 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3992 /* For i386 we use plain pointer to argument area. */
3994 return build_pointer_type (char_type_node);
3996 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3997 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3999 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4000 unsigned_type_node);
4001 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4002 unsigned_type_node);
4003 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4005 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4008 va_list_gpr_counter_field = f_gpr;
4009 va_list_fpr_counter_field = f_fpr;
4011 DECL_FIELD_CONTEXT (f_gpr) = record;
4012 DECL_FIELD_CONTEXT (f_fpr) = record;
4013 DECL_FIELD_CONTEXT (f_ovf) = record;
4014 DECL_FIELD_CONTEXT (f_sav) = record;
4016 TREE_CHAIN (record) = type_decl;
4017 TYPE_NAME (record) = type_decl;
4018 TYPE_FIELDS (record) = f_gpr;
4019 TREE_CHAIN (f_gpr) = f_fpr;
4020 TREE_CHAIN (f_fpr) = f_ovf;
4021 TREE_CHAIN (f_ovf) = f_sav;
4023 layout_type (record);
4025 /* The correct type is an array type of one element. */
4026 return build_array_type (record, build_index_type (size_zero_node));
4029 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4032 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4033 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4036 CUMULATIVE_ARGS next_cum;
4037 rtx save_area = NULL_RTX, mem;
4050 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4053 /* Indicate to allocate space on the stack for varargs save area. */
4054 ix86_save_varrargs_registers = 1;
4056 cfun->stack_alignment_needed = 128;
4058 fntype = TREE_TYPE (current_function_decl);
4059 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
4060 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4061 != void_type_node));
4063 /* For varargs, we do not want to skip the dummy va_dcl argument.
4064 For stdargs, we do want to skip the last named argument. */
4067 function_arg_advance (&next_cum, mode, type, 1);
4070 save_area = frame_pointer_rtx;
4072 set = get_varargs_alias_set ();
4074 for (i = next_cum.regno;
4076 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4079 mem = gen_rtx_MEM (Pmode,
4080 plus_constant (save_area, i * UNITS_PER_WORD));
4081 MEM_NOTRAP_P (mem) = 1;
4082 set_mem_alias_set (mem, set);
4083 emit_move_insn (mem, gen_rtx_REG (Pmode,
4084 x86_64_int_parameter_registers[i]));
4087 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
4089 /* Now emit code to save SSE registers. The AX parameter contains number
4090 of SSE parameter registers used to call this function. We use
4091 sse_prologue_save insn template that produces computed jump across
4092 SSE saves. We need some preparation work to get this working. */
4094 label = gen_label_rtx ();
4095 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4097 /* Compute address to jump to :
4098 label - 5*eax + nnamed_sse_arguments*5 */
4099 tmp_reg = gen_reg_rtx (Pmode);
4100 nsse_reg = gen_reg_rtx (Pmode);
4101 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
4102 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4103 gen_rtx_MULT (Pmode, nsse_reg,
4105 if (next_cum.sse_regno)
4108 gen_rtx_CONST (DImode,
4109 gen_rtx_PLUS (DImode,
4111 GEN_INT (next_cum.sse_regno * 4))));
4113 emit_move_insn (nsse_reg, label_ref);
4114 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4116 /* Compute address of memory block we save into. We always use pointer
4117 pointing 127 bytes after first byte to store - this is needed to keep
4118 instruction size limited by 4 bytes. */
4119 tmp_reg = gen_reg_rtx (Pmode);
4120 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4121 plus_constant (save_area,
4122 8 * REGPARM_MAX + 127)));
4123 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4124 MEM_NOTRAP_P (mem) = 1;
4125 set_mem_alias_set (mem, set);
4126 set_mem_align (mem, BITS_PER_WORD);
4128 /* And finally do the dirty job! */
4129 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4130 GEN_INT (next_cum.sse_regno), label));
4135 /* Implement va_start. */
4138 ix86_va_start (tree valist, rtx nextarg)
4140 HOST_WIDE_INT words, n_gpr, n_fpr;
4141 tree f_gpr, f_fpr, f_ovf, f_sav;
4142 tree gpr, fpr, ovf, sav, t;
4145 /* Only 64bit target needs something special. */
4148 std_expand_builtin_va_start (valist, nextarg);
4152 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4153 f_fpr = TREE_CHAIN (f_gpr);
4154 f_ovf = TREE_CHAIN (f_fpr);
4155 f_sav = TREE_CHAIN (f_ovf);
4157 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4158 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4159 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4160 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4161 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4163 /* Count number of gp and fp argument registers used. */
4164 words = current_function_args_info.words;
4165 n_gpr = current_function_args_info.regno;
4166 n_fpr = current_function_args_info.sse_regno;
4168 if (TARGET_DEBUG_ARG)
4169 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
4170 (int) words, (int) n_gpr, (int) n_fpr);
4172 if (cfun->va_list_gpr_size)
4174 type = TREE_TYPE (gpr);
4175 t = build2 (MODIFY_EXPR, type, gpr,
4176 build_int_cst (type, n_gpr * 8));
4177 TREE_SIDE_EFFECTS (t) = 1;
4178 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4181 if (cfun->va_list_fpr_size)
4183 type = TREE_TYPE (fpr);
4184 t = build2 (MODIFY_EXPR, type, fpr,
4185 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
4186 TREE_SIDE_EFFECTS (t) = 1;
4187 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4190 /* Find the overflow area. */
4191 type = TREE_TYPE (ovf);
4192 t = make_tree (type, virtual_incoming_args_rtx);
4194 t = build2 (PLUS_EXPR, type, t,
4195 build_int_cst (type, words * UNITS_PER_WORD));
4196 t = build2 (MODIFY_EXPR, type, ovf, t);
4197 TREE_SIDE_EFFECTS (t) = 1;
4198 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4200 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
4202 /* Find the register save area.
4203 Prologue of the function save it right above stack frame. */
4204 type = TREE_TYPE (sav);
4205 t = make_tree (type, frame_pointer_rtx);
4206 t = build2 (MODIFY_EXPR, type, sav, t);
4207 TREE_SIDE_EFFECTS (t) = 1;
4208 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4212 /* Implement va_arg. */
4215 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4217 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
4218 tree f_gpr, f_fpr, f_ovf, f_sav;
4219 tree gpr, fpr, ovf, sav, t;
4221 tree lab_false, lab_over = NULL_TREE;
4226 enum machine_mode nat_mode;
4228 /* Only 64bit target needs something special. */
4230 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4232 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4233 f_fpr = TREE_CHAIN (f_gpr);
4234 f_ovf = TREE_CHAIN (f_fpr);
4235 f_sav = TREE_CHAIN (f_ovf);
4237 valist = build_va_arg_indirect_ref (valist);
4238 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4239 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4240 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4241 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4243 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
4245 type = build_pointer_type (type);
4246 size = int_size_in_bytes (type);
4247 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4249 nat_mode = type_natural_mode (type);
4250 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
4251 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
4253 /* Pull the value out of the saved registers. */
4255 addr = create_tmp_var (ptr_type_node, "addr");
4256 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
4260 int needed_intregs, needed_sseregs;
4262 tree int_addr, sse_addr;
4264 lab_false = create_artificial_label ();
4265 lab_over = create_artificial_label ();
4267 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
4269 need_temp = (!REG_P (container)
4270 && ((needed_intregs && TYPE_ALIGN (type) > 64)
4271 || TYPE_ALIGN (type) > 128));
4273 /* In case we are passing structure, verify that it is consecutive block
4274 on the register save area. If not we need to do moves. */
4275 if (!need_temp && !REG_P (container))
4277 /* Verify that all registers are strictly consecutive */
4278 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
4282 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4284 rtx slot = XVECEXP (container, 0, i);
4285 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
4286 || INTVAL (XEXP (slot, 1)) != i * 16)
4294 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4296 rtx slot = XVECEXP (container, 0, i);
4297 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
4298 || INTVAL (XEXP (slot, 1)) != i * 8)
4310 int_addr = create_tmp_var (ptr_type_node, "int_addr");
4311 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
4312 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
4313 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
4316 /* First ensure that we fit completely in registers. */
4319 t = build_int_cst (TREE_TYPE (gpr),
4320 (REGPARM_MAX - needed_intregs + 1) * 8);
4321 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
4322 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4323 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4324 gimplify_and_add (t, pre_p);
4328 t = build_int_cst (TREE_TYPE (fpr),
4329 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
4331 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
4332 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4333 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4334 gimplify_and_add (t, pre_p);
4337 /* Compute index to start of area used for integer regs. */
4340 /* int_addr = gpr + sav; */
4341 t = fold_convert (ptr_type_node, gpr);
4342 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4343 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
4344 gimplify_and_add (t, pre_p);
4348 /* sse_addr = fpr + sav; */
4349 t = fold_convert (ptr_type_node, fpr);
4350 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4351 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
4352 gimplify_and_add (t, pre_p);
4357 tree temp = create_tmp_var (type, "va_arg_tmp");
4360 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
4361 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
4362 gimplify_and_add (t, pre_p);
4364 for (i = 0; i < XVECLEN (container, 0); i++)
4366 rtx slot = XVECEXP (container, 0, i);
4367 rtx reg = XEXP (slot, 0);
4368 enum machine_mode mode = GET_MODE (reg);
4369 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
4370 tree addr_type = build_pointer_type (piece_type);
4373 tree dest_addr, dest;
4375 if (SSE_REGNO_P (REGNO (reg)))
4377 src_addr = sse_addr;
4378 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4382 src_addr = int_addr;
4383 src_offset = REGNO (reg) * 8;
4385 src_addr = fold_convert (addr_type, src_addr);
4386 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
4387 size_int (src_offset)));
4388 src = build_va_arg_indirect_ref (src_addr);
4390 dest_addr = fold_convert (addr_type, addr);
4391 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
4392 size_int (INTVAL (XEXP (slot, 1)))));
4393 dest = build_va_arg_indirect_ref (dest_addr);
4395 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
4396 gimplify_and_add (t, pre_p);
4402 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4403 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4404 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4405 gimplify_and_add (t, pre_p);
4409 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4410 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4411 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4412 gimplify_and_add (t, pre_p);
4415 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4416 gimplify_and_add (t, pre_p);
4418 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4419 append_to_statement_list (t, pre_p);
4422 /* ... otherwise out of the overflow area. */
4424 /* Care for on-stack alignment if needed. */
4425 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
4426 || integer_zerop (TYPE_SIZE (type)))
4430 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4431 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4432 build_int_cst (TREE_TYPE (ovf), align - 1));
4433 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4434 build_int_cst (TREE_TYPE (t), -align));
4436 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4438 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4439 gimplify_and_add (t2, pre_p);
4441 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4442 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4443 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4444 gimplify_and_add (t, pre_p);
4448 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4449 append_to_statement_list (t, pre_p);
4452 ptrtype = build_pointer_type (type);
4453 addr = fold_convert (ptrtype, addr);
4456 addr = build_va_arg_indirect_ref (addr);
4457 return build_va_arg_indirect_ref (addr);
4460 /* Return nonzero if OPNUM's MEM should be matched
4461 in movabs* patterns. */
4464 ix86_check_movabs (rtx insn, int opnum)
4468 set = PATTERN (insn);
4469 if (GET_CODE (set) == PARALLEL)
4470 set = XVECEXP (set, 0, 0);
4471 gcc_assert (GET_CODE (set) == SET);
4472 mem = XEXP (set, opnum);
4473 while (GET_CODE (mem) == SUBREG)
4474 mem = SUBREG_REG (mem);
4475 gcc_assert (GET_CODE (mem) == MEM);
4476 return (volatile_ok || !MEM_VOLATILE_P (mem));
4479 /* Initialize the table of extra 80387 mathematical constants. */
4482 init_ext_80387_constants (void)
4484 static const char * cst[5] =
4486 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4487 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4488 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4489 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4490 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4494 for (i = 0; i < 5; i++)
4496 real_from_string (&ext_80387_constants_table[i], cst[i]);
4497 /* Ensure each constant is rounded to XFmode precision. */
4498 real_convert (&ext_80387_constants_table[i],
4499 XFmode, &ext_80387_constants_table[i]);
4502 ext_80387_constants_init = 1;
4505 /* Return true if the constant is something that can be loaded with
4506 a special instruction. */
4509 standard_80387_constant_p (rtx x)
4511 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4514 if (x == CONST0_RTX (GET_MODE (x)))
4516 if (x == CONST1_RTX (GET_MODE (x)))
4519 /* For XFmode constants, try to find a special 80387 instruction when
4520 optimizing for size or on those CPUs that benefit from them. */
4521 if (GET_MODE (x) == XFmode
4522 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4527 if (! ext_80387_constants_init)
4528 init_ext_80387_constants ();
4530 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4531 for (i = 0; i < 5; i++)
4532 if (real_identical (&r, &ext_80387_constants_table[i]))
4539 /* Return the opcode of the special instruction to be used to load
4543 standard_80387_constant_opcode (rtx x)
4545 switch (standard_80387_constant_p (x))
4566 /* Return the CONST_DOUBLE representing the 80387 constant that is
4567 loaded by the specified special instruction. The argument IDX
4568 matches the return value from standard_80387_constant_p. */
4571 standard_80387_constant_rtx (int idx)
4575 if (! ext_80387_constants_init)
4576 init_ext_80387_constants ();
4592 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4596 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4599 standard_sse_constant_p (rtx x)
4601 if (x == const0_rtx)
4603 return (x == CONST0_RTX (GET_MODE (x)));
4606 /* Returns 1 if OP contains a symbol reference */
4609 symbolic_reference_mentioned_p (rtx op)
4614 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
4617 fmt = GET_RTX_FORMAT (GET_CODE (op));
4618 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
4624 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
4625 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
4629 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
4636 /* Return 1 if it is appropriate to emit `ret' instructions in the
4637 body of a function. Do this only if the epilogue is simple, needing a
4638 couple of insns. Prior to reloading, we can't tell how many registers
4639 must be saved, so return 0 then. Return 0 if there is no frame
4640 marker to de-allocate. */
4643 ix86_can_use_return_insn_p (void)
4645 struct ix86_frame frame;
4647 if (! reload_completed || frame_pointer_needed)
4650 /* Don't allow more than 32 pop, since that's all we can do
4651 with one instruction. */
4652 if (current_function_pops_args
4653 && current_function_args_size >= 32768)
4656 ix86_compute_frame_layout (&frame);
4657 return frame.to_allocate == 0 && frame.nregs == 0;
4660 /* Value should be nonzero if functions must have frame pointers.
4661 Zero means the frame pointer need not be set up (and parms may
4662 be accessed via the stack pointer) in functions that seem suitable. */
4665 ix86_frame_pointer_required (void)
4667 /* If we accessed previous frames, then the generated code expects
4668 to be able to access the saved ebp value in our frame. */
4669 if (cfun->machine->accesses_prev_frame)
4672 /* Several x86 os'es need a frame pointer for other reasons,
4673 usually pertaining to setjmp. */
4674 if (SUBTARGET_FRAME_POINTER_REQUIRED)
4677 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
4678 the frame pointer by default. Turn it back on now if we've not
4679 got a leaf function. */
4680 if (TARGET_OMIT_LEAF_FRAME_POINTER
4681 && (!current_function_is_leaf
4682 || ix86_current_function_calls_tls_descriptor))
4685 if (current_function_profile)
4691 /* Record that the current function accesses previous call frames. */
4694 ix86_setup_frame_addresses (void)
4696 cfun->machine->accesses_prev_frame = 1;
4699 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
4700 # define USE_HIDDEN_LINKONCE 1
4702 # define USE_HIDDEN_LINKONCE 0
4705 static int pic_labels_used;
4707 /* Fills in the label name that should be used for a pc thunk for
4708 the given register. */
4711 get_pc_thunk_name (char name[32], unsigned int regno)
4713 if (USE_HIDDEN_LINKONCE)
4714 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
4716 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
4720 /* This function generates code for -fpic that loads %ebx with
4721 the return address of the caller and then returns. */
4724 ix86_file_end (void)
4729 for (regno = 0; regno < 8; ++regno)
4733 if (! ((pic_labels_used >> regno) & 1))
4736 get_pc_thunk_name (name, regno);
4741 switch_to_section (darwin_sections[text_coal_section]);
4742 fputs ("\t.weak_definition\t", asm_out_file);
4743 assemble_name (asm_out_file, name);
4744 fputs ("\n\t.private_extern\t", asm_out_file);
4745 assemble_name (asm_out_file, name);
4746 fputs ("\n", asm_out_file);
4747 ASM_OUTPUT_LABEL (asm_out_file, name);
4751 if (USE_HIDDEN_LINKONCE)
4755 decl = build_decl (FUNCTION_DECL, get_identifier (name),
4757 TREE_PUBLIC (decl) = 1;
4758 TREE_STATIC (decl) = 1;
4759 DECL_ONE_ONLY (decl) = 1;
4761 (*targetm.asm_out.unique_section) (decl, 0);
4762 switch_to_section (get_named_section (decl, NULL, 0));
4764 (*targetm.asm_out.globalize_label) (asm_out_file, name);
4765 fputs ("\t.hidden\t", asm_out_file);
4766 assemble_name (asm_out_file, name);
4767 fputc ('\n', asm_out_file);
4768 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
4772 switch_to_section (text_section);
4773 ASM_OUTPUT_LABEL (asm_out_file, name);
4776 xops[0] = gen_rtx_REG (SImode, regno);
4777 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
4778 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
4779 output_asm_insn ("ret", xops);
4782 if (NEED_INDICATE_EXEC_STACK)
4783 file_end_indicate_exec_stack ();
4786 /* Emit code for the SET_GOT patterns. */
4789 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
4794 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
4796 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
4798 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
4801 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
4803 output_asm_insn ("call\t%a2", xops);
4806 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
4807 is what will be referenced by the Mach-O PIC subsystem. */
4809 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4812 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4813 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
4816 output_asm_insn ("pop{l}\t%0", xops);
4821 get_pc_thunk_name (name, REGNO (dest));
4822 pic_labels_used |= 1 << REGNO (dest);
4824 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4825 xops[2] = gen_rtx_MEM (QImode, xops[2]);
4826 output_asm_insn ("call\t%X2", xops);
4827 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
4828 is what will be referenced by the Mach-O PIC subsystem. */
4831 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4833 targetm.asm_out.internal_label (asm_out_file, "L",
4834 CODE_LABEL_NUMBER (label));
4841 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
4842 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
4844 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
4849 /* Generate an "push" pattern for input ARG. */
4854 return gen_rtx_SET (VOIDmode,
4856 gen_rtx_PRE_DEC (Pmode,
4857 stack_pointer_rtx)),
4861 /* Return >= 0 if there is an unused call-clobbered register available
4862 for the entire function. */
4865 ix86_select_alt_pic_regnum (void)
4867 if (current_function_is_leaf && !current_function_profile
4868 && !ix86_current_function_calls_tls_descriptor)
4871 for (i = 2; i >= 0; --i)
4872 if (!regs_ever_live[i])
4876 return INVALID_REGNUM;
4879 /* Return 1 if we need to save REGNO. */
4881 ix86_save_reg (unsigned int regno, int maybe_eh_return)
4883 if (pic_offset_table_rtx
4884 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
4885 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4886 || current_function_profile
4887 || current_function_calls_eh_return
4888 || current_function_uses_const_pool))
4890 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
4895 if (current_function_calls_eh_return && maybe_eh_return)
4900 unsigned test = EH_RETURN_DATA_REGNO (i);
4901 if (test == INVALID_REGNUM)
4908 if (cfun->machine->force_align_arg_pointer
4909 && regno == REGNO (cfun->machine->force_align_arg_pointer))
4912 return (regs_ever_live[regno]
4913 && !call_used_regs[regno]
4914 && !fixed_regs[regno]
4915 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
4918 /* Return number of registers to be saved on the stack. */
4921 ix86_nsaved_regs (void)
4926 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4927 if (ix86_save_reg (regno, true))
4932 /* Return the offset between two registers, one to be eliminated, and the other
4933 its replacement, at the start of a routine. */
4936 ix86_initial_elimination_offset (int from, int to)
4938 struct ix86_frame frame;
4939 ix86_compute_frame_layout (&frame);
4941 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
4942 return frame.hard_frame_pointer_offset;
4943 else if (from == FRAME_POINTER_REGNUM
4944 && to == HARD_FRAME_POINTER_REGNUM)
4945 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
4948 gcc_assert (to == STACK_POINTER_REGNUM);
4950 if (from == ARG_POINTER_REGNUM)
4951 return frame.stack_pointer_offset;
4953 gcc_assert (from == FRAME_POINTER_REGNUM);
4954 return frame.stack_pointer_offset - frame.frame_pointer_offset;
4958 /* Fill structure ix86_frame about frame of currently computed function. */
4961 ix86_compute_frame_layout (struct ix86_frame *frame)
4963 HOST_WIDE_INT total_size;
4964 unsigned int stack_alignment_needed;
4965 HOST_WIDE_INT offset;
4966 unsigned int preferred_alignment;
4967 HOST_WIDE_INT size = get_frame_size ();
4969 frame->nregs = ix86_nsaved_regs ();
4972 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
4973 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
4975 /* During reload iteration the amount of registers saved can change.
4976 Recompute the value as needed. Do not recompute when amount of registers
4977 didn't change as reload does multiple calls to the function and does not
4978 expect the decision to change within single iteration. */
4980 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
4982 int count = frame->nregs;
4984 cfun->machine->use_fast_prologue_epilogue_nregs = count;
4985 /* The fast prologue uses move instead of push to save registers. This
4986 is significantly longer, but also executes faster as modern hardware
4987 can execute the moves in parallel, but can't do that for push/pop.
4989 Be careful about choosing what prologue to emit: When function takes
4990 many instructions to execute we may use slow version as well as in
4991 case function is known to be outside hot spot (this is known with
4992 feedback only). Weight the size of function by number of registers
4993 to save as it is cheap to use one or two push instructions but very
4994 slow to use many of them. */
4996 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
4997 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
4998 || (flag_branch_probabilities
4999 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
5000 cfun->machine->use_fast_prologue_epilogue = false;
5002 cfun->machine->use_fast_prologue_epilogue
5003 = !expensive_function_p (count);
5005 if (TARGET_PROLOGUE_USING_MOVE
5006 && cfun->machine->use_fast_prologue_epilogue)
5007 frame->save_regs_using_mov = true;
5009 frame->save_regs_using_mov = false;
5012 /* Skip return address and saved base pointer. */
5013 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
5015 frame->hard_frame_pointer_offset = offset;
5017 /* Do some sanity checking of stack_alignment_needed and
5018 preferred_alignment, since i386 port is the only using those features
5019 that may break easily. */
5021 gcc_assert (!size || stack_alignment_needed);
5022 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
5023 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5024 gcc_assert (stack_alignment_needed
5025 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5027 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
5028 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
5030 /* Register save area */
5031 offset += frame->nregs * UNITS_PER_WORD;
5034 if (ix86_save_varrargs_registers)
5036 offset += X86_64_VARARGS_SIZE;
5037 frame->va_arg_size = X86_64_VARARGS_SIZE;
5040 frame->va_arg_size = 0;
5042 /* Align start of frame for local function. */
5043 frame->padding1 = ((offset + stack_alignment_needed - 1)
5044 & -stack_alignment_needed) - offset;
5046 offset += frame->padding1;
5048 /* Frame pointer points here. */
5049 frame->frame_pointer_offset = offset;
5053 /* Add outgoing arguments area. Can be skipped if we eliminated
5054 all the function calls as dead code.
5055 Skipping is however impossible when function calls alloca. Alloca
5056 expander assumes that last current_function_outgoing_args_size
5057 of stack frame are unused. */
5058 if (ACCUMULATE_OUTGOING_ARGS
5059 && (!current_function_is_leaf || current_function_calls_alloca
5060 || ix86_current_function_calls_tls_descriptor))
5062 offset += current_function_outgoing_args_size;
5063 frame->outgoing_arguments_size = current_function_outgoing_args_size;
5066 frame->outgoing_arguments_size = 0;
5068 /* Align stack boundary. Only needed if we're calling another function
5070 if (!current_function_is_leaf || current_function_calls_alloca
5071 || ix86_current_function_calls_tls_descriptor)
5072 frame->padding2 = ((offset + preferred_alignment - 1)
5073 & -preferred_alignment) - offset;
5075 frame->padding2 = 0;
5077 offset += frame->padding2;
5079 /* We've reached end of stack frame. */
5080 frame->stack_pointer_offset = offset;
5082 /* Size prologue needs to allocate. */
5083 frame->to_allocate =
5084 (size + frame->padding1 + frame->padding2
5085 + frame->outgoing_arguments_size + frame->va_arg_size);
5087 if ((!frame->to_allocate && frame->nregs <= 1)
5088 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
5089 frame->save_regs_using_mov = false;
5091 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
5092 && current_function_is_leaf
5093 && !ix86_current_function_calls_tls_descriptor)
5095 frame->red_zone_size = frame->to_allocate;
5096 if (frame->save_regs_using_mov)
5097 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
5098 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
5099 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
5102 frame->red_zone_size = 0;
5103 frame->to_allocate -= frame->red_zone_size;
5104 frame->stack_pointer_offset -= frame->red_zone_size;
5106 fprintf (stderr, "nregs: %i\n", frame->nregs);
5107 fprintf (stderr, "size: %i\n", size);
5108 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
5109 fprintf (stderr, "padding1: %i\n", frame->padding1);
5110 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
5111 fprintf (stderr, "padding2: %i\n", frame->padding2);
5112 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
5113 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
5114 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
5115 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
5116 frame->hard_frame_pointer_offset);
5117 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
5121 /* Emit code to save registers in the prologue. */
5124 ix86_emit_save_regs (void)
5129 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
5130 if (ix86_save_reg (regno, true))
5132 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
5133 RTX_FRAME_RELATED_P (insn) = 1;
5137 /* Emit code to save registers using MOV insns. First register
5138 is restored from POINTER + OFFSET. */
5140 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
5145 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5146 if (ix86_save_reg (regno, true))
5148 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
5150 gen_rtx_REG (Pmode, regno));
5151 RTX_FRAME_RELATED_P (insn) = 1;
5152 offset += UNITS_PER_WORD;
5156 /* Expand prologue or epilogue stack adjustment.
5157 The pattern exist to put a dependency on all ebp-based memory accesses.
5158 STYLE should be negative if instructions should be marked as frame related,
5159 zero if %r11 register is live and cannot be freely used and positive
5163 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
5168 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
5169 else if (x86_64_immediate_operand (offset, DImode))
5170 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
5174 /* r11 is used by indirect sibcall return as well, set before the
5175 epilogue and used after the epilogue. ATM indirect sibcall
5176 shouldn't be used together with huge frame sizes in one
5177 function because of the frame_size check in sibcall.c. */
5179 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
5180 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
5182 RTX_FRAME_RELATED_P (insn) = 1;
5183 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
5187 RTX_FRAME_RELATED_P (insn) = 1;
5190 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5193 ix86_internal_arg_pointer (void)
5195 bool has_force_align_arg_pointer =
5196 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
5197 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
5198 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
5199 && DECL_NAME (current_function_decl)
5200 && MAIN_NAME_P (DECL_NAME (current_function_decl))
5201 && DECL_FILE_SCOPE_P (current_function_decl))
5202 || ix86_force_align_arg_pointer
5203 || has_force_align_arg_pointer)
5205 /* Nested functions can't realign the stack due to a register
5207 if (DECL_CONTEXT (current_function_decl)
5208 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
5210 if (ix86_force_align_arg_pointer)
5211 warning (0, "-mstackrealign ignored for nested functions");
5212 if (has_force_align_arg_pointer)
5213 error ("%s not supported for nested functions",
5214 ix86_force_align_arg_pointer_string);
5215 return virtual_incoming_args_rtx;
5217 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
5218 return copy_to_reg (cfun->machine->force_align_arg_pointer);
5221 return virtual_incoming_args_rtx;
5224 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5225 This is called from dwarf2out.c to emit call frame instructions
5226 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5228 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
5230 rtx unspec = SET_SRC (pattern);
5231 gcc_assert (GET_CODE (unspec) == UNSPEC);
5235 case UNSPEC_REG_SAVE:
5236 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
5237 SET_DEST (pattern));
5239 case UNSPEC_DEF_CFA:
5240 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
5241 INTVAL (XVECEXP (unspec, 0, 0)));
5248 /* Expand the prologue into a bunch of separate insns. */
5251 ix86_expand_prologue (void)
5255 struct ix86_frame frame;
5256 HOST_WIDE_INT allocate;
5258 ix86_compute_frame_layout (&frame);
5260 if (cfun->machine->force_align_arg_pointer)
5264 /* Grab the argument pointer. */
5265 x = plus_constant (stack_pointer_rtx, 4);
5266 y = cfun->machine->force_align_arg_pointer;
5267 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
5268 RTX_FRAME_RELATED_P (insn) = 1;
5270 /* The unwind info consists of two parts: install the fafp as the cfa,
5271 and record the fafp as the "save register" of the stack pointer.
5272 The later is there in order that the unwinder can see where it
5273 should restore the stack pointer across the and insn. */
5274 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
5275 x = gen_rtx_SET (VOIDmode, y, x);
5276 RTX_FRAME_RELATED_P (x) = 1;
5277 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
5279 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
5280 RTX_FRAME_RELATED_P (y) = 1;
5281 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
5282 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5283 REG_NOTES (insn) = x;
5285 /* Align the stack. */
5286 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
5289 /* And here we cheat like madmen with the unwind info. We force the
5290 cfa register back to sp+4, which is exactly what it was at the
5291 start of the function. Re-pushing the return address results in
5292 the return at the same spot relative to the cfa, and thus is
5293 correct wrt the unwind info. */
5294 x = cfun->machine->force_align_arg_pointer;
5295 x = gen_frame_mem (Pmode, plus_constant (x, -4));
5296 insn = emit_insn (gen_push (x));
5297 RTX_FRAME_RELATED_P (insn) = 1;
5300 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
5301 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
5302 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5303 REG_NOTES (insn) = x;
5306 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5307 slower on all targets. Also sdb doesn't like it. */
5309 if (frame_pointer_needed)
5311 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
5312 RTX_FRAME_RELATED_P (insn) = 1;
5314 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
5315 RTX_FRAME_RELATED_P (insn) = 1;
5318 allocate = frame.to_allocate;
5320 if (!frame.save_regs_using_mov)
5321 ix86_emit_save_regs ();
5323 allocate += frame.nregs * UNITS_PER_WORD;
5325 /* When using red zone we may start register saving before allocating
5326 the stack frame saving one cycle of the prologue. */
5327 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
5328 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
5329 : stack_pointer_rtx,
5330 -frame.nregs * UNITS_PER_WORD);
5334 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
5335 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5336 GEN_INT (-allocate), -1);
5339 /* Only valid for Win32. */
5340 rtx eax = gen_rtx_REG (SImode, 0);
5341 bool eax_live = ix86_eax_live_at_start_p ();
5344 gcc_assert (!TARGET_64BIT);
5348 emit_insn (gen_push (eax));
5352 emit_move_insn (eax, GEN_INT (allocate));
5354 insn = emit_insn (gen_allocate_stack_worker (eax));
5355 RTX_FRAME_RELATED_P (insn) = 1;
5356 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
5357 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
5358 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
5359 t, REG_NOTES (insn));
5363 if (frame_pointer_needed)
5364 t = plus_constant (hard_frame_pointer_rtx,
5367 - frame.nregs * UNITS_PER_WORD);
5369 t = plus_constant (stack_pointer_rtx, allocate);
5370 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
5374 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
5376 if (!frame_pointer_needed || !frame.to_allocate)
5377 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
5379 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
5380 -frame.nregs * UNITS_PER_WORD);
5383 pic_reg_used = false;
5384 if (pic_offset_table_rtx
5385 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
5386 || current_function_profile))
5388 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
5390 if (alt_pic_reg_used != INVALID_REGNUM)
5391 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
5393 pic_reg_used = true;
5399 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
5401 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
5403 /* Even with accurate pre-reload life analysis, we can wind up
5404 deleting all references to the pic register after reload.
5405 Consider if cross-jumping unifies two sides of a branch
5406 controlled by a comparison vs the only read from a global.
5407 In which case, allow the set_got to be deleted, though we're
5408 too late to do anything about the ebx save in the prologue. */
5409 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
5412 /* Prevent function calls from be scheduled before the call to mcount.
5413 In the pic_reg_used case, make sure that the got load isn't deleted. */
5414 if (current_function_profile)
5415 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
5418 /* Emit code to restore saved registers using MOV insns. First register
5419 is restored from POINTER + OFFSET. */
5421 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
5422 int maybe_eh_return)
5425 rtx base_address = gen_rtx_MEM (Pmode, pointer);
5427 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5428 if (ix86_save_reg (regno, maybe_eh_return))
5430 /* Ensure that adjust_address won't be forced to produce pointer
5431 out of range allowed by x86-64 instruction set. */
5432 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
5436 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
5437 emit_move_insn (r11, GEN_INT (offset));
5438 emit_insn (gen_adddi3 (r11, r11, pointer));
5439 base_address = gen_rtx_MEM (Pmode, r11);
5442 emit_move_insn (gen_rtx_REG (Pmode, regno),
5443 adjust_address (base_address, Pmode, offset));
5444 offset += UNITS_PER_WORD;
5448 /* Restore function stack, frame, and registers. */
5451 ix86_expand_epilogue (int style)
5454 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
5455 struct ix86_frame frame;
5456 HOST_WIDE_INT offset;
5458 ix86_compute_frame_layout (&frame);
5460 /* Calculate start of saved registers relative to ebp. Special care
5461 must be taken for the normal return case of a function using
5462 eh_return: the eax and edx registers are marked as saved, but not
5463 restored along this path. */
5464 offset = frame.nregs;
5465 if (current_function_calls_eh_return && style != 2)
5467 offset *= -UNITS_PER_WORD;
5469 /* If we're only restoring one register and sp is not valid then
5470 using a move instruction to restore the register since it's
5471 less work than reloading sp and popping the register.
5473 The default code result in stack adjustment using add/lea instruction,
5474 while this code results in LEAVE instruction (or discrete equivalent),
5475 so it is profitable in some other cases as well. Especially when there
5476 are no registers to restore. We also use this code when TARGET_USE_LEAVE
5477 and there is exactly one register to pop. This heuristic may need some
5478 tuning in future. */
5479 if ((!sp_valid && frame.nregs <= 1)
5480 || (TARGET_EPILOGUE_USING_MOVE
5481 && cfun->machine->use_fast_prologue_epilogue
5482 && (frame.nregs > 1 || frame.to_allocate))
5483 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
5484 || (frame_pointer_needed && TARGET_USE_LEAVE
5485 && cfun->machine->use_fast_prologue_epilogue
5486 && frame.nregs == 1)
5487 || current_function_calls_eh_return)
5489 /* Restore registers. We can use ebp or esp to address the memory
5490 locations. If both are available, default to ebp, since offsets
5491 are known to be small. Only exception is esp pointing directly to the
5492 end of block of saved registers, where we may simplify addressing
5495 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
5496 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
5497 frame.to_allocate, style == 2);
5499 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
5500 offset, style == 2);
5502 /* eh_return epilogues need %ecx added to the stack pointer. */
5505 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
5507 if (frame_pointer_needed)
5509 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
5510 tmp = plus_constant (tmp, UNITS_PER_WORD);
5511 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
5513 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5514 emit_move_insn (hard_frame_pointer_rtx, tmp);
5516 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
5521 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
5522 tmp = plus_constant (tmp, (frame.to_allocate
5523 + frame.nregs * UNITS_PER_WORD));
5524 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
5527 else if (!frame_pointer_needed)
5528 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5529 GEN_INT (frame.to_allocate
5530 + frame.nregs * UNITS_PER_WORD),
5532 /* If not an i386, mov & pop is faster than "leave". */
5533 else if (TARGET_USE_LEAVE || optimize_size
5534 || !cfun->machine->use_fast_prologue_epilogue)
5535 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5538 pro_epilogue_adjust_stack (stack_pointer_rtx,
5539 hard_frame_pointer_rtx,
5542 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5544 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5549 /* First step is to deallocate the stack frame so that we can
5550 pop the registers. */
5553 gcc_assert (frame_pointer_needed);
5554 pro_epilogue_adjust_stack (stack_pointer_rtx,
5555 hard_frame_pointer_rtx,
5556 GEN_INT (offset), style);
5558 else if (frame.to_allocate)
5559 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5560 GEN_INT (frame.to_allocate), style);
5562 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5563 if (ix86_save_reg (regno, false))
5566 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5568 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5570 if (frame_pointer_needed)
5572 /* Leave results in shorter dependency chains on CPUs that are
5573 able to grok it fast. */
5574 if (TARGET_USE_LEAVE)
5575 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5576 else if (TARGET_64BIT)
5577 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5579 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5583 if (cfun->machine->force_align_arg_pointer)
5585 emit_insn (gen_addsi3 (stack_pointer_rtx,
5586 cfun->machine->force_align_arg_pointer,
5590 /* Sibcall epilogues don't want a return instruction. */
5594 if (current_function_pops_args && current_function_args_size)
5596 rtx popc = GEN_INT (current_function_pops_args);
5598 /* i386 can only pop 64K bytes. If asked to pop more, pop
5599 return address, do explicit add, and jump indirectly to the
5602 if (current_function_pops_args >= 65536)
5604 rtx ecx = gen_rtx_REG (SImode, 2);
5606 /* There is no "pascal" calling convention in 64bit ABI. */
5607 gcc_assert (!TARGET_64BIT);
5609 emit_insn (gen_popsi1 (ecx));
5610 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
5611 emit_jump_insn (gen_return_indirect_internal (ecx));
5614 emit_jump_insn (gen_return_pop_internal (popc));
5617 emit_jump_insn (gen_return_internal ());
5620 /* Reset from the function's potential modifications. */
5623 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5624 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5626 if (pic_offset_table_rtx)
5627 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
5630 /* Extract the parts of an RTL expression that is a valid memory address
5631 for an instruction. Return 0 if the structure of the address is
5632 grossly off. Return -1 if the address contains ASHIFT, so it is not
5633 strictly valid, but still used for computing length of lea instruction. */
5636 ix86_decompose_address (rtx addr, struct ix86_address *out)
5638 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
5639 rtx base_reg, index_reg;
5640 HOST_WIDE_INT scale = 1;
5641 rtx scale_rtx = NULL_RTX;
5643 enum ix86_address_seg seg = SEG_DEFAULT;
5645 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
5647 else if (GET_CODE (addr) == PLUS)
5657 addends[n++] = XEXP (op, 1);
5660 while (GET_CODE (op) == PLUS);
5665 for (i = n; i >= 0; --i)
5668 switch (GET_CODE (op))
5673 index = XEXP (op, 0);
5674 scale_rtx = XEXP (op, 1);
5678 if (XINT (op, 1) == UNSPEC_TP
5679 && TARGET_TLS_DIRECT_SEG_REFS
5680 && seg == SEG_DEFAULT)
5681 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
5710 else if (GET_CODE (addr) == MULT)
5712 index = XEXP (addr, 0); /* index*scale */
5713 scale_rtx = XEXP (addr, 1);
5715 else if (GET_CODE (addr) == ASHIFT)
5719 /* We're called for lea too, which implements ashift on occasion. */
5720 index = XEXP (addr, 0);
5721 tmp = XEXP (addr, 1);
5722 if (GET_CODE (tmp) != CONST_INT)
5724 scale = INTVAL (tmp);
5725 if ((unsigned HOST_WIDE_INT) scale > 3)
5731 disp = addr; /* displacement */
5733 /* Extract the integral value of scale. */
5736 if (GET_CODE (scale_rtx) != CONST_INT)
5738 scale = INTVAL (scale_rtx);
5741 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
5742 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
5744 /* Allow arg pointer and stack pointer as index if there is not scaling. */
5745 if (base_reg && index_reg && scale == 1
5746 && (index_reg == arg_pointer_rtx
5747 || index_reg == frame_pointer_rtx
5748 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
5751 tmp = base, base = index, index = tmp;
5752 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
5755 /* Special case: %ebp cannot be encoded as a base without a displacement. */
5756 if ((base_reg == hard_frame_pointer_rtx
5757 || base_reg == frame_pointer_rtx
5758 || base_reg == arg_pointer_rtx) && !disp)
5761 /* Special case: on K6, [%esi] makes the instruction vector decoded.
5762 Avoid this by transforming to [%esi+0]. */
5763 if (ix86_tune == PROCESSOR_K6 && !optimize_size
5764 && base_reg && !index_reg && !disp
5766 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
5769 /* Special case: encode reg+reg instead of reg*2. */
5770 if (!base && index && scale && scale == 2)
5771 base = index, base_reg = index_reg, scale = 1;
5773 /* Special case: scaling cannot be encoded without base or displacement. */
5774 if (!base && !disp && index && scale != 1)
5786 /* Return cost of the memory address x.
5787 For i386, it is better to use a complex address than let gcc copy
5788 the address into a reg and make a new pseudo. But not if the address
5789 requires to two regs - that would mean more pseudos with longer
5792 ix86_address_cost (rtx x)
5794 struct ix86_address parts;
5796 int ok = ix86_decompose_address (x, &parts);
5800 if (parts.base && GET_CODE (parts.base) == SUBREG)
5801 parts.base = SUBREG_REG (parts.base);
5802 if (parts.index && GET_CODE (parts.index) == SUBREG)
5803 parts.index = SUBREG_REG (parts.index);
5805 /* More complex memory references are better. */
5806 if (parts.disp && parts.disp != const0_rtx)
5808 if (parts.seg != SEG_DEFAULT)
5811 /* Attempt to minimize number of registers in the address. */
5813 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
5815 && (!REG_P (parts.index)
5816 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
5820 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
5822 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
5823 && parts.base != parts.index)
5826 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
5827 since it's predecode logic can't detect the length of instructions
5828 and it degenerates to vector decoded. Increase cost of such
5829 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
5830 to split such addresses or even refuse such addresses at all.
5832 Following addressing modes are affected:
5837 The first and last case may be avoidable by explicitly coding the zero in
5838 memory address, but I don't have AMD-K6 machine handy to check this
5842 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
5843 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
5844 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
5850 /* If X is a machine specific address (i.e. a symbol or label being
5851 referenced as a displacement from the GOT implemented using an
5852 UNSPEC), then return the base term. Otherwise return X. */
5855 ix86_find_base_term (rtx x)
5861 if (GET_CODE (x) != CONST)
5864 if (GET_CODE (term) == PLUS
5865 && (GET_CODE (XEXP (term, 1)) == CONST_INT
5866 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
5867 term = XEXP (term, 0);
5868 if (GET_CODE (term) != UNSPEC
5869 || XINT (term, 1) != UNSPEC_GOTPCREL)
5872 term = XVECEXP (term, 0, 0);
5874 if (GET_CODE (term) != SYMBOL_REF
5875 && GET_CODE (term) != LABEL_REF)
5881 term = ix86_delegitimize_address (x);
5883 if (GET_CODE (term) != SYMBOL_REF
5884 && GET_CODE (term) != LABEL_REF)
5890 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
5891 this is used for to form addresses to local data when -fPIC is in
5895 darwin_local_data_pic (rtx disp)
5897 if (GET_CODE (disp) == MINUS)
5899 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
5900 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
5901 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
5903 const char *sym_name = XSTR (XEXP (disp, 1), 0);
5904 if (! strcmp (sym_name, "<pic base>"))
5912 /* Determine if a given RTX is a valid constant. We already know this
5913 satisfies CONSTANT_P. */
5916 legitimate_constant_p (rtx x)
5918 switch (GET_CODE (x))
5923 if (GET_CODE (x) == PLUS)
5925 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5930 if (TARGET_MACHO && darwin_local_data_pic (x))
5933 /* Only some unspecs are valid as "constants". */
5934 if (GET_CODE (x) == UNSPEC)
5935 switch (XINT (x, 1))
5938 return TARGET_64BIT;
5941 x = XVECEXP (x, 0, 0);
5942 return (GET_CODE (x) == SYMBOL_REF
5943 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
5945 x = XVECEXP (x, 0, 0);
5946 return (GET_CODE (x) == SYMBOL_REF
5947 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
5952 /* We must have drilled down to a symbol. */
5953 if (GET_CODE (x) == LABEL_REF)
5955 if (GET_CODE (x) != SYMBOL_REF)
5960 /* TLS symbols are never valid. */
5961 if (SYMBOL_REF_TLS_MODEL (x))
5966 if (GET_MODE (x) == TImode
5967 && x != CONST0_RTX (TImode)
5973 if (x == CONST0_RTX (GET_MODE (x)))
5981 /* Otherwise we handle everything else in the move patterns. */
5985 /* Determine if it's legal to put X into the constant pool. This
5986 is not possible for the address of thread-local symbols, which
5987 is checked above. */
5990 ix86_cannot_force_const_mem (rtx x)
5992 /* We can always put integral constants and vectors in memory. */
5993 switch (GET_CODE (x))
6003 return !legitimate_constant_p (x);
6006 /* Determine if a given RTX is a valid constant address. */
6009 constant_address_p (rtx x)
6011 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
6014 /* Nonzero if the constant value X is a legitimate general operand
6015 when generating PIC code. It is given that flag_pic is on and
6016 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6019 legitimate_pic_operand_p (rtx x)
6023 switch (GET_CODE (x))
6026 inner = XEXP (x, 0);
6027 if (GET_CODE (inner) == PLUS
6028 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
6029 inner = XEXP (inner, 0);
6031 /* Only some unspecs are valid as "constants". */
6032 if (GET_CODE (inner) == UNSPEC)
6033 switch (XINT (inner, 1))
6036 return TARGET_64BIT;
6038 x = XVECEXP (inner, 0, 0);
6039 return (GET_CODE (x) == SYMBOL_REF
6040 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6048 return legitimate_pic_address_disp_p (x);
6055 /* Determine if a given CONST RTX is a valid memory displacement
6059 legitimate_pic_address_disp_p (rtx disp)
6063 /* In 64bit mode we can allow direct addresses of symbols and labels
6064 when they are not dynamic symbols. */
6067 rtx op0 = disp, op1;
6069 switch (GET_CODE (disp))
6075 if (GET_CODE (XEXP (disp, 0)) != PLUS)
6077 op0 = XEXP (XEXP (disp, 0), 0);
6078 op1 = XEXP (XEXP (disp, 0), 1);
6079 if (GET_CODE (op1) != CONST_INT
6080 || INTVAL (op1) >= 16*1024*1024
6081 || INTVAL (op1) < -16*1024*1024)
6083 if (GET_CODE (op0) == LABEL_REF)
6085 if (GET_CODE (op0) != SYMBOL_REF)
6090 /* TLS references should always be enclosed in UNSPEC. */
6091 if (SYMBOL_REF_TLS_MODEL (op0))
6093 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0))
6101 if (GET_CODE (disp) != CONST)
6103 disp = XEXP (disp, 0);
6107 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6108 of GOT tables. We should not need these anyway. */
6109 if (GET_CODE (disp) != UNSPEC
6110 || (XINT (disp, 1) != UNSPEC_GOTPCREL
6111 && XINT (disp, 1) != UNSPEC_GOTOFF))
6114 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
6115 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
6121 if (GET_CODE (disp) == PLUS)
6123 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
6125 disp = XEXP (disp, 0);
6129 if (TARGET_MACHO && darwin_local_data_pic (disp))
6132 if (GET_CODE (disp) != UNSPEC)
6135 switch (XINT (disp, 1))
6140 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
6142 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6143 While ABI specify also 32bit relocation but we don't produce it in
6144 small PIC model at all. */
6145 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6146 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
6148 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
6150 case UNSPEC_GOTTPOFF:
6151 case UNSPEC_GOTNTPOFF:
6152 case UNSPEC_INDNTPOFF:
6155 disp = XVECEXP (disp, 0, 0);
6156 return (GET_CODE (disp) == SYMBOL_REF
6157 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
6159 disp = XVECEXP (disp, 0, 0);
6160 return (GET_CODE (disp) == SYMBOL_REF
6161 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
6163 disp = XVECEXP (disp, 0, 0);
6164 return (GET_CODE (disp) == SYMBOL_REF
6165 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
6171 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6172 memory address for an instruction. The MODE argument is the machine mode
6173 for the MEM expression that wants to use this address.
6175 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6176 convert common non-canonical forms to canonical form so that they will
6180 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
6182 struct ix86_address parts;
6183 rtx base, index, disp;
6184 HOST_WIDE_INT scale;
6185 const char *reason = NULL;
6186 rtx reason_rtx = NULL_RTX;
6188 if (TARGET_DEBUG_ADDR)
6191 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
6192 GET_MODE_NAME (mode), strict);
6196 if (ix86_decompose_address (addr, &parts) <= 0)
6198 reason = "decomposition failed";
6203 index = parts.index;
6205 scale = parts.scale;
6207 /* Validate base register.
6209 Don't allow SUBREG's that span more than a word here. It can lead to spill
6210 failures when the base is one word out of a two word structure, which is
6211 represented internally as a DImode int. */
6220 else if (GET_CODE (base) == SUBREG
6221 && REG_P (SUBREG_REG (base))
6222 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
6224 reg = SUBREG_REG (base);
6227 reason = "base is not a register";
6231 if (GET_MODE (base) != Pmode)
6233 reason = "base is not in Pmode";
6237 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
6238 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
6240 reason = "base is not valid";
6245 /* Validate index register.
6247 Don't allow SUBREG's that span more than a word here -- same as above. */
6256 else if (GET_CODE (index) == SUBREG
6257 && REG_P (SUBREG_REG (index))
6258 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
6260 reg = SUBREG_REG (index);
6263 reason = "index is not a register";
6267 if (GET_MODE (index) != Pmode)
6269 reason = "index is not in Pmode";
6273 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
6274 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
6276 reason = "index is not valid";
6281 /* Validate scale factor. */
6284 reason_rtx = GEN_INT (scale);
6287 reason = "scale without index";
6291 if (scale != 2 && scale != 4 && scale != 8)
6293 reason = "scale is not a valid multiplier";
6298 /* Validate displacement. */
6303 if (GET_CODE (disp) == CONST
6304 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
6305 switch (XINT (XEXP (disp, 0), 1))
6307 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6308 used. While ABI specify also 32bit relocations, we don't produce
6309 them at all and use IP relative instead. */
6312 gcc_assert (flag_pic);
6314 goto is_legitimate_pic;
6315 reason = "64bit address unspec";
6318 case UNSPEC_GOTPCREL:
6319 gcc_assert (flag_pic);
6320 goto is_legitimate_pic;
6322 case UNSPEC_GOTTPOFF:
6323 case UNSPEC_GOTNTPOFF:
6324 case UNSPEC_INDNTPOFF:
6330 reason = "invalid address unspec";
6334 else if (flag_pic && (SYMBOLIC_CONST (disp)
6336 && !machopic_operand_p (disp)
6341 if (TARGET_64BIT && (index || base))
6343 /* foo@dtpoff(%rX) is ok. */
6344 if (GET_CODE (disp) != CONST
6345 || GET_CODE (XEXP (disp, 0)) != PLUS
6346 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
6347 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
6348 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
6349 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
6351 reason = "non-constant pic memory reference";
6355 else if (! legitimate_pic_address_disp_p (disp))
6357 reason = "displacement is an invalid pic construct";
6361 /* This code used to verify that a symbolic pic displacement
6362 includes the pic_offset_table_rtx register.
6364 While this is good idea, unfortunately these constructs may
6365 be created by "adds using lea" optimization for incorrect
6374 This code is nonsensical, but results in addressing
6375 GOT table with pic_offset_table_rtx base. We can't
6376 just refuse it easily, since it gets matched by
6377 "addsi3" pattern, that later gets split to lea in the
6378 case output register differs from input. While this
6379 can be handled by separate addsi pattern for this case
6380 that never results in lea, this seems to be easier and
6381 correct fix for crash to disable this test. */
6383 else if (GET_CODE (disp) != LABEL_REF
6384 && GET_CODE (disp) != CONST_INT
6385 && (GET_CODE (disp) != CONST
6386 || !legitimate_constant_p (disp))
6387 && (GET_CODE (disp) != SYMBOL_REF
6388 || !legitimate_constant_p (disp)))
6390 reason = "displacement is not constant";
6393 else if (TARGET_64BIT
6394 && !x86_64_immediate_operand (disp, VOIDmode))
6396 reason = "displacement is out of range";
6401 /* Everything looks valid. */
6402 if (TARGET_DEBUG_ADDR)
6403 fprintf (stderr, "Success.\n");
6407 if (TARGET_DEBUG_ADDR)
6409 fprintf (stderr, "Error: %s\n", reason);
6410 debug_rtx (reason_rtx);
6415 /* Return a unique alias set for the GOT. */
6417 static HOST_WIDE_INT
6418 ix86_GOT_alias_set (void)
6420 static HOST_WIDE_INT set = -1;
6422 set = new_alias_set ();
6426 /* Return a legitimate reference for ORIG (an address) using the
6427 register REG. If REG is 0, a new pseudo is generated.
6429 There are two types of references that must be handled:
6431 1. Global data references must load the address from the GOT, via
6432 the PIC reg. An insn is emitted to do this load, and the reg is
6435 2. Static data references, constant pool addresses, and code labels
6436 compute the address as an offset from the GOT, whose base is in
6437 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
6438 differentiate them from global data objects. The returned
6439 address is the PIC reg + an unspec constant.
6441 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
6442 reg also appears in the address. */
6445 legitimize_pic_address (rtx orig, rtx reg)
6453 reg = gen_reg_rtx (Pmode);
6454 /* Use the generic Mach-O PIC machinery. */
6455 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
6458 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
6460 else if (TARGET_64BIT
6461 && ix86_cmodel != CM_SMALL_PIC
6462 && local_symbolic_operand (addr, Pmode))
6465 /* This symbol may be referenced via a displacement from the PIC
6466 base address (@GOTOFF). */
6468 if (reload_in_progress)
6469 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6470 if (GET_CODE (addr) == CONST)
6471 addr = XEXP (addr, 0);
6472 if (GET_CODE (addr) == PLUS)
6474 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6475 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6478 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6479 new = gen_rtx_CONST (Pmode, new);
6481 tmpreg = gen_reg_rtx (Pmode);
6484 emit_move_insn (tmpreg, new);
6488 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
6489 tmpreg, 1, OPTAB_DIRECT);
6492 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
6494 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
6496 /* This symbol may be referenced via a displacement from the PIC
6497 base address (@GOTOFF). */
6499 if (reload_in_progress)
6500 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6501 if (GET_CODE (addr) == CONST)
6502 addr = XEXP (addr, 0);
6503 if (GET_CODE (addr) == PLUS)
6505 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6506 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6509 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6510 new = gen_rtx_CONST (Pmode, new);
6511 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6515 emit_move_insn (reg, new);
6519 else if (GET_CODE (addr) == SYMBOL_REF)
6523 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
6524 new = gen_rtx_CONST (Pmode, new);
6525 new = gen_const_mem (Pmode, new);
6526 set_mem_alias_set (new, ix86_GOT_alias_set ());
6529 reg = gen_reg_rtx (Pmode);
6530 /* Use directly gen_movsi, otherwise the address is loaded
6531 into register for CSE. We don't want to CSE this addresses,
6532 instead we CSE addresses from the GOT table, so skip this. */
6533 emit_insn (gen_movsi (reg, new));
6538 /* This symbol must be referenced via a load from the
6539 Global Offset Table (@GOT). */
6541 if (reload_in_progress)
6542 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6543 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
6544 new = gen_rtx_CONST (Pmode, new);
6545 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6546 new = gen_const_mem (Pmode, new);
6547 set_mem_alias_set (new, ix86_GOT_alias_set ());
6550 reg = gen_reg_rtx (Pmode);
6551 emit_move_insn (reg, new);
6557 if (GET_CODE (addr) == CONST_INT
6558 && !x86_64_immediate_operand (addr, VOIDmode))
6562 emit_move_insn (reg, addr);
6566 new = force_reg (Pmode, addr);
6568 else if (GET_CODE (addr) == CONST)
6570 addr = XEXP (addr, 0);
6572 /* We must match stuff we generate before. Assume the only
6573 unspecs that can get here are ours. Not that we could do
6574 anything with them anyway.... */
6575 if (GET_CODE (addr) == UNSPEC
6576 || (GET_CODE (addr) == PLUS
6577 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
6579 gcc_assert (GET_CODE (addr) == PLUS);
6581 if (GET_CODE (addr) == PLUS)
6583 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
6585 /* Check first to see if this is a constant offset from a @GOTOFF
6586 symbol reference. */
6587 if (local_symbolic_operand (op0, Pmode)
6588 && GET_CODE (op1) == CONST_INT)
6592 if (reload_in_progress)
6593 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6594 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
6596 new = gen_rtx_PLUS (Pmode, new, op1);
6597 new = gen_rtx_CONST (Pmode, new);
6598 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6602 emit_move_insn (reg, new);
6608 if (INTVAL (op1) < -16*1024*1024
6609 || INTVAL (op1) >= 16*1024*1024)
6611 if (!x86_64_immediate_operand (op1, Pmode))
6612 op1 = force_reg (Pmode, op1);
6613 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
6619 base = legitimize_pic_address (XEXP (addr, 0), reg);
6620 new = legitimize_pic_address (XEXP (addr, 1),
6621 base == reg ? NULL_RTX : reg);
6623 if (GET_CODE (new) == CONST_INT)
6624 new = plus_constant (base, INTVAL (new));
6627 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
6629 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
6630 new = XEXP (new, 1);
6632 new = gen_rtx_PLUS (Pmode, base, new);
6640 /* Load the thread pointer. If TO_REG is true, force it into a register. */
6643 get_thread_pointer (int to_reg)
6647 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
6651 reg = gen_reg_rtx (Pmode);
6652 insn = gen_rtx_SET (VOIDmode, reg, tp);
6653 insn = emit_insn (insn);
6658 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
6659 false if we expect this to be used for a memory address and true if
6660 we expect to load the address into a register. */
6663 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
6665 rtx dest, base, off, pic, tp;
6670 case TLS_MODEL_GLOBAL_DYNAMIC:
6671 dest = gen_reg_rtx (Pmode);
6672 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
6674 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
6676 rtx rax = gen_rtx_REG (Pmode, 0), insns;
6679 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
6680 insns = get_insns ();
6683 emit_libcall_block (insns, dest, rax, x);
6685 else if (TARGET_64BIT && TARGET_GNU2_TLS)
6686 emit_insn (gen_tls_global_dynamic_64 (dest, x));
6688 emit_insn (gen_tls_global_dynamic_32 (dest, x));
6690 if (TARGET_GNU2_TLS)
6692 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
6694 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
6698 case TLS_MODEL_LOCAL_DYNAMIC:
6699 base = gen_reg_rtx (Pmode);
6700 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
6702 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
6704 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
6707 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
6708 insns = get_insns ();
6711 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
6712 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
6713 emit_libcall_block (insns, base, rax, note);
6715 else if (TARGET_64BIT && TARGET_GNU2_TLS)
6716 emit_insn (gen_tls_local_dynamic_base_64 (base));
6718 emit_insn (gen_tls_local_dynamic_base_32 (base));
6720 if (TARGET_GNU2_TLS)
6722 rtx x = ix86_tls_module_base ();
6724 base = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, base));
6726 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
6729 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
6730 off = gen_rtx_CONST (Pmode, off);
6732 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
6735 case TLS_MODEL_INITIAL_EXEC:
6739 type = UNSPEC_GOTNTPOFF;
6743 if (reload_in_progress)
6744 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6745 pic = pic_offset_table_rtx;
6746 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
6748 else if (!TARGET_ANY_GNU_TLS)
6750 pic = gen_reg_rtx (Pmode);
6751 emit_insn (gen_set_got (pic));
6752 type = UNSPEC_GOTTPOFF;
6757 type = UNSPEC_INDNTPOFF;
6760 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
6761 off = gen_rtx_CONST (Pmode, off);
6763 off = gen_rtx_PLUS (Pmode, pic, off);
6764 off = gen_const_mem (Pmode, off);
6765 set_mem_alias_set (off, ix86_GOT_alias_set ());
6767 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6769 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6770 off = force_reg (Pmode, off);
6771 return gen_rtx_PLUS (Pmode, base, off);
6775 base = get_thread_pointer (true);
6776 dest = gen_reg_rtx (Pmode);
6777 emit_insn (gen_subsi3 (dest, base, off));
6781 case TLS_MODEL_LOCAL_EXEC:
6782 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
6783 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6784 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
6785 off = gen_rtx_CONST (Pmode, off);
6787 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
6789 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6790 return gen_rtx_PLUS (Pmode, base, off);
6794 base = get_thread_pointer (true);
6795 dest = gen_reg_rtx (Pmode);
6796 emit_insn (gen_subsi3 (dest, base, off));
6807 /* Try machine-dependent ways of modifying an illegitimate address
6808 to be legitimate. If we find one, return the new, valid address.
6809 This macro is used in only one place: `memory_address' in explow.c.
6811 OLDX is the address as it was before break_out_memory_refs was called.
6812 In some cases it is useful to look at this to decide what needs to be done.
6814 MODE and WIN are passed so that this macro can use
6815 GO_IF_LEGITIMATE_ADDRESS.
6817 It is always safe for this macro to do nothing. It exists to recognize
6818 opportunities to optimize the output.
6820 For the 80386, we handle X+REG by loading X into a register R and
6821 using R+REG. R will go in a general reg and indexing will be used.
6822 However, if REG is a broken-out memory address or multiplication,
6823 nothing needs to be done because REG can certainly go in a general reg.
6825 When -fpic is used, special handling is needed for symbolic references.
6826 See comments by legitimize_pic_address in i386.c for details. */
6829 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
6834 if (TARGET_DEBUG_ADDR)
6836 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
6837 GET_MODE_NAME (mode));
6841 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
6843 return legitimize_tls_address (x, log, false);
6844 if (GET_CODE (x) == CONST
6845 && GET_CODE (XEXP (x, 0)) == PLUS
6846 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6847 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
6849 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
6850 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
6853 if (flag_pic && SYMBOLIC_CONST (x))
6854 return legitimize_pic_address (x, 0);
6856 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
6857 if (GET_CODE (x) == ASHIFT
6858 && GET_CODE (XEXP (x, 1)) == CONST_INT
6859 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
6862 log = INTVAL (XEXP (x, 1));
6863 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
6864 GEN_INT (1 << log));
6867 if (GET_CODE (x) == PLUS)
6869 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
6871 if (GET_CODE (XEXP (x, 0)) == ASHIFT
6872 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6873 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
6876 log = INTVAL (XEXP (XEXP (x, 0), 1));
6877 XEXP (x, 0) = gen_rtx_MULT (Pmode,
6878 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
6879 GEN_INT (1 << log));
6882 if (GET_CODE (XEXP (x, 1)) == ASHIFT
6883 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
6884 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
6887 log = INTVAL (XEXP (XEXP (x, 1), 1));
6888 XEXP (x, 1) = gen_rtx_MULT (Pmode,
6889 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
6890 GEN_INT (1 << log));
6893 /* Put multiply first if it isn't already. */
6894 if (GET_CODE (XEXP (x, 1)) == MULT)
6896 rtx tmp = XEXP (x, 0);
6897 XEXP (x, 0) = XEXP (x, 1);
6902 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
6903 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
6904 created by virtual register instantiation, register elimination, and
6905 similar optimizations. */
6906 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
6909 x = gen_rtx_PLUS (Pmode,
6910 gen_rtx_PLUS (Pmode, XEXP (x, 0),
6911 XEXP (XEXP (x, 1), 0)),
6912 XEXP (XEXP (x, 1), 1));
6916 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
6917 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
6918 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
6919 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
6920 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
6921 && CONSTANT_P (XEXP (x, 1)))
6924 rtx other = NULL_RTX;
6926 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6928 constant = XEXP (x, 1);
6929 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
6931 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
6933 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
6934 other = XEXP (x, 1);
6942 x = gen_rtx_PLUS (Pmode,
6943 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
6944 XEXP (XEXP (XEXP (x, 0), 1), 0)),
6945 plus_constant (other, INTVAL (constant)));
6949 if (changed && legitimate_address_p (mode, x, FALSE))
6952 if (GET_CODE (XEXP (x, 0)) == MULT)
6955 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
6958 if (GET_CODE (XEXP (x, 1)) == MULT)
6961 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
6965 && GET_CODE (XEXP (x, 1)) == REG
6966 && GET_CODE (XEXP (x, 0)) == REG)
6969 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
6972 x = legitimize_pic_address (x, 0);
6975 if (changed && legitimate_address_p (mode, x, FALSE))
6978 if (GET_CODE (XEXP (x, 0)) == REG)
6980 rtx temp = gen_reg_rtx (Pmode);
6981 rtx val = force_operand (XEXP (x, 1), temp);
6983 emit_move_insn (temp, val);
6989 else if (GET_CODE (XEXP (x, 1)) == REG)
6991 rtx temp = gen_reg_rtx (Pmode);
6992 rtx val = force_operand (XEXP (x, 0), temp);
6994 emit_move_insn (temp, val);
7004 /* Print an integer constant expression in assembler syntax. Addition
7005 and subtraction are the only arithmetic that may appear in these
7006 expressions. FILE is the stdio stream to write to, X is the rtx, and
7007 CODE is the operand print code from the output string. */
7010 output_pic_addr_const (FILE *file, rtx x, int code)
7014 switch (GET_CODE (x))
7017 gcc_assert (flag_pic);
7022 output_addr_const (file, x);
7023 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
7024 fputs ("@PLT", file);
7031 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
7032 assemble_name (asm_out_file, buf);
7036 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7040 /* This used to output parentheses around the expression,
7041 but that does not work on the 386 (either ATT or BSD assembler). */
7042 output_pic_addr_const (file, XEXP (x, 0), code);
7046 if (GET_MODE (x) == VOIDmode)
7048 /* We can use %d if the number is <32 bits and positive. */
7049 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
7050 fprintf (file, "0x%lx%08lx",
7051 (unsigned long) CONST_DOUBLE_HIGH (x),
7052 (unsigned long) CONST_DOUBLE_LOW (x));
7054 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
7057 /* We can't handle floating point constants;
7058 PRINT_OPERAND must handle them. */
7059 output_operand_lossage ("floating constant misused");
7063 /* Some assemblers need integer constants to appear first. */
7064 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
7066 output_pic_addr_const (file, XEXP (x, 0), code);
7068 output_pic_addr_const (file, XEXP (x, 1), code);
7072 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
7073 output_pic_addr_const (file, XEXP (x, 1), code);
7075 output_pic_addr_const (file, XEXP (x, 0), code);
7081 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
7082 output_pic_addr_const (file, XEXP (x, 0), code);
7084 output_pic_addr_const (file, XEXP (x, 1), code);
7086 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
7090 gcc_assert (XVECLEN (x, 0) == 1);
7091 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
7092 switch (XINT (x, 1))
7095 fputs ("@GOT", file);
7098 fputs ("@GOTOFF", file);
7100 case UNSPEC_GOTPCREL:
7101 fputs ("@GOTPCREL(%rip)", file);
7103 case UNSPEC_GOTTPOFF:
7104 /* FIXME: This might be @TPOFF in Sun ld too. */
7105 fputs ("@GOTTPOFF", file);
7108 fputs ("@TPOFF", file);
7112 fputs ("@TPOFF", file);
7114 fputs ("@NTPOFF", file);
7117 fputs ("@DTPOFF", file);
7119 case UNSPEC_GOTNTPOFF:
7121 fputs ("@GOTTPOFF(%rip)", file);
7123 fputs ("@GOTNTPOFF", file);
7125 case UNSPEC_INDNTPOFF:
7126 fputs ("@INDNTPOFF", file);
7129 output_operand_lossage ("invalid UNSPEC as operand");
7135 output_operand_lossage ("invalid expression as operand");
7139 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7140 We need to emit DTP-relative relocations. */
7143 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
7145 fputs (ASM_LONG, file);
7146 output_addr_const (file, x);
7147 fputs ("@DTPOFF", file);
7153 fputs (", 0", file);
7160 /* In the name of slightly smaller debug output, and to cater to
7161 general assembler lossage, recognize PIC+GOTOFF and turn it back
7162 into a direct symbol reference.
7164 On Darwin, this is necessary to avoid a crash, because Darwin
7165 has a different PIC label for each routine but the DWARF debugging
7166 information is not associated with any particular routine, so it's
7167 necessary to remove references to the PIC label from RTL stored by
7168 the DWARF output code. */
7171 ix86_delegitimize_address (rtx orig_x)
7174 /* reg_addend is NULL or a multiple of some register. */
7175 rtx reg_addend = NULL_RTX;
7176 /* const_addend is NULL or a const_int. */
7177 rtx const_addend = NULL_RTX;
7178 /* This is the result, or NULL. */
7179 rtx result = NULL_RTX;
7181 if (GET_CODE (x) == MEM)
7186 if (GET_CODE (x) != CONST
7187 || GET_CODE (XEXP (x, 0)) != UNSPEC
7188 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
7189 || GET_CODE (orig_x) != MEM)
7191 return XVECEXP (XEXP (x, 0), 0, 0);
7194 if (GET_CODE (x) != PLUS
7195 || GET_CODE (XEXP (x, 1)) != CONST)
7198 if (GET_CODE (XEXP (x, 0)) == REG
7199 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
7200 /* %ebx + GOT/GOTOFF */
7202 else if (GET_CODE (XEXP (x, 0)) == PLUS)
7204 /* %ebx + %reg * scale + GOT/GOTOFF */
7205 reg_addend = XEXP (x, 0);
7206 if (GET_CODE (XEXP (reg_addend, 0)) == REG
7207 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
7208 reg_addend = XEXP (reg_addend, 1);
7209 else if (GET_CODE (XEXP (reg_addend, 1)) == REG
7210 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
7211 reg_addend = XEXP (reg_addend, 0);
7214 if (GET_CODE (reg_addend) != REG
7215 && GET_CODE (reg_addend) != MULT
7216 && GET_CODE (reg_addend) != ASHIFT)
7222 x = XEXP (XEXP (x, 1), 0);
7223 if (GET_CODE (x) == PLUS
7224 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7226 const_addend = XEXP (x, 1);
7230 if (GET_CODE (x) == UNSPEC
7231 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
7232 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
7233 result = XVECEXP (x, 0, 0);
7235 if (TARGET_MACHO && darwin_local_data_pic (x)
7236 && GET_CODE (orig_x) != MEM)
7237 result = XEXP (x, 0);
7243 result = gen_rtx_PLUS (Pmode, result, const_addend);
7245 result = gen_rtx_PLUS (Pmode, reg_addend, result);
7250 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
7255 if (mode == CCFPmode || mode == CCFPUmode)
7257 enum rtx_code second_code, bypass_code;
7258 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
7259 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
7260 code = ix86_fp_compare_code_to_integer (code);
7264 code = reverse_condition (code);
7275 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
7279 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
7280 Those same assemblers have the same but opposite lossage on cmov. */
7281 gcc_assert (mode == CCmode);
7282 suffix = fp ? "nbe" : "a";
7302 gcc_assert (mode == CCmode);
7324 gcc_assert (mode == CCmode);
7325 suffix = fp ? "nb" : "ae";
7328 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
7332 gcc_assert (mode == CCmode);
7336 suffix = fp ? "u" : "p";
7339 suffix = fp ? "nu" : "np";
7344 fputs (suffix, file);
7347 /* Print the name of register X to FILE based on its machine mode and number.
7348 If CODE is 'w', pretend the mode is HImode.
7349 If CODE is 'b', pretend the mode is QImode.
7350 If CODE is 'k', pretend the mode is SImode.
7351 If CODE is 'q', pretend the mode is DImode.
7352 If CODE is 'h', pretend the reg is the 'high' byte register.
7353 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
7356 print_reg (rtx x, int code, FILE *file)
7358 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
7359 && REGNO (x) != FRAME_POINTER_REGNUM
7360 && REGNO (x) != FLAGS_REG
7361 && REGNO (x) != FPSR_REG);
7363 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
7366 if (code == 'w' || MMX_REG_P (x))
7368 else if (code == 'b')
7370 else if (code == 'k')
7372 else if (code == 'q')
7374 else if (code == 'y')
7376 else if (code == 'h')
7379 code = GET_MODE_SIZE (GET_MODE (x));
7381 /* Irritatingly, AMD extended registers use different naming convention
7382 from the normal registers. */
7383 if (REX_INT_REG_P (x))
7385 gcc_assert (TARGET_64BIT);
7389 error ("extended registers have no high halves");
7392 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
7395 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
7398 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
7401 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
7404 error ("unsupported operand size for extended register");
7412 if (STACK_TOP_P (x))
7414 fputs ("st(0)", file);
7421 if (! ANY_FP_REG_P (x))
7422 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
7427 fputs (hi_reg_name[REGNO (x)], file);
7430 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
7432 fputs (qi_reg_name[REGNO (x)], file);
7435 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
7437 fputs (qi_high_reg_name[REGNO (x)], file);
7444 /* Locate some local-dynamic symbol still in use by this function
7445 so that we can print its name in some tls_local_dynamic_base
7449 get_some_local_dynamic_name (void)
7453 if (cfun->machine->some_ld_name)
7454 return cfun->machine->some_ld_name;
7456 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
7458 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
7459 return cfun->machine->some_ld_name;
7465 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
7469 if (GET_CODE (x) == SYMBOL_REF
7470 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
7472 cfun->machine->some_ld_name = XSTR (x, 0);
7480 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
7481 C -- print opcode suffix for set/cmov insn.
7482 c -- like C, but print reversed condition
7483 F,f -- likewise, but for floating-point.
7484 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
7486 R -- print the prefix for register names.
7487 z -- print the opcode suffix for the size of the current operand.
7488 * -- print a star (in certain assembler syntax)
7489 A -- print an absolute memory reference.
7490 w -- print the operand as if it's a "word" (HImode) even if it isn't.
7491 s -- print a shift double count, followed by the assemblers argument
7493 b -- print the QImode name of the register for the indicated operand.
7494 %b0 would print %al if operands[0] is reg 0.
7495 w -- likewise, print the HImode name of the register.
7496 k -- likewise, print the SImode name of the register.
7497 q -- likewise, print the DImode name of the register.
7498 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
7499 y -- print "st(0)" instead of "st" as a register.
7500 D -- print condition for SSE cmp instruction.
7501 P -- if PIC, print an @PLT suffix.
7502 X -- don't print any sort of PIC '@' suffix for a symbol.
7503 & -- print some in-use local-dynamic symbol name.
7504 H -- print a memory address offset by 8; used for sse high-parts
7508 print_operand (FILE *file, rtx x, int code)
7515 if (ASSEMBLER_DIALECT == ASM_ATT)
7520 assemble_name (file, get_some_local_dynamic_name ());
7524 switch (ASSEMBLER_DIALECT)
7531 /* Intel syntax. For absolute addresses, registers should not
7532 be surrounded by braces. */
7533 if (GET_CODE (x) != REG)
7536 PRINT_OPERAND (file, x, 0);
7546 PRINT_OPERAND (file, x, 0);
7551 if (ASSEMBLER_DIALECT == ASM_ATT)
7556 if (ASSEMBLER_DIALECT == ASM_ATT)
7561 if (ASSEMBLER_DIALECT == ASM_ATT)
7566 if (ASSEMBLER_DIALECT == ASM_ATT)
7571 if (ASSEMBLER_DIALECT == ASM_ATT)
7576 if (ASSEMBLER_DIALECT == ASM_ATT)
7581 /* 387 opcodes don't get size suffixes if the operands are
7583 if (STACK_REG_P (x))
7586 /* Likewise if using Intel opcodes. */
7587 if (ASSEMBLER_DIALECT == ASM_INTEL)
7590 /* This is the size of op from size of operand. */
7591 switch (GET_MODE_SIZE (GET_MODE (x)))
7594 #ifdef HAVE_GAS_FILDS_FISTS
7600 if (GET_MODE (x) == SFmode)
7615 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
7617 #ifdef GAS_MNEMONICS
7643 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
7645 PRINT_OPERAND (file, x, 0);
7651 /* Little bit of braindamage here. The SSE compare instructions
7652 does use completely different names for the comparisons that the
7653 fp conditional moves. */
7654 switch (GET_CODE (x))
7669 fputs ("unord", file);
7673 fputs ("neq", file);
7677 fputs ("nlt", file);
7681 fputs ("nle", file);
7684 fputs ("ord", file);
7691 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7692 if (ASSEMBLER_DIALECT == ASM_ATT)
7694 switch (GET_MODE (x))
7696 case HImode: putc ('w', file); break;
7698 case SFmode: putc ('l', file); break;
7700 case DFmode: putc ('q', file); break;
7701 default: gcc_unreachable ();
7708 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
7711 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7712 if (ASSEMBLER_DIALECT == ASM_ATT)
7715 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
7718 /* Like above, but reverse condition */
7720 /* Check to see if argument to %c is really a constant
7721 and not a condition code which needs to be reversed. */
7722 if (!COMPARISON_P (x))
7724 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
7727 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
7730 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7731 if (ASSEMBLER_DIALECT == ASM_ATT)
7734 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
7738 /* It doesn't actually matter what mode we use here, as we're
7739 only going to use this for printing. */
7740 x = adjust_address_nv (x, DImode, 8);
7747 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
7750 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
7753 int pred_val = INTVAL (XEXP (x, 0));
7755 if (pred_val < REG_BR_PROB_BASE * 45 / 100
7756 || pred_val > REG_BR_PROB_BASE * 55 / 100)
7758 int taken = pred_val > REG_BR_PROB_BASE / 2;
7759 int cputaken = final_forward_branch_p (current_output_insn) == 0;
7761 /* Emit hints only in the case default branch prediction
7762 heuristics would fail. */
7763 if (taken != cputaken)
7765 /* We use 3e (DS) prefix for taken branches and
7766 2e (CS) prefix for not taken branches. */
7768 fputs ("ds ; ", file);
7770 fputs ("cs ; ", file);
7777 output_operand_lossage ("invalid operand code '%c'", code);
7781 if (GET_CODE (x) == REG)
7782 print_reg (x, code, file);
7784 else if (GET_CODE (x) == MEM)
7786 /* No `byte ptr' prefix for call instructions. */
7787 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
7790 switch (GET_MODE_SIZE (GET_MODE (x)))
7792 case 1: size = "BYTE"; break;
7793 case 2: size = "WORD"; break;
7794 case 4: size = "DWORD"; break;
7795 case 8: size = "QWORD"; break;
7796 case 12: size = "XWORD"; break;
7797 case 16: size = "XMMWORD"; break;
7802 /* Check for explicit size override (codes 'b', 'w' and 'k') */
7805 else if (code == 'w')
7807 else if (code == 'k')
7811 fputs (" PTR ", file);
7815 /* Avoid (%rip) for call operands. */
7816 if (CONSTANT_ADDRESS_P (x) && code == 'P'
7817 && GET_CODE (x) != CONST_INT)
7818 output_addr_const (file, x);
7819 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
7820 output_operand_lossage ("invalid constraints for operand");
7825 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7830 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7831 REAL_VALUE_TO_TARGET_SINGLE (r, l);
7833 if (ASSEMBLER_DIALECT == ASM_ATT)
7835 fprintf (file, "0x%08lx", l);
7838 /* These float cases don't actually occur as immediate operands. */
7839 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7843 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7844 fprintf (file, "%s", dstr);
7847 else if (GET_CODE (x) == CONST_DOUBLE
7848 && GET_MODE (x) == XFmode)
7852 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7853 fprintf (file, "%s", dstr);
7858 /* We have patterns that allow zero sets of memory, for instance.
7859 In 64-bit mode, we should probably support all 8-byte vectors,
7860 since we can in fact encode that into an immediate. */
7861 if (GET_CODE (x) == CONST_VECTOR)
7863 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
7869 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
7871 if (ASSEMBLER_DIALECT == ASM_ATT)
7874 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
7875 || GET_CODE (x) == LABEL_REF)
7877 if (ASSEMBLER_DIALECT == ASM_ATT)
7880 fputs ("OFFSET FLAT:", file);
7883 if (GET_CODE (x) == CONST_INT)
7884 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7886 output_pic_addr_const (file, x, code);
7888 output_addr_const (file, x);
7892 /* Print a memory operand whose address is ADDR. */
7895 print_operand_address (FILE *file, rtx addr)
7897 struct ix86_address parts;
7898 rtx base, index, disp;
7900 int ok = ix86_decompose_address (addr, &parts);
7905 index = parts.index;
7907 scale = parts.scale;
7915 if (USER_LABEL_PREFIX[0] == 0)
7917 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
7923 if (!base && !index)
7925 /* Displacement only requires special attention. */
7927 if (GET_CODE (disp) == CONST_INT)
7929 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
7931 if (USER_LABEL_PREFIX[0] == 0)
7933 fputs ("ds:", file);
7935 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
7938 output_pic_addr_const (file, disp, 0);
7940 output_addr_const (file, disp);
7942 /* Use one byte shorter RIP relative addressing for 64bit mode. */
7945 if (GET_CODE (disp) == CONST
7946 && GET_CODE (XEXP (disp, 0)) == PLUS
7947 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7948 disp = XEXP (XEXP (disp, 0), 0);
7949 if (GET_CODE (disp) == LABEL_REF
7950 || (GET_CODE (disp) == SYMBOL_REF
7951 && SYMBOL_REF_TLS_MODEL (disp) == 0))
7952 fputs ("(%rip)", file);
7957 if (ASSEMBLER_DIALECT == ASM_ATT)
7962 output_pic_addr_const (file, disp, 0);
7963 else if (GET_CODE (disp) == LABEL_REF)
7964 output_asm_label (disp);
7966 output_addr_const (file, disp);
7971 print_reg (base, 0, file);
7975 print_reg (index, 0, file);
7977 fprintf (file, ",%d", scale);
7983 rtx offset = NULL_RTX;
7987 /* Pull out the offset of a symbol; print any symbol itself. */
7988 if (GET_CODE (disp) == CONST
7989 && GET_CODE (XEXP (disp, 0)) == PLUS
7990 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7992 offset = XEXP (XEXP (disp, 0), 1);
7993 disp = gen_rtx_CONST (VOIDmode,
7994 XEXP (XEXP (disp, 0), 0));
7998 output_pic_addr_const (file, disp, 0);
7999 else if (GET_CODE (disp) == LABEL_REF)
8000 output_asm_label (disp);
8001 else if (GET_CODE (disp) == CONST_INT)
8004 output_addr_const (file, disp);
8010 print_reg (base, 0, file);
8013 if (INTVAL (offset) >= 0)
8015 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8019 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8026 print_reg (index, 0, file);
8028 fprintf (file, "*%d", scale);
8036 output_addr_const_extra (FILE *file, rtx x)
8040 if (GET_CODE (x) != UNSPEC)
8043 op = XVECEXP (x, 0, 0);
8044 switch (XINT (x, 1))
8046 case UNSPEC_GOTTPOFF:
8047 output_addr_const (file, op);
8048 /* FIXME: This might be @TPOFF in Sun ld. */
8049 fputs ("@GOTTPOFF", file);
8052 output_addr_const (file, op);
8053 fputs ("@TPOFF", file);
8056 output_addr_const (file, op);
8058 fputs ("@TPOFF", file);
8060 fputs ("@NTPOFF", file);
8063 output_addr_const (file, op);
8064 fputs ("@DTPOFF", file);
8066 case UNSPEC_GOTNTPOFF:
8067 output_addr_const (file, op);
8069 fputs ("@GOTTPOFF(%rip)", file);
8071 fputs ("@GOTNTPOFF", file);
8073 case UNSPEC_INDNTPOFF:
8074 output_addr_const (file, op);
8075 fputs ("@INDNTPOFF", file);
8085 /* Split one or more DImode RTL references into pairs of SImode
8086 references. The RTL can be REG, offsettable MEM, integer constant, or
8087 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8088 split and "num" is its length. lo_half and hi_half are output arrays
8089 that parallel "operands". */
8092 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8096 rtx op = operands[num];
8098 /* simplify_subreg refuse to split volatile memory addresses,
8099 but we still have to handle it. */
8100 if (GET_CODE (op) == MEM)
8102 lo_half[num] = adjust_address (op, SImode, 0);
8103 hi_half[num] = adjust_address (op, SImode, 4);
8107 lo_half[num] = simplify_gen_subreg (SImode, op,
8108 GET_MODE (op) == VOIDmode
8109 ? DImode : GET_MODE (op), 0);
8110 hi_half[num] = simplify_gen_subreg (SImode, op,
8111 GET_MODE (op) == VOIDmode
8112 ? DImode : GET_MODE (op), 4);
8116 /* Split one or more TImode RTL references into pairs of DImode
8117 references. The RTL can be REG, offsettable MEM, integer constant, or
8118 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8119 split and "num" is its length. lo_half and hi_half are output arrays
8120 that parallel "operands". */
8123 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8127 rtx op = operands[num];
8129 /* simplify_subreg refuse to split volatile memory addresses, but we
8130 still have to handle it. */
8131 if (GET_CODE (op) == MEM)
8133 lo_half[num] = adjust_address (op, DImode, 0);
8134 hi_half[num] = adjust_address (op, DImode, 8);
8138 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
8139 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
8144 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8145 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8146 is the expression of the binary operation. The output may either be
8147 emitted here, or returned to the caller, like all output_* functions.
8149 There is no guarantee that the operands are the same mode, as they
8150 might be within FLOAT or FLOAT_EXTEND expressions. */
8152 #ifndef SYSV386_COMPAT
8153 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8154 wants to fix the assemblers because that causes incompatibility
8155 with gcc. No-one wants to fix gcc because that causes
8156 incompatibility with assemblers... You can use the option of
8157 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8158 #define SYSV386_COMPAT 1
8162 output_387_binary_op (rtx insn, rtx *operands)
8164 static char buf[30];
8167 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
8169 #ifdef ENABLE_CHECKING
8170 /* Even if we do not want to check the inputs, this documents input
8171 constraints. Which helps in understanding the following code. */
8172 if (STACK_REG_P (operands[0])
8173 && ((REG_P (operands[1])
8174 && REGNO (operands[0]) == REGNO (operands[1])
8175 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
8176 || (REG_P (operands[2])
8177 && REGNO (operands[0]) == REGNO (operands[2])
8178 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
8179 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
8182 gcc_assert (is_sse);
8185 switch (GET_CODE (operands[3]))
8188 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8189 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8197 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8198 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8206 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8207 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8215 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8216 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8230 if (GET_MODE (operands[0]) == SFmode)
8231 strcat (buf, "ss\t{%2, %0|%0, %2}");
8233 strcat (buf, "sd\t{%2, %0|%0, %2}");
8238 switch (GET_CODE (operands[3]))
8242 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
8244 rtx temp = operands[2];
8245 operands[2] = operands[1];
8249 /* know operands[0] == operands[1]. */
8251 if (GET_CODE (operands[2]) == MEM)
8257 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8259 if (STACK_TOP_P (operands[0]))
8260 /* How is it that we are storing to a dead operand[2]?
8261 Well, presumably operands[1] is dead too. We can't
8262 store the result to st(0) as st(0) gets popped on this
8263 instruction. Instead store to operands[2] (which I
8264 think has to be st(1)). st(1) will be popped later.
8265 gcc <= 2.8.1 didn't have this check and generated
8266 assembly code that the Unixware assembler rejected. */
8267 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8269 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8273 if (STACK_TOP_P (operands[0]))
8274 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8276 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8281 if (GET_CODE (operands[1]) == MEM)
8287 if (GET_CODE (operands[2]) == MEM)
8293 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8296 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
8297 derived assemblers, confusingly reverse the direction of
8298 the operation for fsub{r} and fdiv{r} when the
8299 destination register is not st(0). The Intel assembler
8300 doesn't have this brain damage. Read !SYSV386_COMPAT to
8301 figure out what the hardware really does. */
8302 if (STACK_TOP_P (operands[0]))
8303 p = "{p\t%0, %2|rp\t%2, %0}";
8305 p = "{rp\t%2, %0|p\t%0, %2}";
8307 if (STACK_TOP_P (operands[0]))
8308 /* As above for fmul/fadd, we can't store to st(0). */
8309 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8311 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8316 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
8319 if (STACK_TOP_P (operands[0]))
8320 p = "{rp\t%0, %1|p\t%1, %0}";
8322 p = "{p\t%1, %0|rp\t%0, %1}";
8324 if (STACK_TOP_P (operands[0]))
8325 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
8327 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
8332 if (STACK_TOP_P (operands[0]))
8334 if (STACK_TOP_P (operands[1]))
8335 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8337 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
8340 else if (STACK_TOP_P (operands[1]))
8343 p = "{\t%1, %0|r\t%0, %1}";
8345 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
8351 p = "{r\t%2, %0|\t%0, %2}";
8353 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8366 /* Return needed mode for entity in optimize_mode_switching pass. */
8369 ix86_mode_needed (int entity, rtx insn)
8371 enum attr_i387_cw mode;
8373 /* The mode UNINITIALIZED is used to store control word after a
8374 function call or ASM pattern. The mode ANY specify that function
8375 has no requirements on the control word and make no changes in the
8376 bits we are interested in. */
8379 || (NONJUMP_INSN_P (insn)
8380 && (asm_noperands (PATTERN (insn)) >= 0
8381 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
8382 return I387_CW_UNINITIALIZED;
8384 if (recog_memoized (insn) < 0)
8387 mode = get_attr_i387_cw (insn);
8392 if (mode == I387_CW_TRUNC)
8397 if (mode == I387_CW_FLOOR)
8402 if (mode == I387_CW_CEIL)
8407 if (mode == I387_CW_MASK_PM)
8418 /* Output code to initialize control word copies used by trunc?f?i and
8419 rounding patterns. CURRENT_MODE is set to current control word,
8420 while NEW_MODE is set to new control word. */
8423 emit_i387_cw_initialization (int mode)
8425 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
8430 rtx reg = gen_reg_rtx (HImode);
8432 emit_insn (gen_x86_fnstcw_1 (stored_mode));
8433 emit_move_insn (reg, stored_mode);
8435 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
8440 /* round toward zero (truncate) */
8441 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
8442 slot = SLOT_CW_TRUNC;
8446 /* round down toward -oo */
8447 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8448 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
8449 slot = SLOT_CW_FLOOR;
8453 /* round up toward +oo */
8454 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8455 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
8456 slot = SLOT_CW_CEIL;
8459 case I387_CW_MASK_PM:
8460 /* mask precision exception for nearbyint() */
8461 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8462 slot = SLOT_CW_MASK_PM;
8474 /* round toward zero (truncate) */
8475 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
8476 slot = SLOT_CW_TRUNC;
8480 /* round down toward -oo */
8481 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
8482 slot = SLOT_CW_FLOOR;
8486 /* round up toward +oo */
8487 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
8488 slot = SLOT_CW_CEIL;
8491 case I387_CW_MASK_PM:
8492 /* mask precision exception for nearbyint() */
8493 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8494 slot = SLOT_CW_MASK_PM;
8502 gcc_assert (slot < MAX_386_STACK_LOCALS);
8504 new_mode = assign_386_stack_local (HImode, slot);
8505 emit_move_insn (new_mode, reg);
8508 /* Output code for INSN to convert a float to a signed int. OPERANDS
8509 are the insn operands. The output may be [HSD]Imode and the input
8510 operand may be [SDX]Fmode. */
8513 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
8515 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8516 int dimode_p = GET_MODE (operands[0]) == DImode;
8517 int round_mode = get_attr_i387_cw (insn);
8519 /* Jump through a hoop or two for DImode, since the hardware has no
8520 non-popping instruction. We used to do this a different way, but
8521 that was somewhat fragile and broke with post-reload splitters. */
8522 if ((dimode_p || fisttp) && !stack_top_dies)
8523 output_asm_insn ("fld\t%y1", operands);
8525 gcc_assert (STACK_TOP_P (operands[1]));
8526 gcc_assert (GET_CODE (operands[0]) == MEM);
8529 output_asm_insn ("fisttp%z0\t%0", operands);
8532 if (round_mode != I387_CW_ANY)
8533 output_asm_insn ("fldcw\t%3", operands);
8534 if (stack_top_dies || dimode_p)
8535 output_asm_insn ("fistp%z0\t%0", operands);
8537 output_asm_insn ("fist%z0\t%0", operands);
8538 if (round_mode != I387_CW_ANY)
8539 output_asm_insn ("fldcw\t%2", operands);
8545 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
8546 should be used. UNORDERED_P is true when fucom should be used. */
8549 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
8552 rtx cmp_op0, cmp_op1;
8553 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
8557 cmp_op0 = operands[0];
8558 cmp_op1 = operands[1];
8562 cmp_op0 = operands[1];
8563 cmp_op1 = operands[2];
8568 if (GET_MODE (operands[0]) == SFmode)
8570 return "ucomiss\t{%1, %0|%0, %1}";
8572 return "comiss\t{%1, %0|%0, %1}";
8575 return "ucomisd\t{%1, %0|%0, %1}";
8577 return "comisd\t{%1, %0|%0, %1}";
8580 gcc_assert (STACK_TOP_P (cmp_op0));
8582 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8584 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
8588 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
8589 return TARGET_USE_FFREEP ? "ffreep\t%y1" : "fstp\t%y1";
8592 return "ftst\n\tfnstsw\t%0";
8595 if (STACK_REG_P (cmp_op1)
8597 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
8598 && REGNO (cmp_op1) != FIRST_STACK_REG)
8600 /* If both the top of the 387 stack dies, and the other operand
8601 is also a stack register that dies, then this must be a
8602 `fcompp' float compare */
8606 /* There is no double popping fcomi variant. Fortunately,
8607 eflags is immune from the fstp's cc clobbering. */
8609 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
8611 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
8612 return TARGET_USE_FFREEP ? "ffreep\t%y0" : "fstp\t%y0";
8617 return "fucompp\n\tfnstsw\t%0";
8619 return "fcompp\n\tfnstsw\t%0";
8624 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
8626 static const char * const alt[16] =
8628 "fcom%z2\t%y2\n\tfnstsw\t%0",
8629 "fcomp%z2\t%y2\n\tfnstsw\t%0",
8630 "fucom%z2\t%y2\n\tfnstsw\t%0",
8631 "fucomp%z2\t%y2\n\tfnstsw\t%0",
8633 "ficom%z2\t%y2\n\tfnstsw\t%0",
8634 "ficomp%z2\t%y2\n\tfnstsw\t%0",
8638 "fcomi\t{%y1, %0|%0, %y1}",
8639 "fcomip\t{%y1, %0|%0, %y1}",
8640 "fucomi\t{%y1, %0|%0, %y1}",
8641 "fucomip\t{%y1, %0|%0, %y1}",
8652 mask = eflags_p << 3;
8653 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
8654 mask |= unordered_p << 1;
8655 mask |= stack_top_dies;
8657 gcc_assert (mask < 16);
8666 ix86_output_addr_vec_elt (FILE *file, int value)
8668 const char *directive = ASM_LONG;
8672 directive = ASM_QUAD;
8674 gcc_assert (!TARGET_64BIT);
8677 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
8681 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
8684 fprintf (file, "%s%s%d-%s%d\n",
8685 ASM_LONG, LPREFIX, value, LPREFIX, rel);
8686 else if (HAVE_AS_GOTOFF_IN_DATA)
8687 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
8689 else if (TARGET_MACHO)
8691 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
8692 machopic_output_function_base_name (file);
8693 fprintf(file, "\n");
8697 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
8698 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
8701 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
8705 ix86_expand_clear (rtx dest)
8709 /* We play register width games, which are only valid after reload. */
8710 gcc_assert (reload_completed);
8712 /* Avoid HImode and its attendant prefix byte. */
8713 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
8714 dest = gen_rtx_REG (SImode, REGNO (dest));
8716 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
8718 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
8719 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
8721 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
8722 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
8728 /* X is an unchanging MEM. If it is a constant pool reference, return
8729 the constant pool rtx, else NULL. */
8732 maybe_get_pool_constant (rtx x)
8734 x = ix86_delegitimize_address (XEXP (x, 0));
8736 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
8737 return get_pool_constant (x);
8743 ix86_expand_move (enum machine_mode mode, rtx operands[])
8745 int strict = (reload_in_progress || reload_completed);
8747 enum tls_model model;
8752 if (GET_CODE (op1) == SYMBOL_REF)
8754 model = SYMBOL_REF_TLS_MODEL (op1);
8757 op1 = legitimize_tls_address (op1, model, true);
8758 op1 = force_operand (op1, op0);
8763 else if (GET_CODE (op1) == CONST
8764 && GET_CODE (XEXP (op1, 0)) == PLUS
8765 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
8767 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
8770 rtx addend = XEXP (XEXP (op1, 0), 1);
8771 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
8772 op1 = force_operand (op1, NULL);
8773 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
8774 op0, 1, OPTAB_DIRECT);
8780 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
8785 rtx temp = ((reload_in_progress
8786 || ((op0 && GET_CODE (op0) == REG)
8788 ? op0 : gen_reg_rtx (Pmode));
8789 op1 = machopic_indirect_data_reference (op1, temp);
8790 op1 = machopic_legitimize_pic_address (op1, mode,
8791 temp == op1 ? 0 : temp);
8793 else if (MACHOPIC_INDIRECT)
8794 op1 = machopic_indirect_data_reference (op1, 0);
8798 if (GET_CODE (op0) == MEM)
8799 op1 = force_reg (Pmode, op1);
8801 op1 = legitimize_address (op1, op1, Pmode);
8802 #endif /* TARGET_MACHO */
8806 if (GET_CODE (op0) == MEM
8807 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
8808 || !push_operand (op0, mode))
8809 && GET_CODE (op1) == MEM)
8810 op1 = force_reg (mode, op1);
8812 if (push_operand (op0, mode)
8813 && ! general_no_elim_operand (op1, mode))
8814 op1 = copy_to_mode_reg (mode, op1);
8816 /* Force large constants in 64bit compilation into register
8817 to get them CSEed. */
8818 if (TARGET_64BIT && mode == DImode
8819 && immediate_operand (op1, mode)
8820 && !x86_64_zext_immediate_operand (op1, VOIDmode)
8821 && !register_operand (op0, mode)
8822 && optimize && !reload_completed && !reload_in_progress)
8823 op1 = copy_to_mode_reg (mode, op1);
8825 if (FLOAT_MODE_P (mode))
8827 /* If we are loading a floating point constant to a register,
8828 force the value to memory now, since we'll get better code
8829 out the back end. */
8833 else if (GET_CODE (op1) == CONST_DOUBLE)
8835 op1 = validize_mem (force_const_mem (mode, op1));
8836 if (!register_operand (op0, mode))
8838 rtx temp = gen_reg_rtx (mode);
8839 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
8840 emit_move_insn (op0, temp);
8847 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8851 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
8853 rtx op0 = operands[0], op1 = operands[1];
8855 /* Force constants other than zero into memory. We do not know how
8856 the instructions used to build constants modify the upper 64 bits
8857 of the register, once we have that information we may be able
8858 to handle some of them more efficiently. */
8859 if ((reload_in_progress | reload_completed) == 0
8860 && register_operand (op0, mode)
8861 && CONSTANT_P (op1) && op1 != CONST0_RTX (mode))
8862 op1 = validize_mem (force_const_mem (mode, op1));
8864 /* Make operand1 a register if it isn't already. */
8866 && !register_operand (op0, mode)
8867 && !register_operand (op1, mode))
8869 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
8873 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8876 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
8877 straight to ix86_expand_vector_move. */
8880 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
8889 /* If we're optimizing for size, movups is the smallest. */
8892 op0 = gen_lowpart (V4SFmode, op0);
8893 op1 = gen_lowpart (V4SFmode, op1);
8894 emit_insn (gen_sse_movups (op0, op1));
8898 /* ??? If we have typed data, then it would appear that using
8899 movdqu is the only way to get unaligned data loaded with
8901 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8903 op0 = gen_lowpart (V16QImode, op0);
8904 op1 = gen_lowpart (V16QImode, op1);
8905 emit_insn (gen_sse2_movdqu (op0, op1));
8909 if (TARGET_SSE2 && mode == V2DFmode)
8913 /* When SSE registers are split into halves, we can avoid
8914 writing to the top half twice. */
8915 if (TARGET_SSE_SPLIT_REGS)
8917 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8922 /* ??? Not sure about the best option for the Intel chips.
8923 The following would seem to satisfy; the register is
8924 entirely cleared, breaking the dependency chain. We
8925 then store to the upper half, with a dependency depth
8926 of one. A rumor has it that Intel recommends two movsd
8927 followed by an unpacklpd, but this is unconfirmed. And
8928 given that the dependency depth of the unpacklpd would
8929 still be one, I'm not sure why this would be better. */
8930 zero = CONST0_RTX (V2DFmode);
8933 m = adjust_address (op1, DFmode, 0);
8934 emit_insn (gen_sse2_loadlpd (op0, zero, m));
8935 m = adjust_address (op1, DFmode, 8);
8936 emit_insn (gen_sse2_loadhpd (op0, op0, m));
8940 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
8941 emit_move_insn (op0, CONST0_RTX (mode));
8943 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8945 if (mode != V4SFmode)
8946 op0 = gen_lowpart (V4SFmode, op0);
8947 m = adjust_address (op1, V2SFmode, 0);
8948 emit_insn (gen_sse_loadlps (op0, op0, m));
8949 m = adjust_address (op1, V2SFmode, 8);
8950 emit_insn (gen_sse_loadhps (op0, op0, m));
8953 else if (MEM_P (op0))
8955 /* If we're optimizing for size, movups is the smallest. */
8958 op0 = gen_lowpart (V4SFmode, op0);
8959 op1 = gen_lowpart (V4SFmode, op1);
8960 emit_insn (gen_sse_movups (op0, op1));
8964 /* ??? Similar to above, only less clear because of quote
8965 typeless stores unquote. */
8966 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
8967 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8969 op0 = gen_lowpart (V16QImode, op0);
8970 op1 = gen_lowpart (V16QImode, op1);
8971 emit_insn (gen_sse2_movdqu (op0, op1));
8975 if (TARGET_SSE2 && mode == V2DFmode)
8977 m = adjust_address (op0, DFmode, 0);
8978 emit_insn (gen_sse2_storelpd (m, op1));
8979 m = adjust_address (op0, DFmode, 8);
8980 emit_insn (gen_sse2_storehpd (m, op1));
8984 if (mode != V4SFmode)
8985 op1 = gen_lowpart (V4SFmode, op1);
8986 m = adjust_address (op0, V2SFmode, 0);
8987 emit_insn (gen_sse_storelps (m, op1));
8988 m = adjust_address (op0, V2SFmode, 8);
8989 emit_insn (gen_sse_storehps (m, op1));
8996 /* Expand a push in MODE. This is some mode for which we do not support
8997 proper push instructions, at least from the registers that we expect
8998 the value to live in. */
9001 ix86_expand_push (enum machine_mode mode, rtx x)
9005 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
9006 GEN_INT (-GET_MODE_SIZE (mode)),
9007 stack_pointer_rtx, 1, OPTAB_DIRECT);
9008 if (tmp != stack_pointer_rtx)
9009 emit_move_insn (stack_pointer_rtx, tmp);
9011 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
9012 emit_move_insn (tmp, x);
9015 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
9016 destination to use for the operation. If different from the true
9017 destination in operands[0], a copy operation will be required. */
9020 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
9023 int matching_memory;
9024 rtx src1, src2, dst;
9030 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
9031 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9032 && (rtx_equal_p (dst, src2)
9033 || immediate_operand (src1, mode)))
9040 /* If the destination is memory, and we do not have matching source
9041 operands, do things in registers. */
9042 matching_memory = 0;
9043 if (GET_CODE (dst) == MEM)
9045 if (rtx_equal_p (dst, src1))
9046 matching_memory = 1;
9047 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9048 && rtx_equal_p (dst, src2))
9049 matching_memory = 2;
9051 dst = gen_reg_rtx (mode);
9054 /* Both source operands cannot be in memory. */
9055 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
9057 if (matching_memory != 2)
9058 src2 = force_reg (mode, src2);
9060 src1 = force_reg (mode, src1);
9063 /* If the operation is not commutable, source 1 cannot be a constant
9064 or non-matching memory. */
9065 if ((CONSTANT_P (src1)
9066 || (!matching_memory && GET_CODE (src1) == MEM))
9067 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
9068 src1 = force_reg (mode, src1);
9070 src1 = operands[1] = src1;
9071 src2 = operands[2] = src2;
9075 /* Similarly, but assume that the destination has already been
9079 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
9080 enum machine_mode mode, rtx operands[])
9082 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
9083 gcc_assert (dst == operands[0]);
9086 /* Attempt to expand a binary operator. Make the expansion closer to the
9087 actual machine, then just general_operand, which will allow 3 separate
9088 memory references (one output, two input) in a single insn. */
9091 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
9094 rtx src1, src2, dst, op, clob;
9096 dst = ix86_fixup_binary_operands (code, mode, operands);
9100 /* Emit the instruction. */
9102 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
9103 if (reload_in_progress)
9105 /* Reload doesn't know about the flags register, and doesn't know that
9106 it doesn't want to clobber it. We can only do this with PLUS. */
9107 gcc_assert (code == PLUS);
9112 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9113 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9116 /* Fix up the destination if needed. */
9117 if (dst != operands[0])
9118 emit_move_insn (operands[0], dst);
9121 /* Return TRUE or FALSE depending on whether the binary operator meets the
9122 appropriate constraints. */
9125 ix86_binary_operator_ok (enum rtx_code code,
9126 enum machine_mode mode ATTRIBUTE_UNUSED,
9129 /* Both source operands cannot be in memory. */
9130 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
9132 /* If the operation is not commutable, source 1 cannot be a constant. */
9133 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
9135 /* If the destination is memory, we must have a matching source operand. */
9136 if (GET_CODE (operands[0]) == MEM
9137 && ! (rtx_equal_p (operands[0], operands[1])
9138 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9139 && rtx_equal_p (operands[0], operands[2]))))
9141 /* If the operation is not commutable and the source 1 is memory, we must
9142 have a matching destination. */
9143 if (GET_CODE (operands[1]) == MEM
9144 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
9145 && ! rtx_equal_p (operands[0], operands[1]))
9150 /* Attempt to expand a unary operator. Make the expansion closer to the
9151 actual machine, then just general_operand, which will allow 2 separate
9152 memory references (one output, one input) in a single insn. */
9155 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
9158 int matching_memory;
9159 rtx src, dst, op, clob;
9164 /* If the destination is memory, and we do not have matching source
9165 operands, do things in registers. */
9166 matching_memory = 0;
9169 if (rtx_equal_p (dst, src))
9170 matching_memory = 1;
9172 dst = gen_reg_rtx (mode);
9175 /* When source operand is memory, destination must match. */
9176 if (MEM_P (src) && !matching_memory)
9177 src = force_reg (mode, src);
9179 /* Emit the instruction. */
9181 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
9182 if (reload_in_progress || code == NOT)
9184 /* Reload doesn't know about the flags register, and doesn't know that
9185 it doesn't want to clobber it. */
9186 gcc_assert (code == NOT);
9191 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9192 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9195 /* Fix up the destination if needed. */
9196 if (dst != operands[0])
9197 emit_move_insn (operands[0], dst);
9200 /* Return TRUE or FALSE depending on whether the unary operator meets the
9201 appropriate constraints. */
9204 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
9205 enum machine_mode mode ATTRIBUTE_UNUSED,
9206 rtx operands[2] ATTRIBUTE_UNUSED)
9208 /* If one of operands is memory, source and destination must match. */
9209 if ((GET_CODE (operands[0]) == MEM
9210 || GET_CODE (operands[1]) == MEM)
9211 && ! rtx_equal_p (operands[0], operands[1]))
9216 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
9217 Create a mask for the sign bit in MODE for an SSE register. If VECT is
9218 true, then replicate the mask for all elements of the vector register.
9219 If INVERT is true, then create a mask excluding the sign bit. */
9222 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
9224 enum machine_mode vec_mode;
9225 HOST_WIDE_INT hi, lo;
9230 /* Find the sign bit, sign extended to 2*HWI. */
9232 lo = 0x80000000, hi = lo < 0;
9233 else if (HOST_BITS_PER_WIDE_INT >= 64)
9234 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
9236 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
9241 /* Force this value into the low part of a fp vector constant. */
9242 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
9243 mask = gen_lowpart (mode, mask);
9248 v = gen_rtvec (4, mask, mask, mask, mask);
9250 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
9251 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9252 vec_mode = V4SFmode;
9257 v = gen_rtvec (2, mask, mask);
9259 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
9260 vec_mode = V2DFmode;
9263 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
9266 /* Generate code for floating point ABS or NEG. */
9269 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
9272 rtx mask, set, use, clob, dst, src;
9273 bool matching_memory;
9274 bool use_sse = false;
9275 bool vector_mode = VECTOR_MODE_P (mode);
9276 enum machine_mode elt_mode = mode;
9280 elt_mode = GET_MODE_INNER (mode);
9283 else if (TARGET_SSE_MATH)
9284 use_sse = SSE_FLOAT_MODE_P (mode);
9286 /* NEG and ABS performed with SSE use bitwise mask operations.
9287 Create the appropriate mask now. */
9289 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
9296 /* If the destination is memory, and we don't have matching source
9297 operands or we're using the x87, do things in registers. */
9298 matching_memory = false;
9301 if (use_sse && rtx_equal_p (dst, src))
9302 matching_memory = true;
9304 dst = gen_reg_rtx (mode);
9306 if (MEM_P (src) && !matching_memory)
9307 src = force_reg (mode, src);
9311 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
9312 set = gen_rtx_SET (VOIDmode, dst, set);
9317 set = gen_rtx_fmt_e (code, mode, src);
9318 set = gen_rtx_SET (VOIDmode, dst, set);
9321 use = gen_rtx_USE (VOIDmode, mask);
9322 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9323 emit_insn (gen_rtx_PARALLEL (VOIDmode,
9324 gen_rtvec (3, set, use, clob)));
9330 if (dst != operands[0])
9331 emit_move_insn (operands[0], dst);
9334 /* Expand a copysign operation. Special case operand 0 being a constant. */
9337 ix86_expand_copysign (rtx operands[])
9339 enum machine_mode mode, vmode;
9340 rtx dest, op0, op1, mask, nmask;
9346 mode = GET_MODE (dest);
9347 vmode = mode == SFmode ? V4SFmode : V2DFmode;
9349 if (GET_CODE (op0) == CONST_DOUBLE)
9353 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
9354 op0 = simplify_unary_operation (ABS, mode, op0, mode);
9356 if (op0 == CONST0_RTX (mode))
9357 op0 = CONST0_RTX (vmode);
9361 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
9362 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9364 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
9365 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
9368 mask = ix86_build_signbit_mask (mode, 0, 0);
9371 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
9373 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
9377 nmask = ix86_build_signbit_mask (mode, 0, 1);
9378 mask = ix86_build_signbit_mask (mode, 0, 0);
9381 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
9383 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
9387 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
9388 be a constant, and so has already been expanded into a vector constant. */
9391 ix86_split_copysign_const (rtx operands[])
9393 enum machine_mode mode, vmode;
9394 rtx dest, op0, op1, mask, x;
9401 mode = GET_MODE (dest);
9402 vmode = GET_MODE (mask);
9404 dest = simplify_gen_subreg (vmode, dest, mode, 0);
9405 x = gen_rtx_AND (vmode, dest, mask);
9406 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9408 if (op0 != CONST0_RTX (vmode))
9410 x = gen_rtx_IOR (vmode, dest, op0);
9411 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9415 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
9416 so we have to do two masks. */
9419 ix86_split_copysign_var (rtx operands[])
9421 enum machine_mode mode, vmode;
9422 rtx dest, scratch, op0, op1, mask, nmask, x;
9425 scratch = operands[1];
9428 nmask = operands[4];
9431 mode = GET_MODE (dest);
9432 vmode = GET_MODE (mask);
9434 if (rtx_equal_p (op0, op1))
9436 /* Shouldn't happen often (it's useless, obviously), but when it does
9437 we'd generate incorrect code if we continue below. */
9438 emit_move_insn (dest, op0);
9442 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
9444 gcc_assert (REGNO (op1) == REGNO (scratch));
9446 x = gen_rtx_AND (vmode, scratch, mask);
9447 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9450 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9451 x = gen_rtx_NOT (vmode, dest);
9452 x = gen_rtx_AND (vmode, x, op0);
9453 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9457 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
9459 x = gen_rtx_AND (vmode, scratch, mask);
9461 else /* alternative 2,4 */
9463 gcc_assert (REGNO (mask) == REGNO (scratch));
9464 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
9465 x = gen_rtx_AND (vmode, scratch, op1);
9467 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9469 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
9471 dest = simplify_gen_subreg (vmode, op0, mode, 0);
9472 x = gen_rtx_AND (vmode, dest, nmask);
9474 else /* alternative 3,4 */
9476 gcc_assert (REGNO (nmask) == REGNO (dest));
9478 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9479 x = gen_rtx_AND (vmode, dest, op0);
9481 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9484 x = gen_rtx_IOR (vmode, dest, scratch);
9485 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9488 /* Return TRUE or FALSE depending on whether the first SET in INSN
9489 has source and destination with matching CC modes, and that the
9490 CC mode is at least as constrained as REQ_MODE. */
9493 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
9496 enum machine_mode set_mode;
9498 set = PATTERN (insn);
9499 if (GET_CODE (set) == PARALLEL)
9500 set = XVECEXP (set, 0, 0);
9501 gcc_assert (GET_CODE (set) == SET);
9502 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
9504 set_mode = GET_MODE (SET_DEST (set));
9508 if (req_mode != CCNOmode
9509 && (req_mode != CCmode
9510 || XEXP (SET_SRC (set), 1) != const0_rtx))
9514 if (req_mode == CCGCmode)
9518 if (req_mode == CCGOCmode || req_mode == CCNOmode)
9522 if (req_mode == CCZmode)
9532 return (GET_MODE (SET_SRC (set)) == set_mode);
9535 /* Generate insn patterns to do an integer compare of OPERANDS. */
9538 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
9540 enum machine_mode cmpmode;
9543 cmpmode = SELECT_CC_MODE (code, op0, op1);
9544 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
9546 /* This is very simple, but making the interface the same as in the
9547 FP case makes the rest of the code easier. */
9548 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
9549 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
9551 /* Return the test that should be put into the flags user, i.e.
9552 the bcc, scc, or cmov instruction. */
9553 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
9556 /* Figure out whether to use ordered or unordered fp comparisons.
9557 Return the appropriate mode to use. */
9560 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
9562 /* ??? In order to make all comparisons reversible, we do all comparisons
9563 non-trapping when compiling for IEEE. Once gcc is able to distinguish
9564 all forms trapping and nontrapping comparisons, we can make inequality
9565 comparisons trapping again, since it results in better code when using
9566 FCOM based compares. */
9567 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
9571 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
9573 if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
9574 return ix86_fp_compare_mode (code);
9577 /* Only zero flag is needed. */
9579 case NE: /* ZF!=0 */
9581 /* Codes needing carry flag. */
9582 case GEU: /* CF=0 */
9583 case GTU: /* CF=0 & ZF=0 */
9584 case LTU: /* CF=1 */
9585 case LEU: /* CF=1 | ZF=1 */
9587 /* Codes possibly doable only with sign flag when
9588 comparing against zero. */
9589 case GE: /* SF=OF or SF=0 */
9590 case LT: /* SF<>OF or SF=1 */
9591 if (op1 == const0_rtx)
9594 /* For other cases Carry flag is not required. */
9596 /* Codes doable only with sign flag when comparing
9597 against zero, but we miss jump instruction for it
9598 so we need to use relational tests against overflow
9599 that thus needs to be zero. */
9600 case GT: /* ZF=0 & SF=OF */
9601 case LE: /* ZF=1 | SF<>OF */
9602 if (op1 == const0_rtx)
9606 /* strcmp pattern do (use flags) and combine may ask us for proper
9615 /* Return the fixed registers used for condition codes. */
9618 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9625 /* If two condition code modes are compatible, return a condition code
9626 mode which is compatible with both. Otherwise, return
9629 static enum machine_mode
9630 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
9635 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
9638 if ((m1 == CCGCmode && m2 == CCGOCmode)
9639 || (m1 == CCGOCmode && m2 == CCGCmode))
9667 /* These are only compatible with themselves, which we already
9673 /* Return true if we should use an FCOMI instruction for this fp comparison. */
9676 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
9678 enum rtx_code swapped_code = swap_condition (code);
9679 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
9680 || (ix86_fp_comparison_cost (swapped_code)
9681 == ix86_fp_comparison_fcomi_cost (swapped_code)));
9684 /* Swap, force into registers, or otherwise massage the two operands
9685 to a fp comparison. The operands are updated in place; the new
9686 comparison code is returned. */
9688 static enum rtx_code
9689 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
9691 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
9692 rtx op0 = *pop0, op1 = *pop1;
9693 enum machine_mode op_mode = GET_MODE (op0);
9694 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
9696 /* All of the unordered compare instructions only work on registers.
9697 The same is true of the fcomi compare instructions. The XFmode
9698 compare instructions require registers except when comparing
9699 against zero or when converting operand 1 from fixed point to
9703 && (fpcmp_mode == CCFPUmode
9704 || (op_mode == XFmode
9705 && ! (standard_80387_constant_p (op0) == 1
9706 || standard_80387_constant_p (op1) == 1)
9707 && GET_CODE (op1) != FLOAT)
9708 || ix86_use_fcomi_compare (code)))
9710 op0 = force_reg (op_mode, op0);
9711 op1 = force_reg (op_mode, op1);
9715 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
9716 things around if they appear profitable, otherwise force op0
9719 if (standard_80387_constant_p (op0) == 0
9720 || (GET_CODE (op0) == MEM
9721 && ! (standard_80387_constant_p (op1) == 0
9722 || GET_CODE (op1) == MEM)))
9725 tmp = op0, op0 = op1, op1 = tmp;
9726 code = swap_condition (code);
9729 if (GET_CODE (op0) != REG)
9730 op0 = force_reg (op_mode, op0);
9732 if (CONSTANT_P (op1))
9734 int tmp = standard_80387_constant_p (op1);
9736 op1 = validize_mem (force_const_mem (op_mode, op1));
9740 op1 = force_reg (op_mode, op1);
9743 op1 = force_reg (op_mode, op1);
9747 /* Try to rearrange the comparison to make it cheaper. */
9748 if (ix86_fp_comparison_cost (code)
9749 > ix86_fp_comparison_cost (swap_condition (code))
9750 && (GET_CODE (op1) == REG || !no_new_pseudos))
9753 tmp = op0, op0 = op1, op1 = tmp;
9754 code = swap_condition (code);
9755 if (GET_CODE (op0) != REG)
9756 op0 = force_reg (op_mode, op0);
9764 /* Convert comparison codes we use to represent FP comparison to integer
9765 code that will result in proper branch. Return UNKNOWN if no such code
9769 ix86_fp_compare_code_to_integer (enum rtx_code code)
9798 /* Split comparison code CODE into comparisons we can do using branch
9799 instructions. BYPASS_CODE is comparison code for branch that will
9800 branch around FIRST_CODE and SECOND_CODE. If some of branches
9801 is not required, set value to UNKNOWN.
9802 We never require more than two branches. */
9805 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
9806 enum rtx_code *first_code,
9807 enum rtx_code *second_code)
9810 *bypass_code = UNKNOWN;
9811 *second_code = UNKNOWN;
9813 /* The fcomi comparison sets flags as follows:
9823 case GT: /* GTU - CF=0 & ZF=0 */
9824 case GE: /* GEU - CF=0 */
9825 case ORDERED: /* PF=0 */
9826 case UNORDERED: /* PF=1 */
9827 case UNEQ: /* EQ - ZF=1 */
9828 case UNLT: /* LTU - CF=1 */
9829 case UNLE: /* LEU - CF=1 | ZF=1 */
9830 case LTGT: /* EQ - ZF=0 */
9832 case LT: /* LTU - CF=1 - fails on unordered */
9834 *bypass_code = UNORDERED;
9836 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
9838 *bypass_code = UNORDERED;
9840 case EQ: /* EQ - ZF=1 - fails on unordered */
9842 *bypass_code = UNORDERED;
9844 case NE: /* NE - ZF=0 - fails on unordered */
9846 *second_code = UNORDERED;
9848 case UNGE: /* GEU - CF=0 - fails on unordered */
9850 *second_code = UNORDERED;
9852 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
9854 *second_code = UNORDERED;
9859 if (!TARGET_IEEE_FP)
9861 *second_code = UNKNOWN;
9862 *bypass_code = UNKNOWN;
9866 /* Return cost of comparison done fcom + arithmetics operations on AX.
9867 All following functions do use number of instructions as a cost metrics.
9868 In future this should be tweaked to compute bytes for optimize_size and
9869 take into account performance of various instructions on various CPUs. */
9871 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
9873 if (!TARGET_IEEE_FP)
9875 /* The cost of code output by ix86_expand_fp_compare. */
9903 /* Return cost of comparison done using fcomi operation.
9904 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9906 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
9908 enum rtx_code bypass_code, first_code, second_code;
9909 /* Return arbitrarily high cost when instruction is not supported - this
9910 prevents gcc from using it. */
9913 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9914 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
9917 /* Return cost of comparison done using sahf operation.
9918 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9920 ix86_fp_comparison_sahf_cost (enum rtx_code code)
9922 enum rtx_code bypass_code, first_code, second_code;
9923 /* Return arbitrarily high cost when instruction is not preferred - this
9924 avoids gcc from using it. */
9925 if (!TARGET_USE_SAHF && !optimize_size)
9927 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9928 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
9931 /* Compute cost of the comparison done using any method.
9932 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9934 ix86_fp_comparison_cost (enum rtx_code code)
9936 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
9939 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
9940 sahf_cost = ix86_fp_comparison_sahf_cost (code);
9942 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
9943 if (min > sahf_cost)
9945 if (min > fcomi_cost)
9950 /* Generate insn patterns to do a floating point compare of OPERANDS. */
9953 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
9954 rtx *second_test, rtx *bypass_test)
9956 enum machine_mode fpcmp_mode, intcmp_mode;
9958 int cost = ix86_fp_comparison_cost (code);
9959 enum rtx_code bypass_code, first_code, second_code;
9961 fpcmp_mode = ix86_fp_compare_mode (code);
9962 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
9965 *second_test = NULL_RTX;
9967 *bypass_test = NULL_RTX;
9969 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9971 /* Do fcomi/sahf based test when profitable. */
9972 if ((bypass_code == UNKNOWN || bypass_test)
9973 && (second_code == UNKNOWN || second_test)
9974 && ix86_fp_comparison_arithmetics_cost (code) > cost)
9978 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9979 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
9985 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9986 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9988 scratch = gen_reg_rtx (HImode);
9989 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9990 emit_insn (gen_x86_sahf_1 (scratch));
9993 /* The FP codes work out to act like unsigned. */
9994 intcmp_mode = fpcmp_mode;
9996 if (bypass_code != UNKNOWN)
9997 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
9998 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10000 if (second_code != UNKNOWN)
10001 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
10002 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10007 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
10008 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
10009 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
10011 scratch = gen_reg_rtx (HImode);
10012 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
10014 /* In the unordered case, we have to check C2 for NaN's, which
10015 doesn't happen to work out to anything nice combination-wise.
10016 So do some bit twiddling on the value we've got in AH to come
10017 up with an appropriate set of condition codes. */
10019 intcmp_mode = CCNOmode;
10024 if (code == GT || !TARGET_IEEE_FP)
10026 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
10031 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10032 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
10033 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
10034 intcmp_mode = CCmode;
10040 if (code == LT && TARGET_IEEE_FP)
10042 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10043 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
10044 intcmp_mode = CCmode;
10049 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
10055 if (code == GE || !TARGET_IEEE_FP)
10057 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
10062 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10063 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
10070 if (code == LE && TARGET_IEEE_FP)
10072 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10073 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
10074 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
10075 intcmp_mode = CCmode;
10080 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
10086 if (code == EQ && TARGET_IEEE_FP)
10088 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10089 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
10090 intcmp_mode = CCmode;
10095 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10102 if (code == NE && TARGET_IEEE_FP)
10104 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10105 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
10111 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10117 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10121 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10126 gcc_unreachable ();
10130 /* Return the test that should be put into the flags user, i.e.
10131 the bcc, scc, or cmov instruction. */
10132 return gen_rtx_fmt_ee (code, VOIDmode,
10133 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10138 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
10141 op0 = ix86_compare_op0;
10142 op1 = ix86_compare_op1;
10145 *second_test = NULL_RTX;
10147 *bypass_test = NULL_RTX;
10149 if (ix86_compare_emitted)
10151 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
10152 ix86_compare_emitted = NULL_RTX;
10154 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
10155 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10156 second_test, bypass_test);
10158 ret = ix86_expand_int_compare (code, op0, op1);
10163 /* Return true if the CODE will result in nontrivial jump sequence. */
10165 ix86_fp_jump_nontrivial_p (enum rtx_code code)
10167 enum rtx_code bypass_code, first_code, second_code;
10170 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10171 return bypass_code != UNKNOWN || second_code != UNKNOWN;
10175 ix86_expand_branch (enum rtx_code code, rtx label)
10179 /* If we have emitted a compare insn, go straight to simple.
10180 ix86_expand_compare won't emit anything if ix86_compare_emitted
10182 if (ix86_compare_emitted)
10185 switch (GET_MODE (ix86_compare_op0))
10191 tmp = ix86_expand_compare (code, NULL, NULL);
10192 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10193 gen_rtx_LABEL_REF (VOIDmode, label),
10195 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10204 enum rtx_code bypass_code, first_code, second_code;
10206 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
10207 &ix86_compare_op1);
10209 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10211 /* Check whether we will use the natural sequence with one jump. If
10212 so, we can expand jump early. Otherwise delay expansion by
10213 creating compound insn to not confuse optimizers. */
10214 if (bypass_code == UNKNOWN && second_code == UNKNOWN
10217 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
10218 gen_rtx_LABEL_REF (VOIDmode, label),
10219 pc_rtx, NULL_RTX, NULL_RTX);
10223 tmp = gen_rtx_fmt_ee (code, VOIDmode,
10224 ix86_compare_op0, ix86_compare_op1);
10225 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10226 gen_rtx_LABEL_REF (VOIDmode, label),
10228 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
10230 use_fcomi = ix86_use_fcomi_compare (code);
10231 vec = rtvec_alloc (3 + !use_fcomi);
10232 RTVEC_ELT (vec, 0) = tmp;
10234 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
10236 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
10239 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
10241 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
10250 /* Expand DImode branch into multiple compare+branch. */
10252 rtx lo[2], hi[2], label2;
10253 enum rtx_code code1, code2, code3;
10254 enum machine_mode submode;
10256 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
10258 tmp = ix86_compare_op0;
10259 ix86_compare_op0 = ix86_compare_op1;
10260 ix86_compare_op1 = tmp;
10261 code = swap_condition (code);
10263 if (GET_MODE (ix86_compare_op0) == DImode)
10265 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
10266 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
10271 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
10272 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
10276 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
10277 avoid two branches. This costs one extra insn, so disable when
10278 optimizing for size. */
10280 if ((code == EQ || code == NE)
10282 || hi[1] == const0_rtx || lo[1] == const0_rtx))
10287 if (hi[1] != const0_rtx)
10288 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
10289 NULL_RTX, 0, OPTAB_WIDEN);
10292 if (lo[1] != const0_rtx)
10293 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
10294 NULL_RTX, 0, OPTAB_WIDEN);
10296 tmp = expand_binop (submode, ior_optab, xor1, xor0,
10297 NULL_RTX, 0, OPTAB_WIDEN);
10299 ix86_compare_op0 = tmp;
10300 ix86_compare_op1 = const0_rtx;
10301 ix86_expand_branch (code, label);
10305 /* Otherwise, if we are doing less-than or greater-or-equal-than,
10306 op1 is a constant and the low word is zero, then we can just
10307 examine the high word. */
10309 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
10312 case LT: case LTU: case GE: case GEU:
10313 ix86_compare_op0 = hi[0];
10314 ix86_compare_op1 = hi[1];
10315 ix86_expand_branch (code, label);
10321 /* Otherwise, we need two or three jumps. */
10323 label2 = gen_label_rtx ();
10326 code2 = swap_condition (code);
10327 code3 = unsigned_condition (code);
10331 case LT: case GT: case LTU: case GTU:
10334 case LE: code1 = LT; code2 = GT; break;
10335 case GE: code1 = GT; code2 = LT; break;
10336 case LEU: code1 = LTU; code2 = GTU; break;
10337 case GEU: code1 = GTU; code2 = LTU; break;
10339 case EQ: code1 = UNKNOWN; code2 = NE; break;
10340 case NE: code2 = UNKNOWN; break;
10343 gcc_unreachable ();
10348 * if (hi(a) < hi(b)) goto true;
10349 * if (hi(a) > hi(b)) goto false;
10350 * if (lo(a) < lo(b)) goto true;
10354 ix86_compare_op0 = hi[0];
10355 ix86_compare_op1 = hi[1];
10357 if (code1 != UNKNOWN)
10358 ix86_expand_branch (code1, label);
10359 if (code2 != UNKNOWN)
10360 ix86_expand_branch (code2, label2);
10362 ix86_compare_op0 = lo[0];
10363 ix86_compare_op1 = lo[1];
10364 ix86_expand_branch (code3, label);
10366 if (code2 != UNKNOWN)
10367 emit_label (label2);
10372 gcc_unreachable ();
10376 /* Split branch based on floating point condition. */
10378 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
10379 rtx target1, rtx target2, rtx tmp, rtx pushed)
10381 rtx second, bypass;
10382 rtx label = NULL_RTX;
10384 int bypass_probability = -1, second_probability = -1, probability = -1;
10387 if (target2 != pc_rtx)
10390 code = reverse_condition_maybe_unordered (code);
10395 condition = ix86_expand_fp_compare (code, op1, op2,
10396 tmp, &second, &bypass);
10398 /* Remove pushed operand from stack. */
10400 ix86_free_from_memory (GET_MODE (pushed));
10402 if (split_branch_probability >= 0)
10404 /* Distribute the probabilities across the jumps.
10405 Assume the BYPASS and SECOND to be always test
10407 probability = split_branch_probability;
10409 /* Value of 1 is low enough to make no need for probability
10410 to be updated. Later we may run some experiments and see
10411 if unordered values are more frequent in practice. */
10413 bypass_probability = 1;
10415 second_probability = 1;
10417 if (bypass != NULL_RTX)
10419 label = gen_label_rtx ();
10420 i = emit_jump_insn (gen_rtx_SET
10422 gen_rtx_IF_THEN_ELSE (VOIDmode,
10424 gen_rtx_LABEL_REF (VOIDmode,
10427 if (bypass_probability >= 0)
10429 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10430 GEN_INT (bypass_probability),
10433 i = emit_jump_insn (gen_rtx_SET
10435 gen_rtx_IF_THEN_ELSE (VOIDmode,
10436 condition, target1, target2)));
10437 if (probability >= 0)
10439 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10440 GEN_INT (probability),
10442 if (second != NULL_RTX)
10444 i = emit_jump_insn (gen_rtx_SET
10446 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
10448 if (second_probability >= 0)
10450 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10451 GEN_INT (second_probability),
10454 if (label != NULL_RTX)
10455 emit_label (label);
10459 ix86_expand_setcc (enum rtx_code code, rtx dest)
10461 rtx ret, tmp, tmpreg, equiv;
10462 rtx second_test, bypass_test;
10464 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
10465 return 0; /* FAIL */
10467 gcc_assert (GET_MODE (dest) == QImode);
10469 ret = ix86_expand_compare (code, &second_test, &bypass_test);
10470 PUT_MODE (ret, QImode);
10475 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
10476 if (bypass_test || second_test)
10478 rtx test = second_test;
10480 rtx tmp2 = gen_reg_rtx (QImode);
10483 gcc_assert (!second_test);
10484 test = bypass_test;
10486 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
10488 PUT_MODE (test, QImode);
10489 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
10492 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
10494 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
10497 /* Attach a REG_EQUAL note describing the comparison result. */
10498 if (ix86_compare_op0 && ix86_compare_op1)
10500 equiv = simplify_gen_relational (code, QImode,
10501 GET_MODE (ix86_compare_op0),
10502 ix86_compare_op0, ix86_compare_op1);
10503 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
10506 return 1; /* DONE */
10509 /* Expand comparison setting or clearing carry flag. Return true when
10510 successful and set pop for the operation. */
10512 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
10514 enum machine_mode mode =
10515 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
10517 /* Do not handle DImode compares that go through special path. Also we can't
10518 deal with FP compares yet. This is possible to add. */
10519 if (mode == (TARGET_64BIT ? TImode : DImode))
10521 if (FLOAT_MODE_P (mode))
10523 rtx second_test = NULL, bypass_test = NULL;
10524 rtx compare_op, compare_seq;
10526 /* Shortcut: following common codes never translate into carry flag compares. */
10527 if (code == EQ || code == NE || code == UNEQ || code == LTGT
10528 || code == ORDERED || code == UNORDERED)
10531 /* These comparisons require zero flag; swap operands so they won't. */
10532 if ((code == GT || code == UNLE || code == LE || code == UNGT)
10533 && !TARGET_IEEE_FP)
10538 code = swap_condition (code);
10541 /* Try to expand the comparison and verify that we end up with carry flag
10542 based comparison. This is fails to be true only when we decide to expand
10543 comparison using arithmetic that is not too common scenario. */
10545 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10546 &second_test, &bypass_test);
10547 compare_seq = get_insns ();
10550 if (second_test || bypass_test)
10552 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10553 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10554 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
10556 code = GET_CODE (compare_op);
10557 if (code != LTU && code != GEU)
10559 emit_insn (compare_seq);
10563 if (!INTEGRAL_MODE_P (mode))
10571 /* Convert a==0 into (unsigned)a<1. */
10574 if (op1 != const0_rtx)
10577 code = (code == EQ ? LTU : GEU);
10580 /* Convert a>b into b<a or a>=b-1. */
10583 if (GET_CODE (op1) == CONST_INT)
10585 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
10586 /* Bail out on overflow. We still can swap operands but that
10587 would force loading of the constant into register. */
10588 if (op1 == const0_rtx
10589 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
10591 code = (code == GTU ? GEU : LTU);
10598 code = (code == GTU ? LTU : GEU);
10602 /* Convert a>=0 into (unsigned)a<0x80000000. */
10605 if (mode == DImode || op1 != const0_rtx)
10607 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10608 code = (code == LT ? GEU : LTU);
10612 if (mode == DImode || op1 != constm1_rtx)
10614 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10615 code = (code == LE ? GEU : LTU);
10621 /* Swapping operands may cause constant to appear as first operand. */
10622 if (!nonimmediate_operand (op0, VOIDmode))
10624 if (no_new_pseudos)
10626 op0 = force_reg (mode, op0);
10628 ix86_compare_op0 = op0;
10629 ix86_compare_op1 = op1;
10630 *pop = ix86_expand_compare (code, NULL, NULL);
10631 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
10636 ix86_expand_int_movcc (rtx operands[])
10638 enum rtx_code code = GET_CODE (operands[1]), compare_code;
10639 rtx compare_seq, compare_op;
10640 rtx second_test, bypass_test;
10641 enum machine_mode mode = GET_MODE (operands[0]);
10642 bool sign_bit_compare_p = false;;
10645 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10646 compare_seq = get_insns ();
10649 compare_code = GET_CODE (compare_op);
10651 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
10652 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
10653 sign_bit_compare_p = true;
10655 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
10656 HImode insns, we'd be swallowed in word prefix ops. */
10658 if ((mode != HImode || TARGET_FAST_PREFIX)
10659 && (mode != (TARGET_64BIT ? TImode : DImode))
10660 && GET_CODE (operands[2]) == CONST_INT
10661 && GET_CODE (operands[3]) == CONST_INT)
10663 rtx out = operands[0];
10664 HOST_WIDE_INT ct = INTVAL (operands[2]);
10665 HOST_WIDE_INT cf = INTVAL (operands[3]);
10666 HOST_WIDE_INT diff;
10669 /* Sign bit compares are better done using shifts than we do by using
10671 if (sign_bit_compare_p
10672 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10673 ix86_compare_op1, &compare_op))
10675 /* Detect overlap between destination and compare sources. */
10678 if (!sign_bit_compare_p)
10680 bool fpcmp = false;
10682 compare_code = GET_CODE (compare_op);
10684 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10685 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10688 compare_code = ix86_fp_compare_code_to_integer (compare_code);
10691 /* To simplify rest of code, restrict to the GEU case. */
10692 if (compare_code == LTU)
10694 HOST_WIDE_INT tmp = ct;
10697 compare_code = reverse_condition (compare_code);
10698 code = reverse_condition (code);
10703 PUT_CODE (compare_op,
10704 reverse_condition_maybe_unordered
10705 (GET_CODE (compare_op)));
10707 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10711 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
10712 || reg_overlap_mentioned_p (out, ix86_compare_op1))
10713 tmp = gen_reg_rtx (mode);
10715 if (mode == DImode)
10716 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
10718 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
10722 if (code == GT || code == GE)
10723 code = reverse_condition (code);
10726 HOST_WIDE_INT tmp = ct;
10731 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
10732 ix86_compare_op1, VOIDmode, 0, -1);
10745 tmp = expand_simple_binop (mode, PLUS,
10747 copy_rtx (tmp), 1, OPTAB_DIRECT);
10758 tmp = expand_simple_binop (mode, IOR,
10760 copy_rtx (tmp), 1, OPTAB_DIRECT);
10762 else if (diff == -1 && ct)
10772 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10774 tmp = expand_simple_binop (mode, PLUS,
10775 copy_rtx (tmp), GEN_INT (cf),
10776 copy_rtx (tmp), 1, OPTAB_DIRECT);
10784 * andl cf - ct, dest
10794 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10797 tmp = expand_simple_binop (mode, AND,
10799 gen_int_mode (cf - ct, mode),
10800 copy_rtx (tmp), 1, OPTAB_DIRECT);
10802 tmp = expand_simple_binop (mode, PLUS,
10803 copy_rtx (tmp), GEN_INT (ct),
10804 copy_rtx (tmp), 1, OPTAB_DIRECT);
10807 if (!rtx_equal_p (tmp, out))
10808 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
10810 return 1; /* DONE */
10816 tmp = ct, ct = cf, cf = tmp;
10818 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10820 /* We may be reversing unordered compare to normal compare, that
10821 is not valid in general (we may convert non-trapping condition
10822 to trapping one), however on i386 we currently emit all
10823 comparisons unordered. */
10824 compare_code = reverse_condition_maybe_unordered (compare_code);
10825 code = reverse_condition_maybe_unordered (code);
10829 compare_code = reverse_condition (compare_code);
10830 code = reverse_condition (code);
10834 compare_code = UNKNOWN;
10835 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
10836 && GET_CODE (ix86_compare_op1) == CONST_INT)
10838 if (ix86_compare_op1 == const0_rtx
10839 && (code == LT || code == GE))
10840 compare_code = code;
10841 else if (ix86_compare_op1 == constm1_rtx)
10845 else if (code == GT)
10850 /* Optimize dest = (op0 < 0) ? -1 : cf. */
10851 if (compare_code != UNKNOWN
10852 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
10853 && (cf == -1 || ct == -1))
10855 /* If lea code below could be used, only optimize
10856 if it results in a 2 insn sequence. */
10858 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
10859 || diff == 3 || diff == 5 || diff == 9)
10860 || (compare_code == LT && ct == -1)
10861 || (compare_code == GE && cf == -1))
10864 * notl op1 (if necessary)
10872 code = reverse_condition (code);
10875 out = emit_store_flag (out, code, ix86_compare_op0,
10876 ix86_compare_op1, VOIDmode, 0, -1);
10878 out = expand_simple_binop (mode, IOR,
10880 out, 1, OPTAB_DIRECT);
10881 if (out != operands[0])
10882 emit_move_insn (operands[0], out);
10884 return 1; /* DONE */
10889 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
10890 || diff == 3 || diff == 5 || diff == 9)
10891 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
10893 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
10899 * lea cf(dest*(ct-cf)),dest
10903 * This also catches the degenerate setcc-only case.
10909 out = emit_store_flag (out, code, ix86_compare_op0,
10910 ix86_compare_op1, VOIDmode, 0, 1);
10913 /* On x86_64 the lea instruction operates on Pmode, so we need
10914 to get arithmetics done in proper mode to match. */
10916 tmp = copy_rtx (out);
10920 out1 = copy_rtx (out);
10921 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
10925 tmp = gen_rtx_PLUS (mode, tmp, out1);
10931 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
10934 if (!rtx_equal_p (tmp, out))
10937 out = force_operand (tmp, copy_rtx (out));
10939 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
10941 if (!rtx_equal_p (out, operands[0]))
10942 emit_move_insn (operands[0], copy_rtx (out));
10944 return 1; /* DONE */
10948 * General case: Jumpful:
10949 * xorl dest,dest cmpl op1, op2
10950 * cmpl op1, op2 movl ct, dest
10951 * setcc dest jcc 1f
10952 * decl dest movl cf, dest
10953 * andl (cf-ct),dest 1:
10956 * Size 20. Size 14.
10958 * This is reasonably steep, but branch mispredict costs are
10959 * high on modern cpus, so consider failing only if optimizing
10963 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10964 && BRANCH_COST >= 2)
10970 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10971 /* We may be reversing unordered compare to normal compare,
10972 that is not valid in general (we may convert non-trapping
10973 condition to trapping one), however on i386 we currently
10974 emit all comparisons unordered. */
10975 code = reverse_condition_maybe_unordered (code);
10978 code = reverse_condition (code);
10979 if (compare_code != UNKNOWN)
10980 compare_code = reverse_condition (compare_code);
10984 if (compare_code != UNKNOWN)
10986 /* notl op1 (if needed)
10991 For x < 0 (resp. x <= -1) there will be no notl,
10992 so if possible swap the constants to get rid of the
10994 True/false will be -1/0 while code below (store flag
10995 followed by decrement) is 0/-1, so the constants need
10996 to be exchanged once more. */
10998 if (compare_code == GE || !cf)
11000 code = reverse_condition (code);
11005 HOST_WIDE_INT tmp = cf;
11010 out = emit_store_flag (out, code, ix86_compare_op0,
11011 ix86_compare_op1, VOIDmode, 0, -1);
11015 out = emit_store_flag (out, code, ix86_compare_op0,
11016 ix86_compare_op1, VOIDmode, 0, 1);
11018 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
11019 copy_rtx (out), 1, OPTAB_DIRECT);
11022 out = expand_simple_binop (mode, AND, copy_rtx (out),
11023 gen_int_mode (cf - ct, mode),
11024 copy_rtx (out), 1, OPTAB_DIRECT);
11026 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
11027 copy_rtx (out), 1, OPTAB_DIRECT);
11028 if (!rtx_equal_p (out, operands[0]))
11029 emit_move_insn (operands[0], copy_rtx (out));
11031 return 1; /* DONE */
11035 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
11037 /* Try a few things more with specific constants and a variable. */
11040 rtx var, orig_out, out, tmp;
11042 if (BRANCH_COST <= 2)
11043 return 0; /* FAIL */
11045 /* If one of the two operands is an interesting constant, load a
11046 constant with the above and mask it in with a logical operation. */
11048 if (GET_CODE (operands[2]) == CONST_INT)
11051 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
11052 operands[3] = constm1_rtx, op = and_optab;
11053 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
11054 operands[3] = const0_rtx, op = ior_optab;
11056 return 0; /* FAIL */
11058 else if (GET_CODE (operands[3]) == CONST_INT)
11061 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
11062 operands[2] = constm1_rtx, op = and_optab;
11063 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
11064 operands[2] = const0_rtx, op = ior_optab;
11066 return 0; /* FAIL */
11069 return 0; /* FAIL */
11071 orig_out = operands[0];
11072 tmp = gen_reg_rtx (mode);
11075 /* Recurse to get the constant loaded. */
11076 if (ix86_expand_int_movcc (operands) == 0)
11077 return 0; /* FAIL */
11079 /* Mask in the interesting variable. */
11080 out = expand_binop (mode, op, var, tmp, orig_out, 0,
11082 if (!rtx_equal_p (out, orig_out))
11083 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
11085 return 1; /* DONE */
11089 * For comparison with above,
11099 if (! nonimmediate_operand (operands[2], mode))
11100 operands[2] = force_reg (mode, operands[2]);
11101 if (! nonimmediate_operand (operands[3], mode))
11102 operands[3] = force_reg (mode, operands[3]);
11104 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11106 rtx tmp = gen_reg_rtx (mode);
11107 emit_move_insn (tmp, operands[3]);
11110 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11112 rtx tmp = gen_reg_rtx (mode);
11113 emit_move_insn (tmp, operands[2]);
11117 if (! register_operand (operands[2], VOIDmode)
11119 || ! register_operand (operands[3], VOIDmode)))
11120 operands[2] = force_reg (mode, operands[2]);
11123 && ! register_operand (operands[3], VOIDmode))
11124 operands[3] = force_reg (mode, operands[3]);
11126 emit_insn (compare_seq);
11127 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11128 gen_rtx_IF_THEN_ELSE (mode,
11129 compare_op, operands[2],
11132 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11133 gen_rtx_IF_THEN_ELSE (mode,
11135 copy_rtx (operands[3]),
11136 copy_rtx (operands[0]))));
11138 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11139 gen_rtx_IF_THEN_ELSE (mode,
11141 copy_rtx (operands[2]),
11142 copy_rtx (operands[0]))));
11144 return 1; /* DONE */
11147 /* Swap, force into registers, or otherwise massage the two operands
11148 to an sse comparison with a mask result. Thus we differ a bit from
11149 ix86_prepare_fp_compare_args which expects to produce a flags result.
11151 The DEST operand exists to help determine whether to commute commutative
11152 operators. The POP0/POP1 operands are updated in place. The new
11153 comparison code is returned, or UNKNOWN if not implementable. */
11155 static enum rtx_code
11156 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
11157 rtx *pop0, rtx *pop1)
11165 /* We have no LTGT as an operator. We could implement it with
11166 NE & ORDERED, but this requires an extra temporary. It's
11167 not clear that it's worth it. */
11174 /* These are supported directly. */
11181 /* For commutative operators, try to canonicalize the destination
11182 operand to be first in the comparison - this helps reload to
11183 avoid extra moves. */
11184 if (!dest || !rtx_equal_p (dest, *pop1))
11192 /* These are not supported directly. Swap the comparison operands
11193 to transform into something that is supported. */
11197 code = swap_condition (code);
11201 gcc_unreachable ();
11207 /* Detect conditional moves that exactly match min/max operational
11208 semantics. Note that this is IEEE safe, as long as we don't
11209 interchange the operands.
11211 Returns FALSE if this conditional move doesn't match a MIN/MAX,
11212 and TRUE if the operation is successful and instructions are emitted. */
11215 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
11216 rtx cmp_op1, rtx if_true, rtx if_false)
11218 enum machine_mode mode;
11224 else if (code == UNGE)
11227 if_true = if_false;
11233 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
11235 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
11240 mode = GET_MODE (dest);
11242 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
11243 but MODE may be a vector mode and thus not appropriate. */
11244 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
11246 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
11249 if_true = force_reg (mode, if_true);
11250 v = gen_rtvec (2, if_true, if_false);
11251 tmp = gen_rtx_UNSPEC (mode, v, u);
11255 code = is_min ? SMIN : SMAX;
11256 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
11259 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
11263 /* Expand an sse vector comparison. Return the register with the result. */
11266 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
11267 rtx op_true, rtx op_false)
11269 enum machine_mode mode = GET_MODE (dest);
11272 cmp_op0 = force_reg (mode, cmp_op0);
11273 if (!nonimmediate_operand (cmp_op1, mode))
11274 cmp_op1 = force_reg (mode, cmp_op1);
11277 || reg_overlap_mentioned_p (dest, op_true)
11278 || reg_overlap_mentioned_p (dest, op_false))
11279 dest = gen_reg_rtx (mode);
11281 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
11282 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11287 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
11288 operations. This is used for both scalar and vector conditional moves. */
11291 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
11293 enum machine_mode mode = GET_MODE (dest);
11296 if (op_false == CONST0_RTX (mode))
11298 op_true = force_reg (mode, op_true);
11299 x = gen_rtx_AND (mode, cmp, op_true);
11300 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11302 else if (op_true == CONST0_RTX (mode))
11304 op_false = force_reg (mode, op_false);
11305 x = gen_rtx_NOT (mode, cmp);
11306 x = gen_rtx_AND (mode, x, op_false);
11307 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11311 op_true = force_reg (mode, op_true);
11312 op_false = force_reg (mode, op_false);
11314 t2 = gen_reg_rtx (mode);
11316 t3 = gen_reg_rtx (mode);
11320 x = gen_rtx_AND (mode, op_true, cmp);
11321 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
11323 x = gen_rtx_NOT (mode, cmp);
11324 x = gen_rtx_AND (mode, x, op_false);
11325 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
11327 x = gen_rtx_IOR (mode, t3, t2);
11328 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11332 /* Expand a floating-point conditional move. Return true if successful. */
11335 ix86_expand_fp_movcc (rtx operands[])
11337 enum machine_mode mode = GET_MODE (operands[0]);
11338 enum rtx_code code = GET_CODE (operands[1]);
11339 rtx tmp, compare_op, second_test, bypass_test;
11341 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
11343 enum machine_mode cmode;
11345 /* Since we've no cmove for sse registers, don't force bad register
11346 allocation just to gain access to it. Deny movcc when the
11347 comparison mode doesn't match the move mode. */
11348 cmode = GET_MODE (ix86_compare_op0);
11349 if (cmode == VOIDmode)
11350 cmode = GET_MODE (ix86_compare_op1);
11354 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11356 &ix86_compare_op1);
11357 if (code == UNKNOWN)
11360 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
11361 ix86_compare_op1, operands[2],
11365 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
11366 ix86_compare_op1, operands[2], operands[3]);
11367 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
11371 /* The floating point conditional move instructions don't directly
11372 support conditions resulting from a signed integer comparison. */
11374 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11376 /* The floating point conditional move instructions don't directly
11377 support signed integer comparisons. */
11379 if (!fcmov_comparison_operator (compare_op, VOIDmode))
11381 gcc_assert (!second_test && !bypass_test);
11382 tmp = gen_reg_rtx (QImode);
11383 ix86_expand_setcc (code, tmp);
11385 ix86_compare_op0 = tmp;
11386 ix86_compare_op1 = const0_rtx;
11387 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11389 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11391 tmp = gen_reg_rtx (mode);
11392 emit_move_insn (tmp, operands[3]);
11395 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11397 tmp = gen_reg_rtx (mode);
11398 emit_move_insn (tmp, operands[2]);
11402 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11403 gen_rtx_IF_THEN_ELSE (mode, compare_op,
11404 operands[2], operands[3])));
11406 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11407 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
11408 operands[3], operands[0])));
11410 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11411 gen_rtx_IF_THEN_ELSE (mode, second_test,
11412 operands[2], operands[0])));
11417 /* Expand a floating-point vector conditional move; a vcond operation
11418 rather than a movcc operation. */
11421 ix86_expand_fp_vcond (rtx operands[])
11423 enum rtx_code code = GET_CODE (operands[3]);
11426 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11427 &operands[4], &operands[5]);
11428 if (code == UNKNOWN)
11431 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
11432 operands[5], operands[1], operands[2]))
11435 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
11436 operands[1], operands[2]);
11437 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
11441 /* Expand a signed integral vector conditional move. */
11444 ix86_expand_int_vcond (rtx operands[])
11446 enum machine_mode mode = GET_MODE (operands[0]);
11447 enum rtx_code code = GET_CODE (operands[3]);
11448 bool negate = false;
11451 cop0 = operands[4];
11452 cop1 = operands[5];
11454 /* Canonicalize the comparison to EQ, GT, GTU. */
11465 code = reverse_condition (code);
11471 code = reverse_condition (code);
11477 code = swap_condition (code);
11478 x = cop0, cop0 = cop1, cop1 = x;
11482 gcc_unreachable ();
11485 /* Unsigned parallel compare is not supported by the hardware. Play some
11486 tricks to turn this into a signed comparison against 0. */
11489 cop0 = force_reg (mode, cop0);
11497 /* Perform a parallel modulo subtraction. */
11498 t1 = gen_reg_rtx (mode);
11499 emit_insn (gen_subv4si3 (t1, cop0, cop1));
11501 /* Extract the original sign bit of op0. */
11502 mask = GEN_INT (-0x80000000);
11503 mask = gen_rtx_CONST_VECTOR (mode,
11504 gen_rtvec (4, mask, mask, mask, mask));
11505 mask = force_reg (mode, mask);
11506 t2 = gen_reg_rtx (mode);
11507 emit_insn (gen_andv4si3 (t2, cop0, mask));
11509 /* XOR it back into the result of the subtraction. This results
11510 in the sign bit set iff we saw unsigned underflow. */
11511 x = gen_reg_rtx (mode);
11512 emit_insn (gen_xorv4si3 (x, t1, t2));
11520 /* Perform a parallel unsigned saturating subtraction. */
11521 x = gen_reg_rtx (mode);
11522 emit_insn (gen_rtx_SET (VOIDmode, x,
11523 gen_rtx_US_MINUS (mode, cop0, cop1)));
11530 gcc_unreachable ();
11534 cop1 = CONST0_RTX (mode);
11537 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
11538 operands[1+negate], operands[2-negate]);
11540 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
11541 operands[2-negate]);
11545 /* Expand conditional increment or decrement using adb/sbb instructions.
11546 The default case using setcc followed by the conditional move can be
11547 done by generic code. */
11549 ix86_expand_int_addcc (rtx operands[])
11551 enum rtx_code code = GET_CODE (operands[1]);
11553 rtx val = const0_rtx;
11554 bool fpcmp = false;
11555 enum machine_mode mode = GET_MODE (operands[0]);
11557 if (operands[3] != const1_rtx
11558 && operands[3] != constm1_rtx)
11560 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
11561 ix86_compare_op1, &compare_op))
11563 code = GET_CODE (compare_op);
11565 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11566 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11569 code = ix86_fp_compare_code_to_integer (code);
11576 PUT_CODE (compare_op,
11577 reverse_condition_maybe_unordered
11578 (GET_CODE (compare_op)));
11580 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
11582 PUT_MODE (compare_op, mode);
11584 /* Construct either adc or sbb insn. */
11585 if ((code == LTU) == (operands[3] == constm1_rtx))
11587 switch (GET_MODE (operands[0]))
11590 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
11593 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
11596 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
11599 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11602 gcc_unreachable ();
11607 switch (GET_MODE (operands[0]))
11610 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
11613 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
11616 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
11619 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11622 gcc_unreachable ();
11625 return 1; /* DONE */
11629 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
11630 works for floating pointer parameters and nonoffsetable memories.
11631 For pushes, it returns just stack offsets; the values will be saved
11632 in the right order. Maximally three parts are generated. */
11635 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
11640 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
11642 size = (GET_MODE_SIZE (mode) + 4) / 8;
11644 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
11645 gcc_assert (size >= 2 && size <= 3);
11647 /* Optimize constant pool reference to immediates. This is used by fp
11648 moves, that force all constants to memory to allow combining. */
11649 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
11651 rtx tmp = maybe_get_pool_constant (operand);
11656 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
11658 /* The only non-offsetable memories we handle are pushes. */
11659 int ok = push_operand (operand, VOIDmode);
11663 operand = copy_rtx (operand);
11664 PUT_MODE (operand, Pmode);
11665 parts[0] = parts[1] = parts[2] = operand;
11669 if (GET_CODE (operand) == CONST_VECTOR)
11671 enum machine_mode imode = int_mode_for_mode (mode);
11672 /* Caution: if we looked through a constant pool memory above,
11673 the operand may actually have a different mode now. That's
11674 ok, since we want to pun this all the way back to an integer. */
11675 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
11676 gcc_assert (operand != NULL);
11682 if (mode == DImode)
11683 split_di (&operand, 1, &parts[0], &parts[1]);
11686 if (REG_P (operand))
11688 gcc_assert (reload_completed);
11689 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
11690 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
11692 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
11694 else if (offsettable_memref_p (operand))
11696 operand = adjust_address (operand, SImode, 0);
11697 parts[0] = operand;
11698 parts[1] = adjust_address (operand, SImode, 4);
11700 parts[2] = adjust_address (operand, SImode, 8);
11702 else if (GET_CODE (operand) == CONST_DOUBLE)
11707 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11711 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
11712 parts[2] = gen_int_mode (l[2], SImode);
11715 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
11718 gcc_unreachable ();
11720 parts[1] = gen_int_mode (l[1], SImode);
11721 parts[0] = gen_int_mode (l[0], SImode);
11724 gcc_unreachable ();
11729 if (mode == TImode)
11730 split_ti (&operand, 1, &parts[0], &parts[1]);
11731 if (mode == XFmode || mode == TFmode)
11733 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
11734 if (REG_P (operand))
11736 gcc_assert (reload_completed);
11737 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
11738 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
11740 else if (offsettable_memref_p (operand))
11742 operand = adjust_address (operand, DImode, 0);
11743 parts[0] = operand;
11744 parts[1] = adjust_address (operand, upper_mode, 8);
11746 else if (GET_CODE (operand) == CONST_DOUBLE)
11751 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11752 real_to_target (l, &r, mode);
11754 /* Do not use shift by 32 to avoid warning on 32bit systems. */
11755 if (HOST_BITS_PER_WIDE_INT >= 64)
11758 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
11759 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
11762 parts[0] = immed_double_const (l[0], l[1], DImode);
11764 if (upper_mode == SImode)
11765 parts[1] = gen_int_mode (l[2], SImode);
11766 else if (HOST_BITS_PER_WIDE_INT >= 64)
11769 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
11770 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
11773 parts[1] = immed_double_const (l[2], l[3], DImode);
11776 gcc_unreachable ();
11783 /* Emit insns to perform a move or push of DI, DF, and XF values.
11784 Return false when normal moves are needed; true when all required
11785 insns have been emitted. Operands 2-4 contain the input values
11786 int the correct order; operands 5-7 contain the output values. */
11789 ix86_split_long_move (rtx operands[])
11794 int collisions = 0;
11795 enum machine_mode mode = GET_MODE (operands[0]);
11797 /* The DFmode expanders may ask us to move double.
11798 For 64bit target this is single move. By hiding the fact
11799 here we simplify i386.md splitters. */
11800 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
11802 /* Optimize constant pool reference to immediates. This is used by
11803 fp moves, that force all constants to memory to allow combining. */
11805 if (GET_CODE (operands[1]) == MEM
11806 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
11807 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
11808 operands[1] = get_pool_constant (XEXP (operands[1], 0));
11809 if (push_operand (operands[0], VOIDmode))
11811 operands[0] = copy_rtx (operands[0]);
11812 PUT_MODE (operands[0], Pmode);
11815 operands[0] = gen_lowpart (DImode, operands[0]);
11816 operands[1] = gen_lowpart (DImode, operands[1]);
11817 emit_move_insn (operands[0], operands[1]);
11821 /* The only non-offsettable memory we handle is push. */
11822 if (push_operand (operands[0], VOIDmode))
11825 gcc_assert (GET_CODE (operands[0]) != MEM
11826 || offsettable_memref_p (operands[0]));
11828 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
11829 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
11831 /* When emitting push, take care for source operands on the stack. */
11832 if (push && GET_CODE (operands[1]) == MEM
11833 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
11836 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
11837 XEXP (part[1][2], 0));
11838 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
11839 XEXP (part[1][1], 0));
11842 /* We need to do copy in the right order in case an address register
11843 of the source overlaps the destination. */
11844 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
11846 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
11848 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11851 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
11854 /* Collision in the middle part can be handled by reordering. */
11855 if (collisions == 1 && nparts == 3
11856 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11859 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
11860 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
11863 /* If there are more collisions, we can't handle it by reordering.
11864 Do an lea to the last part and use only one colliding move. */
11865 else if (collisions > 1)
11871 base = part[0][nparts - 1];
11873 /* Handle the case when the last part isn't valid for lea.
11874 Happens in 64-bit mode storing the 12-byte XFmode. */
11875 if (GET_MODE (base) != Pmode)
11876 base = gen_rtx_REG (Pmode, REGNO (base));
11878 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
11879 part[1][0] = replace_equiv_address (part[1][0], base);
11880 part[1][1] = replace_equiv_address (part[1][1],
11881 plus_constant (base, UNITS_PER_WORD));
11883 part[1][2] = replace_equiv_address (part[1][2],
11884 plus_constant (base, 8));
11894 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
11895 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
11896 emit_move_insn (part[0][2], part[1][2]);
11901 /* In 64bit mode we don't have 32bit push available. In case this is
11902 register, it is OK - we will just use larger counterpart. We also
11903 retype memory - these comes from attempt to avoid REX prefix on
11904 moving of second half of TFmode value. */
11905 if (GET_MODE (part[1][1]) == SImode)
11907 switch (GET_CODE (part[1][1]))
11910 part[1][1] = adjust_address (part[1][1], DImode, 0);
11914 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
11918 gcc_unreachable ();
11921 if (GET_MODE (part[1][0]) == SImode)
11922 part[1][0] = part[1][1];
11925 emit_move_insn (part[0][1], part[1][1]);
11926 emit_move_insn (part[0][0], part[1][0]);
11930 /* Choose correct order to not overwrite the source before it is copied. */
11931 if ((REG_P (part[0][0])
11932 && REG_P (part[1][1])
11933 && (REGNO (part[0][0]) == REGNO (part[1][1])
11935 && REGNO (part[0][0]) == REGNO (part[1][2]))))
11937 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
11941 operands[2] = part[0][2];
11942 operands[3] = part[0][1];
11943 operands[4] = part[0][0];
11944 operands[5] = part[1][2];
11945 operands[6] = part[1][1];
11946 operands[7] = part[1][0];
11950 operands[2] = part[0][1];
11951 operands[3] = part[0][0];
11952 operands[5] = part[1][1];
11953 operands[6] = part[1][0];
11960 operands[2] = part[0][0];
11961 operands[3] = part[0][1];
11962 operands[4] = part[0][2];
11963 operands[5] = part[1][0];
11964 operands[6] = part[1][1];
11965 operands[7] = part[1][2];
11969 operands[2] = part[0][0];
11970 operands[3] = part[0][1];
11971 operands[5] = part[1][0];
11972 operands[6] = part[1][1];
11976 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
11979 if (GET_CODE (operands[5]) == CONST_INT
11980 && operands[5] != const0_rtx
11981 && REG_P (operands[2]))
11983 if (GET_CODE (operands[6]) == CONST_INT
11984 && INTVAL (operands[6]) == INTVAL (operands[5]))
11985 operands[6] = operands[2];
11988 && GET_CODE (operands[7]) == CONST_INT
11989 && INTVAL (operands[7]) == INTVAL (operands[5]))
11990 operands[7] = operands[2];
11994 && GET_CODE (operands[6]) == CONST_INT
11995 && operands[6] != const0_rtx
11996 && REG_P (operands[3])
11997 && GET_CODE (operands[7]) == CONST_INT
11998 && INTVAL (operands[7]) == INTVAL (operands[6]))
11999 operands[7] = operands[3];
12002 emit_move_insn (operands[2], operands[5]);
12003 emit_move_insn (operands[3], operands[6]);
12005 emit_move_insn (operands[4], operands[7]);
12010 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
12011 left shift by a constant, either using a single shift or
12012 a sequence of add instructions. */
12015 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
12019 emit_insn ((mode == DImode
12021 : gen_adddi3) (operand, operand, operand));
12023 else if (!optimize_size
12024 && count * ix86_cost->add <= ix86_cost->shift_const)
12027 for (i=0; i<count; i++)
12029 emit_insn ((mode == DImode
12031 : gen_adddi3) (operand, operand, operand));
12035 emit_insn ((mode == DImode
12037 : gen_ashldi3) (operand, operand, GEN_INT (count)));
12041 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
12043 rtx low[2], high[2];
12045 const int single_width = mode == DImode ? 32 : 64;
12047 if (GET_CODE (operands[2]) == CONST_INT)
12049 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12050 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12052 if (count >= single_width)
12054 emit_move_insn (high[0], low[1]);
12055 emit_move_insn (low[0], const0_rtx);
12057 if (count > single_width)
12058 ix86_expand_ashl_const (high[0], count - single_width, mode);
12062 if (!rtx_equal_p (operands[0], operands[1]))
12063 emit_move_insn (operands[0], operands[1]);
12064 emit_insn ((mode == DImode
12066 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
12067 ix86_expand_ashl_const (low[0], count, mode);
12072 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12074 if (operands[1] == const1_rtx)
12076 /* Assuming we've chosen a QImode capable registers, then 1 << N
12077 can be done with two 32/64-bit shifts, no branches, no cmoves. */
12078 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
12080 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
12082 ix86_expand_clear (low[0]);
12083 ix86_expand_clear (high[0]);
12084 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
12086 d = gen_lowpart (QImode, low[0]);
12087 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
12088 s = gen_rtx_EQ (QImode, flags, const0_rtx);
12089 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12091 d = gen_lowpart (QImode, high[0]);
12092 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
12093 s = gen_rtx_NE (QImode, flags, const0_rtx);
12094 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12097 /* Otherwise, we can get the same results by manually performing
12098 a bit extract operation on bit 5/6, and then performing the two
12099 shifts. The two methods of getting 0/1 into low/high are exactly
12100 the same size. Avoiding the shift in the bit extract case helps
12101 pentium4 a bit; no one else seems to care much either way. */
12106 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
12107 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
12109 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
12110 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
12112 emit_insn ((mode == DImode
12114 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
12115 emit_insn ((mode == DImode
12117 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
12118 emit_move_insn (low[0], high[0]);
12119 emit_insn ((mode == DImode
12121 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
12124 emit_insn ((mode == DImode
12126 : gen_ashldi3) (low[0], low[0], operands[2]));
12127 emit_insn ((mode == DImode
12129 : gen_ashldi3) (high[0], high[0], operands[2]));
12133 if (operands[1] == constm1_rtx)
12135 /* For -1 << N, we can avoid the shld instruction, because we
12136 know that we're shifting 0...31/63 ones into a -1. */
12137 emit_move_insn (low[0], constm1_rtx);
12139 emit_move_insn (high[0], low[0]);
12141 emit_move_insn (high[0], constm1_rtx);
12145 if (!rtx_equal_p (operands[0], operands[1]))
12146 emit_move_insn (operands[0], operands[1]);
12148 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12149 emit_insn ((mode == DImode
12151 : gen_x86_64_shld) (high[0], low[0], operands[2]));
12154 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
12156 if (TARGET_CMOVE && scratch)
12158 ix86_expand_clear (scratch);
12159 emit_insn ((mode == DImode
12160 ? gen_x86_shift_adj_1
12161 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
12164 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
12168 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
12170 rtx low[2], high[2];
12172 const int single_width = mode == DImode ? 32 : 64;
12174 if (GET_CODE (operands[2]) == CONST_INT)
12176 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12177 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12179 if (count == single_width * 2 - 1)
12181 emit_move_insn (high[0], high[1]);
12182 emit_insn ((mode == DImode
12184 : gen_ashrdi3) (high[0], high[0],
12185 GEN_INT (single_width - 1)));
12186 emit_move_insn (low[0], high[0]);
12189 else if (count >= single_width)
12191 emit_move_insn (low[0], high[1]);
12192 emit_move_insn (high[0], low[0]);
12193 emit_insn ((mode == DImode
12195 : gen_ashrdi3) (high[0], high[0],
12196 GEN_INT (single_width - 1)));
12197 if (count > single_width)
12198 emit_insn ((mode == DImode
12200 : gen_ashrdi3) (low[0], low[0],
12201 GEN_INT (count - single_width)));
12205 if (!rtx_equal_p (operands[0], operands[1]))
12206 emit_move_insn (operands[0], operands[1]);
12207 emit_insn ((mode == DImode
12209 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12210 emit_insn ((mode == DImode
12212 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
12217 if (!rtx_equal_p (operands[0], operands[1]))
12218 emit_move_insn (operands[0], operands[1]);
12220 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12222 emit_insn ((mode == DImode
12224 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12225 emit_insn ((mode == DImode
12227 : gen_ashrdi3) (high[0], high[0], operands[2]));
12229 if (TARGET_CMOVE && scratch)
12231 emit_move_insn (scratch, high[0]);
12232 emit_insn ((mode == DImode
12234 : gen_ashrdi3) (scratch, scratch,
12235 GEN_INT (single_width - 1)));
12236 emit_insn ((mode == DImode
12237 ? gen_x86_shift_adj_1
12238 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12242 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
12247 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
12249 rtx low[2], high[2];
12251 const int single_width = mode == DImode ? 32 : 64;
12253 if (GET_CODE (operands[2]) == CONST_INT)
12255 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12256 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12258 if (count >= single_width)
12260 emit_move_insn (low[0], high[1]);
12261 ix86_expand_clear (high[0]);
12263 if (count > single_width)
12264 emit_insn ((mode == DImode
12266 : gen_lshrdi3) (low[0], low[0],
12267 GEN_INT (count - single_width)));
12271 if (!rtx_equal_p (operands[0], operands[1]))
12272 emit_move_insn (operands[0], operands[1]);
12273 emit_insn ((mode == DImode
12275 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12276 emit_insn ((mode == DImode
12278 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
12283 if (!rtx_equal_p (operands[0], operands[1]))
12284 emit_move_insn (operands[0], operands[1]);
12286 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12288 emit_insn ((mode == DImode
12290 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12291 emit_insn ((mode == DImode
12293 : gen_lshrdi3) (high[0], high[0], operands[2]));
12295 /* Heh. By reversing the arguments, we can reuse this pattern. */
12296 if (TARGET_CMOVE && scratch)
12298 ix86_expand_clear (scratch);
12299 emit_insn ((mode == DImode
12300 ? gen_x86_shift_adj_1
12301 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12305 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
12309 /* Helper function for the string operations below. Dest VARIABLE whether
12310 it is aligned to VALUE bytes. If true, jump to the label. */
12312 ix86_expand_aligntest (rtx variable, int value)
12314 rtx label = gen_label_rtx ();
12315 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
12316 if (GET_MODE (variable) == DImode)
12317 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
12319 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
12320 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
12325 /* Adjust COUNTER by the VALUE. */
12327 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
12329 if (GET_MODE (countreg) == DImode)
12330 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
12332 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
12335 /* Zero extend possibly SImode EXP to Pmode register. */
12337 ix86_zero_extend_to_Pmode (rtx exp)
12340 if (GET_MODE (exp) == VOIDmode)
12341 return force_reg (Pmode, exp);
12342 if (GET_MODE (exp) == Pmode)
12343 return copy_to_mode_reg (Pmode, exp);
12344 r = gen_reg_rtx (Pmode);
12345 emit_insn (gen_zero_extendsidi2 (r, exp));
12349 /* Expand string move (memcpy) operation. Use i386 string operations when
12350 profitable. expand_clrmem contains similar code. */
12352 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
12354 rtx srcreg, destreg, countreg, srcexp, destexp;
12355 enum machine_mode counter_mode;
12356 HOST_WIDE_INT align = 0;
12357 unsigned HOST_WIDE_INT count = 0;
12359 if (GET_CODE (align_exp) == CONST_INT)
12360 align = INTVAL (align_exp);
12362 /* Can't use any of this if the user has appropriated esi or edi. */
12363 if (global_regs[4] || global_regs[5])
12366 /* This simple hack avoids all inlining code and simplifies code below. */
12367 if (!TARGET_ALIGN_STRINGOPS)
12370 if (GET_CODE (count_exp) == CONST_INT)
12372 count = INTVAL (count_exp);
12373 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12377 /* Figure out proper mode for counter. For 32bits it is always SImode,
12378 for 64bits use SImode when possible, otherwise DImode.
12379 Set count to number of bytes copied when known at compile time. */
12381 || GET_MODE (count_exp) == SImode
12382 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12383 counter_mode = SImode;
12385 counter_mode = DImode;
12387 gcc_assert (counter_mode == SImode || counter_mode == DImode);
12389 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12390 if (destreg != XEXP (dst, 0))
12391 dst = replace_equiv_address_nv (dst, destreg);
12392 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
12393 if (srcreg != XEXP (src, 0))
12394 src = replace_equiv_address_nv (src, srcreg);
12396 /* When optimizing for size emit simple rep ; movsb instruction for
12397 counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)?
12398 sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb.
12399 Sice of (movsl;)*(movsw;)?(movsb;)? sequence is
12400 count / 4 + (count & 3), the other sequence is either 4 or 7 bytes,
12401 but we don't know whether upper 24 (resp. 56) bits of %ecx will be
12402 known to be zero or not. The rep; movsb sequence causes higher
12403 register pressure though, so take that into account. */
12405 if ((!optimize || optimize_size)
12410 || (count & 3) + count / 4 > 6))))
12412 emit_insn (gen_cld ());
12413 countreg = ix86_zero_extend_to_Pmode (count_exp);
12414 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12415 srcexp = gen_rtx_PLUS (Pmode, srcreg, countreg);
12416 emit_insn (gen_rep_mov (destreg, dst, srcreg, src, countreg,
12420 /* For constant aligned (or small unaligned) copies use rep movsl
12421 followed by code copying the rest. For PentiumPro ensure 8 byte
12422 alignment to allow rep movsl acceleration. */
12424 else if (count != 0
12426 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12427 || optimize_size || count < (unsigned int) 64))
12429 unsigned HOST_WIDE_INT offset = 0;
12430 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12431 rtx srcmem, dstmem;
12433 emit_insn (gen_cld ());
12434 if (count & ~(size - 1))
12436 if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4)
12438 enum machine_mode movs_mode = size == 4 ? SImode : DImode;
12440 while (offset < (count & ~(size - 1)))
12442 srcmem = adjust_automodify_address_nv (src, movs_mode,
12444 dstmem = adjust_automodify_address_nv (dst, movs_mode,
12446 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12452 countreg = GEN_INT ((count >> (size == 4 ? 2 : 3))
12453 & (TARGET_64BIT ? -1 : 0x3fffffff));
12454 countreg = copy_to_mode_reg (counter_mode, countreg);
12455 countreg = ix86_zero_extend_to_Pmode (countreg);
12457 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12458 GEN_INT (size == 4 ? 2 : 3));
12459 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
12460 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12462 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
12463 countreg, destexp, srcexp));
12464 offset = count & ~(size - 1);
12467 if (size == 8 && (count & 0x04))
12469 srcmem = adjust_automodify_address_nv (src, SImode, srcreg,
12471 dstmem = adjust_automodify_address_nv (dst, SImode, destreg,
12473 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12478 srcmem = adjust_automodify_address_nv (src, HImode, srcreg,
12480 dstmem = adjust_automodify_address_nv (dst, HImode, destreg,
12482 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12487 srcmem = adjust_automodify_address_nv (src, QImode, srcreg,
12489 dstmem = adjust_automodify_address_nv (dst, QImode, destreg,
12491 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12494 /* The generic code based on the glibc implementation:
12495 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
12496 allowing accelerated copying there)
12497 - copy the data using rep movsl
12498 - copy the rest. */
12503 rtx srcmem, dstmem;
12504 int desired_alignment = (TARGET_PENTIUMPRO
12505 && (count == 0 || count >= (unsigned int) 260)
12506 ? 8 : UNITS_PER_WORD);
12507 /* Get rid of MEM_OFFSETs, they won't be accurate. */
12508 dst = change_address (dst, BLKmode, destreg);
12509 src = change_address (src, BLKmode, srcreg);
12511 /* In case we don't know anything about the alignment, default to
12512 library version, since it is usually equally fast and result in
12515 Also emit call when we know that the count is large and call overhead
12516 will not be important. */
12517 if (!TARGET_INLINE_ALL_STRINGOPS
12518 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12521 if (TARGET_SINGLE_STRINGOP)
12522 emit_insn (gen_cld ());
12524 countreg2 = gen_reg_rtx (Pmode);
12525 countreg = copy_to_mode_reg (counter_mode, count_exp);
12527 /* We don't use loops to align destination and to copy parts smaller
12528 than 4 bytes, because gcc is able to optimize such code better (in
12529 the case the destination or the count really is aligned, gcc is often
12530 able to predict the branches) and also it is friendlier to the
12531 hardware branch prediction.
12533 Using loops is beneficial for generic case, because we can
12534 handle small counts using the loops. Many CPUs (such as Athlon)
12535 have large REP prefix setup costs.
12537 This is quite costly. Maybe we can revisit this decision later or
12538 add some customizability to this code. */
12540 if (count == 0 && align < desired_alignment)
12542 label = gen_label_rtx ();
12543 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12544 LEU, 0, counter_mode, 1, label);
12548 rtx label = ix86_expand_aligntest (destreg, 1);
12549 srcmem = change_address (src, QImode, srcreg);
12550 dstmem = change_address (dst, QImode, destreg);
12551 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12552 ix86_adjust_counter (countreg, 1);
12553 emit_label (label);
12554 LABEL_NUSES (label) = 1;
12558 rtx label = ix86_expand_aligntest (destreg, 2);
12559 srcmem = change_address (src, HImode, srcreg);
12560 dstmem = change_address (dst, HImode, destreg);
12561 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12562 ix86_adjust_counter (countreg, 2);
12563 emit_label (label);
12564 LABEL_NUSES (label) = 1;
12566 if (align <= 4 && desired_alignment > 4)
12568 rtx label = ix86_expand_aligntest (destreg, 4);
12569 srcmem = change_address (src, SImode, srcreg);
12570 dstmem = change_address (dst, SImode, destreg);
12571 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12572 ix86_adjust_counter (countreg, 4);
12573 emit_label (label);
12574 LABEL_NUSES (label) = 1;
12577 if (label && desired_alignment > 4 && !TARGET_64BIT)
12579 emit_label (label);
12580 LABEL_NUSES (label) = 1;
12583 if (!TARGET_SINGLE_STRINGOP)
12584 emit_insn (gen_cld ());
12587 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12589 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12593 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12594 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12596 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
12597 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12598 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
12599 countreg2, destexp, srcexp));
12603 emit_label (label);
12604 LABEL_NUSES (label) = 1;
12606 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12608 srcmem = change_address (src, SImode, srcreg);
12609 dstmem = change_address (dst, SImode, destreg);
12610 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12612 if ((align <= 4 || count == 0) && TARGET_64BIT)
12614 rtx label = ix86_expand_aligntest (countreg, 4);
12615 srcmem = change_address (src, SImode, srcreg);
12616 dstmem = change_address (dst, SImode, destreg);
12617 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12618 emit_label (label);
12619 LABEL_NUSES (label) = 1;
12621 if (align > 2 && count != 0 && (count & 2))
12623 srcmem = change_address (src, HImode, srcreg);
12624 dstmem = change_address (dst, HImode, destreg);
12625 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12627 if (align <= 2 || count == 0)
12629 rtx label = ix86_expand_aligntest (countreg, 2);
12630 srcmem = change_address (src, HImode, srcreg);
12631 dstmem = change_address (dst, HImode, destreg);
12632 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12633 emit_label (label);
12634 LABEL_NUSES (label) = 1;
12636 if (align > 1 && count != 0 && (count & 1))
12638 srcmem = change_address (src, QImode, srcreg);
12639 dstmem = change_address (dst, QImode, destreg);
12640 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12642 if (align <= 1 || count == 0)
12644 rtx label = ix86_expand_aligntest (countreg, 1);
12645 srcmem = change_address (src, QImode, srcreg);
12646 dstmem = change_address (dst, QImode, destreg);
12647 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12648 emit_label (label);
12649 LABEL_NUSES (label) = 1;
12656 /* Expand string clear operation (bzero). Use i386 string operations when
12657 profitable. expand_movmem contains similar code. */
12659 ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
12661 rtx destreg, zeroreg, countreg, destexp;
12662 enum machine_mode counter_mode;
12663 HOST_WIDE_INT align = 0;
12664 unsigned HOST_WIDE_INT count = 0;
12666 if (GET_CODE (align_exp) == CONST_INT)
12667 align = INTVAL (align_exp);
12669 /* Can't use any of this if the user has appropriated esi. */
12670 if (global_regs[4])
12673 /* This simple hack avoids all inlining code and simplifies code below. */
12674 if (!TARGET_ALIGN_STRINGOPS)
12677 if (GET_CODE (count_exp) == CONST_INT)
12679 count = INTVAL (count_exp);
12680 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12683 /* Figure out proper mode for counter. For 32bits it is always SImode,
12684 for 64bits use SImode when possible, otherwise DImode.
12685 Set count to number of bytes copied when known at compile time. */
12687 || GET_MODE (count_exp) == SImode
12688 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12689 counter_mode = SImode;
12691 counter_mode = DImode;
12693 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12694 if (destreg != XEXP (dst, 0))
12695 dst = replace_equiv_address_nv (dst, destreg);
12698 /* When optimizing for size emit simple rep ; movsb instruction for
12699 counts not divisible by 4. The movl $N, %ecx; rep; stosb
12700 sequence is 7 bytes long, so if optimizing for size and count is
12701 small enough that some stosl, stosw and stosb instructions without
12702 rep are shorter, fall back into the next if. */
12704 if ((!optimize || optimize_size)
12707 && (!optimize_size || (count & 0x03) + (count >> 2) > 7))))
12709 emit_insn (gen_cld ());
12711 countreg = ix86_zero_extend_to_Pmode (count_exp);
12712 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12713 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12714 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp));
12716 else if (count != 0
12718 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12719 || optimize_size || count < (unsigned int) 64))
12721 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12722 unsigned HOST_WIDE_INT offset = 0;
12724 emit_insn (gen_cld ());
12726 zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx);
12727 if (count & ~(size - 1))
12729 unsigned HOST_WIDE_INT repcount;
12730 unsigned int max_nonrep;
12732 repcount = count >> (size == 4 ? 2 : 3);
12734 repcount &= 0x3fffffff;
12736 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
12737 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
12738 bytes. In both cases the latter seems to be faster for small
12740 max_nonrep = size == 4 ? 7 : 4;
12741 if (!optimize_size)
12744 case PROCESSOR_PENTIUM4:
12745 case PROCESSOR_NOCONA:
12752 if (repcount <= max_nonrep)
12753 while (repcount-- > 0)
12755 rtx mem = adjust_automodify_address_nv (dst,
12756 GET_MODE (zeroreg),
12758 emit_insn (gen_strset (destreg, mem, zeroreg));
12763 countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount));
12764 countreg = ix86_zero_extend_to_Pmode (countreg);
12765 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12766 GEN_INT (size == 4 ? 2 : 3));
12767 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12768 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg,
12770 offset = count & ~(size - 1);
12773 if (size == 8 && (count & 0x04))
12775 rtx mem = adjust_automodify_address_nv (dst, SImode, destreg,
12777 emit_insn (gen_strset (destreg, mem,
12778 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12783 rtx mem = adjust_automodify_address_nv (dst, HImode, destreg,
12785 emit_insn (gen_strset (destreg, mem,
12786 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12791 rtx mem = adjust_automodify_address_nv (dst, QImode, destreg,
12793 emit_insn (gen_strset (destreg, mem,
12794 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12801 /* Compute desired alignment of the string operation. */
12802 int desired_alignment = (TARGET_PENTIUMPRO
12803 && (count == 0 || count >= (unsigned int) 260)
12804 ? 8 : UNITS_PER_WORD);
12806 /* In case we don't know anything about the alignment, default to
12807 library version, since it is usually equally fast and result in
12810 Also emit call when we know that the count is large and call overhead
12811 will not be important. */
12812 if (!TARGET_INLINE_ALL_STRINGOPS
12813 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12816 if (TARGET_SINGLE_STRINGOP)
12817 emit_insn (gen_cld ());
12819 countreg2 = gen_reg_rtx (Pmode);
12820 countreg = copy_to_mode_reg (counter_mode, count_exp);
12821 zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
12822 /* Get rid of MEM_OFFSET, it won't be accurate. */
12823 dst = change_address (dst, BLKmode, destreg);
12825 if (count == 0 && align < desired_alignment)
12827 label = gen_label_rtx ();
12828 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12829 LEU, 0, counter_mode, 1, label);
12833 rtx label = ix86_expand_aligntest (destreg, 1);
12834 emit_insn (gen_strset (destreg, dst,
12835 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12836 ix86_adjust_counter (countreg, 1);
12837 emit_label (label);
12838 LABEL_NUSES (label) = 1;
12842 rtx label = ix86_expand_aligntest (destreg, 2);
12843 emit_insn (gen_strset (destreg, dst,
12844 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12845 ix86_adjust_counter (countreg, 2);
12846 emit_label (label);
12847 LABEL_NUSES (label) = 1;
12849 if (align <= 4 && desired_alignment > 4)
12851 rtx label = ix86_expand_aligntest (destreg, 4);
12852 emit_insn (gen_strset (destreg, dst,
12854 ? gen_rtx_SUBREG (SImode, zeroreg, 0)
12856 ix86_adjust_counter (countreg, 4);
12857 emit_label (label);
12858 LABEL_NUSES (label) = 1;
12861 if (label && desired_alignment > 4 && !TARGET_64BIT)
12863 emit_label (label);
12864 LABEL_NUSES (label) = 1;
12868 if (!TARGET_SINGLE_STRINGOP)
12869 emit_insn (gen_cld ());
12872 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12874 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12878 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12879 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12881 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12882 emit_insn (gen_rep_stos (destreg, countreg2, dst, zeroreg, destexp));
12886 emit_label (label);
12887 LABEL_NUSES (label) = 1;
12890 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12891 emit_insn (gen_strset (destreg, dst,
12892 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12893 if (TARGET_64BIT && (align <= 4 || count == 0))
12895 rtx label = ix86_expand_aligntest (countreg, 4);
12896 emit_insn (gen_strset (destreg, dst,
12897 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12898 emit_label (label);
12899 LABEL_NUSES (label) = 1;
12901 if (align > 2 && count != 0 && (count & 2))
12902 emit_insn (gen_strset (destreg, dst,
12903 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12904 if (align <= 2 || count == 0)
12906 rtx label = ix86_expand_aligntest (countreg, 2);
12907 emit_insn (gen_strset (destreg, dst,
12908 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12909 emit_label (label);
12910 LABEL_NUSES (label) = 1;
12912 if (align > 1 && count != 0 && (count & 1))
12913 emit_insn (gen_strset (destreg, dst,
12914 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12915 if (align <= 1 || count == 0)
12917 rtx label = ix86_expand_aligntest (countreg, 1);
12918 emit_insn (gen_strset (destreg, dst,
12919 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12920 emit_label (label);
12921 LABEL_NUSES (label) = 1;
12927 /* Expand strlen. */
12929 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
12931 rtx addr, scratch1, scratch2, scratch3, scratch4;
12933 /* The generic case of strlen expander is long. Avoid it's
12934 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12936 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12937 && !TARGET_INLINE_ALL_STRINGOPS
12939 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12942 addr = force_reg (Pmode, XEXP (src, 0));
12943 scratch1 = gen_reg_rtx (Pmode);
12945 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12948 /* Well it seems that some optimizer does not combine a call like
12949 foo(strlen(bar), strlen(bar));
12950 when the move and the subtraction is done here. It does calculate
12951 the length just once when these instructions are done inside of
12952 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12953 often used and I use one fewer register for the lifetime of
12954 output_strlen_unroll() this is better. */
12956 emit_move_insn (out, addr);
12958 ix86_expand_strlensi_unroll_1 (out, src, align);
12960 /* strlensi_unroll_1 returns the address of the zero at the end of
12961 the string, like memchr(), so compute the length by subtracting
12962 the start address. */
12964 emit_insn (gen_subdi3 (out, out, addr));
12966 emit_insn (gen_subsi3 (out, out, addr));
12971 scratch2 = gen_reg_rtx (Pmode);
12972 scratch3 = gen_reg_rtx (Pmode);
12973 scratch4 = force_reg (Pmode, constm1_rtx);
12975 emit_move_insn (scratch3, addr);
12976 eoschar = force_reg (QImode, eoschar);
12978 emit_insn (gen_cld ());
12979 src = replace_equiv_address_nv (src, scratch3);
12981 /* If .md starts supporting :P, this can be done in .md. */
12982 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
12983 scratch4), UNSPEC_SCAS);
12984 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
12987 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
12988 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
12992 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12993 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12999 /* Expand the appropriate insns for doing strlen if not just doing
13002 out = result, initialized with the start address
13003 align_rtx = alignment of the address.
13004 scratch = scratch register, initialized with the startaddress when
13005 not aligned, otherwise undefined
13007 This is just the body. It needs the initializations mentioned above and
13008 some address computing at the end. These things are done in i386.md. */
13011 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
13015 rtx align_2_label = NULL_RTX;
13016 rtx align_3_label = NULL_RTX;
13017 rtx align_4_label = gen_label_rtx ();
13018 rtx end_0_label = gen_label_rtx ();
13020 rtx tmpreg = gen_reg_rtx (SImode);
13021 rtx scratch = gen_reg_rtx (SImode);
13025 if (GET_CODE (align_rtx) == CONST_INT)
13026 align = INTVAL (align_rtx);
13028 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
13030 /* Is there a known alignment and is it less than 4? */
13033 rtx scratch1 = gen_reg_rtx (Pmode);
13034 emit_move_insn (scratch1, out);
13035 /* Is there a known alignment and is it not 2? */
13038 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
13039 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
13041 /* Leave just the 3 lower bits. */
13042 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
13043 NULL_RTX, 0, OPTAB_WIDEN);
13045 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
13046 Pmode, 1, align_4_label);
13047 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
13048 Pmode, 1, align_2_label);
13049 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
13050 Pmode, 1, align_3_label);
13054 /* Since the alignment is 2, we have to check 2 or 0 bytes;
13055 check if is aligned to 4 - byte. */
13057 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
13058 NULL_RTX, 0, OPTAB_WIDEN);
13060 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
13061 Pmode, 1, align_4_label);
13064 mem = change_address (src, QImode, out);
13066 /* Now compare the bytes. */
13068 /* Compare the first n unaligned byte on a byte per byte basis. */
13069 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
13070 QImode, 1, end_0_label);
13072 /* Increment the address. */
13074 emit_insn (gen_adddi3 (out, out, const1_rtx));
13076 emit_insn (gen_addsi3 (out, out, const1_rtx));
13078 /* Not needed with an alignment of 2 */
13081 emit_label (align_2_label);
13083 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
13087 emit_insn (gen_adddi3 (out, out, const1_rtx));
13089 emit_insn (gen_addsi3 (out, out, const1_rtx));
13091 emit_label (align_3_label);
13094 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
13098 emit_insn (gen_adddi3 (out, out, const1_rtx));
13100 emit_insn (gen_addsi3 (out, out, const1_rtx));
13103 /* Generate loop to check 4 bytes at a time. It is not a good idea to
13104 align this loop. It gives only huge programs, but does not help to
13106 emit_label (align_4_label);
13108 mem = change_address (src, SImode, out);
13109 emit_move_insn (scratch, mem);
13111 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
13113 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
13115 /* This formula yields a nonzero result iff one of the bytes is zero.
13116 This saves three branches inside loop and many cycles. */
13118 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
13119 emit_insn (gen_one_cmplsi2 (scratch, scratch));
13120 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
13121 emit_insn (gen_andsi3 (tmpreg, tmpreg,
13122 gen_int_mode (0x80808080, SImode)));
13123 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
13128 rtx reg = gen_reg_rtx (SImode);
13129 rtx reg2 = gen_reg_rtx (Pmode);
13130 emit_move_insn (reg, tmpreg);
13131 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
13133 /* If zero is not in the first two bytes, move two bytes forward. */
13134 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
13135 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13136 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
13137 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
13138 gen_rtx_IF_THEN_ELSE (SImode, tmp,
13141 /* Emit lea manually to avoid clobbering of flags. */
13142 emit_insn (gen_rtx_SET (SImode, reg2,
13143 gen_rtx_PLUS (Pmode, out, const2_rtx)));
13145 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13146 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
13147 emit_insn (gen_rtx_SET (VOIDmode, out,
13148 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
13155 rtx end_2_label = gen_label_rtx ();
13156 /* Is zero in the first two bytes? */
13158 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
13159 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
13160 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
13161 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13162 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
13164 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
13165 JUMP_LABEL (tmp) = end_2_label;
13167 /* Not in the first two. Move two bytes forward. */
13168 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
13170 emit_insn (gen_adddi3 (out, out, const2_rtx));
13172 emit_insn (gen_addsi3 (out, out, const2_rtx));
13174 emit_label (end_2_label);
13178 /* Avoid branch in fixing the byte. */
13179 tmpreg = gen_lowpart (QImode, tmpreg);
13180 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
13181 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
13183 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
13185 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
13187 emit_label (end_0_label);
13191 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
13192 rtx callarg2 ATTRIBUTE_UNUSED,
13193 rtx pop, int sibcall)
13195 rtx use = NULL, call;
13197 if (pop == const0_rtx)
13199 gcc_assert (!TARGET_64BIT || !pop);
13202 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
13203 fnaddr = machopic_indirect_call_target (fnaddr);
13205 /* Static functions and indirect calls don't need the pic register. */
13206 if (! TARGET_64BIT && flag_pic
13207 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
13208 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
13209 use_reg (&use, pic_offset_table_rtx);
13211 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
13213 rtx al = gen_rtx_REG (QImode, 0);
13214 emit_move_insn (al, callarg2);
13215 use_reg (&use, al);
13217 #endif /* TARGET_MACHO */
13219 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
13221 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
13222 fnaddr = gen_rtx_MEM (QImode, fnaddr);
13224 if (sibcall && TARGET_64BIT
13225 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
13228 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
13229 fnaddr = gen_rtx_REG (Pmode, FIRST_REX_INT_REG + 3 /* R11 */);
13230 emit_move_insn (fnaddr, addr);
13231 fnaddr = gen_rtx_MEM (QImode, fnaddr);
13234 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
13236 call = gen_rtx_SET (VOIDmode, retval, call);
13239 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
13240 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
13241 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
13244 call = emit_call_insn (call);
13246 CALL_INSN_FUNCTION_USAGE (call) = use;
13250 /* Clear stack slot assignments remembered from previous functions.
13251 This is called from INIT_EXPANDERS once before RTL is emitted for each
13254 static struct machine_function *
13255 ix86_init_machine_status (void)
13257 struct machine_function *f;
13259 f = ggc_alloc_cleared (sizeof (struct machine_function));
13260 f->use_fast_prologue_epilogue_nregs = -1;
13261 f->tls_descriptor_call_expanded_p = 0;
13266 /* Return a MEM corresponding to a stack slot with mode MODE.
13267 Allocate a new slot if necessary.
13269 The RTL for a function can have several slots available: N is
13270 which slot to use. */
13273 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
13275 struct stack_local_entry *s;
13277 gcc_assert (n < MAX_386_STACK_LOCALS);
13279 for (s = ix86_stack_locals; s; s = s->next)
13280 if (s->mode == mode && s->n == n)
13283 s = (struct stack_local_entry *)
13284 ggc_alloc (sizeof (struct stack_local_entry));
13287 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13289 s->next = ix86_stack_locals;
13290 ix86_stack_locals = s;
13294 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13296 static GTY(()) rtx ix86_tls_symbol;
13298 ix86_tls_get_addr (void)
13301 if (!ix86_tls_symbol)
13303 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
13304 (TARGET_ANY_GNU_TLS
13306 ? "___tls_get_addr"
13307 : "__tls_get_addr");
13310 return ix86_tls_symbol;
13313 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13315 static GTY(()) rtx ix86_tls_module_base_symbol;
13317 ix86_tls_module_base (void)
13320 if (!ix86_tls_module_base_symbol)
13322 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
13323 "_TLS_MODULE_BASE_");
13324 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
13325 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
13328 return ix86_tls_module_base_symbol;
13331 /* Calculate the length of the memory address in the instruction
13332 encoding. Does not include the one-byte modrm, opcode, or prefix. */
13335 memory_address_length (rtx addr)
13337 struct ix86_address parts;
13338 rtx base, index, disp;
13342 if (GET_CODE (addr) == PRE_DEC
13343 || GET_CODE (addr) == POST_INC
13344 || GET_CODE (addr) == PRE_MODIFY
13345 || GET_CODE (addr) == POST_MODIFY)
13348 ok = ix86_decompose_address (addr, &parts);
13351 if (parts.base && GET_CODE (parts.base) == SUBREG)
13352 parts.base = SUBREG_REG (parts.base);
13353 if (parts.index && GET_CODE (parts.index) == SUBREG)
13354 parts.index = SUBREG_REG (parts.index);
13357 index = parts.index;
13362 - esp as the base always wants an index,
13363 - ebp as the base always wants a displacement. */
13365 /* Register Indirect. */
13366 if (base && !index && !disp)
13368 /* esp (for its index) and ebp (for its displacement) need
13369 the two-byte modrm form. */
13370 if (addr == stack_pointer_rtx
13371 || addr == arg_pointer_rtx
13372 || addr == frame_pointer_rtx
13373 || addr == hard_frame_pointer_rtx)
13377 /* Direct Addressing. */
13378 else if (disp && !base && !index)
13383 /* Find the length of the displacement constant. */
13386 if (base && satisfies_constraint_K (disp))
13391 /* ebp always wants a displacement. */
13392 else if (base == hard_frame_pointer_rtx)
13395 /* An index requires the two-byte modrm form.... */
13397 /* ...like esp, which always wants an index. */
13398 || base == stack_pointer_rtx
13399 || base == arg_pointer_rtx
13400 || base == frame_pointer_rtx)
13407 /* Compute default value for "length_immediate" attribute. When SHORTFORM
13408 is set, expect that insn have 8bit immediate alternative. */
13410 ix86_attr_length_immediate_default (rtx insn, int shortform)
13414 extract_insn_cached (insn);
13415 for (i = recog_data.n_operands - 1; i >= 0; --i)
13416 if (CONSTANT_P (recog_data.operand[i]))
13419 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
13423 switch (get_attr_mode (insn))
13434 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
13439 fatal_insn ("unknown insn mode", insn);
13445 /* Compute default value for "length_address" attribute. */
13447 ix86_attr_length_address_default (rtx insn)
13451 if (get_attr_type (insn) == TYPE_LEA)
13453 rtx set = PATTERN (insn);
13455 if (GET_CODE (set) == PARALLEL)
13456 set = XVECEXP (set, 0, 0);
13458 gcc_assert (GET_CODE (set) == SET);
13460 return memory_address_length (SET_SRC (set));
13463 extract_insn_cached (insn);
13464 for (i = recog_data.n_operands - 1; i >= 0; --i)
13465 if (GET_CODE (recog_data.operand[i]) == MEM)
13467 return memory_address_length (XEXP (recog_data.operand[i], 0));
13473 /* Return the maximum number of instructions a cpu can issue. */
13476 ix86_issue_rate (void)
13480 case PROCESSOR_PENTIUM:
13484 case PROCESSOR_PENTIUMPRO:
13485 case PROCESSOR_PENTIUM4:
13486 case PROCESSOR_ATHLON:
13488 case PROCESSOR_NOCONA:
13489 case PROCESSOR_GENERIC32:
13490 case PROCESSOR_GENERIC64:
13498 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
13499 by DEP_INSN and nothing set by DEP_INSN. */
13502 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
13506 /* Simplify the test for uninteresting insns. */
13507 if (insn_type != TYPE_SETCC
13508 && insn_type != TYPE_ICMOV
13509 && insn_type != TYPE_FCMOV
13510 && insn_type != TYPE_IBR)
13513 if ((set = single_set (dep_insn)) != 0)
13515 set = SET_DEST (set);
13518 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
13519 && XVECLEN (PATTERN (dep_insn), 0) == 2
13520 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
13521 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
13523 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13524 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13529 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
13532 /* This test is true if the dependent insn reads the flags but
13533 not any other potentially set register. */
13534 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
13537 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
13543 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
13544 address with operands set by DEP_INSN. */
13547 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
13551 if (insn_type == TYPE_LEA
13554 addr = PATTERN (insn);
13556 if (GET_CODE (addr) == PARALLEL)
13557 addr = XVECEXP (addr, 0, 0);
13559 gcc_assert (GET_CODE (addr) == SET);
13561 addr = SET_SRC (addr);
13566 extract_insn_cached (insn);
13567 for (i = recog_data.n_operands - 1; i >= 0; --i)
13568 if (GET_CODE (recog_data.operand[i]) == MEM)
13570 addr = XEXP (recog_data.operand[i], 0);
13577 return modified_in_p (addr, dep_insn);
13581 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
13583 enum attr_type insn_type, dep_insn_type;
13584 enum attr_memory memory;
13586 int dep_insn_code_number;
13588 /* Anti and output dependencies have zero cost on all CPUs. */
13589 if (REG_NOTE_KIND (link) != 0)
13592 dep_insn_code_number = recog_memoized (dep_insn);
13594 /* If we can't recognize the insns, we can't really do anything. */
13595 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
13598 insn_type = get_attr_type (insn);
13599 dep_insn_type = get_attr_type (dep_insn);
13603 case PROCESSOR_PENTIUM:
13604 /* Address Generation Interlock adds a cycle of latency. */
13605 if (ix86_agi_dependent (insn, dep_insn, insn_type))
13608 /* ??? Compares pair with jump/setcc. */
13609 if (ix86_flags_dependent (insn, dep_insn, insn_type))
13612 /* Floating point stores require value to be ready one cycle earlier. */
13613 if (insn_type == TYPE_FMOV
13614 && get_attr_memory (insn) == MEMORY_STORE
13615 && !ix86_agi_dependent (insn, dep_insn, insn_type))
13619 case PROCESSOR_PENTIUMPRO:
13620 memory = get_attr_memory (insn);
13622 /* INT->FP conversion is expensive. */
13623 if (get_attr_fp_int_src (dep_insn))
13626 /* There is one cycle extra latency between an FP op and a store. */
13627 if (insn_type == TYPE_FMOV
13628 && (set = single_set (dep_insn)) != NULL_RTX
13629 && (set2 = single_set (insn)) != NULL_RTX
13630 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
13631 && GET_CODE (SET_DEST (set2)) == MEM)
13634 /* Show ability of reorder buffer to hide latency of load by executing
13635 in parallel with previous instruction in case
13636 previous instruction is not needed to compute the address. */
13637 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13638 && !ix86_agi_dependent (insn, dep_insn, insn_type))
13640 /* Claim moves to take one cycle, as core can issue one load
13641 at time and the next load can start cycle later. */
13642 if (dep_insn_type == TYPE_IMOV
13643 || dep_insn_type == TYPE_FMOV)
13651 memory = get_attr_memory (insn);
13653 /* The esp dependency is resolved before the instruction is really
13655 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
13656 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
13659 /* INT->FP conversion is expensive. */
13660 if (get_attr_fp_int_src (dep_insn))
13663 /* Show ability of reorder buffer to hide latency of load by executing
13664 in parallel with previous instruction in case
13665 previous instruction is not needed to compute the address. */
13666 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13667 && !ix86_agi_dependent (insn, dep_insn, insn_type))
13669 /* Claim moves to take one cycle, as core can issue one load
13670 at time and the next load can start cycle later. */
13671 if (dep_insn_type == TYPE_IMOV
13672 || dep_insn_type == TYPE_FMOV)
13681 case PROCESSOR_ATHLON:
13683 case PROCESSOR_GENERIC32:
13684 case PROCESSOR_GENERIC64:
13685 memory = get_attr_memory (insn);
13687 /* Show ability of reorder buffer to hide latency of load by executing
13688 in parallel with previous instruction in case
13689 previous instruction is not needed to compute the address. */
13690 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13691 && !ix86_agi_dependent (insn, dep_insn, insn_type))
13693 enum attr_unit unit = get_attr_unit (insn);
13696 /* Because of the difference between the length of integer and
13697 floating unit pipeline preparation stages, the memory operands
13698 for floating point are cheaper.
13700 ??? For Athlon it the difference is most probably 2. */
13701 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
13704 loadcost = TARGET_ATHLON ? 2 : 0;
13706 if (cost >= loadcost)
13719 /* How many alternative schedules to try. This should be as wide as the
13720 scheduling freedom in the DFA, but no wider. Making this value too
13721 large results extra work for the scheduler. */
13724 ia32_multipass_dfa_lookahead (void)
13726 if (ix86_tune == PROCESSOR_PENTIUM)
13729 if (ix86_tune == PROCESSOR_PENTIUMPRO
13730 || ix86_tune == PROCESSOR_K6)
13738 /* Compute the alignment given to a constant that is being placed in memory.
13739 EXP is the constant and ALIGN is the alignment that the object would
13741 The value of this function is used instead of that alignment to align
13745 ix86_constant_alignment (tree exp, int align)
13747 if (TREE_CODE (exp) == REAL_CST)
13749 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
13751 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
13754 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
13755 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
13756 return BITS_PER_WORD;
13761 /* Compute the alignment for a static variable.
13762 TYPE is the data type, and ALIGN is the alignment that
13763 the object would ordinarily have. The value of this function is used
13764 instead of that alignment to align the object. */
13767 ix86_data_alignment (tree type, int align)
13769 int max_align = optimize_size ? BITS_PER_WORD : 256;
13771 if (AGGREGATE_TYPE_P (type)
13772 && TYPE_SIZE (type)
13773 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13774 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
13775 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
13776 && align < max_align)
13779 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13780 to 16byte boundary. */
13783 if (AGGREGATE_TYPE_P (type)
13784 && TYPE_SIZE (type)
13785 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13786 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
13787 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13791 if (TREE_CODE (type) == ARRAY_TYPE)
13793 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13795 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13798 else if (TREE_CODE (type) == COMPLEX_TYPE)
13801 if (TYPE_MODE (type) == DCmode && align < 64)
13803 if (TYPE_MODE (type) == XCmode && align < 128)
13806 else if ((TREE_CODE (type) == RECORD_TYPE
13807 || TREE_CODE (type) == UNION_TYPE
13808 || TREE_CODE (type) == QUAL_UNION_TYPE)
13809 && TYPE_FIELDS (type))
13811 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13813 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13816 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13817 || TREE_CODE (type) == INTEGER_TYPE)
13819 if (TYPE_MODE (type) == DFmode && align < 64)
13821 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13828 /* Compute the alignment for a local variable.
13829 TYPE is the data type, and ALIGN is the alignment that
13830 the object would ordinarily have. The value of this macro is used
13831 instead of that alignment to align the object. */
13834 ix86_local_alignment (tree type, int align)
13836 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13837 to 16byte boundary. */
13840 if (AGGREGATE_TYPE_P (type)
13841 && TYPE_SIZE (type)
13842 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13843 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
13844 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13847 if (TREE_CODE (type) == ARRAY_TYPE)
13849 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13851 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13854 else if (TREE_CODE (type) == COMPLEX_TYPE)
13856 if (TYPE_MODE (type) == DCmode && align < 64)
13858 if (TYPE_MODE (type) == XCmode && align < 128)
13861 else if ((TREE_CODE (type) == RECORD_TYPE
13862 || TREE_CODE (type) == UNION_TYPE
13863 || TREE_CODE (type) == QUAL_UNION_TYPE)
13864 && TYPE_FIELDS (type))
13866 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13868 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13871 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13872 || TREE_CODE (type) == INTEGER_TYPE)
13875 if (TYPE_MODE (type) == DFmode && align < 64)
13877 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13883 /* Emit RTL insns to initialize the variable parts of a trampoline.
13884 FNADDR is an RTX for the address of the function's pure code.
13885 CXT is an RTX for the static chain value for the function. */
13887 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
13891 /* Compute offset from the end of the jmp to the target function. */
13892 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
13893 plus_constant (tramp, 10),
13894 NULL_RTX, 1, OPTAB_DIRECT);
13895 emit_move_insn (gen_rtx_MEM (QImode, tramp),
13896 gen_int_mode (0xb9, QImode));
13897 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
13898 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
13899 gen_int_mode (0xe9, QImode));
13900 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
13905 /* Try to load address using shorter movl instead of movabs.
13906 We may want to support movq for kernel mode, but kernel does not use
13907 trampolines at the moment. */
13908 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
13910 fnaddr = copy_to_mode_reg (DImode, fnaddr);
13911 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13912 gen_int_mode (0xbb41, HImode));
13913 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
13914 gen_lowpart (SImode, fnaddr));
13919 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13920 gen_int_mode (0xbb49, HImode));
13921 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13925 /* Load static chain using movabs to r10. */
13926 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13927 gen_int_mode (0xba49, HImode));
13928 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13931 /* Jump to the r11 */
13932 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13933 gen_int_mode (0xff49, HImode));
13934 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
13935 gen_int_mode (0xe3, QImode));
13937 gcc_assert (offset <= TRAMPOLINE_SIZE);
13940 #ifdef ENABLE_EXECUTE_STACK
13941 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
13942 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
13946 /* Codes for all the SSE/MMX builtins. */
13949 IX86_BUILTIN_ADDPS,
13950 IX86_BUILTIN_ADDSS,
13951 IX86_BUILTIN_DIVPS,
13952 IX86_BUILTIN_DIVSS,
13953 IX86_BUILTIN_MULPS,
13954 IX86_BUILTIN_MULSS,
13955 IX86_BUILTIN_SUBPS,
13956 IX86_BUILTIN_SUBSS,
13958 IX86_BUILTIN_CMPEQPS,
13959 IX86_BUILTIN_CMPLTPS,
13960 IX86_BUILTIN_CMPLEPS,
13961 IX86_BUILTIN_CMPGTPS,
13962 IX86_BUILTIN_CMPGEPS,
13963 IX86_BUILTIN_CMPNEQPS,
13964 IX86_BUILTIN_CMPNLTPS,
13965 IX86_BUILTIN_CMPNLEPS,
13966 IX86_BUILTIN_CMPNGTPS,
13967 IX86_BUILTIN_CMPNGEPS,
13968 IX86_BUILTIN_CMPORDPS,
13969 IX86_BUILTIN_CMPUNORDPS,
13970 IX86_BUILTIN_CMPEQSS,
13971 IX86_BUILTIN_CMPLTSS,
13972 IX86_BUILTIN_CMPLESS,
13973 IX86_BUILTIN_CMPNEQSS,
13974 IX86_BUILTIN_CMPNLTSS,
13975 IX86_BUILTIN_CMPNLESS,
13976 IX86_BUILTIN_CMPNGTSS,
13977 IX86_BUILTIN_CMPNGESS,
13978 IX86_BUILTIN_CMPORDSS,
13979 IX86_BUILTIN_CMPUNORDSS,
13981 IX86_BUILTIN_COMIEQSS,
13982 IX86_BUILTIN_COMILTSS,
13983 IX86_BUILTIN_COMILESS,
13984 IX86_BUILTIN_COMIGTSS,
13985 IX86_BUILTIN_COMIGESS,
13986 IX86_BUILTIN_COMINEQSS,
13987 IX86_BUILTIN_UCOMIEQSS,
13988 IX86_BUILTIN_UCOMILTSS,
13989 IX86_BUILTIN_UCOMILESS,
13990 IX86_BUILTIN_UCOMIGTSS,
13991 IX86_BUILTIN_UCOMIGESS,
13992 IX86_BUILTIN_UCOMINEQSS,
13994 IX86_BUILTIN_CVTPI2PS,
13995 IX86_BUILTIN_CVTPS2PI,
13996 IX86_BUILTIN_CVTSI2SS,
13997 IX86_BUILTIN_CVTSI642SS,
13998 IX86_BUILTIN_CVTSS2SI,
13999 IX86_BUILTIN_CVTSS2SI64,
14000 IX86_BUILTIN_CVTTPS2PI,
14001 IX86_BUILTIN_CVTTSS2SI,
14002 IX86_BUILTIN_CVTTSS2SI64,
14004 IX86_BUILTIN_MAXPS,
14005 IX86_BUILTIN_MAXSS,
14006 IX86_BUILTIN_MINPS,
14007 IX86_BUILTIN_MINSS,
14009 IX86_BUILTIN_LOADUPS,
14010 IX86_BUILTIN_STOREUPS,
14011 IX86_BUILTIN_MOVSS,
14013 IX86_BUILTIN_MOVHLPS,
14014 IX86_BUILTIN_MOVLHPS,
14015 IX86_BUILTIN_LOADHPS,
14016 IX86_BUILTIN_LOADLPS,
14017 IX86_BUILTIN_STOREHPS,
14018 IX86_BUILTIN_STORELPS,
14020 IX86_BUILTIN_MASKMOVQ,
14021 IX86_BUILTIN_MOVMSKPS,
14022 IX86_BUILTIN_PMOVMSKB,
14024 IX86_BUILTIN_MOVNTPS,
14025 IX86_BUILTIN_MOVNTQ,
14027 IX86_BUILTIN_LOADDQU,
14028 IX86_BUILTIN_STOREDQU,
14030 IX86_BUILTIN_PACKSSWB,
14031 IX86_BUILTIN_PACKSSDW,
14032 IX86_BUILTIN_PACKUSWB,
14034 IX86_BUILTIN_PADDB,
14035 IX86_BUILTIN_PADDW,
14036 IX86_BUILTIN_PADDD,
14037 IX86_BUILTIN_PADDQ,
14038 IX86_BUILTIN_PADDSB,
14039 IX86_BUILTIN_PADDSW,
14040 IX86_BUILTIN_PADDUSB,
14041 IX86_BUILTIN_PADDUSW,
14042 IX86_BUILTIN_PSUBB,
14043 IX86_BUILTIN_PSUBW,
14044 IX86_BUILTIN_PSUBD,
14045 IX86_BUILTIN_PSUBQ,
14046 IX86_BUILTIN_PSUBSB,
14047 IX86_BUILTIN_PSUBSW,
14048 IX86_BUILTIN_PSUBUSB,
14049 IX86_BUILTIN_PSUBUSW,
14052 IX86_BUILTIN_PANDN,
14056 IX86_BUILTIN_PAVGB,
14057 IX86_BUILTIN_PAVGW,
14059 IX86_BUILTIN_PCMPEQB,
14060 IX86_BUILTIN_PCMPEQW,
14061 IX86_BUILTIN_PCMPEQD,
14062 IX86_BUILTIN_PCMPGTB,
14063 IX86_BUILTIN_PCMPGTW,
14064 IX86_BUILTIN_PCMPGTD,
14066 IX86_BUILTIN_PMADDWD,
14068 IX86_BUILTIN_PMAXSW,
14069 IX86_BUILTIN_PMAXUB,
14070 IX86_BUILTIN_PMINSW,
14071 IX86_BUILTIN_PMINUB,
14073 IX86_BUILTIN_PMULHUW,
14074 IX86_BUILTIN_PMULHW,
14075 IX86_BUILTIN_PMULLW,
14077 IX86_BUILTIN_PSADBW,
14078 IX86_BUILTIN_PSHUFW,
14080 IX86_BUILTIN_PSLLW,
14081 IX86_BUILTIN_PSLLD,
14082 IX86_BUILTIN_PSLLQ,
14083 IX86_BUILTIN_PSRAW,
14084 IX86_BUILTIN_PSRAD,
14085 IX86_BUILTIN_PSRLW,
14086 IX86_BUILTIN_PSRLD,
14087 IX86_BUILTIN_PSRLQ,
14088 IX86_BUILTIN_PSLLWI,
14089 IX86_BUILTIN_PSLLDI,
14090 IX86_BUILTIN_PSLLQI,
14091 IX86_BUILTIN_PSRAWI,
14092 IX86_BUILTIN_PSRADI,
14093 IX86_BUILTIN_PSRLWI,
14094 IX86_BUILTIN_PSRLDI,
14095 IX86_BUILTIN_PSRLQI,
14097 IX86_BUILTIN_PUNPCKHBW,
14098 IX86_BUILTIN_PUNPCKHWD,
14099 IX86_BUILTIN_PUNPCKHDQ,
14100 IX86_BUILTIN_PUNPCKLBW,
14101 IX86_BUILTIN_PUNPCKLWD,
14102 IX86_BUILTIN_PUNPCKLDQ,
14104 IX86_BUILTIN_SHUFPS,
14106 IX86_BUILTIN_RCPPS,
14107 IX86_BUILTIN_RCPSS,
14108 IX86_BUILTIN_RSQRTPS,
14109 IX86_BUILTIN_RSQRTSS,
14110 IX86_BUILTIN_SQRTPS,
14111 IX86_BUILTIN_SQRTSS,
14113 IX86_BUILTIN_UNPCKHPS,
14114 IX86_BUILTIN_UNPCKLPS,
14116 IX86_BUILTIN_ANDPS,
14117 IX86_BUILTIN_ANDNPS,
14119 IX86_BUILTIN_XORPS,
14122 IX86_BUILTIN_LDMXCSR,
14123 IX86_BUILTIN_STMXCSR,
14124 IX86_BUILTIN_SFENCE,
14126 /* 3DNow! Original */
14127 IX86_BUILTIN_FEMMS,
14128 IX86_BUILTIN_PAVGUSB,
14129 IX86_BUILTIN_PF2ID,
14130 IX86_BUILTIN_PFACC,
14131 IX86_BUILTIN_PFADD,
14132 IX86_BUILTIN_PFCMPEQ,
14133 IX86_BUILTIN_PFCMPGE,
14134 IX86_BUILTIN_PFCMPGT,
14135 IX86_BUILTIN_PFMAX,
14136 IX86_BUILTIN_PFMIN,
14137 IX86_BUILTIN_PFMUL,
14138 IX86_BUILTIN_PFRCP,
14139 IX86_BUILTIN_PFRCPIT1,
14140 IX86_BUILTIN_PFRCPIT2,
14141 IX86_BUILTIN_PFRSQIT1,
14142 IX86_BUILTIN_PFRSQRT,
14143 IX86_BUILTIN_PFSUB,
14144 IX86_BUILTIN_PFSUBR,
14145 IX86_BUILTIN_PI2FD,
14146 IX86_BUILTIN_PMULHRW,
14148 /* 3DNow! Athlon Extensions */
14149 IX86_BUILTIN_PF2IW,
14150 IX86_BUILTIN_PFNACC,
14151 IX86_BUILTIN_PFPNACC,
14152 IX86_BUILTIN_PI2FW,
14153 IX86_BUILTIN_PSWAPDSI,
14154 IX86_BUILTIN_PSWAPDSF,
14157 IX86_BUILTIN_ADDPD,
14158 IX86_BUILTIN_ADDSD,
14159 IX86_BUILTIN_DIVPD,
14160 IX86_BUILTIN_DIVSD,
14161 IX86_BUILTIN_MULPD,
14162 IX86_BUILTIN_MULSD,
14163 IX86_BUILTIN_SUBPD,
14164 IX86_BUILTIN_SUBSD,
14166 IX86_BUILTIN_CMPEQPD,
14167 IX86_BUILTIN_CMPLTPD,
14168 IX86_BUILTIN_CMPLEPD,
14169 IX86_BUILTIN_CMPGTPD,
14170 IX86_BUILTIN_CMPGEPD,
14171 IX86_BUILTIN_CMPNEQPD,
14172 IX86_BUILTIN_CMPNLTPD,
14173 IX86_BUILTIN_CMPNLEPD,
14174 IX86_BUILTIN_CMPNGTPD,
14175 IX86_BUILTIN_CMPNGEPD,
14176 IX86_BUILTIN_CMPORDPD,
14177 IX86_BUILTIN_CMPUNORDPD,
14178 IX86_BUILTIN_CMPNEPD,
14179 IX86_BUILTIN_CMPEQSD,
14180 IX86_BUILTIN_CMPLTSD,
14181 IX86_BUILTIN_CMPLESD,
14182 IX86_BUILTIN_CMPNEQSD,
14183 IX86_BUILTIN_CMPNLTSD,
14184 IX86_BUILTIN_CMPNLESD,
14185 IX86_BUILTIN_CMPORDSD,
14186 IX86_BUILTIN_CMPUNORDSD,
14187 IX86_BUILTIN_CMPNESD,
14189 IX86_BUILTIN_COMIEQSD,
14190 IX86_BUILTIN_COMILTSD,
14191 IX86_BUILTIN_COMILESD,
14192 IX86_BUILTIN_COMIGTSD,
14193 IX86_BUILTIN_COMIGESD,
14194 IX86_BUILTIN_COMINEQSD,
14195 IX86_BUILTIN_UCOMIEQSD,
14196 IX86_BUILTIN_UCOMILTSD,
14197 IX86_BUILTIN_UCOMILESD,
14198 IX86_BUILTIN_UCOMIGTSD,
14199 IX86_BUILTIN_UCOMIGESD,
14200 IX86_BUILTIN_UCOMINEQSD,
14202 IX86_BUILTIN_MAXPD,
14203 IX86_BUILTIN_MAXSD,
14204 IX86_BUILTIN_MINPD,
14205 IX86_BUILTIN_MINSD,
14207 IX86_BUILTIN_ANDPD,
14208 IX86_BUILTIN_ANDNPD,
14210 IX86_BUILTIN_XORPD,
14212 IX86_BUILTIN_SQRTPD,
14213 IX86_BUILTIN_SQRTSD,
14215 IX86_BUILTIN_UNPCKHPD,
14216 IX86_BUILTIN_UNPCKLPD,
14218 IX86_BUILTIN_SHUFPD,
14220 IX86_BUILTIN_LOADUPD,
14221 IX86_BUILTIN_STOREUPD,
14222 IX86_BUILTIN_MOVSD,
14224 IX86_BUILTIN_LOADHPD,
14225 IX86_BUILTIN_LOADLPD,
14227 IX86_BUILTIN_CVTDQ2PD,
14228 IX86_BUILTIN_CVTDQ2PS,
14230 IX86_BUILTIN_CVTPD2DQ,
14231 IX86_BUILTIN_CVTPD2PI,
14232 IX86_BUILTIN_CVTPD2PS,
14233 IX86_BUILTIN_CVTTPD2DQ,
14234 IX86_BUILTIN_CVTTPD2PI,
14236 IX86_BUILTIN_CVTPI2PD,
14237 IX86_BUILTIN_CVTSI2SD,
14238 IX86_BUILTIN_CVTSI642SD,
14240 IX86_BUILTIN_CVTSD2SI,
14241 IX86_BUILTIN_CVTSD2SI64,
14242 IX86_BUILTIN_CVTSD2SS,
14243 IX86_BUILTIN_CVTSS2SD,
14244 IX86_BUILTIN_CVTTSD2SI,
14245 IX86_BUILTIN_CVTTSD2SI64,
14247 IX86_BUILTIN_CVTPS2DQ,
14248 IX86_BUILTIN_CVTPS2PD,
14249 IX86_BUILTIN_CVTTPS2DQ,
14251 IX86_BUILTIN_MOVNTI,
14252 IX86_BUILTIN_MOVNTPD,
14253 IX86_BUILTIN_MOVNTDQ,
14256 IX86_BUILTIN_MASKMOVDQU,
14257 IX86_BUILTIN_MOVMSKPD,
14258 IX86_BUILTIN_PMOVMSKB128,
14260 IX86_BUILTIN_PACKSSWB128,
14261 IX86_BUILTIN_PACKSSDW128,
14262 IX86_BUILTIN_PACKUSWB128,
14264 IX86_BUILTIN_PADDB128,
14265 IX86_BUILTIN_PADDW128,
14266 IX86_BUILTIN_PADDD128,
14267 IX86_BUILTIN_PADDQ128,
14268 IX86_BUILTIN_PADDSB128,
14269 IX86_BUILTIN_PADDSW128,
14270 IX86_BUILTIN_PADDUSB128,
14271 IX86_BUILTIN_PADDUSW128,
14272 IX86_BUILTIN_PSUBB128,
14273 IX86_BUILTIN_PSUBW128,
14274 IX86_BUILTIN_PSUBD128,
14275 IX86_BUILTIN_PSUBQ128,
14276 IX86_BUILTIN_PSUBSB128,
14277 IX86_BUILTIN_PSUBSW128,
14278 IX86_BUILTIN_PSUBUSB128,
14279 IX86_BUILTIN_PSUBUSW128,
14281 IX86_BUILTIN_PAND128,
14282 IX86_BUILTIN_PANDN128,
14283 IX86_BUILTIN_POR128,
14284 IX86_BUILTIN_PXOR128,
14286 IX86_BUILTIN_PAVGB128,
14287 IX86_BUILTIN_PAVGW128,
14289 IX86_BUILTIN_PCMPEQB128,
14290 IX86_BUILTIN_PCMPEQW128,
14291 IX86_BUILTIN_PCMPEQD128,
14292 IX86_BUILTIN_PCMPGTB128,
14293 IX86_BUILTIN_PCMPGTW128,
14294 IX86_BUILTIN_PCMPGTD128,
14296 IX86_BUILTIN_PMADDWD128,
14298 IX86_BUILTIN_PMAXSW128,
14299 IX86_BUILTIN_PMAXUB128,
14300 IX86_BUILTIN_PMINSW128,
14301 IX86_BUILTIN_PMINUB128,
14303 IX86_BUILTIN_PMULUDQ,
14304 IX86_BUILTIN_PMULUDQ128,
14305 IX86_BUILTIN_PMULHUW128,
14306 IX86_BUILTIN_PMULHW128,
14307 IX86_BUILTIN_PMULLW128,
14309 IX86_BUILTIN_PSADBW128,
14310 IX86_BUILTIN_PSHUFHW,
14311 IX86_BUILTIN_PSHUFLW,
14312 IX86_BUILTIN_PSHUFD,
14314 IX86_BUILTIN_PSLLW128,
14315 IX86_BUILTIN_PSLLD128,
14316 IX86_BUILTIN_PSLLQ128,
14317 IX86_BUILTIN_PSRAW128,
14318 IX86_BUILTIN_PSRAD128,
14319 IX86_BUILTIN_PSRLW128,
14320 IX86_BUILTIN_PSRLD128,
14321 IX86_BUILTIN_PSRLQ128,
14322 IX86_BUILTIN_PSLLDQI128,
14323 IX86_BUILTIN_PSLLWI128,
14324 IX86_BUILTIN_PSLLDI128,
14325 IX86_BUILTIN_PSLLQI128,
14326 IX86_BUILTIN_PSRAWI128,
14327 IX86_BUILTIN_PSRADI128,
14328 IX86_BUILTIN_PSRLDQI128,
14329 IX86_BUILTIN_PSRLWI128,
14330 IX86_BUILTIN_PSRLDI128,
14331 IX86_BUILTIN_PSRLQI128,
14333 IX86_BUILTIN_PUNPCKHBW128,
14334 IX86_BUILTIN_PUNPCKHWD128,
14335 IX86_BUILTIN_PUNPCKHDQ128,
14336 IX86_BUILTIN_PUNPCKHQDQ128,
14337 IX86_BUILTIN_PUNPCKLBW128,
14338 IX86_BUILTIN_PUNPCKLWD128,
14339 IX86_BUILTIN_PUNPCKLDQ128,
14340 IX86_BUILTIN_PUNPCKLQDQ128,
14342 IX86_BUILTIN_CLFLUSH,
14343 IX86_BUILTIN_MFENCE,
14344 IX86_BUILTIN_LFENCE,
14346 /* Prescott New Instructions. */
14347 IX86_BUILTIN_ADDSUBPS,
14348 IX86_BUILTIN_HADDPS,
14349 IX86_BUILTIN_HSUBPS,
14350 IX86_BUILTIN_MOVSHDUP,
14351 IX86_BUILTIN_MOVSLDUP,
14352 IX86_BUILTIN_ADDSUBPD,
14353 IX86_BUILTIN_HADDPD,
14354 IX86_BUILTIN_HSUBPD,
14355 IX86_BUILTIN_LDDQU,
14357 IX86_BUILTIN_MONITOR,
14358 IX86_BUILTIN_MWAIT,
14360 IX86_BUILTIN_VEC_INIT_V2SI,
14361 IX86_BUILTIN_VEC_INIT_V4HI,
14362 IX86_BUILTIN_VEC_INIT_V8QI,
14363 IX86_BUILTIN_VEC_EXT_V2DF,
14364 IX86_BUILTIN_VEC_EXT_V2DI,
14365 IX86_BUILTIN_VEC_EXT_V4SF,
14366 IX86_BUILTIN_VEC_EXT_V4SI,
14367 IX86_BUILTIN_VEC_EXT_V8HI,
14368 IX86_BUILTIN_VEC_EXT_V2SI,
14369 IX86_BUILTIN_VEC_EXT_V4HI,
14370 IX86_BUILTIN_VEC_SET_V8HI,
14371 IX86_BUILTIN_VEC_SET_V4HI,
14376 #define def_builtin(MASK, NAME, TYPE, CODE) \
14378 if ((MASK) & target_flags \
14379 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
14380 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
14381 NULL, NULL_TREE); \
14384 /* Bits for builtin_description.flag. */
14386 /* Set when we don't support the comparison natively, and should
14387 swap_comparison in order to support it. */
14388 #define BUILTIN_DESC_SWAP_OPERANDS 1
14390 struct builtin_description
14392 const unsigned int mask;
14393 const enum insn_code icode;
14394 const char *const name;
14395 const enum ix86_builtins code;
14396 const enum rtx_code comparison;
14397 const unsigned int flag;
14400 static const struct builtin_description bdesc_comi[] =
14402 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
14403 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
14404 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
14405 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
14406 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
14407 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
14408 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
14409 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
14410 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
14411 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
14412 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
14413 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
14414 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
14415 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
14416 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
14417 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
14418 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
14419 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
14420 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
14421 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
14422 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
14423 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
14424 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
14425 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
14428 static const struct builtin_description bdesc_2arg[] =
14431 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
14432 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
14433 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
14434 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
14435 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
14436 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
14437 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
14438 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
14440 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
14441 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
14442 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
14443 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
14444 BUILTIN_DESC_SWAP_OPERANDS },
14445 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
14446 BUILTIN_DESC_SWAP_OPERANDS },
14447 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
14448 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
14449 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
14450 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
14451 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
14452 BUILTIN_DESC_SWAP_OPERANDS },
14453 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
14454 BUILTIN_DESC_SWAP_OPERANDS },
14455 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
14456 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
14457 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
14458 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
14459 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
14460 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
14461 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
14462 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
14463 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
14464 BUILTIN_DESC_SWAP_OPERANDS },
14465 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
14466 BUILTIN_DESC_SWAP_OPERANDS },
14467 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
14469 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
14470 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
14471 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
14472 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
14474 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
14475 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
14476 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
14477 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
14479 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
14480 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
14481 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
14482 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
14483 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
14486 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
14487 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
14488 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
14489 { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
14490 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
14491 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
14492 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
14493 { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
14495 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
14496 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
14497 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
14498 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
14499 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
14500 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
14501 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
14502 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
14504 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
14505 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
14506 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
14508 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
14509 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
14510 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
14511 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
14513 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
14514 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
14516 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
14517 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
14518 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
14519 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
14520 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
14521 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
14523 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
14524 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
14525 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
14526 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
14528 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
14529 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
14530 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
14531 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
14532 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
14533 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
14536 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
14537 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
14538 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
14540 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
14541 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
14542 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
14544 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
14545 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
14546 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
14547 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
14548 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
14549 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
14551 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
14552 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
14553 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
14554 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
14555 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
14556 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
14558 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
14559 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
14560 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
14561 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
14563 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
14564 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
14567 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
14568 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
14569 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
14570 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
14571 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
14572 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
14573 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
14574 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
14576 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
14577 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
14578 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
14579 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
14580 BUILTIN_DESC_SWAP_OPERANDS },
14581 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
14582 BUILTIN_DESC_SWAP_OPERANDS },
14583 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
14584 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
14585 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
14586 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
14587 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
14588 BUILTIN_DESC_SWAP_OPERANDS },
14589 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
14590 BUILTIN_DESC_SWAP_OPERANDS },
14591 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
14592 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
14593 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
14594 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
14595 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
14596 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
14597 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
14598 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
14599 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
14601 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
14602 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
14603 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
14604 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
14606 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
14607 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
14608 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
14609 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
14611 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
14612 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
14613 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
14616 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
14617 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
14618 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
14619 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
14620 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
14621 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
14622 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
14623 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
14625 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
14626 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
14627 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
14628 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
14629 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
14630 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
14631 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
14632 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
14634 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
14635 { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
14637 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
14638 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
14639 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
14640 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
14642 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
14643 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
14645 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
14646 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
14647 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
14648 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
14649 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
14650 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
14652 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
14653 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
14654 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
14655 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
14657 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
14658 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
14659 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
14660 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
14661 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
14662 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
14663 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
14664 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
14666 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
14667 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
14668 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
14670 { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
14671 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
14673 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
14674 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
14676 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
14677 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
14678 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
14680 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
14681 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
14682 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
14684 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
14685 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
14687 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
14689 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
14690 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
14691 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
14692 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
14695 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
14696 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
14697 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
14698 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
14699 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
14700 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
14703 static const struct builtin_description bdesc_1arg[] =
14705 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
14706 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
14708 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
14709 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
14710 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
14712 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
14713 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
14714 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
14715 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
14716 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
14717 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
14719 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
14720 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
14722 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
14724 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
14725 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
14727 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
14728 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
14729 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
14730 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
14731 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
14733 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
14735 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
14736 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
14737 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
14738 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
14740 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
14741 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
14742 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
14745 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
14746 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
14750 ix86_init_builtins (void)
14753 ix86_init_mmx_sse_builtins ();
14756 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
14757 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
14760 ix86_init_mmx_sse_builtins (void)
14762 const struct builtin_description * d;
14765 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
14766 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14767 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
14768 tree V2DI_type_node
14769 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
14770 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
14771 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
14772 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
14773 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14774 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14775 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
14777 tree pchar_type_node = build_pointer_type (char_type_node);
14778 tree pcchar_type_node = build_pointer_type (
14779 build_type_variant (char_type_node, 1, 0));
14780 tree pfloat_type_node = build_pointer_type (float_type_node);
14781 tree pcfloat_type_node = build_pointer_type (
14782 build_type_variant (float_type_node, 1, 0));
14783 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
14784 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
14785 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
14788 tree int_ftype_v4sf_v4sf
14789 = build_function_type_list (integer_type_node,
14790 V4SF_type_node, V4SF_type_node, NULL_TREE);
14791 tree v4si_ftype_v4sf_v4sf
14792 = build_function_type_list (V4SI_type_node,
14793 V4SF_type_node, V4SF_type_node, NULL_TREE);
14794 /* MMX/SSE/integer conversions. */
14795 tree int_ftype_v4sf
14796 = build_function_type_list (integer_type_node,
14797 V4SF_type_node, NULL_TREE);
14798 tree int64_ftype_v4sf
14799 = build_function_type_list (long_long_integer_type_node,
14800 V4SF_type_node, NULL_TREE);
14801 tree int_ftype_v8qi
14802 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
14803 tree v4sf_ftype_v4sf_int
14804 = build_function_type_list (V4SF_type_node,
14805 V4SF_type_node, integer_type_node, NULL_TREE);
14806 tree v4sf_ftype_v4sf_int64
14807 = build_function_type_list (V4SF_type_node,
14808 V4SF_type_node, long_long_integer_type_node,
14810 tree v4sf_ftype_v4sf_v2si
14811 = build_function_type_list (V4SF_type_node,
14812 V4SF_type_node, V2SI_type_node, NULL_TREE);
14814 /* Miscellaneous. */
14815 tree v8qi_ftype_v4hi_v4hi
14816 = build_function_type_list (V8QI_type_node,
14817 V4HI_type_node, V4HI_type_node, NULL_TREE);
14818 tree v4hi_ftype_v2si_v2si
14819 = build_function_type_list (V4HI_type_node,
14820 V2SI_type_node, V2SI_type_node, NULL_TREE);
14821 tree v4sf_ftype_v4sf_v4sf_int
14822 = build_function_type_list (V4SF_type_node,
14823 V4SF_type_node, V4SF_type_node,
14824 integer_type_node, NULL_TREE);
14825 tree v2si_ftype_v4hi_v4hi
14826 = build_function_type_list (V2SI_type_node,
14827 V4HI_type_node, V4HI_type_node, NULL_TREE);
14828 tree v4hi_ftype_v4hi_int
14829 = build_function_type_list (V4HI_type_node,
14830 V4HI_type_node, integer_type_node, NULL_TREE);
14831 tree v4hi_ftype_v4hi_di
14832 = build_function_type_list (V4HI_type_node,
14833 V4HI_type_node, long_long_unsigned_type_node,
14835 tree v2si_ftype_v2si_di
14836 = build_function_type_list (V2SI_type_node,
14837 V2SI_type_node, long_long_unsigned_type_node,
14839 tree void_ftype_void
14840 = build_function_type (void_type_node, void_list_node);
14841 tree void_ftype_unsigned
14842 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
14843 tree void_ftype_unsigned_unsigned
14844 = build_function_type_list (void_type_node, unsigned_type_node,
14845 unsigned_type_node, NULL_TREE);
14846 tree void_ftype_pcvoid_unsigned_unsigned
14847 = build_function_type_list (void_type_node, const_ptr_type_node,
14848 unsigned_type_node, unsigned_type_node,
14850 tree unsigned_ftype_void
14851 = build_function_type (unsigned_type_node, void_list_node);
14852 tree v2si_ftype_v4sf
14853 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
14854 /* Loads/stores. */
14855 tree void_ftype_v8qi_v8qi_pchar
14856 = build_function_type_list (void_type_node,
14857 V8QI_type_node, V8QI_type_node,
14858 pchar_type_node, NULL_TREE);
14859 tree v4sf_ftype_pcfloat
14860 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
14861 /* @@@ the type is bogus */
14862 tree v4sf_ftype_v4sf_pv2si
14863 = build_function_type_list (V4SF_type_node,
14864 V4SF_type_node, pv2si_type_node, NULL_TREE);
14865 tree void_ftype_pv2si_v4sf
14866 = build_function_type_list (void_type_node,
14867 pv2si_type_node, V4SF_type_node, NULL_TREE);
14868 tree void_ftype_pfloat_v4sf
14869 = build_function_type_list (void_type_node,
14870 pfloat_type_node, V4SF_type_node, NULL_TREE);
14871 tree void_ftype_pdi_di
14872 = build_function_type_list (void_type_node,
14873 pdi_type_node, long_long_unsigned_type_node,
14875 tree void_ftype_pv2di_v2di
14876 = build_function_type_list (void_type_node,
14877 pv2di_type_node, V2DI_type_node, NULL_TREE);
14878 /* Normal vector unops. */
14879 tree v4sf_ftype_v4sf
14880 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14882 /* Normal vector binops. */
14883 tree v4sf_ftype_v4sf_v4sf
14884 = build_function_type_list (V4SF_type_node,
14885 V4SF_type_node, V4SF_type_node, NULL_TREE);
14886 tree v8qi_ftype_v8qi_v8qi
14887 = build_function_type_list (V8QI_type_node,
14888 V8QI_type_node, V8QI_type_node, NULL_TREE);
14889 tree v4hi_ftype_v4hi_v4hi
14890 = build_function_type_list (V4HI_type_node,
14891 V4HI_type_node, V4HI_type_node, NULL_TREE);
14892 tree v2si_ftype_v2si_v2si
14893 = build_function_type_list (V2SI_type_node,
14894 V2SI_type_node, V2SI_type_node, NULL_TREE);
14895 tree di_ftype_di_di
14896 = build_function_type_list (long_long_unsigned_type_node,
14897 long_long_unsigned_type_node,
14898 long_long_unsigned_type_node, NULL_TREE);
14900 tree v2si_ftype_v2sf
14901 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
14902 tree v2sf_ftype_v2si
14903 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
14904 tree v2si_ftype_v2si
14905 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
14906 tree v2sf_ftype_v2sf
14907 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
14908 tree v2sf_ftype_v2sf_v2sf
14909 = build_function_type_list (V2SF_type_node,
14910 V2SF_type_node, V2SF_type_node, NULL_TREE);
14911 tree v2si_ftype_v2sf_v2sf
14912 = build_function_type_list (V2SI_type_node,
14913 V2SF_type_node, V2SF_type_node, NULL_TREE);
14914 tree pint_type_node = build_pointer_type (integer_type_node);
14915 tree pdouble_type_node = build_pointer_type (double_type_node);
14916 tree pcdouble_type_node = build_pointer_type (
14917 build_type_variant (double_type_node, 1, 0));
14918 tree int_ftype_v2df_v2df
14919 = build_function_type_list (integer_type_node,
14920 V2DF_type_node, V2DF_type_node, NULL_TREE);
14922 tree void_ftype_pcvoid
14923 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
14924 tree v4sf_ftype_v4si
14925 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
14926 tree v4si_ftype_v4sf
14927 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
14928 tree v2df_ftype_v4si
14929 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
14930 tree v4si_ftype_v2df
14931 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
14932 tree v2si_ftype_v2df
14933 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
14934 tree v4sf_ftype_v2df
14935 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
14936 tree v2df_ftype_v2si
14937 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
14938 tree v2df_ftype_v4sf
14939 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
14940 tree int_ftype_v2df
14941 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
14942 tree int64_ftype_v2df
14943 = build_function_type_list (long_long_integer_type_node,
14944 V2DF_type_node, NULL_TREE);
14945 tree v2df_ftype_v2df_int
14946 = build_function_type_list (V2DF_type_node,
14947 V2DF_type_node, integer_type_node, NULL_TREE);
14948 tree v2df_ftype_v2df_int64
14949 = build_function_type_list (V2DF_type_node,
14950 V2DF_type_node, long_long_integer_type_node,
14952 tree v4sf_ftype_v4sf_v2df
14953 = build_function_type_list (V4SF_type_node,
14954 V4SF_type_node, V2DF_type_node, NULL_TREE);
14955 tree v2df_ftype_v2df_v4sf
14956 = build_function_type_list (V2DF_type_node,
14957 V2DF_type_node, V4SF_type_node, NULL_TREE);
14958 tree v2df_ftype_v2df_v2df_int
14959 = build_function_type_list (V2DF_type_node,
14960 V2DF_type_node, V2DF_type_node,
14963 tree v2df_ftype_v2df_pcdouble
14964 = build_function_type_list (V2DF_type_node,
14965 V2DF_type_node, pcdouble_type_node, NULL_TREE);
14966 tree void_ftype_pdouble_v2df
14967 = build_function_type_list (void_type_node,
14968 pdouble_type_node, V2DF_type_node, NULL_TREE);
14969 tree void_ftype_pint_int
14970 = build_function_type_list (void_type_node,
14971 pint_type_node, integer_type_node, NULL_TREE);
14972 tree void_ftype_v16qi_v16qi_pchar
14973 = build_function_type_list (void_type_node,
14974 V16QI_type_node, V16QI_type_node,
14975 pchar_type_node, NULL_TREE);
14976 tree v2df_ftype_pcdouble
14977 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
14978 tree v2df_ftype_v2df_v2df
14979 = build_function_type_list (V2DF_type_node,
14980 V2DF_type_node, V2DF_type_node, NULL_TREE);
14981 tree v16qi_ftype_v16qi_v16qi
14982 = build_function_type_list (V16QI_type_node,
14983 V16QI_type_node, V16QI_type_node, NULL_TREE);
14984 tree v8hi_ftype_v8hi_v8hi
14985 = build_function_type_list (V8HI_type_node,
14986 V8HI_type_node, V8HI_type_node, NULL_TREE);
14987 tree v4si_ftype_v4si_v4si
14988 = build_function_type_list (V4SI_type_node,
14989 V4SI_type_node, V4SI_type_node, NULL_TREE);
14990 tree v2di_ftype_v2di_v2di
14991 = build_function_type_list (V2DI_type_node,
14992 V2DI_type_node, V2DI_type_node, NULL_TREE);
14993 tree v2di_ftype_v2df_v2df
14994 = build_function_type_list (V2DI_type_node,
14995 V2DF_type_node, V2DF_type_node, NULL_TREE);
14996 tree v2df_ftype_v2df
14997 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14998 tree v2di_ftype_v2di_int
14999 = build_function_type_list (V2DI_type_node,
15000 V2DI_type_node, integer_type_node, NULL_TREE);
15001 tree v4si_ftype_v4si_int
15002 = build_function_type_list (V4SI_type_node,
15003 V4SI_type_node, integer_type_node, NULL_TREE);
15004 tree v8hi_ftype_v8hi_int
15005 = build_function_type_list (V8HI_type_node,
15006 V8HI_type_node, integer_type_node, NULL_TREE);
15007 tree v8hi_ftype_v8hi_v2di
15008 = build_function_type_list (V8HI_type_node,
15009 V8HI_type_node, V2DI_type_node, NULL_TREE);
15010 tree v4si_ftype_v4si_v2di
15011 = build_function_type_list (V4SI_type_node,
15012 V4SI_type_node, V2DI_type_node, NULL_TREE);
15013 tree v4si_ftype_v8hi_v8hi
15014 = build_function_type_list (V4SI_type_node,
15015 V8HI_type_node, V8HI_type_node, NULL_TREE);
15016 tree di_ftype_v8qi_v8qi
15017 = build_function_type_list (long_long_unsigned_type_node,
15018 V8QI_type_node, V8QI_type_node, NULL_TREE);
15019 tree di_ftype_v2si_v2si
15020 = build_function_type_list (long_long_unsigned_type_node,
15021 V2SI_type_node, V2SI_type_node, NULL_TREE);
15022 tree v2di_ftype_v16qi_v16qi
15023 = build_function_type_list (V2DI_type_node,
15024 V16QI_type_node, V16QI_type_node, NULL_TREE);
15025 tree v2di_ftype_v4si_v4si
15026 = build_function_type_list (V2DI_type_node,
15027 V4SI_type_node, V4SI_type_node, NULL_TREE);
15028 tree int_ftype_v16qi
15029 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
15030 tree v16qi_ftype_pcchar
15031 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
15032 tree void_ftype_pchar_v16qi
15033 = build_function_type_list (void_type_node,
15034 pchar_type_node, V16QI_type_node, NULL_TREE);
15037 tree float128_type;
15040 /* The __float80 type. */
15041 if (TYPE_MODE (long_double_type_node) == XFmode)
15042 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
15046 /* The __float80 type. */
15047 float80_type = make_node (REAL_TYPE);
15048 TYPE_PRECISION (float80_type) = 80;
15049 layout_type (float80_type);
15050 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
15055 float128_type = make_node (REAL_TYPE);
15056 TYPE_PRECISION (float128_type) = 128;
15057 layout_type (float128_type);
15058 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
15061 /* Add all builtins that are more or less simple operations on two
15063 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15065 /* Use one of the operands; the target can have a different mode for
15066 mask-generating compares. */
15067 enum machine_mode mode;
15072 mode = insn_data[d->icode].operand[1].mode;
15077 type = v16qi_ftype_v16qi_v16qi;
15080 type = v8hi_ftype_v8hi_v8hi;
15083 type = v4si_ftype_v4si_v4si;
15086 type = v2di_ftype_v2di_v2di;
15089 type = v2df_ftype_v2df_v2df;
15092 type = v4sf_ftype_v4sf_v4sf;
15095 type = v8qi_ftype_v8qi_v8qi;
15098 type = v4hi_ftype_v4hi_v4hi;
15101 type = v2si_ftype_v2si_v2si;
15104 type = di_ftype_di_di;
15108 gcc_unreachable ();
15111 /* Override for comparisons. */
15112 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
15113 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
15114 type = v4si_ftype_v4sf_v4sf;
15116 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
15117 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15118 type = v2di_ftype_v2df_v2df;
15120 def_builtin (d->mask, d->name, type, d->code);
15123 /* Add the remaining MMX insns with somewhat more complicated types. */
15124 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
15125 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
15126 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
15127 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
15129 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
15130 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
15131 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
15133 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
15134 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
15136 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
15137 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
15139 /* comi/ucomi insns. */
15140 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
15141 if (d->mask == MASK_SSE2)
15142 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
15144 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
15146 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
15147 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
15148 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
15150 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
15151 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
15152 def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
15153 def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
15154 def_builtin (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
15155 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
15156 def_builtin (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
15157 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
15158 def_builtin (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
15159 def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
15160 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
15162 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
15164 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
15165 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
15167 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
15168 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
15169 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
15170 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
15172 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
15173 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
15174 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
15175 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
15177 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
15179 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
15181 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
15182 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
15183 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
15184 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
15185 def_builtin (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
15186 def_builtin (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
15188 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
15190 /* Original 3DNow! */
15191 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
15192 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
15193 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
15194 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
15195 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
15196 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
15197 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
15198 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
15199 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
15200 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
15201 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
15202 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
15203 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
15204 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
15205 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
15206 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
15207 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
15208 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
15209 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
15210 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
15212 /* 3DNow! extension as used in the Athlon CPU. */
15213 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
15214 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
15215 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
15216 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
15217 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
15218 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
15221 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
15223 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
15224 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
15226 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
15227 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
15229 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
15230 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
15231 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
15232 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
15233 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
15235 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
15236 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
15237 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
15238 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
15240 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
15241 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
15243 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
15245 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
15246 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
15248 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
15249 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
15250 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
15251 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
15252 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
15254 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
15256 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
15257 def_builtin (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
15258 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
15259 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
15261 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
15262 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
15263 def_builtin (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
15265 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
15266 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
15267 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
15268 def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
15270 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
15271 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
15272 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
15274 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
15275 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
15277 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
15278 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
15280 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
15281 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
15282 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
15284 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
15285 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
15286 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
15288 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
15289 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
15291 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
15292 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
15293 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
15294 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
15296 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
15297 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
15298 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
15299 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
15301 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
15302 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
15304 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
15306 /* Prescott New Instructions. */
15307 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
15308 void_ftype_pcvoid_unsigned_unsigned,
15309 IX86_BUILTIN_MONITOR);
15310 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
15311 void_ftype_unsigned_unsigned,
15312 IX86_BUILTIN_MWAIT);
15313 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
15315 IX86_BUILTIN_MOVSHDUP);
15316 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
15318 IX86_BUILTIN_MOVSLDUP);
15319 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
15320 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15322 /* Access to the vec_init patterns. */
15323 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15324 integer_type_node, NULL_TREE);
15325 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15326 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15328 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15329 short_integer_type_node,
15330 short_integer_type_node,
15331 short_integer_type_node, NULL_TREE);
15332 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
15333 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
15335 ftype = build_function_type_list (V8QI_type_node, char_type_node,
15336 char_type_node, char_type_node,
15337 char_type_node, char_type_node,
15338 char_type_node, char_type_node,
15339 char_type_node, NULL_TREE);
15340 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
15341 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
15343 /* Access to the vec_extract patterns. */
15344 ftype = build_function_type_list (double_type_node, V2DF_type_node,
15345 integer_type_node, NULL_TREE);
15346 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
15347 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
15349 ftype = build_function_type_list (long_long_integer_type_node,
15350 V2DI_type_node, integer_type_node,
15352 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
15353 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
15355 ftype = build_function_type_list (float_type_node, V4SF_type_node,
15356 integer_type_node, NULL_TREE);
15357 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
15358 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
15360 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
15361 integer_type_node, NULL_TREE);
15362 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
15363 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
15365 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
15366 integer_type_node, NULL_TREE);
15367 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
15368 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
15370 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
15371 integer_type_node, NULL_TREE);
15372 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
15373 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
15375 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
15376 integer_type_node, NULL_TREE);
15377 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
15378 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
15380 /* Access to the vec_set patterns. */
15381 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
15383 integer_type_node, NULL_TREE);
15384 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
15385 ftype, IX86_BUILTIN_VEC_SET_V8HI);
15387 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
15389 integer_type_node, NULL_TREE);
15390 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
15391 ftype, IX86_BUILTIN_VEC_SET_V4HI);
15394 /* Errors in the source file can cause expand_expr to return const0_rtx
15395 where we expect a vector. To avoid crashing, use one of the vector
15396 clear instructions. */
15398 safe_vector_operand (rtx x, enum machine_mode mode)
15400 if (x == const0_rtx)
15401 x = CONST0_RTX (mode);
15405 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
15408 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
15411 tree arg0 = TREE_VALUE (arglist);
15412 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15413 rtx op0 = expand_normal (arg0);
15414 rtx op1 = expand_normal (arg1);
15415 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15416 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15417 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
15419 if (VECTOR_MODE_P (mode0))
15420 op0 = safe_vector_operand (op0, mode0);
15421 if (VECTOR_MODE_P (mode1))
15422 op1 = safe_vector_operand (op1, mode1);
15424 if (optimize || !target
15425 || GET_MODE (target) != tmode
15426 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15427 target = gen_reg_rtx (tmode);
15429 if (GET_MODE (op1) == SImode && mode1 == TImode)
15431 rtx x = gen_reg_rtx (V4SImode);
15432 emit_insn (gen_sse2_loadd (x, op1));
15433 op1 = gen_lowpart (TImode, x);
15436 /* The insn must want input operands in the same modes as the
15438 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
15439 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
15441 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15442 op0 = copy_to_mode_reg (mode0, op0);
15443 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
15444 op1 = copy_to_mode_reg (mode1, op1);
15446 /* ??? Using ix86_fixup_binary_operands is problematic when
15447 we've got mismatched modes. Fake it. */
15453 if (tmode == mode0 && tmode == mode1)
15455 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
15459 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
15461 op0 = force_reg (mode0, op0);
15462 op1 = force_reg (mode1, op1);
15463 target = gen_reg_rtx (tmode);
15466 pat = GEN_FCN (icode) (target, op0, op1);
15473 /* Subroutine of ix86_expand_builtin to take care of stores. */
15476 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
15479 tree arg0 = TREE_VALUE (arglist);
15480 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15481 rtx op0 = expand_normal (arg0);
15482 rtx op1 = expand_normal (arg1);
15483 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
15484 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
15486 if (VECTOR_MODE_P (mode1))
15487 op1 = safe_vector_operand (op1, mode1);
15489 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15490 op1 = copy_to_mode_reg (mode1, op1);
15492 pat = GEN_FCN (icode) (op0, op1);
15498 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
15501 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
15502 rtx target, int do_load)
15505 tree arg0 = TREE_VALUE (arglist);
15506 rtx op0 = expand_normal (arg0);
15507 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15508 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15510 if (optimize || !target
15511 || GET_MODE (target) != tmode
15512 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15513 target = gen_reg_rtx (tmode);
15515 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15518 if (VECTOR_MODE_P (mode0))
15519 op0 = safe_vector_operand (op0, mode0);
15521 if ((optimize && !register_operand (op0, mode0))
15522 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15523 op0 = copy_to_mode_reg (mode0, op0);
15526 pat = GEN_FCN (icode) (target, op0);
15533 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
15534 sqrtss, rsqrtss, rcpss. */
15537 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
15540 tree arg0 = TREE_VALUE (arglist);
15541 rtx op1, op0 = expand_normal (arg0);
15542 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15543 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15545 if (optimize || !target
15546 || GET_MODE (target) != tmode
15547 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15548 target = gen_reg_rtx (tmode);
15550 if (VECTOR_MODE_P (mode0))
15551 op0 = safe_vector_operand (op0, mode0);
15553 if ((optimize && !register_operand (op0, mode0))
15554 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15555 op0 = copy_to_mode_reg (mode0, op0);
15558 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
15559 op1 = copy_to_mode_reg (mode0, op1);
15561 pat = GEN_FCN (icode) (target, op0, op1);
15568 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
15571 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
15575 tree arg0 = TREE_VALUE (arglist);
15576 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15577 rtx op0 = expand_normal (arg0);
15578 rtx op1 = expand_normal (arg1);
15580 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
15581 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
15582 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
15583 enum rtx_code comparison = d->comparison;
15585 if (VECTOR_MODE_P (mode0))
15586 op0 = safe_vector_operand (op0, mode0);
15587 if (VECTOR_MODE_P (mode1))
15588 op1 = safe_vector_operand (op1, mode1);
15590 /* Swap operands if we have a comparison that isn't available in
15592 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15594 rtx tmp = gen_reg_rtx (mode1);
15595 emit_move_insn (tmp, op1);
15600 if (optimize || !target
15601 || GET_MODE (target) != tmode
15602 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
15603 target = gen_reg_rtx (tmode);
15605 if ((optimize && !register_operand (op0, mode0))
15606 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
15607 op0 = copy_to_mode_reg (mode0, op0);
15608 if ((optimize && !register_operand (op1, mode1))
15609 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
15610 op1 = copy_to_mode_reg (mode1, op1);
15612 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15613 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
15620 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
15623 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
15627 tree arg0 = TREE_VALUE (arglist);
15628 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15629 rtx op0 = expand_normal (arg0);
15630 rtx op1 = expand_normal (arg1);
15632 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
15633 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
15634 enum rtx_code comparison = d->comparison;
15636 if (VECTOR_MODE_P (mode0))
15637 op0 = safe_vector_operand (op0, mode0);
15638 if (VECTOR_MODE_P (mode1))
15639 op1 = safe_vector_operand (op1, mode1);
15641 /* Swap operands if we have a comparison that isn't available in
15643 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15650 target = gen_reg_rtx (SImode);
15651 emit_move_insn (target, const0_rtx);
15652 target = gen_rtx_SUBREG (QImode, target, 0);
15654 if ((optimize && !register_operand (op0, mode0))
15655 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15656 op0 = copy_to_mode_reg (mode0, op0);
15657 if ((optimize && !register_operand (op1, mode1))
15658 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15659 op1 = copy_to_mode_reg (mode1, op1);
15661 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15662 pat = GEN_FCN (d->icode) (op0, op1);
15666 emit_insn (gen_rtx_SET (VOIDmode,
15667 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
15668 gen_rtx_fmt_ee (comparison, QImode,
15672 return SUBREG_REG (target);
15675 /* Return the integer constant in ARG. Constrain it to be in the range
15676 of the subparts of VEC_TYPE; issue an error if not. */
15679 get_element_number (tree vec_type, tree arg)
15681 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15683 if (!host_integerp (arg, 1)
15684 || (elt = tree_low_cst (arg, 1), elt > max))
15686 error ("selector must be an integer constant in the range 0..%wi", max);
15693 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15694 ix86_expand_vector_init. We DO have language-level syntax for this, in
15695 the form of (type){ init-list }. Except that since we can't place emms
15696 instructions from inside the compiler, we can't allow the use of MMX
15697 registers unless the user explicitly asks for it. So we do *not* define
15698 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
15699 we have builtins invoked by mmintrin.h that gives us license to emit
15700 these sorts of instructions. */
15703 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
15705 enum machine_mode tmode = TYPE_MODE (type);
15706 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
15707 int i, n_elt = GET_MODE_NUNITS (tmode);
15708 rtvec v = rtvec_alloc (n_elt);
15710 gcc_assert (VECTOR_MODE_P (tmode));
15712 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
15714 rtx x = expand_normal (TREE_VALUE (arglist));
15715 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15718 gcc_assert (arglist == NULL);
15720 if (!target || !register_operand (target, tmode))
15721 target = gen_reg_rtx (tmode);
15723 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
15727 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15728 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
15729 had a language-level syntax for referencing vector elements. */
15732 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
15734 enum machine_mode tmode, mode0;
15739 arg0 = TREE_VALUE (arglist);
15740 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15742 op0 = expand_normal (arg0);
15743 elt = get_element_number (TREE_TYPE (arg0), arg1);
15745 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15746 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15747 gcc_assert (VECTOR_MODE_P (mode0));
15749 op0 = force_reg (mode0, op0);
15751 if (optimize || !target || !register_operand (target, tmode))
15752 target = gen_reg_rtx (tmode);
15754 ix86_expand_vector_extract (true, target, op0, elt);
15759 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15760 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
15761 a language-level syntax for referencing vector elements. */
15764 ix86_expand_vec_set_builtin (tree arglist)
15766 enum machine_mode tmode, mode1;
15767 tree arg0, arg1, arg2;
15771 arg0 = TREE_VALUE (arglist);
15772 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15773 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15775 tmode = TYPE_MODE (TREE_TYPE (arg0));
15776 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15777 gcc_assert (VECTOR_MODE_P (tmode));
15779 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
15780 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
15781 elt = get_element_number (TREE_TYPE (arg0), arg2);
15783 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15784 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15786 op0 = force_reg (tmode, op0);
15787 op1 = force_reg (mode1, op1);
15789 ix86_expand_vector_set (true, op0, op1, elt);
15794 /* Expand an expression EXP that calls a built-in function,
15795 with result going to TARGET if that's convenient
15796 (and in mode MODE if that's convenient).
15797 SUBTARGET may be used as the target for computing one of EXP's operands.
15798 IGNORE is nonzero if the value is to be ignored. */
15801 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15802 enum machine_mode mode ATTRIBUTE_UNUSED,
15803 int ignore ATTRIBUTE_UNUSED)
15805 const struct builtin_description *d;
15807 enum insn_code icode;
15808 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
15809 tree arglist = TREE_OPERAND (exp, 1);
15810 tree arg0, arg1, arg2;
15811 rtx op0, op1, op2, pat;
15812 enum machine_mode tmode, mode0, mode1, mode2;
15813 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15817 case IX86_BUILTIN_EMMS:
15818 emit_insn (gen_mmx_emms ());
15821 case IX86_BUILTIN_SFENCE:
15822 emit_insn (gen_sse_sfence ());
15825 case IX86_BUILTIN_MASKMOVQ:
15826 case IX86_BUILTIN_MASKMOVDQU:
15827 icode = (fcode == IX86_BUILTIN_MASKMOVQ
15828 ? CODE_FOR_mmx_maskmovq
15829 : CODE_FOR_sse2_maskmovdqu);
15830 /* Note the arg order is different from the operand order. */
15831 arg1 = TREE_VALUE (arglist);
15832 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
15833 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15834 op0 = expand_normal (arg0);
15835 op1 = expand_normal (arg1);
15836 op2 = expand_normal (arg2);
15837 mode0 = insn_data[icode].operand[0].mode;
15838 mode1 = insn_data[icode].operand[1].mode;
15839 mode2 = insn_data[icode].operand[2].mode;
15841 op0 = force_reg (Pmode, op0);
15842 op0 = gen_rtx_MEM (mode1, op0);
15844 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15845 op0 = copy_to_mode_reg (mode0, op0);
15846 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15847 op1 = copy_to_mode_reg (mode1, op1);
15848 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
15849 op2 = copy_to_mode_reg (mode2, op2);
15850 pat = GEN_FCN (icode) (op0, op1, op2);
15856 case IX86_BUILTIN_SQRTSS:
15857 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
15858 case IX86_BUILTIN_RSQRTSS:
15859 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
15860 case IX86_BUILTIN_RCPSS:
15861 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
15863 case IX86_BUILTIN_LOADUPS:
15864 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
15866 case IX86_BUILTIN_STOREUPS:
15867 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
15869 case IX86_BUILTIN_LOADHPS:
15870 case IX86_BUILTIN_LOADLPS:
15871 case IX86_BUILTIN_LOADHPD:
15872 case IX86_BUILTIN_LOADLPD:
15873 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
15874 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
15875 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
15876 : CODE_FOR_sse2_loadlpd);
15877 arg0 = TREE_VALUE (arglist);
15878 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15879 op0 = expand_normal (arg0);
15880 op1 = expand_normal (arg1);
15881 tmode = insn_data[icode].operand[0].mode;
15882 mode0 = insn_data[icode].operand[1].mode;
15883 mode1 = insn_data[icode].operand[2].mode;
15885 op0 = force_reg (mode0, op0);
15886 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
15887 if (optimize || target == 0
15888 || GET_MODE (target) != tmode
15889 || !register_operand (target, tmode))
15890 target = gen_reg_rtx (tmode);
15891 pat = GEN_FCN (icode) (target, op0, op1);
15897 case IX86_BUILTIN_STOREHPS:
15898 case IX86_BUILTIN_STORELPS:
15899 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
15900 : CODE_FOR_sse_storelps);
15901 arg0 = TREE_VALUE (arglist);
15902 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15903 op0 = expand_normal (arg0);
15904 op1 = expand_normal (arg1);
15905 mode0 = insn_data[icode].operand[0].mode;
15906 mode1 = insn_data[icode].operand[1].mode;
15908 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15909 op1 = force_reg (mode1, op1);
15911 pat = GEN_FCN (icode) (op0, op1);
15917 case IX86_BUILTIN_MOVNTPS:
15918 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
15919 case IX86_BUILTIN_MOVNTQ:
15920 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
15922 case IX86_BUILTIN_LDMXCSR:
15923 op0 = expand_normal (TREE_VALUE (arglist));
15924 target = assign_386_stack_local (SImode, SLOT_TEMP);
15925 emit_move_insn (target, op0);
15926 emit_insn (gen_sse_ldmxcsr (target));
15929 case IX86_BUILTIN_STMXCSR:
15930 target = assign_386_stack_local (SImode, SLOT_TEMP);
15931 emit_insn (gen_sse_stmxcsr (target));
15932 return copy_to_mode_reg (SImode, target);
15934 case IX86_BUILTIN_SHUFPS:
15935 case IX86_BUILTIN_SHUFPD:
15936 icode = (fcode == IX86_BUILTIN_SHUFPS
15937 ? CODE_FOR_sse_shufps
15938 : CODE_FOR_sse2_shufpd);
15939 arg0 = TREE_VALUE (arglist);
15940 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15941 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15942 op0 = expand_normal (arg0);
15943 op1 = expand_normal (arg1);
15944 op2 = expand_normal (arg2);
15945 tmode = insn_data[icode].operand[0].mode;
15946 mode0 = insn_data[icode].operand[1].mode;
15947 mode1 = insn_data[icode].operand[2].mode;
15948 mode2 = insn_data[icode].operand[3].mode;
15950 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15951 op0 = copy_to_mode_reg (mode0, op0);
15952 if ((optimize && !register_operand (op1, mode1))
15953 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
15954 op1 = copy_to_mode_reg (mode1, op1);
15955 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15957 /* @@@ better error message */
15958 error ("mask must be an immediate");
15959 return gen_reg_rtx (tmode);
15961 if (optimize || target == 0
15962 || GET_MODE (target) != tmode
15963 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15964 target = gen_reg_rtx (tmode);
15965 pat = GEN_FCN (icode) (target, op0, op1, op2);
15971 case IX86_BUILTIN_PSHUFW:
15972 case IX86_BUILTIN_PSHUFD:
15973 case IX86_BUILTIN_PSHUFHW:
15974 case IX86_BUILTIN_PSHUFLW:
15975 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
15976 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
15977 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
15978 : CODE_FOR_mmx_pshufw);
15979 arg0 = TREE_VALUE (arglist);
15980 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15981 op0 = expand_normal (arg0);
15982 op1 = expand_normal (arg1);
15983 tmode = insn_data[icode].operand[0].mode;
15984 mode1 = insn_data[icode].operand[1].mode;
15985 mode2 = insn_data[icode].operand[2].mode;
15987 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15988 op0 = copy_to_mode_reg (mode1, op0);
15989 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15991 /* @@@ better error message */
15992 error ("mask must be an immediate");
15996 || GET_MODE (target) != tmode
15997 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15998 target = gen_reg_rtx (tmode);
15999 pat = GEN_FCN (icode) (target, op0, op1);
16005 case IX86_BUILTIN_PSLLDQI128:
16006 case IX86_BUILTIN_PSRLDQI128:
16007 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
16008 : CODE_FOR_sse2_lshrti3);
16009 arg0 = TREE_VALUE (arglist);
16010 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16011 op0 = expand_normal (arg0);
16012 op1 = expand_normal (arg1);
16013 tmode = insn_data[icode].operand[0].mode;
16014 mode1 = insn_data[icode].operand[1].mode;
16015 mode2 = insn_data[icode].operand[2].mode;
16017 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
16019 op0 = copy_to_reg (op0);
16020 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
16022 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
16024 error ("shift must be an immediate");
16027 target = gen_reg_rtx (V2DImode);
16028 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
16034 case IX86_BUILTIN_FEMMS:
16035 emit_insn (gen_mmx_femms ());
16038 case IX86_BUILTIN_PAVGUSB:
16039 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
16041 case IX86_BUILTIN_PF2ID:
16042 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
16044 case IX86_BUILTIN_PFACC:
16045 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
16047 case IX86_BUILTIN_PFADD:
16048 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
16050 case IX86_BUILTIN_PFCMPEQ:
16051 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
16053 case IX86_BUILTIN_PFCMPGE:
16054 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
16056 case IX86_BUILTIN_PFCMPGT:
16057 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
16059 case IX86_BUILTIN_PFMAX:
16060 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
16062 case IX86_BUILTIN_PFMIN:
16063 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
16065 case IX86_BUILTIN_PFMUL:
16066 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
16068 case IX86_BUILTIN_PFRCP:
16069 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
16071 case IX86_BUILTIN_PFRCPIT1:
16072 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
16074 case IX86_BUILTIN_PFRCPIT2:
16075 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
16077 case IX86_BUILTIN_PFRSQIT1:
16078 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
16080 case IX86_BUILTIN_PFRSQRT:
16081 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
16083 case IX86_BUILTIN_PFSUB:
16084 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
16086 case IX86_BUILTIN_PFSUBR:
16087 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
16089 case IX86_BUILTIN_PI2FD:
16090 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
16092 case IX86_BUILTIN_PMULHRW:
16093 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
16095 case IX86_BUILTIN_PF2IW:
16096 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
16098 case IX86_BUILTIN_PFNACC:
16099 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
16101 case IX86_BUILTIN_PFPNACC:
16102 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
16104 case IX86_BUILTIN_PI2FW:
16105 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
16107 case IX86_BUILTIN_PSWAPDSI:
16108 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
16110 case IX86_BUILTIN_PSWAPDSF:
16111 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
16113 case IX86_BUILTIN_SQRTSD:
16114 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
16115 case IX86_BUILTIN_LOADUPD:
16116 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
16117 case IX86_BUILTIN_STOREUPD:
16118 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
16120 case IX86_BUILTIN_MFENCE:
16121 emit_insn (gen_sse2_mfence ());
16123 case IX86_BUILTIN_LFENCE:
16124 emit_insn (gen_sse2_lfence ());
16127 case IX86_BUILTIN_CLFLUSH:
16128 arg0 = TREE_VALUE (arglist);
16129 op0 = expand_normal (arg0);
16130 icode = CODE_FOR_sse2_clflush;
16131 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
16132 op0 = copy_to_mode_reg (Pmode, op0);
16134 emit_insn (gen_sse2_clflush (op0));
16137 case IX86_BUILTIN_MOVNTPD:
16138 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
16139 case IX86_BUILTIN_MOVNTDQ:
16140 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
16141 case IX86_BUILTIN_MOVNTI:
16142 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
16144 case IX86_BUILTIN_LOADDQU:
16145 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
16146 case IX86_BUILTIN_STOREDQU:
16147 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
16149 case IX86_BUILTIN_MONITOR:
16150 arg0 = TREE_VALUE (arglist);
16151 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16152 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
16153 op0 = expand_normal (arg0);
16154 op1 = expand_normal (arg1);
16155 op2 = expand_normal (arg2);
16157 op0 = copy_to_mode_reg (Pmode, op0);
16159 op1 = copy_to_mode_reg (SImode, op1);
16161 op2 = copy_to_mode_reg (SImode, op2);
16163 emit_insn (gen_sse3_monitor (op0, op1, op2));
16165 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
16168 case IX86_BUILTIN_MWAIT:
16169 arg0 = TREE_VALUE (arglist);
16170 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16171 op0 = expand_normal (arg0);
16172 op1 = expand_normal (arg1);
16174 op0 = copy_to_mode_reg (SImode, op0);
16176 op1 = copy_to_mode_reg (SImode, op1);
16177 emit_insn (gen_sse3_mwait (op0, op1));
16180 case IX86_BUILTIN_LDDQU:
16181 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
16184 case IX86_BUILTIN_VEC_INIT_V2SI:
16185 case IX86_BUILTIN_VEC_INIT_V4HI:
16186 case IX86_BUILTIN_VEC_INIT_V8QI:
16187 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16189 case IX86_BUILTIN_VEC_EXT_V2DF:
16190 case IX86_BUILTIN_VEC_EXT_V2DI:
16191 case IX86_BUILTIN_VEC_EXT_V4SF:
16192 case IX86_BUILTIN_VEC_EXT_V4SI:
16193 case IX86_BUILTIN_VEC_EXT_V8HI:
16194 case IX86_BUILTIN_VEC_EXT_V2SI:
16195 case IX86_BUILTIN_VEC_EXT_V4HI:
16196 return ix86_expand_vec_ext_builtin (arglist, target);
16198 case IX86_BUILTIN_VEC_SET_V8HI:
16199 case IX86_BUILTIN_VEC_SET_V4HI:
16200 return ix86_expand_vec_set_builtin (arglist);
16206 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16207 if (d->code == fcode)
16209 /* Compares are treated specially. */
16210 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
16211 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
16212 || d->icode == CODE_FOR_sse2_maskcmpv2df3
16213 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
16214 return ix86_expand_sse_compare (d, arglist, target);
16216 return ix86_expand_binop_builtin (d->icode, arglist, target);
16219 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16220 if (d->code == fcode)
16221 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
16223 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
16224 if (d->code == fcode)
16225 return ix86_expand_sse_comi (d, arglist, target);
16227 gcc_unreachable ();
16230 /* Store OPERAND to the memory after reload is completed. This means
16231 that we can't easily use assign_stack_local. */
16233 ix86_force_to_memory (enum machine_mode mode, rtx operand)
16237 gcc_assert (reload_completed);
16238 if (TARGET_RED_ZONE)
16240 result = gen_rtx_MEM (mode,
16241 gen_rtx_PLUS (Pmode,
16243 GEN_INT (-RED_ZONE_SIZE)));
16244 emit_move_insn (result, operand);
16246 else if (!TARGET_RED_ZONE && TARGET_64BIT)
16252 operand = gen_lowpart (DImode, operand);
16256 gen_rtx_SET (VOIDmode,
16257 gen_rtx_MEM (DImode,
16258 gen_rtx_PRE_DEC (DImode,
16259 stack_pointer_rtx)),
16263 gcc_unreachable ();
16265 result = gen_rtx_MEM (mode, stack_pointer_rtx);
16274 split_di (&operand, 1, operands, operands + 1);
16276 gen_rtx_SET (VOIDmode,
16277 gen_rtx_MEM (SImode,
16278 gen_rtx_PRE_DEC (Pmode,
16279 stack_pointer_rtx)),
16282 gen_rtx_SET (VOIDmode,
16283 gen_rtx_MEM (SImode,
16284 gen_rtx_PRE_DEC (Pmode,
16285 stack_pointer_rtx)),
16290 /* Store HImodes as SImodes. */
16291 operand = gen_lowpart (SImode, operand);
16295 gen_rtx_SET (VOIDmode,
16296 gen_rtx_MEM (GET_MODE (operand),
16297 gen_rtx_PRE_DEC (SImode,
16298 stack_pointer_rtx)),
16302 gcc_unreachable ();
16304 result = gen_rtx_MEM (mode, stack_pointer_rtx);
16309 /* Free operand from the memory. */
16311 ix86_free_from_memory (enum machine_mode mode)
16313 if (!TARGET_RED_ZONE)
16317 if (mode == DImode || TARGET_64BIT)
16321 /* Use LEA to deallocate stack space. In peephole2 it will be converted
16322 to pop or add instruction if registers are available. */
16323 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
16324 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
16329 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
16330 QImode must go into class Q_REGS.
16331 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
16332 movdf to do mem-to-mem moves through integer regs. */
16334 ix86_preferred_reload_class (rtx x, enum reg_class class)
16336 enum machine_mode mode = GET_MODE (x);
16338 /* We're only allowed to return a subclass of CLASS. Many of the
16339 following checks fail for NO_REGS, so eliminate that early. */
16340 if (class == NO_REGS)
16343 /* All classes can load zeros. */
16344 if (x == CONST0_RTX (mode))
16347 /* Force constants into memory if we are loading a (nonzero) constant into
16348 an MMX or SSE register. This is because there are no MMX/SSE instructions
16349 to load from a constant. */
16351 && (MAYBE_MMX_CLASS_P (class) || MAYBE_SSE_CLASS_P (class)))
16354 /* Prefer SSE regs only, if we can use them for math. */
16355 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
16356 return SSE_CLASS_P (class) ? class : NO_REGS;
16358 /* Floating-point constants need more complex checks. */
16359 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
16361 /* General regs can load everything. */
16362 if (reg_class_subset_p (class, GENERAL_REGS))
16365 /* Floats can load 0 and 1 plus some others. Note that we eliminated
16366 zero above. We only want to wind up preferring 80387 registers if
16367 we plan on doing computation with them. */
16369 && standard_80387_constant_p (x))
16371 /* Limit class to non-sse. */
16372 if (class == FLOAT_SSE_REGS)
16374 if (class == FP_TOP_SSE_REGS)
16376 if (class == FP_SECOND_SSE_REGS)
16377 return FP_SECOND_REG;
16378 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
16385 /* Generally when we see PLUS here, it's the function invariant
16386 (plus soft-fp const_int). Which can only be computed into general
16388 if (GET_CODE (x) == PLUS)
16389 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
16391 /* QImode constants are easy to load, but non-constant QImode data
16392 must go into Q_REGS. */
16393 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
16395 if (reg_class_subset_p (class, Q_REGS))
16397 if (reg_class_subset_p (Q_REGS, class))
16405 /* Discourage putting floating-point values in SSE registers unless
16406 SSE math is being used, and likewise for the 387 registers. */
16408 ix86_preferred_output_reload_class (rtx x, enum reg_class class)
16410 enum machine_mode mode = GET_MODE (x);
16412 /* Restrict the output reload class to the register bank that we are doing
16413 math on. If we would like not to return a subset of CLASS, reject this
16414 alternative: if reload cannot do this, it will still use its choice. */
16415 mode = GET_MODE (x);
16416 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
16417 return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS;
16419 if (TARGET_80387 && SCALAR_FLOAT_MODE_P (mode))
16421 if (class == FP_TOP_SSE_REGS)
16423 else if (class == FP_SECOND_SSE_REGS)
16424 return FP_SECOND_REG;
16426 return FLOAT_CLASS_P (class) ? class : NO_REGS;
16432 /* If we are copying between general and FP registers, we need a memory
16433 location. The same is true for SSE and MMX registers.
16435 The macro can't work reliably when one of the CLASSES is class containing
16436 registers from multiple units (SSE, MMX, integer). We avoid this by never
16437 combining those units in single alternative in the machine description.
16438 Ensure that this constraint holds to avoid unexpected surprises.
16440 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
16441 enforce these sanity checks. */
16444 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
16445 enum machine_mode mode, int strict)
16447 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
16448 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
16449 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
16450 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
16451 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
16452 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
16454 gcc_assert (!strict);
16458 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
16461 /* ??? This is a lie. We do have moves between mmx/general, and for
16462 mmx/sse2. But by saying we need secondary memory we discourage the
16463 register allocator from using the mmx registers unless needed. */
16464 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
16467 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
16469 /* SSE1 doesn't have any direct moves from other classes. */
16473 /* If the target says that inter-unit moves are more expensive
16474 than moving through memory, then don't generate them. */
16475 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
16478 /* Between SSE and general, we have moves no larger than word size. */
16479 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
16482 /* ??? For the cost of one register reformat penalty, we could use
16483 the same instructions to move SFmode and DFmode data, but the
16484 relevant move patterns don't support those alternatives. */
16485 if (mode == SFmode || mode == DFmode)
16492 /* Return true if the registers in CLASS cannot represent the change from
16493 modes FROM to TO. */
16496 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
16497 enum reg_class class)
16502 /* x87 registers can't do subreg at all, as all values are reformatted
16503 to extended precision. */
16504 if (MAYBE_FLOAT_CLASS_P (class))
16507 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
16509 /* Vector registers do not support QI or HImode loads. If we don't
16510 disallow a change to these modes, reload will assume it's ok to
16511 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
16512 the vec_dupv4hi pattern. */
16513 if (GET_MODE_SIZE (from) < 4)
16516 /* Vector registers do not support subreg with nonzero offsets, which
16517 are otherwise valid for integer registers. Since we can't see
16518 whether we have a nonzero offset from here, prohibit all
16519 nonparadoxical subregs changing size. */
16520 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
16527 /* Return the cost of moving data from a register in class CLASS1 to
16528 one in class CLASS2.
16530 It is not required that the cost always equal 2 when FROM is the same as TO;
16531 on some machines it is expensive to move between registers if they are not
16532 general registers. */
16535 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
16536 enum reg_class class2)
16538 /* In case we require secondary memory, compute cost of the store followed
16539 by load. In order to avoid bad register allocation choices, we need
16540 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
16542 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
16546 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
16547 MEMORY_MOVE_COST (mode, class1, 1));
16548 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
16549 MEMORY_MOVE_COST (mode, class2, 1));
16551 /* In case of copying from general_purpose_register we may emit multiple
16552 stores followed by single load causing memory size mismatch stall.
16553 Count this as arbitrarily high cost of 20. */
16554 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
16557 /* In the case of FP/MMX moves, the registers actually overlap, and we
16558 have to switch modes in order to treat them differently. */
16559 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
16560 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
16566 /* Moves between SSE/MMX and integer unit are expensive. */
16567 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
16568 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
16569 return ix86_cost->mmxsse_to_integer;
16570 if (MAYBE_FLOAT_CLASS_P (class1))
16571 return ix86_cost->fp_move;
16572 if (MAYBE_SSE_CLASS_P (class1))
16573 return ix86_cost->sse_move;
16574 if (MAYBE_MMX_CLASS_P (class1))
16575 return ix86_cost->mmx_move;
16579 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
16582 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
16584 /* Flags and only flags can only hold CCmode values. */
16585 if (CC_REGNO_P (regno))
16586 return GET_MODE_CLASS (mode) == MODE_CC;
16587 if (GET_MODE_CLASS (mode) == MODE_CC
16588 || GET_MODE_CLASS (mode) == MODE_RANDOM
16589 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
16591 if (FP_REGNO_P (regno))
16592 return VALID_FP_MODE_P (mode);
16593 if (SSE_REGNO_P (regno))
16595 /* We implement the move patterns for all vector modes into and
16596 out of SSE registers, even when no operation instructions
16598 return (VALID_SSE_REG_MODE (mode)
16599 || VALID_SSE2_REG_MODE (mode)
16600 || VALID_MMX_REG_MODE (mode)
16601 || VALID_MMX_REG_MODE_3DNOW (mode));
16603 if (MMX_REGNO_P (regno))
16605 /* We implement the move patterns for 3DNOW modes even in MMX mode,
16606 so if the register is available at all, then we can move data of
16607 the given mode into or out of it. */
16608 return (VALID_MMX_REG_MODE (mode)
16609 || VALID_MMX_REG_MODE_3DNOW (mode));
16612 if (mode == QImode)
16614 /* Take care for QImode values - they can be in non-QI regs,
16615 but then they do cause partial register stalls. */
16616 if (regno < 4 || TARGET_64BIT)
16618 if (!TARGET_PARTIAL_REG_STALL)
16620 return reload_in_progress || reload_completed;
16622 /* We handle both integer and floats in the general purpose registers. */
16623 else if (VALID_INT_MODE_P (mode))
16625 else if (VALID_FP_MODE_P (mode))
16627 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
16628 on to use that value in smaller contexts, this can easily force a
16629 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
16630 supporting DImode, allow it. */
16631 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
16637 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
16638 tieable integer mode. */
16641 ix86_tieable_integer_mode_p (enum machine_mode mode)
16650 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
16653 return TARGET_64BIT;
16660 /* Return true if MODE1 is accessible in a register that can hold MODE2
16661 without copying. That is, all register classes that can hold MODE2
16662 can also hold MODE1. */
16665 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
16667 if (mode1 == mode2)
16670 if (ix86_tieable_integer_mode_p (mode1)
16671 && ix86_tieable_integer_mode_p (mode2))
16674 /* MODE2 being XFmode implies fp stack or general regs, which means we
16675 can tie any smaller floating point modes to it. Note that we do not
16676 tie this with TFmode. */
16677 if (mode2 == XFmode)
16678 return mode1 == SFmode || mode1 == DFmode;
16680 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
16681 that we can tie it with SFmode. */
16682 if (mode2 == DFmode)
16683 return mode1 == SFmode;
16685 /* If MODE2 is only appropriate for an SSE register, then tie with
16686 any other mode acceptable to SSE registers. */
16687 if (GET_MODE_SIZE (mode2) >= 8
16688 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
16689 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
16691 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
16692 with any other mode acceptable to MMX registers. */
16693 if (GET_MODE_SIZE (mode2) == 8
16694 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
16695 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
16700 /* Return the cost of moving data of mode M between a
16701 register and memory. A value of 2 is the default; this cost is
16702 relative to those in `REGISTER_MOVE_COST'.
16704 If moving between registers and memory is more expensive than
16705 between two registers, you should define this macro to express the
16708 Model also increased moving costs of QImode registers in non
16712 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
16714 if (FLOAT_CLASS_P (class))
16731 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
16733 if (SSE_CLASS_P (class))
16736 switch (GET_MODE_SIZE (mode))
16750 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
16752 if (MMX_CLASS_P (class))
16755 switch (GET_MODE_SIZE (mode))
16766 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
16768 switch (GET_MODE_SIZE (mode))
16772 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
16773 : ix86_cost->movzbl_load);
16775 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
16776 : ix86_cost->int_store[0] + 4);
16779 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
16781 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
16782 if (mode == TFmode)
16784 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
16785 * (((int) GET_MODE_SIZE (mode)
16786 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
16790 /* Compute a (partial) cost for rtx X. Return true if the complete
16791 cost has been computed, and false if subexpressions should be
16792 scanned. In either case, *TOTAL contains the cost result. */
16795 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
16797 enum machine_mode mode = GET_MODE (x);
16805 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
16807 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
16809 else if (flag_pic && SYMBOLIC_CONST (x)
16811 || (!GET_CODE (x) != LABEL_REF
16812 && (GET_CODE (x) != SYMBOL_REF
16813 || !SYMBOL_REF_LOCAL_P (x)))))
16820 if (mode == VOIDmode)
16823 switch (standard_80387_constant_p (x))
16828 default: /* Other constants */
16833 /* Start with (MEM (SYMBOL_REF)), since that's where
16834 it'll probably end up. Add a penalty for size. */
16835 *total = (COSTS_N_INSNS (1)
16836 + (flag_pic != 0 && !TARGET_64BIT)
16837 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
16843 /* The zero extensions is often completely free on x86_64, so make
16844 it as cheap as possible. */
16845 if (TARGET_64BIT && mode == DImode
16846 && GET_MODE (XEXP (x, 0)) == SImode)
16848 else if (TARGET_ZERO_EXTEND_WITH_AND)
16849 *total = ix86_cost->add;
16851 *total = ix86_cost->movzx;
16855 *total = ix86_cost->movsx;
16859 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16860 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
16862 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16865 *total = ix86_cost->add;
16868 if ((value == 2 || value == 3)
16869 && ix86_cost->lea <= ix86_cost->shift_const)
16871 *total = ix86_cost->lea;
16881 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
16883 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16885 if (INTVAL (XEXP (x, 1)) > 32)
16886 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
16888 *total = ix86_cost->shift_const * 2;
16892 if (GET_CODE (XEXP (x, 1)) == AND)
16893 *total = ix86_cost->shift_var * 2;
16895 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
16900 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16901 *total = ix86_cost->shift_const;
16903 *total = ix86_cost->shift_var;
16908 if (FLOAT_MODE_P (mode))
16910 *total = ix86_cost->fmul;
16915 rtx op0 = XEXP (x, 0);
16916 rtx op1 = XEXP (x, 1);
16918 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16920 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16921 for (nbits = 0; value != 0; value &= value - 1)
16925 /* This is arbitrary. */
16928 /* Compute costs correctly for widening multiplication. */
16929 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
16930 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
16931 == GET_MODE_SIZE (mode))
16933 int is_mulwiden = 0;
16934 enum machine_mode inner_mode = GET_MODE (op0);
16936 if (GET_CODE (op0) == GET_CODE (op1))
16937 is_mulwiden = 1, op1 = XEXP (op1, 0);
16938 else if (GET_CODE (op1) == CONST_INT)
16940 if (GET_CODE (op0) == SIGN_EXTEND)
16941 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
16944 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
16948 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
16951 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
16952 + nbits * ix86_cost->mult_bit
16953 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
16962 if (FLOAT_MODE_P (mode))
16963 *total = ix86_cost->fdiv;
16965 *total = ix86_cost->divide[MODE_INDEX (mode)];
16969 if (FLOAT_MODE_P (mode))
16970 *total = ix86_cost->fadd;
16971 else if (GET_MODE_CLASS (mode) == MODE_INT
16972 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
16974 if (GET_CODE (XEXP (x, 0)) == PLUS
16975 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
16976 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
16977 && CONSTANT_P (XEXP (x, 1)))
16979 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
16980 if (val == 2 || val == 4 || val == 8)
16982 *total = ix86_cost->lea;
16983 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16984 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
16986 *total += rtx_cost (XEXP (x, 1), outer_code);
16990 else if (GET_CODE (XEXP (x, 0)) == MULT
16991 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
16993 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
16994 if (val == 2 || val == 4 || val == 8)
16996 *total = ix86_cost->lea;
16997 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16998 *total += rtx_cost (XEXP (x, 1), outer_code);
17002 else if (GET_CODE (XEXP (x, 0)) == PLUS)
17004 *total = ix86_cost->lea;
17005 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
17006 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
17007 *total += rtx_cost (XEXP (x, 1), outer_code);
17014 if (FLOAT_MODE_P (mode))
17016 *total = ix86_cost->fadd;
17024 if (!TARGET_64BIT && mode == DImode)
17026 *total = (ix86_cost->add * 2
17027 + (rtx_cost (XEXP (x, 0), outer_code)
17028 << (GET_MODE (XEXP (x, 0)) != DImode))
17029 + (rtx_cost (XEXP (x, 1), outer_code)
17030 << (GET_MODE (XEXP (x, 1)) != DImode)));
17036 if (FLOAT_MODE_P (mode))
17038 *total = ix86_cost->fchs;
17044 if (!TARGET_64BIT && mode == DImode)
17045 *total = ix86_cost->add * 2;
17047 *total = ix86_cost->add;
17051 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
17052 && XEXP (XEXP (x, 0), 1) == const1_rtx
17053 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
17054 && XEXP (x, 1) == const0_rtx)
17056 /* This kind of construct is implemented using test[bwl].
17057 Treat it as if we had an AND. */
17058 *total = (ix86_cost->add
17059 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
17060 + rtx_cost (const1_rtx, outer_code));
17066 if (!TARGET_SSE_MATH
17068 || (mode == DFmode && !TARGET_SSE2))
17069 /* For standard 80387 constants, raise the cost to prevent
17070 compress_float_constant() to generate load from memory. */
17071 switch (standard_80387_constant_p (XEXP (x, 0)))
17081 *total = (x86_ext_80387_constants & TUNEMASK
17088 if (FLOAT_MODE_P (mode))
17089 *total = ix86_cost->fabs;
17093 if (FLOAT_MODE_P (mode))
17094 *total = ix86_cost->fsqrt;
17098 if (XINT (x, 1) == UNSPEC_TP)
17109 static int current_machopic_label_num;
17111 /* Given a symbol name and its associated stub, write out the
17112 definition of the stub. */
17115 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17117 unsigned int length;
17118 char *binder_name, *symbol_name, lazy_ptr_name[32];
17119 int label = ++current_machopic_label_num;
17121 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17122 symb = (*targetm.strip_name_encoding) (symb);
17124 length = strlen (stub);
17125 binder_name = alloca (length + 32);
17126 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
17128 length = strlen (symb);
17129 symbol_name = alloca (length + 32);
17130 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17132 sprintf (lazy_ptr_name, "L%d$lz", label);
17135 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
17137 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
17139 fprintf (file, "%s:\n", stub);
17140 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17144 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
17145 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
17146 fprintf (file, "\tjmp\t*%%edx\n");
17149 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
17151 fprintf (file, "%s:\n", binder_name);
17155 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
17156 fprintf (file, "\tpushl\t%%eax\n");
17159 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
17161 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
17163 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17164 fprintf (file, "%s:\n", lazy_ptr_name);
17165 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17166 fprintf (file, "\t.long %s\n", binder_name);
17170 darwin_x86_file_end (void)
17172 darwin_file_end ();
17175 #endif /* TARGET_MACHO */
17177 /* Order the registers for register allocator. */
17180 x86_order_regs_for_local_alloc (void)
17185 /* First allocate the local general purpose registers. */
17186 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17187 if (GENERAL_REGNO_P (i) && call_used_regs[i])
17188 reg_alloc_order [pos++] = i;
17190 /* Global general purpose registers. */
17191 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17192 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
17193 reg_alloc_order [pos++] = i;
17195 /* x87 registers come first in case we are doing FP math
17197 if (!TARGET_SSE_MATH)
17198 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
17199 reg_alloc_order [pos++] = i;
17201 /* SSE registers. */
17202 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
17203 reg_alloc_order [pos++] = i;
17204 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
17205 reg_alloc_order [pos++] = i;
17207 /* x87 registers. */
17208 if (TARGET_SSE_MATH)
17209 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
17210 reg_alloc_order [pos++] = i;
17212 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
17213 reg_alloc_order [pos++] = i;
17215 /* Initialize the rest of array as we do not allocate some registers
17217 while (pos < FIRST_PSEUDO_REGISTER)
17218 reg_alloc_order [pos++] = 0;
17221 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
17222 struct attribute_spec.handler. */
17224 ix86_handle_struct_attribute (tree *node, tree name,
17225 tree args ATTRIBUTE_UNUSED,
17226 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
17229 if (DECL_P (*node))
17231 if (TREE_CODE (*node) == TYPE_DECL)
17232 type = &TREE_TYPE (*node);
17237 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
17238 || TREE_CODE (*type) == UNION_TYPE)))
17240 warning (OPT_Wattributes, "%qs attribute ignored",
17241 IDENTIFIER_POINTER (name));
17242 *no_add_attrs = true;
17245 else if ((is_attribute_p ("ms_struct", name)
17246 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
17247 || ((is_attribute_p ("gcc_struct", name)
17248 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
17250 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
17251 IDENTIFIER_POINTER (name));
17252 *no_add_attrs = true;
17259 ix86_ms_bitfield_layout_p (tree record_type)
17261 return (TARGET_MS_BITFIELD_LAYOUT &&
17262 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
17263 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
17266 /* Returns an expression indicating where the this parameter is
17267 located on entry to the FUNCTION. */
17270 x86_this_parameter (tree function)
17272 tree type = TREE_TYPE (function);
17276 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
17277 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
17280 if (ix86_function_regparm (type, function) > 0)
17284 parm = TYPE_ARG_TYPES (type);
17285 /* Figure out whether or not the function has a variable number of
17287 for (; parm; parm = TREE_CHAIN (parm))
17288 if (TREE_VALUE (parm) == void_type_node)
17290 /* If not, the this parameter is in the first argument. */
17294 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
17296 return gen_rtx_REG (SImode, regno);
17300 if (aggregate_value_p (TREE_TYPE (type), type))
17301 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
17303 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
17306 /* Determine whether x86_output_mi_thunk can succeed. */
17309 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
17310 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
17311 HOST_WIDE_INT vcall_offset, tree function)
17313 /* 64-bit can handle anything. */
17317 /* For 32-bit, everything's fine if we have one free register. */
17318 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
17321 /* Need a free register for vcall_offset. */
17325 /* Need a free register for GOT references. */
17326 if (flag_pic && !(*targetm.binds_local_p) (function))
17329 /* Otherwise ok. */
17333 /* Output the assembler code for a thunk function. THUNK_DECL is the
17334 declaration for the thunk function itself, FUNCTION is the decl for
17335 the target function. DELTA is an immediate constant offset to be
17336 added to THIS. If VCALL_OFFSET is nonzero, the word at
17337 *(*this + vcall_offset) should be added to THIS. */
17340 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
17341 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
17342 HOST_WIDE_INT vcall_offset, tree function)
17345 rtx this = x86_this_parameter (function);
17348 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
17349 pull it in now and let DELTA benefit. */
17352 else if (vcall_offset)
17354 /* Put the this parameter into %eax. */
17356 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
17357 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17360 this_reg = NULL_RTX;
17362 /* Adjust the this parameter by a fixed constant. */
17365 xops[0] = GEN_INT (delta);
17366 xops[1] = this_reg ? this_reg : this;
17369 if (!x86_64_general_operand (xops[0], DImode))
17371 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
17373 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
17377 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
17380 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
17383 /* Adjust the this parameter by a value stored in the vtable. */
17387 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
17390 int tmp_regno = 2 /* ECX */;
17391 if (lookup_attribute ("fastcall",
17392 TYPE_ATTRIBUTES (TREE_TYPE (function))))
17393 tmp_regno = 0 /* EAX */;
17394 tmp = gen_rtx_REG (SImode, tmp_regno);
17397 xops[0] = gen_rtx_MEM (Pmode, this_reg);
17400 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
17402 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17404 /* Adjust the this parameter. */
17405 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
17406 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
17408 rtx tmp2 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
17409 xops[0] = GEN_INT (vcall_offset);
17411 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
17412 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
17414 xops[1] = this_reg;
17416 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
17418 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
17421 /* If necessary, drop THIS back to its stack slot. */
17422 if (this_reg && this_reg != this)
17424 xops[0] = this_reg;
17426 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
17429 xops[0] = XEXP (DECL_RTL (function), 0);
17432 if (!flag_pic || (*targetm.binds_local_p) (function))
17433 output_asm_insn ("jmp\t%P0", xops);
17436 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
17437 tmp = gen_rtx_CONST (Pmode, tmp);
17438 tmp = gen_rtx_MEM (QImode, tmp);
17440 output_asm_insn ("jmp\t%A0", xops);
17445 if (!flag_pic || (*targetm.binds_local_p) (function))
17446 output_asm_insn ("jmp\t%P0", xops);
17451 rtx sym_ref = XEXP (DECL_RTL (function), 0);
17452 tmp = (gen_rtx_SYMBOL_REF
17454 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
17455 tmp = gen_rtx_MEM (QImode, tmp);
17457 output_asm_insn ("jmp\t%0", xops);
17460 #endif /* TARGET_MACHO */
17462 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
17463 output_set_got (tmp, NULL_RTX);
17466 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
17467 output_asm_insn ("jmp\t{*}%1", xops);
17473 x86_file_start (void)
17475 default_file_start ();
17477 darwin_file_start ();
17479 if (X86_FILE_START_VERSION_DIRECTIVE)
17480 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
17481 if (X86_FILE_START_FLTUSED)
17482 fputs ("\t.global\t__fltused\n", asm_out_file);
17483 if (ix86_asm_dialect == ASM_INTEL)
17484 fputs ("\t.intel_syntax\n", asm_out_file);
17488 x86_field_alignment (tree field, int computed)
17490 enum machine_mode mode;
17491 tree type = TREE_TYPE (field);
17493 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
17495 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
17496 ? get_inner_array_type (type) : type);
17497 if (mode == DFmode || mode == DCmode
17498 || GET_MODE_CLASS (mode) == MODE_INT
17499 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
17500 return MIN (32, computed);
17504 /* Output assembler code to FILE to increment profiler label # LABELNO
17505 for profiling a function entry. */
17507 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
17512 #ifndef NO_PROFILE_COUNTERS
17513 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
17515 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
17519 #ifndef NO_PROFILE_COUNTERS
17520 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
17522 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
17526 #ifndef NO_PROFILE_COUNTERS
17527 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
17528 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
17530 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
17534 #ifndef NO_PROFILE_COUNTERS
17535 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
17536 PROFILE_COUNT_REGISTER);
17538 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
17542 /* We don't have exact information about the insn sizes, but we may assume
17543 quite safely that we are informed about all 1 byte insns and memory
17544 address sizes. This is enough to eliminate unnecessary padding in
17548 min_insn_size (rtx insn)
17552 if (!INSN_P (insn) || !active_insn_p (insn))
17555 /* Discard alignments we've emit and jump instructions. */
17556 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
17557 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
17559 if (GET_CODE (insn) == JUMP_INSN
17560 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
17561 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
17564 /* Important case - calls are always 5 bytes.
17565 It is common to have many calls in the row. */
17566 if (GET_CODE (insn) == CALL_INSN
17567 && symbolic_reference_mentioned_p (PATTERN (insn))
17568 && !SIBLING_CALL_P (insn))
17570 if (get_attr_length (insn) <= 1)
17573 /* For normal instructions we may rely on the sizes of addresses
17574 and the presence of symbol to require 4 bytes of encoding.
17575 This is not the case for jumps where references are PC relative. */
17576 if (GET_CODE (insn) != JUMP_INSN)
17578 l = get_attr_length_address (insn);
17579 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
17588 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
17592 ix86_avoid_jump_misspredicts (void)
17594 rtx insn, start = get_insns ();
17595 int nbytes = 0, njumps = 0;
17598 /* Look for all minimal intervals of instructions containing 4 jumps.
17599 The intervals are bounded by START and INSN. NBYTES is the total
17600 size of instructions in the interval including INSN and not including
17601 START. When the NBYTES is smaller than 16 bytes, it is possible
17602 that the end of START and INSN ends up in the same 16byte page.
17604 The smallest offset in the page INSN can start is the case where START
17605 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
17606 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
17608 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17611 nbytes += min_insn_size (insn);
17613 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
17614 INSN_UID (insn), min_insn_size (insn));
17615 if ((GET_CODE (insn) == JUMP_INSN
17616 && GET_CODE (PATTERN (insn)) != ADDR_VEC
17617 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
17618 || GET_CODE (insn) == CALL_INSN)
17625 start = NEXT_INSN (start);
17626 if ((GET_CODE (start) == JUMP_INSN
17627 && GET_CODE (PATTERN (start)) != ADDR_VEC
17628 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
17629 || GET_CODE (start) == CALL_INSN)
17630 njumps--, isjump = 1;
17633 nbytes -= min_insn_size (start);
17635 gcc_assert (njumps >= 0);
17637 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
17638 INSN_UID (start), INSN_UID (insn), nbytes);
17640 if (njumps == 3 && isjump && nbytes < 16)
17642 int padsize = 15 - nbytes + min_insn_size (insn);
17645 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
17646 INSN_UID (insn), padsize);
17647 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
17652 /* AMD Athlon works faster
17653 when RET is not destination of conditional jump or directly preceded
17654 by other jump instruction. We avoid the penalty by inserting NOP just
17655 before the RET instructions in such cases. */
17657 ix86_pad_returns (void)
17662 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
17664 basic_block bb = e->src;
17665 rtx ret = BB_END (bb);
17667 bool replace = false;
17669 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
17670 || !maybe_hot_bb_p (bb))
17672 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
17673 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
17675 if (prev && GET_CODE (prev) == CODE_LABEL)
17680 FOR_EACH_EDGE (e, ei, bb->preds)
17681 if (EDGE_FREQUENCY (e) && e->src->index >= 0
17682 && !(e->flags & EDGE_FALLTHRU))
17687 prev = prev_active_insn (ret);
17689 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
17690 || GET_CODE (prev) == CALL_INSN))
17692 /* Empty functions get branch mispredict even when the jump destination
17693 is not visible to us. */
17694 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
17699 emit_insn_before (gen_return_internal_long (), ret);
17705 /* Implement machine specific optimizations. We implement padding of returns
17706 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
17710 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
17711 ix86_pad_returns ();
17712 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
17713 ix86_avoid_jump_misspredicts ();
17716 /* Return nonzero when QImode register that must be represented via REX prefix
17719 x86_extended_QIreg_mentioned_p (rtx insn)
17722 extract_insn_cached (insn);
17723 for (i = 0; i < recog_data.n_operands; i++)
17724 if (REG_P (recog_data.operand[i])
17725 && REGNO (recog_data.operand[i]) >= 4)
17730 /* Return nonzero when P points to register encoded via REX prefix.
17731 Called via for_each_rtx. */
17733 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
17735 unsigned int regno;
17738 regno = REGNO (*p);
17739 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
17742 /* Return true when INSN mentions register that must be encoded using REX
17745 x86_extended_reg_mentioned_p (rtx insn)
17747 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
17750 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
17751 optabs would emit if we didn't have TFmode patterns. */
17754 x86_emit_floatuns (rtx operands[2])
17756 rtx neglab, donelab, i0, i1, f0, in, out;
17757 enum machine_mode mode, inmode;
17759 inmode = GET_MODE (operands[1]);
17760 gcc_assert (inmode == SImode || inmode == DImode);
17763 in = force_reg (inmode, operands[1]);
17764 mode = GET_MODE (out);
17765 neglab = gen_label_rtx ();
17766 donelab = gen_label_rtx ();
17767 i1 = gen_reg_rtx (Pmode);
17768 f0 = gen_reg_rtx (mode);
17770 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
17772 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
17773 emit_jump_insn (gen_jump (donelab));
17776 emit_label (neglab);
17778 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17779 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17780 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
17781 expand_float (f0, i0, 0);
17782 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
17784 emit_label (donelab);
17787 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17788 with all elements equal to VAR. Return true if successful. */
17791 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
17792 rtx target, rtx val)
17794 enum machine_mode smode, wsmode, wvmode;
17801 if (!mmx_ok && !TARGET_SSE)
17809 val = force_reg (GET_MODE_INNER (mode), val);
17810 x = gen_rtx_VEC_DUPLICATE (mode, val);
17811 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17817 if (TARGET_SSE || TARGET_3DNOW_A)
17819 val = gen_lowpart (SImode, val);
17820 x = gen_rtx_TRUNCATE (HImode, val);
17821 x = gen_rtx_VEC_DUPLICATE (mode, x);
17822 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17844 /* Extend HImode to SImode using a paradoxical SUBREG. */
17845 tmp1 = gen_reg_rtx (SImode);
17846 emit_move_insn (tmp1, gen_lowpart (SImode, val));
17847 /* Insert the SImode value as low element of V4SImode vector. */
17848 tmp2 = gen_reg_rtx (V4SImode);
17849 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
17850 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
17851 CONST0_RTX (V4SImode),
17853 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
17854 /* Cast the V4SImode vector back to a V8HImode vector. */
17855 tmp1 = gen_reg_rtx (V8HImode);
17856 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
17857 /* Duplicate the low short through the whole low SImode word. */
17858 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
17859 /* Cast the V8HImode vector back to a V4SImode vector. */
17860 tmp2 = gen_reg_rtx (V4SImode);
17861 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
17862 /* Replicate the low element of the V4SImode vector. */
17863 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
17864 /* Cast the V2SImode back to V8HImode, and store in target. */
17865 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
17876 /* Extend QImode to SImode using a paradoxical SUBREG. */
17877 tmp1 = gen_reg_rtx (SImode);
17878 emit_move_insn (tmp1, gen_lowpart (SImode, val));
17879 /* Insert the SImode value as low element of V4SImode vector. */
17880 tmp2 = gen_reg_rtx (V4SImode);
17881 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
17882 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
17883 CONST0_RTX (V4SImode),
17885 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
17886 /* Cast the V4SImode vector back to a V16QImode vector. */
17887 tmp1 = gen_reg_rtx (V16QImode);
17888 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
17889 /* Duplicate the low byte through the whole low SImode word. */
17890 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
17891 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
17892 /* Cast the V16QImode vector back to a V4SImode vector. */
17893 tmp2 = gen_reg_rtx (V4SImode);
17894 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
17895 /* Replicate the low element of the V4SImode vector. */
17896 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
17897 /* Cast the V2SImode back to V16QImode, and store in target. */
17898 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
17906 /* Replicate the value once into the next wider mode and recurse. */
17907 val = convert_modes (wsmode, smode, val, true);
17908 x = expand_simple_binop (wsmode, ASHIFT, val,
17909 GEN_INT (GET_MODE_BITSIZE (smode)),
17910 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17911 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
17913 x = gen_reg_rtx (wvmode);
17914 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
17915 gcc_unreachable ();
17916 emit_move_insn (target, gen_lowpart (mode, x));
17924 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17925 whose ONE_VAR element is VAR, and other elements are zero. Return true
17929 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
17930 rtx target, rtx var, int one_var)
17932 enum machine_mode vsimode;
17940 if (!mmx_ok && !TARGET_SSE)
17948 var = force_reg (GET_MODE_INNER (mode), var);
17949 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
17950 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17955 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
17956 new_target = gen_reg_rtx (mode);
17958 new_target = target;
17959 var = force_reg (GET_MODE_INNER (mode), var);
17960 x = gen_rtx_VEC_DUPLICATE (mode, var);
17961 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
17962 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
17965 /* We need to shuffle the value to the correct position, so
17966 create a new pseudo to store the intermediate result. */
17968 /* With SSE2, we can use the integer shuffle insns. */
17969 if (mode != V4SFmode && TARGET_SSE2)
17971 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
17973 GEN_INT (one_var == 1 ? 0 : 1),
17974 GEN_INT (one_var == 2 ? 0 : 1),
17975 GEN_INT (one_var == 3 ? 0 : 1)));
17976 if (target != new_target)
17977 emit_move_insn (target, new_target);
17981 /* Otherwise convert the intermediate result to V4SFmode and
17982 use the SSE1 shuffle instructions. */
17983 if (mode != V4SFmode)
17985 tmp = gen_reg_rtx (V4SFmode);
17986 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
17991 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
17993 GEN_INT (one_var == 1 ? 0 : 1),
17994 GEN_INT (one_var == 2 ? 0+4 : 1+4),
17995 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
17997 if (mode != V4SFmode)
17998 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
17999 else if (tmp != target)
18000 emit_move_insn (target, tmp);
18002 else if (target != new_target)
18003 emit_move_insn (target, new_target);
18008 vsimode = V4SImode;
18014 vsimode = V2SImode;
18020 /* Zero extend the variable element to SImode and recurse. */
18021 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
18023 x = gen_reg_rtx (vsimode);
18024 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
18026 gcc_unreachable ();
18028 emit_move_insn (target, gen_lowpart (mode, x));
18036 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
18037 consisting of the values in VALS. It is known that all elements
18038 except ONE_VAR are constants. Return true if successful. */
18041 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
18042 rtx target, rtx vals, int one_var)
18044 rtx var = XVECEXP (vals, 0, one_var);
18045 enum machine_mode wmode;
18048 const_vec = copy_rtx (vals);
18049 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
18050 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
18058 /* For the two element vectors, it's just as easy to use
18059 the general case. */
18075 /* There's no way to set one QImode entry easily. Combine
18076 the variable value with its adjacent constant value, and
18077 promote to an HImode set. */
18078 x = XVECEXP (vals, 0, one_var ^ 1);
18081 var = convert_modes (HImode, QImode, var, true);
18082 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
18083 NULL_RTX, 1, OPTAB_LIB_WIDEN);
18084 x = GEN_INT (INTVAL (x) & 0xff);
18088 var = convert_modes (HImode, QImode, var, true);
18089 x = gen_int_mode (INTVAL (x) << 8, HImode);
18091 if (x != const0_rtx)
18092 var = expand_simple_binop (HImode, IOR, var, x, var,
18093 1, OPTAB_LIB_WIDEN);
18095 x = gen_reg_rtx (wmode);
18096 emit_move_insn (x, gen_lowpart (wmode, const_vec));
18097 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
18099 emit_move_insn (target, gen_lowpart (mode, x));
18106 emit_move_insn (target, const_vec);
18107 ix86_expand_vector_set (mmx_ok, target, var, one_var);
18111 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
18112 all values variable, and none identical. */
18115 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
18116 rtx target, rtx vals)
18118 enum machine_mode half_mode = GET_MODE_INNER (mode);
18119 rtx op0 = NULL, op1 = NULL;
18120 bool use_vec_concat = false;
18126 if (!mmx_ok && !TARGET_SSE)
18132 /* For the two element vectors, we always implement VEC_CONCAT. */
18133 op0 = XVECEXP (vals, 0, 0);
18134 op1 = XVECEXP (vals, 0, 1);
18135 use_vec_concat = true;
18139 half_mode = V2SFmode;
18142 half_mode = V2SImode;
18148 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
18149 Recurse to load the two halves. */
18151 op0 = gen_reg_rtx (half_mode);
18152 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
18153 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
18155 op1 = gen_reg_rtx (half_mode);
18156 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
18157 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
18159 use_vec_concat = true;
18170 gcc_unreachable ();
18173 if (use_vec_concat)
18175 if (!register_operand (op0, half_mode))
18176 op0 = force_reg (half_mode, op0);
18177 if (!register_operand (op1, half_mode))
18178 op1 = force_reg (half_mode, op1);
18180 emit_insn (gen_rtx_SET (VOIDmode, target,
18181 gen_rtx_VEC_CONCAT (mode, op0, op1)));
18185 int i, j, n_elts, n_words, n_elt_per_word;
18186 enum machine_mode inner_mode;
18187 rtx words[4], shift;
18189 inner_mode = GET_MODE_INNER (mode);
18190 n_elts = GET_MODE_NUNITS (mode);
18191 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
18192 n_elt_per_word = n_elts / n_words;
18193 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
18195 for (i = 0; i < n_words; ++i)
18197 rtx word = NULL_RTX;
18199 for (j = 0; j < n_elt_per_word; ++j)
18201 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
18202 elt = convert_modes (word_mode, inner_mode, elt, true);
18208 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
18209 word, 1, OPTAB_LIB_WIDEN);
18210 word = expand_simple_binop (word_mode, IOR, word, elt,
18211 word, 1, OPTAB_LIB_WIDEN);
18219 emit_move_insn (target, gen_lowpart (mode, words[0]));
18220 else if (n_words == 2)
18222 rtx tmp = gen_reg_rtx (mode);
18223 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
18224 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
18225 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
18226 emit_move_insn (target, tmp);
18228 else if (n_words == 4)
18230 rtx tmp = gen_reg_rtx (V4SImode);
18231 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
18232 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
18233 emit_move_insn (target, gen_lowpart (mode, tmp));
18236 gcc_unreachable ();
18240 /* Initialize vector TARGET via VALS. Suppress the use of MMX
18241 instructions unless MMX_OK is true. */
18244 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
18246 enum machine_mode mode = GET_MODE (target);
18247 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18248 int n_elts = GET_MODE_NUNITS (mode);
18249 int n_var = 0, one_var = -1;
18250 bool all_same = true, all_const_zero = true;
18254 for (i = 0; i < n_elts; ++i)
18256 x = XVECEXP (vals, 0, i);
18257 if (!CONSTANT_P (x))
18258 n_var++, one_var = i;
18259 else if (x != CONST0_RTX (inner_mode))
18260 all_const_zero = false;
18261 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18265 /* Constants are best loaded from the constant pool. */
18268 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
18272 /* If all values are identical, broadcast the value. */
18274 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
18275 XVECEXP (vals, 0, 0)))
18278 /* Values where only one field is non-constant are best loaded from
18279 the pool and overwritten via move later. */
18283 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
18284 XVECEXP (vals, 0, one_var),
18288 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
18292 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
18296 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
18298 enum machine_mode mode = GET_MODE (target);
18299 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18300 bool use_vec_merge = false;
18309 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
18310 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
18312 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
18314 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
18315 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18325 /* For the two element vectors, we implement a VEC_CONCAT with
18326 the extraction of the other element. */
18328 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
18329 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
18332 op0 = val, op1 = tmp;
18334 op0 = tmp, op1 = val;
18336 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
18337 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18345 use_vec_merge = true;
18349 /* tmp = target = A B C D */
18350 tmp = copy_to_reg (target);
18351 /* target = A A B B */
18352 emit_insn (gen_sse_unpcklps (target, target, target));
18353 /* target = X A B B */
18354 ix86_expand_vector_set (false, target, val, 0);
18355 /* target = A X C D */
18356 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18357 GEN_INT (1), GEN_INT (0),
18358 GEN_INT (2+4), GEN_INT (3+4)));
18362 /* tmp = target = A B C D */
18363 tmp = copy_to_reg (target);
18364 /* tmp = X B C D */
18365 ix86_expand_vector_set (false, tmp, val, 0);
18366 /* target = A B X D */
18367 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18368 GEN_INT (0), GEN_INT (1),
18369 GEN_INT (0+4), GEN_INT (3+4)));
18373 /* tmp = target = A B C D */
18374 tmp = copy_to_reg (target);
18375 /* tmp = X B C D */
18376 ix86_expand_vector_set (false, tmp, val, 0);
18377 /* target = A B X D */
18378 emit_insn (gen_sse_shufps_1 (target, target, tmp,
18379 GEN_INT (0), GEN_INT (1),
18380 GEN_INT (2+4), GEN_INT (0+4)));
18384 gcc_unreachable ();
18389 /* Element 0 handled by vec_merge below. */
18392 use_vec_merge = true;
18398 /* With SSE2, use integer shuffles to swap element 0 and ELT,
18399 store into element 0, then shuffle them back. */
18403 order[0] = GEN_INT (elt);
18404 order[1] = const1_rtx;
18405 order[2] = const2_rtx;
18406 order[3] = GEN_INT (3);
18407 order[elt] = const0_rtx;
18409 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
18410 order[1], order[2], order[3]));
18412 ix86_expand_vector_set (false, target, val, 0);
18414 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
18415 order[1], order[2], order[3]));
18419 /* For SSE1, we have to reuse the V4SF code. */
18420 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
18421 gen_lowpart (SFmode, val), elt);
18426 use_vec_merge = TARGET_SSE2;
18429 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
18440 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
18441 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
18442 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18446 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
18448 emit_move_insn (mem, target);
18450 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
18451 emit_move_insn (tmp, val);
18453 emit_move_insn (target, mem);
18458 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
18460 enum machine_mode mode = GET_MODE (vec);
18461 enum machine_mode inner_mode = GET_MODE_INNER (mode);
18462 bool use_vec_extr = false;
18475 use_vec_extr = true;
18487 tmp = gen_reg_rtx (mode);
18488 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
18489 GEN_INT (elt), GEN_INT (elt),
18490 GEN_INT (elt+4), GEN_INT (elt+4)));
18494 tmp = gen_reg_rtx (mode);
18495 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
18499 gcc_unreachable ();
18502 use_vec_extr = true;
18517 tmp = gen_reg_rtx (mode);
18518 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
18519 GEN_INT (elt), GEN_INT (elt),
18520 GEN_INT (elt), GEN_INT (elt)));
18524 tmp = gen_reg_rtx (mode);
18525 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
18529 gcc_unreachable ();
18532 use_vec_extr = true;
18537 /* For SSE1, we have to reuse the V4SF code. */
18538 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
18539 gen_lowpart (V4SFmode, vec), elt);
18545 use_vec_extr = TARGET_SSE2;
18548 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
18553 /* ??? Could extract the appropriate HImode element and shift. */
18560 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
18561 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
18563 /* Let the rtl optimizers know about the zero extension performed. */
18564 if (inner_mode == HImode)
18566 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
18567 target = gen_lowpart (SImode, target);
18570 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
18574 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
18576 emit_move_insn (mem, vec);
18578 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
18579 emit_move_insn (target, tmp);
18583 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
18584 pattern to reduce; DEST is the destination; IN is the input vector. */
18587 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
18589 rtx tmp1, tmp2, tmp3;
18591 tmp1 = gen_reg_rtx (V4SFmode);
18592 tmp2 = gen_reg_rtx (V4SFmode);
18593 tmp3 = gen_reg_rtx (V4SFmode);
18595 emit_insn (gen_sse_movhlps (tmp1, in, in));
18596 emit_insn (fn (tmp2, tmp1, in));
18598 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
18599 GEN_INT (1), GEN_INT (1),
18600 GEN_INT (1+4), GEN_INT (1+4)));
18601 emit_insn (fn (dest, tmp2, tmp3));
18604 /* Target hook for scalar_mode_supported_p. */
18606 ix86_scalar_mode_supported_p (enum machine_mode mode)
18608 if (DECIMAL_FLOAT_MODE_P (mode))
18611 return default_scalar_mode_supported_p (mode);
18614 /* Implements target hook vector_mode_supported_p. */
18616 ix86_vector_mode_supported_p (enum machine_mode mode)
18618 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
18620 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
18622 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
18624 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
18629 /* Worker function for TARGET_MD_ASM_CLOBBERS.
18631 We do this in the new i386 backend to maintain source compatibility
18632 with the old cc0-based compiler. */
18635 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
18636 tree inputs ATTRIBUTE_UNUSED,
18639 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
18641 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
18643 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
18648 /* Return true if this goes in small data/bss. */
18651 ix86_in_large_data_p (tree exp)
18653 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
18656 /* Functions are never large data. */
18657 if (TREE_CODE (exp) == FUNCTION_DECL)
18660 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
18662 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
18663 if (strcmp (section, ".ldata") == 0
18664 || strcmp (section, ".lbss") == 0)
18670 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
18672 /* If this is an incomplete type with size 0, then we can't put it
18673 in data because it might be too big when completed. */
18674 if (!size || size > ix86_section_threshold)
18681 ix86_encode_section_info (tree decl, rtx rtl, int first)
18683 default_encode_section_info (decl, rtl, first);
18685 if (TREE_CODE (decl) == VAR_DECL
18686 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
18687 && ix86_in_large_data_p (decl))
18688 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
18691 /* Worker function for REVERSE_CONDITION. */
18694 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
18696 return (mode != CCFPmode && mode != CCFPUmode
18697 ? reverse_condition (code)
18698 : reverse_condition_maybe_unordered (code));
18701 /* Output code to perform an x87 FP register move, from OPERANDS[1]
18705 output_387_reg_move (rtx insn, rtx *operands)
18707 if (REG_P (operands[1])
18708 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
18710 if (REGNO (operands[0]) == FIRST_STACK_REG
18711 && TARGET_USE_FFREEP)
18712 return "ffreep\t%y0";
18713 return "fstp\t%y0";
18715 if (STACK_TOP_P (operands[0]))
18716 return "fld%z1\t%y1";
18720 /* Output code to perform a conditional jump to LABEL, if C2 flag in
18721 FP status register is set. */
18724 ix86_emit_fp_unordered_jump (rtx label)
18726 rtx reg = gen_reg_rtx (HImode);
18729 emit_insn (gen_x86_fnstsw_1 (reg));
18731 if (TARGET_USE_SAHF)
18733 emit_insn (gen_x86_sahf_1 (reg));
18735 temp = gen_rtx_REG (CCmode, FLAGS_REG);
18736 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
18740 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
18742 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18743 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
18746 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
18747 gen_rtx_LABEL_REF (VOIDmode, label),
18749 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
18750 emit_jump_insn (temp);
18753 /* Output code to perform a log1p XFmode calculation. */
18755 void ix86_emit_i387_log1p (rtx op0, rtx op1)
18757 rtx label1 = gen_label_rtx ();
18758 rtx label2 = gen_label_rtx ();
18760 rtx tmp = gen_reg_rtx (XFmode);
18761 rtx tmp2 = gen_reg_rtx (XFmode);
18763 emit_insn (gen_absxf2 (tmp, op1));
18764 emit_insn (gen_cmpxf (tmp,
18765 CONST_DOUBLE_FROM_REAL_VALUE (
18766 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
18768 emit_jump_insn (gen_bge (label1));
18770 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18771 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
18772 emit_jump (label2);
18774 emit_label (label1);
18775 emit_move_insn (tmp, CONST1_RTX (XFmode));
18776 emit_insn (gen_addxf3 (tmp, op1, tmp));
18777 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18778 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
18780 emit_label (label2);
18783 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
18786 i386_solaris_elf_named_section (const char *name, unsigned int flags,
18789 /* With Binutils 2.15, the "@unwind" marker must be specified on
18790 every occurrence of the ".eh_frame" section, not just the first
18793 && strcmp (name, ".eh_frame") == 0)
18795 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
18796 flags & SECTION_WRITE ? "aw" : "a");
18799 default_elf_asm_named_section (name, flags, decl);
18802 /* Return the mangling of TYPE if it is an extended fundamental type. */
18804 static const char *
18805 ix86_mangle_fundamental_type (tree type)
18807 switch (TYPE_MODE (type))
18810 /* __float128 is "g". */
18813 /* "long double" or __float80 is "e". */
18820 /* For 32-bit code we can save PIC register setup by using
18821 __stack_chk_fail_local hidden function instead of calling
18822 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
18823 register, so it is better to call __stack_chk_fail directly. */
18826 ix86_stack_protect_fail (void)
18828 return TARGET_64BIT
18829 ? default_external_stack_protect_fail ()
18830 : default_hidden_stack_protect_fail ();
18833 /* Select a format to encode pointers in exception handling data. CODE
18834 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
18835 true if the symbol may be affected by dynamic relocations.
18837 ??? All x86 object file formats are capable of representing this.
18838 After all, the relocation needed is the same as for the call insn.
18839 Whether or not a particular assembler allows us to enter such, I
18840 guess we'll have to see. */
18842 asm_preferred_eh_data_format (int code, int global)
18846 int type = DW_EH_PE_sdata8;
18848 || ix86_cmodel == CM_SMALL_PIC
18849 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
18850 type = DW_EH_PE_sdata4;
18851 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
18853 if (ix86_cmodel == CM_SMALL
18854 || (ix86_cmodel == CM_MEDIUM && code))
18855 return DW_EH_PE_udata4;
18856 return DW_EH_PE_absptr;
18859 #include "gt-i386.h"