1 /* Subroutines for the gcc driver.
2 Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
25 const char *host_detect_local_cpu (int argc, const char **argv);
37 /* Returns command line parameters that describe size and
38 cache line size of the processor caches. */
41 describe_cache (struct cache_desc level1, struct cache_desc level2)
43 char size[100], line[100], size2[100];
45 /* At the moment, gcc does not use the information
46 about the associativity of the cache. */
48 snprintf (size, sizeof (size),
49 "--param l1-cache-size=%u ", level1.sizekb);
50 snprintf (line, sizeof (line),
51 "--param l1-cache-line-size=%u ", level1.line);
53 snprintf (size2, sizeof (size2),
54 "--param l2-cache-size=%u ", level2.sizekb);
56 return concat (size, line, size2, NULL);
59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */
62 detect_l2_cache (struct cache_desc *level2)
64 unsigned eax, ebx, ecx, edx;
67 __cpuid (0x80000006, eax, ebx, ecx, edx);
69 level2->sizekb = (ecx >> 16) & 0xffff;
70 level2->line = ecx & 0xff;
72 assoc = (ecx >> 12) & 0xf;
77 else if (assoc >= 0xa && assoc <= 0xc)
78 assoc = 32 + (assoc - 0xa) * 16;
79 else if (assoc >= 0xd && assoc <= 0xe)
80 assoc = 96 + (assoc - 0xd) * 32;
82 level2->assoc = assoc;
85 /* Returns the description of caches for an AMD processor. */
88 detect_caches_amd (unsigned max_ext_level)
90 unsigned eax, ebx, ecx, edx;
92 struct cache_desc level1, level2 = {0, 0, 0};
94 if (max_ext_level < 0x80000005)
97 __cpuid (0x80000005, eax, ebx, ecx, edx);
99 level1.sizekb = (ecx >> 24) & 0xff;
100 level1.assoc = (ecx >> 16) & 0xff;
101 level1.line = ecx & 0xff;
103 if (max_ext_level >= 0x80000006)
104 detect_l2_cache (&level2);
106 return describe_cache (level1, level2);
109 /* Decodes the size, the associativity and the cache line size of
110 L1/L2 caches of an Intel processor. Values are based on
111 "Intel Processor Identification and the CPUID Instruction"
112 [Application Note 485], revision -032, December 2007. */
115 decode_caches_intel (unsigned reg, bool xeon_mp,
116 struct cache_desc *level1, struct cache_desc *level2)
120 for (i = 24; i >= 0; i -= 8)
121 switch ((reg >> i) & 0xff)
124 level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
127 level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
130 level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
133 level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
136 level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
139 level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
142 level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
145 level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
148 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
151 level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
154 level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
157 level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
160 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
163 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
168 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
171 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
174 level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
177 level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
180 level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
183 level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
186 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
189 level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
192 level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
195 level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
198 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
201 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
204 level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
207 level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
210 level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
213 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
216 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
219 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
222 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
229 /* Detect cache parameters using CPUID function 2. */
232 detect_caches_cpuid2 (bool xeon_mp,
233 struct cache_desc *level1, struct cache_desc *level2)
238 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
240 nreps = regs[0] & 0x0f;
245 for (i = 0; i < 4; i++)
246 if (regs[i] && !((regs[i] >> 31) & 1))
247 decode_caches_intel (regs[i], xeon_mp, level1, level2);
250 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
254 /* Detect cache parameters using CPUID function 4. This
255 method doesn't require hardcoded tables. */
266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
267 struct cache_desc *level3)
269 struct cache_desc *cache;
271 unsigned eax, ebx, ecx, edx;
274 for (count = 0;; count++)
276 __cpuid_count(4, count, eax, ebx, ecx, edx);
284 switch ((eax >> 5) & 0x07)
301 unsigned sets = ecx + 1;
302 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
304 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
305 cache->line = (ebx & 0x0fff) + 1;
307 cache->sizekb = (cache->assoc * part
308 * cache->line * sets) / 1024;
317 /* Returns the description of caches for an Intel processor. */
320 detect_caches_intel (bool xeon_mp, unsigned max_level,
321 unsigned max_ext_level, unsigned *l2sizekb)
323 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
326 detect_caches_cpuid4 (&level1, &level2, &level3);
327 else if (max_level >= 2)
328 detect_caches_cpuid2 (xeon_mp, &level1, &level2);
332 if (level1.sizekb == 0)
335 /* Let the L3 replace the L2. This assumes inclusive caches
336 and single threaded program for now. */
340 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
341 method if other methods fail to provide L2 cache parameters. */
342 if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
343 detect_l2_cache (&level2);
345 *l2sizekb = level2.sizekb;
347 return describe_cache (level1, level2);
350 enum vendor_signatures
352 SIG_INTEL = 0x756e6547 /* Genu */,
353 SIG_AMD = 0x68747541 /* Auth */,
354 SIG_CENTAUR = 0x746e6543 /* Cent */,
355 SIG_CYRIX = 0x69727943 /* Cyri */,
356 SIG_NSC = 0x646f6547 /* Geod */
359 enum processor_signatures
361 SIG_GEODE = 0x646f6547 /* Geod */
364 /* This will be called by the spec parser in gcc.c when it sees
365 a %:local_cpu_detect(args) construct. Currently it will be called
366 with either "arch" or "tune" as argument depending on if -march=native
367 or -mtune=native is to be substituted.
369 It returns a string containing new command line parameters to be
370 put at the place of the above two options, depending on what CPU
371 this is executed. E.g. "-march=k8" on an AMD64 machine
374 ARGC and ARGV are set depending on the actual arguments given
377 const char *host_detect_local_cpu (int argc, const char **argv)
379 enum processor_type processor = PROCESSOR_I386;
380 const char *cpu = "i386";
382 const char *cache = "";
383 const char *options = "";
385 unsigned int eax, ebx, ecx, edx;
387 unsigned int max_level, ext_level;
390 unsigned int model, family;
392 unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
393 unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
395 /* Extended features */
396 unsigned int has_lahf_lm = 0, has_sse4a = 0;
397 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
398 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
399 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
400 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
401 unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
402 unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
403 unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
404 unsigned int has_osxsave = 0;
408 unsigned int l2sizekb = 0;
413 arch = !strcmp (argv[0], "arch");
415 if (!arch && strcmp (argv[0], "tune"))
418 max_level = __get_cpuid_max (0, &vendor);
422 __cpuid (1, eax, ebx, ecx, edx);
424 model = (eax >> 4) & 0x0f;
425 family = (eax >> 8) & 0x0f;
426 if (vendor == SIG_INTEL)
428 unsigned int extended_model, extended_family;
430 extended_model = (eax >> 12) & 0xf0;
431 extended_family = (eax >> 20) & 0xff;
434 family += extended_family;
435 model += extended_model;
437 else if (family == 0x06)
438 model += extended_model;
441 has_sse3 = ecx & bit_SSE3;
442 has_ssse3 = ecx & bit_SSSE3;
443 has_sse4_1 = ecx & bit_SSE4_1;
444 has_sse4_2 = ecx & bit_SSE4_2;
445 has_avx = ecx & bit_AVX;
446 has_osxsave = ecx & bit_OSXSAVE;
447 has_cmpxchg16b = ecx & bit_CMPXCHG16B;
448 has_movbe = ecx & bit_MOVBE;
449 has_popcnt = ecx & bit_POPCNT;
450 has_aes = ecx & bit_AES;
451 has_pclmul = ecx & bit_PCLMUL;
452 has_fma = ecx & bit_FMA;
453 has_f16c = ecx & bit_F16C;
454 has_rdrnd = ecx & bit_RDRND;
456 has_cmpxchg8b = edx & bit_CMPXCHG8B;
457 has_cmov = edx & bit_CMOV;
458 has_mmx = edx & bit_MMX;
459 has_sse = edx & bit_SSE;
460 has_sse2 = edx & bit_SSE2;
464 __cpuid_count (7, 0, eax, ebx, ecx, edx);
466 has_bmi = ebx & bit_BMI;
467 has_avx2 = ebx & bit_AVX2;
468 has_bmi2 = ebx & bit_BMI2;
469 has_fsgsbase = ebx & bit_FSGSBASE;
472 /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
473 #define XCR_XFEATURE_ENABLED_MASK 0x0
474 #define XSTATE_FP 0x1
475 #define XSTATE_SSE 0x2
476 #define XSTATE_YMM 0x4
478 asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
479 : "=a" (eax), "=d" (edx)
480 : "c" (XCR_XFEATURE_ENABLED_MASK));
482 /* Check if SSE and YMM states are supported. */
484 || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
493 /* Check cpuid level of extended features. */
494 __cpuid (0x80000000, ext_level, ebx, ecx, edx);
496 if (ext_level > 0x80000000)
498 __cpuid (0x80000001, eax, ebx, ecx, edx);
500 has_lahf_lm = ecx & bit_LAHF_LM;
501 has_sse4a = ecx & bit_SSE4a;
502 has_abm = ecx & bit_ABM;
503 has_lwp = ecx & bit_LWP;
504 has_fma4 = ecx & bit_FMA4;
505 has_xop = ecx & bit_XOP;
506 has_tbm = ecx & bit_TBM;
507 has_lzcnt = ecx & bit_LZCNT;
509 has_longmode = edx & bit_LM;
510 has_3dnowp = edx & bit_3DNOWP;
511 has_3dnow = edx & bit_3DNOW;
516 if (vendor == SIG_AMD
517 || vendor == SIG_CENTAUR
518 || vendor == SIG_CYRIX
519 || vendor == SIG_NSC)
520 cache = detect_caches_amd (ext_level);
521 else if (vendor == SIG_INTEL)
523 bool xeon_mp = (family == 15 && model == 6);
524 cache = detect_caches_intel (xeon_mp, max_level,
525 ext_level, &l2sizekb);
529 if (vendor == SIG_AMD)
533 /* Detect geode processor by its processor signature. */
534 if (ext_level > 0x80000001)
535 __cpuid (0x80000002, name, ebx, ecx, edx);
539 if (name == SIG_GEODE)
540 processor = PROCESSOR_GEODE;
542 processor = PROCESSOR_BDVER2;
544 processor = PROCESSOR_BDVER1;
545 else if (has_sse4a && has_ssse3)
546 processor = PROCESSOR_BTVER1;
548 processor = PROCESSOR_AMDFAM10;
549 else if (has_sse2 || has_longmode)
550 processor = PROCESSOR_K8;
551 else if (has_3dnowp && family == 6)
552 processor = PROCESSOR_ATHLON;
554 processor = PROCESSOR_K6;
556 processor = PROCESSOR_PENTIUM;
558 else if (vendor == SIG_CENTAUR)
566 /* Use the default detection procedure. */
567 processor = PROCESSOR_GENERIC32;
573 processor = PROCESSOR_GENERIC32;
581 processor = PROCESSOR_GENERIC32;
584 /* We have no idea. */
585 processor = PROCESSOR_GENERIC32;
594 processor = PROCESSOR_I486;
597 processor = PROCESSOR_PENTIUM;
600 processor = PROCESSOR_PENTIUMPRO;
603 processor = PROCESSOR_PENTIUM4;
606 /* We have no idea. */
607 processor = PROCESSOR_GENERIC32;
619 case PROCESSOR_PENTIUM:
625 case PROCESSOR_PENTIUMPRO:
663 /* This is unknown family 0x6 CPU. */
665 /* Assume Sandy Bridge. */
668 /* Assume Core i7. */
680 /* It is Core Duo. */
683 /* It is Pentium M. */
686 /* It is Pentium III. */
689 /* It is Pentium II. */
692 /* Default to Pentium Pro. */
696 /* For -mtune, we default to -mtune=generic. */
701 case PROCESSOR_PENTIUM4:
712 case PROCESSOR_GEODE:
716 if (arch && has_3dnow)
721 case PROCESSOR_ATHLON:
728 if (arch && has_sse3)
733 case PROCESSOR_AMDFAM10:
736 case PROCESSOR_BDVER1:
739 case PROCESSOR_BDVER2:
742 case PROCESSOR_BTVER1:
747 /* Use something reasonable. */
765 else if (has_cmpxchg8b)
774 const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
775 const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
776 const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
777 const char *ase = has_aes ? " -maes" : " -mno-aes";
778 const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
779 const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
780 const char *abm = has_abm ? " -mabm" : " -mno-abm";
781 const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
782 const char *fma = has_fma ? " -mfma" : " -mno-fma";
783 const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
784 const char *xop = has_xop ? " -mxop" : " -mno-xop";
785 const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
786 const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
787 const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
788 const char *avx = has_avx ? " -mavx" : " -mno-avx";
789 const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
790 const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
791 const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
792 const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
793 const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
794 const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
795 const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
797 options = concat (options, cx16, sahf, movbe, ase, pclmul,
798 popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
799 tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rdrnd,
800 f16c, fsgsbase, NULL);
804 return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
808 /* If we aren't compiling with GCC then the driver will just ignore
809 -march and -mtune "native" target and will leave to the newly
810 built compiler to generate code for its default target. */
812 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
813 const char **argv ATTRIBUTE_UNUSED)
817 #endif /* __GNUC__ */