1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; Condition code settings.
95 ;; none - insn does not affect cc
96 ;; none_0hit - insn does not affect cc but it does modify operand 0
97 ;; This attribute is used to keep track of when operand 0 changes.
98 ;; See the description of NOTICE_UPDATE_CC for more info.
99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
100 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
101 ;; compare - compare instruction
102 ;; clobber - value of cc is unknown
104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
105 (const_string "clobber"))
107 ;; Provide the maximum length of an assembly instruction in an asm
108 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
110 (define_asm_attributes
111 [(set (attr "length")
112 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
113 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
114 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
117 ;; ----------------------------------------------------------------------
119 ;; ----------------------------------------------------------------------
123 (define_insn "pushqi1_h8300"
124 [(parallel [(set (reg:HI SP_REG)
125 (plus:HI (reg:HI SP_REG) (const_int -2)))
126 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
127 (match_operand:QI 0 "register_operand" "r"))])]
129 && operands[0] != stack_pointer_rtx"
131 [(set_attr "length" "2")])
133 (define_insn "pushqi1_h8300hs"
134 [(parallel [(set (reg:SI SP_REG)
135 (plus:SI (reg:SI SP_REG) (const_int -4)))
136 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
137 (match_operand:QI 0 "register_operand" "r"))])]
138 "(TARGET_H8300H || TARGET_H8300S)
139 && operands[0] != stack_pointer_rtx"
141 [(set_attr "length" "4")])
143 (define_insn "pushqi1_h8300hs_normal"
144 [(parallel [(set (reg:HI SP_REG)
145 (plus:HI (reg:HI SP_REG) (const_int -4)))
146 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
147 (match_operand:QI 0 "register_operand" "r"))])]
148 "(TARGET_H8300H || TARGET_H8300S)
149 && operands[0] != stack_pointer_rtx"
151 [(set_attr "length" "4")])
153 (define_expand "pushqi1"
154 [(match_operand:QI 0 "register_operand" "")]
159 emit_insn (gen_pushqi1_h8300 (operands[0]));
160 else if (!TARGET_NORMAL_MODE)
161 emit_insn (gen_pushqi1_h8300hs (operands[0]));
163 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
167 (define_insn "*movqi_h8300"
168 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
169 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
171 && (register_operand (operands[0], QImode)
172 || register_operand (operands[1], QImode))"
180 [(set_attr "length" "2,2,2,2,4,4")
181 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
183 (define_insn "*movqi_h8300hs"
184 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
185 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
186 "(TARGET_H8300H || TARGET_H8300S)
187 && (register_operand (operands[0], QImode)
188 || register_operand (operands[1], QImode))"
196 [(set (attr "length")
197 (symbol_ref "compute_mov_length (operands)"))
198 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
200 (define_expand "movqi"
201 [(set (match_operand:QI 0 "general_operand_dst" "")
202 (match_operand:QI 1 "general_operand_src" ""))]
206 /* One of the ops has to be in a register. */
207 if (!register_operand (operand0, QImode)
208 && !register_operand (operand1, QImode))
210 operands[1] = copy_to_mode_reg (QImode, operand1);
214 (define_insn "movstrictqi"
215 [(set (strict_low_part
216 (match_operand:QI 0 "register_operand" "+r,r,r,r,r"))
217 (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
225 [(set (attr "length")
226 (symbol_ref "compute_mov_length (operands)"))
227 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
231 (define_expand "pushhi1_h8300"
232 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
233 (match_operand:HI 0 "register_operand" ""))]
235 && operands[0] != stack_pointer_rtx"
238 (define_insn "pushhi1_h8300hs"
239 [(parallel [(set (reg:SI SP_REG)
240 (plus:SI (reg:SI SP_REG) (const_int -4)))
241 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
242 (match_operand:HI 0 "register_operand" "r"))])]
243 "(TARGET_H8300H || TARGET_H8300S)
244 && operands[0] != stack_pointer_rtx"
246 [(set_attr "length" "4")])
248 (define_insn "pushhi1_h8300hs_normal"
249 [(parallel [(set (reg:HI SP_REG)
250 (plus:HI (reg:HI SP_REG) (const_int -4)))
251 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
252 (match_operand:HI 0 "register_operand" "r"))])]
253 "(TARGET_H8300H || TARGET_H8300S)
254 && operands[0] != stack_pointer_rtx"
256 [(set_attr "length" "4")])
258 (define_expand "pushhi1"
259 [(match_operand:HI 0 "register_operand" "")]
264 emit_insn (gen_pushhi1_h8300 (operands[0]));
265 else if (!TARGET_NORMAL_MODE)
266 emit_insn (gen_pushhi1_h8300hs (operands[0]));
268 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
272 (define_insn "*movhi_h8300"
273 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
274 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
276 && (register_operand (operands[0], HImode)
277 || register_operand (operands[1], HImode))
278 && !(GET_CODE (operands[0]) == MEM
279 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
280 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
281 && GET_CODE (operands[1]) == REG
282 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
290 [(set (attr "length")
291 (symbol_ref "compute_mov_length (operands)"))
292 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
294 (define_insn "*movhi_h8300hs"
295 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
296 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
297 "(TARGET_H8300H || TARGET_H8300S)
298 && (register_operand (operands[0], HImode)
299 || register_operand (operands[1], HImode))"
307 [(set (attr "length")
308 (symbol_ref "compute_mov_length (operands)"))
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
311 (define_expand "movhi"
312 [(set (match_operand:HI 0 "general_operand_dst" "")
313 (match_operand:HI 1 "general_operand_src" ""))]
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, HImode)
319 && !register_operand (operand0, HImode))
321 operands[1] = copy_to_mode_reg (HImode, operand1);
325 (define_insn "movstricthi"
326 [(set (strict_low_part
327 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
328 (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
336 [(set (attr "length")
337 (symbol_ref "compute_mov_length (operands)"))
338 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
342 (define_expand "movsi"
343 [(set (match_operand:SI 0 "general_operand_dst" "")
344 (match_operand:SI 1 "general_operand_src" ""))]
350 if (h8300_expand_movsi (operands))
355 /* One of the ops has to be in a register. */
356 if (!register_operand (operand1, SImode)
357 && !register_operand (operand0, SImode))
359 operands[1] = copy_to_mode_reg (SImode, operand1);
364 (define_expand "movsf"
365 [(set (match_operand:SF 0 "general_operand_dst" "")
366 (match_operand:SF 1 "general_operand_src" ""))]
372 if (h8300_expand_movsi (operands))
377 /* One of the ops has to be in a register. */
378 if (!register_operand (operand1, SFmode)
379 && !register_operand (operand0, SFmode))
381 operands[1] = copy_to_mode_reg (SFmode, operand1);
386 (define_insn "*movsi_h8300"
387 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
388 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
390 && (register_operand (operands[0], SImode)
391 || register_operand (operands[1], SImode))"
394 unsigned int rn = -1;
395 switch (which_alternative)
398 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
400 if (REGNO (operands[0]) < REGNO (operands[1]))
401 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
403 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
405 /* Make sure we don't trample the register we index with. */
406 if (GET_CODE (operands[1]) == MEM)
408 rtx inside = XEXP (operands[1], 0);
413 else if (GET_CODE (inside) == PLUS)
415 rtx lhs = XEXP (inside, 0);
416 rtx rhs = XEXP (inside, 1);
417 if (REG_P (lhs)) rn = REGNO (lhs);
418 if (REG_P (rhs)) rn = REGNO (rhs);
421 if (rn == REGNO (operands[0]))
423 /* Move the second word first. */
424 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
428 if (GET_CODE (operands[1]) == CONST_INT)
430 /* If either half is zero, use sub.w to clear that
432 if ((INTVAL (operands[1]) & 0xffff) == 0)
433 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
434 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
435 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
436 /* If the upper half and the lower half are the same,
437 copy one half to the other. */
438 if ((INTVAL (operands[1]) & 0xffff)
439 == ((INTVAL (operands[1]) >> 16) & 0xffff))
440 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
442 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
445 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
447 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
449 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
454 [(set (attr "length")
455 (symbol_ref "compute_mov_length (operands)"))])
457 (define_insn "*movsf_h8300"
458 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
459 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
461 && (register_operand (operands[0], SFmode)
462 || register_operand (operands[1], SFmode))"
465 /* Copy of the movsi stuff. */
466 unsigned int rn = -1;
467 switch (which_alternative)
470 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
472 if (REGNO (operands[0]) < REGNO (operands[1]))
473 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
475 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
477 /* Make sure we don't trample the register we index with. */
478 if (GET_CODE (operands[1]) == MEM)
480 rtx inside = XEXP (operands[1], 0);
485 else if (GET_CODE (inside) == PLUS)
487 rtx lhs = XEXP (inside, 0);
488 rtx rhs = XEXP (inside, 1);
489 if (REG_P (lhs)) rn = REGNO (lhs);
490 if (REG_P (rhs)) rn = REGNO (rhs);
493 if (rn == REGNO (operands[0]))
494 /* Move the second word first. */
495 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
497 /* Move the first word first. */
498 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
501 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
503 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
505 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
510 [(set (attr "length")
511 (symbol_ref "compute_mov_length (operands)"))])
513 (define_insn "*movsi_h8300hs"
514 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
515 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
516 "(TARGET_H8300S || TARGET_H8300H)
517 && (register_operand (operands[0], SImode)
518 || register_operand (operands[1], SImode))
519 && !(GET_CODE (operands[0]) == MEM
520 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
521 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
522 && GET_CODE (operands[1]) == REG
523 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
526 switch (which_alternative)
529 return \"sub.l %S0,%S0\";
533 return \"clrmac\;ldmac %1,macl\";
535 return \"stmac macl,%0\";
537 if (GET_CODE (operands[1]) == CONST_INT)
539 int val = INTVAL (operands[1]);
541 /* Look for constants which can be made by adding an 8-bit
542 number to zero in one of the two low bytes. */
543 if (val == (val & 0xff))
545 operands[1] = GEN_INT ((char) val & 0xff);
546 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
549 if (val == (val & 0xff00))
551 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
552 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
555 /* Look for constants that can be obtained by subs, inc, and
557 switch (val & 0xffffffff)
560 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
562 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
564 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
567 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
569 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
572 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
574 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
577 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
579 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
583 return \"mov.l %S1,%S0\";
585 [(set (attr "length")
586 (symbol_ref "compute_mov_length (operands)"))
587 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
589 (define_insn "*movsf_h8300hs"
590 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
591 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
592 "(TARGET_H8300H || TARGET_H8300S)
593 && (register_operand (operands[0], SFmode)
594 || register_operand (operands[1], SFmode))"
602 [(set (attr "length")
603 (symbol_ref "compute_mov_length (operands)"))
604 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
606 ;; ----------------------------------------------------------------------
608 ;; ----------------------------------------------------------------------
611 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
613 (match_operand 1 "const_int_operand" "n,n")))]
616 [(set_attr "length" "2,4")
617 (set_attr "cc" "set_zn,set_zn")])
620 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
622 (match_operand 1 "const_int_operand" "n")))]
625 [(set_attr "length" "2")
626 (set_attr "cc" "set_zn")])
628 (define_insn_and_split "*tst_extzv_1_n"
630 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
632 (match_operand 1 "const_int_operand" "n,n,n")))
633 (clobber (match_scratch:QI 2 "=X,X,&r"))]
634 "(TARGET_H8300H || TARGET_H8300S)"
640 && !EXTRA_CONSTRAINT (operands[0], 'U')"
643 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
646 (clobber (scratch:QI))])]
648 [(set_attr "length" "2,8,10")
649 (set_attr "cc" "set_zn,set_zn,set_zn")])
652 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
654 (match_operand 1 "const_int_operand" "n")))]
655 "(TARGET_H8300H || TARGET_H8300S)
656 && INTVAL (operands[1]) <= 15"
658 [(set_attr "length" "2")
659 (set_attr "cc" "set_zn")])
661 (define_insn_and_split "*tstsi_upper_bit"
663 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
665 (match_operand 1 "const_int_operand" "n")))
666 (clobber (match_scratch:SI 2 "=&r"))]
667 "(TARGET_H8300H || TARGET_H8300S)
668 && INTVAL (operands[1]) >= 16"
670 "&& reload_completed"
672 (ior:SI (and:SI (match_dup 2)
674 (lshiftrt:SI (match_dup 0)
677 (zero_extract:SI (match_dup 2)
680 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
682 (define_insn "*tstsi_variable_bit"
684 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
686 (and:SI (match_operand:SI 1 "register_operand" "r")
688 "TARGET_H8300H || TARGET_H8300S"
690 [(set_attr "length" "2")
691 (set_attr "cc" "set_zn")])
693 (define_insn_and_split "*tstsi_variable_bit_qi"
695 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
697 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
699 (clobber (match_scratch:QI 2 "=X,X,&r"))]
700 "(TARGET_H8300H || TARGET_H8300S)"
706 && !EXTRA_CONSTRAINT (operands[0], 'U')"
709 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
711 (and:SI (match_dup 1)
713 (clobber (scratch:QI))])]
715 [(set_attr "length" "2,8,10")
716 (set_attr "cc" "set_zn,set_zn,set_zn")])
719 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
722 [(set_attr "length" "2")
723 (set_attr "cc" "set_znv")])
726 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
729 [(set_attr "length" "2")
730 (set_attr "cc" "set_znv")])
732 (define_insn "*tsthi_upper"
734 (and:HI (match_operand:HI 0 "register_operand" "r")
738 [(set_attr "length" "2")
739 (set_attr "cc" "set_znv")])
742 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
743 "TARGET_H8300H || TARGET_H8300S"
745 [(set_attr "length" "2")
746 (set_attr "cc" "set_znv")])
748 (define_insn "*tstsi_upper"
750 (and:SI (match_operand:SI 0 "register_operand" "r")
751 (const_int -65536)))]
754 [(set_attr "length" "2")
755 (set_attr "cc" "set_znv")])
759 (compare (match_operand:QI 0 "register_operand" "r")
760 (match_operand:QI 1 "nonmemory_operand" "rn")))]
763 [(set_attr "length" "2")
764 (set_attr "cc" "compare")])
766 (define_expand "cmphi"
768 (compare (match_operand:HI 0 "register_operand" "")
769 (match_operand:HI 1 "nonmemory_operand" "")))]
773 /* Force operand1 into a register if we're compiling
775 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
776 operands[1] = force_reg (HImode, operands[1]);
779 (define_insn "*cmphi_h8300"
781 (compare (match_operand:HI 0 "register_operand" "r")
782 (match_operand:HI 1 "register_operand" "r")))]
785 [(set_attr "length" "2")
786 (set_attr "cc" "compare")])
788 (define_insn "*cmphi_h8300hs"
790 (compare (match_operand:HI 0 "register_operand" "r,r")
791 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
792 "TARGET_H8300H || TARGET_H8300S"
794 [(set_attr "length" "2,4")
795 (set_attr "cc" "compare,compare")])
799 (compare (match_operand:SI 0 "register_operand" "r,r")
800 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
801 "TARGET_H8300H || TARGET_H8300S"
803 [(set_attr "length" "2,6")
804 (set_attr "cc" "compare,compare")])
806 ;; ----------------------------------------------------------------------
808 ;; ----------------------------------------------------------------------
810 (define_insn "addqi3"
811 [(set (match_operand:QI 0 "register_operand" "=r")
812 (plus:QI (match_operand:QI 1 "register_operand" "%0")
813 (match_operand:QI 2 "nonmemory_operand" "rn")))]
816 [(set_attr "length" "2")
817 (set_attr "cc" "set_zn")])
819 (define_expand "addhi3"
820 [(set (match_operand:HI 0 "register_operand" "")
821 (plus:HI (match_operand:HI 1 "register_operand" "")
822 (match_operand:HI 2 "nonmemory_operand" "")))]
826 (define_insn "*addhi3_h8300"
827 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
828 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
829 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
835 add.b %s2,%s0\;addx %t2,%t0
837 [(set_attr "length" "2,2,2,4,2")
838 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
840 ;; This splitter is very important to make the stack adjustment
841 ;; interrupt-safe. The combination of add.b and addx is unsafe!
843 ;; We apply this split after the peephole2 pass so that we won't end
844 ;; up creating too many adds/subs when a scratch register is
845 ;; available, which is actually a common case because stack unrolling
846 ;; tends to happen immediately after a function call.
849 [(set (match_operand:HI 0 "stack_pointer_operand" "")
850 (plus:HI (match_dup 0)
851 (match_operand 1 "const_int_gt_2_operand" "")))]
852 "TARGET_H8300 && flow2_completed"
854 "split_adds_subs (HImode, operands); DONE;")
857 [(match_scratch:HI 2 "r")
858 (set (match_operand:HI 0 "stack_pointer_operand" "")
859 (plus:HI (match_dup 0)
860 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
865 (plus:HI (match_dup 0)
869 (define_insn "*addhi3_h8300hs"
870 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
871 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
872 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
873 "TARGET_H8300H || TARGET_H8300S"
880 [(set_attr "length" "2,2,2,4,2")
881 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
883 (define_insn "*addhi3_incdec"
884 [(set (match_operand:HI 0 "register_operand" "=r,r")
885 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
886 (match_operand:HI 2 "incdec_operand" "M,O")]
888 "TARGET_H8300H || TARGET_H8300S"
892 [(set_attr "length" "2,2")
893 (set_attr "cc" "set_zn,set_zn")])
896 [(set (match_operand:HI 0 "register_operand" "")
897 (plus:HI (match_dup 0)
898 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
901 "split_adds_subs (HImode, operands); DONE;")
903 (define_expand "addsi3"
904 [(set (match_operand:SI 0 "register_operand" "")
905 (plus:SI (match_operand:SI 1 "register_operand" "")
906 (match_operand:SI 2 "nonmemory_operand" "")))]
910 (define_insn "*addsi_h8300"
911 [(set (match_operand:SI 0 "register_operand" "=r,r")
912 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
913 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
915 "* return output_plussi (operands);"
916 [(set (attr "length")
917 (symbol_ref "compute_plussi_length (operands)"))
919 (symbol_ref "compute_plussi_cc (operands)"))])
921 (define_insn "*addsi_h8300hs"
922 [(set (match_operand:SI 0 "register_operand" "=r,r")
923 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
924 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
925 "TARGET_H8300H || TARGET_H8300S"
926 "* return output_plussi (operands);"
927 [(set (attr "length")
928 (symbol_ref "compute_plussi_length (operands)"))
930 (symbol_ref "compute_plussi_cc (operands)"))])
932 (define_insn "*addsi3_incdec"
933 [(set (match_operand:SI 0 "register_operand" "=r,r")
934 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
935 (match_operand:SI 2 "incdec_operand" "M,O")]
937 "TARGET_H8300H || TARGET_H8300S"
941 [(set_attr "length" "2,2")
942 (set_attr "cc" "set_zn,set_zn")])
945 [(set (match_operand:SI 0 "register_operand" "")
946 (plus:SI (match_dup 0)
947 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
948 "TARGET_H8300H || TARGET_H8300S"
950 "split_adds_subs (SImode, operands); DONE;")
952 ;; ----------------------------------------------------------------------
953 ;; SUBTRACT INSTRUCTIONS
954 ;; ----------------------------------------------------------------------
956 (define_insn "subqi3"
957 [(set (match_operand:QI 0 "register_operand" "=r")
958 (minus:QI (match_operand:QI 1 "register_operand" "0")
959 (match_operand:QI 2 "register_operand" "r")))]
962 [(set_attr "length" "2")
963 (set_attr "cc" "set_zn")])
965 (define_expand "subhi3"
966 [(set (match_operand:HI 0 "register_operand" "")
967 (minus:HI (match_operand:HI 1 "general_operand" "")
968 (match_operand:HI 2 "nonmemory_operand" "")))]
972 (define_insn "*subhi3_h8300"
973 [(set (match_operand:HI 0 "register_operand" "=r,r")
974 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
975 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
979 add.b %E2,%s0\;addx %F2,%t0"
980 [(set_attr "length" "2,4")
981 (set_attr "cc" "set_zn,clobber")])
983 (define_insn "*subhi3_h8300hs"
984 [(set (match_operand:HI 0 "register_operand" "=r,r")
985 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
986 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
987 "TARGET_H8300H || TARGET_H8300S"
991 [(set_attr "length" "2,4")
992 (set_attr "cc" "set_zn,set_zn")])
994 (define_expand "subsi3"
995 [(set (match_operand:SI 0 "register_operand" "")
996 (minus:SI (match_operand:SI 1 "register_operand" "")
997 (match_operand:SI 2 "nonmemory_operand" "")))]
1001 (define_insn "*subsi3_h8300"
1002 [(set (match_operand:SI 0 "register_operand" "=r")
1003 (minus:SI (match_operand:SI 1 "register_operand" "0")
1004 (match_operand:SI 2 "register_operand" "r")))]
1006 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1007 [(set_attr "length" "6")])
1009 (define_insn "*subsi3_h8300hs"
1010 [(set (match_operand:SI 0 "register_operand" "=r,r")
1011 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1012 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1013 "TARGET_H8300H || TARGET_H8300S"
1017 [(set_attr "length" "2,6")
1018 (set_attr "cc" "set_zn,set_zn")])
1020 ;; ----------------------------------------------------------------------
1021 ;; MULTIPLY INSTRUCTIONS
1022 ;; ----------------------------------------------------------------------
1024 ;; Note that the H8/300 can only handle umulqihi3.
1026 (define_insn "mulqihi3"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1029 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1030 "TARGET_H8300H || TARGET_H8300S"
1032 [(set_attr "length" "4")
1033 (set_attr "cc" "set_zn")])
1035 (define_insn "mulhisi3"
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1038 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1039 "TARGET_H8300H || TARGET_H8300S"
1041 [(set_attr "length" "4")
1042 (set_attr "cc" "set_zn")])
1044 (define_insn "umulqihi3"
1045 [(set (match_operand:HI 0 "register_operand" "=r")
1046 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1047 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1050 [(set_attr "length" "2")
1051 (set_attr "cc" "none_0hit")])
1053 (define_insn "umulhisi3"
1054 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1056 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1057 "TARGET_H8300H || TARGET_H8300S"
1059 [(set_attr "length" "2")
1060 (set_attr "cc" "none_0hit")])
1062 ;; This is a "bridge" instruction. Combine can't cram enough insns
1063 ;; together to crate a MAC instruction directly, but it can create
1064 ;; this instruction, which then allows combine to create the real
1067 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1068 ;; insn must generate reasonably correct code. Egad.
1070 [(set (match_operand:SI 0 "register_operand" "=a")
1073 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1075 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1077 "clrmac\;mac @%2+,@%1+"
1078 [(set_attr "length" "6")
1079 (set_attr "cc" "none_0hit")])
1082 [(set (match_operand:SI 0 "register_operand" "=a")
1084 (sign_extend:SI (mem:HI
1085 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1086 (sign_extend:SI (mem:HI
1087 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1088 (match_operand:SI 3 "register_operand" "0")))]
1091 [(set_attr "length" "4")
1092 (set_attr "cc" "none_0hit")])
1094 ;; ----------------------------------------------------------------------
1095 ;; DIVIDE/MOD INSTRUCTIONS
1096 ;; ----------------------------------------------------------------------
1098 (define_insn "udivmodqi4"
1099 [(set (match_operand:QI 0 "register_operand" "=r")
1102 (match_operand:HI 1 "register_operand" "0")
1103 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1104 (set (match_operand:QI 3 "register_operand" "=r")
1108 (zero_extend:HI (match_dup 2)))))]
1112 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1113 return \"divxu.b\\t%X2,%T0\";
1115 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1117 [(set_attr "length" "4")])
1119 (define_insn "divmodqi4"
1120 [(set (match_operand:QI 0 "register_operand" "=r")
1123 (match_operand:HI 1 "register_operand" "0")
1124 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1125 (set (match_operand:QI 3 "register_operand" "=r")
1129 (sign_extend:HI (match_dup 2)))))]
1130 "TARGET_H8300H || TARGET_H8300S"
1133 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1134 return \"divxs.b\\t%X2,%T0\";
1136 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1138 [(set_attr "length" "6")])
1140 (define_insn "udivmodhi4"
1141 [(set (match_operand:HI 0 "register_operand" "=r")
1144 (match_operand:SI 1 "register_operand" "0")
1145 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1146 (set (match_operand:HI 3 "register_operand" "=r")
1150 (zero_extend:SI (match_dup 2)))))]
1151 "TARGET_H8300H || TARGET_H8300S"
1154 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1155 return \"divxu.w\\t%T2,%S0\";
1157 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1159 [(set_attr "length" "4")])
1161 (define_insn "divmodhi4"
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1165 (match_operand:SI 1 "register_operand" "0")
1166 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1167 (set (match_operand:HI 3 "register_operand" "=r")
1171 (sign_extend:SI (match_dup 2)))))]
1172 "TARGET_H8300H || TARGET_H8300S"
1175 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1176 return \"divxs.w\\t%T2,%S0\";
1178 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1180 [(set_attr "length" "6")])
1182 ;; ----------------------------------------------------------------------
1184 ;; ----------------------------------------------------------------------
1186 (define_insn "*andqi3_1"
1187 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1188 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1189 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1190 "register_operand (operands[0], QImode)
1191 || single_zero_operand (operands[2], QImode)"
1195 [(set_attr "length" "2,8")
1196 (set_attr "cc" "set_znv,none_0hit")])
1198 (define_expand "andqi3"
1199 [(set (match_operand:QI 0 "bit_operand" "")
1200 (and:QI (match_operand:QI 1 "bit_operand" "")
1201 (match_operand:QI 2 "nonmemory_operand" "")))]
1205 if (fix_bit_operand (operands, 0, AND))
1209 (define_expand "andhi3"
1210 [(set (match_operand:HI 0 "register_operand" "")
1211 (and:HI (match_operand:HI 1 "register_operand" "")
1212 (match_operand:HI 2 "nonmemory_operand" "")))]
1216 (define_insn "*andorqi3"
1217 [(set (match_operand:QI 0 "register_operand" "=r")
1218 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1219 (match_operand:QI 3 "single_one_operand" "n"))
1220 (match_operand:QI 1 "register_operand" "0")))]
1222 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1223 [(set_attr "length" "6")])
1225 (define_insn "*andorhi3"
1226 [(set (match_operand:HI 0 "register_operand" "=r")
1227 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1228 (match_operand:HI 3 "single_one_operand" "n"))
1229 (match_operand:HI 1 "register_operand" "0")))]
1233 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1234 if (INTVAL (operands[3]) > 128)
1236 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1237 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1239 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1241 [(set_attr "length" "6")])
1243 (define_insn "*andorsi3"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1246 (match_operand:SI 3 "single_one_operand" "n"))
1247 (match_operand:SI 1 "register_operand" "0")))]
1248 "(INTVAL (operands[3]) & 0xffff) != 0"
1251 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1252 if (INTVAL (operands[3]) > 128)
1254 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1255 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1257 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1259 [(set_attr "length" "6")])
1261 (define_insn "*andorsi3_shift_8"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1266 (match_operand:SI 1 "register_operand" "0")))]
1269 [(set_attr "length" "2")])
1271 (define_expand "andsi3"
1272 [(set (match_operand:SI 0 "register_operand" "")
1273 (and:SI (match_operand:SI 1 "register_operand" "")
1274 (match_operand:SI 2 "nonmemory_operand" "")))]
1278 ;; ----------------------------------------------------------------------
1280 ;; ----------------------------------------------------------------------
1282 (define_insn "*iorqi3_1"
1283 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1284 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1285 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1286 "register_operand (operands[0], QImode)
1287 || single_one_operand (operands[2], QImode)"
1291 [(set_attr "length" "2,8")
1292 (set_attr "cc" "set_znv,none_0hit")])
1294 (define_expand "iorqi3"
1295 [(set (match_operand:QI 0 "bit_operand" "")
1296 (ior:QI (match_operand:QI 1 "bit_operand" "")
1297 (match_operand:QI 2 "nonmemory_operand" "")))]
1301 if (fix_bit_operand (operands, 1, IOR))
1305 (define_expand "iorhi3"
1306 [(set (match_operand:HI 0 "register_operand" "")
1307 (ior:HI (match_operand:HI 1 "register_operand" "")
1308 (match_operand:HI 2 "nonmemory_operand" "")))]
1312 (define_expand "iorsi3"
1313 [(set (match_operand:SI 0 "register_operand" "")
1314 (ior:SI (match_operand:SI 1 "register_operand" "")
1315 (match_operand:SI 2 "nonmemory_operand" "")))]
1319 ;; ----------------------------------------------------------------------
1321 ;; ----------------------------------------------------------------------
1323 (define_insn "*xorqi3_1"
1324 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1325 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1326 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1327 "register_operand (operands[0], QImode)
1328 || single_one_operand (operands[2], QImode)"
1332 [(set_attr "length" "2,8")
1333 (set_attr "cc" "set_znv,none_0hit")])
1335 (define_expand "xorqi3"
1336 [(set (match_operand:QI 0 "bit_operand" "")
1337 (xor:QI (match_operand:QI 1 "bit_operand" "")
1338 (match_operand:QI 2 "nonmemory_operand" "")))]
1342 if (fix_bit_operand (operands, 1, XOR))
1346 (define_expand "xorhi3"
1347 [(set (match_operand:HI 0 "register_operand" "")
1348 (xor:HI (match_operand:HI 1 "register_operand" "")
1349 (match_operand:HI 2 "nonmemory_operand" "")))]
1353 (define_expand "xorsi3"
1354 [(set (match_operand:SI 0 "register_operand" "")
1355 (xor:SI (match_operand:SI 1 "register_operand" "")
1356 (match_operand:SI 2 "nonmemory_operand" "")))]
1360 ;; ----------------------------------------------------------------------
1361 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1362 ;; ----------------------------------------------------------------------
1364 (define_insn "*logicalhi3"
1365 [(set (match_operand:HI 0 "register_operand" "=r")
1366 (match_operator:HI 3 "bit_operator"
1367 [(match_operand:HI 1 "register_operand" "%0")
1368 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1370 "* return output_logical_op (HImode, operands);"
1371 [(set (attr "length")
1372 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1374 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1376 (define_insn "*logicalsi3"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (match_operator:SI 3 "bit_operator"
1379 [(match_operand:SI 1 "register_operand" "%0")
1380 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1382 "* return output_logical_op (SImode, operands);"
1383 [(set (attr "length")
1384 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1386 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1388 ;; ----------------------------------------------------------------------
1389 ;; NEGATION INSTRUCTIONS
1390 ;; ----------------------------------------------------------------------
1392 (define_insn "negqi2"
1393 [(set (match_operand:QI 0 "register_operand" "=r")
1394 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1397 [(set_attr "length" "2")
1398 (set_attr "cc" "set_zn")])
1400 (define_expand "neghi2"
1401 [(set (match_operand:HI 0 "register_operand" "")
1402 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1408 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1413 (define_expand "neghi2_h8300"
1415 (not:HI (match_operand:HI 1 "register_operand" "")))
1416 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1417 (set (match_operand:HI 0 "register_operand" "")
1420 "operands[2] = gen_reg_rtx (HImode);")
1422 (define_insn "*neghi2_h8300hs"
1423 [(set (match_operand:HI 0 "register_operand" "=r")
1424 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1425 "TARGET_H8300H || TARGET_H8300S"
1427 [(set_attr "length" "2")
1428 (set_attr "cc" "set_zn")])
1430 (define_expand "negsi2"
1431 [(set (match_operand:SI 0 "register_operand" "")
1432 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1438 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1443 (define_expand "negsi2_h8300"
1445 (not:SI (match_operand:SI 1 "register_operand" "")))
1446 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1447 (set (match_operand:SI 0 "register_operand" "")
1450 "operands[2] = gen_reg_rtx (SImode);")
1452 (define_insn "*negsi2_h8300hs"
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1455 "TARGET_H8300H || TARGET_H8300S"
1457 [(set_attr "length" "2")
1458 (set_attr "cc" "set_zn")])
1460 (define_expand "negsf2"
1461 [(set (match_operand:SF 0 "register_operand" "")
1462 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1466 (define_insn "*negsf2_h8300"
1467 [(set (match_operand:SF 0 "register_operand" "=r")
1468 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1471 [(set_attr "length" "2")])
1473 (define_insn "*negsf2_h8300hs"
1474 [(set (match_operand:SF 0 "register_operand" "=r")
1475 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1476 "TARGET_H8300H || TARGET_H8300S"
1477 "xor.w\\t#32768,%e0"
1478 [(set_attr "length" "4")])
1480 ;; ----------------------------------------------------------------------
1481 ;; ABSOLUTE VALUE INSTRUCTIONS
1482 ;; ----------------------------------------------------------------------
1484 (define_expand "abssf2"
1485 [(set (match_operand:SF 0 "register_operand" "")
1486 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1490 (define_insn "*abssf2_h8300"
1491 [(set (match_operand:SF 0 "register_operand" "=r")
1492 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1495 [(set_attr "length" "2")])
1497 (define_insn "*abssf2_h8300hs"
1498 [(set (match_operand:SF 0 "register_operand" "=r")
1499 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1500 "TARGET_H8300H || TARGET_H8300S"
1501 "and.w\\t#32767,%e0"
1502 [(set_attr "length" "4")])
1504 ;; ----------------------------------------------------------------------
1506 ;; ----------------------------------------------------------------------
1508 (define_insn "one_cmplqi2"
1509 [(set (match_operand:QI 0 "register_operand" "=r")
1510 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1513 [(set_attr "length" "2")
1514 (set_attr "cc" "set_znv")])
1516 (define_expand "one_cmplhi2"
1517 [(set (match_operand:HI 0 "register_operand" "=r")
1518 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1522 (define_insn "*one_cmplhi2_h8300"
1523 [(set (match_operand:HI 0 "register_operand" "=r")
1524 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1527 [(set_attr "length" "4")])
1529 (define_insn "*one_cmplhi2_h8300hs"
1530 [(set (match_operand:HI 0 "register_operand" "=r")
1531 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1532 "TARGET_H8300H || TARGET_H8300S"
1534 [(set_attr "cc" "set_znv")
1535 (set_attr "length" "2")])
1537 (define_expand "one_cmplsi2"
1538 [(set (match_operand:SI 0 "register_operand" "=r")
1539 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1543 (define_insn "*one_complsi2_h8300"
1544 [(set (match_operand:SI 0 "register_operand" "=r")
1545 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1547 "not %w0\;not %x0\;not %y0\;not %z0"
1548 [(set_attr "length" "8")])
1550 (define_insn "*one_complsi2_h8300hs"
1551 [(set (match_operand:SI 0 "register_operand" "=r")
1552 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1553 "TARGET_H8300H || TARGET_H8300S"
1555 [(set_attr "cc" "set_znv")
1556 (set_attr "length" "2")])
1558 ;; ----------------------------------------------------------------------
1559 ;; JUMP INSTRUCTIONS
1560 ;; ----------------------------------------------------------------------
1562 ;; Conditional jump instructions
1564 (define_expand "ble"
1566 (if_then_else (le (cc0)
1568 (label_ref (match_operand 0 "" ""))
1573 (define_expand "bleu"
1575 (if_then_else (leu (cc0)
1577 (label_ref (match_operand 0 "" ""))
1582 (define_expand "bge"
1584 (if_then_else (ge (cc0)
1586 (label_ref (match_operand 0 "" ""))
1591 (define_expand "bgeu"
1593 (if_then_else (geu (cc0)
1595 (label_ref (match_operand 0 "" ""))
1600 (define_expand "blt"
1602 (if_then_else (lt (cc0)
1604 (label_ref (match_operand 0 "" ""))
1609 (define_expand "bltu"
1611 (if_then_else (ltu (cc0)
1613 (label_ref (match_operand 0 "" ""))
1618 (define_expand "bgt"
1620 (if_then_else (gt (cc0)
1622 (label_ref (match_operand 0 "" ""))
1627 (define_expand "bgtu"
1629 (if_then_else (gtu (cc0)
1631 (label_ref (match_operand 0 "" ""))
1636 (define_expand "beq"
1638 (if_then_else (eq (cc0)
1640 (label_ref (match_operand 0 "" ""))
1645 (define_expand "bne"
1647 (if_then_else (ne (cc0)
1649 (label_ref (match_operand 0 "" ""))
1654 (define_insn "branch_true"
1656 (if_then_else (match_operator 1 "comparison_operator"
1657 [(cc0) (const_int 0)])
1658 (label_ref (match_operand 0 "" ""))
1663 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1664 && (GET_CODE (operands[1]) == GT
1665 || GET_CODE (operands[1]) == GE
1666 || GET_CODE (operands[1]) == LE
1667 || GET_CODE (operands[1]) == LT))
1669 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1673 if (get_attr_length (insn) == 2)
1674 return \"b%j1 %l0\";
1675 else if (get_attr_length (insn) == 4)
1676 return \"b%j1 %l0:16\";
1678 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1680 [(set_attr "type" "branch")
1681 (set_attr "cc" "none")])
1683 (define_insn "branch_false"
1685 (if_then_else (match_operator 1 "comparison_operator"
1686 [(cc0) (const_int 0)])
1688 (label_ref (match_operand 0 "" ""))))]
1692 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1693 && (GET_CODE (operands[1]) == GT
1694 || GET_CODE (operands[1]) == GE
1695 || GET_CODE (operands[1]) == LE
1696 || GET_CODE (operands[1]) == LT))
1698 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1702 if (get_attr_length (insn) == 2)
1703 return \"b%k1 %l0\";
1704 else if (get_attr_length (insn) == 4)
1705 return \"b%k1 %l0:16\";
1707 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1709 [(set_attr "type" "branch")
1710 (set_attr "cc" "none")])
1712 ;; Unconditional and other jump instructions.
1716 (label_ref (match_operand 0 "" "")))]
1720 if (get_attr_length (insn) == 2)
1722 else if (get_attr_length (insn) == 4)
1723 return \"bra %l0:16\";
1725 return \"jmp @%l0\";
1727 [(set_attr "type" "branch")
1728 (set_attr "cc" "none")])
1730 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1732 (define_expand "tablejump"
1733 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1734 (use (label_ref (match_operand 1 "" "")))])]
1738 (define_insn "*tablejump_h8300"
1739 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1740 (use (label_ref (match_operand 1 "" "")))]
1743 [(set_attr "cc" "none")
1744 (set_attr "length" "2")])
1746 (define_insn "*tablejump_h8300hs_advanced"
1747 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1748 (use (label_ref (match_operand 1 "" "")))]
1749 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1751 [(set_attr "cc" "none")
1752 (set_attr "length" "2")])
1754 (define_insn "*tablejump_h8300hs_normal"
1755 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1756 (use (label_ref (match_operand 1 "" "")))]
1757 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1759 [(set_attr "cc" "none")
1760 (set_attr "length" "2")])
1762 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1764 (define_expand "indirect_jump"
1765 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1769 (define_insn "*indirect_jump_h8300"
1770 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1773 [(set_attr "cc" "none")
1774 (set_attr "length" "2")])
1776 (define_insn "*indirect_jump_h8300hs_advanced"
1777 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1778 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1780 [(set_attr "cc" "none")
1781 (set_attr "length" "2")])
1783 (define_insn "*indirect_jump_h8300hs_normal"
1784 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1785 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1787 [(set_attr "cc" "none")
1788 (set_attr "length" "2")])
1790 ;; Call subroutine with no return value.
1792 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1795 [(call (match_operand:QI 0 "call_insn_operand" "or")
1796 (match_operand:HI 1 "general_operand" "g"))]
1800 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1801 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1802 return \"jsr\\t@%0:8\";
1804 return \"jsr\\t%0\";
1806 [(set (attr "length")
1807 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1811 ;; Call subroutine, returning value in operand 0
1812 ;; (which must be a hard register).
1814 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1816 (define_insn "call_value"
1817 [(set (match_operand 0 "" "=r")
1818 (call (match_operand:QI 1 "call_insn_operand" "or")
1819 (match_operand:HI 2 "general_operand" "g")))]
1823 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1824 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1825 return \"jsr\\t@%1:8\";
1827 return \"jsr\\t%1\";
1829 [(set (attr "length")
1830 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1838 [(set_attr "cc" "none")
1839 (set_attr "length" "2")])
1841 ;; ----------------------------------------------------------------------
1842 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1843 ;; ----------------------------------------------------------------------
1845 (define_expand "push_h8300"
1846 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1847 (match_operand:HI 0 "register_operand" ""))]
1851 (define_expand "push_h8300hs_advanced"
1852 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1853 (match_operand:SI 0 "register_operand" ""))]
1854 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1857 (define_expand "push_h8300hs_normal"
1858 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1859 (match_operand:SI 0 "register_operand" ""))]
1860 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1863 (define_expand "pop_h8300"
1864 [(set (match_operand:HI 0 "register_operand" "")
1865 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1869 (define_expand "pop_h8300hs_advanced"
1870 [(set (match_operand:SI 0 "register_operand" "")
1871 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1872 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1875 (define_expand "pop_h8300hs_normal"
1876 [(set (match_operand:SI 0 "register_operand" "")
1877 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1878 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1881 (define_insn "stm_h8300s_2_advanced"
1883 [(set (reg:SI SP_REG)
1884 (plus:SI (reg:SI SP_REG) (const_int -8)))
1885 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1886 (match_operand:SI 0 "register_operand" ""))
1887 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1888 (match_operand:SI 1 "register_operand" ""))])]
1889 "TARGET_H8300S && !TARGET_NORMAL_MODE
1890 && h8300_regs_ok_for_stm (2, operands)"
1891 "stm.l\\t%S0-%S1,@-er7"
1892 [(set_attr "cc" "none")
1893 (set_attr "length" "4")])
1895 (define_insn "stm_h8300s_2_normal"
1897 [(set (reg:HI SP_REG)
1898 (plus:HI (reg:HI SP_REG) (const_int -8)))
1899 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1900 (match_operand:SI 0 "register_operand" ""))
1901 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1902 (match_operand:SI 1 "register_operand" ""))])]
1903 "TARGET_H8300S && TARGET_NORMAL_MODE
1904 && h8300_regs_ok_for_stm (2, operands)"
1905 "stm.l\\t%S0-%S1,@-er7"
1906 [(set_attr "cc" "none")
1907 (set_attr "length" "4")])
1909 (define_expand "stm_h8300s_2"
1910 [(match_operand:SI 0 "register_operand" "")
1911 (match_operand:SI 1 "register_operand" "")]
1913 && h8300_regs_ok_for_stm (2, operands)"
1916 if (!TARGET_NORMAL_MODE)
1917 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1919 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1923 (define_insn "stm_h8300s_3_advanced"
1925 [(set (reg:SI SP_REG)
1926 (plus:SI (reg:SI SP_REG) (const_int -12)))
1927 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1928 (match_operand:SI 0 "register_operand" ""))
1929 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1930 (match_operand:SI 1 "register_operand" ""))
1931 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1932 (match_operand:SI 2 "register_operand" ""))])]
1933 "TARGET_H8300S && !TARGET_NORMAL_MODE
1934 && h8300_regs_ok_for_stm (3, operands)"
1935 "stm.l\\t%S0-%S2,@-er7"
1936 [(set_attr "cc" "none")
1937 (set_attr "length" "4")])
1939 (define_insn "stm_h8300s_3_normal"
1941 [(set (reg:HI SP_REG)
1942 (plus:HI (reg:HI SP_REG) (const_int -12)))
1943 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1944 (match_operand:SI 0 "register_operand" ""))
1945 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1946 (match_operand:SI 1 "register_operand" ""))
1947 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1948 (match_operand:SI 2 "register_operand" ""))])]
1949 "TARGET_H8300S && TARGET_NORMAL_MODE
1950 && h8300_regs_ok_for_stm (3, operands)"
1951 "stm.l\\t%S0-%S2,@-er7"
1952 [(set_attr "cc" "none")
1953 (set_attr "length" "4")])
1955 (define_expand "stm_h8300s_3"
1956 [(match_operand:SI 0 "register_operand" "")
1957 (match_operand:SI 1 "register_operand" "")
1958 (match_operand:SI 2 "register_operand" "")]
1960 && h8300_regs_ok_for_stm (3, operands)"
1963 if (!TARGET_NORMAL_MODE)
1964 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
1967 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
1972 (define_insn "stm_h8300s_4_advanced"
1974 [(set (reg:SI SP_REG)
1975 (plus:SI (reg:SI SP_REG) (const_int -16)))
1976 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1977 (match_operand:SI 0 "register_operand" ""))
1978 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1979 (match_operand:SI 1 "register_operand" ""))
1980 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1981 (match_operand:SI 2 "register_operand" ""))
1982 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1983 (match_operand:SI 3 "register_operand" ""))])]
1984 "TARGET_H8300S && !TARGET_NORMAL_MODE
1985 && h8300_regs_ok_for_stm (4, operands)"
1986 "stm.l\\t%S0-%S3,@-er7"
1987 [(set_attr "cc" "none")
1988 (set_attr "length" "4")])
1990 (define_insn "stm_h8300s_4_normal"
1992 [(set (reg:HI SP_REG)
1993 (plus:HI (reg:HI SP_REG) (const_int -16)))
1994 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1995 (match_operand:SI 0 "register_operand" ""))
1996 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1997 (match_operand:SI 1 "register_operand" ""))
1998 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1999 (match_operand:SI 2 "register_operand" ""))
2000 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
2001 (match_operand:SI 3 "register_operand" ""))])]
2002 "TARGET_H8300S && TARGET_NORMAL_MODE
2003 && h8300_regs_ok_for_stm (4, operands)"
2004 "stm.l\\t%S0-%S3,@-er7"
2005 [(set_attr "cc" "none")
2006 (set_attr "length" "4")])
2008 (define_expand "stm_h8300s_4"
2009 [(match_operand:SI 0 "register_operand" "")
2010 (match_operand:SI 1 "register_operand" "")
2011 (match_operand:SI 2 "register_operand" "")
2012 (match_operand:SI 3 "register_operand" "")]
2014 && h8300_regs_ok_for_stm (4, operands)"
2017 if (!TARGET_NORMAL_MODE)
2018 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2019 operands[2], operands[3]));
2021 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2022 operands[2], operands[3]));
2026 (define_insn "ldm_h8300s_2_advanced"
2028 [(set (reg:SI SP_REG)
2029 (plus:SI (reg:SI SP_REG) (const_int 8)))
2030 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2031 (match_operand:SI 0 "register_operand" ""))
2032 (set (mem:SI (reg:SI SP_REG))
2033 (match_operand:SI 1 "register_operand" ""))])]
2034 "TARGET_H8300S && !TARGET_NORMAL_MODE
2035 && h8300_regs_ok_for_stm (2, operands)"
2036 "ldm.l\\t@er7+,%S0-%S1"
2037 [(set_attr "cc" "none")
2038 (set_attr "length" "4")])
2040 (define_insn "ldm_h8300s_2_normal"
2042 [(set (reg:HI SP_REG)
2043 (plus:HI (reg:HI SP_REG) (const_int 8)))
2044 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2045 (match_operand:SI 0 "register_operand" ""))
2046 (set (mem:SI (reg:HI SP_REG))
2047 (match_operand:SI 1 "register_operand" ""))])]
2048 "TARGET_H8300S && TARGET_NORMAL_MODE
2049 && h8300_regs_ok_for_stm (2, operands)"
2050 "ldm.l\\t@er7+,%S0-%S1"
2051 [(set_attr "cc" "none")
2052 (set_attr "length" "4")])
2054 (define_expand "ldm_h8300s_2"
2055 [(match_operand:SI 0 "register_operand" "")
2056 (match_operand:SI 1 "register_operand" "")]
2058 && h8300_regs_ok_for_stm (2, operands)"
2061 if (!TARGET_NORMAL_MODE)
2062 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2064 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2068 (define_insn "ldm_h8300s_3_advanced"
2070 [(set (reg:SI SP_REG)
2071 (plus:SI (reg:SI SP_REG) (const_int 12)))
2072 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2073 (match_operand:SI 0 "register_operand" ""))
2074 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2075 (match_operand:SI 1 "register_operand" ""))
2076 (set (mem:SI (reg:SI SP_REG))
2077 (match_operand:SI 2 "register_operand" ""))])]
2078 "TARGET_H8300S && !TARGET_NORMAL_MODE
2079 && h8300_regs_ok_for_stm (3, operands)"
2080 "ldm.l\\t@er7+,%S0-%S2"
2081 [(set_attr "cc" "none")
2082 (set_attr "length" "4")])
2084 (define_insn "ldm_h8300s_3_normal"
2086 [(set (reg:HI SP_REG)
2087 (plus:HI (reg:HI SP_REG) (const_int 12)))
2088 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2089 (match_operand:SI 0 "register_operand" ""))
2090 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2091 (match_operand:SI 1 "register_operand" ""))
2092 (set (mem:SI (reg:HI SP_REG))
2093 (match_operand:SI 2 "register_operand" ""))])]
2094 "TARGET_H8300S && TARGET_NORMAL_MODE
2095 && h8300_regs_ok_for_stm (3, operands)"
2096 "ldm.l\\t@er7+,%S0-%S2"
2097 [(set_attr "cc" "none")
2098 (set_attr "length" "4")])
2100 (define_expand "ldm_h8300s_3"
2101 [(match_operand:SI 0 "register_operand" "")
2102 (match_operand:SI 1 "register_operand" "")
2103 (match_operand:SI 2 "register_operand" "")]
2105 && h8300_regs_ok_for_stm (3, operands)"
2108 if (!TARGET_NORMAL_MODE)
2109 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2112 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2117 (define_insn "ldm_h8300s_4_advanced"
2119 [(set (reg:SI SP_REG)
2120 (plus:SI (reg:SI SP_REG) (const_int 16)))
2121 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2122 (match_operand:SI 0 "register_operand" ""))
2123 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2124 (match_operand:SI 1 "register_operand" ""))
2125 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2126 (match_operand:SI 2 "register_operand" ""))
2127 (set (mem:SI (reg:SI SP_REG))
2128 (match_operand:SI 3 "register_operand" ""))])]
2129 "TARGET_H8300S && !TARGET_NORMAL_MODE
2130 && h8300_regs_ok_for_stm (4, operands)"
2131 "ldm.l\\t@er7+,%S0-%S3"
2132 [(set_attr "cc" "none")
2133 (set_attr "length" "4")])
2135 (define_insn "ldm_h8300s_4_normal"
2137 [(set (reg:HI SP_REG)
2138 (plus:HI (reg:HI SP_REG) (const_int 16)))
2139 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2140 (match_operand:SI 0 "register_operand" ""))
2141 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2142 (match_operand:SI 1 "register_operand" ""))
2143 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2144 (match_operand:SI 2 "register_operand" ""))
2145 (set (mem:SI (reg:HI SP_REG))
2146 (match_operand:SI 3 "register_operand" ""))])]
2147 "TARGET_H8300S && !TARGET_NORMAL_MODE
2148 && h8300_regs_ok_for_stm (4, operands)"
2149 "ldm.l\\t@er7+,%S0-%S3"
2150 [(set_attr "cc" "none")
2151 (set_attr "length" "4")])
2153 (define_expand "ldm_h8300s_4"
2154 [(match_operand:SI 0 "register_operand" "")
2155 (match_operand:SI 1 "register_operand" "")
2156 (match_operand:SI 2 "register_operand" "")
2157 (match_operand:SI 3 "register_operand" "")]
2158 "TARGET_H8300S && !TARGET_NORMAL_MODE
2159 && h8300_regs_ok_for_stm (4, operands)"
2162 if (!TARGET_NORMAL_MODE)
2163 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2164 operands[2], operands[3]));
2166 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2167 operands[2], operands[3]));
2171 (define_expand "return"
2173 "h8300_can_use_return_insn_p ()"
2176 (define_insn "*return_1"
2181 if (h8300_current_function_interrupt_function_p ())
2186 [(set_attr "cc" "none")
2187 (set_attr "length" "2")])
2189 (define_expand "prologue"
2192 "h8300_expand_prologue (); DONE;")
2194 (define_expand "epilogue"
2197 "h8300_expand_epilogue ();")
2199 (define_insn "monitor_prologue"
2200 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2205 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2206 else if (TARGET_H8300H)
2207 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2208 else if (TARGET_H8300S)
2209 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2212 [(set_attr "length" "20")])
2214 ;; ----------------------------------------------------------------------
2215 ;; EXTEND INSTRUCTIONS
2216 ;; ----------------------------------------------------------------------
2218 (define_expand "zero_extendqihi2"
2219 [(set (match_operand:HI 0 "register_operand" "")
2220 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2224 (define_insn "*zero_extendqihi2_h8300"
2225 [(set (match_operand:HI 0 "register_operand" "=r,r")
2226 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2231 [(set_attr "length" "2,10")])
2233 (define_insn "*zero_extendqihi2_h8300hs"
2234 [(set (match_operand:HI 0 "register_operand" "=r,r")
2235 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2236 "TARGET_H8300H || TARGET_H8300S"
2240 [(set_attr "length" "2,10")
2241 (set_attr "cc" "set_znv,set_znv")])
2243 ;; Split the zero extension of a general operand (actually a memory
2244 ;; operand) into a load of the operand and the actual zero extension
2245 ;; so that 1) the length will be accurate, and 2) the zero extensions
2246 ;; appearing at the end of basic blocks may be merged.
2249 [(set (match_operand:HI 0 "register_operand" "")
2250 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2255 (zero_extend:HI (match_dup 2)))]
2256 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2258 (define_expand "zero_extendqisi2"
2259 [(set (match_operand:SI 0 "register_operand" "")
2260 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2264 (define_insn "*zero_extendqisi2_h8300"
2265 [(set (match_operand:SI 0 "register_operand" "=r,r")
2266 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2269 mov.b #0,%x0\;sub.w %e0,%e0
2270 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2271 [(set_attr "length" "4,8")])
2273 (define_insn "*zero_extendqisi2_h8300hs"
2274 [(set (match_operand:SI 0 "register_operand" "=r,r")
2275 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2276 "TARGET_H8300H || TARGET_H8300S"
2280 [(set (match_operand:SI 0 "register_operand" "")
2281 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2282 "(TARGET_H8300H || TARGET_H8300S)
2283 && reg_overlap_mentioned_p (operands[0], operands[1])
2284 && reload_completed"
2288 (zero_extend:HI (match_dup 2)))
2290 (zero_extend:SI (match_dup 3)))]
2291 "operands[2] = gen_lowpart (QImode, operands[0]);
2292 operands[3] = gen_lowpart (HImode, operands[0]);")
2295 [(set (match_operand:SI 0 "register_operand" "")
2296 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2297 "(TARGET_H8300H || TARGET_H8300S)
2298 && !reg_overlap_mentioned_p (operands[0], operands[1])
2299 && reload_completed"
2302 (set (strict_low_part (match_dup 2))
2304 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2306 (define_expand "zero_extendhisi2"
2307 [(set (match_operand:SI 0 "register_operand" "")
2308 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2312 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2313 (define_insn "*zero_extendhisi2_h8300"
2314 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2315 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2319 mov.w %f1,%f0\;sub.w %e0,%e0
2320 mov.w %e1,%f0\;sub.w %e0,%e0"
2321 [(set_attr "length" "2,4,6")])
2323 (define_insn "*zero_extendhisi2_h8300hs"
2324 [(set (match_operand:SI 0 "register_operand" "=r")
2325 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2326 "TARGET_H8300H || TARGET_H8300S"
2328 [(set_attr "length" "2")
2329 (set_attr "cc" "set_znv")])
2331 (define_expand "extendqihi2"
2332 [(set (match_operand:HI 0 "register_operand" "")
2333 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2337 (define_insn "*extendqihi2_h8300"
2338 [(set (match_operand:HI 0 "register_operand" "=r,r")
2339 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2342 bld #7,%s0\;subx %t0,%t0
2343 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2344 [(set_attr "length" "4,8")])
2346 (define_insn "*extendqihi2_h8300hs"
2347 [(set (match_operand:HI 0 "register_operand" "=r")
2348 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2349 "TARGET_H8300H || TARGET_H8300S"
2351 [(set_attr "length" "2")
2352 (set_attr "cc" "set_znv")])
2354 (define_expand "extendqisi2"
2355 [(set (match_operand:SI 0 "register_operand" "")
2356 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2360 (define_insn "*extendqisi2_h8300"
2361 [(set (match_operand:SI 0 "register_operand" "")
2362 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2365 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2366 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2367 [(set_attr "length" "8,12")])
2369 ;; The following pattern is needed because without the pattern, the
2370 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2371 ;; shifts, one ashift and one ashiftrt.
2373 (define_insn_and_split "*extendqisi2_h8300hs"
2374 [(set (match_operand:SI 0 "register_operand" "=r")
2375 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2376 "(TARGET_H8300H || TARGET_H8300S)"
2378 "&& reload_completed"
2380 (sign_extend:HI (match_dup 1)))
2382 (sign_extend:SI (match_dup 2)))]
2383 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2385 (define_expand "extendhisi2"
2386 [(set (match_operand:SI 0 "register_operand" "")
2387 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2391 (define_insn "*extendhisi2_h8300"
2392 [(set (match_operand:SI 0 "register_operand" "=r,r")
2393 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2396 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2397 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2398 [(set_attr "length" "6,10")])
2400 (define_insn "*extendhisi2_h8300hs"
2401 [(set (match_operand:SI 0 "register_operand" "=r")
2402 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2403 "TARGET_H8300H || TARGET_H8300S"
2405 [(set_attr "length" "2")
2406 (set_attr "cc" "set_znv")])
2408 ;; ----------------------------------------------------------------------
2410 ;; ----------------------------------------------------------------------
2412 ;; We make some attempt to provide real efficient shifting. One example is
2413 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2414 ;; reg and moving 0 into the former reg.
2416 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2417 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2418 ;; give the optimizer more cracks at the code. However, we wish to do things
2419 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2420 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2421 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2422 ;; to detect cases it can optimize.
2424 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2425 ;; easier "do it at insn emit time" route.
2429 (define_expand "ashlqi3"
2430 [(set (match_operand:QI 0 "register_operand" "")
2431 (ashift:QI (match_operand:QI 1 "register_operand" "")
2432 (match_operand:QI 2 "nonmemory_operand" "")))]
2434 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2436 (define_expand "ashrqi3"
2437 [(set (match_operand:QI 0 "register_operand" "")
2438 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2439 (match_operand:QI 2 "nonmemory_operand" "")))]
2441 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2443 (define_expand "lshrqi3"
2444 [(set (match_operand:QI 0 "register_operand" "")
2445 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2446 (match_operand:QI 2 "nonmemory_operand" "")))]
2448 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2450 (define_insn "*shiftqi"
2451 [(set (match_operand:QI 0 "register_operand" "=r,r")
2452 (match_operator:QI 3 "nshift_operator"
2453 [ (match_operand:QI 1 "register_operand" "0,0")
2454 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2455 (clobber (match_scratch:QI 4 "=X,&r"))]
2457 "* return output_a_shift (operands);"
2458 [(set (attr "length")
2459 (symbol_ref "compute_a_shift_length (insn, operands)"))
2461 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2465 (define_expand "ashlhi3"
2466 [(set (match_operand:HI 0 "register_operand" "")
2467 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2468 (match_operand:QI 2 "nonmemory_operand" "")))]
2470 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2472 (define_expand "lshrhi3"
2473 [(set (match_operand:HI 0 "register_operand" "")
2474 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2475 (match_operand:QI 2 "nonmemory_operand" "")))]
2477 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2479 (define_expand "ashrhi3"
2480 [(set (match_operand:HI 0 "register_operand" "")
2481 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2482 (match_operand:QI 2 "nonmemory_operand" "")))]
2484 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2486 (define_insn "*shifthi"
2487 [(set (match_operand:HI 0 "register_operand" "=r,r")
2488 (match_operator:HI 3 "nshift_operator"
2489 [ (match_operand:HI 1 "register_operand" "0,0")
2490 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2491 (clobber (match_scratch:QI 4 "=X,&r"))]
2493 "* return output_a_shift (operands);"
2494 [(set (attr "length")
2495 (symbol_ref "compute_a_shift_length (insn, operands)"))
2497 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2501 (define_expand "ashlsi3"
2502 [(set (match_operand:SI 0 "register_operand" "")
2503 (ashift:SI (match_operand:SI 1 "general_operand" "")
2504 (match_operand:QI 2 "nonmemory_operand" "")))]
2506 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2508 (define_expand "lshrsi3"
2509 [(set (match_operand:SI 0 "register_operand" "")
2510 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2511 (match_operand:QI 2 "nonmemory_operand" "")))]
2513 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2515 (define_expand "ashrsi3"
2516 [(set (match_operand:SI 0 "register_operand" "")
2517 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2518 (match_operand:QI 2 "nonmemory_operand" "")))]
2520 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2522 (define_insn "*shiftsi"
2523 [(set (match_operand:SI 0 "register_operand" "=r,r")
2524 (match_operator:SI 3 "nshift_operator"
2525 [ (match_operand:SI 1 "register_operand" "0,0")
2526 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2527 (clobber (match_scratch:QI 4 "=X,&r"))]
2529 "* return output_a_shift (operands);"
2530 [(set (attr "length")
2531 (symbol_ref "compute_a_shift_length (insn, operands)"))
2533 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2535 ;; Split a variable shift into a loop. If the register containing
2536 ;; the shift count dies, then we just use that register.
2540 [(set (match_operand 0 "register_operand" "")
2541 (match_operator 2 "nshift_operator"
2543 (match_operand:QI 1 "register_operand" "")]))
2544 (clobber (match_operand:QI 3 "register_operand" ""))])]
2546 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2550 (if_then_else (le (cc0) (const_int 0))
2551 (label_ref (match_dup 5))
2556 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2557 (clobber (scratch:QI))])
2559 (plus:QI (match_dup 1) (const_int -1)))
2563 (if_then_else (ne (cc0) (const_int 0))
2564 (label_ref (match_dup 4))
2567 "operands[4] = gen_label_rtx ();
2568 operands[5] = gen_label_rtx ();")
2572 [(set (match_operand 0 "register_operand" "")
2573 (match_operator 2 "nshift_operator"
2575 (match_operand:QI 1 "register_operand" "")]))
2576 (clobber (match_operand:QI 3 "register_operand" ""))])]
2578 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2584 (if_then_else (le (cc0) (const_int 0))
2585 (label_ref (match_dup 5))
2590 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2591 (clobber (scratch:QI))])
2593 (plus:QI (match_dup 3) (const_int -1)))
2597 (if_then_else (ne (cc0) (const_int 0))
2598 (label_ref (match_dup 4))
2601 "operands[4] = gen_label_rtx ();
2602 operands[5] = gen_label_rtx ();")
2604 ;; ----------------------------------------------------------------------
2606 ;; ----------------------------------------------------------------------
2608 (define_expand "rotlqi3"
2609 [(set (match_operand:QI 0 "register_operand" "")
2610 (rotate:QI (match_operand:QI 1 "register_operand" "")
2611 (match_operand:QI 2 "nonmemory_operand" "")))]
2613 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2615 (define_insn "*rotlqi3_1"
2616 [(set (match_operand:QI 0 "register_operand" "=r")
2617 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2618 (match_operand:QI 2 "immediate_operand" "")))]
2620 "* return output_a_rotate (ROTATE, operands);"
2621 [(set (attr "length")
2622 (symbol_ref "compute_a_rotate_length (operands)"))])
2624 (define_expand "rotlhi3"
2625 [(set (match_operand:HI 0 "register_operand" "")
2626 (rotate:HI (match_operand:HI 1 "register_operand" "")
2627 (match_operand:QI 2 "nonmemory_operand" "")))]
2629 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2631 (define_insn "*rotlhi3_1"
2632 [(set (match_operand:HI 0 "register_operand" "=r")
2633 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2634 (match_operand:QI 2 "immediate_operand" "")))]
2636 "* return output_a_rotate (ROTATE, operands);"
2637 [(set (attr "length")
2638 (symbol_ref "compute_a_rotate_length (operands)"))])
2640 (define_expand "rotlsi3"
2641 [(set (match_operand:SI 0 "register_operand" "")
2642 (rotate:SI (match_operand:SI 1 "register_operand" "")
2643 (match_operand:QI 2 "nonmemory_operand" "")))]
2644 "TARGET_H8300H || TARGET_H8300S"
2645 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2647 (define_insn "*rotlsi3_1"
2648 [(set (match_operand:SI 0 "register_operand" "=r")
2649 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2650 (match_operand:QI 2 "immediate_operand" "")))]
2651 "TARGET_H8300H || TARGET_H8300S"
2652 "* return output_a_rotate (ROTATE, operands);"
2653 [(set (attr "length")
2654 (symbol_ref "compute_a_rotate_length (operands)"))])
2656 ;; -----------------------------------------------------------------
2658 ;; -----------------------------------------------------------------
2659 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2660 ;; instructions so let's use them as well as we can.
2662 ;; You'll never believe all these patterns perform one basic action --
2663 ;; load a bit from the source, optionally invert the bit, then store it
2664 ;; in the destination (which is known to be zero).
2666 ;; Combine obviously need some work to better identify this situation and
2667 ;; canonicalize the form better.
2670 ;; Normal loads with a 16bit destination.
2674 [(set (match_operand:HI 0 "register_operand" "=&r")
2675 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2677 (match_operand:HI 2 "immediate_operand" "n")))]
2679 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2680 [(set_attr "length" "6")])
2683 ;; Inverted loads with a 16bit destination.
2687 [(set (match_operand:HI 0 "register_operand" "=&r")
2688 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2689 (match_operand:HI 3 "const_int_operand" "n"))
2691 (match_operand:HI 2 "const_int_operand" "n")))]
2693 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2694 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2695 [(set_attr "length" "8")])
2698 ;; Normal loads with a 32bit destination.
2701 (define_insn "*extzv_1_r_h8300"
2702 [(set (match_operand:SI 0 "register_operand" "=&r")
2703 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2705 (match_operand 2 "const_int_operand" "n")))]
2707 && INTVAL (operands[2]) < 16"
2708 "* return output_simode_bld (0, operands);"
2709 [(set_attr "length" "8")])
2711 (define_insn "*extzv_1_r_h8300hs"
2712 [(set (match_operand:SI 0 "register_operand" "=r,r")
2713 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2715 (match_operand 2 "const_int_operand" "n,n")))]
2716 "(TARGET_H8300H || TARGET_H8300S)
2717 && INTVAL (operands[2]) < 16"
2718 "* return output_simode_bld (0, operands);"
2719 [(set_attr "cc" "set_znv,set_znv")
2720 (set_attr "length" "8,6")])
2723 ;; Inverted loads with a 32bit destination.
2726 (define_insn "*extzv_1_r_inv_h8300"
2727 [(set (match_operand:SI 0 "register_operand" "=&r")
2728 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2729 (match_operand:HI 3 "const_int_operand" "n"))
2731 (match_operand 2 "const_int_operand" "n")))]
2733 && INTVAL (operands[2]) < 16
2734 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2735 "* return output_simode_bld (1, operands);"
2736 [(set_attr "length" "8")])
2738 (define_insn "*extzv_1_r_inv_h8300hs"
2739 [(set (match_operand:SI 0 "register_operand" "=r,r")
2740 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2741 (match_operand 3 "const_int_operand" "n,n"))
2743 (match_operand 2 "const_int_operand" "n,n")))]
2744 "(TARGET_H8300H || TARGET_H8300S)
2745 && INTVAL (operands[2]) < 16
2746 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2747 "* return output_simode_bld (1, operands);"
2748 [(set_attr "cc" "set_znv,set_znv")
2749 (set_attr "length" "8,6")])
2751 (define_expand "insv"
2752 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2753 (match_operand:HI 1 "general_operand" "")
2754 (match_operand:HI 2 "general_operand" ""))
2755 (match_operand:HI 3 "general_operand" ""))]
2759 /* We only have single bit bit-field instructions. */
2760 if (INTVAL (operands[1]) != 1)
2763 /* For now, we don't allow memory operands. */
2764 if (GET_CODE (operands[0]) == MEM
2765 || GET_CODE (operands[3]) == MEM)
2770 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2772 (match_operand:HI 1 "immediate_operand" "n"))
2773 (match_operand:HI 2 "register_operand" "r"))]
2775 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2776 [(set_attr "length" "4")])
2778 (define_expand "extzv"
2779 [(set (match_operand:HI 0 "register_operand" "")
2780 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2781 (match_operand:HI 2 "general_operand" "")
2782 (match_operand:HI 3 "general_operand" "")))]
2786 /* We only have single bit bit-field instructions. */
2787 if (INTVAL (operands[2]) != 1)
2790 /* For now, we don't allow memory operands. */
2791 if (GET_CODE (operands[1]) == MEM)
2795 ;; BAND, BOR, and BXOR patterns
2798 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2799 (match_operator:HI 4 "bit_operator"
2800 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2802 (match_operand:HI 2 "immediate_operand" "n"))
2803 (match_operand:HI 3 "bit_operand" "0")]))]
2805 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2806 [(set_attr "length" "6")])
2809 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2810 (match_operator:HI 5 "bit_operator"
2811 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2813 (match_operand:HI 2 "immediate_operand" "n"))
2814 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2816 (match_operand:HI 4 "immediate_operand" "n"))]))]
2818 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2819 [(set_attr "length" "6")])
2821 ;; -----------------------------------------------------------------
2823 ;; -----------------------------------------------------------------
2827 (define_insn "*insv_si_1_n"
2828 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2830 (match_operand:SI 1 "const_int_operand" "n"))
2831 (match_operand:SI 2 "register_operand" "r"))]
2832 "(TARGET_H8300H || TARGET_H8300S)
2833 && INTVAL (operands[1]) < 16"
2834 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2835 [(set_attr "length" "4")])
2837 (define_insn "*insv_si_1_n_lshiftrt"
2838 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2840 (match_operand:SI 1 "const_int_operand" "n"))
2841 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2842 (match_operand:SI 3 "const_int_operand" "n")))]
2843 "(TARGET_H8300H || TARGET_H8300S)
2844 && INTVAL (operands[1]) < 16
2845 && INTVAL (operands[3]) < 16"
2846 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2847 [(set_attr "length" "4")])
2849 (define_insn "*insv_si_1_n_lshiftrt_16"
2850 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2852 (match_operand:SI 1 "const_int_operand" "n"))
2853 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2855 "(TARGET_H8300H || TARGET_H8300S)
2856 && INTVAL (operands[1]) < 16"
2857 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2858 [(set_attr "length" "6")])
2860 (define_insn "*insv_si_8_8"
2861 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2864 (match_operand:SI 1 "register_operand" "r"))]
2865 "TARGET_H8300H || TARGET_H8300S"
2867 [(set_attr "length" "2")])
2869 (define_insn "*insv_si_8_8_lshiftrt_8"
2870 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2873 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2875 "TARGET_H8300H || TARGET_H8300S"
2877 [(set_attr "length" "2")])
2881 (define_insn "*extzv_8_8"
2882 [(set (match_operand:SI 0 "register_operand" "=r,r")
2883 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2886 "TARGET_H8300H || TARGET_H8300S"
2888 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2889 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2890 [(set_attr "cc" "set_znv,clobber")
2891 (set_attr "length" "6,4")])
2893 (define_insn "*extzv_8_16"
2894 [(set (match_operand:SI 0 "register_operand" "=r")
2895 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2898 "TARGET_H8300H || TARGET_H8300S"
2899 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2900 [(set_attr "cc" "set_znv")
2901 (set_attr "length" "6")])
2903 (define_insn "*extzv_16_8"
2904 [(set (match_operand:SI 0 "register_operand" "=r")
2905 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2908 (clobber (match_scratch:SI 2 "=&r"))]
2910 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2911 [(set_attr "length" "8")
2912 (set_attr "cc" "set_znv")])
2914 ;; Extract the exponent of a float.
2916 (define_insn_and_split "*extzv_8_23"
2917 [(set (match_operand:SI 0 "register_operand" "=r")
2918 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2921 "(TARGET_H8300H || TARGET_H8300S)"
2923 "&& reload_completed"
2924 [(parallel [(set (match_dup 0)
2925 (ashift:SI (match_dup 0)
2927 (clobber (scratch:QI))])
2928 (parallel [(set (match_dup 0)
2929 (lshiftrt:SI (match_dup 0)
2931 (clobber (scratch:QI))])]
2936 ;; ((SImode) HImode) << 15
2938 (define_insn_and_split "*twoshifts_l16_r1"
2939 [(set (match_operand:SI 0 "register_operand" "=r")
2940 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2942 (const_int 2147450880)))]
2943 "(TARGET_H8300H || TARGET_H8300S)"
2945 "&& reload_completed"
2946 [(parallel [(set (match_dup 0)
2947 (ashift:SI (match_dup 0)
2949 (clobber (scratch:QI))])
2950 (parallel [(set (match_dup 0)
2951 (lshiftrt:SI (match_dup 0)
2953 (clobber (scratch:QI))])]
2956 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2958 (define_insn_and_split "*andsi3_ashift_n_lower"
2959 [(set (match_operand:SI 0 "register_operand" "=r,r")
2960 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2961 (match_operand:QI 2 "const_int_operand" "S,n"))
2962 (match_operand:SI 3 "const_int_operand" "n,n")))
2963 (clobber (match_scratch:QI 4 "=X,&r"))]
2964 "(TARGET_H8300H || TARGET_H8300S)
2965 && INTVAL (operands[2]) <= 15
2966 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2968 "&& reload_completed"
2969 [(parallel [(set (match_dup 5)
2970 (ashift:HI (match_dup 5)
2972 (clobber (match_dup 4))])
2974 (zero_extend:SI (match_dup 5)))]
2975 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2977 ;; Accept (A >> 30) & 2 and the like.
2979 (define_insn "*andsi3_lshiftrt_n_sb"
2980 [(set (match_operand:SI 0 "register_operand" "=r")
2981 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2982 (match_operand:SI 2 "const_int_operand" "n"))
2983 (match_operand:SI 3 "single_one_operand" "n")))]
2984 "(TARGET_H8300H || TARGET_H8300S)
2985 && exact_log2 (INTVAL (operands[3])) < 16
2986 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2989 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2990 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2992 [(set_attr "length" "8")])
2994 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2995 [(set (match_operand:SI 0 "register_operand" "=r")
2996 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2998 (const_int 4194304)))]
2999 "(TARGET_H8300H || TARGET_H8300S)"
3001 "&& reload_completed"
3003 (and:SI (lshiftrt:SI (match_dup 0)
3006 (parallel [(set (match_dup 0)
3007 (ashift:SI (match_dup 0)
3009 (clobber (scratch:QI))])]
3014 (define_insn "*addsi3_upper"
3015 [(set (match_operand:SI 0 "register_operand" "=r")
3016 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3018 (match_operand:SI 2 "register_operand" "0")))]
3019 "TARGET_H8300H || TARGET_H8300S"
3021 [(set_attr "length" "2")])
3023 (define_insn "*addsi3_lshiftrt_16_zexthi"
3024 [(set (match_operand:SI 0 "register_operand" "=r")
3025 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3027 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3028 "TARGET_H8300H || TARGET_H8300S"
3029 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3030 [(set_attr "length" "6")])
3032 (define_insn_and_split "*addsi3_and_r_1"
3033 [(set (match_operand:SI 0 "register_operand" "=r")
3034 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3036 (match_operand:SI 2 "register_operand" "0")))]
3037 "(TARGET_H8300H || TARGET_H8300S)"
3039 "&& reload_completed"
3041 (zero_extract:SI (match_dup 1)
3045 (if_then_else (eq (cc0)
3047 (label_ref (match_dup 3))
3050 (plus:SI (match_dup 2)
3053 "operands[3] = gen_label_rtx ();")
3055 (define_insn_and_split "*addsi3_and_not_r_1"
3056 [(set (match_operand:SI 0 "register_operand" "=r")
3057 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3059 (match_operand:SI 2 "register_operand" "0")))]
3060 "(TARGET_H8300H || TARGET_H8300S)"
3062 "&& reload_completed"
3064 (zero_extract:SI (match_dup 1)
3068 (if_then_else (ne (cc0)
3070 (label_ref (match_dup 3))
3073 (plus:SI (match_dup 2)
3076 "operands[3] = gen_label_rtx ();")
3080 (define_insn "*ixorhi3_zext"
3081 [(set (match_operand:HI 0 "register_operand" "=r")
3082 (match_operator:HI 1 "iorxor_operator"
3083 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3084 (match_operand:HI 3 "register_operand" "0")]))]
3087 [(set_attr "length" "2")])
3091 (define_insn "*ixorsi3_zext_qi"
3092 [(set (match_operand:SI 0 "register_operand" "=r")
3093 (match_operator:SI 1 "iorxor_operator"
3094 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3095 (match_operand:SI 3 "register_operand" "0")]))]
3098 [(set_attr "length" "2")])
3100 (define_insn "*ixorsi3_zext_hi"
3101 [(set (match_operand:SI 0 "register_operand" "=r")
3102 (match_operator:SI 1 "iorxor_operator"
3103 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3104 (match_operand:SI 3 "register_operand" "0")]))]
3105 "TARGET_H8300H || TARGET_H8300S"
3107 [(set_attr "length" "2")])
3109 (define_insn "*ixorsi3_ashift_16"
3110 [(set (match_operand:SI 0 "register_operand" "=r")
3111 (match_operator:SI 1 "iorxor_operator"
3112 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3114 (match_operand:SI 3 "register_operand" "0")]))]
3115 "TARGET_H8300H || TARGET_H8300S"
3117 [(set_attr "length" "2")])
3119 (define_insn "*ixorsi3_lshiftrt_16"
3120 [(set (match_operand:SI 0 "register_operand" "=r")
3121 (match_operator:SI 1 "iorxor_operator"
3122 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3124 (match_operand:SI 3 "register_operand" "0")]))]
3125 "TARGET_H8300H || TARGET_H8300S"
3127 [(set_attr "length" "2")])
3131 (define_insn "*iorhi3_ashift_8"
3132 [(set (match_operand:HI 0 "register_operand" "=r")
3133 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3135 (match_operand:HI 2 "register_operand" "0")))]
3138 [(set_attr "length" "2")])
3140 (define_insn "*iorhi3_lshiftrt_8"
3141 [(set (match_operand:HI 0 "register_operand" "=r")
3142 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3144 (match_operand:HI 2 "register_operand" "0")))]
3147 [(set_attr "length" "2")])
3149 (define_insn "*iorhi3_two_qi"
3150 [(set (match_operand:HI 0 "register_operand" "=r")
3151 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3152 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3156 [(set_attr "length" "2")])
3158 (define_insn "*iorhi3_two_qi_mem"
3159 [(set (match_operand:HI 0 "register_operand" "=&r")
3160 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3161 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3164 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3165 [(set_attr "length" "16")])
3168 [(set (match_operand:HI 0 "register_operand" "")
3169 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3170 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3172 "(TARGET_H8300H || TARGET_H8300S)
3174 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3177 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3181 (define_insn "*iorsi3_two_hi"
3182 [(set (match_operand:SI 0 "register_operand" "=r")
3183 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3184 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3186 "TARGET_H8300H || TARGET_H8300S"
3188 [(set_attr "length" "2")])
3190 (define_insn_and_split "*iorsi3_two_qi_zext"
3191 [(set (match_operand:SI 0 "register_operand" "=&r")
3192 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3194 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3196 (const_int 65280))))]
3197 "(TARGET_H8300H || TARGET_H8300S)"
3199 "&& reload_completed"
3201 (ior:HI (zero_extend:HI (match_dup 1))
3202 (ashift:HI (subreg:HI (match_dup 2) 0)
3205 (zero_extend:SI (match_dup 3)))]
3206 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3208 (define_insn "*iorsi3_e2f"
3209 [(set (match_operand:SI 0 "register_operand" "=r")
3210 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3212 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3214 "TARGET_H8300H || TARGET_H8300S"
3216 [(set_attr "length" "2")])
3218 (define_insn_and_split "*iorsi3_two_qi_sext"
3219 [(set (match_operand:SI 0 "register_operand" "=r")
3220 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3221 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3223 "(TARGET_H8300H || TARGET_H8300S)"
3225 "&& reload_completed"
3227 (ior:HI (zero_extend:HI (match_dup 1))
3228 (ashift:HI (match_dup 4)
3231 (sign_extend:SI (match_dup 3)))]
3232 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3233 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3235 (define_insn "*iorsi3_w"
3236 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3237 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3239 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3240 "TARGET_H8300H || TARGET_H8300S"
3242 [(set_attr "length" "2,8")])
3244 (define_insn "*iorsi3_ashift_31"
3245 [(set (match_operand:SI 0 "register_operand" "=&r")
3246 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3248 (match_operand:SI 2 "register_operand" "0")))]
3249 "TARGET_H8300H || TARGET_H8300S"
3250 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3251 [(set_attr "length" "6")
3252 (set_attr "cc" "set_znv")])
3254 (define_insn "*iorsi3_and_ashift"
3255 [(set (match_operand:SI 0 "register_operand" "=r")
3256 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3257 (match_operand:SI 2 "const_int_operand" "n"))
3258 (match_operand:SI 3 "single_one_operand" "n"))
3259 (match_operand:SI 4 "register_operand" "0")))]
3260 "(TARGET_H8300H || TARGET_H8300S)
3261 && (INTVAL (operands[3]) & ~0xffff) == 0"
3264 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3265 - INTVAL (operands[2]));
3266 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3267 operands[2] = srcpos;
3268 operands[3] = dstpos;
3269 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3271 [(set_attr "length" "6")])
3273 (define_insn "*iorsi3_and_lshiftrt"
3274 [(set (match_operand:SI 0 "register_operand" "=r")
3275 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3276 (match_operand:SI 2 "const_int_operand" "n"))
3277 (match_operand:SI 3 "single_one_operand" "n"))
3278 (match_operand:SI 4 "register_operand" "0")))]
3279 "(TARGET_H8300H || TARGET_H8300S)
3280 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3283 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3284 + INTVAL (operands[2]));
3285 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3286 operands[2] = srcpos;
3287 operands[3] = dstpos;
3288 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3290 [(set_attr "length" "6")])
3292 (define_insn "*iorsi3_zero_extract"
3293 [(set (match_operand:SI 0 "register_operand" "=r")
3294 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3296 (match_operand:SI 2 "const_int_operand" "n"))
3297 (match_operand:SI 3 "register_operand" "0")))]
3298 "(TARGET_H8300H || TARGET_H8300S)
3299 && INTVAL (operands[2]) < 16"
3300 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3301 [(set_attr "length" "6")])
3303 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3304 [(set (match_operand:SI 0 "register_operand" "=r")
3305 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3308 (match_operand:SI 2 "register_operand" "0")))]
3309 "(TARGET_H8300H || TARGET_H8300S)"
3310 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3311 [(set_attr "length" "8")])
3313 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3314 [(set (match_operand:SI 0 "register_operand" "=r")
3315 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3317 (const_int 4194304))
3318 (match_operand:SI 2 "register_operand" "0")))
3319 (clobber (match_scratch:HI 3 "=&r"))]
3320 "(TARGET_H8300H || TARGET_H8300S)"
3323 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3324 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3326 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3328 [(set_attr "length" "10")])
3330 ;; Used to OR the exponent of a float.
3332 (define_insn "*iorsi3_shift"
3333 [(set (match_operand:SI 0 "register_operand" "=r")
3334 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3336 (match_operand:SI 2 "register_operand" "0")))
3337 (clobber (match_scratch:SI 3 "=&r"))]
3338 "TARGET_H8300H || TARGET_H8300S"
3343 [(set (match_operand:SI 0 "register_operand" "")
3344 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3347 (clobber (match_operand:SI 2 "register_operand" ""))])]
3348 "(TARGET_H8300H || TARGET_H8300S)
3350 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3351 && REGNO (operands[0]) != REGNO (operands[1])"
3352 [(parallel [(set (match_dup 3)
3353 (ashift:HI (match_dup 3)
3355 (clobber (scratch:QI))])
3357 (ior:SI (ashift:SI (match_dup 1)
3360 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3364 [(set (match_operand:SI 0 "register_operand" "")
3365 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3368 (clobber (match_operand:SI 2 "register_operand" ""))])]
3369 "(TARGET_H8300H || TARGET_H8300S)
3371 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3372 && REGNO (operands[0]) != REGNO (operands[1]))"
3375 (parallel [(set (match_dup 3)
3376 (ashift:HI (match_dup 3)
3378 (clobber (scratch:QI))])
3380 (ior:SI (ashift:SI (match_dup 2)
3383 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3385 (define_insn "*iorsi2_and_1_lshiftrt_1"
3386 [(set (match_operand:SI 0 "register_operand" "=r")
3387 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3389 (lshiftrt:SI (match_dup 1)
3391 "TARGET_H8300H || TARGET_H8300S"
3392 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3393 [(set_attr "length" "6")])
3395 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3396 [(set (match_operand:SI 0 "register_operand" "=r")
3397 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3399 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3401 "(TARGET_H8300H || TARGET_H8300S)"
3403 "&& reload_completed"
3405 (ior:HI (ashift:HI (match_dup 4)
3408 (parallel [(set (match_dup 0)
3409 (ashift:SI (match_dup 0)
3411 (clobber (scratch:QI))])]
3412 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3413 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3415 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3416 [(set (match_operand:SI 0 "register_operand" "=&r")
3417 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3419 (const_int 16711680))
3420 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3422 "(TARGET_H8300H || TARGET_H8300S)"
3424 "&& reload_completed"
3426 (ior:HI (zero_extend:HI (match_dup 1))
3427 (ashift:HI (subreg:HI (match_dup 2) 0)
3429 (parallel [(set (match_dup 0)
3430 (ashift:SI (match_dup 0)
3432 (clobber (scratch:QI))])]
3433 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3435 ;; Used to add the exponent of a float.
3437 (define_insn "*addsi3_shift"
3438 [(set (match_operand:SI 0 "register_operand" "=r")
3439 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3440 (const_int 8388608))
3441 (match_operand:SI 2 "register_operand" "0")))
3442 (clobber (match_scratch:SI 3 "=&r"))]
3443 "TARGET_H8300H || TARGET_H8300S"
3448 [(set (match_operand:SI 0 "register_operand" "")
3449 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3450 (const_int 8388608))
3452 (clobber (match_operand:SI 2 "register_operand" ""))])]
3453 "(TARGET_H8300H || TARGET_H8300S)
3455 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3456 && REGNO (operands[0]) != REGNO (operands[1])"
3457 [(parallel [(set (match_dup 3)
3458 (ashift:HI (match_dup 3)
3460 (clobber (scratch:QI))])
3462 (plus:SI (mult:SI (match_dup 1)
3465 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3469 [(set (match_operand:SI 0 "register_operand" "")
3470 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3471 (const_int 8388608))
3473 (clobber (match_operand:SI 2 "register_operand" ""))])]
3474 "(TARGET_H8300H || TARGET_H8300S)
3476 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3477 && REGNO (operands[0]) != REGNO (operands[1]))"
3480 (parallel [(set (match_dup 3)
3481 (ashift:HI (match_dup 3)
3483 (clobber (scratch:QI))])
3485 (plus:SI (mult:SI (match_dup 2)
3488 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3492 (define_insn_and_split "*ashiftsi_sextqi_7"
3493 [(set (match_operand:SI 0 "register_operand" "=r")
3494 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3496 "(TARGET_H8300H || TARGET_H8300S)"
3498 "&& reload_completed"
3499 [(parallel [(set (match_dup 2)
3500 (ashift:HI (match_dup 2)
3502 (clobber (scratch:QI))])
3504 (sign_extend:SI (match_dup 2)))
3505 (parallel [(set (match_dup 0)
3506 (ashiftrt:SI (match_dup 0)
3508 (clobber (scratch:QI))])]
3509 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3511 ;; Storing a part of HImode to QImode.
3514 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3515 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3519 [(set_attr "cc" "set_znv")
3520 (set_attr "length" "8")])
3522 ;; Storing a part of SImode to QImode.
3525 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3526 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3530 [(set_attr "cc" "set_znv")
3531 (set_attr "length" "8")])
3534 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3535 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3537 (clobber (match_scratch:SI 2 "=&r"))]
3538 "TARGET_H8300H || TARGET_H8300S"
3539 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3540 [(set_attr "cc" "set_znv")
3541 (set_attr "length" "10")])
3544 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3545 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3547 (clobber (match_scratch:SI 2 "=&r"))]
3548 "TARGET_H8300H || TARGET_H8300S"
3549 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3550 [(set_attr "cc" "set_znv")
3551 (set_attr "length" "10")])
3553 (define_insn_and_split ""
3555 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3559 (label_ref (match_operand 1 "" ""))
3567 (if_then_else (ge (cc0)
3569 (label_ref (match_dup 1))
3573 (define_insn_and_split ""
3575 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3579 (label_ref (match_operand 1 "" ""))
3587 (if_then_else (lt (cc0)
3589 (label_ref (match_dup 1))
3593 ;; -----------------------------------------------------------------
3594 ;; PEEPHOLE PATTERNS
3595 ;; -----------------------------------------------------------------
3597 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3601 [(set (match_operand:HI 0 "register_operand" "")
3602 (lshiftrt:HI (match_dup 0)
3603 (match_operand:HI 1 "const_int_operand" "")))
3604 (clobber (match_operand:HI 2 "" ""))])
3606 (and:HI (match_dup 0)
3607 (match_operand:HI 3 "const_int_operand" "")))]
3608 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3610 (and:HI (match_dup 0)
3614 (lshiftrt:HI (match_dup 0)
3616 (clobber (match_dup 2))])]
3619 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3623 [(set (match_operand:HI 0 "register_operand" "")
3624 (ashift:HI (match_dup 0)
3625 (match_operand:HI 1 "const_int_operand" "")))
3626 (clobber (match_operand:HI 2 "" ""))])
3628 (and:HI (match_dup 0)
3629 (match_operand:HI 3 "const_int_operand" "")))]
3630 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3632 (and:HI (match_dup 0)
3636 (ashift:HI (match_dup 0)
3638 (clobber (match_dup 2))])]
3641 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3645 [(set (match_operand:SI 0 "register_operand" "")
3646 (lshiftrt:SI (match_dup 0)
3647 (match_operand:SI 1 "const_int_operand" "")))
3648 (clobber (match_operand:SI 2 "" ""))])
3650 (and:SI (match_dup 0)
3651 (match_operand:SI 3 "const_int_operand" "")))]
3652 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3654 (and:SI (match_dup 0)
3658 (lshiftrt:SI (match_dup 0)
3660 (clobber (match_dup 2))])]
3663 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3667 [(set (match_operand:SI 0 "register_operand" "")
3668 (ashift:SI (match_dup 0)
3669 (match_operand:SI 1 "const_int_operand" "")))
3670 (clobber (match_operand:SI 2 "" ""))])
3672 (and:SI (match_dup 0)
3673 (match_operand:SI 3 "const_int_operand" "")))]
3674 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3676 (and:SI (match_dup 0)
3680 (ashift:SI (match_dup 0)
3682 (clobber (match_dup 2))])]
3685 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3689 [(set (match_operand:SI 0 "register_operand" "")
3690 (lshiftrt:SI (match_dup 0)
3691 (match_operand:SI 1 "const_int_operand" "")))
3692 (clobber (match_operand:SI 2 "" ""))])
3694 (and:SI (match_dup 0)
3695 (match_operand:SI 3 "const_int_operand" "")))]
3696 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3698 (and:SI (match_dup 0)
3702 (lshiftrt:SI (match_dup 0)
3704 (clobber (match_dup 2))])]
3707 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3711 [(set (match_operand:SI 0 "register_operand" "")
3712 (ashift:SI (match_dup 0)
3713 (match_operand:SI 1 "const_int_operand" "")))
3714 (clobber (match_operand:SI 2 "" ""))])
3716 (and:SI (match_dup 0)
3717 (match_operand:SI 3 "const_int_operand" "")))]
3718 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3720 (and:SI (match_dup 0)
3724 (ashift:SI (match_dup 0)
3726 (clobber (match_dup 2))])]
3729 ;; Convert a QImode push into an SImode push so that the
3730 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3733 [(parallel [(set (reg:SI SP_REG)
3734 (plus:SI (reg:SI SP_REG) (const_int -4)))
3735 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3736 (match_operand:QI 0 "register_operand" ""))])]
3737 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3738 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3740 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3743 [(parallel [(set (reg:HI SP_REG)
3744 (plus:HI (reg:HI SP_REG) (const_int -4)))
3745 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3746 (match_operand:QI 0 "register_operand" ""))])]
3747 "TARGET_H8300S && TARGET_NORMAL_MODE"
3748 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3750 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3752 ;; Convert a HImode push into an SImode push so that the
3753 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3756 [(parallel [(set (reg:SI SP_REG)
3757 (plus:SI (reg:SI SP_REG) (const_int -4)))
3758 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3759 (match_operand:HI 0 "register_operand" ""))])]
3760 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3761 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3763 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3766 [(parallel [(set (reg:HI SP_REG)
3767 (plus:HI (reg:HI SP_REG) (const_int -4)))
3768 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3769 (match_operand:HI 0 "register_operand" ""))])]
3770 "TARGET_H8300S && TARGET_NORMAL_MODE"
3771 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3773 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3775 ;; Cram four pushes into stm.l.
3778 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3779 (match_operand:SI 0 "register_operand" ""))
3780 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3781 (match_operand:SI 1 "register_operand" ""))
3782 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3783 (match_operand:SI 2 "register_operand" ""))
3784 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3785 (match_operand:SI 3 "register_operand" ""))]
3786 "TARGET_H8300S && !TARGET_NORMAL_MODE
3787 && REGNO (operands[0]) == 0
3788 && REGNO (operands[1]) == 1
3789 && REGNO (operands[2]) == 2
3790 && REGNO (operands[3]) == 3"
3791 [(parallel [(set (reg:SI SP_REG)
3792 (plus:SI (reg:SI SP_REG)
3794 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3796 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3798 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3800 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3805 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3806 (match_operand:SI 0 "register_operand" ""))
3807 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3808 (match_operand:SI 1 "register_operand" ""))
3809 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3810 (match_operand:SI 2 "register_operand" ""))
3811 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3812 (match_operand:SI 3 "register_operand" ""))]
3813 "TARGET_H8300S && TARGET_NORMAL_MODE
3814 && REGNO (operands[0]) == 0
3815 && REGNO (operands[1]) == 1
3816 && REGNO (operands[2]) == 2
3817 && REGNO (operands[3]) == 3"
3818 [(parallel [(set (reg:HI SP_REG)
3819 (plus:HI (reg:HI SP_REG)
3821 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3823 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3825 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3827 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3831 ;; Cram three pushes into stm.l.
3834 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3835 (match_operand:SI 0 "register_operand" ""))
3836 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3837 (match_operand:SI 1 "register_operand" ""))
3838 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3839 (match_operand:SI 2 "register_operand" ""))]
3840 "TARGET_H8300S && !TARGET_NORMAL_MODE
3841 && ((REGNO (operands[0]) == 0
3842 && REGNO (operands[1]) == 1
3843 && REGNO (operands[2]) == 2)
3844 || (REGNO (operands[0]) == 4
3845 && REGNO (operands[1]) == 5
3846 && REGNO (operands[2]) == 6))"
3847 [(parallel [(set (reg:SI SP_REG)
3848 (plus:SI (reg:SI SP_REG)
3850 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3852 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3854 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3859 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3860 (match_operand:SI 0 "register_operand" ""))
3861 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3862 (match_operand:SI 1 "register_operand" ""))
3863 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3864 (match_operand:SI 2 "register_operand" ""))]
3865 "TARGET_H8300S && TARGET_NORMAL_MODE
3866 && ((REGNO (operands[0]) == 0
3867 && REGNO (operands[1]) == 1
3868 && REGNO (operands[2]) == 2)
3869 || (REGNO (operands[0]) == 4
3870 && REGNO (operands[1]) == 5
3871 && REGNO (operands[2]) == 6))"
3872 [(parallel [(set (reg:HI SP_REG)
3873 (plus:HI (reg:HI SP_REG)
3875 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3877 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3879 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3883 ;; Cram two pushes into stm.l.
3886 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3887 (match_operand:SI 0 "register_operand" ""))
3888 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3889 (match_operand:SI 1 "register_operand" ""))]
3890 "TARGET_H8300S && !TARGET_NORMAL_MODE
3891 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3892 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3893 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3894 [(parallel [(set (reg:SI SP_REG)
3895 (plus:SI (reg:SI SP_REG)
3897 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3899 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3904 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3905 (match_operand:SI 0 "register_operand" ""))
3906 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3907 (match_operand:SI 1 "register_operand" ""))]
3908 "TARGET_H8300S && TARGET_NORMAL_MODE
3909 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3910 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3911 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3912 [(parallel [(set (reg:HI SP_REG)
3913 (plus:HI (reg:HI SP_REG)
3915 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3917 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3924 ;; add.w r7,r0 (6 bytes)
3929 ;; adds #2,r0 (4 bytes)
3932 [(set (match_operand:HI 0 "register_operand" "")
3933 (match_operand:HI 1 "const_int_operand" ""))
3935 (plus:HI (match_dup 0)
3936 (match_operand:HI 2 "register_operand" "")))]
3937 "REG_P (operands[0]) && REG_P (operands[2])
3938 && REGNO (operands[0]) != REGNO (operands[2])
3939 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3940 || CONST_OK_FOR_L (INTVAL (operands[1]))
3941 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3945 (plus:HI (match_dup 0)
3953 ;; add.l er7,er0 (6 bytes)
3958 ;; adds #4,er0 (4 bytes)
3961 [(set (match_operand:SI 0 "register_operand" "")
3962 (match_operand:SI 1 "const_int_operand" ""))
3964 (plus:SI (match_dup 0)
3965 (match_operand:SI 2 "register_operand" "")))]
3966 "(TARGET_H8300H || TARGET_H8300S)
3967 && REG_P (operands[0]) && REG_P (operands[2])
3968 && REGNO (operands[0]) != REGNO (operands[2])
3969 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3970 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3974 (plus:SI (match_dup 0)
3981 ;; add.l #10,er0 (takes 8 bytes)
3987 ;; add.l er7,er0 (takes 6 bytes)
3990 [(set (match_operand:SI 0 "register_operand" "")
3991 (match_operand:SI 1 "register_operand" ""))
3993 (plus:SI (match_dup 0)
3994 (match_operand:SI 2 "const_int_operand" "")))]
3995 "(TARGET_H8300H || TARGET_H8300S)
3996 && REG_P (operands[0]) && REG_P (operands[1])
3997 && REGNO (operands[0]) != REGNO (operands[1])
3998 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3999 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4000 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4001 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4002 || INTVAL (operands[2]) == 0xffff
4003 || INTVAL (operands[2]) == 0xfffe)"
4007 (plus:SI (match_dup 0)
4023 [(set (match_operand:HI 0 "register_operand" "")
4024 (plus:HI (match_dup 0)
4025 (match_operand 1 "incdec_operand" "")))
4029 (if_then_else (match_operator 3 "eqne_operator"
4030 [(cc0) (const_int 0)])
4031 (label_ref (match_operand 2 "" ""))
4033 "TARGET_H8300H || TARGET_H8300S"
4034 [(set (match_operand:HI 0 "register_operand" "")
4035 (unspec:HI [(match_dup 0)
4041 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4042 (label_ref (match_dup 2))
4046 ;; The SImode version of the previous pattern.
4049 [(set (match_operand:SI 0 "register_operand" "")
4050 (plus:SI (match_dup 0)
4051 (match_operand 1 "incdec_operand" "")))
4055 (if_then_else (match_operator 3 "eqne_operator"
4056 [(cc0) (const_int 0)])
4057 (label_ref (match_operand 2 "" ""))
4059 "TARGET_H8300H || TARGET_H8300S"
4060 [(set (match_operand:SI 0 "register_operand" "")
4061 (unspec:SI [(match_dup 0)
4067 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4068 (label_ref (match_dup 2))
4073 [(parallel [(set (cc0)
4074 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4077 (clobber (scratch:QI))])
4079 (if_then_else (match_operator 1 "eqne_operator"
4080 [(cc0) (const_int 0)])
4081 (label_ref (match_operand 2 "" ""))
4083 "(TARGET_H8300H || TARGET_H8300S)"
4087 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4088 (label_ref (match_dup 2))
4090 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4091 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4092 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4094 ;; The next three peephole2's will try to transform
4096 ;; mov.b A,r0l (or mov.l A,er0)
4103 ;; and.b #CST,r0l (if CST is not 255)
4106 [(set (match_operand:QI 0 "register_operand" "")
4107 (match_operand:QI 1 "general_operand" ""))
4108 (set (match_operand:SI 2 "register_operand" "")
4109 (and:SI (match_dup 2)
4111 "(TARGET_H8300H || TARGET_H8300S)
4112 && !reg_overlap_mentioned_p (operands[2], operands[1])
4113 && REGNO (operands[0]) == REGNO (operands[2])"
4116 (set (strict_low_part (match_dup 0))
4121 [(set (match_operand:SI 0 "register_operand" "")
4122 (match_operand:SI 1 "general_operand" ""))
4124 (and:SI (match_dup 0)
4126 "(TARGET_H8300H || TARGET_H8300S)
4127 && !reg_overlap_mentioned_p (operands[0], operands[1])
4128 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4131 (set (strict_low_part (match_dup 2))
4133 "operands[2] = gen_lowpart (QImode, operands[0]);
4134 operands[3] = gen_lowpart (QImode, operands[1]);")
4137 [(set (match_operand 0 "register_operand" "")
4138 (match_operand 1 "general_operand" ""))
4139 (set (match_operand:SI 2 "register_operand" "")
4140 (and:SI (match_dup 2)
4141 (match_operand:SI 3 "const_int_qi_operand" "")))]
4142 "(TARGET_H8300H || TARGET_H8300S)
4143 && (GET_MODE (operands[0]) == QImode
4144 || GET_MODE (operands[0]) == HImode
4145 || GET_MODE (operands[0]) == SImode)
4146 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4147 && REGNO (operands[0]) == REGNO (operands[2])
4148 && !reg_overlap_mentioned_p (operands[2], operands[1])
4149 && !(GET_MODE (operands[1]) != QImode
4150 && GET_CODE (operands[1]) == MEM
4151 && MEM_VOLATILE_P (operands[1]))"
4154 (set (strict_low_part (match_dup 4))
4157 (and:SI (match_dup 2)
4159 "operands[4] = gen_lowpart (QImode, operands[0]);
4160 operands[5] = gen_lowpart (QImode, operands[1]);
4161 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4164 [(set (match_operand:SI 0 "register_operand" "")
4165 (match_operand:SI 1 "register_operand" ""))
4167 (and:SI (match_dup 0)
4168 (const_int 65280)))]
4169 "(TARGET_H8300H || TARGET_H8300S)
4170 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4173 (set (zero_extract:SI (match_dup 0)
4176 (lshiftrt:SI (match_dup 1)
4180 ;; If a load of mem:SI is followed by an AND that turns off the upper
4181 ;; half, then we can load mem:HI instead.
4184 [(set (match_operand:SI 0 "register_operand" "")
4185 (match_operand:SI 1 "memory_operand" ""))
4187 (and:SI (match_dup 0)
4188 (match_operand:SI 2 "const_int_operand" "")))]
4189 "(TARGET_H8300H || TARGET_H8300S)
4190 && !MEM_VOLATILE_P (operands[1])
4191 && (INTVAL (operands[2]) & ~0xffff) == 0
4192 && INTVAL (operands[2]) != 255"
4196 (and:SI (match_dup 0)
4198 "operands[3] = gen_lowpart (HImode, operands[0]);
4199 operands[4] = gen_lowpart (HImode, operands[1]);")
4201 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4202 ;; the equivalent with shorter sequences. Here is the summary. Cases
4203 ;; are grouped for each define_peephole2.
4205 ;; reg const_int use insn
4206 ;; --------------------------------------------------------
4207 ;; dead -2 eq/ne inc.l
4208 ;; dead -1 eq/ne inc.l
4209 ;; dead 1 eq/ne dec.l
4210 ;; dead 2 eq/ne dec.l
4212 ;; dead 1 geu/ltu shar.l
4213 ;; dead 3 (H8S) geu/ltu shar.l
4215 ;; ---- 255 geu/ltu mov.b
4229 (compare (match_operand:HI 0 "register_operand" "")
4230 (match_operand:HI 1 "incdec_operand" "")))
4232 (if_then_else (match_operator 3 "eqne_operator"
4233 [(cc0) (const_int 0)])
4234 (label_ref (match_operand 2 "" ""))
4236 "(TARGET_H8300H || TARGET_H8300S)
4237 && peep2_reg_dead_p (1, operands[0])"
4239 (unspec:HI [(match_dup 0)
4245 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4246 (label_ref (match_dup 2))
4248 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4262 (compare (match_operand:HI 0 "register_operand" "")
4263 (match_operand:HI 1 "const_int_operand" "")))
4265 (if_then_else (match_operator 2 "gtle_operator"
4266 [(cc0) (const_int 0)])
4267 (label_ref (match_operand 3 "" ""))
4269 "(TARGET_H8300H || TARGET_H8300S)
4270 && peep2_reg_dead_p (1, operands[0])
4271 && (INTVAL (operands[1]) == 1
4272 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4273 [(parallel [(set (match_dup 0)
4274 (ashiftrt:HI (match_dup 0)
4276 (clobber (scratch:QI))])
4280 (if_then_else (match_dup 4)
4281 (label_ref (match_dup 3))
4283 "switch (GET_CODE (operands[2]))
4286 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4289 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4292 operands[4] = operands[2];
4295 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4309 (compare (match_operand:HI 0 "register_operand" "")
4312 (if_then_else (match_operator 1 "gtle_operator"
4313 [(cc0) (const_int 0)])
4314 (label_ref (match_operand 2 "" ""))
4316 "TARGET_H8300H || TARGET_H8300S"
4318 (and:HI (match_dup 0)
4321 (if_then_else (match_dup 3)
4322 (label_ref (match_dup 2))
4324 "switch (GET_CODE (operands[1]))
4327 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4330 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4333 operands[3] = operands[1];
4337 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4338 ;; the equivalent with shorter sequences. Here is the summary. Cases
4339 ;; are grouped for each define_peephole2.
4341 ;; reg const_int use insn
4342 ;; --------------------------------------------------------
4343 ;; live -2 eq/ne copy and inc.l
4344 ;; live -1 eq/ne copy and inc.l
4345 ;; live 1 eq/ne copy and dec.l
4346 ;; live 2 eq/ne copy and dec.l
4348 ;; dead -2 eq/ne inc.l
4349 ;; dead -1 eq/ne inc.l
4350 ;; dead 1 eq/ne dec.l
4351 ;; dead 2 eq/ne dec.l
4353 ;; dead -131072 eq/ne inc.w and test
4354 ;; dead -65536 eq/ne inc.w and test
4355 ;; dead 65536 eq/ne dec.w and test
4356 ;; dead 131072 eq/ne dec.w and test
4358 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4359 ;; dead 0x0000??00 eq/ne xor.b and test
4360 ;; dead 0x0000ffff eq/ne not.w and test
4362 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4363 ;; dead 0xffff??ff eq/ne xor.b and not.l
4364 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4365 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4367 ;; live 1 geu/ltu copy and shar.l
4368 ;; live 3 (H8S) geu/ltu copy and shar.l
4370 ;; dead 1 geu/ltu shar.l
4371 ;; dead 3 (H8S) geu/ltu shar.l
4373 ;; dead 3 (H8/300H) geu/ltu and.b and test
4374 ;; dead 7 geu/ltu and.b and test
4375 ;; dead 15 geu/ltu and.b and test
4376 ;; dead 31 geu/ltu and.b and test
4377 ;; dead 63 geu/ltu and.b and test
4378 ;; dead 127 geu/ltu and.b and test
4379 ;; dead 255 geu/ltu and.b and test
4381 ;; ---- 65535 geu/ltu mov.w
4383 ;; For a small constant, it is cheaper to actually do the subtraction
4384 ;; and then test the register.
4388 (compare (match_operand:SI 0 "register_operand" "")
4389 (match_operand:SI 1 "incdec_operand" "")))
4391 (if_then_else (match_operator 3 "eqne_operator"
4392 [(cc0) (const_int 0)])
4393 (label_ref (match_operand 2 "" ""))
4395 "(TARGET_H8300H || TARGET_H8300S)
4396 && peep2_reg_dead_p (1, operands[0])"
4398 (unspec:SI [(match_dup 0)
4404 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4405 (label_ref (match_dup 2))
4407 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4411 (compare (match_operand:SI 0 "register_operand" "")
4412 (match_operand:SI 1 "const_int_operand" "")))
4414 (if_then_else (match_operator 3 "eqne_operator"
4415 [(cc0) (const_int 0)])
4416 (label_ref (match_operand 2 "" ""))
4418 "(TARGET_H8300H || TARGET_H8300S)
4419 && peep2_reg_dead_p (1, operands[0])
4420 && (INTVAL (operands[1]) == -131072
4421 || INTVAL (operands[1]) == -65536
4422 || INTVAL (operands[1]) == 65536
4423 || INTVAL (operands[1]) == 131072)"
4425 (plus:SI (match_dup 0)
4430 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4431 (label_ref (match_dup 2))
4433 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4435 ;; For certain (in)equality comparisons against a constant, we can
4436 ;; XOR the register with the constant, and test the register against
4441 (compare (match_operand:SI 0 "register_operand" "")
4442 (match_operand:SI 1 "const_int_operand" "")))
4444 (if_then_else (match_operator 3 "eqne_operator"
4445 [(cc0) (const_int 0)])
4446 (label_ref (match_operand 2 "" ""))
4448 "(TARGET_H8300H || TARGET_H8300S)
4449 && peep2_reg_dead_p (1, operands[0])
4450 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4451 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4452 || INTVAL (operands[1]) == 0x0000ffff)
4453 && INTVAL (operands[1]) != 1
4454 && INTVAL (operands[1]) != 2"
4456 (xor:SI (match_dup 0)
4461 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4462 (label_ref (match_dup 2))
4468 (compare (match_operand:SI 0 "register_operand" "")
4469 (match_operand:SI 1 "const_int_operand" "")))
4471 (if_then_else (match_operator 3 "eqne_operator"
4472 [(cc0) (const_int 0)])
4473 (label_ref (match_operand 2 "" ""))
4475 "(TARGET_H8300H || TARGET_H8300S)
4476 && peep2_reg_dead_p (1, operands[0])
4477 && ((INTVAL (operands[1]) | 0x00ff) == -1
4478 || (INTVAL (operands[1]) | 0xff00) == -1)
4479 && INTVAL (operands[1]) != -1
4480 && INTVAL (operands[1]) != -2"
4482 (xor:SI (match_dup 0)
4485 (not:SI (match_dup 0)))
4489 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4490 (label_ref (match_dup 2))
4492 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4496 (compare (match_operand:SI 0 "register_operand" "")
4497 (match_operand:SI 1 "const_int_operand" "")))
4499 (if_then_else (match_operator 3 "eqne_operator"
4500 [(cc0) (const_int 0)])
4501 (label_ref (match_operand 2 "" ""))
4503 "(TARGET_H8300H || TARGET_H8300S)
4504 && peep2_reg_dead_p (1, operands[0])
4505 && (INTVAL (operands[1]) == -2147483647 - 1
4506 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4508 (rotate:SI (match_dup 0)
4511 (unspec:SI [(match_dup 0)
4517 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4518 (label_ref (match_dup 2))
4520 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4533 ;; We avoid this transformation if we see more than one copy of the
4534 ;; same compare insn immediately before this one.
4537 [(match_scratch:SI 4 "r")
4539 (compare (match_operand:SI 0 "register_operand" "")
4540 (match_operand:SI 1 "const_int_operand" "")))
4542 (if_then_else (match_operator 2 "gtle_operator"
4543 [(cc0) (const_int 0)])
4544 (label_ref (match_operand 3 "" ""))
4546 "(TARGET_H8300H || TARGET_H8300S)
4547 && !peep2_reg_dead_p (1, operands[0])
4548 && (INTVAL (operands[1]) == 1
4549 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4550 && !same_cmp_preceding_p (insn)"
4553 (parallel [(set (match_dup 4)
4554 (ashiftrt:SI (match_dup 4)
4556 (clobber (scratch:QI))])
4560 (if_then_else (match_dup 5)
4561 (label_ref (match_dup 3))
4563 "switch (GET_CODE (operands[2]))
4566 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4569 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4572 operands[5] = operands[2];
4575 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4589 (compare (match_operand:SI 0 "register_operand" "")
4590 (match_operand:SI 1 "const_int_operand" "")))
4592 (if_then_else (match_operator 2 "gtle_operator"
4593 [(cc0) (const_int 0)])
4594 (label_ref (match_operand 3 "" ""))
4596 "(TARGET_H8300H || TARGET_H8300S)
4597 && peep2_reg_dead_p (1, operands[0])
4598 && (INTVAL (operands[1]) == 1
4599 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4600 [(parallel [(set (match_dup 0)
4601 (ashiftrt:SI (match_dup 0)
4603 (clobber (scratch:QI))])
4607 (if_then_else (match_dup 4)
4608 (label_ref (match_dup 3))
4610 "switch (GET_CODE (operands[2]))
4613 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4616 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4619 operands[4] = operands[2];
4622 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4637 (compare (match_operand:SI 0 "register_operand" "")
4638 (match_operand:SI 1 "const_int_operand" "")))
4640 (if_then_else (match_operator 2 "gtle_operator"
4641 [(cc0) (const_int 0)])
4642 (label_ref (match_operand 3 "" ""))
4644 "(TARGET_H8300H || TARGET_H8300S)
4645 && peep2_reg_dead_p (1, operands[0])
4646 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4647 || INTVAL (operands[1]) == 7
4648 || INTVAL (operands[1]) == 15
4649 || INTVAL (operands[1]) == 31
4650 || INTVAL (operands[1]) == 63
4651 || INTVAL (operands[1]) == 127
4652 || INTVAL (operands[1]) == 255)"
4654 (and:SI (match_dup 0)
4659 (if_then_else (match_dup 4)
4660 (label_ref (match_dup 3))
4662 "switch (GET_CODE (operands[2]))
4665 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4668 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4671 operands[4] = operands[2];
4674 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4676 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4680 (compare (match_operand:SI 0 "register_operand" "")
4683 (if_then_else (match_operator 1 "gtle_operator"
4684 [(cc0) (const_int 0)])
4685 (label_ref (match_operand 2 "" ""))
4687 "TARGET_H8300H || TARGET_H8300S"
4689 (and:SI (match_dup 0)
4690 (const_int -65536)))
4692 (if_then_else (match_dup 3)
4693 (label_ref (match_dup 2))
4695 "switch (GET_CODE (operands[1]))
4698 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4701 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4704 operands[3] = operands[1];
4708 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4709 ;; of the register being tested, do the subtraction on the copy, and
4710 ;; then test the copy. We avoid this transformation if we see more
4711 ;; than one copy of the same compare insn.
4714 [(match_scratch:SI 4 "r")
4716 (compare (match_operand:SI 0 "register_operand" "")
4717 (match_operand:SI 1 "incdec_operand" "")))
4719 (if_then_else (match_operator 3 "eqne_operator"
4720 [(cc0) (const_int 0)])
4721 (label_ref (match_operand 2 "" ""))
4723 "(TARGET_H8300H || TARGET_H8300S)
4724 && !peep2_reg_dead_p (1, operands[0])
4725 && !same_cmp_following_p (insn)"
4729 (unspec:SI [(match_dup 4)
4735 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4736 (label_ref (match_dup 2))
4738 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4740 ;; Narrow the mode of testing if possible.
4743 [(set (match_operand:HI 0 "register_operand" "")
4744 (and:HI (match_dup 0)
4745 (match_operand:HI 1 "const_int_qi_operand" "")))
4749 (if_then_else (match_operator 3 "eqne_operator"
4750 [(cc0) (const_int 0)])
4751 (label_ref (match_operand 2 "" ""))
4753 "peep2_reg_dead_p (2, operands[0])"
4755 (and:QI (match_dup 4)
4760 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4761 (label_ref (match_dup 2))
4763 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4764 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4767 [(set (match_operand:SI 0 "register_operand" "")
4768 (and:SI (match_dup 0)
4769 (match_operand:SI 1 "const_int_qi_operand" "")))
4773 (if_then_else (match_operator 3 "eqne_operator"
4774 [(cc0) (const_int 0)])
4775 (label_ref (match_operand 2 "" ""))
4777 "peep2_reg_dead_p (2, operands[0])"
4779 (and:QI (match_dup 4)
4784 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4785 (label_ref (match_dup 2))
4787 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4788 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4791 [(set (match_operand:SI 0 "register_operand" "")
4792 (and:SI (match_dup 0)
4793 (match_operand:SI 1 "const_int_hi_operand" "")))
4797 (if_then_else (match_operator 3 "eqne_operator"
4798 [(cc0) (const_int 0)])
4799 (label_ref (match_operand 2 "" ""))
4801 "peep2_reg_dead_p (2, operands[0])"
4803 (and:HI (match_dup 4)
4808 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4809 (label_ref (match_dup 2))
4811 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4812 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4815 [(set (match_operand:SI 0 "register_operand" "")
4816 (and:SI (match_dup 0)
4817 (match_operand:SI 1 "const_int_qi_operand" "")))
4819 (xor:SI (match_dup 0)
4820 (match_operand:SI 2 "const_int_qi_operand" "")))
4824 (if_then_else (match_operator 4 "eqne_operator"
4825 [(cc0) (const_int 0)])
4826 (label_ref (match_operand 3 "" ""))
4828 "peep2_reg_dead_p (3, operands[0])
4829 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4831 (and:QI (match_dup 5)
4834 (xor:QI (match_dup 5)
4839 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4840 (label_ref (match_dup 3))
4842 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4843 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4844 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
4846 ;; These triggers right at the end of allocation of locals in the
4847 ;; prologue (and possibly at other places).
4849 ;; stack adjustment of -8, generate one push
4851 ;; before : 14 bytes, 22 clocks
4852 ;; after : 8 bytes, 20 clocks
4855 [(set (reg:SI SP_REG)
4856 (plus:SI (reg:SI SP_REG)
4858 (set (mem:SI (reg:SI SP_REG))
4859 (match_operand:SI 0 "register_operand" ""))]
4860 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4861 && REGNO (operands[0]) != SP_REG"
4862 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4866 ;; stack adjustment of -12, generate one push
4868 ;; before : 10 bytes, 14 clocks
4869 ;; after : 8 bytes, 14 clocks
4872 [(set (reg:SI SP_REG)
4873 (plus:SI (reg:SI SP_REG)
4875 (set (mem:SI (reg:SI SP_REG))
4876 (match_operand:SI 0 "register_operand" ""))]
4877 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4878 && REGNO (operands[0]) != SP_REG"
4879 [(set (reg:SI SP_REG)
4880 (plus:SI (reg:SI SP_REG)
4882 (set (reg:SI SP_REG)
4883 (plus:SI (reg:SI SP_REG)
4885 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))