1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; Condition code settings.
95 ;; none - insn does not affect cc
96 ;; none_0hit - insn does not affect cc but it does modify operand 0
97 ;; This attribute is used to keep track of when operand 0 changes.
98 ;; See the description of NOTICE_UPDATE_CC for more info.
99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
100 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
101 ;; compare - compare instruction
102 ;; clobber - value of cc is unknown
104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
105 (const_string "clobber"))
107 ;; Provide the maximum length of an assembly instruction in an asm
108 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
110 (define_asm_attributes
111 [(set (attr "length")
112 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
113 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
114 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
117 ;; ----------------------------------------------------------------------
119 ;; ----------------------------------------------------------------------
123 (define_insn "pushqi1_h8300"
124 [(set (reg:HI SP_REG)
125 (plus:HI (reg:HI SP_REG) (const_int -2)))
126 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
127 (match_operand:QI 0 "register_operand" "r"))]
129 && operands[0] != stack_pointer_rtx"
131 [(set_attr "length" "2")])
133 (define_insn "pushqi1_h8300hs"
134 [(set (reg:SI SP_REG)
135 (plus:SI (reg:SI SP_REG) (const_int -4)))
136 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
137 (match_operand:QI 0 "register_operand" "r"))]
138 "(TARGET_H8300H || TARGET_H8300S)
139 && operands[0] != stack_pointer_rtx"
141 [(set_attr "length" "4")])
143 (define_insn "pushqi1_h8300hs_normal"
144 [(set (reg:HI SP_REG)
145 (plus:HI (reg:HI SP_REG) (const_int -4)))
146 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
147 (match_operand:QI 0 "register_operand" "r"))]
148 "(TARGET_H8300H || TARGET_H8300S)
149 && operands[0] != stack_pointer_rtx"
151 [(set_attr "length" "4")])
153 (define_expand "pushqi1"
154 [(match_operand:QI 0 "register_operand" "")]
159 emit_insn (gen_pushqi1_h8300 (operands[0]));
160 else if (!TARGET_NORMAL_MODE)
161 emit_insn (gen_pushqi1_h8300hs (operands[0]));
163 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
167 (define_insn "*movqi_h8300"
168 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
169 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
171 && (register_operand (operands[0], QImode)
172 || register_operand (operands[1], QImode))"
180 [(set_attr "length" "2,2,2,2,4,4")
181 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
183 (define_insn "*movqi_h8300hs"
184 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
185 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
186 "(TARGET_H8300H || TARGET_H8300S)
187 && (register_operand (operands[0], QImode)
188 || register_operand (operands[1], QImode))"
196 [(set (attr "length")
197 (symbol_ref "compute_mov_length (operands)"))
198 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
200 (define_expand "movqi"
201 [(set (match_operand:QI 0 "general_operand_dst" "")
202 (match_operand:QI 1 "general_operand_src" ""))]
206 /* One of the ops has to be in a register. */
207 if (!register_operand (operand0, QImode)
208 && !register_operand (operand1, QImode))
210 operands[1] = copy_to_mode_reg (QImode, operand1);
214 (define_insn "movstrictqi"
215 [(set (strict_low_part
216 (match_operand:QI 0 "register_operand" "+r,r,r,r,r"))
217 (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
225 [(set (attr "length")
226 (symbol_ref "compute_mov_length (operands)"))
227 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
231 (define_expand "pushhi1_h8300"
232 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
233 (match_operand:HI 0 "register_operand" ""))]
235 && operands[0] != stack_pointer_rtx"
238 (define_insn "pushhi1_h8300hs"
239 [(set (reg:SI SP_REG)
240 (plus:SI (reg:SI SP_REG) (const_int -4)))
241 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
242 (match_operand:HI 0 "register_operand" "r"))]
243 "(TARGET_H8300H || TARGET_H8300S)
244 && operands[0] != stack_pointer_rtx"
246 [(set_attr "length" "4")])
248 (define_insn "pushhi1_h8300hs_normal"
249 [(set (reg:HI SP_REG)
250 (plus:HI (reg:HI SP_REG) (const_int -4)))
251 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
252 (match_operand:HI 0 "register_operand" "r"))]
253 "(TARGET_H8300H || TARGET_H8300S)
254 && operands[0] != stack_pointer_rtx"
256 [(set_attr "length" "4")])
258 (define_expand "pushhi1"
259 [(match_operand:HI 0 "register_operand" "")]
264 emit_insn (gen_pushhi1_h8300 (operands[0]));
265 else if (!TARGET_NORMAL_MODE)
266 emit_insn (gen_pushhi1_h8300hs (operands[0]));
268 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
272 (define_insn "*movhi_h8300"
273 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
274 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
276 && (register_operand (operands[0], HImode)
277 || register_operand (operands[1], HImode))
278 && !(GET_CODE (operands[0]) == MEM
279 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
280 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
281 && GET_CODE (operands[1]) == REG
282 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
290 [(set (attr "length")
291 (symbol_ref "compute_mov_length (operands)"))
292 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
294 (define_insn "*movhi_h8300hs"
295 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
296 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
297 "(TARGET_H8300H || TARGET_H8300S)
298 && (register_operand (operands[0], HImode)
299 || register_operand (operands[1], HImode))"
307 [(set (attr "length")
308 (symbol_ref "compute_mov_length (operands)"))
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
311 (define_expand "movhi"
312 [(set (match_operand:HI 0 "general_operand_dst" "")
313 (match_operand:HI 1 "general_operand_src" ""))]
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, HImode)
319 && !register_operand (operand0, HImode))
321 operands[1] = copy_to_mode_reg (HImode, operand1);
325 (define_insn "movstricthi"
326 [(set (strict_low_part
327 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
328 (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
336 [(set (attr "length")
337 (symbol_ref "compute_mov_length (operands)"))
338 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
342 (define_expand "movsi"
343 [(set (match_operand:SI 0 "general_operand_dst" "")
344 (match_operand:SI 1 "general_operand_src" ""))]
350 if (h8300_expand_movsi (operands))
355 /* One of the ops has to be in a register. */
356 if (!register_operand (operand1, SImode)
357 && !register_operand (operand0, SImode))
359 operands[1] = copy_to_mode_reg (SImode, operand1);
364 (define_expand "movsf"
365 [(set (match_operand:SF 0 "general_operand_dst" "")
366 (match_operand:SF 1 "general_operand_src" ""))]
372 if (h8300_expand_movsi (operands))
377 /* One of the ops has to be in a register. */
378 if (!register_operand (operand1, SFmode)
379 && !register_operand (operand0, SFmode))
381 operands[1] = copy_to_mode_reg (SFmode, operand1);
386 (define_insn "*movsi_h8300"
387 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
388 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
390 && (register_operand (operands[0], SImode)
391 || register_operand (operands[1], SImode))"
394 unsigned int rn = -1;
395 switch (which_alternative)
398 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
400 if (REGNO (operands[0]) < REGNO (operands[1]))
401 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
403 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
405 /* Make sure we don't trample the register we index with. */
406 if (GET_CODE (operands[1]) == MEM)
408 rtx inside = XEXP (operands[1], 0);
413 else if (GET_CODE (inside) == PLUS)
415 rtx lhs = XEXP (inside, 0);
416 rtx rhs = XEXP (inside, 1);
417 if (REG_P (lhs)) rn = REGNO (lhs);
418 if (REG_P (rhs)) rn = REGNO (rhs);
421 if (rn == REGNO (operands[0]))
423 /* Move the second word first. */
424 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
428 if (GET_CODE (operands[1]) == CONST_INT)
430 /* If either half is zero, use sub.w to clear that
432 if ((INTVAL (operands[1]) & 0xffff) == 0)
433 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
434 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
435 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
436 /* If the upper half and the lower half are the same,
437 copy one half to the other. */
438 if ((INTVAL (operands[1]) & 0xffff)
439 == ((INTVAL (operands[1]) >> 16) & 0xffff))
440 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
442 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
445 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
447 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
449 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
454 [(set (attr "length")
455 (symbol_ref "compute_mov_length (operands)"))])
457 (define_insn "*movsf_h8300"
458 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
459 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
461 && (register_operand (operands[0], SFmode)
462 || register_operand (operands[1], SFmode))"
465 /* Copy of the movsi stuff. */
466 unsigned int rn = -1;
467 switch (which_alternative)
470 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
472 if (REGNO (operands[0]) < REGNO (operands[1]))
473 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
475 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
477 /* Make sure we don't trample the register we index with. */
478 if (GET_CODE (operands[1]) == MEM)
480 rtx inside = XEXP (operands[1], 0);
485 else if (GET_CODE (inside) == PLUS)
487 rtx lhs = XEXP (inside, 0);
488 rtx rhs = XEXP (inside, 1);
489 if (REG_P (lhs)) rn = REGNO (lhs);
490 if (REG_P (rhs)) rn = REGNO (rhs);
493 if (rn == REGNO (operands[0]))
494 /* Move the second word first. */
495 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
497 /* Move the first word first. */
498 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
501 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
503 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
505 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
510 [(set (attr "length")
511 (symbol_ref "compute_mov_length (operands)"))])
513 (define_insn "*movsi_h8300hs"
514 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
515 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
516 "(TARGET_H8300S || TARGET_H8300H)
517 && (register_operand (operands[0], SImode)
518 || register_operand (operands[1], SImode))
519 && !(GET_CODE (operands[0]) == MEM
520 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
521 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
522 && GET_CODE (operands[1]) == REG
523 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
526 switch (which_alternative)
529 return \"sub.l %S0,%S0\";
533 return \"clrmac\;ldmac %1,macl\";
535 return \"stmac macl,%0\";
537 if (GET_CODE (operands[1]) == CONST_INT)
539 int val = INTVAL (operands[1]);
541 /* Look for constants which can be made by adding an 8-bit
542 number to zero in one of the two low bytes. */
543 if (val == (val & 0xff))
545 operands[1] = GEN_INT ((char) val & 0xff);
546 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
549 if (val == (val & 0xff00))
551 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
552 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
555 /* Look for constants that can be obtained by subs, inc, and
557 switch (val & 0xffffffff)
560 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
562 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
564 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
567 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
569 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
572 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
574 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
577 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
579 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
583 return \"mov.l %S1,%S0\";
585 [(set (attr "length")
586 (symbol_ref "compute_mov_length (operands)"))
587 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
589 (define_insn "*movsf_h8300hs"
590 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
591 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
592 "(TARGET_H8300H || TARGET_H8300S)
593 && (register_operand (operands[0], SFmode)
594 || register_operand (operands[1], SFmode))"
602 [(set (attr "length")
603 (symbol_ref "compute_mov_length (operands)"))
604 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
606 ;; ----------------------------------------------------------------------
608 ;; ----------------------------------------------------------------------
611 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
613 (match_operand 1 "const_int_operand" "n,n")))]
616 [(set_attr "length" "2,4")
617 (set_attr "cc" "set_zn,set_zn")])
620 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
622 (match_operand 1 "const_int_operand" "n")))]
625 [(set_attr "length" "2")
626 (set_attr "cc" "set_zn")])
628 (define_insn_and_split "*tst_extzv_1_n"
630 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
632 (match_operand 1 "const_int_operand" "n,n,n")))
633 (clobber (match_scratch:QI 2 "=X,X,&r"))]
634 "(TARGET_H8300H || TARGET_H8300S)"
640 && !EXTRA_CONSTRAINT (operands[0], 'U')"
643 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
646 (clobber (scratch:QI))])]
648 [(set_attr "length" "2,8,10")
649 (set_attr "cc" "set_zn,set_zn,set_zn")])
652 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
654 (match_operand 1 "const_int_operand" "n")))]
655 "(TARGET_H8300H || TARGET_H8300S)
656 && INTVAL (operands[1]) <= 15"
658 [(set_attr "length" "2")
659 (set_attr "cc" "set_zn")])
661 (define_insn_and_split "*tstsi_upper_bit"
663 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
665 (match_operand 1 "const_int_operand" "n")))
666 (clobber (match_scratch:SI 2 "=&r"))]
667 "(TARGET_H8300H || TARGET_H8300S)
668 && INTVAL (operands[1]) >= 16"
670 "&& reload_completed"
672 (ior:SI (and:SI (match_dup 2)
674 (lshiftrt:SI (match_dup 0)
677 (zero_extract:SI (match_dup 2)
680 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
682 (define_insn "*tstsi_variable_bit"
684 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
686 (and:SI (match_operand:SI 1 "register_operand" "r")
688 "TARGET_H8300H || TARGET_H8300S"
690 [(set_attr "length" "2")
691 (set_attr "cc" "set_zn")])
693 (define_insn_and_split "*tstsi_variable_bit_qi"
695 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
697 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
699 (clobber (match_scratch:QI 2 "=X,X,&r"))]
700 "(TARGET_H8300H || TARGET_H8300S)"
706 && !EXTRA_CONSTRAINT (operands[0], 'U')"
709 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
711 (and:SI (match_dup 1)
713 (clobber (scratch:QI))])]
715 [(set_attr "length" "2,8,10")
716 (set_attr "cc" "set_zn,set_zn,set_zn")])
719 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
722 [(set_attr "length" "2")
723 (set_attr "cc" "set_znv")])
726 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
729 [(set_attr "length" "2")
730 (set_attr "cc" "set_znv")])
732 (define_insn "*tsthi_upper"
734 (and:HI (match_operand:HI 0 "register_operand" "r")
738 [(set_attr "length" "2")
739 (set_attr "cc" "set_znv")])
742 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
743 "TARGET_H8300H || TARGET_H8300S"
745 [(set_attr "length" "2")
746 (set_attr "cc" "set_znv")])
748 (define_insn "*tstsi_upper"
750 (and:SI (match_operand:SI 0 "register_operand" "r")
751 (const_int -65536)))]
754 [(set_attr "length" "2")
755 (set_attr "cc" "set_znv")])
759 (compare (match_operand:QI 0 "register_operand" "r")
760 (match_operand:QI 1 "nonmemory_operand" "rn")))]
763 [(set_attr "length" "2")
764 (set_attr "cc" "compare")])
766 (define_expand "cmphi"
768 (compare (match_operand:HI 0 "register_operand" "")
769 (match_operand:HI 1 "nonmemory_operand" "")))]
773 /* Force operand1 into a register if we're compiling
775 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
776 operands[1] = force_reg (HImode, operands[1]);
779 (define_insn "*cmphi_h8300"
781 (compare (match_operand:HI 0 "register_operand" "r")
782 (match_operand:HI 1 "register_operand" "r")))]
785 [(set_attr "length" "2")
786 (set_attr "cc" "compare")])
788 (define_insn "*cmphi_h8300hs"
790 (compare (match_operand:HI 0 "register_operand" "r,r")
791 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
792 "TARGET_H8300H || TARGET_H8300S"
794 [(set_attr "length" "2,4")
795 (set_attr "cc" "compare,compare")])
799 (compare (match_operand:SI 0 "register_operand" "r,r")
800 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
801 "TARGET_H8300H || TARGET_H8300S"
803 [(set_attr "length" "2,6")
804 (set_attr "cc" "compare,compare")])
806 ;; ----------------------------------------------------------------------
808 ;; ----------------------------------------------------------------------
810 (define_insn "addqi3"
811 [(set (match_operand:QI 0 "register_operand" "=r")
812 (plus:QI (match_operand:QI 1 "register_operand" "%0")
813 (match_operand:QI 2 "nonmemory_operand" "rn")))]
816 [(set_attr "length" "2")
817 (set_attr "cc" "set_zn")])
819 (define_expand "addhi3"
820 [(set (match_operand:HI 0 "register_operand" "")
821 (plus:HI (match_operand:HI 1 "register_operand" "")
822 (match_operand:HI 2 "nonmemory_operand" "")))]
826 (define_insn "*addhi3_h8300"
827 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
828 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
829 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
835 add.b %s2,%s0\;addx %t2,%t0
837 [(set_attr "length" "2,2,2,4,2")
838 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
840 ;; This splitter is very important to make the stack adjustment
841 ;; interrupt-safe. The combination of add.b and addx is unsafe!
843 ;; We apply this split after the peephole2 pass so that we won't end
844 ;; up creating too many adds/subs when a scratch register is
845 ;; available, which is actually a common case because stack unrolling
846 ;; tends to happen immediately after a function call.
849 [(set (match_operand:HI 0 "stack_pointer_operand" "")
850 (plus:HI (match_dup 0)
851 (match_operand 1 "const_int_gt_2_operand" "")))]
852 "TARGET_H8300 && flow2_completed"
854 "split_adds_subs (HImode, operands); DONE;")
857 [(match_scratch:HI 2 "r")
858 (set (match_operand:HI 0 "stack_pointer_operand" "")
859 (plus:HI (match_dup 0)
860 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
865 (plus:HI (match_dup 0)
869 (define_insn "*addhi3_h8300hs"
870 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
871 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
872 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
873 "TARGET_H8300H || TARGET_H8300S"
880 [(set_attr "length" "2,2,2,4,2")
881 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
883 (define_insn "*addhi3_incdec"
884 [(set (match_operand:HI 0 "register_operand" "=r,r")
885 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
886 (match_operand:HI 2 "incdec_operand" "M,O")]
888 "TARGET_H8300H || TARGET_H8300S"
892 [(set_attr "length" "2,2")
893 (set_attr "cc" "set_zn,set_zn")])
896 [(set (match_operand:HI 0 "register_operand" "")
897 (plus:HI (match_dup 0)
898 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
901 "split_adds_subs (HImode, operands); DONE;")
903 (define_expand "addsi3"
904 [(set (match_operand:SI 0 "register_operand" "")
905 (plus:SI (match_operand:SI 1 "register_operand" "")
906 (match_operand:SI 2 "nonmemory_operand" "")))]
910 (define_insn "*addsi_h8300"
911 [(set (match_operand:SI 0 "register_operand" "=r,r")
912 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
913 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
915 "* return output_plussi (operands);"
916 [(set (attr "length")
917 (symbol_ref "compute_plussi_length (operands)"))
919 (symbol_ref "compute_plussi_cc (operands)"))])
921 (define_insn "*addsi_h8300hs"
922 [(set (match_operand:SI 0 "register_operand" "=r,r")
923 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
924 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
925 "TARGET_H8300H || TARGET_H8300S"
926 "* return output_plussi (operands);"
927 [(set (attr "length")
928 (symbol_ref "compute_plussi_length (operands)"))
930 (symbol_ref "compute_plussi_cc (operands)"))])
932 (define_insn "*addsi3_incdec"
933 [(set (match_operand:SI 0 "register_operand" "=r,r")
934 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
935 (match_operand:SI 2 "incdec_operand" "M,O")]
937 "TARGET_H8300H || TARGET_H8300S"
941 [(set_attr "length" "2,2")
942 (set_attr "cc" "set_zn,set_zn")])
945 [(set (match_operand:SI 0 "register_operand" "")
946 (plus:SI (match_dup 0)
947 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
948 "TARGET_H8300H || TARGET_H8300S"
950 "split_adds_subs (SImode, operands); DONE;")
952 ;; ----------------------------------------------------------------------
953 ;; SUBTRACT INSTRUCTIONS
954 ;; ----------------------------------------------------------------------
956 (define_insn "subqi3"
957 [(set (match_operand:QI 0 "register_operand" "=r")
958 (minus:QI (match_operand:QI 1 "register_operand" "0")
959 (match_operand:QI 2 "register_operand" "r")))]
962 [(set_attr "length" "2")
963 (set_attr "cc" "set_zn")])
965 (define_expand "subhi3"
966 [(set (match_operand:HI 0 "register_operand" "")
967 (minus:HI (match_operand:HI 1 "general_operand" "")
968 (match_operand:HI 2 "nonmemory_operand" "")))]
972 (define_insn "*subhi3_h8300"
973 [(set (match_operand:HI 0 "register_operand" "=r,r")
974 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
975 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
979 add.b %E2,%s0\;addx %F2,%t0"
980 [(set_attr "length" "2,4")
981 (set_attr "cc" "set_zn,clobber")])
983 (define_insn "*subhi3_h8300hs"
984 [(set (match_operand:HI 0 "register_operand" "=r,r")
985 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
986 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
987 "TARGET_H8300H || TARGET_H8300S"
991 [(set_attr "length" "2,4")
992 (set_attr "cc" "set_zn,set_zn")])
994 (define_expand "subsi3"
995 [(set (match_operand:SI 0 "register_operand" "")
996 (minus:SI (match_operand:SI 1 "register_operand" "")
997 (match_operand:SI 2 "nonmemory_operand" "")))]
1001 (define_insn "*subsi3_h8300"
1002 [(set (match_operand:SI 0 "register_operand" "=r")
1003 (minus:SI (match_operand:SI 1 "register_operand" "0")
1004 (match_operand:SI 2 "register_operand" "r")))]
1006 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1007 [(set_attr "length" "6")])
1009 (define_insn "*subsi3_h8300hs"
1010 [(set (match_operand:SI 0 "register_operand" "=r,r")
1011 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1012 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1013 "TARGET_H8300H || TARGET_H8300S"
1017 [(set_attr "length" "2,6")
1018 (set_attr "cc" "set_zn,set_zn")])
1020 ;; ----------------------------------------------------------------------
1021 ;; MULTIPLY INSTRUCTIONS
1022 ;; ----------------------------------------------------------------------
1024 ;; Note that the H8/300 can only handle umulqihi3.
1026 (define_insn "mulqihi3"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1029 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1030 "TARGET_H8300H || TARGET_H8300S"
1032 [(set_attr "length" "4")
1033 (set_attr "cc" "set_zn")])
1035 (define_insn "mulhisi3"
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1038 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1039 "TARGET_H8300H || TARGET_H8300S"
1041 [(set_attr "length" "4")
1042 (set_attr "cc" "set_zn")])
1044 (define_insn "umulqihi3"
1045 [(set (match_operand:HI 0 "register_operand" "=r")
1046 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1047 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1050 [(set_attr "length" "2")
1051 (set_attr "cc" "none_0hit")])
1053 (define_insn "umulhisi3"
1054 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1056 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1057 "TARGET_H8300H || TARGET_H8300S"
1059 [(set_attr "length" "2")
1060 (set_attr "cc" "none_0hit")])
1062 ;; This is a "bridge" instruction. Combine can't cram enough insns
1063 ;; together to crate a MAC instruction directly, but it can create
1064 ;; this instruction, which then allows combine to create the real
1067 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1068 ;; insn must generate reasonably correct code. Egad.
1070 [(set (match_operand:SI 0 "register_operand" "=a")
1073 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1075 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1077 "clrmac\;mac @%2+,@%1+"
1078 [(set_attr "length" "6")
1079 (set_attr "cc" "none_0hit")])
1082 [(set (match_operand:SI 0 "register_operand" "=a")
1084 (sign_extend:SI (mem:HI
1085 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1086 (sign_extend:SI (mem:HI
1087 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1088 (match_operand:SI 3 "register_operand" "0")))]
1091 [(set_attr "length" "4")
1092 (set_attr "cc" "none_0hit")])
1094 ;; ----------------------------------------------------------------------
1095 ;; DIVIDE/MOD INSTRUCTIONS
1096 ;; ----------------------------------------------------------------------
1098 (define_insn "udivmodqi4"
1099 [(set (match_operand:QI 0 "register_operand" "=r")
1102 (match_operand:HI 1 "register_operand" "0")
1103 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1104 (set (match_operand:QI 3 "register_operand" "=r")
1108 (zero_extend:HI (match_dup 2)))))]
1112 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1113 return \"divxu.b\\t%X2,%T0\";
1115 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1117 [(set_attr "length" "4")])
1119 (define_insn "divmodqi4"
1120 [(set (match_operand:QI 0 "register_operand" "=r")
1123 (match_operand:HI 1 "register_operand" "0")
1124 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1125 (set (match_operand:QI 3 "register_operand" "=r")
1129 (sign_extend:HI (match_dup 2)))))]
1130 "TARGET_H8300H || TARGET_H8300S"
1133 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1134 return \"divxs.b\\t%X2,%T0\";
1136 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1138 [(set_attr "length" "6")])
1140 (define_insn "udivmodhi4"
1141 [(set (match_operand:HI 0 "register_operand" "=r")
1144 (match_operand:SI 1 "register_operand" "0")
1145 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1146 (set (match_operand:HI 3 "register_operand" "=r")
1150 (zero_extend:SI (match_dup 2)))))]
1151 "TARGET_H8300H || TARGET_H8300S"
1154 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1155 return \"divxu.w\\t%T2,%S0\";
1157 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1159 [(set_attr "length" "4")])
1161 (define_insn "divmodhi4"
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1165 (match_operand:SI 1 "register_operand" "0")
1166 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1167 (set (match_operand:HI 3 "register_operand" "=r")
1171 (sign_extend:SI (match_dup 2)))))]
1172 "TARGET_H8300H || TARGET_H8300S"
1175 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1176 return \"divxs.w\\t%T2,%S0\";
1178 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1180 [(set_attr "length" "6")])
1182 ;; ----------------------------------------------------------------------
1184 ;; ----------------------------------------------------------------------
1186 (define_insn "*andqi3_1"
1187 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1188 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1189 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1190 "register_operand (operands[0], QImode)
1191 || single_zero_operand (operands[2], QImode)"
1195 [(set_attr "length" "2,8")
1196 (set_attr "cc" "set_znv,none_0hit")])
1198 (define_expand "andqi3"
1199 [(set (match_operand:QI 0 "bit_operand" "")
1200 (and:QI (match_operand:QI 1 "bit_operand" "")
1201 (match_operand:QI 2 "nonmemory_operand" "")))]
1205 if (fix_bit_operand (operands, 0, AND))
1209 (define_expand "andhi3"
1210 [(set (match_operand:HI 0 "register_operand" "")
1211 (and:HI (match_operand:HI 1 "register_operand" "")
1212 (match_operand:HI 2 "nonmemory_operand" "")))]
1216 (define_insn "*andorqi3"
1217 [(set (match_operand:QI 0 "register_operand" "=r")
1218 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1219 (match_operand:QI 3 "single_one_operand" "n"))
1220 (match_operand:QI 1 "register_operand" "0")))]
1222 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1223 [(set_attr "length" "6")])
1225 (define_insn "*andorhi3"
1226 [(set (match_operand:HI 0 "register_operand" "=r")
1227 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1228 (match_operand:HI 3 "single_one_operand" "n"))
1229 (match_operand:HI 1 "register_operand" "0")))]
1233 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1234 if (INTVAL (operands[3]) > 128)
1236 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1237 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1239 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1241 [(set_attr "length" "6")])
1243 (define_insn "*andorsi3"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1246 (match_operand:SI 3 "single_one_operand" "n"))
1247 (match_operand:SI 1 "register_operand" "0")))]
1248 "(INTVAL (operands[3]) & 0xffff) != 0"
1251 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1252 if (INTVAL (operands[3]) > 128)
1254 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1255 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1257 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1259 [(set_attr "length" "6")])
1261 (define_insn "*andorsi3_shift_8"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1266 (match_operand:SI 1 "register_operand" "0")))]
1269 [(set_attr "length" "2")])
1271 (define_expand "andsi3"
1272 [(set (match_operand:SI 0 "register_operand" "")
1273 (and:SI (match_operand:SI 1 "register_operand" "")
1274 (match_operand:SI 2 "nonmemory_operand" "")))]
1278 ;; ----------------------------------------------------------------------
1280 ;; ----------------------------------------------------------------------
1282 (define_insn "*iorqi3_1"
1283 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1284 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1285 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1286 "register_operand (operands[0], QImode)
1287 || single_one_operand (operands[2], QImode)"
1291 [(set_attr "length" "2,8")
1292 (set_attr "cc" "set_znv,none_0hit")])
1294 (define_expand "iorqi3"
1295 [(set (match_operand:QI 0 "bit_operand" "")
1296 (ior:QI (match_operand:QI 1 "bit_operand" "")
1297 (match_operand:QI 2 "nonmemory_operand" "")))]
1301 if (fix_bit_operand (operands, 1, IOR))
1305 (define_expand "iorhi3"
1306 [(set (match_operand:HI 0 "register_operand" "")
1307 (ior:HI (match_operand:HI 1 "register_operand" "")
1308 (match_operand:HI 2 "nonmemory_operand" "")))]
1312 (define_expand "iorsi3"
1313 [(set (match_operand:SI 0 "register_operand" "")
1314 (ior:SI (match_operand:SI 1 "register_operand" "")
1315 (match_operand:SI 2 "nonmemory_operand" "")))]
1319 ;; ----------------------------------------------------------------------
1321 ;; ----------------------------------------------------------------------
1323 (define_insn "*xorqi3_1"
1324 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1325 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1326 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1327 "register_operand (operands[0], QImode)
1328 || single_one_operand (operands[2], QImode)"
1332 [(set_attr "length" "2,8")
1333 (set_attr "cc" "set_znv,none_0hit")])
1335 (define_expand "xorqi3"
1336 [(set (match_operand:QI 0 "bit_operand" "")
1337 (xor:QI (match_operand:QI 1 "bit_operand" "")
1338 (match_operand:QI 2 "nonmemory_operand" "")))]
1342 if (fix_bit_operand (operands, 1, XOR))
1346 (define_expand "xorhi3"
1347 [(set (match_operand:HI 0 "register_operand" "")
1348 (xor:HI (match_operand:HI 1 "register_operand" "")
1349 (match_operand:HI 2 "nonmemory_operand" "")))]
1353 (define_expand "xorsi3"
1354 [(set (match_operand:SI 0 "register_operand" "")
1355 (xor:SI (match_operand:SI 1 "register_operand" "")
1356 (match_operand:SI 2 "nonmemory_operand" "")))]
1360 ;; ----------------------------------------------------------------------
1361 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1362 ;; ----------------------------------------------------------------------
1364 (define_insn "*logicalhi3"
1365 [(set (match_operand:HI 0 "register_operand" "=r")
1366 (match_operator:HI 3 "bit_operator"
1367 [(match_operand:HI 1 "register_operand" "%0")
1368 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1370 "* return output_logical_op (HImode, operands);"
1371 [(set (attr "length")
1372 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1374 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1376 (define_insn "*logicalsi3"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (match_operator:SI 3 "bit_operator"
1379 [(match_operand:SI 1 "register_operand" "%0")
1380 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1382 "* return output_logical_op (SImode, operands);"
1383 [(set (attr "length")
1384 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1386 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1388 ;; ----------------------------------------------------------------------
1389 ;; NEGATION INSTRUCTIONS
1390 ;; ----------------------------------------------------------------------
1392 (define_insn "negqi2"
1393 [(set (match_operand:QI 0 "register_operand" "=r")
1394 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1397 [(set_attr "length" "2")
1398 (set_attr "cc" "set_zn")])
1400 (define_expand "neghi2"
1401 [(set (match_operand:HI 0 "register_operand" "")
1402 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1408 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1413 (define_expand "neghi2_h8300"
1415 (not:HI (match_operand:HI 1 "register_operand" "")))
1416 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1417 (set (match_operand:HI 0 "register_operand" "")
1420 "operands[2] = gen_reg_rtx (HImode);")
1422 (define_insn "*neghi2_h8300hs"
1423 [(set (match_operand:HI 0 "register_operand" "=r")
1424 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1425 "TARGET_H8300H || TARGET_H8300S"
1427 [(set_attr "length" "2")
1428 (set_attr "cc" "set_zn")])
1430 (define_expand "negsi2"
1431 [(set (match_operand:SI 0 "register_operand" "")
1432 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1438 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1443 (define_expand "negsi2_h8300"
1445 (not:SI (match_operand:SI 1 "register_operand" "")))
1446 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1447 (set (match_operand:SI 0 "register_operand" "")
1450 "operands[2] = gen_reg_rtx (SImode);")
1452 (define_insn "*negsi2_h8300hs"
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1455 "TARGET_H8300H || TARGET_H8300S"
1457 [(set_attr "length" "2")
1458 (set_attr "cc" "set_zn")])
1460 (define_expand "negsf2"
1461 [(set (match_operand:SF 0 "register_operand" "")
1462 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1466 (define_insn "*negsf2_h8300"
1467 [(set (match_operand:SF 0 "register_operand" "=r")
1468 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1471 [(set_attr "length" "2")])
1473 (define_insn "*negsf2_h8300hs"
1474 [(set (match_operand:SF 0 "register_operand" "=r")
1475 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1476 "TARGET_H8300H || TARGET_H8300S"
1477 "xor.w\\t#32768,%e0"
1478 [(set_attr "length" "4")])
1480 ;; ----------------------------------------------------------------------
1481 ;; ABSOLUTE VALUE INSTRUCTIONS
1482 ;; ----------------------------------------------------------------------
1484 (define_expand "abssf2"
1485 [(set (match_operand:SF 0 "register_operand" "")
1486 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1490 (define_insn "*abssf2_h8300"
1491 [(set (match_operand:SF 0 "register_operand" "=r")
1492 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1495 [(set_attr "length" "2")])
1497 (define_insn "*abssf2_h8300hs"
1498 [(set (match_operand:SF 0 "register_operand" "=r")
1499 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1500 "TARGET_H8300H || TARGET_H8300S"
1501 "and.w\\t#32767,%e0"
1502 [(set_attr "length" "4")])
1504 ;; ----------------------------------------------------------------------
1506 ;; ----------------------------------------------------------------------
1508 (define_insn "one_cmplqi2"
1509 [(set (match_operand:QI 0 "register_operand" "=r")
1510 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1513 [(set_attr "length" "2")
1514 (set_attr "cc" "set_znv")])
1516 (define_expand "one_cmplhi2"
1517 [(set (match_operand:HI 0 "register_operand" "=r")
1518 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1522 (define_insn "*one_cmplhi2_h8300"
1523 [(set (match_operand:HI 0 "register_operand" "=r")
1524 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1527 [(set_attr "length" "4")])
1529 (define_insn "*one_cmplhi2_h8300hs"
1530 [(set (match_operand:HI 0 "register_operand" "=r")
1531 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1532 "TARGET_H8300H || TARGET_H8300S"
1534 [(set_attr "cc" "set_znv")
1535 (set_attr "length" "2")])
1537 (define_expand "one_cmplsi2"
1538 [(set (match_operand:SI 0 "register_operand" "=r")
1539 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1543 (define_insn "*one_complsi2_h8300"
1544 [(set (match_operand:SI 0 "register_operand" "=r")
1545 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1547 "not %w0\;not %x0\;not %y0\;not %z0"
1548 [(set_attr "length" "8")])
1550 (define_insn "*one_complsi2_h8300hs"
1551 [(set (match_operand:SI 0 "register_operand" "=r")
1552 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1553 "TARGET_H8300H || TARGET_H8300S"
1555 [(set_attr "cc" "set_znv")
1556 (set_attr "length" "2")])
1558 ;; ----------------------------------------------------------------------
1559 ;; JUMP INSTRUCTIONS
1560 ;; ----------------------------------------------------------------------
1562 ;; Conditional jump instructions
1564 (define_expand "ble"
1566 (if_then_else (le (cc0)
1568 (label_ref (match_operand 0 "" ""))
1573 (define_expand "bleu"
1575 (if_then_else (leu (cc0)
1577 (label_ref (match_operand 0 "" ""))
1582 (define_expand "bge"
1584 (if_then_else (ge (cc0)
1586 (label_ref (match_operand 0 "" ""))
1591 (define_expand "bgeu"
1593 (if_then_else (geu (cc0)
1595 (label_ref (match_operand 0 "" ""))
1600 (define_expand "blt"
1602 (if_then_else (lt (cc0)
1604 (label_ref (match_operand 0 "" ""))
1609 (define_expand "bltu"
1611 (if_then_else (ltu (cc0)
1613 (label_ref (match_operand 0 "" ""))
1618 (define_expand "bgt"
1620 (if_then_else (gt (cc0)
1622 (label_ref (match_operand 0 "" ""))
1627 (define_expand "bgtu"
1629 (if_then_else (gtu (cc0)
1631 (label_ref (match_operand 0 "" ""))
1636 (define_expand "beq"
1638 (if_then_else (eq (cc0)
1640 (label_ref (match_operand 0 "" ""))
1645 (define_expand "bne"
1647 (if_then_else (ne (cc0)
1649 (label_ref (match_operand 0 "" ""))
1654 (define_insn "branch_true"
1656 (if_then_else (match_operator 1 "comparison_operator"
1657 [(cc0) (const_int 0)])
1658 (label_ref (match_operand 0 "" ""))
1663 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1664 && (GET_CODE (operands[1]) == GT
1665 || GET_CODE (operands[1]) == GE
1666 || GET_CODE (operands[1]) == LE
1667 || GET_CODE (operands[1]) == LT))
1669 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1673 if (get_attr_length (insn) == 2)
1674 return \"b%j1 %l0\";
1675 else if (get_attr_length (insn) == 4)
1676 return \"b%j1 %l0:16\";
1678 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1680 [(set_attr "type" "branch")
1681 (set_attr "cc" "none")])
1683 (define_insn "branch_false"
1685 (if_then_else (match_operator 1 "comparison_operator"
1686 [(cc0) (const_int 0)])
1688 (label_ref (match_operand 0 "" ""))))]
1692 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1693 && (GET_CODE (operands[1]) == GT
1694 || GET_CODE (operands[1]) == GE
1695 || GET_CODE (operands[1]) == LE
1696 || GET_CODE (operands[1]) == LT))
1698 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1702 if (get_attr_length (insn) == 2)
1703 return \"b%k1 %l0\";
1704 else if (get_attr_length (insn) == 4)
1705 return \"b%k1 %l0:16\";
1707 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1709 [(set_attr "type" "branch")
1710 (set_attr "cc" "none")])
1712 ;; Unconditional and other jump instructions.
1716 (label_ref (match_operand 0 "" "")))]
1720 if (get_attr_length (insn) == 2)
1722 else if (get_attr_length (insn) == 4)
1723 return \"bra %l0:16\";
1725 return \"jmp @%l0\";
1727 [(set_attr "type" "branch")
1728 (set_attr "cc" "none")])
1730 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1732 (define_expand "tablejump"
1733 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1734 (use (label_ref (match_operand 1 "" "")))])]
1738 (define_insn "*tablejump_h8300"
1739 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1740 (use (label_ref (match_operand 1 "" "")))]
1743 [(set_attr "cc" "none")
1744 (set_attr "length" "2")])
1746 (define_insn "*tablejump_h8300hs_advanced"
1747 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1748 (use (label_ref (match_operand 1 "" "")))]
1749 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1751 [(set_attr "cc" "none")
1752 (set_attr "length" "2")])
1754 (define_insn "*tablejump_h8300hs_normal"
1755 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1756 (use (label_ref (match_operand 1 "" "")))]
1757 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1759 [(set_attr "cc" "none")
1760 (set_attr "length" "2")])
1762 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1764 (define_expand "indirect_jump"
1765 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1769 (define_insn "*indirect_jump_h8300"
1770 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1773 [(set_attr "cc" "none")
1774 (set_attr "length" "2")])
1776 (define_insn "*indirect_jump_h8300hs_advanced"
1777 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1778 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1780 [(set_attr "cc" "none")
1781 (set_attr "length" "2")])
1783 (define_insn "*indirect_jump_h8300hs_normal"
1784 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1785 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1787 [(set_attr "cc" "none")
1788 (set_attr "length" "2")])
1790 ;; Call subroutine with no return value.
1792 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1795 [(call (match_operand:QI 0 "call_insn_operand" "or")
1796 (match_operand:HI 1 "general_operand" "g"))]
1800 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1801 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1802 return \"jsr\\t@%0:8\";
1804 return \"jsr\\t%0\";
1806 [(set (attr "length")
1807 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1811 ;; Call subroutine, returning value in operand 0
1812 ;; (which must be a hard register).
1814 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1816 (define_insn "call_value"
1817 [(set (match_operand 0 "" "=r")
1818 (call (match_operand:QI 1 "call_insn_operand" "or")
1819 (match_operand:HI 2 "general_operand" "g")))]
1823 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1824 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1825 return \"jsr\\t@%1:8\";
1827 return \"jsr\\t%1\";
1829 [(set (attr "length")
1830 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1838 [(set_attr "cc" "none")
1839 (set_attr "length" "2")])
1841 ;; ----------------------------------------------------------------------
1842 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1843 ;; ----------------------------------------------------------------------
1845 (define_expand "push_h8300"
1846 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1847 (match_operand:HI 0 "register_operand" ""))]
1851 (define_expand "push_h8300hs_advanced"
1852 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1853 (match_operand:SI 0 "register_operand" ""))]
1854 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1857 (define_expand "push_h8300hs_normal"
1858 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1859 (match_operand:SI 0 "register_operand" ""))]
1860 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1863 (define_expand "pop_h8300"
1864 [(set (match_operand:HI 0 "register_operand" "")
1865 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1869 (define_expand "pop_h8300hs_advanced"
1870 [(set (match_operand:SI 0 "register_operand" "")
1871 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1872 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1875 (define_expand "pop_h8300hs_normal"
1876 [(set (match_operand:SI 0 "register_operand" "")
1877 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1878 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1881 (define_insn "stm_h8300s_2_advanced"
1882 [(set (reg:SI SP_REG)
1883 (plus:SI (reg:SI SP_REG) (const_int -8)))
1884 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1885 (match_operand:SI 0 "register_operand" ""))
1886 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1887 (match_operand:SI 1 "register_operand" ""))]
1888 "TARGET_H8300S && !TARGET_NORMAL_MODE
1889 && h8300_regs_ok_for_stm (2, operands)"
1890 "stm.l\\t%S0-%S1,@-er7"
1891 [(set_attr "cc" "none")
1892 (set_attr "length" "4")])
1894 (define_insn "stm_h8300s_2_normal"
1895 [(set (reg:HI SP_REG)
1896 (plus:HI (reg:HI SP_REG) (const_int -8)))
1897 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1898 (match_operand:SI 0 "register_operand" ""))
1899 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1900 (match_operand:SI 1 "register_operand" ""))]
1901 "TARGET_H8300S && TARGET_NORMAL_MODE
1902 && h8300_regs_ok_for_stm (2, operands)"
1903 "stm.l\\t%S0-%S1,@-er7"
1904 [(set_attr "cc" "none")
1905 (set_attr "length" "4")])
1907 (define_expand "stm_h8300s_2"
1908 [(match_operand:SI 0 "register_operand" "")
1909 (match_operand:SI 1 "register_operand" "")]
1911 && h8300_regs_ok_for_stm (2, operands)"
1914 if (!TARGET_NORMAL_MODE)
1915 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1917 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1921 (define_insn "stm_h8300s_3_advanced"
1922 [(set (reg:SI SP_REG)
1923 (plus:SI (reg:SI SP_REG) (const_int -12)))
1924 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1925 (match_operand:SI 0 "register_operand" ""))
1926 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1927 (match_operand:SI 1 "register_operand" ""))
1928 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1929 (match_operand:SI 2 "register_operand" ""))]
1930 "TARGET_H8300S && !TARGET_NORMAL_MODE
1931 && h8300_regs_ok_for_stm (3, operands)"
1932 "stm.l\\t%S0-%S2,@-er7"
1933 [(set_attr "cc" "none")
1934 (set_attr "length" "4")])
1936 (define_insn "stm_h8300s_3_normal"
1937 [(set (reg:HI SP_REG)
1938 (plus:HI (reg:HI SP_REG) (const_int -12)))
1939 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1940 (match_operand:SI 0 "register_operand" ""))
1941 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1942 (match_operand:SI 1 "register_operand" ""))
1943 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1944 (match_operand:SI 2 "register_operand" ""))]
1945 "TARGET_H8300S && TARGET_NORMAL_MODE
1946 && h8300_regs_ok_for_stm (3, operands)"
1947 "stm.l\\t%S0-%S2,@-er7"
1948 [(set_attr "cc" "none")
1949 (set_attr "length" "4")])
1951 (define_expand "stm_h8300s_3"
1952 [(match_operand:SI 0 "register_operand" "")
1953 (match_operand:SI 1 "register_operand" "")
1954 (match_operand:SI 2 "register_operand" "")]
1956 && h8300_regs_ok_for_stm (3, operands)"
1959 if (!TARGET_NORMAL_MODE)
1960 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
1963 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
1968 (define_insn "stm_h8300s_4_advanced"
1969 [(set (reg:SI SP_REG)
1970 (plus:SI (reg:SI SP_REG) (const_int -16)))
1971 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1972 (match_operand:SI 0 "register_operand" ""))
1973 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1974 (match_operand:SI 1 "register_operand" ""))
1975 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1976 (match_operand:SI 2 "register_operand" ""))
1977 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1978 (match_operand:SI 3 "register_operand" ""))]
1979 "TARGET_H8300S && !TARGET_NORMAL_MODE
1980 && h8300_regs_ok_for_stm (4, operands)"
1981 "stm.l\\t%S0-%S3,@-er7"
1982 [(set_attr "cc" "none")
1983 (set_attr "length" "4")])
1985 (define_insn "stm_h8300s_4_normal"
1986 [(set (reg:HI SP_REG)
1987 (plus:HI (reg:HI SP_REG) (const_int -16)))
1988 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1989 (match_operand:SI 0 "register_operand" ""))
1990 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1991 (match_operand:SI 1 "register_operand" ""))
1992 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1993 (match_operand:SI 2 "register_operand" ""))
1994 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
1995 (match_operand:SI 3 "register_operand" ""))]
1996 "TARGET_H8300S && TARGET_NORMAL_MODE
1997 && h8300_regs_ok_for_stm (4, operands)"
1998 "stm.l\\t%S0-%S3,@-er7"
1999 [(set_attr "cc" "none")
2000 (set_attr "length" "4")])
2002 (define_expand "stm_h8300s_4"
2003 [(match_operand:SI 0 "register_operand" "")
2004 (match_operand:SI 1 "register_operand" "")
2005 (match_operand:SI 2 "register_operand" "")
2006 (match_operand:SI 3 "register_operand" "")]
2008 && h8300_regs_ok_for_stm (4, operands)"
2011 if (!TARGET_NORMAL_MODE)
2012 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2013 operands[2], operands[3]));
2015 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2016 operands[2], operands[3]));
2020 (define_insn "ldm_h8300s_2_advanced"
2021 [(set (reg:SI SP_REG)
2022 (plus:SI (reg:SI SP_REG) (const_int 8)))
2023 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2024 (match_operand:SI 0 "register_operand" ""))
2025 (set (mem:SI (reg:SI SP_REG))
2026 (match_operand:SI 1 "register_operand" ""))]
2027 "TARGET_H8300S && !TARGET_NORMAL_MODE
2028 && h8300_regs_ok_for_stm (2, operands)"
2029 "ldm.l\\t@er7+,%S0-%S1"
2030 [(set_attr "cc" "none")
2031 (set_attr "length" "4")])
2033 (define_insn "ldm_h8300s_2_normal"
2034 [(set (reg:HI SP_REG)
2035 (plus:HI (reg:HI SP_REG) (const_int 8)))
2036 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2037 (match_operand:SI 0 "register_operand" ""))
2038 (set (mem:SI (reg:HI SP_REG))
2039 (match_operand:SI 1 "register_operand" ""))]
2040 "TARGET_H8300S && TARGET_NORMAL_MODE
2041 && h8300_regs_ok_for_stm (2, operands)"
2042 "ldm.l\\t@er7+,%S0-%S1"
2043 [(set_attr "cc" "none")
2044 (set_attr "length" "4")])
2046 (define_expand "ldm_h8300s_2"
2047 [(match_operand:SI 0 "register_operand" "")
2048 (match_operand:SI 1 "register_operand" "")]
2050 && h8300_regs_ok_for_stm (2, operands)"
2053 if (!TARGET_NORMAL_MODE)
2054 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2056 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2060 (define_insn "ldm_h8300s_3_advanced"
2061 [(set (reg:SI SP_REG)
2062 (plus:SI (reg:SI SP_REG) (const_int 12)))
2063 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2064 (match_operand:SI 0 "register_operand" ""))
2065 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2066 (match_operand:SI 1 "register_operand" ""))
2067 (set (mem:SI (reg:SI SP_REG))
2068 (match_operand:SI 2 "register_operand" ""))]
2069 "TARGET_H8300S && !TARGET_NORMAL_MODE
2070 && h8300_regs_ok_for_stm (3, operands)"
2071 "ldm.l\\t@er7+,%S0-%S2"
2072 [(set_attr "cc" "none")
2073 (set_attr "length" "4")])
2075 (define_insn "ldm_h8300s_3_normal"
2076 [(set (reg:HI SP_REG)
2077 (plus:HI (reg:HI SP_REG) (const_int 12)))
2078 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2079 (match_operand:SI 0 "register_operand" ""))
2080 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2081 (match_operand:SI 1 "register_operand" ""))
2082 (set (mem:SI (reg:HI SP_REG))
2083 (match_operand:SI 2 "register_operand" ""))]
2084 "TARGET_H8300S && TARGET_NORMAL_MODE
2085 && h8300_regs_ok_for_stm (3, operands)"
2086 "ldm.l\\t@er7+,%S0-%S2"
2087 [(set_attr "cc" "none")
2088 (set_attr "length" "4")])
2090 (define_expand "ldm_h8300s_3"
2091 [(match_operand:SI 0 "register_operand" "")
2092 (match_operand:SI 1 "register_operand" "")
2093 (match_operand:SI 2 "register_operand" "")]
2095 && h8300_regs_ok_for_stm (3, operands)"
2098 if (!TARGET_NORMAL_MODE)
2099 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2102 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2107 (define_insn "ldm_h8300s_4_advanced"
2108 [(set (reg:SI SP_REG)
2109 (plus:SI (reg:SI SP_REG) (const_int 16)))
2110 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2111 (match_operand:SI 0 "register_operand" ""))
2112 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2113 (match_operand:SI 1 "register_operand" ""))
2114 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2115 (match_operand:SI 2 "register_operand" ""))
2116 (set (mem:SI (reg:SI SP_REG))
2117 (match_operand:SI 3 "register_operand" ""))]
2118 "TARGET_H8300S && !TARGET_NORMAL_MODE
2119 && h8300_regs_ok_for_stm (4, operands)"
2120 "ldm.l\\t@er7+,%S0-%S3"
2121 [(set_attr "cc" "none")
2122 (set_attr "length" "4")])
2124 (define_insn "ldm_h8300s_4_normal"
2125 [(set (reg:HI SP_REG)
2126 (plus:HI (reg:HI SP_REG) (const_int 16)))
2127 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2128 (match_operand:SI 0 "register_operand" ""))
2129 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2130 (match_operand:SI 1 "register_operand" ""))
2131 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2132 (match_operand:SI 2 "register_operand" ""))
2133 (set (mem:SI (reg:HI SP_REG))
2134 (match_operand:SI 3 "register_operand" ""))]
2135 "TARGET_H8300S && !TARGET_NORMAL_MODE
2136 && h8300_regs_ok_for_stm (4, operands)"
2137 "ldm.l\\t@er7+,%S0-%S3"
2138 [(set_attr "cc" "none")
2139 (set_attr "length" "4")])
2141 (define_expand "ldm_h8300s_4"
2142 [(match_operand:SI 0 "register_operand" "")
2143 (match_operand:SI 1 "register_operand" "")
2144 (match_operand:SI 2 "register_operand" "")
2145 (match_operand:SI 3 "register_operand" "")]
2146 "TARGET_H8300S && !TARGET_NORMAL_MODE
2147 && h8300_regs_ok_for_stm (4, operands)"
2150 if (!TARGET_NORMAL_MODE)
2151 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2152 operands[2], operands[3]));
2154 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2155 operands[2], operands[3]));
2159 (define_expand "return"
2161 "h8300_can_use_return_insn_p ()"
2164 (define_insn "*return_1"
2169 if (h8300_current_function_interrupt_function_p ())
2174 [(set_attr "cc" "none")
2175 (set_attr "length" "2")])
2177 (define_expand "prologue"
2180 "h8300_expand_prologue (); DONE;")
2182 (define_expand "epilogue"
2185 "h8300_expand_epilogue ();")
2187 (define_insn "monitor_prologue"
2188 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2193 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2194 else if (TARGET_H8300H)
2195 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2196 else if (TARGET_H8300S)
2197 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2200 [(set_attr "length" "20")])
2202 ;; ----------------------------------------------------------------------
2203 ;; EXTEND INSTRUCTIONS
2204 ;; ----------------------------------------------------------------------
2206 (define_expand "zero_extendqihi2"
2207 [(set (match_operand:HI 0 "register_operand" "")
2208 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2212 (define_insn "*zero_extendqihi2_h8300"
2213 [(set (match_operand:HI 0 "register_operand" "=r,r")
2214 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2219 [(set_attr "length" "2,10")])
2221 (define_insn "*zero_extendqihi2_h8300hs"
2222 [(set (match_operand:HI 0 "register_operand" "=r,r")
2223 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2224 "TARGET_H8300H || TARGET_H8300S"
2228 [(set_attr "length" "2,10")
2229 (set_attr "cc" "set_znv,set_znv")])
2231 ;; Split the zero extension of a general operand (actually a memory
2232 ;; operand) into a load of the operand and the actual zero extension
2233 ;; so that 1) the length will be accurate, and 2) the zero extensions
2234 ;; appearing at the end of basic blocks may be merged.
2237 [(set (match_operand:HI 0 "register_operand" "")
2238 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2243 (zero_extend:HI (match_dup 2)))]
2244 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2246 (define_expand "zero_extendqisi2"
2247 [(set (match_operand:SI 0 "register_operand" "")
2248 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2252 (define_insn "*zero_extendqisi2_h8300"
2253 [(set (match_operand:SI 0 "register_operand" "=r,r")
2254 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2257 mov.b #0,%x0\;sub.w %e0,%e0
2258 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2259 [(set_attr "length" "4,8")])
2261 (define_insn "*zero_extendqisi2_h8300hs"
2262 [(set (match_operand:SI 0 "register_operand" "=r,r")
2263 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2264 "TARGET_H8300H || TARGET_H8300S"
2268 [(set (match_operand:SI 0 "register_operand" "")
2269 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2270 "(TARGET_H8300H || TARGET_H8300S)
2271 && reg_overlap_mentioned_p (operands[0], operands[1])
2272 && reload_completed"
2276 (zero_extend:HI (match_dup 2)))
2278 (zero_extend:SI (match_dup 3)))]
2279 "operands[2] = gen_lowpart (QImode, operands[0]);
2280 operands[3] = gen_lowpart (HImode, operands[0]);")
2283 [(set (match_operand:SI 0 "register_operand" "")
2284 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2285 "(TARGET_H8300H || TARGET_H8300S)
2286 && !reg_overlap_mentioned_p (operands[0], operands[1])
2287 && reload_completed"
2290 (set (strict_low_part (match_dup 2))
2292 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2294 (define_expand "zero_extendhisi2"
2295 [(set (match_operand:SI 0 "register_operand" "")
2296 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2300 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2301 (define_insn "*zero_extendhisi2_h8300"
2302 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2303 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2307 mov.w %f1,%f0\;sub.w %e0,%e0
2308 mov.w %e1,%f0\;sub.w %e0,%e0"
2309 [(set_attr "length" "2,4,6")])
2311 (define_insn "*zero_extendhisi2_h8300hs"
2312 [(set (match_operand:SI 0 "register_operand" "=r")
2313 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2314 "TARGET_H8300H || TARGET_H8300S"
2316 [(set_attr "length" "2")
2317 (set_attr "cc" "set_znv")])
2319 (define_expand "extendqihi2"
2320 [(set (match_operand:HI 0 "register_operand" "")
2321 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2325 (define_insn "*extendqihi2_h8300"
2326 [(set (match_operand:HI 0 "register_operand" "=r,r")
2327 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2330 bld #7,%s0\;subx %t0,%t0
2331 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2332 [(set_attr "length" "4,8")])
2334 (define_insn "*extendqihi2_h8300hs"
2335 [(set (match_operand:HI 0 "register_operand" "=r")
2336 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2337 "TARGET_H8300H || TARGET_H8300S"
2339 [(set_attr "length" "2")
2340 (set_attr "cc" "set_znv")])
2342 (define_expand "extendqisi2"
2343 [(set (match_operand:SI 0 "register_operand" "")
2344 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2348 (define_insn "*extendqisi2_h8300"
2349 [(set (match_operand:SI 0 "register_operand" "")
2350 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2353 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2354 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2355 [(set_attr "length" "8,12")])
2357 ;; The following pattern is needed because without the pattern, the
2358 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2359 ;; shifts, one ashift and one ashiftrt.
2361 (define_insn_and_split "*extendqisi2_h8300hs"
2362 [(set (match_operand:SI 0 "register_operand" "=r")
2363 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2364 "(TARGET_H8300H || TARGET_H8300S)"
2366 "&& reload_completed"
2368 (sign_extend:HI (match_dup 1)))
2370 (sign_extend:SI (match_dup 2)))]
2371 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2373 (define_expand "extendhisi2"
2374 [(set (match_operand:SI 0 "register_operand" "")
2375 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2379 (define_insn "*extendhisi2_h8300"
2380 [(set (match_operand:SI 0 "register_operand" "=r,r")
2381 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2384 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2385 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2386 [(set_attr "length" "6,10")])
2388 (define_insn "*extendhisi2_h8300hs"
2389 [(set (match_operand:SI 0 "register_operand" "=r")
2390 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2391 "TARGET_H8300H || TARGET_H8300S"
2393 [(set_attr "length" "2")
2394 (set_attr "cc" "set_znv")])
2396 ;; ----------------------------------------------------------------------
2398 ;; ----------------------------------------------------------------------
2400 ;; We make some attempt to provide real efficient shifting. One example is
2401 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2402 ;; reg and moving 0 into the former reg.
2404 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2405 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2406 ;; give the optimizer more cracks at the code. However, we wish to do things
2407 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2408 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2409 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2410 ;; to detect cases it can optimize.
2412 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2413 ;; easier "do it at insn emit time" route.
2417 (define_expand "ashlqi3"
2418 [(set (match_operand:QI 0 "register_operand" "")
2419 (ashift:QI (match_operand:QI 1 "register_operand" "")
2420 (match_operand:QI 2 "nonmemory_operand" "")))]
2422 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2424 (define_expand "ashrqi3"
2425 [(set (match_operand:QI 0 "register_operand" "")
2426 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2427 (match_operand:QI 2 "nonmemory_operand" "")))]
2429 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2431 (define_expand "lshrqi3"
2432 [(set (match_operand:QI 0 "register_operand" "")
2433 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2434 (match_operand:QI 2 "nonmemory_operand" "")))]
2436 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2438 (define_insn "*shiftqi"
2439 [(set (match_operand:QI 0 "register_operand" "=r,r")
2440 (match_operator:QI 3 "nshift_operator"
2441 [ (match_operand:QI 1 "register_operand" "0,0")
2442 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2443 (clobber (match_scratch:QI 4 "=X,&r"))]
2445 "* return output_a_shift (operands);"
2446 [(set (attr "length")
2447 (symbol_ref "compute_a_shift_length (insn, operands)"))
2449 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2453 (define_expand "ashlhi3"
2454 [(set (match_operand:HI 0 "register_operand" "")
2455 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2456 (match_operand:QI 2 "nonmemory_operand" "")))]
2458 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2460 (define_expand "lshrhi3"
2461 [(set (match_operand:HI 0 "register_operand" "")
2462 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2463 (match_operand:QI 2 "nonmemory_operand" "")))]
2465 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2467 (define_expand "ashrhi3"
2468 [(set (match_operand:HI 0 "register_operand" "")
2469 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2470 (match_operand:QI 2 "nonmemory_operand" "")))]
2472 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2474 (define_insn "*shifthi"
2475 [(set (match_operand:HI 0 "register_operand" "=r,r")
2476 (match_operator:HI 3 "nshift_operator"
2477 [ (match_operand:HI 1 "register_operand" "0,0")
2478 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2479 (clobber (match_scratch:QI 4 "=X,&r"))]
2481 "* return output_a_shift (operands);"
2482 [(set (attr "length")
2483 (symbol_ref "compute_a_shift_length (insn, operands)"))
2485 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2489 (define_expand "ashlsi3"
2490 [(set (match_operand:SI 0 "register_operand" "")
2491 (ashift:SI (match_operand:SI 1 "general_operand" "")
2492 (match_operand:QI 2 "nonmemory_operand" "")))]
2494 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2496 (define_expand "lshrsi3"
2497 [(set (match_operand:SI 0 "register_operand" "")
2498 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2499 (match_operand:QI 2 "nonmemory_operand" "")))]
2501 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2503 (define_expand "ashrsi3"
2504 [(set (match_operand:SI 0 "register_operand" "")
2505 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2506 (match_operand:QI 2 "nonmemory_operand" "")))]
2508 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2510 (define_insn "*shiftsi"
2511 [(set (match_operand:SI 0 "register_operand" "=r,r")
2512 (match_operator:SI 3 "nshift_operator"
2513 [ (match_operand:SI 1 "register_operand" "0,0")
2514 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2515 (clobber (match_scratch:QI 4 "=X,&r"))]
2517 "* return output_a_shift (operands);"
2518 [(set (attr "length")
2519 (symbol_ref "compute_a_shift_length (insn, operands)"))
2521 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2523 ;; Split a variable shift into a loop. If the register containing
2524 ;; the shift count dies, then we just use that register.
2527 [(set (match_operand 0 "register_operand" "")
2528 (match_operator 2 "nshift_operator"
2530 (match_operand:QI 1 "register_operand" "")]))
2531 (clobber (match_operand:QI 3 "register_operand" ""))]
2533 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2537 (if_then_else (le (cc0) (const_int 0))
2538 (label_ref (match_dup 5))
2543 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2544 (clobber (scratch:QI))])
2546 (plus:QI (match_dup 1) (const_int -1)))
2550 (if_then_else (ne (cc0) (const_int 0))
2551 (label_ref (match_dup 4))
2554 "operands[4] = gen_label_rtx ();
2555 operands[5] = gen_label_rtx ();")
2558 [(set (match_operand 0 "register_operand" "")
2559 (match_operator 2 "nshift_operator"
2561 (match_operand:QI 1 "register_operand" "")]))
2562 (clobber (match_operand:QI 3 "register_operand" ""))]
2564 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2570 (if_then_else (le (cc0) (const_int 0))
2571 (label_ref (match_dup 5))
2576 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2577 (clobber (scratch:QI))])
2579 (plus:QI (match_dup 3) (const_int -1)))
2583 (if_then_else (ne (cc0) (const_int 0))
2584 (label_ref (match_dup 4))
2587 "operands[4] = gen_label_rtx ();
2588 operands[5] = gen_label_rtx ();")
2590 ;; ----------------------------------------------------------------------
2592 ;; ----------------------------------------------------------------------
2594 (define_expand "rotlqi3"
2595 [(set (match_operand:QI 0 "register_operand" "")
2596 (rotate:QI (match_operand:QI 1 "register_operand" "")
2597 (match_operand:QI 2 "nonmemory_operand" "")))]
2599 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2601 (define_insn "*rotlqi3_1"
2602 [(set (match_operand:QI 0 "register_operand" "=r")
2603 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2604 (match_operand:QI 2 "immediate_operand" "")))]
2606 "* return output_a_rotate (ROTATE, operands);"
2607 [(set (attr "length")
2608 (symbol_ref "compute_a_rotate_length (operands)"))])
2610 (define_expand "rotlhi3"
2611 [(set (match_operand:HI 0 "register_operand" "")
2612 (rotate:HI (match_operand:HI 1 "register_operand" "")
2613 (match_operand:QI 2 "nonmemory_operand" "")))]
2615 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2617 (define_insn "*rotlhi3_1"
2618 [(set (match_operand:HI 0 "register_operand" "=r")
2619 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2620 (match_operand:QI 2 "immediate_operand" "")))]
2622 "* return output_a_rotate (ROTATE, operands);"
2623 [(set (attr "length")
2624 (symbol_ref "compute_a_rotate_length (operands)"))])
2626 (define_expand "rotlsi3"
2627 [(set (match_operand:SI 0 "register_operand" "")
2628 (rotate:SI (match_operand:SI 1 "register_operand" "")
2629 (match_operand:QI 2 "nonmemory_operand" "")))]
2630 "TARGET_H8300H || TARGET_H8300S"
2631 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2633 (define_insn "*rotlsi3_1"
2634 [(set (match_operand:SI 0 "register_operand" "=r")
2635 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2636 (match_operand:QI 2 "immediate_operand" "")))]
2637 "TARGET_H8300H || TARGET_H8300S"
2638 "* return output_a_rotate (ROTATE, operands);"
2639 [(set (attr "length")
2640 (symbol_ref "compute_a_rotate_length (operands)"))])
2642 ;; -----------------------------------------------------------------
2644 ;; -----------------------------------------------------------------
2645 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2646 ;; instructions so let's use them as well as we can.
2648 ;; You'll never believe all these patterns perform one basic action --
2649 ;; load a bit from the source, optionally invert the bit, then store it
2650 ;; in the destination (which is known to be zero).
2652 ;; Combine obviously need some work to better identify this situation and
2653 ;; canonicalize the form better.
2656 ;; Normal loads with a 16bit destination.
2660 [(set (match_operand:HI 0 "register_operand" "=&r")
2661 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2663 (match_operand:HI 2 "immediate_operand" "n")))]
2665 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2666 [(set_attr "length" "6")])
2669 ;; Inverted loads with a 16bit destination.
2673 [(set (match_operand:HI 0 "register_operand" "=&r")
2674 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2675 (match_operand:HI 3 "const_int_operand" "n"))
2677 (match_operand:HI 2 "const_int_operand" "n")))]
2679 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2680 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2681 [(set_attr "length" "8")])
2684 ;; Normal loads with a 32bit destination.
2687 (define_insn "*extzv_1_r_h8300"
2688 [(set (match_operand:SI 0 "register_operand" "=&r")
2689 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2691 (match_operand 2 "const_int_operand" "n")))]
2693 && INTVAL (operands[2]) < 16"
2694 "* return output_simode_bld (0, operands);"
2695 [(set_attr "length" "8")])
2697 (define_insn "*extzv_1_r_h8300hs"
2698 [(set (match_operand:SI 0 "register_operand" "=r,r")
2699 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2701 (match_operand 2 "const_int_operand" "n,n")))]
2702 "(TARGET_H8300H || TARGET_H8300S)
2703 && INTVAL (operands[2]) < 16"
2704 "* return output_simode_bld (0, operands);"
2705 [(set_attr "cc" "set_znv,set_znv")
2706 (set_attr "length" "8,6")])
2709 ;; Inverted loads with a 32bit destination.
2712 (define_insn "*extzv_1_r_inv_h8300"
2713 [(set (match_operand:SI 0 "register_operand" "=&r")
2714 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2715 (match_operand:HI 3 "const_int_operand" "n"))
2717 (match_operand 2 "const_int_operand" "n")))]
2719 && INTVAL (operands[2]) < 16
2720 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2721 "* return output_simode_bld (1, operands);"
2722 [(set_attr "length" "8")])
2724 (define_insn "*extzv_1_r_inv_h8300hs"
2725 [(set (match_operand:SI 0 "register_operand" "=r,r")
2726 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2727 (match_operand 3 "const_int_operand" "n,n"))
2729 (match_operand 2 "const_int_operand" "n,n")))]
2730 "(TARGET_H8300H || TARGET_H8300S)
2731 && INTVAL (operands[2]) < 16
2732 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2733 "* return output_simode_bld (1, operands);"
2734 [(set_attr "cc" "set_znv,set_znv")
2735 (set_attr "length" "8,6")])
2737 (define_expand "insv"
2738 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2739 (match_operand:HI 1 "general_operand" "")
2740 (match_operand:HI 2 "general_operand" ""))
2741 (match_operand:HI 3 "general_operand" ""))]
2745 /* We only have single bit bit-field instructions. */
2746 if (INTVAL (operands[1]) != 1)
2749 /* For now, we don't allow memory operands. */
2750 if (GET_CODE (operands[0]) == MEM
2751 || GET_CODE (operands[3]) == MEM)
2756 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2758 (match_operand:HI 1 "immediate_operand" "n"))
2759 (match_operand:HI 2 "register_operand" "r"))]
2761 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2762 [(set_attr "length" "4")])
2764 (define_expand "extzv"
2765 [(set (match_operand:HI 0 "register_operand" "")
2766 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2767 (match_operand:HI 2 "general_operand" "")
2768 (match_operand:HI 3 "general_operand" "")))]
2772 /* We only have single bit bit-field instructions. */
2773 if (INTVAL (operands[2]) != 1)
2776 /* For now, we don't allow memory operands. */
2777 if (GET_CODE (operands[1]) == MEM)
2781 ;; BAND, BOR, and BXOR patterns
2784 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2785 (match_operator:HI 4 "bit_operator"
2786 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2788 (match_operand:HI 2 "immediate_operand" "n"))
2789 (match_operand:HI 3 "bit_operand" "0")]))]
2791 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2792 [(set_attr "length" "6")])
2795 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2796 (match_operator:HI 5 "bit_operator"
2797 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2799 (match_operand:HI 2 "immediate_operand" "n"))
2800 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2802 (match_operand:HI 4 "immediate_operand" "n"))]))]
2804 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2805 [(set_attr "length" "6")])
2807 ;; -----------------------------------------------------------------
2809 ;; -----------------------------------------------------------------
2813 (define_insn "*insv_si_1_n"
2814 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2816 (match_operand:SI 1 "const_int_operand" "n"))
2817 (match_operand:SI 2 "register_operand" "r"))]
2818 "(TARGET_H8300H || TARGET_H8300S)
2819 && INTVAL (operands[1]) < 16"
2820 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2821 [(set_attr "length" "4")])
2823 (define_insn "*insv_si_1_n_lshiftrt"
2824 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2826 (match_operand:SI 1 "const_int_operand" "n"))
2827 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2828 (match_operand:SI 3 "const_int_operand" "n")))]
2829 "(TARGET_H8300H || TARGET_H8300S)
2830 && INTVAL (operands[1]) < 16
2831 && INTVAL (operands[3]) < 16"
2832 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2833 [(set_attr "length" "4")])
2835 (define_insn "*insv_si_1_n_lshiftrt_16"
2836 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2838 (match_operand:SI 1 "const_int_operand" "n"))
2839 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2841 "(TARGET_H8300H || TARGET_H8300S)
2842 && INTVAL (operands[1]) < 16"
2843 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2844 [(set_attr "length" "6")])
2846 (define_insn "*insv_si_8_8"
2847 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2850 (match_operand:SI 1 "register_operand" "r"))]
2851 "TARGET_H8300H || TARGET_H8300S"
2853 [(set_attr "length" "2")])
2855 (define_insn "*insv_si_8_8_lshiftrt_8"
2856 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2859 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2861 "TARGET_H8300H || TARGET_H8300S"
2863 [(set_attr "length" "2")])
2867 (define_insn "*extzv_8_8"
2868 [(set (match_operand:SI 0 "register_operand" "=r,r")
2869 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2872 "TARGET_H8300H || TARGET_H8300S"
2874 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2875 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2876 [(set_attr "cc" "set_znv,clobber")
2877 (set_attr "length" "6,4")])
2879 (define_insn "*extzv_8_16"
2880 [(set (match_operand:SI 0 "register_operand" "=r")
2881 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2884 "TARGET_H8300H || TARGET_H8300S"
2885 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2886 [(set_attr "cc" "set_znv")
2887 (set_attr "length" "6")])
2889 (define_insn "*extzv_16_8"
2890 [(set (match_operand:SI 0 "register_operand" "=r")
2891 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2894 (clobber (match_scratch:SI 2 "=&r"))]
2896 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2897 [(set_attr "length" "8")
2898 (set_attr "cc" "set_znv")])
2900 ;; Extract the exponent of a float.
2902 (define_insn_and_split "*extzv_8_23"
2903 [(set (match_operand:SI 0 "register_operand" "=r")
2904 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2907 "(TARGET_H8300H || TARGET_H8300S)"
2909 "&& reload_completed"
2910 [(parallel [(set (match_dup 0)
2911 (ashift:SI (match_dup 0)
2913 (clobber (scratch:QI))])
2914 (parallel [(set (match_dup 0)
2915 (lshiftrt:SI (match_dup 0)
2917 (clobber (scratch:QI))])]
2922 ;; ((SImode) HImode) << 15
2924 (define_insn_and_split "*twoshifts_l16_r1"
2925 [(set (match_operand:SI 0 "register_operand" "=r")
2926 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2928 (const_int 2147450880)))]
2929 "(TARGET_H8300H || TARGET_H8300S)"
2931 "&& reload_completed"
2932 [(parallel [(set (match_dup 0)
2933 (ashift:SI (match_dup 0)
2935 (clobber (scratch:QI))])
2936 (parallel [(set (match_dup 0)
2937 (lshiftrt:SI (match_dup 0)
2939 (clobber (scratch:QI))])]
2942 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2944 (define_insn_and_split "*andsi3_ashift_n_lower"
2945 [(set (match_operand:SI 0 "register_operand" "=r,r")
2946 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2947 (match_operand:QI 2 "const_int_operand" "S,n"))
2948 (match_operand:SI 3 "const_int_operand" "n,n")))
2949 (clobber (match_scratch:QI 4 "=X,&r"))]
2950 "(TARGET_H8300H || TARGET_H8300S)
2951 && INTVAL (operands[2]) <= 15
2952 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2954 "&& reload_completed"
2955 [(parallel [(set (match_dup 5)
2956 (ashift:HI (match_dup 5)
2958 (clobber (match_dup 4))])
2960 (zero_extend:SI (match_dup 5)))]
2961 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2963 ;; Accept (A >> 30) & 2 and the like.
2965 (define_insn "*andsi3_lshiftrt_n_sb"
2966 [(set (match_operand:SI 0 "register_operand" "=r")
2967 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2968 (match_operand:SI 2 "const_int_operand" "n"))
2969 (match_operand:SI 3 "single_one_operand" "n")))]
2970 "(TARGET_H8300H || TARGET_H8300S)
2971 && exact_log2 (INTVAL (operands[3])) < 16
2972 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2975 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2976 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2978 [(set_attr "length" "8")])
2980 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2981 [(set (match_operand:SI 0 "register_operand" "=r")
2982 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2984 (const_int 4194304)))]
2985 "(TARGET_H8300H || TARGET_H8300S)"
2987 "&& reload_completed"
2989 (and:SI (lshiftrt:SI (match_dup 0)
2992 (parallel [(set (match_dup 0)
2993 (ashift:SI (match_dup 0)
2995 (clobber (scratch:QI))])]
3000 (define_insn "*addsi3_upper"
3001 [(set (match_operand:SI 0 "register_operand" "=r")
3002 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3004 (match_operand:SI 2 "register_operand" "0")))]
3005 "TARGET_H8300H || TARGET_H8300S"
3007 [(set_attr "length" "2")])
3009 (define_insn "*addsi3_lshiftrt_16_zexthi"
3010 [(set (match_operand:SI 0 "register_operand" "=r")
3011 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3013 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3014 "TARGET_H8300H || TARGET_H8300S"
3015 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3016 [(set_attr "length" "6")])
3018 (define_insn_and_split "*addsi3_and_r_1"
3019 [(set (match_operand:SI 0 "register_operand" "=r")
3020 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3022 (match_operand:SI 2 "register_operand" "0")))]
3023 "(TARGET_H8300H || TARGET_H8300S)"
3025 "&& reload_completed"
3027 (zero_extract:SI (match_dup 1)
3031 (if_then_else (eq (cc0)
3033 (label_ref (match_dup 3))
3036 (plus:SI (match_dup 2)
3039 "operands[3] = gen_label_rtx ();")
3041 (define_insn_and_split "*addsi3_and_not_r_1"
3042 [(set (match_operand:SI 0 "register_operand" "=r")
3043 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3045 (match_operand:SI 2 "register_operand" "0")))]
3046 "(TARGET_H8300H || TARGET_H8300S)"
3048 "&& reload_completed"
3050 (zero_extract:SI (match_dup 1)
3054 (if_then_else (ne (cc0)
3056 (label_ref (match_dup 3))
3059 (plus:SI (match_dup 2)
3062 "operands[3] = gen_label_rtx ();")
3066 (define_insn "*ixorhi3_zext"
3067 [(set (match_operand:HI 0 "register_operand" "=r")
3068 (match_operator:HI 1 "iorxor_operator"
3069 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3070 (match_operand:HI 3 "register_operand" "0")]))]
3073 [(set_attr "length" "2")])
3077 (define_insn "*ixorsi3_zext_qi"
3078 [(set (match_operand:SI 0 "register_operand" "=r")
3079 (match_operator:SI 1 "iorxor_operator"
3080 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3081 (match_operand:SI 3 "register_operand" "0")]))]
3084 [(set_attr "length" "2")])
3086 (define_insn "*ixorsi3_zext_hi"
3087 [(set (match_operand:SI 0 "register_operand" "=r")
3088 (match_operator:SI 1 "iorxor_operator"
3089 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3090 (match_operand:SI 3 "register_operand" "0")]))]
3091 "TARGET_H8300H || TARGET_H8300S"
3093 [(set_attr "length" "2")])
3095 (define_insn "*ixorsi3_ashift_16"
3096 [(set (match_operand:SI 0 "register_operand" "=r")
3097 (match_operator:SI 1 "iorxor_operator"
3098 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3100 (match_operand:SI 3 "register_operand" "0")]))]
3101 "TARGET_H8300H || TARGET_H8300S"
3103 [(set_attr "length" "2")])
3105 (define_insn "*ixorsi3_lshiftrt_16"
3106 [(set (match_operand:SI 0 "register_operand" "=r")
3107 (match_operator:SI 1 "iorxor_operator"
3108 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3110 (match_operand:SI 3 "register_operand" "0")]))]
3111 "TARGET_H8300H || TARGET_H8300S"
3113 [(set_attr "length" "2")])
3117 (define_insn "*iorhi3_ashift_8"
3118 [(set (match_operand:HI 0 "register_operand" "=r")
3119 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3121 (match_operand:HI 2 "register_operand" "0")))]
3124 [(set_attr "length" "2")])
3126 (define_insn "*iorhi3_lshiftrt_8"
3127 [(set (match_operand:HI 0 "register_operand" "=r")
3128 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3130 (match_operand:HI 2 "register_operand" "0")))]
3133 [(set_attr "length" "2")])
3135 (define_insn "*iorhi3_two_qi"
3136 [(set (match_operand:HI 0 "register_operand" "=r")
3137 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3138 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3142 [(set_attr "length" "2")])
3144 (define_insn "*iorhi3_two_qi_mem"
3145 [(set (match_operand:HI 0 "register_operand" "=&r")
3146 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3147 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3150 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3151 [(set_attr "length" "16")])
3154 [(set (match_operand:HI 0 "register_operand" "")
3155 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3156 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3158 "(TARGET_H8300H || TARGET_H8300S)
3160 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3163 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3167 (define_insn "*iorsi3_two_hi"
3168 [(set (match_operand:SI 0 "register_operand" "=r")
3169 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3170 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3172 "TARGET_H8300H || TARGET_H8300S"
3174 [(set_attr "length" "2")])
3176 (define_insn_and_split "*iorsi3_two_qi_zext"
3177 [(set (match_operand:SI 0 "register_operand" "=&r")
3178 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3180 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3182 (const_int 65280))))]
3183 "(TARGET_H8300H || TARGET_H8300S)"
3185 "&& reload_completed"
3187 (ior:HI (zero_extend:HI (match_dup 1))
3188 (ashift:HI (subreg:HI (match_dup 2) 0)
3191 (zero_extend:SI (match_dup 3)))]
3192 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3194 (define_insn "*iorsi3_e2f"
3195 [(set (match_operand:SI 0 "register_operand" "=r")
3196 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3198 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3200 "TARGET_H8300H || TARGET_H8300S"
3202 [(set_attr "length" "2")])
3204 (define_insn_and_split "*iorsi3_two_qi_sext"
3205 [(set (match_operand:SI 0 "register_operand" "=r")
3206 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3207 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3209 "(TARGET_H8300H || TARGET_H8300S)"
3211 "&& reload_completed"
3213 (ior:HI (zero_extend:HI (match_dup 1))
3214 (ashift:HI (match_dup 4)
3217 (sign_extend:SI (match_dup 3)))]
3218 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3219 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3221 (define_insn "*iorsi3_w"
3222 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3223 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3225 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3226 "TARGET_H8300H || TARGET_H8300S"
3228 [(set_attr "length" "2,8")])
3230 (define_insn "*iorsi3_ashift_31"
3231 [(set (match_operand:SI 0 "register_operand" "=&r")
3232 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3234 (match_operand:SI 2 "register_operand" "0")))]
3235 "TARGET_H8300H || TARGET_H8300S"
3236 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3237 [(set_attr "length" "6")
3238 (set_attr "cc" "set_znv")])
3240 (define_insn "*iorsi3_and_ashift"
3241 [(set (match_operand:SI 0 "register_operand" "=r")
3242 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3243 (match_operand:SI 2 "const_int_operand" "n"))
3244 (match_operand:SI 3 "single_one_operand" "n"))
3245 (match_operand:SI 4 "register_operand" "0")))]
3246 "(TARGET_H8300H || TARGET_H8300S)
3247 && (INTVAL (operands[3]) & ~0xffff) == 0"
3250 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3251 - INTVAL (operands[2]));
3252 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3253 operands[2] = srcpos;
3254 operands[3] = dstpos;
3255 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3257 [(set_attr "length" "6")])
3259 (define_insn "*iorsi3_and_lshiftrt"
3260 [(set (match_operand:SI 0 "register_operand" "=r")
3261 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3262 (match_operand:SI 2 "const_int_operand" "n"))
3263 (match_operand:SI 3 "single_one_operand" "n"))
3264 (match_operand:SI 4 "register_operand" "0")))]
3265 "(TARGET_H8300H || TARGET_H8300S)
3266 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3269 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3270 + INTVAL (operands[2]));
3271 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3272 operands[2] = srcpos;
3273 operands[3] = dstpos;
3274 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3276 [(set_attr "length" "6")])
3278 (define_insn "*iorsi3_zero_extract"
3279 [(set (match_operand:SI 0 "register_operand" "=r")
3280 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3282 (match_operand:SI 2 "const_int_operand" "n"))
3283 (match_operand:SI 3 "register_operand" "0")))]
3284 "(TARGET_H8300H || TARGET_H8300S)
3285 && INTVAL (operands[2]) < 16"
3286 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3287 [(set_attr "length" "6")])
3289 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3290 [(set (match_operand:SI 0 "register_operand" "=r")
3291 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3294 (match_operand:SI 2 "register_operand" "0")))]
3295 "(TARGET_H8300H || TARGET_H8300S)"
3296 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3297 [(set_attr "length" "8")])
3299 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3300 [(set (match_operand:SI 0 "register_operand" "=r")
3301 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3303 (const_int 4194304))
3304 (match_operand:SI 2 "register_operand" "0")))
3305 (clobber (match_scratch:HI 3 "=&r"))]
3306 "(TARGET_H8300H || TARGET_H8300S)"
3309 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3310 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3312 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3314 [(set_attr "length" "10")])
3316 ;; Used to OR the exponent of a float.
3318 (define_insn "*iorsi3_shift"
3319 [(set (match_operand:SI 0 "register_operand" "=r")
3320 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3322 (match_operand:SI 2 "register_operand" "0")))
3323 (clobber (match_scratch:SI 3 "=&r"))]
3324 "TARGET_H8300H || TARGET_H8300S"
3328 [(set (match_operand:SI 0 "register_operand" "")
3329 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3332 (clobber (match_operand:SI 2 "register_operand" ""))]
3333 "(TARGET_H8300H || TARGET_H8300S)
3335 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3336 && REGNO (operands[0]) != REGNO (operands[1])"
3337 [(parallel [(set (match_dup 3)
3338 (ashift:HI (match_dup 3)
3340 (clobber (scratch:QI))])
3342 (ior:SI (ashift:SI (match_dup 1)
3345 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3348 [(set (match_operand:SI 0 "register_operand" "")
3349 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3352 (clobber (match_operand:SI 2 "register_operand" ""))]
3353 "(TARGET_H8300H || TARGET_H8300S)
3355 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3356 && REGNO (operands[0]) != REGNO (operands[1]))"
3359 (parallel [(set (match_dup 3)
3360 (ashift:HI (match_dup 3)
3362 (clobber (scratch:QI))])
3364 (ior:SI (ashift:SI (match_dup 2)
3367 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3369 (define_insn "*iorsi2_and_1_lshiftrt_1"
3370 [(set (match_operand:SI 0 "register_operand" "=r")
3371 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3373 (lshiftrt:SI (match_dup 1)
3375 "TARGET_H8300H || TARGET_H8300S"
3376 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3377 [(set_attr "length" "6")])
3379 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3380 [(set (match_operand:SI 0 "register_operand" "=r")
3381 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3383 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3385 "(TARGET_H8300H || TARGET_H8300S)"
3387 "&& reload_completed"
3389 (ior:HI (ashift:HI (match_dup 4)
3392 (parallel [(set (match_dup 0)
3393 (ashift:SI (match_dup 0)
3395 (clobber (scratch:QI))])]
3396 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3397 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3399 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3400 [(set (match_operand:SI 0 "register_operand" "=&r")
3401 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3403 (const_int 16711680))
3404 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3406 "(TARGET_H8300H || TARGET_H8300S)"
3408 "&& reload_completed"
3410 (ior:HI (zero_extend:HI (match_dup 1))
3411 (ashift:HI (subreg:HI (match_dup 2) 0)
3413 (parallel [(set (match_dup 0)
3414 (ashift:SI (match_dup 0)
3416 (clobber (scratch:QI))])]
3417 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3419 ;; Used to add the exponent of a float.
3421 (define_insn "*addsi3_shift"
3422 [(set (match_operand:SI 0 "register_operand" "=r")
3423 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3424 (const_int 8388608))
3425 (match_operand:SI 2 "register_operand" "0")))
3426 (clobber (match_scratch:SI 3 "=&r"))]
3427 "TARGET_H8300H || TARGET_H8300S"
3431 [(set (match_operand:SI 0 "register_operand" "")
3432 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3433 (const_int 8388608))
3435 (clobber (match_operand:SI 2 "register_operand" ""))]
3436 "(TARGET_H8300H || TARGET_H8300S)
3438 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3439 && REGNO (operands[0]) != REGNO (operands[1])"
3440 [(parallel [(set (match_dup 3)
3441 (ashift:HI (match_dup 3)
3443 (clobber (scratch:QI))])
3445 (plus:SI (mult:SI (match_dup 1)
3448 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3451 [(set (match_operand:SI 0 "register_operand" "")
3452 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3453 (const_int 8388608))
3455 (clobber (match_operand:SI 2 "register_operand" ""))]
3456 "(TARGET_H8300H || TARGET_H8300S)
3458 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3459 && REGNO (operands[0]) != REGNO (operands[1]))"
3462 (parallel [(set (match_dup 3)
3463 (ashift:HI (match_dup 3)
3465 (clobber (scratch:QI))])
3467 (plus:SI (mult:SI (match_dup 2)
3470 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3474 (define_insn_and_split "*ashiftsi_sextqi_7"
3475 [(set (match_operand:SI 0 "register_operand" "=r")
3476 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3478 "(TARGET_H8300H || TARGET_H8300S)"
3480 "&& reload_completed"
3481 [(parallel [(set (match_dup 2)
3482 (ashift:HI (match_dup 2)
3484 (clobber (scratch:QI))])
3486 (sign_extend:SI (match_dup 2)))
3487 (parallel [(set (match_dup 0)
3488 (ashiftrt:SI (match_dup 0)
3490 (clobber (scratch:QI))])]
3491 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3493 ;; Storing a part of HImode to QImode.
3496 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3497 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3501 [(set_attr "cc" "set_znv")
3502 (set_attr "length" "8")])
3504 ;; Storing a part of SImode to QImode.
3507 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3508 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3512 [(set_attr "cc" "set_znv")
3513 (set_attr "length" "8")])
3516 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3517 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3519 (clobber (match_scratch:SI 2 "=&r"))]
3520 "TARGET_H8300H || TARGET_H8300S"
3521 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3522 [(set_attr "cc" "set_znv")
3523 (set_attr "length" "10")])
3526 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3527 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3529 (clobber (match_scratch:SI 2 "=&r"))]
3530 "TARGET_H8300H || TARGET_H8300S"
3531 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3532 [(set_attr "cc" "set_znv")
3533 (set_attr "length" "10")])
3535 (define_insn_and_split ""
3537 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3541 (label_ref (match_operand 1 "" ""))
3549 (if_then_else (ge (cc0)
3551 (label_ref (match_dup 1))
3555 (define_insn_and_split ""
3557 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3561 (label_ref (match_operand 1 "" ""))
3569 (if_then_else (lt (cc0)
3571 (label_ref (match_dup 1))
3575 ;; -----------------------------------------------------------------
3576 ;; PEEPHOLE PATTERNS
3577 ;; -----------------------------------------------------------------
3579 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3583 [(set (match_operand:HI 0 "register_operand" "")
3584 (lshiftrt:HI (match_dup 0)
3585 (match_operand:HI 1 "const_int_operand" "")))
3586 (clobber (match_operand:HI 2 "" ""))])
3588 (and:HI (match_dup 0)
3589 (match_operand:HI 3 "const_int_operand" "")))]
3590 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3592 (and:HI (match_dup 0)
3596 (lshiftrt:HI (match_dup 0)
3598 (clobber (match_dup 2))])]
3601 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3605 [(set (match_operand:HI 0 "register_operand" "")
3606 (ashift:HI (match_dup 0)
3607 (match_operand:HI 1 "const_int_operand" "")))
3608 (clobber (match_operand:HI 2 "" ""))])
3610 (and:HI (match_dup 0)
3611 (match_operand:HI 3 "const_int_operand" "")))]
3612 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3614 (and:HI (match_dup 0)
3618 (ashift:HI (match_dup 0)
3620 (clobber (match_dup 2))])]
3623 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3627 [(set (match_operand:SI 0 "register_operand" "")
3628 (lshiftrt:SI (match_dup 0)
3629 (match_operand:SI 1 "const_int_operand" "")))
3630 (clobber (match_operand:SI 2 "" ""))])
3632 (and:SI (match_dup 0)
3633 (match_operand:SI 3 "const_int_operand" "")))]
3634 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3636 (and:SI (match_dup 0)
3640 (lshiftrt:SI (match_dup 0)
3642 (clobber (match_dup 2))])]
3645 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3649 [(set (match_operand:SI 0 "register_operand" "")
3650 (ashift:SI (match_dup 0)
3651 (match_operand:SI 1 "const_int_operand" "")))
3652 (clobber (match_operand:SI 2 "" ""))])
3654 (and:SI (match_dup 0)
3655 (match_operand:SI 3 "const_int_operand" "")))]
3656 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3658 (and:SI (match_dup 0)
3662 (ashift:SI (match_dup 0)
3664 (clobber (match_dup 2))])]
3667 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3671 [(set (match_operand:SI 0 "register_operand" "")
3672 (lshiftrt:SI (match_dup 0)
3673 (match_operand:SI 1 "const_int_operand" "")))
3674 (clobber (match_operand:SI 2 "" ""))])
3676 (and:SI (match_dup 0)
3677 (match_operand:SI 3 "const_int_operand" "")))]
3678 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3680 (and:SI (match_dup 0)
3684 (lshiftrt:SI (match_dup 0)
3686 (clobber (match_dup 2))])]
3689 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3693 [(set (match_operand:SI 0 "register_operand" "")
3694 (ashift:SI (match_dup 0)
3695 (match_operand:SI 1 "const_int_operand" "")))
3696 (clobber (match_operand:SI 2 "" ""))])
3698 (and:SI (match_dup 0)
3699 (match_operand:SI 3 "const_int_operand" "")))]
3700 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3702 (and:SI (match_dup 0)
3706 (ashift:SI (match_dup 0)
3708 (clobber (match_dup 2))])]
3711 ;; Convert a QImode push into an SImode push so that the
3712 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3715 [(parallel [(set (reg:SI SP_REG)
3716 (plus:SI (reg:SI SP_REG) (const_int -4)))
3717 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3718 (match_operand:QI 0 "register_operand" ""))])]
3719 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3720 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3722 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3725 [(parallel [(set (reg:HI SP_REG)
3726 (plus:HI (reg:HI SP_REG) (const_int -4)))
3727 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3728 (match_operand:QI 0 "register_operand" ""))])]
3729 "TARGET_H8300S && TARGET_NORMAL_MODE"
3730 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3732 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3734 ;; Convert a HImode push into an SImode push so that the
3735 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3738 [(parallel [(set (reg:SI SP_REG)
3739 (plus:SI (reg:SI SP_REG) (const_int -4)))
3740 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3741 (match_operand:HI 0 "register_operand" ""))])]
3742 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3743 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3745 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3748 [(parallel [(set (reg:HI SP_REG)
3749 (plus:HI (reg:HI SP_REG) (const_int -4)))
3750 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3751 (match_operand:HI 0 "register_operand" ""))])]
3752 "TARGET_H8300S && TARGET_NORMAL_MODE"
3753 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3755 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3757 ;; Cram four pushes into stm.l.
3760 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3761 (match_operand:SI 0 "register_operand" ""))
3762 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3763 (match_operand:SI 1 "register_operand" ""))
3764 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3765 (match_operand:SI 2 "register_operand" ""))
3766 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3767 (match_operand:SI 3 "register_operand" ""))]
3768 "TARGET_H8300S && !TARGET_NORMAL_MODE
3769 && REGNO (operands[0]) == 0
3770 && REGNO (operands[1]) == 1
3771 && REGNO (operands[2]) == 2
3772 && REGNO (operands[3]) == 3"
3773 [(parallel [(set (reg:SI SP_REG)
3774 (plus:SI (reg:SI SP_REG)
3776 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3778 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3780 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3782 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3787 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3788 (match_operand:SI 0 "register_operand" ""))
3789 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3790 (match_operand:SI 1 "register_operand" ""))
3791 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3792 (match_operand:SI 2 "register_operand" ""))
3793 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3794 (match_operand:SI 3 "register_operand" ""))]
3795 "TARGET_H8300S && TARGET_NORMAL_MODE
3796 && REGNO (operands[0]) == 0
3797 && REGNO (operands[1]) == 1
3798 && REGNO (operands[2]) == 2
3799 && REGNO (operands[3]) == 3"
3800 [(parallel [(set (reg:HI SP_REG)
3801 (plus:HI (reg:HI SP_REG)
3803 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3805 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3807 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3809 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3813 ;; Cram three pushes into stm.l.
3816 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3817 (match_operand:SI 0 "register_operand" ""))
3818 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3819 (match_operand:SI 1 "register_operand" ""))
3820 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3821 (match_operand:SI 2 "register_operand" ""))]
3822 "TARGET_H8300S && !TARGET_NORMAL_MODE
3823 && ((REGNO (operands[0]) == 0
3824 && REGNO (operands[1]) == 1
3825 && REGNO (operands[2]) == 2)
3826 || (REGNO (operands[0]) == 4
3827 && REGNO (operands[1]) == 5
3828 && REGNO (operands[2]) == 6))"
3829 [(parallel [(set (reg:SI SP_REG)
3830 (plus:SI (reg:SI SP_REG)
3832 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3834 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3836 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3841 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3842 (match_operand:SI 0 "register_operand" ""))
3843 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3844 (match_operand:SI 1 "register_operand" ""))
3845 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3846 (match_operand:SI 2 "register_operand" ""))]
3847 "TARGET_H8300S && TARGET_NORMAL_MODE
3848 && ((REGNO (operands[0]) == 0
3849 && REGNO (operands[1]) == 1
3850 && REGNO (operands[2]) == 2)
3851 || (REGNO (operands[0]) == 4
3852 && REGNO (operands[1]) == 5
3853 && REGNO (operands[2]) == 6))"
3854 [(parallel [(set (reg:HI SP_REG)
3855 (plus:HI (reg:HI SP_REG)
3857 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3859 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3861 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3865 ;; Cram two pushes into stm.l.
3868 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3869 (match_operand:SI 0 "register_operand" ""))
3870 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3871 (match_operand:SI 1 "register_operand" ""))]
3872 "TARGET_H8300S && !TARGET_NORMAL_MODE
3873 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3874 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3875 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3876 [(parallel [(set (reg:SI SP_REG)
3877 (plus:SI (reg:SI SP_REG)
3879 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3881 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3886 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3887 (match_operand:SI 0 "register_operand" ""))
3888 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3889 (match_operand:SI 1 "register_operand" ""))]
3890 "TARGET_H8300S && TARGET_NORMAL_MODE
3891 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3892 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3893 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3894 [(parallel [(set (reg:HI SP_REG)
3895 (plus:HI (reg:HI SP_REG)
3897 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3899 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3906 ;; add.w r7,r0 (6 bytes)
3911 ;; adds #2,r0 (4 bytes)
3914 [(set (match_operand:HI 0 "register_operand" "")
3915 (match_operand:HI 1 "const_int_operand" ""))
3917 (plus:HI (match_dup 0)
3918 (match_operand:HI 2 "register_operand" "")))]
3919 "REG_P (operands[0]) && REG_P (operands[2])
3920 && REGNO (operands[0]) != REGNO (operands[2])
3921 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3922 || CONST_OK_FOR_L (INTVAL (operands[1]))
3923 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3927 (plus:HI (match_dup 0)
3935 ;; add.l er7,er0 (6 bytes)
3940 ;; adds #4,er0 (4 bytes)
3943 [(set (match_operand:SI 0 "register_operand" "")
3944 (match_operand:SI 1 "const_int_operand" ""))
3946 (plus:SI (match_dup 0)
3947 (match_operand:SI 2 "register_operand" "")))]
3948 "(TARGET_H8300H || TARGET_H8300S)
3949 && REG_P (operands[0]) && REG_P (operands[2])
3950 && REGNO (operands[0]) != REGNO (operands[2])
3951 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3952 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3956 (plus:SI (match_dup 0)
3963 ;; add.l #10,er0 (takes 8 bytes)
3969 ;; add.l er7,er0 (takes 6 bytes)
3972 [(set (match_operand:SI 0 "register_operand" "")
3973 (match_operand:SI 1 "register_operand" ""))
3975 (plus:SI (match_dup 0)
3976 (match_operand:SI 2 "const_int_operand" "")))]
3977 "(TARGET_H8300H || TARGET_H8300S)
3978 && REG_P (operands[0]) && REG_P (operands[1])
3979 && REGNO (operands[0]) != REGNO (operands[1])
3980 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3981 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3982 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3983 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3984 || INTVAL (operands[2]) == 0xffff
3985 || INTVAL (operands[2]) == 0xfffe)"
3989 (plus:SI (match_dup 0)
4005 [(set (match_operand:HI 0 "register_operand" "")
4006 (plus:HI (match_dup 0)
4007 (match_operand 1 "incdec_operand" "")))
4011 (if_then_else (match_operator 3 "eqne_operator"
4012 [(cc0) (const_int 0)])
4013 (label_ref (match_operand 2 "" ""))
4015 "TARGET_H8300H || TARGET_H8300S"
4016 [(set (match_operand:HI 0 "register_operand" "")
4017 (unspec:HI [(match_dup 0)
4023 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4024 (label_ref (match_dup 2))
4028 ;; The SImode version of the previous pattern.
4031 [(set (match_operand:SI 0 "register_operand" "")
4032 (plus:SI (match_dup 0)
4033 (match_operand 1 "incdec_operand" "")))
4037 (if_then_else (match_operator 3 "eqne_operator"
4038 [(cc0) (const_int 0)])
4039 (label_ref (match_operand 2 "" ""))
4041 "TARGET_H8300H || TARGET_H8300S"
4042 [(set (match_operand:SI 0 "register_operand" "")
4043 (unspec:SI [(match_dup 0)
4049 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4050 (label_ref (match_dup 2))
4055 [(parallel [(set (cc0)
4056 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4059 (clobber (scratch:QI))])
4061 (if_then_else (match_operator 1 "eqne_operator"
4062 [(cc0) (const_int 0)])
4063 (label_ref (match_operand 2 "" ""))
4065 "(TARGET_H8300H || TARGET_H8300S)"
4069 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4070 (label_ref (match_dup 2))
4072 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4073 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4074 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4076 ;; The next three peephole2's will try to transform
4078 ;; mov.b A,r0l (or mov.l A,er0)
4085 ;; and.b #CST,r0l (if CST is not 255)
4088 [(set (match_operand:QI 0 "register_operand" "")
4089 (match_operand:QI 1 "general_operand" ""))
4090 (set (match_operand:SI 2 "register_operand" "")
4091 (and:SI (match_dup 2)
4093 "(TARGET_H8300H || TARGET_H8300S)
4094 && !reg_overlap_mentioned_p (operands[2], operands[1])
4095 && REGNO (operands[0]) == REGNO (operands[2])"
4098 (set (strict_low_part (match_dup 0))
4103 [(set (match_operand:SI 0 "register_operand" "")
4104 (match_operand:SI 1 "general_operand" ""))
4106 (and:SI (match_dup 0)
4108 "(TARGET_H8300H || TARGET_H8300S)
4109 && !reg_overlap_mentioned_p (operands[0], operands[1])
4110 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4113 (set (strict_low_part (match_dup 2))
4115 "operands[2] = gen_lowpart (QImode, operands[0]);
4116 operands[3] = gen_lowpart (QImode, operands[1]);")
4119 [(set (match_operand 0 "register_operand" "")
4120 (match_operand 1 "general_operand" ""))
4121 (set (match_operand:SI 2 "register_operand" "")
4122 (and:SI (match_dup 2)
4123 (match_operand:SI 3 "const_int_qi_operand" "")))]
4124 "(TARGET_H8300H || TARGET_H8300S)
4125 && (GET_MODE (operands[0]) == QImode
4126 || GET_MODE (operands[0]) == HImode
4127 || GET_MODE (operands[0]) == SImode)
4128 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4129 && REGNO (operands[0]) == REGNO (operands[2])
4130 && !reg_overlap_mentioned_p (operands[2], operands[1])
4131 && !(GET_MODE (operands[1]) != QImode
4132 && GET_CODE (operands[1]) == MEM
4133 && MEM_VOLATILE_P (operands[1]))"
4136 (set (strict_low_part (match_dup 4))
4139 (and:SI (match_dup 2)
4141 "operands[4] = gen_lowpart (QImode, operands[0]);
4142 operands[5] = gen_lowpart (QImode, operands[1]);
4143 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4146 [(set (match_operand:SI 0 "register_operand" "")
4147 (match_operand:SI 1 "register_operand" ""))
4149 (and:SI (match_dup 0)
4150 (const_int 65280)))]
4151 "(TARGET_H8300H || TARGET_H8300S)
4152 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4155 (set (zero_extract:SI (match_dup 0)
4158 (lshiftrt:SI (match_dup 1)
4162 ;; If a load of mem:SI is followed by an AND that turns off the upper
4163 ;; half, then we can load mem:HI instead.
4166 [(set (match_operand:SI 0 "register_operand" "")
4167 (match_operand:SI 1 "memory_operand" ""))
4169 (and:SI (match_dup 0)
4170 (match_operand:SI 2 "const_int_operand" "")))]
4171 "(TARGET_H8300H || TARGET_H8300S)
4172 && !MEM_VOLATILE_P (operands[1])
4173 && (INTVAL (operands[2]) & ~0xffff) == 0
4174 && INTVAL (operands[2]) != 255"
4178 (and:SI (match_dup 0)
4180 "operands[3] = gen_lowpart (HImode, operands[0]);
4181 operands[4] = gen_lowpart (HImode, operands[1]);")
4183 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4184 ;; the equivalent with shorter sequences. Here is the summary. Cases
4185 ;; are grouped for each define_peephole2.
4187 ;; reg const_int use insn
4188 ;; --------------------------------------------------------
4189 ;; dead -2 eq/ne inc.l
4190 ;; dead -1 eq/ne inc.l
4191 ;; dead 1 eq/ne dec.l
4192 ;; dead 2 eq/ne dec.l
4194 ;; dead 1 geu/ltu shar.l
4195 ;; dead 3 (H8S) geu/ltu shar.l
4197 ;; ---- 255 geu/ltu mov.b
4211 (compare (match_operand:HI 0 "register_operand" "")
4212 (match_operand:HI 1 "incdec_operand" "")))
4214 (if_then_else (match_operator 3 "eqne_operator"
4215 [(cc0) (const_int 0)])
4216 (label_ref (match_operand 2 "" ""))
4218 "(TARGET_H8300H || TARGET_H8300S)
4219 && peep2_reg_dead_p (1, operands[0])"
4221 (unspec:HI [(match_dup 0)
4227 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4228 (label_ref (match_dup 2))
4230 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4244 (compare (match_operand:HI 0 "register_operand" "")
4245 (match_operand:HI 1 "const_int_operand" "")))
4247 (if_then_else (match_operator 2 "gtle_operator"
4248 [(cc0) (const_int 0)])
4249 (label_ref (match_operand 3 "" ""))
4251 "(TARGET_H8300H || TARGET_H8300S)
4252 && peep2_reg_dead_p (1, operands[0])
4253 && (INTVAL (operands[1]) == 1
4254 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4255 [(parallel [(set (match_dup 0)
4256 (ashiftrt:HI (match_dup 0)
4258 (clobber (scratch:QI))])
4262 (if_then_else (match_dup 4)
4263 (label_ref (match_dup 3))
4265 "switch (GET_CODE (operands[2]))
4268 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4271 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4274 operands[4] = operands[2];
4277 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4291 (compare (match_operand:HI 0 "register_operand" "")
4294 (if_then_else (match_operator 1 "gtle_operator"
4295 [(cc0) (const_int 0)])
4296 (label_ref (match_operand 2 "" ""))
4298 "TARGET_H8300H || TARGET_H8300S"
4300 (and:HI (match_dup 0)
4303 (if_then_else (match_dup 3)
4304 (label_ref (match_dup 2))
4306 "switch (GET_CODE (operands[1]))
4309 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4312 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4315 operands[3] = operands[1];
4319 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4320 ;; the equivalent with shorter sequences. Here is the summary. Cases
4321 ;; are grouped for each define_peephole2.
4323 ;; reg const_int use insn
4324 ;; --------------------------------------------------------
4325 ;; live -2 eq/ne copy and inc.l
4326 ;; live -1 eq/ne copy and inc.l
4327 ;; live 1 eq/ne copy and dec.l
4328 ;; live 2 eq/ne copy and dec.l
4330 ;; dead -2 eq/ne inc.l
4331 ;; dead -1 eq/ne inc.l
4332 ;; dead 1 eq/ne dec.l
4333 ;; dead 2 eq/ne dec.l
4335 ;; dead -131072 eq/ne inc.w and test
4336 ;; dead -65536 eq/ne inc.w and test
4337 ;; dead 65536 eq/ne dec.w and test
4338 ;; dead 131072 eq/ne dec.w and test
4340 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4341 ;; dead 0x0000??00 eq/ne xor.b and test
4342 ;; dead 0x0000ffff eq/ne not.w and test
4344 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4345 ;; dead 0xffff??ff eq/ne xor.b and not.l
4346 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4347 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4349 ;; live 1 geu/ltu copy and shar.l
4350 ;; live 3 (H8S) geu/ltu copy and shar.l
4352 ;; dead 1 geu/ltu shar.l
4353 ;; dead 3 (H8S) geu/ltu shar.l
4355 ;; dead 3 (H8/300H) geu/ltu and.b and test
4356 ;; dead 7 geu/ltu and.b and test
4357 ;; dead 15 geu/ltu and.b and test
4358 ;; dead 31 geu/ltu and.b and test
4359 ;; dead 63 geu/ltu and.b and test
4360 ;; dead 127 geu/ltu and.b and test
4361 ;; dead 255 geu/ltu and.b and test
4363 ;; ---- 65535 geu/ltu mov.w
4365 ;; For a small constant, it is cheaper to actually do the subtraction
4366 ;; and then test the register.
4370 (compare (match_operand:SI 0 "register_operand" "")
4371 (match_operand:SI 1 "incdec_operand" "")))
4373 (if_then_else (match_operator 3 "eqne_operator"
4374 [(cc0) (const_int 0)])
4375 (label_ref (match_operand 2 "" ""))
4377 "(TARGET_H8300H || TARGET_H8300S)
4378 && peep2_reg_dead_p (1, operands[0])"
4380 (unspec:SI [(match_dup 0)
4386 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4387 (label_ref (match_dup 2))
4389 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4393 (compare (match_operand:SI 0 "register_operand" "")
4394 (match_operand:SI 1 "const_int_operand" "")))
4396 (if_then_else (match_operator 3 "eqne_operator"
4397 [(cc0) (const_int 0)])
4398 (label_ref (match_operand 2 "" ""))
4400 "(TARGET_H8300H || TARGET_H8300S)
4401 && peep2_reg_dead_p (1, operands[0])
4402 && (INTVAL (operands[1]) == -131072
4403 || INTVAL (operands[1]) == -65536
4404 || INTVAL (operands[1]) == 65536
4405 || INTVAL (operands[1]) == 131072)"
4407 (plus:SI (match_dup 0)
4412 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4413 (label_ref (match_dup 2))
4415 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4417 ;; For certain (in)equality comparisons against a constant, we can
4418 ;; XOR the register with the constant, and test the register against
4423 (compare (match_operand:SI 0 "register_operand" "")
4424 (match_operand:SI 1 "const_int_operand" "")))
4426 (if_then_else (match_operator 3 "eqne_operator"
4427 [(cc0) (const_int 0)])
4428 (label_ref (match_operand 2 "" ""))
4430 "(TARGET_H8300H || TARGET_H8300S)
4431 && peep2_reg_dead_p (1, operands[0])
4432 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4433 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4434 || INTVAL (operands[1]) == 0x0000ffff)
4435 && INTVAL (operands[1]) != 1
4436 && INTVAL (operands[1]) != 2"
4438 (xor:SI (match_dup 0)
4443 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4444 (label_ref (match_dup 2))
4450 (compare (match_operand:SI 0 "register_operand" "")
4451 (match_operand:SI 1 "const_int_operand" "")))
4453 (if_then_else (match_operator 3 "eqne_operator"
4454 [(cc0) (const_int 0)])
4455 (label_ref (match_operand 2 "" ""))
4457 "(TARGET_H8300H || TARGET_H8300S)
4458 && peep2_reg_dead_p (1, operands[0])
4459 && ((INTVAL (operands[1]) | 0x00ff) == -1
4460 || (INTVAL (operands[1]) | 0xff00) == -1)
4461 && INTVAL (operands[1]) != -1
4462 && INTVAL (operands[1]) != -2"
4464 (xor:SI (match_dup 0)
4467 (not:SI (match_dup 0)))
4471 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4472 (label_ref (match_dup 2))
4474 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4478 (compare (match_operand:SI 0 "register_operand" "")
4479 (match_operand:SI 1 "const_int_operand" "")))
4481 (if_then_else (match_operator 3 "eqne_operator"
4482 [(cc0) (const_int 0)])
4483 (label_ref (match_operand 2 "" ""))
4485 "(TARGET_H8300H || TARGET_H8300S)
4486 && peep2_reg_dead_p (1, operands[0])
4487 && (INTVAL (operands[1]) == -2147483647 - 1
4488 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4490 (rotate:SI (match_dup 0)
4493 (unspec:SI [(match_dup 0)
4499 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4500 (label_ref (match_dup 2))
4502 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4515 ;; We avoid this transformation if we see more than one copy of the
4516 ;; same compare insn immediately before this one.
4519 [(match_scratch:SI 4 "r")
4521 (compare (match_operand:SI 0 "register_operand" "")
4522 (match_operand:SI 1 "const_int_operand" "")))
4524 (if_then_else (match_operator 2 "gtle_operator"
4525 [(cc0) (const_int 0)])
4526 (label_ref (match_operand 3 "" ""))
4528 "(TARGET_H8300H || TARGET_H8300S)
4529 && !peep2_reg_dead_p (1, operands[0])
4530 && (INTVAL (operands[1]) == 1
4531 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4532 && !same_cmp_preceding_p (insn)"
4535 (parallel [(set (match_dup 4)
4536 (ashiftrt:SI (match_dup 4)
4538 (clobber (scratch:QI))])
4542 (if_then_else (match_dup 5)
4543 (label_ref (match_dup 3))
4545 "switch (GET_CODE (operands[2]))
4548 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4551 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4554 operands[5] = operands[2];
4557 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4571 (compare (match_operand:SI 0 "register_operand" "")
4572 (match_operand:SI 1 "const_int_operand" "")))
4574 (if_then_else (match_operator 2 "gtle_operator"
4575 [(cc0) (const_int 0)])
4576 (label_ref (match_operand 3 "" ""))
4578 "(TARGET_H8300H || TARGET_H8300S)
4579 && peep2_reg_dead_p (1, operands[0])
4580 && (INTVAL (operands[1]) == 1
4581 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4582 [(parallel [(set (match_dup 0)
4583 (ashiftrt:SI (match_dup 0)
4585 (clobber (scratch:QI))])
4589 (if_then_else (match_dup 4)
4590 (label_ref (match_dup 3))
4592 "switch (GET_CODE (operands[2]))
4595 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4598 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4601 operands[4] = operands[2];
4604 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4619 (compare (match_operand:SI 0 "register_operand" "")
4620 (match_operand:SI 1 "const_int_operand" "")))
4622 (if_then_else (match_operator 2 "gtle_operator"
4623 [(cc0) (const_int 0)])
4624 (label_ref (match_operand 3 "" ""))
4626 "(TARGET_H8300H || TARGET_H8300S)
4627 && peep2_reg_dead_p (1, operands[0])
4628 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4629 || INTVAL (operands[1]) == 7
4630 || INTVAL (operands[1]) == 15
4631 || INTVAL (operands[1]) == 31
4632 || INTVAL (operands[1]) == 63
4633 || INTVAL (operands[1]) == 127
4634 || INTVAL (operands[1]) == 255)"
4636 (and:SI (match_dup 0)
4641 (if_then_else (match_dup 4)
4642 (label_ref (match_dup 3))
4644 "switch (GET_CODE (operands[2]))
4647 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4650 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4653 operands[4] = operands[2];
4656 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4658 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4662 (compare (match_operand:SI 0 "register_operand" "")
4665 (if_then_else (match_operator 1 "gtle_operator"
4666 [(cc0) (const_int 0)])
4667 (label_ref (match_operand 2 "" ""))
4669 "TARGET_H8300H || TARGET_H8300S"
4671 (and:SI (match_dup 0)
4672 (const_int -65536)))
4674 (if_then_else (match_dup 3)
4675 (label_ref (match_dup 2))
4677 "switch (GET_CODE (operands[1]))
4680 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4683 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4686 operands[3] = operands[1];
4690 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4691 ;; of the register being tested, do the subtraction on the copy, and
4692 ;; then test the copy. We avoid this transformation if we see more
4693 ;; than one copy of the same compare insn.
4696 [(match_scratch:SI 4 "r")
4698 (compare (match_operand:SI 0 "register_operand" "")
4699 (match_operand:SI 1 "incdec_operand" "")))
4701 (if_then_else (match_operator 3 "eqne_operator"
4702 [(cc0) (const_int 0)])
4703 (label_ref (match_operand 2 "" ""))
4705 "(TARGET_H8300H || TARGET_H8300S)
4706 && !peep2_reg_dead_p (1, operands[0])
4707 && !same_cmp_following_p (insn)"
4711 (unspec:SI [(match_dup 4)
4717 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4718 (label_ref (match_dup 2))
4720 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4722 ;; Narrow the mode of testing if possible.
4725 [(set (match_operand:HI 0 "register_operand" "")
4726 (and:HI (match_dup 0)
4727 (match_operand:HI 1 "const_int_qi_operand" "")))
4731 (if_then_else (match_operator 3 "eqne_operator"
4732 [(cc0) (const_int 0)])
4733 (label_ref (match_operand 2 "" ""))
4735 "peep2_reg_dead_p (2, operands[0])"
4737 (and:QI (match_dup 4)
4742 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4743 (label_ref (match_dup 2))
4745 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4746 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4749 [(set (match_operand:SI 0 "register_operand" "")
4750 (and:SI (match_dup 0)
4751 (match_operand:SI 1 "const_int_qi_operand" "")))
4755 (if_then_else (match_operator 3 "eqne_operator"
4756 [(cc0) (const_int 0)])
4757 (label_ref (match_operand 2 "" ""))
4759 "peep2_reg_dead_p (2, operands[0])"
4761 (and:QI (match_dup 4)
4766 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4767 (label_ref (match_dup 2))
4769 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4770 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4773 [(set (match_operand:SI 0 "register_operand" "")
4774 (and:SI (match_dup 0)
4775 (match_operand:SI 1 "const_int_hi_operand" "")))
4779 (if_then_else (match_operator 3 "eqne_operator"
4780 [(cc0) (const_int 0)])
4781 (label_ref (match_operand 2 "" ""))
4783 "peep2_reg_dead_p (2, operands[0])"
4785 (and:HI (match_dup 4)
4790 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4791 (label_ref (match_dup 2))
4793 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4794 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4797 [(set (match_operand:SI 0 "register_operand" "")
4798 (and:SI (match_dup 0)
4799 (match_operand:SI 1 "const_int_qi_operand" "")))
4801 (xor:SI (match_dup 0)
4802 (match_operand:SI 2 "const_int_qi_operand" "")))
4806 (if_then_else (match_operator 4 "eqne_operator"
4807 [(cc0) (const_int 0)])
4808 (label_ref (match_operand 3 "" ""))
4810 "peep2_reg_dead_p (3, operands[0])
4811 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4813 (and:QI (match_dup 5)
4816 (xor:QI (match_dup 5)
4821 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4822 (label_ref (match_dup 3))
4824 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4825 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4826 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
4828 ;; These triggers right at the end of allocation of locals in the
4829 ;; prologue (and possibly at other places).
4831 ;; stack adjustment of -4, generate one push
4833 ;; before : 6 bytes, 10 clocks
4834 ;; after : 4 bytes, 10 clocks
4837 [(set (reg:SI SP_REG)
4838 (plus:SI (reg:SI SP_REG)
4840 (set (mem:SI (reg:SI SP_REG))
4841 (match_operand:SI 0 "register_operand" ""))]
4842 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4843 && REGNO (operands[0]) != SP_REG"
4844 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4848 ;; stack adjustment of -12, generate one push
4850 ;; before : 10 bytes, 14 clocks
4851 ;; after : 8 bytes, 14 clocks
4854 [(set (reg:SI SP_REG)
4855 (plus:SI (reg:SI SP_REG)
4857 (set (mem:SI (reg:SI SP_REG))
4858 (match_operand:SI 0 "register_operand" ""))]
4859 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4860 && REGNO (operands[0]) != SP_REG"
4861 [(set (reg:SI SP_REG)
4862 (plus:SI (reg:SI SP_REG)
4864 (set (reg:SI SP_REG)
4865 (plus:SI (reg:SI SP_REG)
4867 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))