1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; Condition code settings.
95 ;; none - insn does not affect cc
96 ;; none_0hit - insn does not affect cc but it does modify operand 0
97 ;; This attribute is used to keep track of when operand 0 changes.
98 ;; See the description of NOTICE_UPDATE_CC for more info.
99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
100 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
101 ;; compare - compare instruction
102 ;; clobber - value of cc is unknown
104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
105 (const_string "clobber"))
107 ;; Provide the maximum length of an assembly instruction in an asm
108 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
110 (define_asm_attributes
111 [(set (attr "length")
112 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
113 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
114 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
117 ;; ----------------------------------------------------------------------
119 ;; ----------------------------------------------------------------------
123 (define_insn "*movqi_h8300"
124 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
125 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
127 && (register_operand (operands[0], QImode)
128 || register_operand (operands[1], QImode))"
136 [(set_attr "length" "2,2,2,2,4,4")
137 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
139 (define_insn "*movqi_h8300hs"
140 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
141 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
142 "(TARGET_H8300H || TARGET_H8300S)
143 && (register_operand (operands[0], QImode)
144 || register_operand (operands[1], QImode))"
152 [(set (attr "length")
153 (symbol_ref "compute_mov_length (operands)"))
154 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
156 (define_expand "movqi"
157 [(set (match_operand:QI 0 "general_operand_dst" "")
158 (match_operand:QI 1 "general_operand_src" ""))]
162 /* One of the ops has to be in a register. */
163 if (!register_operand (operand0, QImode)
164 && !register_operand (operand1, QImode))
166 operands[1] = copy_to_mode_reg (QImode, operand1);
170 (define_insn "movstrictqi"
171 [(set (strict_low_part
172 (match_operand:QI 0 "register_operand" "+r,r,r,r,r"))
173 (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
181 [(set (attr "length")
182 (symbol_ref "compute_mov_length (operands)"))
183 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
187 (define_insn "*movhi_h8300"
188 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
189 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
191 && (register_operand (operands[0], HImode)
192 || register_operand (operands[1], HImode))
193 && !(GET_CODE (operands[0]) == MEM
194 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
195 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
196 && GET_CODE (operands[1]) == REG
197 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
205 [(set (attr "length")
206 (symbol_ref "compute_mov_length (operands)"))
207 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
209 (define_insn "*movhi_h8300hs"
210 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
211 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
212 "(TARGET_H8300H || TARGET_H8300S)
213 && (register_operand (operands[0], HImode)
214 || register_operand (operands[1], HImode))"
222 [(set (attr "length")
223 (symbol_ref "compute_mov_length (operands)"))
224 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
226 (define_expand "movhi"
227 [(set (match_operand:HI 0 "general_operand_dst" "")
228 (match_operand:HI 1 "general_operand_src" ""))]
232 /* One of the ops has to be in a register. */
233 if (!register_operand (operand1, HImode)
234 && !register_operand (operand0, HImode))
236 operands[1] = copy_to_mode_reg (HImode, operand1);
240 (define_insn "movstricthi"
241 [(set (strict_low_part
242 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
243 (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
251 [(set (attr "length")
252 (symbol_ref "compute_mov_length (operands)"))
253 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
257 (define_expand "movsi"
258 [(set (match_operand:SI 0 "general_operand_dst" "")
259 (match_operand:SI 1 "general_operand_src" ""))]
265 if (h8300_expand_movsi (operands))
270 /* One of the ops has to be in a register. */
271 if (!register_operand (operand1, SImode)
272 && !register_operand (operand0, SImode))
274 operands[1] = copy_to_mode_reg (SImode, operand1);
279 (define_insn "*movsi_h8300"
280 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
281 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
283 && (register_operand (operands[0], SImode)
284 || register_operand (operands[1], SImode))"
287 unsigned int rn = -1;
288 switch (which_alternative)
291 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
293 if (REGNO (operands[0]) < REGNO (operands[1]))
294 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
296 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
298 /* Make sure we don't trample the register we index with. */
299 if (GET_CODE (operands[1]) == MEM)
301 rtx inside = XEXP (operands[1], 0);
306 else if (GET_CODE (inside) == PLUS)
308 rtx lhs = XEXP (inside, 0);
309 rtx rhs = XEXP (inside, 1);
310 if (REG_P (lhs)) rn = REGNO (lhs);
311 if (REG_P (rhs)) rn = REGNO (rhs);
314 if (rn == REGNO (operands[0]))
316 /* Move the second word first. */
317 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
321 if (GET_CODE (operands[1]) == CONST_INT)
323 /* If either half is zero, use sub.w to clear that
325 if ((INTVAL (operands[1]) & 0xffff) == 0)
326 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
327 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
328 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
329 /* If the upper half and the lower half are the same,
330 copy one half to the other. */
331 if ((INTVAL (operands[1]) & 0xffff)
332 == ((INTVAL (operands[1]) >> 16) & 0xffff))
333 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
335 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
338 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
340 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
342 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
347 [(set (attr "length")
348 (symbol_ref "compute_mov_length (operands)"))])
350 (define_insn "*movsi_h8300hs"
351 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
352 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
353 "(TARGET_H8300S || TARGET_H8300H)
354 && (register_operand (operands[0], SImode)
355 || register_operand (operands[1], SImode))
356 && !(GET_CODE (operands[0]) == MEM
357 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
358 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
359 && GET_CODE (operands[1]) == REG
360 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
363 switch (which_alternative)
366 return \"sub.l %S0,%S0\";
370 return \"clrmac\;ldmac %1,macl\";
372 return \"stmac macl,%0\";
374 if (GET_CODE (operands[1]) == CONST_INT)
376 int val = INTVAL (operands[1]);
378 /* Look for constants which can be made by adding an 8-bit
379 number to zero in one of the two low bytes. */
380 if (val == (val & 0xff))
382 operands[1] = GEN_INT ((char) val & 0xff);
383 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
386 if (val == (val & 0xff00))
388 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
389 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
392 /* Look for constants that can be obtained by subs, inc, and
394 switch (val & 0xffffffff)
397 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
399 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
401 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
404 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
406 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
409 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
411 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
414 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
416 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
420 return \"mov.l %S1,%S0\";
422 [(set (attr "length")
423 (symbol_ref "compute_mov_length (operands)"))
424 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
426 (define_expand "movsf"
427 [(set (match_operand:SF 0 "general_operand_dst" "")
428 (match_operand:SF 1 "general_operand_src" ""))]
434 if (h8300_expand_movsi (operands))
439 /* One of the ops has to be in a register. */
440 if (!register_operand (operand1, SFmode)
441 && !register_operand (operand0, SFmode))
443 operands[1] = copy_to_mode_reg (SFmode, operand1);
448 (define_insn "*movsf_h8300"
449 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
450 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
452 && (register_operand (operands[0], SFmode)
453 || register_operand (operands[1], SFmode))"
456 /* Copy of the movsi stuff. */
457 unsigned int rn = -1;
458 switch (which_alternative)
461 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
463 if (REGNO (operands[0]) < REGNO (operands[1]))
464 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
466 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
468 /* Make sure we don't trample the register we index with. */
469 if (GET_CODE (operands[1]) == MEM)
471 rtx inside = XEXP (operands[1], 0);
476 else if (GET_CODE (inside) == PLUS)
478 rtx lhs = XEXP (inside, 0);
479 rtx rhs = XEXP (inside, 1);
480 if (REG_P (lhs)) rn = REGNO (lhs);
481 if (REG_P (rhs)) rn = REGNO (rhs);
484 if (rn == REGNO (operands[0]))
485 /* Move the second word first. */
486 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
488 /* Move the first word first. */
489 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
492 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
494 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
496 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
501 [(set (attr "length")
502 (symbol_ref "compute_mov_length (operands)"))])
504 (define_insn "*movsf_h8300hs"
505 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
506 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
507 "(TARGET_H8300H || TARGET_H8300S)
508 && (register_operand (operands[0], SFmode)
509 || register_operand (operands[1], SFmode))"
517 [(set (attr "length")
518 (symbol_ref "compute_mov_length (operands)"))
519 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
521 ;; ----------------------------------------------------------------------
523 ;; ----------------------------------------------------------------------
525 (define_insn "pushqi1_h8300"
526 [(set (reg:HI SP_REG)
527 (plus:HI (reg:HI SP_REG) (const_int -2)))
528 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
529 (match_operand:QI 0 "register_operand" "r"))]
531 && operands[0] != stack_pointer_rtx"
533 [(set_attr "length" "2")])
535 (define_insn "pushqi1_h8300hs"
536 [(set (reg:SI SP_REG)
537 (plus:SI (reg:SI SP_REG) (const_int -4)))
538 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
539 (match_operand:QI 0 "register_operand" "r"))]
540 "(TARGET_H8300H || TARGET_H8300S)
541 && operands[0] != stack_pointer_rtx"
543 [(set_attr "length" "4")])
545 (define_insn "pushqi1_h8300hs_normal"
546 [(set (reg:HI SP_REG)
547 (plus:HI (reg:HI SP_REG) (const_int -4)))
548 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
549 (match_operand:QI 0 "register_operand" "r"))]
550 "(TARGET_H8300H || TARGET_H8300S)
551 && operands[0] != stack_pointer_rtx"
553 [(set_attr "length" "4")])
555 (define_expand "pushqi1"
556 [(match_operand:QI 0 "register_operand" "")]
561 emit_insn (gen_pushqi1_h8300 (operands[0]));
562 else if (!TARGET_NORMAL_MODE)
563 emit_insn (gen_pushqi1_h8300hs (operands[0]));
565 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
569 (define_expand "pushhi1_h8300"
570 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
571 (match_operand:HI 0 "register_operand" ""))]
573 && operands[0] != stack_pointer_rtx"
576 (define_insn "pushhi1_h8300hs"
577 [(set (reg:SI SP_REG)
578 (plus:SI (reg:SI SP_REG) (const_int -4)))
579 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
580 (match_operand:HI 0 "register_operand" "r"))]
581 "(TARGET_H8300H || TARGET_H8300S)
582 && operands[0] != stack_pointer_rtx"
584 [(set_attr "length" "4")])
586 (define_insn "pushhi1_h8300hs_normal"
587 [(set (reg:HI SP_REG)
588 (plus:HI (reg:HI SP_REG) (const_int -4)))
589 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
590 (match_operand:HI 0 "register_operand" "r"))]
591 "(TARGET_H8300H || TARGET_H8300S)
592 && operands[0] != stack_pointer_rtx"
594 [(set_attr "length" "4")])
596 (define_expand "pushhi1"
597 [(match_operand:HI 0 "register_operand" "")]
602 emit_insn (gen_pushhi1_h8300 (operands[0]));
603 else if (!TARGET_NORMAL_MODE)
604 emit_insn (gen_pushhi1_h8300hs (operands[0]));
606 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
610 ;; ----------------------------------------------------------------------
612 ;; ----------------------------------------------------------------------
615 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
617 (match_operand 1 "const_int_operand" "n,n")))]
620 [(set_attr "length" "2,4")
621 (set_attr "cc" "set_zn,set_zn")])
624 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
626 (match_operand 1 "const_int_operand" "n")))]
629 [(set_attr "length" "2")
630 (set_attr "cc" "set_zn")])
632 (define_insn_and_split "*tst_extzv_1_n"
634 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
636 (match_operand 1 "const_int_operand" "n,n,n")))
637 (clobber (match_scratch:QI 2 "=X,X,&r"))]
638 "(TARGET_H8300H || TARGET_H8300S)"
644 && !EXTRA_CONSTRAINT (operands[0], 'U')"
647 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
650 (clobber (scratch:QI))])]
652 [(set_attr "length" "2,8,10")
653 (set_attr "cc" "set_zn,set_zn,set_zn")])
656 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
658 (match_operand 1 "const_int_operand" "n")))]
659 "(TARGET_H8300H || TARGET_H8300S)
660 && INTVAL (operands[1]) <= 15"
662 [(set_attr "length" "2")
663 (set_attr "cc" "set_zn")])
665 (define_insn_and_split "*tstsi_upper_bit"
667 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
669 (match_operand 1 "const_int_operand" "n")))
670 (clobber (match_scratch:SI 2 "=&r"))]
671 "(TARGET_H8300H || TARGET_H8300S)
672 && INTVAL (operands[1]) >= 16"
674 "&& reload_completed"
676 (ior:SI (and:SI (match_dup 2)
678 (lshiftrt:SI (match_dup 0)
681 (zero_extract:SI (match_dup 2)
684 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
686 (define_insn "*tstsi_variable_bit"
688 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
690 (and:SI (match_operand:SI 1 "register_operand" "r")
692 "TARGET_H8300H || TARGET_H8300S"
694 [(set_attr "length" "2")
695 (set_attr "cc" "set_zn")])
697 (define_insn_and_split "*tstsi_variable_bit_qi"
699 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
701 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
703 (clobber (match_scratch:QI 2 "=X,X,&r"))]
704 "(TARGET_H8300H || TARGET_H8300S)"
710 && !EXTRA_CONSTRAINT (operands[0], 'U')"
713 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
715 (and:SI (match_dup 1)
717 (clobber (scratch:QI))])]
719 [(set_attr "length" "2,8,10")
720 (set_attr "cc" "set_zn,set_zn,set_zn")])
723 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
726 [(set_attr "length" "2")
727 (set_attr "cc" "set_znv")])
730 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
733 [(set_attr "length" "2")
734 (set_attr "cc" "set_znv")])
736 (define_insn "*tsthi_upper"
738 (and:HI (match_operand:HI 0 "register_operand" "r")
742 [(set_attr "length" "2")
743 (set_attr "cc" "set_znv")])
746 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
747 "TARGET_H8300H || TARGET_H8300S"
749 [(set_attr "length" "2")
750 (set_attr "cc" "set_znv")])
752 (define_insn "*tstsi_upper"
754 (and:SI (match_operand:SI 0 "register_operand" "r")
755 (const_int -65536)))]
758 [(set_attr "length" "2")
759 (set_attr "cc" "set_znv")])
763 (compare (match_operand:QI 0 "register_operand" "r")
764 (match_operand:QI 1 "nonmemory_operand" "rn")))]
767 [(set_attr "length" "2")
768 (set_attr "cc" "compare")])
770 (define_expand "cmphi"
772 (compare (match_operand:HI 0 "register_operand" "")
773 (match_operand:HI 1 "nonmemory_operand" "")))]
777 /* Force operand1 into a register if we're compiling
779 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
780 operands[1] = force_reg (HImode, operands[1]);
783 (define_insn "*cmphi_h8300"
785 (compare (match_operand:HI 0 "register_operand" "r")
786 (match_operand:HI 1 "register_operand" "r")))]
789 [(set_attr "length" "2")
790 (set_attr "cc" "compare")])
792 (define_insn "*cmphi_h8300hs"
794 (compare (match_operand:HI 0 "register_operand" "r,r")
795 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
796 "TARGET_H8300H || TARGET_H8300S"
798 [(set_attr "length" "2,4")
799 (set_attr "cc" "compare,compare")])
803 (compare (match_operand:SI 0 "register_operand" "r,r")
804 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
805 "TARGET_H8300H || TARGET_H8300S"
807 [(set_attr "length" "2,6")
808 (set_attr "cc" "compare,compare")])
810 ;; ----------------------------------------------------------------------
812 ;; ----------------------------------------------------------------------
814 (define_insn "addqi3"
815 [(set (match_operand:QI 0 "register_operand" "=r")
816 (plus:QI (match_operand:QI 1 "register_operand" "%0")
817 (match_operand:QI 2 "nonmemory_operand" "rn")))]
820 [(set_attr "length" "2")
821 (set_attr "cc" "set_zn")])
823 (define_expand "addhi3"
824 [(set (match_operand:HI 0 "register_operand" "")
825 (plus:HI (match_operand:HI 1 "register_operand" "")
826 (match_operand:HI 2 "nonmemory_operand" "")))]
830 (define_insn "*addhi3_h8300"
831 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
832 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
833 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
839 add.b %s2,%s0\;addx %t2,%t0
841 [(set_attr "length" "2,2,2,4,2")
842 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
844 ;; This splitter is very important to make the stack adjustment
845 ;; interrupt-safe. The combination of add.b and addx is unsafe!
847 ;; We apply this split after the peephole2 pass so that we won't end
848 ;; up creating too many adds/subs when a scratch register is
849 ;; available, which is actually a common case because stack unrolling
850 ;; tends to happen immediately after a function call.
853 [(set (match_operand:HI 0 "stack_pointer_operand" "")
854 (plus:HI (match_dup 0)
855 (match_operand 1 "const_int_gt_2_operand" "")))]
856 "TARGET_H8300 && flow2_completed"
858 "split_adds_subs (HImode, operands); DONE;")
861 [(match_scratch:HI 2 "r")
862 (set (match_operand:HI 0 "stack_pointer_operand" "")
863 (plus:HI (match_dup 0)
864 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
869 (plus:HI (match_dup 0)
873 (define_insn "*addhi3_h8300hs"
874 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
875 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
876 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
877 "TARGET_H8300H || TARGET_H8300S"
884 [(set_attr "length" "2,2,2,4,2")
885 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
887 (define_insn "*addhi3_incdec"
888 [(set (match_operand:HI 0 "register_operand" "=r,r")
889 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
890 (match_operand:HI 2 "incdec_operand" "M,O")]
892 "TARGET_H8300H || TARGET_H8300S"
896 [(set_attr "length" "2,2")
897 (set_attr "cc" "set_zn,set_zn")])
900 [(set (match_operand:HI 0 "register_operand" "")
901 (plus:HI (match_dup 0)
902 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
905 "split_adds_subs (HImode, operands); DONE;")
907 (define_expand "addsi3"
908 [(set (match_operand:SI 0 "register_operand" "")
909 (plus:SI (match_operand:SI 1 "register_operand" "")
910 (match_operand:SI 2 "nonmemory_operand" "")))]
914 (define_insn "*addsi_h8300"
915 [(set (match_operand:SI 0 "register_operand" "=r,r")
916 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
917 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
919 "* return output_plussi (operands);"
920 [(set (attr "length")
921 (symbol_ref "compute_plussi_length (operands)"))
923 (symbol_ref "compute_plussi_cc (operands)"))])
925 (define_insn "*addsi_h8300hs"
926 [(set (match_operand:SI 0 "register_operand" "=r,r")
927 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
928 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
929 "TARGET_H8300H || TARGET_H8300S"
930 "* return output_plussi (operands);"
931 [(set (attr "length")
932 (symbol_ref "compute_plussi_length (operands)"))
934 (symbol_ref "compute_plussi_cc (operands)"))])
936 (define_insn "*addsi3_incdec"
937 [(set (match_operand:SI 0 "register_operand" "=r,r")
938 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
939 (match_operand:SI 2 "incdec_operand" "M,O")]
941 "TARGET_H8300H || TARGET_H8300S"
945 [(set_attr "length" "2,2")
946 (set_attr "cc" "set_zn,set_zn")])
949 [(set (match_operand:SI 0 "register_operand" "")
950 (plus:SI (match_dup 0)
951 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
952 "TARGET_H8300H || TARGET_H8300S"
954 "split_adds_subs (SImode, operands); DONE;")
956 ;; ----------------------------------------------------------------------
957 ;; SUBTRACT INSTRUCTIONS
958 ;; ----------------------------------------------------------------------
960 (define_insn "subqi3"
961 [(set (match_operand:QI 0 "register_operand" "=r")
962 (minus:QI (match_operand:QI 1 "register_operand" "0")
963 (match_operand:QI 2 "register_operand" "r")))]
966 [(set_attr "length" "2")
967 (set_attr "cc" "set_zn")])
969 (define_expand "subhi3"
970 [(set (match_operand:HI 0 "register_operand" "")
971 (minus:HI (match_operand:HI 1 "general_operand" "")
972 (match_operand:HI 2 "nonmemory_operand" "")))]
976 (define_insn "*subhi3_h8300"
977 [(set (match_operand:HI 0 "register_operand" "=r,r")
978 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
979 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
983 add.b %E2,%s0\;addx %F2,%t0"
984 [(set_attr "length" "2,4")
985 (set_attr "cc" "set_zn,clobber")])
987 (define_insn "*subhi3_h8300hs"
988 [(set (match_operand:HI 0 "register_operand" "=r,r")
989 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
990 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
991 "TARGET_H8300H || TARGET_H8300S"
995 [(set_attr "length" "2,4")
996 (set_attr "cc" "set_zn,set_zn")])
998 (define_expand "subsi3"
999 [(set (match_operand:SI 0 "register_operand" "")
1000 (minus:SI (match_operand:SI 1 "register_operand" "")
1001 (match_operand:SI 2 "nonmemory_operand" "")))]
1005 (define_insn "*subsi3_h8300"
1006 [(set (match_operand:SI 0 "register_operand" "=r")
1007 (minus:SI (match_operand:SI 1 "register_operand" "0")
1008 (match_operand:SI 2 "register_operand" "r")))]
1010 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1011 [(set_attr "length" "6")])
1013 (define_insn "*subsi3_h8300hs"
1014 [(set (match_operand:SI 0 "register_operand" "=r,r")
1015 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1016 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1017 "TARGET_H8300H || TARGET_H8300S"
1021 [(set_attr "length" "2,6")
1022 (set_attr "cc" "set_zn,set_zn")])
1024 ;; ----------------------------------------------------------------------
1025 ;; MULTIPLY INSTRUCTIONS
1026 ;; ----------------------------------------------------------------------
1028 ;; Note that the H8/300 can only handle umulqihi3.
1030 (define_insn "mulqihi3"
1031 [(set (match_operand:HI 0 "register_operand" "=r")
1032 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1033 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1034 "TARGET_H8300H || TARGET_H8300S"
1036 [(set_attr "length" "4")
1037 (set_attr "cc" "set_zn")])
1039 (define_insn "mulhisi3"
1040 [(set (match_operand:SI 0 "register_operand" "=r")
1041 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1042 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1043 "TARGET_H8300H || TARGET_H8300S"
1045 [(set_attr "length" "4")
1046 (set_attr "cc" "set_zn")])
1048 (define_insn "umulqihi3"
1049 [(set (match_operand:HI 0 "register_operand" "=r")
1050 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1051 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1054 [(set_attr "length" "2")
1055 (set_attr "cc" "none_0hit")])
1057 (define_insn "umulhisi3"
1058 [(set (match_operand:SI 0 "register_operand" "=r")
1059 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1060 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1061 "TARGET_H8300H || TARGET_H8300S"
1063 [(set_attr "length" "2")
1064 (set_attr "cc" "none_0hit")])
1066 ;; This is a "bridge" instruction. Combine can't cram enough insns
1067 ;; together to crate a MAC instruction directly, but it can create
1068 ;; this instruction, which then allows combine to create the real
1071 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1072 ;; insn must generate reasonably correct code. Egad.
1074 [(set (match_operand:SI 0 "register_operand" "=a")
1077 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1079 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1081 "clrmac\;mac @%2+,@%1+"
1082 [(set_attr "length" "6")
1083 (set_attr "cc" "none_0hit")])
1086 [(set (match_operand:SI 0 "register_operand" "=a")
1088 (sign_extend:SI (mem:HI
1089 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1090 (sign_extend:SI (mem:HI
1091 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1092 (match_operand:SI 3 "register_operand" "0")))]
1095 [(set_attr "length" "4")
1096 (set_attr "cc" "none_0hit")])
1098 ;; ----------------------------------------------------------------------
1099 ;; DIVIDE/MOD INSTRUCTIONS
1100 ;; ----------------------------------------------------------------------
1102 (define_insn "udivmodqi4"
1103 [(set (match_operand:QI 0 "register_operand" "=r")
1106 (match_operand:HI 1 "register_operand" "0")
1107 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1108 (set (match_operand:QI 3 "register_operand" "=r")
1112 (zero_extend:HI (match_dup 2)))))]
1116 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1117 return \"divxu.b\\t%X2,%T0\";
1119 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1121 [(set_attr "length" "4")])
1123 (define_insn "divmodqi4"
1124 [(set (match_operand:QI 0 "register_operand" "=r")
1127 (match_operand:HI 1 "register_operand" "0")
1128 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1129 (set (match_operand:QI 3 "register_operand" "=r")
1133 (sign_extend:HI (match_dup 2)))))]
1134 "TARGET_H8300H || TARGET_H8300S"
1137 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1138 return \"divxs.b\\t%X2,%T0\";
1140 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1142 [(set_attr "length" "6")])
1144 (define_insn "udivmodhi4"
1145 [(set (match_operand:HI 0 "register_operand" "=r")
1148 (match_operand:SI 1 "register_operand" "0")
1149 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1150 (set (match_operand:HI 3 "register_operand" "=r")
1154 (zero_extend:SI (match_dup 2)))))]
1155 "TARGET_H8300H || TARGET_H8300S"
1158 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1159 return \"divxu.w\\t%T2,%S0\";
1161 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1163 [(set_attr "length" "4")])
1165 (define_insn "divmodhi4"
1166 [(set (match_operand:HI 0 "register_operand" "=r")
1169 (match_operand:SI 1 "register_operand" "0")
1170 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1171 (set (match_operand:HI 3 "register_operand" "=r")
1175 (sign_extend:SI (match_dup 2)))))]
1176 "TARGET_H8300H || TARGET_H8300S"
1179 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1180 return \"divxs.w\\t%T2,%S0\";
1182 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1184 [(set_attr "length" "6")])
1186 ;; ----------------------------------------------------------------------
1188 ;; ----------------------------------------------------------------------
1190 (define_insn "andqi3_1"
1191 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1192 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1193 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1194 "register_operand (operands[0], QImode)
1195 || single_zero_operand (operands[2], QImode)"
1199 [(set_attr "length" "2,8")
1200 (set_attr "cc" "set_znv,none_0hit")])
1202 (define_expand "andqi3"
1203 [(set (match_operand:QI 0 "bit_operand" "")
1204 (and:QI (match_operand:QI 1 "bit_operand" "")
1205 (match_operand:QI 2 "nonmemory_operand" "")))]
1209 if (fix_bit_operand (operands, AND))
1213 (define_expand "andhi3"
1214 [(set (match_operand:HI 0 "register_operand" "")
1215 (and:HI (match_operand:HI 1 "register_operand" "")
1216 (match_operand:HI 2 "nonmemory_operand" "")))]
1220 (define_insn "*andorqi3"
1221 [(set (match_operand:QI 0 "register_operand" "=r")
1222 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1223 (match_operand:QI 3 "single_one_operand" "n"))
1224 (match_operand:QI 1 "register_operand" "0")))]
1226 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1227 [(set_attr "length" "6")])
1229 (define_insn "*andorhi3"
1230 [(set (match_operand:HI 0 "register_operand" "=r")
1231 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1232 (match_operand:HI 3 "single_one_operand" "n"))
1233 (match_operand:HI 1 "register_operand" "0")))]
1237 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1238 if (INTVAL (operands[3]) > 128)
1240 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1241 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1243 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1245 [(set_attr "length" "6")])
1247 (define_insn "*andorsi3"
1248 [(set (match_operand:SI 0 "register_operand" "=r")
1249 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1250 (match_operand:SI 3 "single_one_operand" "n"))
1251 (match_operand:SI 1 "register_operand" "0")))]
1252 "(INTVAL (operands[3]) & 0xffff) != 0"
1255 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1256 if (INTVAL (operands[3]) > 128)
1258 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1259 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1261 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1263 [(set_attr "length" "6")])
1265 (define_insn "*andorsi3_shift_8"
1266 [(set (match_operand:SI 0 "register_operand" "=r")
1267 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1270 (match_operand:SI 1 "register_operand" "0")))]
1273 [(set_attr "length" "2")])
1275 (define_expand "andsi3"
1276 [(set (match_operand:SI 0 "register_operand" "")
1277 (and:SI (match_operand:SI 1 "register_operand" "")
1278 (match_operand:SI 2 "nonmemory_operand" "")))]
1282 ;; ----------------------------------------------------------------------
1284 ;; ----------------------------------------------------------------------
1286 (define_insn "iorqi3_1"
1287 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1288 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1289 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1290 "register_operand (operands[0], QImode)
1291 || single_one_operand (operands[2], QImode)"
1295 [(set_attr "length" "2,8")
1296 (set_attr "cc" "set_znv,none_0hit")])
1298 (define_expand "iorqi3"
1299 [(set (match_operand:QI 0 "bit_operand" "")
1300 (ior:QI (match_operand:QI 1 "bit_operand" "")
1301 (match_operand:QI 2 "nonmemory_operand" "")))]
1305 if (fix_bit_operand (operands, IOR))
1309 (define_expand "iorhi3"
1310 [(set (match_operand:HI 0 "register_operand" "")
1311 (ior:HI (match_operand:HI 1 "register_operand" "")
1312 (match_operand:HI 2 "nonmemory_operand" "")))]
1316 (define_expand "iorsi3"
1317 [(set (match_operand:SI 0 "register_operand" "")
1318 (ior:SI (match_operand:SI 1 "register_operand" "")
1319 (match_operand:SI 2 "nonmemory_operand" "")))]
1323 ;; ----------------------------------------------------------------------
1325 ;; ----------------------------------------------------------------------
1327 (define_insn "xorqi3_1"
1328 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1329 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1330 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1331 "register_operand (operands[0], QImode)
1332 || single_one_operand (operands[2], QImode)"
1336 [(set_attr "length" "2,8")
1337 (set_attr "cc" "set_znv,none_0hit")])
1339 (define_expand "xorqi3"
1340 [(set (match_operand:QI 0 "bit_operand" "")
1341 (xor:QI (match_operand:QI 1 "bit_operand" "")
1342 (match_operand:QI 2 "nonmemory_operand" "")))]
1346 if (fix_bit_operand (operands, XOR))
1350 (define_expand "xorhi3"
1351 [(set (match_operand:HI 0 "register_operand" "")
1352 (xor:HI (match_operand:HI 1 "register_operand" "")
1353 (match_operand:HI 2 "nonmemory_operand" "")))]
1357 (define_expand "xorsi3"
1358 [(set (match_operand:SI 0 "register_operand" "")
1359 (xor:SI (match_operand:SI 1 "register_operand" "")
1360 (match_operand:SI 2 "nonmemory_operand" "")))]
1364 ;; ----------------------------------------------------------------------
1365 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1366 ;; ----------------------------------------------------------------------
1368 (define_insn "*logicalhi3"
1369 [(set (match_operand:HI 0 "register_operand" "=r")
1370 (match_operator:HI 3 "bit_operator"
1371 [(match_operand:HI 1 "register_operand" "%0")
1372 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1374 "* return output_logical_op (HImode, operands);"
1375 [(set (attr "length")
1376 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1378 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1380 (define_insn "*logicalsi3"
1381 [(set (match_operand:SI 0 "register_operand" "=r")
1382 (match_operator:SI 3 "bit_operator"
1383 [(match_operand:SI 1 "register_operand" "%0")
1384 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1386 "* return output_logical_op (SImode, operands);"
1387 [(set (attr "length")
1388 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1390 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1392 ;; ----------------------------------------------------------------------
1393 ;; NEGATION INSTRUCTIONS
1394 ;; ----------------------------------------------------------------------
1396 (define_insn "negqi2"
1397 [(set (match_operand:QI 0 "register_operand" "=r")
1398 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1401 [(set_attr "length" "2")
1402 (set_attr "cc" "set_zn")])
1404 (define_expand "neghi2"
1405 [(set (match_operand:HI 0 "register_operand" "")
1406 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1412 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1417 (define_expand "neghi2_h8300"
1419 (not:HI (match_operand:HI 1 "register_operand" "")))
1420 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1421 (set (match_operand:HI 0 "register_operand" "")
1424 "operands[2] = gen_reg_rtx (HImode);")
1426 (define_insn "*neghi2_h8300hs"
1427 [(set (match_operand:HI 0 "register_operand" "=r")
1428 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1429 "TARGET_H8300H || TARGET_H8300S"
1431 [(set_attr "length" "2")
1432 (set_attr "cc" "set_zn")])
1434 (define_expand "negsi2"
1435 [(set (match_operand:SI 0 "register_operand" "")
1436 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1442 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1447 (define_expand "negsi2_h8300"
1449 (not:SI (match_operand:SI 1 "register_operand" "")))
1450 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1451 (set (match_operand:SI 0 "register_operand" "")
1454 "operands[2] = gen_reg_rtx (SImode);")
1456 (define_insn "*negsi2_h8300hs"
1457 [(set (match_operand:SI 0 "register_operand" "=r")
1458 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1459 "TARGET_H8300H || TARGET_H8300S"
1461 [(set_attr "length" "2")
1462 (set_attr "cc" "set_zn")])
1464 (define_expand "negsf2"
1465 [(set (match_operand:SF 0 "register_operand" "")
1466 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1470 (define_insn "*negsf2_h8300"
1471 [(set (match_operand:SF 0 "register_operand" "=r")
1472 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1475 [(set_attr "length" "2")])
1477 (define_insn "*negsf2_h8300hs"
1478 [(set (match_operand:SF 0 "register_operand" "=r")
1479 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1480 "TARGET_H8300H || TARGET_H8300S"
1481 "xor.w\\t#32768,%e0"
1482 [(set_attr "length" "4")])
1484 ;; ----------------------------------------------------------------------
1485 ;; ABSOLUTE VALUE INSTRUCTIONS
1486 ;; ----------------------------------------------------------------------
1488 (define_expand "abssf2"
1489 [(set (match_operand:SF 0 "register_operand" "")
1490 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1494 (define_insn "*abssf2_h8300"
1495 [(set (match_operand:SF 0 "register_operand" "=r")
1496 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1499 [(set_attr "length" "2")])
1501 (define_insn "*abssf2_h8300hs"
1502 [(set (match_operand:SF 0 "register_operand" "=r")
1503 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1504 "TARGET_H8300H || TARGET_H8300S"
1505 "and.w\\t#32767,%e0"
1506 [(set_attr "length" "4")])
1508 ;; ----------------------------------------------------------------------
1510 ;; ----------------------------------------------------------------------
1512 (define_insn "one_cmplqi2"
1513 [(set (match_operand:QI 0 "register_operand" "=r")
1514 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1517 [(set_attr "length" "2")
1518 (set_attr "cc" "set_znv")])
1520 (define_expand "one_cmplhi2"
1521 [(set (match_operand:HI 0 "register_operand" "=r")
1522 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1526 (define_insn "*one_cmplhi2_h8300"
1527 [(set (match_operand:HI 0 "register_operand" "=r")
1528 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1531 [(set_attr "length" "4")])
1533 (define_insn "*one_cmplhi2_h8300hs"
1534 [(set (match_operand:HI 0 "register_operand" "=r")
1535 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1536 "TARGET_H8300H || TARGET_H8300S"
1538 [(set_attr "cc" "set_znv")
1539 (set_attr "length" "2")])
1541 (define_expand "one_cmplsi2"
1542 [(set (match_operand:SI 0 "register_operand" "=r")
1543 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1547 (define_insn "*one_cmplsi2_h8300"
1548 [(set (match_operand:SI 0 "register_operand" "=r")
1549 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1551 "not %w0\;not %x0\;not %y0\;not %z0"
1552 [(set_attr "length" "8")])
1554 (define_insn "*one_cmplsi2_h8300hs"
1555 [(set (match_operand:SI 0 "register_operand" "=r")
1556 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1557 "TARGET_H8300H || TARGET_H8300S"
1559 [(set_attr "cc" "set_znv")
1560 (set_attr "length" "2")])
1562 ;; ----------------------------------------------------------------------
1563 ;; JUMP INSTRUCTIONS
1564 ;; ----------------------------------------------------------------------
1566 ;; Conditional jump instructions
1568 (define_expand "ble"
1569 [(match_operand 0 "" "")]
1571 "h8300_expand_branch (LE, operands[0]); DONE;")
1573 (define_expand "bleu"
1574 [(match_operand 0 "" "")]
1576 "h8300_expand_branch (LEU, operands[0]); DONE;")
1578 (define_expand "bge"
1579 [(match_operand 0 "" "")]
1581 "h8300_expand_branch (GE, operands[0]); DONE;")
1583 (define_expand "bgeu"
1584 [(match_operand 0 "" "")]
1586 "h8300_expand_branch (GEU, operands[0]); DONE;")
1588 (define_expand "blt"
1589 [(match_operand 0 "" "")]
1591 "h8300_expand_branch (LT, operands[0]); DONE;")
1593 (define_expand "bltu"
1594 [(match_operand 0 "" "")]
1596 "h8300_expand_branch (LTU, operands[0]); DONE;")
1598 (define_expand "bgt"
1599 [(match_operand 0 "" "")]
1601 "h8300_expand_branch (GT, operands[0]); DONE;")
1603 (define_expand "bgtu"
1604 [(match_operand 0 "" "")]
1606 "h8300_expand_branch (GTU, operands[0]); DONE;")
1608 (define_expand "beq"
1609 [(match_operand 0 "" "")]
1611 "h8300_expand_branch (EQ, operands[0]); DONE;")
1613 (define_expand "bne"
1614 [(match_operand 0 "" "")]
1616 "h8300_expand_branch (NE, operands[0]); DONE;")
1618 (define_insn "branch_true"
1620 (if_then_else (match_operator 1 "comparison_operator"
1621 [(cc0) (const_int 0)])
1622 (label_ref (match_operand 0 "" ""))
1627 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1628 && (GET_CODE (operands[1]) == GT
1629 || GET_CODE (operands[1]) == GE
1630 || GET_CODE (operands[1]) == LE
1631 || GET_CODE (operands[1]) == LT))
1633 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1637 if (get_attr_length (insn) == 2)
1638 return \"b%j1 %l0\";
1639 else if (get_attr_length (insn) == 4)
1640 return \"b%j1 %l0:16\";
1642 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1644 [(set_attr "type" "branch")
1645 (set_attr "cc" "none")])
1647 (define_insn "branch_false"
1649 (if_then_else (match_operator 1 "comparison_operator"
1650 [(cc0) (const_int 0)])
1652 (label_ref (match_operand 0 "" ""))))]
1656 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1657 && (GET_CODE (operands[1]) == GT
1658 || GET_CODE (operands[1]) == GE
1659 || GET_CODE (operands[1]) == LE
1660 || GET_CODE (operands[1]) == LT))
1662 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1666 if (get_attr_length (insn) == 2)
1667 return \"b%k1 %l0\";
1668 else if (get_attr_length (insn) == 4)
1669 return \"b%k1 %l0:16\";
1671 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1673 [(set_attr "type" "branch")
1674 (set_attr "cc" "none")])
1676 ;; Unconditional and other jump instructions.
1680 (label_ref (match_operand 0 "" "")))]
1684 if (get_attr_length (insn) == 2)
1686 else if (get_attr_length (insn) == 4)
1687 return \"bra %l0:16\";
1689 return \"jmp @%l0\";
1691 [(set_attr "type" "branch")
1692 (set_attr "cc" "none")])
1694 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1696 (define_expand "tablejump"
1697 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1698 (use (label_ref (match_operand 1 "" "")))])]
1702 (define_insn "*tablejump_h8300"
1703 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1704 (use (label_ref (match_operand 1 "" "")))]
1707 [(set_attr "cc" "none")
1708 (set_attr "length" "2")])
1710 (define_insn "*tablejump_h8300hs_advanced"
1711 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1712 (use (label_ref (match_operand 1 "" "")))]
1713 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1715 [(set_attr "cc" "none")
1716 (set_attr "length" "2")])
1718 (define_insn "*tablejump_h8300hs_normal"
1719 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1720 (use (label_ref (match_operand 1 "" "")))]
1721 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1723 [(set_attr "cc" "none")
1724 (set_attr "length" "2")])
1726 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1728 (define_expand "indirect_jump"
1729 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1733 (define_insn "*indirect_jump_h8300"
1734 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1737 [(set_attr "cc" "none")
1738 (set_attr "length" "2")])
1740 (define_insn "*indirect_jump_h8300hs_advanced"
1741 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1742 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1744 [(set_attr "cc" "none")
1745 (set_attr "length" "2")])
1747 (define_insn "*indirect_jump_h8300hs_normal"
1748 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1749 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1751 [(set_attr "cc" "none")
1752 (set_attr "length" "2")])
1754 ;; Call subroutine with no return value.
1756 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1759 [(call (match_operand:QI 0 "call_insn_operand" "or")
1760 (match_operand:HI 1 "general_operand" "g"))]
1764 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1765 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1766 return \"jsr\\t@%0:8\";
1768 return \"jsr\\t%0\";
1770 [(set (attr "length")
1771 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1775 ;; Call subroutine, returning value in operand 0
1776 ;; (which must be a hard register).
1778 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1780 (define_insn "call_value"
1781 [(set (match_operand 0 "" "=r")
1782 (call (match_operand:QI 1 "call_insn_operand" "or")
1783 (match_operand:HI 2 "general_operand" "g")))]
1787 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1788 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1789 return \"jsr\\t@%1:8\";
1791 return \"jsr\\t%1\";
1793 [(set (attr "length")
1794 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1802 [(set_attr "cc" "none")
1803 (set_attr "length" "2")])
1805 ;; ----------------------------------------------------------------------
1806 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1807 ;; ----------------------------------------------------------------------
1809 (define_expand "push_h8300"
1810 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1811 (match_operand:HI 0 "register_operand" ""))]
1815 (define_expand "push_h8300hs_advanced"
1816 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1817 (match_operand:SI 0 "register_operand" ""))]
1818 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1821 (define_expand "push_h8300hs_normal"
1822 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1823 (match_operand:SI 0 "register_operand" ""))]
1824 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1827 (define_expand "pop_h8300"
1828 [(set (match_operand:HI 0 "register_operand" "")
1829 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1833 (define_expand "pop_h8300hs_advanced"
1834 [(set (match_operand:SI 0 "register_operand" "")
1835 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1836 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1839 (define_expand "pop_h8300hs_normal"
1840 [(set (match_operand:SI 0 "register_operand" "")
1841 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1842 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1845 (define_insn "stm_h8300s_2_advanced"
1846 [(set (reg:SI SP_REG)
1847 (plus:SI (reg:SI SP_REG) (const_int -8)))
1848 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1849 (match_operand:SI 0 "register_operand" ""))
1850 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1851 (match_operand:SI 1 "register_operand" ""))]
1852 "TARGET_H8300S && !TARGET_NORMAL_MODE
1853 && h8300_regs_ok_for_stm (2, operands)"
1854 "stm.l\\t%S0-%S1,@-er7"
1855 [(set_attr "cc" "none")
1856 (set_attr "length" "4")])
1858 (define_insn "stm_h8300s_2_normal"
1859 [(set (reg:HI SP_REG)
1860 (plus:HI (reg:HI SP_REG) (const_int -8)))
1861 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1862 (match_operand:SI 0 "register_operand" ""))
1863 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1864 (match_operand:SI 1 "register_operand" ""))]
1865 "TARGET_H8300S && TARGET_NORMAL_MODE
1866 && h8300_regs_ok_for_stm (2, operands)"
1867 "stm.l\\t%S0-%S1,@-er7"
1868 [(set_attr "cc" "none")
1869 (set_attr "length" "4")])
1871 (define_expand "stm_h8300s_2"
1872 [(match_operand:SI 0 "register_operand" "")
1873 (match_operand:SI 1 "register_operand" "")]
1875 && h8300_regs_ok_for_stm (2, operands)"
1878 if (!TARGET_NORMAL_MODE)
1879 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1881 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1885 (define_insn "stm_h8300s_3_advanced"
1886 [(set (reg:SI SP_REG)
1887 (plus:SI (reg:SI SP_REG) (const_int -12)))
1888 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1889 (match_operand:SI 0 "register_operand" ""))
1890 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1891 (match_operand:SI 1 "register_operand" ""))
1892 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1893 (match_operand:SI 2 "register_operand" ""))]
1894 "TARGET_H8300S && !TARGET_NORMAL_MODE
1895 && h8300_regs_ok_for_stm (3, operands)"
1896 "stm.l\\t%S0-%S2,@-er7"
1897 [(set_attr "cc" "none")
1898 (set_attr "length" "4")])
1900 (define_insn "stm_h8300s_3_normal"
1901 [(set (reg:HI SP_REG)
1902 (plus:HI (reg:HI SP_REG) (const_int -12)))
1903 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1904 (match_operand:SI 0 "register_operand" ""))
1905 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1906 (match_operand:SI 1 "register_operand" ""))
1907 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1908 (match_operand:SI 2 "register_operand" ""))]
1909 "TARGET_H8300S && TARGET_NORMAL_MODE
1910 && h8300_regs_ok_for_stm (3, operands)"
1911 "stm.l\\t%S0-%S2,@-er7"
1912 [(set_attr "cc" "none")
1913 (set_attr "length" "4")])
1915 (define_expand "stm_h8300s_3"
1916 [(match_operand:SI 0 "register_operand" "")
1917 (match_operand:SI 1 "register_operand" "")
1918 (match_operand:SI 2 "register_operand" "")]
1920 && h8300_regs_ok_for_stm (3, operands)"
1923 if (!TARGET_NORMAL_MODE)
1924 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
1927 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
1932 (define_insn "stm_h8300s_4_advanced"
1933 [(set (reg:SI SP_REG)
1934 (plus:SI (reg:SI SP_REG) (const_int -16)))
1935 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1936 (match_operand:SI 0 "register_operand" ""))
1937 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1938 (match_operand:SI 1 "register_operand" ""))
1939 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1940 (match_operand:SI 2 "register_operand" ""))
1941 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1942 (match_operand:SI 3 "register_operand" ""))]
1943 "TARGET_H8300S && !TARGET_NORMAL_MODE
1944 && h8300_regs_ok_for_stm (4, operands)"
1945 "stm.l\\t%S0-%S3,@-er7"
1946 [(set_attr "cc" "none")
1947 (set_attr "length" "4")])
1949 (define_insn "stm_h8300s_4_normal"
1950 [(set (reg:HI SP_REG)
1951 (plus:HI (reg:HI SP_REG) (const_int -16)))
1952 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1953 (match_operand:SI 0 "register_operand" ""))
1954 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1955 (match_operand:SI 1 "register_operand" ""))
1956 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1957 (match_operand:SI 2 "register_operand" ""))
1958 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
1959 (match_operand:SI 3 "register_operand" ""))]
1960 "TARGET_H8300S && TARGET_NORMAL_MODE
1961 && h8300_regs_ok_for_stm (4, operands)"
1962 "stm.l\\t%S0-%S3,@-er7"
1963 [(set_attr "cc" "none")
1964 (set_attr "length" "4")])
1966 (define_expand "stm_h8300s_4"
1967 [(match_operand:SI 0 "register_operand" "")
1968 (match_operand:SI 1 "register_operand" "")
1969 (match_operand:SI 2 "register_operand" "")
1970 (match_operand:SI 3 "register_operand" "")]
1972 && h8300_regs_ok_for_stm (4, operands)"
1975 if (!TARGET_NORMAL_MODE)
1976 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
1977 operands[2], operands[3]));
1979 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
1980 operands[2], operands[3]));
1984 (define_insn "ldm_h8300s_2_advanced"
1985 [(set (reg:SI SP_REG)
1986 (plus:SI (reg:SI SP_REG) (const_int 8)))
1987 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1988 (match_operand:SI 0 "register_operand" ""))
1989 (set (mem:SI (reg:SI SP_REG))
1990 (match_operand:SI 1 "register_operand" ""))]
1991 "TARGET_H8300S && !TARGET_NORMAL_MODE
1992 && h8300_regs_ok_for_stm (2, operands)"
1993 "ldm.l\\t@er7+,%S0-%S1"
1994 [(set_attr "cc" "none")
1995 (set_attr "length" "4")])
1997 (define_insn "ldm_h8300s_2_normal"
1998 [(set (reg:HI SP_REG)
1999 (plus:HI (reg:HI SP_REG) (const_int 8)))
2000 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2001 (match_operand:SI 0 "register_operand" ""))
2002 (set (mem:SI (reg:HI SP_REG))
2003 (match_operand:SI 1 "register_operand" ""))]
2004 "TARGET_H8300S && TARGET_NORMAL_MODE
2005 && h8300_regs_ok_for_stm (2, operands)"
2006 "ldm.l\\t@er7+,%S0-%S1"
2007 [(set_attr "cc" "none")
2008 (set_attr "length" "4")])
2010 (define_expand "ldm_h8300s_2"
2011 [(match_operand:SI 0 "register_operand" "")
2012 (match_operand:SI 1 "register_operand" "")]
2014 && h8300_regs_ok_for_stm (2, operands)"
2017 if (!TARGET_NORMAL_MODE)
2018 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2020 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2024 (define_insn "ldm_h8300s_3_advanced"
2025 [(set (reg:SI SP_REG)
2026 (plus:SI (reg:SI SP_REG) (const_int 12)))
2027 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2028 (match_operand:SI 0 "register_operand" ""))
2029 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2030 (match_operand:SI 1 "register_operand" ""))
2031 (set (mem:SI (reg:SI SP_REG))
2032 (match_operand:SI 2 "register_operand" ""))]
2033 "TARGET_H8300S && !TARGET_NORMAL_MODE
2034 && h8300_regs_ok_for_stm (3, operands)"
2035 "ldm.l\\t@er7+,%S0-%S2"
2036 [(set_attr "cc" "none")
2037 (set_attr "length" "4")])
2039 (define_insn "ldm_h8300s_3_normal"
2040 [(set (reg:HI SP_REG)
2041 (plus:HI (reg:HI SP_REG) (const_int 12)))
2042 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2043 (match_operand:SI 0 "register_operand" ""))
2044 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2045 (match_operand:SI 1 "register_operand" ""))
2046 (set (mem:SI (reg:HI SP_REG))
2047 (match_operand:SI 2 "register_operand" ""))]
2048 "TARGET_H8300S && TARGET_NORMAL_MODE
2049 && h8300_regs_ok_for_stm (3, operands)"
2050 "ldm.l\\t@er7+,%S0-%S2"
2051 [(set_attr "cc" "none")
2052 (set_attr "length" "4")])
2054 (define_expand "ldm_h8300s_3"
2055 [(match_operand:SI 0 "register_operand" "")
2056 (match_operand:SI 1 "register_operand" "")
2057 (match_operand:SI 2 "register_operand" "")]
2059 && h8300_regs_ok_for_stm (3, operands)"
2062 if (!TARGET_NORMAL_MODE)
2063 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2066 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2071 (define_insn "ldm_h8300s_4_advanced"
2072 [(set (reg:SI SP_REG)
2073 (plus:SI (reg:SI SP_REG) (const_int 16)))
2074 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2075 (match_operand:SI 0 "register_operand" ""))
2076 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2077 (match_operand:SI 1 "register_operand" ""))
2078 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2079 (match_operand:SI 2 "register_operand" ""))
2080 (set (mem:SI (reg:SI SP_REG))
2081 (match_operand:SI 3 "register_operand" ""))]
2082 "TARGET_H8300S && !TARGET_NORMAL_MODE
2083 && h8300_regs_ok_for_stm (4, operands)"
2084 "ldm.l\\t@er7+,%S0-%S3"
2085 [(set_attr "cc" "none")
2086 (set_attr "length" "4")])
2088 (define_insn "ldm_h8300s_4_normal"
2089 [(set (reg:HI SP_REG)
2090 (plus:HI (reg:HI SP_REG) (const_int 16)))
2091 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2092 (match_operand:SI 0 "register_operand" ""))
2093 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2094 (match_operand:SI 1 "register_operand" ""))
2095 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2096 (match_operand:SI 2 "register_operand" ""))
2097 (set (mem:SI (reg:HI SP_REG))
2098 (match_operand:SI 3 "register_operand" ""))]
2099 "TARGET_H8300S && !TARGET_NORMAL_MODE
2100 && h8300_regs_ok_for_stm (4, operands)"
2101 "ldm.l\\t@er7+,%S0-%S3"
2102 [(set_attr "cc" "none")
2103 (set_attr "length" "4")])
2105 (define_expand "ldm_h8300s_4"
2106 [(match_operand:SI 0 "register_operand" "")
2107 (match_operand:SI 1 "register_operand" "")
2108 (match_operand:SI 2 "register_operand" "")
2109 (match_operand:SI 3 "register_operand" "")]
2110 "TARGET_H8300S && !TARGET_NORMAL_MODE
2111 && h8300_regs_ok_for_stm (4, operands)"
2114 if (!TARGET_NORMAL_MODE)
2115 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2116 operands[2], operands[3]));
2118 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2119 operands[2], operands[3]));
2123 (define_expand "return"
2125 "h8300_can_use_return_insn_p ()"
2128 (define_insn "*return_1"
2133 if (h8300_current_function_interrupt_function_p ())
2138 [(set_attr "cc" "none")
2139 (set_attr "length" "2")])
2141 (define_expand "prologue"
2144 "h8300_expand_prologue (); DONE;")
2146 (define_expand "epilogue"
2149 "h8300_expand_epilogue ();")
2151 (define_insn "monitor_prologue"
2152 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2157 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2158 else if (TARGET_H8300H)
2159 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2160 else if (TARGET_H8300S)
2161 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2164 [(set_attr "length" "20")])
2166 ;; ----------------------------------------------------------------------
2167 ;; EXTEND INSTRUCTIONS
2168 ;; ----------------------------------------------------------------------
2170 (define_expand "zero_extendqihi2"
2171 [(set (match_operand:HI 0 "register_operand" "")
2172 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2176 (define_insn "*zero_extendqihi2_h8300"
2177 [(set (match_operand:HI 0 "register_operand" "=r,r")
2178 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2183 [(set_attr "length" "2,10")])
2185 (define_insn "*zero_extendqihi2_h8300hs"
2186 [(set (match_operand:HI 0 "register_operand" "=r,r")
2187 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2188 "TARGET_H8300H || TARGET_H8300S"
2192 [(set_attr "length" "2,10")
2193 (set_attr "cc" "set_znv,set_znv")])
2195 ;; Split the zero extension of a general operand (actually a memory
2196 ;; operand) into a load of the operand and the actual zero extension
2197 ;; so that 1) the length will be accurate, and 2) the zero extensions
2198 ;; appearing at the end of basic blocks may be merged.
2201 [(set (match_operand:HI 0 "register_operand" "")
2202 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2207 (zero_extend:HI (match_dup 2)))]
2208 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2210 (define_expand "zero_extendqisi2"
2211 [(set (match_operand:SI 0 "register_operand" "")
2212 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2216 (define_insn "*zero_extendqisi2_h8300"
2217 [(set (match_operand:SI 0 "register_operand" "=r,r")
2218 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2221 mov.b #0,%x0\;sub.w %e0,%e0
2222 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2223 [(set_attr "length" "4,8")])
2225 (define_insn "*zero_extendqisi2_h8300hs"
2226 [(set (match_operand:SI 0 "register_operand" "=r,r")
2227 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2228 "TARGET_H8300H || TARGET_H8300S"
2232 [(set (match_operand:SI 0 "register_operand" "")
2233 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2234 "(TARGET_H8300H || TARGET_H8300S)
2235 && reg_overlap_mentioned_p (operands[0], operands[1])
2236 && reload_completed"
2240 (zero_extend:HI (match_dup 2)))
2242 (zero_extend:SI (match_dup 3)))]
2243 "operands[2] = gen_lowpart (QImode, operands[0]);
2244 operands[3] = gen_lowpart (HImode, operands[0]);")
2247 [(set (match_operand:SI 0 "register_operand" "")
2248 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2249 "(TARGET_H8300H || TARGET_H8300S)
2250 && !reg_overlap_mentioned_p (operands[0], operands[1])
2251 && reload_completed"
2254 (set (strict_low_part (match_dup 2))
2256 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2258 (define_expand "zero_extendhisi2"
2259 [(set (match_operand:SI 0 "register_operand" "")
2260 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2264 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2265 (define_insn "*zero_extendhisi2_h8300"
2266 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2267 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2271 mov.w %f1,%f0\;sub.w %e0,%e0
2272 mov.w %e1,%f0\;sub.w %e0,%e0"
2273 [(set_attr "length" "2,4,6")])
2275 (define_insn "*zero_extendhisi2_h8300hs"
2276 [(set (match_operand:SI 0 "register_operand" "=r")
2277 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2278 "TARGET_H8300H || TARGET_H8300S"
2280 [(set_attr "length" "2")
2281 (set_attr "cc" "set_znv")])
2283 (define_expand "extendqihi2"
2284 [(set (match_operand:HI 0 "register_operand" "")
2285 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2289 (define_insn "*extendqihi2_h8300"
2290 [(set (match_operand:HI 0 "register_operand" "=r,r")
2291 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2294 bld #7,%s0\;subx %t0,%t0
2295 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2296 [(set_attr "length" "4,8")])
2298 (define_insn "*extendqihi2_h8300hs"
2299 [(set (match_operand:HI 0 "register_operand" "=r")
2300 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2301 "TARGET_H8300H || TARGET_H8300S"
2303 [(set_attr "length" "2")
2304 (set_attr "cc" "set_znv")])
2306 (define_expand "extendqisi2"
2307 [(set (match_operand:SI 0 "register_operand" "")
2308 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2312 (define_insn "*extendqisi2_h8300"
2313 [(set (match_operand:SI 0 "register_operand" "")
2314 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2317 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2318 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2319 [(set_attr "length" "8,12")])
2321 ;; The following pattern is needed because without the pattern, the
2322 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2323 ;; shifts, one ashift and one ashiftrt.
2325 (define_insn_and_split "*extendqisi2_h8300hs"
2326 [(set (match_operand:SI 0 "register_operand" "=r")
2327 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2328 "(TARGET_H8300H || TARGET_H8300S)"
2330 "&& reload_completed"
2332 (sign_extend:HI (match_dup 1)))
2334 (sign_extend:SI (match_dup 2)))]
2335 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2337 (define_expand "extendhisi2"
2338 [(set (match_operand:SI 0 "register_operand" "")
2339 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2343 (define_insn "*extendhisi2_h8300"
2344 [(set (match_operand:SI 0 "register_operand" "=r,r")
2345 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2348 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2349 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2350 [(set_attr "length" "6,10")])
2352 (define_insn "*extendhisi2_h8300hs"
2353 [(set (match_operand:SI 0 "register_operand" "=r")
2354 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2355 "TARGET_H8300H || TARGET_H8300S"
2357 [(set_attr "length" "2")
2358 (set_attr "cc" "set_znv")])
2360 ;; ----------------------------------------------------------------------
2362 ;; ----------------------------------------------------------------------
2364 ;; We make some attempt to provide real efficient shifting. One example is
2365 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2366 ;; reg and moving 0 into the former reg.
2368 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2369 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2370 ;; give the optimizer more cracks at the code. However, we wish to do things
2371 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2372 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2373 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2374 ;; to detect cases it can optimize.
2376 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2377 ;; easier "do it at insn emit time" route.
2381 (define_expand "ashlqi3"
2382 [(set (match_operand:QI 0 "register_operand" "")
2383 (ashift:QI (match_operand:QI 1 "register_operand" "")
2384 (match_operand:QI 2 "nonmemory_operand" "")))]
2386 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2388 (define_expand "ashrqi3"
2389 [(set (match_operand:QI 0 "register_operand" "")
2390 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2391 (match_operand:QI 2 "nonmemory_operand" "")))]
2393 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2395 (define_expand "lshrqi3"
2396 [(set (match_operand:QI 0 "register_operand" "")
2397 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2398 (match_operand:QI 2 "nonmemory_operand" "")))]
2400 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2402 (define_insn "*shiftqi"
2403 [(set (match_operand:QI 0 "register_operand" "=r,r")
2404 (match_operator:QI 3 "nshift_operator"
2405 [ (match_operand:QI 1 "register_operand" "0,0")
2406 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2407 (clobber (match_scratch:QI 4 "=X,&r"))]
2409 "* return output_a_shift (operands);"
2410 [(set (attr "length")
2411 (symbol_ref "compute_a_shift_length (insn, operands)"))
2413 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2417 (define_expand "ashlhi3"
2418 [(set (match_operand:HI 0 "register_operand" "")
2419 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2420 (match_operand:QI 2 "nonmemory_operand" "")))]
2422 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2424 (define_expand "lshrhi3"
2425 [(set (match_operand:HI 0 "register_operand" "")
2426 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2427 (match_operand:QI 2 "nonmemory_operand" "")))]
2429 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2431 (define_expand "ashrhi3"
2432 [(set (match_operand:HI 0 "register_operand" "")
2433 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2434 (match_operand:QI 2 "nonmemory_operand" "")))]
2436 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2438 (define_insn "*shifthi"
2439 [(set (match_operand:HI 0 "register_operand" "=r,r")
2440 (match_operator:HI 3 "nshift_operator"
2441 [ (match_operand:HI 1 "register_operand" "0,0")
2442 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2443 (clobber (match_scratch:QI 4 "=X,&r"))]
2445 "* return output_a_shift (operands);"
2446 [(set (attr "length")
2447 (symbol_ref "compute_a_shift_length (insn, operands)"))
2449 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2453 (define_expand "ashlsi3"
2454 [(set (match_operand:SI 0 "register_operand" "")
2455 (ashift:SI (match_operand:SI 1 "general_operand" "")
2456 (match_operand:QI 2 "nonmemory_operand" "")))]
2458 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2460 (define_expand "lshrsi3"
2461 [(set (match_operand:SI 0 "register_operand" "")
2462 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2463 (match_operand:QI 2 "nonmemory_operand" "")))]
2465 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2467 (define_expand "ashrsi3"
2468 [(set (match_operand:SI 0 "register_operand" "")
2469 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2470 (match_operand:QI 2 "nonmemory_operand" "")))]
2472 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2474 (define_insn "*shiftsi"
2475 [(set (match_operand:SI 0 "register_operand" "=r,r")
2476 (match_operator:SI 3 "nshift_operator"
2477 [ (match_operand:SI 1 "register_operand" "0,0")
2478 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2479 (clobber (match_scratch:QI 4 "=X,&r"))]
2481 "* return output_a_shift (operands);"
2482 [(set (attr "length")
2483 (symbol_ref "compute_a_shift_length (insn, operands)"))
2485 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2487 ;; Split a variable shift into a loop. If the register containing
2488 ;; the shift count dies, then we just use that register.
2491 [(set (match_operand 0 "register_operand" "")
2492 (match_operator 2 "nshift_operator"
2494 (match_operand:QI 1 "register_operand" "")]))
2495 (clobber (match_operand:QI 3 "register_operand" ""))]
2497 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2501 (if_then_else (le (cc0) (const_int 0))
2502 (label_ref (match_dup 5))
2507 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2508 (clobber (scratch:QI))])
2510 (plus:QI (match_dup 1) (const_int -1)))
2514 (if_then_else (ne (cc0) (const_int 0))
2515 (label_ref (match_dup 4))
2518 "operands[4] = gen_label_rtx ();
2519 operands[5] = gen_label_rtx ();")
2522 [(set (match_operand 0 "register_operand" "")
2523 (match_operator 2 "nshift_operator"
2525 (match_operand:QI 1 "register_operand" "")]))
2526 (clobber (match_operand:QI 3 "register_operand" ""))]
2528 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2534 (if_then_else (le (cc0) (const_int 0))
2535 (label_ref (match_dup 5))
2540 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2541 (clobber (scratch:QI))])
2543 (plus:QI (match_dup 3) (const_int -1)))
2547 (if_then_else (ne (cc0) (const_int 0))
2548 (label_ref (match_dup 4))
2551 "operands[4] = gen_label_rtx ();
2552 operands[5] = gen_label_rtx ();")
2554 ;; ----------------------------------------------------------------------
2556 ;; ----------------------------------------------------------------------
2558 (define_expand "rotlqi3"
2559 [(set (match_operand:QI 0 "register_operand" "")
2560 (rotate:QI (match_operand:QI 1 "register_operand" "")
2561 (match_operand:QI 2 "nonmemory_operand" "")))]
2563 "if (expand_a_rotate (operands)) DONE; else FAIL;")
2565 (define_insn "rotlqi3_1"
2566 [(set (match_operand:QI 0 "register_operand" "=r")
2567 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2568 (match_operand:QI 2 "immediate_operand" "")))]
2570 "* return output_a_rotate (ROTATE, operands);"
2571 [(set (attr "length")
2572 (symbol_ref "compute_a_rotate_length (operands)"))])
2574 (define_expand "rotlhi3"
2575 [(set (match_operand:HI 0 "register_operand" "")
2576 (rotate:HI (match_operand:HI 1 "register_operand" "")
2577 (match_operand:QI 2 "nonmemory_operand" "")))]
2579 "if (expand_a_rotate (operands)) DONE; else FAIL;")
2581 (define_insn "rotlhi3_1"
2582 [(set (match_operand:HI 0 "register_operand" "=r")
2583 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2584 (match_operand:QI 2 "immediate_operand" "")))]
2586 "* return output_a_rotate (ROTATE, operands);"
2587 [(set (attr "length")
2588 (symbol_ref "compute_a_rotate_length (operands)"))])
2590 (define_expand "rotlsi3"
2591 [(set (match_operand:SI 0 "register_operand" "")
2592 (rotate:SI (match_operand:SI 1 "register_operand" "")
2593 (match_operand:QI 2 "nonmemory_operand" "")))]
2594 "TARGET_H8300H || TARGET_H8300S"
2595 "if (expand_a_rotate (operands)) DONE; else FAIL;")
2597 (define_insn "rotlsi3_1"
2598 [(set (match_operand:SI 0 "register_operand" "=r")
2599 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2600 (match_operand:QI 2 "immediate_operand" "")))]
2601 "TARGET_H8300H || TARGET_H8300S"
2602 "* return output_a_rotate (ROTATE, operands);"
2603 [(set (attr "length")
2604 (symbol_ref "compute_a_rotate_length (operands)"))])
2606 ;; -----------------------------------------------------------------
2608 ;; -----------------------------------------------------------------
2609 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2610 ;; instructions so let's use them as well as we can.
2612 ;; You'll never believe all these patterns perform one basic action --
2613 ;; load a bit from the source, optionally invert the bit, then store it
2614 ;; in the destination (which is known to be zero).
2616 ;; Combine obviously need some work to better identify this situation and
2617 ;; canonicalize the form better.
2620 ;; Normal loads with a 16bit destination.
2624 [(set (match_operand:HI 0 "register_operand" "=&r")
2625 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2627 (match_operand:HI 2 "immediate_operand" "n")))]
2629 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2630 [(set_attr "length" "6")])
2633 ;; Inverted loads with a 16bit destination.
2637 [(set (match_operand:HI 0 "register_operand" "=&r")
2638 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2639 (match_operand:HI 3 "const_int_operand" "n"))
2641 (match_operand:HI 2 "const_int_operand" "n")))]
2643 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2644 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2645 [(set_attr "length" "8")])
2648 ;; Normal loads with a 32bit destination.
2651 (define_insn "*extzv_1_r_h8300"
2652 [(set (match_operand:SI 0 "register_operand" "=&r")
2653 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2655 (match_operand 2 "const_int_operand" "n")))]
2657 && INTVAL (operands[2]) < 16"
2658 "* return output_simode_bld (0, operands);"
2659 [(set_attr "length" "8")])
2661 (define_insn "*extzv_1_r_h8300hs"
2662 [(set (match_operand:SI 0 "register_operand" "=r,r")
2663 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2665 (match_operand 2 "const_int_operand" "n,n")))]
2666 "(TARGET_H8300H || TARGET_H8300S)
2667 && INTVAL (operands[2]) < 16"
2668 "* return output_simode_bld (0, operands);"
2669 [(set_attr "cc" "set_znv,set_znv")
2670 (set_attr "length" "8,6")])
2673 ;; Inverted loads with a 32bit destination.
2676 (define_insn "*extzv_1_r_inv_h8300"
2677 [(set (match_operand:SI 0 "register_operand" "=&r")
2678 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2679 (match_operand:HI 3 "const_int_operand" "n"))
2681 (match_operand 2 "const_int_operand" "n")))]
2683 && INTVAL (operands[2]) < 16
2684 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2685 "* return output_simode_bld (1, operands);"
2686 [(set_attr "length" "8")])
2688 (define_insn "*extzv_1_r_inv_h8300hs"
2689 [(set (match_operand:SI 0 "register_operand" "=r,r")
2690 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2691 (match_operand 3 "const_int_operand" "n,n"))
2693 (match_operand 2 "const_int_operand" "n,n")))]
2694 "(TARGET_H8300H || TARGET_H8300S)
2695 && INTVAL (operands[2]) < 16
2696 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2697 "* return output_simode_bld (1, operands);"
2698 [(set_attr "cc" "set_znv,set_znv")
2699 (set_attr "length" "8,6")])
2701 (define_expand "insv"
2702 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2703 (match_operand:HI 1 "general_operand" "")
2704 (match_operand:HI 2 "general_operand" ""))
2705 (match_operand:HI 3 "general_operand" ""))]
2709 /* We only have single bit bit-field instructions. */
2710 if (INTVAL (operands[1]) != 1)
2713 /* For now, we don't allow memory operands. */
2714 if (GET_CODE (operands[0]) == MEM
2715 || GET_CODE (operands[3]) == MEM)
2720 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2722 (match_operand:HI 1 "immediate_operand" "n"))
2723 (match_operand:HI 2 "register_operand" "r"))]
2725 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2726 [(set_attr "length" "4")])
2728 (define_expand "extzv"
2729 [(set (match_operand:HI 0 "register_operand" "")
2730 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2731 (match_operand:HI 2 "general_operand" "")
2732 (match_operand:HI 3 "general_operand" "")))]
2736 /* We only have single bit bit-field instructions. */
2737 if (INTVAL (operands[2]) != 1)
2740 /* For now, we don't allow memory operands. */
2741 if (GET_CODE (operands[1]) == MEM)
2745 ;; BAND, BOR, and BXOR patterns
2748 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2749 (match_operator:HI 4 "bit_operator"
2750 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2752 (match_operand:HI 2 "immediate_operand" "n"))
2753 (match_operand:HI 3 "bit_operand" "0")]))]
2755 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2756 [(set_attr "length" "6")])
2759 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2760 (match_operator:HI 5 "bit_operator"
2761 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2763 (match_operand:HI 2 "immediate_operand" "n"))
2764 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2766 (match_operand:HI 4 "immediate_operand" "n"))]))]
2768 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2769 [(set_attr "length" "6")])
2771 ;; -----------------------------------------------------------------
2773 ;; -----------------------------------------------------------------
2777 (define_insn "*insv_si_1_n"
2778 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2780 (match_operand:SI 1 "const_int_operand" "n"))
2781 (match_operand:SI 2 "register_operand" "r"))]
2782 "(TARGET_H8300H || TARGET_H8300S)
2783 && INTVAL (operands[1]) < 16"
2784 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2785 [(set_attr "length" "4")])
2787 (define_insn "*insv_si_1_n_lshiftrt"
2788 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2790 (match_operand:SI 1 "const_int_operand" "n"))
2791 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2792 (match_operand:SI 3 "const_int_operand" "n")))]
2793 "(TARGET_H8300H || TARGET_H8300S)
2794 && INTVAL (operands[1]) < 16
2795 && INTVAL (operands[3]) < 16"
2796 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2797 [(set_attr "length" "4")])
2799 (define_insn "*insv_si_1_n_lshiftrt_16"
2800 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2802 (match_operand:SI 1 "const_int_operand" "n"))
2803 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2805 "(TARGET_H8300H || TARGET_H8300S)
2806 && INTVAL (operands[1]) < 16"
2807 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2808 [(set_attr "length" "6")])
2810 (define_insn "*insv_si_8_8"
2811 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2814 (match_operand:SI 1 "register_operand" "r"))]
2815 "TARGET_H8300H || TARGET_H8300S"
2817 [(set_attr "length" "2")])
2819 (define_insn "*insv_si_8_8_lshiftrt_8"
2820 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2823 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2825 "TARGET_H8300H || TARGET_H8300S"
2827 [(set_attr "length" "2")])
2831 (define_insn "*extzv_8_8"
2832 [(set (match_operand:SI 0 "register_operand" "=r,r")
2833 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2836 "TARGET_H8300H || TARGET_H8300S"
2838 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2839 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2840 [(set_attr "cc" "set_znv,clobber")
2841 (set_attr "length" "6,4")])
2843 (define_insn "*extzv_8_16"
2844 [(set (match_operand:SI 0 "register_operand" "=r")
2845 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2848 "TARGET_H8300H || TARGET_H8300S"
2849 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2850 [(set_attr "cc" "set_znv")
2851 (set_attr "length" "6")])
2853 (define_insn "*extzv_16_8"
2854 [(set (match_operand:SI 0 "register_operand" "=r")
2855 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2858 (clobber (match_scratch:SI 2 "=&r"))]
2860 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2861 [(set_attr "length" "8")
2862 (set_attr "cc" "set_znv")])
2864 ;; Extract the exponent of a float.
2866 (define_insn_and_split "*extzv_8_23"
2867 [(set (match_operand:SI 0 "register_operand" "=r")
2868 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2871 "(TARGET_H8300H || TARGET_H8300S)"
2873 "&& reload_completed"
2874 [(parallel [(set (match_dup 0)
2875 (ashift:SI (match_dup 0)
2877 (clobber (scratch:QI))])
2878 (parallel [(set (match_dup 0)
2879 (lshiftrt:SI (match_dup 0)
2881 (clobber (scratch:QI))])]
2886 ;; ((SImode) HImode) << 15
2888 (define_insn_and_split "*twoshifts_l16_r1"
2889 [(set (match_operand:SI 0 "register_operand" "=r")
2890 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2892 (const_int 2147450880)))]
2893 "(TARGET_H8300H || TARGET_H8300S)"
2895 "&& reload_completed"
2896 [(parallel [(set (match_dup 0)
2897 (ashift:SI (match_dup 0)
2899 (clobber (scratch:QI))])
2900 (parallel [(set (match_dup 0)
2901 (lshiftrt:SI (match_dup 0)
2903 (clobber (scratch:QI))])]
2906 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2908 (define_insn_and_split "*andsi3_ashift_n_lower"
2909 [(set (match_operand:SI 0 "register_operand" "=r,r")
2910 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2911 (match_operand:QI 2 "const_int_operand" "S,n"))
2912 (match_operand:SI 3 "const_int_operand" "n,n")))
2913 (clobber (match_scratch:QI 4 "=X,&r"))]
2914 "(TARGET_H8300H || TARGET_H8300S)
2915 && INTVAL (operands[2]) <= 15
2916 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2918 "&& reload_completed"
2919 [(parallel [(set (match_dup 5)
2920 (ashift:HI (match_dup 5)
2922 (clobber (match_dup 4))])
2924 (zero_extend:SI (match_dup 5)))]
2925 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2927 ;; Accept (A >> 30) & 2 and the like.
2929 (define_insn "*andsi3_lshiftrt_n_sb"
2930 [(set (match_operand:SI 0 "register_operand" "=r")
2931 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2932 (match_operand:SI 2 "const_int_operand" "n"))
2933 (match_operand:SI 3 "single_one_operand" "n")))]
2934 "(TARGET_H8300H || TARGET_H8300S)
2935 && exact_log2 (INTVAL (operands[3])) < 16
2936 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2939 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2940 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2942 [(set_attr "length" "8")])
2944 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2945 [(set (match_operand:SI 0 "register_operand" "=r")
2946 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2948 (const_int 4194304)))]
2949 "(TARGET_H8300H || TARGET_H8300S)"
2951 "&& reload_completed"
2953 (and:SI (lshiftrt:SI (match_dup 0)
2956 (parallel [(set (match_dup 0)
2957 (ashift:SI (match_dup 0)
2959 (clobber (scratch:QI))])]
2964 (define_insn "*addsi3_upper"
2965 [(set (match_operand:SI 0 "register_operand" "=r")
2966 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
2968 (match_operand:SI 2 "register_operand" "0")))]
2969 "TARGET_H8300H || TARGET_H8300S"
2971 [(set_attr "length" "2")])
2973 (define_insn "*addsi3_lshiftrt_16_zexthi"
2974 [(set (match_operand:SI 0 "register_operand" "=r")
2975 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2977 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2978 "TARGET_H8300H || TARGET_H8300S"
2979 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
2980 [(set_attr "length" "6")])
2982 (define_insn_and_split "*addsi3_and_r_1"
2983 [(set (match_operand:SI 0 "register_operand" "=r")
2984 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
2986 (match_operand:SI 2 "register_operand" "0")))]
2987 "(TARGET_H8300H || TARGET_H8300S)"
2989 "&& reload_completed"
2991 (zero_extract:SI (match_dup 1)
2995 (if_then_else (eq (cc0)
2997 (label_ref (match_dup 3))
3000 (plus:SI (match_dup 2)
3003 "operands[3] = gen_label_rtx ();")
3005 (define_insn_and_split "*addsi3_and_not_r_1"
3006 [(set (match_operand:SI 0 "register_operand" "=r")
3007 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3009 (match_operand:SI 2 "register_operand" "0")))]
3010 "(TARGET_H8300H || TARGET_H8300S)"
3012 "&& reload_completed"
3014 (zero_extract:SI (match_dup 1)
3018 (if_then_else (ne (cc0)
3020 (label_ref (match_dup 3))
3023 (plus:SI (match_dup 2)
3026 "operands[3] = gen_label_rtx ();")
3030 (define_insn "*ixorhi3_zext"
3031 [(set (match_operand:HI 0 "register_operand" "=r")
3032 (match_operator:HI 1 "iorxor_operator"
3033 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3034 (match_operand:HI 3 "register_operand" "0")]))]
3037 [(set_attr "length" "2")])
3041 (define_insn "*ixorsi3_zext_qi"
3042 [(set (match_operand:SI 0 "register_operand" "=r")
3043 (match_operator:SI 1 "iorxor_operator"
3044 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3045 (match_operand:SI 3 "register_operand" "0")]))]
3048 [(set_attr "length" "2")])
3050 (define_insn "*ixorsi3_zext_hi"
3051 [(set (match_operand:SI 0 "register_operand" "=r")
3052 (match_operator:SI 1 "iorxor_operator"
3053 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3054 (match_operand:SI 3 "register_operand" "0")]))]
3055 "TARGET_H8300H || TARGET_H8300S"
3057 [(set_attr "length" "2")])
3059 (define_insn "*ixorsi3_ashift_16"
3060 [(set (match_operand:SI 0 "register_operand" "=r")
3061 (match_operator:SI 1 "iorxor_operator"
3062 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3064 (match_operand:SI 3 "register_operand" "0")]))]
3065 "TARGET_H8300H || TARGET_H8300S"
3067 [(set_attr "length" "2")])
3069 (define_insn "*ixorsi3_lshiftrt_16"
3070 [(set (match_operand:SI 0 "register_operand" "=r")
3071 (match_operator:SI 1 "iorxor_operator"
3072 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3074 (match_operand:SI 3 "register_operand" "0")]))]
3075 "TARGET_H8300H || TARGET_H8300S"
3077 [(set_attr "length" "2")])
3081 (define_insn "*iorhi3_ashift_8"
3082 [(set (match_operand:HI 0 "register_operand" "=r")
3083 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3085 (match_operand:HI 2 "register_operand" "0")))]
3088 [(set_attr "length" "2")])
3090 (define_insn "*iorhi3_lshiftrt_8"
3091 [(set (match_operand:HI 0 "register_operand" "=r")
3092 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3094 (match_operand:HI 2 "register_operand" "0")))]
3097 [(set_attr "length" "2")])
3099 (define_insn "*iorhi3_two_qi"
3100 [(set (match_operand:HI 0 "register_operand" "=r")
3101 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3102 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3106 [(set_attr "length" "2")])
3108 (define_insn "*iorhi3_two_qi_mem"
3109 [(set (match_operand:HI 0 "register_operand" "=&r")
3110 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3111 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3114 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3115 [(set_attr "length" "16")])
3118 [(set (match_operand:HI 0 "register_operand" "")
3119 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3120 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3122 "(TARGET_H8300H || TARGET_H8300S)
3124 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3127 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3131 (define_insn "*iorsi3_two_hi"
3132 [(set (match_operand:SI 0 "register_operand" "=r")
3133 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3134 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3136 "TARGET_H8300H || TARGET_H8300S"
3138 [(set_attr "length" "2")])
3140 (define_insn_and_split "*iorsi3_two_qi_zext"
3141 [(set (match_operand:SI 0 "register_operand" "=&r")
3142 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3144 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3146 (const_int 65280))))]
3147 "(TARGET_H8300H || TARGET_H8300S)"
3149 "&& reload_completed"
3151 (ior:HI (zero_extend:HI (match_dup 1))
3152 (ashift:HI (subreg:HI (match_dup 2) 0)
3155 (zero_extend:SI (match_dup 3)))]
3156 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3158 (define_insn "*iorsi3_e2f"
3159 [(set (match_operand:SI 0 "register_operand" "=r")
3160 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3162 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3164 "TARGET_H8300H || TARGET_H8300S"
3166 [(set_attr "length" "2")])
3168 (define_insn_and_split "*iorsi3_two_qi_sext"
3169 [(set (match_operand:SI 0 "register_operand" "=r")
3170 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3171 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3173 "(TARGET_H8300H || TARGET_H8300S)"
3175 "&& reload_completed"
3177 (ior:HI (zero_extend:HI (match_dup 1))
3178 (ashift:HI (match_dup 4)
3181 (sign_extend:SI (match_dup 3)))]
3182 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3183 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3185 (define_insn "*iorsi3_w"
3186 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3187 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3189 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3190 "TARGET_H8300H || TARGET_H8300S"
3192 [(set_attr "length" "2,8")])
3194 (define_insn "*iorsi3_ashift_31"
3195 [(set (match_operand:SI 0 "register_operand" "=&r")
3196 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3198 (match_operand:SI 2 "register_operand" "0")))]
3199 "TARGET_H8300H || TARGET_H8300S"
3200 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3201 [(set_attr "length" "6")
3202 (set_attr "cc" "set_znv")])
3204 (define_insn "*iorsi3_and_ashift"
3205 [(set (match_operand:SI 0 "register_operand" "=r")
3206 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3207 (match_operand:SI 2 "const_int_operand" "n"))
3208 (match_operand:SI 3 "single_one_operand" "n"))
3209 (match_operand:SI 4 "register_operand" "0")))]
3210 "(TARGET_H8300H || TARGET_H8300S)
3211 && (INTVAL (operands[3]) & ~0xffff) == 0"
3214 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3215 - INTVAL (operands[2]));
3216 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3217 operands[2] = srcpos;
3218 operands[3] = dstpos;
3219 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3221 [(set_attr "length" "6")])
3223 (define_insn "*iorsi3_and_lshiftrt"
3224 [(set (match_operand:SI 0 "register_operand" "=r")
3225 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3226 (match_operand:SI 2 "const_int_operand" "n"))
3227 (match_operand:SI 3 "single_one_operand" "n"))
3228 (match_operand:SI 4 "register_operand" "0")))]
3229 "(TARGET_H8300H || TARGET_H8300S)
3230 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3233 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3234 + INTVAL (operands[2]));
3235 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3236 operands[2] = srcpos;
3237 operands[3] = dstpos;
3238 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3240 [(set_attr "length" "6")])
3242 (define_insn "*iorsi3_zero_extract"
3243 [(set (match_operand:SI 0 "register_operand" "=r")
3244 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3246 (match_operand:SI 2 "const_int_operand" "n"))
3247 (match_operand:SI 3 "register_operand" "0")))]
3248 "(TARGET_H8300H || TARGET_H8300S)
3249 && INTVAL (operands[2]) < 16"
3250 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3251 [(set_attr "length" "6")])
3253 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3254 [(set (match_operand:SI 0 "register_operand" "=r")
3255 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3258 (match_operand:SI 2 "register_operand" "0")))]
3259 "(TARGET_H8300H || TARGET_H8300S)"
3260 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3261 [(set_attr "length" "8")])
3263 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3264 [(set (match_operand:SI 0 "register_operand" "=r")
3265 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3267 (const_int 4194304))
3268 (match_operand:SI 2 "register_operand" "0")))
3269 (clobber (match_scratch:HI 3 "=&r"))]
3270 "(TARGET_H8300H || TARGET_H8300S)"
3273 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3274 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3276 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3278 [(set_attr "length" "10")])
3280 ;; Used to OR the exponent of a float.
3282 (define_insn "*iorsi3_shift"
3283 [(set (match_operand:SI 0 "register_operand" "=r")
3284 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3286 (match_operand:SI 2 "register_operand" "0")))
3287 (clobber (match_scratch:SI 3 "=&r"))]
3288 "TARGET_H8300H || TARGET_H8300S"
3292 [(set (match_operand:SI 0 "register_operand" "")
3293 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3296 (clobber (match_operand:SI 2 "register_operand" ""))]
3297 "(TARGET_H8300H || TARGET_H8300S)
3299 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3300 && REGNO (operands[0]) != REGNO (operands[1])"
3301 [(parallel [(set (match_dup 3)
3302 (ashift:HI (match_dup 3)
3304 (clobber (scratch:QI))])
3306 (ior:SI (ashift:SI (match_dup 1)
3309 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3312 [(set (match_operand:SI 0 "register_operand" "")
3313 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3316 (clobber (match_operand:SI 2 "register_operand" ""))]
3317 "(TARGET_H8300H || TARGET_H8300S)
3319 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3320 && REGNO (operands[0]) != REGNO (operands[1]))"
3323 (parallel [(set (match_dup 3)
3324 (ashift:HI (match_dup 3)
3326 (clobber (scratch:QI))])
3328 (ior:SI (ashift:SI (match_dup 2)
3331 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3333 (define_insn "*iorsi2_and_1_lshiftrt_1"
3334 [(set (match_operand:SI 0 "register_operand" "=r")
3335 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3337 (lshiftrt:SI (match_dup 1)
3339 "TARGET_H8300H || TARGET_H8300S"
3340 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3341 [(set_attr "length" "6")])
3343 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3344 [(set (match_operand:SI 0 "register_operand" "=r")
3345 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3347 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3349 "(TARGET_H8300H || TARGET_H8300S)"
3351 "&& reload_completed"
3353 (ior:HI (ashift:HI (match_dup 4)
3356 (parallel [(set (match_dup 0)
3357 (ashift:SI (match_dup 0)
3359 (clobber (scratch:QI))])]
3360 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3361 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3363 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3364 [(set (match_operand:SI 0 "register_operand" "=&r")
3365 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3367 (const_int 16711680))
3368 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3370 "(TARGET_H8300H || TARGET_H8300S)"
3372 "&& reload_completed"
3374 (ior:HI (zero_extend:HI (match_dup 1))
3375 (ashift:HI (subreg:HI (match_dup 2) 0)
3377 (parallel [(set (match_dup 0)
3378 (ashift:SI (match_dup 0)
3380 (clobber (scratch:QI))])]
3381 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3383 ;; Used to add the exponent of a float.
3385 (define_insn "*addsi3_shift"
3386 [(set (match_operand:SI 0 "register_operand" "=r")
3387 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3388 (const_int 8388608))
3389 (match_operand:SI 2 "register_operand" "0")))
3390 (clobber (match_scratch:SI 3 "=&r"))]
3391 "TARGET_H8300H || TARGET_H8300S"
3395 [(set (match_operand:SI 0 "register_operand" "")
3396 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3397 (const_int 8388608))
3399 (clobber (match_operand:SI 2 "register_operand" ""))]
3400 "(TARGET_H8300H || TARGET_H8300S)
3402 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3403 && REGNO (operands[0]) != REGNO (operands[1])"
3404 [(parallel [(set (match_dup 3)
3405 (ashift:HI (match_dup 3)
3407 (clobber (scratch:QI))])
3409 (plus:SI (mult:SI (match_dup 1)
3412 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3415 [(set (match_operand:SI 0 "register_operand" "")
3416 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3417 (const_int 8388608))
3419 (clobber (match_operand:SI 2 "register_operand" ""))]
3420 "(TARGET_H8300H || TARGET_H8300S)
3422 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3423 && REGNO (operands[0]) != REGNO (operands[1]))"
3426 (parallel [(set (match_dup 3)
3427 (ashift:HI (match_dup 3)
3429 (clobber (scratch:QI))])
3431 (plus:SI (mult:SI (match_dup 2)
3434 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3438 (define_insn_and_split "*ashiftsi_sextqi_7"
3439 [(set (match_operand:SI 0 "register_operand" "=r")
3440 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3442 "(TARGET_H8300H || TARGET_H8300S)"
3444 "&& reload_completed"
3445 [(parallel [(set (match_dup 2)
3446 (ashift:HI (match_dup 2)
3448 (clobber (scratch:QI))])
3450 (sign_extend:SI (match_dup 2)))
3451 (parallel [(set (match_dup 0)
3452 (ashiftrt:SI (match_dup 0)
3454 (clobber (scratch:QI))])]
3455 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3457 ;; Storing a part of HImode to QImode.
3460 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3461 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3465 [(set_attr "cc" "set_znv")
3466 (set_attr "length" "8")])
3468 ;; Storing a part of SImode to QImode.
3471 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3472 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3476 [(set_attr "cc" "set_znv")
3477 (set_attr "length" "8")])
3480 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3481 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3483 (clobber (match_scratch:SI 2 "=&r"))]
3484 "TARGET_H8300H || TARGET_H8300S"
3485 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3486 [(set_attr "cc" "set_znv")
3487 (set_attr "length" "10")])
3490 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3491 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3493 (clobber (match_scratch:SI 2 "=&r"))]
3494 "TARGET_H8300H || TARGET_H8300S"
3495 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3496 [(set_attr "cc" "set_znv")
3497 (set_attr "length" "10")])
3499 (define_insn_and_split ""
3501 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3505 (label_ref (match_operand 1 "" ""))
3513 (if_then_else (ge (cc0)
3515 (label_ref (match_dup 1))
3519 (define_insn_and_split ""
3521 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3525 (label_ref (match_operand 1 "" ""))
3533 (if_then_else (lt (cc0)
3535 (label_ref (match_dup 1))
3539 ;; -----------------------------------------------------------------
3540 ;; PEEPHOLE PATTERNS
3541 ;; -----------------------------------------------------------------
3543 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3547 [(set (match_operand:HI 0 "register_operand" "")
3548 (lshiftrt:HI (match_dup 0)
3549 (match_operand:HI 1 "const_int_operand" "")))
3550 (clobber (match_operand:HI 2 "" ""))])
3552 (and:HI (match_dup 0)
3553 (match_operand:HI 3 "const_int_operand" "")))]
3554 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3556 (and:HI (match_dup 0)
3560 (lshiftrt:HI (match_dup 0)
3562 (clobber (match_dup 2))])]
3565 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3569 [(set (match_operand:HI 0 "register_operand" "")
3570 (ashift:HI (match_dup 0)
3571 (match_operand:HI 1 "const_int_operand" "")))
3572 (clobber (match_operand:HI 2 "" ""))])
3574 (and:HI (match_dup 0)
3575 (match_operand:HI 3 "const_int_operand" "")))]
3576 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3578 (and:HI (match_dup 0)
3582 (ashift:HI (match_dup 0)
3584 (clobber (match_dup 2))])]
3587 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3591 [(set (match_operand:SI 0 "register_operand" "")
3592 (lshiftrt:SI (match_dup 0)
3593 (match_operand:SI 1 "const_int_operand" "")))
3594 (clobber (match_operand:SI 2 "" ""))])
3596 (and:SI (match_dup 0)
3597 (match_operand:SI 3 "const_int_operand" "")))]
3598 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3600 (and:SI (match_dup 0)
3604 (lshiftrt:SI (match_dup 0)
3606 (clobber (match_dup 2))])]
3609 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3613 [(set (match_operand:SI 0 "register_operand" "")
3614 (ashift:SI (match_dup 0)
3615 (match_operand:SI 1 "const_int_operand" "")))
3616 (clobber (match_operand:SI 2 "" ""))])
3618 (and:SI (match_dup 0)
3619 (match_operand:SI 3 "const_int_operand" "")))]
3620 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3622 (and:SI (match_dup 0)
3626 (ashift:SI (match_dup 0)
3628 (clobber (match_dup 2))])]
3631 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3635 [(set (match_operand:SI 0 "register_operand" "")
3636 (lshiftrt:SI (match_dup 0)
3637 (match_operand:SI 1 "const_int_operand" "")))
3638 (clobber (match_operand:SI 2 "" ""))])
3640 (and:SI (match_dup 0)
3641 (match_operand:SI 3 "const_int_operand" "")))]
3642 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3644 (and:SI (match_dup 0)
3648 (lshiftrt:SI (match_dup 0)
3650 (clobber (match_dup 2))])]
3653 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3657 [(set (match_operand:SI 0 "register_operand" "")
3658 (ashift:SI (match_dup 0)
3659 (match_operand:SI 1 "const_int_operand" "")))
3660 (clobber (match_operand:SI 2 "" ""))])
3662 (and:SI (match_dup 0)
3663 (match_operand:SI 3 "const_int_operand" "")))]
3664 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3666 (and:SI (match_dup 0)
3670 (ashift:SI (match_dup 0)
3672 (clobber (match_dup 2))])]
3675 ;; Convert a QImode push into an SImode push so that the
3676 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3679 [(parallel [(set (reg:SI SP_REG)
3680 (plus:SI (reg:SI SP_REG) (const_int -4)))
3681 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3682 (match_operand:QI 0 "register_operand" ""))])]
3683 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3684 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3686 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3689 [(parallel [(set (reg:HI SP_REG)
3690 (plus:HI (reg:HI SP_REG) (const_int -4)))
3691 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3692 (match_operand:QI 0 "register_operand" ""))])]
3693 "TARGET_H8300S && TARGET_NORMAL_MODE"
3694 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3696 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3698 ;; Convert a HImode push into an SImode push so that the
3699 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3702 [(parallel [(set (reg:SI SP_REG)
3703 (plus:SI (reg:SI SP_REG) (const_int -4)))
3704 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3705 (match_operand:HI 0 "register_operand" ""))])]
3706 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3707 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3709 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3712 [(parallel [(set (reg:HI SP_REG)
3713 (plus:HI (reg:HI SP_REG) (const_int -4)))
3714 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3715 (match_operand:HI 0 "register_operand" ""))])]
3716 "TARGET_H8300S && TARGET_NORMAL_MODE"
3717 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3719 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3721 ;; Cram four pushes into stm.l.
3724 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3725 (match_operand:SI 0 "register_operand" ""))
3726 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3727 (match_operand:SI 1 "register_operand" ""))
3728 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3729 (match_operand:SI 2 "register_operand" ""))
3730 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3731 (match_operand:SI 3 "register_operand" ""))]
3732 "TARGET_H8300S && !TARGET_NORMAL_MODE
3733 && h8300_regs_ok_for_stm (4, operands)"
3734 [(parallel [(set (reg:SI SP_REG)
3735 (plus:SI (reg:SI SP_REG)
3737 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3739 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3741 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3743 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3748 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3749 (match_operand:SI 0 "register_operand" ""))
3750 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3751 (match_operand:SI 1 "register_operand" ""))
3752 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3753 (match_operand:SI 2 "register_operand" ""))
3754 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3755 (match_operand:SI 3 "register_operand" ""))]
3756 "TARGET_H8300S && TARGET_NORMAL_MODE
3757 && h8300_regs_ok_for_stm (4, operands)"
3758 [(parallel [(set (reg:HI SP_REG)
3759 (plus:HI (reg:HI SP_REG)
3761 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3763 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3765 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3767 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3771 ;; Cram three pushes into stm.l.
3774 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3775 (match_operand:SI 0 "register_operand" ""))
3776 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3777 (match_operand:SI 1 "register_operand" ""))
3778 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3779 (match_operand:SI 2 "register_operand" ""))]
3780 "TARGET_H8300S && !TARGET_NORMAL_MODE
3781 && h8300_regs_ok_for_stm (3, operands)"
3782 [(parallel [(set (reg:SI SP_REG)
3783 (plus:SI (reg:SI SP_REG)
3785 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3787 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3789 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3794 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3795 (match_operand:SI 0 "register_operand" ""))
3796 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3797 (match_operand:SI 1 "register_operand" ""))
3798 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3799 (match_operand:SI 2 "register_operand" ""))]
3800 "TARGET_H8300S && TARGET_NORMAL_MODE
3801 && h8300_regs_ok_for_stm (3, operands)"
3802 [(parallel [(set (reg:HI SP_REG)
3803 (plus:HI (reg:HI SP_REG)
3805 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3807 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3809 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3813 ;; Cram two pushes into stm.l.
3816 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3817 (match_operand:SI 0 "register_operand" ""))
3818 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3819 (match_operand:SI 1 "register_operand" ""))]
3820 "TARGET_H8300S && !TARGET_NORMAL_MODE
3821 && h8300_regs_ok_for_stm (2, operands)"
3822 [(parallel [(set (reg:SI SP_REG)
3823 (plus:SI (reg:SI SP_REG)
3825 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3827 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3832 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3833 (match_operand:SI 0 "register_operand" ""))
3834 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3835 (match_operand:SI 1 "register_operand" ""))]
3836 "TARGET_H8300S && TARGET_NORMAL_MODE
3837 && h8300_regs_ok_for_stm (2, operands)"
3838 [(parallel [(set (reg:HI SP_REG)
3839 (plus:HI (reg:HI SP_REG)
3841 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3843 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3850 ;; add.w r7,r0 (6 bytes)
3855 ;; adds #2,r0 (4 bytes)
3858 [(set (match_operand:HI 0 "register_operand" "")
3859 (match_operand:HI 1 "const_int_operand" ""))
3861 (plus:HI (match_dup 0)
3862 (match_operand:HI 2 "register_operand" "")))]
3863 "REG_P (operands[0]) && REG_P (operands[2])
3864 && REGNO (operands[0]) != REGNO (operands[2])
3865 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3866 || CONST_OK_FOR_L (INTVAL (operands[1]))
3867 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3871 (plus:HI (match_dup 0)
3879 ;; add.l er7,er0 (6 bytes)
3884 ;; adds #4,er0 (4 bytes)
3887 [(set (match_operand:SI 0 "register_operand" "")
3888 (match_operand:SI 1 "const_int_operand" ""))
3890 (plus:SI (match_dup 0)
3891 (match_operand:SI 2 "register_operand" "")))]
3892 "(TARGET_H8300H || TARGET_H8300S)
3893 && REG_P (operands[0]) && REG_P (operands[2])
3894 && REGNO (operands[0]) != REGNO (operands[2])
3895 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3896 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3900 (plus:SI (match_dup 0)
3907 ;; add.l #10,er0 (takes 8 bytes)
3913 ;; add.l er7,er0 (takes 6 bytes)
3916 [(set (match_operand:SI 0 "register_operand" "")
3917 (match_operand:SI 1 "register_operand" ""))
3919 (plus:SI (match_dup 0)
3920 (match_operand:SI 2 "const_int_operand" "")))]
3921 "(TARGET_H8300H || TARGET_H8300S)
3922 && REG_P (operands[0]) && REG_P (operands[1])
3923 && REGNO (operands[0]) != REGNO (operands[1])
3924 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3925 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3926 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3927 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3928 || INTVAL (operands[2]) == 0xffff
3929 || INTVAL (operands[2]) == 0xfffe)"
3933 (plus:SI (match_dup 0)
3949 [(set (match_operand:HI 0 "register_operand" "")
3950 (plus:HI (match_dup 0)
3951 (match_operand 1 "incdec_operand" "")))
3955 (if_then_else (match_operator 3 "eqne_operator"
3956 [(cc0) (const_int 0)])
3957 (label_ref (match_operand 2 "" ""))
3959 "TARGET_H8300H || TARGET_H8300S"
3960 [(set (match_operand:HI 0 "register_operand" "")
3961 (unspec:HI [(match_dup 0)
3967 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3968 (label_ref (match_dup 2))
3972 ;; The SImode version of the previous pattern.
3975 [(set (match_operand:SI 0 "register_operand" "")
3976 (plus:SI (match_dup 0)
3977 (match_operand 1 "incdec_operand" "")))
3981 (if_then_else (match_operator 3 "eqne_operator"
3982 [(cc0) (const_int 0)])
3983 (label_ref (match_operand 2 "" ""))
3985 "TARGET_H8300H || TARGET_H8300S"
3986 [(set (match_operand:SI 0 "register_operand" "")
3987 (unspec:SI [(match_dup 0)
3993 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3994 (label_ref (match_dup 2))
3999 [(parallel [(set (cc0)
4000 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4003 (clobber (scratch:QI))])
4005 (if_then_else (match_operator 1 "eqne_operator"
4006 [(cc0) (const_int 0)])
4007 (label_ref (match_operand 2 "" ""))
4009 "(TARGET_H8300H || TARGET_H8300S)"
4013 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4014 (label_ref (match_dup 2))
4016 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4017 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4018 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4020 ;; The next three peephole2's will try to transform
4022 ;; mov.b A,r0l (or mov.l A,er0)
4029 ;; and.b #CST,r0l (if CST is not 255)
4032 [(set (match_operand:QI 0 "register_operand" "")
4033 (match_operand:QI 1 "general_operand" ""))
4034 (set (match_operand:SI 2 "register_operand" "")
4035 (and:SI (match_dup 2)
4037 "(TARGET_H8300H || TARGET_H8300S)
4038 && !reg_overlap_mentioned_p (operands[2], operands[1])
4039 && REGNO (operands[0]) == REGNO (operands[2])"
4042 (set (strict_low_part (match_dup 0))
4047 [(set (match_operand:SI 0 "register_operand" "")
4048 (match_operand:SI 1 "general_operand" ""))
4050 (and:SI (match_dup 0)
4052 "(TARGET_H8300H || TARGET_H8300S)
4053 && !reg_overlap_mentioned_p (operands[0], operands[1])
4054 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4057 (set (strict_low_part (match_dup 2))
4059 "operands[2] = gen_lowpart (QImode, operands[0]);
4060 operands[3] = gen_lowpart (QImode, operands[1]);")
4063 [(set (match_operand 0 "register_operand" "")
4064 (match_operand 1 "general_operand" ""))
4065 (set (match_operand:SI 2 "register_operand" "")
4066 (and:SI (match_dup 2)
4067 (match_operand:SI 3 "const_int_qi_operand" "")))]
4068 "(TARGET_H8300H || TARGET_H8300S)
4069 && (GET_MODE (operands[0]) == QImode
4070 || GET_MODE (operands[0]) == HImode
4071 || GET_MODE (operands[0]) == SImode)
4072 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4073 && REGNO (operands[0]) == REGNO (operands[2])
4074 && !reg_overlap_mentioned_p (operands[2], operands[1])
4075 && !(GET_MODE (operands[1]) != QImode
4076 && GET_CODE (operands[1]) == MEM
4077 && MEM_VOLATILE_P (operands[1]))"
4080 (set (strict_low_part (match_dup 4))
4083 (and:SI (match_dup 2)
4085 "operands[4] = gen_lowpart (QImode, operands[0]);
4086 operands[5] = gen_lowpart (QImode, operands[1]);
4087 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4090 [(set (match_operand:SI 0 "register_operand" "")
4091 (match_operand:SI 1 "register_operand" ""))
4093 (and:SI (match_dup 0)
4094 (const_int 65280)))]
4095 "(TARGET_H8300H || TARGET_H8300S)
4096 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4099 (set (zero_extract:SI (match_dup 0)
4102 (lshiftrt:SI (match_dup 1)
4106 ;; If a load of mem:SI is followed by an AND that turns off the upper
4107 ;; half, then we can load mem:HI instead.
4110 [(set (match_operand:SI 0 "register_operand" "")
4111 (match_operand:SI 1 "memory_operand" ""))
4113 (and:SI (match_dup 0)
4114 (match_operand:SI 2 "const_int_operand" "")))]
4115 "(TARGET_H8300H || TARGET_H8300S)
4116 && !MEM_VOLATILE_P (operands[1])
4117 && (INTVAL (operands[2]) & ~0xffff) == 0
4118 && INTVAL (operands[2]) != 255"
4122 (and:SI (match_dup 0)
4124 "operands[3] = gen_lowpart (HImode, operands[0]);
4125 operands[4] = gen_lowpart (HImode, operands[1]);")
4127 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4128 ;; the equivalent with shorter sequences. Here is the summary. Cases
4129 ;; are grouped for each define_peephole2.
4131 ;; reg const_int use insn
4132 ;; --------------------------------------------------------
4133 ;; dead -2 eq/ne inc.l
4134 ;; dead -1 eq/ne inc.l
4135 ;; dead 1 eq/ne dec.l
4136 ;; dead 2 eq/ne dec.l
4138 ;; dead 1 geu/ltu shar.l
4139 ;; dead 3 (H8S) geu/ltu shar.l
4141 ;; ---- 255 geu/ltu mov.b
4155 (compare (match_operand:HI 0 "register_operand" "")
4156 (match_operand:HI 1 "incdec_operand" "")))
4158 (if_then_else (match_operator 3 "eqne_operator"
4159 [(cc0) (const_int 0)])
4160 (label_ref (match_operand 2 "" ""))
4162 "(TARGET_H8300H || TARGET_H8300S)
4163 && peep2_reg_dead_p (1, operands[0])"
4165 (unspec:HI [(match_dup 0)
4171 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4172 (label_ref (match_dup 2))
4174 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4188 (compare (match_operand:HI 0 "register_operand" "")
4189 (match_operand:HI 1 "const_int_operand" "")))
4191 (if_then_else (match_operator 2 "gtle_operator"
4192 [(cc0) (const_int 0)])
4193 (label_ref (match_operand 3 "" ""))
4195 "(TARGET_H8300H || TARGET_H8300S)
4196 && peep2_reg_dead_p (1, operands[0])
4197 && (INTVAL (operands[1]) == 1
4198 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4199 [(parallel [(set (match_dup 0)
4200 (ashiftrt:HI (match_dup 0)
4202 (clobber (scratch:QI))])
4206 (if_then_else (match_dup 4)
4207 (label_ref (match_dup 3))
4209 "switch (GET_CODE (operands[2]))
4212 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4215 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4218 operands[4] = operands[2];
4221 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4235 (compare (match_operand:HI 0 "register_operand" "")
4238 (if_then_else (match_operator 1 "gtle_operator"
4239 [(cc0) (const_int 0)])
4240 (label_ref (match_operand 2 "" ""))
4242 "TARGET_H8300H || TARGET_H8300S"
4244 (and:HI (match_dup 0)
4247 (if_then_else (match_dup 3)
4248 (label_ref (match_dup 2))
4250 "switch (GET_CODE (operands[1]))
4253 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4256 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4259 operands[3] = operands[1];
4263 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4264 ;; the equivalent with shorter sequences. Here is the summary. Cases
4265 ;; are grouped for each define_peephole2.
4267 ;; reg const_int use insn
4268 ;; --------------------------------------------------------
4269 ;; live -2 eq/ne copy and inc.l
4270 ;; live -1 eq/ne copy and inc.l
4271 ;; live 1 eq/ne copy and dec.l
4272 ;; live 2 eq/ne copy and dec.l
4274 ;; dead -2 eq/ne inc.l
4275 ;; dead -1 eq/ne inc.l
4276 ;; dead 1 eq/ne dec.l
4277 ;; dead 2 eq/ne dec.l
4279 ;; dead -131072 eq/ne inc.w and test
4280 ;; dead -65536 eq/ne inc.w and test
4281 ;; dead 65536 eq/ne dec.w and test
4282 ;; dead 131072 eq/ne dec.w and test
4284 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4285 ;; dead 0x0000??00 eq/ne xor.b and test
4286 ;; dead 0x0000ffff eq/ne not.w and test
4288 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4289 ;; dead 0xffff??ff eq/ne xor.b and not.l
4290 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4291 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4293 ;; live 1 geu/ltu copy and shar.l
4294 ;; live 3 (H8S) geu/ltu copy and shar.l
4296 ;; dead 1 geu/ltu shar.l
4297 ;; dead 3 (H8S) geu/ltu shar.l
4299 ;; dead 3 (H8/300H) geu/ltu and.b and test
4300 ;; dead 7 geu/ltu and.b and test
4301 ;; dead 15 geu/ltu and.b and test
4302 ;; dead 31 geu/ltu and.b and test
4303 ;; dead 63 geu/ltu and.b and test
4304 ;; dead 127 geu/ltu and.b and test
4305 ;; dead 255 geu/ltu and.b and test
4307 ;; ---- 65535 geu/ltu mov.w
4309 ;; For a small constant, it is cheaper to actually do the subtraction
4310 ;; and then test the register.
4314 (compare (match_operand:SI 0 "register_operand" "")
4315 (match_operand:SI 1 "incdec_operand" "")))
4317 (if_then_else (match_operator 3 "eqne_operator"
4318 [(cc0) (const_int 0)])
4319 (label_ref (match_operand 2 "" ""))
4321 "(TARGET_H8300H || TARGET_H8300S)
4322 && peep2_reg_dead_p (1, operands[0])"
4324 (unspec:SI [(match_dup 0)
4330 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4331 (label_ref (match_dup 2))
4333 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4337 (compare (match_operand:SI 0 "register_operand" "")
4338 (match_operand:SI 1 "const_int_operand" "")))
4340 (if_then_else (match_operator 3 "eqne_operator"
4341 [(cc0) (const_int 0)])
4342 (label_ref (match_operand 2 "" ""))
4344 "(TARGET_H8300H || TARGET_H8300S)
4345 && peep2_reg_dead_p (1, operands[0])
4346 && (INTVAL (operands[1]) == -131072
4347 || INTVAL (operands[1]) == -65536
4348 || INTVAL (operands[1]) == 65536
4349 || INTVAL (operands[1]) == 131072)"
4351 (plus:SI (match_dup 0)
4356 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4357 (label_ref (match_dup 2))
4359 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4361 ;; For certain (in)equality comparisons against a constant, we can
4362 ;; XOR the register with the constant, and test the register against
4367 (compare (match_operand:SI 0 "register_operand" "")
4368 (match_operand:SI 1 "const_int_operand" "")))
4370 (if_then_else (match_operator 3 "eqne_operator"
4371 [(cc0) (const_int 0)])
4372 (label_ref (match_operand 2 "" ""))
4374 "(TARGET_H8300H || TARGET_H8300S)
4375 && peep2_reg_dead_p (1, operands[0])
4376 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4377 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4378 || INTVAL (operands[1]) == 0x0000ffff)
4379 && INTVAL (operands[1]) != 1
4380 && INTVAL (operands[1]) != 2"
4382 (xor:SI (match_dup 0)
4387 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4388 (label_ref (match_dup 2))
4394 (compare (match_operand:SI 0 "register_operand" "")
4395 (match_operand:SI 1 "const_int_operand" "")))
4397 (if_then_else (match_operator 3 "eqne_operator"
4398 [(cc0) (const_int 0)])
4399 (label_ref (match_operand 2 "" ""))
4401 "(TARGET_H8300H || TARGET_H8300S)
4402 && peep2_reg_dead_p (1, operands[0])
4403 && ((INTVAL (operands[1]) | 0x00ff) == -1
4404 || (INTVAL (operands[1]) | 0xff00) == -1)
4405 && INTVAL (operands[1]) != -1
4406 && INTVAL (operands[1]) != -2"
4408 (xor:SI (match_dup 0)
4411 (not:SI (match_dup 0)))
4415 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4416 (label_ref (match_dup 2))
4418 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4422 (compare (match_operand:SI 0 "register_operand" "")
4423 (match_operand:SI 1 "const_int_operand" "")))
4425 (if_then_else (match_operator 3 "eqne_operator"
4426 [(cc0) (const_int 0)])
4427 (label_ref (match_operand 2 "" ""))
4429 "(TARGET_H8300H || TARGET_H8300S)
4430 && peep2_reg_dead_p (1, operands[0])
4431 && (INTVAL (operands[1]) == -2147483647 - 1
4432 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4434 (rotate:SI (match_dup 0)
4437 (unspec:SI [(match_dup 0)
4443 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4444 (label_ref (match_dup 2))
4446 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4459 ;; We avoid this transformation if we see more than one copy of the
4460 ;; same compare insn immediately before this one.
4463 [(match_scratch:SI 4 "r")
4465 (compare (match_operand:SI 0 "register_operand" "")
4466 (match_operand:SI 1 "const_int_operand" "")))
4468 (if_then_else (match_operator 2 "gtle_operator"
4469 [(cc0) (const_int 0)])
4470 (label_ref (match_operand 3 "" ""))
4472 "(TARGET_H8300H || TARGET_H8300S)
4473 && !peep2_reg_dead_p (1, operands[0])
4474 && (INTVAL (operands[1]) == 1
4475 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4476 && !same_cmp_preceding_p (insn)"
4479 (parallel [(set (match_dup 4)
4480 (ashiftrt:SI (match_dup 4)
4482 (clobber (scratch:QI))])
4486 (if_then_else (match_dup 5)
4487 (label_ref (match_dup 3))
4489 "switch (GET_CODE (operands[2]))
4492 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4495 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4498 operands[5] = operands[2];
4501 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4515 (compare (match_operand:SI 0 "register_operand" "")
4516 (match_operand:SI 1 "const_int_operand" "")))
4518 (if_then_else (match_operator 2 "gtle_operator"
4519 [(cc0) (const_int 0)])
4520 (label_ref (match_operand 3 "" ""))
4522 "(TARGET_H8300H || TARGET_H8300S)
4523 && peep2_reg_dead_p (1, operands[0])
4524 && (INTVAL (operands[1]) == 1
4525 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4526 [(parallel [(set (match_dup 0)
4527 (ashiftrt:SI (match_dup 0)
4529 (clobber (scratch:QI))])
4533 (if_then_else (match_dup 4)
4534 (label_ref (match_dup 3))
4536 "switch (GET_CODE (operands[2]))
4539 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4542 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4545 operands[4] = operands[2];
4548 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4563 (compare (match_operand:SI 0 "register_operand" "")
4564 (match_operand:SI 1 "const_int_operand" "")))
4566 (if_then_else (match_operator 2 "gtle_operator"
4567 [(cc0) (const_int 0)])
4568 (label_ref (match_operand 3 "" ""))
4570 "(TARGET_H8300H || TARGET_H8300S)
4571 && peep2_reg_dead_p (1, operands[0])
4572 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4573 || INTVAL (operands[1]) == 7
4574 || INTVAL (operands[1]) == 15
4575 || INTVAL (operands[1]) == 31
4576 || INTVAL (operands[1]) == 63
4577 || INTVAL (operands[1]) == 127
4578 || INTVAL (operands[1]) == 255)"
4580 (and:SI (match_dup 0)
4585 (if_then_else (match_dup 4)
4586 (label_ref (match_dup 3))
4588 "switch (GET_CODE (operands[2]))
4591 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4594 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4597 operands[4] = operands[2];
4600 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4614 (compare (match_operand:SI 0 "register_operand" "")
4617 (if_then_else (match_operator 1 "gtle_operator"
4618 [(cc0) (const_int 0)])
4619 (label_ref (match_operand 2 "" ""))
4621 "TARGET_H8300H || TARGET_H8300S"
4623 (and:SI (match_dup 0)
4624 (const_int -65536)))
4626 (if_then_else (match_dup 3)
4627 (label_ref (match_dup 2))
4629 "switch (GET_CODE (operands[1]))
4632 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4635 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4638 operands[3] = operands[1];
4642 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4643 ;; of the register being tested, do the subtraction on the copy, and
4644 ;; then test the copy. We avoid this transformation if we see more
4645 ;; than one copy of the same compare insn.
4648 [(match_scratch:SI 4 "r")
4650 (compare (match_operand:SI 0 "register_operand" "")
4651 (match_operand:SI 1 "incdec_operand" "")))
4653 (if_then_else (match_operator 3 "eqne_operator"
4654 [(cc0) (const_int 0)])
4655 (label_ref (match_operand 2 "" ""))
4657 "(TARGET_H8300H || TARGET_H8300S)
4658 && !peep2_reg_dead_p (1, operands[0])
4659 && !same_cmp_following_p (insn)"
4663 (unspec:SI [(match_dup 4)
4669 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4670 (label_ref (match_dup 2))
4672 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4674 ;; Narrow the mode of testing if possible.
4677 [(set (match_operand:HI 0 "register_operand" "")
4678 (and:HI (match_dup 0)
4679 (match_operand:HI 1 "const_int_qi_operand" "")))
4683 (if_then_else (match_operator 3 "eqne_operator"
4684 [(cc0) (const_int 0)])
4685 (label_ref (match_operand 2 "" ""))
4687 "peep2_reg_dead_p (2, operands[0])"
4689 (and:QI (match_dup 4)
4694 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4695 (label_ref (match_dup 2))
4697 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4698 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4701 [(set (match_operand:SI 0 "register_operand" "")
4702 (and:SI (match_dup 0)
4703 (match_operand:SI 1 "const_int_qi_operand" "")))
4707 (if_then_else (match_operator 3 "eqne_operator"
4708 [(cc0) (const_int 0)])
4709 (label_ref (match_operand 2 "" ""))
4711 "peep2_reg_dead_p (2, operands[0])"
4713 (and:QI (match_dup 4)
4718 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4719 (label_ref (match_dup 2))
4721 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4722 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4725 [(set (match_operand:SI 0 "register_operand" "")
4726 (and:SI (match_dup 0)
4727 (match_operand:SI 1 "const_int_hi_operand" "")))
4731 (if_then_else (match_operator 3 "eqne_operator"
4732 [(cc0) (const_int 0)])
4733 (label_ref (match_operand 2 "" ""))
4735 "peep2_reg_dead_p (2, operands[0])"
4737 (and:HI (match_dup 4)
4742 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4743 (label_ref (match_dup 2))
4745 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4746 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4749 [(set (match_operand:SI 0 "register_operand" "")
4750 (and:SI (match_dup 0)
4751 (match_operand:SI 1 "const_int_qi_operand" "")))
4753 (xor:SI (match_dup 0)
4754 (match_operand:SI 2 "const_int_qi_operand" "")))
4758 (if_then_else (match_operator 4 "eqne_operator"
4759 [(cc0) (const_int 0)])
4760 (label_ref (match_operand 3 "" ""))
4762 "peep2_reg_dead_p (3, operands[0])
4763 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4765 (and:QI (match_dup 5)
4768 (xor:QI (match_dup 5)
4773 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4774 (label_ref (match_dup 3))
4776 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4777 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4778 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
4780 ;; These triggers right at the end of allocation of locals in the
4781 ;; prologue (and possibly at other places).
4783 ;; stack adjustment of -4, generate one push
4785 ;; before : 6 bytes, 10 clocks
4786 ;; after : 4 bytes, 10 clocks
4789 [(set (reg:SI SP_REG)
4790 (plus:SI (reg:SI SP_REG)
4792 (set (mem:SI (reg:SI SP_REG))
4793 (match_operand:SI 0 "register_operand" ""))]
4794 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4795 && REGNO (operands[0]) != SP_REG"
4796 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4800 ;; stack adjustment of -12, generate one push
4802 ;; before : 10 bytes, 14 clocks
4803 ;; after : 8 bytes, 14 clocks
4806 [(set (reg:SI SP_REG)
4807 (plus:SI (reg:SI SP_REG)
4809 (set (mem:SI (reg:SI SP_REG))
4810 (match_operand:SI 0 "register_operand" ""))]
4811 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4812 && REGNO (operands[0]) != SP_REG"
4813 [(set (reg:SI SP_REG)
4814 (plus:SI (reg:SI SP_REG)
4816 (set (reg:SI SP_REG)
4817 (plus:SI (reg:SI SP_REG)
4819 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))