1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (define_attr "cpu" "h8300,h8300h"
30 (const (symbol_ref "cpu_type")))
32 ;; Many logical operations should have "bit" variants if only one
33 ;; bit is going to be operated on.
35 ;; (and (logical op) (const_int X))
36 ;; If const_int only specifies a few bits (like a single byte in a 4 byte
37 ;; operation, then it's more efficient to only apply the and and logical_op
38 ;; to the bits we care about.
40 ;; Some of the extend instructions accept a general_operand_src, which
41 ;; allows all the normal memory addressing modes. The length computations
42 ;; don't take this into account. The lengths in the MD file should be
43 ;; "worst case" and then be adjusted to their correct values by
44 ;; h8300_adjust_insn_length.
46 ;; On the h8300h, adds/subs operate on the 32bit "er" registers. Right
47 ;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
48 ;; for addhi and subhi is safe.
49 ;; Long term, we want to expose the "e" half to the compiler (gives us
50 ;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
52 ;; There's currently no way to have a insv/extzv expander for the h8/300h
53 ;; because word_mode is different for the h8/300 and h8/300h.
55 ;; Shifts/rotates by small constants should be handled by special
56 ;; patterns so we get the length and cc status correct.
58 ;; Bitfield operations no longer accept memory operands. We need
59 ;; to add variants which operate on memory back to the MD.
61 ;; ??? Implement remaining bit ops available on the h8300
63 (define_attr "type" "branch,arith"
64 (const_string "arith"))
66 ;; The size of instructions in bytes.
68 (define_attr "length" ""
69 (cond [(eq_attr "type" "branch")
70 (if_then_else (and (ge (minus (pc) (match_dup 0))
72 (le (minus (pc) (match_dup 0))
75 (if_then_else (and (eq_attr "cpu" "h8300h")
76 (and (ge (minus (pc) (match_dup 0))
78 (le (minus (pc) (match_dup 0))
84 ;; Condition code settings.
85 ;; none - insn does not affect cc
86 ;; none_0hit - insn does not affect cc but it does modify operand 0
87 ;; This attribute is used to keep track of when operand 0 changes.
88 ;; See the description of NOTICE_UPDATE_CC for more info.
89 ;; set - insn sets flags z,n. v,c are set to 0.
90 ;; (c may not really be set to 0 but that's ok, we don't need it anyway).
91 ;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
92 ;; be known (if it isn't that's ok, we don't need it anyway).
93 ;; compare - compare instruction
94 ;; clobber - value of cc is unknown
95 (define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
96 (const_string "clobber"))
98 ;; ----------------------------------------------------------------------
100 ;; ----------------------------------------------------------------------
104 (define_insn "movqi_push"
105 [(set (match_operand:QI 0 "push_operand" "=<")
106 (match_operand:QI 1 "register_operand" "r"))]
111 return \"push.w %T1\";
113 return \"push.l %S1\";
115 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
116 (set_attr "cc" "set")])
119 [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,o")
120 (match_operand:QI 1 "general_operand_src" "I,r>,r,io,r"))]
121 "register_operand (operands[0],QImode)
122 || register_operand (operands[1], QImode)"
129 [(set_attr_alternative "length"
130 [(const_int 2) (const_int 2) (const_int 2)
131 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
132 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
133 (set_attr "cc" "set_zn_c0,set,set,set,set")])
135 (define_expand "movqi"
136 [(set (match_operand:QI 0 "general_operand_dst" "")
137 (match_operand:QI 1 "general_operand_src" ""))]
141 /* One of the ops has to be in a register */
142 if (!register_operand(operand0, QImode)
143 && !register_operand(operand1, QImode))
145 operands[1] = copy_to_mode_reg(QImode, operand1);
149 (define_insn "movstrictqi"
150 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r"))
151 (match_operand:QI 1 "general_operand_src" "I,r,io"))]
157 [(set_attr_alternative "length"
158 [(const_int 2) (const_int 2)
159 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
160 (set_attr "cc" "set_zn_c0,set,set")])
164 ;; ??? We use push.l on the h8300h to push a 16bit value?!? We have
166 (define_insn "movhi_push"
167 [(set (match_operand:HI 0 "push_operand" "=<")
168 (match_operand:HI 1 "register_operand" "r"))]
173 return \"push.w %T1\";
175 return \"push.l %S1\";
177 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
178 (set_attr "cc" "set")])
181 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,o")
182 (match_operand:HI 1 "general_operand_src" "I,r>,r,io,r"))]
183 "register_operand (operands[0],HImode)
184 || register_operand (operands[1], HImode)"
191 [(set_attr_alternative "length"
192 [(const_int 2) (const_int 2) (const_int 2)
193 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
194 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
195 (set_attr "cc" "set_zn_c0,set,set,set,set")])
197 (define_expand "movhi"
198 [(set (match_operand:HI 0 "general_operand_dst" "")
199 (match_operand:HI 1 "general_operand_src" ""))]
203 /* One of the ops has to be in a register */
204 if (!register_operand(operand1, HImode)
205 && !register_operand(operand0, HImode))
207 operands[1] = copy_to_mode_reg(HImode, operand1);
211 (define_insn "movstricthi"
212 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r"))
213 (match_operand:HI 1 "general_operand_src" "I,r,io"))]
219 [(set_attr_alternative "length"
220 [(const_int 2) (const_int 2)
221 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
222 (set_attr "cc" "set_zn_c0,set,set")])
226 (define_expand "movsi"
227 [(set (match_operand:SI 0 "general_operand_dst" "")
228 (match_operand:SI 1 "general_operand_src" ""))]
234 if (do_movsi (operands))
237 else /* TARGET_H8300H */
239 /* One of the ops has to be in a register. */
240 if (!register_operand (operand1, SImode)
241 && !register_operand (operand0, SImode))
243 operands[1] = copy_to_mode_reg (SImode, operand1);
248 (define_expand "movsf"
249 [(set (match_operand:SF 0 "general_operand_dst" "")
250 (match_operand:SF 1 "general_operand_src" ""))]
256 if (do_movsi (operands))
259 else /* TARGET_H8300H */
261 /* One of the ops has to be in a register. */
262 if (!register_operand (operand1, SFmode)
263 && !register_operand (operand0, SFmode))
265 operands[1] = copy_to_mode_reg (SFmode, operand1);
270 (define_insn "movsi_h8300"
271 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
272 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
274 && (register_operand (operands[0], SImode)
275 || register_operand (operands[1], SImode))"
279 switch (which_alternative)
282 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
284 if (REGNO(operands[0]) < REGNO(operands[1]))
285 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
287 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
289 /* Make sure we don't trample the register we index with. */
291 if (GET_CODE(operands[1]) == MEM)
293 rtx inside = XEXP (operands[1],0);
298 else if (GET_CODE (inside) == PLUS)
300 rtx lhs = XEXP (inside,0);
301 rtx rhs = XEXP (inside,1);
302 if (REG_P (lhs)) rn = REGNO (lhs);
303 if (REG_P (rhs)) rn = REGNO (rhs);
306 if (rn == REGNO (operands[0]))
308 /* Move the second word first. */
309 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
313 /* See if either half is zero. If so, use sub.w to clear
315 if (GET_CODE (operands[1]) == CONST_INT)
317 if ((INTVAL (operands[1]) & 0xffff) == 0)
318 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
319 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
320 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
322 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
325 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
327 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
329 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
332 [(set_attr "length" "4,4,8,8,4,4")
333 (set_attr "cc" "clobber")])
335 (define_insn "movsf_h8300"
336 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
337 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
339 && (register_operand (operands[0], SFmode)
340 || register_operand (operands[1], SFmode))"
343 /* Copy of the movsi stuff */
345 switch (which_alternative)
348 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
350 if (REGNO(operands[0]) < REGNO(operands[1]))
351 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
353 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
355 /* Make sure we don't trample the register we index with. */
357 if (GET_CODE (operands[1]) == MEM)
359 rtx inside = XEXP (operands[1],0);
364 else if (GET_CODE (inside) == PLUS)
366 rtx lhs = XEXP (inside,0);
367 rtx rhs = XEXP (inside,1);
368 if (REG_P (lhs)) rn = REGNO (lhs);
369 if (REG_P (rhs)) rn = REGNO (rhs);
372 if (rn == REGNO (operands[0]))
374 /* move the second word first */
375 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
379 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
383 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
385 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
387 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
391 [(set_attr "length" "4,4,8,8,4,4")
392 (set_attr "cc" "clobber")])
394 (define_insn "movsi_h8300h"
395 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
396 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
398 && (register_operand (operands[0], SImode)
399 || register_operand (operands[1], SImode))"
402 if (which_alternative == 0)
403 return \"sub.l %S0,%S0\";
404 if (GET_CODE (operands[1]) == CONST_INT)
406 int val = INTVAL (operands[1]);
408 /* Look for constants which can be made by adding an 8-bit
409 number to zero in one of the two low bytes. */
410 if (val == (val & 0xff))
412 operands[1] = GEN_INT ((char)val & 0xff);
413 return \"sub.l %S0,%S0\;add.b %1,%w0\";
416 if (val == (val & 0xff00))
418 operands[1] = GEN_INT ((char)(val >> 8) & 0xff);
419 return \"sub.l %S0,%S0\;add.b %1,%x0\";
422 /* Now look for small negative numbers. We can subtract them
423 from zero to get the desired constant. */
424 if (val == -4 || val == -2 || val == -1)
426 operands[1] = GEN_INT (-INTVAL (operands[1]));
427 return \"sub.l %S0,%S0\;subs %1,%S0\";
430 return \"mov.l %S1,%S0\";
432 [(set_attr "length" "2,2,10,10,4,4")
433 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
435 (define_insn "movsf_h8300h"
436 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
437 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
439 && (register_operand (operands[0], SFmode)
440 || register_operand (operands[1], SFmode))"
448 [(set_attr "length" "2,2,10,10,4,4")
449 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
451 ;; ----------------------------------------------------------------------
453 ;; ----------------------------------------------------------------------
456 [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
458 (match_operand:HI 1 "const_int_operand" "n")))]
461 [(set_attr "length" "2")
462 (set_attr "cc" "set_zn_c0")])
465 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
467 (match_operand:HI 1 "const_int_operand" "n")))]
470 [(set_attr "length" "2")
471 (set_attr "cc" "set_zn_c0")])
474 [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
476 (match_operand:HI 1 "const_int_operand" "n")))]
479 [(set_attr "length" "2")
480 (set_attr "cc" "set_zn_c0")])
483 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
486 [(set_attr "length" "2")
487 (set_attr "cc" "set")])
490 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
493 [(set_attr "length" "2")
494 (set_attr "cc" "set")])
497 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
500 [(set_attr "length" "2")
501 (set_attr "cc" "set")])
505 (compare:QI (match_operand:QI 0 "register_operand" "r")
506 (match_operand:QI 1 "nonmemory_operand" "ri")))]
509 [(set_attr "length" "2")
510 (set_attr "cc" "compare")])
512 (define_expand "cmphi"
514 (compare:HI (match_operand:HI 0 "register_operand" "")
515 (match_operand:HI 1 "nonmemory_operand" "")))]
519 /* Force operand1 into a register if we're compiling
521 if (GET_CODE (operands[1]) != REG && !TARGET_H8300H)
522 operands[1] = force_reg (HImode, operands[1]);
527 (compare:HI (match_operand:HI 0 "register_operand" "r")
528 (match_operand:HI 1 "register_operand" "r")))]
531 [(set_attr "length" "2")
532 (set_attr "cc" "compare")])
536 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
537 (match_operand:HI 1 "nonmemory_operand" "r,i")))]
540 [(set_attr "length" "2,4")
541 (set_attr "cc" "compare,compare")])
545 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
546 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
549 [(set_attr "length" "2,6")
550 (set_attr "cc" "compare,compare")])
552 ;; ----------------------------------------------------------------------
554 ;; ----------------------------------------------------------------------
556 (define_insn "addqi3"
557 [(set (match_operand:QI 0 "register_operand" "=r")
558 (plus:QI (match_operand:QI 1 "register_operand" "%0")
559 (match_operand:QI 2 "nonmemory_operand" "ri")))]
562 [(set_attr "length" "2")
563 (set_attr "cc" "set_zn_c0")])
565 (define_expand "addhi3"
566 [(set (match_operand:HI 0 "register_operand" "")
567 (plus:HI (match_operand:HI 1 "register_operand" "")
568 (match_operand:HI 2 "nonmemory_operand" "")))]
572 ;; Specialized version using adds/subs. This must come before
573 ;; the more general patterns below.
575 [(set (match_operand:HI 0 "register_operand" "=r")
576 (plus:HI (match_operand:HI 1 "register_operand" "%0")
577 (match_operand:HI 2 "adds_subs_operand" "i")))]
579 "* return output_adds_subs (operands);"
580 [(set_attr "cc" "none_0hit")
582 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
588 [(set (match_operand:HI 0 "register_operand" "=&r,r,&r")
589 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,g")
590 (match_operand:HI 2 "nonmemory_operand" "n,r,r")))]
593 add.b %s2,%s0\;addx %t2,%t0
595 mov.w %T1,%T0\;add.w %T2,%T0"
596 [(set_attr "length" "4,2,6")
597 (set_attr "cc" "clobber,set_zn_c0,set_zn_c0")])
600 [(set (match_operand:HI 0 "register_operand" "=r,r")
601 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
602 (match_operand:HI 2 "nonmemory_operand" "i,r")))]
607 [(set_attr "length" "4,2")
608 (set_attr "cc" "set_zn_c0,set_zn_c0")])
610 (define_expand "addsi3"
611 [(set (match_operand:SI 0 "register_operand" "")
612 (plus:SI (match_operand:SI 1 "register_operand" "")
613 (match_operand:SI 2 "nonmemory_operand" "")))]
617 ;; Specialized version using adds/subs. This must come before
618 ;; the more general patterns below.
620 [(set (match_operand:SI 0 "register_operand" "=r")
621 (plus:SI (match_operand:SI 1 "register_operand" "%0")
622 (match_operand:SI 2 "adds_subs_operand" "i")))]
624 "* return output_adds_subs (operands);"
625 [(set_attr "cc" "none_0hit")
627 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
632 (define_insn "addsi_h8300"
633 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
634 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
635 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
638 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
639 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
640 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
641 [(set_attr "length" "8,6,10")
642 (set_attr "cc" "clobber")])
644 (define_insn "addsi_h8300h"
645 [(set (match_operand:SI 0 "register_operand" "=r,r")
646 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
647 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
652 [(set_attr "length" "6,2")
653 (set_attr "cc" "set_zn_c0,set_zn_c0")])
655 ;; ----------------------------------------------------------------------
656 ;; SUBTRACT INSTRUCTIONS
657 ;; ----------------------------------------------------------------------
659 (define_insn "subqi3"
660 [(set (match_operand:QI 0 "register_operand" "=r,r")
661 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
662 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
667 [(set_attr "length" "2")
668 (set_attr "cc" "set_zn_c0")])
670 (define_expand "subhi3"
671 [(set (match_operand:HI 0 "register_operand" "")
672 (minus:HI (match_operand:HI 1 "general_operand" "")
673 (match_operand:HI 2 "nonmemory_operand" "")))]
677 ;; Specialized version using adds/subs. This must come before
678 ;; the more general patterns below. This may not be needed
679 ;; due to instruction canonicalization.
681 [(set (match_operand:HI 0 "register_operand" "=r")
682 (minus:HI (match_operand:HI 1 "register_operand" "r")
683 (match_operand:HI 2 "adds_subs_operand" "i")))]
687 operands[2] = GEN_INT (-INTVAL (operands[2]));
688 return output_adds_subs (operands);
690 [(set_attr "cc" "none_0hit")
692 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
698 [(set (match_operand:HI 0 "register_operand" "=r,&r")
699 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
700 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
704 add.b %E2,%s0\;addx %F2,%t0"
705 [(set_attr "length" "2,4")
706 (set_attr "cc" "set_zn_c0,clobber")])
709 [(set (match_operand:HI 0 "register_operand" "=r,&r")
710 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
711 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
716 [(set_attr "length" "2,4")
717 (set_attr "cc" "set_zn_c0,set_zn_c0")])
719 (define_expand "subsi3"
720 [(set (match_operand:SI 0 "register_operand" "")
721 (minus:SI (match_operand:SI 1 "register_operand" "")
722 (match_operand:SI 2 "nonmemory_operand" "")))]
726 (define_insn "subsi3_h8300"
727 [(set (match_operand:SI 0 "register_operand" "=r")
728 (minus:SI (match_operand:SI 1 "register_operand" "0")
729 (match_operand:SI 2 "register_operand" "r")))]
731 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
732 [(set_attr "length" "6")
733 (set_attr "cc" "clobber")])
735 ;; Specialized version using adds/subs. This must come before
736 ;; the more general patterns below. This may not be needed
737 ;; due to instruction canonicalization.
739 [(set (match_operand:SI 0 "register_operand" "=r")
740 (minus:SI (match_operand:SI 1 "general_operand" "0")
741 (match_operand:SI 2 "adds_subs_operand" "i")))]
745 operands[2] = GEN_INT (-INTVAL (operands[2]));
746 return output_adds_subs (operands);
748 [(set_attr "cc" "none_0hit")
750 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
755 (define_insn "subsi3_h8300h"
756 [(set (match_operand:SI 0 "register_operand" "=r,r")
757 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
758 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
763 [(set_attr "length" "2,6")
764 (set_attr "cc" "set_zn_c0,set_zn_c0")])
766 ;; ----------------------------------------------------------------------
767 ;; MULTIPLY INSTRUCTIONS
768 ;; ----------------------------------------------------------------------
770 ;; Note that the h8/300 can only handle umulqihi3.
772 (define_insn "mulqihi3"
773 [(set (match_operand:HI 0 "register_operand" "=r")
774 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
775 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
778 [(set_attr "length" "4")
779 (set_attr "cc" "set_zn_c0")])
781 (define_insn "mulhisi3"
782 [(set (match_operand:SI 0 "register_operand" "=r")
783 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
784 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
787 [(set_attr "length" "4")
788 (set_attr "cc" "set_zn_c0")])
790 (define_insn "umulqihi3"
791 [(set (match_operand:HI 0 "register_operand" "=r")
792 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
793 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
796 [(set_attr "length" "2")
797 (set_attr "cc" "none_0hit")])
799 (define_insn "umulhisi3"
800 [(set (match_operand:SI 0 "register_operand" "=r")
801 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
802 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
805 [(set_attr "length" "2")
806 (set_attr "cc" "none_0hit")])
808 ;; ----------------------------------------------------------------------
809 ;; DIVIDE INSTRUCTIONS
810 ;; ----------------------------------------------------------------------
812 (define_insn "udivqi3"
813 [(set (match_operand:QI 0 "register_operand" "=r")
814 (udiv:QI (match_operand:HI 1 "general_operand" "0")
815 (match_operand:QI 2 "register_operand" "r")))]
818 [(set_attr "length" "2")
819 (set_attr "cc" "clobber")])
821 ;; ??? Will divxu always work here?
823 (define_insn "divqi3"
824 [(set (match_operand:QI 0 "register_operand" "=r")
825 (div:QI (match_operand:HI 1 "general_operand" "0")
826 (match_operand:QI 2 "register_operand" "r")))]
829 [(set_attr "length" "2")
830 (set_attr "cc" "clobber")])
832 (define_insn "udivhi3"
833 [(set (match_operand:HI 0 "register_operand" "=r")
834 (udiv:HI (match_operand:SI 1 "general_operand" "0")
835 (match_operand:HI 2 "register_operand" "r")))]
838 [(set_attr "length" "2")
839 (set_attr "cc" "clobber")])
841 (define_insn "divhi3"
842 [(set (match_operand:HI 0 "register_operand" "=r")
843 (div:HI (match_operand:SI 1 "general_operand" "0")
844 (match_operand:HI 2 "register_operand" "r")))]
847 [(set_attr "length" "4")
848 (set_attr "cc" "clobber")])
850 ;; ----------------------------------------------------------------------
852 ;; ----------------------------------------------------------------------
854 (define_insn "umodqi3"
855 [(set (match_operand:QI 0 "register_operand" "=r")
856 (umod:QI (match_operand:HI 1 "general_operand" "0")
857 (match_operand:QI 2 "register_operand" "r")))]
859 "divxu %X2,%T0\;mov %t0,%s0"
860 [(set_attr "length" "4")
861 (set_attr "cc" "clobber")])
863 (define_insn "modqi3"
864 [(set (match_operand:QI 0 "register_operand" "=r")
865 (mod:QI (match_operand:HI 1 "general_operand" "0")
866 (match_operand:QI 2 "register_operand" "r")))]
868 "divxs.b %X2,%T0\;mov %t0,%s0"
869 [(set_attr "length" "6")
870 (set_attr "cc" "clobber")])
872 (define_insn "umodhi3"
873 [(set (match_operand:HI 0 "register_operand" "=r")
874 (umod:HI (match_operand:SI 1 "general_operand" "0")
875 (match_operand:HI 2 "register_operand" "r")))]
877 "divxu.w %T2,%S0\;mov %e0,%f0"
878 [(set_attr "length" "4")
879 (set_attr "cc" "clobber")])
881 (define_insn "modhi3"
882 [(set (match_operand:HI 0 "register_operand" "=r")
883 (mod:HI (match_operand:SI 1 "general_operand" "0")
884 (match_operand:HI 2 "register_operand" "r")))]
886 "divxs.w %T2,%S0\;mov %e0,%f0"
887 [(set_attr "length" "6")
888 (set_attr "cc" "clobber")])
890 ;; ----------------------------------------------------------------------
892 ;; ----------------------------------------------------------------------
895 [(set (match_operand:QI 0 "bit_operand" "=r,U")
896 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
897 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
898 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
902 [(set_attr "length" "2,4")
903 (set_attr "cc" "set,none_0hit")])
905 (define_expand "andqi3"
906 [(set (match_operand:QI 0 "bit_operand" "")
907 (and:QI (match_operand:QI 1 "bit_operand" "")
908 (match_operand:QI 2 "nonmemory_operand" "")))]
912 if (fix_bit_operand (operands, 'O', AND))
916 (define_insn "andhi3"
917 [(set (match_operand:HI 0 "register_operand" "=r")
918 (and:HI (match_operand:HI 1 "register_operand" "%0")
919 (match_operand:HI 2 "nonmemory_operand" "rn")))]
923 if (GET_CODE (operands[2]) == CONST_INT)
925 int i = INTVAL (operands[2]);
927 if ((i & 0x00ff) != 0x00ff)
928 output_asm_insn (\"and %s2,%s0\", operands);
929 if ((i & 0xff00) != 0xff00)
930 output_asm_insn (\"and %t2,%t0\", operands);
934 return \"and.w %T2,%T0\";
935 return \"and %s2,%s0\;and %t2,%t0;\";
937 [(set_attr "length" "4")
938 (set_attr "cc" "clobber")])
940 (define_insn "andsi3"
941 [(set (match_operand:SI 0 "register_operand" "=r")
942 (and:SI (match_operand:SI 1 "register_operand" "%0")
943 (match_operand:SI 2 "nonmemory_operand" "rn")))]
947 if (GET_CODE (operands[2]) == CONST_INT)
949 int i = INTVAL (operands[2]);
950 int upper_cleared, lower_cleared;
952 /* The h8300h can't do byte-wise operations on the
953 upper 16bits of 32bit registers. However, if
954 those bits aren't going to change, or they're
955 going to be zero'd out, then we can work on the
958 && ((i & 0xffff0000) != 0xffff0000
959 || (i & 0xffff0000) == 0x00000000))
960 return \"and.l %S2,%S0\";
963 if ((i & 0x0000ffff) == 0x00000000)
965 output_asm_insn (\"sub.w %f0,%f0\", operands);
970 if ((i & 0xffff0000) == 0x00000000)
972 output_asm_insn (\"sub.w %e0,%e0\", operands);
976 if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
977 output_asm_insn (\"and %w2,%w0\", operands);
978 if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
979 output_asm_insn (\"and %x2,%x0\", operands);
980 if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared)
981 output_asm_insn (\"and %y2,%y0\", operands);
982 if ((i & 0xff000000) != 0xff000000 && !upper_cleared)
983 output_asm_insn (\"and %z2,%z0\", operands);
987 return \"and.l %S2,%S0\";
988 return \"and %w2,%w0\;and %x2,%x0\;and %y2,%y0\;and %z2,%z0\;\";
990 [(set_attr "length" "8")
991 (set_attr "cc" "clobber")])
994 ;; ----------------------------------------------------------------------
996 ;; ----------------------------------------------------------------------
999 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1000 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1001 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1002 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1006 [(set_attr "length" "2,4")
1007 (set_attr "cc" "set,none_0hit")])
1009 (define_expand "iorqi3"
1010 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1011 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1012 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1016 if (fix_bit_operand (operands, 'P', IOR))
1020 (define_insn "iorhi3"
1021 [(set (match_operand:HI 0 "general_operand" "=r,r")
1022 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1023 (match_operand:HI 2 "general_operand" "J,rn")))]
1027 if (GET_CODE (operands[2]) == CONST_INT)
1029 int i = INTVAL (operands[2]);
1031 if ((i & 0x00ff) != 0)
1032 output_asm_insn (\"or %s2,%s0\", operands);
1033 if ((i & 0xff00) != 0)
1034 output_asm_insn (\"or %t2,%t0\", operands);
1038 return \"or.w %T2,%T0\";
1039 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
1041 [(set_attr "length" "2,4")
1042 (set_attr "cc" "clobber,clobber")])
1044 (define_insn "iorsi3"
1045 [(set (match_operand:SI 0 "register_operand" "=r,r")
1046 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1047 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1051 if (GET_CODE (operands[2]) == CONST_INT)
1053 int i = INTVAL (operands[2]);
1055 /* The h8300h can't do byte-wise operations on the
1056 upper 16bits of 32bit registers. However, if
1057 those bits aren't going to change, then we can
1058 work on the low-order bits. */
1060 && (i & 0xffff0000) != 0x00000000)
1061 return \"or.l %S2,%S0\";
1063 if ((i & 0x000000ff) != 0)
1064 output_asm_insn (\"or %w2,%w0\", operands);
1065 if ((i & 0x0000ff00) != 0)
1066 output_asm_insn (\"or %x2,%x0\", operands);
1067 if ((i & 0x00ff0000) != 0)
1068 output_asm_insn (\"or %y2,%y0\", operands);
1069 if ((i & 0xff000000) != 0)
1070 output_asm_insn (\"or %z2,%z0\", operands);
1074 return \"or.l %S2,%S0\";
1075 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
1077 [(set_attr "length" "2,8")
1078 (set_attr "cc" "clobber,clobber")])
1080 ;; ----------------------------------------------------------------------
1082 ;; ----------------------------------------------------------------------
1085 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1086 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1087 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1088 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1092 [(set_attr "length" "2,4")
1093 (set_attr "cc" "set,none_0hit")])
1095 (define_expand "xorqi3"
1096 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1097 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1098 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1102 if (fix_bit_operand (operands, 'O', XOR))
1106 (define_insn "xorhi3"
1107 [(set (match_operand:HI 0 "register_operand" "=r,r")
1108 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1109 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1113 if (GET_CODE (operands[2]) == CONST_INT)
1115 int i = INTVAL (operands[2]);
1117 if ((i & 0x00ff) != 0)
1118 output_asm_insn (\"xor %s2,%s0\", operands);
1119 if ((i & 0xff00) != 0)
1120 output_asm_insn (\"xor %t2,%t0\", operands);
1124 return \"xor.w %T2,%T0\";
1125 return \"xor %s2,%s0\;xor %t2,%t0\";
1127 [(set_attr "length" "2,4")
1128 (set_attr "cc" "clobber,clobber")])
1130 (define_insn "xorsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r")
1132 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1133 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1137 if (GET_CODE (operands[2]) == CONST_INT)
1139 int i = INTVAL (operands[2]);
1141 /* The h8300h can't do byte-wise operations on the
1142 upper 16bits of 32bit registers. However, if
1143 those bits aren't going to change, then we can
1144 work on the low-order bits. */
1146 && (i & 0xffff0000) != 0x00000000)
1147 return \"xor.l %S2,%S0\";
1149 if ((i & 0x000000ff) != 0)
1150 output_asm_insn (\"xor %w2,%w0\", operands);
1151 if ((i & 0x0000ff00) != 0)
1152 output_asm_insn (\"xor %x2,%x0\", operands);
1153 if ((i & 0x00ff0000) != 0)
1154 output_asm_insn (\"xor %y2,%y0\", operands);
1155 if ((i & 0xff000000) != 0)
1156 output_asm_insn (\"xor %z2,%z0\", operands);
1160 return \"xor.l %S2,%S0\";
1161 return \"xor %w2,%w0\;xor %x2,%x0\;xor %y2,%y0\;xor %z2,%z0\;\";
1163 [(set_attr "length" "2,8")
1164 (set_attr "cc" "clobber,clobber")])
1166 ;; ----------------------------------------------------------------------
1167 ;; NEGATION INSTRUCTIONS
1168 ;; ----------------------------------------------------------------------
1170 (define_insn "negqi2"
1171 [(set (match_operand:QI 0 "register_operand" "=r")
1172 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1175 [(set_attr "length" "2")
1176 (set_attr "cc" "set_zn_c0")])
1178 (define_expand "neghi2"
1179 [(set (match_operand:HI 0 "register_operand" "=r")
1180 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1186 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1191 (define_expand "neghi2_h8300"
1193 (not:HI (match_operand:HI 1 "register_operand" "r")))
1194 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1195 (set (match_operand:HI 0 "register_operand" "=r")
1198 "{ operands[2] = gen_reg_rtx (HImode); }")
1200 (define_insn "neghi2_h8300h"
1201 [(set (match_operand:HI 0 "register_operand" "=r")
1202 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1205 [(set_attr "length" "2")
1206 (set_attr "cc" "set_zn_c0")])
1208 (define_expand "negsi2"
1209 [(set (match_operand:SI 0 "register_operand" "=r")
1210 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1216 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1221 (define_expand "negsi2_h8300"
1223 (not:SI (match_operand:SI 1 "register_operand" "r")))
1224 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1225 (set (match_operand:SI 0 "register_operand" "=r")
1228 "{ operands[2] = gen_reg_rtx(SImode); }")
1230 (define_insn "negsi2_h8300h"
1231 [(set (match_operand:SI 0 "register_operand" "=r")
1232 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1235 [(set_attr "length" "2")
1236 (set_attr "cc" "set_zn_c0")])
1238 ;; ----------------------------------------------------------------------
1240 ;; ----------------------------------------------------------------------
1242 (define_insn "one_cmplqi2"
1243 [(set (match_operand:QI 0 "register_operand" "=r")
1244 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1247 [(set_attr "length" "2")
1248 (set_attr "cc" "set")])
1250 (define_insn "one_cmplhi2"
1251 [(set (match_operand:HI 0 "register_operand" "=r")
1252 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1257 return \"not %s0\;not %t0\";
1261 [(set_attr "cc" "clobber")
1262 (set (attr "length")
1263 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1267 (define_insn "one_cmplsi2"
1268 [(set (match_operand:SI 0 "register_operand" "=r")
1269 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1274 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1278 [(set_attr "cc" "clobber")
1279 (set (attr "length")
1280 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1285 ;; ----------------------------------------------------------------------
1286 ;; JUMP INSTRUCTIONS
1287 ;; ----------------------------------------------------------------------
1289 ;; Conditional jump instructions
1291 (define_expand "ble"
1293 (if_then_else (le (cc0)
1295 (label_ref (match_operand 0 "" ""))
1300 (define_expand "bleu"
1302 (if_then_else (leu (cc0)
1304 (label_ref (match_operand 0 "" ""))
1309 (define_expand "bge"
1311 (if_then_else (ge (cc0)
1313 (label_ref (match_operand 0 "" ""))
1318 (define_expand "bgeu"
1320 (if_then_else (geu (cc0)
1322 (label_ref (match_operand 0 "" ""))
1327 (define_expand "blt"
1329 (if_then_else (lt (cc0)
1331 (label_ref (match_operand 0 "" ""))
1336 (define_expand "bltu"
1338 (if_then_else (ltu (cc0)
1340 (label_ref (match_operand 0 "" ""))
1345 (define_expand "bgt"
1347 (if_then_else (gt (cc0)
1349 (label_ref (match_operand 0 "" ""))
1354 (define_expand "bgtu"
1356 (if_then_else (gtu (cc0)
1358 (label_ref (match_operand 0 "" ""))
1363 (define_expand "beq"
1365 (if_then_else (eq (cc0)
1367 (label_ref (match_operand 0 "" ""))
1372 (define_expand "bne"
1374 (if_then_else (ne (cc0)
1376 (label_ref (match_operand 0 "" ""))
1381 (define_insn "branch_true"
1383 (if_then_else (match_operator 1 "comparison_operator"
1384 [(cc0) (const_int 0)])
1385 (label_ref (match_operand 0 "" ""))
1390 /* If we erroneously deleted a compare insn (which can happen if we need
1391 CC bits set that aren't), emit the compare. */
1392 if (restore_compare_p (operands[1]))
1395 if (get_attr_length (insn) == 2)
1396 return \"b%j1 %l0\";
1397 else if (get_attr_length (insn) == 4)
1398 return \"b%j1 %l0:16\";
1400 return \"b%k1 %L0\;jmp @%l0\;%L0:\";
1402 [(set_attr "type" "branch")
1403 (set_attr "cc" "none")])
1405 (define_insn "branch_false"
1407 (if_then_else (match_operator 1 "comparison_operator"
1408 [(cc0) (const_int 0)])
1410 (label_ref (match_operand 0 "" ""))))]
1414 /* If we erroneously deleted a compare insn (which can happen if we need
1415 CC bits set that aren't), emit the compare. */
1416 if (restore_compare_p (operands[1]))
1419 if (get_attr_length (insn) == 2)
1420 return \"b%k1 %l0\";
1421 else if (get_attr_length (insn) == 4)
1422 return \"b%k1 %l0:16\";
1424 return \"b%j1 %L0\;jmp @%l0\;%L0:\";
1426 [(set_attr "type" "branch")
1427 (set_attr "cc" "none")])
1429 ;; Unconditional and other jump instructions.
1433 (label_ref (match_operand 0 "" "")))]
1437 if (get_attr_length (insn) == 2)
1439 else if (get_attr_length (insn) == 4)
1440 return \"bra %l0:16\";
1442 return \"jmp @%l0\";
1444 [(set_attr "type" "branch")
1445 (set_attr "cc" "none")])
1447 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1449 (define_expand "tablejump"
1450 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1451 (use (label_ref (match_operand 1 "" "")))])]
1455 (define_insn "tablejump_h8300"
1456 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1457 (use (label_ref (match_operand 1 "" "")))]
1460 [(set_attr "cc" "none")
1461 (set_attr "length" "2")])
1463 (define_insn "tablejump_h8300h"
1464 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1465 (use (label_ref (match_operand 1 "" "")))]
1468 [(set_attr "cc" "none")
1469 (set_attr "length" "2")])
1471 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1473 (define_expand "indirect_jump"
1474 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1478 (define_insn "indirect_jump_h8300"
1479 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1482 [(set_attr "cc" "none")
1483 (set_attr "length" "2")])
1485 (define_insn "indirect_jump_h8300h"
1486 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1489 [(set_attr "cc" "none")
1490 (set_attr "length" "2")])
1492 ;; Call subroutine with no return value.
1494 ;; ??? Even though we use HImode here, this works for the 300h.
1497 [(call (match_operand:QI 0 "call_insn_operand" "or")
1498 (match_operand:HI 1 "general_operand" "g"))]
1502 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1503 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1504 return \"jsr\\t\@%0:8\";
1506 return \"jsr\\t%0\";
1508 [(set_attr "cc" "clobber")
1509 (set (attr "length")
1510 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1514 ;; Call subroutine, returning value in operand 0
1515 ;; (which must be a hard register).
1517 ;; ??? Even though we use HImode here, this works on the 300h.
1519 (define_insn "call_value"
1520 [(set (match_operand 0 "" "=r")
1521 (call (match_operand:QI 1 "call_insn_operand" "or")
1522 (match_operand:HI 2 "general_operand" "g")))]
1526 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1527 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1528 return \"jsr\\t\@%1:8\";
1530 return \"jsr\\t%1\";
1532 [(set_attr "cc" "clobber")
1533 (set (attr "length")
1534 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1542 [(set_attr "cc" "none")
1543 (set_attr "length" "2")])
1545 ;; ----------------------------------------------------------------------
1546 ;; EXTEND INSTRUCTIONS
1547 ;; ----------------------------------------------------------------------
1549 (define_insn "zero_extendqihi2"
1550 [(set (match_operand:HI 0 "register_operand" "=r,r")
1551 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1555 mov.b %R1,%s0\;mov.b #0,%t0"
1556 [(set_attr "length" "2,4")
1557 (set_attr "cc" "clobber,clobber")])
1559 ;; The compiler can synthesize a 300H variant of this which is
1560 ;; just as efficient as one that we'd create
1561 (define_insn "zero_extendqisi2"
1562 [(set (match_operand:SI 0 "register_operand" "=r,r")
1563 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1566 mov.b #0,%x0\;sub.w %e0,%e0
1567 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1568 [(set_attr "length" "4,6")
1569 (set_attr "cc" "clobber,clobber")])
1571 (define_expand "zero_extendhisi2"
1572 [(set (match_operand:SI 0 "register_operand" "")
1573 (zero_extend:SI (match_operand:HI 1 "general_operand" "")))]
1577 extern int optimize;
1580 && GET_CODE (operands[1]) != CONST_INT
1583 emit_insn (gen_zero_extendhisi2_h8300 (operands[0], operands[1]));
1588 ;; This is used when not optimizing. It avoids severe code explosion
1589 ;; due to poor register allocation.
1590 (define_expand "zero_extendhisi2_h8300"
1591 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1592 (set (reg:SI 0) (zero_extend:SI (reg:HI 1)))
1593 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1598 [(set (match_operand:SI 0 "register_operand" "=r,r")
1599 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1603 mov.w %e1,%f0\;sub.w %e0,%e0"
1604 [(set_attr "length" "2,4")
1605 (set_attr "cc" "clobber,clobber")])
1608 [(set (match_operand:SI 0 "register_operand" "=r,r")
1609 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1613 mov.w %T1,%T0\;extu.l %S0"
1614 [(set_attr "length" "2,4")
1615 (set_attr "cc" "set,set")])
1617 (define_expand "extendqihi2"
1618 [(set (match_operand:HI 0 "register_operand" "")
1619 (sign_extend:HI (match_operand:QI 1 "general_operand" "")))]
1624 [(set (match_operand:HI 0 "register_operand" "=r,r")
1625 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1628 bld #7,%s0\;subx %t0,%t0
1629 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1630 [(set_attr "length" "4,6")
1631 (set_attr "cc" "clobber,clobber")])
1634 [(set (match_operand:HI 0 "register_operand" "=r,r")
1635 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1639 mov.b %R1,%s0\;exts.w %T0"
1640 [(set_attr "length" "2,4")
1641 (set_attr "cc" "set,set")])
1643 ;; The compiler can synthesize a 300H variant of this which is
1644 ;; just as efficient as one that we'd create
1645 (define_insn "extendqisi2"
1646 [(set (match_operand:SI 0 "register_operand" "=r,r")
1647 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1650 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1651 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1652 [(set_attr "length" "8,10")
1653 (set_attr "cc" "clobber,clobber")])
1655 (define_expand "extendhisi2"
1656 [(set (match_operand:SI 0 "register_operand" "")
1657 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1661 extern int optimize;
1663 && GET_CODE (operands[1]) != CONST_INT
1666 emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
1671 ;; This is used when not optimizing. It avoids severe code explosion
1672 ;; due to poor register allocation.
1673 (define_expand "extendhisi2_h8300"
1674 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1675 (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
1676 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1681 [(set (match_operand:SI 0 "register_operand" "=r,r")
1682 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1685 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1686 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1687 [(set_attr "length" "6,8")
1688 (set_attr "cc" "clobber,clobber")])
1691 [(set (match_operand:SI 0 "register_operand" "=r,r")
1692 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1696 mov.w %T1,%T0\;exts.l %S0"
1697 [(set_attr "length" "2,4")
1698 (set_attr "cc" "set,set")])
1700 ;; ----------------------------------------------------------------------
1702 ;; ----------------------------------------------------------------------
1704 ;; We make some attempt to provide real efficient shifting. One example is
1705 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1706 ;; reg and moving 0 into the former reg.
1708 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1709 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1710 ;; give the optimizer more cracks at the code. However, we wish to do things
1711 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1712 ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
1713 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1714 ;; to detect cases it can optimize.
1716 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1717 ;; easier "do it at insn emit time" route.
1721 (define_expand "ashlqi3"
1722 [(set (match_operand:QI 0 "register_operand" "")
1723 (ashift:QI (match_operand:QI 1 "register_operand" "")
1724 (match_operand:QI 2 "nonmemory_operand" "")))]
1726 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1728 (define_expand "ashrqi3"
1729 [(set (match_operand:QI 0 "register_operand" "")
1730 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1731 (match_operand:QI 2 "nonmemory_operand" "")))]
1733 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1735 (define_expand "lshrqi3"
1736 [(set (match_operand:QI 0 "register_operand" "")
1737 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1738 (match_operand:QI 2 "nonmemory_operand" "")))]
1740 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1743 [(set (match_operand:QI 0 "register_operand" "=r,r")
1744 (match_operator:QI 3 "nshift_operator"
1745 [ (match_operand:QI 1 "register_operand" "0,0")
1746 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1747 (clobber (match_scratch:QI 4 "=X,&r"))]
1749 "* return emit_a_shift (insn, operands);"
1750 [(set_attr "length" "20")
1751 (set_attr "cc" "clobber")])
1755 (define_expand "ashlhi3"
1756 [(set (match_operand:HI 0 "register_operand" "")
1757 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1758 (match_operand:QI 2 "nonmemory_operand" "")))]
1760 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1762 (define_expand "lshrhi3"
1763 [(set (match_operand:HI 0 "register_operand" "")
1764 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1765 (match_operand:QI 2 "nonmemory_operand" "")))]
1767 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1769 (define_expand "ashrhi3"
1770 [(set (match_operand:HI 0 "register_operand" "")
1771 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1772 (match_operand:QI 2 "nonmemory_operand" "")))]
1774 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1777 [(set (match_operand:HI 0 "register_operand" "=r,r")
1778 (match_operator:HI 3 "nshift_operator"
1779 [ (match_operand:HI 1 "register_operand" "0,0")
1780 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1781 (clobber (match_scratch:QI 4 "=X,&r"))]
1783 "* return emit_a_shift (insn, operands);"
1784 [(set_attr "length" "20")
1785 (set_attr "cc" "clobber")])
1789 (define_expand "ashlsi3"
1790 [(set (match_operand:SI 0 "register_operand" "")
1792 (match_operand:SI 1 "general_operand" "")
1793 (match_operand:QI 2 "nonmemory_operand" "")))]
1795 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1797 (define_expand "lshrsi3"
1798 [(set (match_operand:SI 0 "register_operand" "")
1800 (match_operand:SI 1 "general_operand" "")
1801 (match_operand:QI 2 "nonmemory_operand" "")))]
1803 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1805 (define_expand "ashrsi3"
1806 [(set (match_operand:SI 0 "register_operand" "")
1808 (match_operand:SI 1 "general_operand" "")
1809 (match_operand:QI 2 "nonmemory_operand" "")))]
1811 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1814 [(set (match_operand:SI 0 "register_operand" "=r,r")
1815 (match_operator:SI 3 "nshift_operator"
1816 [ (match_operand:SI 1 "register_operand" "0,0")
1817 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1818 (clobber (match_scratch:QI 4 "=X,&r"))]
1820 "* return emit_a_shift (insn, operands);"
1821 [(set_attr "length" "20")
1822 (set_attr "cc" "clobber")])
1824 ;; -----------------------------------------------------------------
1826 ;; -----------------------------------------------------------------
1827 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1828 ;; instructions so let's use them as well as we can.
1830 ;; You'll never believe all these patterns perform one basic action --
1831 ;; load a bit from the source, optionally invert the bit, then store it
1832 ;; in the destination (which is known to be zero)..
1834 ;; Combine obviously need some work to better identify this situation and
1835 ;; canonicalize the form better.
1838 ;; Normal loads with a 16bit destination.
1840 ;; Yes, both cases are needed.
1843 [(set (match_operand:HI 0 "register_operand" "=&r")
1844 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1846 (match_operand:HI 2 "immediate_operand" "i")))]
1848 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1849 [(set_attr "cc" "clobber")
1850 (set_attr "length" "6")])
1853 [(set (match_operand:HI 0 "register_operand" "=&r")
1854 (subreg:HI (zero_extract:SI
1855 (match_operand:HI 1 "register_operand" "r")
1857 (match_operand:HI 2 "immediate_operand" "i")) 1))]
1859 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1860 [(set_attr "cc" "clobber")
1861 (set_attr "length" "6")])
1864 ;; Inverted loads with a 16bit destination.
1866 ;; Yes, all four cases are needed.
1870 [(set (match_operand:HI 0 "register_operand" "=&r")
1871 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1872 (match_operand:HI 3 "p_operand" "P"))
1874 (match_operand:HI 2 "const_int_operand" "n")))]
1875 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1876 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1877 [(set_attr "cc" "clobber")
1878 (set_attr "length" "8")])
1881 [(set (match_operand:HI 0 "register_operand" "=&r")
1884 (match_operand:HI 1 "bit_operand" "Ur")
1885 (match_operand:HI 2 "const_int_operand" "n")))
1888 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1889 [(set_attr "cc" "clobber")
1890 (set_attr "length" "8")])
1893 [(set (match_operand:HI 0 "register_operand" "=&r")
1897 (match_operand:SI 1 "register_operand" "Ur")
1898 (match_operand:SI 2 "const_int_operand" "n")) 1))
1900 "INTVAL (operands[2]) < 16"
1901 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1902 [(set_attr "cc" "clobber")
1903 (set_attr "length" "8")])
1906 [(set (match_operand:HI 0 "register_operand" "=&r")
1910 (match_operand:SI 1 "bit_operand" "Ur")
1911 (match_operand:SI 2 "const_int_operand" "n")) 0))
1913 "TARGET_H8300H && INTVAL (operands[2]) < 16"
1914 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1915 [(set_attr "cc" "clobber")
1916 (set_attr "length" "8")])
1919 ;; Normal loads with a 32bit destination.
1921 ;; Yes, all three cases are needed.
1924 [(set (match_operand:SI 0 "register_operand" "=&r")
1925 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1927 (match_operand:HI 2 "const_int_operand" "n")))]
1929 "* return output_simode_bld (0, 0, operands);"
1930 [(set_attr "cc" "clobber")
1931 (set (attr "length")
1932 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1937 [(set (match_operand:SI 0 "register_operand" "=&r")
1938 (and:SI (zero_extend:SI
1940 (match_operand:QI 1 "bit_operand" "Ur")
1941 (match_operand:QI 2 "const_int_operand" "n")))
1944 "* return output_simode_bld (0, 0, operands);"
1945 [(set_attr "cc" "clobber")
1946 (set (attr "length")
1947 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1952 [(set (match_operand:SI 0 "register_operand" "=&r")
1953 (and:SI (zero_extend:SI
1955 (match_operand:HI 1 "bit_operand" "Ur")
1956 (match_operand:HI 2 "const_int_operand" "n")))
1959 "* return output_simode_bld (0, 0, operands);"
1960 [(set_attr "cc" "clobber")
1961 (set (attr "length")
1962 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1967 ;; Inverted loads with a 32bit destination.
1969 ;; Yes, all seven cases are needed.
1972 [(set (match_operand:SI 0 "register_operand" "=&r")
1974 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
1975 (match_operand:SI 2 "p_operand" "P")))]
1977 "* return output_simode_bld (1, 1, operands);"
1978 [(set_attr "cc" "clobber")
1979 (set (attr "length")
1980 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1984 [(set (match_operand:SI 0 "register_operand" "=&r")
1987 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
1988 (match_operand:HI 2 "const_int_operand" "n"))))
1991 "* return output_simode_bld (1, 0, operands);"
1992 [(set_attr "cc" "clobber")
1993 (set (attr "length")
1994 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1999 [(set (match_operand:SI 0 "register_operand" "=&r")
2001 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
2002 (match_operand:SI 2 "p_operand" "P")))]
2004 "* return output_simode_bld (1, 1, operands);"
2005 [(set_attr "cc" "clobber")
2006 (set (attr "length")
2007 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2011 [(set (match_operand:SI 0 "register_operand" "=&r")
2014 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2015 (match_operand:QI 2 "const_int_operand" "n"))))
2018 "* return output_simode_bld (1, 0, operands);"
2019 [(set_attr "cc" "clobber")
2020 (set (attr "length")
2021 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2026 [(set (match_operand:SI 0 "register_operand" "=&r")
2030 (match_operand:HI 1 "bit_operand" "Ur")
2031 (match_operand:HI 2 "const_int_operand" "n")) 0))
2034 "* return output_simode_bld (1, 0, operands);"
2035 [(set_attr "cc" "clobber")
2036 (set (attr "length")
2037 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2042 [(set (match_operand:SI 0 "register_operand" "=&r")
2046 (match_operand:QI 1 "bit_operand" "Ur")
2047 (match_operand:QI 2 "const_int_operand" "n")) 0))
2050 "* return output_simode_bld (1, 0, operands);"
2051 [(set_attr "cc" "clobber")
2052 (set (attr "length")
2053 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2058 [(set (match_operand:SI 0 "register_operand" "=&r")
2059 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2060 (match_operand:HI 3 "p_operand" "P"))
2062 (match_operand:HI 2 "const_int_operand" "n")))]
2063 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2064 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2065 [(set_attr "cc" "clobber")
2066 (set_attr "length" "8")])
2068 (define_expand "insv"
2069 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2070 (match_operand:HI 1 "general_operand" "")
2071 (match_operand:HI 2 "general_operand" ""))
2072 (match_operand:HI 3 "general_operand" ""))]
2076 /* We only have single bit bitfield instructions. */
2077 if (INTVAL (operands[1]) != 1)
2080 /* For now, we don't allow memory operands. */
2081 if (GET_CODE (operands[0]) == MEM
2082 || GET_CODE (operands[3]) == MEM)
2087 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2089 (match_operand:HI 1 "immediate_operand" "i"))
2090 (match_operand:HI 2 "register_operand" "r"))]
2092 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2093 [(set_attr "cc" "clobber")
2094 (set_attr "length" "4")])
2096 (define_expand "extzv"
2097 [(set (match_operand:HI 0 "register_operand" "")
2098 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2099 (match_operand:HI 2 "general_operand" "")
2100 (match_operand:HI 3 "general_operand" "")))]
2104 /* We only have single bit bitfield instructions. */
2105 if (INTVAL (operands[2]) != 1)
2108 /* For now, we don't allow memory operands. */
2109 if (GET_CODE (operands[1]) == MEM)
2113 ;; BAND, BOR, and BXOR patterns
2116 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2117 (match_operator:HI 4 "bit_operator"
2118 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2120 (match_operand:HI 2 "immediate_operand" "i"))
2121 (match_operand:HI 3 "bit_operand" "0")]))]
2123 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2124 [(set_attr "cc" "clobber")
2125 (set_attr "length" "6")])
2128 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2129 (match_operator:HI 5 "bit_operator"
2130 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2132 (match_operand:HI 2 "immediate_operand" "i"))
2133 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2135 (match_operand:HI 4 "immediate_operand" "i"))]))]
2137 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2138 [(set_attr "cc" "clobber")
2139 (set_attr "length" "6")])
2142 ;; ----------------------------------------------
2143 ;; Peepholes go at the end.
2144 ;; ----------------------------------------------
2146 ;; Notice when two byte moves in a row could be a word move.
2149 [(set (match_operand:QI 0 "register_operand" "=r")
2150 (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
2151 (match_operand:HI 2 "immediate_operand" "n"))))
2152 (set (match_operand:QI 3 "register_operand" "=r")
2153 (mem:QI (plus:HI (match_dup 1)
2154 (match_operand:HI 4 "immediate_operand" "n"))))]
2155 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
2156 "mov.w @(%u4,%T1),%T0"
2157 [(set_attr "length" "6")
2158 (set_attr "cc" "set")])
2161 [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
2162 (match_operand:HI 2 "immediate_operand" "n")))
2163 (match_operand:QI 0 "register_operand" "r"))
2164 (set (mem:QI (plus:HI (match_dup 1)
2165 (match_operand:HI 4 "immediate_operand" "n")))
2166 (match_operand:QI 3 "register_operand" "r"))]
2167 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
2168 "mov.w %T0,@(%u4,%T1)"
2169 [(set_attr "length" "6")
2170 (set_attr "cc" "set")])
2172 ;; Notice a move which could be post incremented.
2175 [(set (match_operand:QI 0 "register_operand" "")
2176 (mem:QI (match_operand:HI 1 "register_operand" "")))
2177 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
2178 "REGNO(operands[1]) != REGNO(operands[0])"
2180 [(set_attr "length" "2")
2181 (set_attr "cc" "set")])
2184 [(set (match_operand:HI 0 "register_operand" "")
2185 (mem:HI (match_operand:HI 1 "register_operand" "")))
2186 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
2187 "REGNO(operands[1]) != REGNO(operands[0])"
2189 [(set_attr "length" "2")
2190 (set_attr "cc" "set")])
2192 ;; Notice a move which could be predecremented.
2195 [(set (match_operand:HI 1 "register_operand" "")
2196 (plus:HI (match_dup 1) (const_int -1)))
2197 (set (mem:QI (match_dup 1))
2198 (match_operand:QI 0 "register_operand" ""))]
2199 "REGNO(operands[1]) != REGNO(operands[0])"
2201 [(set_attr "length" "2")
2202 (set_attr "cc" "set")])
2205 [(set (match_operand:HI 1 "register_operand" "")
2206 (plus:HI (match_dup 1) (const_int -1)))
2207 (set (mem:HI (match_dup 1))
2208 (match_operand:HI 0 "register_operand" ""))]
2209 "REGNO(operands[1]) != REGNO(operands[0])"
2211 [(set_attr "length" "2")
2212 (set_attr "cc" "set")])