1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 93-99, 2000 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (define_attr "cpu" "h8300,h8300h"
30 (const (symbol_ref "cpu_type")))
32 ;; Many logical operations should have "bit" variants if only one
33 ;; bit is going to be operated on.
35 ;; (and (logical op) (const_int X))
36 ;; If const_int only specifies a few bits (like a single byte in a 4 byte
37 ;; operation, then it's more efficient to only apply the and and logical_op
38 ;; to the bits we care about.
40 ;; Some of the extend instructions accept a general_operand_src, which
41 ;; allows all the normal memory addressing modes. The length computations
42 ;; don't take this into account. The lengths in the MD file should be
43 ;; "worst case" and then be adjusted to their correct values by
44 ;; h8300_adjust_insn_length.
46 ;; On the h8300h, adds/subs operate on the 32bit "er" registers. Right
47 ;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
48 ;; for addhi and subhi is safe.
49 ;; Long term, we want to expose the "e" half to the compiler (gives us
50 ;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
52 ;; There's currently no way to have a insv/extzv expander for the h8/300h
53 ;; because word_mode is different for the h8/300 and h8/300h.
55 ;; Shifts/rotates by small constants should be handled by special
56 ;; patterns so we get the length and cc status correct.
58 ;; Bitfield operations no longer accept memory operands. We need
59 ;; to add variants which operate on memory back to the MD.
61 ;; ??? Implement remaining bit ops available on the h8300
63 (define_attr "type" "branch,arith"
64 (const_string "arith"))
66 ;; The size of instructions in bytes.
68 (define_attr "length" ""
69 (cond [(eq_attr "type" "branch")
70 (if_then_else (and (ge (minus (pc) (match_dup 0))
72 (le (minus (pc) (match_dup 0))
75 (if_then_else (and (eq_attr "cpu" "h8300h")
76 (and (ge (minus (pc) (match_dup 0))
78 (le (minus (pc) (match_dup 0))
84 ;; The necessity of instruction length adjustment.
86 (define_attr "adjust_length" "yes,no"
87 (cond [(eq_attr "type" "branch") (const_string "no")]
88 (const_string "yes")))
90 ;; Condition code settings.
91 ;; none - insn does not affect cc
92 ;; none_0hit - insn does not affect cc but it does modify operand 0
93 ;; This attribute is used to keep track of when operand 0 changes.
94 ;; See the description of NOTICE_UPDATE_CC for more info.
95 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
96 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
97 ;; compare - compare instruction
98 ;; clobber - value of cc is unknown
99 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
100 (const_string "clobber"))
102 ;; ----------------------------------------------------------------------
104 ;; ----------------------------------------------------------------------
108 (define_insn "movqi_push"
109 [(set (match_operand:QI 0 "push_operand" "=<")
110 (match_operand:QI 1 "register_operand" "r"))]
115 return \"push.w %T1\";
117 return \"push.l %S1\";
119 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
120 (set_attr "cc" "set_znv")])
123 [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
124 (match_operand:QI 1 "general_operand_src" "I,r>,r,n,m,r"))]
125 "register_operand (operands[0],QImode)
126 || register_operand (operands[1], QImode)"
134 [(set_attr_alternative "length"
135 [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
136 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
137 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
138 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
140 (define_expand "movqi"
141 [(set (match_operand:QI 0 "general_operand_dst" "")
142 (match_operand:QI 1 "general_operand_src" ""))]
146 /* One of the ops has to be in a register */
147 if (!register_operand(operand0, QImode)
148 && !register_operand(operand1, QImode))
150 operands[1] = copy_to_mode_reg(QImode, operand1);
154 (define_insn "movstrictqi"
155 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,r"))
156 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
163 [(set_attr_alternative "length"
164 [(const_int 2) (const_int 2) (const_int 2)
165 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
166 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
170 ;; ??? We use push.l on the h8300h to push a 16bit value?!? We have
172 (define_insn "movhi_push"
173 [(set (match_operand:HI 0 "push_operand" "=<")
174 (match_operand:HI 1 "register_operand" "r"))]
179 return \"push.w %T1\";
181 return \"push.l %S1\";
183 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
184 (set_attr "cc" "set_znv")])
187 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
188 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
189 "register_operand (operands[0],HImode)
190 || register_operand (operands[1], HImode)"
198 [(set_attr_alternative "length"
199 [(const_int 2) (const_int 2) (const_int 2) (const_int 4)
200 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
201 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
202 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
204 (define_expand "movhi"
205 [(set (match_operand:HI 0 "general_operand_dst" "")
206 (match_operand:HI 1 "general_operand_src" ""))]
210 /* One of the ops has to be in a register */
211 if (!register_operand(operand1, HImode)
212 && !register_operand(operand0, HImode))
214 operands[1] = copy_to_mode_reg(HImode, operand1);
218 (define_insn "movstricthi"
219 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,r"))
220 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
227 [(set_attr_alternative "length"
228 [(const_int 2) (const_int 2) (const_int 4)
229 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
230 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
234 (define_expand "movsi"
235 [(set (match_operand:SI 0 "general_operand_dst" "")
236 (match_operand:SI 1 "general_operand_src" ""))]
242 if (do_movsi (operands))
247 /* One of the ops has to be in a register. */
248 if (!register_operand (operand1, SImode)
249 && !register_operand (operand0, SImode))
251 operands[1] = copy_to_mode_reg (SImode, operand1);
256 (define_expand "movsf"
257 [(set (match_operand:SF 0 "general_operand_dst" "")
258 (match_operand:SF 1 "general_operand_src" ""))]
264 if (do_movsi (operands))
269 /* One of the ops has to be in a register. */
270 if (!register_operand (operand1, SFmode)
271 && !register_operand (operand0, SFmode))
273 operands[1] = copy_to_mode_reg (SFmode, operand1);
278 (define_insn "movsi_h8300"
279 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
280 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
282 && (register_operand (operands[0], SImode)
283 || register_operand (operands[1], SImode))"
287 switch (which_alternative)
290 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
292 if (REGNO(operands[0]) < REGNO(operands[1]))
293 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
295 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
297 /* Make sure we don't trample the register we index with. */
299 if (GET_CODE(operands[1]) == MEM)
301 rtx inside = XEXP (operands[1],0);
306 else if (GET_CODE (inside) == PLUS)
308 rtx lhs = XEXP (inside,0);
309 rtx rhs = XEXP (inside,1);
310 if (REG_P (lhs)) rn = REGNO (lhs);
311 if (REG_P (rhs)) rn = REGNO (rhs);
314 if (rn == REGNO (operands[0]))
316 /* Move the second word first. */
317 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
321 /* See if either half is zero. If so, use sub.w to clear
323 if (GET_CODE (operands[1]) == CONST_INT)
325 if ((INTVAL (operands[1]) & 0xffff) == 0)
326 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
327 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
328 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
330 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
333 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
335 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
337 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
342 [(set_attr "length" "4,4,8,8,4,4")
343 (set_attr "cc" "clobber")])
345 (define_insn "movsf_h8300"
346 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
347 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
349 && (register_operand (operands[0], SFmode)
350 || register_operand (operands[1], SFmode))"
353 /* Copy of the movsi stuff */
355 switch (which_alternative)
358 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
360 if (REGNO(operands[0]) < REGNO(operands[1]))
361 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
363 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
365 /* Make sure we don't trample the register we index with. */
367 if (GET_CODE (operands[1]) == MEM)
369 rtx inside = XEXP (operands[1],0);
374 else if (GET_CODE (inside) == PLUS)
376 rtx lhs = XEXP (inside,0);
377 rtx rhs = XEXP (inside,1);
378 if (REG_P (lhs)) rn = REGNO (lhs);
379 if (REG_P (rhs)) rn = REGNO (rhs);
382 if (rn == REGNO (operands[0]))
384 /* move the second word first */
385 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
389 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
393 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
395 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
397 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
402 [(set_attr "length" "4,4,8,8,4,4")
403 (set_attr "cc" "clobber")])
405 (define_insn "movsi_h8300hs"
406 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
407 (match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
408 "(TARGET_H8300S || TARGET_H8300H)
409 && (register_operand (operands[0], SImode)
410 || register_operand (operands[1], SImode))"
413 if (which_alternative == 0)
414 return \"sub.l %S0,%S0\";
415 if (which_alternative == 6)
417 if (which_alternative == 7)
418 return \"clrmac\;ldmac %1,macl\";
419 if (which_alternative == 8)
420 return \"stmac macl,%0\";
421 if (GET_CODE (operands[1]) == CONST_INT)
423 int val = INTVAL (operands[1]);
425 /* Look for constants which can be made by adding an 8-bit
426 number to zero in one of the two low bytes. */
427 if (val == (val & 0xff))
429 operands[1] = GEN_INT ((char)val & 0xff);
430 return \"sub.l %S0,%S0\;add.b %1,%w0\";
433 if (val == (val & 0xff00))
435 operands[1] = GEN_INT ((char)(val >> 8) & 0xff);
436 return \"sub.l %S0,%S0\;add.b %1,%x0\";
439 /* Now look for small negative numbers. We can subtract them
440 from zero to get the desired constant. */
441 if (val == -4 || val == -2 || val == -1)
443 operands[1] = GEN_INT (-INTVAL (operands[1]));
444 return \"sub.l %S0,%S0\;subs %1,%S0\";
447 return \"mov.l %S1,%S0\";
449 [(set_attr "length" "2,2,10,10,4,4,2,6,4")
450 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
452 (define_insn "movsf_h8300h"
453 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
454 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
455 "(TARGET_H8300H || TARGET_H8300S)
456 && (register_operand (operands[0], SFmode)
457 || register_operand (operands[1], SFmode))"
465 [(set_attr "length" "2,2,10,10,4,4")
466 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
468 ;; ----------------------------------------------------------------------
470 ;; ----------------------------------------------------------------------
473 [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
475 (match_operand:QI 1 "const_int_operand" "n")))]
478 [(set_attr "length" "2")
479 (set_attr "cc" "set_zn")])
482 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
484 (match_operand:QI 1 "const_int_operand" "n")))]
487 [(set_attr "length" "2")
488 (set_attr "cc" "set_zn")])
491 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
493 (match_operand:QI 1 "const_int_operand" "n")))]
496 [(set_attr "length" "2")
497 (set_attr "cc" "set_zn")])
500 [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
502 (match_operand:HI 1 "const_int_operand" "n")))]
505 [(set_attr "length" "2")
506 (set_attr "cc" "set_zn")])
509 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
511 (match_operand:HI 1 "const_int_operand" "n")))]
514 [(set_attr "length" "2")
515 (set_attr "cc" "set_zn")])
518 [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
520 (match_operand:HI 1 "const_int_operand" "n")))]
523 [(set_attr "length" "2")
524 (set_attr "cc" "set_zn")])
527 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
530 [(set_attr "length" "2")
531 (set_attr "cc" "set_znv")])
534 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
537 [(set_attr "length" "2")
538 (set_attr "cc" "set_znv")])
541 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
542 "TARGET_H8300H || TARGET_H8300S"
544 [(set_attr "length" "2")
545 (set_attr "cc" "set_znv")])
549 (compare:QI (match_operand:QI 0 "register_operand" "r")
550 (match_operand:QI 1 "nonmemory_operand" "rn")))]
553 [(set_attr "length" "2")
554 (set_attr "cc" "compare")])
556 (define_expand "cmphi"
558 (compare:HI (match_operand:HI 0 "register_operand" "")
559 (match_operand:HI 1 "nonmemory_operand" "")))]
563 /* Force operand1 into a register if we're compiling
565 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
566 operands[1] = force_reg (HImode, operands[1]);
571 (compare:HI (match_operand:HI 0 "register_operand" "r")
572 (match_operand:HI 1 "register_operand" "r")))]
575 [(set_attr "length" "2")
576 (set_attr "cc" "compare")])
580 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
581 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
582 "TARGET_H8300H || TARGET_H8300S"
584 [(set_attr "length" "2,4")
585 (set_attr "cc" "compare,compare")])
589 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
590 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
591 "TARGET_H8300H || TARGET_H8300S"
593 [(set_attr "length" "2,6")
594 (set_attr "cc" "compare,compare")])
596 ;; ----------------------------------------------------------------------
598 ;; ----------------------------------------------------------------------
600 (define_insn "addqi3"
601 [(set (match_operand:QI 0 "register_operand" "=r")
602 (plus:QI (match_operand:QI 1 "register_operand" "%0")
603 (match_operand:QI 2 "nonmemory_operand" "rn")))]
606 [(set_attr "length" "2")
607 (set_attr "cc" "set_zn")])
609 (define_expand "addhi3"
610 [(set (match_operand:HI 0 "register_operand" "")
611 (plus:HI (match_operand:HI 1 "register_operand" "")
612 (match_operand:HI 2 "nonmemory_operand" "")))]
616 ;; Specialized version using adds/subs. This must come before
617 ;; the more general patterns below.
619 [(set (match_operand:HI 0 "register_operand" "=r")
620 (plus:HI (match_operand:HI 1 "register_operand" "%0")
621 (match_operand:HI 2 "adds_subs_operand" "n")))]
623 "* return output_adds_subs (operands);"
624 [(set_attr "cc" "none_0hit")
626 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
632 [(set (match_operand:HI 0 "register_operand" "=&r,r,&r")
633 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,g")
634 (match_operand:HI 2 "nonmemory_operand" "n,r,r")))]
637 add.b %s2,%s0\;addx %t2,%t0
639 mov.w %T1,%T0\;add.w %T2,%T0"
640 [(set_attr "length" "4,2,6")
641 (set_attr "cc" "clobber,set_zn,set_zn")])
644 [(set (match_operand:HI 0 "register_operand" "=r,r")
645 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
646 (match_operand:HI 2 "nonmemory_operand" "n,r")))]
647 "TARGET_H8300H || TARGET_H8300S"
651 [(set_attr "length" "4,2")
652 (set_attr "cc" "set_zn,set_zn")])
654 (define_expand "addsi3"
655 [(set (match_operand:SI 0 "register_operand" "")
656 (plus:SI (match_operand:SI 1 "register_operand" "")
657 (match_operand:SI 2 "nonmemory_operand" "")))]
661 ;; Specialized version using adds/subs. This must come before
662 ;; the more general patterns below.
664 [(set (match_operand:SI 0 "register_operand" "=r")
665 (plus:SI (match_operand:SI 1 "register_operand" "%0")
666 (match_operand:SI 2 "adds_subs_operand" "n")))]
667 "TARGET_H8300H || TARGET_H8300S"
668 "* return output_adds_subs (operands);"
669 [(set_attr "cc" "none_0hit")
671 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
676 (define_insn "addsi_h8300"
677 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
678 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
679 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
682 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
683 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
684 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
685 [(set_attr "length" "8,6,10")
686 (set_attr "cc" "clobber")])
688 (define_insn "addsi_h8300h"
689 [(set (match_operand:SI 0 "register_operand" "=r,r")
690 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
691 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
692 "TARGET_H8300H || TARGET_H8300S"
696 [(set_attr "length" "6,2")
697 (set_attr "cc" "set_zn,set_zn")])
699 ;; ----------------------------------------------------------------------
700 ;; SUBTRACT INSTRUCTIONS
701 ;; ----------------------------------------------------------------------
703 (define_insn "subqi3"
704 [(set (match_operand:QI 0 "register_operand" "=r,r")
705 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
706 (match_operand:QI 2 "nonmemory_operand" "r,n")))]
711 [(set_attr "length" "2")
712 (set_attr "cc" "set_zn")])
714 (define_expand "subhi3"
715 [(set (match_operand:HI 0 "register_operand" "")
716 (minus:HI (match_operand:HI 1 "general_operand" "")
717 (match_operand:HI 2 "nonmemory_operand" "")))]
721 ;; Specialized version using adds/subs. This must come before
722 ;; the more general patterns below. This may not be needed
723 ;; due to instruction canonicalization.
725 [(set (match_operand:HI 0 "register_operand" "=r")
726 (minus:HI (match_operand:HI 1 "register_operand" "r")
727 (match_operand:HI 2 "adds_subs_operand" "n")))]
731 operands[2] = GEN_INT (-INTVAL (operands[2]));
732 return output_adds_subs (operands);
734 [(set_attr "cc" "none_0hit")
736 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
742 [(set (match_operand:HI 0 "register_operand" "=r,&r")
743 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
744 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
748 add.b %E2,%s0\;addx %F2,%t0"
749 [(set_attr "length" "2,4")
750 (set_attr "cc" "set_zn,clobber")])
753 [(set (match_operand:HI 0 "register_operand" "=r,&r")
754 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
755 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
756 "TARGET_H8300H || TARGET_H8300S"
760 [(set_attr "length" "2,4")
761 (set_attr "cc" "set_zn,set_zn")])
763 (define_expand "subsi3"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (minus:SI (match_operand:SI 1 "register_operand" "")
766 (match_operand:SI 2 "nonmemory_operand" "")))]
770 (define_insn "subsi3_h8300"
771 [(set (match_operand:SI 0 "register_operand" "=r")
772 (minus:SI (match_operand:SI 1 "register_operand" "0")
773 (match_operand:SI 2 "register_operand" "r")))]
775 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
776 [(set_attr "length" "6")
777 (set_attr "cc" "clobber")])
779 ;; Specialized version using adds/subs. This must come before
780 ;; the more general patterns below. This may not be needed
781 ;; due to instruction canonicalization.
783 [(set (match_operand:SI 0 "register_operand" "=r")
784 (minus:SI (match_operand:SI 1 "general_operand" "0")
785 (match_operand:SI 2 "adds_subs_operand" "n")))]
786 "TARGET_H8300H || TARGET_H8300S"
789 operands[2] = GEN_INT (-INTVAL (operands[2]));
790 return output_adds_subs (operands);
792 [(set_attr "cc" "none_0hit")
794 (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
799 (define_insn "subsi3_h8300h"
800 [(set (match_operand:SI 0 "register_operand" "=r,r")
801 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
802 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
803 "TARGET_H8300H || TARGET_H8300S"
807 [(set_attr "length" "2,6")
808 (set_attr "cc" "set_zn,set_zn")])
810 ;; ----------------------------------------------------------------------
811 ;; MULTIPLY INSTRUCTIONS
812 ;; ----------------------------------------------------------------------
814 ;; Note that the h8/300 can only handle umulqihi3.
816 (define_insn "mulqihi3"
817 [(set (match_operand:HI 0 "register_operand" "=r")
818 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
819 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
820 "TARGET_H8300H || TARGET_H8300S"
822 [(set_attr "length" "4")
823 (set_attr "cc" "set_zn")])
825 (define_insn "mulhisi3"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
828 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
829 "TARGET_H8300H || TARGET_H8300S"
831 [(set_attr "length" "4")
832 (set_attr "cc" "set_zn")])
834 (define_insn "umulqihi3"
835 [(set (match_operand:HI 0 "register_operand" "=r")
836 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
837 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
840 [(set_attr "length" "2")
841 (set_attr "cc" "none_0hit")])
843 (define_insn "umulhisi3"
844 [(set (match_operand:SI 0 "register_operand" "=r")
845 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
846 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
847 "TARGET_H8300H || TARGET_H8300S"
849 [(set_attr "length" "2")
850 (set_attr "cc" "none_0hit")])
852 ;; This is a "bridge" instruction. Combine can't cram enough insns
853 ;; together to crate a MAC instruction directly, but it can create
854 ;; this instruction, which then allows combine to create the real
857 ;; Unfortunately, if combine doesn't create a MAC instruction, this
858 ;; insn must generate reasonably correct code. Egad.
860 [(set (match_operand:SI 0 "register_operand" "=a")
863 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
865 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
868 [(set_attr "length" "6")
869 (set_attr "cc" "none_0hit")])
872 [(set (match_operand:SI 0 "register_operand" "=a")
874 (sign_extend:SI (mem:HI
875 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
876 (sign_extend:SI (mem:HI
877 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
878 (match_operand:SI 3 "register_operand" "0")))]
881 [(set_attr "length" "4")
882 (set_attr "cc" "none_0hit")])
884 ;; ----------------------------------------------------------------------
885 ;; DIVIDE INSTRUCTIONS
886 ;; ----------------------------------------------------------------------
888 (define_insn "udivqi3"
889 [(set (match_operand:QI 0 "register_operand" "=r")
892 (match_operand:HI 1 "general_operand" "0")
893 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
896 [(set_attr "length" "2")
897 (set_attr "cc" "clobber")])
899 ;; ??? Will divxu always work here?
901 (define_insn "divqi3"
902 [(set (match_operand:QI 0 "register_operand" "=r")
905 (match_operand:HI 1 "general_operand" "0")
906 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
909 [(set_attr "length" "2")
910 (set_attr "cc" "clobber")])
912 (define_insn "udivhi3"
913 [(set (match_operand:HI 0 "register_operand" "=r")
916 (match_operand:SI 1 "general_operand" "0")
917 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
918 "TARGET_H8300H || TARGET_H8300S"
920 [(set_attr "length" "2")
921 (set_attr "cc" "clobber")])
923 (define_insn "divhi3"
924 [(set (match_operand:HI 0 "register_operand" "=r")
927 (match_operand:SI 1 "general_operand" "0")
928 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
929 "TARGET_H8300H || TARGET_H8300S"
931 [(set_attr "length" "4")
932 (set_attr "cc" "clobber")])
934 ;; ----------------------------------------------------------------------
936 ;; ----------------------------------------------------------------------
938 (define_insn "umodqi3"
939 [(set (match_operand:QI 0 "register_operand" "=r")
942 (match_operand:HI 1 "general_operand" "0")
943 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
945 "divxu %X2,%T0\;mov %t0,%s0"
946 [(set_attr "length" "4")
947 (set_attr "cc" "clobber")])
949 (define_insn "modqi3"
950 [(set (match_operand:QI 0 "register_operand" "=r")
953 (match_operand:HI 1 "general_operand" "0")
954 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
955 "TARGET_H8300H || TARGET_H8300S"
956 "divxs.b %X2,%T0\;mov %t0,%s0"
957 [(set_attr "length" "6")
958 (set_attr "cc" "clobber")])
960 (define_insn "umodhi3"
961 [(set (match_operand:HI 0 "register_operand" "=r")
964 (match_operand:SI 1 "general_operand" "0")
965 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
966 "TARGET_H8300H || TARGET_H8300S"
967 "divxu.w %T2,%S0\;mov %e0,%f0"
968 [(set_attr "length" "4")
969 (set_attr "cc" "clobber")])
971 (define_insn "modhi3"
972 [(set (match_operand:HI 0 "register_operand" "=r")
975 (match_operand:SI 1 "general_operand" "0")
976 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
977 "TARGET_H8300H || TARGET_H8300S"
978 "divxs.w %T2,%S0\;mov %e0,%f0"
979 [(set_attr "length" "6")
980 (set_attr "cc" "clobber")])
982 ;; ----------------------------------------------------------------------
984 ;; ----------------------------------------------------------------------
987 [(set (match_operand:QI 0 "bit_operand" "=r,U")
988 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
989 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
990 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
994 [(set_attr "length" "2,4")
995 (set_attr "adjust_length" "no")
996 (set_attr "cc" "set_znv,none_0hit")])
998 (define_expand "andqi3"
999 [(set (match_operand:QI 0 "bit_operand" "")
1000 (and:QI (match_operand:QI 1 "bit_operand" "")
1001 (match_operand:QI 2 "nonmemory_operand" "")))]
1005 if (fix_bit_operand (operands, 'O', AND))
1009 (define_insn "andhi3"
1010 [(set (match_operand:HI 0 "register_operand" "=r")
1011 (and:HI (match_operand:HI 1 "register_operand" "%0")
1012 (match_operand:HI 2 "nonmemory_operand" "rn")))]
1016 if (GET_CODE (operands[2]) == CONST_INT)
1018 int i = INTVAL (operands[2]);
1020 if ((i & 0x00ff) != 0x00ff)
1021 output_asm_insn (\"and %s2,%s0\", operands);
1022 if ((i & 0xff00) != 0xff00)
1023 output_asm_insn (\"and %t2,%t0\", operands);
1026 if (TARGET_H8300H || TARGET_H8300S)
1027 return \"and.w %T2,%T0\";
1028 return \"and %s2,%s0\;and %t2,%t0;\";
1030 [(set_attr "length" "4")
1031 (set_attr "cc" "clobber")])
1033 (define_insn "andsi3"
1034 [(set (match_operand:SI 0 "register_operand" "=r")
1035 (and:SI (match_operand:SI 1 "register_operand" "%0")
1036 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1040 if (GET_CODE (operands[2]) == CONST_INT)
1042 int i = INTVAL (operands[2]);
1043 int upper_cleared, lower_cleared;
1045 /* The h8300h can't do byte-wise operations on the
1046 upper 16bits of 32bit registers. However, if
1047 those bits aren't going to change, or they're
1048 going to be zero'd out, then we can work on the
1050 if ((TARGET_H8300H || TARGET_H8300S)
1051 && ((i & 0xffff0000) != 0xffff0000
1052 || (i & 0xffff0000) == 0x00000000))
1053 return \"and.l %S2,%S0\";
1056 if ((i & 0x0000ffff) == 0x00000000)
1058 output_asm_insn (\"sub.w %f0,%f0\", operands);
1063 if ((i & 0xffff0000) == 0x00000000)
1065 output_asm_insn (\"sub.w %e0,%e0\", operands);
1069 if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
1070 output_asm_insn (\"and %w2,%w0\", operands);
1071 if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
1072 output_asm_insn (\"and %x2,%x0\", operands);
1073 if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared)
1074 output_asm_insn (\"and %y2,%y0\", operands);
1075 if ((i & 0xff000000) != 0xff000000 && !upper_cleared)
1076 output_asm_insn (\"and %z2,%z0\", operands);
1079 if (TARGET_H8300H || TARGET_H8300S)
1080 return \"and.l %S2,%S0\";
1081 return \"and %w2,%w0\;and %x2,%x0\;and %y2,%y0\;and %z2,%z0\;\";
1083 [(set_attr "length" "8")
1084 (set_attr "cc" "clobber")])
1087 ;; ----------------------------------------------------------------------
1089 ;; ----------------------------------------------------------------------
1092 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1093 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1094 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1095 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1099 [(set_attr "length" "2,4")
1100 (set_attr "adjust_length" "no")
1101 (set_attr "cc" "set_znv,none_0hit")])
1103 (define_expand "iorqi3"
1104 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1105 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1106 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1110 if (fix_bit_operand (operands, 'P', IOR))
1114 (define_insn "iorhi3"
1115 [(set (match_operand:HI 0 "general_operand" "=r,r")
1116 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1117 (match_operand:HI 2 "general_operand" "J,rn")))]
1121 if (GET_CODE (operands[2]) == CONST_INT)
1123 int i = INTVAL (operands[2]);
1125 if ((i & 0x00ff) != 0)
1126 output_asm_insn (\"or %s2,%s0\", operands);
1127 if ((i & 0xff00) != 0)
1128 output_asm_insn (\"or %t2,%t0\", operands);
1131 if (TARGET_H8300H || TARGET_H8300S)
1132 return \"or.w %T2,%T0\";
1133 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
1135 [(set_attr "length" "2,4")
1136 (set_attr "cc" "clobber,clobber")])
1138 (define_insn "iorsi3"
1139 [(set (match_operand:SI 0 "register_operand" "=r,r")
1140 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1141 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1145 if (GET_CODE (operands[2]) == CONST_INT)
1147 int i = INTVAL (operands[2]);
1149 /* The h8300h can't do byte-wise operations on the
1150 upper 16bits of 32bit registers. However, if
1151 those bits aren't going to change, then we can
1152 work on the low-order bits. */
1153 if ((TARGET_H8300H || TARGET_H8300S)
1154 && (i & 0xffff0000) != 0x00000000)
1155 return \"or.l %S2,%S0\";
1157 if ((i & 0x000000ff) != 0)
1158 output_asm_insn (\"or %w2,%w0\", operands);
1159 if ((i & 0x0000ff00) != 0)
1160 output_asm_insn (\"or %x2,%x0\", operands);
1161 if ((i & 0x00ff0000) != 0)
1162 output_asm_insn (\"or %y2,%y0\", operands);
1163 if ((i & 0xff000000) != 0)
1164 output_asm_insn (\"or %z2,%z0\", operands);
1167 if (TARGET_H8300H || TARGET_H8300S)
1168 return \"or.l %S2,%S0\";
1169 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
1171 [(set_attr "length" "2,8")
1172 (set_attr "cc" "clobber,clobber")])
1174 ;; ----------------------------------------------------------------------
1176 ;; ----------------------------------------------------------------------
1179 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1180 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1181 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1182 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1186 [(set_attr "length" "2,4")
1187 (set_attr "adjust_length" "no")
1188 (set_attr "cc" "set_znv,none_0hit")])
1190 (define_expand "xorqi3"
1191 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1192 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1193 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1197 if (fix_bit_operand (operands, 'O', XOR))
1201 (define_insn "xorhi3"
1202 [(set (match_operand:HI 0 "register_operand" "=r,r")
1203 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1204 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1208 if (GET_CODE (operands[2]) == CONST_INT)
1210 int i = INTVAL (operands[2]);
1212 if ((i & 0x00ff) != 0)
1213 output_asm_insn (\"xor %s2,%s0\", operands);
1214 if ((i & 0xff00) != 0)
1215 output_asm_insn (\"xor %t2,%t0\", operands);
1218 if (TARGET_H8300H || TARGET_H8300S)
1219 return \"xor.w %T2,%T0\";
1220 return \"xor %s2,%s0\;xor %t2,%t0\";
1222 [(set_attr "length" "2,4")
1223 (set_attr "cc" "clobber,clobber")])
1225 (define_insn "xorsi3"
1226 [(set (match_operand:SI 0 "register_operand" "=r,r")
1227 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1228 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1232 if (GET_CODE (operands[2]) == CONST_INT)
1234 int i = INTVAL (operands[2]);
1236 /* The h8300h can't do byte-wise operations on the
1237 upper 16bits of 32bit registers. However, if
1238 those bits aren't going to change, then we can
1239 work on the low-order bits. */
1240 if ((TARGET_H8300H || TARGET_H8300S)
1241 && (i & 0xffff0000) != 0x00000000)
1242 return \"xor.l %S2,%S0\";
1244 if ((i & 0x000000ff) != 0)
1245 output_asm_insn (\"xor %w2,%w0\", operands);
1246 if ((i & 0x0000ff00) != 0)
1247 output_asm_insn (\"xor %x2,%x0\", operands);
1248 if ((i & 0x00ff0000) != 0)
1249 output_asm_insn (\"xor %y2,%y0\", operands);
1250 if ((i & 0xff000000) != 0)
1251 output_asm_insn (\"xor %z2,%z0\", operands);
1254 if (TARGET_H8300H || TARGET_H8300S)
1255 return \"xor.l %S2,%S0\";
1256 return \"xor %w2,%w0\;xor %x2,%x0\;xor %y2,%y0\;xor %z2,%z0\;\";
1258 [(set_attr "length" "2,8")
1259 (set_attr "cc" "clobber,clobber")])
1261 ;; ----------------------------------------------------------------------
1262 ;; NEGATION INSTRUCTIONS
1263 ;; ----------------------------------------------------------------------
1265 (define_insn "negqi2"
1266 [(set (match_operand:QI 0 "register_operand" "=r")
1267 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1270 [(set_attr "length" "2")
1271 (set_attr "cc" "set_zn")])
1273 (define_expand "neghi2"
1274 [(set (match_operand:HI 0 "register_operand" "=r")
1275 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1281 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1286 (define_expand "neghi2_h8300"
1288 (not:HI (match_operand:HI 1 "register_operand" "r")))
1289 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1290 (set (match_operand:HI 0 "register_operand" "=r")
1293 "{ operands[2] = gen_reg_rtx (HImode); }")
1295 (define_insn "neghi2_h8300h"
1296 [(set (match_operand:HI 0 "register_operand" "=r")
1297 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1298 "TARGET_H8300H || TARGET_H8300S"
1300 [(set_attr "length" "2")
1301 (set_attr "cc" "set_zn")])
1303 (define_expand "negsi2"
1304 [(set (match_operand:SI 0 "register_operand" "=r")
1305 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1311 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1316 (define_expand "negsi2_h8300"
1318 (not:SI (match_operand:SI 1 "register_operand" "r")))
1319 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1320 (set (match_operand:SI 0 "register_operand" "=r")
1323 "{ operands[2] = gen_reg_rtx(SImode); }")
1325 (define_insn "negsi2_h8300h"
1326 [(set (match_operand:SI 0 "register_operand" "=r")
1327 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1328 "TARGET_H8300H || TARGET_H8300S"
1330 [(set_attr "length" "2")
1331 (set_attr "cc" "set_zn")])
1333 ;; ----------------------------------------------------------------------
1335 ;; ----------------------------------------------------------------------
1337 (define_insn "one_cmplqi2"
1338 [(set (match_operand:QI 0 "register_operand" "=r")
1339 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1342 [(set_attr "length" "2")
1343 (set_attr "cc" "set_znv")])
1345 (define_insn "one_cmplhi2"
1346 [(set (match_operand:HI 0 "register_operand" "=r")
1347 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1352 return \"not %s0\;not %t0\";
1356 [(set_attr "cc" "clobber")
1357 (set (attr "length")
1358 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1363 (define_insn "one_cmplsi2"
1364 [(set (match_operand:SI 0 "register_operand" "=r")
1365 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1370 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1374 [(set_attr "cc" "clobber")
1375 (set (attr "length")
1376 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1382 ;; ----------------------------------------------------------------------
1383 ;; JUMP INSTRUCTIONS
1384 ;; ----------------------------------------------------------------------
1386 ;; Conditional jump instructions
1388 (define_expand "ble"
1390 (if_then_else (le (cc0)
1392 (label_ref (match_operand 0 "" ""))
1397 (define_expand "bleu"
1399 (if_then_else (leu (cc0)
1401 (label_ref (match_operand 0 "" ""))
1406 (define_expand "bge"
1408 (if_then_else (ge (cc0)
1410 (label_ref (match_operand 0 "" ""))
1415 (define_expand "bgeu"
1417 (if_then_else (geu (cc0)
1419 (label_ref (match_operand 0 "" ""))
1424 (define_expand "blt"
1426 (if_then_else (lt (cc0)
1428 (label_ref (match_operand 0 "" ""))
1433 (define_expand "bltu"
1435 (if_then_else (ltu (cc0)
1437 (label_ref (match_operand 0 "" ""))
1442 (define_expand "bgt"
1444 (if_then_else (gt (cc0)
1446 (label_ref (match_operand 0 "" ""))
1451 (define_expand "bgtu"
1453 (if_then_else (gtu (cc0)
1455 (label_ref (match_operand 0 "" ""))
1460 (define_expand "beq"
1462 (if_then_else (eq (cc0)
1464 (label_ref (match_operand 0 "" ""))
1469 (define_expand "bne"
1471 (if_then_else (ne (cc0)
1473 (label_ref (match_operand 0 "" ""))
1478 (define_insn "branch_true"
1480 (if_then_else (match_operator 1 "comparison_operator"
1481 [(cc0) (const_int 0)])
1482 (label_ref (match_operand 0 "" ""))
1487 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1488 && (GET_CODE (operands[1]) == GT
1489 || GET_CODE (operands[1]) == GE
1490 || GET_CODE (operands[1]) == LE
1491 || GET_CODE (operands[1]) == LT))
1493 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1497 if (get_attr_length (insn) == 2)
1498 return \"b%j1 %l0\";
1499 else if (get_attr_length (insn) == 4)
1500 return \"b%j1 %l0:16\";
1502 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1504 [(set_attr "type" "branch")
1505 (set_attr "cc" "none")])
1507 (define_insn "branch_false"
1509 (if_then_else (match_operator 1 "comparison_operator"
1510 [(cc0) (const_int 0)])
1512 (label_ref (match_operand 0 "" ""))))]
1516 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1517 && (GET_CODE (operands[1]) == GT
1518 || GET_CODE (operands[1]) == GE
1519 || GET_CODE (operands[1]) == LE
1520 || GET_CODE (operands[1]) == LT))
1522 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1526 if (get_attr_length (insn) == 2)
1527 return \"b%k1 %l0\";
1528 else if (get_attr_length (insn) == 4)
1529 return \"b%k1 %l0:16\";
1531 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1533 [(set_attr "type" "branch")
1534 (set_attr "cc" "none")])
1536 ;; Unconditional and other jump instructions.
1540 (label_ref (match_operand 0 "" "")))]
1544 if (get_attr_length (insn) == 2)
1546 else if (get_attr_length (insn) == 4)
1547 return \"bra %l0:16\";
1549 return \"jmp @%l0\";
1551 [(set_attr "type" "branch")
1552 (set_attr "cc" "none")])
1554 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1556 (define_expand "tablejump"
1557 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1558 (use (label_ref (match_operand 1 "" "")))])]
1562 (define_insn "tablejump_h8300"
1563 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1564 (use (label_ref (match_operand 1 "" "")))]
1567 [(set_attr "cc" "none")
1568 (set_attr "length" "2")])
1570 (define_insn "tablejump_h8300h"
1571 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1572 (use (label_ref (match_operand 1 "" "")))]
1573 "TARGET_H8300H || TARGET_H8300S"
1575 [(set_attr "cc" "none")
1576 (set_attr "length" "2")])
1578 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1580 (define_expand "indirect_jump"
1581 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1585 (define_insn "indirect_jump_h8300"
1586 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1589 [(set_attr "cc" "none")
1590 (set_attr "length" "2")])
1592 (define_insn "indirect_jump_h8300h"
1593 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1594 "TARGET_H8300H || TARGET_H8300S"
1596 [(set_attr "cc" "none")
1597 (set_attr "length" "2")])
1599 ;; Call subroutine with no return value.
1601 ;; ??? Even though we use HImode here, this works for the 300h.
1604 [(call (match_operand:QI 0 "call_insn_operand" "or")
1605 (match_operand:HI 1 "general_operand" "g"))]
1609 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1610 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1611 return \"jsr\\t\@%0:8\";
1613 return \"jsr\\t%0\";
1615 [(set_attr "cc" "clobber")
1616 (set (attr "length")
1617 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1621 ;; Call subroutine, returning value in operand 0
1622 ;; (which must be a hard register).
1624 ;; ??? Even though we use HImode here, this works on the 300h.
1626 (define_insn "call_value"
1627 [(set (match_operand 0 "" "=r")
1628 (call (match_operand:QI 1 "call_insn_operand" "or")
1629 (match_operand:HI 2 "general_operand" "g")))]
1633 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1634 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1635 return \"jsr\\t\@%1:8\";
1637 return \"jsr\\t%1\";
1639 [(set_attr "cc" "clobber")
1640 (set (attr "length")
1641 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1649 [(set_attr "cc" "none")
1650 (set_attr "length" "2")])
1652 ;; ----------------------------------------------------------------------
1653 ;; EXTEND INSTRUCTIONS
1654 ;; ----------------------------------------------------------------------
1656 (define_insn "zero_extendqihi2"
1657 [(set (match_operand:HI 0 "register_operand" "=r,r")
1658 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1662 mov.b %R1,%s0\;mov.b #0,%t0"
1663 [(set_attr "length" "2,4")
1664 (set_attr "cc" "clobber,clobber")])
1666 ;; The compiler can synthesize a 300H variant of this which is
1667 ;; just as efficient as one that we'd create
1668 (define_insn "zero_extendqisi2"
1669 [(set (match_operand:SI 0 "register_operand" "=r,r")
1670 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1673 mov.b #0,%x0\;sub.w %e0,%e0
1674 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1675 [(set_attr "length" "4,6")
1676 (set_attr "cc" "clobber,clobber")])
1678 (define_expand "zero_extendhisi2"
1679 [(set (match_operand:SI 0 "register_operand" "")
1680 (zero_extend:SI (match_operand:HI 1 "general_operand" "")))]
1685 && GET_CODE (operands[1]) != CONST_INT
1688 emit_insn (gen_zero_extendhisi2_h8300 (operands[0], operands[1]));
1693 ;; This is used when not optimizing. It avoids severe code explosion
1694 ;; due to poor register allocation.
1695 (define_expand "zero_extendhisi2_h8300"
1696 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1697 (set (reg:SI 0) (zero_extend:SI (reg:HI 1)))
1698 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1702 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1704 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1705 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1709 mov.w %f1,%f0\;sub.w %e0,%e0
1710 mov.w %e1,%f0\;sub.w %e0,%e0"
1711 [(set_attr "length" "2,4,4")
1712 (set_attr "cc" "clobber,clobber,clobber")])
1715 [(set (match_operand:SI 0 "register_operand" "=r,r")
1716 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1717 "TARGET_H8300H || TARGET_H8300S"
1720 mov.w %T1,%T0\;extu.l %S0"
1721 [(set_attr "length" "2,4")
1722 (set_attr "cc" "set_znv,set_znv")])
1724 (define_expand "extendqihi2"
1725 [(set (match_operand:HI 0 "register_operand" "")
1726 (sign_extend:HI (match_operand:QI 1 "general_operand" "")))]
1731 [(set (match_operand:HI 0 "register_operand" "=r,r")
1732 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1735 bld #7,%s0\;subx %t0,%t0
1736 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1737 [(set_attr "length" "4,6")
1738 (set_attr "cc" "clobber,clobber")])
1741 [(set (match_operand:HI 0 "register_operand" "=r,r")
1742 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1743 "TARGET_H8300H || TARGET_H8300S"
1746 mov.b %R1,%s0\;exts.w %T0"
1747 [(set_attr "length" "2,4")
1748 (set_attr "cc" "set_znv,set_znv")])
1750 ;; The compiler can synthesize a 300H variant of this which is
1751 ;; just as efficient as one that we'd create
1752 (define_insn "extendqisi2"
1753 [(set (match_operand:SI 0 "register_operand" "=r,r")
1754 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1757 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1758 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1759 [(set_attr "length" "8,10")
1760 (set_attr "cc" "clobber,clobber")])
1762 (define_expand "extendhisi2"
1763 [(set (match_operand:SI 0 "register_operand" "")
1764 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1769 && GET_CODE (operands[1]) != CONST_INT
1772 emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
1777 ;; This is used when not optimizing. It avoids severe code explosion
1778 ;; due to poor register allocation.
1779 (define_expand "extendhisi2_h8300"
1780 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1781 (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
1782 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1787 [(set (match_operand:SI 0 "register_operand" "=r,r")
1788 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1791 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1792 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1793 [(set_attr "length" "6,8")
1794 (set_attr "cc" "clobber,clobber")])
1797 [(set (match_operand:SI 0 "register_operand" "=r,r")
1798 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1799 "TARGET_H8300H || TARGET_H8300S"
1802 mov.w %T1,%T0\;exts.l %S0"
1803 [(set_attr "length" "2,4")
1804 (set_attr "cc" "set_znv,set_znv")])
1806 ;; ----------------------------------------------------------------------
1808 ;; ----------------------------------------------------------------------
1810 ;; We make some attempt to provide real efficient shifting. One example is
1811 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1812 ;; reg and moving 0 into the former reg.
1814 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1815 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1816 ;; give the optimizer more cracks at the code. However, we wish to do things
1817 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1818 ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
1819 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1820 ;; to detect cases it can optimize.
1822 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1823 ;; easier "do it at insn emit time" route.
1827 (define_expand "ashlqi3"
1828 [(set (match_operand:QI 0 "register_operand" "")
1829 (ashift:QI (match_operand:QI 1 "register_operand" "")
1830 (match_operand:QI 2 "nonmemory_operand" "")))]
1832 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1834 (define_expand "ashrqi3"
1835 [(set (match_operand:QI 0 "register_operand" "")
1836 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1837 (match_operand:QI 2 "nonmemory_operand" "")))]
1839 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1841 (define_expand "lshrqi3"
1842 [(set (match_operand:QI 0 "register_operand" "")
1843 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1844 (match_operand:QI 2 "nonmemory_operand" "")))]
1846 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1849 [(set (match_operand:QI 0 "register_operand" "=r,r")
1850 (match_operator:QI 3 "nshift_operator"
1851 [ (match_operand:QI 1 "register_operand" "0,0")
1852 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1853 (clobber (match_scratch:QI 4 "=X,&r"))]
1855 "* return emit_a_shift (insn, operands);"
1856 [(set_attr "length" "20")
1857 (set_attr "cc" "clobber")])
1861 (define_expand "ashlhi3"
1862 [(set (match_operand:HI 0 "register_operand" "")
1863 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1864 (match_operand:QI 2 "nonmemory_operand" "")))]
1866 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1868 (define_expand "lshrhi3"
1869 [(set (match_operand:HI 0 "register_operand" "")
1870 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1871 (match_operand:QI 2 "nonmemory_operand" "")))]
1873 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1875 (define_expand "ashrhi3"
1876 [(set (match_operand:HI 0 "register_operand" "")
1877 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1878 (match_operand:QI 2 "nonmemory_operand" "")))]
1880 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1883 [(set (match_operand:HI 0 "register_operand" "=r,r")
1884 (match_operator:HI 3 "nshift_operator"
1885 [ (match_operand:HI 1 "register_operand" "0,0")
1886 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1887 (clobber (match_scratch:QI 4 "=X,&r"))]
1889 "* return emit_a_shift (insn, operands);"
1890 [(set_attr "length" "20")
1891 (set_attr "cc" "clobber")])
1895 (define_expand "ashlsi3"
1896 [(set (match_operand:SI 0 "register_operand" "")
1898 (match_operand:SI 1 "general_operand" "")
1899 (match_operand:QI 2 "nonmemory_operand" "")))]
1901 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1903 (define_expand "lshrsi3"
1904 [(set (match_operand:SI 0 "register_operand" "")
1906 (match_operand:SI 1 "general_operand" "")
1907 (match_operand:QI 2 "nonmemory_operand" "")))]
1909 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1911 (define_expand "ashrsi3"
1912 [(set (match_operand:SI 0 "register_operand" "")
1914 (match_operand:SI 1 "general_operand" "")
1915 (match_operand:QI 2 "nonmemory_operand" "")))]
1917 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1920 [(set (match_operand:SI 0 "register_operand" "=r,r")
1921 (match_operator:SI 3 "nshift_operator"
1922 [ (match_operand:SI 1 "register_operand" "0,0")
1923 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1924 (clobber (match_scratch:QI 4 "=X,&r"))]
1926 "* return emit_a_shift (insn, operands);"
1927 [(set_attr "length" "20")
1928 (set_attr "cc" "clobber")])
1930 ;; -----------------------------------------------------------------
1932 ;; -----------------------------------------------------------------
1933 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1934 ;; instructions so let's use them as well as we can.
1936 ;; You'll never believe all these patterns perform one basic action --
1937 ;; load a bit from the source, optionally invert the bit, then store it
1938 ;; in the destination (which is known to be zero)..
1940 ;; Combine obviously need some work to better identify this situation and
1941 ;; canonicalize the form better.
1944 ;; Normal loads with a 16bit destination.
1946 ;; Yes, both cases are needed.
1949 [(set (match_operand:HI 0 "register_operand" "=&r")
1950 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1952 (match_operand:HI 2 "immediate_operand" "n")))]
1954 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1955 [(set_attr "cc" "clobber")
1956 (set_attr "length" "6")])
1959 [(set (match_operand:HI 0 "register_operand" "=&r")
1960 (subreg:HI (zero_extract:SI
1961 (match_operand:HI 1 "register_operand" "r")
1963 (match_operand:HI 2 "immediate_operand" "n")) 1))]
1965 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1966 [(set_attr "cc" "clobber")
1967 (set_attr "length" "6")])
1970 ;; Inverted loads with a 16bit destination.
1972 ;; Yes, all four cases are needed.
1976 [(set (match_operand:HI 0 "register_operand" "=&r")
1977 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1978 (match_operand:HI 3 "p_operand" "P"))
1980 (match_operand:HI 2 "const_int_operand" "n")))]
1981 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1982 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1983 [(set_attr "cc" "clobber")
1984 (set_attr "length" "8")])
1987 [(set (match_operand:HI 0 "register_operand" "=&r")
1990 (match_operand:HI 1 "bit_operand" "Ur")
1991 (match_operand:HI 2 "const_int_operand" "n")))
1994 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1995 [(set_attr "cc" "clobber")
1996 (set_attr "length" "8")])
1999 [(set (match_operand:HI 0 "register_operand" "=&r")
2003 (match_operand:SI 1 "register_operand" "Ur")
2004 (match_operand:SI 2 "const_int_operand" "n")) 1))
2006 "INTVAL (operands[2]) < 16"
2007 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2008 [(set_attr "cc" "clobber")
2009 (set_attr "length" "8")])
2012 [(set (match_operand:HI 0 "register_operand" "=&r")
2016 (match_operand:SI 1 "bit_operand" "Ur")
2017 (match_operand:SI 2 "const_int_operand" "n")) 0))
2019 "(TARGET_H8300H || TARGET_H8300S)
2020 && INTVAL (operands[2]) < 16"
2021 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2022 [(set_attr "cc" "clobber")
2023 (set_attr "length" "8")])
2026 ;; Normal loads with a 32bit destination.
2028 ;; Yes, all three cases are needed.
2031 [(set (match_operand:SI 0 "register_operand" "=&r")
2032 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2034 (match_operand:HI 2 "const_int_operand" "n")))]
2036 "* return output_simode_bld (0, 0, operands);"
2037 [(set_attr "cc" "clobber")
2038 (set (attr "length")
2039 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2045 [(set (match_operand:SI 0 "register_operand" "=&r")
2046 (and:SI (zero_extend:SI
2048 (match_operand:QI 1 "bit_operand" "Ur")
2049 (match_operand:QI 2 "const_int_operand" "n")))
2052 "* return output_simode_bld (0, 0, operands);"
2053 [(set_attr "cc" "clobber")
2054 (set (attr "length")
2055 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2061 [(set (match_operand:SI 0 "register_operand" "=&r")
2062 (and:SI (zero_extend:SI
2064 (match_operand:HI 1 "bit_operand" "Ur")
2065 (match_operand:HI 2 "const_int_operand" "n")))
2068 "* return output_simode_bld (0, 0, operands);"
2069 [(set_attr "cc" "clobber")
2070 (set (attr "length")
2071 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2077 ;; Inverted loads with a 32bit destination.
2079 ;; Yes, all seven cases are needed.
2082 [(set (match_operand:SI 0 "register_operand" "=&r")
2084 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
2085 (match_operand:SI 2 "p_operand" "P")))]
2087 "* return output_simode_bld (1, 1, operands);"
2088 [(set_attr "cc" "clobber")
2089 (set (attr "length")
2090 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2095 [(set (match_operand:SI 0 "register_operand" "=&r")
2098 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2099 (match_operand:HI 2 "const_int_operand" "n"))))
2102 "* return output_simode_bld (1, 0, operands);"
2103 [(set_attr "cc" "clobber")
2104 (set (attr "length")
2105 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2111 [(set (match_operand:SI 0 "register_operand" "=&r")
2113 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
2114 (match_operand:SI 2 "p_operand" "P")))]
2116 "* return output_simode_bld (1, 1, operands);"
2117 [(set_attr "cc" "clobber")
2118 (set (attr "length")
2119 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2124 [(set (match_operand:SI 0 "register_operand" "=&r")
2127 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2128 (match_operand:QI 2 "const_int_operand" "n"))))
2131 "* return output_simode_bld (1, 0, operands);"
2132 [(set_attr "cc" "clobber")
2133 (set (attr "length")
2134 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2140 [(set (match_operand:SI 0 "register_operand" "=&r")
2144 (match_operand:HI 1 "bit_operand" "Ur")
2145 (match_operand:HI 2 "const_int_operand" "n")) 0))
2148 "* return output_simode_bld (1, 0, operands);"
2149 [(set_attr "cc" "clobber")
2150 (set (attr "length")
2151 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2157 [(set (match_operand:SI 0 "register_operand" "=&r")
2161 (match_operand:QI 1 "bit_operand" "Ur")
2162 (match_operand:QI 2 "const_int_operand" "n")) 0))
2165 "* return output_simode_bld (1, 0, operands);"
2166 [(set_attr "cc" "clobber")
2167 (set (attr "length")
2168 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2174 [(set (match_operand:SI 0 "register_operand" "=&r")
2175 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2176 (match_operand:HI 3 "p_operand" "P"))
2178 (match_operand:HI 2 "const_int_operand" "n")))]
2179 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2180 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2181 [(set_attr "cc" "clobber")
2182 (set_attr "length" "8")])
2184 (define_expand "insv"
2185 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2186 (match_operand:HI 1 "general_operand" "")
2187 (match_operand:HI 2 "general_operand" ""))
2188 (match_operand:HI 3 "general_operand" ""))]
2192 /* We only have single bit bitfield instructions. */
2193 if (INTVAL (operands[1]) != 1)
2196 /* For now, we don't allow memory operands. */
2197 if (GET_CODE (operands[0]) == MEM
2198 || GET_CODE (operands[3]) == MEM)
2203 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2205 (match_operand:HI 1 "immediate_operand" "n"))
2206 (match_operand:HI 2 "register_operand" "r"))]
2208 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2209 [(set_attr "cc" "clobber")
2210 (set_attr "length" "4")])
2212 (define_expand "extzv"
2213 [(set (match_operand:HI 0 "register_operand" "")
2214 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2215 (match_operand:HI 2 "general_operand" "")
2216 (match_operand:HI 3 "general_operand" "")))]
2220 /* We only have single bit bitfield instructions. */
2221 if (INTVAL (operands[2]) != 1)
2224 /* For now, we don't allow memory operands. */
2225 if (GET_CODE (operands[1]) == MEM)
2229 ;; BAND, BOR, and BXOR patterns
2232 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2233 (match_operator:HI 4 "bit_operator"
2234 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2236 (match_operand:HI 2 "immediate_operand" "n"))
2237 (match_operand:HI 3 "bit_operand" "0")]))]
2239 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2240 [(set_attr "cc" "clobber")
2241 (set_attr "length" "6")
2242 (set_attr "adjust_length" "no")])
2245 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2246 (match_operator:HI 5 "bit_operator"
2247 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2249 (match_operand:HI 2 "immediate_operand" "n"))
2250 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2252 (match_operand:HI 4 "immediate_operand" "n"))]))]
2254 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2255 [(set_attr "cc" "clobber")
2256 (set_attr "length" "6")
2257 (set_attr "adjust_length" "no")])
2260 ;; ----------------------------------------------
2261 ;; Peepholes go at the end.
2262 ;; ----------------------------------------------
2264 ;; Notice a move which could be post incremented.
2267 [(set (match_operand:QI 0 "register_operand" "")
2268 (mem:QI (match_operand:HI 1 "register_operand" "")))
2269 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
2270 "REGNO(operands[1]) != REGNO(operands[0])"
2272 [(set_attr "length" "2")
2273 (set_attr "cc" "set_znv")])
2276 [(set (match_operand:HI 0 "register_operand" "")
2277 (mem:HI (match_operand:HI 1 "register_operand" "")))
2278 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
2279 "REGNO(operands[1]) != REGNO(operands[0])"
2281 [(set_attr "length" "2")
2282 (set_attr "cc" "set_znv")])
2284 ;; Notice a move which could be predecremented.
2287 [(set (match_operand:HI 1 "register_operand" "")
2288 (plus:HI (match_dup 1) (const_int -1)))
2289 (set (mem:QI (match_dup 1))
2290 (match_operand:QI 0 "register_operand" ""))]
2291 "REGNO(operands[1]) != REGNO(operands[0])"
2293 [(set_attr "length" "2")
2294 (set_attr "cc" "set_znv")])
2297 [(set (match_operand:HI 1 "register_operand" "")
2298 (plus:HI (match_dup 1) (const_int -2)))
2299 (set (mem:HI (match_dup 1))
2300 (match_operand:HI 0 "register_operand" ""))]
2301 "REGNO(operands[1]) != REGNO(operands[0])"
2303 [(set_attr "length" "2")
2304 (set_attr "cc" "set_znv")])