1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (define_attr "cpu" "h8300,h8300h"
30 (const (symbol_ref "cpu_type")))
32 ;; ??? If we can remove the operand type on all the insns, do it.
33 ;; ??? Otherwise, try to have the operand type on all the insns.
35 (define_attr "type" "branch,return,call,arith,move,float,multi"
36 (const_string "arith"))
38 ;; The size of instructions in bytes.
40 (define_attr "length" ""
41 (cond [(eq_attr "type" "branch")
42 (if_then_else (and (ge (minus (pc) (match_dup 0))
44 (le (minus (pc) (match_dup 0))
47 (if_then_else (and (eq_attr "cpu" "h8300h")
48 (and (ge (minus (pc) (match_dup 0))
50 (le (minus (pc) (match_dup 0))
54 (eq_attr "type" "move") (const_int 4)
55 (eq_attr "type" "return") (const_int 2)
56 (eq_attr "type" "float") (const_int 12)
57 (eq_attr "type" "call") (const_int 4)]
60 (define_attr "cc" "none,clobber,none_0hit,set,compare,whoops,cbit"
61 (const_string "whoops"))
63 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
69 (define_insn "movqi_push"
70 [(set (match_operand:QI 0 "push_operand" "=<")
71 (match_operand:QI 1 "register_operand" "r"))]
76 return \"push.w %T1\";
78 return \"push.l %S1\";
80 [(set_attr "type" "move")
81 (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
82 (set_attr "cc" "set")])
84 (define_insn "movqi_internal"
85 [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<,r")
86 (match_operand:QI 1 "general_operand_src" "I,r>,io,r,r,c"))]
87 "register_operand (operands[0],QImode) || register_operand (operands[1], QImode)"
94 xor %X0,%X0\;bst #0,%X0"
95 [(set_attr "type" "move")
96 (set_attr_alternative "length"
97 [(const_int 2) (const_int 2)
98 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
99 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
100 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))
102 (set_attr "cc" "set,set,set,set,set,none")])
104 (define_expand "movqi"
105 [(set (match_operand:QI 0 "general_operand_dst" "")
106 (match_operand:QI 1 "general_operand_src" ""))]
110 /* One of the ops has to be in a register */
111 if (!register_operand(operand0, QImode)
112 && !register_operand(operand1, QImode))
114 operands[1] = copy_to_mode_reg(QImode, operand1);
118 (define_insn "movstrictqi"
119 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<"))
120 (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))]
128 [(set_attr "type" "move")
129 (set_attr_alternative "length"
130 [(const_int 2) (const_int 2)
131 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
132 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
133 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
134 (set_attr "cc" "set")])
138 (define_insn "movhi_push"
139 [(set (match_operand:HI 0 "push_operand" "=<")
140 (match_operand:HI 1 "register_operand" "ra"))]
145 return \"push.w %T1\";
147 return \"push.l %S1\";
149 [(set_attr "type" "move")
150 (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
151 (set_attr "cc" "set")])
153 (define_insn "movhi_internal"
154 [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<")
155 (match_operand:HI 1 "general_operand_src" "I,ra>,ion,ra,ra"))]
163 [(set_attr "type" "move")
164 (set_attr_alternative "length"
165 [(const_int 2) (const_int 2)
166 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
167 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
168 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
169 (set_attr "cc" "set")])
171 (define_expand "movhi"
172 [(set (match_operand:HI 0 "general_operand_dst" "")
173 (match_operand:HI 1 "general_operand_src" ""))]
177 /* One of the ops has to be in a register */
178 if (!register_operand(operand1, HImode)
179 && !register_operand(operand0, HImode))
181 operands[1] = copy_to_mode_reg(HImode, operand1);
185 (define_insn "movstricthi"
186 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<"))
187 (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))]
195 [(set_attr "type" "move")
196 (set_attr_alternative "length"
197 [(const_int 2) (const_int 2)
198 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
199 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
200 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
201 (set_attr "cc" "set")])
205 (define_expand "movsi"
206 [(set (match_operand:SI 0 "general_operand_dst" "")
207 (match_operand:SI 1 "general_operand_src" ""))]
213 if (do_movsi (operands))
216 else /* TARGET_H8300H */
218 /* One of the ops has to be in a register. */
219 if (!register_operand (operand1, SImode)
220 && !register_operand (operand0, SImode))
222 operands[1] = copy_to_mode_reg (SImode, operand1);
227 (define_expand "movsf"
228 [(set (match_operand:SF 0 "general_operand_dst" "")
229 (match_operand:SF 1 "general_operand_src" ""))]
235 if (do_movsi (operands))
238 else /* TARGET_H8300H */
240 /* One of the ops has to be in a register. */
241 if (!register_operand (operand1, SFmode)
242 && !register_operand (operand0, SFmode))
244 operands[1] = copy_to_mode_reg (SFmode, operand1);
249 (define_insn "movsi_h8300"
250 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
251 (match_operand:SI 1 "general_operand_src" "I,r,ion,r,r,>"))]
253 && (register_operand (operands[0], SImode)
254 || register_operand (operands[1], SImode))"
258 switch (which_alternative)
261 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
263 if (REGNO(operands[0]) < REGNO(operands[1]))
264 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
266 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
268 /* Make sure we don't trample the register we index with. */
270 if (GET_CODE(operands[1]) == MEM)
272 rtx inside = XEXP (operands[1],0);
277 else if (GET_CODE (inside) == PLUS)
279 rtx lhs = XEXP (inside,0);
280 rtx rhs = XEXP (inside,1);
281 if (REG_P (lhs)) rn = REGNO (lhs);
282 if (REG_P (rhs)) rn = REGNO (rhs);
285 if (rn == REGNO (operands[0]))
287 /* Move the second word first. */
288 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
292 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
296 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
298 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
300 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
303 [(set_attr "type" "move")
304 (set_attr "length" "4,4,8,8,4,4")
305 (set_attr "cc" "clobber")])
307 (define_insn "movsf_h8300"
308 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
309 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
311 && (register_operand (operands[0], SFmode)
312 || register_operand (operands[1], SFmode))"
315 /* Copy of the movsi stuff */
317 switch (which_alternative)
320 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
322 if (REGNO(operands[0]) < REGNO(operands[1]))
323 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
325 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
327 /* Make sure we don't trample the register we index with. */
329 if (GET_CODE (operands[1]) == MEM)
331 rtx inside = XEXP (operands[1],0);
336 else if (GET_CODE (inside) == PLUS)
338 rtx lhs = XEXP (inside,0);
339 rtx rhs = XEXP (inside,1);
340 if (REG_P (lhs)) rn = REGNO (lhs);
341 if (REG_P (rhs)) rn = REGNO (rhs);
344 if (rn == REGNO (operands[0]))
346 /* move the second word first */
347 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
351 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
355 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
357 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
359 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
363 [(set_attr "type" "move")
364 (set_attr "length" "4,4,8,8,4,4")
365 (set_attr "cc" "clobber")])
367 (define_insn "movsi_h8300h"
368 [(set (match_operand:SI 0 "general_operand_dst" "=ra,ra,ra,o,<,ra")
369 (match_operand:SI 1 "general_operand_src" "I,ra,ion,ra,ra,>"))]
371 && (register_operand (operands[0], SImode)
372 || register_operand (operands[1], SImode))"
380 [(set_attr "type" "move")
381 (set_attr "length" "2,2,8,8,4,4")
382 (set_attr "cc" "set")])
384 (define_insn "movsf_h8300h"
385 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<")
386 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r"))]
388 && (register_operand (operands[0], SFmode)
389 || register_operand (operands[1], SFmode))"
396 [(set_attr "type" "move")
397 (set_attr "length" "2,2,8,8,4")
398 (set_attr "cc" "set")])
400 ;; ----------------------------------------------------------------------
402 ;; ----------------------------------------------------------------------
405 [(set (cc0) (match_operand:QI 0 "register_operand" "ra"))]
409 /* ??? I don't think this is right. --Jim */
410 if (cc_prev_status.flags & CC_DONE_CBIT)
411 return \"btst #0,%X0\";
413 return \"cmp.b #0,%X0\";
415 [(set_attr "type" "arith")
416 (set_attr "length" "4")
417 (set_attr "cc" "set")])
420 [(set (cc0) (match_operand:HI 0 "general_operand" "ra"))]
424 /* ??? I don't think this is right. --Jim */
425 if (cc_prev_status.flags & CC_DONE_CBIT)
426 return \"btst #0,%0l\";
428 return \"mov.w %T0,%T0\";
430 [(set_attr "type" "arith")
431 (set_attr "length" "4")
432 (set_attr "cc" "set")])
435 [(set (cc0) (match_operand:SI 0 "general_operand" "ra"))]
439 /* ??? I don't think this is right. --Jim */
440 if (cc_prev_status.flags & CC_DONE_CBIT)
441 return \"btst #0,%0l\";
443 return \"mov.l %S0,%S0\";
445 [(set_attr "type" "arith")
446 (set_attr "length" "4")
447 (set_attr "cc" "set")])
451 (compare:QI (match_operand:QI 0 "register_operand" "ra")
452 (match_operand:QI 1 "nonmemory_operand" "rai")))]
455 [(set_attr "type" "arith")
456 (set_attr "length" "2")
457 (set_attr "cc" "compare")])
459 ;; ??? 300h can have an immediate operand here.
463 (compare:HI (match_operand:HI 0 "register_operand" "ra")
464 (match_operand:HI 1 "register_operand" "ra")))]
467 [(set_attr "type" "arith")
468 (set_attr "length" "2")
469 (set_attr "cc" "compare")])
471 ;; ??? 300h can have an immediate operand here.
475 (compare:SI (match_operand:SI 0 "register_operand" "ra")
476 (match_operand:SI 1 "register_operand" "ra")))]
479 [(set_attr "type" "arith")
480 (set_attr "length" "2")
481 (set_attr "cc" "compare")])
483 ;; ----------------------------------------------------------------------
485 ;; ----------------------------------------------------------------------
487 (define_insn "addqi3"
488 [(set (match_operand:QI 0 "register_operand" "=r")
489 (plus:QI (match_operand:QI 1 "register_operand" "%0")
490 (match_operand:QI 2 "nonmemory_operand" "ri")))]
493 [(set_attr "type" "arith")
494 (set_attr "length" "2")
495 (set_attr "cc" "set")])
497 ;; ??? adds operates on the 32bit register. We can use it because we don't
498 ;; use the e0-7 registers.
499 ;; ??? 4 can be handled in one insn on the 300h.
501 (define_insn "addhi3_internal"
502 [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,ra,r,ra")
503 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
504 (match_operand:HI 2 "nonmemory_operand" "K,M,L,N,n,ra")))]
508 adds #2,%A0\;adds %C2,%A0
510 subs #2,%A0\;subs %M2,%A0
511 add.b %s2,%s0\;addx %t2,%t0
513 [(set_attr "type" "arith,multi,arith,multi,multi,arith")
514 (set_attr "length" "2,4,2,4,4,2")
515 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,set")])
517 ;; ??? Why is this here?
518 (define_expand "addhi3"
519 [(set (match_operand:HI 0 "register_operand" "")
520 (plus:HI (match_operand:HI 1 "register_operand" "")
521 (match_operand:HI 2 "nonmemory_operand" "")))]
525 (define_expand "addsi3"
526 [(set (match_operand:SI 0 "register_operand" "")
527 (plus:SI (match_operand:SI 1 "register_operand" "")
528 (match_operand:SI 2 "nonmemory_operand" "")))]
532 (define_insn "addsi_h8300"
533 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
534 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
535 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
538 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
539 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
540 mov %f1,%f0\;mov %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
541 [(set_attr "type" "arith")
542 (set_attr "length" "8,6,20")
543 (set_attr "cc" "clobber")])
545 ;; ??? 4 can be handled in one insn on the 300h.
546 ;; ??? Should the 'n' constraint be 'i' here?
547 ;; ??? We don't handle (reg + symbol_ref) which the 300h can handle.
549 (define_insn "addsi_h8300h"
550 [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,ra,r,ra")
551 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
552 (match_operand:SI 2 "nonmemory_operand" "K,M,L,N,n,ra")))]
556 adds #2,%S0\;adds %C2,%S0
558 subs #2,%S0\;subs %M2,%S0
561 [(set_attr "type" "multi,multi,multi,multi,arith,arith")
562 (set_attr "length" "2,4,2,4,6,2")
563 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,clobber")])
565 ;; ----------------------------------------------------------------------
566 ;; SUBTRACT INSTRUCTIONS
567 ;; ----------------------------------------------------------------------
569 (define_insn "subqi3"
570 [(set (match_operand:QI 0 "register_operand" "=r,r")
571 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
572 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
577 [(set_attr "type" "arith")
578 (set_attr "length" "2")
579 (set_attr "cc" "set")])
581 ;; ??? subs operates on the 32bit register. We can use it because we don't
582 ;; use the e0-7 registers.
583 ;; ??? 4 can be handled in one insn on the 300h.
584 ;; ??? The fourth alternative can use sub.w on the 300h.
585 ;; ??? Should the 'n' constraint be an 'i' here?
587 (define_insn "subhi3_internal"
588 [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r")
589 (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
590 (match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))]
594 subs #2,%T0\;subs %M2,%T0
596 add.b %E2,%s0\;addx %F2,%t0 ; -%0"
597 [(set_attr "type" "multi")
598 (set_attr "length" "2,4,2,4")
599 (set_attr "cc" "none_0hit,none_0hit,set,clobber")])
601 ;; ??? Why is this here?
602 (define_expand "subhi3"
603 [(set (match_operand:HI 0 "register_operand" "")
604 (minus:HI (match_operand:HI 1 "register_operand" "")
605 (match_operand:HI 2 "nonmemory_operand" "")))]
609 (define_expand "subsi3"
610 [(set (match_operand:SI 0 "register_operand" "")
611 (minus:SI (match_operand:SI 1 "register_operand" "")
612 (match_operand:SI 2 "nonmemory_operand" "")))]
616 (define_insn "subsi3_h8300"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (minus:SI (match_operand:SI 1 "register_operand" "0")
619 (match_operand:SI 2 "register_operand" "r")))]
621 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
622 [(set_attr "type" "arith")
623 (set_attr "length" "6")
624 (set_attr "cc" "clobber")])
626 ;; ??? 4 can be handled in one insn on the 300h.
628 (define_insn "subsi3_h8300h"
629 [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,r")
630 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
631 (match_operand:SI 2 "nonmemory_operand" "K,M,ra,n")))]
635 subs #2,%T0\;subs %E2,%T0
638 [(set_attr "type" "multi")
639 (set_attr "length" "2,4,2,6")
640 (set_attr "cc" "none_0hit,none_0hit,set,set")])
642 ;; ----------------------------------------------------------------------
643 ;; MULTIPLY INSTRUCTIONS
644 ;; ----------------------------------------------------------------------
646 ;; Note that the h8/300 can only handle umulqihi3.
648 (define_insn "mulqihi3"
649 [(set (match_operand:HI 0 "register_operand" "=r")
650 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
651 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
654 [(set_attr "type" "multi")
655 (set_attr "length" "4")
656 (set_attr "cc" "set")])
658 (define_insn "mulhisi3"
659 [(set (match_operand:SI 0 "register_operand" "=r")
660 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
661 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
664 [(set_attr "type" "multi")
665 (set_attr "length" "4")
666 (set_attr "cc" "set")])
668 (define_insn "umulqihi3"
669 [(set (match_operand:HI 0 "register_operand" "=r")
670 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
671 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
674 [(set_attr "type" "multi")
675 (set_attr "length" "2")
676 (set_attr "cc" "none_0hit")])
678 (define_insn "umulhisi3"
679 [(set (match_operand:SI 0 "register_operand" "=r")
680 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
681 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
684 [(set_attr "type" "multi")
685 (set_attr "length" "2")
686 (set_attr "cc" "none_0hit")])
688 ;; ----------------------------------------------------------------------
689 ;; DIVIDE INSTRUCTIONS
690 ;; ----------------------------------------------------------------------
692 (define_insn "udivqi3"
693 [(set (match_operand:QI 0 "register_operand" "=r")
694 (udiv:QI (match_operand:HI 1 "general_operand" "0")
695 (match_operand:QI 2 "register_operand" "r")))]
698 [(set_attr "type" "multi")
699 (set_attr "length" "2")
700 (set_attr "cc" "clobber")])
702 ;; ??? Will divxu always work here?
704 (define_insn "divqi3"
705 [(set (match_operand:QI 0 "register_operand" "=r")
706 (div:QI (match_operand:HI 1 "general_operand" "0")
707 (match_operand:QI 2 "register_operand" "r")))]
710 [(set_attr "type" "multi")
711 (set_attr "length" "2")
712 (set_attr "cc" "clobber")])
714 (define_insn "udivhi3"
715 [(set (match_operand:HI 0 "register_operand" "=r")
716 (udiv:HI (match_operand:SI 1 "general_operand" "0")
717 (match_operand:HI 2 "register_operand" "r")))]
720 [(set_attr "type" "multi")
721 (set_attr "length" "2")
722 (set_attr "cc" "clobber")])
724 (define_insn "divhi3"
725 [(set (match_operand:HI 0 "register_operand" "=r")
726 (div:HI (match_operand:SI 1 "general_operand" "0")
727 (match_operand:HI 2 "register_operand" "r")))]
730 [(set_attr "type" "multi")
731 (set_attr "length" "4")
732 (set_attr "cc" "clobber")])
734 ;; ----------------------------------------------------------------------
736 ;; ----------------------------------------------------------------------
738 (define_insn "umodqi3"
739 [(set (match_operand:QI 0 "register_operand" "=r")
740 (umod:QI (match_operand:HI 1 "general_operand" "0")
741 (match_operand:QI 2 "register_operand" "r")))]
743 "divxu %X2,%T0\;mov %t0,%s0"
744 [(set_attr "type" "multi")
745 (set_attr "length" "4")
746 (set_attr "cc" "clobber")])
748 (define_insn "modqi3"
749 [(set (match_operand:QI 0 "register_operand" "=r")
750 (mod:QI (match_operand:HI 1 "general_operand" "0")
751 (match_operand:QI 2 "register_operand" "r")))]
753 "divxs.b %X2,%T0\;mov %t0,%s0"
754 [(set_attr "type" "multi")
755 (set_attr "length" "6")
756 (set_attr "cc" "clobber")])
758 (define_insn "umodhi3"
759 [(set (match_operand:HI 0 "register_operand" "=r")
760 (umod:HI (match_operand:SI 1 "general_operand" "0")
761 (match_operand:HI 2 "register_operand" "r")))]
763 "divxu.w %T2,%S0\;mov %e0,%f0"
764 [(set_attr "type" "multi")
765 (set_attr "length" "4")
766 (set_attr "cc" "clobber")])
768 (define_insn "modhi3"
769 [(set (match_operand:HI 0 "register_operand" "=r")
770 (mod:HI (match_operand:SI 1 "general_operand" "0")
771 (match_operand:HI 2 "register_operand" "r")))]
773 "divxs.w %T2,%S0\;mov %e0,%f0"
774 [(set_attr "type" "multi")
775 (set_attr "length" "6")
776 (set_attr "cc" "clobber")])
778 ;; ----------------------------------------------------------------------
780 ;; ----------------------------------------------------------------------
782 (define_insn "andqi3_internal"
783 [(set (match_operand:QI 0 "bit_operand" "=r,U")
784 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
785 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
786 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
790 [(set_attr "type" "arith")
791 (set_attr "length" "2,4")
792 (set_attr "cc" "set,none_0hit")])
794 (define_expand "andqi3"
795 [(set (match_operand:QI 0 "bit_operand" "=r,U")
796 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
797 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
801 if (fix_bit_operand (operands, 'O', AND))
805 ;; ??? Should have a bclr case here also.
807 (define_insn "andhi3"
808 [(set (match_operand:HI 0 "register_operand" "=r")
809 (and:HI (match_operand:HI 1 "register_operand" "%0")
810 (match_operand:HI 2 "nonmemory_operand" "ri")))]
814 if (GET_CODE (operands[2]) == CONST_INT)
816 int i = INTVAL (operands[2]);
817 if ((i & 0x00ff) != 0x00ff)
818 output_asm_insn (\"and %s2,%s0\", operands);
819 if ((i & 0xff00) != 0xff00)
820 output_asm_insn (\"and %t2,%t0\", operands);
823 return \"and %s2,%s0\;and %t2,%t0;\";
825 [(set_attr "type" "multi")
826 (set_attr "length" "4")
827 (set_attr "cc" "clobber")])
829 ;; ??? There is an iorsi3 for TARGET_H8300. Should we have andsi3?
831 (define_insn "andsi3"
832 [(set (match_operand:SI 0 "register_operand" "=r,r")
833 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
834 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
839 [(set_attr "type" "arith")
840 (set_attr "length" "4,6")
841 (set_attr "cc" "clobber")])
843 ;; ----------------------------------------------------------------------
845 ;; ----------------------------------------------------------------------
847 (define_insn "iorqi3_internal"
848 [(set (match_operand:QI 0 "bit_operand" "=U,r")
849 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
850 (match_operand:QI 2 "nonmemory_operand" "P,rn")))]
851 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
855 [(set_attr "type" "arith")
856 (set_attr "length" "4,2")
857 (set_attr "cc" "none_0hit,set")])
859 (define_expand "iorqi3"
860 [(set (match_operand:QI 0 "bit_operand" "=r,U")
861 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
862 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
866 if (fix_bit_operand (operands, 'P', IOR))
870 ;; ??? Should have a bset case here also.
872 (define_insn "iorhi3"
873 [(set (match_operand:HI 0 "general_operand" "=r,r")
874 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
875 (match_operand:HI 2 "general_operand" "J,ri")))]
881 if (GET_CODE (operands[2]) == CONST_INT)
883 int i = INTVAL (operands[2]);
884 if ((i & 0x00ff) != 0)
885 output_asm_insn (\"or %s2,%s0\", operands);
886 if ((i & 0xff00) != 0)
887 output_asm_insn (\"or %t2,%t0\", operands);
890 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
894 return \"or %S2,%S0\";
897 [(set_attr "type" "multi")
898 (set_attr "length" "2,4")
899 (set_attr "cc" "clobber,clobber")])
901 (define_insn "iorsi3"
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (ior:SI (match_operand:SI 1 "register_operand" "%0")
904 (match_operand:SI 2 "nonmemory_operand" "ri")))]
910 if (GET_CODE (operands[2]) == CONST_INT)
912 int i = INTVAL (operands[2]);
913 if ((i & 0x000000ff) != 0)
914 output_asm_insn (\"or %w2,%w0\", operands);
915 if ((i & 0x0000ff00) != 0)
916 output_asm_insn (\"or %x2,%x0\", operands);
917 if ((i & 0x00ff0000) != 0)
918 output_asm_insn (\"or %y2,%y0\", operands);
919 if ((i & 0xff000000) != 0)
920 output_asm_insn (\"or %z2,%z0\", operands);
923 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
927 return \"or %S2,%S0\";
930 [(set_attr "type" "multi")
931 (set_attr "length" "8")
932 (set_attr "cc" "clobber")])
934 ;; ----------------------------------------------------------------------
936 ;; ----------------------------------------------------------------------
938 (define_insn "xorqi3_internal"
939 [(set (match_operand:QI 0 "bit_operand" "=r,U")
940 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
941 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
942 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
946 [(set_attr "type" "arith")
947 (set_attr "length" "2,4")
948 (set_attr "cc" "set,none_0hit")])
950 (define_expand "xorqi3"
951 [(set (match_operand:QI 0 "bit_operand" "=r,U")
952 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
953 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
957 if (fix_bit_operand (operands, 'O', XOR))
961 (define_insn "xorhi3"
962 [(set (match_operand:HI 0 "register_operand" "=r")
963 (xor:HI (match_operand:HI 1 "general_operand" "%0")
964 (match_operand:HI 2 "nonmemory_operand" "ri")))]
969 return \"xor %s2,%s0\;xor %t2,%t0\";
971 return \"xor %S2,%S0\";
973 [(set_attr "type" "multi")
974 (set_attr "length" "4")
975 (set_attr "cc" "clobber")])
977 ;; ??? There is an iorsi3 for TARGET_H8300. Should we have xorsi3?
979 (define_insn "xorsi3"
980 [(set (match_operand:SI 0 "register_operand" "=r,r")
981 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
982 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
987 [(set_attr "type" "arith")
988 (set_attr "length" "4,6")
989 (set_attr "cc" "clobber")])
991 ;; ----------------------------------------------------------------------
992 ;; NEGATION INSTRUCTIONS
993 ;; ----------------------------------------------------------------------
995 (define_insn "negqi2"
996 [(set (match_operand:QI 0 "register_operand" "=r")
997 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1000 [(set_attr "type" "arith")
1001 (set_attr "length" "2")
1002 (set_attr "cc" "clobber")])
1004 (define_expand "neghi2"
1005 [(set (match_operand:HI 0 "register_operand" "=r")
1006 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1012 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1017 (define_expand "neghi2_h8300"
1019 (not:HI (match_operand:HI 1 "register_operand" "r")))
1020 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1021 (set (match_operand:HI 0 "register_operand" "=r")
1024 "{ operands[2] = gen_reg_rtx (HImode); }")
1026 (define_insn "neghi2_h8300h"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1031 [(set_attr "type" "arith")
1032 (set_attr "length" "2")
1033 (set_attr "cc" "clobber")])
1035 (define_expand "negsi2"
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1043 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1048 (define_expand "negsi2_h8300"
1050 (not:SI (match_operand:SI 1 "register_operand" "r")))
1051 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1052 (set (match_operand:SI 0 "register_operand" "=r")
1055 "{ operands[2] = gen_reg_rtx(SImode); }")
1057 (define_insn "negsi2_h8300h"
1058 [(set (match_operand:SI 0 "register_operand" "=r")
1059 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1062 [(set_attr "type" "arith")
1063 (set_attr "length" "2")
1064 (set_attr "cc" "clobber")])
1066 ;; ----------------------------------------------------------------------
1068 ;; ----------------------------------------------------------------------
1070 (define_insn "one_cmplqi2"
1071 [(set (match_operand:QI 0 "register_operand" "=r")
1072 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1075 [(set_attr "type" "arith")
1076 (set_attr "length" "2")
1077 (set_attr "cc" "set")])
1079 (define_insn "one_cmplhi2"
1080 [(set (match_operand:HI 0 "register_operand" "=r")
1081 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1086 return \"not %s0\;not %t0\";
1090 [(set_attr "type" "arith")
1091 (set_attr "length" "4")
1092 (set_attr "cc" "clobber")])
1094 (define_insn "one_cmplsi2"
1095 [(set (match_operand:SI 0 "register_operand" "=r")
1096 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1101 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1105 [(set_attr "type" "arith")
1106 ;; ??? length is wrong for 300h
1107 (set_attr "length" "8")
1108 (set_attr "cc" "clobber")])
1110 ;; ----------------------------------------------------------------------
1111 ;; JUMP INSTRUCTIONS
1112 ;; ----------------------------------------------------------------------
1114 ;; Conditional jump instructions
1116 (define_expand "ble"
1118 (if_then_else (le (cc0)
1120 (label_ref (match_operand 0 "" ""))
1125 (define_expand "bleu"
1127 (if_then_else (leu (cc0)
1129 (label_ref (match_operand 0 "" ""))
1134 (define_expand "bge"
1136 (if_then_else (ge (cc0)
1138 (label_ref (match_operand 0 "" ""))
1143 (define_expand "bgeu"
1145 (if_then_else (geu (cc0)
1147 (label_ref (match_operand 0 "" ""))
1152 (define_expand "blt"
1154 (if_then_else (lt (cc0)
1156 (label_ref (match_operand 0 "" ""))
1161 (define_expand "bltu"
1163 (if_then_else (ltu (cc0)
1165 (label_ref (match_operand 0 "" ""))
1170 (define_expand "bgt"
1172 (if_then_else (gt (cc0)
1174 (label_ref (match_operand 0 "" ""))
1179 (define_expand "bgtu"
1181 (if_then_else (gtu (cc0)
1183 (label_ref (match_operand 0 "" ""))
1188 (define_expand "beq"
1190 (if_then_else (eq (cc0)
1192 (label_ref (match_operand 0 "" ""))
1197 (define_expand "bne"
1199 (if_then_else (ne (cc0)
1201 (label_ref (match_operand 0 "" ""))
1206 (define_insn "branch_true"
1208 (if_then_else (match_operator 1 "comparison_operator"
1209 [(cc0) (const_int 0)])
1210 (label_ref (match_operand 0 "" ""))
1215 if (get_attr_length (insn) == 2)
1216 return \"b%j1 %l0\";
1217 else if (get_attr_length (insn) == 4)
1218 return \"b%j1 %l0:16\";
1220 return \"b%k1 %L0\;jmp @%l0\;%L0:\";
1222 [(set_attr "type" "branch")
1223 (set_attr "cc" "none")])
1225 (define_insn "branch_false"
1227 (if_then_else (match_operator 1 "comparison_operator"
1228 [(cc0) (const_int 0)])
1230 (label_ref (match_operand 0 "" ""))))]
1232 ;; ??? We don't take advantage of 16 bit relative jumps in the 300h.
1235 if (get_attr_length (insn) == 2)
1236 return \"b%k1 %l0\";
1237 else if (get_attr_length (insn) == 4)
1238 return \"b%k1 %l0:16\";
1240 return \"b%j1 %L0\;jmp @%l0\;%L0:\";
1242 [(set_attr "type" "branch")
1243 (set_attr "cc" "none")])
1245 ;; Unconditional and other jump instructions.
1249 (label_ref (match_operand 0 "" "")))]
1253 if (get_attr_length (insn) == 2)
1255 else if (get_attr_length (insn) == 4)
1256 return \"bra %l0:16\";
1258 return \"jmp @%l0\";
1260 [(set_attr "type" "branch")
1261 (set_attr "cc" "none")])
1263 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1265 (define_expand "tablejump"
1266 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1267 (use (label_ref (match_operand 1 "" "")))])]
1271 (define_insn "tablejump_h8300"
1272 [(set (pc) (match_operand:HI 0 "register_operand" ""))
1273 (use (label_ref (match_operand 1 "" "")))]
1276 [(set_attr "type" "branch")
1277 (set_attr "cc" "none")
1278 (set_attr "length" "2")])
1280 (define_insn "tablejump_h8300h"
1281 [(set (pc) (match_operand:SI 0 "register_operand" ""))
1282 (use (label_ref (match_operand 1 "" "")))]
1285 [(set_attr "type" "branch")
1286 (set_attr "cc" "none")
1287 (set_attr "length" "2")])
1289 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1291 ;(define_insn "indirect_jump"
1292 ; [(set (pc) (match_operand:HI 0 "register_operand" "r"))]
1295 ; [(set_attr "type" "branch")
1296 ; (set_attr "cc" "none")
1297 ; (set_attr "length" "2")])
1299 (define_expand "indirect_jump"
1300 [(set (pc) (match_operand 0 "jump_address_operand" "Vr"))]
1304 (define_insn "indirect_jump_h8300"
1305 [(set (pc) (match_operand:HI 0 "jump_address_operand" "V,r"))]
1310 [(set_attr "type" "branch")
1311 (set_attr "cc" "none")
1312 (set_attr "length" "2")])
1314 (define_insn "indirect_jump_h8300h"
1315 [(set (pc) (match_operand:SI 0 "jump_address_operand" "V,r"))]
1320 [(set_attr "type" "branch")
1321 (set_attr "cc" "none")
1322 (set_attr "length" "2")])
1324 ;; Call subroutine with no return value.
1326 ;; ??? Even though we use HImode here, this works for the 300h.
1329 [(call (match_operand:QI 0 "call_insn_operand" "or")
1330 (match_operand:HI 1 "general_operand" "g"))]
1333 [(set_attr "type" "call")
1334 (set_attr "cc" "clobber")
1335 (set_attr "length" "4")])
1337 ;; Call subroutine, returning value in operand 0
1338 ;; (which must be a hard register).
1340 ;; ??? Even though we use HImode here, this works on the 300h.
1342 (define_insn "call_value"
1343 [(set (match_operand 0 "" "=r")
1344 (call (match_operand:QI 1 "call_insn_operand" "or")
1345 (match_operand:HI 2 "general_operand" "g")))]
1348 [(set_attr "type" "call")
1349 (set_attr "cc" "clobber")
1350 (set_attr "length" "4")])
1356 [(set_attr "type" "multi")
1357 (set_attr "cc" "none")
1358 (set_attr "length" "2")])
1360 ;; ----------------------------------------------------------------------
1361 ;; EXTEND INSTRUCTIONS
1362 ;; ----------------------------------------------------------------------
1364 (define_insn "zero_extendqihi2"
1365 [(set (match_operand:HI 0 "register_operand" "=r,r")
1366 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,g")))]
1370 if (which_alternative==0)
1371 return \"mov.b #0,%t0\";
1374 return \"mov.b %X1,%s0\;mov.b #0,%t0\";
1377 /* ??? See how often this gets optimized. */
1378 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1379 return \"extu.w %T0\";
1381 return \"mov.b %X1,%s0\;extu.w %T0\";
1384 [(set_attr "type" "multi")
1385 ;; ??? This length is wrong for one case.
1386 (set_attr "length" "4")
1387 (set_attr "cc" "clobber")])
1389 (define_insn "zero_extendhisi2"
1390 [(set (match_operand:SI 0 "register_operand" "=r")
1391 (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
1395 /* ??? See how often this gets optimized. */
1396 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1397 return \"extu.l %S0\";
1399 return \"mov.w %T1,%T0\;extu.l %S0\";
1401 [(set_attr "type" "multi")
1402 ;; ??? This length is wrong for one case.
1403 (set_attr "length" "4")
1404 (set_attr "cc" "clobber")])
1406 (define_insn "extendqihi2"
1407 [(set (match_operand:HI 0 "register_operand" "=r")
1408 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1414 /* ??? See how often this gets optimized. */
1415 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1416 return \"bld #7,%s0\;subx %t0,%t0\";
1418 return \"mov.b %X1,%s0\;bld #7,%s0\;subx %t0,%t0\";
1422 /* ??? See how often this gets optimized. */
1423 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1424 return \"exts.w %T0\";
1426 return \"mov.b %X1,%s0\;exts.w %T0\";
1429 [(set_attr "type" "multi")
1430 ;; ??? Length is wrong in some cases.
1431 (set_attr "length" "6")
1432 (set_attr "cc" "clobber")])
1434 (define_expand "extendhisi2"
1435 [(set (match_operand:SI 0 "register_operand" "")
1436 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1441 emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
1443 emit_insn (gen_extendhisi2_h8300h (operands[0], operands[1]));
1447 (define_expand "extendhisi2_h8300"
1448 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1449 (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
1450 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1454 (define_expand "extendhisi2_h8300h"
1455 [(set (match_operand:SI 0 "register_operand" "")
1456 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1460 (define_insn "extendhisi2_h8300_internal"
1461 [(set (match_operand:SI 0 "register_operand" "=r")
1462 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1464 "mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1465 [(set_attr "length" "10")
1466 (set_attr "cc" "clobber")])
1468 (define_insn "extendhisi2_h8300h_internal"
1469 [(set (match_operand:SI 0 "register_operand" "=r")
1470 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
1474 /* ??? See how often this gets optimized. */
1475 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1476 return \"exts.l %S0\";
1478 return \"mov.w %T1,%T0\;exts.l %S0\";
1480 [(set_attr "length" "10")
1481 (set_attr "cc" "clobber")])
1483 ;; ----------------------------------------------------------------------
1485 ;; ----------------------------------------------------------------------
1487 ;; We make some attempt to provide real efficient shifting. One example is
1488 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1489 ;; reg and moving 0 into the former reg.
1491 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1492 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1493 ;; give the optimizer more cracks at the code. However, we wish to do things
1494 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1495 ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
1496 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1497 ;; to detect cases it can optimize.
1499 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1500 ;; easier "do it at insn emit time" route.
1504 (define_expand "ashlqi3"
1505 [(set (match_operand:QI 0 "register_operand" "")
1506 (ashift:QI (match_operand:QI 1 "register_operand" "")
1507 (match_operand:QI 2 "nonmemory_operand" "")))]
1509 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1511 (define_expand "ashrqi3"
1512 [(set (match_operand:QI 0 "register_operand" "")
1513 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1514 (match_operand:QI 2 "nonmemory_operand" "")))]
1516 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1518 (define_expand "lshrqi3"
1519 [(set (match_operand:QI 0 "register_operand" "")
1520 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1521 (match_operand:QI 2 "nonmemory_operand" "")))]
1523 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1525 ;; WARNING: The constraints on the scratch register say one is not needed
1526 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1528 (define_insn "shiftbyn_QI"
1529 [(set (match_operand:QI 0 "register_operand" "=r,r")
1530 (match_operator:QI 3 "nshift_operator"
1531 [ (match_operand:QI 1 "register_operand" "0,0")
1532 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1533 (clobber (match_scratch:QI 4 "=X,&r"))]
1535 "* return emit_a_shift (insn, operands);"
1536 [(set_attr "type" "arith")
1537 (set_attr "length" "20")
1538 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1539 ;; However, for cases that loop or are done in pieces, cc does not contain
1540 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1541 (set_attr "cc" "clobber")])
1545 (define_expand "ashlhi3"
1546 [(set (match_operand:HI 0 "register_operand" "")
1547 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1548 (match_operand:QI 2 "nonmemory_operand" "")))]
1550 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1552 (define_expand "lshrhi3"
1553 [(set (match_operand:HI 0 "register_operand" "")
1554 (lshiftrt:HI (match_operand:HI 1 "general_operand_src" "")
1555 (match_operand:QI 2 "nonmemory_operand" "")))]
1557 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1559 (define_expand "ashrhi3"
1560 [(set (match_operand:HI 0 "register_operand" "")
1561 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1562 (match_operand:QI 2 "nonmemory_operand" "")))]
1564 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1566 ;; WARNING: The constraints on the scratch register say one is not needed
1567 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1569 (define_insn "shiftbyn_HI"
1570 [(set (match_operand:HI 0 "register_operand" "=r,r")
1571 (match_operator:HI 3 "nshift_operator"
1572 [ (match_operand:HI 1 "register_operand" "0,0")
1573 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1574 (clobber (match_scratch:QI 4 "=X,&r"))]
1576 "* return emit_a_shift (insn, operands);"
1577 [(set_attr "type" "arith")
1578 (set_attr "length" "20")
1579 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1580 ;; However, for cases that loop or are done in pieces, cc does not contain
1581 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1582 (set_attr "cc" "clobber")])
1586 (define_expand "ashlsi3"
1587 [(set (match_operand:SI 0 "register_operand" "")
1589 (match_operand:SI 1 "general_operand_src" "")
1590 (match_operand:QI 2 "nonmemory_operand" "")))]
1592 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1594 (define_expand "lshrsi3"
1595 [(set (match_operand:SI 0 "register_operand" "")
1597 (match_operand:SI 1 "general_operand_src" "")
1598 (match_operand:QI 2 "nonmemory_operand" "")))]
1600 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1602 (define_expand "ashrsi3"
1603 [(set (match_operand:SI 0 "register_operand" "")
1605 (match_operand:SI 1 "general_operand_src" "")
1606 (match_operand:QI 2 "nonmemory_operand" "")))]
1608 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1610 ;; WARNING: The constraints on the scratch register say one is not needed
1611 ;; for constant shifts of 1,2. Emit_a_shift() must know this.
1613 (define_insn "shiftbyn_SI"
1614 [(set (match_operand:SI 0 "register_operand" "=r,r")
1615 (match_operator:SI 3 "nshift_operator"
1616 [ (match_operand:SI 1 "register_operand" "0,0")
1617 (match_operand:QI 2 "nonmemory_operand" "IK,rn")]))
1618 (clobber (match_scratch:QI 4 "=X,&r"))]
1620 "* return emit_a_shift (insn, operands);"
1621 [(set_attr "type" "arith")
1622 (set_attr "length" "20")
1623 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1624 ;; However, for cases that loop or are done in pieces, cc does not contain
1625 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1626 (set_attr "cc" "clobber")])
1628 ;; -----------------------------------------------------------------
1630 ;; -----------------------------------------------------------------
1631 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1632 ;; instuctions so let's use them as well as we can
1634 ;; BCC and BCS patterns.
1636 (define_insn "bcs_qiqi"
1639 (match_operator 1 "eq_operator"
1640 [(zero_extract:QI (match_operand:QI 2 "bit_operand" "Ur")
1642 (match_operand:HI 3 "immediate_operand" "i"))
1644 (label_ref (match_operand 0 "" ""))
1649 output_asm_insn(\"bld %Z3,%Y2\", operands);
1650 if (get_attr_length (insn) == 2)
1651 return \"b%d1 %l0\";
1652 else if (get_attr_length (insn) == 4)
1653 return \"b%d1 %l0:16\";
1655 return \"b%g1 %L0\;jmp @%l0\;%L0:\";
1657 [(set_attr "type" "branch")
1658 (set_attr "cc" "clobber")])
1660 (define_insn "bcs_hihi"
1663 (match_operator 1 "eq_operator"
1664 [(zero_extract:HI (match_operand:HI 2 "bit_operand" "Ur")
1666 (match_operand:HI 3 "immediate_operand" "i"))
1668 (label_ref (match_operand 0 "" ""))
1673 output_asm_insn(\"bld %Z3,%Y2\", operands);
1674 if (get_attr_length (insn) == 2)
1676 else if (get_attr_length (insn) == 4)
1677 return \"%d1 %l0:16\";
1679 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1681 [(set_attr "type" "branch")
1682 (set_attr "cc" "clobber")])
1684 (define_insn "bcs_hiqi"
1687 (match_operator 1 "eq_operator"
1688 [(zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur")
1690 (match_operand:HI 3 "immediate_operand" "i"))
1692 (label_ref (match_operand 0 "" ""))
1697 output_asm_insn(\"bld %Z3,%Y2\", operands);
1698 if (get_attr_length (insn) == 2)
1700 else if (get_attr_length (insn) == 4)
1701 return \"%d1 %l0:16\";
1703 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1705 [(set_attr "type" "branch")
1706 (set_attr "cc" "clobber")])
1708 ;; BLD and BST patterns
1710 (define_insn "extract_1"
1711 [(set (match_operand:HI 0 "register_operand" "=&r")
1712 (zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1714 (match_operand:HI 2 "immediate_operand" "i")))]
1716 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0")
1718 (define_insn "extract_1_hi"
1719 [(set (match_operand:HI 0 "register_operand" "=&r")
1720 (zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1722 (match_operand:HI 2 "immediate_operand" "i")))]
1724 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0")
1726 (define_insn "insert_1"
1727 [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "+Ur")
1729 (match_operand:HI 1 "immediate_operand" "i"))
1730 (zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur")
1734 "bld #0,%X2\;bst %Z1,%Y0 ; i1")
1736 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1737 ;; in combine.c, but there is no problem with writing it this way so we do.
1738 (define_insn "extract_insert_1"
1739 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur")
1741 (match_operand:HI 1 "immediate_operand" "i"))
1742 (lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur")
1743 (match_operand:HI 3 "immediate_operand" "i")))]
1745 "bld %Z3,%Y2\;bst %Z1,%Y0; ei1")
1747 ;; BAND, BOR, and BXOR patterns
1749 (define_insn "bitlogical_1"
1750 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1751 (match_operator:HI 4 "bit_operator"
1752 [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1754 (match_operand:HI 2 "immediate_operand" "i"))
1755 (match_operand:HI 3 "bit_operand" "0")]))]
1757 "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl1")
1759 (define_insn "bitlogical_1_hi"
1760 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1761 (match_operator:HI 4 "bit_operator"
1762 [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1764 (match_operand:HI 2 "immediate_operand" "i"))
1765 (match_operand:HI 3 "bit_operand" "0")]))]
1767 "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl2")
1769 (define_insn "bitlogical_2"
1770 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1771 (match_operator:HI 5 "bit_operator"
1772 [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1774 (match_operand:HI 2 "immediate_operand" "i"))
1775 (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur")
1777 (match_operand:HI 4 "immediate_operand" "i"))]))]
1779 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3")
1781 (define_insn "bitlogical_2_hi"
1782 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1783 (match_operator:HI 5 "bit_operator"
1784 [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1786 (match_operand:HI 2 "immediate_operand" "i"))
1787 (zero_extract:HI (match_operand:HI 3 "bit_operand" "Ur")
1789 (match_operand:HI 4 "immediate_operand" "i"))]))]
1791 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3")
1793 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1794 ;; in combine.c, but there is no problem with writing it this way so we do.
1795 (define_insn "bitlogical_3"
1796 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur")
1798 (match_operand:HI 1 "immediate_operand" "i"))
1799 (match_operator:QI 6 "bit_operator"
1800 [(lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur")
1801 (match_operand:HI 3 "immediate_operand" "i"))
1802 (lshiftrt:QI (match_operand:QI 4 "bit_operand" "Ur")
1803 (match_operand:HI 5 "immediate_operand" "i"))]))]
1805 "bld %Z3,%Y2\;%b6 %Z5,%Y4\;bst %Z1,%Y0; bl5")
1807 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1808 ;; in combine.c, but there is no problem with writing it this way so we do.
1809 (define_insn "bitnot_1"
1810 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=Ur")
1812 (match_operand:HI 1 "immediate_operand" "i"))
1813 (lshiftrt:QI (xor:QI (match_operand:QI 2 "bit_operand" "0")
1814 (match_operand:HI 3 "immediate_operand" "i"))
1815 (match_operand:HI 4 "immediate_operand" "1")))]
1816 "GET_CODE (operands[3]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
1817 && exact_log2 (INTVAL (operands[3])) == INTVAL (operands[1])"
1820 ;; ??? Implement BIAND, BIOR, BIXOR
1822 ;; ??? Implement BILD, BIST
1824 ;; ??? Apparently general_operand for the 1st and 2nd operands is useful,
1825 ;; but I don't know why. --Jim
1827 (define_expand "insv"
1828 [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "Ur")
1829 (match_operand:HI 1 "general_operand" "g")
1830 (match_operand:HI 2 "general_operand" "g"))
1831 (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur")
1834 ;; ??? This should have word mode which is SImode for the h8/300h.
1838 if (INTVAL (operands[1]) != 1)
1842 This INSV pattern is wrong. It should use HImode for operand 3.
1843 Also, the zero_extract around operand 3 is superfluous and should be
1844 deleted. Fixing this is more work than we care to do for the moment,
1845 because it means most of the above patterns would need to be rewritten,
1846 and we also need more combine.c patches to make this work.
1848 So, for now, we work around this bug by simply not accepting any bitfield
1849 inserts that have a position greater than fits in QImode. */
1851 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 8)
1854 /* The bit_operand predicate accepts any memory durint RTL generation, but
1855 only 'U' memory afterwards, so if this is a MEM operand, we must force
1856 it to be valid for 'U' by reloading the address. */
1858 if (GET_CODE (operands[0]) == MEM && ! EXTRA_CONSTRAINT (operands[0], 'U'))
1861 mem = gen_rtx (MEM, GET_MODE (operands[0]),
1862 copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
1863 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]);
1864 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[0]);
1865 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[0]);
1869 /* Likewise for operands[3]. */
1871 if (GET_CODE (operands[3]) == MEM && ! EXTRA_CONSTRAINT (operands[3], 'U'))
1874 mem = gen_rtx (MEM, GET_MODE (operands[3]),
1875 copy_to_mode_reg (Pmode, XEXP (operands[3], 0)));
1876 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[3]);
1877 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[3]);
1878 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[3]);
1883 ;; ??? Apparently general_operand for the 2nd and 3rd operands is useful,
1884 ;; but I don't know why. --Jim
1886 (define_expand "extzv"
1887 [(set (match_operand:HI 0 "register_operand" "")
1888 (zero_extract:HI (match_operand:QI 1 "bit_operand" "")
1889 (match_operand:HI 2 "general_operand" "g")
1890 (match_operand:HI 3 "general_operand" "g")))]
1891 ;; ??? This should have word mode which is SImode for the h8/300h.
1895 if (INTVAL (operands[2]) != 1)
1898 /* The bit_operand predicate accepts any memory durint RTL generation, but
1899 only 'U' memory afterwards, so if this is a MEM operand, we must force
1900 it to be valid for 'U' by reloading the address. */
1902 if (GET_CODE (operands[1]) == MEM && ! EXTRA_CONSTRAINT (operands[1], 'U'))
1905 mem = gen_rtx (MEM, GET_MODE (operands[1]),
1906 copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
1907 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]);
1908 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[1]);
1909 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[1]);
1914 ;; -----------------------------------------------------------------
1915 ;; STACK POINTER MANIPULATIONS
1916 ;; -----------------------------------------------------------------
1918 ;; This pattern is needed because there is no way on the H8/300
1919 ;; to add a 16 bit immediate value to the stack pointer in one
1920 ;; instruction, which could leave an invalid instruction if interrupted
1921 ;; half way through. Here we add to the stack pointer from a
1924 (define_insn "stack_pointer_manip"
1925 [(set (match_operand:HI 0 "register_operand" "=&ra")
1926 (plus:HI (match_operand:HI 1 "general_operand_src" "g")
1927 (match_operand:HI 2 "register_operand" "ra")))]
1929 "mov.w %T1,%T0\;add.w %T2,%T0"
1930 [(set_attr "type" "arith")
1931 (set_attr "length" "6")
1932 (set_attr "cc" "set")])
1935 ;; -------------------------------------------
1937 ;; -------------------------------------------
1939 (define_expand "movstrhi"
1940 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
1941 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
1942 (use (match_operand:HI 2 "general_operand" ""))
1943 (use (match_operand:HI 3 "immediate_operand" ""))
1944 (clobber (match_dup 3))
1949 rtx src_ptr = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
1950 rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP(operands[0], 0));
1952 int max = GET_CODE (operands[2]) == CONST_INT
1953 ? MIN (INTVAL (operands[2]), INTVAL (operands[3])) : 1;
1954 enum machine_mode mode = max >= 2 ? HImode : QImode;
1955 rtx tmpreg = gen_reg_rtx (mode);
1956 rtx increment = mode == QImode ? const1_rtx : const2_rtx;
1957 rtx length = operands[2];
1958 rtx label = gen_label_rtx ();
1959 rtx end_src_ptr = gen_reg_rtx (Pmode);
1961 /* emit_move_insn (length, gen_rtx(MINUS, HImode, length, increment));*/
1963 if (Pmode == HImode)
1964 emit_insn (gen_addhi3 (end_src_ptr, src_ptr, length));
1966 emit_insn (gen_addsi3 (end_src_ptr, src_ptr, length));
1969 emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr));
1970 emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg);
1971 emit_insn (gen_rtx (SET, VOIDmode, src_ptr,
1972 gen_rtx (PLUS, Pmode, src_ptr, increment)));
1973 emit_insn (gen_rtx (SET, VOIDmode, dst_ptr,
1974 gen_rtx (PLUS, Pmode, dst_ptr, increment)));
1976 emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx,
1977 gen_rtx (COMPARE, Pmode, src_ptr, end_src_ptr)));
1978 emit_jump_insn (gen_bne (label));
1983 ;; ----------------------------------------------
1984 ;; Peepholes go at the end.
1985 ;; ----------------------------------------------
1987 ;; Notice when two byte moves in a row could be a word move.
1990 [(set (match_operand:QI 0 "register_operand" "=r")
1991 (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra")
1992 (match_operand:HI 2 "immediate_operand" "n"))))
1993 (set (match_operand:QI 3 "register_operand" "=r")
1994 (mem:QI (plus:HI (match_dup 1)
1995 (match_operand:HI 4 "immediate_operand" "n"))))]
1996 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
1997 "mov.w @(%u4,%T1),%T0"
1998 [(set_attr "length" "6")
1999 (set_attr "cc" "set")])
2002 [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra")
2003 (match_operand:HI 2 "immediate_operand" "n")))
2004 (match_operand:QI 0 "register_operand" "r"))
2005 (set (mem:QI (plus:HI (match_dup 1)
2006 (match_operand:HI 4 "immediate_operand" "n")))
2007 (match_operand:QI 3 "register_operand" "r"))]
2008 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
2009 "mov.w %T0,@(%u4,%T1)"
2010 [(set_attr "length" "6")
2011 (set_attr "cc" "set")])
2013 ;; Notice a move which could be post incremented.
2016 [(set (match_operand:QI 0 "register_operand" "")
2017 (mem:QI (match_operand:HI 1 "register_operand" "")))
2018 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
2019 "REGNO(operands[1]) != REGNO(operands[0])"
2021 [(set_attr "length" "2")
2022 (set_attr "cc" "set")])
2025 [(set (match_operand:HI 0 "register_operand" "")
2026 (mem:HI (match_operand:HI 1 "register_operand" "")))
2027 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
2028 "REGNO(operands[1]) != REGNO(operands[0])"
2030 [(set_attr "length" "2")
2031 (set_attr "cc" "set")])
2033 ;; Notice a move which could be predecremented.
2036 [(set (match_operand:HI 1 "register_operand" "")
2037 (plus:HI (match_dup 1) (const_int -1)))
2038 (set (mem:QI (match_dup 1))
2039 (match_operand:QI 0 "register_operand" ""))]
2040 "REGNO(operands[1]) != REGNO(operands[0])"
2042 [(set_attr "length" "2")
2043 (set_attr "cc" "set")])
2046 [(set (match_operand:HI 1 "register_operand" "")
2047 (plus:HI (match_dup 1) (const_int -1)))
2048 (set (mem:HI (match_dup 1))
2049 (match_operand:HI 0 "register_operand" ""))]
2050 "REGNO(operands[1]) != REGNO(operands[0])"
2052 [(set_attr "length" "2")
2053 (set_attr "cc" "set")])
2056 ; [(set (match_operand:HI 0 "register_operand" "=r")
2057 ; (MEM:HI (match_operand:HI 1 "register_operand" "r")))
2058 ; (set (match_operand:HI 3 "register_operand" "=r")
2059 ; (zero_extract:HI (match_dup 0)
2061 ; (match_operand:HI 2 "general_operand" "g")))
2062 ; (set (MEM:HI (match_dup 1) (match_dup 3)))]
2064 ; "bld #0,%3l\;bst %Z2,%0%Y1"
2065 ; [(set_attr "type" "multi")
2066 ; (set_attr "length" "4")
2067 ; (set_attr "cc" "clobber")])
2069 (define_insn "fancybset1"
2070 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2072 (ashift:HI (const_int 1)
2073 (subreg:QI (match_operand:HI 1 "register_operand" "ri") 0)) 0)
2078 (define_insn "fancybset"
2079 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2081 (ashift:HI (const_int 1)
2082 (match_operand:HI 1 "nonmemory_operand" "ri") ) 0)
2083 (match_operand:QI 2 "general_operand" "Ur")))]
2085 "mov.b %X2,%X0\;bset %X1,%X0")
2088 (define_insn "fancybclr4"
2089 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2092 (rotate:HI (const_int -2)
2093 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2094 (match_operand:QI 1 "general_operand" "0,Ur")))
2095 (clobber (match_scratch:HI 3 "=X,&r"))]
2099 mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0; l3")
2101 (define_insn "fancybclr5"
2102 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2105 (rotate:HI (const_int -2)
2106 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2107 (match_operand:QI 1 "general_operand" "0,Ur")))
2108 (clobber (match_scratch:HI 3 "=X,&r"))]
2112 mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0;l2")
2114 (define_insn "fancybclr2"
2115 [(set (match_operand:QI 0 "general_operand" "=U,r")
2118 (rotate:HI (const_int -2)
2119 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2120 (match_operand:QI 1 "general_operand" "0,0")))]
2124 (define_insn "fancybclr3"
2125 [(set (match_operand:QI 0 "general_operand" "=U,r")
2128 (rotate:HI (const_int -2)
2129 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2130 (match_operand:QI 1 "general_operand" "0,0")))]
2134 (define_insn "fancybclr"
2135 [(set (match_operand:QI 0 "general_operand" "=r")
2136 (and:QI (not:QI (match_operand:QI 1 "general_operand" "0"))
2137 (match_operand:QI 2 "general_operand" "r")))]
2139 "not %X0\;and %X2,%X0")
2141 (define_insn "fancybsetp3"
2142 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2143 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2144 (match_operand:QI 1 "register_operand" "r")) 0)
2145 (match_operand:QI 2 "bit_operand" "0")))]
2149 (define_insn "fancybsetp2"
2150 [(set (match_operand:QI 0 "general_operand" "=r,U")
2151 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2152 (match_operand:QI 1 "register_operand" "r,r")) 0)
2153 (match_operand:QI 2 "general_operand" "U,r")))]
2155 "mov.b %X2,%X0\;bset %X1,%X0")
2157 (define_insn "fancybnot"
2158 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2159 (xor:QI (subreg:QI (ashift:HI (const_int 1)
2160 (match_operand:QI 1 "register_operand" "r")) 0)
2161 (match_operand:QI 2 "bit_operand" "0")))]
2166 (define_insn "fancy_btst"
2168 (if_then_else (eq (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur"))
2170 (match_operand:HI 1 "nonmemory_operand" "rn"))
2172 (label_ref (match_operand 2 "" ""))
2177 if (get_attr_length (insn) == 2)
2178 return \"btst %X1,%X0\;beq %l2\";
2179 else if (get_attr_length (insn) == 4)
2180 return \"btst %X1,%X0\;beq %l2:16\";
2182 return \"btst %X1,%X0\;bne %L0\;jmp @%l2\;%L0:\";
2184 [(set_attr "type" "branch")
2185 (set_attr "cc" "clobber")])
2187 (define_insn "fancy_btst1"
2189 (if_then_else (ne (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur"))
2191 (match_operand:HI 1 "nonmemory_operand" "rn"))
2193 (label_ref (match_operand 2 "" ""))
2198 if (get_attr_length (insn) == 2)
2199 return \"btst %X1,%X0\;bne %l2\";
2200 else if (get_attr_length (insn) == 4)
2201 return \"btst %X1,%X0\;bne %l2:16\";
2203 return \"btst %X1,%X0\;beq %L0\;jmp @%l2\;%L0:\";
2205 [(set_attr "type" "branch")
2206 (set_attr "cc" "clobber")])
2209 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=r,U")
2211 (match_operand 1 "immediate_operand" "n,n"))
2212 (and:QI (not:QI (match_operand:QI 2 "bit_operand" "r,U"))
2215 "bld #0,%X2\;bist %1,%0"
2216 [(set_attr "type" "arith")
2217 (set_attr "length" "4")
2218 (set_attr "cc" "clobber")])