1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8/S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have a insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
53 (define_attr "cpu" "h8300,h8300h"
54 (const (symbol_ref "cpu_type")))
56 (define_attr "type" "branch,arith"
57 (const_string "arith"))
59 ;; The size of instructions in bytes.
61 (define_attr "length" ""
62 (cond [(eq_attr "type" "branch")
63 (if_then_else (and (ge (minus (pc) (match_dup 0))
65 (le (minus (pc) (match_dup 0))
68 (if_then_else (and (eq_attr "cpu" "h8300h")
69 (and (ge (minus (pc) (match_dup 0))
71 (le (minus (pc) (match_dup 0))
77 ;; The necessity of instruction length adjustment.
79 (define_attr "adjust_length" "yes,no"
80 (cond [(eq_attr "type" "branch") (const_string "no")]
81 (const_string "yes")))
83 ;; Condition code settings.
85 ;; none - insn does not affect cc
86 ;; none_0hit - insn does not affect cc but it does modify operand 0
87 ;; This attribute is used to keep track of when operand 0 changes.
88 ;; See the description of NOTICE_UPDATE_CC for more info.
89 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
90 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
91 ;; compare - compare instruction
92 ;; clobber - value of cc is unknown
94 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
95 (const_string "clobber"))
97 ;; ----------------------------------------------------------------------
99 ;; ----------------------------------------------------------------------
103 (define_insn "pushqi1_h8300"
104 [(parallel [(set (reg:HI 7)
105 (plus:HI (reg:HI 7) (const_int -2)))
106 (set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
107 (match_operand:QI 0 "register_operand" "r"))])]
110 [(set_attr "length" "2")
111 (set_attr "cc" "clobber")])
113 (define_insn "pushqi1_h8300hs"
114 [(parallel [(set (reg:SI 7)
115 (plus:SI (reg:SI 7) (const_int -4)))
116 (set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
117 (match_operand:QI 0 "register_operand" "r"))])]
118 "TARGET_H8300H || TARGET_H8300S"
120 [(set_attr "length" "4")
121 (set_attr "cc" "clobber")])
123 (define_expand "pushqi1"
124 [(use (match_operand:QI 0 "register_operand" ""))]
129 emit_insn (gen_pushqi1_h8300 (operands[0]));
131 emit_insn (gen_pushqi1_h8300hs (operands[0]));
136 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
137 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
139 && (register_operand (operands[0], QImode)
140 || register_operand (operands[1], QImode))"
148 [(set_attr "length" "2,2,2,2,4,4")
149 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
152 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
153 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
154 "(TARGET_H8300H || TARGET_H8300S)
155 && (register_operand (operands[0], QImode)
156 || register_operand (operands[1], QImode))"
164 [(set_attr "length" "2,2,2,2,8,8")
165 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
167 (define_expand "movqi"
168 [(set (match_operand:QI 0 "general_operand_dst" "")
169 (match_operand:QI 1 "general_operand_src" ""))]
173 /* One of the ops has to be in a register. */
174 if (!register_operand (operand0, QImode)
175 && !register_operand (operand1, QImode))
177 operands[1] = copy_to_mode_reg (QImode, operand1);
181 (define_insn "movstrictqi"
182 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
183 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
190 [(set_attr_alternative "length"
191 [(const_int 2) (const_int 2) (const_int 2)
192 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
193 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
197 (define_expand "pushhi1_h8300"
198 [(set (mem:QI (pre_dec:HI (reg:HI 7)))
199 (match_operand:QI 0 "register_operand" ""))]
203 (define_insn "pushhi1_h8300hs"
204 [(parallel [(set (reg:SI 7)
205 (plus:SI (reg:SI 7) (const_int -4)))
206 (set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
207 (match_operand:HI 0 "register_operand" "r"))])]
208 "TARGET_H8300H || TARGET_H8300S"
210 [(set_attr "length" "4")
211 (set_attr "cc" "clobber")])
213 (define_expand "pushhi1"
214 [(use (match_operand:QI 0 "register_operand" ""))]
219 emit_insn (gen_pushhi1_h8300 (operands[0]));
221 emit_insn (gen_pushhi1_h8300hs (operands[0]));
226 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
227 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
229 && (register_operand (operands[0], HImode)
230 || register_operand (operands[1], HImode))
231 && !(GET_CODE (operands[0]) == MEM
232 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
233 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
234 && GET_CODE (operands[1]) == REG
235 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
243 [(set_attr "length" "2,2,2,4,4,4")
244 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
247 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
248 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
249 "(TARGET_H8300H || TARGET_H8300S)
250 && (register_operand (operands[0], HImode)
251 || register_operand (operands[1], HImode))"
259 [(set_attr "length" "2,2,2,4,8,8")
260 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
262 (define_expand "movhi"
263 [(set (match_operand:HI 0 "general_operand_dst" "")
264 (match_operand:HI 1 "general_operand_src" ""))]
268 /* One of the ops has to be in a register. */
269 if (!register_operand (operand1, HImode)
270 && !register_operand (operand0, HImode))
272 operands[1] = copy_to_mode_reg (HImode, operand1);
276 (define_insn "movstricthi"
277 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
278 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
285 [(set_attr_alternative "length"
286 [(const_int 2) (const_int 2) (const_int 4)
287 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
288 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
292 (define_expand "movsi"
293 [(set (match_operand:SI 0 "general_operand_dst" "")
294 (match_operand:SI 1 "general_operand_src" ""))]
300 if (do_movsi (operands))
305 /* One of the ops has to be in a register. */
306 if (!register_operand (operand1, SImode)
307 && !register_operand (operand0, SImode))
309 operands[1] = copy_to_mode_reg (SImode, operand1);
314 (define_expand "movsf"
315 [(set (match_operand:SF 0 "general_operand_dst" "")
316 (match_operand:SF 1 "general_operand_src" ""))]
322 if (do_movsi (operands))
327 /* One of the ops has to be in a register. */
328 if (!register_operand (operand1, SFmode)
329 && !register_operand (operand0, SFmode))
331 operands[1] = copy_to_mode_reg (SFmode, operand1);
336 (define_insn "movsi_h8300"
337 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
338 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
340 && (register_operand (operands[0], SImode)
341 || register_operand (operands[1], SImode))"
345 switch (which_alternative)
348 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
350 if (REGNO (operands[0]) < REGNO (operands[1]))
351 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
353 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
355 /* Make sure we don't trample the register we index with. */
356 if (GET_CODE (operands[1]) == MEM)
358 rtx inside = XEXP (operands[1], 0);
363 else if (GET_CODE (inside) == PLUS)
365 rtx lhs = XEXP (inside, 0);
366 rtx rhs = XEXP (inside, 1);
367 if (REG_P (lhs)) rn = REGNO (lhs);
368 if (REG_P (rhs)) rn = REGNO (rhs);
371 if (rn == REGNO (operands[0]))
373 /* Move the second word first. */
374 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
378 /* See if either half is zero. If so, use sub.w to clear
380 if (GET_CODE (operands[1]) == CONST_INT)
382 if ((INTVAL (operands[1]) & 0xffff) == 0)
383 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
384 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
385 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
387 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
390 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
392 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
394 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
399 [(set_attr "length" "4,4,8,8,4,4")
400 (set_attr "cc" "clobber")])
402 (define_insn "movsf_h8300"
403 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
404 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
406 && (register_operand (operands[0], SFmode)
407 || register_operand (operands[1], SFmode))"
410 /* Copy of the movsi stuff. */
412 switch (which_alternative)
415 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
417 if (REGNO (operands[0]) < REGNO (operands[1]))
418 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
420 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
422 /* Make sure we don't trample the register we index with. */
423 if (GET_CODE (operands[1]) == MEM)
425 rtx inside = XEXP (operands[1], 0);
430 else if (GET_CODE (inside) == PLUS)
432 rtx lhs = XEXP (inside, 0);
433 rtx rhs = XEXP (inside, 1);
434 if (REG_P (lhs)) rn = REGNO (lhs);
435 if (REG_P (rhs)) rn = REGNO (rhs);
438 if (rn == REGNO (operands[0]))
439 /* Move the second word first. */
440 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
442 /* Move the first word first. */
443 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
446 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
448 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
450 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
455 [(set_attr "length" "4,4,8,8,4,4")
456 (set_attr "cc" "clobber")])
458 (define_insn "movsi_h8300hs"
459 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
460 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
461 "(TARGET_H8300S || TARGET_H8300H)
462 && (register_operand (operands[0], SImode)
463 || register_operand (operands[1], SImode))
464 && !(GET_CODE (operands[0]) == MEM
465 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
466 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
467 && GET_CODE (operands[1]) == REG
468 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
471 switch (which_alternative)
474 return \"sub.l %S0,%S0\";
478 return \"clrmac\;ldmac %1,macl\";
480 return \"stmac macl,%0\";
482 if (GET_CODE (operands[1]) == CONST_INT)
484 int val = INTVAL (operands[1]);
486 /* Look for constants which can be made by adding an 8-bit
487 number to zero in one of the two low bytes. */
488 if (val == (val & 0xff))
490 operands[1] = GEN_INT ((char) val & 0xff);
491 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
494 if (val == (val & 0xff00))
496 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
497 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
500 /* Look for constants that can be obtained by subs, inc, and
502 switch (val & 0xffffffff)
505 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
507 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
509 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
512 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
514 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
517 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
519 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
522 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
524 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
528 return \"mov.l %S1,%S0\";
530 [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
531 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
533 (define_insn "movsf_h8300h"
534 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
535 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
536 "(TARGET_H8300H || TARGET_H8300S)
537 && (register_operand (operands[0], SFmode)
538 || register_operand (operands[1], SFmode))"
546 [(set_attr "length" "2,2,10,10,4,4")
547 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
549 ;; ----------------------------------------------------------------------
551 ;; ----------------------------------------------------------------------
554 [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
556 (match_operand:QI 1 "const_int_operand" "n,n")))]
559 [(set_attr "length" "2,8")
560 (set_attr "cc" "set_zn,set_zn")])
563 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
565 (match_operand:QI 1 "const_int_operand" "n,n")))]
568 [(set_attr "length" "2,8")
569 (set_attr "cc" "set_zn,set_zn")])
572 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
574 (match_operand:QI 1 "const_int_operand" "n,n")))]
577 [(set_attr "length" "2,8")
578 (set_attr "cc" "set_zn,set_zn")])
581 [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
583 (match_operand:HI 1 "const_int_operand" "n")))]
586 [(set_attr "length" "2")
587 (set_attr "cc" "set_zn")])
590 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
592 (match_operand:HI 1 "const_int_operand" "n")))]
595 [(set_attr "length" "2")
596 (set_attr "cc" "set_zn")])
599 [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
601 (match_operand:HI 1 "const_int_operand" "n")))]
604 [(set_attr "length" "2")
605 (set_attr "cc" "set_zn")])
608 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
611 [(set_attr "length" "2")
612 (set_attr "cc" "set_znv")])
615 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
618 [(set_attr "length" "2")
619 (set_attr "cc" "set_znv")])
622 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
623 "TARGET_H8300H || TARGET_H8300S"
625 [(set_attr "length" "2")
626 (set_attr "cc" "set_znv")])
630 (compare:QI (match_operand:QI 0 "register_operand" "r")
631 (match_operand:QI 1 "nonmemory_operand" "rn")))]
634 [(set_attr "length" "2")
635 (set_attr "cc" "compare")])
637 (define_expand "cmphi"
639 (compare:HI (match_operand:HI 0 "register_operand" "")
640 (match_operand:HI 1 "nonmemory_operand" "")))]
644 /* Force operand1 into a register if we're compiling
646 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
647 operands[1] = force_reg (HImode, operands[1]);
652 (compare:HI (match_operand:HI 0 "register_operand" "r")
653 (match_operand:HI 1 "register_operand" "r")))]
656 [(set_attr "length" "2")
657 (set_attr "cc" "compare")])
661 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
662 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
663 "TARGET_H8300H || TARGET_H8300S"
665 [(set_attr "length" "2,4")
666 (set_attr "cc" "compare,compare")])
670 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
671 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
672 "TARGET_H8300H || TARGET_H8300S"
674 [(set_attr "length" "2,6")
675 (set_attr "cc" "compare,compare")])
677 ;; ----------------------------------------------------------------------
679 ;; ----------------------------------------------------------------------
681 (define_insn "addqi3"
682 [(set (match_operand:QI 0 "register_operand" "=r")
683 (plus:QI (match_operand:QI 1 "register_operand" "%0")
684 (match_operand:QI 2 "nonmemory_operand" "rn")))]
687 [(set_attr "length" "2")
688 (set_attr "cc" "set_zn")])
690 (define_expand "addhi3"
691 [(set (match_operand:HI 0 "register_operand" "")
692 (plus:HI (match_operand:HI 1 "register_operand" "")
693 (match_operand:HI 2 "nonmemory_operand" "")))]
698 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
699 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
700 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
705 add.b %s2,%s0\;addx %t2,%t0
707 mov.w %T1,%T0\;add.w %T2,%T0"
708 [(set_attr "length" "2,2,4,2,6")
709 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
712 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
713 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
714 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
715 "TARGET_H8300H || TARGET_H8300S"
721 [(set_attr "length" "2,2,4,2")
722 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
725 [(set (match_operand:HI 0 "register_operand" "")
726 (plus:HI (match_dup 0)
727 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
730 "split_adds_subs (HImode, operands); DONE;")
732 (define_expand "addsi3"
733 [(set (match_operand:SI 0 "register_operand" "")
734 (plus:SI (match_operand:SI 1 "register_operand" "")
735 (match_operand:SI 2 "nonmemory_operand" "")))]
739 (define_insn "addsi_h8300"
740 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
741 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
742 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
745 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
746 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
747 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
748 [(set_attr "length" "8,6,10")
749 (set_attr "cc" "clobber")])
751 (define_insn "addsi_h8300h"
752 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
753 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
754 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
755 "TARGET_H8300H || TARGET_H8300S"
761 [(set_attr "length" "2,2,6,2")
762 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
765 [(set (match_operand:SI 0 "register_operand" "")
766 (plus:SI (match_dup 0)
767 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
768 "TARGET_H8300H || TARGET_H8300S"
770 "split_adds_subs (SImode, operands); DONE;")
772 ;; ----------------------------------------------------------------------
773 ;; SUBTRACT INSTRUCTIONS
774 ;; ----------------------------------------------------------------------
776 (define_insn "subqi3"
777 [(set (match_operand:QI 0 "register_operand" "=r,r")
778 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
779 (match_operand:QI 2 "nonmemory_operand" "r,n")))]
784 [(set_attr "length" "2")
785 (set_attr "cc" "set_zn")])
787 (define_expand "subhi3"
788 [(set (match_operand:HI 0 "register_operand" "")
789 (minus:HI (match_operand:HI 1 "general_operand" "")
790 (match_operand:HI 2 "nonmemory_operand" "")))]
795 [(set (match_operand:HI 0 "register_operand" "=r,&r")
796 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
797 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
801 add.b %E2,%s0\;addx %F2,%t0"
802 [(set_attr "length" "2,4")
803 (set_attr "cc" "set_zn,clobber")])
806 [(set (match_operand:HI 0 "register_operand" "=r,&r")
807 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
808 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
809 "TARGET_H8300H || TARGET_H8300S"
813 [(set_attr "length" "2,4")
814 (set_attr "cc" "set_zn,set_zn")])
816 (define_expand "subsi3"
817 [(set (match_operand:SI 0 "register_operand" "")
818 (minus:SI (match_operand:SI 1 "register_operand" "")
819 (match_operand:SI 2 "nonmemory_operand" "")))]
823 (define_insn "subsi3_h8300"
824 [(set (match_operand:SI 0 "register_operand" "=r")
825 (minus:SI (match_operand:SI 1 "register_operand" "0")
826 (match_operand:SI 2 "register_operand" "r")))]
828 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
829 [(set_attr "length" "6")
830 (set_attr "cc" "clobber")])
832 (define_insn "subsi3_h8300h"
833 [(set (match_operand:SI 0 "register_operand" "=r,r")
834 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
835 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
836 "TARGET_H8300H || TARGET_H8300S"
840 [(set_attr "length" "2,6")
841 (set_attr "cc" "set_zn,set_zn")])
843 ;; ----------------------------------------------------------------------
844 ;; MULTIPLY INSTRUCTIONS
845 ;; ----------------------------------------------------------------------
847 ;; Note that the H8/300 can only handle umulqihi3.
849 (define_insn "mulqihi3"
850 [(set (match_operand:HI 0 "register_operand" "=r")
851 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
852 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
853 "TARGET_H8300H || TARGET_H8300S"
855 [(set_attr "length" "4")
856 (set_attr "cc" "set_zn")])
858 (define_insn "mulhisi3"
859 [(set (match_operand:SI 0 "register_operand" "=r")
860 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
861 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
862 "TARGET_H8300H || TARGET_H8300S"
864 [(set_attr "length" "4")
865 (set_attr "cc" "set_zn")])
867 (define_insn "umulqihi3"
868 [(set (match_operand:HI 0 "register_operand" "=r")
869 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
870 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
873 [(set_attr "length" "2")
874 (set_attr "cc" "none_0hit")])
876 (define_insn "umulhisi3"
877 [(set (match_operand:SI 0 "register_operand" "=r")
878 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
879 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
880 "TARGET_H8300H || TARGET_H8300S"
882 [(set_attr "length" "2")
883 (set_attr "cc" "none_0hit")])
885 ;; This is a "bridge" instruction. Combine can't cram enough insns
886 ;; together to crate a MAC instruction directly, but it can create
887 ;; this instruction, which then allows combine to create the real
890 ;; Unfortunately, if combine doesn't create a MAC instruction, this
891 ;; insn must generate reasonably correct code. Egad.
893 [(set (match_operand:SI 0 "register_operand" "=a")
896 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
898 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
900 "clrmac\;mac @%2+,@%1+"
901 [(set_attr "length" "6")
902 (set_attr "cc" "none_0hit")])
905 [(set (match_operand:SI 0 "register_operand" "=a")
907 (sign_extend:SI (mem:HI
908 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
909 (sign_extend:SI (mem:HI
910 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
911 (match_operand:SI 3 "register_operand" "0")))]
914 [(set_attr "length" "4")
915 (set_attr "cc" "none_0hit")])
917 ;; ----------------------------------------------------------------------
918 ;; DIVIDE/MOD INSTRUCTIONS
919 ;; ----------------------------------------------------------------------
921 (define_insn "udivmodqi4"
922 [(set (match_operand:QI 0 "register_operand" "=r")
925 (match_operand:HI 1 "general_operand" "0")
926 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
927 (set (match_operand:QI 3 "register_operand" "=r")
931 (zero_extend:HI (match_dup 2)))))]
932 "TARGET_H8300H || TARGET_H8300S"
935 if (find_reg_note (insn, REG_UNUSED, operands[3]))
936 return \"divxu.b\\t%X2,%T0\";
938 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
940 [(set_attr "length" "4")
941 (set_attr "cc" "clobber")])
943 (define_insn "divmodqi4"
944 [(set (match_operand:QI 0 "register_operand" "=r")
947 (match_operand:HI 1 "general_operand" "0")
948 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
949 (set (match_operand:QI 3 "register_operand" "=r")
953 (sign_extend:HI (match_dup 2)))))]
954 "TARGET_H8300H || TARGET_H8300S"
957 if (find_reg_note (insn, REG_UNUSED, operands[3]))
958 return \"divxs.b\\t%X2,%T0\";
960 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
962 [(set_attr "length" "6")
963 (set_attr "cc" "clobber")])
965 (define_insn "udivmodhi4"
966 [(set (match_operand:HI 0 "register_operand" "=r")
969 (match_operand:SI 1 "general_operand" "0")
970 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
971 (set (match_operand:HI 3 "register_operand" "=r")
975 (zero_extend:SI (match_dup 2)))))]
976 "TARGET_H8300H || TARGET_H8300S"
979 if (find_reg_note (insn, REG_UNUSED, operands[3]))
980 return \"divxu.w\\t%T2,%S0\";
982 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
984 [(set_attr "length" "4")
985 (set_attr "cc" "clobber")])
987 (define_insn "divmodhi4"
988 [(set (match_operand:HI 0 "register_operand" "=r")
991 (match_operand:SI 1 "general_operand" "0")
992 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
993 (set (match_operand:HI 3 "register_operand" "=r")
997 (sign_extend:SI (match_dup 2)))))]
998 "TARGET_H8300H || TARGET_H8300S"
1001 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1002 return \"divxs.w\\t%T2,%S0\";
1004 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1006 [(set_attr "length" "6")
1007 (set_attr "cc" "clobber")])
1009 ;; ----------------------------------------------------------------------
1011 ;; ----------------------------------------------------------------------
1014 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1015 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1016 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1017 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
1021 [(set_attr "length" "2,8")
1022 (set_attr "adjust_length" "no")
1023 (set_attr "cc" "set_znv,none_0hit")])
1025 (define_expand "andqi3"
1026 [(set (match_operand:QI 0 "bit_operand" "")
1027 (and:QI (match_operand:QI 1 "bit_operand" "")
1028 (match_operand:QI 2 "nonmemory_operand" "")))]
1032 if (fix_bit_operand (operands, 'O', AND))
1036 (define_expand "andhi3"
1037 [(set (match_operand:HI 0 "register_operand" "")
1038 (and:HI (match_operand:HI 1 "register_operand" "")
1039 (match_operand:HI 2 "nonmemory_operand" "")))]
1044 [(set (match_operand:HI 0 "register_operand" "=r")
1045 (and:HI (match_operand:HI 1 "register_operand" "%0")
1046 (match_operand:HI 2 "nonmemory_operand" "rn")))]
1048 "* return output_logical_op (HImode, AND, operands);"
1049 [(set_attr "length" "4")
1050 (set_attr "cc" "clobber")])
1053 [(set (match_operand:HI 0 "register_operand" "=r,r")
1054 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
1055 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
1056 "TARGET_H8300H || TARGET_H8300S"
1057 "* return output_logical_op (HImode, AND, operands);"
1058 [(set_attr "length" "2,4")
1059 (set_attr "cc" "set_znv,clobber")])
1061 (define_insn "*andorhi3"
1062 [(set (match_operand:HI 0 "register_operand" "=r")
1063 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1064 (match_operand:HI 3 "const_int_operand" "n"))
1065 (match_operand:HI 1 "register_operand" "0")))]
1066 "exact_log2 (INTVAL (operands[3]) & 0xffff) != -1"
1069 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1070 if (INTVAL (operands[3]) > 128)
1072 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1073 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1075 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1077 [(set_attr "length" "4")
1078 (set_attr "cc" "clobber")])
1080 (define_expand "andsi3"
1081 [(set (match_operand:SI 0 "register_operand" "")
1082 (and:SI (match_operand:SI 1 "register_operand" "")
1083 (match_operand:SI 2 "nonmemory_operand" "")))]
1088 [(set (match_operand:SI 0 "register_operand" "=r")
1089 (and:SI (match_operand:SI 1 "register_operand" "%0")
1090 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1092 "* return output_logical_op (SImode, AND, operands);"
1093 [(set_attr "length" "8")
1094 (set_attr "cc" "clobber")])
1097 [(set (match_operand:SI 0 "register_operand" "=r,r")
1098 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1099 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1100 "TARGET_H8300H || TARGET_H8300S"
1101 "* return output_logical_op (SImode, AND, operands);"
1102 [(set_attr "length" "4,6")
1103 (set_attr "cc" "set_znv,clobber")])
1105 ;; ----------------------------------------------------------------------
1107 ;; ----------------------------------------------------------------------
1110 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1111 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1112 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1113 "register_operand (operands[0], QImode)
1114 || (GET_CODE (operands[2]) == CONST_INT
1115 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1118 switch (which_alternative)
1121 return \"or\t%X2,%X0\";
1123 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1124 return \"bset\t%V2,%R0\";
1129 [(set_attr "length" "2,8")
1130 (set_attr "adjust_length" "no")
1131 (set_attr "cc" "set_znv,none_0hit")])
1133 (define_expand "iorqi3"
1134 [(set (match_operand:QI 0 "bit_operand" "")
1135 (ior:QI (match_operand:QI 1 "bit_operand" "")
1136 (match_operand:QI 2 "nonmemory_operand" "")))]
1140 if (fix_bit_operand (operands, 'P', IOR))
1144 (define_expand "iorhi3"
1145 [(set (match_operand:HI 0 "general_operand" "")
1146 (ior:HI (match_operand:HI 1 "general_operand" "")
1147 (match_operand:HI 2 "general_operand" "")))]
1152 [(set (match_operand:HI 0 "general_operand" "=r,r")
1153 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1154 (match_operand:HI 2 "general_operand" "J,rn")))]
1156 "* return output_logical_op (HImode, IOR, operands);"
1157 [(set_attr "length" "2,4")
1158 (set_attr "cc" "clobber,clobber")])
1161 [(set (match_operand:HI 0 "general_operand" "=r,r,r")
1162 (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1163 (match_operand:HI 2 "general_operand" "J,r,n")))]
1164 "TARGET_H8300H || TARGET_H8300S"
1165 "* return output_logical_op (HImode, IOR, operands);"
1166 [(set_attr "length" "2,2,4")
1167 (set_attr "cc" "clobber,set_znv,clobber")])
1169 (define_expand "iorsi3"
1170 [(set (match_operand:SI 0 "register_operand" "")
1171 (ior:SI (match_operand:SI 1 "register_operand" "")
1172 (match_operand:SI 2 "nonmemory_operand" "")))]
1177 [(set (match_operand:SI 0 "register_operand" "=r,r")
1178 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1179 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1181 "* return output_logical_op (SImode, IOR, operands);"
1182 [(set_attr "length" "2,8")
1183 (set_attr "cc" "clobber,clobber")])
1186 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1187 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1188 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1189 "TARGET_H8300H || TARGET_H8300S"
1190 "* return output_logical_op (SImode, IOR, operands);"
1191 [(set_attr "length" "2,4,6")
1192 (set_attr "cc" "clobber,set_znv,clobber")])
1194 ;; ----------------------------------------------------------------------
1196 ;; ----------------------------------------------------------------------
1199 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1200 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1201 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1202 "register_operand (operands[0], QImode)
1203 || (GET_CODE (operands[2]) == CONST_INT
1204 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1207 switch (which_alternative)
1210 return \"xor\t%X2,%X0\";
1212 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1213 return \"bnot\t%V2,%R0\";
1218 [(set_attr "length" "2,8")
1219 (set_attr "adjust_length" "no")
1220 (set_attr "cc" "set_znv,none_0hit")])
1222 (define_expand "xorqi3"
1223 [(set (match_operand:QI 0 "bit_operand" "")
1224 (xor:QI (match_operand:QI 1 "bit_operand" "")
1225 (match_operand:QI 2 "nonmemory_operand" "")))]
1229 if (fix_bit_operand (operands, 'O', XOR))
1233 (define_expand "xorhi3"
1234 [(set (match_operand:HI 0 "register_operand" "")
1235 (xor:HI (match_operand:HI 1 "general_operand" "")
1236 (match_operand:HI 2 "nonmemory_operand" "")))]
1241 [(set (match_operand:HI 0 "register_operand" "=r,r")
1242 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1243 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1245 "* return output_logical_op (HImode, XOR, operands);"
1246 [(set_attr "length" "2,4")
1247 (set_attr "cc" "clobber,clobber")])
1250 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1251 (xor:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1252 (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
1253 "TARGET_H8300H || TARGET_H8300S"
1254 "* return output_logical_op (HImode, XOR, operands);"
1255 [(set_attr "length" "2,2,4")
1256 (set_attr "cc" "clobber,set_znv,clobber")])
1258 (define_expand "xorsi3"
1259 [(set (match_operand:SI 0 "register_operand" "")
1260 (xor:SI (match_operand:SI 1 "register_operand" "")
1261 (match_operand:SI 2 "nonmemory_operand" "")))]
1266 [(set (match_operand:SI 0 "register_operand" "=r,r")
1267 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1268 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1270 "* return output_logical_op (SImode, XOR, operands);"
1271 [(set_attr "length" "2,8")
1272 (set_attr "cc" "clobber,clobber")])
1275 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1276 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1277 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1278 "TARGET_H8300H || TARGET_H8300S"
1279 "* return output_logical_op (SImode, XOR, operands);"
1280 [(set_attr "length" "2,4,6")
1281 (set_attr "cc" "clobber,set_znv,clobber")])
1283 ;; ----------------------------------------------------------------------
1284 ;; NEGATION INSTRUCTIONS
1285 ;; ----------------------------------------------------------------------
1287 (define_insn "negqi2"
1288 [(set (match_operand:QI 0 "register_operand" "=r")
1289 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1292 [(set_attr "length" "2")
1293 (set_attr "cc" "set_zn")])
1295 (define_expand "neghi2"
1296 [(set (match_operand:HI 0 "register_operand" "")
1297 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1303 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1308 (define_expand "neghi2_h8300"
1310 (not:HI (match_operand:HI 1 "register_operand" "")))
1311 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1312 (set (match_operand:HI 0 "register_operand" "")
1315 "{ operands[2] = gen_reg_rtx (HImode); }")
1317 (define_insn "neghi2_h8300h"
1318 [(set (match_operand:HI 0 "register_operand" "=r")
1319 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1320 "TARGET_H8300H || TARGET_H8300S"
1322 [(set_attr "length" "2")
1323 (set_attr "cc" "set_zn")])
1325 (define_expand "negsi2"
1326 [(set (match_operand:SI 0 "register_operand" "")
1327 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1333 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1338 (define_expand "negsi2_h8300"
1340 (not:SI (match_operand:SI 1 "register_operand" "")))
1341 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1342 (set (match_operand:SI 0 "register_operand" "")
1345 "{ operands[2] = gen_reg_rtx(SImode); }")
1347 (define_insn "negsi2_h8300h"
1348 [(set (match_operand:SI 0 "register_operand" "=r")
1349 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1350 "TARGET_H8300H || TARGET_H8300S"
1352 [(set_attr "length" "2")
1353 (set_attr "cc" "set_zn")])
1355 ;; ----------------------------------------------------------------------
1357 ;; ----------------------------------------------------------------------
1359 (define_insn "one_cmplqi2"
1360 [(set (match_operand:QI 0 "register_operand" "=r")
1361 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1364 [(set_attr "length" "2")
1365 (set_attr "cc" "set_znv")])
1367 (define_insn "one_cmplhi2"
1368 [(set (match_operand:HI 0 "register_operand" "=r")
1369 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1374 return \"not %s0\;not %t0\";
1378 [(set_attr "cc" "clobber")
1379 (set (attr "length")
1380 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1385 (define_insn "one_cmplsi2"
1386 [(set (match_operand:SI 0 "register_operand" "=r")
1387 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1392 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1396 [(set_attr "cc" "clobber")
1397 (set (attr "length")
1398 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1403 ;; ----------------------------------------------------------------------
1404 ;; JUMP INSTRUCTIONS
1405 ;; ----------------------------------------------------------------------
1407 ;; Conditional jump instructions
1409 (define_expand "ble"
1411 (if_then_else (le (cc0)
1413 (label_ref (match_operand 0 "" ""))
1418 (define_expand "bleu"
1420 (if_then_else (leu (cc0)
1422 (label_ref (match_operand 0 "" ""))
1427 (define_expand "bge"
1429 (if_then_else (ge (cc0)
1431 (label_ref (match_operand 0 "" ""))
1436 (define_expand "bgeu"
1438 (if_then_else (geu (cc0)
1440 (label_ref (match_operand 0 "" ""))
1445 (define_expand "blt"
1447 (if_then_else (lt (cc0)
1449 (label_ref (match_operand 0 "" ""))
1454 (define_expand "bltu"
1456 (if_then_else (ltu (cc0)
1458 (label_ref (match_operand 0 "" ""))
1463 (define_expand "bgt"
1465 (if_then_else (gt (cc0)
1467 (label_ref (match_operand 0 "" ""))
1472 (define_expand "bgtu"
1474 (if_then_else (gtu (cc0)
1476 (label_ref (match_operand 0 "" ""))
1481 (define_expand "beq"
1483 (if_then_else (eq (cc0)
1485 (label_ref (match_operand 0 "" ""))
1490 (define_expand "bne"
1492 (if_then_else (ne (cc0)
1494 (label_ref (match_operand 0 "" ""))
1499 (define_insn "branch_true"
1501 (if_then_else (match_operator 1 "comparison_operator"
1502 [(cc0) (const_int 0)])
1503 (label_ref (match_operand 0 "" ""))
1508 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1509 && (GET_CODE (operands[1]) == GT
1510 || GET_CODE (operands[1]) == GE
1511 || GET_CODE (operands[1]) == LE
1512 || GET_CODE (operands[1]) == LT))
1514 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1518 if (get_attr_length (insn) == 2)
1519 return \"b%j1 %l0\";
1520 else if (get_attr_length (insn) == 4)
1521 return \"b%j1 %l0:16\";
1523 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1525 [(set_attr "type" "branch")
1526 (set_attr "cc" "none")])
1528 (define_insn "branch_false"
1530 (if_then_else (match_operator 1 "comparison_operator"
1531 [(cc0) (const_int 0)])
1533 (label_ref (match_operand 0 "" ""))))]
1537 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1538 && (GET_CODE (operands[1]) == GT
1539 || GET_CODE (operands[1]) == GE
1540 || GET_CODE (operands[1]) == LE
1541 || GET_CODE (operands[1]) == LT))
1543 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1547 if (get_attr_length (insn) == 2)
1548 return \"b%k1 %l0\";
1549 else if (get_attr_length (insn) == 4)
1550 return \"b%k1 %l0:16\";
1552 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1554 [(set_attr "type" "branch")
1555 (set_attr "cc" "none")])
1557 ;; Unconditional and other jump instructions.
1561 (label_ref (match_operand 0 "" "")))]
1565 if (get_attr_length (insn) == 2)
1567 else if (get_attr_length (insn) == 4)
1568 return \"bra %l0:16\";
1570 return \"jmp @%l0\";
1572 [(set_attr "type" "branch")
1573 (set_attr "cc" "none")])
1575 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1577 (define_expand "tablejump"
1578 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1579 (use (label_ref (match_operand 1 "" "")))])]
1583 (define_insn "tablejump_h8300"
1584 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1585 (use (label_ref (match_operand 1 "" "")))]
1588 [(set_attr "cc" "none")
1589 (set_attr "length" "2")])
1591 (define_insn "tablejump_h8300h"
1592 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1593 (use (label_ref (match_operand 1 "" "")))]
1594 "TARGET_H8300H || TARGET_H8300S"
1596 [(set_attr "cc" "none")
1597 (set_attr "length" "2")])
1599 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1601 (define_expand "indirect_jump"
1602 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1606 (define_insn "indirect_jump_h8300"
1607 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1610 [(set_attr "cc" "none")
1611 (set_attr "length" "2")])
1613 (define_insn "indirect_jump_h8300h"
1614 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1615 "TARGET_H8300H || TARGET_H8300S"
1617 [(set_attr "cc" "none")
1618 (set_attr "length" "2")])
1620 ;; Call subroutine with no return value.
1622 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1625 [(call (match_operand:QI 0 "call_insn_operand" "or")
1626 (match_operand:HI 1 "general_operand" "g"))]
1630 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1631 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1632 return \"jsr\\t@%0:8\";
1634 return \"jsr\\t%0\";
1636 [(set_attr "cc" "clobber")
1637 (set (attr "length")
1638 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1642 ;; Call subroutine, returning value in operand 0
1643 ;; (which must be a hard register).
1645 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1647 (define_insn "call_value"
1648 [(set (match_operand 0 "" "=r")
1649 (call (match_operand:QI 1 "call_insn_operand" "or")
1650 (match_operand:HI 2 "general_operand" "g")))]
1654 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1655 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1656 return \"jsr\\t@%1:8\";
1658 return \"jsr\\t%1\";
1660 [(set_attr "cc" "clobber")
1661 (set (attr "length")
1662 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1670 [(set_attr "cc" "none")
1671 (set_attr "length" "2")])
1673 ;; ----------------------------------------------------------------------
1674 ;; EXTEND INSTRUCTIONS
1675 ;; ----------------------------------------------------------------------
1677 (define_expand "zero_extendqihi2"
1678 [(set (match_operand:HI 0 "register_operand" "")
1679 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1684 [(set (match_operand:HI 0 "register_operand" "=r,r")
1685 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1689 mov.b %R1,%s0\;mov.b #0,%t0"
1690 [(set_attr "length" "2,10")
1691 (set_attr "cc" "clobber,clobber")])
1694 [(set (match_operand:HI 0 "register_operand" "=r,r")
1695 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1696 "TARGET_H8300H || TARGET_H8300S"
1699 mov.b %R1,%s0\;extu.w %T0"
1700 [(set_attr "length" "2,10")
1701 (set_attr "cc" "set_znv,set_znv")])
1703 ;; The compiler can synthesize a 300H variant of this which is
1704 ;; just as efficient as one that we'd create
1705 (define_insn "zero_extendqisi2"
1706 [(set (match_operand:SI 0 "register_operand" "=r,r")
1707 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1710 mov.b #0,%x0\;sub.w %e0,%e0
1711 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1712 [(set_attr "length" "4,6")
1713 (set_attr "cc" "clobber,clobber")])
1715 (define_expand "zero_extendhisi2"
1716 [(set (match_operand:SI 0 "register_operand" "")
1717 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1721 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1723 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1724 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1728 mov.w %f1,%f0\;sub.w %e0,%e0
1729 mov.w %e1,%f0\;sub.w %e0,%e0"
1730 [(set_attr "length" "2,4,4")
1731 (set_attr "cc" "clobber,clobber,clobber")])
1734 [(set (match_operand:SI 0 "register_operand" "=r")
1735 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1736 "TARGET_H8300H || TARGET_H8300S"
1738 [(set_attr "length" "2")
1739 (set_attr "cc" "set_znv")])
1741 (define_expand "extendqihi2"
1742 [(set (match_operand:HI 0 "register_operand" "")
1743 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1748 [(set (match_operand:HI 0 "register_operand" "=r,r")
1749 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1752 bld #7,%s0\;subx %t0,%t0
1753 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1754 [(set_attr "length" "4,8")
1755 (set_attr "cc" "clobber,clobber")])
1758 [(set (match_operand:HI 0 "register_operand" "=r")
1759 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1760 "TARGET_H8300H || TARGET_H8300S"
1762 [(set_attr "length" "2")
1763 (set_attr "cc" "set_znv")])
1765 ;; The compiler can synthesize a 300H variant of this which is
1766 ;; just as efficient as one that we'd create
1767 (define_insn "extendqisi2"
1768 [(set (match_operand:SI 0 "register_operand" "=r,r")
1769 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1772 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1773 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1774 [(set_attr "length" "8,10")
1775 (set_attr "cc" "clobber,clobber")])
1777 (define_expand "extendhisi2"
1778 [(set (match_operand:SI 0 "register_operand" "")
1779 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1784 [(set (match_operand:SI 0 "register_operand" "=r,r")
1785 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1788 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1789 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1790 [(set_attr "length" "6,8")
1791 (set_attr "cc" "clobber,clobber")])
1794 [(set (match_operand:SI 0 "register_operand" "=r")
1795 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1796 "TARGET_H8300H || TARGET_H8300S"
1798 [(set_attr "length" "2")
1799 (set_attr "cc" "set_znv")])
1801 ;; ----------------------------------------------------------------------
1803 ;; ----------------------------------------------------------------------
1805 ;; We make some attempt to provide real efficient shifting. One example is
1806 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1807 ;; reg and moving 0 into the former reg.
1809 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1810 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1811 ;; give the optimizer more cracks at the code. However, we wish to do things
1812 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1813 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1814 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1815 ;; to detect cases it can optimize.
1817 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1818 ;; easier "do it at insn emit time" route.
1822 (define_expand "ashlqi3"
1823 [(set (match_operand:QI 0 "register_operand" "")
1824 (ashift:QI (match_operand:QI 1 "register_operand" "")
1825 (match_operand:QI 2 "nonmemory_operand" "")))]
1827 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1829 (define_expand "ashrqi3"
1830 [(set (match_operand:QI 0 "register_operand" "")
1831 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1832 (match_operand:QI 2 "nonmemory_operand" "")))]
1834 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1836 (define_expand "lshrqi3"
1837 [(set (match_operand:QI 0 "register_operand" "")
1838 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1839 (match_operand:QI 2 "nonmemory_operand" "")))]
1841 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1844 [(set (match_operand:QI 0 "register_operand" "=r,r")
1845 (match_operator:QI 3 "nshift_operator"
1846 [ (match_operand:QI 1 "register_operand" "0,0")
1847 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1848 (clobber (match_scratch:QI 4 "=X,&r"))]
1850 "* return output_a_shift (insn, operands);"
1851 [(set_attr "length" "20")
1852 (set_attr "cc" "clobber")])
1856 (define_expand "ashlhi3"
1857 [(set (match_operand:HI 0 "register_operand" "")
1858 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1859 (match_operand:QI 2 "nonmemory_operand" "")))]
1861 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1863 (define_expand "lshrhi3"
1864 [(set (match_operand:HI 0 "register_operand" "")
1865 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1866 (match_operand:QI 2 "nonmemory_operand" "")))]
1868 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1870 (define_expand "ashrhi3"
1871 [(set (match_operand:HI 0 "register_operand" "")
1872 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1873 (match_operand:QI 2 "nonmemory_operand" "")))]
1875 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1878 [(set (match_operand:HI 0 "register_operand" "=r,r")
1879 (match_operator:HI 3 "nshift_operator"
1880 [ (match_operand:HI 1 "register_operand" "0,0")
1881 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1882 (clobber (match_scratch:QI 4 "=X,&r"))]
1884 "* return output_a_shift (insn, operands);"
1885 [(set_attr "length" "20")
1886 (set_attr "cc" "clobber")])
1890 (define_expand "ashlsi3"
1891 [(set (match_operand:SI 0 "register_operand" "")
1893 (match_operand:SI 1 "general_operand" "")
1894 (match_operand:QI 2 "nonmemory_operand" "")))]
1896 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1898 (define_expand "lshrsi3"
1899 [(set (match_operand:SI 0 "register_operand" "")
1901 (match_operand:SI 1 "general_operand" "")
1902 (match_operand:QI 2 "nonmemory_operand" "")))]
1904 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1906 (define_expand "ashrsi3"
1907 [(set (match_operand:SI 0 "register_operand" "")
1909 (match_operand:SI 1 "general_operand" "")
1910 (match_operand:QI 2 "nonmemory_operand" "")))]
1912 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
1915 [(set (match_operand:SI 0 "register_operand" "=r,r")
1916 (match_operator:SI 3 "nshift_operator"
1917 [ (match_operand:SI 1 "register_operand" "0,0")
1918 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1919 (clobber (match_scratch:QI 4 "=X,&r"))]
1921 "* return output_a_shift (insn, operands);"
1922 [(set_attr "length" "20")
1923 (set_attr "cc" "clobber")])
1925 ;; ----------------------------------------------------------------------
1927 ;; ----------------------------------------------------------------------
1929 (define_expand "rotlqi3"
1930 [(set (match_operand:QI 0 "register_operand" "")
1931 (rotate:QI (match_operand:QI 1 "register_operand" "")
1932 (match_operand:QI 2 "nonmemory_operand" "")))]
1934 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1936 (define_insn "*rotlqi3_1"
1937 [(set (match_operand:QI 0 "register_operand" "=r")
1938 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1939 (match_operand:QI 2 "immediate_operand" "")))]
1941 "* return emit_a_rotate (ROTATE, operands);"
1942 [(set_attr "length" "20")
1943 (set_attr "cc" "clobber")])
1945 (define_expand "rotlhi3"
1946 [(set (match_operand:HI 0 "register_operand" "")
1947 (rotate:HI (match_operand:HI 1 "register_operand" "")
1948 (match_operand:QI 2 "nonmemory_operand" "")))]
1950 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1952 (define_insn "*rotlhi3_1"
1953 [(set (match_operand:HI 0 "register_operand" "=r")
1954 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1955 (match_operand:QI 2 "immediate_operand" "")))]
1957 "* return emit_a_rotate (ROTATE, operands);"
1958 [(set_attr "length" "20")
1959 (set_attr "cc" "clobber")])
1961 (define_expand "rotlsi3"
1962 [(set (match_operand:SI 0 "register_operand" "")
1963 (rotate:SI (match_operand:SI 1 "register_operand" "")
1964 (match_operand:QI 2 "nonmemory_operand" "")))]
1965 "TARGET_H8300H || TARGET_H8300S"
1966 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1968 (define_insn "*rotlsi3_1"
1969 [(set (match_operand:SI 0 "register_operand" "=r")
1970 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1971 (match_operand:QI 2 "immediate_operand" "")))]
1972 "TARGET_H8300H || TARGET_H8300S"
1973 "* return emit_a_rotate (ROTATE, operands);"
1974 [(set_attr "length" "20")
1975 (set_attr "cc" "clobber")])
1977 ;; -----------------------------------------------------------------
1979 ;; -----------------------------------------------------------------
1980 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1981 ;; instructions so let's use them as well as we can.
1983 ;; You'll never believe all these patterns perform one basic action --
1984 ;; load a bit from the source, optionally invert the bit, then store it
1985 ;; in the destination (which is known to be zero).
1987 ;; Combine obviously need some work to better identify this situation and
1988 ;; canonicalize the form better.
1991 ;; Normal loads with a 16bit destination.
1993 ;; Yes, both cases are needed.
1996 [(set (match_operand:HI 0 "register_operand" "=&r")
1997 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1999 (match_operand:HI 2 "immediate_operand" "n")))]
2001 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2002 [(set_attr "cc" "clobber")
2003 (set_attr "length" "6")])
2006 [(set (match_operand:HI 0 "register_operand" "=&r")
2007 (subreg:HI (zero_extract:SI
2008 (match_operand:HI 1 "register_operand" "r")
2010 (match_operand:HI 2 "immediate_operand" "n")) 2))]
2012 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2013 [(set_attr "cc" "clobber")
2014 (set_attr "length" "6")])
2017 ;; Inverted loads with a 16bit destination.
2019 ;; Yes, all four cases are needed.
2023 [(set (match_operand:HI 0 "register_operand" "=&r")
2024 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2025 (match_operand:HI 3 "p_operand" "P"))
2027 (match_operand:HI 2 "const_int_operand" "n")))]
2028 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2029 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2030 [(set_attr "cc" "clobber")
2031 (set_attr "length" "8")])
2034 [(set (match_operand:HI 0 "register_operand" "=&r")
2037 (match_operand:HI 1 "bit_operand" "Ur")
2038 (match_operand:HI 2 "const_int_operand" "n")))
2041 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2042 [(set_attr "cc" "clobber")
2043 (set_attr "length" "8")])
2046 [(set (match_operand:HI 0 "register_operand" "=&r")
2050 (match_operand:SI 1 "register_operand" "Ur")
2051 (match_operand:SI 2 "const_int_operand" "n")) 2))
2053 "INTVAL (operands[2]) < 16"
2054 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2055 [(set_attr "cc" "clobber")
2056 (set_attr "length" "8")])
2059 [(set (match_operand:HI 0 "register_operand" "=&r")
2063 (match_operand:SI 1 "bit_operand" "Ur")
2064 (match_operand:SI 2 "const_int_operand" "n")) 0))
2066 "(TARGET_H8300H || TARGET_H8300S)
2067 && INTVAL (operands[2]) < 16"
2068 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2069 [(set_attr "cc" "clobber")
2070 (set_attr "length" "8")])
2073 ;; Normal loads with a 32bit destination.
2075 ;; Yes, all three cases are needed.
2078 [(set (match_operand:SI 0 "register_operand" "=&r")
2079 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2081 (match_operand:HI 2 "const_int_operand" "n")))]
2083 "* return output_simode_bld (0, 0, operands);"
2084 [(set_attr "cc" "clobber")
2085 (set (attr "length")
2086 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2092 [(set (match_operand:SI 0 "register_operand" "=&r")
2093 (and:SI (zero_extend:SI
2095 (match_operand:QI 1 "bit_operand" "Ur")
2096 (match_operand:QI 2 "const_int_operand" "n")))
2099 "* return output_simode_bld (0, 0, operands);"
2100 [(set_attr "cc" "clobber")
2101 (set (attr "length")
2102 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2108 [(set (match_operand:SI 0 "register_operand" "=&r")
2109 (and:SI (zero_extend:SI
2111 (match_operand:HI 1 "bit_operand" "Ur")
2112 (match_operand:HI 2 "const_int_operand" "n")))
2115 "* return output_simode_bld (0, 0, operands);"
2116 [(set_attr "cc" "clobber")
2117 (set (attr "length")
2118 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2124 ;; Inverted loads with a 32bit destination.
2126 ;; Yes, all five cases are needed.
2129 [(set (match_operand:SI 0 "register_operand" "=&r")
2132 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2133 (match_operand:HI 2 "const_int_operand" "n"))))
2136 "* return output_simode_bld (1, 0, operands);"
2137 [(set_attr "cc" "clobber")
2138 (set (attr "length")
2139 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2145 [(set (match_operand:SI 0 "register_operand" "=&r")
2148 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2149 (match_operand:QI 2 "const_int_operand" "n"))))
2152 "* return output_simode_bld (1, 0, operands);"
2153 [(set_attr "cc" "clobber")
2154 (set (attr "length")
2155 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2161 [(set (match_operand:SI 0 "register_operand" "=&r")
2165 (match_operand:HI 1 "bit_operand" "Ur")
2166 (match_operand:HI 2 "const_int_operand" "n")) 0))
2169 "* return output_simode_bld (1, 0, operands);"
2170 [(set_attr "cc" "clobber")
2171 (set (attr "length")
2172 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2178 [(set (match_operand:SI 0 "register_operand" "=&r")
2182 (match_operand:QI 1 "bit_operand" "Ur")
2183 (match_operand:QI 2 "const_int_operand" "n")) 0))
2186 "* return output_simode_bld (1, 0, operands);"
2187 [(set_attr "cc" "clobber")
2188 (set (attr "length")
2189 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2195 [(set (match_operand:SI 0 "register_operand" "=&r")
2196 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2197 (match_operand:HI 3 "p_operand" "P"))
2199 (match_operand:HI 2 "const_int_operand" "n")))]
2200 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2201 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2202 [(set_attr "cc" "clobber")
2203 (set_attr "length" "8")])
2205 (define_expand "insv"
2206 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2207 (match_operand:HI 1 "general_operand" "")
2208 (match_operand:HI 2 "general_operand" ""))
2209 (match_operand:HI 3 "general_operand" ""))]
2213 /* We only have single bit bitfield instructions. */
2214 if (INTVAL (operands[1]) != 1)
2217 /* For now, we don't allow memory operands. */
2218 if (GET_CODE (operands[0]) == MEM
2219 || GET_CODE (operands[3]) == MEM)
2224 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2226 (match_operand:HI 1 "immediate_operand" "n"))
2227 (match_operand:HI 2 "register_operand" "r"))]
2229 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2230 [(set_attr "cc" "clobber")
2231 (set_attr "length" "4")])
2233 (define_expand "extzv"
2234 [(set (match_operand:HI 0 "register_operand" "")
2235 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2236 (match_operand:HI 2 "general_operand" "")
2237 (match_operand:HI 3 "general_operand" "")))]
2241 /* We only have single bit bitfield instructions. */
2242 if (INTVAL (operands[2]) != 1)
2245 /* For now, we don't allow memory operands. */
2246 if (GET_CODE (operands[1]) == MEM)
2250 ;; BAND, BOR, and BXOR patterns
2253 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2254 (match_operator:HI 4 "bit_operator"
2255 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2257 (match_operand:HI 2 "immediate_operand" "n"))
2258 (match_operand:HI 3 "bit_operand" "0")]))]
2260 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2261 [(set_attr "cc" "clobber")
2262 (set_attr "length" "6")
2263 (set_attr "adjust_length" "no")])
2266 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2267 (match_operator:HI 5 "bit_operator"
2268 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2270 (match_operand:HI 2 "immediate_operand" "n"))
2271 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2273 (match_operand:HI 4 "immediate_operand" "n"))]))]
2275 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2276 [(set_attr "cc" "clobber")
2277 (set_attr "length" "6")
2278 (set_attr "adjust_length" "no")])
2280 ;; -----------------------------------------------------------------
2282 ;; -----------------------------------------------------------------
2285 [(set (match_operand:HI 0 "register_operand" "=r")
2287 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2288 (match_operand:HI 2 "register_operand" "0")))]
2289 "REG_P (operands[0])
2290 && REG_P (operands[1])
2291 && REGNO (operands[0]) != REGNO (operands[1])"
2293 [(set_attr "cc" "clobber")
2294 (set_attr "length" "2")])
2297 [(set (match_operand:SI 0 "register_operand" "=r")
2299 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2300 (match_operand:SI 2 "register_operand" "0")))]
2301 "(TARGET_H8300H || TARGET_H8300S)
2302 && REG_P (operands[0])
2303 && REG_P (operands[1])
2304 && (REGNO (operands[0]) != REGNO (operands[1]))"
2306 [(set_attr "cc" "clobber")
2307 (set_attr "length" "2")])
2310 [(set (match_operand:SI 0 "register_operand" "=r")
2312 (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2313 (match_operand:SI 2 "register_operand" "0")))]
2314 "REG_P (operands[0])
2315 && REG_P (operands[1])
2316 && REGNO (operands[0]) != REGNO (operands[1])"
2318 [(set_attr "cc" "clobber")
2319 (set_attr "length" "2")])
2322 [(set (match_operand:HI 0 "register_operand" "=r")
2324 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2325 (match_operand:HI 2 "register_operand" "0")))]
2326 "REG_P (operands[0])
2327 && REG_P (operands[1])
2328 && REGNO (operands[0]) != REGNO (operands[1])"
2330 [(set_attr "cc" "clobber")
2331 (set_attr "length" "2")])
2334 [(set (match_operand:SI 0 "register_operand" "=r")
2336 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2337 (match_operand:SI 2 "register_operand" "0")))]
2338 "(TARGET_H8300H || TARGET_H8300S)
2339 && REG_P (operands[0])
2340 && REG_P (operands[1])
2341 && (REGNO (operands[0]) != REGNO (operands[1]))"
2343 [(set_attr "cc" "clobber")
2344 (set_attr "length" "2")])
2347 [(set (match_operand:SI 0 "register_operand" "=r")
2349 (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2350 (match_operand:SI 2 "register_operand" "0")))]
2351 "REG_P (operands[0])
2352 && REG_P (operands[1])
2353 && REGNO (operands[0]) != REGNO (operands[1])"
2355 [(set_attr "cc" "clobber")
2356 (set_attr "length" "2")])
2359 [(set (match_operand:HI 0 "register_operand" "=r")
2361 (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2362 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2364 "REG_P (operands[0])
2365 && REG_P (operands[2])
2366 && REGNO (operands[0]) != REGNO (operands[2])"
2368 [(set_attr "cc" "clobber")
2369 (set_attr "length" "2")])
2372 [(set (match_operand:SI 0 "register_operand" "=r")
2374 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2375 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2377 "(TARGET_H8300H || TARGET_H8300S)
2378 && REG_P (operands[0])
2379 && REG_P (operands[2])
2380 && (REGNO (operands[0]) != REGNO (operands[2]))"
2382 [(set_attr "cc" "clobber")
2383 (set_attr "length" "2")])