1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
334 byte_reg (rtx x, int b)
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
344 return names_small[REGNO (x) * 2 + b];
347 /* REGNO must be saved/restored across calls if this macro is true. */
349 #define WORD_REG_USED(regno) \
351 /* No need to save registers if this function will not return. */ \
352 && ! TREE_THIS_VOLATILE (current_function_decl) \
353 && (h8300_saveall_function_p (current_function_decl) \
354 /* Save any call saved register that was used. */ \
355 || (regs_ever_live[regno] && !call_used_regs[regno]) \
356 /* Save the frame pointer if it was used. */ \
357 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
358 /* Save any register used in an interrupt handler. */ \
359 || (h8300_current_function_interrupt_function_p () \
360 && regs_ever_live[regno]) \
361 /* Save call clobbered registers in non-leaf interrupt \
363 || (h8300_current_function_interrupt_function_p () \
364 && call_used_regs[regno] \
365 && !current_function_is_leaf)))
367 /* Output assembly language to FILE for the operation OP with operand size
368 SIZE to adjust the stack pointer. */
371 h8300_emit_stack_adjustment (int sign, unsigned int size)
373 /* If the frame size is 0, we don't have anything to do. */
377 /* H8/300 cannot add/subtract a large constant with a single
378 instruction. If a temporary register is available, load the
379 constant to it and then do the addition. */
382 && !h8300_current_function_interrupt_function_p ()
383 && !(current_function_needs_context && sign < 0))
385 rtx r3 = gen_rtx_REG (Pmode, 3);
386 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
387 emit_insn (gen_addhi3 (stack_pointer_rtx,
388 stack_pointer_rtx, r3));
392 /* The stack adjustment made here is further optimized by the
393 splitter. In case of H8/300, the splitter always splits the
394 addition emitted here to make the adjustment
397 emit_insn (gen_addhi3 (stack_pointer_rtx,
398 stack_pointer_rtx, GEN_INT (sign * size)));
400 emit_insn (gen_addsi3 (stack_pointer_rtx,
401 stack_pointer_rtx, GEN_INT (sign * size)));
405 /* Round up frame size SIZE. */
408 round_frame_size (int size)
410 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
411 & -STACK_BOUNDARY / BITS_PER_UNIT);
414 /* Compute which registers to push/pop.
415 Return a bit vector of registers. */
418 compute_saved_regs (void)
420 unsigned int saved_regs = 0;
423 /* Construct a bit vector of registers to be pushed/popped. */
424 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
426 if (WORD_REG_USED (regno))
427 saved_regs |= 1 << regno;
430 /* Don't push/pop the frame pointer as it is treated separately. */
431 if (frame_pointer_needed)
432 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
437 /* Emit an insn to push register RN. */
442 rtx reg = gen_rtx_REG (word_mode, rn);
446 x = gen_push_h8300 (reg);
447 else if (!TARGET_NORMAL_MODE)
448 x = gen_push_h8300hs_advanced (reg);
450 x = gen_push_h8300hs_normal (reg);
452 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
455 /* Emit an insn to pop register RN. */
460 rtx reg = gen_rtx_REG (word_mode, rn);
464 x = gen_pop_h8300 (reg);
465 else if (!TARGET_NORMAL_MODE)
466 x = gen_pop_h8300hs_advanced (reg);
468 x = gen_pop_h8300hs_normal (reg);
470 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
473 /* This is what the stack looks like after the prolog of
474 a function with a frame has been set up:
480 <saved registers> <- sp
482 This is what the stack looks like after the prolog of
483 a function which doesn't have a frame:
488 <saved registers> <- sp
491 /* Generate RTL code for the function prologue. */
494 h8300_expand_prologue (void)
500 /* If the current function has the OS_Task attribute set, then
501 we have a naked prologue. */
502 if (h8300_os_task_function_p (current_function_decl))
505 if (h8300_monitor_function_p (current_function_decl))
506 /* My understanding of monitor functions is they act just like
507 interrupt functions, except the prologue must mask
509 emit_insn (gen_monitor_prologue ());
511 if (frame_pointer_needed)
514 push (HARD_FRAME_POINTER_REGNUM);
515 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
518 /* Push the rest of the registers in ascending order. */
519 saved_regs = compute_saved_regs ();
520 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
523 if (saved_regs & (1 << regno))
527 /* See how many registers we can push at the same time. */
528 if ((regno == 0 || regno == 4)
529 && ((saved_regs >> regno) & 0x0f) == 0x0f)
532 else if ((regno == 0 || regno == 4)
533 && ((saved_regs >> regno) & 0x07) == 0x07)
536 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
537 && ((saved_regs >> regno) & 0x03) == 0x03)
547 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
548 gen_rtx_REG (SImode, regno + 1)));
551 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
552 gen_rtx_REG (SImode, regno + 1),
553 gen_rtx_REG (SImode, regno + 2)));
556 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
557 gen_rtx_REG (SImode, regno + 1),
558 gen_rtx_REG (SImode, regno + 2),
559 gen_rtx_REG (SImode, regno + 3)));
567 /* Leave room for locals. */
568 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
572 h8300_can_use_return_insn_p (void)
574 return (reload_completed
575 && !frame_pointer_needed
576 && get_frame_size () == 0
577 && compute_saved_regs () == 0);
580 /* Generate RTL code for the function epilogue. */
583 h8300_expand_epilogue (void)
589 if (h8300_os_task_function_p (current_function_decl))
590 /* OS_Task epilogues are nearly naked -- they just have an
594 /* Deallocate locals. */
595 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
597 /* Pop the saved registers in descending order. */
598 saved_regs = compute_saved_regs ();
599 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
602 if (saved_regs & (1 << regno))
606 /* See how many registers we can pop at the same time. */
607 if ((regno == 7 || regno == 3)
608 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
611 else if ((regno == 6 || regno == 2)
612 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
615 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
616 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
626 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
627 gen_rtx_REG (SImode, regno)));
630 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
631 gen_rtx_REG (SImode, regno - 1),
632 gen_rtx_REG (SImode, regno)));
635 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
636 gen_rtx_REG (SImode, regno - 2),
637 gen_rtx_REG (SImode, regno - 1),
638 gen_rtx_REG (SImode, regno)));
646 /* Pop frame pointer if we had one. */
647 if (frame_pointer_needed)
648 pop (HARD_FRAME_POINTER_REGNUM);
651 /* Return nonzero if the current function is an interrupt
655 h8300_current_function_interrupt_function_p (void)
657 return (h8300_interrupt_function_p (current_function_decl)
658 || h8300_monitor_function_p (current_function_decl));
661 /* Output assembly code for the start of the file. */
664 h8300_file_start (void)
666 default_file_start ();
669 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
670 else if (TARGET_H8300S)
671 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
674 /* Output assembly language code for the end of file. */
677 h8300_file_end (void)
679 fputs ("\t.end\n", asm_out_file);
682 /* Return true if OP is a valid source operand for an integer move
686 general_operand_src (rtx op, enum machine_mode mode)
688 if (GET_MODE (op) == mode
689 && GET_CODE (op) == MEM
690 && GET_CODE (XEXP (op, 0)) == POST_INC)
692 return general_operand (op, mode);
695 /* Return true if OP is a valid destination operand for an integer move
699 general_operand_dst (rtx op, enum machine_mode mode)
701 if (GET_MODE (op) == mode
702 && GET_CODE (op) == MEM
703 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
705 return general_operand (op, mode);
708 /* Return true if OP is a constant that contains only one 1 in its
709 binary representation. */
712 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
714 if (GET_CODE (operand) == CONST_INT)
716 /* We really need to do this masking because 0x80 in QImode is
717 represented as -128 for example. */
718 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
725 /* Return true if OP is a constant that contains only one 0 in its
726 binary representation. */
729 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
731 if (GET_CODE (operand) == CONST_INT)
733 /* We really need to do this masking because 0x80 in QImode is
734 represented as -128 for example. */
735 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
742 /* Return true if OP is a valid call operand. */
745 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
747 if (GET_CODE (op) == MEM)
749 rtx inside = XEXP (op, 0);
750 if (register_operand (inside, Pmode))
752 if (CONSTANT_ADDRESS_P (inside))
758 /* Return 1 if an addition/subtraction of a constant integer can be
759 transformed into two consecutive adds/subs that are faster than the
760 straightforward way. Otherwise, return 0. */
763 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
765 if (GET_CODE (op) == CONST_INT)
767 HOST_WIDE_INT value = INTVAL (op);
769 /* Force VALUE to be positive so that we do not have to consider
770 the negative case. */
773 if (TARGET_H8300H || TARGET_H8300S)
775 /* A constant addition/subtraction takes 2 states in QImode,
776 4 states in HImode, and 6 states in SImode. Thus, the
777 only case we can win is when SImode is used, in which
778 case, two adds/subs are used, taking 4 states. */
788 /* We do not profit directly by splitting addition or
789 subtraction of 3 and 4. However, since these are
790 implemented as a sequence of adds or subs, they do not
791 clobber (cc0) unlike a sequence of add.b and add.x. */
802 /* Split an add of a small constant into two adds/subs insns.
804 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
805 instead of adds/subs. */
808 split_adds_subs (enum machine_mode mode, rtx *operands)
810 HOST_WIDE_INT val = INTVAL (operands[1]);
811 rtx reg = operands[0];
812 HOST_WIDE_INT sign = 1;
813 HOST_WIDE_INT amount;
814 rtx (*gen_add) (rtx, rtx, rtx);
816 /* Force VAL to be positive so that we do not have to consider the
827 gen_add = gen_addhi3;
831 gen_add = gen_addsi3;
838 /* Try different amounts in descending order. */
839 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
843 for (; val >= amount; val -= amount)
844 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
850 /* Return true if OP is a valid call operand, and OP represents
851 an operand for a small call (4 bytes instead of 6 bytes). */
854 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
856 if (GET_CODE (op) == MEM)
858 rtx inside = XEXP (op, 0);
860 /* Register indirect is a small call. */
861 if (register_operand (inside, Pmode))
864 /* A call through the function vector is a small call too. */
865 if (GET_CODE (inside) == SYMBOL_REF
866 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
869 /* Otherwise it's a large call. */
873 /* Return true if OP is a valid jump operand. */
876 jump_address_operand (rtx op, enum machine_mode mode)
878 if (GET_CODE (op) == REG)
879 return mode == Pmode;
881 if (GET_CODE (op) == MEM)
883 rtx inside = XEXP (op, 0);
884 if (register_operand (inside, Pmode))
886 if (CONSTANT_ADDRESS_P (inside))
892 /* Recognize valid operands for bit-field instructions. */
895 bit_operand (rtx op, enum machine_mode mode)
897 /* We can accept any general operand, except that MEM operands must
898 be limited to those that use addresses valid for the 'U' constraint. */
899 if (!general_operand (op, mode))
902 /* Accept any mem during RTL generation. Otherwise, the code that does
903 insv and extzv will think that we can not handle memory. However,
904 to avoid reload problems, we only accept 'U' MEM operands after RTL
905 generation. This means that any named pattern which uses this predicate
906 must force its operands to match 'U' before emitting RTL. */
908 if (GET_CODE (op) == REG)
910 if (GET_CODE (op) == SUBREG)
912 return (GET_CODE (op) == MEM
913 && EXTRA_CONSTRAINT (op, 'U'));
917 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
919 return (GET_CODE (op) == MEM
920 && EXTRA_CONSTRAINT (op, 'U'));
923 /* Handle machine specific pragmas for compatibility with existing
924 compilers for the H8/300.
926 pragma saveall generates prologue/epilogue code which saves and
927 restores all the registers on function entry.
929 pragma interrupt saves and restores all registers, and exits with
930 an rte instruction rather than an rts. A pointer to a function
931 with this attribute may be safely used in an interrupt vector. */
934 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
936 pragma_interrupt = 1;
940 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
945 /* If the next function argument with MODE and TYPE is to be passed in
946 a register, return a reg RTX for the hard register in which to pass
947 the argument. CUM represents the state after the last argument.
948 If the argument is to be pushed, NULL_RTX is returned. */
951 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
952 tree type, int named)
954 static const char *const hand_list[] = {
973 rtx result = NULL_RTX;
977 /* Never pass unnamed arguments in registers. */
981 /* Pass 3 regs worth of data in regs when user asked on the command line. */
982 if (TARGET_QUICKCALL)
985 /* If calling hand written assembler, use 4 regs of args. */
988 const char * const *p;
990 fname = XSTR (cum->libcall, 0);
992 /* See if this libcall is one of the hand coded ones. */
993 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1004 if (mode == BLKmode)
1005 size = int_size_in_bytes (type);
1007 size = GET_MODE_SIZE (mode);
1009 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1010 && cum->nbytes / UNITS_PER_WORD <= 3)
1011 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1018 h8300_and_costs (rtx x)
1022 if (GET_MODE (x) == QImode)
1025 if (GET_MODE (x) != HImode
1026 && GET_MODE (x) != SImode)
1031 operands[2] = XEXP (x, 1);
1033 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1037 h8300_shift_costs (rtx x)
1041 if (GET_MODE (x) != QImode
1042 && GET_MODE (x) != HImode
1043 && GET_MODE (x) != SImode)
1048 operands[2] = XEXP (x, 1);
1050 return compute_a_shift_length (NULL, operands) / 2;
1054 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1060 HOST_WIDE_INT n = INTVAL (x);
1062 if (-4 <= n || n <= 4)
1073 *total = 0 + (outer_code == SET);
1077 if (TARGET_H8300H || TARGET_H8300S)
1078 *total = 0 + (outer_code == SET);
1099 *total = COSTS_N_INSNS (h8300_and_costs (x));
1102 /* We say that MOD and DIV are so expensive because otherwise we'll
1103 generate some really horrible code for division of a power of two. */
1116 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1121 if (GET_MODE (x) == HImode)
1133 /* Documentation for the machine specific operand escapes:
1135 'E' like s but negative.
1136 'F' like t but negative.
1137 'G' constant just the negative
1138 'R' print operand as a byte:8 address if appropriate, else fall back to
1140 'S' print operand as a long word
1141 'T' print operand as a word
1142 'V' find the set bit, and print its number.
1143 'W' find the clear bit, and print its number.
1144 'X' print operand as a byte
1145 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1146 If this operand isn't a register, fall back to 'R' handling.
1148 'c' print the opcode corresponding to rtl
1149 'e' first word of 32 bit value - if reg, then least reg. if mem
1150 then least. if const then most sig word
1151 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1152 then +2. if const then least sig word
1153 'j' print operand as condition code.
1154 'k' print operand as reverse condition code.
1155 's' print as low byte of 16 bit value
1156 't' print as high byte of 16 bit value
1157 'w' print as low byte of 32 bit value
1158 'x' print as 2nd byte of 32 bit value
1159 'y' print as 3rd byte of 32 bit value
1160 'z' print as msb of 32 bit value
1163 /* Return assembly language string which identifies a comparison type. */
1166 cond_string (enum rtx_code code)
1195 /* Print operand X using operand code CODE to assembly language output file
1199 print_operand (FILE *file, rtx x, int code)
1201 /* This is used for communication between codes V,W,Z and Y. */
1207 switch (GET_CODE (x))
1210 fprintf (file, "%sl", names_big[REGNO (x)]);
1213 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1220 switch (GET_CODE (x))
1223 fprintf (file, "%sh", names_big[REGNO (x)]);
1226 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1233 if (GET_CODE (x) != CONST_INT)
1235 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1238 if (GET_CODE (x) == REG)
1239 fprintf (file, "%s", names_extended[REGNO (x)]);
1244 if (GET_CODE (x) == REG)
1245 fprintf (file, "%s", names_big[REGNO (x)]);
1250 bitint = exact_log2 (INTVAL (x) & 0xff);
1253 fprintf (file, "#%d", bitint);
1256 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1259 fprintf (file, "#%d", bitint);
1263 if (GET_CODE (x) == REG)
1264 fprintf (file, "%s", byte_reg (x, 0));
1271 if (GET_CODE (x) == REG)
1272 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1274 print_operand (file, x, 'R');
1278 bitint = INTVAL (x);
1279 fprintf (file, "#%d", bitint & 7);
1282 switch (GET_CODE (x))
1285 fprintf (file, "or");
1288 fprintf (file, "xor");
1291 fprintf (file, "and");
1298 switch (GET_CODE (x))
1302 fprintf (file, "%s", names_big[REGNO (x)]);
1304 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1307 print_operand (file, x, 0);
1310 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1316 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1317 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1318 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1327 switch (GET_CODE (x))
1331 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1333 fprintf (file, "%s", names_big[REGNO (x)]);
1336 x = adjust_address (x, HImode, 2);
1337 print_operand (file, x, 0);
1340 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1346 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1347 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1348 fprintf (file, "#%ld", (val & 0xffff));
1356 fputs (cond_string (GET_CODE (x)), file);
1359 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1362 if (GET_CODE (x) == CONST_INT)
1363 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1365 fprintf (file, "%s", byte_reg (x, 0));
1368 if (GET_CODE (x) == CONST_INT)
1369 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1371 fprintf (file, "%s", byte_reg (x, 1));
1374 if (GET_CODE (x) == CONST_INT)
1375 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1377 fprintf (file, "%s",
1378 byte_reg (x, TARGET_H8300 ? 2 : 0));
1381 if (GET_CODE (x) == CONST_INT)
1382 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1384 fprintf (file, "%s",
1385 byte_reg (x, TARGET_H8300 ? 3 : 1));
1388 if (GET_CODE (x) == CONST_INT)
1389 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1391 fprintf (file, "%s", byte_reg (x, 0));
1394 if (GET_CODE (x) == CONST_INT)
1395 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1397 fprintf (file, "%s", byte_reg (x, 1));
1402 switch (GET_CODE (x))
1405 switch (GET_MODE (x))
1408 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1409 fprintf (file, "%s", byte_reg (x, 0));
1410 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1411 fprintf (file, "%s", names_big[REGNO (x)]);
1415 fprintf (file, "%s", names_big[REGNO (x)]);
1419 fprintf (file, "%s", names_extended[REGNO (x)]);
1428 rtx addr = XEXP (x, 0);
1430 fprintf (file, "@");
1431 output_address (addr);
1433 /* We fall back from smaller addressing to larger
1434 addressing in various ways depending on CODE. */
1438 /* Used for mov.b and bit operations. */
1439 if (h8300_eightbit_constant_address_p (addr))
1441 fprintf (file, ":8");
1445 /* Fall through. We should not get here if we are
1446 processing bit operations on H8/300 or H8/300H
1447 because 'U' constraint does not allow bit
1448 operations on the tiny area on these machines. */
1452 /* Used for mov.w and mov.l. */
1453 if (h8300_tiny_constant_address_p (addr))
1454 fprintf (file, ":16");
1466 fprintf (file, "#");
1467 print_operand_address (file, x);
1473 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1474 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1475 fprintf (file, "#%ld", val);
1484 /* Output assembly language output for the address ADDR to FILE. */
1487 print_operand_address (FILE *file, rtx addr)
1489 switch (GET_CODE (addr))
1492 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1496 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1500 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1504 fprintf (file, "(");
1505 if (GET_CODE (XEXP (addr, 0)) == REG)
1508 print_operand_address (file, XEXP (addr, 1));
1509 fprintf (file, ",");
1510 print_operand_address (file, XEXP (addr, 0));
1515 print_operand_address (file, XEXP (addr, 0));
1516 fprintf (file, "+");
1517 print_operand_address (file, XEXP (addr, 1));
1519 fprintf (file, ")");
1524 /* Since the H8/300 only has 16 bit pointers, negative values are also
1525 those >= 32768. This happens for example with pointer minus a
1526 constant. We don't want to turn (char *p - 2) into
1527 (char *p + 65534) because loop unrolling can build upon this
1528 (IE: char *p + 131068). */
1529 int n = INTVAL (addr);
1531 n = (int) (short) n;
1532 fprintf (file, "%d", n);
1537 output_addr_const (file, addr);
1542 /* Output all insn addresses and their sizes into the assembly language
1543 output file. This is helpful for debugging whether the length attributes
1544 in the md file are correct. This is not meant to be a user selectable
1548 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1549 int num_operands ATTRIBUTE_UNUSED)
1551 /* This holds the last insn address. */
1552 static int last_insn_address = 0;
1554 const int uid = INSN_UID (insn);
1556 if (TARGET_ADDRESSES)
1558 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1559 INSN_ADDRESSES (uid) - last_insn_address);
1560 last_insn_address = INSN_ADDRESSES (uid);
1564 /* Prepare for an SI sized move. */
1567 h8300_expand_movsi (rtx operands[])
1569 rtx src = operands[1];
1570 rtx dst = operands[0];
1571 if (!reload_in_progress && !reload_completed)
1573 if (!register_operand (dst, GET_MODE (dst)))
1575 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1576 emit_move_insn (tmp, src);
1583 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1584 Define the offset between two registers, one to be eliminated, and
1585 the other its replacement, at the start of a routine. */
1588 h8300_initial_elimination_offset (int from, int to)
1590 /* The number of bytes that the return address takes on the stack. */
1591 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1593 /* The number of bytes that the saved frame pointer takes on the stack. */
1594 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1596 /* The number of bytes that the saved registers, excluding the frame
1597 pointer, take on the stack. */
1598 int saved_regs_size = 0;
1600 /* The number of bytes that the locals takes on the stack. */
1601 int frame_size = round_frame_size (get_frame_size ());
1605 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1606 if (WORD_REG_USED (regno))
1607 saved_regs_size += UNITS_PER_WORD;
1609 /* Adjust saved_regs_size because the above loop took the frame
1610 pointer int account. */
1611 saved_regs_size -= fp_size;
1613 if (to == HARD_FRAME_POINTER_REGNUM)
1617 case ARG_POINTER_REGNUM:
1618 return pc_size + fp_size;
1619 case RETURN_ADDRESS_POINTER_REGNUM:
1621 case FRAME_POINTER_REGNUM:
1622 return -saved_regs_size;
1627 else if (to == STACK_POINTER_REGNUM)
1631 case ARG_POINTER_REGNUM:
1632 return pc_size + saved_regs_size + frame_size;
1633 case RETURN_ADDRESS_POINTER_REGNUM:
1634 return saved_regs_size + frame_size;
1635 case FRAME_POINTER_REGNUM:
1646 h8300_return_addr_rtx (int count, rtx frame)
1651 ret = gen_rtx_MEM (Pmode,
1652 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1653 else if (flag_omit_frame_pointer)
1656 ret = gen_rtx_MEM (Pmode,
1657 memory_address (Pmode,
1658 plus_constant (frame, UNITS_PER_WORD)));
1659 set_mem_alias_set (ret, get_frame_alias_set ());
1663 /* Update the condition code from the insn. */
1666 notice_update_cc (rtx body, rtx insn)
1670 switch (get_attr_cc (insn))
1673 /* Insn does not affect CC at all. */
1677 /* Insn does not change CC, but the 0'th operand has been changed. */
1678 if (cc_status.value1 != 0
1679 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1680 cc_status.value1 = 0;
1681 if (cc_status.value2 != 0
1682 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1683 cc_status.value2 = 0;
1687 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1688 The V flag is unusable. The C flag may or may not be known but
1689 that's ok because alter_cond will change tests to use EQ/NE. */
1691 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1692 set = single_set (insn);
1693 cc_status.value1 = SET_SRC (set);
1694 if (SET_DEST (set) != cc0_rtx)
1695 cc_status.value2 = SET_DEST (set);
1699 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1700 The C flag may or may not be known but that's ok because
1701 alter_cond will change tests to use EQ/NE. */
1703 cc_status.flags |= CC_NO_CARRY;
1704 set = single_set (insn);
1705 cc_status.value1 = SET_SRC (set);
1706 if (SET_DEST (set) != cc0_rtx)
1708 /* If the destination is STRICT_LOW_PART, strip off
1710 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1711 cc_status.value2 = XEXP (SET_DEST (set), 0);
1713 cc_status.value2 = SET_DEST (set);
1718 /* The insn is a compare instruction. */
1720 cc_status.value1 = SET_SRC (body);
1724 /* Insn doesn't leave CC in a usable state. */
1730 /* Return nonzero if X is a stack pointer. */
1733 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1735 return x == stack_pointer_rtx;
1738 /* Return nonzero if X is a constant whose absolute value is greater
1742 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1744 return (GET_CODE (x) == CONST_INT
1745 && abs (INTVAL (x)) > 2);
1748 /* Return nonzero if X is a constant whose absolute value is no
1752 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1754 return (GET_CODE (x) == CONST_INT
1755 && abs (INTVAL (x)) >= 8);
1758 /* Return nonzero if X is a constant expressible in QImode. */
1761 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1763 return (GET_CODE (x) == CONST_INT
1764 && (INTVAL (x) & 0xff) == INTVAL (x));
1767 /* Return nonzero if X is a constant expressible in HImode. */
1770 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1772 return (GET_CODE (x) == CONST_INT
1773 && (INTVAL (x) & 0xffff) == INTVAL (x));
1776 /* Return nonzero if X is a constant suitable for inc/dec. */
1779 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1781 return (GET_CODE (x) == CONST_INT
1782 && (CONST_OK_FOR_M (INTVAL (x))
1783 || CONST_OK_FOR_O (INTVAL (x))));
1786 /* Return nonzero if X is either EQ or NE. */
1789 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1791 enum rtx_code code = GET_CODE (x);
1793 return (code == EQ || code == NE);
1796 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1799 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1801 enum rtx_code code = GET_CODE (x);
1803 return (code == GT || code == LE || code == GTU || code == LEU);
1806 /* Return nonzero if X is either GTU or LEU. */
1809 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1811 enum rtx_code code = GET_CODE (x);
1813 return (code == GTU || code == LEU);
1816 /* Return nonzero if X is either IOR or XOR. */
1819 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1821 enum rtx_code code = GET_CODE (x);
1823 return (code == IOR || code == XOR);
1826 /* Recognize valid operators for bit instructions. */
1829 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1831 enum rtx_code code = GET_CODE (x);
1838 /* Return the length of mov instruction. */
1841 compute_mov_length (rtx *operands)
1843 /* If the mov instruction involves a memory operand, we compute the
1844 length, assuming the largest addressing mode is used, and then
1845 adjust later in the function. Otherwise, we compute and return
1846 the exact length in one step. */
1847 enum machine_mode mode = GET_MODE (operands[0]);
1848 rtx dest = operands[0];
1849 rtx src = operands[1];
1852 if (GET_CODE (src) == MEM)
1853 addr = XEXP (src, 0);
1854 else if (GET_CODE (dest) == MEM)
1855 addr = XEXP (dest, 0);
1861 unsigned int base_length;
1866 if (addr == NULL_RTX)
1869 /* The eightbit addressing is available only in QImode, so
1870 go ahead and take care of it. */
1871 if (h8300_eightbit_constant_address_p (addr))
1878 if (addr == NULL_RTX)
1883 if (src == const0_rtx)
1893 if (addr == NULL_RTX)
1898 if (GET_CODE (src) == CONST_INT)
1900 if (src == const0_rtx)
1903 if ((INTVAL (src) & 0xffff) == 0)
1906 if ((INTVAL (src) & 0xffff) == 0)
1909 if ((INTVAL (src) & 0xffff)
1910 == ((INTVAL (src) >> 16) & 0xffff))
1920 if (addr == NULL_RTX)
1925 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1938 /* Adjust the length based on the addressing mode used.
1939 Specifically, we subtract the difference between the actual
1940 length and the longest one, which is @(d:16,Rs). For SImode
1941 and SFmode, we double the adjustment because two mov.w are
1942 used to do the job. */
1944 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1945 if (GET_CODE (addr) == PRE_DEC
1946 || GET_CODE (addr) == POST_INC)
1948 if (mode == QImode || mode == HImode)
1949 return base_length - 2;
1951 /* In SImode and SFmode, we use two mov.w instructions, so
1952 double the adjustment. */
1953 return base_length - 4;
1956 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1957 in SImode and SFmode, the second mov.w involves an address
1958 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1960 if (GET_CODE (addr) == REG)
1961 return base_length - 2;
1967 unsigned int base_length;
1972 if (addr == NULL_RTX)
1975 /* The eightbit addressing is available only in QImode, so
1976 go ahead and take care of it. */
1977 if (h8300_eightbit_constant_address_p (addr))
1984 if (addr == NULL_RTX)
1989 if (src == const0_rtx)
1999 if (addr == NULL_RTX)
2003 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2009 if (GET_CODE (src) == CONST_INT)
2011 int val = INTVAL (src);
2016 if (val == (val & 0x00ff) || val == (val & 0xff00))
2019 switch (val & 0xffffffff)
2040 if (addr == NULL_RTX)
2045 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2058 /* Adjust the length based on the addressing mode used.
2059 Specifically, we subtract the difference between the actual
2060 length and the longest one, which is @(d:24,ERs). */
2062 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2063 if (GET_CODE (addr) == PRE_DEC
2064 || GET_CODE (addr) == POST_INC)
2065 return base_length - 6;
2067 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2068 if (GET_CODE (addr) == REG)
2069 return base_length - 6;
2071 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2073 if (GET_CODE (addr) == PLUS
2074 && GET_CODE (XEXP (addr, 0)) == REG
2075 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2076 && INTVAL (XEXP (addr, 1)) > -32768
2077 && INTVAL (XEXP (addr, 1)) < 32767)
2078 return base_length - 4;
2080 /* @aa:16 is 4 bytes shorter than the longest. */
2081 if (h8300_tiny_constant_address_p (addr))
2082 return base_length - 4;
2084 /* @aa:24 is 2 bytes shorter than the longest. */
2085 if (CONSTANT_P (addr))
2086 return base_length - 2;
2093 output_plussi (rtx *operands)
2095 enum machine_mode mode = GET_MODE (operands[0]);
2102 if (GET_CODE (operands[2]) == REG)
2103 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2105 if (GET_CODE (operands[2]) == CONST_INT)
2107 HOST_WIDE_INT n = INTVAL (operands[2]);
2109 if ((n & 0xffffff) == 0)
2110 return "add\t%z2,%z0";
2111 if ((n & 0xffff) == 0)
2112 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2113 if ((n & 0xff) == 0)
2114 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2117 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2121 if (GET_CODE (operands[2]) == REG)
2122 return "add.l\t%S2,%S0";
2124 if (GET_CODE (operands[2]) == CONST_INT)
2126 HOST_WIDE_INT intval = INTVAL (operands[2]);
2128 /* See if we can finish with 2 bytes. */
2130 switch ((unsigned int) intval & 0xffffffff)
2135 return "adds\t%2,%S0";
2140 return "subs\t%G2,%S0";
2144 operands[2] = GEN_INT (intval >> 16);
2145 return "inc.w\t%2,%e0";
2149 operands[2] = GEN_INT (intval >> 16);
2150 return "dec.w\t%G2,%e0";
2153 /* See if we can finish with 4 bytes. */
2154 if ((intval & 0xffff) == 0)
2156 operands[2] = GEN_INT (intval >> 16);
2157 return "add.w\t%2,%e0";
2161 return "add.l\t%S2,%S0";
2166 compute_plussi_length (rtx *operands)
2168 enum machine_mode mode = GET_MODE (operands[0]);
2175 if (GET_CODE (operands[2]) == REG)
2178 if (GET_CODE (operands[2]) == CONST_INT)
2180 HOST_WIDE_INT n = INTVAL (operands[2]);
2182 if ((n & 0xffffff) == 0)
2184 if ((n & 0xffff) == 0)
2186 if ((n & 0xff) == 0)
2194 if (GET_CODE (operands[2]) == REG)
2197 if (GET_CODE (operands[2]) == CONST_INT)
2199 HOST_WIDE_INT intval = INTVAL (operands[2]);
2201 /* See if we can finish with 2 bytes. */
2203 switch ((unsigned int) intval & 0xffffffff)
2224 /* See if we can finish with 4 bytes. */
2225 if ((intval & 0xffff) == 0)
2234 compute_plussi_cc (rtx *operands)
2236 enum machine_mode mode = GET_MODE (operands[0]);
2247 if (GET_CODE (operands[2]) == REG)
2250 if (GET_CODE (operands[2]) == CONST_INT)
2252 HOST_WIDE_INT intval = INTVAL (operands[2]);
2254 /* See if we can finish with 2 bytes. */
2256 switch ((unsigned int) intval & 0xffffffff)
2261 return CC_NONE_0HIT;
2266 return CC_NONE_0HIT;
2277 /* See if we can finish with 4 bytes. */
2278 if ((intval & 0xffff) == 0)
2287 output_logical_op (enum machine_mode mode, rtx *operands)
2289 /* Figure out the logical op that we need to perform. */
2290 enum rtx_code code = GET_CODE (operands[3]);
2291 /* Pretend that every byte is affected if both operands are registers. */
2292 const unsigned HOST_WIDE_INT intval =
2293 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2294 ? INTVAL (operands[2]) : 0x55555555);
2295 /* The determinant of the algorithm. If we perform an AND, 0
2296 affects a bit. Otherwise, 1 affects a bit. */
2297 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2298 /* Break up DET into pieces. */
2299 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2300 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2301 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2302 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2303 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2304 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2305 int lower_half_easy_p = 0;
2306 int upper_half_easy_p = 0;
2307 /* The name of an insn. */
2329 /* First, see if we can finish with one insn. */
2330 if ((TARGET_H8300H || TARGET_H8300S)
2334 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2335 output_asm_insn (insn_buf, operands);
2339 /* Take care of the lower byte. */
2342 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2343 output_asm_insn (insn_buf, operands);
2345 /* Take care of the upper byte. */
2348 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2349 output_asm_insn (insn_buf, operands);
2354 if (TARGET_H8300H || TARGET_H8300S)
2356 /* Determine if the lower half can be taken care of in no more
2358 lower_half_easy_p = (b0 == 0
2360 || (code != IOR && w0 == 0xffff));
2362 /* Determine if the upper half can be taken care of in no more
2364 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2365 || (code == AND && w1 == 0xff00));
2368 /* Check if doing everything with one insn is no worse than
2369 using multiple insns. */
2370 if ((TARGET_H8300H || TARGET_H8300S)
2371 && w0 != 0 && w1 != 0
2372 && !(lower_half_easy_p && upper_half_easy_p)
2373 && !(code == IOR && w1 == 0xffff
2374 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2376 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2377 output_asm_insn (insn_buf, operands);
2381 /* Take care of the lower and upper words individually. For
2382 each word, we try different methods in the order of
2384 1) the special insn (in case of AND or XOR),
2385 2) the word-wise insn, and
2386 3) The byte-wise insn. */
2388 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2389 output_asm_insn ((code == AND)
2390 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2392 else if ((TARGET_H8300H || TARGET_H8300S)
2396 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2397 output_asm_insn (insn_buf, operands);
2403 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2404 output_asm_insn (insn_buf, operands);
2408 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2409 output_asm_insn (insn_buf, operands);
2414 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2415 output_asm_insn ((code == AND)
2416 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2418 else if ((TARGET_H8300H || TARGET_H8300S)
2421 && (w0 & 0x8000) != 0)
2423 output_asm_insn ("exts.l\t%S0", operands);
2425 else if ((TARGET_H8300H || TARGET_H8300S)
2429 output_asm_insn ("extu.w\t%e0", operands);
2431 else if (TARGET_H8300H || TARGET_H8300S)
2435 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2436 output_asm_insn (insn_buf, operands);
2443 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2444 output_asm_insn (insn_buf, operands);
2448 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2449 output_asm_insn (insn_buf, operands);
2461 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2463 /* Figure out the logical op that we need to perform. */
2464 enum rtx_code code = GET_CODE (operands[3]);
2465 /* Pretend that every byte is affected if both operands are registers. */
2466 const unsigned HOST_WIDE_INT intval =
2467 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2468 ? INTVAL (operands[2]) : 0x55555555);
2469 /* The determinant of the algorithm. If we perform an AND, 0
2470 affects a bit. Otherwise, 1 affects a bit. */
2471 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2472 /* Break up DET into pieces. */
2473 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2474 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2475 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2476 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2477 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2478 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2479 int lower_half_easy_p = 0;
2480 int upper_half_easy_p = 0;
2482 unsigned int length = 0;
2487 /* First, see if we can finish with one insn. */
2488 if ((TARGET_H8300H || TARGET_H8300S)
2492 if (REG_P (operands[2]))
2499 /* Take care of the lower byte. */
2503 /* Take care of the upper byte. */
2509 if (TARGET_H8300H || TARGET_H8300S)
2511 /* Determine if the lower half can be taken care of in no more
2513 lower_half_easy_p = (b0 == 0
2515 || (code != IOR && w0 == 0xffff));
2517 /* Determine if the upper half can be taken care of in no more
2519 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2520 || (code == AND && w1 == 0xff00));
2523 /* Check if doing everything with one insn is no worse than
2524 using multiple insns. */
2525 if ((TARGET_H8300H || TARGET_H8300S)
2526 && w0 != 0 && w1 != 0
2527 && !(lower_half_easy_p && upper_half_easy_p)
2528 && !(code == IOR && w1 == 0xffff
2529 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2531 if (REG_P (operands[2]))
2538 /* Take care of the lower and upper words individually. For
2539 each word, we try different methods in the order of
2541 1) the special insn (in case of AND or XOR),
2542 2) the word-wise insn, and
2543 3) The byte-wise insn. */
2545 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2549 else if ((TARGET_H8300H || TARGET_H8300S)
2565 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2569 else if ((TARGET_H8300H || TARGET_H8300S)
2572 && (w0 & 0x8000) != 0)
2576 else if ((TARGET_H8300H || TARGET_H8300S)
2582 else if (TARGET_H8300H || TARGET_H8300S)
2604 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2606 /* Figure out the logical op that we need to perform. */
2607 enum rtx_code code = GET_CODE (operands[3]);
2608 /* Pretend that every byte is affected if both operands are registers. */
2609 const unsigned HOST_WIDE_INT intval =
2610 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2611 ? INTVAL (operands[2]) : 0x55555555);
2612 /* The determinant of the algorithm. If we perform an AND, 0
2613 affects a bit. Otherwise, 1 affects a bit. */
2614 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2615 /* Break up DET into pieces. */
2616 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2617 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2618 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2619 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2620 int lower_half_easy_p = 0;
2621 int upper_half_easy_p = 0;
2622 /* Condition code. */
2623 enum attr_cc cc = CC_CLOBBER;
2628 /* First, see if we can finish with one insn. */
2629 if ((TARGET_H8300H || TARGET_H8300S)
2637 if (TARGET_H8300H || TARGET_H8300S)
2639 /* Determine if the lower half can be taken care of in no more
2641 lower_half_easy_p = (b0 == 0
2643 || (code != IOR && w0 == 0xffff));
2645 /* Determine if the upper half can be taken care of in no more
2647 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2648 || (code == AND && w1 == 0xff00));
2651 /* Check if doing everything with one insn is no worse than
2652 using multiple insns. */
2653 if ((TARGET_H8300H || TARGET_H8300S)
2654 && w0 != 0 && w1 != 0
2655 && !(lower_half_easy_p && upper_half_easy_p)
2656 && !(code == IOR && w1 == 0xffff
2657 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2663 if ((TARGET_H8300H || TARGET_H8300S)
2666 && (w0 & 0x8000) != 0)
2680 We devote a fair bit of code to getting efficient shifts since we
2681 can only shift one bit at a time on the H8/300 and H8/300H and only
2682 one or two bits at a time on the H8S.
2684 All shift code falls into one of the following ways of
2687 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2688 when a straight line shift is about the same size or smaller than
2691 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2692 off the bits we don't need. This is used when only a few of the
2693 bits in the original value will survive in the shifted value.
2695 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2696 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2697 shifts can be added if the shift count is slightly more than 8 or
2698 16. This case also includes other oddballs that are not worth
2701 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2703 For each shift count, we try to use code that has no trade-off
2704 between code size and speed whenever possible.
2706 If the trade-off is unavoidable, we try to be reasonable.
2707 Specifically, the fastest version is one instruction longer than
2708 the shortest version, we take the fastest version. We also provide
2709 the use a way to switch back to the shortest version with -Os.
2711 For the details of the shift algorithms for various shift counts,
2712 refer to shift_alg_[qhs]i. */
2715 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2717 switch (GET_CODE (x))
2729 /* Emit code to do shifts. */
2732 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2734 emit_move_insn (operands[0], operands[1]);
2736 /* Need a loop to get all the bits we want - we generate the
2737 code at emit time, but need to allocate a scratch reg now. */
2739 emit_insn (gen_rtx_PARALLEL
2742 gen_rtx_SET (VOIDmode, operands[0],
2743 gen_rtx_fmt_ee (code, mode,
2744 operands[0], operands[2])),
2745 gen_rtx_CLOBBER (VOIDmode,
2746 gen_rtx_SCRATCH (QImode)))));
2749 /* Symbols of the various modes which can be used as indices. */
2753 QIshift, HIshift, SIshift
2756 /* For single bit shift insns, record assembler and what bits of the
2757 condition code are valid afterwards (represented as various CC_FOO
2758 bits, 0 means CC isn't left in a usable state). */
2762 const char *const assembler;
2766 /* Assembler instruction shift table.
2768 These tables are used to look up the basic shifts.
2769 They are indexed by cpu, shift_type, and mode. */
2771 static const struct shift_insn shift_one[2][3][3] =
2777 { "shll\t%X0", CC_SET_ZNV },
2778 { "add.w\t%T0,%T0", CC_SET_ZN },
2779 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2781 /* SHIFT_LSHIFTRT */
2783 { "shlr\t%X0", CC_SET_ZNV },
2784 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2785 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2787 /* SHIFT_ASHIFTRT */
2789 { "shar\t%X0", CC_SET_ZNV },
2790 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2791 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2798 { "shll.b\t%X0", CC_SET_ZNV },
2799 { "shll.w\t%T0", CC_SET_ZNV },
2800 { "shll.l\t%S0", CC_SET_ZNV }
2802 /* SHIFT_LSHIFTRT */
2804 { "shlr.b\t%X0", CC_SET_ZNV },
2805 { "shlr.w\t%T0", CC_SET_ZNV },
2806 { "shlr.l\t%S0", CC_SET_ZNV }
2808 /* SHIFT_ASHIFTRT */
2810 { "shar.b\t%X0", CC_SET_ZNV },
2811 { "shar.w\t%T0", CC_SET_ZNV },
2812 { "shar.l\t%S0", CC_SET_ZNV }
2817 static const struct shift_insn shift_two[3][3] =
2821 { "shll.b\t#2,%X0", CC_SET_ZNV },
2822 { "shll.w\t#2,%T0", CC_SET_ZNV },
2823 { "shll.l\t#2,%S0", CC_SET_ZNV }
2825 /* SHIFT_LSHIFTRT */
2827 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2828 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2829 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2831 /* SHIFT_ASHIFTRT */
2833 { "shar.b\t#2,%X0", CC_SET_ZNV },
2834 { "shar.w\t#2,%T0", CC_SET_ZNV },
2835 { "shar.l\t#2,%S0", CC_SET_ZNV }
2839 /* Rotates are organized by which shift they'll be used in implementing.
2840 There's no need to record whether the cc is valid afterwards because
2841 it is the AND insn that will decide this. */
2843 static const char *const rotate_one[2][3][3] =
2850 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2853 /* SHIFT_LSHIFTRT */
2856 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2859 /* SHIFT_ASHIFTRT */
2862 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2874 /* SHIFT_LSHIFTRT */
2880 /* SHIFT_ASHIFTRT */
2889 static const char *const rotate_two[3][3] =
2897 /* SHIFT_LSHIFTRT */
2903 /* SHIFT_ASHIFTRT */
2912 /* Shift algorithm. */
2915 /* The number of bits to be shifted by shift1 and shift2. Valid
2916 when ALG is SHIFT_SPECIAL. */
2917 unsigned int remainder;
2919 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2920 const char *special;
2922 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2923 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2926 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2927 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2930 /* CC status for SHIFT_INLINE. */
2933 /* CC status for SHIFT_SPECIAL. */
2937 static void get_shift_alg (enum shift_type,
2938 enum shift_mode, unsigned int,
2939 struct shift_info *);
2941 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2942 best algorithm for doing the shift. The assembler code is stored
2943 in the pointers in INFO. We achieve the maximum efficiency in most
2944 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2945 SImode in particular have a lot of room to optimize.
2947 We first determine the strategy of the shift algorithm by a table
2948 lookup. If that tells us to use a hand crafted assembly code, we
2949 go into the big switch statement to find what that is. Otherwise,
2950 we resort to a generic way, such as inlining. In either case, the
2951 result is returned through INFO. */
2954 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2955 unsigned int count, struct shift_info *info)
2959 /* Find the target CPU. */
2962 else if (TARGET_H8300H)
2967 /* Find the shift algorithm. */
2968 info->alg = SHIFT_LOOP;
2972 if (count < GET_MODE_BITSIZE (QImode))
2973 info->alg = shift_alg_qi[cpu][shift_type][count];
2977 if (count < GET_MODE_BITSIZE (HImode))
2978 info->alg = shift_alg_hi[cpu][shift_type][count];
2982 if (count < GET_MODE_BITSIZE (SImode))
2983 info->alg = shift_alg_si[cpu][shift_type][count];
2990 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2994 info->remainder = count;
2998 /* It is up to the caller to know that looping clobbers cc. */
2999 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3000 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3001 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3005 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3006 info->shift2 = rotate_two[shift_type][shift_mode];
3007 info->cc_inline = CC_CLOBBER;
3011 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3012 info->remainder = 0;
3013 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3014 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3015 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3016 info->cc_special = CC_CLOBBER;
3020 /* Here we only deal with SHIFT_SPECIAL. */
3024 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3025 through the entire value. */
3026 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3028 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3040 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3042 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3044 case SHIFT_LSHIFTRT:
3046 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3048 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3050 case SHIFT_ASHIFTRT:
3051 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3055 else if ((8 <= count && count <= 13)
3056 || (TARGET_H8300S && count == 14))
3058 info->remainder = count - 8;
3063 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3065 case SHIFT_LSHIFTRT:
3068 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3069 info->shift1 = "shlr.b\t%s0";
3070 info->cc_inline = CC_SET_ZNV;
3074 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3075 info->cc_special = CC_SET_ZNV;
3078 case SHIFT_ASHIFTRT:
3081 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3082 info->shift1 = "shar.b\t%s0";
3086 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3087 info->cc_special = CC_SET_ZNV;
3092 else if (count == 14)
3098 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3100 case SHIFT_LSHIFTRT:
3102 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3104 case SHIFT_ASHIFTRT:
3106 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3107 else if (TARGET_H8300H)
3109 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3110 info->cc_special = CC_SET_ZNV;
3112 else /* TARGET_H8300S */
3117 else if (count == 15)
3122 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3124 case SHIFT_LSHIFTRT:
3125 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3127 case SHIFT_ASHIFTRT:
3128 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3135 if (TARGET_H8300 && 8 <= count && count <= 9)
3137 info->remainder = count - 8;
3142 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3144 case SHIFT_LSHIFTRT:
3145 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3146 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3148 case SHIFT_ASHIFTRT:
3149 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3153 else if (count == 8 && !TARGET_H8300)
3158 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3160 case SHIFT_LSHIFTRT:
3161 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3163 case SHIFT_ASHIFTRT:
3164 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3168 else if (count == 15 && TARGET_H8300)
3174 case SHIFT_LSHIFTRT:
3175 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3177 case SHIFT_ASHIFTRT:
3178 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3182 else if (count == 15 && !TARGET_H8300)
3187 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3188 info->cc_special = CC_SET_ZNV;
3190 case SHIFT_LSHIFTRT:
3191 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3192 info->cc_special = CC_SET_ZNV;
3194 case SHIFT_ASHIFTRT:
3198 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3199 || (TARGET_H8300H && 16 <= count && count <= 19)
3200 || (TARGET_H8300S && 16 <= count && count <= 21))
3202 info->remainder = count - 16;
3207 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3209 info->shift1 = "add.w\t%e0,%e0";
3211 case SHIFT_LSHIFTRT:
3214 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3215 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3219 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3220 info->cc_special = CC_SET_ZNV;
3223 case SHIFT_ASHIFTRT:
3226 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3227 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3231 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3232 info->cc_special = CC_SET_ZNV;
3237 else if (TARGET_H8300 && 24 <= count && count <= 28)
3239 info->remainder = count - 24;
3244 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3245 info->shift1 = "shll.b\t%z0";
3246 info->cc_inline = CC_SET_ZNV;
3248 case SHIFT_LSHIFTRT:
3249 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3250 info->shift1 = "shlr.b\t%w0";
3251 info->cc_inline = CC_SET_ZNV;
3253 case SHIFT_ASHIFTRT:
3254 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3255 info->shift1 = "shar.b\t%w0";
3256 info->cc_inline = CC_SET_ZNV;
3260 else if ((TARGET_H8300H && count == 24)
3261 || (TARGET_H8300S && 24 <= count && count <= 25))
3263 info->remainder = count - 24;
3268 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3270 case SHIFT_LSHIFTRT:
3271 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3272 info->cc_special = CC_SET_ZNV;
3274 case SHIFT_ASHIFTRT:
3275 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3276 info->cc_special = CC_SET_ZNV;
3280 else if (!TARGET_H8300 && count == 28)
3286 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3288 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3290 case SHIFT_LSHIFTRT:
3293 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3294 info->cc_special = CC_SET_ZNV;
3297 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3299 case SHIFT_ASHIFTRT:
3303 else if (!TARGET_H8300 && count == 29)
3309 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3311 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3313 case SHIFT_LSHIFTRT:
3316 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3317 info->cc_special = CC_SET_ZNV;
3321 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3322 info->cc_special = CC_SET_ZNV;
3325 case SHIFT_ASHIFTRT:
3329 else if (!TARGET_H8300 && count == 30)
3335 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3337 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3339 case SHIFT_LSHIFTRT:
3341 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3343 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3345 case SHIFT_ASHIFTRT:
3349 else if (count == 31)
3356 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3358 case SHIFT_LSHIFTRT:
3359 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3361 case SHIFT_ASHIFTRT:
3362 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3371 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3372 info->cc_special = CC_SET_ZNV;
3374 case SHIFT_LSHIFTRT:
3375 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3376 info->cc_special = CC_SET_ZNV;
3378 case SHIFT_ASHIFTRT:
3379 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3380 info->cc_special = CC_SET_ZNV;
3393 info->shift2 = NULL;
3396 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3397 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3400 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3405 if (GET_MODE_BITSIZE (mode) <= count)
3408 /* Find out the target CPU. */
3411 else if (TARGET_H8300H)
3416 /* Find the shift algorithm. */
3420 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3421 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3422 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3426 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3427 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3428 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3432 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3433 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3434 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3441 /* On H8/300H, count == 8 uses a scratch register. */
3442 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3443 || (TARGET_H8300H && mode == SImode && count == 8));
3446 /* Emit the assembler code for doing shifts. */
3449 output_a_shift (rtx *operands)
3451 static int loopend_lab;
3452 rtx shift = operands[3];
3453 enum machine_mode mode = GET_MODE (shift);
3454 enum rtx_code code = GET_CODE (shift);
3455 enum shift_type shift_type;
3456 enum shift_mode shift_mode;
3457 struct shift_info info;
3464 shift_mode = QIshift;
3467 shift_mode = HIshift;
3470 shift_mode = SIshift;
3479 shift_type = SHIFT_ASHIFTRT;
3482 shift_type = SHIFT_LSHIFTRT;
3485 shift_type = SHIFT_ASHIFT;
3491 if (GET_CODE (operands[2]) != CONST_INT)
3493 /* This case must be taken care of by one of the two splitters
3494 that convert a variable shift into a loop. */
3499 int n = INTVAL (operands[2]);
3501 /* If the count is negative, make it 0. */
3504 /* If the count is too big, truncate it.
3505 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3506 do the intuitive thing. */
3507 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3508 n = GET_MODE_BITSIZE (mode);
3510 get_shift_alg (shift_type, shift_mode, n, &info);
3515 output_asm_insn (info.special, operands);
3521 /* Emit two bit shifts first. */
3522 if (info.shift2 != NULL)
3524 for (; n > 1; n -= 2)
3525 output_asm_insn (info.shift2, operands);
3528 /* Now emit one bit shifts for any residual. */
3530 output_asm_insn (info.shift1, operands);
3535 int m = GET_MODE_BITSIZE (mode) - n;
3536 const int mask = (shift_type == SHIFT_ASHIFT
3537 ? ((1 << m) - 1) << n
3541 /* Not all possibilities of rotate are supported. They shouldn't
3542 be generated, but let's watch for 'em. */
3543 if (info.shift1 == 0)
3546 /* Emit two bit rotates first. */
3547 if (info.shift2 != NULL)
3549 for (; m > 1; m -= 2)
3550 output_asm_insn (info.shift2, operands);
3553 /* Now single bit rotates for any residual. */
3555 output_asm_insn (info.shift1, operands);
3557 /* Now mask off the high bits. */
3559 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3560 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3561 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3565 output_asm_insn (insn_buf, operands);
3570 /* A loop to shift by a "large" constant value.
3571 If we have shift-by-2 insns, use them. */
3572 if (info.shift2 != NULL)
3574 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3575 names_big[REGNO (operands[4])]);
3576 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3577 output_asm_insn (info.shift2, operands);
3578 output_asm_insn ("add #0xff,%X4", operands);
3579 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3581 output_asm_insn (info.shift1, operands);
3585 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3586 names_big[REGNO (operands[4])]);
3587 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3588 output_asm_insn (info.shift1, operands);
3589 output_asm_insn ("add #0xff,%X4", operands);
3590 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3601 h8300_asm_insn_count (const char *template)
3603 unsigned int count = 1;
3605 for (; *template; template++)
3606 if (*template == '\n')
3613 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3615 rtx shift = operands[3];
3616 enum machine_mode mode = GET_MODE (shift);
3617 enum rtx_code code = GET_CODE (shift);
3618 enum shift_type shift_type;
3619 enum shift_mode shift_mode;
3620 struct shift_info info;
3621 unsigned int wlength = 0;
3626 shift_mode = QIshift;
3629 shift_mode = HIshift;
3632 shift_mode = SIshift;
3641 shift_type = SHIFT_ASHIFTRT;
3644 shift_type = SHIFT_LSHIFTRT;
3647 shift_type = SHIFT_ASHIFT;
3653 if (GET_CODE (operands[2]) != CONST_INT)
3655 /* Get the assembler code to do one shift. */
3656 get_shift_alg (shift_type, shift_mode, 1, &info);
3658 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3662 int n = INTVAL (operands[2]);
3664 /* If the count is negative, make it 0. */
3667 /* If the count is too big, truncate it.
3668 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3669 do the intuitive thing. */
3670 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3671 n = GET_MODE_BITSIZE (mode);
3673 get_shift_alg (shift_type, shift_mode, n, &info);
3678 wlength += h8300_asm_insn_count (info.special);
3680 /* Every assembly instruction used in SHIFT_SPECIAL case
3681 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3682 see xor.l, we just pretend that xor.l counts as two insns
3683 so that the insn length will be computed correctly. */
3684 if (strstr (info.special, "xor.l") != NULL)
3692 if (info.shift2 != NULL)
3694 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3698 wlength += h8300_asm_insn_count (info.shift1) * n;
3704 int m = GET_MODE_BITSIZE (mode) - n;
3706 /* Not all possibilities of rotate are supported. They shouldn't
3707 be generated, but let's watch for 'em. */
3708 if (info.shift1 == 0)
3711 if (info.shift2 != NULL)
3713 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3717 wlength += h8300_asm_insn_count (info.shift1) * m;
3719 /* Now mask off the high bits. */
3740 /* A loop to shift by a "large" constant value.
3741 If we have shift-by-2 insns, use them. */
3742 if (info.shift2 != NULL)
3744 wlength += 3 + h8300_asm_insn_count (info.shift2);
3746 wlength += h8300_asm_insn_count (info.shift1);
3750 wlength += 3 + h8300_asm_insn_count (info.shift1);
3761 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3763 rtx shift = operands[3];
3764 enum machine_mode mode = GET_MODE (shift);
3765 enum rtx_code code = GET_CODE (shift);
3766 enum shift_type shift_type;
3767 enum shift_mode shift_mode;
3768 struct shift_info info;
3773 shift_mode = QIshift;
3776 shift_mode = HIshift;
3779 shift_mode = SIshift;
3788 shift_type = SHIFT_ASHIFTRT;
3791 shift_type = SHIFT_LSHIFTRT;
3794 shift_type = SHIFT_ASHIFT;
3800 if (GET_CODE (operands[2]) != CONST_INT)
3802 /* This case must be taken care of by one of the two splitters
3803 that convert a variable shift into a loop. */
3808 int n = INTVAL (operands[2]);
3810 /* If the count is negative, make it 0. */
3813 /* If the count is too big, truncate it.
3814 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3815 do the intuitive thing. */
3816 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3817 n = GET_MODE_BITSIZE (mode);
3819 get_shift_alg (shift_type, shift_mode, n, &info);
3824 if (info.remainder == 0)
3825 return info.cc_special;
3830 return info.cc_inline;
3833 /* This case always ends with an and instruction. */
3837 /* A loop to shift by a "large" constant value.
3838 If we have shift-by-2 insns, use them. */
3839 if (info.shift2 != NULL)
3842 return info.cc_inline;
3852 /* A rotation by a non-constant will cause a loop to be generated, in
3853 which a rotation by one bit is used. A rotation by a constant,
3854 including the one in the loop, will be taken care of by
3855 output_a_rotate () at the insn emit time. */
3858 expand_a_rotate (enum rtx_code code, rtx operands[])
3860 rtx dst = operands[0];
3861 rtx src = operands[1];
3862 rtx rotate_amount = operands[2];
3863 enum machine_mode mode = GET_MODE (dst);
3866 /* We rotate in place. */
3867 emit_move_insn (dst, src);
3869 if (GET_CODE (rotate_amount) != CONST_INT)
3871 rtx counter = gen_reg_rtx (QImode);
3872 rtx start_label = gen_label_rtx ();
3873 rtx end_label = gen_label_rtx ();
3875 /* If the rotate amount is less than or equal to 0,
3876 we go out of the loop. */
3877 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
3878 QImode, 0, end_label);
3880 /* Initialize the loop counter. */
3881 emit_move_insn (counter, rotate_amount);
3883 emit_label (start_label);
3885 /* Rotate by one bit. */
3886 tmp = gen_rtx_fmt_ee (code, mode, dst, const1_rtx);
3887 emit_insn (gen_rtx_SET (mode, dst, tmp));
3889 /* Decrement the counter by 1. */
3890 tmp = gen_rtx_PLUS (QImode, counter, constm1_rtx);
3891 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3893 /* If the loop counter is nonzero, we go back to the beginning
3895 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
3898 emit_label (end_label);
3902 /* Rotate by AMOUNT bits. */
3903 tmp = gen_rtx_fmt_ee (code, mode, dst, rotate_amount);
3904 emit_insn (gen_rtx_SET (mode, dst, tmp));
3910 /* Output rotate insns. */
3913 output_a_rotate (enum rtx_code code, rtx *operands)
3915 rtx dst = operands[0];
3916 rtx rotate_amount = operands[2];
3917 enum shift_mode rotate_mode;
3918 enum shift_type rotate_type;
3919 const char *insn_buf;
3922 enum machine_mode mode = GET_MODE (dst);
3924 if (GET_CODE (rotate_amount) != CONST_INT)
3930 rotate_mode = QIshift;
3933 rotate_mode = HIshift;
3936 rotate_mode = SIshift;
3945 rotate_type = SHIFT_ASHIFT;
3948 rotate_type = SHIFT_LSHIFTRT;
3954 amount = INTVAL (rotate_amount);
3956 /* Clean up AMOUNT. */
3959 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3960 amount = GET_MODE_BITSIZE (mode);
3962 /* Determine the faster direction. After this phase, amount will be
3963 at most a half of GET_MODE_BITSIZE (mode). */
3964 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3966 /* Flip the direction. */
3967 amount = GET_MODE_BITSIZE (mode) - amount;
3969 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3972 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3973 boost up the rotation. */
3974 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3975 || (mode == HImode && TARGET_H8300H && amount >= 6)
3976 || (mode == HImode && TARGET_H8300S && amount == 8)
3977 || (mode == SImode && TARGET_H8300H && amount >= 10)
3978 || (mode == SImode && TARGET_H8300S && amount >= 13))
3983 /* This code works on any family. */
3984 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3985 output_asm_insn (insn_buf, operands);
3989 /* This code works on the H8/300H and H8S. */
3990 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3991 output_asm_insn (insn_buf, operands);
3998 /* Adjust AMOUNT and flip the direction. */
3999 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4001 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4004 /* Emit rotate insns. */
4005 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4008 insn_buf = rotate_two[rotate_type][rotate_mode];
4010 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4012 for (; amount >= bits; amount -= bits)
4013 output_asm_insn (insn_buf, operands);
4020 compute_a_rotate_length (rtx *operands)
4022 rtx src = operands[1];
4023 rtx amount_rtx = operands[2];
4024 enum machine_mode mode = GET_MODE (src);
4026 unsigned int length = 0;
4028 if (GET_CODE (amount_rtx) != CONST_INT)
4031 amount = INTVAL (amount_rtx);
4033 /* Clean up AMOUNT. */
4036 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4037 amount = GET_MODE_BITSIZE (mode);
4039 /* Determine the faster direction. After this phase, amount
4040 will be at most a half of GET_MODE_BITSIZE (mode). */
4041 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4042 /* Flip the direction. */
4043 amount = GET_MODE_BITSIZE (mode) - amount;
4045 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4046 boost up the rotation. */
4047 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4048 || (mode == HImode && TARGET_H8300H && amount >= 6)
4049 || (mode == HImode && TARGET_H8300S && amount == 8)
4050 || (mode == SImode && TARGET_H8300H && amount >= 10)
4051 || (mode == SImode && TARGET_H8300S && amount >= 13))
4053 /* Adjust AMOUNT and flip the direction. */
4054 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4058 /* We use 2-bit rotations on the H8S. */
4060 amount = amount / 2 + amount % 2;
4062 /* The H8/300 uses three insns to rotate one bit, taking 6
4064 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4069 /* Fix the operands of a gen_xxx so that it could become a bit
4073 fix_bit_operand (rtx *operands, int what, enum rtx_code code)
4075 /* The bit_operand predicate accepts any memory during RTL generation, but
4076 only 'U' memory afterwards, so if this is a MEM operand, we must force
4077 it to be valid for 'U' by reloading the address. */
4079 if ((what == 0 && single_zero_operand (operands[2], QImode))
4080 || (what == 1 && single_one_operand (operands[2], QImode)))
4082 /* OK to have a memory dest. */
4083 if (GET_CODE (operands[0]) == MEM
4084 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4086 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4087 copy_to_mode_reg (Pmode,
4088 XEXP (operands[0], 0)));
4089 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4093 if (GET_CODE (operands[1]) == MEM
4094 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4096 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4097 copy_to_mode_reg (Pmode,
4098 XEXP (operands[1], 0)));
4099 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4105 /* Dest and src op must be register. */
4107 operands[1] = force_reg (QImode, operands[1]);
4109 rtx res = gen_reg_rtx (QImode);
4113 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4116 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4119 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4124 emit_insn (gen_movqi (operands[0], res));
4129 /* Return nonzero if FUNC is an interrupt function as specified
4130 by the "interrupt" attribute. */
4133 h8300_interrupt_function_p (tree func)
4137 if (TREE_CODE (func) != FUNCTION_DECL)
4140 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4141 return a != NULL_TREE;
4144 /* Return nonzero if FUNC is a saveall function as specified by the
4145 "saveall" attribute. */
4148 h8300_saveall_function_p (tree func)
4152 if (TREE_CODE (func) != FUNCTION_DECL)
4155 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4156 return a != NULL_TREE;
4159 /* Return nonzero if FUNC is an OS_Task function as specified
4160 by the "OS_Task" attribute. */
4163 h8300_os_task_function_p (tree func)
4167 if (TREE_CODE (func) != FUNCTION_DECL)
4170 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4171 return a != NULL_TREE;
4174 /* Return nonzero if FUNC is a monitor function as specified
4175 by the "monitor" attribute. */
4178 h8300_monitor_function_p (tree func)
4182 if (TREE_CODE (func) != FUNCTION_DECL)
4185 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4186 return a != NULL_TREE;
4189 /* Return nonzero if FUNC is a function that should be called
4190 through the function vector. */
4193 h8300_funcvec_function_p (tree func)
4197 if (TREE_CODE (func) != FUNCTION_DECL)
4200 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4201 return a != NULL_TREE;
4204 /* Return nonzero if DECL is a variable that's in the eight bit
4208 h8300_eightbit_data_p (tree decl)
4212 if (TREE_CODE (decl) != VAR_DECL)
4215 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4216 return a != NULL_TREE;
4219 /* Return nonzero if DECL is a variable that's in the tiny
4223 h8300_tiny_data_p (tree decl)
4227 if (TREE_CODE (decl) != VAR_DECL)
4230 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4231 return a != NULL_TREE;
4234 /* Generate an 'interrupt_handler' attribute for decls. We convert
4235 all the pragmas to corresponding attributes. */
4238 h8300_insert_attributes (tree node, tree *attributes)
4240 if (TREE_CODE (node) == FUNCTION_DECL)
4242 if (pragma_interrupt)
4244 pragma_interrupt = 0;
4246 /* Add an 'interrupt_handler' attribute. */
4247 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4255 /* Add an 'saveall' attribute. */
4256 *attributes = tree_cons (get_identifier ("saveall"),
4262 /* Supported attributes:
4264 interrupt_handler: output a prologue and epilogue suitable for an
4267 saveall: output a prologue and epilogue that saves and restores
4268 all registers except the stack pointer.
4270 function_vector: This function should be called through the
4273 eightbit_data: This variable lives in the 8-bit data area and can
4274 be referenced with 8-bit absolute memory addresses.
4276 tiny_data: This variable lives in the tiny data area and can be
4277 referenced with 16-bit absolute memory references. */
4279 const struct attribute_spec h8300_attribute_table[] =
4281 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4282 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4283 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4284 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4285 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4286 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4287 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4288 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4289 { NULL, 0, 0, false, false, false, NULL }
4293 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4294 struct attribute_spec.handler. */
4296 h8300_handle_fndecl_attribute (tree *node, tree name,
4297 tree args ATTRIBUTE_UNUSED,
4298 int flags ATTRIBUTE_UNUSED,
4301 if (TREE_CODE (*node) != FUNCTION_DECL)
4303 warning ("`%s' attribute only applies to functions",
4304 IDENTIFIER_POINTER (name));
4305 *no_add_attrs = true;
4311 /* Handle an "eightbit_data" attribute; arguments as in
4312 struct attribute_spec.handler. */
4314 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4315 tree args ATTRIBUTE_UNUSED,
4316 int flags ATTRIBUTE_UNUSED,
4321 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4323 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4327 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4328 *no_add_attrs = true;
4334 /* Handle an "tiny_data" attribute; arguments as in
4335 struct attribute_spec.handler. */
4337 h8300_handle_tiny_data_attribute (tree *node, tree name,
4338 tree args ATTRIBUTE_UNUSED,
4339 int flags ATTRIBUTE_UNUSED,
4344 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4346 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4350 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4351 *no_add_attrs = true;
4357 /* Mark function vectors, and various small data objects. */
4360 h8300_encode_section_info (tree decl, rtx rtl, int first)
4362 int extra_flags = 0;
4364 default_encode_section_info (decl, rtl, first);
4366 if (TREE_CODE (decl) == FUNCTION_DECL
4367 && h8300_funcvec_function_p (decl))
4368 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4369 else if (TREE_CODE (decl) == VAR_DECL
4370 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4372 if (h8300_eightbit_data_p (decl))
4373 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4374 else if (first && h8300_tiny_data_p (decl))
4375 extra_flags = SYMBOL_FLAG_TINY_DATA;
4379 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4383 output_simode_bld (int bild, rtx operands[])
4387 /* Clear the destination register. */
4388 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4390 /* Now output the bit load or bit inverse load, and store it in
4393 output_asm_insn ("bild\t%Z2,%Y1", operands);
4395 output_asm_insn ("bld\t%Z2,%Y1", operands);
4397 output_asm_insn ("bst\t#0,%w0", operands);
4401 /* Determine if we can clear the destination first. */
4402 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4403 && REGNO (operands[0]) != REGNO (operands[1]));
4406 output_asm_insn ("sub.l\t%S0,%S0", operands);
4408 /* Output the bit load or bit inverse load. */
4410 output_asm_insn ("bild\t%Z2,%Y1", operands);
4412 output_asm_insn ("bld\t%Z2,%Y1", operands);
4415 output_asm_insn ("xor.l\t%S0,%S0", operands);
4417 /* Perform the bit store. */
4418 output_asm_insn ("rotxl.l\t%S0", operands);
4425 #ifndef OBJECT_FORMAT_ELF
4427 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4429 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4430 fprintf (asm_out_file, "\t.section %s\n", name);
4432 #endif /* ! OBJECT_FORMAT_ELF */
4434 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4435 which is a special case of the 'R' operand. */
4438 h8300_eightbit_constant_address_p (rtx x)
4440 /* The ranges of the 8-bit area. */
4441 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4442 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4443 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4444 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4445 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4446 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4448 unsigned HOST_WIDE_INT addr;
4450 /* We accept symbols declared with eightbit_data. */
4451 if (GET_CODE (x) == SYMBOL_REF)
4452 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4454 if (GET_CODE (x) != CONST_INT)
4460 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4461 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4462 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4465 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4466 on H8/300H and H8S. */
4469 h8300_tiny_constant_address_p (rtx x)
4471 /* The ranges of the 16-bit area. */
4472 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4473 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4474 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4475 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4476 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4477 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4478 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4479 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4481 unsigned HOST_WIDE_INT addr;
4483 switch (GET_CODE (x))
4486 /* In the normal mode, any symbol fits in the 16-bit absolute
4487 address range. We also accept symbols declared with
4489 return (TARGET_NORMAL_MODE
4490 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
4494 return (TARGET_NORMAL_MODE
4496 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4498 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4501 return TARGET_NORMAL_MODE;
4510 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4512 HOST_WIDE_INT offset1, offset2;
4520 else if (GET_CODE (addr1) == PLUS
4521 && REG_P (XEXP (addr1, 0))
4522 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4524 reg1 = XEXP (addr1, 0);
4525 offset1 = INTVAL (XEXP (addr1, 1));
4535 else if (GET_CODE (addr2) == PLUS
4536 && REG_P (XEXP (addr2, 0))
4537 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4539 reg2 = XEXP (addr2, 0);
4540 offset2 = INTVAL (XEXP (addr2, 1));
4545 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4546 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4548 && offset1 + 1 == offset2)
4554 /* Return nonzero if we have the same comparison insn as I3 two insns
4555 before I3. I3 is assumed to be a comparison insn. */
4558 same_cmp_preceding_p (rtx i3)
4562 /* Make sure we have a sequence of three insns. */
4563 i2 = prev_nonnote_insn (i3);
4566 i1 = prev_nonnote_insn (i2);
4570 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4571 && any_condjump_p (i2) && onlyjump_p (i2));
4574 /* Return nonzero if we have the same comparison insn as I1 two insns
4575 after I1. I1 is assumed to be a comparison insn. */
4578 same_cmp_following_p (rtx i1)
4582 /* Make sure we have a sequence of three insns. */
4583 i2 = next_nonnote_insn (i1);
4586 i3 = next_nonnote_insn (i2);
4590 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4591 && any_condjump_p (i2) && onlyjump_p (i2));
4594 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
4595 (or pops) N registers. OPERANDS are asssumed to be an array of
4599 h8300_regs_ok_for_stm (int n, rtx operands[])
4604 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4605 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4606 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
4608 return ((REGNO (operands[0]) == 0
4609 && REGNO (operands[1]) == 1
4610 && REGNO (operands[2]) == 2)
4611 || (REGNO (operands[0]) == 4
4612 && REGNO (operands[1]) == 5
4613 && REGNO (operands[2]) == 6));
4616 return (REGNO (operands[0]) == 0
4617 && REGNO (operands[1]) == 1
4618 && REGNO (operands[2]) == 2
4619 && REGNO (operands[3]) == 3);
4625 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4628 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4629 unsigned int new_reg)
4631 /* Interrupt functions can only use registers that have already been
4632 saved by the prologue, even if they would normally be
4635 if (h8300_current_function_interrupt_function_p ()
4636 && !regs_ever_live[new_reg])
4642 /* Return nonzero if X is a legitimate constant. */
4645 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4650 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4653 h8300_rtx_ok_for_base_p (rtx x, int strict)
4655 /* Strip off SUBREG if any. */
4656 if (GET_CODE (x) == SUBREG)
4661 ? REG_OK_FOR_BASE_STRICT_P (x)
4662 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4665 /* Return nozero if X is a legitimate address. On the H8/300, a
4666 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4667 CONSTANT_ADDRESS. */
4670 h8300_legitimate_address_p (rtx x, int strict)
4672 /* The register indirect addresses like @er0 is always valid. */
4673 if (h8300_rtx_ok_for_base_p (x, strict))
4676 if (CONSTANT_ADDRESS_P (x))
4679 if (GET_CODE (x) == PLUS
4680 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4681 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4687 /* Perform target dependent optabs initialization. */
4689 h8300_init_libfuncs (void)
4691 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4692 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4693 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4694 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4695 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4699 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4701 return (TYPE_MODE (type) == BLKmode
4702 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4705 /* Initialize the GCC target structure. */
4706 #undef TARGET_ATTRIBUTE_TABLE
4707 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4709 #undef TARGET_ASM_ALIGNED_HI_OP
4710 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4712 #undef TARGET_ASM_FILE_START
4713 #define TARGET_ASM_FILE_START h8300_file_start
4714 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4715 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4717 #undef TARGET_ASM_FILE_END
4718 #define TARGET_ASM_FILE_END h8300_file_end
4720 #undef TARGET_ENCODE_SECTION_INFO
4721 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4723 #undef TARGET_INSERT_ATTRIBUTES
4724 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4726 #undef TARGET_RTX_COSTS
4727 #define TARGET_RTX_COSTS h8300_rtx_costs
4729 #undef TARGET_INIT_LIBFUNCS
4730 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4732 #undef TARGET_RETURN_IN_MEMORY
4733 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4735 struct gcc_target targetm = TARGET_INITIALIZER;