1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
334 byte_reg (rtx x, int b)
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
341 return names_small[REGNO (x) * 2 + b];
344 /* REGNO must be saved/restored across calls if this macro is true. */
346 #define WORD_REG_USED(regno) \
348 /* No need to save registers if this function will not return. */ \
349 && ! TREE_THIS_VOLATILE (current_function_decl) \
350 && (h8300_saveall_function_p (current_function_decl) \
351 /* Save any call saved register that was used. */ \
352 || (regs_ever_live[regno] && !call_used_regs[regno]) \
353 /* Save the frame pointer if it was used. */ \
354 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
355 /* Save any register used in an interrupt handler. */ \
356 || (h8300_current_function_interrupt_function_p () \
357 && regs_ever_live[regno]) \
358 /* Save call clobbered registers in non-leaf interrupt \
360 || (h8300_current_function_interrupt_function_p () \
361 && call_used_regs[regno] \
362 && !current_function_is_leaf)))
364 /* Output assembly language to FILE for the operation OP with operand size
365 SIZE to adjust the stack pointer. */
368 h8300_emit_stack_adjustment (int sign, unsigned int size)
370 /* H8/300 cannot add/subtract a large constant with a single
371 instruction. If a temporary register is available, load the
372 constant to it and then do the addition. */
375 && !h8300_current_function_interrupt_function_p ()
376 && !(current_function_needs_context && sign < 0))
379 rtx r3 = gen_rtx_REG (Pmode, 3);
380 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
381 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
382 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
386 /* The stack adjustment made here is further optimized by the
387 splitter. In case of H8/300, the splitter always splits the
388 addition emitted here to make the adjustment
390 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
391 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
395 /* Round up frame size SIZE. */
398 round_frame_size (int size)
400 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
401 & -STACK_BOUNDARY / BITS_PER_UNIT);
404 /* Compute which registers to push/pop.
405 Return a bit vector of registers. */
408 compute_saved_regs (void)
410 unsigned int saved_regs = 0;
413 /* Construct a bit vector of registers to be pushed/popped. */
414 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
416 if (WORD_REG_USED (regno))
417 saved_regs |= 1 << regno;
420 /* Don't push/pop the frame pointer as it is treated separately. */
421 if (frame_pointer_needed)
422 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
427 /* Emit an insn to push register RN. */
432 rtx reg = gen_rtx_REG (word_mode, rn);
436 x = gen_push_h8300 (reg);
437 else if (!TARGET_NORMAL_MODE)
438 x = gen_push_h8300hs_advanced (reg);
440 x = gen_push_h8300hs_normal (reg);
442 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
445 /* Emit an insn to pop register RN. */
450 rtx reg = gen_rtx_REG (word_mode, rn);
454 x = gen_pop_h8300 (reg);
455 else if (!TARGET_NORMAL_MODE)
456 x = gen_pop_h8300hs_advanced (reg);
458 x = gen_pop_h8300hs_normal (reg);
460 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
463 /* This is what the stack looks like after the prolog of
464 a function with a frame has been set up:
470 <saved registers> <- sp
472 This is what the stack looks like after the prolog of
473 a function which doesn't have a frame:
478 <saved registers> <- sp
481 /* Generate RTL code for the function prologue. */
484 h8300_expand_prologue (void)
490 /* If the current function has the OS_Task attribute set, then
491 we have a naked prologue. */
492 if (h8300_os_task_function_p (current_function_decl))
495 if (h8300_monitor_function_p (current_function_decl))
496 /* My understanding of monitor functions is they act just like
497 interrupt functions, except the prologue must mask
499 emit_insn (gen_monitor_prologue ());
501 if (frame_pointer_needed)
504 push (FRAME_POINTER_REGNUM);
505 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
508 /* Leave room for locals. */
509 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
511 /* Push the rest of the registers in ascending order. */
512 saved_regs = compute_saved_regs ();
513 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
516 if (saved_regs & (1 << regno))
520 /* See how many registers we can push at the same time. */
521 if ((regno == 0 || regno == 4)
522 && ((saved_regs >> regno) & 0x0f) == 0x0f)
525 else if ((regno == 0 || regno == 4)
526 && ((saved_regs >> regno) & 0x07) == 0x07)
529 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
530 && ((saved_regs >> regno) & 0x03) == 0x03)
540 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
541 gen_rtx_REG (SImode, regno + 1)));
544 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
545 gen_rtx_REG (SImode, regno + 1),
546 gen_rtx_REG (SImode, regno + 2)));
549 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
550 gen_rtx_REG (SImode, regno + 1),
551 gen_rtx_REG (SImode, regno + 2),
552 gen_rtx_REG (SImode, regno + 3)));
562 h8300_can_use_return_insn_p (void)
564 return (reload_completed
565 && !frame_pointer_needed
566 && get_frame_size () == 0
567 && compute_saved_regs () == 0);
570 /* Generate RTL code for the function epilogue. */
573 h8300_expand_epilogue (void)
579 if (h8300_os_task_function_p (current_function_decl))
580 /* OS_Task epilogues are nearly naked -- they just have an
584 /* Pop the saved registers in descending order. */
585 saved_regs = compute_saved_regs ();
586 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
589 if (saved_regs & (1 << regno))
593 /* See how many registers we can pop at the same time. */
594 if ((regno == 7 || regno == 3)
595 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
598 else if ((regno == 6 || regno == 2)
599 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
602 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
603 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
613 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
614 gen_rtx_REG (SImode, regno)));
617 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
618 gen_rtx_REG (SImode, regno - 1),
619 gen_rtx_REG (SImode, regno)));
622 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
623 gen_rtx_REG (SImode, regno - 2),
624 gen_rtx_REG (SImode, regno - 1),
625 gen_rtx_REG (SImode, regno)));
633 /* Deallocate locals. */
634 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
636 /* Pop frame pointer if we had one. */
637 if (frame_pointer_needed)
638 pop (FRAME_POINTER_REGNUM);
641 /* Return nonzero if the current function is an interrupt
645 h8300_current_function_interrupt_function_p (void)
647 return (h8300_interrupt_function_p (current_function_decl)
648 || h8300_monitor_function_p (current_function_decl));
651 /* Output assembly code for the start of the file. */
654 h8300_file_start (void)
656 default_file_start ();
659 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
660 else if (TARGET_H8300S)
661 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
664 /* Output assembly language code for the end of file. */
667 h8300_file_end (void)
669 fputs ("\t.end\n", asm_out_file);
672 /* Return true if OP is a valid source operand for an integer move
676 general_operand_src (rtx op, enum machine_mode mode)
678 if (GET_MODE (op) == mode
679 && GET_CODE (op) == MEM
680 && GET_CODE (XEXP (op, 0)) == POST_INC)
682 return general_operand (op, mode);
685 /* Return true if OP is a valid destination operand for an integer move
689 general_operand_dst (rtx op, enum machine_mode mode)
691 if (GET_MODE (op) == mode
692 && GET_CODE (op) == MEM
693 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
695 return general_operand (op, mode);
698 /* Return true if OP is a constant that contains only one 1 in its
699 binary representation. */
702 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
704 if (GET_CODE (operand) == CONST_INT)
706 /* We really need to do this masking because 0x80 in QImode is
707 represented as -128 for example. */
708 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
715 /* Return true if OP is a constant that contains only one 0 in its
716 binary representation. */
719 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
721 if (GET_CODE (operand) == CONST_INT)
723 /* We really need to do this masking because 0x80 in QImode is
724 represented as -128 for example. */
725 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
732 /* Return true if OP is a valid call operand. */
735 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
737 if (GET_CODE (op) == MEM)
739 rtx inside = XEXP (op, 0);
740 if (register_operand (inside, Pmode))
742 if (CONSTANT_ADDRESS_P (inside))
748 /* Return 1 if an addition/subtraction of a constant integer can be
749 transformed into two consecutive adds/subs that are faster than the
750 straightforward way. Otherwise, return 0. */
753 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
755 if (GET_CODE (op) == CONST_INT)
757 HOST_WIDE_INT value = INTVAL (op);
759 /* Force VALUE to be positive so that we do not have to consider
760 the negative case. */
763 if (TARGET_H8300H || TARGET_H8300S)
765 /* A constant addition/subtraction takes 2 states in QImode,
766 4 states in HImode, and 6 states in SImode. Thus, the
767 only case we can win is when SImode is used, in which
768 case, two adds/subs are used, taking 4 states. */
778 /* We do not profit directly by splitting addition or
779 subtraction of 3 and 4. However, since these are
780 implemented as a sequence of adds or subs, they do not
781 clobber (cc0) unlike a sequence of add.b and add.x. */
792 /* Split an add of a small constant into two adds/subs insns.
794 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
795 instead of adds/subs. */
798 split_adds_subs (enum machine_mode mode, rtx *operands)
800 HOST_WIDE_INT val = INTVAL (operands[1]);
801 rtx reg = operands[0];
802 HOST_WIDE_INT sign = 1;
803 HOST_WIDE_INT amount;
804 rtx (*gen_add) (rtx, rtx, rtx);
806 /* Force VAL to be positive so that we do not have to consider the
817 gen_add = gen_addhi3;
821 gen_add = gen_addsi3;
828 /* Try different amounts in descending order. */
829 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
833 for (; val >= amount; val -= amount)
834 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
840 /* Return true if OP is a valid call operand, and OP represents
841 an operand for a small call (4 bytes instead of 6 bytes). */
844 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
846 if (GET_CODE (op) == MEM)
848 rtx inside = XEXP (op, 0);
850 /* Register indirect is a small call. */
851 if (register_operand (inside, Pmode))
854 /* A call through the function vector is a small call too. */
855 if (GET_CODE (inside) == SYMBOL_REF
856 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
859 /* Otherwise it's a large call. */
863 /* Return true if OP is a valid jump operand. */
866 jump_address_operand (rtx op, enum machine_mode mode)
868 if (GET_CODE (op) == REG)
869 return mode == Pmode;
871 if (GET_CODE (op) == MEM)
873 rtx inside = XEXP (op, 0);
874 if (register_operand (inside, Pmode))
876 if (CONSTANT_ADDRESS_P (inside))
882 /* Recognize valid operands for bit-field instructions. */
884 extern int rtx_equal_function_value_matters;
887 bit_operand (rtx op, enum machine_mode mode)
889 /* We can accept any general operand, except that MEM operands must
890 be limited to those that use addresses valid for the 'U' constraint. */
891 if (!general_operand (op, mode))
894 /* Accept any mem during RTL generation. Otherwise, the code that does
895 insv and extzv will think that we can not handle memory. However,
896 to avoid reload problems, we only accept 'U' MEM operands after RTL
897 generation. This means that any named pattern which uses this predicate
898 must force its operands to match 'U' before emitting RTL. */
900 if (GET_CODE (op) == REG)
902 if (GET_CODE (op) == SUBREG)
904 return (GET_CODE (op) == MEM
905 && EXTRA_CONSTRAINT (op, 'U'));
909 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
911 return (GET_CODE (op) == MEM
912 && EXTRA_CONSTRAINT (op, 'U'));
915 /* Handle machine specific pragmas for compatibility with existing
916 compilers for the H8/300.
918 pragma saveall generates prologue/epilogue code which saves and
919 restores all the registers on function entry.
921 pragma interrupt saves and restores all registers, and exits with
922 an rte instruction rather than an rts. A pointer to a function
923 with this attribute may be safely used in an interrupt vector. */
926 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
928 pragma_interrupt = 1;
932 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
937 /* If the next function argument with MODE and TYPE is to be passed in
938 a register, return a reg RTX for the hard register in which to pass
939 the argument. CUM represents the state after the last argument.
940 If the argument is to be pushed, NULL_RTX is returned. */
943 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
944 tree type, int named)
946 static const char *const hand_list[] = {
965 rtx result = NULL_RTX;
969 /* Never pass unnamed arguments in registers. */
973 /* Pass 3 regs worth of data in regs when user asked on the command line. */
974 if (TARGET_QUICKCALL)
977 /* If calling hand written assembler, use 4 regs of args. */
980 const char * const *p;
982 fname = XSTR (cum->libcall, 0);
984 /* See if this libcall is one of the hand coded ones. */
985 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
997 size = int_size_in_bytes (type);
999 size = GET_MODE_SIZE (mode);
1001 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1002 && cum->nbytes / UNITS_PER_WORD <= 3)
1003 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1010 h8300_and_costs (rtx x)
1014 if (GET_MODE (x) == QImode)
1017 if (GET_MODE (x) != HImode
1018 && GET_MODE (x) != SImode)
1023 operands[2] = XEXP (x, 1);
1025 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1029 h8300_shift_costs (rtx x)
1033 if (GET_MODE (x) != QImode
1034 && GET_MODE (x) != HImode
1035 && GET_MODE (x) != SImode)
1040 operands[2] = XEXP (x, 1);
1042 return compute_a_shift_length (NULL, operands) / 2;
1046 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1052 HOST_WIDE_INT n = INTVAL (x);
1054 if (-4 <= n || n <= 4)
1065 *total = 0 + (outer_code == SET);
1069 if (TARGET_H8300H || TARGET_H8300S)
1070 *total = 0 + (outer_code == SET);
1091 *total = COSTS_N_INSNS (h8300_and_costs (x));
1094 /* We say that MOD and DIV are so expensive because otherwise we'll
1095 generate some really horrible code for division of a power of two. */
1108 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1113 if (GET_MODE (x) == HImode)
1125 /* Documentation for the machine specific operand escapes:
1127 'E' like s but negative.
1128 'F' like t but negative.
1129 'G' constant just the negative
1130 'R' print operand as a byte:8 address if appropriate, else fall back to
1132 'S' print operand as a long word
1133 'T' print operand as a word
1134 'V' find the set bit, and print its number.
1135 'W' find the clear bit, and print its number.
1136 'X' print operand as a byte
1137 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1138 If this operand isn't a register, fall back to 'R' handling.
1140 'c' print the opcode corresponding to rtl
1141 'e' first word of 32 bit value - if reg, then least reg. if mem
1142 then least. if const then most sig word
1143 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1144 then +2. if const then least sig word
1145 'j' print operand as condition code.
1146 'k' print operand as reverse condition code.
1147 's' print as low byte of 16 bit value
1148 't' print as high byte of 16 bit value
1149 'w' print as low byte of 32 bit value
1150 'x' print as 2nd byte of 32 bit value
1151 'y' print as 3rd byte of 32 bit value
1152 'z' print as msb of 32 bit value
1155 /* Return assembly language string which identifies a comparison type. */
1158 cond_string (enum rtx_code code)
1187 /* Print operand X using operand code CODE to assembly language output file
1191 print_operand (FILE *file, rtx x, int code)
1193 /* This is used for communication between codes V,W,Z and Y. */
1199 switch (GET_CODE (x))
1202 fprintf (file, "%sl", names_big[REGNO (x)]);
1205 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1212 switch (GET_CODE (x))
1215 fprintf (file, "%sh", names_big[REGNO (x)]);
1218 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1225 if (GET_CODE (x) != CONST_INT)
1227 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1230 if (GET_CODE (x) == REG)
1231 fprintf (file, "%s", names_extended[REGNO (x)]);
1236 if (GET_CODE (x) == REG)
1237 fprintf (file, "%s", names_big[REGNO (x)]);
1242 bitint = exact_log2 (INTVAL (x) & 0xff);
1245 fprintf (file, "#%d", bitint);
1248 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1251 fprintf (file, "#%d", bitint);
1255 if (GET_CODE (x) == REG)
1256 fprintf (file, "%s", byte_reg (x, 0));
1263 if (GET_CODE (x) == REG)
1264 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1266 print_operand (file, x, 'R');
1270 bitint = INTVAL (x);
1271 fprintf (file, "#%d", bitint & 7);
1274 switch (GET_CODE (x))
1277 fprintf (file, "or");
1280 fprintf (file, "xor");
1283 fprintf (file, "and");
1290 switch (GET_CODE (x))
1294 fprintf (file, "%s", names_big[REGNO (x)]);
1296 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1299 print_operand (file, x, 0);
1302 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1308 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1309 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1310 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1319 switch (GET_CODE (x))
1323 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1325 fprintf (file, "%s", names_big[REGNO (x)]);
1328 x = adjust_address (x, HImode, 2);
1329 print_operand (file, x, 0);
1332 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1338 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1339 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1340 fprintf (file, "#%ld", (val & 0xffff));
1348 fputs (cond_string (GET_CODE (x)), file);
1351 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1354 if (GET_CODE (x) == CONST_INT)
1355 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1357 fprintf (file, "%s", byte_reg (x, 0));
1360 if (GET_CODE (x) == CONST_INT)
1361 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1363 fprintf (file, "%s", byte_reg (x, 1));
1366 if (GET_CODE (x) == CONST_INT)
1367 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1369 fprintf (file, "%s",
1370 byte_reg (x, TARGET_H8300 ? 2 : 0));
1373 if (GET_CODE (x) == CONST_INT)
1374 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1376 fprintf (file, "%s",
1377 byte_reg (x, TARGET_H8300 ? 3 : 1));
1380 if (GET_CODE (x) == CONST_INT)
1381 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1383 fprintf (file, "%s", byte_reg (x, 0));
1386 if (GET_CODE (x) == CONST_INT)
1387 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1389 fprintf (file, "%s", byte_reg (x, 1));
1394 switch (GET_CODE (x))
1397 switch (GET_MODE (x))
1400 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1401 fprintf (file, "%s", byte_reg (x, 0));
1402 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1403 fprintf (file, "%s", names_big[REGNO (x)]);
1407 fprintf (file, "%s", names_big[REGNO (x)]);
1411 fprintf (file, "%s", names_extended[REGNO (x)]);
1420 rtx addr = XEXP (x, 0);
1422 fprintf (file, "@");
1423 output_address (addr);
1425 /* We fall back from smaller addressing to larger
1426 addressing in various ways depending on CODE. */
1430 /* Used for mov.b and bit operations. */
1431 if (h8300_eightbit_constant_address_p (addr))
1433 fprintf (file, ":8");
1437 /* Fall through. We should not get here if we are
1438 processing bit operations on H8/300 or H8/300H
1439 because 'U' constraint does not allow bit
1440 operations on the tiny area on these machines. */
1444 /* Used for mov.w and mov.l. */
1445 if (h8300_tiny_constant_address_p (addr))
1446 fprintf (file, ":16");
1458 fprintf (file, "#");
1459 print_operand_address (file, x);
1465 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1466 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1467 fprintf (file, "#%ld", val);
1476 /* Output assembly language output for the address ADDR to FILE. */
1479 print_operand_address (FILE *file, rtx addr)
1481 switch (GET_CODE (addr))
1484 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1488 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1492 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1496 fprintf (file, "(");
1497 if (GET_CODE (XEXP (addr, 0)) == REG)
1500 print_operand_address (file, XEXP (addr, 1));
1501 fprintf (file, ",");
1502 print_operand_address (file, XEXP (addr, 0));
1507 print_operand_address (file, XEXP (addr, 0));
1508 fprintf (file, "+");
1509 print_operand_address (file, XEXP (addr, 1));
1511 fprintf (file, ")");
1516 /* Since the H8/300 only has 16 bit pointers, negative values are also
1517 those >= 32768. This happens for example with pointer minus a
1518 constant. We don't want to turn (char *p - 2) into
1519 (char *p + 65534) because loop unrolling can build upon this
1520 (IE: char *p + 131068). */
1521 int n = INTVAL (addr);
1523 n = (int) (short) n;
1524 fprintf (file, "%d", n);
1529 output_addr_const (file, addr);
1534 /* Output all insn addresses and their sizes into the assembly language
1535 output file. This is helpful for debugging whether the length attributes
1536 in the md file are correct. This is not meant to be a user selectable
1540 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1541 int num_operands ATTRIBUTE_UNUSED)
1543 /* This holds the last insn address. */
1544 static int last_insn_address = 0;
1546 const int uid = INSN_UID (insn);
1548 if (TARGET_ADDRESSES)
1550 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1551 INSN_ADDRESSES (uid) - last_insn_address);
1552 last_insn_address = INSN_ADDRESSES (uid);
1556 /* Prepare for an SI sized move. */
1559 do_movsi (rtx operands[])
1561 rtx src = operands[1];
1562 rtx dst = operands[0];
1563 if (!reload_in_progress && !reload_completed)
1565 if (!register_operand (dst, GET_MODE (dst)))
1567 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1568 emit_move_insn (tmp, src);
1575 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1576 Define the offset between two registers, one to be eliminated, and
1577 the other its replacement, at the start of a routine. */
1580 h8300_initial_elimination_offset (int from, int to)
1583 /* The number of bytes that the return address takes on the stack. */
1584 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1586 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1587 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1588 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1589 offset = frame_pointer_needed * UNITS_PER_WORD;
1594 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1595 if (WORD_REG_USED (regno))
1596 offset += UNITS_PER_WORD;
1598 /* See the comments for get_frame_size. We need to round it up to
1601 offset += round_frame_size (get_frame_size ());
1603 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1604 /* Skip saved PC. */
1612 h8300_return_addr_rtx (int count, rtx frame)
1617 ret = gen_rtx_MEM (Pmode,
1618 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1619 else if (flag_omit_frame_pointer)
1622 ret = gen_rtx_MEM (Pmode,
1623 memory_address (Pmode,
1624 plus_constant (frame, UNITS_PER_WORD)));
1625 set_mem_alias_set (ret, get_frame_alias_set ());
1629 /* Update the condition code from the insn. */
1632 notice_update_cc (rtx body, rtx insn)
1636 switch (get_attr_cc (insn))
1639 /* Insn does not affect CC at all. */
1643 /* Insn does not change CC, but the 0'th operand has been changed. */
1644 if (cc_status.value1 != 0
1645 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1646 cc_status.value1 = 0;
1647 if (cc_status.value2 != 0
1648 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1649 cc_status.value2 = 0;
1653 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1654 The V flag is unusable. The C flag may or may not be known but
1655 that's ok because alter_cond will change tests to use EQ/NE. */
1657 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1658 set = single_set (insn);
1659 cc_status.value1 = SET_SRC (set);
1660 if (SET_DEST (set) != cc0_rtx)
1661 cc_status.value2 = SET_DEST (set);
1665 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1666 The C flag may or may not be known but that's ok because
1667 alter_cond will change tests to use EQ/NE. */
1669 cc_status.flags |= CC_NO_CARRY;
1670 set = single_set (insn);
1671 cc_status.value1 = SET_SRC (set);
1672 if (SET_DEST (set) != cc0_rtx)
1674 /* If the destination is STRICT_LOW_PART, strip off
1676 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1677 cc_status.value2 = XEXP (SET_DEST (set), 0);
1679 cc_status.value2 = SET_DEST (set);
1684 /* The insn is a compare instruction. */
1686 cc_status.value1 = SET_SRC (body);
1690 /* Insn doesn't leave CC in a usable state. */
1696 /* Return nonzero if X is a stack pointer. */
1699 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1701 return x == stack_pointer_rtx;
1704 /* Return nonzero if X is a constant whose absolute value is greater
1708 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1710 return (GET_CODE (x) == CONST_INT
1711 && abs (INTVAL (x)) > 2);
1714 /* Return nonzero if X is a constant whose absolute value is no
1718 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1720 return (GET_CODE (x) == CONST_INT
1721 && abs (INTVAL (x)) >= 8);
1724 /* Return nonzero if X is a constant expressible in QImode. */
1727 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1729 return (GET_CODE (x) == CONST_INT
1730 && (INTVAL (x) & 0xff) == INTVAL (x));
1733 /* Return nonzero if X is a constant expressible in HImode. */
1736 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1738 return (GET_CODE (x) == CONST_INT
1739 && (INTVAL (x) & 0xffff) == INTVAL (x));
1742 /* Return nonzero if X is a constant suitable for inc/dec. */
1745 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1747 return (GET_CODE (x) == CONST_INT
1748 && (CONST_OK_FOR_M (INTVAL (x))
1749 || CONST_OK_FOR_O (INTVAL (x))));
1752 /* Return nonzero if X is either EQ or NE. */
1755 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1757 enum rtx_code code = GET_CODE (x);
1759 return (code == EQ || code == NE);
1762 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1765 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1767 enum rtx_code code = GET_CODE (x);
1769 return (code == GT || code == LE || code == GTU || code == LEU);
1772 /* Return nonzero if X is either GTU or LEU. */
1775 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1777 enum rtx_code code = GET_CODE (x);
1779 return (code == GTU || code == LEU);
1782 /* Return nonzero if X is either IOR or XOR. */
1785 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1787 enum rtx_code code = GET_CODE (x);
1789 return (code == IOR || code == XOR);
1792 /* Recognize valid operators for bit instructions. */
1795 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1797 enum rtx_code code = GET_CODE (x);
1804 /* Return the length of mov instruction. */
1807 compute_mov_length (rtx *operands)
1809 /* If the mov instruction involves a memory operand, we compute the
1810 length, assuming the largest addressing mode is used, and then
1811 adjust later in the function. Otherwise, we compute and return
1812 the exact length in one step. */
1813 enum machine_mode mode = GET_MODE (operands[0]);
1814 rtx dest = operands[0];
1815 rtx src = operands[1];
1818 if (GET_CODE (src) == MEM)
1819 addr = XEXP (src, 0);
1820 else if (GET_CODE (dest) == MEM)
1821 addr = XEXP (dest, 0);
1827 unsigned int base_length;
1832 if (addr == NULL_RTX)
1835 /* The eightbit addressing is available only in QImode, so
1836 go ahead and take care of it. */
1837 if (h8300_eightbit_constant_address_p (addr))
1844 if (addr == NULL_RTX)
1849 if (src == const0_rtx)
1859 if (addr == NULL_RTX)
1864 if (GET_CODE (src) == CONST_INT)
1866 if (src == const0_rtx)
1869 if ((INTVAL (src) & 0xffff) == 0)
1872 if ((INTVAL (src) & 0xffff) == 0)
1875 if ((INTVAL (src) & 0xffff)
1876 == ((INTVAL (src) >> 16) & 0xffff))
1886 if (addr == NULL_RTX)
1891 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1904 /* Adjust the length based on the addressing mode used.
1905 Specifically, we subtract the difference between the actual
1906 length and the longest one, which is @(d:16,Rs). For SImode
1907 and SFmode, we double the adjustment because two mov.w are
1908 used to do the job. */
1910 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1911 if (GET_CODE (addr) == PRE_DEC
1912 || GET_CODE (addr) == POST_INC)
1914 if (mode == QImode || mode == HImode)
1915 return base_length - 2;
1917 /* In SImode and SFmode, we use two mov.w instructions, so
1918 double the adjustment. */
1919 return base_length - 4;
1922 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1923 in SImode and SFmode, the second mov.w involves an address
1924 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1926 if (GET_CODE (addr) == REG)
1927 return base_length - 2;
1933 unsigned int base_length;
1938 if (addr == NULL_RTX)
1941 /* The eightbit addressing is available only in QImode, so
1942 go ahead and take care of it. */
1943 if (h8300_eightbit_constant_address_p (addr))
1950 if (addr == NULL_RTX)
1955 if (src == const0_rtx)
1965 if (addr == NULL_RTX)
1969 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
1975 if (GET_CODE (src) == CONST_INT)
1977 int val = INTVAL (src);
1982 if (val == (val & 0x00ff) || val == (val & 0xff00))
1985 switch (val & 0xffffffff)
2006 if (addr == NULL_RTX)
2011 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2024 /* Adjust the length based on the addressing mode used.
2025 Specifically, we subtract the difference between the actual
2026 length and the longest one, which is @(d:24,ERs). */
2028 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2029 if (GET_CODE (addr) == PRE_DEC
2030 || GET_CODE (addr) == POST_INC)
2031 return base_length - 6;
2033 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2034 if (GET_CODE (addr) == REG)
2035 return base_length - 6;
2037 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2039 if (GET_CODE (addr) == PLUS
2040 && GET_CODE (XEXP (addr, 0)) == REG
2041 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2042 && INTVAL (XEXP (addr, 1)) > -32768
2043 && INTVAL (XEXP (addr, 1)) < 32767)
2044 return base_length - 4;
2046 /* @aa:16 is 4 bytes shorter than the longest. */
2047 if (h8300_tiny_constant_address_p (addr))
2048 return base_length - 4;
2050 /* @aa:24 is 2 bytes shorter than the longest. */
2051 if (CONSTANT_P (addr))
2052 return base_length - 2;
2059 output_plussi (rtx *operands)
2061 enum machine_mode mode = GET_MODE (operands[0]);
2068 if (GET_CODE (operands[2]) == REG)
2069 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2071 if (GET_CODE (operands[2]) == CONST_INT)
2073 HOST_WIDE_INT n = INTVAL (operands[2]);
2075 if ((n & 0xffffff) == 0)
2076 return "add\t%z2,%z0";
2077 if ((n & 0xffff) == 0)
2078 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2079 if ((n & 0xff) == 0)
2080 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2083 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2087 if (GET_CODE (operands[2]) == REG)
2088 return "add.l\t%S2,%S0";
2090 if (GET_CODE (operands[2]) == CONST_INT)
2092 HOST_WIDE_INT intval = INTVAL (operands[2]);
2094 /* See if we can finish with 2 bytes. */
2096 switch ((unsigned int) intval & 0xffffffff)
2101 return "adds\t%2,%S0";
2106 return "subs\t%G2,%S0";
2110 operands[2] = GEN_INT (intval >> 16);
2111 return "inc.w\t%2,%e0";
2115 operands[2] = GEN_INT (intval >> 16);
2116 return "dec.w\t%G2,%e0";
2119 /* See if we can finish with 4 bytes. */
2120 if ((intval & 0xffff) == 0)
2122 operands[2] = GEN_INT (intval >> 16);
2123 return "add.w\t%2,%e0";
2127 return "add.l\t%S2,%S0";
2132 compute_plussi_length (rtx *operands)
2134 enum machine_mode mode = GET_MODE (operands[0]);
2141 if (GET_CODE (operands[2]) == REG)
2144 if (GET_CODE (operands[2]) == CONST_INT)
2146 HOST_WIDE_INT n = INTVAL (operands[2]);
2148 if ((n & 0xffffff) == 0)
2150 if ((n & 0xffff) == 0)
2152 if ((n & 0xff) == 0)
2160 if (GET_CODE (operands[2]) == REG)
2163 if (GET_CODE (operands[2]) == CONST_INT)
2165 HOST_WIDE_INT intval = INTVAL (operands[2]);
2167 /* See if we can finish with 2 bytes. */
2169 switch ((unsigned int) intval & 0xffffffff)
2190 /* See if we can finish with 4 bytes. */
2191 if ((intval & 0xffff) == 0)
2200 compute_plussi_cc (rtx *operands)
2202 enum machine_mode mode = GET_MODE (operands[0]);
2213 if (GET_CODE (operands[2]) == REG)
2216 if (GET_CODE (operands[2]) == CONST_INT)
2218 HOST_WIDE_INT intval = INTVAL (operands[2]);
2220 /* See if we can finish with 2 bytes. */
2222 switch ((unsigned int) intval & 0xffffffff)
2227 return CC_NONE_0HIT;
2232 return CC_NONE_0HIT;
2243 /* See if we can finish with 4 bytes. */
2244 if ((intval & 0xffff) == 0)
2253 output_logical_op (enum machine_mode mode, rtx *operands)
2255 /* Figure out the logical op that we need to perform. */
2256 enum rtx_code code = GET_CODE (operands[3]);
2257 /* Pretend that every byte is affected if both operands are registers. */
2258 const unsigned HOST_WIDE_INT intval =
2259 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2260 ? INTVAL (operands[2]) : 0x55555555);
2261 /* The determinant of the algorithm. If we perform an AND, 0
2262 affects a bit. Otherwise, 1 affects a bit. */
2263 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2264 /* Break up DET into pieces. */
2265 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2266 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2267 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2268 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2269 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2270 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2271 int lower_half_easy_p = 0;
2272 int upper_half_easy_p = 0;
2273 /* The name of an insn. */
2295 /* First, see if we can finish with one insn. */
2296 if ((TARGET_H8300H || TARGET_H8300S)
2300 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2301 output_asm_insn (insn_buf, operands);
2305 /* Take care of the lower byte. */
2308 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2309 output_asm_insn (insn_buf, operands);
2311 /* Take care of the upper byte. */
2314 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2315 output_asm_insn (insn_buf, operands);
2320 if (TARGET_H8300H || TARGET_H8300S)
2322 /* Determine if the lower half can be taken care of in no more
2324 lower_half_easy_p = (b0 == 0
2326 || (code != IOR && w0 == 0xffff));
2328 /* Determine if the upper half can be taken care of in no more
2330 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2331 || (code == AND && w1 == 0xff00));
2334 /* Check if doing everything with one insn is no worse than
2335 using multiple insns. */
2336 if ((TARGET_H8300H || TARGET_H8300S)
2337 && w0 != 0 && w1 != 0
2338 && !(lower_half_easy_p && upper_half_easy_p)
2339 && !(code == IOR && w1 == 0xffff
2340 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2342 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2343 output_asm_insn (insn_buf, operands);
2347 /* Take care of the lower and upper words individually. For
2348 each word, we try different methods in the order of
2350 1) the special insn (in case of AND or XOR),
2351 2) the word-wise insn, and
2352 3) The byte-wise insn. */
2354 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2355 output_asm_insn ((code == AND)
2356 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2358 else if ((TARGET_H8300H || TARGET_H8300S)
2362 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2363 output_asm_insn (insn_buf, operands);
2369 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2370 output_asm_insn (insn_buf, operands);
2374 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2375 output_asm_insn (insn_buf, operands);
2380 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2381 output_asm_insn ((code == AND)
2382 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2384 else if ((TARGET_H8300H || TARGET_H8300S)
2387 && (w0 & 0x8000) != 0)
2389 output_asm_insn ("exts.l\t%S0", operands);
2391 else if ((TARGET_H8300H || TARGET_H8300S)
2395 output_asm_insn ("extu.w\t%e0", operands);
2397 else if (TARGET_H8300H || TARGET_H8300S)
2401 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2402 output_asm_insn (insn_buf, operands);
2409 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2410 output_asm_insn (insn_buf, operands);
2414 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2415 output_asm_insn (insn_buf, operands);
2427 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2429 /* Figure out the logical op that we need to perform. */
2430 enum rtx_code code = GET_CODE (operands[3]);
2431 /* Pretend that every byte is affected if both operands are registers. */
2432 const unsigned HOST_WIDE_INT intval =
2433 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2434 ? INTVAL (operands[2]) : 0x55555555);
2435 /* The determinant of the algorithm. If we perform an AND, 0
2436 affects a bit. Otherwise, 1 affects a bit. */
2437 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2438 /* Break up DET into pieces. */
2439 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2440 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2441 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2442 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2443 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2444 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2445 int lower_half_easy_p = 0;
2446 int upper_half_easy_p = 0;
2448 unsigned int length = 0;
2453 /* First, see if we can finish with one insn. */
2454 if ((TARGET_H8300H || TARGET_H8300S)
2458 if (REG_P (operands[2]))
2465 /* Take care of the lower byte. */
2469 /* Take care of the upper byte. */
2475 if (TARGET_H8300H || TARGET_H8300S)
2477 /* Determine if the lower half can be taken care of in no more
2479 lower_half_easy_p = (b0 == 0
2481 || (code != IOR && w0 == 0xffff));
2483 /* Determine if the upper half can be taken care of in no more
2485 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2486 || (code == AND && w1 == 0xff00));
2489 /* Check if doing everything with one insn is no worse than
2490 using multiple insns. */
2491 if ((TARGET_H8300H || TARGET_H8300S)
2492 && w0 != 0 && w1 != 0
2493 && !(lower_half_easy_p && upper_half_easy_p)
2494 && !(code == IOR && w1 == 0xffff
2495 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2497 if (REG_P (operands[2]))
2504 /* Take care of the lower and upper words individually. For
2505 each word, we try different methods in the order of
2507 1) the special insn (in case of AND or XOR),
2508 2) the word-wise insn, and
2509 3) The byte-wise insn. */
2511 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2515 else if ((TARGET_H8300H || TARGET_H8300S)
2531 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2535 else if ((TARGET_H8300H || TARGET_H8300S)
2538 && (w0 & 0x8000) != 0)
2542 else if ((TARGET_H8300H || TARGET_H8300S)
2548 else if (TARGET_H8300H || TARGET_H8300S)
2570 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2572 /* Figure out the logical op that we need to perform. */
2573 enum rtx_code code = GET_CODE (operands[3]);
2574 /* Pretend that every byte is affected if both operands are registers. */
2575 const unsigned HOST_WIDE_INT intval =
2576 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2577 ? INTVAL (operands[2]) : 0x55555555);
2578 /* The determinant of the algorithm. If we perform an AND, 0
2579 affects a bit. Otherwise, 1 affects a bit. */
2580 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2581 /* Break up DET into pieces. */
2582 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2583 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2584 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2585 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2586 int lower_half_easy_p = 0;
2587 int upper_half_easy_p = 0;
2588 /* Condition code. */
2589 enum attr_cc cc = CC_CLOBBER;
2594 /* First, see if we can finish with one insn. */
2595 if ((TARGET_H8300H || TARGET_H8300S)
2603 if (TARGET_H8300H || TARGET_H8300S)
2605 /* Determine if the lower half can be taken care of in no more
2607 lower_half_easy_p = (b0 == 0
2609 || (code != IOR && w0 == 0xffff));
2611 /* Determine if the upper half can be taken care of in no more
2613 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2614 || (code == AND && w1 == 0xff00));
2617 /* Check if doing everything with one insn is no worse than
2618 using multiple insns. */
2619 if ((TARGET_H8300H || TARGET_H8300S)
2620 && w0 != 0 && w1 != 0
2621 && !(lower_half_easy_p && upper_half_easy_p)
2622 && !(code == IOR && w1 == 0xffff
2623 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2629 if ((TARGET_H8300H || TARGET_H8300S)
2632 && (w0 & 0x8000) != 0)
2646 We devote a fair bit of code to getting efficient shifts since we
2647 can only shift one bit at a time on the H8/300 and H8/300H and only
2648 one or two bits at a time on the H8S.
2650 All shift code falls into one of the following ways of
2653 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2654 when a straight line shift is about the same size or smaller than
2657 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2658 off the bits we don't need. This is used when only a few of the
2659 bits in the original value will survive in the shifted value.
2661 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2662 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2663 shifts can be added if the shift count is slightly more than 8 or
2664 16. This case also includes other oddballs that are not worth
2667 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2669 For each shift count, we try to use code that has no trade-off
2670 between code size and speed whenever possible.
2672 If the trade-off is unavoidable, we try to be reasonable.
2673 Specifically, the fastest version is one instruction longer than
2674 the shortest version, we take the fastest version. We also provide
2675 the use a way to switch back to the shortest version with -Os.
2677 For the details of the shift algorithms for various shift counts,
2678 refer to shift_alg_[qhs]i. */
2681 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2683 switch (GET_CODE (x))
2695 /* Emit code to do shifts. */
2698 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2700 emit_move_insn (operands[0], operands[1]);
2702 /* Need a loop to get all the bits we want - we generate the
2703 code at emit time, but need to allocate a scratch reg now. */
2705 emit_insn (gen_rtx_PARALLEL
2708 gen_rtx_SET (VOIDmode, operands[0],
2709 gen_rtx (code, mode, operands[0],
2711 gen_rtx_CLOBBER (VOIDmode,
2712 gen_rtx_SCRATCH (QImode)))));
2715 /* Symbols of the various modes which can be used as indices. */
2719 QIshift, HIshift, SIshift
2722 /* For single bit shift insns, record assembler and what bits of the
2723 condition code are valid afterwards (represented as various CC_FOO
2724 bits, 0 means CC isn't left in a usable state). */
2728 const char *const assembler;
2732 /* Assembler instruction shift table.
2734 These tables are used to look up the basic shifts.
2735 They are indexed by cpu, shift_type, and mode. */
2737 static const struct shift_insn shift_one[2][3][3] =
2743 { "shll\t%X0", CC_SET_ZNV },
2744 { "add.w\t%T0,%T0", CC_SET_ZN },
2745 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2747 /* SHIFT_LSHIFTRT */
2749 { "shlr\t%X0", CC_SET_ZNV },
2750 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2751 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2753 /* SHIFT_ASHIFTRT */
2755 { "shar\t%X0", CC_SET_ZNV },
2756 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2757 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2764 { "shll.b\t%X0", CC_SET_ZNV },
2765 { "shll.w\t%T0", CC_SET_ZNV },
2766 { "shll.l\t%S0", CC_SET_ZNV }
2768 /* SHIFT_LSHIFTRT */
2770 { "shlr.b\t%X0", CC_SET_ZNV },
2771 { "shlr.w\t%T0", CC_SET_ZNV },
2772 { "shlr.l\t%S0", CC_SET_ZNV }
2774 /* SHIFT_ASHIFTRT */
2776 { "shar.b\t%X0", CC_SET_ZNV },
2777 { "shar.w\t%T0", CC_SET_ZNV },
2778 { "shar.l\t%S0", CC_SET_ZNV }
2783 static const struct shift_insn shift_two[3][3] =
2787 { "shll.b\t#2,%X0", CC_SET_ZNV },
2788 { "shll.w\t#2,%T0", CC_SET_ZNV },
2789 { "shll.l\t#2,%S0", CC_SET_ZNV }
2791 /* SHIFT_LSHIFTRT */
2793 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2794 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2795 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2797 /* SHIFT_ASHIFTRT */
2799 { "shar.b\t#2,%X0", CC_SET_ZNV },
2800 { "shar.w\t#2,%T0", CC_SET_ZNV },
2801 { "shar.l\t#2,%S0", CC_SET_ZNV }
2805 /* Rotates are organized by which shift they'll be used in implementing.
2806 There's no need to record whether the cc is valid afterwards because
2807 it is the AND insn that will decide this. */
2809 static const char *const rotate_one[2][3][3] =
2816 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2819 /* SHIFT_LSHIFTRT */
2822 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2825 /* SHIFT_ASHIFTRT */
2828 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2840 /* SHIFT_LSHIFTRT */
2846 /* SHIFT_ASHIFTRT */
2855 static const char *const rotate_two[3][3] =
2863 /* SHIFT_LSHIFTRT */
2869 /* SHIFT_ASHIFTRT */
2878 /* Shift algorithm. */
2881 /* The number of bits to be shifted by shift1 and shift2. Valid
2882 when ALG is SHIFT_SPECIAL. */
2883 unsigned int remainder;
2885 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2886 const char *special;
2888 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2889 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2892 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2893 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2896 /* CC status for SHIFT_INLINE. */
2899 /* CC status for SHIFT_SPECIAL. */
2903 static void get_shift_alg (enum shift_type,
2904 enum shift_mode, unsigned int,
2905 struct shift_info *);
2907 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2908 best algorithm for doing the shift. The assembler code is stored
2909 in the pointers in INFO. We achieve the maximum efficiency in most
2910 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2911 SImode in particular have a lot of room to optimize.
2913 We first determine the strategy of the shift algorithm by a table
2914 lookup. If that tells us to use a hand crafted assembly code, we
2915 go into the big switch statement to find what that is. Otherwise,
2916 we resort to a generic way, such as inlining. In either case, the
2917 result is returned through INFO. */
2920 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2921 unsigned int count, struct shift_info *info)
2925 /* Find the target CPU. */
2928 else if (TARGET_H8300H)
2933 /* Find the shift algorithm. */
2934 info->alg = SHIFT_LOOP;
2938 if (count < GET_MODE_BITSIZE (QImode))
2939 info->alg = shift_alg_qi[cpu][shift_type][count];
2943 if (count < GET_MODE_BITSIZE (HImode))
2944 info->alg = shift_alg_hi[cpu][shift_type][count];
2948 if (count < GET_MODE_BITSIZE (SImode))
2949 info->alg = shift_alg_si[cpu][shift_type][count];
2956 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2960 info->remainder = count;
2964 /* It is up to the caller to know that looping clobbers cc. */
2965 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2966 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2967 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2971 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2972 info->shift2 = rotate_two[shift_type][shift_mode];
2973 info->cc_inline = CC_CLOBBER;
2977 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2978 info->remainder = 0;
2979 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2980 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2981 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2982 info->cc_special = CC_CLOBBER;
2986 /* Here we only deal with SHIFT_SPECIAL. */
2990 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2991 through the entire value. */
2992 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2994 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3006 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3008 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3010 case SHIFT_LSHIFTRT:
3012 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3014 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3016 case SHIFT_ASHIFTRT:
3017 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3021 else if ((8 <= count && count <= 13)
3022 || (TARGET_H8300S && count == 14))
3024 info->remainder = count - 8;
3029 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3031 case SHIFT_LSHIFTRT:
3034 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3035 info->shift1 = "shlr.b\t%s0";
3036 info->cc_inline = CC_SET_ZNV;
3040 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3041 info->cc_special = CC_SET_ZNV;
3044 case SHIFT_ASHIFTRT:
3047 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3048 info->shift1 = "shar.b\t%s0";
3052 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3053 info->cc_special = CC_SET_ZNV;
3058 else if (count == 14)
3064 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3066 case SHIFT_LSHIFTRT:
3068 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3070 case SHIFT_ASHIFTRT:
3072 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3073 else if (TARGET_H8300H)
3075 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3076 info->cc_special = CC_SET_ZNV;
3078 else /* TARGET_H8300S */
3083 else if (count == 15)
3088 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3090 case SHIFT_LSHIFTRT:
3091 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3093 case SHIFT_ASHIFTRT:
3094 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3101 if (TARGET_H8300 && 8 <= count && count <= 9)
3103 info->remainder = count - 8;
3108 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3110 case SHIFT_LSHIFTRT:
3111 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3112 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3114 case SHIFT_ASHIFTRT:
3115 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3119 else if (count == 8 && !TARGET_H8300)
3124 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3126 case SHIFT_LSHIFTRT:
3127 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3129 case SHIFT_ASHIFTRT:
3130 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3134 else if (count == 15 && TARGET_H8300)
3140 case SHIFT_LSHIFTRT:
3141 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3143 case SHIFT_ASHIFTRT:
3144 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3148 else if (count == 15 && !TARGET_H8300)
3153 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3154 info->cc_special = CC_SET_ZNV;
3156 case SHIFT_LSHIFTRT:
3157 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3158 info->cc_special = CC_SET_ZNV;
3160 case SHIFT_ASHIFTRT:
3164 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3165 || (TARGET_H8300H && 16 <= count && count <= 19)
3166 || (TARGET_H8300S && 16 <= count && count <= 21))
3168 info->remainder = count - 16;
3173 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3175 info->shift1 = "add.w\t%e0,%e0";
3177 case SHIFT_LSHIFTRT:
3180 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3181 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3185 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3186 info->cc_special = CC_SET_ZNV;
3189 case SHIFT_ASHIFTRT:
3192 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3193 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3197 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3198 info->cc_special = CC_SET_ZNV;
3203 else if (TARGET_H8300 && 24 <= count && count <= 28)
3205 info->remainder = count - 24;
3210 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3211 info->shift1 = "shll.b\t%z0";
3212 info->cc_inline = CC_SET_ZNV;
3214 case SHIFT_LSHIFTRT:
3215 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3216 info->shift1 = "shlr.b\t%w0";
3217 info->cc_inline = CC_SET_ZNV;
3219 case SHIFT_ASHIFTRT:
3220 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3221 info->shift1 = "shar.b\t%w0";
3222 info->cc_inline = CC_SET_ZNV;
3226 else if ((TARGET_H8300H && count == 24)
3227 || (TARGET_H8300S && 24 <= count && count <= 25))
3229 info->remainder = count - 24;
3234 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3236 case SHIFT_LSHIFTRT:
3237 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3238 info->cc_special = CC_SET_ZNV;
3240 case SHIFT_ASHIFTRT:
3241 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3242 info->cc_special = CC_SET_ZNV;
3246 else if (!TARGET_H8300 && count == 28)
3252 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3254 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3256 case SHIFT_LSHIFTRT:
3259 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3260 info->cc_special = CC_SET_ZNV;
3263 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3265 case SHIFT_ASHIFTRT:
3269 else if (!TARGET_H8300 && count == 29)
3275 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3277 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3279 case SHIFT_LSHIFTRT:
3282 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3283 info->cc_special = CC_SET_ZNV;
3287 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3288 info->cc_special = CC_SET_ZNV;
3291 case SHIFT_ASHIFTRT:
3295 else if (!TARGET_H8300 && count == 30)
3301 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3303 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3305 case SHIFT_LSHIFTRT:
3307 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3309 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3311 case SHIFT_ASHIFTRT:
3315 else if (count == 31)
3322 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3324 case SHIFT_LSHIFTRT:
3325 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3327 case SHIFT_ASHIFTRT:
3328 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3337 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3338 info->cc_special = CC_SET_ZNV;
3340 case SHIFT_LSHIFTRT:
3341 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3342 info->cc_special = CC_SET_ZNV;
3344 case SHIFT_ASHIFTRT:
3345 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3346 info->cc_special = CC_SET_ZNV;
3359 info->shift2 = NULL;
3362 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3363 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3366 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3371 if (GET_MODE_BITSIZE (mode) <= count)
3374 /* Find out the target CPU. */
3377 else if (TARGET_H8300H)
3382 /* Find the shift algorithm. */
3386 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3387 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3388 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3392 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3393 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3394 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3398 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3399 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3400 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3407 /* On H8/300H, count == 8 uses a scratch register. */
3408 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3409 || (TARGET_H8300H && mode == SImode && count == 8));
3412 /* Emit the assembler code for doing shifts. */
3415 output_a_shift (rtx *operands)
3417 static int loopend_lab;
3418 rtx shift = operands[3];
3419 enum machine_mode mode = GET_MODE (shift);
3420 enum rtx_code code = GET_CODE (shift);
3421 enum shift_type shift_type;
3422 enum shift_mode shift_mode;
3423 struct shift_info info;
3430 shift_mode = QIshift;
3433 shift_mode = HIshift;
3436 shift_mode = SIshift;
3445 shift_type = SHIFT_ASHIFTRT;
3448 shift_type = SHIFT_LSHIFTRT;
3451 shift_type = SHIFT_ASHIFT;
3457 if (GET_CODE (operands[2]) != CONST_INT)
3459 /* This case must be taken care of by one of the two splitters
3460 that convert a variable shift into a loop. */
3465 int n = INTVAL (operands[2]);
3467 /* If the count is negative, make it 0. */
3470 /* If the count is too big, truncate it.
3471 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3472 do the intuitive thing. */
3473 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3474 n = GET_MODE_BITSIZE (mode);
3476 get_shift_alg (shift_type, shift_mode, n, &info);
3481 output_asm_insn (info.special, operands);
3487 /* Emit two bit shifts first. */
3488 if (info.shift2 != NULL)
3490 for (; n > 1; n -= 2)
3491 output_asm_insn (info.shift2, operands);
3494 /* Now emit one bit shifts for any residual. */
3496 output_asm_insn (info.shift1, operands);
3501 int m = GET_MODE_BITSIZE (mode) - n;
3502 const int mask = (shift_type == SHIFT_ASHIFT
3503 ? ((1 << m) - 1) << n
3507 /* Not all possibilities of rotate are supported. They shouldn't
3508 be generated, but let's watch for 'em. */
3509 if (info.shift1 == 0)
3512 /* Emit two bit rotates first. */
3513 if (info.shift2 != NULL)
3515 for (; m > 1; m -= 2)
3516 output_asm_insn (info.shift2, operands);
3519 /* Now single bit rotates for any residual. */
3521 output_asm_insn (info.shift1, operands);
3523 /* Now mask off the high bits. */
3525 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3526 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3527 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3531 output_asm_insn (insn_buf, operands);
3536 /* A loop to shift by a "large" constant value.
3537 If we have shift-by-2 insns, use them. */
3538 if (info.shift2 != NULL)
3540 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3541 names_big[REGNO (operands[4])]);
3542 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3543 output_asm_insn (info.shift2, operands);
3544 output_asm_insn ("add #0xff,%X4", operands);
3545 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3547 output_asm_insn (info.shift1, operands);
3551 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3552 names_big[REGNO (operands[4])]);
3553 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3554 output_asm_insn (info.shift1, operands);
3555 output_asm_insn ("add #0xff,%X4", operands);
3556 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3567 h8300_asm_insn_count (const char *template)
3569 unsigned int count = 1;
3571 for (; *template; template++)
3572 if (*template == '\n')
3579 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3581 rtx shift = operands[3];
3582 enum machine_mode mode = GET_MODE (shift);
3583 enum rtx_code code = GET_CODE (shift);
3584 enum shift_type shift_type;
3585 enum shift_mode shift_mode;
3586 struct shift_info info;
3587 unsigned int wlength = 0;
3592 shift_mode = QIshift;
3595 shift_mode = HIshift;
3598 shift_mode = SIshift;
3607 shift_type = SHIFT_ASHIFTRT;
3610 shift_type = SHIFT_LSHIFTRT;
3613 shift_type = SHIFT_ASHIFT;
3619 if (GET_CODE (operands[2]) != CONST_INT)
3621 /* Get the assembler code to do one shift. */
3622 get_shift_alg (shift_type, shift_mode, 1, &info);
3624 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3628 int n = INTVAL (operands[2]);
3630 /* If the count is negative, make it 0. */
3633 /* If the count is too big, truncate it.
3634 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3635 do the intuitive thing. */
3636 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3637 n = GET_MODE_BITSIZE (mode);
3639 get_shift_alg (shift_type, shift_mode, n, &info);
3644 wlength += h8300_asm_insn_count (info.special);
3646 /* Every assembly instruction used in SHIFT_SPECIAL case
3647 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3648 see xor.l, we just pretend that xor.l counts as two insns
3649 so that the insn length will be computed correctly. */
3650 if (strstr (info.special, "xor.l") != NULL)
3658 if (info.shift2 != NULL)
3660 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3664 wlength += h8300_asm_insn_count (info.shift1) * n;
3670 int m = GET_MODE_BITSIZE (mode) - n;
3672 /* Not all possibilities of rotate are supported. They shouldn't
3673 be generated, but let's watch for 'em. */
3674 if (info.shift1 == 0)
3677 if (info.shift2 != NULL)
3679 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3683 wlength += h8300_asm_insn_count (info.shift1) * m;
3685 /* Now mask off the high bits. */
3706 /* A loop to shift by a "large" constant value.
3707 If we have shift-by-2 insns, use them. */
3708 if (info.shift2 != NULL)
3710 wlength += 3 + h8300_asm_insn_count (info.shift2);
3712 wlength += h8300_asm_insn_count (info.shift1);
3716 wlength += 3 + h8300_asm_insn_count (info.shift1);
3727 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3729 rtx shift = operands[3];
3730 enum machine_mode mode = GET_MODE (shift);
3731 enum rtx_code code = GET_CODE (shift);
3732 enum shift_type shift_type;
3733 enum shift_mode shift_mode;
3734 struct shift_info info;
3739 shift_mode = QIshift;
3742 shift_mode = HIshift;
3745 shift_mode = SIshift;
3754 shift_type = SHIFT_ASHIFTRT;
3757 shift_type = SHIFT_LSHIFTRT;
3760 shift_type = SHIFT_ASHIFT;
3766 if (GET_CODE (operands[2]) != CONST_INT)
3768 /* This case must be taken care of by one of the two splitters
3769 that convert a variable shift into a loop. */
3774 int n = INTVAL (operands[2]);
3776 /* If the count is negative, make it 0. */
3779 /* If the count is too big, truncate it.
3780 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3781 do the intuitive thing. */
3782 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3783 n = GET_MODE_BITSIZE (mode);
3785 get_shift_alg (shift_type, shift_mode, n, &info);
3790 if (info.remainder == 0)
3791 return info.cc_special;
3796 return info.cc_inline;
3799 /* This case always ends with an and instruction. */
3803 /* A loop to shift by a "large" constant value.
3804 If we have shift-by-2 insns, use them. */
3805 if (info.shift2 != NULL)
3808 return info.cc_inline;
3818 /* A rotation by a non-constant will cause a loop to be generated, in
3819 which a rotation by one bit is used. A rotation by a constant,
3820 including the one in the loop, will be taken care of by
3821 output_a_rotate () at the insn emit time. */
3824 expand_a_rotate (enum rtx_code code, rtx operands[])
3826 rtx dst = operands[0];
3827 rtx src = operands[1];
3828 rtx rotate_amount = operands[2];
3829 enum machine_mode mode = GET_MODE (dst);
3832 /* We rotate in place. */
3833 emit_move_insn (dst, src);
3835 if (GET_CODE (rotate_amount) != CONST_INT)
3837 rtx counter = gen_reg_rtx (QImode);
3838 rtx start_label = gen_label_rtx ();
3839 rtx end_label = gen_label_rtx ();
3841 /* If the rotate amount is less than or equal to 0,
3842 we go out of the loop. */
3843 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3844 QImode, 0, end_label);
3846 /* Initialize the loop counter. */
3847 emit_move_insn (counter, rotate_amount);
3849 emit_label (start_label);
3851 /* Rotate by one bit. */
3852 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3853 emit_insn (gen_rtx_SET (mode, dst, tmp));
3855 /* Decrement the counter by 1. */
3856 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3857 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3859 /* If the loop counter is nonzero, we go back to the beginning
3861 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3864 emit_label (end_label);
3868 /* Rotate by AMOUNT bits. */
3869 tmp = gen_rtx (code, mode, dst, rotate_amount);
3870 emit_insn (gen_rtx_SET (mode, dst, tmp));
3876 /* Output rotate insns. */
3879 output_a_rotate (enum rtx_code code, rtx *operands)
3881 rtx dst = operands[0];
3882 rtx rotate_amount = operands[2];
3883 enum shift_mode rotate_mode;
3884 enum shift_type rotate_type;
3885 const char *insn_buf;
3888 enum machine_mode mode = GET_MODE (dst);
3890 if (GET_CODE (rotate_amount) != CONST_INT)
3896 rotate_mode = QIshift;
3899 rotate_mode = HIshift;
3902 rotate_mode = SIshift;
3911 rotate_type = SHIFT_ASHIFT;
3914 rotate_type = SHIFT_LSHIFTRT;
3920 amount = INTVAL (rotate_amount);
3922 /* Clean up AMOUNT. */
3925 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3926 amount = GET_MODE_BITSIZE (mode);
3928 /* Determine the faster direction. After this phase, amount will be
3929 at most a half of GET_MODE_BITSIZE (mode). */
3930 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3932 /* Flip the direction. */
3933 amount = GET_MODE_BITSIZE (mode) - amount;
3935 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3938 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3939 boost up the rotation. */
3940 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3941 || (mode == HImode && TARGET_H8300H && amount >= 6)
3942 || (mode == HImode && TARGET_H8300S && amount == 8)
3943 || (mode == SImode && TARGET_H8300H && amount >= 10)
3944 || (mode == SImode && TARGET_H8300S && amount >= 13))
3949 /* This code works on any family. */
3950 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3951 output_asm_insn (insn_buf, operands);
3955 /* This code works on the H8/300H and H8S. */
3956 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3957 output_asm_insn (insn_buf, operands);
3964 /* Adjust AMOUNT and flip the direction. */
3965 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3967 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3970 /* Emit rotate insns. */
3971 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3974 insn_buf = rotate_two[rotate_type][rotate_mode];
3976 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3978 for (; amount >= bits; amount -= bits)
3979 output_asm_insn (insn_buf, operands);
3986 compute_a_rotate_length (rtx *operands)
3988 rtx src = operands[1];
3989 rtx amount_rtx = operands[2];
3990 enum machine_mode mode = GET_MODE (src);
3992 unsigned int length = 0;
3994 if (GET_CODE (amount_rtx) != CONST_INT)
3997 amount = INTVAL (amount_rtx);
3999 /* Clean up AMOUNT. */
4002 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4003 amount = GET_MODE_BITSIZE (mode);
4005 /* Determine the faster direction. After this phase, amount
4006 will be at most a half of GET_MODE_BITSIZE (mode). */
4007 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4008 /* Flip the direction. */
4009 amount = GET_MODE_BITSIZE (mode) - amount;
4011 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4012 boost up the rotation. */
4013 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4014 || (mode == HImode && TARGET_H8300H && amount >= 6)
4015 || (mode == HImode && TARGET_H8300S && amount == 8)
4016 || (mode == SImode && TARGET_H8300H && amount >= 10)
4017 || (mode == SImode && TARGET_H8300S && amount >= 13))
4019 /* Adjust AMOUNT and flip the direction. */
4020 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4024 /* We use 2-bit rotations on the H8S. */
4026 amount = amount / 2 + amount % 2;
4028 /* The H8/300 uses three insns to rotate one bit, taking 6
4030 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4035 /* Fix the operands of a gen_xxx so that it could become a bit
4039 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4041 /* The bit_operand predicate accepts any memory during RTL generation, but
4042 only 'U' memory afterwards, so if this is a MEM operand, we must force
4043 it to be valid for 'U' by reloading the address. */
4045 if ((what == 0 && single_zero_operand (operands[2], QImode))
4046 || (what == 1 && single_one_operand (operands[2], QImode)))
4048 /* OK to have a memory dest. */
4049 if (GET_CODE (operands[0]) == MEM
4050 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4052 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4053 copy_to_mode_reg (Pmode,
4054 XEXP (operands[0], 0)));
4055 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4059 if (GET_CODE (operands[1]) == MEM
4060 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4062 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4063 copy_to_mode_reg (Pmode,
4064 XEXP (operands[1], 0)));
4065 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4071 /* Dest and src op must be register. */
4073 operands[1] = force_reg (QImode, operands[1]);
4075 rtx res = gen_reg_rtx (QImode);
4076 emit_insn (gen_rtx_SET (VOIDmode, res,
4077 gen_rtx (type, QImode, operands[1], operands[2])));
4078 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4083 /* Return nonzero if FUNC is an interrupt function as specified
4084 by the "interrupt" attribute. */
4087 h8300_interrupt_function_p (tree func)
4091 if (TREE_CODE (func) != FUNCTION_DECL)
4094 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4095 return a != NULL_TREE;
4098 /* Return nonzero if FUNC is a saveall function as specified by the
4099 "saveall" attribute. */
4102 h8300_saveall_function_p (tree func)
4106 if (TREE_CODE (func) != FUNCTION_DECL)
4109 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4110 return a != NULL_TREE;
4113 /* Return nonzero if FUNC is an OS_Task function as specified
4114 by the "OS_Task" attribute. */
4117 h8300_os_task_function_p (tree func)
4121 if (TREE_CODE (func) != FUNCTION_DECL)
4124 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4125 return a != NULL_TREE;
4128 /* Return nonzero if FUNC is a monitor function as specified
4129 by the "monitor" attribute. */
4132 h8300_monitor_function_p (tree func)
4136 if (TREE_CODE (func) != FUNCTION_DECL)
4139 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4140 return a != NULL_TREE;
4143 /* Return nonzero if FUNC is a function that should be called
4144 through the function vector. */
4147 h8300_funcvec_function_p (tree func)
4151 if (TREE_CODE (func) != FUNCTION_DECL)
4154 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4155 return a != NULL_TREE;
4158 /* Return nonzero if DECL is a variable that's in the eight bit
4162 h8300_eightbit_data_p (tree decl)
4166 if (TREE_CODE (decl) != VAR_DECL)
4169 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4170 return a != NULL_TREE;
4173 /* Return nonzero if DECL is a variable that's in the tiny
4177 h8300_tiny_data_p (tree decl)
4181 if (TREE_CODE (decl) != VAR_DECL)
4184 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4185 return a != NULL_TREE;
4188 /* Generate an 'interrupt_handler' attribute for decls. We convert
4189 all the pragmas to corresponding attributes. */
4192 h8300_insert_attributes (tree node, tree *attributes)
4194 if (TREE_CODE (node) == FUNCTION_DECL)
4196 if (pragma_interrupt)
4198 pragma_interrupt = 0;
4200 /* Add an 'interrupt_handler' attribute. */
4201 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4209 /* Add an 'saveall' attribute. */
4210 *attributes = tree_cons (get_identifier ("saveall"),
4216 /* Supported attributes:
4218 interrupt_handler: output a prologue and epilogue suitable for an
4221 saveall: output a prologue and epilogue that saves and restores
4222 all registers except the stack pointer.
4224 function_vector: This function should be called through the
4227 eightbit_data: This variable lives in the 8-bit data area and can
4228 be referenced with 8-bit absolute memory addresses.
4230 tiny_data: This variable lives in the tiny data area and can be
4231 referenced with 16-bit absolute memory references. */
4233 const struct attribute_spec h8300_attribute_table[] =
4235 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4236 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4237 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4238 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4239 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4240 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4241 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4242 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4243 { NULL, 0, 0, false, false, false, NULL }
4247 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4248 struct attribute_spec.handler. */
4250 h8300_handle_fndecl_attribute (tree *node, tree name,
4251 tree args ATTRIBUTE_UNUSED,
4252 int flags ATTRIBUTE_UNUSED,
4255 if (TREE_CODE (*node) != FUNCTION_DECL)
4257 warning ("`%s' attribute only applies to functions",
4258 IDENTIFIER_POINTER (name));
4259 *no_add_attrs = true;
4265 /* Handle an "eightbit_data" attribute; arguments as in
4266 struct attribute_spec.handler. */
4268 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4269 tree args ATTRIBUTE_UNUSED,
4270 int flags ATTRIBUTE_UNUSED,
4275 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4277 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4281 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4282 *no_add_attrs = true;
4288 /* Handle an "tiny_data" attribute; arguments as in
4289 struct attribute_spec.handler. */
4291 h8300_handle_tiny_data_attribute (tree *node, tree name,
4292 tree args ATTRIBUTE_UNUSED,
4293 int flags ATTRIBUTE_UNUSED,
4298 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4300 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4304 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4305 *no_add_attrs = true;
4311 /* Mark function vectors, and various small data objects. */
4314 h8300_encode_section_info (tree decl, rtx rtl, int first)
4316 int extra_flags = 0;
4318 default_encode_section_info (decl, rtl, first);
4320 if (TREE_CODE (decl) == FUNCTION_DECL
4321 && h8300_funcvec_function_p (decl))
4322 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4323 else if (TREE_CODE (decl) == VAR_DECL
4324 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4326 if (h8300_eightbit_data_p (decl))
4327 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4328 else if (first && h8300_tiny_data_p (decl))
4329 extra_flags = SYMBOL_FLAG_TINY_DATA;
4333 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4337 output_simode_bld (int bild, rtx operands[])
4341 /* Clear the destination register. */
4342 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4344 /* Now output the bit load or bit inverse load, and store it in
4347 output_asm_insn ("bild\t%Z2,%Y1", operands);
4349 output_asm_insn ("bld\t%Z2,%Y1", operands);
4351 output_asm_insn ("bst\t#0,%w0", operands);
4355 /* Determine if we can clear the destination first. */
4356 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4357 && REGNO (operands[0]) != REGNO (operands[1]));
4360 output_asm_insn ("sub.l\t%S0,%S0", operands);
4362 /* Output the bit load or bit inverse load. */
4364 output_asm_insn ("bild\t%Z2,%Y1", operands);
4366 output_asm_insn ("bld\t%Z2,%Y1", operands);
4369 output_asm_insn ("xor.l\t%S0,%S0", operands);
4371 /* Perform the bit store. */
4372 output_asm_insn ("rotxl.l\t%S0", operands);
4379 #ifndef OBJECT_FORMAT_ELF
4381 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4383 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4384 fprintf (asm_out_file, "\t.section %s\n", name);
4386 #endif /* ! OBJECT_FORMAT_ELF */
4388 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4389 which is a special case of the 'R' operand. */
4392 h8300_eightbit_constant_address_p (rtx x)
4394 /* The ranges of the 8-bit area. */
4395 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4396 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4397 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4398 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4399 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4400 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4402 unsigned HOST_WIDE_INT addr;
4404 /* We accept symbols declared with eightbit_data. */
4405 if (GET_CODE (x) == SYMBOL_REF)
4406 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4408 if (GET_CODE (x) != CONST_INT)
4414 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4415 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4416 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4419 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4420 on H8/300H and H8S. */
4423 h8300_tiny_constant_address_p (rtx x)
4425 /* The ranges of the 16-bit area. */
4426 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4427 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4428 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4429 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4430 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4431 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4432 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4433 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4435 unsigned HOST_WIDE_INT addr;
4437 /* We accept symbols declared with tiny_data. */
4438 if (GET_CODE (x) == SYMBOL_REF)
4439 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4441 if (GET_CODE (x) != CONST_INT)
4447 || TARGET_NORMAL_MODE
4449 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4451 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4455 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4457 HOST_WIDE_INT offset1, offset2;
4465 else if (GET_CODE (addr1) == PLUS
4466 && REG_P (XEXP (addr1, 0))
4467 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4469 reg1 = XEXP (addr1, 0);
4470 offset1 = INTVAL (XEXP (addr1, 1));
4480 else if (GET_CODE (addr2) == PLUS
4481 && REG_P (XEXP (addr2, 0))
4482 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4484 reg2 = XEXP (addr2, 0);
4485 offset2 = INTVAL (XEXP (addr2, 1));
4490 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4491 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4493 && offset1 + 1 == offset2)
4499 /* Return nonzero if we have the same comparison insn as I3 two insns
4500 before I3. I3 is assumed to be a comparison insn. */
4503 same_cmp_preceding_p (rtx i3)
4507 /* Make sure we have a sequence of three insns. */
4508 i2 = prev_nonnote_insn (i3);
4511 i1 = prev_nonnote_insn (i2);
4515 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4516 && any_condjump_p (i2) && onlyjump_p (i2));
4519 /* Return nonzero if we have the same comparison insn as I1 two insns
4520 after I1. I1 is assumed to be a comparison insn. */
4523 same_cmp_following_p (rtx i1)
4527 /* Make sure we have a sequence of three insns. */
4528 i2 = next_nonnote_insn (i1);
4531 i3 = next_nonnote_insn (i2);
4535 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4536 && any_condjump_p (i2) && onlyjump_p (i2));
4539 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4542 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4543 unsigned int new_reg)
4545 /* Interrupt functions can only use registers that have already been
4546 saved by the prologue, even if they would normally be
4549 if (h8300_current_function_interrupt_function_p ()
4550 && !regs_ever_live[new_reg])
4556 /* Perform target dependent optabs initialization. */
4558 h8300_init_libfuncs (void)
4560 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4561 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4562 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4563 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4564 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4567 /* Initialize the GCC target structure. */
4568 #undef TARGET_ATTRIBUTE_TABLE
4569 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4571 #undef TARGET_ASM_ALIGNED_HI_OP
4572 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4574 #undef TARGET_ASM_FILE_START
4575 #define TARGET_ASM_FILE_START h8300_file_start
4576 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4577 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4579 #undef TARGET_ASM_FILE_END
4580 #define TARGET_ASM_FILE_END h8300_file_end
4582 #undef TARGET_ENCODE_SECTION_INFO
4583 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4585 #undef TARGET_INSERT_ATTRIBUTES
4586 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4588 #undef TARGET_RTX_COSTS
4589 #define TARGET_RTX_COSTS h8300_rtx_costs
4591 #undef TARGET_INIT_LIBFUNCS
4592 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4594 struct gcc_target targetm = TARGET_INITIALIZER;