1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
334 byte_reg (rtx x, int b)
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
344 return names_small[REGNO (x) * 2 + b];
347 /* REGNO must be saved/restored across calls if this macro is true. */
349 #define WORD_REG_USED(regno) \
351 /* No need to save registers if this function will not return. */ \
352 && ! TREE_THIS_VOLATILE (current_function_decl) \
353 && (h8300_saveall_function_p (current_function_decl) \
354 /* Save any call saved register that was used. */ \
355 || (regs_ever_live[regno] && !call_used_regs[regno]) \
356 /* Save the frame pointer if it was used. */ \
357 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
358 /* Save any register used in an interrupt handler. */ \
359 || (h8300_current_function_interrupt_function_p () \
360 && regs_ever_live[regno]) \
361 /* Save call clobbered registers in non-leaf interrupt \
363 || (h8300_current_function_interrupt_function_p () \
364 && call_used_regs[regno] \
365 && !current_function_is_leaf)))
367 /* Output assembly language to FILE for the operation OP with operand size
368 SIZE to adjust the stack pointer. */
371 h8300_emit_stack_adjustment (int sign, unsigned int size)
373 /* If the frame size is 0, we don't have anything to do. */
377 /* H8/300 cannot add/subtract a large constant with a single
378 instruction. If a temporary register is available, load the
379 constant to it and then do the addition. */
382 && !h8300_current_function_interrupt_function_p ()
383 && !(current_function_needs_context && sign < 0))
385 rtx r3 = gen_rtx_REG (Pmode, 3);
386 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
387 emit_insn (gen_addhi3 (stack_pointer_rtx,
388 stack_pointer_rtx, r3));
392 /* The stack adjustment made here is further optimized by the
393 splitter. In case of H8/300, the splitter always splits the
394 addition emitted here to make the adjustment
397 emit_insn (gen_addhi3 (stack_pointer_rtx,
398 stack_pointer_rtx, GEN_INT (sign * size)));
400 emit_insn (gen_addsi3 (stack_pointer_rtx,
401 stack_pointer_rtx, GEN_INT (sign * size)));
405 /* Round up frame size SIZE. */
408 round_frame_size (int size)
410 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
411 & -STACK_BOUNDARY / BITS_PER_UNIT);
414 /* Compute which registers to push/pop.
415 Return a bit vector of registers. */
418 compute_saved_regs (void)
420 unsigned int saved_regs = 0;
423 /* Construct a bit vector of registers to be pushed/popped. */
424 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
426 if (WORD_REG_USED (regno))
427 saved_regs |= 1 << regno;
430 /* Don't push/pop the frame pointer as it is treated separately. */
431 if (frame_pointer_needed)
432 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
437 /* Emit an insn to push register RN. */
442 rtx reg = gen_rtx_REG (word_mode, rn);
446 x = gen_push_h8300 (reg);
447 else if (!TARGET_NORMAL_MODE)
448 x = gen_push_h8300hs_advanced (reg);
450 x = gen_push_h8300hs_normal (reg);
452 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
455 /* Emit an insn to pop register RN. */
460 rtx reg = gen_rtx_REG (word_mode, rn);
464 x = gen_pop_h8300 (reg);
465 else if (!TARGET_NORMAL_MODE)
466 x = gen_pop_h8300hs_advanced (reg);
468 x = gen_pop_h8300hs_normal (reg);
470 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
473 /* This is what the stack looks like after the prolog of
474 a function with a frame has been set up:
480 <saved registers> <- sp
482 This is what the stack looks like after the prolog of
483 a function which doesn't have a frame:
488 <saved registers> <- sp
491 /* Generate RTL code for the function prologue. */
494 h8300_expand_prologue (void)
500 /* If the current function has the OS_Task attribute set, then
501 we have a naked prologue. */
502 if (h8300_os_task_function_p (current_function_decl))
505 if (h8300_monitor_function_p (current_function_decl))
506 /* My understanding of monitor functions is they act just like
507 interrupt functions, except the prologue must mask
509 emit_insn (gen_monitor_prologue ());
511 if (frame_pointer_needed)
514 push (HARD_FRAME_POINTER_REGNUM);
515 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
518 /* Push the rest of the registers in ascending order. */
519 saved_regs = compute_saved_regs ();
520 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
523 if (saved_regs & (1 << regno))
527 /* See how many registers we can push at the same time. */
528 if ((regno == 0 || regno == 4)
529 && ((saved_regs >> regno) & 0x0f) == 0x0f)
532 else if ((regno == 0 || regno == 4)
533 && ((saved_regs >> regno) & 0x07) == 0x07)
536 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
537 && ((saved_regs >> regno) & 0x03) == 0x03)
547 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
548 gen_rtx_REG (SImode, regno + 1)));
551 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
552 gen_rtx_REG (SImode, regno + 1),
553 gen_rtx_REG (SImode, regno + 2)));
556 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
557 gen_rtx_REG (SImode, regno + 1),
558 gen_rtx_REG (SImode, regno + 2),
559 gen_rtx_REG (SImode, regno + 3)));
567 /* Leave room for locals. */
568 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
572 h8300_can_use_return_insn_p (void)
574 return (reload_completed
575 && !frame_pointer_needed
576 && get_frame_size () == 0
577 && compute_saved_regs () == 0);
580 /* Generate RTL code for the function epilogue. */
583 h8300_expand_epilogue (void)
589 if (h8300_os_task_function_p (current_function_decl))
590 /* OS_Task epilogues are nearly naked -- they just have an
594 /* Deallocate locals. */
595 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
597 /* Pop the saved registers in descending order. */
598 saved_regs = compute_saved_regs ();
599 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
602 if (saved_regs & (1 << regno))
606 /* See how many registers we can pop at the same time. */
607 if ((regno == 7 || regno == 3)
608 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
611 else if ((regno == 6 || regno == 2)
612 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
615 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
616 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
626 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
627 gen_rtx_REG (SImode, regno)));
630 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
631 gen_rtx_REG (SImode, regno - 1),
632 gen_rtx_REG (SImode, regno)));
635 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
636 gen_rtx_REG (SImode, regno - 2),
637 gen_rtx_REG (SImode, regno - 1),
638 gen_rtx_REG (SImode, regno)));
646 /* Pop frame pointer if we had one. */
647 if (frame_pointer_needed)
648 pop (HARD_FRAME_POINTER_REGNUM);
651 /* Return nonzero if the current function is an interrupt
655 h8300_current_function_interrupt_function_p (void)
657 return (h8300_interrupt_function_p (current_function_decl)
658 || h8300_monitor_function_p (current_function_decl));
661 /* Output assembly code for the start of the file. */
664 h8300_file_start (void)
666 default_file_start ();
669 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
670 else if (TARGET_H8300S)
671 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
674 /* Output assembly language code for the end of file. */
677 h8300_file_end (void)
679 fputs ("\t.end\n", asm_out_file);
682 /* Return true if OP is a valid source operand for an integer move
686 general_operand_src (rtx op, enum machine_mode mode)
688 if (GET_MODE (op) == mode
689 && GET_CODE (op) == MEM
690 && GET_CODE (XEXP (op, 0)) == POST_INC)
692 return general_operand (op, mode);
695 /* Return true if OP is a valid destination operand for an integer move
699 general_operand_dst (rtx op, enum machine_mode mode)
701 if (GET_MODE (op) == mode
702 && GET_CODE (op) == MEM
703 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
705 return general_operand (op, mode);
708 /* Return true if OP is a constant that contains only one 1 in its
709 binary representation. */
712 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
714 if (GET_CODE (operand) == CONST_INT)
716 /* We really need to do this masking because 0x80 in QImode is
717 represented as -128 for example. */
718 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
725 /* Return true if OP is a constant that contains only one 0 in its
726 binary representation. */
729 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
731 if (GET_CODE (operand) == CONST_INT)
733 /* We really need to do this masking because 0x80 in QImode is
734 represented as -128 for example. */
735 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
742 /* Return true if OP is a valid call operand. */
745 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
747 if (GET_CODE (op) == MEM)
749 rtx inside = XEXP (op, 0);
750 if (register_operand (inside, Pmode))
752 if (CONSTANT_ADDRESS_P (inside))
758 /* Return 1 if an addition/subtraction of a constant integer can be
759 transformed into two consecutive adds/subs that are faster than the
760 straightforward way. Otherwise, return 0. */
763 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
765 if (GET_CODE (op) == CONST_INT)
767 HOST_WIDE_INT value = INTVAL (op);
769 /* Force VALUE to be positive so that we do not have to consider
770 the negative case. */
773 if (TARGET_H8300H || TARGET_H8300S)
775 /* A constant addition/subtraction takes 2 states in QImode,
776 4 states in HImode, and 6 states in SImode. Thus, the
777 only case we can win is when SImode is used, in which
778 case, two adds/subs are used, taking 4 states. */
788 /* We do not profit directly by splitting addition or
789 subtraction of 3 and 4. However, since these are
790 implemented as a sequence of adds or subs, they do not
791 clobber (cc0) unlike a sequence of add.b and add.x. */
802 /* Split an add of a small constant into two adds/subs insns.
804 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
805 instead of adds/subs. */
808 split_adds_subs (enum machine_mode mode, rtx *operands)
810 HOST_WIDE_INT val = INTVAL (operands[1]);
811 rtx reg = operands[0];
812 HOST_WIDE_INT sign = 1;
813 HOST_WIDE_INT amount;
814 rtx (*gen_add) (rtx, rtx, rtx);
816 /* Force VAL to be positive so that we do not have to consider the
827 gen_add = gen_addhi3;
831 gen_add = gen_addsi3;
838 /* Try different amounts in descending order. */
839 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
843 for (; val >= amount; val -= amount)
844 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
850 /* Return true if OP is a valid call operand, and OP represents
851 an operand for a small call (4 bytes instead of 6 bytes). */
854 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
856 if (GET_CODE (op) == MEM)
858 rtx inside = XEXP (op, 0);
860 /* Register indirect is a small call. */
861 if (register_operand (inside, Pmode))
864 /* A call through the function vector is a small call too. */
865 if (GET_CODE (inside) == SYMBOL_REF
866 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
869 /* Otherwise it's a large call. */
873 /* Return true if OP is a valid jump operand. */
876 jump_address_operand (rtx op, enum machine_mode mode)
878 if (GET_CODE (op) == REG)
879 return mode == Pmode;
881 if (GET_CODE (op) == MEM)
883 rtx inside = XEXP (op, 0);
884 if (register_operand (inside, Pmode))
886 if (CONSTANT_ADDRESS_P (inside))
892 /* Recognize valid operands for bit-field instructions. */
894 extern int rtx_equal_function_value_matters;
897 bit_operand (rtx op, enum machine_mode mode)
899 /* We can accept any general operand, except that MEM operands must
900 be limited to those that use addresses valid for the 'U' constraint. */
901 if (!general_operand (op, mode))
904 /* Accept any mem during RTL generation. Otherwise, the code that does
905 insv and extzv will think that we can not handle memory. However,
906 to avoid reload problems, we only accept 'U' MEM operands after RTL
907 generation. This means that any named pattern which uses this predicate
908 must force its operands to match 'U' before emitting RTL. */
910 if (GET_CODE (op) == REG)
912 if (GET_CODE (op) == SUBREG)
914 return (GET_CODE (op) == MEM
915 && EXTRA_CONSTRAINT (op, 'U'));
919 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
921 return (GET_CODE (op) == MEM
922 && EXTRA_CONSTRAINT (op, 'U'));
925 /* Handle machine specific pragmas for compatibility with existing
926 compilers for the H8/300.
928 pragma saveall generates prologue/epilogue code which saves and
929 restores all the registers on function entry.
931 pragma interrupt saves and restores all registers, and exits with
932 an rte instruction rather than an rts. A pointer to a function
933 with this attribute may be safely used in an interrupt vector. */
936 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
938 pragma_interrupt = 1;
942 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
947 /* If the next function argument with MODE and TYPE is to be passed in
948 a register, return a reg RTX for the hard register in which to pass
949 the argument. CUM represents the state after the last argument.
950 If the argument is to be pushed, NULL_RTX is returned. */
953 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
954 tree type, int named)
956 static const char *const hand_list[] = {
975 rtx result = NULL_RTX;
979 /* Never pass unnamed arguments in registers. */
983 /* Pass 3 regs worth of data in regs when user asked on the command line. */
984 if (TARGET_QUICKCALL)
987 /* If calling hand written assembler, use 4 regs of args. */
990 const char * const *p;
992 fname = XSTR (cum->libcall, 0);
994 /* See if this libcall is one of the hand coded ones. */
995 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1006 if (mode == BLKmode)
1007 size = int_size_in_bytes (type);
1009 size = GET_MODE_SIZE (mode);
1011 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1012 && cum->nbytes / UNITS_PER_WORD <= 3)
1013 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1020 h8300_and_costs (rtx x)
1024 if (GET_MODE (x) == QImode)
1027 if (GET_MODE (x) != HImode
1028 && GET_MODE (x) != SImode)
1033 operands[2] = XEXP (x, 1);
1035 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1039 h8300_shift_costs (rtx x)
1043 if (GET_MODE (x) != QImode
1044 && GET_MODE (x) != HImode
1045 && GET_MODE (x) != SImode)
1050 operands[2] = XEXP (x, 1);
1052 return compute_a_shift_length (NULL, operands) / 2;
1056 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1062 HOST_WIDE_INT n = INTVAL (x);
1064 if (-4 <= n || n <= 4)
1075 *total = 0 + (outer_code == SET);
1079 if (TARGET_H8300H || TARGET_H8300S)
1080 *total = 0 + (outer_code == SET);
1101 *total = COSTS_N_INSNS (h8300_and_costs (x));
1104 /* We say that MOD and DIV are so expensive because otherwise we'll
1105 generate some really horrible code for division of a power of two. */
1118 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1123 if (GET_MODE (x) == HImode)
1135 /* Documentation for the machine specific operand escapes:
1137 'E' like s but negative.
1138 'F' like t but negative.
1139 'G' constant just the negative
1140 'R' print operand as a byte:8 address if appropriate, else fall back to
1142 'S' print operand as a long word
1143 'T' print operand as a word
1144 'V' find the set bit, and print its number.
1145 'W' find the clear bit, and print its number.
1146 'X' print operand as a byte
1147 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1148 If this operand isn't a register, fall back to 'R' handling.
1150 'c' print the opcode corresponding to rtl
1151 'e' first word of 32 bit value - if reg, then least reg. if mem
1152 then least. if const then most sig word
1153 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1154 then +2. if const then least sig word
1155 'j' print operand as condition code.
1156 'k' print operand as reverse condition code.
1157 's' print as low byte of 16 bit value
1158 't' print as high byte of 16 bit value
1159 'w' print as low byte of 32 bit value
1160 'x' print as 2nd byte of 32 bit value
1161 'y' print as 3rd byte of 32 bit value
1162 'z' print as msb of 32 bit value
1165 /* Return assembly language string which identifies a comparison type. */
1168 cond_string (enum rtx_code code)
1197 /* Print operand X using operand code CODE to assembly language output file
1201 print_operand (FILE *file, rtx x, int code)
1203 /* This is used for communication between codes V,W,Z and Y. */
1209 switch (GET_CODE (x))
1212 fprintf (file, "%sl", names_big[REGNO (x)]);
1215 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1222 switch (GET_CODE (x))
1225 fprintf (file, "%sh", names_big[REGNO (x)]);
1228 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1235 if (GET_CODE (x) != CONST_INT)
1237 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1240 if (GET_CODE (x) == REG)
1241 fprintf (file, "%s", names_extended[REGNO (x)]);
1246 if (GET_CODE (x) == REG)
1247 fprintf (file, "%s", names_big[REGNO (x)]);
1252 bitint = exact_log2 (INTVAL (x) & 0xff);
1255 fprintf (file, "#%d", bitint);
1258 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1261 fprintf (file, "#%d", bitint);
1265 if (GET_CODE (x) == REG)
1266 fprintf (file, "%s", byte_reg (x, 0));
1273 if (GET_CODE (x) == REG)
1274 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1276 print_operand (file, x, 'R');
1280 bitint = INTVAL (x);
1281 fprintf (file, "#%d", bitint & 7);
1284 switch (GET_CODE (x))
1287 fprintf (file, "or");
1290 fprintf (file, "xor");
1293 fprintf (file, "and");
1300 switch (GET_CODE (x))
1304 fprintf (file, "%s", names_big[REGNO (x)]);
1306 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1309 print_operand (file, x, 0);
1312 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1318 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1319 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1320 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1329 switch (GET_CODE (x))
1333 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1335 fprintf (file, "%s", names_big[REGNO (x)]);
1338 x = adjust_address (x, HImode, 2);
1339 print_operand (file, x, 0);
1342 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1348 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1349 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1350 fprintf (file, "#%ld", (val & 0xffff));
1358 fputs (cond_string (GET_CODE (x)), file);
1361 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1364 if (GET_CODE (x) == CONST_INT)
1365 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1367 fprintf (file, "%s", byte_reg (x, 0));
1370 if (GET_CODE (x) == CONST_INT)
1371 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1373 fprintf (file, "%s", byte_reg (x, 1));
1376 if (GET_CODE (x) == CONST_INT)
1377 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1379 fprintf (file, "%s",
1380 byte_reg (x, TARGET_H8300 ? 2 : 0));
1383 if (GET_CODE (x) == CONST_INT)
1384 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1386 fprintf (file, "%s",
1387 byte_reg (x, TARGET_H8300 ? 3 : 1));
1390 if (GET_CODE (x) == CONST_INT)
1391 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1393 fprintf (file, "%s", byte_reg (x, 0));
1396 if (GET_CODE (x) == CONST_INT)
1397 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1399 fprintf (file, "%s", byte_reg (x, 1));
1404 switch (GET_CODE (x))
1407 switch (GET_MODE (x))
1410 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1411 fprintf (file, "%s", byte_reg (x, 0));
1412 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1413 fprintf (file, "%s", names_big[REGNO (x)]);
1417 fprintf (file, "%s", names_big[REGNO (x)]);
1421 fprintf (file, "%s", names_extended[REGNO (x)]);
1430 rtx addr = XEXP (x, 0);
1432 fprintf (file, "@");
1433 output_address (addr);
1435 /* We fall back from smaller addressing to larger
1436 addressing in various ways depending on CODE. */
1440 /* Used for mov.b and bit operations. */
1441 if (h8300_eightbit_constant_address_p (addr))
1443 fprintf (file, ":8");
1447 /* Fall through. We should not get here if we are
1448 processing bit operations on H8/300 or H8/300H
1449 because 'U' constraint does not allow bit
1450 operations on the tiny area on these machines. */
1454 /* Used for mov.w and mov.l. */
1455 if (h8300_tiny_constant_address_p (addr))
1456 fprintf (file, ":16");
1468 fprintf (file, "#");
1469 print_operand_address (file, x);
1475 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1476 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1477 fprintf (file, "#%ld", val);
1486 /* Output assembly language output for the address ADDR to FILE. */
1489 print_operand_address (FILE *file, rtx addr)
1491 switch (GET_CODE (addr))
1494 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1498 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1502 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1506 fprintf (file, "(");
1507 if (GET_CODE (XEXP (addr, 0)) == REG)
1510 print_operand_address (file, XEXP (addr, 1));
1511 fprintf (file, ",");
1512 print_operand_address (file, XEXP (addr, 0));
1517 print_operand_address (file, XEXP (addr, 0));
1518 fprintf (file, "+");
1519 print_operand_address (file, XEXP (addr, 1));
1521 fprintf (file, ")");
1526 /* Since the H8/300 only has 16 bit pointers, negative values are also
1527 those >= 32768. This happens for example with pointer minus a
1528 constant. We don't want to turn (char *p - 2) into
1529 (char *p + 65534) because loop unrolling can build upon this
1530 (IE: char *p + 131068). */
1531 int n = INTVAL (addr);
1533 n = (int) (short) n;
1534 fprintf (file, "%d", n);
1539 output_addr_const (file, addr);
1544 /* Output all insn addresses and their sizes into the assembly language
1545 output file. This is helpful for debugging whether the length attributes
1546 in the md file are correct. This is not meant to be a user selectable
1550 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1551 int num_operands ATTRIBUTE_UNUSED)
1553 /* This holds the last insn address. */
1554 static int last_insn_address = 0;
1556 const int uid = INSN_UID (insn);
1558 if (TARGET_ADDRESSES)
1560 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1561 INSN_ADDRESSES (uid) - last_insn_address);
1562 last_insn_address = INSN_ADDRESSES (uid);
1566 /* Prepare for an SI sized move. */
1569 h8300_expand_movsi (rtx operands[])
1571 rtx src = operands[1];
1572 rtx dst = operands[0];
1573 if (!reload_in_progress && !reload_completed)
1575 if (!register_operand (dst, GET_MODE (dst)))
1577 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1578 emit_move_insn (tmp, src);
1585 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1586 Define the offset between two registers, one to be eliminated, and
1587 the other its replacement, at the start of a routine. */
1590 h8300_initial_elimination_offset (int from, int to)
1592 /* The number of bytes that the return address takes on the stack. */
1593 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1595 /* The number of bytes that the saved frame pointer takes on the stack. */
1596 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1598 /* The number of bytes that the saved registers, excluding the frame
1599 pointer, take on the stack. */
1600 int saved_regs_size = 0;
1602 /* The number of bytes that the locals takes on the stack. */
1603 int frame_size = round_frame_size (get_frame_size ());
1607 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1608 if (WORD_REG_USED (regno))
1609 saved_regs_size += UNITS_PER_WORD;
1611 /* Adjust saved_regs_size because the above loop took the frame
1612 pointer int account. */
1613 saved_regs_size -= fp_size;
1615 if (to == HARD_FRAME_POINTER_REGNUM)
1619 case ARG_POINTER_REGNUM:
1620 return pc_size + fp_size;
1621 case RETURN_ADDRESS_POINTER_REGNUM:
1623 case FRAME_POINTER_REGNUM:
1624 return -saved_regs_size;
1629 else if (to == STACK_POINTER_REGNUM)
1633 case ARG_POINTER_REGNUM:
1634 return pc_size + saved_regs_size + frame_size;
1635 case RETURN_ADDRESS_POINTER_REGNUM:
1636 return saved_regs_size + frame_size;
1637 case FRAME_POINTER_REGNUM:
1648 h8300_return_addr_rtx (int count, rtx frame)
1653 ret = gen_rtx_MEM (Pmode,
1654 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1655 else if (flag_omit_frame_pointer)
1658 ret = gen_rtx_MEM (Pmode,
1659 memory_address (Pmode,
1660 plus_constant (frame, UNITS_PER_WORD)));
1661 set_mem_alias_set (ret, get_frame_alias_set ());
1665 /* Update the condition code from the insn. */
1668 notice_update_cc (rtx body, rtx insn)
1672 switch (get_attr_cc (insn))
1675 /* Insn does not affect CC at all. */
1679 /* Insn does not change CC, but the 0'th operand has been changed. */
1680 if (cc_status.value1 != 0
1681 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1682 cc_status.value1 = 0;
1683 if (cc_status.value2 != 0
1684 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1685 cc_status.value2 = 0;
1689 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1690 The V flag is unusable. The C flag may or may not be known but
1691 that's ok because alter_cond will change tests to use EQ/NE. */
1693 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1694 set = single_set (insn);
1695 cc_status.value1 = SET_SRC (set);
1696 if (SET_DEST (set) != cc0_rtx)
1697 cc_status.value2 = SET_DEST (set);
1701 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1702 The C flag may or may not be known but that's ok because
1703 alter_cond will change tests to use EQ/NE. */
1705 cc_status.flags |= CC_NO_CARRY;
1706 set = single_set (insn);
1707 cc_status.value1 = SET_SRC (set);
1708 if (SET_DEST (set) != cc0_rtx)
1710 /* If the destination is STRICT_LOW_PART, strip off
1712 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1713 cc_status.value2 = XEXP (SET_DEST (set), 0);
1715 cc_status.value2 = SET_DEST (set);
1720 /* The insn is a compare instruction. */
1722 cc_status.value1 = SET_SRC (body);
1726 /* Insn doesn't leave CC in a usable state. */
1732 /* Return nonzero if X is a stack pointer. */
1735 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1737 return x == stack_pointer_rtx;
1740 /* Return nonzero if X is a constant whose absolute value is greater
1744 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1746 return (GET_CODE (x) == CONST_INT
1747 && abs (INTVAL (x)) > 2);
1750 /* Return nonzero if X is a constant whose absolute value is no
1754 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1756 return (GET_CODE (x) == CONST_INT
1757 && abs (INTVAL (x)) >= 8);
1760 /* Return nonzero if X is a constant expressible in QImode. */
1763 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1765 return (GET_CODE (x) == CONST_INT
1766 && (INTVAL (x) & 0xff) == INTVAL (x));
1769 /* Return nonzero if X is a constant expressible in HImode. */
1772 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1774 return (GET_CODE (x) == CONST_INT
1775 && (INTVAL (x) & 0xffff) == INTVAL (x));
1778 /* Return nonzero if X is a constant suitable for inc/dec. */
1781 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1783 return (GET_CODE (x) == CONST_INT
1784 && (CONST_OK_FOR_M (INTVAL (x))
1785 || CONST_OK_FOR_O (INTVAL (x))));
1788 /* Return nonzero if X is either EQ or NE. */
1791 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1793 enum rtx_code code = GET_CODE (x);
1795 return (code == EQ || code == NE);
1798 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1801 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1803 enum rtx_code code = GET_CODE (x);
1805 return (code == GT || code == LE || code == GTU || code == LEU);
1808 /* Return nonzero if X is either GTU or LEU. */
1811 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1813 enum rtx_code code = GET_CODE (x);
1815 return (code == GTU || code == LEU);
1818 /* Return nonzero if X is either IOR or XOR. */
1821 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1823 enum rtx_code code = GET_CODE (x);
1825 return (code == IOR || code == XOR);
1828 /* Recognize valid operators for bit instructions. */
1831 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1833 enum rtx_code code = GET_CODE (x);
1840 /* Return the length of mov instruction. */
1843 compute_mov_length (rtx *operands)
1845 /* If the mov instruction involves a memory operand, we compute the
1846 length, assuming the largest addressing mode is used, and then
1847 adjust later in the function. Otherwise, we compute and return
1848 the exact length in one step. */
1849 enum machine_mode mode = GET_MODE (operands[0]);
1850 rtx dest = operands[0];
1851 rtx src = operands[1];
1854 if (GET_CODE (src) == MEM)
1855 addr = XEXP (src, 0);
1856 else if (GET_CODE (dest) == MEM)
1857 addr = XEXP (dest, 0);
1863 unsigned int base_length;
1868 if (addr == NULL_RTX)
1871 /* The eightbit addressing is available only in QImode, so
1872 go ahead and take care of it. */
1873 if (h8300_eightbit_constant_address_p (addr))
1880 if (addr == NULL_RTX)
1885 if (src == const0_rtx)
1895 if (addr == NULL_RTX)
1900 if (GET_CODE (src) == CONST_INT)
1902 if (src == const0_rtx)
1905 if ((INTVAL (src) & 0xffff) == 0)
1908 if ((INTVAL (src) & 0xffff) == 0)
1911 if ((INTVAL (src) & 0xffff)
1912 == ((INTVAL (src) >> 16) & 0xffff))
1922 if (addr == NULL_RTX)
1927 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1940 /* Adjust the length based on the addressing mode used.
1941 Specifically, we subtract the difference between the actual
1942 length and the longest one, which is @(d:16,Rs). For SImode
1943 and SFmode, we double the adjustment because two mov.w are
1944 used to do the job. */
1946 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1947 if (GET_CODE (addr) == PRE_DEC
1948 || GET_CODE (addr) == POST_INC)
1950 if (mode == QImode || mode == HImode)
1951 return base_length - 2;
1953 /* In SImode and SFmode, we use two mov.w instructions, so
1954 double the adjustment. */
1955 return base_length - 4;
1958 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1959 in SImode and SFmode, the second mov.w involves an address
1960 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1962 if (GET_CODE (addr) == REG)
1963 return base_length - 2;
1969 unsigned int base_length;
1974 if (addr == NULL_RTX)
1977 /* The eightbit addressing is available only in QImode, so
1978 go ahead and take care of it. */
1979 if (h8300_eightbit_constant_address_p (addr))
1986 if (addr == NULL_RTX)
1991 if (src == const0_rtx)
2001 if (addr == NULL_RTX)
2005 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2011 if (GET_CODE (src) == CONST_INT)
2013 int val = INTVAL (src);
2018 if (val == (val & 0x00ff) || val == (val & 0xff00))
2021 switch (val & 0xffffffff)
2042 if (addr == NULL_RTX)
2047 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2060 /* Adjust the length based on the addressing mode used.
2061 Specifically, we subtract the difference between the actual
2062 length and the longest one, which is @(d:24,ERs). */
2064 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2065 if (GET_CODE (addr) == PRE_DEC
2066 || GET_CODE (addr) == POST_INC)
2067 return base_length - 6;
2069 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2070 if (GET_CODE (addr) == REG)
2071 return base_length - 6;
2073 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2075 if (GET_CODE (addr) == PLUS
2076 && GET_CODE (XEXP (addr, 0)) == REG
2077 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2078 && INTVAL (XEXP (addr, 1)) > -32768
2079 && INTVAL (XEXP (addr, 1)) < 32767)
2080 return base_length - 4;
2082 /* @aa:16 is 4 bytes shorter than the longest. */
2083 if (h8300_tiny_constant_address_p (addr))
2084 return base_length - 4;
2086 /* @aa:24 is 2 bytes shorter than the longest. */
2087 if (CONSTANT_P (addr))
2088 return base_length - 2;
2095 output_plussi (rtx *operands)
2097 enum machine_mode mode = GET_MODE (operands[0]);
2104 if (GET_CODE (operands[2]) == REG)
2105 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2107 if (GET_CODE (operands[2]) == CONST_INT)
2109 HOST_WIDE_INT n = INTVAL (operands[2]);
2111 if ((n & 0xffffff) == 0)
2112 return "add\t%z2,%z0";
2113 if ((n & 0xffff) == 0)
2114 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2115 if ((n & 0xff) == 0)
2116 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2119 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2123 if (GET_CODE (operands[2]) == REG)
2124 return "add.l\t%S2,%S0";
2126 if (GET_CODE (operands[2]) == CONST_INT)
2128 HOST_WIDE_INT intval = INTVAL (operands[2]);
2130 /* See if we can finish with 2 bytes. */
2132 switch ((unsigned int) intval & 0xffffffff)
2137 return "adds\t%2,%S0";
2142 return "subs\t%G2,%S0";
2146 operands[2] = GEN_INT (intval >> 16);
2147 return "inc.w\t%2,%e0";
2151 operands[2] = GEN_INT (intval >> 16);
2152 return "dec.w\t%G2,%e0";
2155 /* See if we can finish with 4 bytes. */
2156 if ((intval & 0xffff) == 0)
2158 operands[2] = GEN_INT (intval >> 16);
2159 return "add.w\t%2,%e0";
2163 return "add.l\t%S2,%S0";
2168 compute_plussi_length (rtx *operands)
2170 enum machine_mode mode = GET_MODE (operands[0]);
2177 if (GET_CODE (operands[2]) == REG)
2180 if (GET_CODE (operands[2]) == CONST_INT)
2182 HOST_WIDE_INT n = INTVAL (operands[2]);
2184 if ((n & 0xffffff) == 0)
2186 if ((n & 0xffff) == 0)
2188 if ((n & 0xff) == 0)
2196 if (GET_CODE (operands[2]) == REG)
2199 if (GET_CODE (operands[2]) == CONST_INT)
2201 HOST_WIDE_INT intval = INTVAL (operands[2]);
2203 /* See if we can finish with 2 bytes. */
2205 switch ((unsigned int) intval & 0xffffffff)
2226 /* See if we can finish with 4 bytes. */
2227 if ((intval & 0xffff) == 0)
2236 compute_plussi_cc (rtx *operands)
2238 enum machine_mode mode = GET_MODE (operands[0]);
2249 if (GET_CODE (operands[2]) == REG)
2252 if (GET_CODE (operands[2]) == CONST_INT)
2254 HOST_WIDE_INT intval = INTVAL (operands[2]);
2256 /* See if we can finish with 2 bytes. */
2258 switch ((unsigned int) intval & 0xffffffff)
2263 return CC_NONE_0HIT;
2268 return CC_NONE_0HIT;
2279 /* See if we can finish with 4 bytes. */
2280 if ((intval & 0xffff) == 0)
2289 output_logical_op (enum machine_mode mode, rtx *operands)
2291 /* Figure out the logical op that we need to perform. */
2292 enum rtx_code code = GET_CODE (operands[3]);
2293 /* Pretend that every byte is affected if both operands are registers. */
2294 const unsigned HOST_WIDE_INT intval =
2295 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2296 ? INTVAL (operands[2]) : 0x55555555);
2297 /* The determinant of the algorithm. If we perform an AND, 0
2298 affects a bit. Otherwise, 1 affects a bit. */
2299 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2300 /* Break up DET into pieces. */
2301 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2302 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2303 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2304 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2305 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2306 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2307 int lower_half_easy_p = 0;
2308 int upper_half_easy_p = 0;
2309 /* The name of an insn. */
2331 /* First, see if we can finish with one insn. */
2332 if ((TARGET_H8300H || TARGET_H8300S)
2336 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2337 output_asm_insn (insn_buf, operands);
2341 /* Take care of the lower byte. */
2344 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2345 output_asm_insn (insn_buf, operands);
2347 /* Take care of the upper byte. */
2350 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2351 output_asm_insn (insn_buf, operands);
2356 if (TARGET_H8300H || TARGET_H8300S)
2358 /* Determine if the lower half can be taken care of in no more
2360 lower_half_easy_p = (b0 == 0
2362 || (code != IOR && w0 == 0xffff));
2364 /* Determine if the upper half can be taken care of in no more
2366 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2367 || (code == AND && w1 == 0xff00));
2370 /* Check if doing everything with one insn is no worse than
2371 using multiple insns. */
2372 if ((TARGET_H8300H || TARGET_H8300S)
2373 && w0 != 0 && w1 != 0
2374 && !(lower_half_easy_p && upper_half_easy_p)
2375 && !(code == IOR && w1 == 0xffff
2376 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2378 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2379 output_asm_insn (insn_buf, operands);
2383 /* Take care of the lower and upper words individually. For
2384 each word, we try different methods in the order of
2386 1) the special insn (in case of AND or XOR),
2387 2) the word-wise insn, and
2388 3) The byte-wise insn. */
2390 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2391 output_asm_insn ((code == AND)
2392 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2394 else if ((TARGET_H8300H || TARGET_H8300S)
2398 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2399 output_asm_insn (insn_buf, operands);
2405 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2406 output_asm_insn (insn_buf, operands);
2410 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2411 output_asm_insn (insn_buf, operands);
2416 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2417 output_asm_insn ((code == AND)
2418 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2420 else if ((TARGET_H8300H || TARGET_H8300S)
2423 && (w0 & 0x8000) != 0)
2425 output_asm_insn ("exts.l\t%S0", operands);
2427 else if ((TARGET_H8300H || TARGET_H8300S)
2431 output_asm_insn ("extu.w\t%e0", operands);
2433 else if (TARGET_H8300H || TARGET_H8300S)
2437 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2438 output_asm_insn (insn_buf, operands);
2445 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2446 output_asm_insn (insn_buf, operands);
2450 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2451 output_asm_insn (insn_buf, operands);
2463 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2465 /* Figure out the logical op that we need to perform. */
2466 enum rtx_code code = GET_CODE (operands[3]);
2467 /* Pretend that every byte is affected if both operands are registers. */
2468 const unsigned HOST_WIDE_INT intval =
2469 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2470 ? INTVAL (operands[2]) : 0x55555555);
2471 /* The determinant of the algorithm. If we perform an AND, 0
2472 affects a bit. Otherwise, 1 affects a bit. */
2473 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2474 /* Break up DET into pieces. */
2475 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2476 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2477 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2478 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2479 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2480 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2481 int lower_half_easy_p = 0;
2482 int upper_half_easy_p = 0;
2484 unsigned int length = 0;
2489 /* First, see if we can finish with one insn. */
2490 if ((TARGET_H8300H || TARGET_H8300S)
2494 if (REG_P (operands[2]))
2501 /* Take care of the lower byte. */
2505 /* Take care of the upper byte. */
2511 if (TARGET_H8300H || TARGET_H8300S)
2513 /* Determine if the lower half can be taken care of in no more
2515 lower_half_easy_p = (b0 == 0
2517 || (code != IOR && w0 == 0xffff));
2519 /* Determine if the upper half can be taken care of in no more
2521 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2522 || (code == AND && w1 == 0xff00));
2525 /* Check if doing everything with one insn is no worse than
2526 using multiple insns. */
2527 if ((TARGET_H8300H || TARGET_H8300S)
2528 && w0 != 0 && w1 != 0
2529 && !(lower_half_easy_p && upper_half_easy_p)
2530 && !(code == IOR && w1 == 0xffff
2531 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2533 if (REG_P (operands[2]))
2540 /* Take care of the lower and upper words individually. For
2541 each word, we try different methods in the order of
2543 1) the special insn (in case of AND or XOR),
2544 2) the word-wise insn, and
2545 3) The byte-wise insn. */
2547 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2551 else if ((TARGET_H8300H || TARGET_H8300S)
2567 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2571 else if ((TARGET_H8300H || TARGET_H8300S)
2574 && (w0 & 0x8000) != 0)
2578 else if ((TARGET_H8300H || TARGET_H8300S)
2584 else if (TARGET_H8300H || TARGET_H8300S)
2606 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2608 /* Figure out the logical op that we need to perform. */
2609 enum rtx_code code = GET_CODE (operands[3]);
2610 /* Pretend that every byte is affected if both operands are registers. */
2611 const unsigned HOST_WIDE_INT intval =
2612 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2613 ? INTVAL (operands[2]) : 0x55555555);
2614 /* The determinant of the algorithm. If we perform an AND, 0
2615 affects a bit. Otherwise, 1 affects a bit. */
2616 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2617 /* Break up DET into pieces. */
2618 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2619 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2620 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2621 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2622 int lower_half_easy_p = 0;
2623 int upper_half_easy_p = 0;
2624 /* Condition code. */
2625 enum attr_cc cc = CC_CLOBBER;
2630 /* First, see if we can finish with one insn. */
2631 if ((TARGET_H8300H || TARGET_H8300S)
2639 if (TARGET_H8300H || TARGET_H8300S)
2641 /* Determine if the lower half can be taken care of in no more
2643 lower_half_easy_p = (b0 == 0
2645 || (code != IOR && w0 == 0xffff));
2647 /* Determine if the upper half can be taken care of in no more
2649 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2650 || (code == AND && w1 == 0xff00));
2653 /* Check if doing everything with one insn is no worse than
2654 using multiple insns. */
2655 if ((TARGET_H8300H || TARGET_H8300S)
2656 && w0 != 0 && w1 != 0
2657 && !(lower_half_easy_p && upper_half_easy_p)
2658 && !(code == IOR && w1 == 0xffff
2659 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2665 if ((TARGET_H8300H || TARGET_H8300S)
2668 && (w0 & 0x8000) != 0)
2682 We devote a fair bit of code to getting efficient shifts since we
2683 can only shift one bit at a time on the H8/300 and H8/300H and only
2684 one or two bits at a time on the H8S.
2686 All shift code falls into one of the following ways of
2689 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2690 when a straight line shift is about the same size or smaller than
2693 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2694 off the bits we don't need. This is used when only a few of the
2695 bits in the original value will survive in the shifted value.
2697 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2698 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2699 shifts can be added if the shift count is slightly more than 8 or
2700 16. This case also includes other oddballs that are not worth
2703 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2705 For each shift count, we try to use code that has no trade-off
2706 between code size and speed whenever possible.
2708 If the trade-off is unavoidable, we try to be reasonable.
2709 Specifically, the fastest version is one instruction longer than
2710 the shortest version, we take the fastest version. We also provide
2711 the use a way to switch back to the shortest version with -Os.
2713 For the details of the shift algorithms for various shift counts,
2714 refer to shift_alg_[qhs]i. */
2717 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2719 switch (GET_CODE (x))
2731 /* Emit code to do shifts. */
2734 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2736 emit_move_insn (operands[0], operands[1]);
2738 /* Need a loop to get all the bits we want - we generate the
2739 code at emit time, but need to allocate a scratch reg now. */
2741 emit_insn (gen_rtx_PARALLEL
2744 gen_rtx_SET (VOIDmode, operands[0],
2745 gen_rtx_fmt_ee (code, mode,
2746 operands[0], operands[2])),
2747 gen_rtx_CLOBBER (VOIDmode,
2748 gen_rtx_SCRATCH (QImode)))));
2751 /* Symbols of the various modes which can be used as indices. */
2755 QIshift, HIshift, SIshift
2758 /* For single bit shift insns, record assembler and what bits of the
2759 condition code are valid afterwards (represented as various CC_FOO
2760 bits, 0 means CC isn't left in a usable state). */
2764 const char *const assembler;
2768 /* Assembler instruction shift table.
2770 These tables are used to look up the basic shifts.
2771 They are indexed by cpu, shift_type, and mode. */
2773 static const struct shift_insn shift_one[2][3][3] =
2779 { "shll\t%X0", CC_SET_ZNV },
2780 { "add.w\t%T0,%T0", CC_SET_ZN },
2781 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2783 /* SHIFT_LSHIFTRT */
2785 { "shlr\t%X0", CC_SET_ZNV },
2786 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2787 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2789 /* SHIFT_ASHIFTRT */
2791 { "shar\t%X0", CC_SET_ZNV },
2792 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2793 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2800 { "shll.b\t%X0", CC_SET_ZNV },
2801 { "shll.w\t%T0", CC_SET_ZNV },
2802 { "shll.l\t%S0", CC_SET_ZNV }
2804 /* SHIFT_LSHIFTRT */
2806 { "shlr.b\t%X0", CC_SET_ZNV },
2807 { "shlr.w\t%T0", CC_SET_ZNV },
2808 { "shlr.l\t%S0", CC_SET_ZNV }
2810 /* SHIFT_ASHIFTRT */
2812 { "shar.b\t%X0", CC_SET_ZNV },
2813 { "shar.w\t%T0", CC_SET_ZNV },
2814 { "shar.l\t%S0", CC_SET_ZNV }
2819 static const struct shift_insn shift_two[3][3] =
2823 { "shll.b\t#2,%X0", CC_SET_ZNV },
2824 { "shll.w\t#2,%T0", CC_SET_ZNV },
2825 { "shll.l\t#2,%S0", CC_SET_ZNV }
2827 /* SHIFT_LSHIFTRT */
2829 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2830 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2831 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2833 /* SHIFT_ASHIFTRT */
2835 { "shar.b\t#2,%X0", CC_SET_ZNV },
2836 { "shar.w\t#2,%T0", CC_SET_ZNV },
2837 { "shar.l\t#2,%S0", CC_SET_ZNV }
2841 /* Rotates are organized by which shift they'll be used in implementing.
2842 There's no need to record whether the cc is valid afterwards because
2843 it is the AND insn that will decide this. */
2845 static const char *const rotate_one[2][3][3] =
2852 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2855 /* SHIFT_LSHIFTRT */
2858 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2861 /* SHIFT_ASHIFTRT */
2864 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2876 /* SHIFT_LSHIFTRT */
2882 /* SHIFT_ASHIFTRT */
2891 static const char *const rotate_two[3][3] =
2899 /* SHIFT_LSHIFTRT */
2905 /* SHIFT_ASHIFTRT */
2914 /* Shift algorithm. */
2917 /* The number of bits to be shifted by shift1 and shift2. Valid
2918 when ALG is SHIFT_SPECIAL. */
2919 unsigned int remainder;
2921 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2922 const char *special;
2924 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2925 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2928 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2929 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2932 /* CC status for SHIFT_INLINE. */
2935 /* CC status for SHIFT_SPECIAL. */
2939 static void get_shift_alg (enum shift_type,
2940 enum shift_mode, unsigned int,
2941 struct shift_info *);
2943 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2944 best algorithm for doing the shift. The assembler code is stored
2945 in the pointers in INFO. We achieve the maximum efficiency in most
2946 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2947 SImode in particular have a lot of room to optimize.
2949 We first determine the strategy of the shift algorithm by a table
2950 lookup. If that tells us to use a hand crafted assembly code, we
2951 go into the big switch statement to find what that is. Otherwise,
2952 we resort to a generic way, such as inlining. In either case, the
2953 result is returned through INFO. */
2956 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2957 unsigned int count, struct shift_info *info)
2961 /* Find the target CPU. */
2964 else if (TARGET_H8300H)
2969 /* Find the shift algorithm. */
2970 info->alg = SHIFT_LOOP;
2974 if (count < GET_MODE_BITSIZE (QImode))
2975 info->alg = shift_alg_qi[cpu][shift_type][count];
2979 if (count < GET_MODE_BITSIZE (HImode))
2980 info->alg = shift_alg_hi[cpu][shift_type][count];
2984 if (count < GET_MODE_BITSIZE (SImode))
2985 info->alg = shift_alg_si[cpu][shift_type][count];
2992 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2996 info->remainder = count;
3000 /* It is up to the caller to know that looping clobbers cc. */
3001 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3002 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3003 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3007 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3008 info->shift2 = rotate_two[shift_type][shift_mode];
3009 info->cc_inline = CC_CLOBBER;
3013 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3014 info->remainder = 0;
3015 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3016 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3017 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3018 info->cc_special = CC_CLOBBER;
3022 /* Here we only deal with SHIFT_SPECIAL. */
3026 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3027 through the entire value. */
3028 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3030 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3042 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3044 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3046 case SHIFT_LSHIFTRT:
3048 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3050 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3052 case SHIFT_ASHIFTRT:
3053 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3057 else if ((8 <= count && count <= 13)
3058 || (TARGET_H8300S && count == 14))
3060 info->remainder = count - 8;
3065 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3067 case SHIFT_LSHIFTRT:
3070 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3071 info->shift1 = "shlr.b\t%s0";
3072 info->cc_inline = CC_SET_ZNV;
3076 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3077 info->cc_special = CC_SET_ZNV;
3080 case SHIFT_ASHIFTRT:
3083 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3084 info->shift1 = "shar.b\t%s0";
3088 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3089 info->cc_special = CC_SET_ZNV;
3094 else if (count == 14)
3100 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3102 case SHIFT_LSHIFTRT:
3104 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3106 case SHIFT_ASHIFTRT:
3108 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3109 else if (TARGET_H8300H)
3111 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3112 info->cc_special = CC_SET_ZNV;
3114 else /* TARGET_H8300S */
3119 else if (count == 15)
3124 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3126 case SHIFT_LSHIFTRT:
3127 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3129 case SHIFT_ASHIFTRT:
3130 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3137 if (TARGET_H8300 && 8 <= count && count <= 9)
3139 info->remainder = count - 8;
3144 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3146 case SHIFT_LSHIFTRT:
3147 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3148 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3150 case SHIFT_ASHIFTRT:
3151 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3155 else if (count == 8 && !TARGET_H8300)
3160 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3162 case SHIFT_LSHIFTRT:
3163 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3165 case SHIFT_ASHIFTRT:
3166 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3170 else if (count == 15 && TARGET_H8300)
3176 case SHIFT_LSHIFTRT:
3177 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3179 case SHIFT_ASHIFTRT:
3180 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3184 else if (count == 15 && !TARGET_H8300)
3189 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3190 info->cc_special = CC_SET_ZNV;
3192 case SHIFT_LSHIFTRT:
3193 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3194 info->cc_special = CC_SET_ZNV;
3196 case SHIFT_ASHIFTRT:
3200 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3201 || (TARGET_H8300H && 16 <= count && count <= 19)
3202 || (TARGET_H8300S && 16 <= count && count <= 21))
3204 info->remainder = count - 16;
3209 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3211 info->shift1 = "add.w\t%e0,%e0";
3213 case SHIFT_LSHIFTRT:
3216 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3217 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3221 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3222 info->cc_special = CC_SET_ZNV;
3225 case SHIFT_ASHIFTRT:
3228 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3229 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3233 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3234 info->cc_special = CC_SET_ZNV;
3239 else if (TARGET_H8300 && 24 <= count && count <= 28)
3241 info->remainder = count - 24;
3246 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3247 info->shift1 = "shll.b\t%z0";
3248 info->cc_inline = CC_SET_ZNV;
3250 case SHIFT_LSHIFTRT:
3251 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3252 info->shift1 = "shlr.b\t%w0";
3253 info->cc_inline = CC_SET_ZNV;
3255 case SHIFT_ASHIFTRT:
3256 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3257 info->shift1 = "shar.b\t%w0";
3258 info->cc_inline = CC_SET_ZNV;
3262 else if ((TARGET_H8300H && count == 24)
3263 || (TARGET_H8300S && 24 <= count && count <= 25))
3265 info->remainder = count - 24;
3270 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3272 case SHIFT_LSHIFTRT:
3273 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3274 info->cc_special = CC_SET_ZNV;
3276 case SHIFT_ASHIFTRT:
3277 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3278 info->cc_special = CC_SET_ZNV;
3282 else if (!TARGET_H8300 && count == 28)
3288 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3290 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3292 case SHIFT_LSHIFTRT:
3295 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3296 info->cc_special = CC_SET_ZNV;
3299 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3301 case SHIFT_ASHIFTRT:
3305 else if (!TARGET_H8300 && count == 29)
3311 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3313 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3315 case SHIFT_LSHIFTRT:
3318 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3319 info->cc_special = CC_SET_ZNV;
3323 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3324 info->cc_special = CC_SET_ZNV;
3327 case SHIFT_ASHIFTRT:
3331 else if (!TARGET_H8300 && count == 30)
3337 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3339 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3341 case SHIFT_LSHIFTRT:
3343 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3345 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3347 case SHIFT_ASHIFTRT:
3351 else if (count == 31)
3358 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3360 case SHIFT_LSHIFTRT:
3361 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3363 case SHIFT_ASHIFTRT:
3364 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3373 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3374 info->cc_special = CC_SET_ZNV;
3376 case SHIFT_LSHIFTRT:
3377 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3378 info->cc_special = CC_SET_ZNV;
3380 case SHIFT_ASHIFTRT:
3381 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3382 info->cc_special = CC_SET_ZNV;
3395 info->shift2 = NULL;
3398 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3399 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3402 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3407 if (GET_MODE_BITSIZE (mode) <= count)
3410 /* Find out the target CPU. */
3413 else if (TARGET_H8300H)
3418 /* Find the shift algorithm. */
3422 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3423 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3424 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3428 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3429 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3430 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3434 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3435 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3436 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3443 /* On H8/300H, count == 8 uses a scratch register. */
3444 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3445 || (TARGET_H8300H && mode == SImode && count == 8));
3448 /* Emit the assembler code for doing shifts. */
3451 output_a_shift (rtx *operands)
3453 static int loopend_lab;
3454 rtx shift = operands[3];
3455 enum machine_mode mode = GET_MODE (shift);
3456 enum rtx_code code = GET_CODE (shift);
3457 enum shift_type shift_type;
3458 enum shift_mode shift_mode;
3459 struct shift_info info;
3466 shift_mode = QIshift;
3469 shift_mode = HIshift;
3472 shift_mode = SIshift;
3481 shift_type = SHIFT_ASHIFTRT;
3484 shift_type = SHIFT_LSHIFTRT;
3487 shift_type = SHIFT_ASHIFT;
3493 if (GET_CODE (operands[2]) != CONST_INT)
3495 /* This case must be taken care of by one of the two splitters
3496 that convert a variable shift into a loop. */
3501 int n = INTVAL (operands[2]);
3503 /* If the count is negative, make it 0. */
3506 /* If the count is too big, truncate it.
3507 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3508 do the intuitive thing. */
3509 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3510 n = GET_MODE_BITSIZE (mode);
3512 get_shift_alg (shift_type, shift_mode, n, &info);
3517 output_asm_insn (info.special, operands);
3523 /* Emit two bit shifts first. */
3524 if (info.shift2 != NULL)
3526 for (; n > 1; n -= 2)
3527 output_asm_insn (info.shift2, operands);
3530 /* Now emit one bit shifts for any residual. */
3532 output_asm_insn (info.shift1, operands);
3537 int m = GET_MODE_BITSIZE (mode) - n;
3538 const int mask = (shift_type == SHIFT_ASHIFT
3539 ? ((1 << m) - 1) << n
3543 /* Not all possibilities of rotate are supported. They shouldn't
3544 be generated, but let's watch for 'em. */
3545 if (info.shift1 == 0)
3548 /* Emit two bit rotates first. */
3549 if (info.shift2 != NULL)
3551 for (; m > 1; m -= 2)
3552 output_asm_insn (info.shift2, operands);
3555 /* Now single bit rotates for any residual. */
3557 output_asm_insn (info.shift1, operands);
3559 /* Now mask off the high bits. */
3561 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3562 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3563 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3567 output_asm_insn (insn_buf, operands);
3572 /* A loop to shift by a "large" constant value.
3573 If we have shift-by-2 insns, use them. */
3574 if (info.shift2 != NULL)
3576 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3577 names_big[REGNO (operands[4])]);
3578 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3579 output_asm_insn (info.shift2, operands);
3580 output_asm_insn ("add #0xff,%X4", operands);
3581 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3583 output_asm_insn (info.shift1, operands);
3587 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3588 names_big[REGNO (operands[4])]);
3589 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3590 output_asm_insn (info.shift1, operands);
3591 output_asm_insn ("add #0xff,%X4", operands);
3592 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3603 h8300_asm_insn_count (const char *template)
3605 unsigned int count = 1;
3607 for (; *template; template++)
3608 if (*template == '\n')
3615 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3617 rtx shift = operands[3];
3618 enum machine_mode mode = GET_MODE (shift);
3619 enum rtx_code code = GET_CODE (shift);
3620 enum shift_type shift_type;
3621 enum shift_mode shift_mode;
3622 struct shift_info info;
3623 unsigned int wlength = 0;
3628 shift_mode = QIshift;
3631 shift_mode = HIshift;
3634 shift_mode = SIshift;
3643 shift_type = SHIFT_ASHIFTRT;
3646 shift_type = SHIFT_LSHIFTRT;
3649 shift_type = SHIFT_ASHIFT;
3655 if (GET_CODE (operands[2]) != CONST_INT)
3657 /* Get the assembler code to do one shift. */
3658 get_shift_alg (shift_type, shift_mode, 1, &info);
3660 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3664 int n = INTVAL (operands[2]);
3666 /* If the count is negative, make it 0. */
3669 /* If the count is too big, truncate it.
3670 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3671 do the intuitive thing. */
3672 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3673 n = GET_MODE_BITSIZE (mode);
3675 get_shift_alg (shift_type, shift_mode, n, &info);
3680 wlength += h8300_asm_insn_count (info.special);
3682 /* Every assembly instruction used in SHIFT_SPECIAL case
3683 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3684 see xor.l, we just pretend that xor.l counts as two insns
3685 so that the insn length will be computed correctly. */
3686 if (strstr (info.special, "xor.l") != NULL)
3694 if (info.shift2 != NULL)
3696 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3700 wlength += h8300_asm_insn_count (info.shift1) * n;
3706 int m = GET_MODE_BITSIZE (mode) - n;
3708 /* Not all possibilities of rotate are supported. They shouldn't
3709 be generated, but let's watch for 'em. */
3710 if (info.shift1 == 0)
3713 if (info.shift2 != NULL)
3715 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3719 wlength += h8300_asm_insn_count (info.shift1) * m;
3721 /* Now mask off the high bits. */
3742 /* A loop to shift by a "large" constant value.
3743 If we have shift-by-2 insns, use them. */
3744 if (info.shift2 != NULL)
3746 wlength += 3 + h8300_asm_insn_count (info.shift2);
3748 wlength += h8300_asm_insn_count (info.shift1);
3752 wlength += 3 + h8300_asm_insn_count (info.shift1);
3763 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3765 rtx shift = operands[3];
3766 enum machine_mode mode = GET_MODE (shift);
3767 enum rtx_code code = GET_CODE (shift);
3768 enum shift_type shift_type;
3769 enum shift_mode shift_mode;
3770 struct shift_info info;
3775 shift_mode = QIshift;
3778 shift_mode = HIshift;
3781 shift_mode = SIshift;
3790 shift_type = SHIFT_ASHIFTRT;
3793 shift_type = SHIFT_LSHIFTRT;
3796 shift_type = SHIFT_ASHIFT;
3802 if (GET_CODE (operands[2]) != CONST_INT)
3804 /* This case must be taken care of by one of the two splitters
3805 that convert a variable shift into a loop. */
3810 int n = INTVAL (operands[2]);
3812 /* If the count is negative, make it 0. */
3815 /* If the count is too big, truncate it.
3816 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3817 do the intuitive thing. */
3818 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3819 n = GET_MODE_BITSIZE (mode);
3821 get_shift_alg (shift_type, shift_mode, n, &info);
3826 if (info.remainder == 0)
3827 return info.cc_special;
3832 return info.cc_inline;
3835 /* This case always ends with an and instruction. */
3839 /* A loop to shift by a "large" constant value.
3840 If we have shift-by-2 insns, use them. */
3841 if (info.shift2 != NULL)
3844 return info.cc_inline;
3854 /* A rotation by a non-constant will cause a loop to be generated, in
3855 which a rotation by one bit is used. A rotation by a constant,
3856 including the one in the loop, will be taken care of by
3857 output_a_rotate () at the insn emit time. */
3860 expand_a_rotate (enum rtx_code code, rtx operands[])
3862 rtx dst = operands[0];
3863 rtx src = operands[1];
3864 rtx rotate_amount = operands[2];
3865 enum machine_mode mode = GET_MODE (dst);
3868 /* We rotate in place. */
3869 emit_move_insn (dst, src);
3871 if (GET_CODE (rotate_amount) != CONST_INT)
3873 rtx counter = gen_reg_rtx (QImode);
3874 rtx start_label = gen_label_rtx ();
3875 rtx end_label = gen_label_rtx ();
3877 /* If the rotate amount is less than or equal to 0,
3878 we go out of the loop. */
3879 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
3880 QImode, 0, end_label);
3882 /* Initialize the loop counter. */
3883 emit_move_insn (counter, rotate_amount);
3885 emit_label (start_label);
3887 /* Rotate by one bit. */
3888 tmp = gen_rtx_fmt_ee (code, mode, dst, const1_rtx);
3889 emit_insn (gen_rtx_SET (mode, dst, tmp));
3891 /* Decrement the counter by 1. */
3892 tmp = gen_rtx_PLUS (QImode, counter, constm1_rtx);
3893 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3895 /* If the loop counter is nonzero, we go back to the beginning
3897 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
3900 emit_label (end_label);
3904 /* Rotate by AMOUNT bits. */
3905 tmp = gen_rtx_fmt_ee (code, mode, dst, rotate_amount);
3906 emit_insn (gen_rtx_SET (mode, dst, tmp));
3912 /* Output rotate insns. */
3915 output_a_rotate (enum rtx_code code, rtx *operands)
3917 rtx dst = operands[0];
3918 rtx rotate_amount = operands[2];
3919 enum shift_mode rotate_mode;
3920 enum shift_type rotate_type;
3921 const char *insn_buf;
3924 enum machine_mode mode = GET_MODE (dst);
3926 if (GET_CODE (rotate_amount) != CONST_INT)
3932 rotate_mode = QIshift;
3935 rotate_mode = HIshift;
3938 rotate_mode = SIshift;
3947 rotate_type = SHIFT_ASHIFT;
3950 rotate_type = SHIFT_LSHIFTRT;
3956 amount = INTVAL (rotate_amount);
3958 /* Clean up AMOUNT. */
3961 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3962 amount = GET_MODE_BITSIZE (mode);
3964 /* Determine the faster direction. After this phase, amount will be
3965 at most a half of GET_MODE_BITSIZE (mode). */
3966 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3968 /* Flip the direction. */
3969 amount = GET_MODE_BITSIZE (mode) - amount;
3971 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3974 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3975 boost up the rotation. */
3976 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3977 || (mode == HImode && TARGET_H8300H && amount >= 6)
3978 || (mode == HImode && TARGET_H8300S && amount == 8)
3979 || (mode == SImode && TARGET_H8300H && amount >= 10)
3980 || (mode == SImode && TARGET_H8300S && amount >= 13))
3985 /* This code works on any family. */
3986 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3987 output_asm_insn (insn_buf, operands);
3991 /* This code works on the H8/300H and H8S. */
3992 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3993 output_asm_insn (insn_buf, operands);
4000 /* Adjust AMOUNT and flip the direction. */
4001 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4003 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4006 /* Emit rotate insns. */
4007 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4010 insn_buf = rotate_two[rotate_type][rotate_mode];
4012 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4014 for (; amount >= bits; amount -= bits)
4015 output_asm_insn (insn_buf, operands);
4022 compute_a_rotate_length (rtx *operands)
4024 rtx src = operands[1];
4025 rtx amount_rtx = operands[2];
4026 enum machine_mode mode = GET_MODE (src);
4028 unsigned int length = 0;
4030 if (GET_CODE (amount_rtx) != CONST_INT)
4033 amount = INTVAL (amount_rtx);
4035 /* Clean up AMOUNT. */
4038 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4039 amount = GET_MODE_BITSIZE (mode);
4041 /* Determine the faster direction. After this phase, amount
4042 will be at most a half of GET_MODE_BITSIZE (mode). */
4043 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4044 /* Flip the direction. */
4045 amount = GET_MODE_BITSIZE (mode) - amount;
4047 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4048 boost up the rotation. */
4049 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4050 || (mode == HImode && TARGET_H8300H && amount >= 6)
4051 || (mode == HImode && TARGET_H8300S && amount == 8)
4052 || (mode == SImode && TARGET_H8300H && amount >= 10)
4053 || (mode == SImode && TARGET_H8300S && amount >= 13))
4055 /* Adjust AMOUNT and flip the direction. */
4056 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4060 /* We use 2-bit rotations on the H8S. */
4062 amount = amount / 2 + amount % 2;
4064 /* The H8/300 uses three insns to rotate one bit, taking 6
4066 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4071 /* Fix the operands of a gen_xxx so that it could become a bit
4075 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4077 /* The bit_operand predicate accepts any memory during RTL generation, but
4078 only 'U' memory afterwards, so if this is a MEM operand, we must force
4079 it to be valid for 'U' by reloading the address. */
4081 if ((what == 0 && single_zero_operand (operands[2], QImode))
4082 || (what == 1 && single_one_operand (operands[2], QImode)))
4084 /* OK to have a memory dest. */
4085 if (GET_CODE (operands[0]) == MEM
4086 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4088 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4089 copy_to_mode_reg (Pmode,
4090 XEXP (operands[0], 0)));
4091 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4095 if (GET_CODE (operands[1]) == MEM
4096 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4098 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4099 copy_to_mode_reg (Pmode,
4100 XEXP (operands[1], 0)));
4101 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4107 /* Dest and src op must be register. */
4109 operands[1] = force_reg (QImode, operands[1]);
4111 rtx res = gen_reg_rtx (QImode);
4115 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4118 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4121 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4126 emit_insn (gen_movqi (operands[0], res));
4131 /* Return nonzero if FUNC is an interrupt function as specified
4132 by the "interrupt" attribute. */
4135 h8300_interrupt_function_p (tree func)
4139 if (TREE_CODE (func) != FUNCTION_DECL)
4142 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4143 return a != NULL_TREE;
4146 /* Return nonzero if FUNC is a saveall function as specified by the
4147 "saveall" attribute. */
4150 h8300_saveall_function_p (tree func)
4154 if (TREE_CODE (func) != FUNCTION_DECL)
4157 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4158 return a != NULL_TREE;
4161 /* Return nonzero if FUNC is an OS_Task function as specified
4162 by the "OS_Task" attribute. */
4165 h8300_os_task_function_p (tree func)
4169 if (TREE_CODE (func) != FUNCTION_DECL)
4172 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4173 return a != NULL_TREE;
4176 /* Return nonzero if FUNC is a monitor function as specified
4177 by the "monitor" attribute. */
4180 h8300_monitor_function_p (tree func)
4184 if (TREE_CODE (func) != FUNCTION_DECL)
4187 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4188 return a != NULL_TREE;
4191 /* Return nonzero if FUNC is a function that should be called
4192 through the function vector. */
4195 h8300_funcvec_function_p (tree func)
4199 if (TREE_CODE (func) != FUNCTION_DECL)
4202 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4203 return a != NULL_TREE;
4206 /* Return nonzero if DECL is a variable that's in the eight bit
4210 h8300_eightbit_data_p (tree decl)
4214 if (TREE_CODE (decl) != VAR_DECL)
4217 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4218 return a != NULL_TREE;
4221 /* Return nonzero if DECL is a variable that's in the tiny
4225 h8300_tiny_data_p (tree decl)
4229 if (TREE_CODE (decl) != VAR_DECL)
4232 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4233 return a != NULL_TREE;
4236 /* Generate an 'interrupt_handler' attribute for decls. We convert
4237 all the pragmas to corresponding attributes. */
4240 h8300_insert_attributes (tree node, tree *attributes)
4242 if (TREE_CODE (node) == FUNCTION_DECL)
4244 if (pragma_interrupt)
4246 pragma_interrupt = 0;
4248 /* Add an 'interrupt_handler' attribute. */
4249 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4257 /* Add an 'saveall' attribute. */
4258 *attributes = tree_cons (get_identifier ("saveall"),
4264 /* Supported attributes:
4266 interrupt_handler: output a prologue and epilogue suitable for an
4269 saveall: output a prologue and epilogue that saves and restores
4270 all registers except the stack pointer.
4272 function_vector: This function should be called through the
4275 eightbit_data: This variable lives in the 8-bit data area and can
4276 be referenced with 8-bit absolute memory addresses.
4278 tiny_data: This variable lives in the tiny data area and can be
4279 referenced with 16-bit absolute memory references. */
4281 const struct attribute_spec h8300_attribute_table[] =
4283 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4284 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4285 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4286 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4287 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4288 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4289 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4290 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4291 { NULL, 0, 0, false, false, false, NULL }
4295 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4296 struct attribute_spec.handler. */
4298 h8300_handle_fndecl_attribute (tree *node, tree name,
4299 tree args ATTRIBUTE_UNUSED,
4300 int flags ATTRIBUTE_UNUSED,
4303 if (TREE_CODE (*node) != FUNCTION_DECL)
4305 warning ("`%s' attribute only applies to functions",
4306 IDENTIFIER_POINTER (name));
4307 *no_add_attrs = true;
4313 /* Handle an "eightbit_data" attribute; arguments as in
4314 struct attribute_spec.handler. */
4316 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4317 tree args ATTRIBUTE_UNUSED,
4318 int flags ATTRIBUTE_UNUSED,
4323 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4325 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4329 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4330 *no_add_attrs = true;
4336 /* Handle an "tiny_data" attribute; arguments as in
4337 struct attribute_spec.handler. */
4339 h8300_handle_tiny_data_attribute (tree *node, tree name,
4340 tree args ATTRIBUTE_UNUSED,
4341 int flags ATTRIBUTE_UNUSED,
4346 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4348 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4352 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4353 *no_add_attrs = true;
4359 /* Mark function vectors, and various small data objects. */
4362 h8300_encode_section_info (tree decl, rtx rtl, int first)
4364 int extra_flags = 0;
4366 default_encode_section_info (decl, rtl, first);
4368 if (TREE_CODE (decl) == FUNCTION_DECL
4369 && h8300_funcvec_function_p (decl))
4370 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4371 else if (TREE_CODE (decl) == VAR_DECL
4372 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4374 if (h8300_eightbit_data_p (decl))
4375 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4376 else if (first && h8300_tiny_data_p (decl))
4377 extra_flags = SYMBOL_FLAG_TINY_DATA;
4381 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4385 output_simode_bld (int bild, rtx operands[])
4389 /* Clear the destination register. */
4390 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4392 /* Now output the bit load or bit inverse load, and store it in
4395 output_asm_insn ("bild\t%Z2,%Y1", operands);
4397 output_asm_insn ("bld\t%Z2,%Y1", operands);
4399 output_asm_insn ("bst\t#0,%w0", operands);
4403 /* Determine if we can clear the destination first. */
4404 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4405 && REGNO (operands[0]) != REGNO (operands[1]));
4408 output_asm_insn ("sub.l\t%S0,%S0", operands);
4410 /* Output the bit load or bit inverse load. */
4412 output_asm_insn ("bild\t%Z2,%Y1", operands);
4414 output_asm_insn ("bld\t%Z2,%Y1", operands);
4417 output_asm_insn ("xor.l\t%S0,%S0", operands);
4419 /* Perform the bit store. */
4420 output_asm_insn ("rotxl.l\t%S0", operands);
4427 #ifndef OBJECT_FORMAT_ELF
4429 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4431 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4432 fprintf (asm_out_file, "\t.section %s\n", name);
4434 #endif /* ! OBJECT_FORMAT_ELF */
4436 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4437 which is a special case of the 'R' operand. */
4440 h8300_eightbit_constant_address_p (rtx x)
4442 /* The ranges of the 8-bit area. */
4443 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4444 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4445 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4446 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4447 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4448 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4450 unsigned HOST_WIDE_INT addr;
4452 /* We accept symbols declared with eightbit_data. */
4453 if (GET_CODE (x) == SYMBOL_REF)
4454 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4456 if (GET_CODE (x) != CONST_INT)
4462 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4463 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4464 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4467 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4468 on H8/300H and H8S. */
4471 h8300_tiny_constant_address_p (rtx x)
4473 /* The ranges of the 16-bit area. */
4474 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4475 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4476 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4477 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4478 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4479 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4480 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4481 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4483 unsigned HOST_WIDE_INT addr;
4485 switch (GET_CODE (x))
4488 /* In the normal mode, any symbol fits in the 16-bit absolute
4489 address range. We also accept symbols declared with
4491 return (TARGET_NORMAL_MODE
4492 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
4496 return (TARGET_NORMAL_MODE
4498 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4500 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4503 return TARGET_NORMAL_MODE;
4512 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4514 HOST_WIDE_INT offset1, offset2;
4522 else if (GET_CODE (addr1) == PLUS
4523 && REG_P (XEXP (addr1, 0))
4524 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4526 reg1 = XEXP (addr1, 0);
4527 offset1 = INTVAL (XEXP (addr1, 1));
4537 else if (GET_CODE (addr2) == PLUS
4538 && REG_P (XEXP (addr2, 0))
4539 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4541 reg2 = XEXP (addr2, 0);
4542 offset2 = INTVAL (XEXP (addr2, 1));
4547 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4548 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4550 && offset1 + 1 == offset2)
4556 /* Return nonzero if we have the same comparison insn as I3 two insns
4557 before I3. I3 is assumed to be a comparison insn. */
4560 same_cmp_preceding_p (rtx i3)
4564 /* Make sure we have a sequence of three insns. */
4565 i2 = prev_nonnote_insn (i3);
4568 i1 = prev_nonnote_insn (i2);
4572 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4573 && any_condjump_p (i2) && onlyjump_p (i2));
4576 /* Return nonzero if we have the same comparison insn as I1 two insns
4577 after I1. I1 is assumed to be a comparison insn. */
4580 same_cmp_following_p (rtx i1)
4584 /* Make sure we have a sequence of three insns. */
4585 i2 = next_nonnote_insn (i1);
4588 i3 = next_nonnote_insn (i2);
4592 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4593 && any_condjump_p (i2) && onlyjump_p (i2));
4596 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
4597 (or pops) N registers. OPERANDS are asssumed to be an array of
4601 h8300_regs_ok_for_stm (int n, rtx operands[])
4606 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4607 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4608 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
4610 return ((REGNO (operands[0]) == 0
4611 && REGNO (operands[1]) == 1
4612 && REGNO (operands[2]) == 2)
4613 || (REGNO (operands[0]) == 4
4614 && REGNO (operands[1]) == 5
4615 && REGNO (operands[2]) == 6));
4618 return (REGNO (operands[0]) == 0
4619 && REGNO (operands[1]) == 1
4620 && REGNO (operands[2]) == 2
4621 && REGNO (operands[3]) == 3);
4627 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4630 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4631 unsigned int new_reg)
4633 /* Interrupt functions can only use registers that have already been
4634 saved by the prologue, even if they would normally be
4637 if (h8300_current_function_interrupt_function_p ()
4638 && !regs_ever_live[new_reg])
4644 /* Return nonzero if X is a legitimate constant. */
4647 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4652 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4655 h8300_rtx_ok_for_base_p (rtx x, int strict)
4657 /* Strip off SUBREG if any. */
4658 if (GET_CODE (x) == SUBREG)
4663 ? REG_OK_FOR_BASE_STRICT_P (x)
4664 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4667 /* Return nozero if X is a legitimate address. On the H8/300, a
4668 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4669 CONSTANT_ADDRESS. */
4672 h8300_legitimate_address_p (rtx x, int strict)
4674 /* The register indirect addresses like @er0 is always valid. */
4675 if (h8300_rtx_ok_for_base_p (x, strict))
4678 if (CONSTANT_ADDRESS_P (x))
4681 if (GET_CODE (x) == PLUS
4682 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4683 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4689 /* Perform target dependent optabs initialization. */
4691 h8300_init_libfuncs (void)
4693 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4694 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4695 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4696 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4697 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4701 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4703 return (TYPE_MODE (type) == BLKmode
4704 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4707 /* Initialize the GCC target structure. */
4708 #undef TARGET_ATTRIBUTE_TABLE
4709 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4711 #undef TARGET_ASM_ALIGNED_HI_OP
4712 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4714 #undef TARGET_ASM_FILE_START
4715 #define TARGET_ASM_FILE_START h8300_file_start
4716 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4717 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4719 #undef TARGET_ASM_FILE_END
4720 #define TARGET_ASM_FILE_END h8300_file_end
4722 #undef TARGET_ENCODE_SECTION_INFO
4723 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4725 #undef TARGET_INSERT_ATTRIBUTES
4726 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4728 #undef TARGET_RTX_COSTS
4729 #define TARGET_RTX_COSTS h8300_rtx_costs
4731 #undef TARGET_INIT_LIBFUNCS
4732 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4734 #undef TARGET_RETURN_IN_MEMORY
4735 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4737 struct gcc_target targetm = TARGET_INITIALIZER;