1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
80 /* Forward declarations. */
81 static const char *byte_reg (rtx, int);
82 static int h8300_interrupt_function_p (tree);
83 static int h8300_saveall_function_p (tree);
84 static int h8300_monitor_function_p (tree);
85 static int h8300_os_task_function_p (tree);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT);
87 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
94 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
95 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree);
99 static int h8300_and_costs (rtx);
100 static int h8300_shift_costs (rtx);
101 static void h8300_push_pop (int, int, int, int);
102 static int h8300_stack_offset_p (rtx, int);
103 static int h8300_ldm_stm_regno (rtx, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx);
106 static unsigned int h8300_displacement_length (rtx, int);
107 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
108 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
109 static unsigned int h8300_unary_length (rtx);
110 static unsigned int h8300_short_immediate_length (rtx);
111 static unsigned int h8300_bitfield_length (rtx, rtx);
112 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
113 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
114 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 /* CPU_TYPE, says what cpu we're compiling for. */
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt;
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall;
126 static const char *const names_big[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
129 static const char *const names_extended[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
132 static const char *const names_upper_extended[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names;
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
141 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio;
146 /* See below where shifts are handled for explanation of this enum. */
156 /* Symbols of the various shifts which can be used as indices. */
160 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
174 static enum shift_alg shift_alg_qi[3][3][8] = {
177 /* 0 1 2 3 4 5 6 7 */
178 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
179 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
180 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
187 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
194 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
198 static enum shift_alg shift_alg_hi[3][3][16] = {
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL, INL, INL, INL, INL, INL, INL, SPC,
204 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
205 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
207 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL, INL, INL, INL, INL, INL, INL, SPC,
215 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, INL, INL, SPC,
217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL, INL, INL, INL, INL, INL, INL, INL,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
227 { INL, INL, INL, INL, INL, INL, INL, INL,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
234 static enum shift_alg shift_alg_si[3][3][32] = {
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
242 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
243 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
244 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
245 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
247 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
248 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
249 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
251 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
262 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
263 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
264 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
266 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
268 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
270 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL, INL, INL, INL, INL, INL, INL, INL,
280 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
281 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
282 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
283 { INL, INL, INL, INL, INL, INL, INL, INL,
284 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
285 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
286 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
287 { INL, INL, INL, INL, INL, INL, INL, INL,
288 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
289 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
290 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
306 /* Initialize various cpu specific globals at start up. */
309 h8300_init_once (void)
311 static const char *const h8_push_ops[2] = { "push" , "push.l" };
312 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
313 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
317 cpu_type = (int) CPU_H8300;
318 h8_reg_names = names_big;
322 /* For this we treat the H8/300H and H8S the same. */
323 cpu_type = (int) CPU_H8300H;
324 h8_reg_names = names_extended;
326 h8_push_op = h8_push_ops[cpu_type];
327 h8_pop_op = h8_pop_ops[cpu_type];
328 h8_mov_op = h8_mov_ops[cpu_type];
330 if (!TARGET_H8300S && TARGET_MAC)
332 error ("-ms2600 is used without -ms");
333 target_flags |= MASK_H8300S_1;
336 if (TARGET_H8300 && TARGET_NORMAL_MODE)
338 error ("-mn is used without -mh or -ms");
339 target_flags ^= MASK_NORMAL_MODE;
342 /* Some of the shifts are optimized for speed by default.
343 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
344 If optimizing for size, change shift_alg for those shift to
349 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
350 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
351 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
352 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
354 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
355 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
357 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
358 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
361 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
362 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
364 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
365 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
367 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
368 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
369 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
370 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
373 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
376 /* Work out a value for MOVE_RATIO. */
379 /* Memory-memory moves are quite expensive without the
380 h8sx instructions. */
381 h8300_move_ratio = 3;
383 else if (flag_omit_frame_pointer)
385 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
386 sometimes be as short as two individual memory-to-memory moves,
387 but since they use all the call-saved registers, it seems better
388 to allow up to three moves here. */
389 h8300_move_ratio = 4;
391 else if (optimize_size)
393 /* In this case we don't use movmd sequences since they tend
394 to be longer than calls to memcpy(). Memory-to-memory
395 moves are cheaper than for !TARGET_H8300SX, so it makes
396 sense to have a slightly higher threshold. */
397 h8300_move_ratio = 4;
401 /* We use movmd sequences for some moves since it can be quicker
402 than calling memcpy(). The sequences will need to save and
403 restore er6 though, so bump up the cost. */
404 h8300_move_ratio = 6;
408 /* Implement REG_CLASS_FROM_LETTER.
410 Some patterns need to use er6 as a scratch register. This is
411 difficult to arrange since er6 is the frame pointer and usually
414 Such patterns should define two alternatives, one which allows only
415 er6 and one which allows any general register. The former alternative
416 should have a 'd' constraint while the latter should be disparaged and
419 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
420 However, there are cases where they should be NO_REGS:
422 - 'd' should be NO_REGS when reloading a function that uses the
423 frame pointer. In this case, DESTINATION_REGS won't contain any
424 spillable registers, so the first alternative can't be used.
426 - -fno-omit-frame-pointer means that the frame pointer will
427 always be in use. It's therefore better to map 'd' to NO_REGS
428 before reload so that register allocator will pick the second
431 - we would like 'D' to be be NO_REGS when the frame pointer isn't
432 live, but we the frame pointer may turn out to be needed after
433 we start reload, and then we may have already decided we don't
434 have a choice, so we can't do that. Forcing the register
435 allocator to use er6 if possible might produce better code for
436 small functions: it's more efficient to save and restore er6 in
437 the prologue & epilogue than to do it in a define_split.
438 Hopefully disparaging 'D' will have a similar effect, without
439 forcing a reload failure if the frame pointer is found to be
443 h8300_reg_class_from_letter (int c)
454 if (!flag_omit_frame_pointer && !reload_completed)
456 if (frame_pointer_needed && reload_in_progress)
458 return DESTINATION_REGS;
461 /* The meaning of a constraint shouldn't change dynamically, so
462 we can't make this NO_REGS. */
473 /* Return the byte register name for a register rtx X. B should be 0
474 if you want a lower byte register. B should be 1 if you want an
475 upper byte register. */
478 byte_reg (rtx x, int b)
480 static const char *const names_small[] = {
481 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
482 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
485 gcc_assert (REG_P (x));
487 return names_small[REGNO (x) * 2 + b];
490 /* REGNO must be saved/restored across calls if this macro is true. */
492 #define WORD_REG_USED(regno) \
494 /* No need to save registers if this function will not return. */ \
495 && ! TREE_THIS_VOLATILE (current_function_decl) \
496 && (h8300_saveall_function_p (current_function_decl) \
497 /* Save any call saved register that was used. */ \
498 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
499 /* Save the frame pointer if it was used. */ \
500 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
501 /* Save any register used in an interrupt handler. */ \
502 || (h8300_current_function_interrupt_function_p () \
503 && df_regs_ever_live_p (regno)) \
504 /* Save call clobbered registers in non-leaf interrupt \
506 || (h8300_current_function_interrupt_function_p () \
507 && call_used_regs[regno] \
508 && !current_function_is_leaf)))
510 /* Output assembly language to FILE for the operation OP with operand size
511 SIZE to adjust the stack pointer. */
514 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size)
516 /* If the frame size is 0, we don't have anything to do. */
520 /* H8/300 cannot add/subtract a large constant with a single
521 instruction. If a temporary register is available, load the
522 constant to it and then do the addition. */
525 && !h8300_current_function_interrupt_function_p ()
526 && !(cfun->static_chain_decl != NULL && sign < 0))
528 rtx r3 = gen_rtx_REG (Pmode, 3);
529 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
530 emit_insn (gen_addhi3 (stack_pointer_rtx,
531 stack_pointer_rtx, r3));
535 /* The stack adjustment made here is further optimized by the
536 splitter. In case of H8/300, the splitter always splits the
537 addition emitted here to make the adjustment
540 emit_insn (gen_addhi3 (stack_pointer_rtx,
541 stack_pointer_rtx, GEN_INT (sign * size)));
543 emit_insn (gen_addsi3 (stack_pointer_rtx,
544 stack_pointer_rtx, GEN_INT (sign * size)));
548 /* Round up frame size SIZE. */
551 round_frame_size (HOST_WIDE_INT size)
553 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
554 & -STACK_BOUNDARY / BITS_PER_UNIT);
557 /* Compute which registers to push/pop.
558 Return a bit vector of registers. */
561 compute_saved_regs (void)
563 unsigned int saved_regs = 0;
566 /* Construct a bit vector of registers to be pushed/popped. */
567 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
569 if (WORD_REG_USED (regno))
570 saved_regs |= 1 << regno;
573 /* Don't push/pop the frame pointer as it is treated separately. */
574 if (frame_pointer_needed)
575 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
580 /* Emit an insn to push register RN. */
585 rtx reg = gen_rtx_REG (word_mode, rn);
589 x = gen_push_h8300 (reg);
590 else if (!TARGET_NORMAL_MODE)
591 x = gen_push_h8300hs_advanced (reg);
593 x = gen_push_h8300hs_normal (reg);
595 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
598 /* Emit an insn to pop register RN. */
603 rtx reg = gen_rtx_REG (word_mode, rn);
607 x = gen_pop_h8300 (reg);
608 else if (!TARGET_NORMAL_MODE)
609 x = gen_pop_h8300hs_advanced (reg);
611 x = gen_pop_h8300hs_normal (reg);
613 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
616 /* Emit an instruction to push or pop NREGS consecutive registers
617 starting at register REGNO. POP_P selects a pop rather than a
618 push and RETURN_P is true if the instruction should return.
620 It must be possible to do the requested operation in a single
621 instruction. If NREGS == 1 && !RETURN_P, use a normal push
622 or pop insn. Otherwise emit a parallel of the form:
625 [(return) ;; if RETURN_P
626 (save or restore REGNO)
627 (save or restore REGNO + 1)
629 (save or restore REGNO + NREGS - 1)
630 (set sp (plus sp (const_int adjust)))] */
633 h8300_push_pop (int regno, int nregs, int pop_p, int return_p)
639 /* See whether we can use a simple push or pop. */
640 if (!return_p && nregs == 1)
649 /* We need one element for the return insn, if present, one for each
650 register, and one for stack adjustment. */
651 vec = rtvec_alloc ((return_p != 0) + nregs + 1);
652 sp = stack_pointer_rtx;
655 /* Add the return instruction. */
658 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
662 /* Add the register moves. */
663 for (j = 0; j < nregs; j++)
669 /* Register REGNO + NREGS - 1 is popped first. Before the
670 stack adjustment, its slot is at address @sp. */
671 lhs = gen_rtx_REG (SImode, regno + j);
672 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
676 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
677 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
678 rhs = gen_rtx_REG (SImode, regno + j);
680 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
683 /* Add the stack adjustment. */
684 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
685 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
686 gen_rtx_PLUS (Pmode, sp, offset));
688 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
691 /* Return true if X has the value sp + OFFSET. */
694 h8300_stack_offset_p (rtx x, int offset)
697 return x == stack_pointer_rtx;
699 return (GET_CODE (x) == PLUS
700 && XEXP (x, 0) == stack_pointer_rtx
701 && GET_CODE (XEXP (x, 1)) == CONST_INT
702 && INTVAL (XEXP (x, 1)) == offset);
705 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
706 something that may be an ldm or stm instruction. If it fits
707 the required template, return the register it loads or stores,
710 LOAD_P is true if X should be a load, false if it should be a store.
711 NREGS is the number of registers that the whole instruction is expected
712 to load or store. INDEX is the index of the register that X should
713 load or store, relative to the lowest-numbered register. */
716 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
718 int regindex, memindex, offset;
721 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
723 memindex = 0, regindex = 1, offset = (index + 1) * -4;
725 if (GET_CODE (x) == SET
726 && GET_CODE (XEXP (x, regindex)) == REG
727 && GET_CODE (XEXP (x, memindex)) == MEM
728 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
729 return REGNO (XEXP (x, regindex));
734 /* Return true if the elements of VEC starting at FIRST describe an
735 ldm or stm instruction (LOAD_P says which). */
738 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
741 int nregs, i, regno, adjust;
743 /* There must be a stack adjustment, a register move, and at least one
744 other operation (a return or another register move). */
745 if (GET_NUM_ELEM (vec) < 3)
748 /* Get the range of registers to be pushed or popped. */
749 nregs = GET_NUM_ELEM (vec) - first - 1;
750 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
752 /* Check that the call to h8300_ldm_stm_regno succeeded and
753 that we're only dealing with GPRs. */
754 if (regno < 0 || regno + nregs > 8)
757 /* 2-register h8s instructions must start with an even-numbered register.
758 3- and 4-register instructions must start with er0 or er4. */
761 if ((regno & 1) != 0)
763 if (nregs > 2 && (regno & 3) != 0)
767 /* Check the other loads or stores. */
768 for (i = 1; i < nregs; i++)
769 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
773 /* Check the stack adjustment. */
774 last = RTVEC_ELT (vec, first + nregs);
775 adjust = (load_p ? nregs : -nregs) * 4;
776 return (GET_CODE (last) == SET
777 && SET_DEST (last) == stack_pointer_rtx
778 && h8300_stack_offset_p (SET_SRC (last), adjust));
781 /* This is what the stack looks like after the prolog of
782 a function with a frame has been set up:
788 <saved registers> <- sp
790 This is what the stack looks like after the prolog of
791 a function which doesn't have a frame:
796 <saved registers> <- sp
799 /* Generate RTL code for the function prologue. */
802 h8300_expand_prologue (void)
808 /* If the current function has the OS_Task attribute set, then
809 we have a naked prologue. */
810 if (h8300_os_task_function_p (current_function_decl))
813 if (h8300_monitor_function_p (current_function_decl))
814 /* My understanding of monitor functions is they act just like
815 interrupt functions, except the prologue must mask
817 emit_insn (gen_monitor_prologue ());
819 if (frame_pointer_needed)
822 push (HARD_FRAME_POINTER_REGNUM);
823 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
826 /* Push the rest of the registers in ascending order. */
827 saved_regs = compute_saved_regs ();
828 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
831 if (saved_regs & (1 << regno))
835 /* See how many registers we can push at the same time. */
836 if ((!TARGET_H8300SX || (regno & 3) == 0)
837 && ((saved_regs >> regno) & 0x0f) == 0x0f)
840 else if ((!TARGET_H8300SX || (regno & 3) == 0)
841 && ((saved_regs >> regno) & 0x07) == 0x07)
844 else if ((!TARGET_H8300SX || (regno & 1) == 0)
845 && ((saved_regs >> regno) & 0x03) == 0x03)
849 h8300_push_pop (regno, n_regs, 0, 0);
853 /* Leave room for locals. */
854 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
857 /* Return nonzero if we can use "rts" for the function currently being
861 h8300_can_use_return_insn_p (void)
863 return (reload_completed
864 && !frame_pointer_needed
865 && get_frame_size () == 0
866 && compute_saved_regs () == 0);
869 /* Generate RTL code for the function epilogue. */
872 h8300_expand_epilogue (void)
877 HOST_WIDE_INT frame_size;
880 if (h8300_os_task_function_p (current_function_decl))
881 /* OS_Task epilogues are nearly naked -- they just have an
885 frame_size = round_frame_size (get_frame_size ());
888 /* Deallocate locals. */
889 h8300_emit_stack_adjustment (1, frame_size);
891 /* Pop the saved registers in descending order. */
892 saved_regs = compute_saved_regs ();
893 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
896 if (saved_regs & (1 << regno))
900 /* See how many registers we can pop at the same time. */
901 if ((TARGET_H8300SX || (regno & 3) == 3)
902 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
905 else if ((TARGET_H8300SX || (regno & 3) == 2)
906 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
909 else if ((TARGET_H8300SX || (regno & 1) == 1)
910 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
914 /* See if this pop would be the last insn before the return.
915 If so, use rte/l or rts/l instead of pop or ldm.l. */
917 && !frame_pointer_needed
919 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
922 h8300_push_pop (regno - n_regs + 1, n_regs, 1, returned_p);
926 /* Pop frame pointer if we had one. */
927 if (frame_pointer_needed)
931 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, 1, returned_p);
935 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
938 /* Return nonzero if the current function is an interrupt
942 h8300_current_function_interrupt_function_p (void)
944 return (h8300_interrupt_function_p (current_function_decl)
945 || h8300_monitor_function_p (current_function_decl));
948 /* Output assembly code for the start of the file. */
951 h8300_file_start (void)
953 default_file_start ();
956 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
957 else if (TARGET_H8300SX)
958 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
959 else if (TARGET_H8300S)
960 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
963 /* Output assembly language code for the end of file. */
966 h8300_file_end (void)
968 fputs ("\t.end\n", asm_out_file);
971 /* Split an add of a small constant into two adds/subs insns.
973 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
974 instead of adds/subs. */
977 split_adds_subs (enum machine_mode mode, rtx *operands)
979 HOST_WIDE_INT val = INTVAL (operands[1]);
980 rtx reg = operands[0];
981 HOST_WIDE_INT sign = 1;
982 HOST_WIDE_INT amount;
983 rtx (*gen_add) (rtx, rtx, rtx);
985 /* Force VAL to be positive so that we do not have to consider the
996 gen_add = gen_addhi3;
1000 gen_add = gen_addsi3;
1007 /* Try different amounts in descending order. */
1008 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1012 for (; val >= amount; val -= amount)
1013 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1019 /* Handle machine specific pragmas for compatibility with existing
1020 compilers for the H8/300.
1022 pragma saveall generates prologue/epilogue code which saves and
1023 restores all the registers on function entry.
1025 pragma interrupt saves and restores all registers, and exits with
1026 an rte instruction rather than an rts. A pointer to a function
1027 with this attribute may be safely used in an interrupt vector. */
1030 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1032 pragma_interrupt = 1;
1036 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1041 /* If the next function argument with MODE and TYPE is to be passed in
1042 a register, return a reg RTX for the hard register in which to pass
1043 the argument. CUM represents the state after the last argument.
1044 If the argument is to be pushed, NULL_RTX is returned. */
1047 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1048 tree type, int named)
1050 static const char *const hand_list[] = {
1069 rtx result = NULL_RTX;
1073 /* Never pass unnamed arguments in registers. */
1077 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1078 if (TARGET_QUICKCALL)
1081 /* If calling hand written assembler, use 4 regs of args. */
1084 const char * const *p;
1086 fname = XSTR (cum->libcall, 0);
1088 /* See if this libcall is one of the hand coded ones. */
1089 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1100 if (mode == BLKmode)
1101 size = int_size_in_bytes (type);
1103 size = GET_MODE_SIZE (mode);
1105 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1106 && cum->nbytes / UNITS_PER_WORD <= 3)
1107 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1113 /* Compute the cost of an and insn. */
1116 h8300_and_costs (rtx x)
1120 if (GET_MODE (x) == QImode)
1123 if (GET_MODE (x) != HImode
1124 && GET_MODE (x) != SImode)
1128 operands[1] = XEXP (x, 0);
1129 operands[2] = XEXP (x, 1);
1131 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1134 /* Compute the cost of a shift insn. */
1137 h8300_shift_costs (rtx x)
1141 if (GET_MODE (x) != QImode
1142 && GET_MODE (x) != HImode
1143 && GET_MODE (x) != SImode)
1148 operands[2] = XEXP (x, 1);
1150 return compute_a_shift_length (NULL, operands) / 2;
1153 /* Worker function for TARGET_RTX_COSTS. */
1156 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1158 if (TARGET_H8300SX && outer_code == MEM)
1160 /* Estimate the number of execution states needed to calculate
1162 if (register_operand (x, VOIDmode)
1163 || GET_CODE (x) == POST_INC
1164 || GET_CODE (x) == POST_DEC
1168 *total = COSTS_N_INSNS (1);
1176 HOST_WIDE_INT n = INTVAL (x);
1180 /* Constant operands need the same number of processor
1181 states as register operands. Although we could try to
1182 use a size-based cost for !speed, the lack of
1183 of a mode makes the results very unpredictable. */
1187 if (-4 <= n || n <= 4)
1198 *total = 0 + (outer_code == SET);
1202 if (TARGET_H8300H || TARGET_H8300S)
1203 *total = 0 + (outer_code == SET);
1218 /* See comment for CONST_INT. */
1230 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1231 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1233 *total = COSTS_N_INSNS (h8300_and_costs (x));
1236 /* We say that MOD and DIV are so expensive because otherwise we'll
1237 generate some really horrible code for division of a power of two. */
1243 switch (GET_MODE (x))
1247 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1251 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1257 *total = COSTS_N_INSNS (12);
1262 switch (GET_MODE (x))
1266 *total = COSTS_N_INSNS (2);
1270 *total = COSTS_N_INSNS (5);
1276 *total = COSTS_N_INSNS (4);
1282 if (h8sx_binary_shift_operator (x, VOIDmode))
1284 *total = COSTS_N_INSNS (2);
1287 else if (h8sx_unary_shift_operator (x, VOIDmode))
1289 *total = COSTS_N_INSNS (1);
1292 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1297 if (GET_MODE (x) == HImode)
1304 *total = COSTS_N_INSNS (1);
1309 /* Documentation for the machine specific operand escapes:
1311 'E' like s but negative.
1312 'F' like t but negative.
1313 'G' constant just the negative
1314 'R' print operand as a byte:8 address if appropriate, else fall back to
1316 'S' print operand as a long word
1317 'T' print operand as a word
1318 'V' find the set bit, and print its number.
1319 'W' find the clear bit, and print its number.
1320 'X' print operand as a byte
1321 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1322 If this operand isn't a register, fall back to 'R' handling.
1324 'c' print the opcode corresponding to rtl
1325 'e' first word of 32-bit value - if reg, then least reg. if mem
1326 then least. if const then most sig word
1327 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1328 then +2. if const then least sig word
1329 'j' print operand as condition code.
1330 'k' print operand as reverse condition code.
1331 'm' convert an integer operand to a size suffix (.b, .w or .l)
1332 'o' print an integer without a leading '#'
1333 's' print as low byte of 16-bit value
1334 't' print as high byte of 16-bit value
1335 'w' print as low byte of 32-bit value
1336 'x' print as 2nd byte of 32-bit value
1337 'y' print as 3rd byte of 32-bit value
1338 'z' print as msb of 32-bit value
1341 /* Return assembly language string which identifies a comparison type. */
1344 cond_string (enum rtx_code code)
1373 /* Print operand X using operand code CODE to assembly language output file
1377 print_operand (FILE *file, rtx x, int code)
1379 /* This is used for communication between codes V,W,Z and Y. */
1385 switch (GET_CODE (x))
1388 fprintf (file, "%sl", names_big[REGNO (x)]);
1391 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1398 switch (GET_CODE (x))
1401 fprintf (file, "%sh", names_big[REGNO (x)]);
1404 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1411 gcc_assert (GET_CODE (x) == CONST_INT);
1412 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1415 if (GET_CODE (x) == REG)
1416 fprintf (file, "%s", names_extended[REGNO (x)]);
1421 if (GET_CODE (x) == REG)
1422 fprintf (file, "%s", names_big[REGNO (x)]);
1427 bitint = exact_log2 (INTVAL (x) & 0xff);
1428 gcc_assert (bitint >= 0);
1429 fprintf (file, "#%d", bitint);
1432 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1433 gcc_assert (bitint >= 0);
1434 fprintf (file, "#%d", bitint);
1438 if (GET_CODE (x) == REG)
1439 fprintf (file, "%s", byte_reg (x, 0));
1444 gcc_assert (bitint >= 0);
1445 if (GET_CODE (x) == REG)
1446 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1448 print_operand (file, x, 'R');
1452 bitint = INTVAL (x);
1453 fprintf (file, "#%d", bitint & 7);
1456 switch (GET_CODE (x))
1459 fprintf (file, "or");
1462 fprintf (file, "xor");
1465 fprintf (file, "and");
1472 switch (GET_CODE (x))
1476 fprintf (file, "%s", names_big[REGNO (x)]);
1478 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1481 print_operand (file, x, 0);
1484 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1490 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1491 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1492 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1501 switch (GET_CODE (x))
1505 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1507 fprintf (file, "%s", names_big[REGNO (x)]);
1510 x = adjust_address (x, HImode, 2);
1511 print_operand (file, x, 0);
1514 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1520 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1521 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1522 fprintf (file, "#%ld", (val & 0xffff));
1530 fputs (cond_string (GET_CODE (x)), file);
1533 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1536 gcc_assert (GET_CODE (x) == CONST_INT);
1556 print_operand_address (file, x);
1559 if (GET_CODE (x) == CONST_INT)
1560 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1562 fprintf (file, "%s", byte_reg (x, 0));
1565 if (GET_CODE (x) == CONST_INT)
1566 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1568 fprintf (file, "%s", byte_reg (x, 1));
1571 if (GET_CODE (x) == CONST_INT)
1572 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1574 fprintf (file, "%s",
1575 byte_reg (x, TARGET_H8300 ? 2 : 0));
1578 if (GET_CODE (x) == CONST_INT)
1579 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1581 fprintf (file, "%s",
1582 byte_reg (x, TARGET_H8300 ? 3 : 1));
1585 if (GET_CODE (x) == CONST_INT)
1586 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1588 fprintf (file, "%s", byte_reg (x, 0));
1591 if (GET_CODE (x) == CONST_INT)
1592 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1594 fprintf (file, "%s", byte_reg (x, 1));
1599 switch (GET_CODE (x))
1602 switch (GET_MODE (x))
1605 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1606 fprintf (file, "%s", byte_reg (x, 0));
1607 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1608 fprintf (file, "%s", names_big[REGNO (x)]);
1612 fprintf (file, "%s", names_big[REGNO (x)]);
1616 fprintf (file, "%s", names_extended[REGNO (x)]);
1625 rtx addr = XEXP (x, 0);
1627 fprintf (file, "@");
1628 output_address (addr);
1630 /* Add a length suffix to constant addresses. Although this
1631 is often unnecessary, it helps to avoid ambiguity in the
1632 syntax of mova. If we wrote an insn like:
1634 mova/w.l @(1,@foo.b),er0
1636 then .b would be considered part of the symbol name.
1637 Adding a length after foo will avoid this. */
1638 if (CONSTANT_P (addr))
1642 /* Used for mov.b and bit operations. */
1643 if (h8300_eightbit_constant_address_p (addr))
1645 fprintf (file, ":8");
1649 /* Fall through. We should not get here if we are
1650 processing bit operations on H8/300 or H8/300H
1651 because 'U' constraint does not allow bit
1652 operations on the tiny area on these machines. */
1657 if (h8300_constant_length (addr) == 2)
1658 fprintf (file, ":16");
1660 fprintf (file, ":32");
1672 fprintf (file, "#");
1673 print_operand_address (file, x);
1679 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1680 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1681 fprintf (file, "#%ld", val);
1690 /* Output assembly language output for the address ADDR to FILE. */
1693 print_operand_address (FILE *file, rtx addr)
1698 switch (GET_CODE (addr))
1701 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1705 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1709 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1713 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1717 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1721 fprintf (file, "(");
1723 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1724 if (GET_CODE (index) == REG)
1727 print_operand_address (file, XEXP (addr, 1));
1728 fprintf (file, ",");
1732 print_operand_address (file, index);
1736 print_operand (file, index, 'X');
1741 print_operand (file, index, 'T');
1746 print_operand (file, index, 'S');
1750 /* print_operand_address (file, XEXP (addr, 0)); */
1755 print_operand_address (file, XEXP (addr, 0));
1756 fprintf (file, "+");
1757 print_operand_address (file, XEXP (addr, 1));
1759 fprintf (file, ")");
1764 /* Since the H8/300 only has 16-bit pointers, negative values are also
1765 those >= 32768. This happens for example with pointer minus a
1766 constant. We don't want to turn (char *p - 2) into
1767 (char *p + 65534) because loop unrolling can build upon this
1768 (IE: char *p + 131068). */
1769 int n = INTVAL (addr);
1771 n = (int) (short) n;
1772 fprintf (file, "%d", n);
1777 output_addr_const (file, addr);
1782 /* Output all insn addresses and their sizes into the assembly language
1783 output file. This is helpful for debugging whether the length attributes
1784 in the md file are correct. This is not meant to be a user selectable
1788 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1789 int num_operands ATTRIBUTE_UNUSED)
1791 /* This holds the last insn address. */
1792 static int last_insn_address = 0;
1794 const int uid = INSN_UID (insn);
1796 if (TARGET_ADDRESSES)
1798 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1799 INSN_ADDRESSES (uid) - last_insn_address);
1800 last_insn_address = INSN_ADDRESSES (uid);
1804 /* Prepare for an SI sized move. */
1807 h8300_expand_movsi (rtx operands[])
1809 rtx src = operands[1];
1810 rtx dst = operands[0];
1811 if (!reload_in_progress && !reload_completed)
1813 if (!register_operand (dst, GET_MODE (dst)))
1815 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1816 emit_move_insn (tmp, src);
1823 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1824 Define the offset between two registers, one to be eliminated, and
1825 the other its replacement, at the start of a routine. */
1828 h8300_initial_elimination_offset (int from, int to)
1830 /* The number of bytes that the return address takes on the stack. */
1831 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1833 /* The number of bytes that the saved frame pointer takes on the stack. */
1834 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1836 /* The number of bytes that the saved registers, excluding the frame
1837 pointer, take on the stack. */
1838 int saved_regs_size = 0;
1840 /* The number of bytes that the locals takes on the stack. */
1841 int frame_size = round_frame_size (get_frame_size ());
1845 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1846 if (WORD_REG_USED (regno))
1847 saved_regs_size += UNITS_PER_WORD;
1849 /* Adjust saved_regs_size because the above loop took the frame
1850 pointer int account. */
1851 saved_regs_size -= fp_size;
1855 case HARD_FRAME_POINTER_REGNUM:
1858 case ARG_POINTER_REGNUM:
1859 return pc_size + fp_size;
1860 case RETURN_ADDRESS_POINTER_REGNUM:
1862 case FRAME_POINTER_REGNUM:
1863 return -saved_regs_size;
1868 case STACK_POINTER_REGNUM:
1871 case ARG_POINTER_REGNUM:
1872 return pc_size + saved_regs_size + frame_size;
1873 case RETURN_ADDRESS_POINTER_REGNUM:
1874 return saved_regs_size + frame_size;
1875 case FRAME_POINTER_REGNUM:
1887 /* Worker function for RETURN_ADDR_RTX. */
1890 h8300_return_addr_rtx (int count, rtx frame)
1895 ret = gen_rtx_MEM (Pmode,
1896 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1897 else if (flag_omit_frame_pointer)
1900 ret = gen_rtx_MEM (Pmode,
1901 memory_address (Pmode,
1902 plus_constant (frame, UNITS_PER_WORD)));
1903 set_mem_alias_set (ret, get_frame_alias_set ());
1907 /* Update the condition code from the insn. */
1910 notice_update_cc (rtx body, rtx insn)
1914 switch (get_attr_cc (insn))
1917 /* Insn does not affect CC at all. */
1921 /* Insn does not change CC, but the 0'th operand has been changed. */
1922 if (cc_status.value1 != 0
1923 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1924 cc_status.value1 = 0;
1925 if (cc_status.value2 != 0
1926 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1927 cc_status.value2 = 0;
1931 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1932 The V flag is unusable. The C flag may or may not be known but
1933 that's ok because alter_cond will change tests to use EQ/NE. */
1935 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1936 set = single_set (insn);
1937 cc_status.value1 = SET_SRC (set);
1938 if (SET_DEST (set) != cc0_rtx)
1939 cc_status.value2 = SET_DEST (set);
1943 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1944 The C flag may or may not be known but that's ok because
1945 alter_cond will change tests to use EQ/NE. */
1947 cc_status.flags |= CC_NO_CARRY;
1948 set = single_set (insn);
1949 cc_status.value1 = SET_SRC (set);
1950 if (SET_DEST (set) != cc0_rtx)
1952 /* If the destination is STRICT_LOW_PART, strip off
1954 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1955 cc_status.value2 = XEXP (SET_DEST (set), 0);
1957 cc_status.value2 = SET_DEST (set);
1962 /* The insn is a compare instruction. */
1964 cc_status.value1 = SET_SRC (body);
1968 /* Insn doesn't leave CC in a usable state. */
1974 /* Given that X occurs in an address of the form (plus X constant),
1975 return the part of X that is expected to be a register. There are
1976 four kinds of addressing mode to recognize:
1983 If SIZE is nonnull, and the address is one of the last three forms,
1984 set *SIZE to the index multiplication factor. Set it to 0 for
1985 plain @(dd,Rn) addresses.
1987 MODE is the mode of the value being accessed. It can be VOIDmode
1988 if the address is known to be valid, but its mode is unknown. */
1991 h8300_get_index (rtx x, enum machine_mode mode, int *size)
1998 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2001 && (mode == VOIDmode
2002 || GET_MODE_CLASS (mode) == MODE_INT
2003 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2005 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2007 /* When accessing byte-sized values, the index can be
2008 a zero-extended QImode or HImode register. */
2009 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2014 /* We're looking for addresses of the form:
2017 or (mult (zero_extend X) I)
2019 where I is the size of the operand being accessed.
2020 The canonical form of the second expression is:
2022 (and (mult (subreg X) I) J)
2024 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2027 if (GET_CODE (x) == AND
2028 && GET_CODE (XEXP (x, 1)) == CONST_INT
2030 || INTVAL (XEXP (x, 1)) == 0xff * factor
2031 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2033 index = XEXP (x, 0);
2034 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2042 if (GET_CODE (index) == MULT
2043 && GET_CODE (XEXP (index, 1)) == CONST_INT
2044 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2045 return XEXP (index, 0);
2052 static const h8300_length_table addb_length_table =
2054 /* #xx Rs @aa @Rs @xx */
2055 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2056 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2057 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2058 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2061 static const h8300_length_table addw_length_table =
2063 /* #xx Rs @aa @Rs @xx */
2064 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2065 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2066 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2067 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2070 static const h8300_length_table addl_length_table =
2072 /* #xx Rs @aa @Rs @xx */
2073 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2074 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2075 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2076 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2079 #define logicb_length_table addb_length_table
2080 #define logicw_length_table addw_length_table
2082 static const h8300_length_table logicl_length_table =
2084 /* #xx Rs @aa @Rs @xx */
2085 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2086 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2087 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2088 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2091 static const h8300_length_table movb_length_table =
2093 /* #xx Rs @aa @Rs @xx */
2094 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2095 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2096 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2097 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2100 #define movw_length_table movb_length_table
2102 static const h8300_length_table movl_length_table =
2104 /* #xx Rs @aa @Rs @xx */
2105 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2106 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2107 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2108 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2111 /* Return the size of the given address or displacement constant. */
2114 h8300_constant_length (rtx constant)
2116 /* Check for (@d:16,Reg). */
2117 if (GET_CODE (constant) == CONST_INT
2118 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2121 /* Check for (@d:16,Reg) in cases where the displacement is
2122 an absolute address. */
2123 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2129 /* Return the size of a displacement field in address ADDR, which should
2130 have the form (plus X constant). SIZE is the number of bytes being
2134 h8300_displacement_length (rtx addr, int size)
2138 offset = XEXP (addr, 1);
2140 /* Check for @(d:2,Reg). */
2141 if (register_operand (XEXP (addr, 0), VOIDmode)
2142 && GET_CODE (offset) == CONST_INT
2143 && (INTVAL (offset) == size
2144 || INTVAL (offset) == size * 2
2145 || INTVAL (offset) == size * 3))
2148 return h8300_constant_length (offset);
2151 /* Store the class of operand OP in *OPCLASS and return the length of any
2152 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2153 can be null if only the length is needed. */
2156 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2158 enum h8300_operand_class dummy;
2163 if (CONSTANT_P (op))
2165 *opclass = H8OP_IMMEDIATE;
2167 /* Byte-sized immediates are stored in the opcode fields. */
2171 /* If this is a 32-bit instruction, see whether the constant
2172 will fit into a 16-bit immediate field. */
2175 && GET_CODE (op) == CONST_INT
2176 && IN_RANGE (INTVAL (op), 0, 0xffff))
2181 else if (GET_CODE (op) == MEM)
2184 if (CONSTANT_P (op))
2186 *opclass = H8OP_MEM_ABSOLUTE;
2187 return h8300_constant_length (op);
2189 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2191 *opclass = H8OP_MEM_COMPLEX;
2192 return h8300_displacement_length (op, size);
2194 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2196 *opclass = H8OP_MEM_COMPLEX;
2199 else if (register_operand (op, VOIDmode))
2201 *opclass = H8OP_MEM_BASE;
2205 gcc_assert (register_operand (op, VOIDmode));
2206 *opclass = H8OP_REGISTER;
2210 /* Return the length of the instruction described by TABLE given that
2211 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2212 and OP2 must be an h8300_src_operand. */
2215 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2217 enum h8300_operand_class op1_class, op2_class;
2218 unsigned int size, immediate_length;
2220 size = GET_MODE_SIZE (GET_MODE (op1));
2221 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2222 + h8300_classify_operand (op2, size, &op2_class));
2223 return immediate_length + (*table)[op1_class - 1][op2_class];
2226 /* Return the length of a unary instruction such as neg or not given that
2227 its operand is OP. */
2230 h8300_unary_length (rtx op)
2232 enum h8300_operand_class opclass;
2233 unsigned int size, operand_length;
2235 size = GET_MODE_SIZE (GET_MODE (op));
2236 operand_length = h8300_classify_operand (op, size, &opclass);
2243 return (size == 4 ? 6 : 4);
2245 case H8OP_MEM_ABSOLUTE:
2246 return operand_length + (size == 4 ? 6 : 4);
2248 case H8OP_MEM_COMPLEX:
2249 return operand_length + 6;
2256 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2259 h8300_short_immediate_length (rtx op)
2261 enum h8300_operand_class opclass;
2262 unsigned int size, operand_length;
2264 size = GET_MODE_SIZE (GET_MODE (op));
2265 operand_length = h8300_classify_operand (op, size, &opclass);
2273 case H8OP_MEM_ABSOLUTE:
2274 case H8OP_MEM_COMPLEX:
2275 return 4 + operand_length;
2282 /* Likewise bitfield load and store instructions. */
2285 h8300_bitfield_length (rtx op, rtx op2)
2287 enum h8300_operand_class opclass;
2288 unsigned int size, operand_length;
2290 if (GET_CODE (op) == REG)
2292 gcc_assert (GET_CODE (op) != REG);
2294 size = GET_MODE_SIZE (GET_MODE (op));
2295 operand_length = h8300_classify_operand (op, size, &opclass);
2300 case H8OP_MEM_ABSOLUTE:
2301 case H8OP_MEM_COMPLEX:
2302 return 4 + operand_length;
2309 /* Calculate the length of general binary instruction INSN using TABLE. */
2312 h8300_binary_length (rtx insn, const h8300_length_table *table)
2316 set = single_set (insn);
2319 if (BINARY_P (SET_SRC (set)))
2320 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2321 XEXP (SET_SRC (set), 1), table);
2324 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2325 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2326 XEXP (XEXP (SET_SRC (set), 1), 1),
2331 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2332 memory reference and either (1) it has the form @(d:16,Rn) or
2333 (2) its address has the code given by INC_CODE. */
2336 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2341 if (GET_CODE (op) != MEM)
2344 addr = XEXP (op, 0);
2345 size = GET_MODE_SIZE (GET_MODE (op));
2346 if (size != 1 && size != 2)
2349 return (GET_CODE (addr) == inc_code
2350 || (GET_CODE (addr) == PLUS
2351 && GET_CODE (XEXP (addr, 0)) == REG
2352 && h8300_displacement_length (addr, size) == 2));
2355 /* Calculate the length of move instruction INSN using the given length
2356 table. Although the tables are correct for most cases, there is some
2357 irregularity in the length of mov.b and mov.w. The following forms:
2364 are two bytes shorter than most other "mov Rs, @complex" or
2365 "mov @complex,Rd" combinations. */
2368 h8300_move_length (rtx *operands, const h8300_length_table *table)
2372 size = h8300_length_from_table (operands[0], operands[1], table);
2373 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2375 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2380 /* Return the length of a mova instruction with the given operands.
2381 DEST is the register destination, SRC is the source address and
2382 OFFSET is the 16-bit or 32-bit displacement. */
2385 h8300_mova_length (rtx dest, rtx src, rtx offset)
2390 + h8300_constant_length (offset)
2391 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2392 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2397 /* Compute the length of INSN based on its length_table attribute.
2398 OPERANDS is the array of its operands. */
2401 h8300_insn_length_from_table (rtx insn, rtx * operands)
2403 switch (get_attr_length_table (insn))
2405 case LENGTH_TABLE_NONE:
2408 case LENGTH_TABLE_ADDB:
2409 return h8300_binary_length (insn, &addb_length_table);
2411 case LENGTH_TABLE_ADDW:
2412 return h8300_binary_length (insn, &addw_length_table);
2414 case LENGTH_TABLE_ADDL:
2415 return h8300_binary_length (insn, &addl_length_table);
2417 case LENGTH_TABLE_LOGICB:
2418 return h8300_binary_length (insn, &logicb_length_table);
2420 case LENGTH_TABLE_MOVB:
2421 return h8300_move_length (operands, &movb_length_table);
2423 case LENGTH_TABLE_MOVW:
2424 return h8300_move_length (operands, &movw_length_table);
2426 case LENGTH_TABLE_MOVL:
2427 return h8300_move_length (operands, &movl_length_table);
2429 case LENGTH_TABLE_MOVA:
2430 return h8300_mova_length (operands[0], operands[1], operands[2]);
2432 case LENGTH_TABLE_MOVA_ZERO:
2433 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2435 case LENGTH_TABLE_UNARY:
2436 return h8300_unary_length (operands[0]);
2438 case LENGTH_TABLE_MOV_IMM4:
2439 return 2 + h8300_classify_operand (operands[0], 0, 0);
2441 case LENGTH_TABLE_SHORT_IMMEDIATE:
2442 return h8300_short_immediate_length (operands[0]);
2444 case LENGTH_TABLE_BITFIELD:
2445 return h8300_bitfield_length (operands[0], operands[1]);
2447 case LENGTH_TABLE_BITBRANCH:
2448 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2455 /* Return true if LHS and RHS are memory references that can be mapped
2456 to the same h8sx assembly operand. LHS appears as the destination of
2457 an instruction and RHS appears as a source.
2459 Three cases are allowed:
2461 - RHS is @+Rn or @-Rn, LHS is @Rn
2462 - RHS is @Rn, LHS is @Rn+ or @Rn-
2463 - RHS and LHS have the same address and neither has side effects. */
2466 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2468 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2470 rhs = XEXP (rhs, 0);
2471 lhs = XEXP (lhs, 0);
2473 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2474 return rtx_equal_p (XEXP (rhs, 0), lhs);
2476 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2477 return rtx_equal_p (rhs, XEXP (lhs, 0));
2479 if (rtx_equal_p (rhs, lhs))
2485 /* Return true if OPERANDS[1] can be mapped to the same assembly
2486 operand as OPERANDS[0]. */
2489 h8300_operands_match_p (rtx *operands)
2491 if (register_operand (operands[0], VOIDmode)
2492 && register_operand (operands[1], VOIDmode))
2495 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2501 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2502 region DEST. The two regions do not overlap and have the common
2503 alignment given by ALIGNMENT. Return true on success.
2505 Using movmd for variable-length moves seems to involve some
2506 complex trade-offs. For instance:
2508 - Preparing for a movmd instruction is similar to preparing
2509 for a memcpy. The main difference is that the arguments
2510 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2512 - Since movmd clobbers the frame pointer, we need to save
2513 and restore it somehow when frame_pointer_needed. This can
2514 sometimes make movmd sequences longer than calls to memcpy().
2516 - The counter register is 16 bits, so the instruction is only
2517 suitable for variable-length moves when sizeof (size_t) == 2.
2518 That's only true in normal mode.
2520 - We will often lack static alignment information. Falling back
2521 on movmd.b would likely be slower than calling memcpy(), at least
2524 This function therefore only uses movmd when the length is a
2525 known constant, and only then if -fomit-frame-pointer is in
2526 effect or if we're not optimizing for size.
2528 At the moment the function uses movmd for all in-range constants,
2529 but it might be better to fall back on memcpy() for large moves
2530 if ALIGNMENT == 1. */
2533 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2534 HOST_WIDE_INT alignment)
2536 if (!flag_omit_frame_pointer && optimize_size)
2539 if (GET_CODE (length) == CONST_INT)
2541 rtx dest_reg, src_reg, first_dest, first_src;
2545 /* Use movmd.l if the alignment allows it, otherwise fall back
2547 factor = (alignment >= 2 ? 4 : 1);
2549 /* Make sure the length is within range. We can handle counter
2550 values up to 65536, although HImode truncation will make
2551 the count appear negative in rtl dumps. */
2552 n = INTVAL (length);
2553 if (n <= 0 || n / factor > 65536)
2556 /* Create temporary registers for the source and destination
2557 pointers. Initialize them to the start of each region. */
2558 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2559 src_reg = copy_addr_to_reg (XEXP (src, 0));
2561 /* Create references to the movmd source and destination blocks. */
2562 first_dest = replace_equiv_address (dest, dest_reg);
2563 first_src = replace_equiv_address (src, src_reg);
2565 set_mem_size (first_dest, GEN_INT (n & -factor));
2566 set_mem_size (first_src, GEN_INT (n & -factor));
2568 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2569 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2571 if ((n & -factor) != n)
2573 /* Move SRC and DEST past the region we just copied.
2574 This is done to update the memory attributes. */
2575 dest = adjust_address (dest, BLKmode, n & -factor);
2576 src = adjust_address (src, BLKmode, n & -factor);
2578 /* Replace the addresses with the source and destination
2579 registers, which movmd has left with the right values. */
2580 dest = replace_equiv_address (dest, dest_reg);
2581 src = replace_equiv_address (src, src_reg);
2583 /* Mop up the left-over bytes. */
2585 emit_move_insn (adjust_address (dest, HImode, 0),
2586 adjust_address (src, HImode, 0));
2588 emit_move_insn (adjust_address (dest, QImode, n & 2),
2589 adjust_address (src, QImode, n & 2));
2596 /* Move ADDR into er6 after pushing its old value onto the stack. */
2599 h8300_swap_into_er6 (rtx addr)
2601 push (HARD_FRAME_POINTER_REGNUM);
2602 emit_move_insn (hard_frame_pointer_rtx, addr);
2603 if (REGNO (addr) == SP_REG)
2604 emit_move_insn (hard_frame_pointer_rtx,
2605 plus_constant (hard_frame_pointer_rtx,
2606 GET_MODE_SIZE (word_mode)));
2609 /* Move the current value of er6 into ADDR and pop its old value
2613 h8300_swap_out_of_er6 (rtx addr)
2615 if (REGNO (addr) != SP_REG)
2616 emit_move_insn (addr, hard_frame_pointer_rtx);
2617 pop (HARD_FRAME_POINTER_REGNUM);
2620 /* Return the length of mov instruction. */
2623 compute_mov_length (rtx *operands)
2625 /* If the mov instruction involves a memory operand, we compute the
2626 length, assuming the largest addressing mode is used, and then
2627 adjust later in the function. Otherwise, we compute and return
2628 the exact length in one step. */
2629 enum machine_mode mode = GET_MODE (operands[0]);
2630 rtx dest = operands[0];
2631 rtx src = operands[1];
2634 if (GET_CODE (src) == MEM)
2635 addr = XEXP (src, 0);
2636 else if (GET_CODE (dest) == MEM)
2637 addr = XEXP (dest, 0);
2643 unsigned int base_length;
2648 if (addr == NULL_RTX)
2651 /* The eightbit addressing is available only in QImode, so
2652 go ahead and take care of it. */
2653 if (h8300_eightbit_constant_address_p (addr))
2660 if (addr == NULL_RTX)
2665 if (src == const0_rtx)
2675 if (addr == NULL_RTX)
2680 if (GET_CODE (src) == CONST_INT)
2682 if (src == const0_rtx)
2685 if ((INTVAL (src) & 0xffff) == 0)
2688 if ((INTVAL (src) & 0xffff) == 0)
2691 if ((INTVAL (src) & 0xffff)
2692 == ((INTVAL (src) >> 16) & 0xffff))
2702 if (addr == NULL_RTX)
2707 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2720 /* Adjust the length based on the addressing mode used.
2721 Specifically, we subtract the difference between the actual
2722 length and the longest one, which is @(d:16,Rs). For SImode
2723 and SFmode, we double the adjustment because two mov.w are
2724 used to do the job. */
2726 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2727 if (GET_CODE (addr) == PRE_DEC
2728 || GET_CODE (addr) == POST_INC)
2730 if (mode == QImode || mode == HImode)
2731 return base_length - 2;
2733 /* In SImode and SFmode, we use two mov.w instructions, so
2734 double the adjustment. */
2735 return base_length - 4;
2738 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2739 in SImode and SFmode, the second mov.w involves an address
2740 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2742 if (GET_CODE (addr) == REG)
2743 return base_length - 2;
2749 unsigned int base_length;
2754 if (addr == NULL_RTX)
2757 /* The eightbit addressing is available only in QImode, so
2758 go ahead and take care of it. */
2759 if (h8300_eightbit_constant_address_p (addr))
2766 if (addr == NULL_RTX)
2771 if (src == const0_rtx)
2781 if (addr == NULL_RTX)
2785 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2791 if (GET_CODE (src) == CONST_INT)
2793 int val = INTVAL (src);
2798 if (val == (val & 0x00ff) || val == (val & 0xff00))
2801 switch (val & 0xffffffff)
2822 if (addr == NULL_RTX)
2827 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2840 /* Adjust the length based on the addressing mode used.
2841 Specifically, we subtract the difference between the actual
2842 length and the longest one, which is @(d:24,ERs). */
2844 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2845 if (GET_CODE (addr) == PRE_DEC
2846 || GET_CODE (addr) == POST_INC)
2847 return base_length - 6;
2849 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2850 if (GET_CODE (addr) == REG)
2851 return base_length - 6;
2853 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2855 if (GET_CODE (addr) == PLUS
2856 && GET_CODE (XEXP (addr, 0)) == REG
2857 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2858 && INTVAL (XEXP (addr, 1)) > -32768
2859 && INTVAL (XEXP (addr, 1)) < 32767)
2860 return base_length - 4;
2862 /* @aa:16 is 4 bytes shorter than the longest. */
2863 if (h8300_tiny_constant_address_p (addr))
2864 return base_length - 4;
2866 /* @aa:24 is 2 bytes shorter than the longest. */
2867 if (CONSTANT_P (addr))
2868 return base_length - 2;
2874 /* Output an addition insn. */
2877 output_plussi (rtx *operands)
2879 enum machine_mode mode = GET_MODE (operands[0]);
2881 gcc_assert (mode == SImode);
2885 if (GET_CODE (operands[2]) == REG)
2886 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2888 if (GET_CODE (operands[2]) == CONST_INT)
2890 HOST_WIDE_INT n = INTVAL (operands[2]);
2892 if ((n & 0xffffff) == 0)
2893 return "add\t%z2,%z0";
2894 if ((n & 0xffff) == 0)
2895 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2896 if ((n & 0xff) == 0)
2897 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2900 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2904 if (GET_CODE (operands[2]) == CONST_INT
2905 && register_operand (operands[1], VOIDmode))
2907 HOST_WIDE_INT intval = INTVAL (operands[2]);
2909 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2910 return "add.l\t%S2,%S0";
2911 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2912 return "sub.l\t%G2,%S0";
2914 /* See if we can finish with 2 bytes. */
2916 switch ((unsigned int) intval & 0xffffffff)
2921 return "adds\t%2,%S0";
2926 return "subs\t%G2,%S0";
2930 operands[2] = GEN_INT (intval >> 16);
2931 return "inc.w\t%2,%e0";
2935 operands[2] = GEN_INT (intval >> 16);
2936 return "dec.w\t%G2,%e0";
2939 /* See if we can finish with 4 bytes. */
2940 if ((intval & 0xffff) == 0)
2942 operands[2] = GEN_INT (intval >> 16);
2943 return "add.w\t%2,%e0";
2947 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
2949 operands[2] = GEN_INT (-INTVAL (operands[2]));
2950 return "sub.l\t%S2,%S0";
2952 return "add.l\t%S2,%S0";
2956 /* ??? It would be much easier to add the h8sx stuff if a single function
2957 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
2958 /* Compute the length of an addition insn. */
2961 compute_plussi_length (rtx *operands)
2963 enum machine_mode mode = GET_MODE (operands[0]);
2965 gcc_assert (mode == SImode);
2969 if (GET_CODE (operands[2]) == REG)
2972 if (GET_CODE (operands[2]) == CONST_INT)
2974 HOST_WIDE_INT n = INTVAL (operands[2]);
2976 if ((n & 0xffffff) == 0)
2978 if ((n & 0xffff) == 0)
2980 if ((n & 0xff) == 0)
2988 if (GET_CODE (operands[2]) == CONST_INT
2989 && register_operand (operands[1], VOIDmode))
2991 HOST_WIDE_INT intval = INTVAL (operands[2]);
2993 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2995 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2998 /* See if we can finish with 2 bytes. */
3000 switch ((unsigned int) intval & 0xffffffff)
3021 /* See if we can finish with 4 bytes. */
3022 if ((intval & 0xffff) == 0)
3026 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3027 return h8300_length_from_table (operands[0],
3028 GEN_INT (-INTVAL (operands[2])),
3029 &addl_length_table);
3031 return h8300_length_from_table (operands[0], operands[2],
3032 &addl_length_table);
3037 /* Compute which flag bits are valid after an addition insn. */
3040 compute_plussi_cc (rtx *operands)
3042 enum machine_mode mode = GET_MODE (operands[0]);
3044 gcc_assert (mode == SImode);
3052 if (GET_CODE (operands[2]) == CONST_INT
3053 && register_operand (operands[1], VOIDmode))
3055 HOST_WIDE_INT intval = INTVAL (operands[2]);
3057 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3059 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3062 /* See if we can finish with 2 bytes. */
3064 switch ((unsigned int) intval & 0xffffffff)
3069 return CC_NONE_0HIT;
3074 return CC_NONE_0HIT;
3085 /* See if we can finish with 4 bytes. */
3086 if ((intval & 0xffff) == 0)
3094 /* Output a logical insn. */
3097 output_logical_op (enum machine_mode mode, rtx *operands)
3099 /* Figure out the logical op that we need to perform. */
3100 enum rtx_code code = GET_CODE (operands[3]);
3101 /* Pretend that every byte is affected if both operands are registers. */
3102 const unsigned HOST_WIDE_INT intval =
3103 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3104 /* Always use the full instruction if the
3105 first operand is in memory. It is better
3106 to use define_splits to generate the shorter
3107 sequence where valid. */
3108 && register_operand (operands[1], VOIDmode)
3109 ? INTVAL (operands[2]) : 0x55555555);
3110 /* The determinant of the algorithm. If we perform an AND, 0
3111 affects a bit. Otherwise, 1 affects a bit. */
3112 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3113 /* Break up DET into pieces. */
3114 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3115 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3116 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3117 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3118 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3119 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3120 int lower_half_easy_p = 0;
3121 int upper_half_easy_p = 0;
3122 /* The name of an insn. */
3144 /* First, see if we can finish with one insn. */
3145 if ((TARGET_H8300H || TARGET_H8300S)
3149 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3150 output_asm_insn (insn_buf, operands);
3154 /* Take care of the lower byte. */
3157 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3158 output_asm_insn (insn_buf, operands);
3160 /* Take care of the upper byte. */
3163 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3164 output_asm_insn (insn_buf, operands);
3169 if (TARGET_H8300H || TARGET_H8300S)
3171 /* Determine if the lower half can be taken care of in no more
3173 lower_half_easy_p = (b0 == 0
3175 || (code != IOR && w0 == 0xffff));
3177 /* Determine if the upper half can be taken care of in no more
3179 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3180 || (code == AND && w1 == 0xff00));
3183 /* Check if doing everything with one insn is no worse than
3184 using multiple insns. */
3185 if ((TARGET_H8300H || TARGET_H8300S)
3186 && w0 != 0 && w1 != 0
3187 && !(lower_half_easy_p && upper_half_easy_p)
3188 && !(code == IOR && w1 == 0xffff
3189 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3191 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3192 output_asm_insn (insn_buf, operands);
3196 /* Take care of the lower and upper words individually. For
3197 each word, we try different methods in the order of
3199 1) the special insn (in case of AND or XOR),
3200 2) the word-wise insn, and
3201 3) The byte-wise insn. */
3203 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3204 output_asm_insn ((code == AND)
3205 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3207 else if ((TARGET_H8300H || TARGET_H8300S)
3211 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3212 output_asm_insn (insn_buf, operands);
3218 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3219 output_asm_insn (insn_buf, operands);
3223 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3224 output_asm_insn (insn_buf, operands);
3229 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3230 output_asm_insn ((code == AND)
3231 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3233 else if ((TARGET_H8300H || TARGET_H8300S)
3236 && (w0 & 0x8000) != 0)
3238 output_asm_insn ("exts.l\t%S0", operands);
3240 else if ((TARGET_H8300H || TARGET_H8300S)
3244 output_asm_insn ("extu.w\t%e0", operands);
3246 else if (TARGET_H8300H || TARGET_H8300S)
3250 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3251 output_asm_insn (insn_buf, operands);
3258 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3259 output_asm_insn (insn_buf, operands);
3263 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3264 output_asm_insn (insn_buf, operands);
3275 /* Compute the length of a logical insn. */
3278 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3280 /* Figure out the logical op that we need to perform. */
3281 enum rtx_code code = GET_CODE (operands[3]);
3282 /* Pretend that every byte is affected if both operands are registers. */
3283 const unsigned HOST_WIDE_INT intval =
3284 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3285 /* Always use the full instruction if the
3286 first operand is in memory. It is better
3287 to use define_splits to generate the shorter
3288 sequence where valid. */
3289 && register_operand (operands[1], VOIDmode)
3290 ? INTVAL (operands[2]) : 0x55555555);
3291 /* The determinant of the algorithm. If we perform an AND, 0
3292 affects a bit. Otherwise, 1 affects a bit. */
3293 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3294 /* Break up DET into pieces. */
3295 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3296 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3297 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3298 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3299 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3300 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3301 int lower_half_easy_p = 0;
3302 int upper_half_easy_p = 0;
3304 unsigned int length = 0;
3309 /* First, see if we can finish with one insn. */
3310 if ((TARGET_H8300H || TARGET_H8300S)
3314 length = h8300_length_from_table (operands[1], operands[2],
3315 &logicw_length_table);
3319 /* Take care of the lower byte. */
3323 /* Take care of the upper byte. */
3329 if (TARGET_H8300H || TARGET_H8300S)
3331 /* Determine if the lower half can be taken care of in no more
3333 lower_half_easy_p = (b0 == 0
3335 || (code != IOR && w0 == 0xffff));
3337 /* Determine if the upper half can be taken care of in no more
3339 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3340 || (code == AND && w1 == 0xff00));
3343 /* Check if doing everything with one insn is no worse than
3344 using multiple insns. */
3345 if ((TARGET_H8300H || TARGET_H8300S)
3346 && w0 != 0 && w1 != 0
3347 && !(lower_half_easy_p && upper_half_easy_p)
3348 && !(code == IOR && w1 == 0xffff
3349 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3351 length = h8300_length_from_table (operands[1], operands[2],
3352 &logicl_length_table);
3356 /* Take care of the lower and upper words individually. For
3357 each word, we try different methods in the order of
3359 1) the special insn (in case of AND or XOR),
3360 2) the word-wise insn, and
3361 3) The byte-wise insn. */
3363 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3367 else if ((TARGET_H8300H || TARGET_H8300S)
3383 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3387 else if ((TARGET_H8300H || TARGET_H8300S)
3390 && (w0 & 0x8000) != 0)
3394 else if ((TARGET_H8300H || TARGET_H8300S)
3400 else if (TARGET_H8300H || TARGET_H8300S)
3421 /* Compute which flag bits are valid after a logical insn. */
3424 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3426 /* Figure out the logical op that we need to perform. */
3427 enum rtx_code code = GET_CODE (operands[3]);
3428 /* Pretend that every byte is affected if both operands are registers. */
3429 const unsigned HOST_WIDE_INT intval =
3430 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3431 /* Always use the full instruction if the
3432 first operand is in memory. It is better
3433 to use define_splits to generate the shorter
3434 sequence where valid. */
3435 && register_operand (operands[1], VOIDmode)
3436 ? INTVAL (operands[2]) : 0x55555555);
3437 /* The determinant of the algorithm. If we perform an AND, 0
3438 affects a bit. Otherwise, 1 affects a bit. */
3439 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3440 /* Break up DET into pieces. */
3441 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3442 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3443 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3444 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3445 int lower_half_easy_p = 0;
3446 int upper_half_easy_p = 0;
3447 /* Condition code. */
3448 enum attr_cc cc = CC_CLOBBER;
3453 /* First, see if we can finish with one insn. */
3454 if ((TARGET_H8300H || TARGET_H8300S)
3462 if (TARGET_H8300H || TARGET_H8300S)
3464 /* Determine if the lower half can be taken care of in no more
3466 lower_half_easy_p = (b0 == 0
3468 || (code != IOR && w0 == 0xffff));
3470 /* Determine if the upper half can be taken care of in no more
3472 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3473 || (code == AND && w1 == 0xff00));
3476 /* Check if doing everything with one insn is no worse than
3477 using multiple insns. */
3478 if ((TARGET_H8300H || TARGET_H8300S)
3479 && w0 != 0 && w1 != 0
3480 && !(lower_half_easy_p && upper_half_easy_p)
3481 && !(code == IOR && w1 == 0xffff
3482 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3488 if ((TARGET_H8300H || TARGET_H8300S)
3491 && (w0 & 0x8000) != 0)
3503 /* Expand a conditional branch. */
3506 h8300_expand_branch (enum rtx_code code, rtx label)
3510 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3511 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3512 gen_rtx_LABEL_REF (VOIDmode, label),
3514 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3519 We devote a fair bit of code to getting efficient shifts since we
3520 can only shift one bit at a time on the H8/300 and H8/300H and only
3521 one or two bits at a time on the H8S.
3523 All shift code falls into one of the following ways of
3526 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3527 when a straight line shift is about the same size or smaller than
3530 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3531 off the bits we don't need. This is used when only a few of the
3532 bits in the original value will survive in the shifted value.
3534 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3535 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3536 shifts can be added if the shift count is slightly more than 8 or
3537 16. This case also includes other oddballs that are not worth
3540 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3542 For each shift count, we try to use code that has no trade-off
3543 between code size and speed whenever possible.
3545 If the trade-off is unavoidable, we try to be reasonable.
3546 Specifically, the fastest version is one instruction longer than
3547 the shortest version, we take the fastest version. We also provide
3548 the use a way to switch back to the shortest version with -Os.
3550 For the details of the shift algorithms for various shift counts,
3551 refer to shift_alg_[qhs]i. */
3553 /* Classify a shift with the given mode and code. OP is the shift amount. */
3555 enum h8sx_shift_type
3556 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3558 if (!TARGET_H8300SX)
3559 return H8SX_SHIFT_NONE;
3565 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3566 if (GET_CODE (op) != CONST_INT)
3567 return H8SX_SHIFT_BINARY;
3569 /* Reject out-of-range shift amounts. */
3570 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3571 return H8SX_SHIFT_NONE;
3573 /* Power-of-2 shifts are effectively unary operations. */
3574 if (exact_log2 (INTVAL (op)) >= 0)
3575 return H8SX_SHIFT_UNARY;
3577 return H8SX_SHIFT_BINARY;
3580 if (op == const1_rtx || op == const2_rtx)
3581 return H8SX_SHIFT_UNARY;
3582 return H8SX_SHIFT_NONE;
3585 if (GET_CODE (op) == CONST_INT
3586 && (INTVAL (op) == 1
3588 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3589 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3590 return H8SX_SHIFT_UNARY;
3591 return H8SX_SHIFT_NONE;
3594 return H8SX_SHIFT_NONE;
3598 /* Return the asm template for a single h8sx shift instruction.
3599 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3600 is the source and OPERANDS[3] is the shift. SUFFIX is the
3601 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3602 prefix for the destination operand. */
3605 output_h8sx_shift (rtx *operands, int suffix, int optype)
3607 static char buffer[16];
3610 switch (GET_CODE (operands[3]))
3626 if (INTVAL (operands[2]) > 2)
3628 /* This is really a right rotate. */
3629 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3630 - INTVAL (operands[2]));
3638 if (operands[2] == const1_rtx)
3639 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3641 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3645 /* Emit code to do shifts. */
3648 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
3650 switch (h8sx_classify_shift (mode, code, operands[2]))
3652 case H8SX_SHIFT_BINARY:
3653 operands[1] = force_reg (mode, operands[1]);
3656 case H8SX_SHIFT_UNARY:
3659 case H8SX_SHIFT_NONE:
3663 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3665 /* Need a loop to get all the bits we want - we generate the
3666 code at emit time, but need to allocate a scratch reg now. */
3668 emit_insn (gen_rtx_PARALLEL
3671 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3672 gen_rtx_fmt_ee (code, mode,
3673 copy_rtx (operands[0]), operands[2])),
3674 gen_rtx_CLOBBER (VOIDmode,
3675 gen_rtx_SCRATCH (QImode)))));
3679 /* Symbols of the various modes which can be used as indices. */
3683 QIshift, HIshift, SIshift
3686 /* For single bit shift insns, record assembler and what bits of the
3687 condition code are valid afterwards (represented as various CC_FOO
3688 bits, 0 means CC isn't left in a usable state). */
3692 const char *const assembler;
3696 /* Assembler instruction shift table.
3698 These tables are used to look up the basic shifts.
3699 They are indexed by cpu, shift_type, and mode. */
3701 static const struct shift_insn shift_one[2][3][3] =
3707 { "shll\t%X0", CC_SET_ZNV },
3708 { "add.w\t%T0,%T0", CC_SET_ZN },
3709 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3711 /* SHIFT_LSHIFTRT */
3713 { "shlr\t%X0", CC_SET_ZNV },
3714 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3715 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3717 /* SHIFT_ASHIFTRT */
3719 { "shar\t%X0", CC_SET_ZNV },
3720 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3721 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3728 { "shll.b\t%X0", CC_SET_ZNV },
3729 { "shll.w\t%T0", CC_SET_ZNV },
3730 { "shll.l\t%S0", CC_SET_ZNV }
3732 /* SHIFT_LSHIFTRT */
3734 { "shlr.b\t%X0", CC_SET_ZNV },
3735 { "shlr.w\t%T0", CC_SET_ZNV },
3736 { "shlr.l\t%S0", CC_SET_ZNV }
3738 /* SHIFT_ASHIFTRT */
3740 { "shar.b\t%X0", CC_SET_ZNV },
3741 { "shar.w\t%T0", CC_SET_ZNV },
3742 { "shar.l\t%S0", CC_SET_ZNV }
3747 static const struct shift_insn shift_two[3][3] =
3751 { "shll.b\t#2,%X0", CC_SET_ZNV },
3752 { "shll.w\t#2,%T0", CC_SET_ZNV },
3753 { "shll.l\t#2,%S0", CC_SET_ZNV }
3755 /* SHIFT_LSHIFTRT */
3757 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3758 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3759 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3761 /* SHIFT_ASHIFTRT */
3763 { "shar.b\t#2,%X0", CC_SET_ZNV },
3764 { "shar.w\t#2,%T0", CC_SET_ZNV },
3765 { "shar.l\t#2,%S0", CC_SET_ZNV }
3769 /* Rotates are organized by which shift they'll be used in implementing.
3770 There's no need to record whether the cc is valid afterwards because
3771 it is the AND insn that will decide this. */
3773 static const char *const rotate_one[2][3][3] =
3780 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3783 /* SHIFT_LSHIFTRT */
3786 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3789 /* SHIFT_ASHIFTRT */
3792 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3804 /* SHIFT_LSHIFTRT */
3810 /* SHIFT_ASHIFTRT */
3819 static const char *const rotate_two[3][3] =
3827 /* SHIFT_LSHIFTRT */
3833 /* SHIFT_ASHIFTRT */
3842 /* Shift algorithm. */
3845 /* The number of bits to be shifted by shift1 and shift2. Valid
3846 when ALG is SHIFT_SPECIAL. */
3847 unsigned int remainder;
3849 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3850 const char *special;
3852 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3853 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3856 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3857 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3860 /* CC status for SHIFT_INLINE. */
3863 /* CC status for SHIFT_SPECIAL. */
3867 static void get_shift_alg (enum shift_type,
3868 enum shift_mode, unsigned int,
3869 struct shift_info *);
3871 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3872 best algorithm for doing the shift. The assembler code is stored
3873 in the pointers in INFO. We achieve the maximum efficiency in most
3874 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3875 SImode in particular have a lot of room to optimize.
3877 We first determine the strategy of the shift algorithm by a table
3878 lookup. If that tells us to use a hand crafted assembly code, we
3879 go into the big switch statement to find what that is. Otherwise,
3880 we resort to a generic way, such as inlining. In either case, the
3881 result is returned through INFO. */
3884 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3885 unsigned int count, struct shift_info *info)
3889 /* Find the target CPU. */
3892 else if (TARGET_H8300H)
3897 /* Find the shift algorithm. */
3898 info->alg = SHIFT_LOOP;
3902 if (count < GET_MODE_BITSIZE (QImode))
3903 info->alg = shift_alg_qi[cpu][shift_type][count];
3907 if (count < GET_MODE_BITSIZE (HImode))
3908 info->alg = shift_alg_hi[cpu][shift_type][count];
3912 if (count < GET_MODE_BITSIZE (SImode))
3913 info->alg = shift_alg_si[cpu][shift_type][count];
3920 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3924 info->remainder = count;
3928 /* It is up to the caller to know that looping clobbers cc. */
3929 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3930 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3931 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3935 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3936 info->shift2 = rotate_two[shift_type][shift_mode];
3937 info->cc_inline = CC_CLOBBER;
3941 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3942 info->remainder = 0;
3943 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3944 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3945 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3946 info->cc_special = CC_CLOBBER;
3950 /* Here we only deal with SHIFT_SPECIAL. */
3954 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3955 through the entire value. */
3956 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
3957 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3967 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3969 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3971 case SHIFT_LSHIFTRT:
3973 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3975 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3977 case SHIFT_ASHIFTRT:
3978 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3982 else if ((8 <= count && count <= 13)
3983 || (TARGET_H8300S && count == 14))
3985 info->remainder = count - 8;
3990 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3992 case SHIFT_LSHIFTRT:
3995 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3996 info->shift1 = "shlr.b\t%s0";
3997 info->cc_inline = CC_SET_ZNV;
4001 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4002 info->cc_special = CC_SET_ZNV;
4005 case SHIFT_ASHIFTRT:
4008 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4009 info->shift1 = "shar.b\t%s0";
4013 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4014 info->cc_special = CC_SET_ZNV;
4019 else if (count == 14)
4025 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4027 case SHIFT_LSHIFTRT:
4029 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4031 case SHIFT_ASHIFTRT:
4033 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4034 else if (TARGET_H8300H)
4036 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4037 info->cc_special = CC_SET_ZNV;
4039 else /* TARGET_H8300S */
4044 else if (count == 15)
4049 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4051 case SHIFT_LSHIFTRT:
4052 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4054 case SHIFT_ASHIFTRT:
4055 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4062 if (TARGET_H8300 && 8 <= count && count <= 9)
4064 info->remainder = count - 8;
4069 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4071 case SHIFT_LSHIFTRT:
4072 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4073 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4075 case SHIFT_ASHIFTRT:
4076 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4080 else if (count == 8 && !TARGET_H8300)
4085 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4087 case SHIFT_LSHIFTRT:
4088 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4090 case SHIFT_ASHIFTRT:
4091 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4095 else if (count == 15 && TARGET_H8300)
4101 case SHIFT_LSHIFTRT:
4102 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4104 case SHIFT_ASHIFTRT:
4105 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4109 else if (count == 15 && !TARGET_H8300)
4114 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4115 info->cc_special = CC_SET_ZNV;
4117 case SHIFT_LSHIFTRT:
4118 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4119 info->cc_special = CC_SET_ZNV;
4121 case SHIFT_ASHIFTRT:
4125 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4126 || (TARGET_H8300H && 16 <= count && count <= 19)
4127 || (TARGET_H8300S && 16 <= count && count <= 21))
4129 info->remainder = count - 16;
4134 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4136 info->shift1 = "add.w\t%e0,%e0";
4138 case SHIFT_LSHIFTRT:
4141 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4142 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4146 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4147 info->cc_special = CC_SET_ZNV;
4150 case SHIFT_ASHIFTRT:
4153 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4154 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4158 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4159 info->cc_special = CC_SET_ZNV;
4164 else if (TARGET_H8300 && 24 <= count && count <= 28)
4166 info->remainder = count - 24;
4171 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4172 info->shift1 = "shll.b\t%z0";
4173 info->cc_inline = CC_SET_ZNV;
4175 case SHIFT_LSHIFTRT:
4176 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4177 info->shift1 = "shlr.b\t%w0";
4178 info->cc_inline = CC_SET_ZNV;
4180 case SHIFT_ASHIFTRT:
4181 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4182 info->shift1 = "shar.b\t%w0";
4183 info->cc_inline = CC_SET_ZNV;
4187 else if ((TARGET_H8300H && count == 24)
4188 || (TARGET_H8300S && 24 <= count && count <= 25))
4190 info->remainder = count - 24;
4195 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4197 case SHIFT_LSHIFTRT:
4198 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4199 info->cc_special = CC_SET_ZNV;
4201 case SHIFT_ASHIFTRT:
4202 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4203 info->cc_special = CC_SET_ZNV;
4207 else if (!TARGET_H8300 && count == 28)
4213 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4215 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4217 case SHIFT_LSHIFTRT:
4220 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4221 info->cc_special = CC_SET_ZNV;
4224 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4226 case SHIFT_ASHIFTRT:
4230 else if (!TARGET_H8300 && count == 29)
4236 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4238 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4240 case SHIFT_LSHIFTRT:
4243 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4244 info->cc_special = CC_SET_ZNV;
4248 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4249 info->cc_special = CC_SET_ZNV;
4252 case SHIFT_ASHIFTRT:
4256 else if (!TARGET_H8300 && count == 30)
4262 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4264 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4266 case SHIFT_LSHIFTRT:
4268 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4270 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4272 case SHIFT_ASHIFTRT:
4276 else if (count == 31)
4283 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4285 case SHIFT_LSHIFTRT:
4286 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4288 case SHIFT_ASHIFTRT:
4289 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4298 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4299 info->cc_special = CC_SET_ZNV;
4301 case SHIFT_LSHIFTRT:
4302 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4303 info->cc_special = CC_SET_ZNV;
4305 case SHIFT_ASHIFTRT:
4306 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4307 info->cc_special = CC_SET_ZNV;
4320 info->shift2 = NULL;
4323 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4324 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4327 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4332 if (GET_MODE_BITSIZE (mode) <= count)
4335 /* Find out the target CPU. */
4338 else if (TARGET_H8300H)
4343 /* Find the shift algorithm. */
4347 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4348 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4349 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4353 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4354 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4355 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4359 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4360 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4361 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4368 /* On H8/300H, count == 8 uses a scratch register. */
4369 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4370 || (TARGET_H8300H && mode == SImode && count == 8));
4373 /* Output the assembler code for doing shifts. */
4376 output_a_shift (rtx *operands)
4378 static int loopend_lab;
4379 rtx shift = operands[3];
4380 enum machine_mode mode = GET_MODE (shift);
4381 enum rtx_code code = GET_CODE (shift);
4382 enum shift_type shift_type;
4383 enum shift_mode shift_mode;
4384 struct shift_info info;
4392 shift_mode = QIshift;
4395 shift_mode = HIshift;
4398 shift_mode = SIshift;
4407 shift_type = SHIFT_ASHIFTRT;
4410 shift_type = SHIFT_LSHIFTRT;
4413 shift_type = SHIFT_ASHIFT;
4419 /* This case must be taken care of by one of the two splitters
4420 that convert a variable shift into a loop. */
4421 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4423 n = INTVAL (operands[2]);
4425 /* If the count is negative, make it 0. */
4428 /* If the count is too big, truncate it.
4429 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4430 do the intuitive thing. */
4431 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4432 n = GET_MODE_BITSIZE (mode);
4434 get_shift_alg (shift_type, shift_mode, n, &info);
4439 output_asm_insn (info.special, operands);
4445 /* Emit two bit shifts first. */
4446 if (info.shift2 != NULL)
4448 for (; n > 1; n -= 2)
4449 output_asm_insn (info.shift2, operands);
4452 /* Now emit one bit shifts for any residual. */
4454 output_asm_insn (info.shift1, operands);
4459 int m = GET_MODE_BITSIZE (mode) - n;
4460 const int mask = (shift_type == SHIFT_ASHIFT
4461 ? ((1 << m) - 1) << n
4465 /* Not all possibilities of rotate are supported. They shouldn't
4466 be generated, but let's watch for 'em. */
4467 gcc_assert (info.shift1);
4469 /* Emit two bit rotates first. */
4470 if (info.shift2 != NULL)
4472 for (; m > 1; m -= 2)
4473 output_asm_insn (info.shift2, operands);
4476 /* Now single bit rotates for any residual. */
4478 output_asm_insn (info.shift1, operands);
4480 /* Now mask off the high bits. */
4484 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4488 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4489 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4496 output_asm_insn (insn_buf, operands);
4501 /* A loop to shift by a "large" constant value.
4502 If we have shift-by-2 insns, use them. */
4503 if (info.shift2 != NULL)
4505 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4506 names_big[REGNO (operands[4])]);
4507 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4508 output_asm_insn (info.shift2, operands);
4509 output_asm_insn ("add #0xff,%X4", operands);
4510 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4512 output_asm_insn (info.shift1, operands);
4516 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4517 names_big[REGNO (operands[4])]);
4518 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4519 output_asm_insn (info.shift1, operands);
4520 output_asm_insn ("add #0xff,%X4", operands);
4521 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4530 /* Count the number of assembly instructions in a string TEMPL. */
4533 h8300_asm_insn_count (const char *templ)
4535 unsigned int count = 1;
4537 for (; *templ; templ++)
4544 /* Compute the length of a shift insn. */
4547 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4549 rtx shift = operands[3];
4550 enum machine_mode mode = GET_MODE (shift);
4551 enum rtx_code code = GET_CODE (shift);
4552 enum shift_type shift_type;
4553 enum shift_mode shift_mode;
4554 struct shift_info info;
4555 unsigned int wlength = 0;
4560 shift_mode = QIshift;
4563 shift_mode = HIshift;
4566 shift_mode = SIshift;
4575 shift_type = SHIFT_ASHIFTRT;
4578 shift_type = SHIFT_LSHIFTRT;
4581 shift_type = SHIFT_ASHIFT;
4587 if (GET_CODE (operands[2]) != CONST_INT)
4589 /* Get the assembler code to do one shift. */
4590 get_shift_alg (shift_type, shift_mode, 1, &info);
4592 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4596 int n = INTVAL (operands[2]);
4598 /* If the count is negative, make it 0. */
4601 /* If the count is too big, truncate it.
4602 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4603 do the intuitive thing. */
4604 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4605 n = GET_MODE_BITSIZE (mode);
4607 get_shift_alg (shift_type, shift_mode, n, &info);
4612 wlength += h8300_asm_insn_count (info.special);
4614 /* Every assembly instruction used in SHIFT_SPECIAL case
4615 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4616 see xor.l, we just pretend that xor.l counts as two insns
4617 so that the insn length will be computed correctly. */
4618 if (strstr (info.special, "xor.l") != NULL)
4626 if (info.shift2 != NULL)
4628 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4632 wlength += h8300_asm_insn_count (info.shift1) * n;
4638 int m = GET_MODE_BITSIZE (mode) - n;
4640 /* Not all possibilities of rotate are supported. They shouldn't
4641 be generated, but let's watch for 'em. */
4642 gcc_assert (info.shift1);
4644 if (info.shift2 != NULL)
4646 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4650 wlength += h8300_asm_insn_count (info.shift1) * m;
4652 /* Now mask off the high bits. */
4662 gcc_assert (!TARGET_H8300);
4672 /* A loop to shift by a "large" constant value.
4673 If we have shift-by-2 insns, use them. */
4674 if (info.shift2 != NULL)
4676 wlength += 3 + h8300_asm_insn_count (info.shift2);
4678 wlength += h8300_asm_insn_count (info.shift1);
4682 wlength += 3 + h8300_asm_insn_count (info.shift1);
4692 /* Compute which flag bits are valid after a shift insn. */
4695 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4697 rtx shift = operands[3];
4698 enum machine_mode mode = GET_MODE (shift);
4699 enum rtx_code code = GET_CODE (shift);
4700 enum shift_type shift_type;
4701 enum shift_mode shift_mode;
4702 struct shift_info info;
4708 shift_mode = QIshift;
4711 shift_mode = HIshift;
4714 shift_mode = SIshift;
4723 shift_type = SHIFT_ASHIFTRT;
4726 shift_type = SHIFT_LSHIFTRT;
4729 shift_type = SHIFT_ASHIFT;
4735 /* This case must be taken care of by one of the two splitters
4736 that convert a variable shift into a loop. */
4737 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4739 n = INTVAL (operands[2]);
4741 /* If the count is negative, make it 0. */
4744 /* If the count is too big, truncate it.
4745 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4746 do the intuitive thing. */
4747 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4748 n = GET_MODE_BITSIZE (mode);
4750 get_shift_alg (shift_type, shift_mode, n, &info);
4755 if (info.remainder == 0)
4756 return info.cc_special;
4761 return info.cc_inline;
4764 /* This case always ends with an and instruction. */
4768 /* A loop to shift by a "large" constant value.
4769 If we have shift-by-2 insns, use them. */
4770 if (info.shift2 != NULL)
4773 return info.cc_inline;
4782 /* A rotation by a non-constant will cause a loop to be generated, in
4783 which a rotation by one bit is used. A rotation by a constant,
4784 including the one in the loop, will be taken care of by
4785 output_a_rotate () at the insn emit time. */
4788 expand_a_rotate (rtx operands[])
4790 rtx dst = operands[0];
4791 rtx src = operands[1];
4792 rtx rotate_amount = operands[2];
4793 enum machine_mode mode = GET_MODE (dst);
4795 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4798 /* We rotate in place. */
4799 emit_move_insn (dst, src);
4801 if (GET_CODE (rotate_amount) != CONST_INT)
4803 rtx counter = gen_reg_rtx (QImode);
4804 rtx start_label = gen_label_rtx ();
4805 rtx end_label = gen_label_rtx ();
4807 /* If the rotate amount is less than or equal to 0,
4808 we go out of the loop. */
4809 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4810 QImode, 0, end_label);
4812 /* Initialize the loop counter. */
4813 emit_move_insn (counter, rotate_amount);
4815 emit_label (start_label);
4817 /* Rotate by one bit. */
4821 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4824 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4827 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4833 /* Decrement the counter by 1. */
4834 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4836 /* If the loop counter is nonzero, we go back to the beginning
4838 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4841 emit_label (end_label);
4845 /* Rotate by AMOUNT bits. */
4849 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4852 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4855 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4865 /* Output a rotate insn. */
4868 output_a_rotate (enum rtx_code code, rtx *operands)
4870 rtx dst = operands[0];
4871 rtx rotate_amount = operands[2];
4872 enum shift_mode rotate_mode;
4873 enum shift_type rotate_type;
4874 const char *insn_buf;
4877 enum machine_mode mode = GET_MODE (dst);
4879 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4884 rotate_mode = QIshift;
4887 rotate_mode = HIshift;
4890 rotate_mode = SIshift;
4899 rotate_type = SHIFT_ASHIFT;
4902 rotate_type = SHIFT_LSHIFTRT;
4908 amount = INTVAL (rotate_amount);
4910 /* Clean up AMOUNT. */
4913 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4914 amount = GET_MODE_BITSIZE (mode);
4916 /* Determine the faster direction. After this phase, amount will be
4917 at most a half of GET_MODE_BITSIZE (mode). */
4918 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4920 /* Flip the direction. */
4921 amount = GET_MODE_BITSIZE (mode) - amount;
4923 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4926 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4927 boost up the rotation. */
4928 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4929 || (mode == HImode && TARGET_H8300H && amount >= 6)
4930 || (mode == HImode && TARGET_H8300S && amount == 8)
4931 || (mode == SImode && TARGET_H8300H && amount >= 10)
4932 || (mode == SImode && TARGET_H8300S && amount >= 13))
4937 /* This code works on any family. */
4938 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4939 output_asm_insn (insn_buf, operands);
4943 /* This code works on the H8/300H and H8S. */
4944 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4945 output_asm_insn (insn_buf, operands);
4952 /* Adjust AMOUNT and flip the direction. */
4953 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4955 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4958 /* Output rotate insns. */
4959 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4962 insn_buf = rotate_two[rotate_type][rotate_mode];
4964 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4966 for (; amount >= bits; amount -= bits)
4967 output_asm_insn (insn_buf, operands);
4973 /* Compute the length of a rotate insn. */
4976 compute_a_rotate_length (rtx *operands)
4978 rtx src = operands[1];
4979 rtx amount_rtx = operands[2];
4980 enum machine_mode mode = GET_MODE (src);
4982 unsigned int length = 0;
4984 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
4986 amount = INTVAL (amount_rtx);
4988 /* Clean up AMOUNT. */
4991 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4992 amount = GET_MODE_BITSIZE (mode);
4994 /* Determine the faster direction. After this phase, amount
4995 will be at most a half of GET_MODE_BITSIZE (mode). */
4996 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4997 /* Flip the direction. */
4998 amount = GET_MODE_BITSIZE (mode) - amount;
5000 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5001 boost up the rotation. */
5002 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5003 || (mode == HImode && TARGET_H8300H && amount >= 6)
5004 || (mode == HImode && TARGET_H8300S && amount == 8)
5005 || (mode == SImode && TARGET_H8300H && amount >= 10)
5006 || (mode == SImode && TARGET_H8300S && amount >= 13))
5008 /* Adjust AMOUNT and flip the direction. */
5009 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5013 /* We use 2-bit rotations on the H8S. */
5015 amount = amount / 2 + amount % 2;
5017 /* The H8/300 uses three insns to rotate one bit, taking 6
5019 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5024 /* Fix the operands of a gen_xxx so that it could become a bit
5028 fix_bit_operand (rtx *operands, enum rtx_code code)
5030 /* The bit_operand predicate accepts any memory during RTL generation, but
5031 only 'U' memory afterwards, so if this is a MEM operand, we must force
5032 it to be valid for 'U' by reloading the address. */
5035 ? single_zero_operand (operands[2], QImode)
5036 : single_one_operand (operands[2], QImode))
5038 /* OK to have a memory dest. */
5039 if (GET_CODE (operands[0]) == MEM
5040 && !OK_FOR_U (operands[0]))
5042 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5043 copy_to_mode_reg (Pmode,
5044 XEXP (operands[0], 0)));
5045 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5049 if (GET_CODE (operands[1]) == MEM
5050 && !OK_FOR_U (operands[1]))
5052 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5053 copy_to_mode_reg (Pmode,
5054 XEXP (operands[1], 0)));
5055 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5061 /* Dest and src op must be register. */
5063 operands[1] = force_reg (QImode, operands[1]);
5065 rtx res = gen_reg_rtx (QImode);
5069 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5072 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5075 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5080 emit_insn (gen_movqi (operands[0], res));
5085 /* Return nonzero if FUNC is an interrupt function as specified
5086 by the "interrupt" attribute. */
5089 h8300_interrupt_function_p (tree func)
5093 if (TREE_CODE (func) != FUNCTION_DECL)
5096 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5097 return a != NULL_TREE;
5100 /* Return nonzero if FUNC is a saveall function as specified by the
5101 "saveall" attribute. */
5104 h8300_saveall_function_p (tree func)
5108 if (TREE_CODE (func) != FUNCTION_DECL)
5111 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5112 return a != NULL_TREE;
5115 /* Return nonzero if FUNC is an OS_Task function as specified
5116 by the "OS_Task" attribute. */
5119 h8300_os_task_function_p (tree func)
5123 if (TREE_CODE (func) != FUNCTION_DECL)
5126 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5127 return a != NULL_TREE;
5130 /* Return nonzero if FUNC is a monitor function as specified
5131 by the "monitor" attribute. */
5134 h8300_monitor_function_p (tree func)
5138 if (TREE_CODE (func) != FUNCTION_DECL)
5141 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5142 return a != NULL_TREE;
5145 /* Return nonzero if FUNC is a function that should be called
5146 through the function vector. */
5149 h8300_funcvec_function_p (tree func)
5153 if (TREE_CODE (func) != FUNCTION_DECL)
5156 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5157 return a != NULL_TREE;
5160 /* Return nonzero if DECL is a variable that's in the eight bit
5164 h8300_eightbit_data_p (tree decl)
5168 if (TREE_CODE (decl) != VAR_DECL)
5171 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5172 return a != NULL_TREE;
5175 /* Return nonzero if DECL is a variable that's in the tiny
5179 h8300_tiny_data_p (tree decl)
5183 if (TREE_CODE (decl) != VAR_DECL)
5186 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5187 return a != NULL_TREE;
5190 /* Generate an 'interrupt_handler' attribute for decls. We convert
5191 all the pragmas to corresponding attributes. */
5194 h8300_insert_attributes (tree node, tree *attributes)
5196 if (TREE_CODE (node) == FUNCTION_DECL)
5198 if (pragma_interrupt)
5200 pragma_interrupt = 0;
5202 /* Add an 'interrupt_handler' attribute. */
5203 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5211 /* Add an 'saveall' attribute. */
5212 *attributes = tree_cons (get_identifier ("saveall"),
5218 /* Supported attributes:
5220 interrupt_handler: output a prologue and epilogue suitable for an
5223 saveall: output a prologue and epilogue that saves and restores
5224 all registers except the stack pointer.
5226 function_vector: This function should be called through the
5229 eightbit_data: This variable lives in the 8-bit data area and can
5230 be referenced with 8-bit absolute memory addresses.
5232 tiny_data: This variable lives in the tiny data area and can be
5233 referenced with 16-bit absolute memory references. */
5235 const struct attribute_spec h8300_attribute_table[] =
5237 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5238 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5239 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5240 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5241 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5242 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5243 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
5244 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
5245 { NULL, 0, 0, false, false, false, NULL }
5249 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5250 struct attribute_spec.handler. */
5252 h8300_handle_fndecl_attribute (tree *node, tree name,
5253 tree args ATTRIBUTE_UNUSED,
5254 int flags ATTRIBUTE_UNUSED,
5257 if (TREE_CODE (*node) != FUNCTION_DECL)
5259 warning (OPT_Wattributes, "%qs attribute only applies to functions",
5260 IDENTIFIER_POINTER (name));
5261 *no_add_attrs = true;
5267 /* Handle an "eightbit_data" attribute; arguments as in
5268 struct attribute_spec.handler. */
5270 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5271 tree args ATTRIBUTE_UNUSED,
5272 int flags ATTRIBUTE_UNUSED,
5277 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5279 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5283 warning (OPT_Wattributes, "%qs attribute ignored",
5284 IDENTIFIER_POINTER (name));
5285 *no_add_attrs = true;
5291 /* Handle an "tiny_data" attribute; arguments as in
5292 struct attribute_spec.handler. */
5294 h8300_handle_tiny_data_attribute (tree *node, tree name,
5295 tree args ATTRIBUTE_UNUSED,
5296 int flags ATTRIBUTE_UNUSED,
5301 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5303 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5307 warning (OPT_Wattributes, "%qs attribute ignored",
5308 IDENTIFIER_POINTER (name));
5309 *no_add_attrs = true;
5315 /* Mark function vectors, and various small data objects. */
5318 h8300_encode_section_info (tree decl, rtx rtl, int first)
5320 int extra_flags = 0;
5322 default_encode_section_info (decl, rtl, first);
5324 if (TREE_CODE (decl) == FUNCTION_DECL
5325 && h8300_funcvec_function_p (decl))
5326 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5327 else if (TREE_CODE (decl) == VAR_DECL
5328 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5330 if (h8300_eightbit_data_p (decl))
5331 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5332 else if (first && h8300_tiny_data_p (decl))
5333 extra_flags = SYMBOL_FLAG_TINY_DATA;
5337 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5340 /* Output a single-bit extraction. */
5343 output_simode_bld (int bild, rtx operands[])
5347 /* Clear the destination register. */
5348 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5350 /* Now output the bit load or bit inverse load, and store it in
5353 output_asm_insn ("bild\t%Z2,%Y1", operands);
5355 output_asm_insn ("bld\t%Z2,%Y1", operands);
5357 output_asm_insn ("bst\t#0,%w0", operands);
5361 /* Determine if we can clear the destination first. */
5362 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5363 && REGNO (operands[0]) != REGNO (operands[1]));
5366 output_asm_insn ("sub.l\t%S0,%S0", operands);
5368 /* Output the bit load or bit inverse load. */
5370 output_asm_insn ("bild\t%Z2,%Y1", operands);
5372 output_asm_insn ("bld\t%Z2,%Y1", operands);
5375 output_asm_insn ("xor.l\t%S0,%S0", operands);
5377 /* Perform the bit store. */
5378 output_asm_insn ("rotxl.l\t%S0", operands);
5385 /* Delayed-branch scheduling is more effective if we have some idea
5386 how long each instruction will be. Use a shorten_branches pass
5387 to get an initial estimate. */
5392 if (flag_delayed_branch)
5393 shorten_branches (get_insns ());
5396 #ifndef OBJECT_FORMAT_ELF
5398 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5401 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5402 fprintf (asm_out_file, "\t.section %s\n", name);
5404 #endif /* ! OBJECT_FORMAT_ELF */
5406 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5407 which is a special case of the 'R' operand. */
5410 h8300_eightbit_constant_address_p (rtx x)
5412 /* The ranges of the 8-bit area. */
5413 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5414 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5415 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5416 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5417 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5418 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5420 unsigned HOST_WIDE_INT addr;
5422 /* We accept symbols declared with eightbit_data. */
5423 if (GET_CODE (x) == SYMBOL_REF)
5424 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5426 if (GET_CODE (x) != CONST_INT)
5432 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5433 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5434 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5437 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5438 on H8/300H and H8S. */
5441 h8300_tiny_constant_address_p (rtx x)
5443 /* The ranges of the 16-bit area. */
5444 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5445 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5446 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5447 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5448 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5449 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5450 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5451 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5453 unsigned HOST_WIDE_INT addr;
5455 switch (GET_CODE (x))
5458 /* In the normal mode, any symbol fits in the 16-bit absolute
5459 address range. We also accept symbols declared with
5461 return (TARGET_NORMAL_MODE
5462 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5466 return (TARGET_NORMAL_MODE
5468 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5470 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5473 return TARGET_NORMAL_MODE;
5481 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5482 locations that can be accessed as a 16-bit word. */
5485 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5487 HOST_WIDE_INT offset1, offset2;
5495 else if (GET_CODE (addr1) == PLUS
5496 && REG_P (XEXP (addr1, 0))
5497 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5499 reg1 = XEXP (addr1, 0);
5500 offset1 = INTVAL (XEXP (addr1, 1));
5510 else if (GET_CODE (addr2) == PLUS
5511 && REG_P (XEXP (addr2, 0))
5512 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5514 reg2 = XEXP (addr2, 0);
5515 offset2 = INTVAL (XEXP (addr2, 1));
5520 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5521 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5523 && offset1 + 1 == offset2)
5529 /* Return nonzero if we have the same comparison insn as I3 two insns
5530 before I3. I3 is assumed to be a comparison insn. */
5533 same_cmp_preceding_p (rtx i3)
5537 /* Make sure we have a sequence of three insns. */
5538 i2 = prev_nonnote_insn (i3);
5541 i1 = prev_nonnote_insn (i2);
5545 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5546 && any_condjump_p (i2) && onlyjump_p (i2));
5549 /* Return nonzero if we have the same comparison insn as I1 two insns
5550 after I1. I1 is assumed to be a comparison insn. */
5553 same_cmp_following_p (rtx i1)
5557 /* Make sure we have a sequence of three insns. */
5558 i2 = next_nonnote_insn (i1);
5561 i3 = next_nonnote_insn (i2);
5565 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5566 && any_condjump_p (i2) && onlyjump_p (i2));
5569 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5570 (or pops) N registers. OPERANDS are assumed to be an array of
5574 h8300_regs_ok_for_stm (int n, rtx operands[])
5579 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5580 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5581 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5583 return ((REGNO (operands[0]) == 0
5584 && REGNO (operands[1]) == 1
5585 && REGNO (operands[2]) == 2)
5586 || (REGNO (operands[0]) == 4
5587 && REGNO (operands[1]) == 5
5588 && REGNO (operands[2]) == 6));
5591 return (REGNO (operands[0]) == 0
5592 && REGNO (operands[1]) == 1
5593 && REGNO (operands[2]) == 2
5594 && REGNO (operands[3]) == 3);
5600 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5603 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5604 unsigned int new_reg)
5606 /* Interrupt functions can only use registers that have already been
5607 saved by the prologue, even if they would normally be
5610 if (h8300_current_function_interrupt_function_p ()
5611 && !df_regs_ever_live_p (new_reg))
5617 /* Returns true if register REGNO is safe to be allocated as a scratch
5618 register in the current function. */
5621 h8300_hard_regno_scratch_ok (unsigned int regno)
5623 if (h8300_current_function_interrupt_function_p ()
5624 && ! WORD_REG_USED (regno))
5631 /* Return nonzero if X is a legitimate constant. */
5634 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
5639 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5642 h8300_rtx_ok_for_base_p (rtx x, int strict)
5644 /* Strip off SUBREG if any. */
5645 if (GET_CODE (x) == SUBREG)
5650 ? REG_OK_FOR_BASE_STRICT_P (x)
5651 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5654 /* Return nozero if X is a legitimate address. On the H8/300, a
5655 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5656 CONSTANT_ADDRESS. */
5659 h8300_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
5661 /* The register indirect addresses like @er0 is always valid. */
5662 if (h8300_rtx_ok_for_base_p (x, strict))
5665 if (CONSTANT_ADDRESS_P (x))
5669 && ( GET_CODE (x) == PRE_INC
5670 || GET_CODE (x) == PRE_DEC
5671 || GET_CODE (x) == POST_INC
5672 || GET_CODE (x) == POST_DEC)
5673 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5676 if (GET_CODE (x) == PLUS
5677 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5678 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5685 /* Worker function for HARD_REGNO_NREGS.
5687 We pretend the MAC register is 32bits -- we don't have any data
5688 types on the H8 series to handle more than 32bits. */
5691 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5693 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5696 /* Worker function for HARD_REGNO_MODE_OK. */
5699 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5702 /* If an even reg, then anything goes. Otherwise the mode must be
5704 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5706 /* MAC register can only be of SImode. Otherwise, anything
5708 return regno == MAC_REG ? mode == SImode : 1;
5711 /* Perform target dependent optabs initialization. */
5713 h8300_init_libfuncs (void)
5715 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5716 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5717 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5718 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5719 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5722 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5725 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5727 return (TYPE_MODE (type) == BLKmode
5728 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5731 /* Initialize the GCC target structure. */
5732 #undef TARGET_ATTRIBUTE_TABLE
5733 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5735 #undef TARGET_ASM_ALIGNED_HI_OP
5736 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5738 #undef TARGET_ASM_FILE_START
5739 #define TARGET_ASM_FILE_START h8300_file_start
5740 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5741 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5743 #undef TARGET_ASM_FILE_END
5744 #define TARGET_ASM_FILE_END h8300_file_end
5746 #undef TARGET_ENCODE_SECTION_INFO
5747 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5749 #undef TARGET_INSERT_ATTRIBUTES
5750 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5752 #undef TARGET_RTX_COSTS
5753 #define TARGET_RTX_COSTS h8300_rtx_costs
5755 #undef TARGET_INIT_LIBFUNCS
5756 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5758 #undef TARGET_RETURN_IN_MEMORY
5759 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5761 #undef TARGET_MACHINE_DEPENDENT_REORG
5762 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5764 #undef TARGET_HARD_REGNO_SCRATCH_OK
5765 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5767 #undef TARGET_DEFAULT_TARGET_FLAGS
5768 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5770 struct gcc_target targetm = TARGET_INITIALIZER;