1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* Forward declarations. */
47 static int h8300_interrupt_function_p PARAMS ((tree));
48 static int h8300_monitor_function_p PARAMS ((tree));
49 static int h8300_os_task_function_p PARAMS ((tree));
50 static void dosize PARAMS ((FILE *, const char *, unsigned int));
51 static int round_frame_size PARAMS ((int));
52 static unsigned int compute_saved_regs PARAMS ((void));
53 static void push PARAMS ((FILE *, int));
54 static void pop PARAMS ((FILE *, int));
55 static const char *cond_string PARAMS ((enum rtx_code));
56 static int h8300_valid_decl_attribute PARAMS ((tree, tree, tree, tree));
58 /* CPU_TYPE, says what cpu we're compiling for. */
61 /* True if the current function is an interrupt handler
62 (either via #pragma or an attribute specification). */
63 int interrupt_handler;
65 /* True if the current function is an OS Task
66 (via an attribute specification). */
69 /* True if the current function is a monitor
70 (via an attribute specification). */
73 /* True if a #pragma saveall has been seen for the current function. */
76 static const char *const names_big[] =
77 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
79 static const char *const names_extended[] =
80 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
82 static const char *const names_upper_extended[] =
83 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
85 /* Points to one of the above. */
86 /* ??? The above could be put in an array indexed by CPU_TYPE. */
87 const char * const *h8_reg_names;
89 /* Various operations needed by the following, indexed by CPU_TYPE. */
91 static const char *const h8_push_ops[2] = { "push", "push.l" };
92 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
93 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Initialize the GCC target structure. */
98 #undef TARGET_VALID_DECL_ATTRIBUTE
99 #define TARGET_VALID_DECL_ATTRIBUTE h8300_valid_decl_attribute
101 struct gcc_target target = TARGET_INITIALIZER;
103 /* Initialize various cpu specific globals at start up. */
110 cpu_type = (int) CPU_H8300;
111 h8_reg_names = names_big;
115 /* For this we treat the H8/300H and H8/S the same. */
116 cpu_type = (int) CPU_H8300H;
117 h8_reg_names = names_extended;
119 h8_push_op = h8_push_ops[cpu_type];
120 h8_pop_op = h8_pop_ops[cpu_type];
121 h8_mov_op = h8_mov_ops[cpu_type];
123 if (!TARGET_H8300S && TARGET_MAC)
125 error ("-ms2600 is used without -ms.");
135 static const char *const names_small[] =
136 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
137 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
139 return names_small[REGNO (x) * 2 + b];
142 /* REGNO must be saved/restored across calls if this macro is true. */
144 #define WORD_REG_USED(regno) \
146 /* No need to save registers if this function will not return. */\
147 && ! TREE_THIS_VOLATILE (current_function_decl) \
149 /* Save any call saved register that was used. */ \
150 || (regs_ever_live[regno] && !call_used_regs[regno]) \
151 /* Save the frame pointer if it was used. */ \
152 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
153 /* Save any register used in an interrupt handler. */ \
154 || (interrupt_handler && regs_ever_live[regno]) \
155 /* Save call clobbered registers in non-leaf interrupt \
157 || (interrupt_handler \
158 && call_used_regs[regno] \
159 && !current_function_is_leaf)))
161 /* Output assembly language to FILE for the operation OP with operand size
162 SIZE to adjust the stack pointer. */
165 dosize (file, op, size)
170 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
171 better to use adds/subs insns rather than add.l/sub.l with an
174 Also, on the H8/300, if we don't have a temporary to hold the
175 size of the frame in the prologue, we simply emit a sequence of
176 subs since this shouldn't happen often. */
177 if ((TARGET_H8300 && size <= 4)
178 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
179 || (TARGET_H8300 && current_function_needs_context
180 && strcmp (op, "sub")))
182 unsigned HOST_WIDE_INT amount;
184 /* Try different amounts in descending order. */
185 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
189 for (; size >= amount; size -= amount)
190 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
196 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
198 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
202 /* Round up frame size SIZE. */
205 round_frame_size (size)
208 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
211 /* Compute which registers to push/pop.
212 Return a bit vector of registers. */
215 compute_saved_regs ()
217 unsigned int saved_regs = 0;
220 /* Construct a bit vector of registers to be pushed/popped. */
221 for (regno = 0; regno <= 6; regno++)
223 if (WORD_REG_USED (regno))
224 saved_regs |= 1 << regno;
227 /* Don't push/pop the frame pointer as it is treated separately. */
228 if (frame_pointer_needed)
229 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
234 /* Output assembly language code to push register RN. */
241 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
244 /* Output assembly language code to pop register RN. */
251 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
254 /* This is what the stack looks like after the prolog of
255 a function with a frame has been set up:
261 <saved registers> <- sp
263 This is what the stack looks like after the prolog of
264 a function which doesn't have a frame:
269 <saved registers> <- sp
272 /* Output assembly language code for the function prologue. */
275 function_prologue (file, size)
279 int fsize = round_frame_size (size);
284 /* Note a function with the interrupt attribute and set interrupt_handler
286 if (h8300_interrupt_function_p (current_function_decl))
287 interrupt_handler = 1;
289 /* If the current function has the OS_Task attribute set, then
290 we have a naked prologue. */
291 if (h8300_os_task_function_p (current_function_decl))
293 fprintf (file, ";OS_Task prologue\n");
298 if (h8300_monitor_function_p (current_function_decl))
300 /* My understanding of monitor functions is they act just
301 like interrupt functions, except the prologue must
303 fprintf (file, ";monitor prologue\n");
304 interrupt_handler = 1;
308 fprintf (file, "\tsubs\t#2,sp\n");
310 fprintf (file, "\tstc\tccr,r0l\n");
311 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
313 fprintf (file, "\torc\t#128,ccr\n");
315 else if (TARGET_H8300H)
318 fprintf (file, "\tstc\tccr,r0l\n");
319 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
321 fprintf (file, "\torc\t#128,ccr\n");
323 else if (TARGET_H8300S)
325 fprintf (file, "\tstc\texr,@-sp\n");
327 fprintf (file, "\tstc\tccr,r0l\n");
328 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
330 fprintf (file, "\torc\t#128,ccr\n");
336 if (frame_pointer_needed)
339 push (file, FRAME_POINTER_REGNUM);
340 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
341 h8_reg_names[STACK_POINTER_REGNUM],
342 h8_reg_names[FRAME_POINTER_REGNUM]);
345 /* Leave room for locals. */
346 dosize (file, "sub", fsize);
348 /* Push the rest of the registers in ascending order. */
349 saved_regs = compute_saved_regs ();
350 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
355 if (saved_regs & (1 << regno))
359 /* See how many registers we can push at the same time. */
360 if ((regno == 0 || regno == 4)
361 && ((saved_regs >> regno) & 0x0f) == 0x0f)
364 else if ((regno == 0 || regno == 4)
365 && ((saved_regs >> regno) & 0x07) == 0x07)
368 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
369 && ((saved_regs >> regno) & 0x03) == 0x03)
376 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
378 h8_reg_names[regno + (n_regs - 1)]);
383 /* Output assembly language code for the function epilogue. */
386 function_epilogue (file, size)
390 int fsize = round_frame_size (size);
392 rtx insn = get_last_insn ();
398 /* OS_Task epilogues are nearly naked -- they just have an
400 fprintf (file, ";OS_task epilogue\n");
401 fprintf (file, "\trts\n");
405 /* Monitor epilogues are the same as interrupt function epilogues.
406 Just make a note that we're in an monitor epilogue. */
408 fprintf (file, ";monitor epilogue\n");
410 /* If the last insn was a BARRIER, we don't have to write any code. */
411 if (GET_CODE (insn) == NOTE)
412 insn = prev_nonnote_insn (insn);
413 if (insn && GET_CODE (insn) == BARRIER)
416 /* Pop the saved registers in descending order. */
417 saved_regs = compute_saved_regs ();
418 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
420 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
423 if (saved_regs & (1 << regno))
427 /* See how many registers we can pop at the same time. */
428 if ((regno == 7 || regno == 3)
429 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
432 else if ((regno == 6 || regno == 2)
433 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
436 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
437 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
444 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
445 h8_reg_names[regno - (n_regs - 1)],
446 h8_reg_names[regno]);
450 /* Deallocate locals. */
451 dosize (file, "add", fsize);
453 /* Pop frame pointer if we had one. */
454 if (frame_pointer_needed)
455 pop (file, FRAME_POINTER_REGNUM);
457 if (interrupt_handler)
458 fprintf (file, "\trte\n");
460 fprintf (file, "\trts\n");
463 interrupt_handler = 0;
469 /* Output assembly code for the start of the file. */
472 asm_file_start (file)
475 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
476 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
478 fprintf (file, "; -O%d\n", optimize);
480 fprintf (file, "\n\t.h8300h\n");
481 else if (TARGET_H8300S)
482 fprintf (file, "\n\t.h8300s\n");
484 fprintf (file, "\n\n");
485 output_file_directive (file, main_input_filename);
488 /* Output assembly language code for the end of file. */
494 fprintf (file, "\t.end\n");
497 /* Return true if VALUE is a valid constant for constraint 'P'.
498 IE: VALUE is a power of two <= 2**15. */
501 small_power_of_two (value)
504 int power = exact_log2 (value);
505 return power >= 0 && power <= 15;
508 /* Return true if VALUE is a valid constant for constraint 'O', which
509 means that the constant would be ok to use as a bit for a bclr
516 return small_power_of_two ((~value) & 0xff);
519 /* Return true if OP is a valid source operand for an integer move
523 general_operand_src (op, mode)
525 enum machine_mode mode;
527 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
529 return general_operand (op, mode);
532 /* Return true if OP is a valid destination operand for an integer move
536 general_operand_dst (op, mode)
538 enum machine_mode mode;
540 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
542 return general_operand (op, mode);
545 /* Return true if OP is a const valid for a bit clear instruction. */
548 o_operand (operand, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 return (GET_CODE (operand) == CONST_INT
553 && CONST_OK_FOR_O (INTVAL (operand)));
556 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
559 p_operand (operand, mode)
561 enum machine_mode mode ATTRIBUTE_UNUSED;
563 return (GET_CODE (operand) == CONST_INT
564 && CONST_OK_FOR_P (INTVAL (operand)));
567 /* Return true if OP is a valid call operand. */
570 call_insn_operand (op, mode)
572 enum machine_mode mode ATTRIBUTE_UNUSED;
574 if (GET_CODE (op) == MEM)
576 rtx inside = XEXP (op, 0);
577 if (register_operand (inside, Pmode))
579 if (CONSTANT_ADDRESS_P (inside))
585 /* Return 1 if an addition/subtraction of a constant integer can be
586 transformed into two consecutive adds/subs that are faster than the
587 straightforward way. Otherwise, return 0. */
590 two_insn_adds_subs_operand (op, mode)
592 enum machine_mode mode;
594 if (GET_CODE (op) == CONST_INT)
596 HOST_WIDE_INT value = INTVAL (op);
598 /* Force VALUE to be positive so that we do not have to consider
599 the negative case. */
602 if (TARGET_H8300H || TARGET_H8300S)
604 /* A constant addition/subtraction takes 2 states in QImode,
605 4 states in HImode, and 6 states in SImode. Thus, the
606 only case we can win is when SImode is used, in which
607 case, two adds/subs are used, taking 4 states. */
617 /* A constant addition/subtraction takes 2 states in
618 QImode. It takes 6 states in HImode, requiring the
619 constant to be loaded to a register first, and a lot more
620 in SImode. Thus the only case we can win is when either
621 HImode or SImode is used. */
632 /* Split an add of a small constant into two adds/subs insns. */
635 split_adds_subs (mode, operands)
636 enum machine_mode mode;
639 HOST_WIDE_INT val = INTVAL (operands[1]);
640 rtx reg = operands[0];
641 HOST_WIDE_INT sign = 1;
642 HOST_WIDE_INT amount;
644 /* Force VAL to be positive so that we do not have to consider the
652 /* Try different amounts in descending order. */
653 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
657 for (; val >= amount; val -= amount)
659 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
660 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
667 /* Return true if OP is a valid call operand, and OP represents
668 an operand for a small call (4 bytes instead of 6 bytes). */
671 small_call_insn_operand (op, mode)
673 enum machine_mode mode ATTRIBUTE_UNUSED;
675 if (GET_CODE (op) == MEM)
677 rtx inside = XEXP (op, 0);
679 /* Register indirect is a small call. */
680 if (register_operand (inside, Pmode))
683 /* A call through the function vector is a small
685 if (GET_CODE (inside) == SYMBOL_REF
686 && SYMBOL_REF_FLAG (inside))
689 /* Otherwise it's a large call. */
693 /* Return true if OP is a valid jump operand. */
696 jump_address_operand (op, mode)
698 enum machine_mode mode;
700 if (GET_CODE (op) == REG)
701 return mode == Pmode;
703 if (GET_CODE (op) == MEM)
705 rtx inside = XEXP (op, 0);
706 if (register_operand (inside, Pmode))
708 if (CONSTANT_ADDRESS_P (inside))
714 /* Recognize valid operands for bitfield instructions. */
716 extern int rtx_equal_function_value_matters;
719 bit_operand (op, mode)
721 enum machine_mode mode;
723 /* We can except any general operand, expept that MEM operands must
724 be limited to those that use addresses valid for the 'U' constraint. */
725 if (!general_operand (op, mode))
728 /* Accept any mem during RTL generation. Otherwise, the code that does
729 insv and extzv will think that we can not handle memory. However,
730 to avoid reload problems, we only accept 'U' MEM operands after RTL
731 generation. This means that any named pattern which uses this predicate
732 must force its operands to match 'U' before emitting RTL. */
734 if (GET_CODE (op) == REG)
736 if (GET_CODE (op) == SUBREG)
738 if (!rtx_equal_function_value_matters)
739 /* We're building rtl. */
740 return GET_CODE (op) == MEM;
742 return (GET_CODE (op) == MEM
743 && EXTRA_CONSTRAINT (op, 'U'));
747 bit_memory_operand (op, mode)
749 enum machine_mode mode ATTRIBUTE_UNUSED;
751 return (GET_CODE (op) == MEM
752 && EXTRA_CONSTRAINT (op, 'U'));
755 /* Recognize valid operators for bit test. */
758 eq_operator (x, mode)
760 enum machine_mode mode ATTRIBUTE_UNUSED;
762 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
765 /* Handle machine specific pragmas for compatibility with existing
766 compilers for the H8/300.
768 pragma saveall generates prolog/epilog code which saves and
769 restores all the registers on function entry.
771 pragma interrupt saves and restores all registers, and exits with
772 an rte instruction rather than an rts. A pointer to a function
773 with this attribute may be safely used in an interrupt vector. */
776 h8300_pr_interrupt (pfile)
777 cpp_reader *pfile ATTRIBUTE_UNUSED;
779 interrupt_handler = 1;
783 h8300_pr_saveall (pfile)
784 cpp_reader *pfile ATTRIBUTE_UNUSED;
789 /* If the next arg with MODE and TYPE is to be passed in a register, return
790 the rtx to represent where it is passed. CUM represents the state after
791 the last argument. NAMED is not used. */
793 static const char *const hand_list[] =
813 /* Return an RTX to represent where a value with mode MODE will be returned
814 from a function. If the result is 0, the argument is pushed. */
817 function_arg (cum, mode, type, named)
818 CUMULATIVE_ARGS *cum;
819 enum machine_mode mode;
827 /* Never pass unnamed arguments in registers. */
831 /* Pass 3 regs worth of data in regs when user asked on the command line. */
832 if (TARGET_QUICKCALL)
835 /* If calling hand written assembler, use 4 regs of args. */
839 const char * const *p;
841 fname = XSTR (cum->libcall, 0);
843 /* See if this libcall is one of the hand coded ones. */
845 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
857 size = int_size_in_bytes (type);
859 size = GET_MODE_SIZE (mode);
861 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
867 switch (cum->nbytes / UNITS_PER_WORD)
870 result = gen_rtx_REG (mode, 0);
873 result = gen_rtx_REG (mode, 1);
876 result = gen_rtx_REG (mode, 2);
879 result = gen_rtx_REG (mode, 3);
890 /* Return the cost of the rtx R with code CODE. */
910 if (TARGET_H8300H || TARGET_H8300S)
931 /* Documentation for the machine specific operand escapes:
933 'A' print rn in H8/300 mode, erN in H8/300H mode
934 'C' print (operand - 2).
935 'E' like s but negative.
936 'F' like t but negative.
937 'G' constant just the negative
938 'M' turn a 'M' constant into its negative mod 2.
939 'P' if operand is incing/decing sp, print .w, otherwise .b.
940 'R' print operand as a byte:8 address if appropriate, else fall back to
942 'S' print operand as a long word
943 'T' print operand as a word
944 'U' if operand is incing/decing sp, print l, otherwise nothing.
945 'V' find the set bit, and print its number.
946 'W' find the clear bit, and print its number.
947 'X' print operand as a byte
948 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
949 If this operand isn't a register, fall back to 'R' handling.
951 'b' print the bit opcode
952 'c' print the ibit opcode
953 'd' bcc if EQ, bcs if NE
954 'e' first word of 32 bit value - if reg, then least reg. if mem
955 then least. if const then most sig word
956 'f' second word of 32 bit value - if reg, then biggest reg. if mem
957 then +2. if const then least sig word
958 'g' bcs if EQ, bcc if NE
959 'j' print operand as condition code.
960 'k' print operand as reverse condition code.
961 's' print as low byte of 16 bit value
962 't' print as high byte of 16 bit value
963 'w' print as low byte of 32 bit value
964 'x' print as 2nd byte of 32 bit value
965 'y' print as 3rd byte of 32 bit value
966 'z' print as msb of 32 bit value
969 /* Return assembly language string which identifies a comparison type. */
1002 /* Print operand X using operand code CODE to assembly language output file
1006 print_operand (file, x, code)
1011 /* This is used for communication between the 'P' and 'U' codes. */
1012 static const char *last_p;
1014 /* This is used for communication between codes V,W,Z and Y. */
1020 if (GET_CODE (x) == REG)
1021 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1026 fprintf (file, "#%d", INTVAL (x) - 2);
1029 switch (GET_CODE (x))
1032 fprintf (file, "%sl", names_big[REGNO (x)]);
1035 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1042 switch (GET_CODE (x))
1045 fprintf (file, "%sh", names_big[REGNO (x)]);
1048 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1055 if (GET_CODE (x) != CONST_INT)
1057 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1060 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1067 fprintf (file, "#2");
1073 fprintf (file, "#1");
1080 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1083 fprintf (file, ".w");
1088 fprintf (file, ".b");
1092 if (GET_CODE (x) == REG)
1093 fprintf (file, "%s", names_extended[REGNO (x)]);
1098 if (GET_CODE (x) == REG)
1099 fprintf (file, "%s", names_big[REGNO (x)]);
1104 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1107 bitint = exact_log2 (INTVAL (x));
1110 fprintf (file, "#%d", bitint & 7);
1113 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1116 fprintf (file, "#%d", bitint & 7);
1120 if (GET_CODE (x) == REG)
1121 fprintf (file, "%s", byte_reg (x, 0));
1128 if (GET_CODE (x) == REG)
1129 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1131 print_operand (file, x, 'R');
1135 bitint = INTVAL (x);
1136 fprintf (file, "#%d", bitint & 7);
1139 switch (GET_CODE (x))
1142 fprintf (file, "bor");
1145 fprintf (file, "bxor");
1148 fprintf (file, "band");
1155 switch (GET_CODE (x))
1158 fprintf (file, "bior");
1161 fprintf (file, "bixor");
1164 fprintf (file, "biand");
1171 switch (GET_CODE (x))
1174 fprintf (file, "bcc");
1177 fprintf (file, "bcs");
1184 switch (GET_CODE (x))
1188 fprintf (file, "%s", names_big[REGNO (x)]);
1190 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1193 print_operand (file, x, 0);
1196 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1202 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1203 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1204 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1213 switch (GET_CODE (x))
1217 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1219 fprintf (file, "%s", names_big[REGNO (x)]);
1222 x = adjust_address (x, HImode, 2);
1223 print_operand (file, x, 0);
1226 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1232 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1233 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1234 fprintf (file, "#%ld", (val & 0xffff));
1242 switch (GET_CODE (x))
1245 fprintf (file, "bcc");
1248 fprintf (file, "bcs");
1255 asm_fprintf (file, cond_string (GET_CODE (x)));
1258 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1261 if (GET_CODE (x) == CONST_INT)
1262 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1264 fprintf (file, "%s", byte_reg (x, 0));
1267 if (GET_CODE (x) == CONST_INT)
1268 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1270 fprintf (file, "%s", byte_reg (x, 1));
1273 if (GET_CODE (x) != CONST_INT)
1275 fprintf (file, "%d", INTVAL (x));
1278 if (GET_CODE (x) == CONST_INT)
1279 fprintf (file, "#%d", INTVAL (x) & 0xff);
1281 fprintf (file, "%s",
1282 byte_reg (x, TARGET_H8300 ? 2 : 0));
1285 if (GET_CODE (x) == CONST_INT)
1286 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1288 fprintf (file, "%s",
1289 byte_reg (x, TARGET_H8300 ? 3 : 1));
1292 if (GET_CODE (x) == CONST_INT)
1293 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1295 fprintf (file, "%s", byte_reg (x, 0));
1298 if (GET_CODE (x) == CONST_INT)
1299 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1301 fprintf (file, "%s", byte_reg (x, 1));
1306 switch (GET_CODE (x))
1309 switch (GET_MODE (x))
1312 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1313 fprintf (file, "%s", byte_reg (x, 0));
1314 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1315 fprintf (file, "%s", names_big[REGNO (x)]);
1319 fprintf (file, "%s", names_big[REGNO (x)]);
1323 fprintf (file, "%s", names_extended[REGNO (x)]);
1331 fprintf (file, "@");
1332 output_address (XEXP (x, 0));
1334 /* If this is an 'R' operand (reference into the 8-bit
1335 area), then specify a symbolic address as "foo:8",
1336 otherwise if operand is still in eight bit section, use
1338 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1339 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1340 fprintf (file, (code == 'R' ? ":8" : ":16"));
1341 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1342 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1343 fprintf (file, ":16");
1344 else if ((code == 'R')
1345 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1346 fprintf (file, ":8");
1353 fprintf (file, "#");
1354 print_operand_address (file, x);
1360 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1361 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1362 fprintf (file, "#%ld", val);
1371 /* Output assembly language output for the address ADDR to FILE. */
1374 print_operand_address (file, addr)
1378 switch (GET_CODE (addr))
1381 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1385 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1389 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1393 fprintf (file, "(");
1394 if (GET_CODE (XEXP (addr, 0)) == REG)
1397 print_operand_address (file, XEXP (addr, 1));
1398 fprintf (file, ",");
1399 print_operand_address (file, XEXP (addr, 0));
1404 print_operand_address (file, XEXP (addr, 0));
1405 fprintf (file, "+");
1406 print_operand_address (file, XEXP (addr, 1));
1408 fprintf (file, ")");
1413 /* Since the H8/300 only has 16 bit pointers, negative values are also
1414 those >= 32768. This happens for example with pointer minus a
1415 constant. We don't want to turn (char *p - 2) into
1416 (char *p + 65534) because loop unrolling can build upon this
1417 (IE: char *p + 131068). */
1418 int n = INTVAL (addr);
1420 n = (int) (short) n;
1422 /* ??? Why the special case for -ve values? */
1423 fprintf (file, "-%d", -n);
1425 fprintf (file, "%d", n);
1430 output_addr_const (file, addr);
1435 /* Output all insn addresses and their sizes into the assembly language
1436 output file. This is helpful for debugging whether the length attributes
1437 in the md file are correct. This is not meant to be a user selectable
1441 final_prescan_insn (insn, operand, num_operands)
1442 rtx insn, *operand ATTRIBUTE_UNUSED;
1443 int num_operands ATTRIBUTE_UNUSED;
1445 /* This holds the last insn address. */
1446 static int last_insn_address = 0;
1448 int uid = INSN_UID (insn);
1450 if (TARGET_RTL_DUMP)
1452 fprintf (asm_out_file, "\n****************");
1453 print_rtl (asm_out_file, PATTERN (insn));
1454 fprintf (asm_out_file, "\n");
1457 if (TARGET_ADDRESSES)
1459 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1460 INSN_ADDRESSES (uid) - last_insn_address);
1461 last_insn_address = INSN_ADDRESSES (uid);
1465 /* Prepare for an SI sized move. */
1471 rtx src = operands[1];
1472 rtx dst = operands[0];
1473 if (!reload_in_progress && !reload_completed)
1475 if (!register_operand (dst, GET_MODE (dst)))
1477 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1478 emit_move_insn (tmp, src);
1485 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1486 Define the offset between two registers, one to be eliminated, and
1487 the other its replacement, at the start of a routine. */
1490 initial_offset (from, to)
1495 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1496 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1501 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1502 if (WORD_REG_USED (regno))
1503 offset += UNITS_PER_WORD;
1505 /* See the comments for get_frame_size. We need to round it up to
1508 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1509 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1511 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1512 offset += UNITS_PER_WORD; /* Skip saved PC */
1517 /* Update the condition code from the insn. */
1520 notice_update_cc (body, insn)
1524 switch (get_attr_cc (insn))
1527 /* Insn does not affect CC at all. */
1531 /* Insn does not change CC, but the 0'th operand has been changed. */
1532 if (cc_status.value1 != 0
1533 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1534 cc_status.value1 = 0;
1538 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1539 The V flag is unusable. The C flag may or may not be known but
1540 that's ok because alter_cond will change tests to use EQ/NE. */
1542 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1543 cc_status.value1 = recog_data.operand[0];
1547 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1548 The C flag may or may not be known but that's ok because
1549 alter_cond will change tests to use EQ/NE. */
1551 cc_status.flags |= CC_NO_CARRY;
1552 cc_status.value1 = recog_data.operand[0];
1556 /* The insn is a compare instruction. */
1558 cc_status.value1 = SET_SRC (body);
1562 /* Insn doesn't leave CC in a usable state. */
1568 /* Recognize valid operators for bit instructions. */
1571 bit_operator (x, mode)
1573 enum machine_mode mode ATTRIBUTE_UNUSED;
1575 enum rtx_code code = GET_CODE (x);
1584 We devote a fair bit of code to getting efficient shifts since we can only
1585 shift one bit at a time on the H8/300 and H8/300H and only one or two
1586 bits at a time on the H8/S.
1588 The basic shift methods:
1590 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1591 this is the default. SHIFT_LOOP
1593 * inlined shifts -- emit straight line code for the shift; this is
1594 used when a straight line shift is about the same size or smaller
1595 than a loop. We allow the inline version to be slightly longer in
1596 some cases as it saves a register. SHIFT_INLINE
1598 * rotate + and -- rotate the value the opposite direction, then
1599 mask off the values we don't need. This is used when only a few
1600 of the bits in the original value will survive in the shifted value.
1601 Again, this is used when it's about the same size or smaller than
1602 a loop. We allow this version to be slightly longer as it is usually
1603 much faster than a loop. SHIFT_ROT_AND
1605 * swap (+ shifts) -- often it's possible to swap bytes/words to
1606 simulate a shift by 8/16. Once swapped a few inline shifts can be
1607 added if the shift count is slightly more than 8 or 16. This is used
1608 when it's about the same size or smaller than a loop. We allow this
1609 version to be slightly longer as it is usually much faster than a loop.
1612 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1614 Here are some thoughts on what the absolutely positively best code is.
1615 "Best" here means some rational trade-off between code size and speed,
1616 where speed is more preferred but not at the expense of generating 20 insns.
1618 A trailing '*' after the shift count indicates the "best" mode isn't
1621 H8/300 QImode shifts
1622 1-4 - do them inline
1623 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1625 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1626 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1628 H8/300 HImode shifts
1629 1-4 - do them inline
1631 7 - shift 2nd half other way into carry.
1632 copy 1st half into 2nd half
1633 rotate 2nd half other way with carry
1634 rotate 1st half other way (no carry)
1635 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1636 sign extend 1st half (ASHIFTRT)
1637 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1638 9-12 - do shift by 8, inline remaining shifts
1639 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1641 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1642 - ASHIFTRT: shll, subx, set other byte
1644 H8/300 SImode shifts
1645 1-2 - do them inline
1647 7* - shift other way once, move bytes into place,
1648 move carry into place (possibly with sign extension)
1649 8 - move bytes into place, zero or sign extend other
1651 15* - shift other way once, move word into place, move carry into place
1652 16 - move word, zero or sign extend other
1654 24* - move bytes into place, zero or sign extend other
1656 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1659 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1661 ASHIFTRT: shll top byte, subx, copy to other bytes
1663 H8/300H QImode shifts (same as H8/300 QImode shifts)
1664 1-4 - do them inline
1665 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1667 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1668 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1670 H8/300H HImode shifts
1671 1-4 - do them inline
1673 7 - shift 2nd half other way into carry.
1674 copy 1st half into 2nd half
1675 rotate entire word other way using carry
1676 mask off remaining bits (ASHIFT | LSHIFTRT)
1677 sign extend remaining bits (ASHIFTRT)
1678 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1679 9-12 - do shift by 8, inline remaining shifts
1680 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1682 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1683 - ASHIFTRT: shll, subx, set other byte
1685 H8/300H SImode shifts
1686 (These are complicated by the fact that we don't have byte level access to
1688 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1689 1-4 - do them inline
1691 15* - shift other way once, move word into place, move carry into place
1692 (with sign extension for ASHIFTRT)
1693 16 - move word into place, zero or sign extend other
1694 17-20 - do 16bit shift, then inline remaining shifts
1696 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1697 move word 0 to word 1, zero word 0
1698 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1699 zero word 1, zero byte 1
1700 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1701 sign extend byte 0, sign extend word 0
1702 25-27* - either loop, or
1703 do 24 bit shift, inline rest
1704 28-30 - ASHIFT: rotate 4/3/2, mask
1705 LSHIFTRT: rotate 4/3/2, mask
1707 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1710 1-6 - do them inline
1711 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1712 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1715 1-7 - do them inline
1716 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1717 9-12 - do shift by 8, inline remaining shifts
1718 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1720 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1721 - ASHIFTRT: shll, subx, set other byte
1724 (These are complicated by the fact that we don't have byte level access to
1726 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1727 1-10 - do them inline
1729 15* - shift other way once, move word into place, move carry into place
1730 (with sign extension for ASHIFTRT)
1731 16 - move word into place, zero or sign extend other
1732 17-20 - do 16bit shift, then inline remaining shifts
1734 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1735 move word 0 to word 1, zero word 0
1736 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1737 zero word 1, zero byte 1
1738 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1739 sign extend byte 0, sign extend word 0
1740 25-27* - either loop, or
1741 do 24 bit shift, inline rest
1742 28-30 - ASHIFT: rotate 4/3/2, mask
1743 LSHIFTRT: rotate 4/3/2, mask
1745 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1750 nshift_operator (x, mode)
1752 enum machine_mode mode ATTRIBUTE_UNUSED;
1754 switch (GET_CODE (x))
1766 /* Called from the .md file to emit code to do shifts.
1767 Return a boolean indicating success.
1768 (Currently this is always TRUE). */
1771 expand_a_shift (mode, code, operands)
1772 enum machine_mode mode;
1776 emit_move_insn (operands[0], operands[1]);
1778 /* Need a loop to get all the bits we want - we generate the
1779 code at emit time, but need to allocate a scratch reg now. */
1781 emit_insn (gen_rtx_PARALLEL
1784 gen_rtx_SET (VOIDmode, operands[0],
1785 gen_rtx (code, mode, operands[0],
1787 gen_rtx_CLOBBER (VOIDmode,
1788 gen_rtx_SCRATCH (QImode)))));
1793 /* Shift algorithm determination.
1795 There are various ways of doing a shift:
1796 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1798 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1799 necessary bits into position and then set the rest to zero.
1800 SHIFT_SPECIAL: Hand crafted assembler.
1801 SHIFT_LOOP: If the above methods fail, just loop. */
1812 /* Symbols of the various shifts which can be used as indices. */
1816 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1819 /* Symbols of the various modes which can be used as indices. */
1823 QIshift, HIshift, SIshift
1826 /* For single bit shift insns, record assembler and what bits of the
1827 condition code are valid afterwards (represented as various CC_FOO
1828 bits, 0 means CC isn't left in a usable state). */
1832 const char *assembler;
1836 /* Assembler instruction shift table.
1838 These tables are used to look up the basic shifts.
1839 They are indexed by cpu, shift_type, and mode. */
1841 static const struct shift_insn shift_one[2][3][3] =
1847 { "shll\t%X0", CC_NO_CARRY },
1848 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1849 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1851 /* SHIFT_LSHIFTRT */
1853 { "shlr\t%X0", CC_NO_CARRY },
1854 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1855 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1857 /* SHIFT_ASHIFTRT */
1859 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1860 { "shar\t%t0\n\trotxr\t%s0", 0 },
1861 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1868 { "shll.b\t%X0", CC_NO_CARRY },
1869 { "shll.w\t%T0", CC_NO_CARRY },
1870 { "shll.l\t%S0", CC_NO_CARRY }
1872 /* SHIFT_LSHIFTRT */
1874 { "shlr.b\t%X0", CC_NO_CARRY },
1875 { "shlr.w\t%T0", CC_NO_CARRY },
1876 { "shlr.l\t%S0", CC_NO_CARRY }
1878 /* SHIFT_ASHIFTRT */
1880 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1881 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1882 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1887 static const struct shift_insn shift_two[3][3] =
1891 { "shll.b\t#2,%X0", CC_NO_CARRY },
1892 { "shll.w\t#2,%T0", CC_NO_CARRY },
1893 { "shll.l\t#2,%S0", CC_NO_CARRY }
1895 /* SHIFT_LSHIFTRT */
1897 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1898 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1899 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1901 /* SHIFT_ASHIFTRT */
1903 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1904 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1905 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1909 /* Rotates are organized by which shift they'll be used in implementing.
1910 There's no need to record whether the cc is valid afterwards because
1911 it is the AND insn that will decide this. */
1913 static const char *const rotate_one[2][3][3] =
1920 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
1923 /* SHIFT_LSHIFTRT */
1926 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1929 /* SHIFT_ASHIFTRT */
1932 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1944 /* SHIFT_LSHIFTRT */
1950 /* SHIFT_ASHIFTRT */
1959 static const char *const rotate_two[3][3] =
1967 /* SHIFT_LSHIFTRT */
1973 /* SHIFT_ASHIFTRT */
1982 /* Shift algorithm. */
1985 /* The number of bits to be shifted by shift1 and shift2. Valid
1986 when ALG is SHIFT_SPECIAL. */
1987 unsigned int remainder;
1989 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
1990 const char *special;
1992 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
1993 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
1996 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
1997 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2000 /* Valid CC flags. */
2004 static enum shift_alg get_shift_alg PARAMS ((enum shift_type,
2005 enum shift_mode, int,
2006 struct shift_info *));
2008 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2009 best algorithm for doing the shift. The assembler code is stored
2010 in the pointers in INFO. We don't achieve maximum efficiency in
2011 all cases, but the hooks are here to do so.
2013 For now we just use lots of switch statements. Since we don't even come
2014 close to supporting all the cases, this is simplest. If this function ever
2015 gets too big, perhaps resort to a more table based lookup. Of course,
2016 at this point you may just wish to do it all in rtl.
2018 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2019 1,2,3,4 will be inlined (1,2 for SI). */
2021 static enum shift_alg
2022 get_shift_alg (shift_type, shift_mode, count, info)
2023 enum shift_type shift_type;
2024 enum shift_mode shift_mode;
2026 struct shift_info *info;
2028 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2029 It is up to the caller to know that looping clobbers cc. */
2030 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2032 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2034 info->shift2 = NULL;
2035 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2037 /* Now look for cases we want to optimize. */
2043 return SHIFT_INLINE;
2046 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2047 fast as SHIFT_ROT_AND, plus CC is valid. */
2048 if (TARGET_H8300S && count <= 6)
2049 return SHIFT_INLINE;
2051 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2052 through the entire value. */
2053 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2055 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2056 info->cc_valid_p = 0;
2057 return SHIFT_SPECIAL;
2060 /* Other ASHIFTRTs are too much of a pain. */
2061 if (shift_type == SHIFT_ASHIFTRT)
2064 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2065 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2067 info->shift2 = rotate_two[shift_type][shift_mode];
2068 info->cc_valid_p = 0;
2069 return SHIFT_ROT_AND;
2074 return SHIFT_INLINE;
2075 else if (TARGET_H8300S && count <= 7)
2076 return SHIFT_INLINE;
2077 else if (count == 7)
2079 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2081 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2082 info->cc_valid_p = 0;
2083 return SHIFT_SPECIAL;
2086 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2088 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2089 info->cc_valid_p = 0;
2090 return SHIFT_SPECIAL;
2093 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2095 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2096 info->cc_valid_p = 0;
2097 return SHIFT_SPECIAL;
2100 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2102 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2103 info->cc_valid_p = 0;
2104 return SHIFT_SPECIAL;
2107 if (shift_type == SHIFT_ASHIFTRT)
2109 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2110 info->cc_valid_p = 0;
2111 return SHIFT_SPECIAL;
2114 else if (count == 8)
2119 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2120 info->cc_valid_p = 0;
2121 return SHIFT_SPECIAL;
2122 case SHIFT_LSHIFTRT:
2123 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2124 info->cc_valid_p = 0;
2125 return SHIFT_SPECIAL;
2126 case SHIFT_ASHIFTRT:
2128 info->special = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0";
2130 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2131 info->cc_valid_p = 0;
2132 return SHIFT_SPECIAL;
2135 else if (count == 9)
2140 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2141 info->cc_valid_p = 0;
2142 return SHIFT_SPECIAL;
2143 case SHIFT_LSHIFTRT:
2144 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2145 info->cc_valid_p = 0;
2146 return SHIFT_SPECIAL;
2147 case SHIFT_ASHIFTRT:
2149 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2151 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2152 info->cc_valid_p = 0;
2153 return SHIFT_SPECIAL;
2156 else if (count == 10)
2162 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0";
2164 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2165 info->cc_valid_p = 0;
2166 return SHIFT_SPECIAL;
2167 case SHIFT_LSHIFTRT:
2169 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2171 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2172 info->cc_valid_p = 0;
2173 return SHIFT_SPECIAL;
2174 case SHIFT_ASHIFTRT:
2176 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2177 else if (TARGET_H8300H)
2178 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2179 else if (TARGET_H8300S)
2180 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2181 info->cc_valid_p = 0;
2182 return SHIFT_SPECIAL;
2185 else if (count == 11)
2191 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2193 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2194 info->cc_valid_p = 0;
2195 return SHIFT_SPECIAL;
2196 case SHIFT_LSHIFTRT:
2198 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2200 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2201 info->cc_valid_p = 0;
2202 return SHIFT_SPECIAL;
2203 case SHIFT_ASHIFTRT:
2205 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2206 else if (TARGET_H8300H)
2207 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2208 else if (TARGET_H8300S)
2209 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2210 info->cc_valid_p = 0;
2211 return SHIFT_SPECIAL;
2214 else if (count == 12)
2220 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2222 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2223 info->cc_valid_p = 0;
2224 return SHIFT_SPECIAL;
2225 case SHIFT_LSHIFTRT:
2227 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2229 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2230 info->cc_valid_p = 0;
2231 return SHIFT_SPECIAL;
2232 case SHIFT_ASHIFTRT:
2234 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2235 else if (TARGET_H8300H)
2236 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2237 else if (TARGET_H8300S)
2238 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2239 info->cc_valid_p = 0;
2240 return SHIFT_SPECIAL;
2243 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2246 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2248 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2249 info->cc_valid_p = 0;
2250 return SHIFT_SPECIAL;
2252 else if (shift_type != SHIFT_ASHIFTRT)
2254 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2256 info->shift2 = rotate_two[shift_type][shift_mode];
2258 info->shift2 = NULL;
2259 info->cc_valid_p = 0;
2260 return SHIFT_ROT_AND;
2266 if (count <= (TARGET_H8300 ? 2 : 4))
2267 return SHIFT_INLINE;
2268 else if (TARGET_H8300S && count <= 10)
2269 return SHIFT_INLINE;
2270 else if (count == 8 && TARGET_H8300)
2275 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2276 info->cc_valid_p = 0;
2277 return SHIFT_SPECIAL;
2278 case SHIFT_LSHIFTRT:
2279 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2280 info->cc_valid_p = 0;
2281 return SHIFT_SPECIAL;
2282 case SHIFT_ASHIFTRT:
2283 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2284 info->cc_valid_p = 0;
2285 return SHIFT_SPECIAL;
2288 else if (count == 8 && !TARGET_H8300)
2293 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2294 info->cc_valid_p = 0;
2295 return SHIFT_SPECIAL;
2296 case SHIFT_LSHIFTRT:
2297 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2298 info->cc_valid_p = 0;
2299 return SHIFT_SPECIAL;
2300 case SHIFT_ASHIFTRT:
2301 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2302 info->cc_valid_p = 0;
2303 return SHIFT_SPECIAL;
2306 else if (count == 16)
2311 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2312 info->cc_valid_p = 0;
2313 return SHIFT_SPECIAL;
2314 case SHIFT_LSHIFTRT:
2315 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2316 info->cc_valid_p = 0;
2317 return SHIFT_SPECIAL;
2318 case SHIFT_ASHIFTRT:
2320 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2322 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2323 info->cc_valid_p = 0;
2324 return SHIFT_SPECIAL;
2327 else if (count == 17 && !TARGET_H8300)
2332 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2333 info->cc_valid_p = 0;
2334 return SHIFT_SPECIAL;
2335 case SHIFT_LSHIFTRT:
2336 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2337 info->cc_valid_p = 0;
2338 return SHIFT_SPECIAL;
2339 case SHIFT_ASHIFTRT:
2340 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2341 info->cc_valid_p = 0;
2342 return SHIFT_SPECIAL;
2345 else if (count == 18 && !TARGET_H8300)
2351 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2353 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2354 info->cc_valid_p = 0;
2355 return SHIFT_SPECIAL;
2356 case SHIFT_LSHIFTRT:
2358 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2360 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2361 info->cc_valid_p = 0;
2362 return SHIFT_SPECIAL;
2363 case SHIFT_ASHIFTRT:
2365 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2367 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2368 info->cc_valid_p = 0;
2369 return SHIFT_SPECIAL;
2372 else if (count == 19 && !TARGET_H8300)
2378 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2380 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2381 info->cc_valid_p = 0;
2382 return SHIFT_SPECIAL;
2383 case SHIFT_LSHIFTRT:
2385 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2387 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2388 info->cc_valid_p = 0;
2389 return SHIFT_SPECIAL;
2390 case SHIFT_ASHIFTRT:
2392 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2394 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2395 info->cc_valid_p = 0;
2396 return SHIFT_SPECIAL;
2399 else if (count == 20 && TARGET_H8300S)
2404 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2405 info->cc_valid_p = 0;
2406 return SHIFT_SPECIAL;
2407 case SHIFT_LSHIFTRT:
2408 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2409 info->cc_valid_p = 0;
2410 return SHIFT_SPECIAL;
2411 case SHIFT_ASHIFTRT:
2412 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2413 info->cc_valid_p = 0;
2414 return SHIFT_SPECIAL;
2417 else if (count == 24 && !TARGET_H8300)
2422 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2423 info->cc_valid_p = 0;
2424 return SHIFT_SPECIAL;
2425 case SHIFT_LSHIFTRT:
2426 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2427 info->cc_valid_p = 0;
2428 return SHIFT_SPECIAL;
2429 case SHIFT_ASHIFTRT:
2430 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2431 info->cc_valid_p = 0;
2432 return SHIFT_SPECIAL;
2435 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2437 if (shift_type == SHIFT_ASHIFTRT)
2443 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2445 info->shift2 = rotate_two[shift_type][shift_mode];
2447 info->shift2 = NULL;
2448 info->cc_valid_p = 0;
2449 return SHIFT_ROT_AND;
2452 else if (count == 31)
2454 if (shift_type == SHIFT_ASHIFTRT)
2457 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2459 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2460 info->cc_valid_p = 0;
2461 return SHIFT_SPECIAL;
2467 if (shift_type == SHIFT_ASHIFT)
2468 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2470 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2471 info->cc_valid_p = 0;
2472 return SHIFT_SPECIAL;
2476 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2478 info->shift2 = rotate_two[shift_type][shift_mode];
2480 info->shift2 = NULL;
2481 info->cc_valid_p = 0;
2482 return SHIFT_ROT_AND;
2492 /* No fancy method is available. Just loop. */
2496 /* Emit the assembler code for doing shifts. */
2499 emit_a_shift (insn, operands)
2500 rtx insn ATTRIBUTE_UNUSED;
2503 static int loopend_lab;
2504 rtx shift = operands[3];
2505 enum machine_mode mode = GET_MODE (shift);
2506 enum rtx_code code = GET_CODE (shift);
2507 enum shift_type shift_type;
2508 enum shift_mode shift_mode;
2509 struct shift_info info;
2516 shift_mode = QIshift;
2519 shift_mode = HIshift;
2522 shift_mode = SIshift;
2531 shift_type = SHIFT_ASHIFTRT;
2534 shift_type = SHIFT_LSHIFTRT;
2537 shift_type = SHIFT_ASHIFT;
2543 if (GET_CODE (operands[2]) != CONST_INT)
2545 /* Indexing by reg, so have to loop and test at top. */
2546 output_asm_insn ("mov.b %X2,%X4", operands);
2547 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2549 /* Get the assembler code to do one shift. */
2550 get_shift_alg (shift_type, shift_mode, 1, &info);
2552 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2553 output_asm_insn (info.shift1, operands);
2554 output_asm_insn ("add #0xff,%X4", operands);
2555 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2556 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2562 int n = INTVAL (operands[2]);
2565 /* If the count is negative, make it 0. */
2568 /* If the count is too big, truncate it.
2569 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2570 do the intuitive thing. */
2571 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2572 n = GET_MODE_BITSIZE (mode);
2574 alg = get_shift_alg (shift_type, shift_mode, n, &info);
2579 /* Emit two bit shifts first. */
2580 while (n > 1 && info.shift2 != NULL)
2582 output_asm_insn (info.shift2, operands);
2586 /* Now emit one bit shifts for any residual. */
2589 output_asm_insn (info.shift1, operands);
2593 /* Keep track of CC. */
2594 if (info.cc_valid_p)
2596 cc_status.value1 = operands[0];
2597 cc_status.flags |= info.cc_valid_p;
2603 int m = GET_MODE_BITSIZE (mode) - n;
2604 int mask = (shift_type == SHIFT_ASHIFT
2605 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2606 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2609 /* Not all possibilities of rotate are supported. They shouldn't
2610 be generated, but let's watch for 'em. */
2611 if (info.shift1 == 0)
2614 /* Emit two bit rotates first. */
2615 while (m > 1 && info.shift2 != NULL)
2617 output_asm_insn (info.shift2, operands);
2621 /* Now single bit rotates for any residual. */
2624 output_asm_insn (info.shift1, operands);
2628 /* Now mask off the high bits. */
2634 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2635 cc_status.value1 = operands[0];
2636 cc_status.flags |= CC_NO_CARRY;
2639 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2640 mask & 255, mask >> 8);
2650 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2651 "bwl"[shift_mode], mask,
2652 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2653 cc_status.value1 = operands[0];
2654 cc_status.flags |= CC_NO_CARRY;
2656 output_asm_insn (insn_buf, operands);
2661 output_asm_insn (info.special, operands);
2665 /* A loop to shift by a "large" constant value.
2666 If we have shift-by-2 insns, use them. */
2667 if (info.shift2 != NULL)
2669 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2670 names_big[REGNO (operands[4])]);
2671 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2672 output_asm_insn (info.shift2, operands);
2673 output_asm_insn ("add #0xff,%X4", operands);
2674 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2676 output_asm_insn (info.shift1, operands);
2680 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2681 names_big[REGNO (operands[4])]);
2682 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2683 output_asm_insn (info.shift1, operands);
2684 output_asm_insn ("add #0xff,%X4", operands);
2685 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2695 /* A rotation by a non-constant will cause a loop to be generated, in
2696 which a rotation by one bit is used. A rotation by a constant,
2697 including the one in the loop, will be taken care of by
2698 emit_a_rotate () at the insn emit time. */
2701 expand_a_rotate (code, operands)
2705 rtx dst = operands[0];
2706 rtx src = operands[1];
2707 rtx rotate_amount = operands[2];
2708 enum machine_mode mode = GET_MODE (dst);
2711 /* We rotate in place. */
2712 emit_move_insn (dst, src);
2714 if (GET_CODE (rotate_amount) != CONST_INT)
2716 rtx counter = gen_reg_rtx (QImode);
2717 rtx start_label = gen_label_rtx ();
2718 rtx end_label = gen_label_rtx ();
2720 /* If the rotate amount is less than or equal to 0,
2721 we go out of the loop. */
2722 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2723 LE, NULL_RTX, QImode, 0, 0, end_label);
2725 /* Initialize the loop counter. */
2726 emit_move_insn (counter, rotate_amount);
2728 emit_label (start_label);
2730 /* Rotate by one bit. */
2731 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2732 emit_insn (gen_rtx_SET (mode, dst, tmp));
2734 /* Decrement the counter by 1. */
2735 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2736 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2738 /* If the loop counter is non-zero, we go back to the beginning
2740 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2741 NE, NULL_RTX, QImode, 1, 0, start_label);
2743 emit_label (end_label);
2747 /* Rotate by AMOUNT bits. */
2748 tmp = gen_rtx (code, mode, dst, rotate_amount);
2749 emit_insn (gen_rtx_SET (mode, dst, tmp));
2755 /* Emit rotate insns. */
2758 emit_a_rotate (code, operands)
2762 rtx dst = operands[0];
2763 rtx rotate_amount = operands[2];
2764 enum shift_mode rotate_mode;
2765 enum shift_type rotate_type;
2766 const char *insn_buf;
2769 enum machine_mode mode = GET_MODE (dst);
2771 if (GET_CODE (rotate_amount) != CONST_INT)
2777 rotate_mode = QIshift;
2780 rotate_mode = HIshift;
2783 rotate_mode = SIshift;
2792 rotate_type = SHIFT_ASHIFT;
2795 rotate_type = SHIFT_LSHIFTRT;
2801 amount = INTVAL (rotate_amount);
2803 /* Clean up AMOUNT. */
2806 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2807 amount = GET_MODE_BITSIZE (mode);
2809 /* Determine the faster direction. After this phase, amount will be
2810 at most a half of GET_MODE_BITSIZE (mode). */
2811 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
2813 /* Flip the direction. */
2814 amount = GET_MODE_BITSIZE (mode) - amount;
2816 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2819 /* See if a byte swap (in HImode) or a word swap (in SImode) can
2820 boost up the rotation. */
2821 if ((mode == HImode && TARGET_H8300 && amount >= 5)
2822 || (mode == HImode && TARGET_H8300H && amount >= 6)
2823 || (mode == HImode && TARGET_H8300S && amount == 8)
2824 || (mode == SImode && TARGET_H8300H && amount >= 10)
2825 || (mode == SImode && TARGET_H8300S && amount >= 13))
2830 /* This code works on any family. */
2831 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
2832 output_asm_insn (insn_buf, operands);
2836 /* This code works on the H8/300H and H8/S. */
2837 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
2838 output_asm_insn (insn_buf, operands);
2845 /* Adjust AMOUNT and flip the direction. */
2846 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
2848 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2851 /* Emit rotate insns. */
2852 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
2855 insn_buf = rotate_two[rotate_type][rotate_mode];
2857 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2859 for (; amount >= bits; amount -= bits)
2860 output_asm_insn (insn_buf, operands);
2866 /* Fix the operands of a gen_xxx so that it could become a bit
2870 fix_bit_operand (operands, what, type)
2875 /* The bit_operand predicate accepts any memory during RTL generation, but
2876 only 'U' memory afterwards, so if this is a MEM operand, we must force
2877 it to be valid for 'U' by reloading the address. */
2879 if (GET_CODE (operands[2]) == CONST_INT)
2881 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2883 /* Ok to have a memory dest. */
2884 if (GET_CODE (operands[0]) == MEM
2885 && !EXTRA_CONSTRAINT (operands[0], 'U'))
2887 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2888 copy_to_mode_reg (Pmode,
2889 XEXP (operands[0], 0)));
2890 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2894 if (GET_CODE (operands[1]) == MEM
2895 && !EXTRA_CONSTRAINT (operands[1], 'U'))
2897 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2898 copy_to_mode_reg (Pmode,
2899 XEXP (operands[1], 0)));
2900 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2907 /* Dest and src op must be register. */
2909 operands[1] = force_reg (QImode, operands[1]);
2911 rtx res = gen_reg_rtx (QImode);
2912 emit_insn (gen_rtx_SET (VOIDmode, res,
2913 gen_rtx (type, QImode, operands[1], operands[2])));
2914 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2919 /* Return nonzero if FUNC is an interrupt function as specified
2920 by the "interrupt" attribute. */
2923 h8300_interrupt_function_p (func)
2928 if (TREE_CODE (func) != FUNCTION_DECL)
2931 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2932 return a != NULL_TREE;
2935 /* Return nonzero if FUNC is an OS_Task function as specified
2936 by the "OS_Task" attribute. */
2939 h8300_os_task_function_p (func)
2944 if (TREE_CODE (func) != FUNCTION_DECL)
2947 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2948 return a != NULL_TREE;
2951 /* Return nonzero if FUNC is a monitor function as specified
2952 by the "monitor" attribute. */
2955 h8300_monitor_function_p (func)
2960 if (TREE_CODE (func) != FUNCTION_DECL)
2963 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2964 return a != NULL_TREE;
2967 /* Return nonzero if FUNC is a function that should be called
2968 through the function vector. */
2971 h8300_funcvec_function_p (func)
2976 if (TREE_CODE (func) != FUNCTION_DECL)
2979 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2980 return a != NULL_TREE;
2983 /* Return nonzero if DECL is a variable that's in the eight bit
2987 h8300_eightbit_data_p (decl)
2992 if (TREE_CODE (decl) != VAR_DECL)
2995 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2996 return a != NULL_TREE;
2999 /* Return nonzero if DECL is a variable that's in the tiny
3003 h8300_tiny_data_p (decl)
3008 if (TREE_CODE (decl) != VAR_DECL)
3011 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
3012 return a != NULL_TREE;
3015 /* Return nonzero if ATTR is a valid attribute for DECL.
3016 ATTRIBUTES are any existing attributes and ARGS are the arguments
3019 Supported attributes:
3021 interrupt_handler: output a prologue and epilogue suitable for an
3024 function_vector: This function should be called through the
3027 eightbit_data: This variable lives in the 8-bit data area and can
3028 be referenced with 8-bit absolute memory addresses.
3030 tiny_data: This variable lives in the tiny data area and can be
3031 referenced with 16-bit absolute memory references. */
3034 h8300_valid_decl_attribute (decl, attributes, attr, args)
3036 tree attributes ATTRIBUTE_UNUSED;
3040 if (args != NULL_TREE)
3043 if (is_attribute_p ("interrupt_handler", attr)
3044 || is_attribute_p ("OS_Task", attr)
3045 || is_attribute_p ("monitor", attr)
3046 || is_attribute_p ("function_vector", attr))
3047 return TREE_CODE (decl) == FUNCTION_DECL;
3049 if (is_attribute_p ("eightbit_data", attr)
3050 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3052 if (DECL_INITIAL (decl) == NULL_TREE)
3054 warning ("Only initialized variables can be placed into the 8-bit area.");
3057 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3061 if (is_attribute_p ("tiny_data", attr)
3062 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3064 if (DECL_INITIAL (decl) == NULL_TREE)
3066 warning ("Only initialized variables can be placed into the 8-bit area.");
3069 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3077 h8300_encode_label (decl)
3080 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3081 int len = strlen (str);
3084 newstr = ggc_alloc_string (NULL, len + 1);
3086 strcpy (newstr + 1, str);
3088 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3092 output_simode_bld (bild, log2, operands)
3097 /* Clear the destination register. */
3098 if (TARGET_H8300H || TARGET_H8300S)
3099 output_asm_insn ("sub.l\t%S0,%S0", operands);
3101 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3103 /* Get the bit number we want to load. */
3105 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3107 /* Now output the bit load or bit inverse load, and store it in
3110 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3112 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3118 /* Given INSN and its current length LENGTH, return the adjustment
3119 (in bytes) to correctly compute INSN's length.
3121 We use this to get the lengths of various memory references correct. */
3124 h8300_adjust_insn_length (insn, length)
3126 int length ATTRIBUTE_UNUSED;
3130 /* We must filter these ou before calling get_attr_adjust_length. */
3131 if (GET_CODE (PATTERN (insn)) == USE
3132 || GET_CODE (PATTERN (insn)) == CLOBBER
3133 || GET_CODE (PATTERN (insn)) == SEQUENCE
3134 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3135 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3138 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3141 pat = PATTERN (insn);
3143 /* Adjust length for reg->mem and mem->reg copies. */
3144 if (GET_CODE (pat) == SET
3145 && (GET_CODE (SET_SRC (pat)) == MEM
3146 || GET_CODE (SET_DEST (pat)) == MEM))
3148 /* This insn might need a length adjustment. */
3151 if (GET_CODE (SET_SRC (pat)) == MEM)
3152 addr = XEXP (SET_SRC (pat), 0);
3154 addr = XEXP (SET_DEST (pat), 0);
3156 /* On the H8/300, only one adjustment is necessary; if the
3157 address mode is register indirect, then this insn is two
3158 bytes shorter than indicated in the machine description. */
3159 if (TARGET_H8300 && GET_CODE (addr) == REG)
3162 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3163 indicated in the machine description. */
3164 if ((TARGET_H8300H || TARGET_H8300S)
3165 && GET_CODE (addr) == REG)
3168 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3169 bytes shorter than indicated in the machine description. */
3170 if ((TARGET_H8300H || TARGET_H8300S)
3171 && GET_CODE (addr) == PLUS
3172 && GET_CODE (XEXP (addr, 0)) == REG
3173 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3174 && INTVAL (XEXP (addr, 1)) > -32768
3175 && INTVAL (XEXP (addr, 1)) < 32767)
3178 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3179 more general abs:24. */
3180 if ((TARGET_H8300H || TARGET_H8300S)
3181 && GET_CODE (addr) == SYMBOL_REF
3182 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3186 /* Loading some constants needs adjustment. */
3187 if (GET_CODE (pat) == SET
3188 && GET_CODE (SET_SRC (pat)) == CONST_INT
3189 && GET_MODE (SET_DEST (pat)) == SImode
3190 && INTVAL (SET_SRC (pat)) != 0)
3192 int val = INTVAL (SET_SRC (pat));
3195 && ((val & 0xffff) == 0
3196 || ((val >> 16) & 0xffff) == 0))
3199 if (TARGET_H8300H || TARGET_H8300S)
3201 if (val == (val & 0xff)
3202 || val == (val & 0xff00))
3205 if (val == -4 || val == -2 || val == -1)
3210 /* Shifts need various adjustments. */
3211 if (GET_CODE (pat) == PARALLEL
3212 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3213 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3214 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3215 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3217 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3218 enum machine_mode mode = GET_MODE (src);
3221 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3224 shift = INTVAL (XEXP (src, 1));
3225 /* According to ANSI, negative shift is undefined. It is
3226 considered to be zero in this case (see function
3227 emit_a_shift above). */
3231 /* QImode shifts by small constants take one insn
3232 per shift. So the adjustment is 20 (md length) -
3234 if (mode == QImode && shift <= 4)
3235 return -(20 - shift * 2);
3237 /* Similarly for HImode and SImode shifts by
3238 small constants on the H8/300H and H8/300S. */
3239 if ((TARGET_H8300H || TARGET_H8300S)
3240 && (mode == HImode || mode == SImode) && shift <= 4)
3241 return -(20 - shift * 2);
3243 /* HImode shifts by small constants for the H8/300. */
3244 if (mode == HImode && shift <= 4)
3245 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3247 /* SImode shifts by small constants for the H8/300. */
3248 if (mode == SImode && shift <= 2)
3249 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3251 /* XXX ??? Could check for more shift/rotate cases here. */
3254 /* Rotations need various adjustments. */
3255 if (GET_CODE (pat) == SET
3256 && (GET_CODE (SET_SRC (pat)) == ROTATE
3257 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3259 rtx src = SET_SRC (pat);
3260 enum machine_mode mode = GET_MODE (src);
3264 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3267 amount = INTVAL (XEXP (src, 1));
3269 /* Clean up AMOUNT. */
3272 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3273 amount = GET_MODE_BITSIZE (mode);
3275 /* Determine the faster direction. After this phase, amount
3276 will be at most a half of GET_MODE_BITSIZE (mode). */
3277 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3278 /* Flip the direction. */
3279 amount = GET_MODE_BITSIZE (mode) - amount;
3281 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3282 boost up the rotation. */
3283 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3284 || (mode == HImode && TARGET_H8300H && amount >= 6)
3285 || (mode == HImode && TARGET_H8300S && amount == 8)
3286 || (mode == SImode && TARGET_H8300H && amount >= 10)
3287 || (mode == SImode && TARGET_H8300S && amount >= 13))
3289 /* Adjust AMOUNT and flip the direction. */
3290 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3294 /* We use 2-bit rotatations on the H8/S. */
3296 amount = amount / 2 + amount % 2;
3298 /* The H8/300 uses three insns to rotate one bit, taking 6
3300 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3302 return -(20 - states);