1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
80 /* Forward declarations. */
81 static const char *byte_reg (rtx, int);
82 static int h8300_interrupt_function_p (tree);
83 static int h8300_saveall_function_p (tree);
84 static int h8300_monitor_function_p (tree);
85 static int h8300_os_task_function_p (tree);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
87 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
94 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
95 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree);
99 static int h8300_and_costs (rtx);
100 static int h8300_shift_costs (rtx);
101 static void h8300_push_pop (int, int, bool, bool);
102 static int h8300_stack_offset_p (rtx, int);
103 static int h8300_ldm_stm_regno (rtx, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx);
106 static unsigned int h8300_displacement_length (rtx, int);
107 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
108 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
109 static unsigned int h8300_unary_length (rtx);
110 static unsigned int h8300_short_immediate_length (rtx);
111 static unsigned int h8300_bitfield_length (rtx, rtx);
112 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
113 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
114 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 /* CPU_TYPE, says what cpu we're compiling for. */
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt;
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall;
126 static const char *const names_big[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
129 static const char *const names_extended[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
132 static const char *const names_upper_extended[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names;
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
141 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio;
146 /* See below where shifts are handled for explanation of this enum. */
156 /* Symbols of the various shifts which can be used as indices. */
160 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
174 static enum shift_alg shift_alg_qi[3][3][8] = {
177 /* 0 1 2 3 4 5 6 7 */
178 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
179 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
180 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
187 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
194 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
198 static enum shift_alg shift_alg_hi[3][3][16] = {
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL, INL, INL, INL, INL, INL, INL, SPC,
204 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
205 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
207 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL, INL, INL, INL, INL, INL, INL, SPC,
215 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, INL, INL, SPC,
217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL, INL, INL, INL, INL, INL, INL, INL,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
227 { INL, INL, INL, INL, INL, INL, INL, INL,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
234 static enum shift_alg shift_alg_si[3][3][32] = {
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
242 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
243 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
244 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
245 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
247 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
248 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
249 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
251 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
262 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
263 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
264 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
266 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
268 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
270 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL, INL, INL, INL, INL, INL, INL, INL,
280 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
281 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
282 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
283 { INL, INL, INL, INL, INL, INL, INL, INL,
284 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
285 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
286 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
287 { INL, INL, INL, INL, INL, INL, INL, INL,
288 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
289 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
290 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
306 /* Initialize various cpu specific globals at start up. */
309 h8300_init_once (void)
311 static const char *const h8_push_ops[2] = { "push" , "push.l" };
312 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
313 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
317 cpu_type = (int) CPU_H8300;
318 h8_reg_names = names_big;
322 /* For this we treat the H8/300H and H8S the same. */
323 cpu_type = (int) CPU_H8300H;
324 h8_reg_names = names_extended;
326 h8_push_op = h8_push_ops[cpu_type];
327 h8_pop_op = h8_pop_ops[cpu_type];
328 h8_mov_op = h8_mov_ops[cpu_type];
330 if (!TARGET_H8300S && TARGET_MAC)
332 error ("-ms2600 is used without -ms");
333 target_flags |= MASK_H8300S_1;
336 if (TARGET_H8300 && TARGET_NORMAL_MODE)
338 error ("-mn is used without -mh or -ms");
339 target_flags ^= MASK_NORMAL_MODE;
342 /* Some of the shifts are optimized for speed by default.
343 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
344 If optimizing for size, change shift_alg for those shift to
349 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
350 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
351 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
352 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
354 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
355 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
357 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
358 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
361 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
362 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
364 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
365 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
367 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
368 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
369 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
370 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
373 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
376 /* Work out a value for MOVE_RATIO. */
379 /* Memory-memory moves are quite expensive without the
380 h8sx instructions. */
381 h8300_move_ratio = 3;
383 else if (flag_omit_frame_pointer)
385 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
386 sometimes be as short as two individual memory-to-memory moves,
387 but since they use all the call-saved registers, it seems better
388 to allow up to three moves here. */
389 h8300_move_ratio = 4;
391 else if (optimize_size)
393 /* In this case we don't use movmd sequences since they tend
394 to be longer than calls to memcpy(). Memory-to-memory
395 moves are cheaper than for !TARGET_H8300SX, so it makes
396 sense to have a slightly higher threshold. */
397 h8300_move_ratio = 4;
401 /* We use movmd sequences for some moves since it can be quicker
402 than calling memcpy(). The sequences will need to save and
403 restore er6 though, so bump up the cost. */
404 h8300_move_ratio = 6;
408 /* Implement REG_CLASS_FROM_LETTER.
410 Some patterns need to use er6 as a scratch register. This is
411 difficult to arrange since er6 is the frame pointer and usually
414 Such patterns should define two alternatives, one which allows only
415 er6 and one which allows any general register. The former alternative
416 should have a 'd' constraint while the latter should be disparaged and
419 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
420 However, there are cases where they should be NO_REGS:
422 - 'd' should be NO_REGS when reloading a function that uses the
423 frame pointer. In this case, DESTINATION_REGS won't contain any
424 spillable registers, so the first alternative can't be used.
426 - -fno-omit-frame-pointer means that the frame pointer will
427 always be in use. It's therefore better to map 'd' to NO_REGS
428 before reload so that register allocator will pick the second
431 - we would like 'D' to be be NO_REGS when the frame pointer isn't
432 live, but we the frame pointer may turn out to be needed after
433 we start reload, and then we may have already decided we don't
434 have a choice, so we can't do that. Forcing the register
435 allocator to use er6 if possible might produce better code for
436 small functions: it's more efficient to save and restore er6 in
437 the prologue & epilogue than to do it in a define_split.
438 Hopefully disparaging 'D' will have a similar effect, without
439 forcing a reload failure if the frame pointer is found to be
443 h8300_reg_class_from_letter (int c)
454 if (!flag_omit_frame_pointer && !reload_completed)
456 if (frame_pointer_needed && reload_in_progress)
458 return DESTINATION_REGS;
461 /* The meaning of a constraint shouldn't change dynamically, so
462 we can't make this NO_REGS. */
473 /* Return the byte register name for a register rtx X. B should be 0
474 if you want a lower byte register. B should be 1 if you want an
475 upper byte register. */
478 byte_reg (rtx x, int b)
480 static const char *const names_small[] = {
481 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
482 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
485 gcc_assert (REG_P (x));
487 return names_small[REGNO (x) * 2 + b];
490 /* REGNO must be saved/restored across calls if this macro is true. */
492 #define WORD_REG_USED(regno) \
494 /* No need to save registers if this function will not return. */ \
495 && ! TREE_THIS_VOLATILE (current_function_decl) \
496 && (h8300_saveall_function_p (current_function_decl) \
497 /* Save any call saved register that was used. */ \
498 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
499 /* Save the frame pointer if it was used. */ \
500 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
501 /* Save any register used in an interrupt handler. */ \
502 || (h8300_current_function_interrupt_function_p () \
503 && df_regs_ever_live_p (regno)) \
504 /* Save call clobbered registers in non-leaf interrupt \
506 || (h8300_current_function_interrupt_function_p () \
507 && call_used_regs[regno] \
508 && !current_function_is_leaf)))
510 /* We use this to wrap all emitted insns in the prologue. */
512 F (rtx x, bool set_it)
515 RTX_FRAME_RELATED_P (x) = 1;
519 /* Mark all the subexpressions of the PARALLEL rtx PAR as
520 frame-related. Return PAR.
522 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
523 PARALLEL rtx other than the first if they do not have the
524 FRAME_RELATED flag set on them. */
528 int len = XVECLEN (par, 0);
531 for (i = 0; i < len; i++)
532 F (XVECEXP (par, 0, i), true);
537 /* Output assembly language to FILE for the operation OP with operand size
538 SIZE to adjust the stack pointer. */
541 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
543 /* If the frame size is 0, we don't have anything to do. */
547 /* H8/300 cannot add/subtract a large constant with a single
548 instruction. If a temporary register is available, load the
549 constant to it and then do the addition. */
552 && !h8300_current_function_interrupt_function_p ()
553 && !(cfun->static_chain_decl != NULL && sign < 0))
555 rtx r3 = gen_rtx_REG (Pmode, 3);
556 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
557 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
558 stack_pointer_rtx, r3)), in_prologue);
562 /* The stack adjustment made here is further optimized by the
563 splitter. In case of H8/300, the splitter always splits the
564 addition emitted here to make the adjustment interrupt-safe.
565 FIXME: We don't always tag those, because we don't know what
566 the splitter will do. */
569 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
570 stack_pointer_rtx, GEN_INT (sign * size)));
575 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
576 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
580 /* Round up frame size SIZE. */
583 round_frame_size (HOST_WIDE_INT size)
585 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
586 & -STACK_BOUNDARY / BITS_PER_UNIT);
589 /* Compute which registers to push/pop.
590 Return a bit vector of registers. */
593 compute_saved_regs (void)
595 unsigned int saved_regs = 0;
598 /* Construct a bit vector of registers to be pushed/popped. */
599 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
601 if (WORD_REG_USED (regno))
602 saved_regs |= 1 << regno;
605 /* Don't push/pop the frame pointer as it is treated separately. */
606 if (frame_pointer_needed)
607 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
612 /* Emit an insn to push register RN. */
617 rtx reg = gen_rtx_REG (word_mode, rn);
621 x = gen_push_h8300 (reg);
622 else if (!TARGET_NORMAL_MODE)
623 x = gen_push_h8300hs_advanced (reg);
625 x = gen_push_h8300hs_normal (reg);
626 x = F (emit_insn (x), true);
627 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
630 /* Emit an insn to pop register RN. */
635 rtx reg = gen_rtx_REG (word_mode, rn);
639 x = gen_pop_h8300 (reg);
640 else if (!TARGET_NORMAL_MODE)
641 x = gen_pop_h8300hs_advanced (reg);
643 x = gen_pop_h8300hs_normal (reg);
645 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
648 /* Emit an instruction to push or pop NREGS consecutive registers
649 starting at register REGNO. POP_P selects a pop rather than a
650 push and RETURN_P is true if the instruction should return.
652 It must be possible to do the requested operation in a single
653 instruction. If NREGS == 1 && !RETURN_P, use a normal push
654 or pop insn. Otherwise emit a parallel of the form:
657 [(return) ;; if RETURN_P
658 (save or restore REGNO)
659 (save or restore REGNO + 1)
661 (save or restore REGNO + NREGS - 1)
662 (set sp (plus sp (const_int adjust)))] */
665 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
671 /* See whether we can use a simple push or pop. */
672 if (!return_p && nregs == 1)
681 /* We need one element for the return insn, if present, one for each
682 register, and one for stack adjustment. */
683 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
684 sp = stack_pointer_rtx;
687 /* Add the return instruction. */
690 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
694 /* Add the register moves. */
695 for (j = 0; j < nregs; j++)
701 /* Register REGNO + NREGS - 1 is popped first. Before the
702 stack adjustment, its slot is at address @sp. */
703 lhs = gen_rtx_REG (SImode, regno + j);
704 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
708 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
709 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
710 rhs = gen_rtx_REG (SImode, regno + j);
712 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
715 /* Add the stack adjustment. */
716 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
717 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
718 gen_rtx_PLUS (Pmode, sp, offset));
720 x = gen_rtx_PARALLEL (VOIDmode, vec);
730 /* Return true if X has the value sp + OFFSET. */
733 h8300_stack_offset_p (rtx x, int offset)
736 return x == stack_pointer_rtx;
738 return (GET_CODE (x) == PLUS
739 && XEXP (x, 0) == stack_pointer_rtx
740 && GET_CODE (XEXP (x, 1)) == CONST_INT
741 && INTVAL (XEXP (x, 1)) == offset);
744 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
745 something that may be an ldm or stm instruction. If it fits
746 the required template, return the register it loads or stores,
749 LOAD_P is true if X should be a load, false if it should be a store.
750 NREGS is the number of registers that the whole instruction is expected
751 to load or store. INDEX is the index of the register that X should
752 load or store, relative to the lowest-numbered register. */
755 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
757 int regindex, memindex, offset;
760 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
762 memindex = 0, regindex = 1, offset = (index + 1) * -4;
764 if (GET_CODE (x) == SET
765 && GET_CODE (XEXP (x, regindex)) == REG
766 && GET_CODE (XEXP (x, memindex)) == MEM
767 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
768 return REGNO (XEXP (x, regindex));
773 /* Return true if the elements of VEC starting at FIRST describe an
774 ldm or stm instruction (LOAD_P says which). */
777 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
780 int nregs, i, regno, adjust;
782 /* There must be a stack adjustment, a register move, and at least one
783 other operation (a return or another register move). */
784 if (GET_NUM_ELEM (vec) < 3)
787 /* Get the range of registers to be pushed or popped. */
788 nregs = GET_NUM_ELEM (vec) - first - 1;
789 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
791 /* Check that the call to h8300_ldm_stm_regno succeeded and
792 that we're only dealing with GPRs. */
793 if (regno < 0 || regno + nregs > 8)
796 /* 2-register h8s instructions must start with an even-numbered register.
797 3- and 4-register instructions must start with er0 or er4. */
800 if ((regno & 1) != 0)
802 if (nregs > 2 && (regno & 3) != 0)
806 /* Check the other loads or stores. */
807 for (i = 1; i < nregs; i++)
808 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
812 /* Check the stack adjustment. */
813 last = RTVEC_ELT (vec, first + nregs);
814 adjust = (load_p ? nregs : -nregs) * 4;
815 return (GET_CODE (last) == SET
816 && SET_DEST (last) == stack_pointer_rtx
817 && h8300_stack_offset_p (SET_SRC (last), adjust));
820 /* This is what the stack looks like after the prolog of
821 a function with a frame has been set up:
827 <saved registers> <- sp
829 This is what the stack looks like after the prolog of
830 a function which doesn't have a frame:
835 <saved registers> <- sp
838 /* Generate RTL code for the function prologue. */
841 h8300_expand_prologue (void)
847 /* If the current function has the OS_Task attribute set, then
848 we have a naked prologue. */
849 if (h8300_os_task_function_p (current_function_decl))
852 if (h8300_monitor_function_p (current_function_decl))
853 /* My understanding of monitor functions is they act just like
854 interrupt functions, except the prologue must mask
856 emit_insn (gen_monitor_prologue ());
858 if (frame_pointer_needed)
861 push (HARD_FRAME_POINTER_REGNUM);
862 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
865 /* Push the rest of the registers in ascending order. */
866 saved_regs = compute_saved_regs ();
867 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
870 if (saved_regs & (1 << regno))
874 /* See how many registers we can push at the same time. */
875 if ((!TARGET_H8300SX || (regno & 3) == 0)
876 && ((saved_regs >> regno) & 0x0f) == 0x0f)
879 else if ((!TARGET_H8300SX || (regno & 3) == 0)
880 && ((saved_regs >> regno) & 0x07) == 0x07)
883 else if ((!TARGET_H8300SX || (regno & 1) == 0)
884 && ((saved_regs >> regno) & 0x03) == 0x03)
888 h8300_push_pop (regno, n_regs, false, false);
892 /* Leave room for locals. */
893 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
896 /* Return nonzero if we can use "rts" for the function currently being
900 h8300_can_use_return_insn_p (void)
902 return (reload_completed
903 && !frame_pointer_needed
904 && get_frame_size () == 0
905 && compute_saved_regs () == 0);
908 /* Generate RTL code for the function epilogue. */
911 h8300_expand_epilogue (void)
916 HOST_WIDE_INT frame_size;
919 if (h8300_os_task_function_p (current_function_decl))
920 /* OS_Task epilogues are nearly naked -- they just have an
924 frame_size = round_frame_size (get_frame_size ());
927 /* Deallocate locals. */
928 h8300_emit_stack_adjustment (1, frame_size, false);
930 /* Pop the saved registers in descending order. */
931 saved_regs = compute_saved_regs ();
932 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
935 if (saved_regs & (1 << regno))
939 /* See how many registers we can pop at the same time. */
940 if ((TARGET_H8300SX || (regno & 3) == 3)
941 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
944 else if ((TARGET_H8300SX || (regno & 3) == 2)
945 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
948 else if ((TARGET_H8300SX || (regno & 1) == 1)
949 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
953 /* See if this pop would be the last insn before the return.
954 If so, use rte/l or rts/l instead of pop or ldm.l. */
956 && !frame_pointer_needed
958 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
961 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
965 /* Pop frame pointer if we had one. */
966 if (frame_pointer_needed)
970 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
974 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
977 /* Return nonzero if the current function is an interrupt
981 h8300_current_function_interrupt_function_p (void)
983 return (h8300_interrupt_function_p (current_function_decl)
984 || h8300_monitor_function_p (current_function_decl));
987 /* Output assembly code for the start of the file. */
990 h8300_file_start (void)
992 default_file_start ();
995 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
996 else if (TARGET_H8300SX)
997 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
998 else if (TARGET_H8300S)
999 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1002 /* Output assembly language code for the end of file. */
1005 h8300_file_end (void)
1007 fputs ("\t.end\n", asm_out_file);
1010 /* Split an add of a small constant into two adds/subs insns.
1012 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1013 instead of adds/subs. */
1016 split_adds_subs (enum machine_mode mode, rtx *operands)
1018 HOST_WIDE_INT val = INTVAL (operands[1]);
1019 rtx reg = operands[0];
1020 HOST_WIDE_INT sign = 1;
1021 HOST_WIDE_INT amount;
1022 rtx (*gen_add) (rtx, rtx, rtx);
1024 /* Force VAL to be positive so that we do not have to consider the
1035 gen_add = gen_addhi3;
1039 gen_add = gen_addsi3;
1046 /* Try different amounts in descending order. */
1047 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1051 for (; val >= amount; val -= amount)
1052 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1058 /* Handle machine specific pragmas for compatibility with existing
1059 compilers for the H8/300.
1061 pragma saveall generates prologue/epilogue code which saves and
1062 restores all the registers on function entry.
1064 pragma interrupt saves and restores all registers, and exits with
1065 an rte instruction rather than an rts. A pointer to a function
1066 with this attribute may be safely used in an interrupt vector. */
1069 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1071 pragma_interrupt = 1;
1075 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1080 /* If the next function argument with MODE and TYPE is to be passed in
1081 a register, return a reg RTX for the hard register in which to pass
1082 the argument. CUM represents the state after the last argument.
1083 If the argument is to be pushed, NULL_RTX is returned. */
1086 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1087 tree type, int named)
1089 static const char *const hand_list[] = {
1108 rtx result = NULL_RTX;
1112 /* Never pass unnamed arguments in registers. */
1116 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1117 if (TARGET_QUICKCALL)
1120 /* If calling hand written assembler, use 4 regs of args. */
1123 const char * const *p;
1125 fname = XSTR (cum->libcall, 0);
1127 /* See if this libcall is one of the hand coded ones. */
1128 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1139 if (mode == BLKmode)
1140 size = int_size_in_bytes (type);
1142 size = GET_MODE_SIZE (mode);
1144 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1145 && cum->nbytes / UNITS_PER_WORD <= 3)
1146 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1152 /* Compute the cost of an and insn. */
1155 h8300_and_costs (rtx x)
1159 if (GET_MODE (x) == QImode)
1162 if (GET_MODE (x) != HImode
1163 && GET_MODE (x) != SImode)
1167 operands[1] = XEXP (x, 0);
1168 operands[2] = XEXP (x, 1);
1170 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1173 /* Compute the cost of a shift insn. */
1176 h8300_shift_costs (rtx x)
1180 if (GET_MODE (x) != QImode
1181 && GET_MODE (x) != HImode
1182 && GET_MODE (x) != SImode)
1187 operands[2] = XEXP (x, 1);
1189 return compute_a_shift_length (NULL, operands) / 2;
1192 /* Worker function for TARGET_RTX_COSTS. */
1195 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1197 if (TARGET_H8300SX && outer_code == MEM)
1199 /* Estimate the number of execution states needed to calculate
1201 if (register_operand (x, VOIDmode)
1202 || GET_CODE (x) == POST_INC
1203 || GET_CODE (x) == POST_DEC
1207 *total = COSTS_N_INSNS (1);
1215 HOST_WIDE_INT n = INTVAL (x);
1219 /* Constant operands need the same number of processor
1220 states as register operands. Although we could try to
1221 use a size-based cost for !speed, the lack of
1222 of a mode makes the results very unpredictable. */
1226 if (-4 <= n || n <= 4)
1237 *total = 0 + (outer_code == SET);
1241 if (TARGET_H8300H || TARGET_H8300S)
1242 *total = 0 + (outer_code == SET);
1257 /* See comment for CONST_INT. */
1269 if (XEXP (x, 1) == const0_rtx)
1274 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1275 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1277 *total = COSTS_N_INSNS (h8300_and_costs (x));
1280 /* We say that MOD and DIV are so expensive because otherwise we'll
1281 generate some really horrible code for division of a power of two. */
1287 switch (GET_MODE (x))
1291 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1295 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1301 *total = COSTS_N_INSNS (12);
1306 switch (GET_MODE (x))
1310 *total = COSTS_N_INSNS (2);
1314 *total = COSTS_N_INSNS (5);
1320 *total = COSTS_N_INSNS (4);
1326 if (h8sx_binary_shift_operator (x, VOIDmode))
1328 *total = COSTS_N_INSNS (2);
1331 else if (h8sx_unary_shift_operator (x, VOIDmode))
1333 *total = COSTS_N_INSNS (1);
1336 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1341 if (GET_MODE (x) == HImode)
1348 *total = COSTS_N_INSNS (1);
1353 /* Documentation for the machine specific operand escapes:
1355 'E' like s but negative.
1356 'F' like t but negative.
1357 'G' constant just the negative
1358 'R' print operand as a byte:8 address if appropriate, else fall back to
1360 'S' print operand as a long word
1361 'T' print operand as a word
1362 'V' find the set bit, and print its number.
1363 'W' find the clear bit, and print its number.
1364 'X' print operand as a byte
1365 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1366 If this operand isn't a register, fall back to 'R' handling.
1368 'c' print the opcode corresponding to rtl
1369 'e' first word of 32-bit value - if reg, then least reg. if mem
1370 then least. if const then most sig word
1371 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1372 then +2. if const then least sig word
1373 'j' print operand as condition code.
1374 'k' print operand as reverse condition code.
1375 'm' convert an integer operand to a size suffix (.b, .w or .l)
1376 'o' print an integer without a leading '#'
1377 's' print as low byte of 16-bit value
1378 't' print as high byte of 16-bit value
1379 'w' print as low byte of 32-bit value
1380 'x' print as 2nd byte of 32-bit value
1381 'y' print as 3rd byte of 32-bit value
1382 'z' print as msb of 32-bit value
1385 /* Return assembly language string which identifies a comparison type. */
1388 cond_string (enum rtx_code code)
1417 /* Print operand X using operand code CODE to assembly language output file
1421 print_operand (FILE *file, rtx x, int code)
1423 /* This is used for communication between codes V,W,Z and Y. */
1429 switch (GET_CODE (x))
1432 fprintf (file, "%sl", names_big[REGNO (x)]);
1435 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1442 switch (GET_CODE (x))
1445 fprintf (file, "%sh", names_big[REGNO (x)]);
1448 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1455 gcc_assert (GET_CODE (x) == CONST_INT);
1456 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1459 if (GET_CODE (x) == REG)
1460 fprintf (file, "%s", names_extended[REGNO (x)]);
1465 if (GET_CODE (x) == REG)
1466 fprintf (file, "%s", names_big[REGNO (x)]);
1471 bitint = exact_log2 (INTVAL (x) & 0xff);
1472 gcc_assert (bitint >= 0);
1473 fprintf (file, "#%d", bitint);
1476 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1477 gcc_assert (bitint >= 0);
1478 fprintf (file, "#%d", bitint);
1482 if (GET_CODE (x) == REG)
1483 fprintf (file, "%s", byte_reg (x, 0));
1488 gcc_assert (bitint >= 0);
1489 if (GET_CODE (x) == REG)
1490 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1492 print_operand (file, x, 'R');
1496 bitint = INTVAL (x);
1497 fprintf (file, "#%d", bitint & 7);
1500 switch (GET_CODE (x))
1503 fprintf (file, "or");
1506 fprintf (file, "xor");
1509 fprintf (file, "and");
1516 switch (GET_CODE (x))
1520 fprintf (file, "%s", names_big[REGNO (x)]);
1522 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1525 print_operand (file, x, 0);
1528 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1534 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1535 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1536 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1545 switch (GET_CODE (x))
1549 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1551 fprintf (file, "%s", names_big[REGNO (x)]);
1554 x = adjust_address (x, HImode, 2);
1555 print_operand (file, x, 0);
1558 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1564 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1565 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1566 fprintf (file, "#%ld", (val & 0xffff));
1574 fputs (cond_string (GET_CODE (x)), file);
1577 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1580 gcc_assert (GET_CODE (x) == CONST_INT);
1600 print_operand_address (file, x);
1603 if (GET_CODE (x) == CONST_INT)
1604 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1606 fprintf (file, "%s", byte_reg (x, 0));
1609 if (GET_CODE (x) == CONST_INT)
1610 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1612 fprintf (file, "%s", byte_reg (x, 1));
1615 if (GET_CODE (x) == CONST_INT)
1616 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1618 fprintf (file, "%s",
1619 byte_reg (x, TARGET_H8300 ? 2 : 0));
1622 if (GET_CODE (x) == CONST_INT)
1623 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1625 fprintf (file, "%s",
1626 byte_reg (x, TARGET_H8300 ? 3 : 1));
1629 if (GET_CODE (x) == CONST_INT)
1630 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1632 fprintf (file, "%s", byte_reg (x, 0));
1635 if (GET_CODE (x) == CONST_INT)
1636 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1638 fprintf (file, "%s", byte_reg (x, 1));
1643 switch (GET_CODE (x))
1646 switch (GET_MODE (x))
1649 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1650 fprintf (file, "%s", byte_reg (x, 0));
1651 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1652 fprintf (file, "%s", names_big[REGNO (x)]);
1656 fprintf (file, "%s", names_big[REGNO (x)]);
1660 fprintf (file, "%s", names_extended[REGNO (x)]);
1669 rtx addr = XEXP (x, 0);
1671 fprintf (file, "@");
1672 output_address (addr);
1674 /* Add a length suffix to constant addresses. Although this
1675 is often unnecessary, it helps to avoid ambiguity in the
1676 syntax of mova. If we wrote an insn like:
1678 mova/w.l @(1,@foo.b),er0
1680 then .b would be considered part of the symbol name.
1681 Adding a length after foo will avoid this. */
1682 if (CONSTANT_P (addr))
1686 /* Used for mov.b and bit operations. */
1687 if (h8300_eightbit_constant_address_p (addr))
1689 fprintf (file, ":8");
1693 /* Fall through. We should not get here if we are
1694 processing bit operations on H8/300 or H8/300H
1695 because 'U' constraint does not allow bit
1696 operations on the tiny area on these machines. */
1701 if (h8300_constant_length (addr) == 2)
1702 fprintf (file, ":16");
1704 fprintf (file, ":32");
1716 fprintf (file, "#");
1717 print_operand_address (file, x);
1723 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1724 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1725 fprintf (file, "#%ld", val);
1734 /* Output assembly language output for the address ADDR to FILE. */
1737 print_operand_address (FILE *file, rtx addr)
1742 switch (GET_CODE (addr))
1745 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1749 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1753 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1757 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1761 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1765 fprintf (file, "(");
1767 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1768 if (GET_CODE (index) == REG)
1771 print_operand_address (file, XEXP (addr, 1));
1772 fprintf (file, ",");
1776 print_operand_address (file, index);
1780 print_operand (file, index, 'X');
1785 print_operand (file, index, 'T');
1790 print_operand (file, index, 'S');
1794 /* print_operand_address (file, XEXP (addr, 0)); */
1799 print_operand_address (file, XEXP (addr, 0));
1800 fprintf (file, "+");
1801 print_operand_address (file, XEXP (addr, 1));
1803 fprintf (file, ")");
1808 /* Since the H8/300 only has 16-bit pointers, negative values are also
1809 those >= 32768. This happens for example with pointer minus a
1810 constant. We don't want to turn (char *p - 2) into
1811 (char *p + 65534) because loop unrolling can build upon this
1812 (IE: char *p + 131068). */
1813 int n = INTVAL (addr);
1815 n = (int) (short) n;
1816 fprintf (file, "%d", n);
1821 output_addr_const (file, addr);
1826 /* Output all insn addresses and their sizes into the assembly language
1827 output file. This is helpful for debugging whether the length attributes
1828 in the md file are correct. This is not meant to be a user selectable
1832 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1833 int num_operands ATTRIBUTE_UNUSED)
1835 /* This holds the last insn address. */
1836 static int last_insn_address = 0;
1838 const int uid = INSN_UID (insn);
1840 if (TARGET_ADDRESSES)
1842 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1843 INSN_ADDRESSES (uid) - last_insn_address);
1844 last_insn_address = INSN_ADDRESSES (uid);
1848 /* Prepare for an SI sized move. */
1851 h8300_expand_movsi (rtx operands[])
1853 rtx src = operands[1];
1854 rtx dst = operands[0];
1855 if (!reload_in_progress && !reload_completed)
1857 if (!register_operand (dst, GET_MODE (dst)))
1859 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1860 emit_move_insn (tmp, src);
1867 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1868 Frame pointer elimination is automatically handled.
1870 For the h8300, if frame pointer elimination is being done, we would like to
1871 convert ap and rp into sp, not fp.
1873 All other eliminations are valid. */
1876 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1878 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1881 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1882 Define the offset between two registers, one to be eliminated, and
1883 the other its replacement, at the start of a routine. */
1886 h8300_initial_elimination_offset (int from, int to)
1888 /* The number of bytes that the return address takes on the stack. */
1889 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1891 /* The number of bytes that the saved frame pointer takes on the stack. */
1892 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1894 /* The number of bytes that the saved registers, excluding the frame
1895 pointer, take on the stack. */
1896 int saved_regs_size = 0;
1898 /* The number of bytes that the locals takes on the stack. */
1899 int frame_size = round_frame_size (get_frame_size ());
1903 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1904 if (WORD_REG_USED (regno))
1905 saved_regs_size += UNITS_PER_WORD;
1907 /* Adjust saved_regs_size because the above loop took the frame
1908 pointer int account. */
1909 saved_regs_size -= fp_size;
1913 case HARD_FRAME_POINTER_REGNUM:
1916 case ARG_POINTER_REGNUM:
1917 return pc_size + fp_size;
1918 case RETURN_ADDRESS_POINTER_REGNUM:
1920 case FRAME_POINTER_REGNUM:
1921 return -saved_regs_size;
1926 case STACK_POINTER_REGNUM:
1929 case ARG_POINTER_REGNUM:
1930 return pc_size + saved_regs_size + frame_size;
1931 case RETURN_ADDRESS_POINTER_REGNUM:
1932 return saved_regs_size + frame_size;
1933 case FRAME_POINTER_REGNUM:
1945 /* Worker function for RETURN_ADDR_RTX. */
1948 h8300_return_addr_rtx (int count, rtx frame)
1953 ret = gen_rtx_MEM (Pmode,
1954 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1955 else if (flag_omit_frame_pointer)
1958 ret = gen_rtx_MEM (Pmode,
1959 memory_address (Pmode,
1960 plus_constant (frame, UNITS_PER_WORD)));
1961 set_mem_alias_set (ret, get_frame_alias_set ());
1965 /* Update the condition code from the insn. */
1968 notice_update_cc (rtx body, rtx insn)
1972 switch (get_attr_cc (insn))
1975 /* Insn does not affect CC at all. */
1979 /* Insn does not change CC, but the 0'th operand has been changed. */
1980 if (cc_status.value1 != 0
1981 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1982 cc_status.value1 = 0;
1983 if (cc_status.value2 != 0
1984 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1985 cc_status.value2 = 0;
1989 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1990 The V flag is unusable. The C flag may or may not be known but
1991 that's ok because alter_cond will change tests to use EQ/NE. */
1993 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1994 set = single_set (insn);
1995 cc_status.value1 = SET_SRC (set);
1996 if (SET_DEST (set) != cc0_rtx)
1997 cc_status.value2 = SET_DEST (set);
2001 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2002 The C flag may or may not be known but that's ok because
2003 alter_cond will change tests to use EQ/NE. */
2005 cc_status.flags |= CC_NO_CARRY;
2006 set = single_set (insn);
2007 cc_status.value1 = SET_SRC (set);
2008 if (SET_DEST (set) != cc0_rtx)
2010 /* If the destination is STRICT_LOW_PART, strip off
2012 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2013 cc_status.value2 = XEXP (SET_DEST (set), 0);
2015 cc_status.value2 = SET_DEST (set);
2020 /* The insn is a compare instruction. */
2022 cc_status.value1 = SET_SRC (body);
2026 /* Insn doesn't leave CC in a usable state. */
2032 /* Given that X occurs in an address of the form (plus X constant),
2033 return the part of X that is expected to be a register. There are
2034 four kinds of addressing mode to recognize:
2041 If SIZE is nonnull, and the address is one of the last three forms,
2042 set *SIZE to the index multiplication factor. Set it to 0 for
2043 plain @(dd,Rn) addresses.
2045 MODE is the mode of the value being accessed. It can be VOIDmode
2046 if the address is known to be valid, but its mode is unknown. */
2049 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2056 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2059 && (mode == VOIDmode
2060 || GET_MODE_CLASS (mode) == MODE_INT
2061 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2063 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2065 /* When accessing byte-sized values, the index can be
2066 a zero-extended QImode or HImode register. */
2067 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2072 /* We're looking for addresses of the form:
2075 or (mult (zero_extend X) I)
2077 where I is the size of the operand being accessed.
2078 The canonical form of the second expression is:
2080 (and (mult (subreg X) I) J)
2082 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2085 if (GET_CODE (x) == AND
2086 && GET_CODE (XEXP (x, 1)) == CONST_INT
2088 || INTVAL (XEXP (x, 1)) == 0xff * factor
2089 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2091 index = XEXP (x, 0);
2092 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2100 if (GET_CODE (index) == MULT
2101 && GET_CODE (XEXP (index, 1)) == CONST_INT
2102 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2103 return XEXP (index, 0);
2110 static const h8300_length_table addb_length_table =
2112 /* #xx Rs @aa @Rs @xx */
2113 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2114 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2115 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2116 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2119 static const h8300_length_table addw_length_table =
2121 /* #xx Rs @aa @Rs @xx */
2122 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2123 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2124 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2125 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2128 static const h8300_length_table addl_length_table =
2130 /* #xx Rs @aa @Rs @xx */
2131 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2132 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2133 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2134 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2137 #define logicb_length_table addb_length_table
2138 #define logicw_length_table addw_length_table
2140 static const h8300_length_table logicl_length_table =
2142 /* #xx Rs @aa @Rs @xx */
2143 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2144 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2145 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2146 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2149 static const h8300_length_table movb_length_table =
2151 /* #xx Rs @aa @Rs @xx */
2152 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2153 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2154 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2155 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2158 #define movw_length_table movb_length_table
2160 static const h8300_length_table movl_length_table =
2162 /* #xx Rs @aa @Rs @xx */
2163 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2164 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2165 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2166 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2169 /* Return the size of the given address or displacement constant. */
2172 h8300_constant_length (rtx constant)
2174 /* Check for (@d:16,Reg). */
2175 if (GET_CODE (constant) == CONST_INT
2176 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2179 /* Check for (@d:16,Reg) in cases where the displacement is
2180 an absolute address. */
2181 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2187 /* Return the size of a displacement field in address ADDR, which should
2188 have the form (plus X constant). SIZE is the number of bytes being
2192 h8300_displacement_length (rtx addr, int size)
2196 offset = XEXP (addr, 1);
2198 /* Check for @(d:2,Reg). */
2199 if (register_operand (XEXP (addr, 0), VOIDmode)
2200 && GET_CODE (offset) == CONST_INT
2201 && (INTVAL (offset) == size
2202 || INTVAL (offset) == size * 2
2203 || INTVAL (offset) == size * 3))
2206 return h8300_constant_length (offset);
2209 /* Store the class of operand OP in *OPCLASS and return the length of any
2210 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2211 can be null if only the length is needed. */
2214 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2216 enum h8300_operand_class dummy;
2221 if (CONSTANT_P (op))
2223 *opclass = H8OP_IMMEDIATE;
2225 /* Byte-sized immediates are stored in the opcode fields. */
2229 /* If this is a 32-bit instruction, see whether the constant
2230 will fit into a 16-bit immediate field. */
2233 && GET_CODE (op) == CONST_INT
2234 && IN_RANGE (INTVAL (op), 0, 0xffff))
2239 else if (GET_CODE (op) == MEM)
2242 if (CONSTANT_P (op))
2244 *opclass = H8OP_MEM_ABSOLUTE;
2245 return h8300_constant_length (op);
2247 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2249 *opclass = H8OP_MEM_COMPLEX;
2250 return h8300_displacement_length (op, size);
2252 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2254 *opclass = H8OP_MEM_COMPLEX;
2257 else if (register_operand (op, VOIDmode))
2259 *opclass = H8OP_MEM_BASE;
2263 gcc_assert (register_operand (op, VOIDmode));
2264 *opclass = H8OP_REGISTER;
2268 /* Return the length of the instruction described by TABLE given that
2269 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2270 and OP2 must be an h8300_src_operand. */
2273 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2275 enum h8300_operand_class op1_class, op2_class;
2276 unsigned int size, immediate_length;
2278 size = GET_MODE_SIZE (GET_MODE (op1));
2279 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2280 + h8300_classify_operand (op2, size, &op2_class));
2281 return immediate_length + (*table)[op1_class - 1][op2_class];
2284 /* Return the length of a unary instruction such as neg or not given that
2285 its operand is OP. */
2288 h8300_unary_length (rtx op)
2290 enum h8300_operand_class opclass;
2291 unsigned int size, operand_length;
2293 size = GET_MODE_SIZE (GET_MODE (op));
2294 operand_length = h8300_classify_operand (op, size, &opclass);
2301 return (size == 4 ? 6 : 4);
2303 case H8OP_MEM_ABSOLUTE:
2304 return operand_length + (size == 4 ? 6 : 4);
2306 case H8OP_MEM_COMPLEX:
2307 return operand_length + 6;
2314 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2317 h8300_short_immediate_length (rtx op)
2319 enum h8300_operand_class opclass;
2320 unsigned int size, operand_length;
2322 size = GET_MODE_SIZE (GET_MODE (op));
2323 operand_length = h8300_classify_operand (op, size, &opclass);
2331 case H8OP_MEM_ABSOLUTE:
2332 case H8OP_MEM_COMPLEX:
2333 return 4 + operand_length;
2340 /* Likewise bitfield load and store instructions. */
2343 h8300_bitfield_length (rtx op, rtx op2)
2345 enum h8300_operand_class opclass;
2346 unsigned int size, operand_length;
2348 if (GET_CODE (op) == REG)
2350 gcc_assert (GET_CODE (op) != REG);
2352 size = GET_MODE_SIZE (GET_MODE (op));
2353 operand_length = h8300_classify_operand (op, size, &opclass);
2358 case H8OP_MEM_ABSOLUTE:
2359 case H8OP_MEM_COMPLEX:
2360 return 4 + operand_length;
2367 /* Calculate the length of general binary instruction INSN using TABLE. */
2370 h8300_binary_length (rtx insn, const h8300_length_table *table)
2374 set = single_set (insn);
2377 if (BINARY_P (SET_SRC (set)))
2378 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2379 XEXP (SET_SRC (set), 1), table);
2382 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2383 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2384 XEXP (XEXP (SET_SRC (set), 1), 1),
2389 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2390 memory reference and either (1) it has the form @(d:16,Rn) or
2391 (2) its address has the code given by INC_CODE. */
2394 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2399 if (GET_CODE (op) != MEM)
2402 addr = XEXP (op, 0);
2403 size = GET_MODE_SIZE (GET_MODE (op));
2404 if (size != 1 && size != 2)
2407 return (GET_CODE (addr) == inc_code
2408 || (GET_CODE (addr) == PLUS
2409 && GET_CODE (XEXP (addr, 0)) == REG
2410 && h8300_displacement_length (addr, size) == 2));
2413 /* Calculate the length of move instruction INSN using the given length
2414 table. Although the tables are correct for most cases, there is some
2415 irregularity in the length of mov.b and mov.w. The following forms:
2422 are two bytes shorter than most other "mov Rs, @complex" or
2423 "mov @complex,Rd" combinations. */
2426 h8300_move_length (rtx *operands, const h8300_length_table *table)
2430 size = h8300_length_from_table (operands[0], operands[1], table);
2431 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2433 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2438 /* Return the length of a mova instruction with the given operands.
2439 DEST is the register destination, SRC is the source address and
2440 OFFSET is the 16-bit or 32-bit displacement. */
2443 h8300_mova_length (rtx dest, rtx src, rtx offset)
2448 + h8300_constant_length (offset)
2449 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2450 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2455 /* Compute the length of INSN based on its length_table attribute.
2456 OPERANDS is the array of its operands. */
2459 h8300_insn_length_from_table (rtx insn, rtx * operands)
2461 switch (get_attr_length_table (insn))
2463 case LENGTH_TABLE_NONE:
2466 case LENGTH_TABLE_ADDB:
2467 return h8300_binary_length (insn, &addb_length_table);
2469 case LENGTH_TABLE_ADDW:
2470 return h8300_binary_length (insn, &addw_length_table);
2472 case LENGTH_TABLE_ADDL:
2473 return h8300_binary_length (insn, &addl_length_table);
2475 case LENGTH_TABLE_LOGICB:
2476 return h8300_binary_length (insn, &logicb_length_table);
2478 case LENGTH_TABLE_MOVB:
2479 return h8300_move_length (operands, &movb_length_table);
2481 case LENGTH_TABLE_MOVW:
2482 return h8300_move_length (operands, &movw_length_table);
2484 case LENGTH_TABLE_MOVL:
2485 return h8300_move_length (operands, &movl_length_table);
2487 case LENGTH_TABLE_MOVA:
2488 return h8300_mova_length (operands[0], operands[1], operands[2]);
2490 case LENGTH_TABLE_MOVA_ZERO:
2491 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2493 case LENGTH_TABLE_UNARY:
2494 return h8300_unary_length (operands[0]);
2496 case LENGTH_TABLE_MOV_IMM4:
2497 return 2 + h8300_classify_operand (operands[0], 0, 0);
2499 case LENGTH_TABLE_SHORT_IMMEDIATE:
2500 return h8300_short_immediate_length (operands[0]);
2502 case LENGTH_TABLE_BITFIELD:
2503 return h8300_bitfield_length (operands[0], operands[1]);
2505 case LENGTH_TABLE_BITBRANCH:
2506 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2513 /* Return true if LHS and RHS are memory references that can be mapped
2514 to the same h8sx assembly operand. LHS appears as the destination of
2515 an instruction and RHS appears as a source.
2517 Three cases are allowed:
2519 - RHS is @+Rn or @-Rn, LHS is @Rn
2520 - RHS is @Rn, LHS is @Rn+ or @Rn-
2521 - RHS and LHS have the same address and neither has side effects. */
2524 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2526 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2528 rhs = XEXP (rhs, 0);
2529 lhs = XEXP (lhs, 0);
2531 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2532 return rtx_equal_p (XEXP (rhs, 0), lhs);
2534 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2535 return rtx_equal_p (rhs, XEXP (lhs, 0));
2537 if (rtx_equal_p (rhs, lhs))
2543 /* Return true if OPERANDS[1] can be mapped to the same assembly
2544 operand as OPERANDS[0]. */
2547 h8300_operands_match_p (rtx *operands)
2549 if (register_operand (operands[0], VOIDmode)
2550 && register_operand (operands[1], VOIDmode))
2553 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2559 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2560 region DEST. The two regions do not overlap and have the common
2561 alignment given by ALIGNMENT. Return true on success.
2563 Using movmd for variable-length moves seems to involve some
2564 complex trade-offs. For instance:
2566 - Preparing for a movmd instruction is similar to preparing
2567 for a memcpy. The main difference is that the arguments
2568 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2570 - Since movmd clobbers the frame pointer, we need to save
2571 and restore it somehow when frame_pointer_needed. This can
2572 sometimes make movmd sequences longer than calls to memcpy().
2574 - The counter register is 16 bits, so the instruction is only
2575 suitable for variable-length moves when sizeof (size_t) == 2.
2576 That's only true in normal mode.
2578 - We will often lack static alignment information. Falling back
2579 on movmd.b would likely be slower than calling memcpy(), at least
2582 This function therefore only uses movmd when the length is a
2583 known constant, and only then if -fomit-frame-pointer is in
2584 effect or if we're not optimizing for size.
2586 At the moment the function uses movmd for all in-range constants,
2587 but it might be better to fall back on memcpy() for large moves
2588 if ALIGNMENT == 1. */
2591 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2592 HOST_WIDE_INT alignment)
2594 if (!flag_omit_frame_pointer && optimize_size)
2597 if (GET_CODE (length) == CONST_INT)
2599 rtx dest_reg, src_reg, first_dest, first_src;
2603 /* Use movmd.l if the alignment allows it, otherwise fall back
2605 factor = (alignment >= 2 ? 4 : 1);
2607 /* Make sure the length is within range. We can handle counter
2608 values up to 65536, although HImode truncation will make
2609 the count appear negative in rtl dumps. */
2610 n = INTVAL (length);
2611 if (n <= 0 || n / factor > 65536)
2614 /* Create temporary registers for the source and destination
2615 pointers. Initialize them to the start of each region. */
2616 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2617 src_reg = copy_addr_to_reg (XEXP (src, 0));
2619 /* Create references to the movmd source and destination blocks. */
2620 first_dest = replace_equiv_address (dest, dest_reg);
2621 first_src = replace_equiv_address (src, src_reg);
2623 set_mem_size (first_dest, GEN_INT (n & -factor));
2624 set_mem_size (first_src, GEN_INT (n & -factor));
2626 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2627 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2629 if ((n & -factor) != n)
2631 /* Move SRC and DEST past the region we just copied.
2632 This is done to update the memory attributes. */
2633 dest = adjust_address (dest, BLKmode, n & -factor);
2634 src = adjust_address (src, BLKmode, n & -factor);
2636 /* Replace the addresses with the source and destination
2637 registers, which movmd has left with the right values. */
2638 dest = replace_equiv_address (dest, dest_reg);
2639 src = replace_equiv_address (src, src_reg);
2641 /* Mop up the left-over bytes. */
2643 emit_move_insn (adjust_address (dest, HImode, 0),
2644 adjust_address (src, HImode, 0));
2646 emit_move_insn (adjust_address (dest, QImode, n & 2),
2647 adjust_address (src, QImode, n & 2));
2654 /* Move ADDR into er6 after pushing its old value onto the stack. */
2657 h8300_swap_into_er6 (rtx addr)
2659 push (HARD_FRAME_POINTER_REGNUM);
2660 emit_move_insn (hard_frame_pointer_rtx, addr);
2661 if (REGNO (addr) == SP_REG)
2662 emit_move_insn (hard_frame_pointer_rtx,
2663 plus_constant (hard_frame_pointer_rtx,
2664 GET_MODE_SIZE (word_mode)));
2667 /* Move the current value of er6 into ADDR and pop its old value
2671 h8300_swap_out_of_er6 (rtx addr)
2673 if (REGNO (addr) != SP_REG)
2674 emit_move_insn (addr, hard_frame_pointer_rtx);
2675 pop (HARD_FRAME_POINTER_REGNUM);
2678 /* Return the length of mov instruction. */
2681 compute_mov_length (rtx *operands)
2683 /* If the mov instruction involves a memory operand, we compute the
2684 length, assuming the largest addressing mode is used, and then
2685 adjust later in the function. Otherwise, we compute and return
2686 the exact length in one step. */
2687 enum machine_mode mode = GET_MODE (operands[0]);
2688 rtx dest = operands[0];
2689 rtx src = operands[1];
2692 if (GET_CODE (src) == MEM)
2693 addr = XEXP (src, 0);
2694 else if (GET_CODE (dest) == MEM)
2695 addr = XEXP (dest, 0);
2701 unsigned int base_length;
2706 if (addr == NULL_RTX)
2709 /* The eightbit addressing is available only in QImode, so
2710 go ahead and take care of it. */
2711 if (h8300_eightbit_constant_address_p (addr))
2718 if (addr == NULL_RTX)
2723 if (src == const0_rtx)
2733 if (addr == NULL_RTX)
2738 if (GET_CODE (src) == CONST_INT)
2740 if (src == const0_rtx)
2743 if ((INTVAL (src) & 0xffff) == 0)
2746 if ((INTVAL (src) & 0xffff) == 0)
2749 if ((INTVAL (src) & 0xffff)
2750 == ((INTVAL (src) >> 16) & 0xffff))
2760 if (addr == NULL_RTX)
2765 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2778 /* Adjust the length based on the addressing mode used.
2779 Specifically, we subtract the difference between the actual
2780 length and the longest one, which is @(d:16,Rs). For SImode
2781 and SFmode, we double the adjustment because two mov.w are
2782 used to do the job. */
2784 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2785 if (GET_CODE (addr) == PRE_DEC
2786 || GET_CODE (addr) == POST_INC)
2788 if (mode == QImode || mode == HImode)
2789 return base_length - 2;
2791 /* In SImode and SFmode, we use two mov.w instructions, so
2792 double the adjustment. */
2793 return base_length - 4;
2796 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2797 in SImode and SFmode, the second mov.w involves an address
2798 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2800 if (GET_CODE (addr) == REG)
2801 return base_length - 2;
2807 unsigned int base_length;
2812 if (addr == NULL_RTX)
2815 /* The eightbit addressing is available only in QImode, so
2816 go ahead and take care of it. */
2817 if (h8300_eightbit_constant_address_p (addr))
2824 if (addr == NULL_RTX)
2829 if (src == const0_rtx)
2839 if (addr == NULL_RTX)
2843 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2849 if (GET_CODE (src) == CONST_INT)
2851 int val = INTVAL (src);
2856 if (val == (val & 0x00ff) || val == (val & 0xff00))
2859 switch (val & 0xffffffff)
2880 if (addr == NULL_RTX)
2885 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2898 /* Adjust the length based on the addressing mode used.
2899 Specifically, we subtract the difference between the actual
2900 length and the longest one, which is @(d:24,ERs). */
2902 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2903 if (GET_CODE (addr) == PRE_DEC
2904 || GET_CODE (addr) == POST_INC)
2905 return base_length - 6;
2907 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2908 if (GET_CODE (addr) == REG)
2909 return base_length - 6;
2911 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2913 if (GET_CODE (addr) == PLUS
2914 && GET_CODE (XEXP (addr, 0)) == REG
2915 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2916 && INTVAL (XEXP (addr, 1)) > -32768
2917 && INTVAL (XEXP (addr, 1)) < 32767)
2918 return base_length - 4;
2920 /* @aa:16 is 4 bytes shorter than the longest. */
2921 if (h8300_tiny_constant_address_p (addr))
2922 return base_length - 4;
2924 /* @aa:24 is 2 bytes shorter than the longest. */
2925 if (CONSTANT_P (addr))
2926 return base_length - 2;
2932 /* Output an addition insn. */
2935 output_plussi (rtx *operands)
2937 enum machine_mode mode = GET_MODE (operands[0]);
2939 gcc_assert (mode == SImode);
2943 if (GET_CODE (operands[2]) == REG)
2944 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2946 if (GET_CODE (operands[2]) == CONST_INT)
2948 HOST_WIDE_INT n = INTVAL (operands[2]);
2950 if ((n & 0xffffff) == 0)
2951 return "add\t%z2,%z0";
2952 if ((n & 0xffff) == 0)
2953 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2954 if ((n & 0xff) == 0)
2955 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2958 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2962 if (GET_CODE (operands[2]) == CONST_INT
2963 && register_operand (operands[1], VOIDmode))
2965 HOST_WIDE_INT intval = INTVAL (operands[2]);
2967 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2968 return "add.l\t%S2,%S0";
2969 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2970 return "sub.l\t%G2,%S0";
2972 /* See if we can finish with 2 bytes. */
2974 switch ((unsigned int) intval & 0xffffffff)
2979 return "adds\t%2,%S0";
2984 return "subs\t%G2,%S0";
2988 operands[2] = GEN_INT (intval >> 16);
2989 return "inc.w\t%2,%e0";
2993 operands[2] = GEN_INT (intval >> 16);
2994 return "dec.w\t%G2,%e0";
2997 /* See if we can finish with 4 bytes. */
2998 if ((intval & 0xffff) == 0)
3000 operands[2] = GEN_INT (intval >> 16);
3001 return "add.w\t%2,%e0";
3005 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3007 operands[2] = GEN_INT (-INTVAL (operands[2]));
3008 return "sub.l\t%S2,%S0";
3010 return "add.l\t%S2,%S0";
3014 /* ??? It would be much easier to add the h8sx stuff if a single function
3015 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3016 /* Compute the length of an addition insn. */
3019 compute_plussi_length (rtx *operands)
3021 enum machine_mode mode = GET_MODE (operands[0]);
3023 gcc_assert (mode == SImode);
3027 if (GET_CODE (operands[2]) == REG)
3030 if (GET_CODE (operands[2]) == CONST_INT)
3032 HOST_WIDE_INT n = INTVAL (operands[2]);
3034 if ((n & 0xffffff) == 0)
3036 if ((n & 0xffff) == 0)
3038 if ((n & 0xff) == 0)
3046 if (GET_CODE (operands[2]) == CONST_INT
3047 && register_operand (operands[1], VOIDmode))
3049 HOST_WIDE_INT intval = INTVAL (operands[2]);
3051 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3053 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3056 /* See if we can finish with 2 bytes. */
3058 switch ((unsigned int) intval & 0xffffffff)
3079 /* See if we can finish with 4 bytes. */
3080 if ((intval & 0xffff) == 0)
3084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3085 return h8300_length_from_table (operands[0],
3086 GEN_INT (-INTVAL (operands[2])),
3087 &addl_length_table);
3089 return h8300_length_from_table (operands[0], operands[2],
3090 &addl_length_table);
3095 /* Compute which flag bits are valid after an addition insn. */
3098 compute_plussi_cc (rtx *operands)
3100 enum machine_mode mode = GET_MODE (operands[0]);
3102 gcc_assert (mode == SImode);
3110 if (GET_CODE (operands[2]) == CONST_INT
3111 && register_operand (operands[1], VOIDmode))
3113 HOST_WIDE_INT intval = INTVAL (operands[2]);
3115 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3117 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3120 /* See if we can finish with 2 bytes. */
3122 switch ((unsigned int) intval & 0xffffffff)
3127 return CC_NONE_0HIT;
3132 return CC_NONE_0HIT;
3143 /* See if we can finish with 4 bytes. */
3144 if ((intval & 0xffff) == 0)
3152 /* Output a logical insn. */
3155 output_logical_op (enum machine_mode mode, rtx *operands)
3157 /* Figure out the logical op that we need to perform. */
3158 enum rtx_code code = GET_CODE (operands[3]);
3159 /* Pretend that every byte is affected if both operands are registers. */
3160 const unsigned HOST_WIDE_INT intval =
3161 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3162 /* Always use the full instruction if the
3163 first operand is in memory. It is better
3164 to use define_splits to generate the shorter
3165 sequence where valid. */
3166 && register_operand (operands[1], VOIDmode)
3167 ? INTVAL (operands[2]) : 0x55555555);
3168 /* The determinant of the algorithm. If we perform an AND, 0
3169 affects a bit. Otherwise, 1 affects a bit. */
3170 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3171 /* Break up DET into pieces. */
3172 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3173 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3174 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3175 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3176 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3177 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3178 int lower_half_easy_p = 0;
3179 int upper_half_easy_p = 0;
3180 /* The name of an insn. */
3202 /* First, see if we can finish with one insn. */
3203 if ((TARGET_H8300H || TARGET_H8300S)
3207 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3208 output_asm_insn (insn_buf, operands);
3212 /* Take care of the lower byte. */
3215 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3216 output_asm_insn (insn_buf, operands);
3218 /* Take care of the upper byte. */
3221 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3222 output_asm_insn (insn_buf, operands);
3227 if (TARGET_H8300H || TARGET_H8300S)
3229 /* Determine if the lower half can be taken care of in no more
3231 lower_half_easy_p = (b0 == 0
3233 || (code != IOR && w0 == 0xffff));
3235 /* Determine if the upper half can be taken care of in no more
3237 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3238 || (code == AND && w1 == 0xff00));
3241 /* Check if doing everything with one insn is no worse than
3242 using multiple insns. */
3243 if ((TARGET_H8300H || TARGET_H8300S)
3244 && w0 != 0 && w1 != 0
3245 && !(lower_half_easy_p && upper_half_easy_p)
3246 && !(code == IOR && w1 == 0xffff
3247 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3249 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3250 output_asm_insn (insn_buf, operands);
3254 /* Take care of the lower and upper words individually. For
3255 each word, we try different methods in the order of
3257 1) the special insn (in case of AND or XOR),
3258 2) the word-wise insn, and
3259 3) The byte-wise insn. */
3261 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3262 output_asm_insn ((code == AND)
3263 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3265 else if ((TARGET_H8300H || TARGET_H8300S)
3269 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3270 output_asm_insn (insn_buf, operands);
3276 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3277 output_asm_insn (insn_buf, operands);
3281 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3282 output_asm_insn (insn_buf, operands);
3287 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3288 output_asm_insn ((code == AND)
3289 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3291 else if ((TARGET_H8300H || TARGET_H8300S)
3294 && (w0 & 0x8000) != 0)
3296 output_asm_insn ("exts.l\t%S0", operands);
3298 else if ((TARGET_H8300H || TARGET_H8300S)
3302 output_asm_insn ("extu.w\t%e0", operands);
3304 else if (TARGET_H8300H || TARGET_H8300S)
3308 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3309 output_asm_insn (insn_buf, operands);
3316 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3317 output_asm_insn (insn_buf, operands);
3321 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3322 output_asm_insn (insn_buf, operands);
3333 /* Compute the length of a logical insn. */
3336 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3338 /* Figure out the logical op that we need to perform. */
3339 enum rtx_code code = GET_CODE (operands[3]);
3340 /* Pretend that every byte is affected if both operands are registers. */
3341 const unsigned HOST_WIDE_INT intval =
3342 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3343 /* Always use the full instruction if the
3344 first operand is in memory. It is better
3345 to use define_splits to generate the shorter
3346 sequence where valid. */
3347 && register_operand (operands[1], VOIDmode)
3348 ? INTVAL (operands[2]) : 0x55555555);
3349 /* The determinant of the algorithm. If we perform an AND, 0
3350 affects a bit. Otherwise, 1 affects a bit. */
3351 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3352 /* Break up DET into pieces. */
3353 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3354 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3355 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3356 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3357 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3358 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3359 int lower_half_easy_p = 0;
3360 int upper_half_easy_p = 0;
3362 unsigned int length = 0;
3367 /* First, see if we can finish with one insn. */
3368 if ((TARGET_H8300H || TARGET_H8300S)
3372 length = h8300_length_from_table (operands[1], operands[2],
3373 &logicw_length_table);
3377 /* Take care of the lower byte. */
3381 /* Take care of the upper byte. */
3387 if (TARGET_H8300H || TARGET_H8300S)
3389 /* Determine if the lower half can be taken care of in no more
3391 lower_half_easy_p = (b0 == 0
3393 || (code != IOR && w0 == 0xffff));
3395 /* Determine if the upper half can be taken care of in no more
3397 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3398 || (code == AND && w1 == 0xff00));
3401 /* Check if doing everything with one insn is no worse than
3402 using multiple insns. */
3403 if ((TARGET_H8300H || TARGET_H8300S)
3404 && w0 != 0 && w1 != 0
3405 && !(lower_half_easy_p && upper_half_easy_p)
3406 && !(code == IOR && w1 == 0xffff
3407 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3409 length = h8300_length_from_table (operands[1], operands[2],
3410 &logicl_length_table);
3414 /* Take care of the lower and upper words individually. For
3415 each word, we try different methods in the order of
3417 1) the special insn (in case of AND or XOR),
3418 2) the word-wise insn, and
3419 3) The byte-wise insn. */
3421 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3425 else if ((TARGET_H8300H || TARGET_H8300S)
3441 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3445 else if ((TARGET_H8300H || TARGET_H8300S)
3448 && (w0 & 0x8000) != 0)
3452 else if ((TARGET_H8300H || TARGET_H8300S)
3458 else if (TARGET_H8300H || TARGET_H8300S)
3479 /* Compute which flag bits are valid after a logical insn. */
3482 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3484 /* Figure out the logical op that we need to perform. */
3485 enum rtx_code code = GET_CODE (operands[3]);
3486 /* Pretend that every byte is affected if both operands are registers. */
3487 const unsigned HOST_WIDE_INT intval =
3488 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3489 /* Always use the full instruction if the
3490 first operand is in memory. It is better
3491 to use define_splits to generate the shorter
3492 sequence where valid. */
3493 && register_operand (operands[1], VOIDmode)
3494 ? INTVAL (operands[2]) : 0x55555555);
3495 /* The determinant of the algorithm. If we perform an AND, 0
3496 affects a bit. Otherwise, 1 affects a bit. */
3497 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3498 /* Break up DET into pieces. */
3499 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3500 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3501 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3502 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3503 int lower_half_easy_p = 0;
3504 int upper_half_easy_p = 0;
3505 /* Condition code. */
3506 enum attr_cc cc = CC_CLOBBER;
3511 /* First, see if we can finish with one insn. */
3512 if ((TARGET_H8300H || TARGET_H8300S)
3520 if (TARGET_H8300H || TARGET_H8300S)
3522 /* Determine if the lower half can be taken care of in no more
3524 lower_half_easy_p = (b0 == 0
3526 || (code != IOR && w0 == 0xffff));
3528 /* Determine if the upper half can be taken care of in no more
3530 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3531 || (code == AND && w1 == 0xff00));
3534 /* Check if doing everything with one insn is no worse than
3535 using multiple insns. */
3536 if ((TARGET_H8300H || TARGET_H8300S)
3537 && w0 != 0 && w1 != 0
3538 && !(lower_half_easy_p && upper_half_easy_p)
3539 && !(code == IOR && w1 == 0xffff
3540 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3546 if ((TARGET_H8300H || TARGET_H8300S)
3549 && (w0 & 0x8000) != 0)
3561 /* Expand a conditional branch. */
3564 h8300_expand_branch (rtx operands[])
3566 enum rtx_code code = GET_CODE (operands[0]);
3567 rtx op0 = operands[1];
3568 rtx op1 = operands[2];
3569 rtx label = operands[3];
3572 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3573 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3575 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3576 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3577 gen_rtx_LABEL_REF (VOIDmode, label),
3579 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3583 /* Expand a conditional store. */
3586 h8300_expand_store (rtx operands[])
3588 rtx dest = operands[0];
3589 enum rtx_code code = GET_CODE (operands[1]);
3590 rtx op0 = operands[2];
3591 rtx op1 = operands[3];
3594 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3595 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3597 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3598 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3603 We devote a fair bit of code to getting efficient shifts since we
3604 can only shift one bit at a time on the H8/300 and H8/300H and only
3605 one or two bits at a time on the H8S.
3607 All shift code falls into one of the following ways of
3610 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3611 when a straight line shift is about the same size or smaller than
3614 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3615 off the bits we don't need. This is used when only a few of the
3616 bits in the original value will survive in the shifted value.
3618 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3619 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3620 shifts can be added if the shift count is slightly more than 8 or
3621 16. This case also includes other oddballs that are not worth
3624 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3626 For each shift count, we try to use code that has no trade-off
3627 between code size and speed whenever possible.
3629 If the trade-off is unavoidable, we try to be reasonable.
3630 Specifically, the fastest version is one instruction longer than
3631 the shortest version, we take the fastest version. We also provide
3632 the use a way to switch back to the shortest version with -Os.
3634 For the details of the shift algorithms for various shift counts,
3635 refer to shift_alg_[qhs]i. */
3637 /* Classify a shift with the given mode and code. OP is the shift amount. */
3639 enum h8sx_shift_type
3640 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3642 if (!TARGET_H8300SX)
3643 return H8SX_SHIFT_NONE;
3649 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3650 if (GET_CODE (op) != CONST_INT)
3651 return H8SX_SHIFT_BINARY;
3653 /* Reject out-of-range shift amounts. */
3654 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3655 return H8SX_SHIFT_NONE;
3657 /* Power-of-2 shifts are effectively unary operations. */
3658 if (exact_log2 (INTVAL (op)) >= 0)
3659 return H8SX_SHIFT_UNARY;
3661 return H8SX_SHIFT_BINARY;
3664 if (op == const1_rtx || op == const2_rtx)
3665 return H8SX_SHIFT_UNARY;
3666 return H8SX_SHIFT_NONE;
3669 if (GET_CODE (op) == CONST_INT
3670 && (INTVAL (op) == 1
3672 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3673 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3674 return H8SX_SHIFT_UNARY;
3675 return H8SX_SHIFT_NONE;
3678 return H8SX_SHIFT_NONE;
3682 /* Return the asm template for a single h8sx shift instruction.
3683 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3684 is the source and OPERANDS[3] is the shift. SUFFIX is the
3685 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3686 prefix for the destination operand. */
3689 output_h8sx_shift (rtx *operands, int suffix, int optype)
3691 static char buffer[16];
3694 switch (GET_CODE (operands[3]))
3710 if (INTVAL (operands[2]) > 2)
3712 /* This is really a right rotate. */
3713 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3714 - INTVAL (operands[2]));
3722 if (operands[2] == const1_rtx)
3723 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3725 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3729 /* Emit code to do shifts. */
3732 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
3734 switch (h8sx_classify_shift (mode, code, operands[2]))
3736 case H8SX_SHIFT_BINARY:
3737 operands[1] = force_reg (mode, operands[1]);
3740 case H8SX_SHIFT_UNARY:
3743 case H8SX_SHIFT_NONE:
3747 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3749 /* Need a loop to get all the bits we want - we generate the
3750 code at emit time, but need to allocate a scratch reg now. */
3752 emit_insn (gen_rtx_PARALLEL
3755 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3756 gen_rtx_fmt_ee (code, mode,
3757 copy_rtx (operands[0]), operands[2])),
3758 gen_rtx_CLOBBER (VOIDmode,
3759 gen_rtx_SCRATCH (QImode)))));
3763 /* Symbols of the various modes which can be used as indices. */
3767 QIshift, HIshift, SIshift
3770 /* For single bit shift insns, record assembler and what bits of the
3771 condition code are valid afterwards (represented as various CC_FOO
3772 bits, 0 means CC isn't left in a usable state). */
3776 const char *const assembler;
3780 /* Assembler instruction shift table.
3782 These tables are used to look up the basic shifts.
3783 They are indexed by cpu, shift_type, and mode. */
3785 static const struct shift_insn shift_one[2][3][3] =
3791 { "shll\t%X0", CC_SET_ZNV },
3792 { "add.w\t%T0,%T0", CC_SET_ZN },
3793 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3795 /* SHIFT_LSHIFTRT */
3797 { "shlr\t%X0", CC_SET_ZNV },
3798 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3799 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3801 /* SHIFT_ASHIFTRT */
3803 { "shar\t%X0", CC_SET_ZNV },
3804 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3805 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3812 { "shll.b\t%X0", CC_SET_ZNV },
3813 { "shll.w\t%T0", CC_SET_ZNV },
3814 { "shll.l\t%S0", CC_SET_ZNV }
3816 /* SHIFT_LSHIFTRT */
3818 { "shlr.b\t%X0", CC_SET_ZNV },
3819 { "shlr.w\t%T0", CC_SET_ZNV },
3820 { "shlr.l\t%S0", CC_SET_ZNV }
3822 /* SHIFT_ASHIFTRT */
3824 { "shar.b\t%X0", CC_SET_ZNV },
3825 { "shar.w\t%T0", CC_SET_ZNV },
3826 { "shar.l\t%S0", CC_SET_ZNV }
3831 static const struct shift_insn shift_two[3][3] =
3835 { "shll.b\t#2,%X0", CC_SET_ZNV },
3836 { "shll.w\t#2,%T0", CC_SET_ZNV },
3837 { "shll.l\t#2,%S0", CC_SET_ZNV }
3839 /* SHIFT_LSHIFTRT */
3841 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3842 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3843 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3845 /* SHIFT_ASHIFTRT */
3847 { "shar.b\t#2,%X0", CC_SET_ZNV },
3848 { "shar.w\t#2,%T0", CC_SET_ZNV },
3849 { "shar.l\t#2,%S0", CC_SET_ZNV }
3853 /* Rotates are organized by which shift they'll be used in implementing.
3854 There's no need to record whether the cc is valid afterwards because
3855 it is the AND insn that will decide this. */
3857 static const char *const rotate_one[2][3][3] =
3864 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3867 /* SHIFT_LSHIFTRT */
3870 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3873 /* SHIFT_ASHIFTRT */
3876 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3888 /* SHIFT_LSHIFTRT */
3894 /* SHIFT_ASHIFTRT */
3903 static const char *const rotate_two[3][3] =
3911 /* SHIFT_LSHIFTRT */
3917 /* SHIFT_ASHIFTRT */
3926 /* Shift algorithm. */
3929 /* The number of bits to be shifted by shift1 and shift2. Valid
3930 when ALG is SHIFT_SPECIAL. */
3931 unsigned int remainder;
3933 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3934 const char *special;
3936 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3937 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3940 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3941 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3944 /* CC status for SHIFT_INLINE. */
3947 /* CC status for SHIFT_SPECIAL. */
3951 static void get_shift_alg (enum shift_type,
3952 enum shift_mode, unsigned int,
3953 struct shift_info *);
3955 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3956 best algorithm for doing the shift. The assembler code is stored
3957 in the pointers in INFO. We achieve the maximum efficiency in most
3958 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3959 SImode in particular have a lot of room to optimize.
3961 We first determine the strategy of the shift algorithm by a table
3962 lookup. If that tells us to use a hand crafted assembly code, we
3963 go into the big switch statement to find what that is. Otherwise,
3964 we resort to a generic way, such as inlining. In either case, the
3965 result is returned through INFO. */
3968 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3969 unsigned int count, struct shift_info *info)
3973 /* Find the target CPU. */
3976 else if (TARGET_H8300H)
3981 /* Find the shift algorithm. */
3982 info->alg = SHIFT_LOOP;
3986 if (count < GET_MODE_BITSIZE (QImode))
3987 info->alg = shift_alg_qi[cpu][shift_type][count];
3991 if (count < GET_MODE_BITSIZE (HImode))
3992 info->alg = shift_alg_hi[cpu][shift_type][count];
3996 if (count < GET_MODE_BITSIZE (SImode))
3997 info->alg = shift_alg_si[cpu][shift_type][count];
4004 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4008 info->remainder = count;
4012 /* It is up to the caller to know that looping clobbers cc. */
4013 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4014 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4015 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4019 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4020 info->shift2 = rotate_two[shift_type][shift_mode];
4021 info->cc_inline = CC_CLOBBER;
4025 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4026 info->remainder = 0;
4027 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4028 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4029 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4030 info->cc_special = CC_CLOBBER;
4034 /* Here we only deal with SHIFT_SPECIAL. */
4038 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4039 through the entire value. */
4040 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4041 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4051 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4053 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4055 case SHIFT_LSHIFTRT:
4057 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4059 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4061 case SHIFT_ASHIFTRT:
4062 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4066 else if ((8 <= count && count <= 13)
4067 || (TARGET_H8300S && count == 14))
4069 info->remainder = count - 8;
4074 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4076 case SHIFT_LSHIFTRT:
4079 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4080 info->shift1 = "shlr.b\t%s0";
4081 info->cc_inline = CC_SET_ZNV;
4085 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4086 info->cc_special = CC_SET_ZNV;
4089 case SHIFT_ASHIFTRT:
4092 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4093 info->shift1 = "shar.b\t%s0";
4097 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4098 info->cc_special = CC_SET_ZNV;
4103 else if (count == 14)
4109 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4111 case SHIFT_LSHIFTRT:
4113 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4115 case SHIFT_ASHIFTRT:
4117 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4118 else if (TARGET_H8300H)
4120 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4121 info->cc_special = CC_SET_ZNV;
4123 else /* TARGET_H8300S */
4128 else if (count == 15)
4133 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4135 case SHIFT_LSHIFTRT:
4136 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4138 case SHIFT_ASHIFTRT:
4139 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4146 if (TARGET_H8300 && 8 <= count && count <= 9)
4148 info->remainder = count - 8;
4153 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4155 case SHIFT_LSHIFTRT:
4156 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4157 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4159 case SHIFT_ASHIFTRT:
4160 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4164 else if (count == 8 && !TARGET_H8300)
4169 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4171 case SHIFT_LSHIFTRT:
4172 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4174 case SHIFT_ASHIFTRT:
4175 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4179 else if (count == 15 && TARGET_H8300)
4185 case SHIFT_LSHIFTRT:
4186 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4188 case SHIFT_ASHIFTRT:
4189 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4193 else if (count == 15 && !TARGET_H8300)
4198 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4199 info->cc_special = CC_SET_ZNV;
4201 case SHIFT_LSHIFTRT:
4202 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4203 info->cc_special = CC_SET_ZNV;
4205 case SHIFT_ASHIFTRT:
4209 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4210 || (TARGET_H8300H && 16 <= count && count <= 19)
4211 || (TARGET_H8300S && 16 <= count && count <= 21))
4213 info->remainder = count - 16;
4218 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4220 info->shift1 = "add.w\t%e0,%e0";
4222 case SHIFT_LSHIFTRT:
4225 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4226 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4230 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4231 info->cc_special = CC_SET_ZNV;
4234 case SHIFT_ASHIFTRT:
4237 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4238 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4242 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4243 info->cc_special = CC_SET_ZNV;
4248 else if (TARGET_H8300 && 24 <= count && count <= 28)
4250 info->remainder = count - 24;
4255 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4256 info->shift1 = "shll.b\t%z0";
4257 info->cc_inline = CC_SET_ZNV;
4259 case SHIFT_LSHIFTRT:
4260 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4261 info->shift1 = "shlr.b\t%w0";
4262 info->cc_inline = CC_SET_ZNV;
4264 case SHIFT_ASHIFTRT:
4265 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4266 info->shift1 = "shar.b\t%w0";
4267 info->cc_inline = CC_SET_ZNV;
4271 else if ((TARGET_H8300H && count == 24)
4272 || (TARGET_H8300S && 24 <= count && count <= 25))
4274 info->remainder = count - 24;
4279 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4281 case SHIFT_LSHIFTRT:
4282 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4283 info->cc_special = CC_SET_ZNV;
4285 case SHIFT_ASHIFTRT:
4286 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4287 info->cc_special = CC_SET_ZNV;
4291 else if (!TARGET_H8300 && count == 28)
4297 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4299 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4301 case SHIFT_LSHIFTRT:
4304 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4305 info->cc_special = CC_SET_ZNV;
4308 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4310 case SHIFT_ASHIFTRT:
4314 else if (!TARGET_H8300 && count == 29)
4320 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4322 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4324 case SHIFT_LSHIFTRT:
4327 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4328 info->cc_special = CC_SET_ZNV;
4332 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4333 info->cc_special = CC_SET_ZNV;
4336 case SHIFT_ASHIFTRT:
4340 else if (!TARGET_H8300 && count == 30)
4346 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4348 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4350 case SHIFT_LSHIFTRT:
4352 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4354 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4356 case SHIFT_ASHIFTRT:
4360 else if (count == 31)
4367 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4369 case SHIFT_LSHIFTRT:
4370 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4372 case SHIFT_ASHIFTRT:
4373 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4382 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4383 info->cc_special = CC_SET_ZNV;
4385 case SHIFT_LSHIFTRT:
4386 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4387 info->cc_special = CC_SET_ZNV;
4389 case SHIFT_ASHIFTRT:
4390 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4391 info->cc_special = CC_SET_ZNV;
4404 info->shift2 = NULL;
4407 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4408 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4411 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4416 if (GET_MODE_BITSIZE (mode) <= count)
4419 /* Find out the target CPU. */
4422 else if (TARGET_H8300H)
4427 /* Find the shift algorithm. */
4431 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4432 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4433 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4437 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4438 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4439 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4443 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4444 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4445 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4452 /* On H8/300H, count == 8 uses a scratch register. */
4453 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4454 || (TARGET_H8300H && mode == SImode && count == 8));
4457 /* Output the assembler code for doing shifts. */
4460 output_a_shift (rtx *operands)
4462 static int loopend_lab;
4463 rtx shift = operands[3];
4464 enum machine_mode mode = GET_MODE (shift);
4465 enum rtx_code code = GET_CODE (shift);
4466 enum shift_type shift_type;
4467 enum shift_mode shift_mode;
4468 struct shift_info info;
4476 shift_mode = QIshift;
4479 shift_mode = HIshift;
4482 shift_mode = SIshift;
4491 shift_type = SHIFT_ASHIFTRT;
4494 shift_type = SHIFT_LSHIFTRT;
4497 shift_type = SHIFT_ASHIFT;
4503 /* This case must be taken care of by one of the two splitters
4504 that convert a variable shift into a loop. */
4505 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4507 n = INTVAL (operands[2]);
4509 /* If the count is negative, make it 0. */
4512 /* If the count is too big, truncate it.
4513 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4514 do the intuitive thing. */
4515 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4516 n = GET_MODE_BITSIZE (mode);
4518 get_shift_alg (shift_type, shift_mode, n, &info);
4523 output_asm_insn (info.special, operands);
4529 /* Emit two bit shifts first. */
4530 if (info.shift2 != NULL)
4532 for (; n > 1; n -= 2)
4533 output_asm_insn (info.shift2, operands);
4536 /* Now emit one bit shifts for any residual. */
4538 output_asm_insn (info.shift1, operands);
4543 int m = GET_MODE_BITSIZE (mode) - n;
4544 const int mask = (shift_type == SHIFT_ASHIFT
4545 ? ((1 << m) - 1) << n
4549 /* Not all possibilities of rotate are supported. They shouldn't
4550 be generated, but let's watch for 'em. */
4551 gcc_assert (info.shift1);
4553 /* Emit two bit rotates first. */
4554 if (info.shift2 != NULL)
4556 for (; m > 1; m -= 2)
4557 output_asm_insn (info.shift2, operands);
4560 /* Now single bit rotates for any residual. */
4562 output_asm_insn (info.shift1, operands);
4564 /* Now mask off the high bits. */
4568 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4572 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4573 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4580 output_asm_insn (insn_buf, operands);
4585 /* A loop to shift by a "large" constant value.
4586 If we have shift-by-2 insns, use them. */
4587 if (info.shift2 != NULL)
4589 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4590 names_big[REGNO (operands[4])]);
4591 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4592 output_asm_insn (info.shift2, operands);
4593 output_asm_insn ("add #0xff,%X4", operands);
4594 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4596 output_asm_insn (info.shift1, operands);
4600 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4601 names_big[REGNO (operands[4])]);
4602 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4603 output_asm_insn (info.shift1, operands);
4604 output_asm_insn ("add #0xff,%X4", operands);
4605 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4614 /* Count the number of assembly instructions in a string TEMPL. */
4617 h8300_asm_insn_count (const char *templ)
4619 unsigned int count = 1;
4621 for (; *templ; templ++)
4628 /* Compute the length of a shift insn. */
4631 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4633 rtx shift = operands[3];
4634 enum machine_mode mode = GET_MODE (shift);
4635 enum rtx_code code = GET_CODE (shift);
4636 enum shift_type shift_type;
4637 enum shift_mode shift_mode;
4638 struct shift_info info;
4639 unsigned int wlength = 0;
4644 shift_mode = QIshift;
4647 shift_mode = HIshift;
4650 shift_mode = SIshift;
4659 shift_type = SHIFT_ASHIFTRT;
4662 shift_type = SHIFT_LSHIFTRT;
4665 shift_type = SHIFT_ASHIFT;
4671 if (GET_CODE (operands[2]) != CONST_INT)
4673 /* Get the assembler code to do one shift. */
4674 get_shift_alg (shift_type, shift_mode, 1, &info);
4676 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4680 int n = INTVAL (operands[2]);
4682 /* If the count is negative, make it 0. */
4685 /* If the count is too big, truncate it.
4686 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4687 do the intuitive thing. */
4688 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4689 n = GET_MODE_BITSIZE (mode);
4691 get_shift_alg (shift_type, shift_mode, n, &info);
4696 wlength += h8300_asm_insn_count (info.special);
4698 /* Every assembly instruction used in SHIFT_SPECIAL case
4699 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4700 see xor.l, we just pretend that xor.l counts as two insns
4701 so that the insn length will be computed correctly. */
4702 if (strstr (info.special, "xor.l") != NULL)
4710 if (info.shift2 != NULL)
4712 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4716 wlength += h8300_asm_insn_count (info.shift1) * n;
4722 int m = GET_MODE_BITSIZE (mode) - n;
4724 /* Not all possibilities of rotate are supported. They shouldn't
4725 be generated, but let's watch for 'em. */
4726 gcc_assert (info.shift1);
4728 if (info.shift2 != NULL)
4730 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4734 wlength += h8300_asm_insn_count (info.shift1) * m;
4736 /* Now mask off the high bits. */
4746 gcc_assert (!TARGET_H8300);
4756 /* A loop to shift by a "large" constant value.
4757 If we have shift-by-2 insns, use them. */
4758 if (info.shift2 != NULL)
4760 wlength += 3 + h8300_asm_insn_count (info.shift2);
4762 wlength += h8300_asm_insn_count (info.shift1);
4766 wlength += 3 + h8300_asm_insn_count (info.shift1);
4776 /* Compute which flag bits are valid after a shift insn. */
4779 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4781 rtx shift = operands[3];
4782 enum machine_mode mode = GET_MODE (shift);
4783 enum rtx_code code = GET_CODE (shift);
4784 enum shift_type shift_type;
4785 enum shift_mode shift_mode;
4786 struct shift_info info;
4792 shift_mode = QIshift;
4795 shift_mode = HIshift;
4798 shift_mode = SIshift;
4807 shift_type = SHIFT_ASHIFTRT;
4810 shift_type = SHIFT_LSHIFTRT;
4813 shift_type = SHIFT_ASHIFT;
4819 /* This case must be taken care of by one of the two splitters
4820 that convert a variable shift into a loop. */
4821 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4823 n = INTVAL (operands[2]);
4825 /* If the count is negative, make it 0. */
4828 /* If the count is too big, truncate it.
4829 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4830 do the intuitive thing. */
4831 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4832 n = GET_MODE_BITSIZE (mode);
4834 get_shift_alg (shift_type, shift_mode, n, &info);
4839 if (info.remainder == 0)
4840 return info.cc_special;
4845 return info.cc_inline;
4848 /* This case always ends with an and instruction. */
4852 /* A loop to shift by a "large" constant value.
4853 If we have shift-by-2 insns, use them. */
4854 if (info.shift2 != NULL)
4857 return info.cc_inline;
4866 /* A rotation by a non-constant will cause a loop to be generated, in
4867 which a rotation by one bit is used. A rotation by a constant,
4868 including the one in the loop, will be taken care of by
4869 output_a_rotate () at the insn emit time. */
4872 expand_a_rotate (rtx operands[])
4874 rtx dst = operands[0];
4875 rtx src = operands[1];
4876 rtx rotate_amount = operands[2];
4877 enum machine_mode mode = GET_MODE (dst);
4879 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4882 /* We rotate in place. */
4883 emit_move_insn (dst, src);
4885 if (GET_CODE (rotate_amount) != CONST_INT)
4887 rtx counter = gen_reg_rtx (QImode);
4888 rtx start_label = gen_label_rtx ();
4889 rtx end_label = gen_label_rtx ();
4891 /* If the rotate amount is less than or equal to 0,
4892 we go out of the loop. */
4893 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4894 QImode, 0, end_label);
4896 /* Initialize the loop counter. */
4897 emit_move_insn (counter, rotate_amount);
4899 emit_label (start_label);
4901 /* Rotate by one bit. */
4905 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4908 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4911 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4917 /* Decrement the counter by 1. */
4918 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4920 /* If the loop counter is nonzero, we go back to the beginning
4922 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4925 emit_label (end_label);
4929 /* Rotate by AMOUNT bits. */
4933 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4936 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4939 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4949 /* Output a rotate insn. */
4952 output_a_rotate (enum rtx_code code, rtx *operands)
4954 rtx dst = operands[0];
4955 rtx rotate_amount = operands[2];
4956 enum shift_mode rotate_mode;
4957 enum shift_type rotate_type;
4958 const char *insn_buf;
4961 enum machine_mode mode = GET_MODE (dst);
4963 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4968 rotate_mode = QIshift;
4971 rotate_mode = HIshift;
4974 rotate_mode = SIshift;
4983 rotate_type = SHIFT_ASHIFT;
4986 rotate_type = SHIFT_LSHIFTRT;
4992 amount = INTVAL (rotate_amount);
4994 /* Clean up AMOUNT. */
4997 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4998 amount = GET_MODE_BITSIZE (mode);
5000 /* Determine the faster direction. After this phase, amount will be
5001 at most a half of GET_MODE_BITSIZE (mode). */
5002 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5004 /* Flip the direction. */
5005 amount = GET_MODE_BITSIZE (mode) - amount;
5007 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5010 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5011 boost up the rotation. */
5012 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5013 || (mode == HImode && TARGET_H8300H && amount >= 6)
5014 || (mode == HImode && TARGET_H8300S && amount == 8)
5015 || (mode == SImode && TARGET_H8300H && amount >= 10)
5016 || (mode == SImode && TARGET_H8300S && amount >= 13))
5021 /* This code works on any family. */
5022 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5023 output_asm_insn (insn_buf, operands);
5027 /* This code works on the H8/300H and H8S. */
5028 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5029 output_asm_insn (insn_buf, operands);
5036 /* Adjust AMOUNT and flip the direction. */
5037 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5039 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5042 /* Output rotate insns. */
5043 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5046 insn_buf = rotate_two[rotate_type][rotate_mode];
5048 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5050 for (; amount >= bits; amount -= bits)
5051 output_asm_insn (insn_buf, operands);
5057 /* Compute the length of a rotate insn. */
5060 compute_a_rotate_length (rtx *operands)
5062 rtx src = operands[1];
5063 rtx amount_rtx = operands[2];
5064 enum machine_mode mode = GET_MODE (src);
5066 unsigned int length = 0;
5068 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5070 amount = INTVAL (amount_rtx);
5072 /* Clean up AMOUNT. */
5075 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5076 amount = GET_MODE_BITSIZE (mode);
5078 /* Determine the faster direction. After this phase, amount
5079 will be at most a half of GET_MODE_BITSIZE (mode). */
5080 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5081 /* Flip the direction. */
5082 amount = GET_MODE_BITSIZE (mode) - amount;
5084 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5085 boost up the rotation. */
5086 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5087 || (mode == HImode && TARGET_H8300H && amount >= 6)
5088 || (mode == HImode && TARGET_H8300S && amount == 8)
5089 || (mode == SImode && TARGET_H8300H && amount >= 10)
5090 || (mode == SImode && TARGET_H8300S && amount >= 13))
5092 /* Adjust AMOUNT and flip the direction. */
5093 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5097 /* We use 2-bit rotations on the H8S. */
5099 amount = amount / 2 + amount % 2;
5101 /* The H8/300 uses three insns to rotate one bit, taking 6
5103 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5108 /* Fix the operands of a gen_xxx so that it could become a bit
5112 fix_bit_operand (rtx *operands, enum rtx_code code)
5114 /* The bit_operand predicate accepts any memory during RTL generation, but
5115 only 'U' memory afterwards, so if this is a MEM operand, we must force
5116 it to be valid for 'U' by reloading the address. */
5119 ? single_zero_operand (operands[2], QImode)
5120 : single_one_operand (operands[2], QImode))
5122 /* OK to have a memory dest. */
5123 if (GET_CODE (operands[0]) == MEM
5124 && !OK_FOR_U (operands[0]))
5126 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5127 copy_to_mode_reg (Pmode,
5128 XEXP (operands[0], 0)));
5129 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5133 if (GET_CODE (operands[1]) == MEM
5134 && !OK_FOR_U (operands[1]))
5136 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5137 copy_to_mode_reg (Pmode,
5138 XEXP (operands[1], 0)));
5139 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5145 /* Dest and src op must be register. */
5147 operands[1] = force_reg (QImode, operands[1]);
5149 rtx res = gen_reg_rtx (QImode);
5153 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5156 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5159 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5164 emit_insn (gen_movqi (operands[0], res));
5169 /* Return nonzero if FUNC is an interrupt function as specified
5170 by the "interrupt" attribute. */
5173 h8300_interrupt_function_p (tree func)
5177 if (TREE_CODE (func) != FUNCTION_DECL)
5180 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5181 return a != NULL_TREE;
5184 /* Return nonzero if FUNC is a saveall function as specified by the
5185 "saveall" attribute. */
5188 h8300_saveall_function_p (tree func)
5192 if (TREE_CODE (func) != FUNCTION_DECL)
5195 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5196 return a != NULL_TREE;
5199 /* Return nonzero if FUNC is an OS_Task function as specified
5200 by the "OS_Task" attribute. */
5203 h8300_os_task_function_p (tree func)
5207 if (TREE_CODE (func) != FUNCTION_DECL)
5210 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5211 return a != NULL_TREE;
5214 /* Return nonzero if FUNC is a monitor function as specified
5215 by the "monitor" attribute. */
5218 h8300_monitor_function_p (tree func)
5222 if (TREE_CODE (func) != FUNCTION_DECL)
5225 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5226 return a != NULL_TREE;
5229 /* Return nonzero if FUNC is a function that should be called
5230 through the function vector. */
5233 h8300_funcvec_function_p (tree func)
5237 if (TREE_CODE (func) != FUNCTION_DECL)
5240 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5241 return a != NULL_TREE;
5244 /* Return nonzero if DECL is a variable that's in the eight bit
5248 h8300_eightbit_data_p (tree decl)
5252 if (TREE_CODE (decl) != VAR_DECL)
5255 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5256 return a != NULL_TREE;
5259 /* Return nonzero if DECL is a variable that's in the tiny
5263 h8300_tiny_data_p (tree decl)
5267 if (TREE_CODE (decl) != VAR_DECL)
5270 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5271 return a != NULL_TREE;
5274 /* Generate an 'interrupt_handler' attribute for decls. We convert
5275 all the pragmas to corresponding attributes. */
5278 h8300_insert_attributes (tree node, tree *attributes)
5280 if (TREE_CODE (node) == FUNCTION_DECL)
5282 if (pragma_interrupt)
5284 pragma_interrupt = 0;
5286 /* Add an 'interrupt_handler' attribute. */
5287 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5295 /* Add an 'saveall' attribute. */
5296 *attributes = tree_cons (get_identifier ("saveall"),
5302 /* Supported attributes:
5304 interrupt_handler: output a prologue and epilogue suitable for an
5307 saveall: output a prologue and epilogue that saves and restores
5308 all registers except the stack pointer.
5310 function_vector: This function should be called through the
5313 eightbit_data: This variable lives in the 8-bit data area and can
5314 be referenced with 8-bit absolute memory addresses.
5316 tiny_data: This variable lives in the tiny data area and can be
5317 referenced with 16-bit absolute memory references. */
5319 static const struct attribute_spec h8300_attribute_table[] =
5321 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5322 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5323 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5324 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5325 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5326 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5327 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
5328 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
5329 { NULL, 0, 0, false, false, false, NULL }
5333 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5334 struct attribute_spec.handler. */
5336 h8300_handle_fndecl_attribute (tree *node, tree name,
5337 tree args ATTRIBUTE_UNUSED,
5338 int flags ATTRIBUTE_UNUSED,
5341 if (TREE_CODE (*node) != FUNCTION_DECL)
5343 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5345 *no_add_attrs = true;
5351 /* Handle an "eightbit_data" attribute; arguments as in
5352 struct attribute_spec.handler. */
5354 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5355 tree args ATTRIBUTE_UNUSED,
5356 int flags ATTRIBUTE_UNUSED,
5361 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5363 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5367 warning (OPT_Wattributes, "%qE attribute ignored",
5369 *no_add_attrs = true;
5375 /* Handle an "tiny_data" attribute; arguments as in
5376 struct attribute_spec.handler. */
5378 h8300_handle_tiny_data_attribute (tree *node, tree name,
5379 tree args ATTRIBUTE_UNUSED,
5380 int flags ATTRIBUTE_UNUSED,
5385 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5387 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5391 warning (OPT_Wattributes, "%qE attribute ignored",
5393 *no_add_attrs = true;
5399 /* Mark function vectors, and various small data objects. */
5402 h8300_encode_section_info (tree decl, rtx rtl, int first)
5404 int extra_flags = 0;
5406 default_encode_section_info (decl, rtl, first);
5408 if (TREE_CODE (decl) == FUNCTION_DECL
5409 && h8300_funcvec_function_p (decl))
5410 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5411 else if (TREE_CODE (decl) == VAR_DECL
5412 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5414 if (h8300_eightbit_data_p (decl))
5415 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5416 else if (first && h8300_tiny_data_p (decl))
5417 extra_flags = SYMBOL_FLAG_TINY_DATA;
5421 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5424 /* Output a single-bit extraction. */
5427 output_simode_bld (int bild, rtx operands[])
5431 /* Clear the destination register. */
5432 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5434 /* Now output the bit load or bit inverse load, and store it in
5437 output_asm_insn ("bild\t%Z2,%Y1", operands);
5439 output_asm_insn ("bld\t%Z2,%Y1", operands);
5441 output_asm_insn ("bst\t#0,%w0", operands);
5445 /* Determine if we can clear the destination first. */
5446 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5447 && REGNO (operands[0]) != REGNO (operands[1]));
5450 output_asm_insn ("sub.l\t%S0,%S0", operands);
5452 /* Output the bit load or bit inverse load. */
5454 output_asm_insn ("bild\t%Z2,%Y1", operands);
5456 output_asm_insn ("bld\t%Z2,%Y1", operands);
5459 output_asm_insn ("xor.l\t%S0,%S0", operands);
5461 /* Perform the bit store. */
5462 output_asm_insn ("rotxl.l\t%S0", operands);
5469 /* Delayed-branch scheduling is more effective if we have some idea
5470 how long each instruction will be. Use a shorten_branches pass
5471 to get an initial estimate. */
5476 if (flag_delayed_branch)
5477 shorten_branches (get_insns ());
5480 #ifndef OBJECT_FORMAT_ELF
5482 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5485 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5486 fprintf (asm_out_file, "\t.section %s\n", name);
5488 #endif /* ! OBJECT_FORMAT_ELF */
5490 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5491 which is a special case of the 'R' operand. */
5494 h8300_eightbit_constant_address_p (rtx x)
5496 /* The ranges of the 8-bit area. */
5497 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5498 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5499 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5500 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5501 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5502 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5504 unsigned HOST_WIDE_INT addr;
5506 /* We accept symbols declared with eightbit_data. */
5507 if (GET_CODE (x) == SYMBOL_REF)
5508 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5510 if (GET_CODE (x) != CONST_INT)
5516 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5517 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5518 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5521 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5522 on H8/300H and H8S. */
5525 h8300_tiny_constant_address_p (rtx x)
5527 /* The ranges of the 16-bit area. */
5528 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5529 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5530 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5531 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5532 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5533 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5534 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5535 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5537 unsigned HOST_WIDE_INT addr;
5539 switch (GET_CODE (x))
5542 /* In the normal mode, any symbol fits in the 16-bit absolute
5543 address range. We also accept symbols declared with
5545 return (TARGET_NORMAL_MODE
5546 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5550 return (TARGET_NORMAL_MODE
5552 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5554 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5557 return TARGET_NORMAL_MODE;
5565 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5566 locations that can be accessed as a 16-bit word. */
5569 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5571 HOST_WIDE_INT offset1, offset2;
5579 else if (GET_CODE (addr1) == PLUS
5580 && REG_P (XEXP (addr1, 0))
5581 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5583 reg1 = XEXP (addr1, 0);
5584 offset1 = INTVAL (XEXP (addr1, 1));
5594 else if (GET_CODE (addr2) == PLUS
5595 && REG_P (XEXP (addr2, 0))
5596 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5598 reg2 = XEXP (addr2, 0);
5599 offset2 = INTVAL (XEXP (addr2, 1));
5604 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5605 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5607 && offset1 + 1 == offset2)
5613 /* Return nonzero if we have the same comparison insn as I3 two insns
5614 before I3. I3 is assumed to be a comparison insn. */
5617 same_cmp_preceding_p (rtx i3)
5621 /* Make sure we have a sequence of three insns. */
5622 i2 = prev_nonnote_insn (i3);
5625 i1 = prev_nonnote_insn (i2);
5629 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5630 && any_condjump_p (i2) && onlyjump_p (i2));
5633 /* Return nonzero if we have the same comparison insn as I1 two insns
5634 after I1. I1 is assumed to be a comparison insn. */
5637 same_cmp_following_p (rtx i1)
5641 /* Make sure we have a sequence of three insns. */
5642 i2 = next_nonnote_insn (i1);
5645 i3 = next_nonnote_insn (i2);
5649 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5650 && any_condjump_p (i2) && onlyjump_p (i2));
5653 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5654 (or pops) N registers. OPERANDS are assumed to be an array of
5658 h8300_regs_ok_for_stm (int n, rtx operands[])
5663 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5664 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5665 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5667 return ((REGNO (operands[0]) == 0
5668 && REGNO (operands[1]) == 1
5669 && REGNO (operands[2]) == 2)
5670 || (REGNO (operands[0]) == 4
5671 && REGNO (operands[1]) == 5
5672 && REGNO (operands[2]) == 6));
5675 return (REGNO (operands[0]) == 0
5676 && REGNO (operands[1]) == 1
5677 && REGNO (operands[2]) == 2
5678 && REGNO (operands[3]) == 3);
5684 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5687 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5688 unsigned int new_reg)
5690 /* Interrupt functions can only use registers that have already been
5691 saved by the prologue, even if they would normally be
5694 if (h8300_current_function_interrupt_function_p ()
5695 && !df_regs_ever_live_p (new_reg))
5701 /* Returns true if register REGNO is safe to be allocated as a scratch
5702 register in the current function. */
5705 h8300_hard_regno_scratch_ok (unsigned int regno)
5707 if (h8300_current_function_interrupt_function_p ()
5708 && ! WORD_REG_USED (regno))
5715 /* Return nonzero if X is a legitimate constant. */
5718 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
5723 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5726 h8300_rtx_ok_for_base_p (rtx x, int strict)
5728 /* Strip off SUBREG if any. */
5729 if (GET_CODE (x) == SUBREG)
5734 ? REG_OK_FOR_BASE_STRICT_P (x)
5735 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5738 /* Return nozero if X is a legitimate address. On the H8/300, a
5739 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5740 CONSTANT_ADDRESS. */
5743 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5745 /* The register indirect addresses like @er0 is always valid. */
5746 if (h8300_rtx_ok_for_base_p (x, strict))
5749 if (CONSTANT_ADDRESS_P (x))
5753 && ( GET_CODE (x) == PRE_INC
5754 || GET_CODE (x) == PRE_DEC
5755 || GET_CODE (x) == POST_INC
5756 || GET_CODE (x) == POST_DEC)
5757 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5760 if (GET_CODE (x) == PLUS
5761 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5762 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5769 /* Worker function for HARD_REGNO_NREGS.
5771 We pretend the MAC register is 32bits -- we don't have any data
5772 types on the H8 series to handle more than 32bits. */
5775 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5777 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5780 /* Worker function for HARD_REGNO_MODE_OK. */
5783 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5786 /* If an even reg, then anything goes. Otherwise the mode must be
5788 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5790 /* MAC register can only be of SImode. Otherwise, anything
5792 return regno == MAC_REG ? mode == SImode : 1;
5795 /* Perform target dependent optabs initialization. */
5797 h8300_init_libfuncs (void)
5799 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5800 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5801 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5802 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5803 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5806 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5809 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5811 return (TYPE_MODE (type) == BLKmode
5812 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5815 /* We emit the entire trampoline here. Depending on the pointer size,
5816 we use a different trampoline.
5820 1 0000 7903xxxx mov.w #0x1234,r3
5821 2 0004 5A00xxxx jmp @0x1234
5826 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5827 3 0006 5Axxxxxx jmp @0x123456
5832 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5834 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5837 if (Pmode == HImode)
5839 mem = adjust_address (m_tramp, HImode, 0);
5840 emit_move_insn (mem, GEN_INT (0x7903));
5841 mem = adjust_address (m_tramp, Pmode, 2);
5842 emit_move_insn (mem, cxt);
5843 mem = adjust_address (m_tramp, HImode, 4);
5844 emit_move_insn (mem, GEN_INT (0x5a00));
5845 mem = adjust_address (m_tramp, Pmode, 6);
5846 emit_move_insn (mem, fnaddr);
5852 mem = adjust_address (m_tramp, HImode, 0);
5853 emit_move_insn (mem, GEN_INT (0x7a03));
5854 mem = adjust_address (m_tramp, Pmode, 2);
5855 emit_move_insn (mem, cxt);
5857 tem = copy_to_reg (fnaddr);
5858 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5859 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5860 mem = adjust_address (m_tramp, SImode, 6);
5861 emit_move_insn (mem, tem);
5865 /* Initialize the GCC target structure. */
5866 #undef TARGET_ATTRIBUTE_TABLE
5867 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5869 #undef TARGET_ASM_ALIGNED_HI_OP
5870 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5872 #undef TARGET_ASM_FILE_START
5873 #define TARGET_ASM_FILE_START h8300_file_start
5874 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5875 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5877 #undef TARGET_ASM_FILE_END
5878 #define TARGET_ASM_FILE_END h8300_file_end
5880 #undef TARGET_ENCODE_SECTION_INFO
5881 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5883 #undef TARGET_INSERT_ATTRIBUTES
5884 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5886 #undef TARGET_RTX_COSTS
5887 #define TARGET_RTX_COSTS h8300_rtx_costs
5889 #undef TARGET_INIT_LIBFUNCS
5890 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5892 #undef TARGET_RETURN_IN_MEMORY
5893 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5895 #undef TARGET_MACHINE_DEPENDENT_REORG
5896 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5898 #undef TARGET_HARD_REGNO_SCRATCH_OK
5899 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5901 #undef TARGET_LEGITIMATE_ADDRESS_P
5902 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5904 #undef TARGET_DEFAULT_TARGET_FLAGS
5905 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5907 #undef TARGET_CAN_ELIMINATE
5908 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5910 #undef TARGET_TRAMPOLINE_INIT
5911 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5913 struct gcc_target targetm = TARGET_INITIALIZER;