1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
42 #include "c-family/c-pragma.h" /* ??? */
44 #include "tm-constrs.h"
47 #include "target-def.h"
50 /* Classifies a h8300_src_operand or h8300_dst_operand.
53 A constant operand of some sort.
59 A memory reference with a constant address.
62 A memory reference with a register as its address.
65 Some other kind of memory reference. */
66 enum h8300_operand_class
76 /* For a general two-operand instruction, element [X][Y] gives
77 the length of the opcode fields when the first operand has class
78 (X + 1) and the second has class Y. */
79 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
81 /* Forward declarations. */
82 static const char *byte_reg (rtx, int);
83 static int h8300_interrupt_function_p (tree);
84 static int h8300_saveall_function_p (tree);
85 static int h8300_monitor_function_p (tree);
86 static int h8300_os_task_function_p (tree);
87 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
88 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
89 static unsigned int compute_saved_regs (void);
90 static const char *cond_string (enum rtx_code);
91 static unsigned int h8300_asm_insn_count (const char *);
92 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
93 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
94 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
95 static void h8300_print_operand_address (FILE *, rtx);
96 static void h8300_print_operand (FILE *, rtx, int);
97 static bool h8300_print_operand_punct_valid_p (unsigned char code);
98 #ifndef OBJECT_FORMAT_ELF
99 static void h8300_asm_named_section (const char *, unsigned int, tree);
101 static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
102 static int h8300_and_costs (rtx);
103 static int h8300_shift_costs (rtx);
104 static void h8300_push_pop (int, int, bool, bool);
105 static int h8300_stack_offset_p (rtx, int);
106 static int h8300_ldm_stm_regno (rtx, int, int, int);
107 static void h8300_reorg (void);
108 static unsigned int h8300_constant_length (rtx);
109 static unsigned int h8300_displacement_length (rtx, int);
110 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
111 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
112 static unsigned int h8300_unary_length (rtx);
113 static unsigned int h8300_short_immediate_length (rtx);
114 static unsigned int h8300_bitfield_length (rtx, rtx);
115 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
116 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
117 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
118 static bool h8300_hard_regno_scratch_ok (unsigned int);
119 static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
121 /* CPU_TYPE, says what cpu we're compiling for. */
124 /* True if a #pragma interrupt has been seen for the current function. */
125 static int pragma_interrupt;
127 /* True if a #pragma saveall has been seen for the current function. */
128 static int pragma_saveall;
130 static const char *const names_big[] =
131 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
133 static const char *const names_extended[] =
134 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
136 static const char *const names_upper_extended[] =
137 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
139 /* Points to one of the above. */
140 /* ??? The above could be put in an array indexed by CPU_TYPE. */
141 const char * const *h8_reg_names;
143 /* Various operations needed by the following, indexed by CPU_TYPE. */
145 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
147 /* Value of MOVE_RATIO. */
148 int h8300_move_ratio;
150 /* See below where shifts are handled for explanation of this enum. */
160 /* Symbols of the various shifts which can be used as indices. */
164 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
167 /* Macros to keep the shift algorithm tables small. */
168 #define INL SHIFT_INLINE
169 #define ROT SHIFT_ROT_AND
170 #define LOP SHIFT_LOOP
171 #define SPC SHIFT_SPECIAL
173 /* The shift algorithms for each machine, mode, shift type, and shift
174 count are defined below. The three tables below correspond to
175 QImode, HImode, and SImode, respectively. Each table is organized
176 by, in the order of indices, machine, shift type, and shift count. */
178 static enum shift_alg shift_alg_qi[3][3][8] = {
181 /* 0 1 2 3 4 5 6 7 */
182 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
184 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
188 /* 0 1 2 3 4 5 6 7 */
189 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
190 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
191 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
197 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
198 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
202 static enum shift_alg shift_alg_hi[3][3][16] = {
205 /* 0 1 2 3 4 5 6 7 */
206 /* 8 9 10 11 12 13 14 15 */
207 { INL, INL, INL, INL, INL, INL, INL, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
209 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
211 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
212 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
216 /* 0 1 2 3 4 5 6 7 */
217 /* 8 9 10 11 12 13 14 15 */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
222 { INL, INL, INL, INL, INL, INL, INL, SPC,
223 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
227 /* 0 1 2 3 4 5 6 7 */
228 /* 8 9 10 11 12 13 14 15 */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
233 { INL, INL, INL, INL, INL, INL, INL, INL,
234 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
238 static enum shift_alg shift_alg_si[3][3][32] = {
241 /* 0 1 2 3 4 5 6 7 */
242 /* 8 9 10 11 12 13 14 15 */
243 /* 16 17 18 19 20 21 22 23 */
244 /* 24 25 26 27 28 29 30 31 */
245 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
246 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
247 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
248 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
249 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
250 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
251 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
253 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
254 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
255 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
256 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
260 /* 0 1 2 3 4 5 6 7 */
261 /* 8 9 10 11 12 13 14 15 */
262 /* 16 17 18 19 20 21 22 23 */
263 /* 24 25 26 27 28 29 30 31 */
264 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
266 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
268 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
270 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
272 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
274 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
275 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
279 /* 0 1 2 3 4 5 6 7 */
280 /* 8 9 10 11 12 13 14 15 */
281 /* 16 17 18 19 20 21 22 23 */
282 /* 24 25 26 27 28 29 30 31 */
283 { INL, INL, INL, INL, INL, INL, INL, INL,
284 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
285 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
286 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
287 { INL, INL, INL, INL, INL, INL, INL, INL,
288 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
289 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
290 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
291 { INL, INL, INL, INL, INL, INL, INL, INL,
292 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
293 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
294 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
310 /* Initialize various cpu specific globals at start up. */
313 h8300_option_override (void)
315 static const char *const h8_push_ops[2] = { "push" , "push.l" };
316 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
317 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
321 cpu_type = (int) CPU_H8300;
322 h8_reg_names = names_big;
326 /* For this we treat the H8/300H and H8S the same. */
327 cpu_type = (int) CPU_H8300H;
328 h8_reg_names = names_extended;
330 h8_push_op = h8_push_ops[cpu_type];
331 h8_pop_op = h8_pop_ops[cpu_type];
332 h8_mov_op = h8_mov_ops[cpu_type];
334 if (!TARGET_H8300S && TARGET_MAC)
336 error ("-ms2600 is used without -ms");
337 target_flags |= MASK_H8300S_1;
340 if (TARGET_H8300 && TARGET_NORMAL_MODE)
342 error ("-mn is used without -mh or -ms");
343 target_flags ^= MASK_NORMAL_MODE;
346 /* Some of the shifts are optimized for speed by default.
347 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
348 If optimizing for size, change shift_alg for those shift to
353 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
354 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
355 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
356 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
358 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
359 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
361 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
362 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
365 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
366 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
368 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
369 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
371 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
372 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
373 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
374 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
377 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
380 /* Work out a value for MOVE_RATIO. */
383 /* Memory-memory moves are quite expensive without the
384 h8sx instructions. */
385 h8300_move_ratio = 3;
387 else if (flag_omit_frame_pointer)
389 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
390 sometimes be as short as two individual memory-to-memory moves,
391 but since they use all the call-saved registers, it seems better
392 to allow up to three moves here. */
393 h8300_move_ratio = 4;
395 else if (optimize_size)
397 /* In this case we don't use movmd sequences since they tend
398 to be longer than calls to memcpy(). Memory-to-memory
399 moves are cheaper than for !TARGET_H8300SX, so it makes
400 sense to have a slightly higher threshold. */
401 h8300_move_ratio = 4;
405 /* We use movmd sequences for some moves since it can be quicker
406 than calling memcpy(). The sequences will need to save and
407 restore er6 though, so bump up the cost. */
408 h8300_move_ratio = 6;
411 /* This target defaults to strict volatile bitfields. */
412 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
413 flag_strict_volatile_bitfields = 1;
416 /* Return the byte register name for a register rtx X. B should be 0
417 if you want a lower byte register. B should be 1 if you want an
418 upper byte register. */
421 byte_reg (rtx x, int b)
423 static const char *const names_small[] = {
424 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
425 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
428 gcc_assert (REG_P (x));
430 return names_small[REGNO (x) * 2 + b];
433 /* REGNO must be saved/restored across calls if this macro is true. */
435 #define WORD_REG_USED(regno) \
437 /* No need to save registers if this function will not return. */ \
438 && ! TREE_THIS_VOLATILE (current_function_decl) \
439 && (h8300_saveall_function_p (current_function_decl) \
440 /* Save any call saved register that was used. */ \
441 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
442 /* Save the frame pointer if it was used. */ \
443 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
444 /* Save any register used in an interrupt handler. */ \
445 || (h8300_current_function_interrupt_function_p () \
446 && df_regs_ever_live_p (regno)) \
447 /* Save call clobbered registers in non-leaf interrupt \
449 || (h8300_current_function_interrupt_function_p () \
450 && call_used_regs[regno] \
451 && !current_function_is_leaf)))
453 /* We use this to wrap all emitted insns in the prologue. */
455 F (rtx x, bool set_it)
458 RTX_FRAME_RELATED_P (x) = 1;
462 /* Mark all the subexpressions of the PARALLEL rtx PAR as
463 frame-related. Return PAR.
465 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
466 PARALLEL rtx other than the first if they do not have the
467 FRAME_RELATED flag set on them. */
471 int len = XVECLEN (par, 0);
474 for (i = 0; i < len; i++)
475 F (XVECEXP (par, 0, i), true);
480 /* Output assembly language to FILE for the operation OP with operand size
481 SIZE to adjust the stack pointer. */
484 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
486 /* If the frame size is 0, we don't have anything to do. */
490 /* H8/300 cannot add/subtract a large constant with a single
491 instruction. If a temporary register is available, load the
492 constant to it and then do the addition. */
495 && !h8300_current_function_interrupt_function_p ()
496 && !(cfun->static_chain_decl != NULL && sign < 0))
498 rtx r3 = gen_rtx_REG (Pmode, 3);
499 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
500 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
501 stack_pointer_rtx, r3)), in_prologue);
505 /* The stack adjustment made here is further optimized by the
506 splitter. In case of H8/300, the splitter always splits the
507 addition emitted here to make the adjustment interrupt-safe.
508 FIXME: We don't always tag those, because we don't know what
509 the splitter will do. */
512 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
513 stack_pointer_rtx, GEN_INT (sign * size)));
518 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
519 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
523 /* Round up frame size SIZE. */
526 round_frame_size (HOST_WIDE_INT size)
528 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
529 & -STACK_BOUNDARY / BITS_PER_UNIT);
532 /* Compute which registers to push/pop.
533 Return a bit vector of registers. */
536 compute_saved_regs (void)
538 unsigned int saved_regs = 0;
541 /* Construct a bit vector of registers to be pushed/popped. */
542 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
544 if (WORD_REG_USED (regno))
545 saved_regs |= 1 << regno;
548 /* Don't push/pop the frame pointer as it is treated separately. */
549 if (frame_pointer_needed)
550 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
555 /* Emit an insn to push register RN. */
560 rtx reg = gen_rtx_REG (word_mode, rn);
564 x = gen_push_h8300 (reg);
565 else if (!TARGET_NORMAL_MODE)
566 x = gen_push_h8300hs_advanced (reg);
568 x = gen_push_h8300hs_normal (reg);
569 x = F (emit_insn (x), true);
570 add_reg_note (x, REG_INC, stack_pointer_rtx);
574 /* Emit an insn to pop register RN. */
579 rtx reg = gen_rtx_REG (word_mode, rn);
583 x = gen_pop_h8300 (reg);
584 else if (!TARGET_NORMAL_MODE)
585 x = gen_pop_h8300hs_advanced (reg);
587 x = gen_pop_h8300hs_normal (reg);
589 add_reg_note (x, REG_INC, stack_pointer_rtx);
593 /* Emit an instruction to push or pop NREGS consecutive registers
594 starting at register REGNO. POP_P selects a pop rather than a
595 push and RETURN_P is true if the instruction should return.
597 It must be possible to do the requested operation in a single
598 instruction. If NREGS == 1 && !RETURN_P, use a normal push
599 or pop insn. Otherwise emit a parallel of the form:
602 [(return) ;; if RETURN_P
603 (save or restore REGNO)
604 (save or restore REGNO + 1)
606 (save or restore REGNO + NREGS - 1)
607 (set sp (plus sp (const_int adjust)))] */
610 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
616 /* See whether we can use a simple push or pop. */
617 if (!return_p && nregs == 1)
626 /* We need one element for the return insn, if present, one for each
627 register, and one for stack adjustment. */
628 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
629 sp = stack_pointer_rtx;
632 /* Add the return instruction. */
635 RTVEC_ELT (vec, i) = ret_rtx;
639 /* Add the register moves. */
640 for (j = 0; j < nregs; j++)
646 /* Register REGNO + NREGS - 1 is popped first. Before the
647 stack adjustment, its slot is at address @sp. */
648 lhs = gen_rtx_REG (SImode, regno + j);
649 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
653 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
654 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
655 rhs = gen_rtx_REG (SImode, regno + j);
657 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
660 /* Add the stack adjustment. */
661 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
662 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
663 gen_rtx_PLUS (Pmode, sp, offset));
665 x = gen_rtx_PARALLEL (VOIDmode, vec);
675 /* Return true if X has the value sp + OFFSET. */
678 h8300_stack_offset_p (rtx x, int offset)
681 return x == stack_pointer_rtx;
683 return (GET_CODE (x) == PLUS
684 && XEXP (x, 0) == stack_pointer_rtx
685 && GET_CODE (XEXP (x, 1)) == CONST_INT
686 && INTVAL (XEXP (x, 1)) == offset);
689 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
690 something that may be an ldm or stm instruction. If it fits
691 the required template, return the register it loads or stores,
694 LOAD_P is true if X should be a load, false if it should be a store.
695 NREGS is the number of registers that the whole instruction is expected
696 to load or store. INDEX is the index of the register that X should
697 load or store, relative to the lowest-numbered register. */
700 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
702 int regindex, memindex, offset;
705 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
707 memindex = 0, regindex = 1, offset = (index + 1) * -4;
709 if (GET_CODE (x) == SET
710 && GET_CODE (XEXP (x, regindex)) == REG
711 && GET_CODE (XEXP (x, memindex)) == MEM
712 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
713 return REGNO (XEXP (x, regindex));
718 /* Return true if the elements of VEC starting at FIRST describe an
719 ldm or stm instruction (LOAD_P says which). */
722 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
725 int nregs, i, regno, adjust;
727 /* There must be a stack adjustment, a register move, and at least one
728 other operation (a return or another register move). */
729 if (GET_NUM_ELEM (vec) < 3)
732 /* Get the range of registers to be pushed or popped. */
733 nregs = GET_NUM_ELEM (vec) - first - 1;
734 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
736 /* Check that the call to h8300_ldm_stm_regno succeeded and
737 that we're only dealing with GPRs. */
738 if (regno < 0 || regno + nregs > 8)
741 /* 2-register h8s instructions must start with an even-numbered register.
742 3- and 4-register instructions must start with er0 or er4. */
745 if ((regno & 1) != 0)
747 if (nregs > 2 && (regno & 3) != 0)
751 /* Check the other loads or stores. */
752 for (i = 1; i < nregs; i++)
753 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
757 /* Check the stack adjustment. */
758 last = RTVEC_ELT (vec, first + nregs);
759 adjust = (load_p ? nregs : -nregs) * 4;
760 return (GET_CODE (last) == SET
761 && SET_DEST (last) == stack_pointer_rtx
762 && h8300_stack_offset_p (SET_SRC (last), adjust));
765 /* This is what the stack looks like after the prolog of
766 a function with a frame has been set up:
772 <saved registers> <- sp
774 This is what the stack looks like after the prolog of
775 a function which doesn't have a frame:
780 <saved registers> <- sp
783 /* Generate RTL code for the function prologue. */
786 h8300_expand_prologue (void)
792 /* If the current function has the OS_Task attribute set, then
793 we have a naked prologue. */
794 if (h8300_os_task_function_p (current_function_decl))
797 if (h8300_monitor_function_p (current_function_decl))
798 /* My understanding of monitor functions is they act just like
799 interrupt functions, except the prologue must mask
801 emit_insn (gen_monitor_prologue ());
803 if (frame_pointer_needed)
806 push (HARD_FRAME_POINTER_REGNUM);
807 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
810 /* Push the rest of the registers in ascending order. */
811 saved_regs = compute_saved_regs ();
812 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
815 if (saved_regs & (1 << regno))
819 /* See how many registers we can push at the same time. */
820 if ((!TARGET_H8300SX || (regno & 3) == 0)
821 && ((saved_regs >> regno) & 0x0f) == 0x0f)
824 else if ((!TARGET_H8300SX || (regno & 3) == 0)
825 && ((saved_regs >> regno) & 0x07) == 0x07)
828 else if ((!TARGET_H8300SX || (regno & 1) == 0)
829 && ((saved_regs >> regno) & 0x03) == 0x03)
833 h8300_push_pop (regno, n_regs, false, false);
837 /* Leave room for locals. */
838 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
841 /* Return nonzero if we can use "rts" for the function currently being
845 h8300_can_use_return_insn_p (void)
847 return (reload_completed
848 && !frame_pointer_needed
849 && get_frame_size () == 0
850 && compute_saved_regs () == 0);
853 /* Generate RTL code for the function epilogue. */
856 h8300_expand_epilogue (void)
861 HOST_WIDE_INT frame_size;
864 if (h8300_os_task_function_p (current_function_decl))
865 /* OS_Task epilogues are nearly naked -- they just have an
869 frame_size = round_frame_size (get_frame_size ());
872 /* Deallocate locals. */
873 h8300_emit_stack_adjustment (1, frame_size, false);
875 /* Pop the saved registers in descending order. */
876 saved_regs = compute_saved_regs ();
877 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
880 if (saved_regs & (1 << regno))
884 /* See how many registers we can pop at the same time. */
885 if ((TARGET_H8300SX || (regno & 3) == 3)
886 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
889 else if ((TARGET_H8300SX || (regno & 3) == 2)
890 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
893 else if ((TARGET_H8300SX || (regno & 1) == 1)
894 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
898 /* See if this pop would be the last insn before the return.
899 If so, use rte/l or rts/l instead of pop or ldm.l. */
901 && !frame_pointer_needed
903 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
906 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
910 /* Pop frame pointer if we had one. */
911 if (frame_pointer_needed)
915 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
919 emit_jump_insn (ret_rtx);
922 /* Return nonzero if the current function is an interrupt
926 h8300_current_function_interrupt_function_p (void)
928 return (h8300_interrupt_function_p (current_function_decl)
929 || h8300_monitor_function_p (current_function_decl));
932 /* Output assembly code for the start of the file. */
935 h8300_file_start (void)
937 default_file_start ();
940 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
941 else if (TARGET_H8300SX)
942 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
943 else if (TARGET_H8300S)
944 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
947 /* Output assembly language code for the end of file. */
950 h8300_file_end (void)
952 fputs ("\t.end\n", asm_out_file);
955 /* Split an add of a small constant into two adds/subs insns.
957 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
958 instead of adds/subs. */
961 split_adds_subs (enum machine_mode mode, rtx *operands)
963 HOST_WIDE_INT val = INTVAL (operands[1]);
964 rtx reg = operands[0];
965 HOST_WIDE_INT sign = 1;
966 HOST_WIDE_INT amount;
967 rtx (*gen_add) (rtx, rtx, rtx);
969 /* Force VAL to be positive so that we do not have to consider the
980 gen_add = gen_addhi3;
984 gen_add = gen_addsi3;
991 /* Try different amounts in descending order. */
992 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
996 for (; val >= amount; val -= amount)
997 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1003 /* Handle machine specific pragmas for compatibility with existing
1004 compilers for the H8/300.
1006 pragma saveall generates prologue/epilogue code which saves and
1007 restores all the registers on function entry.
1009 pragma interrupt saves and restores all registers, and exits with
1010 an rte instruction rather than an rts. A pointer to a function
1011 with this attribute may be safely used in an interrupt vector. */
1014 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1016 pragma_interrupt = 1;
1020 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1025 /* If the next function argument with MODE and TYPE is to be passed in
1026 a register, return a reg RTX for the hard register in which to pass
1027 the argument. CUM represents the state after the last argument.
1028 If the argument is to be pushed, NULL_RTX is returned.
1030 On the H8/300 all normal args are pushed, unless -mquickcall in which
1031 case the first 3 arguments are passed in registers. */
1034 h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1035 const_tree type, bool named)
1037 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1039 static const char *const hand_list[] = {
1058 rtx result = NULL_RTX;
1062 /* Never pass unnamed arguments in registers. */
1066 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1067 if (TARGET_QUICKCALL)
1070 /* If calling hand written assembler, use 4 regs of args. */
1073 const char * const *p;
1075 fname = XSTR (cum->libcall, 0);
1077 /* See if this libcall is one of the hand coded ones. */
1078 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1089 if (mode == BLKmode)
1090 size = int_size_in_bytes (type);
1092 size = GET_MODE_SIZE (mode);
1094 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1095 && cum->nbytes / UNITS_PER_WORD <= 3)
1096 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1102 /* Update the data in CUM to advance over an argument
1103 of mode MODE and data type TYPE.
1104 (TYPE is null for libcalls where that information may not be available.) */
1107 h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1108 const_tree type, bool named ATTRIBUTE_UNUSED)
1110 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1112 cum->nbytes += (mode != BLKmode
1113 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1114 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1118 /* Implements TARGET_REGISTER_MOVE_COST.
1120 Any SI register-to-register move may need to be reloaded,
1121 so inmplement h8300_register_move_cost to return > 2 so that reload never
1125 h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1126 reg_class_t from, reg_class_t to)
1128 if (from == MAC_REGS || to == MAC_REG)
1134 /* Compute the cost of an and insn. */
1137 h8300_and_costs (rtx x)
1141 if (GET_MODE (x) == QImode)
1144 if (GET_MODE (x) != HImode
1145 && GET_MODE (x) != SImode)
1149 operands[1] = XEXP (x, 0);
1150 operands[2] = XEXP (x, 1);
1152 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1155 /* Compute the cost of a shift insn. */
1158 h8300_shift_costs (rtx x)
1162 if (GET_MODE (x) != QImode
1163 && GET_MODE (x) != HImode
1164 && GET_MODE (x) != SImode)
1169 operands[2] = XEXP (x, 1);
1171 return compute_a_shift_length (NULL, operands) / 2;
1174 /* Worker function for TARGET_RTX_COSTS. */
1177 h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1178 int *total, bool speed)
1180 if (TARGET_H8300SX && outer_code == MEM)
1182 /* Estimate the number of execution states needed to calculate
1184 if (register_operand (x, VOIDmode)
1185 || GET_CODE (x) == POST_INC
1186 || GET_CODE (x) == POST_DEC
1190 *total = COSTS_N_INSNS (1);
1198 HOST_WIDE_INT n = INTVAL (x);
1202 /* Constant operands need the same number of processor
1203 states as register operands. Although we could try to
1204 use a size-based cost for !speed, the lack of
1205 of a mode makes the results very unpredictable. */
1209 if (-4 <= n || n <= 4)
1220 *total = 0 + (outer_code == SET);
1224 if (TARGET_H8300H || TARGET_H8300S)
1225 *total = 0 + (outer_code == SET);
1240 /* See comment for CONST_INT. */
1252 if (XEXP (x, 1) == const0_rtx)
1257 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1258 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1260 *total = COSTS_N_INSNS (h8300_and_costs (x));
1263 /* We say that MOD and DIV are so expensive because otherwise we'll
1264 generate some really horrible code for division of a power of two. */
1270 switch (GET_MODE (x))
1274 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1278 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1284 *total = COSTS_N_INSNS (12);
1289 switch (GET_MODE (x))
1293 *total = COSTS_N_INSNS (2);
1297 *total = COSTS_N_INSNS (5);
1303 *total = COSTS_N_INSNS (4);
1309 if (h8sx_binary_shift_operator (x, VOIDmode))
1311 *total = COSTS_N_INSNS (2);
1314 else if (h8sx_unary_shift_operator (x, VOIDmode))
1316 *total = COSTS_N_INSNS (1);
1319 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1324 if (GET_MODE (x) == HImode)
1331 *total = COSTS_N_INSNS (1);
1336 /* Documentation for the machine specific operand escapes:
1338 'E' like s but negative.
1339 'F' like t but negative.
1340 'G' constant just the negative
1341 'R' print operand as a byte:8 address if appropriate, else fall back to
1343 'S' print operand as a long word
1344 'T' print operand as a word
1345 'V' find the set bit, and print its number.
1346 'W' find the clear bit, and print its number.
1347 'X' print operand as a byte
1348 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1349 If this operand isn't a register, fall back to 'R' handling.
1351 'c' print the opcode corresponding to rtl
1352 'e' first word of 32-bit value - if reg, then least reg. if mem
1353 then least. if const then most sig word
1354 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1355 then +2. if const then least sig word
1356 'j' print operand as condition code.
1357 'k' print operand as reverse condition code.
1358 'm' convert an integer operand to a size suffix (.b, .w or .l)
1359 'o' print an integer without a leading '#'
1360 's' print as low byte of 16-bit value
1361 't' print as high byte of 16-bit value
1362 'w' print as low byte of 32-bit value
1363 'x' print as 2nd byte of 32-bit value
1364 'y' print as 3rd byte of 32-bit value
1365 'z' print as msb of 32-bit value
1368 /* Return assembly language string which identifies a comparison type. */
1371 cond_string (enum rtx_code code)
1400 /* Print operand X using operand code CODE to assembly language output file
1404 h8300_print_operand (FILE *file, rtx x, int code)
1406 /* This is used for communication between codes V,W,Z and Y. */
1412 switch (GET_CODE (x))
1415 fprintf (file, "%sl", names_big[REGNO (x)]);
1418 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1425 switch (GET_CODE (x))
1428 fprintf (file, "%sh", names_big[REGNO (x)]);
1431 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1438 gcc_assert (GET_CODE (x) == CONST_INT);
1439 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1442 if (GET_CODE (x) == REG)
1443 fprintf (file, "%s", names_extended[REGNO (x)]);
1448 if (GET_CODE (x) == REG)
1449 fprintf (file, "%s", names_big[REGNO (x)]);
1454 bitint = (INTVAL (x) & 0xffff);
1455 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1456 bitint = exact_log2 (bitint & 0xff);
1458 bitint = exact_log2 ((bitint >> 8) & 0xff);
1459 gcc_assert (bitint >= 0);
1460 fprintf (file, "#%d", bitint);
1463 bitint = ((~INTVAL (x)) & 0xffff);
1464 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1465 bitint = exact_log2 (bitint & 0xff);
1467 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1468 gcc_assert (bitint >= 0);
1469 fprintf (file, "#%d", bitint);
1473 if (GET_CODE (x) == REG)
1474 fprintf (file, "%s", byte_reg (x, 0));
1479 gcc_assert (bitint >= 0);
1480 if (GET_CODE (x) == REG)
1481 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1483 h8300_print_operand (file, x, 'R');
1487 bitint = INTVAL (x);
1488 fprintf (file, "#%d", bitint & 7);
1491 switch (GET_CODE (x))
1494 fprintf (file, "or");
1497 fprintf (file, "xor");
1500 fprintf (file, "and");
1507 switch (GET_CODE (x))
1511 fprintf (file, "%s", names_big[REGNO (x)]);
1513 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1516 h8300_print_operand (file, x, 0);
1519 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1525 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1526 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1527 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1536 switch (GET_CODE (x))
1540 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1542 fprintf (file, "%s", names_big[REGNO (x)]);
1545 x = adjust_address (x, HImode, 2);
1546 h8300_print_operand (file, x, 0);
1549 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1555 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1556 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1557 fprintf (file, "#%ld", (val & 0xffff));
1565 fputs (cond_string (GET_CODE (x)), file);
1568 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1571 gcc_assert (GET_CODE (x) == CONST_INT);
1591 h8300_print_operand_address (file, x);
1594 if (GET_CODE (x) == CONST_INT)
1595 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1597 fprintf (file, "%s", byte_reg (x, 0));
1600 if (GET_CODE (x) == CONST_INT)
1601 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1603 fprintf (file, "%s", byte_reg (x, 1));
1606 if (GET_CODE (x) == CONST_INT)
1607 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1609 fprintf (file, "%s",
1610 byte_reg (x, TARGET_H8300 ? 2 : 0));
1613 if (GET_CODE (x) == CONST_INT)
1614 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1616 fprintf (file, "%s",
1617 byte_reg (x, TARGET_H8300 ? 3 : 1));
1620 if (GET_CODE (x) == CONST_INT)
1621 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1623 fprintf (file, "%s", byte_reg (x, 0));
1626 if (GET_CODE (x) == CONST_INT)
1627 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1629 fprintf (file, "%s", byte_reg (x, 1));
1634 switch (GET_CODE (x))
1637 switch (GET_MODE (x))
1640 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1641 fprintf (file, "%s", byte_reg (x, 0));
1642 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1643 fprintf (file, "%s", names_big[REGNO (x)]);
1647 fprintf (file, "%s", names_big[REGNO (x)]);
1651 fprintf (file, "%s", names_extended[REGNO (x)]);
1660 rtx addr = XEXP (x, 0);
1662 fprintf (file, "@");
1663 output_address (addr);
1665 /* Add a length suffix to constant addresses. Although this
1666 is often unnecessary, it helps to avoid ambiguity in the
1667 syntax of mova. If we wrote an insn like:
1669 mova/w.l @(1,@foo.b),er0
1671 then .b would be considered part of the symbol name.
1672 Adding a length after foo will avoid this. */
1673 if (CONSTANT_P (addr))
1677 /* Used for mov.b and bit operations. */
1678 if (h8300_eightbit_constant_address_p (addr))
1680 fprintf (file, ":8");
1684 /* Fall through. We should not get here if we are
1685 processing bit operations on H8/300 or H8/300H
1686 because 'U' constraint does not allow bit
1687 operations on the tiny area on these machines. */
1692 if (h8300_constant_length (addr) == 2)
1693 fprintf (file, ":16");
1695 fprintf (file, ":32");
1707 fprintf (file, "#");
1708 h8300_print_operand_address (file, x);
1714 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1715 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1716 fprintf (file, "#%ld", val);
1725 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1728 h8300_print_operand_punct_valid_p (unsigned char code)
1730 return (code == '#');
1733 /* Output assembly language output for the address ADDR to FILE. */
1736 h8300_print_operand_address (FILE *file, rtx addr)
1741 switch (GET_CODE (addr))
1744 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1748 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1752 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1756 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1760 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1764 fprintf (file, "(");
1766 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1767 if (GET_CODE (index) == REG)
1770 h8300_print_operand_address (file, XEXP (addr, 1));
1771 fprintf (file, ",");
1775 h8300_print_operand_address (file, index);
1779 h8300_print_operand (file, index, 'X');
1784 h8300_print_operand (file, index, 'T');
1789 h8300_print_operand (file, index, 'S');
1793 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1798 h8300_print_operand_address (file, XEXP (addr, 0));
1799 fprintf (file, "+");
1800 h8300_print_operand_address (file, XEXP (addr, 1));
1802 fprintf (file, ")");
1807 /* Since the H8/300 only has 16-bit pointers, negative values are also
1808 those >= 32768. This happens for example with pointer minus a
1809 constant. We don't want to turn (char *p - 2) into
1810 (char *p + 65534) because loop unrolling can build upon this
1811 (IE: char *p + 131068). */
1812 int n = INTVAL (addr);
1814 n = (int) (short) n;
1815 fprintf (file, "%d", n);
1820 output_addr_const (file, addr);
1825 /* Output all insn addresses and their sizes into the assembly language
1826 output file. This is helpful for debugging whether the length attributes
1827 in the md file are correct. This is not meant to be a user selectable
1831 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1832 int num_operands ATTRIBUTE_UNUSED)
1834 /* This holds the last insn address. */
1835 static int last_insn_address = 0;
1837 const int uid = INSN_UID (insn);
1839 if (TARGET_ADDRESSES)
1841 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1842 INSN_ADDRESSES (uid) - last_insn_address);
1843 last_insn_address = INSN_ADDRESSES (uid);
1847 /* Prepare for an SI sized move. */
1850 h8300_expand_movsi (rtx operands[])
1852 rtx src = operands[1];
1853 rtx dst = operands[0];
1854 if (!reload_in_progress && !reload_completed)
1856 if (!register_operand (dst, GET_MODE (dst)))
1858 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1859 emit_move_insn (tmp, src);
1866 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1867 Frame pointer elimination is automatically handled.
1869 For the h8300, if frame pointer elimination is being done, we would like to
1870 convert ap and rp into sp, not fp.
1872 All other eliminations are valid. */
1875 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1877 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1880 /* Conditionally modify register usage based on target flags. */
1883 h8300_conditional_register_usage (void)
1886 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1889 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1890 Define the offset between two registers, one to be eliminated, and
1891 the other its replacement, at the start of a routine. */
1894 h8300_initial_elimination_offset (int from, int to)
1896 /* The number of bytes that the return address takes on the stack. */
1897 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1899 /* The number of bytes that the saved frame pointer takes on the stack. */
1900 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1902 /* The number of bytes that the saved registers, excluding the frame
1903 pointer, take on the stack. */
1904 int saved_regs_size = 0;
1906 /* The number of bytes that the locals takes on the stack. */
1907 int frame_size = round_frame_size (get_frame_size ());
1911 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1912 if (WORD_REG_USED (regno))
1913 saved_regs_size += UNITS_PER_WORD;
1915 /* Adjust saved_regs_size because the above loop took the frame
1916 pointer int account. */
1917 saved_regs_size -= fp_size;
1921 case HARD_FRAME_POINTER_REGNUM:
1924 case ARG_POINTER_REGNUM:
1925 return pc_size + fp_size;
1926 case RETURN_ADDRESS_POINTER_REGNUM:
1928 case FRAME_POINTER_REGNUM:
1929 return -saved_regs_size;
1934 case STACK_POINTER_REGNUM:
1937 case ARG_POINTER_REGNUM:
1938 return pc_size + saved_regs_size + frame_size;
1939 case RETURN_ADDRESS_POINTER_REGNUM:
1940 return saved_regs_size + frame_size;
1941 case FRAME_POINTER_REGNUM:
1953 /* Worker function for RETURN_ADDR_RTX. */
1956 h8300_return_addr_rtx (int count, rtx frame)
1961 ret = gen_rtx_MEM (Pmode,
1962 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1963 else if (flag_omit_frame_pointer)
1966 ret = gen_rtx_MEM (Pmode,
1967 memory_address (Pmode,
1968 plus_constant (frame, UNITS_PER_WORD)));
1969 set_mem_alias_set (ret, get_frame_alias_set ());
1973 /* Update the condition code from the insn. */
1976 notice_update_cc (rtx body, rtx insn)
1980 switch (get_attr_cc (insn))
1983 /* Insn does not affect CC at all. */
1987 /* Insn does not change CC, but the 0'th operand has been changed. */
1988 if (cc_status.value1 != 0
1989 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1990 cc_status.value1 = 0;
1991 if (cc_status.value2 != 0
1992 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1993 cc_status.value2 = 0;
1997 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1998 The V flag is unusable. The C flag may or may not be known but
1999 that's ok because alter_cond will change tests to use EQ/NE. */
2001 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2002 set = single_set (insn);
2003 cc_status.value1 = SET_SRC (set);
2004 if (SET_DEST (set) != cc0_rtx)
2005 cc_status.value2 = SET_DEST (set);
2009 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2010 The C flag may or may not be known but that's ok because
2011 alter_cond will change tests to use EQ/NE. */
2013 cc_status.flags |= CC_NO_CARRY;
2014 set = single_set (insn);
2015 cc_status.value1 = SET_SRC (set);
2016 if (SET_DEST (set) != cc0_rtx)
2018 /* If the destination is STRICT_LOW_PART, strip off
2020 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2021 cc_status.value2 = XEXP (SET_DEST (set), 0);
2023 cc_status.value2 = SET_DEST (set);
2028 /* The insn is a compare instruction. */
2030 cc_status.value1 = SET_SRC (body);
2034 /* Insn doesn't leave CC in a usable state. */
2040 /* Given that X occurs in an address of the form (plus X constant),
2041 return the part of X that is expected to be a register. There are
2042 four kinds of addressing mode to recognize:
2049 If SIZE is nonnull, and the address is one of the last three forms,
2050 set *SIZE to the index multiplication factor. Set it to 0 for
2051 plain @(dd,Rn) addresses.
2053 MODE is the mode of the value being accessed. It can be VOIDmode
2054 if the address is known to be valid, but its mode is unknown. */
2057 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2064 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2067 && (mode == VOIDmode
2068 || GET_MODE_CLASS (mode) == MODE_INT
2069 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2071 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2073 /* When accessing byte-sized values, the index can be
2074 a zero-extended QImode or HImode register. */
2075 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2080 /* We're looking for addresses of the form:
2083 or (mult (zero_extend X) I)
2085 where I is the size of the operand being accessed.
2086 The canonical form of the second expression is:
2088 (and (mult (subreg X) I) J)
2090 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2093 if (GET_CODE (x) == AND
2094 && GET_CODE (XEXP (x, 1)) == CONST_INT
2096 || INTVAL (XEXP (x, 1)) == 0xff * factor
2097 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2099 index = XEXP (x, 0);
2100 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2108 if (GET_CODE (index) == MULT
2109 && GET_CODE (XEXP (index, 1)) == CONST_INT
2110 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2111 return XEXP (index, 0);
2118 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2120 On the H8/300, the predecrement and postincrement address depend thus
2121 (the amount of decrement or increment being the length of the operand). */
2124 h8300_mode_dependent_address_p (const_rtx addr)
2126 if (GET_CODE (addr) == PLUS
2127 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2133 static const h8300_length_table addb_length_table =
2135 /* #xx Rs @aa @Rs @xx */
2136 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2137 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2138 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2139 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2142 static const h8300_length_table addw_length_table =
2144 /* #xx Rs @aa @Rs @xx */
2145 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2146 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2147 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2148 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2151 static const h8300_length_table addl_length_table =
2153 /* #xx Rs @aa @Rs @xx */
2154 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2155 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2156 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2157 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2160 #define logicb_length_table addb_length_table
2161 #define logicw_length_table addw_length_table
2163 static const h8300_length_table logicl_length_table =
2165 /* #xx Rs @aa @Rs @xx */
2166 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2167 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2168 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2169 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2172 static const h8300_length_table movb_length_table =
2174 /* #xx Rs @aa @Rs @xx */
2175 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2176 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2177 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2178 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2181 #define movw_length_table movb_length_table
2183 static const h8300_length_table movl_length_table =
2185 /* #xx Rs @aa @Rs @xx */
2186 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2187 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2188 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2189 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2192 /* Return the size of the given address or displacement constant. */
2195 h8300_constant_length (rtx constant)
2197 /* Check for (@d:16,Reg). */
2198 if (GET_CODE (constant) == CONST_INT
2199 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2202 /* Check for (@d:16,Reg) in cases where the displacement is
2203 an absolute address. */
2204 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2210 /* Return the size of a displacement field in address ADDR, which should
2211 have the form (plus X constant). SIZE is the number of bytes being
2215 h8300_displacement_length (rtx addr, int size)
2219 offset = XEXP (addr, 1);
2221 /* Check for @(d:2,Reg). */
2222 if (register_operand (XEXP (addr, 0), VOIDmode)
2223 && GET_CODE (offset) == CONST_INT
2224 && (INTVAL (offset) == size
2225 || INTVAL (offset) == size * 2
2226 || INTVAL (offset) == size * 3))
2229 return h8300_constant_length (offset);
2232 /* Store the class of operand OP in *OPCLASS and return the length of any
2233 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2234 can be null if only the length is needed. */
2237 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2239 enum h8300_operand_class dummy;
2244 if (CONSTANT_P (op))
2246 *opclass = H8OP_IMMEDIATE;
2248 /* Byte-sized immediates are stored in the opcode fields. */
2252 /* If this is a 32-bit instruction, see whether the constant
2253 will fit into a 16-bit immediate field. */
2256 && GET_CODE (op) == CONST_INT
2257 && IN_RANGE (INTVAL (op), 0, 0xffff))
2262 else if (GET_CODE (op) == MEM)
2265 if (CONSTANT_P (op))
2267 *opclass = H8OP_MEM_ABSOLUTE;
2268 return h8300_constant_length (op);
2270 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2272 *opclass = H8OP_MEM_COMPLEX;
2273 return h8300_displacement_length (op, size);
2275 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2277 *opclass = H8OP_MEM_COMPLEX;
2280 else if (register_operand (op, VOIDmode))
2282 *opclass = H8OP_MEM_BASE;
2286 gcc_assert (register_operand (op, VOIDmode));
2287 *opclass = H8OP_REGISTER;
2291 /* Return the length of the instruction described by TABLE given that
2292 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2293 and OP2 must be an h8300_src_operand. */
2296 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2298 enum h8300_operand_class op1_class, op2_class;
2299 unsigned int size, immediate_length;
2301 size = GET_MODE_SIZE (GET_MODE (op1));
2302 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2303 + h8300_classify_operand (op2, size, &op2_class));
2304 return immediate_length + (*table)[op1_class - 1][op2_class];
2307 /* Return the length of a unary instruction such as neg or not given that
2308 its operand is OP. */
2311 h8300_unary_length (rtx op)
2313 enum h8300_operand_class opclass;
2314 unsigned int size, operand_length;
2316 size = GET_MODE_SIZE (GET_MODE (op));
2317 operand_length = h8300_classify_operand (op, size, &opclass);
2324 return (size == 4 ? 6 : 4);
2326 case H8OP_MEM_ABSOLUTE:
2327 return operand_length + (size == 4 ? 6 : 4);
2329 case H8OP_MEM_COMPLEX:
2330 return operand_length + 6;
2337 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2340 h8300_short_immediate_length (rtx op)
2342 enum h8300_operand_class opclass;
2343 unsigned int size, operand_length;
2345 size = GET_MODE_SIZE (GET_MODE (op));
2346 operand_length = h8300_classify_operand (op, size, &opclass);
2354 case H8OP_MEM_ABSOLUTE:
2355 case H8OP_MEM_COMPLEX:
2356 return 4 + operand_length;
2363 /* Likewise bitfield load and store instructions. */
2366 h8300_bitfield_length (rtx op, rtx op2)
2368 enum h8300_operand_class opclass;
2369 unsigned int size, operand_length;
2371 if (GET_CODE (op) == REG)
2373 gcc_assert (GET_CODE (op) != REG);
2375 size = GET_MODE_SIZE (GET_MODE (op));
2376 operand_length = h8300_classify_operand (op, size, &opclass);
2381 case H8OP_MEM_ABSOLUTE:
2382 case H8OP_MEM_COMPLEX:
2383 return 4 + operand_length;
2390 /* Calculate the length of general binary instruction INSN using TABLE. */
2393 h8300_binary_length (rtx insn, const h8300_length_table *table)
2397 set = single_set (insn);
2400 if (BINARY_P (SET_SRC (set)))
2401 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2402 XEXP (SET_SRC (set), 1), table);
2405 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2406 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2407 XEXP (XEXP (SET_SRC (set), 1), 1),
2412 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2413 memory reference and either (1) it has the form @(d:16,Rn) or
2414 (2) its address has the code given by INC_CODE. */
2417 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2422 if (GET_CODE (op) != MEM)
2425 addr = XEXP (op, 0);
2426 size = GET_MODE_SIZE (GET_MODE (op));
2427 if (size != 1 && size != 2)
2430 return (GET_CODE (addr) == inc_code
2431 || (GET_CODE (addr) == PLUS
2432 && GET_CODE (XEXP (addr, 0)) == REG
2433 && h8300_displacement_length (addr, size) == 2));
2436 /* Calculate the length of move instruction INSN using the given length
2437 table. Although the tables are correct for most cases, there is some
2438 irregularity in the length of mov.b and mov.w. The following forms:
2445 are two bytes shorter than most other "mov Rs, @complex" or
2446 "mov @complex,Rd" combinations. */
2449 h8300_move_length (rtx *operands, const h8300_length_table *table)
2453 size = h8300_length_from_table (operands[0], operands[1], table);
2454 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2456 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2461 /* Return the length of a mova instruction with the given operands.
2462 DEST is the register destination, SRC is the source address and
2463 OFFSET is the 16-bit or 32-bit displacement. */
2466 h8300_mova_length (rtx dest, rtx src, rtx offset)
2471 + h8300_constant_length (offset)
2472 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2473 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2478 /* Compute the length of INSN based on its length_table attribute.
2479 OPERANDS is the array of its operands. */
2482 h8300_insn_length_from_table (rtx insn, rtx * operands)
2484 switch (get_attr_length_table (insn))
2486 case LENGTH_TABLE_NONE:
2489 case LENGTH_TABLE_ADDB:
2490 return h8300_binary_length (insn, &addb_length_table);
2492 case LENGTH_TABLE_ADDW:
2493 return h8300_binary_length (insn, &addw_length_table);
2495 case LENGTH_TABLE_ADDL:
2496 return h8300_binary_length (insn, &addl_length_table);
2498 case LENGTH_TABLE_LOGICB:
2499 return h8300_binary_length (insn, &logicb_length_table);
2501 case LENGTH_TABLE_MOVB:
2502 return h8300_move_length (operands, &movb_length_table);
2504 case LENGTH_TABLE_MOVW:
2505 return h8300_move_length (operands, &movw_length_table);
2507 case LENGTH_TABLE_MOVL:
2508 return h8300_move_length (operands, &movl_length_table);
2510 case LENGTH_TABLE_MOVA:
2511 return h8300_mova_length (operands[0], operands[1], operands[2]);
2513 case LENGTH_TABLE_MOVA_ZERO:
2514 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2516 case LENGTH_TABLE_UNARY:
2517 return h8300_unary_length (operands[0]);
2519 case LENGTH_TABLE_MOV_IMM4:
2520 return 2 + h8300_classify_operand (operands[0], 0, 0);
2522 case LENGTH_TABLE_SHORT_IMMEDIATE:
2523 return h8300_short_immediate_length (operands[0]);
2525 case LENGTH_TABLE_BITFIELD:
2526 return h8300_bitfield_length (operands[0], operands[1]);
2528 case LENGTH_TABLE_BITBRANCH:
2529 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2536 /* Return true if LHS and RHS are memory references that can be mapped
2537 to the same h8sx assembly operand. LHS appears as the destination of
2538 an instruction and RHS appears as a source.
2540 Three cases are allowed:
2542 - RHS is @+Rn or @-Rn, LHS is @Rn
2543 - RHS is @Rn, LHS is @Rn+ or @Rn-
2544 - RHS and LHS have the same address and neither has side effects. */
2547 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2549 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2551 rhs = XEXP (rhs, 0);
2552 lhs = XEXP (lhs, 0);
2554 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2555 return rtx_equal_p (XEXP (rhs, 0), lhs);
2557 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2558 return rtx_equal_p (rhs, XEXP (lhs, 0));
2560 if (rtx_equal_p (rhs, lhs))
2566 /* Return true if OPERANDS[1] can be mapped to the same assembly
2567 operand as OPERANDS[0]. */
2570 h8300_operands_match_p (rtx *operands)
2572 if (register_operand (operands[0], VOIDmode)
2573 && register_operand (operands[1], VOIDmode))
2576 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2582 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2583 region DEST. The two regions do not overlap and have the common
2584 alignment given by ALIGNMENT. Return true on success.
2586 Using movmd for variable-length moves seems to involve some
2587 complex trade-offs. For instance:
2589 - Preparing for a movmd instruction is similar to preparing
2590 for a memcpy. The main difference is that the arguments
2591 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2593 - Since movmd clobbers the frame pointer, we need to save
2594 and restore it somehow when frame_pointer_needed. This can
2595 sometimes make movmd sequences longer than calls to memcpy().
2597 - The counter register is 16 bits, so the instruction is only
2598 suitable for variable-length moves when sizeof (size_t) == 2.
2599 That's only true in normal mode.
2601 - We will often lack static alignment information. Falling back
2602 on movmd.b would likely be slower than calling memcpy(), at least
2605 This function therefore only uses movmd when the length is a
2606 known constant, and only then if -fomit-frame-pointer is in
2607 effect or if we're not optimizing for size.
2609 At the moment the function uses movmd for all in-range constants,
2610 but it might be better to fall back on memcpy() for large moves
2611 if ALIGNMENT == 1. */
2614 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2615 HOST_WIDE_INT alignment)
2617 if (!flag_omit_frame_pointer && optimize_size)
2620 if (GET_CODE (length) == CONST_INT)
2622 rtx dest_reg, src_reg, first_dest, first_src;
2626 /* Use movmd.l if the alignment allows it, otherwise fall back
2628 factor = (alignment >= 2 ? 4 : 1);
2630 /* Make sure the length is within range. We can handle counter
2631 values up to 65536, although HImode truncation will make
2632 the count appear negative in rtl dumps. */
2633 n = INTVAL (length);
2634 if (n <= 0 || n / factor > 65536)
2637 /* Create temporary registers for the source and destination
2638 pointers. Initialize them to the start of each region. */
2639 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2640 src_reg = copy_addr_to_reg (XEXP (src, 0));
2642 /* Create references to the movmd source and destination blocks. */
2643 first_dest = replace_equiv_address (dest, dest_reg);
2644 first_src = replace_equiv_address (src, src_reg);
2646 set_mem_size (first_dest, n & -factor);
2647 set_mem_size (first_src, n & -factor);
2649 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2650 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2652 if ((n & -factor) != n)
2654 /* Move SRC and DEST past the region we just copied.
2655 This is done to update the memory attributes. */
2656 dest = adjust_address (dest, BLKmode, n & -factor);
2657 src = adjust_address (src, BLKmode, n & -factor);
2659 /* Replace the addresses with the source and destination
2660 registers, which movmd has left with the right values. */
2661 dest = replace_equiv_address (dest, dest_reg);
2662 src = replace_equiv_address (src, src_reg);
2664 /* Mop up the left-over bytes. */
2666 emit_move_insn (adjust_address (dest, HImode, 0),
2667 adjust_address (src, HImode, 0));
2669 emit_move_insn (adjust_address (dest, QImode, n & 2),
2670 adjust_address (src, QImode, n & 2));
2677 /* Move ADDR into er6 after pushing its old value onto the stack. */
2680 h8300_swap_into_er6 (rtx addr)
2682 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2683 if (frame_pointer_needed)
2684 add_reg_note (insn, REG_CFA_DEF_CFA,
2685 plus_constant (gen_rtx_MEM (Pmode, stack_pointer_rtx),
2686 2 * UNITS_PER_WORD));
2688 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2689 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2690 plus_constant (stack_pointer_rtx, 4)));
2692 emit_move_insn (hard_frame_pointer_rtx, addr);
2693 if (REGNO (addr) == SP_REG)
2694 emit_move_insn (hard_frame_pointer_rtx,
2695 plus_constant (hard_frame_pointer_rtx,
2696 GET_MODE_SIZE (word_mode)));
2699 /* Move the current value of er6 into ADDR and pop its old value
2703 h8300_swap_out_of_er6 (rtx addr)
2707 if (REGNO (addr) != SP_REG)
2708 emit_move_insn (addr, hard_frame_pointer_rtx);
2710 insn = pop (HARD_FRAME_POINTER_REGNUM);
2711 RTX_FRAME_RELATED_P (insn) = 1;
2712 if (frame_pointer_needed)
2713 add_reg_note (insn, REG_CFA_DEF_CFA,
2714 plus_constant (hard_frame_pointer_rtx, 2 * UNITS_PER_WORD));
2716 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2717 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2718 plus_constant (stack_pointer_rtx, -4)));
2721 /* Return the length of mov instruction. */
2724 compute_mov_length (rtx *operands)
2726 /* If the mov instruction involves a memory operand, we compute the
2727 length, assuming the largest addressing mode is used, and then
2728 adjust later in the function. Otherwise, we compute and return
2729 the exact length in one step. */
2730 enum machine_mode mode = GET_MODE (operands[0]);
2731 rtx dest = operands[0];
2732 rtx src = operands[1];
2735 if (GET_CODE (src) == MEM)
2736 addr = XEXP (src, 0);
2737 else if (GET_CODE (dest) == MEM)
2738 addr = XEXP (dest, 0);
2744 unsigned int base_length;
2749 if (addr == NULL_RTX)
2752 /* The eightbit addressing is available only in QImode, so
2753 go ahead and take care of it. */
2754 if (h8300_eightbit_constant_address_p (addr))
2761 if (addr == NULL_RTX)
2766 if (src == const0_rtx)
2776 if (addr == NULL_RTX)
2781 if (GET_CODE (src) == CONST_INT)
2783 if (src == const0_rtx)
2786 if ((INTVAL (src) & 0xffff) == 0)
2789 if ((INTVAL (src) & 0xffff) == 0)
2792 if ((INTVAL (src) & 0xffff)
2793 == ((INTVAL (src) >> 16) & 0xffff))
2803 if (addr == NULL_RTX)
2808 if (satisfies_constraint_G (src))
2821 /* Adjust the length based on the addressing mode used.
2822 Specifically, we subtract the difference between the actual
2823 length and the longest one, which is @(d:16,Rs). For SImode
2824 and SFmode, we double the adjustment because two mov.w are
2825 used to do the job. */
2827 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2828 if (GET_CODE (addr) == PRE_DEC
2829 || GET_CODE (addr) == POST_INC)
2831 if (mode == QImode || mode == HImode)
2832 return base_length - 2;
2834 /* In SImode and SFmode, we use two mov.w instructions, so
2835 double the adjustment. */
2836 return base_length - 4;
2839 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2840 in SImode and SFmode, the second mov.w involves an address
2841 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2843 if (GET_CODE (addr) == REG)
2844 return base_length - 2;
2850 unsigned int base_length;
2855 if (addr == NULL_RTX)
2858 /* The eightbit addressing is available only in QImode, so
2859 go ahead and take care of it. */
2860 if (h8300_eightbit_constant_address_p (addr))
2867 if (addr == NULL_RTX)
2872 if (src == const0_rtx)
2882 if (addr == NULL_RTX)
2886 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2892 if (GET_CODE (src) == CONST_INT)
2894 int val = INTVAL (src);
2899 if (val == (val & 0x00ff) || val == (val & 0xff00))
2902 switch (val & 0xffffffff)
2923 if (addr == NULL_RTX)
2928 if (satisfies_constraint_G (src))
2941 /* Adjust the length based on the addressing mode used.
2942 Specifically, we subtract the difference between the actual
2943 length and the longest one, which is @(d:24,ERs). */
2945 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2946 if (GET_CODE (addr) == PRE_DEC
2947 || GET_CODE (addr) == POST_INC)
2948 return base_length - 6;
2950 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2951 if (GET_CODE (addr) == REG)
2952 return base_length - 6;
2954 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2956 if (GET_CODE (addr) == PLUS
2957 && GET_CODE (XEXP (addr, 0)) == REG
2958 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2959 && INTVAL (XEXP (addr, 1)) > -32768
2960 && INTVAL (XEXP (addr, 1)) < 32767)
2961 return base_length - 4;
2963 /* @aa:16 is 4 bytes shorter than the longest. */
2964 if (h8300_tiny_constant_address_p (addr))
2965 return base_length - 4;
2967 /* @aa:24 is 2 bytes shorter than the longest. */
2968 if (CONSTANT_P (addr))
2969 return base_length - 2;
2975 /* Output an addition insn. */
2978 output_plussi (rtx *operands)
2980 enum machine_mode mode = GET_MODE (operands[0]);
2982 gcc_assert (mode == SImode);
2986 if (GET_CODE (operands[2]) == REG)
2987 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2989 if (GET_CODE (operands[2]) == CONST_INT)
2991 HOST_WIDE_INT n = INTVAL (operands[2]);
2993 if ((n & 0xffffff) == 0)
2994 return "add\t%z2,%z0";
2995 if ((n & 0xffff) == 0)
2996 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2997 if ((n & 0xff) == 0)
2998 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3001 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3005 if (GET_CODE (operands[2]) == CONST_INT
3006 && register_operand (operands[1], VOIDmode))
3008 HOST_WIDE_INT intval = INTVAL (operands[2]);
3010 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3011 return "add.l\t%S2,%S0";
3012 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3013 return "sub.l\t%G2,%S0";
3015 /* See if we can finish with 2 bytes. */
3017 switch ((unsigned int) intval & 0xffffffff)
3022 return "adds\t%2,%S0";
3027 return "subs\t%G2,%S0";
3031 operands[2] = GEN_INT (intval >> 16);
3032 return "inc.w\t%2,%e0";
3036 operands[2] = GEN_INT (intval >> 16);
3037 return "dec.w\t%G2,%e0";
3040 /* See if we can finish with 4 bytes. */
3041 if ((intval & 0xffff) == 0)
3043 operands[2] = GEN_INT (intval >> 16);
3044 return "add.w\t%2,%e0";
3048 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3050 operands[2] = GEN_INT (-INTVAL (operands[2]));
3051 return "sub.l\t%S2,%S0";
3053 return "add.l\t%S2,%S0";
3057 /* ??? It would be much easier to add the h8sx stuff if a single function
3058 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3059 /* Compute the length of an addition insn. */
3062 compute_plussi_length (rtx *operands)
3064 enum machine_mode mode = GET_MODE (operands[0]);
3066 gcc_assert (mode == SImode);
3070 if (GET_CODE (operands[2]) == REG)
3073 if (GET_CODE (operands[2]) == CONST_INT)
3075 HOST_WIDE_INT n = INTVAL (operands[2]);
3077 if ((n & 0xffffff) == 0)
3079 if ((n & 0xffff) == 0)
3081 if ((n & 0xff) == 0)
3089 if (GET_CODE (operands[2]) == CONST_INT
3090 && register_operand (operands[1], VOIDmode))
3092 HOST_WIDE_INT intval = INTVAL (operands[2]);
3094 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3096 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3099 /* See if we can finish with 2 bytes. */
3101 switch ((unsigned int) intval & 0xffffffff)
3122 /* See if we can finish with 4 bytes. */
3123 if ((intval & 0xffff) == 0)
3127 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3128 return h8300_length_from_table (operands[0],
3129 GEN_INT (-INTVAL (operands[2])),
3130 &addl_length_table);
3132 return h8300_length_from_table (operands[0], operands[2],
3133 &addl_length_table);
3138 /* Compute which flag bits are valid after an addition insn. */
3141 compute_plussi_cc (rtx *operands)
3143 enum machine_mode mode = GET_MODE (operands[0]);
3145 gcc_assert (mode == SImode);
3153 if (GET_CODE (operands[2]) == CONST_INT
3154 && register_operand (operands[1], VOIDmode))
3156 HOST_WIDE_INT intval = INTVAL (operands[2]);
3158 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3160 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3163 /* See if we can finish with 2 bytes. */
3165 switch ((unsigned int) intval & 0xffffffff)
3170 return CC_NONE_0HIT;
3175 return CC_NONE_0HIT;
3186 /* See if we can finish with 4 bytes. */
3187 if ((intval & 0xffff) == 0)
3195 /* Output a logical insn. */
3198 output_logical_op (enum machine_mode mode, rtx *operands)
3200 /* Figure out the logical op that we need to perform. */
3201 enum rtx_code code = GET_CODE (operands[3]);
3202 /* Pretend that every byte is affected if both operands are registers. */
3203 const unsigned HOST_WIDE_INT intval =
3204 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3205 /* Always use the full instruction if the
3206 first operand is in memory. It is better
3207 to use define_splits to generate the shorter
3208 sequence where valid. */
3209 && register_operand (operands[1], VOIDmode)
3210 ? INTVAL (operands[2]) : 0x55555555);
3211 /* The determinant of the algorithm. If we perform an AND, 0
3212 affects a bit. Otherwise, 1 affects a bit. */
3213 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3214 /* Break up DET into pieces. */
3215 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3216 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3217 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3218 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3219 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3220 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3221 int lower_half_easy_p = 0;
3222 int upper_half_easy_p = 0;
3223 /* The name of an insn. */
3245 /* First, see if we can finish with one insn. */
3246 if ((TARGET_H8300H || TARGET_H8300S)
3250 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3251 output_asm_insn (insn_buf, operands);
3255 /* Take care of the lower byte. */
3258 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3259 output_asm_insn (insn_buf, operands);
3261 /* Take care of the upper byte. */
3264 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3265 output_asm_insn (insn_buf, operands);
3270 if (TARGET_H8300H || TARGET_H8300S)
3272 /* Determine if the lower half can be taken care of in no more
3274 lower_half_easy_p = (b0 == 0
3276 || (code != IOR && w0 == 0xffff));
3278 /* Determine if the upper half can be taken care of in no more
3280 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3281 || (code == AND && w1 == 0xff00));
3284 /* Check if doing everything with one insn is no worse than
3285 using multiple insns. */
3286 if ((TARGET_H8300H || TARGET_H8300S)
3287 && w0 != 0 && w1 != 0
3288 && !(lower_half_easy_p && upper_half_easy_p)
3289 && !(code == IOR && w1 == 0xffff
3290 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3292 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3293 output_asm_insn (insn_buf, operands);
3297 /* Take care of the lower and upper words individually. For
3298 each word, we try different methods in the order of
3300 1) the special insn (in case of AND or XOR),
3301 2) the word-wise insn, and
3302 3) The byte-wise insn. */
3304 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3305 output_asm_insn ((code == AND)
3306 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3308 else if ((TARGET_H8300H || TARGET_H8300S)
3312 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3313 output_asm_insn (insn_buf, operands);
3319 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3320 output_asm_insn (insn_buf, operands);
3324 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3325 output_asm_insn (insn_buf, operands);
3330 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3331 output_asm_insn ((code == AND)
3332 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3334 else if ((TARGET_H8300H || TARGET_H8300S)
3337 && (w0 & 0x8000) != 0)
3339 output_asm_insn ("exts.l\t%S0", operands);
3341 else if ((TARGET_H8300H || TARGET_H8300S)
3345 output_asm_insn ("extu.w\t%e0", operands);
3347 else if (TARGET_H8300H || TARGET_H8300S)
3351 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3352 output_asm_insn (insn_buf, operands);
3359 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3360 output_asm_insn (insn_buf, operands);
3364 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3365 output_asm_insn (insn_buf, operands);
3376 /* Compute the length of a logical insn. */
3379 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3381 /* Figure out the logical op that we need to perform. */
3382 enum rtx_code code = GET_CODE (operands[3]);
3383 /* Pretend that every byte is affected if both operands are registers. */
3384 const unsigned HOST_WIDE_INT intval =
3385 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3386 /* Always use the full instruction if the
3387 first operand is in memory. It is better
3388 to use define_splits to generate the shorter
3389 sequence where valid. */
3390 && register_operand (operands[1], VOIDmode)
3391 ? INTVAL (operands[2]) : 0x55555555);
3392 /* The determinant of the algorithm. If we perform an AND, 0
3393 affects a bit. Otherwise, 1 affects a bit. */
3394 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3395 /* Break up DET into pieces. */
3396 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3397 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3398 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3399 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3400 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3401 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3402 int lower_half_easy_p = 0;
3403 int upper_half_easy_p = 0;
3405 unsigned int length = 0;
3410 /* First, see if we can finish with one insn. */
3411 if ((TARGET_H8300H || TARGET_H8300S)
3415 length = h8300_length_from_table (operands[1], operands[2],
3416 &logicw_length_table);
3420 /* Take care of the lower byte. */
3424 /* Take care of the upper byte. */
3430 if (TARGET_H8300H || TARGET_H8300S)
3432 /* Determine if the lower half can be taken care of in no more
3434 lower_half_easy_p = (b0 == 0
3436 || (code != IOR && w0 == 0xffff));
3438 /* Determine if the upper half can be taken care of in no more
3440 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3441 || (code == AND && w1 == 0xff00));
3444 /* Check if doing everything with one insn is no worse than
3445 using multiple insns. */
3446 if ((TARGET_H8300H || TARGET_H8300S)
3447 && w0 != 0 && w1 != 0
3448 && !(lower_half_easy_p && upper_half_easy_p)
3449 && !(code == IOR && w1 == 0xffff
3450 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3452 length = h8300_length_from_table (operands[1], operands[2],
3453 &logicl_length_table);
3457 /* Take care of the lower and upper words individually. For
3458 each word, we try different methods in the order of
3460 1) the special insn (in case of AND or XOR),
3461 2) the word-wise insn, and
3462 3) The byte-wise insn. */
3464 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3468 else if ((TARGET_H8300H || TARGET_H8300S)
3484 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3488 else if ((TARGET_H8300H || TARGET_H8300S)
3491 && (w0 & 0x8000) != 0)
3495 else if ((TARGET_H8300H || TARGET_H8300S)
3501 else if (TARGET_H8300H || TARGET_H8300S)
3522 /* Compute which flag bits are valid after a logical insn. */
3525 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3527 /* Figure out the logical op that we need to perform. */
3528 enum rtx_code code = GET_CODE (operands[3]);
3529 /* Pretend that every byte is affected if both operands are registers. */
3530 const unsigned HOST_WIDE_INT intval =
3531 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3532 /* Always use the full instruction if the
3533 first operand is in memory. It is better
3534 to use define_splits to generate the shorter
3535 sequence where valid. */
3536 && register_operand (operands[1], VOIDmode)
3537 ? INTVAL (operands[2]) : 0x55555555);
3538 /* The determinant of the algorithm. If we perform an AND, 0
3539 affects a bit. Otherwise, 1 affects a bit. */
3540 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3541 /* Break up DET into pieces. */
3542 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3543 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3544 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3545 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3546 int lower_half_easy_p = 0;
3547 int upper_half_easy_p = 0;
3548 /* Condition code. */
3549 enum attr_cc cc = CC_CLOBBER;
3554 /* First, see if we can finish with one insn. */
3555 if ((TARGET_H8300H || TARGET_H8300S)
3563 if (TARGET_H8300H || TARGET_H8300S)
3565 /* Determine if the lower half can be taken care of in no more
3567 lower_half_easy_p = (b0 == 0
3569 || (code != IOR && w0 == 0xffff));
3571 /* Determine if the upper half can be taken care of in no more
3573 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3574 || (code == AND && w1 == 0xff00));
3577 /* Check if doing everything with one insn is no worse than
3578 using multiple insns. */
3579 if ((TARGET_H8300H || TARGET_H8300S)
3580 && w0 != 0 && w1 != 0
3581 && !(lower_half_easy_p && upper_half_easy_p)
3582 && !(code == IOR && w1 == 0xffff
3583 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3589 if ((TARGET_H8300H || TARGET_H8300S)
3592 && (w0 & 0x8000) != 0)
3604 /* Expand a conditional branch. */
3607 h8300_expand_branch (rtx operands[])
3609 enum rtx_code code = GET_CODE (operands[0]);
3610 rtx op0 = operands[1];
3611 rtx op1 = operands[2];
3612 rtx label = operands[3];
3615 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3616 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3618 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3619 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3620 gen_rtx_LABEL_REF (VOIDmode, label),
3622 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3626 /* Expand a conditional store. */
3629 h8300_expand_store (rtx operands[])
3631 rtx dest = operands[0];
3632 enum rtx_code code = GET_CODE (operands[1]);
3633 rtx op0 = operands[2];
3634 rtx op1 = operands[3];
3637 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3638 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3640 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3641 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3646 We devote a fair bit of code to getting efficient shifts since we
3647 can only shift one bit at a time on the H8/300 and H8/300H and only
3648 one or two bits at a time on the H8S.
3650 All shift code falls into one of the following ways of
3653 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3654 when a straight line shift is about the same size or smaller than
3657 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3658 off the bits we don't need. This is used when only a few of the
3659 bits in the original value will survive in the shifted value.
3661 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3662 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3663 shifts can be added if the shift count is slightly more than 8 or
3664 16. This case also includes other oddballs that are not worth
3667 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3669 For each shift count, we try to use code that has no trade-off
3670 between code size and speed whenever possible.
3672 If the trade-off is unavoidable, we try to be reasonable.
3673 Specifically, the fastest version is one instruction longer than
3674 the shortest version, we take the fastest version. We also provide
3675 the use a way to switch back to the shortest version with -Os.
3677 For the details of the shift algorithms for various shift counts,
3678 refer to shift_alg_[qhs]i. */
3680 /* Classify a shift with the given mode and code. OP is the shift amount. */
3682 enum h8sx_shift_type
3683 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3685 if (!TARGET_H8300SX)
3686 return H8SX_SHIFT_NONE;
3692 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3693 if (GET_CODE (op) != CONST_INT)
3694 return H8SX_SHIFT_BINARY;
3696 /* Reject out-of-range shift amounts. */
3697 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3698 return H8SX_SHIFT_NONE;
3700 /* Power-of-2 shifts are effectively unary operations. */
3701 if (exact_log2 (INTVAL (op)) >= 0)
3702 return H8SX_SHIFT_UNARY;
3704 return H8SX_SHIFT_BINARY;
3707 if (op == const1_rtx || op == const2_rtx)
3708 return H8SX_SHIFT_UNARY;
3709 return H8SX_SHIFT_NONE;
3712 if (GET_CODE (op) == CONST_INT
3713 && (INTVAL (op) == 1
3715 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3716 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3717 return H8SX_SHIFT_UNARY;
3718 return H8SX_SHIFT_NONE;
3721 return H8SX_SHIFT_NONE;
3725 /* Return the asm template for a single h8sx shift instruction.
3726 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3727 is the source and OPERANDS[3] is the shift. SUFFIX is the
3728 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3729 prefix for the destination operand. */
3732 output_h8sx_shift (rtx *operands, int suffix, int optype)
3734 static char buffer[16];
3737 switch (GET_CODE (operands[3]))
3753 if (INTVAL (operands[2]) > 2)
3755 /* This is really a right rotate. */
3756 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3757 - INTVAL (operands[2]));
3765 if (operands[2] == const1_rtx)
3766 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3768 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3772 /* Emit code to do shifts. */
3775 expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
3777 switch (h8sx_classify_shift (mode, code, operands[2]))
3779 case H8SX_SHIFT_BINARY:
3780 operands[1] = force_reg (mode, operands[1]);
3783 case H8SX_SHIFT_UNARY:
3786 case H8SX_SHIFT_NONE:
3790 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3792 /* Need a loop to get all the bits we want - we generate the
3793 code at emit time, but need to allocate a scratch reg now. */
3795 emit_insn (gen_rtx_PARALLEL
3798 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3799 gen_rtx_fmt_ee (code, mode,
3800 copy_rtx (operands[0]), operands[2])),
3801 gen_rtx_CLOBBER (VOIDmode,
3802 gen_rtx_SCRATCH (QImode)))));
3806 /* Symbols of the various modes which can be used as indices. */
3810 QIshift, HIshift, SIshift
3813 /* For single bit shift insns, record assembler and what bits of the
3814 condition code are valid afterwards (represented as various CC_FOO
3815 bits, 0 means CC isn't left in a usable state). */
3819 const char *const assembler;
3820 const enum attr_cc cc_valid;
3823 /* Assembler instruction shift table.
3825 These tables are used to look up the basic shifts.
3826 They are indexed by cpu, shift_type, and mode. */
3828 static const struct shift_insn shift_one[2][3][3] =
3834 { "shll\t%X0", CC_SET_ZNV },
3835 { "add.w\t%T0,%T0", CC_SET_ZN },
3836 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3838 /* SHIFT_LSHIFTRT */
3840 { "shlr\t%X0", CC_SET_ZNV },
3841 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3842 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3844 /* SHIFT_ASHIFTRT */
3846 { "shar\t%X0", CC_SET_ZNV },
3847 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3848 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3855 { "shll.b\t%X0", CC_SET_ZNV },
3856 { "shll.w\t%T0", CC_SET_ZNV },
3857 { "shll.l\t%S0", CC_SET_ZNV }
3859 /* SHIFT_LSHIFTRT */
3861 { "shlr.b\t%X0", CC_SET_ZNV },
3862 { "shlr.w\t%T0", CC_SET_ZNV },
3863 { "shlr.l\t%S0", CC_SET_ZNV }
3865 /* SHIFT_ASHIFTRT */
3867 { "shar.b\t%X0", CC_SET_ZNV },
3868 { "shar.w\t%T0", CC_SET_ZNV },
3869 { "shar.l\t%S0", CC_SET_ZNV }
3874 static const struct shift_insn shift_two[3][3] =
3878 { "shll.b\t#2,%X0", CC_SET_ZNV },
3879 { "shll.w\t#2,%T0", CC_SET_ZNV },
3880 { "shll.l\t#2,%S0", CC_SET_ZNV }
3882 /* SHIFT_LSHIFTRT */
3884 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3885 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3886 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3888 /* SHIFT_ASHIFTRT */
3890 { "shar.b\t#2,%X0", CC_SET_ZNV },
3891 { "shar.w\t#2,%T0", CC_SET_ZNV },
3892 { "shar.l\t#2,%S0", CC_SET_ZNV }
3896 /* Rotates are organized by which shift they'll be used in implementing.
3897 There's no need to record whether the cc is valid afterwards because
3898 it is the AND insn that will decide this. */
3900 static const char *const rotate_one[2][3][3] =
3907 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3910 /* SHIFT_LSHIFTRT */
3913 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3916 /* SHIFT_ASHIFTRT */
3919 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3931 /* SHIFT_LSHIFTRT */
3937 /* SHIFT_ASHIFTRT */
3946 static const char *const rotate_two[3][3] =
3954 /* SHIFT_LSHIFTRT */
3960 /* SHIFT_ASHIFTRT */
3969 /* Shift algorithm. */
3972 /* The number of bits to be shifted by shift1 and shift2. Valid
3973 when ALG is SHIFT_SPECIAL. */
3974 unsigned int remainder;
3976 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3977 const char *special;
3979 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3980 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3983 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3984 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3987 /* CC status for SHIFT_INLINE. */
3988 enum attr_cc cc_inline;
3990 /* CC status for SHIFT_SPECIAL. */
3991 enum attr_cc cc_special;
3994 static void get_shift_alg (enum shift_type,
3995 enum shift_mode, unsigned int,
3996 struct shift_info *);
3998 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3999 best algorithm for doing the shift. The assembler code is stored
4000 in the pointers in INFO. We achieve the maximum efficiency in most
4001 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4002 SImode in particular have a lot of room to optimize.
4004 We first determine the strategy of the shift algorithm by a table
4005 lookup. If that tells us to use a hand crafted assembly code, we
4006 go into the big switch statement to find what that is. Otherwise,
4007 we resort to a generic way, such as inlining. In either case, the
4008 result is returned through INFO. */
4011 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4012 unsigned int count, struct shift_info *info)
4016 /* Find the target CPU. */
4019 else if (TARGET_H8300H)
4024 /* Find the shift algorithm. */
4025 info->alg = SHIFT_LOOP;
4029 if (count < GET_MODE_BITSIZE (QImode))
4030 info->alg = shift_alg_qi[cpu][shift_type][count];
4034 if (count < GET_MODE_BITSIZE (HImode))
4035 info->alg = shift_alg_hi[cpu][shift_type][count];
4039 if (count < GET_MODE_BITSIZE (SImode))
4040 info->alg = shift_alg_si[cpu][shift_type][count];
4047 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4051 info->remainder = count;
4055 /* It is up to the caller to know that looping clobbers cc. */
4056 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4057 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4058 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4062 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4063 info->shift2 = rotate_two[shift_type][shift_mode];
4064 info->cc_inline = CC_CLOBBER;
4068 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4069 info->remainder = 0;
4070 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4071 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4072 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4073 info->cc_special = CC_CLOBBER;
4077 /* Here we only deal with SHIFT_SPECIAL. */
4081 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4082 through the entire value. */
4083 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4084 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4094 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4096 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4098 case SHIFT_LSHIFTRT:
4100 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4102 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4104 case SHIFT_ASHIFTRT:
4105 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4109 else if ((8 <= count && count <= 13)
4110 || (TARGET_H8300S && count == 14))
4112 info->remainder = count - 8;
4117 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4119 case SHIFT_LSHIFTRT:
4122 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4123 info->shift1 = "shlr.b\t%s0";
4124 info->cc_inline = CC_SET_ZNV;
4128 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4129 info->cc_special = CC_SET_ZNV;
4132 case SHIFT_ASHIFTRT:
4135 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4136 info->shift1 = "shar.b\t%s0";
4140 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4141 info->cc_special = CC_SET_ZNV;
4146 else if (count == 14)
4152 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4154 case SHIFT_LSHIFTRT:
4156 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4158 case SHIFT_ASHIFTRT:
4160 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4161 else if (TARGET_H8300H)
4163 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4164 info->cc_special = CC_SET_ZNV;
4166 else /* TARGET_H8300S */
4171 else if (count == 15)
4176 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4178 case SHIFT_LSHIFTRT:
4179 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4181 case SHIFT_ASHIFTRT:
4182 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4189 if (TARGET_H8300 && 8 <= count && count <= 9)
4191 info->remainder = count - 8;
4196 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4198 case SHIFT_LSHIFTRT:
4199 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4200 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4202 case SHIFT_ASHIFTRT:
4203 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4207 else if (count == 8 && !TARGET_H8300)
4212 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4214 case SHIFT_LSHIFTRT:
4215 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4217 case SHIFT_ASHIFTRT:
4218 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4222 else if (count == 15 && TARGET_H8300)
4228 case SHIFT_LSHIFTRT:
4229 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4231 case SHIFT_ASHIFTRT:
4232 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4236 else if (count == 15 && !TARGET_H8300)
4241 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4242 info->cc_special = CC_SET_ZNV;
4244 case SHIFT_LSHIFTRT:
4245 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4246 info->cc_special = CC_SET_ZNV;
4248 case SHIFT_ASHIFTRT:
4252 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4253 || (TARGET_H8300H && 16 <= count && count <= 19)
4254 || (TARGET_H8300S && 16 <= count && count <= 21))
4256 info->remainder = count - 16;
4261 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4263 info->shift1 = "add.w\t%e0,%e0";
4265 case SHIFT_LSHIFTRT:
4268 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4269 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4273 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4274 info->cc_special = CC_SET_ZNV;
4277 case SHIFT_ASHIFTRT:
4280 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4281 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4285 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4286 info->cc_special = CC_SET_ZNV;
4291 else if (TARGET_H8300 && 24 <= count && count <= 28)
4293 info->remainder = count - 24;
4298 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4299 info->shift1 = "shll.b\t%z0";
4300 info->cc_inline = CC_SET_ZNV;
4302 case SHIFT_LSHIFTRT:
4303 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4304 info->shift1 = "shlr.b\t%w0";
4305 info->cc_inline = CC_SET_ZNV;
4307 case SHIFT_ASHIFTRT:
4308 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4309 info->shift1 = "shar.b\t%w0";
4310 info->cc_inline = CC_SET_ZNV;
4314 else if ((TARGET_H8300H && count == 24)
4315 || (TARGET_H8300S && 24 <= count && count <= 25))
4317 info->remainder = count - 24;
4322 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4324 case SHIFT_LSHIFTRT:
4325 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4326 info->cc_special = CC_SET_ZNV;
4328 case SHIFT_ASHIFTRT:
4329 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4330 info->cc_special = CC_SET_ZNV;
4334 else if (!TARGET_H8300 && count == 28)
4340 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4342 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4344 case SHIFT_LSHIFTRT:
4347 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4348 info->cc_special = CC_SET_ZNV;
4351 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4353 case SHIFT_ASHIFTRT:
4357 else if (!TARGET_H8300 && count == 29)
4363 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4365 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4367 case SHIFT_LSHIFTRT:
4370 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4371 info->cc_special = CC_SET_ZNV;
4375 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4376 info->cc_special = CC_SET_ZNV;
4379 case SHIFT_ASHIFTRT:
4383 else if (!TARGET_H8300 && count == 30)
4389 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4391 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4393 case SHIFT_LSHIFTRT:
4395 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4397 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4399 case SHIFT_ASHIFTRT:
4403 else if (count == 31)
4410 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4412 case SHIFT_LSHIFTRT:
4413 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4415 case SHIFT_ASHIFTRT:
4416 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4425 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4426 info->cc_special = CC_SET_ZNV;
4428 case SHIFT_LSHIFTRT:
4429 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4430 info->cc_special = CC_SET_ZNV;
4432 case SHIFT_ASHIFTRT:
4433 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4434 info->cc_special = CC_SET_ZNV;
4447 info->shift2 = NULL;
4450 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4451 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4454 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4459 if (GET_MODE_BITSIZE (mode) <= count)
4462 /* Find out the target CPU. */
4465 else if (TARGET_H8300H)
4470 /* Find the shift algorithm. */
4474 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4475 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4476 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4480 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4481 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4482 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4486 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4487 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4488 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4495 /* On H8/300H, count == 8 uses a scratch register. */
4496 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4497 || (TARGET_H8300H && mode == SImode && count == 8));
4500 /* Output the assembler code for doing shifts. */
4503 output_a_shift (rtx *operands)
4505 static int loopend_lab;
4506 rtx shift = operands[3];
4507 enum machine_mode mode = GET_MODE (shift);
4508 enum rtx_code code = GET_CODE (shift);
4509 enum shift_type shift_type;
4510 enum shift_mode shift_mode;
4511 struct shift_info info;
4519 shift_mode = QIshift;
4522 shift_mode = HIshift;
4525 shift_mode = SIshift;
4534 shift_type = SHIFT_ASHIFTRT;
4537 shift_type = SHIFT_LSHIFTRT;
4540 shift_type = SHIFT_ASHIFT;
4546 /* This case must be taken care of by one of the two splitters
4547 that convert a variable shift into a loop. */
4548 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4550 n = INTVAL (operands[2]);
4552 /* If the count is negative, make it 0. */
4555 /* If the count is too big, truncate it.
4556 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4557 do the intuitive thing. */
4558 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4559 n = GET_MODE_BITSIZE (mode);
4561 get_shift_alg (shift_type, shift_mode, n, &info);
4566 output_asm_insn (info.special, operands);
4572 /* Emit two bit shifts first. */
4573 if (info.shift2 != NULL)
4575 for (; n > 1; n -= 2)
4576 output_asm_insn (info.shift2, operands);
4579 /* Now emit one bit shifts for any residual. */
4581 output_asm_insn (info.shift1, operands);
4586 int m = GET_MODE_BITSIZE (mode) - n;
4587 const int mask = (shift_type == SHIFT_ASHIFT
4588 ? ((1 << m) - 1) << n
4592 /* Not all possibilities of rotate are supported. They shouldn't
4593 be generated, but let's watch for 'em. */
4594 gcc_assert (info.shift1);
4596 /* Emit two bit rotates first. */
4597 if (info.shift2 != NULL)
4599 for (; m > 1; m -= 2)
4600 output_asm_insn (info.shift2, operands);
4603 /* Now single bit rotates for any residual. */
4605 output_asm_insn (info.shift1, operands);
4607 /* Now mask off the high bits. */
4611 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4615 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4616 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4623 output_asm_insn (insn_buf, operands);
4628 /* A loop to shift by a "large" constant value.
4629 If we have shift-by-2 insns, use them. */
4630 if (info.shift2 != NULL)
4632 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4633 names_big[REGNO (operands[4])]);
4634 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4635 output_asm_insn (info.shift2, operands);
4636 output_asm_insn ("add #0xff,%X4", operands);
4637 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4639 output_asm_insn (info.shift1, operands);
4643 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4644 names_big[REGNO (operands[4])]);
4645 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4646 output_asm_insn (info.shift1, operands);
4647 output_asm_insn ("add #0xff,%X4", operands);
4648 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4657 /* Count the number of assembly instructions in a string TEMPL. */
4660 h8300_asm_insn_count (const char *templ)
4662 unsigned int count = 1;
4664 for (; *templ; templ++)
4671 /* Compute the length of a shift insn. */
4674 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4676 rtx shift = operands[3];
4677 enum machine_mode mode = GET_MODE (shift);
4678 enum rtx_code code = GET_CODE (shift);
4679 enum shift_type shift_type;
4680 enum shift_mode shift_mode;
4681 struct shift_info info;
4682 unsigned int wlength = 0;
4687 shift_mode = QIshift;
4690 shift_mode = HIshift;
4693 shift_mode = SIshift;
4702 shift_type = SHIFT_ASHIFTRT;
4705 shift_type = SHIFT_LSHIFTRT;
4708 shift_type = SHIFT_ASHIFT;
4714 if (GET_CODE (operands[2]) != CONST_INT)
4716 /* Get the assembler code to do one shift. */
4717 get_shift_alg (shift_type, shift_mode, 1, &info);
4719 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4723 int n = INTVAL (operands[2]);
4725 /* If the count is negative, make it 0. */
4728 /* If the count is too big, truncate it.
4729 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4730 do the intuitive thing. */
4731 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4732 n = GET_MODE_BITSIZE (mode);
4734 get_shift_alg (shift_type, shift_mode, n, &info);
4739 wlength += h8300_asm_insn_count (info.special);
4741 /* Every assembly instruction used in SHIFT_SPECIAL case
4742 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4743 see xor.l, we just pretend that xor.l counts as two insns
4744 so that the insn length will be computed correctly. */
4745 if (strstr (info.special, "xor.l") != NULL)
4753 if (info.shift2 != NULL)
4755 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4759 wlength += h8300_asm_insn_count (info.shift1) * n;
4765 int m = GET_MODE_BITSIZE (mode) - n;
4767 /* Not all possibilities of rotate are supported. They shouldn't
4768 be generated, but let's watch for 'em. */
4769 gcc_assert (info.shift1);
4771 if (info.shift2 != NULL)
4773 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4777 wlength += h8300_asm_insn_count (info.shift1) * m;
4779 /* Now mask off the high bits. */
4789 gcc_assert (!TARGET_H8300);
4799 /* A loop to shift by a "large" constant value.
4800 If we have shift-by-2 insns, use them. */
4801 if (info.shift2 != NULL)
4803 wlength += 3 + h8300_asm_insn_count (info.shift2);
4805 wlength += h8300_asm_insn_count (info.shift1);
4809 wlength += 3 + h8300_asm_insn_count (info.shift1);
4819 /* Compute which flag bits are valid after a shift insn. */
4822 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4824 rtx shift = operands[3];
4825 enum machine_mode mode = GET_MODE (shift);
4826 enum rtx_code code = GET_CODE (shift);
4827 enum shift_type shift_type;
4828 enum shift_mode shift_mode;
4829 struct shift_info info;
4835 shift_mode = QIshift;
4838 shift_mode = HIshift;
4841 shift_mode = SIshift;
4850 shift_type = SHIFT_ASHIFTRT;
4853 shift_type = SHIFT_LSHIFTRT;
4856 shift_type = SHIFT_ASHIFT;
4862 /* This case must be taken care of by one of the two splitters
4863 that convert a variable shift into a loop. */
4864 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4866 n = INTVAL (operands[2]);
4868 /* If the count is negative, make it 0. */
4871 /* If the count is too big, truncate it.
4872 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4873 do the intuitive thing. */
4874 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4875 n = GET_MODE_BITSIZE (mode);
4877 get_shift_alg (shift_type, shift_mode, n, &info);
4882 if (info.remainder == 0)
4883 return info.cc_special;
4888 return info.cc_inline;
4891 /* This case always ends with an and instruction. */
4895 /* A loop to shift by a "large" constant value.
4896 If we have shift-by-2 insns, use them. */
4897 if (info.shift2 != NULL)
4900 return info.cc_inline;
4909 /* A rotation by a non-constant will cause a loop to be generated, in
4910 which a rotation by one bit is used. A rotation by a constant,
4911 including the one in the loop, will be taken care of by
4912 output_a_rotate () at the insn emit time. */
4915 expand_a_rotate (rtx operands[])
4917 rtx dst = operands[0];
4918 rtx src = operands[1];
4919 rtx rotate_amount = operands[2];
4920 enum machine_mode mode = GET_MODE (dst);
4922 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4925 /* We rotate in place. */
4926 emit_move_insn (dst, src);
4928 if (GET_CODE (rotate_amount) != CONST_INT)
4930 rtx counter = gen_reg_rtx (QImode);
4931 rtx start_label = gen_label_rtx ();
4932 rtx end_label = gen_label_rtx ();
4934 /* If the rotate amount is less than or equal to 0,
4935 we go out of the loop. */
4936 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4937 QImode, 0, end_label);
4939 /* Initialize the loop counter. */
4940 emit_move_insn (counter, rotate_amount);
4942 emit_label (start_label);
4944 /* Rotate by one bit. */
4948 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4951 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4954 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4960 /* Decrement the counter by 1. */
4961 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4963 /* If the loop counter is nonzero, we go back to the beginning
4965 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4968 emit_label (end_label);
4972 /* Rotate by AMOUNT bits. */
4976 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4979 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4982 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4992 /* Output a rotate insn. */
4995 output_a_rotate (enum rtx_code code, rtx *operands)
4997 rtx dst = operands[0];
4998 rtx rotate_amount = operands[2];
4999 enum shift_mode rotate_mode;
5000 enum shift_type rotate_type;
5001 const char *insn_buf;
5004 enum machine_mode mode = GET_MODE (dst);
5006 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5011 rotate_mode = QIshift;
5014 rotate_mode = HIshift;
5017 rotate_mode = SIshift;
5026 rotate_type = SHIFT_ASHIFT;
5029 rotate_type = SHIFT_LSHIFTRT;
5035 amount = INTVAL (rotate_amount);
5037 /* Clean up AMOUNT. */
5040 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5041 amount = GET_MODE_BITSIZE (mode);
5043 /* Determine the faster direction. After this phase, amount will be
5044 at most a half of GET_MODE_BITSIZE (mode). */
5045 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5047 /* Flip the direction. */
5048 amount = GET_MODE_BITSIZE (mode) - amount;
5050 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5053 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5054 boost up the rotation. */
5055 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5056 || (mode == HImode && TARGET_H8300H && amount >= 6)
5057 || (mode == HImode && TARGET_H8300S && amount == 8)
5058 || (mode == SImode && TARGET_H8300H && amount >= 10)
5059 || (mode == SImode && TARGET_H8300S && amount >= 13))
5064 /* This code works on any family. */
5065 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5066 output_asm_insn (insn_buf, operands);
5070 /* This code works on the H8/300H and H8S. */
5071 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5072 output_asm_insn (insn_buf, operands);
5079 /* Adjust AMOUNT and flip the direction. */
5080 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5082 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5085 /* Output rotate insns. */
5086 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5089 insn_buf = rotate_two[rotate_type][rotate_mode];
5091 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5093 for (; amount >= bits; amount -= bits)
5094 output_asm_insn (insn_buf, operands);
5100 /* Compute the length of a rotate insn. */
5103 compute_a_rotate_length (rtx *operands)
5105 rtx src = operands[1];
5106 rtx amount_rtx = operands[2];
5107 enum machine_mode mode = GET_MODE (src);
5109 unsigned int length = 0;
5111 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5113 amount = INTVAL (amount_rtx);
5115 /* Clean up AMOUNT. */
5118 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5119 amount = GET_MODE_BITSIZE (mode);
5121 /* Determine the faster direction. After this phase, amount
5122 will be at most a half of GET_MODE_BITSIZE (mode). */
5123 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5124 /* Flip the direction. */
5125 amount = GET_MODE_BITSIZE (mode) - amount;
5127 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5128 boost up the rotation. */
5129 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5130 || (mode == HImode && TARGET_H8300H && amount >= 6)
5131 || (mode == HImode && TARGET_H8300S && amount == 8)
5132 || (mode == SImode && TARGET_H8300H && amount >= 10)
5133 || (mode == SImode && TARGET_H8300S && amount >= 13))
5135 /* Adjust AMOUNT and flip the direction. */
5136 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5140 /* We use 2-bit rotations on the H8S. */
5142 amount = amount / 2 + amount % 2;
5144 /* The H8/300 uses three insns to rotate one bit, taking 6
5146 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5151 /* Fix the operands of a gen_xxx so that it could become a bit
5155 fix_bit_operand (rtx *operands, enum rtx_code code)
5157 /* The bit_operand predicate accepts any memory during RTL generation, but
5158 only 'U' memory afterwards, so if this is a MEM operand, we must force
5159 it to be valid for 'U' by reloading the address. */
5162 ? single_zero_operand (operands[2], QImode)
5163 : single_one_operand (operands[2], QImode))
5165 /* OK to have a memory dest. */
5166 if (GET_CODE (operands[0]) == MEM
5167 && !satisfies_constraint_U (operands[0]))
5169 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5170 copy_to_mode_reg (Pmode,
5171 XEXP (operands[0], 0)));
5172 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5176 if (GET_CODE (operands[1]) == MEM
5177 && !satisfies_constraint_U (operands[1]))
5179 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5180 copy_to_mode_reg (Pmode,
5181 XEXP (operands[1], 0)));
5182 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5188 /* Dest and src op must be register. */
5190 operands[1] = force_reg (QImode, operands[1]);
5192 rtx res = gen_reg_rtx (QImode);
5196 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5199 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5202 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5207 emit_insn (gen_movqi (operands[0], res));
5212 /* Return nonzero if FUNC is an interrupt function as specified
5213 by the "interrupt" attribute. */
5216 h8300_interrupt_function_p (tree func)
5220 if (TREE_CODE (func) != FUNCTION_DECL)
5223 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5224 return a != NULL_TREE;
5227 /* Return nonzero if FUNC is a saveall function as specified by the
5228 "saveall" attribute. */
5231 h8300_saveall_function_p (tree func)
5235 if (TREE_CODE (func) != FUNCTION_DECL)
5238 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5239 return a != NULL_TREE;
5242 /* Return nonzero if FUNC is an OS_Task function as specified
5243 by the "OS_Task" attribute. */
5246 h8300_os_task_function_p (tree func)
5250 if (TREE_CODE (func) != FUNCTION_DECL)
5253 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5254 return a != NULL_TREE;
5257 /* Return nonzero if FUNC is a monitor function as specified
5258 by the "monitor" attribute. */
5261 h8300_monitor_function_p (tree func)
5265 if (TREE_CODE (func) != FUNCTION_DECL)
5268 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5269 return a != NULL_TREE;
5272 /* Return nonzero if FUNC is a function that should be called
5273 through the function vector. */
5276 h8300_funcvec_function_p (tree func)
5280 if (TREE_CODE (func) != FUNCTION_DECL)
5283 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5284 return a != NULL_TREE;
5287 /* Return nonzero if DECL is a variable that's in the eight bit
5291 h8300_eightbit_data_p (tree decl)
5295 if (TREE_CODE (decl) != VAR_DECL)
5298 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5299 return a != NULL_TREE;
5302 /* Return nonzero if DECL is a variable that's in the tiny
5306 h8300_tiny_data_p (tree decl)
5310 if (TREE_CODE (decl) != VAR_DECL)
5313 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5314 return a != NULL_TREE;
5317 /* Generate an 'interrupt_handler' attribute for decls. We convert
5318 all the pragmas to corresponding attributes. */
5321 h8300_insert_attributes (tree node, tree *attributes)
5323 if (TREE_CODE (node) == FUNCTION_DECL)
5325 if (pragma_interrupt)
5327 pragma_interrupt = 0;
5329 /* Add an 'interrupt_handler' attribute. */
5330 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5338 /* Add an 'saveall' attribute. */
5339 *attributes = tree_cons (get_identifier ("saveall"),
5345 /* Supported attributes:
5347 interrupt_handler: output a prologue and epilogue suitable for an
5350 saveall: output a prologue and epilogue that saves and restores
5351 all registers except the stack pointer.
5353 function_vector: This function should be called through the
5356 eightbit_data: This variable lives in the 8-bit data area and can
5357 be referenced with 8-bit absolute memory addresses.
5359 tiny_data: This variable lives in the tiny data area and can be
5360 referenced with 16-bit absolute memory references. */
5362 static const struct attribute_spec h8300_attribute_table[] =
5364 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5365 affects_type_identity } */
5366 { "interrupt_handler", 0, 0, true, false, false,
5367 h8300_handle_fndecl_attribute, false },
5368 { "saveall", 0, 0, true, false, false,
5369 h8300_handle_fndecl_attribute, false },
5370 { "OS_Task", 0, 0, true, false, false,
5371 h8300_handle_fndecl_attribute, false },
5372 { "monitor", 0, 0, true, false, false,
5373 h8300_handle_fndecl_attribute, false },
5374 { "function_vector", 0, 0, true, false, false,
5375 h8300_handle_fndecl_attribute, false },
5376 { "eightbit_data", 0, 0, true, false, false,
5377 h8300_handle_eightbit_data_attribute, false },
5378 { "tiny_data", 0, 0, true, false, false,
5379 h8300_handle_tiny_data_attribute, false },
5380 { NULL, 0, 0, false, false, false, NULL, false }
5384 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5385 struct attribute_spec.handler. */
5387 h8300_handle_fndecl_attribute (tree *node, tree name,
5388 tree args ATTRIBUTE_UNUSED,
5389 int flags ATTRIBUTE_UNUSED,
5392 if (TREE_CODE (*node) != FUNCTION_DECL)
5394 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5396 *no_add_attrs = true;
5402 /* Handle an "eightbit_data" attribute; arguments as in
5403 struct attribute_spec.handler. */
5405 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5406 tree args ATTRIBUTE_UNUSED,
5407 int flags ATTRIBUTE_UNUSED,
5412 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5414 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5418 warning (OPT_Wattributes, "%qE attribute ignored",
5420 *no_add_attrs = true;
5426 /* Handle an "tiny_data" attribute; arguments as in
5427 struct attribute_spec.handler. */
5429 h8300_handle_tiny_data_attribute (tree *node, tree name,
5430 tree args ATTRIBUTE_UNUSED,
5431 int flags ATTRIBUTE_UNUSED,
5436 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5438 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5442 warning (OPT_Wattributes, "%qE attribute ignored",
5444 *no_add_attrs = true;
5450 /* Mark function vectors, and various small data objects. */
5453 h8300_encode_section_info (tree decl, rtx rtl, int first)
5455 int extra_flags = 0;
5457 default_encode_section_info (decl, rtl, first);
5459 if (TREE_CODE (decl) == FUNCTION_DECL
5460 && h8300_funcvec_function_p (decl))
5461 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5462 else if (TREE_CODE (decl) == VAR_DECL
5463 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5465 if (h8300_eightbit_data_p (decl))
5466 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5467 else if (first && h8300_tiny_data_p (decl))
5468 extra_flags = SYMBOL_FLAG_TINY_DATA;
5472 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5475 /* Output a single-bit extraction. */
5478 output_simode_bld (int bild, rtx operands[])
5482 /* Clear the destination register. */
5483 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5485 /* Now output the bit load or bit inverse load, and store it in
5488 output_asm_insn ("bild\t%Z2,%Y1", operands);
5490 output_asm_insn ("bld\t%Z2,%Y1", operands);
5492 output_asm_insn ("bst\t#0,%w0", operands);
5496 /* Determine if we can clear the destination first. */
5497 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5498 && REGNO (operands[0]) != REGNO (operands[1]));
5501 output_asm_insn ("sub.l\t%S0,%S0", operands);
5503 /* Output the bit load or bit inverse load. */
5505 output_asm_insn ("bild\t%Z2,%Y1", operands);
5507 output_asm_insn ("bld\t%Z2,%Y1", operands);
5510 output_asm_insn ("xor.l\t%S0,%S0", operands);
5512 /* Perform the bit store. */
5513 output_asm_insn ("rotxl.l\t%S0", operands);
5520 /* Delayed-branch scheduling is more effective if we have some idea
5521 how long each instruction will be. Use a shorten_branches pass
5522 to get an initial estimate. */
5527 if (flag_delayed_branch)
5528 shorten_branches (get_insns ());
5531 #ifndef OBJECT_FORMAT_ELF
5533 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5536 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5537 fprintf (asm_out_file, "\t.section %s\n", name);
5539 #endif /* ! OBJECT_FORMAT_ELF */
5541 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5542 which is a special case of the 'R' operand. */
5545 h8300_eightbit_constant_address_p (rtx x)
5547 /* The ranges of the 8-bit area. */
5548 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5549 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5550 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5551 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5552 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5553 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5555 unsigned HOST_WIDE_INT addr;
5557 /* We accept symbols declared with eightbit_data. */
5558 if (GET_CODE (x) == SYMBOL_REF)
5559 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5561 if (GET_CODE (x) != CONST_INT)
5567 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5568 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5569 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5572 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5573 on H8/300H and H8S. */
5576 h8300_tiny_constant_address_p (rtx x)
5578 /* The ranges of the 16-bit area. */
5579 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5580 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5581 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5582 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5583 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5584 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5585 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5586 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5588 unsigned HOST_WIDE_INT addr;
5590 switch (GET_CODE (x))
5593 /* In the normal mode, any symbol fits in the 16-bit absolute
5594 address range. We also accept symbols declared with
5596 return (TARGET_NORMAL_MODE
5597 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5601 return (TARGET_NORMAL_MODE
5603 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5605 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5608 return TARGET_NORMAL_MODE;
5616 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5617 locations that can be accessed as a 16-bit word. */
5620 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5622 HOST_WIDE_INT offset1, offset2;
5630 else if (GET_CODE (addr1) == PLUS
5631 && REG_P (XEXP (addr1, 0))
5632 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5634 reg1 = XEXP (addr1, 0);
5635 offset1 = INTVAL (XEXP (addr1, 1));
5645 else if (GET_CODE (addr2) == PLUS
5646 && REG_P (XEXP (addr2, 0))
5647 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5649 reg2 = XEXP (addr2, 0);
5650 offset2 = INTVAL (XEXP (addr2, 1));
5655 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5656 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5658 && offset1 + 1 == offset2)
5664 /* Return nonzero if we have the same comparison insn as I3 two insns
5665 before I3. I3 is assumed to be a comparison insn. */
5668 same_cmp_preceding_p (rtx i3)
5672 /* Make sure we have a sequence of three insns. */
5673 i2 = prev_nonnote_insn (i3);
5676 i1 = prev_nonnote_insn (i2);
5680 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5681 && any_condjump_p (i2) && onlyjump_p (i2));
5684 /* Return nonzero if we have the same comparison insn as I1 two insns
5685 after I1. I1 is assumed to be a comparison insn. */
5688 same_cmp_following_p (rtx i1)
5692 /* Make sure we have a sequence of three insns. */
5693 i2 = next_nonnote_insn (i1);
5696 i3 = next_nonnote_insn (i2);
5700 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5701 && any_condjump_p (i2) && onlyjump_p (i2));
5704 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5705 (or pops) N registers. OPERANDS are assumed to be an array of
5709 h8300_regs_ok_for_stm (int n, rtx operands[])
5714 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5715 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5716 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5718 return ((REGNO (operands[0]) == 0
5719 && REGNO (operands[1]) == 1
5720 && REGNO (operands[2]) == 2)
5721 || (REGNO (operands[0]) == 4
5722 && REGNO (operands[1]) == 5
5723 && REGNO (operands[2]) == 6));
5726 return (REGNO (operands[0]) == 0
5727 && REGNO (operands[1]) == 1
5728 && REGNO (operands[2]) == 2
5729 && REGNO (operands[3]) == 3);
5735 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5738 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5739 unsigned int new_reg)
5741 /* Interrupt functions can only use registers that have already been
5742 saved by the prologue, even if they would normally be
5745 if (h8300_current_function_interrupt_function_p ()
5746 && !df_regs_ever_live_p (new_reg))
5752 /* Returns true if register REGNO is safe to be allocated as a scratch
5753 register in the current function. */
5756 h8300_hard_regno_scratch_ok (unsigned int regno)
5758 if (h8300_current_function_interrupt_function_p ()
5759 && ! WORD_REG_USED (regno))
5766 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5769 h8300_rtx_ok_for_base_p (rtx x, int strict)
5771 /* Strip off SUBREG if any. */
5772 if (GET_CODE (x) == SUBREG)
5777 ? REG_OK_FOR_BASE_STRICT_P (x)
5778 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5781 /* Return nozero if X is a legitimate address. On the H8/300, a
5782 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5783 CONSTANT_ADDRESS. */
5786 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5788 /* The register indirect addresses like @er0 is always valid. */
5789 if (h8300_rtx_ok_for_base_p (x, strict))
5792 if (CONSTANT_ADDRESS_P (x))
5796 && ( GET_CODE (x) == PRE_INC
5797 || GET_CODE (x) == PRE_DEC
5798 || GET_CODE (x) == POST_INC
5799 || GET_CODE (x) == POST_DEC)
5800 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5803 if (GET_CODE (x) == PLUS
5804 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5805 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5812 /* Worker function for HARD_REGNO_NREGS.
5814 We pretend the MAC register is 32bits -- we don't have any data
5815 types on the H8 series to handle more than 32bits. */
5818 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5820 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5823 /* Worker function for HARD_REGNO_MODE_OK. */
5826 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5829 /* If an even reg, then anything goes. Otherwise the mode must be
5831 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5833 /* MAC register can only be of SImode. Otherwise, anything
5835 return regno == MAC_REG ? mode == SImode : 1;
5838 /* Helper function for the move patterns. Make sure a move is legitimate. */
5841 h8300_move_ok (rtx dest, rtx src)
5845 /* Validate that at least one operand is a register. */
5848 if (MEM_P (src) || CONSTANT_P (src))
5850 addr = XEXP (dest, 0);
5853 else if (MEM_P (src))
5855 addr = XEXP (src, 0);
5861 /* Validate that auto-inc doesn't affect OTHER. */
5862 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5864 addr = XEXP (addr, 0);
5866 if (addr == stack_pointer_rtx)
5867 return register_no_sp_elim_operand (other, VOIDmode);
5869 return !reg_overlap_mentioned_p(other, addr);
5872 /* Perform target dependent optabs initialization. */
5874 h8300_init_libfuncs (void)
5876 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5877 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5878 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5879 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5880 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5883 /* Worker function for TARGET_FUNCTION_VALUE.
5885 On the H8 the return value is in R0/R1. */
5888 h8300_function_value (const_tree ret_type,
5889 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5890 bool outgoing ATTRIBUTE_UNUSED)
5892 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5895 /* Worker function for TARGET_LIBCALL_VALUE.
5897 On the H8 the return value is in R0/R1. */
5900 h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5902 return gen_rtx_REG (mode, R0_REG);
5905 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5907 On the H8, R0 is the only register thus used. */
5910 h8300_function_value_regno_p (const unsigned int regno)
5912 return (regno == R0_REG);
5915 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5918 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5920 return (TYPE_MODE (type) == BLKmode
5921 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5924 /* We emit the entire trampoline here. Depending on the pointer size,
5925 we use a different trampoline.
5929 1 0000 7903xxxx mov.w #0x1234,r3
5930 2 0004 5A00xxxx jmp @0x1234
5935 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5936 3 0006 5Axxxxxx jmp @0x123456
5941 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5943 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5946 if (Pmode == HImode)
5948 mem = adjust_address (m_tramp, HImode, 0);
5949 emit_move_insn (mem, GEN_INT (0x7903));
5950 mem = adjust_address (m_tramp, Pmode, 2);
5951 emit_move_insn (mem, cxt);
5952 mem = adjust_address (m_tramp, HImode, 4);
5953 emit_move_insn (mem, GEN_INT (0x5a00));
5954 mem = adjust_address (m_tramp, Pmode, 6);
5955 emit_move_insn (mem, fnaddr);
5961 mem = adjust_address (m_tramp, HImode, 0);
5962 emit_move_insn (mem, GEN_INT (0x7a03));
5963 mem = adjust_address (m_tramp, Pmode, 2);
5964 emit_move_insn (mem, cxt);
5966 tem = copy_to_reg (fnaddr);
5967 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5968 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5969 mem = adjust_address (m_tramp, SImode, 6);
5970 emit_move_insn (mem, tem);
5974 /* Initialize the GCC target structure. */
5975 #undef TARGET_ATTRIBUTE_TABLE
5976 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5978 #undef TARGET_ASM_ALIGNED_HI_OP
5979 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5981 #undef TARGET_ASM_FILE_START
5982 #define TARGET_ASM_FILE_START h8300_file_start
5983 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5984 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5986 #undef TARGET_ASM_FILE_END
5987 #define TARGET_ASM_FILE_END h8300_file_end
5989 #undef TARGET_PRINT_OPERAND
5990 #define TARGET_PRINT_OPERAND h8300_print_operand
5991 #undef TARGET_PRINT_OPERAND_ADDRESS
5992 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5993 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5994 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5996 #undef TARGET_ENCODE_SECTION_INFO
5997 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5999 #undef TARGET_INSERT_ATTRIBUTES
6000 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6002 #undef TARGET_REGISTER_MOVE_COST
6003 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6005 #undef TARGET_RTX_COSTS
6006 #define TARGET_RTX_COSTS h8300_rtx_costs
6008 #undef TARGET_INIT_LIBFUNCS
6009 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6011 #undef TARGET_FUNCTION_VALUE
6012 #define TARGET_FUNCTION_VALUE h8300_function_value
6014 #undef TARGET_LIBCALL_VALUE
6015 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6017 #undef TARGET_FUNCTION_VALUE_REGNO_P
6018 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6020 #undef TARGET_RETURN_IN_MEMORY
6021 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6023 #undef TARGET_FUNCTION_ARG
6024 #define TARGET_FUNCTION_ARG h8300_function_arg
6026 #undef TARGET_FUNCTION_ARG_ADVANCE
6027 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6029 #undef TARGET_MACHINE_DEPENDENT_REORG
6030 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6032 #undef TARGET_HARD_REGNO_SCRATCH_OK
6033 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6035 #undef TARGET_LEGITIMATE_ADDRESS_P
6036 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6038 #undef TARGET_CAN_ELIMINATE
6039 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6041 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6042 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6044 #undef TARGET_TRAMPOLINE_INIT
6045 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6047 #undef TARGET_OPTION_OVERRIDE
6048 #define TARGET_OPTION_OVERRIDE h8300_option_override
6050 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6051 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6053 struct gcc_target targetm = TARGET_INITIALIZER;