1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005 Free Software Foundation,
4 ;; Contributed by Red Hat, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; ::::::::::::::::::::
30 ;; ::::::::::::::::::::
32 ;; GOT constants must go 12/HI/LO for the splitter to work
38 (UNSPEC_PIC_PROLOGUE 3)
40 (UNSPEC_STACK_ADJUST 5)
41 (UNSPEC_EH_RETURN_EPILOGUE 6)
45 (UNSPEC_GETTLSOFF 200)
46 (UNSPEC_TLS_LOAD_GOTTLSOFF12 201)
47 (UNSPEC_TLS_INDIRECT_CALL 202)
48 (UNSPEC_TLS_TLSDESC_LDD 203)
49 (UNSPEC_TLS_TLSDESC_LDD_AUX 204)
50 (UNSPEC_TLS_TLSOFF_LD 205)
52 (UNSPEC_TLSOFF_HILO 207)
58 (R_FRV_FUNCDESC_GOT12 15)
59 (R_FRV_FUNCDESC_GOTHI 16)
60 (R_FRV_FUNCDESC_GOTLO 17)
61 (R_FRV_FUNCDESC_VALUE 18)
62 (R_FRV_FUNCDESC_GOTOFF12 19)
63 (R_FRV_FUNCDESC_GOTOFFHI 20)
64 (R_FRV_FUNCDESC_GOTOFFLO 21)
71 (R_FRV_GOTTLSOFF_HI 28)
72 (R_FRV_GOTTLSOFF_LO 29)
78 (R_FRV_GOTTLSDESCHI 35)
79 (R_FRV_GOTTLSDESCLO 36)
84 ;; LR_REG conflicts with definition in frv.h
91 ;; ::::::::::::::::::::
95 ;; ::::::::::::::::::::
97 ;; Standard Constraints
99 ;; `m' A memory operand is allowed, with any kind of address that the
100 ;; machine supports in general.
102 ;; `o' A memory operand is allowed, but only if the address is
103 ;; "offsettable". This means that adding a small integer (actually, the
104 ;; width in bytes of the operand, as determined by its machine mode) may be
105 ;; added to the address and the result is also a valid memory address.
107 ;; `V' A memory operand that is not offsettable. In other words,
108 ;; anything that would fit the `m' constraint but not the `o' constraint.
110 ;; `<' A memory operand with autodecrement addressing (either
111 ;; predecrement or postdecrement) is allowed.
113 ;; `>' A memory operand with autoincrement addressing (either
114 ;; preincrement or postincrement) is allowed.
116 ;; `r' A register operand is allowed provided that it is in a general
119 ;; `d', `a', `f', ...
120 ;; Other letters can be defined in machine-dependent fashion to stand for
121 ;; particular classes of registers. `d', `a' and `f' are defined on the
122 ;; 68000/68020 to stand for data, address and floating point registers.
124 ;; `i' An immediate integer operand (one with constant value) is allowed.
125 ;; This includes symbolic constants whose values will be known only at
128 ;; `n' An immediate integer operand with a known numeric value is allowed.
129 ;; Many systems cannot support assembly-time constants for operands less
130 ;; than a word wide. Constraints for these operands should use `n' rather
133 ;; 'I' First machine-dependent integer constant (6 bit signed ints).
134 ;; 'J' Second machine-dependent integer constant (10 bit signed ints).
135 ;; 'K' Third machine-dependent integer constant (-2048).
136 ;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).
137 ;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).
138 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
139 ;; 'O' Seventh machine-dependent integer constant (zero).
140 ;; 'P' Eighth machine-dependent integer constant (1..2047).
142 ;; Other letters in the range `I' through `P' may be defined in a
143 ;; machine-dependent fashion to permit immediate integer operands with
144 ;; explicit integer values in specified ranges. For example, on the 68000,
145 ;; `I' is defined to stand for the range of values 1 to 8. This is the
146 ;; range permitted as a shift count in the shift instructions.
148 ;; `E' An immediate floating operand (expression code `const_double') is
149 ;; allowed, but only if the target floating point format is the same as
150 ;; that of the host machine (on which the compiler is running).
152 ;; `F' An immediate floating operand (expression code `const_double') is
155 ;; 'G' First machine-dependent const_double.
156 ;; 'H' Second machine-dependent const_double.
158 ;; `s' An immediate integer operand whose value is not an explicit
159 ;; integer is allowed.
161 ;; This might appear strange; if an insn allows a constant operand with a
162 ;; value not known at compile time, it certainly must allow any known
163 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
166 ;; For example, on the 68000 in a fullword instruction it is possible to
167 ;; use an immediate operand; but if the immediate value is between -128 and
168 ;; 127, better code results from loading the value into a register and
169 ;; using the register. This is because the load into the register can be
170 ;; done with a `moveq' instruction. We arrange for this to happen by
171 ;; defining the letter `K' to mean "any integer outside the range -128 to
172 ;; 127", and then specifying `Ks' in the operand constraints.
174 ;; `g' Any register, memory or immediate integer operand is allowed,
175 ;; except for registers that are not general registers.
177 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
178 ;; `general_operand'. This is normally used in the constraint of a
179 ;; `match_scratch' when certain alternatives will not actually require a
182 ;; `0' Match operand 0.
183 ;; `1' Match operand 1.
184 ;; `2' Match operand 2.
185 ;; `3' Match operand 3.
186 ;; `4' Match operand 4.
187 ;; `5' Match operand 5.
188 ;; `6' Match operand 6.
189 ;; `7' Match operand 7.
190 ;; `8' Match operand 8.
191 ;; `9' Match operand 9.
193 ;; An operand that matches the specified operand number is allowed. If a
194 ;; digit is used together with letters within the same alternative, the
195 ;; digit should come last.
197 ;; This is called a "matching constraint" and what it really means is that
198 ;; the assembler has only a single operand that fills two roles considered
199 ;; separate in the RTL insn. For example, an add insn has two input
200 ;; operands and one output operand in the RTL, but on most CISC machines an
201 ;; add instruction really has only two operands, one of them an
202 ;; input-output operand:
206 ;; Matching constraints are used in these circumstances. More precisely,
207 ;; the two operands that match must include one input-only operand and one
208 ;; output-only operand. Moreover, the digit must be a smaller number than
209 ;; the number of the operand that uses it in the constraint.
211 ;; For operands to match in a particular case usually means that they are
212 ;; identical-looking RTL expressions. But in a few special cases specific
213 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
214 ;; operand will match `*x++' as an output operand. For proper results in
215 ;; such cases, the output template should always use the output-operand's
216 ;; number when printing the operand.
218 ;; `p' An operand that is a valid memory address is allowed. This is for
219 ;; "load address" and "push address" instructions.
221 ;; `p' in the constraint must be accompanied by `address_operand' as the
222 ;; predicate in the `match_operand'. This predicate interprets the mode
223 ;; specified in the `match_operand' as the mode of the memory reference for
224 ;; which the address would be valid.
226 ;; `Q` First non constant, non register machine-dependent insns
227 ;; `R` Second non constant, non register machine-dependent insns
228 ;; `S` Third non constant, non register machine-dependent insns
229 ;; `T` Fourth non constant, non register machine-dependent insns
230 ;; `U` Fifth non constant, non register machine-dependent insns
232 ;; Letters in the range `Q' through `U' may be defined in a
233 ;; machine-dependent fashion to stand for arbitrary operand types. The
234 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
235 ;; its first argument and the constraint letter as its second operand.
237 ;; A typical use for this would be to distinguish certain types of memory
238 ;; references that affect other insn operands.
240 ;; Do not define these constraint letters to accept register references
241 ;; (`reg'); the reload pass does not expect this and would not handle it
244 ;; Multiple Alternative Constraints
245 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
246 ;; choice when no alternative applies exactly. The compiler regards this
247 ;; alternative as one unit more costly for each `?' that appears in it.
249 ;; `!' Disparage severely the alternative that the `!' appears in. This
250 ;; alternative can still be used if it fits without reloading, but if
251 ;; reloading is needed, some other alternative will be used.
253 ;; Constraint modifiers
254 ;; `=' Means that this operand is write-only for this instruction: the
255 ;; previous value is discarded and replaced by output data.
257 ;; `+' Means that this operand is both read and written by the
260 ;; When the compiler fixes up the operands to satisfy the constraints, it
261 ;; needs to know which operands are inputs to the instruction and which are
262 ;; outputs from it. `=' identifies an output; `+' identifies an operand
263 ;; that is both input and output; all other operands are assumed to be
266 ;; `&' Means (in a particular alternative) that this operand is written
267 ;; before the instruction is finished using the input operands. Therefore,
268 ;; this operand may not lie in a register that is used as an input operand
269 ;; or as part of any memory address.
271 ;; `&' applies only to the alternative in which it is written. In
272 ;; constraints with multiple alternatives, sometimes one alternative
273 ;; requires `&' while others do not.
275 ;; `&' does not obviate the need to write `='.
277 ;; `%' Declares the instruction to be commutative for this operand and the
278 ;; following operand. This means that the compiler may interchange the two
279 ;; operands if that is the cheapest way to make all operands fit the
280 ;; constraints. This is often used in patterns for addition instructions
281 ;; that really have only two operands: the result must go in one of the
284 ;; `#' Says that all following characters, up to the next comma, are to be
285 ;; ignored as a constraint. They are significant only for choosing
286 ;; register preferences.
288 ;; `*' Says that the following character should be ignored when choosing
289 ;; register preferences. `*' has no effect on the meaning of the
290 ;; constraint as a constraint, and no effect on reloading.
293 ;; ::::::::::::::::::::
297 ;; ::::::::::::::::::::
299 ;; The `define_attr' expression is used to define each attribute required by
300 ;; the target machine. It looks like:
302 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
304 ;; NAME is a string specifying the name of the attribute being defined.
306 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
307 ;; values that can be assigned to the attribute, or a null string to indicate
308 ;; that the attribute takes numeric values.
310 ;; DEFAULT is an attribute expression that gives the value of this attribute
311 ;; for insns that match patterns whose definition does not include an explicit
312 ;; value for this attribute.
314 ;; For each defined attribute, a number of definitions are written to the
315 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
316 ;; for an attribute, the following are defined:
318 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
320 ;; * An enumeral class is defined for `attr_NAME' with elements of the
321 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
322 ;; converted to upper case.
324 ;; * A function `get_attr_NAME' is defined that is passed an insn and
325 ;; returns the attribute value for that insn.
327 ;; For example, if the following is present in the `md' file:
329 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
331 ;; the following lines will be written to the file `insn-attr.h'.
333 ;; #define HAVE_ATTR_type
334 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
335 ;; extern enum attr_type get_attr_type ();
337 ;; If the attribute takes numeric values, no `enum' type will be defined and
338 ;; the function to obtain the attribute's value will return `int'.
340 (define_attr "length" "" (const_int 4))
342 ;; Processor type -- this attribute must exactly match the processor_type
343 ;; enumeration in frv-protos.h.
345 (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"
346 (const (symbol_ref "frv_cpu_type")))
348 ;; Attribute is "yes" for branches and jumps that span too great a distance
349 ;; to be implemented in the most natural way. Such instructions will use
350 ;; a call instruction in some way.
352 (define_attr "far_jump" "yes,no" (const_string "no"))
355 ;; "unknown" must come last.
357 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
358 (const_string "unknown"))
360 (define_attr "acc_group" "none,even,odd"
361 (symbol_ref "frv_acc_group (insn)"))
363 ;; Scheduling and Packing Overview
364 ;; -------------------------------
366 ;; FR-V instructions are divided into five groups: integer, floating-point,
367 ;; media, branch and control. Each group is associated with a separate set
368 ;; of processing units, the number and behavior of which depend on the target
369 ;; target processor. Integer units have names like I0 and I1, floating-point
370 ;; units have names like F0 and F1, and so on.
372 ;; Each member of the FR-V family has its own restrictions on which
373 ;; instructions can issue to which units. For example, some processors
374 ;; allow loads to issue to I0 or I1 while others only allow them to issue
375 ;; to I0. As well as these processor-specific restrictions, there is a
376 ;; general rule that an instruction can only issue to unit X + 1 if an
377 ;; instruction in the same packet issued to unit X.
379 ;; Sometimes the only way to honor these restrictions is by adding nops
380 ;; to a packet. For example, on the fr550, media instructions that access
381 ;; ACC4-7 can only issue to M1 or M3. It is therefore only possible to
382 ;; execute these instructions by packing them with something that issues
383 ;; to M0. When no useful M0 instruction exists, an "mnop" can be used
386 ;; Having decided which instructions should issue to which units, the packet
387 ;; should be ordered according to the following template:
389 ;; I0 F0/M0 I1 F1/M1 .... B0 B1 ...
391 ;; Note that VLIW packets execute strictly in parallel. Every instruction
392 ;; in the packet will stall until all input operands are ready. These
393 ;; operands are then read simultaneously before any registers are modified.
394 ;; This means that it's OK to have write-after-read hazards between
395 ;; instructions in the same packet, even if the write is listed earlier
398 ;; Three gcc passes are involved in generating VLIW packets:
400 ;; (1) The scheduler. This pass uses the standard scheduling code and
401 ;; behaves in much the same way as it would for a superscalar RISC
404 ;; (2) frv_reorg. This pass inserts nops into packets in order to meet
405 ;; the processor's issue requirements. It also has code to optimize
406 ;; the type of padding used to align labels.
408 ;; (3) frv_pack_insns. The final packing phase, which puts the
409 ;; instructions into assembly language order according to the
410 ;; "I0 F0/M0 ..." template above.
412 ;; In the ideal case, these three passes will agree on which instructions
413 ;; should be packed together, but this won't always happen. In particular:
415 ;; (a) (2) might not pack predicated instructions in the same way as (1).
416 ;; The scheduler tries to schedule predicated instructions for the
417 ;; worst case, assuming the predicate is true. However, if we have
418 ;; something like a predicated load, it isn't always possible to
419 ;; fill the load delay with useful instructions. (2) should then
420 ;; pack the user of the loaded value as aggressively as possible,
421 ;; in order to optimize the case when the predicate is false.
422 ;; See frv_pack_insn_p for more details.
424 ;; (b) The final shorten_branches pass runs between (2) and (3).
425 ;; Since (2) inserts nops, it is possible that some branches
426 ;; that were thought to be in range during (2) turned out to
427 ;; out-of-range in (3).
429 ;; All three passes use DFAs to model issue restrictions. The main
430 ;; question that the DFAs are supposed to answer is simply: can these
431 ;; instructions be packed together? The DFAs are not responsible for
432 ;; assigning instructions to execution units; that's the job of
433 ;; frv_sort_insn_group, see below for details.
435 ;; To get the best results, the DFAs should try to allow packets to
436 ;; be built in every possible order. This gives the scheduler more
437 ;; flexibility, removing the need for things like multipass lookahead.
438 ;; It also means we can take more advantage of inter-packet dependencies.
440 ;; For example, suppose we're compiling for the fr400 and we have:
443 ;; ldi @(gr6,gr0),gr4
445 ;; We can pack these instructions together by assigning the load to I0 and
446 ;; the addition to I1. However, because of the anti dependence between the
447 ;; two instructions, the scheduler must schedule the addition first.
448 ;; We should generally get better schedules if the DFA allows both
449 ;; (ldi, addi) and (addi, ldi), leaving the final packing pass to
450 ;; reorder the packet where appropriate.
452 ;; Almost all integer instructions can issue to any unit in the range I0
453 ;; to Ix, where the value of "x" depends on the type of instruction and
454 ;; on the target processor. The rules for other instruction groups are
457 ;; When the restrictions are as regular as this, we can get the desired
458 ;; behavior by claiming the DFA unit associated with the highest unused
459 ;; execution unit. For example, if an instruction can issue to I0 or I1,
460 ;; the DFA first tries to take the DFA unit associated with I1, and will
461 ;; only take I0's unit if I1 isn't free. (Note that, as mentioned above,
462 ;; the DFA does not assign instructions to units. An instruction that
463 ;; claims DFA unit I1 will not necessarily issue to I1 in the final packet.)
465 ;; There are some cases, such as the fr550 media restriction mentioned
466 ;; above, where the rule is not as simple as "any unit between 0 and X".
467 ;; Even so, allocating higher units first brings us close to the ideal.
469 ;; Having divided instructions into packets, passes (2) and (3) must
470 ;; assign instructions to specific execution units. They do this using
471 ;; the following algorithm:
473 ;; 1. Partition the instructions into groups (integer, float/media, etc.)
475 ;; 2. For each group of instructions:
477 ;; (a) Issue each instruction in the reset DFA state and use the
478 ;; DFA cpu_unit_query interface to find out which unit it picks
481 ;; (b) Sort the instructions into ascending order of picked units.
482 ;; Instructions that pick I1 first come after those that pick
483 ;; I0 first, and so on. Let S be the sorted sequence and S[i]
484 ;; be the ith element of it (counting from zero).
486 ;; (c) If this is the control or branch group, goto (i)
488 ;; (d) Find the largest L such that S[0]...S[L-1] can be issued
489 ;; consecutively from the reset state and such that the DFA
490 ;; claims unit X when S[X] is added. Let D be the DFA state
491 ;; after instructions S[0]...S[L-1] have been issued.
493 ;; (e) If L is the length of S, goto (i)
495 ;; (f) Let U be the number of units belonging to this group and #S be
496 ;; the length of S. Create a new sequence S' by concatenating
497 ;; S[L]...S[#S-1] and (U - #S) nops.
499 ;; (g) For each permutation S'' of S', try issuing S'' from last to
500 ;; first, starting with state D. See if the DFA claims unit
501 ;; X + L when each S''[X] is added. If so, set S to the
502 ;; concatenation of S[0]...S[L-1] and S'', then goto (i).
504 ;; (h) If (g) found no permutation, abort.
506 ;; (i) S is now the sorted sequence for this group, meaning that S[X]
507 ;; issues to unit X. Trim any unwanted nops from the end of S.
509 ;; The sequence calculated by (b) is trivially correct for control
510 ;; instructions since they can't be packed. It is also correct for branch
511 ;; instructions due to their simple issue requirements. For integer and
512 ;; floating-point/media instructions, the sequence calculated by (b) is
513 ;; often the correct answer; the rest of the algorithm is optimized for
514 ;; the case in which it is correct.
516 ;; If there were no irregularities in the issue restrictions then step
517 ;; (d) would not be needed. It is mainly there to cope with the fr550
518 ;; integer restrictions, where a store can issue to I1, but only if a store
519 ;; also issues to I0. (Note that if a packet has two stores, they will be
520 ;; at the beginning of the sequence calculated by (b).) It also copes
521 ;; with fr400 M-2 instructions, which must issue to M0, and which cannot
522 ;; be issued together with an mnop in M1.
524 ;; Step (g) is the main one for integer and float/media instructions.
525 ;; The first permutation it tries is S' itself (because, as noted above,
526 ;; the sequence calculated by (b) is often correct). If S' doesn't work,
527 ;; the implementation tries varying the beginning of the sequence first.
528 ;; Thus the nops towards the end of the sequence will only move to lower
529 ;; positions if absolutely necessary.
531 ;; The algorithm is theoretically exponential in the number of instructions
532 ;; in a group, although it's only O(n log(n)) if the sequence calculated by
533 ;; (b) is acceptable. In practice, the algorithm completes quickly even
534 ;; in the rare cases where (g) needs to try other permutations.
535 (define_automaton "integer, float_media, branch, control, idiv, div")
537 ;; The main issue units. Note that not all units are available on
539 (define_query_cpu_unit "i0,i1,i2,i3" "integer")
540 (define_query_cpu_unit "f0,f1,f2,f3" "float_media")
541 (define_query_cpu_unit "b0,b1" "branch")
542 (define_query_cpu_unit "c" "control")
545 (define_cpu_unit "idiv1,idiv2" "idiv")
546 (define_cpu_unit "div1,div2,root" "div")
548 ;; Control instructions cannot be packed with others.
549 (define_reservation "control" "i0+i1+i2+i3+f0+f1+f2+f3+b0+b1")
551 ;; Generic reservation for control insns
552 (define_insn_reservation "control" 1
553 (eq_attr "type" "trap,spr,unknown,multi")
556 ;; Reservation for relaxable calls to gettlsoff.
557 (define_insn_reservation "load_or_call" 3
558 (eq_attr "type" "load_or_call")
561 ;; ::::::::::::::::::::
563 ;; :: Generic/FR500 scheduler description
565 ;; ::::::::::::::::::::
568 ;; Synthetic units used to describe issue restrictions.
569 (define_automaton "fr500_integer")
570 (define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")
571 (exclusion_set "fr500_load0,fr500_load1" "fr500_store0")
573 (define_bypass 0 "fr500_i1_sethi" "fr500_i1_setlo")
574 (define_insn_reservation "fr500_i1_sethi" 1
575 (and (eq_attr "cpu" "generic,fr500,tomcat")
576 (eq_attr "type" "sethi"))
579 (define_insn_reservation "fr500_i1_setlo" 1
580 (and (eq_attr "cpu" "generic,fr500,tomcat")
581 (eq_attr "type" "setlo"))
584 (define_insn_reservation "fr500_i1_int" 1
585 (and (eq_attr "cpu" "generic,fr500,tomcat")
586 (eq_attr "type" "int"))
589 (define_insn_reservation "fr500_i1_mul" 3
590 (and (eq_attr "cpu" "generic,fr500,tomcat")
591 (eq_attr "type" "mul"))
594 (define_insn_reservation "fr500_i1_div" 19
595 (and (eq_attr "cpu" "generic,fr500,tomcat")
596 (eq_attr "type" "div"))
597 "(i1|i0),(idiv1*18|idiv2*18)")
599 (define_insn_reservation "fr500_i2" 4
600 (and (eq_attr "cpu" "generic,fr500,tomcat")
601 (eq_attr "type" "gload,fload"))
602 "(i1|i0) + (fr500_load0|fr500_load1)")
604 (define_insn_reservation "fr500_i3" 0
605 (and (eq_attr "cpu" "generic,fr500,tomcat")
606 (eq_attr "type" "gstore,fstore"))
609 (define_insn_reservation "fr500_i4" 3
610 (and (eq_attr "cpu" "generic,fr500,tomcat")
611 (eq_attr "type" "movgf,movfg"))
614 (define_insn_reservation "fr500_i5" 0
615 (and (eq_attr "cpu" "generic,fr500,tomcat")
616 (eq_attr "type" "jumpl"))
620 ;; Branch-instructions
622 (define_insn_reservation "fr500_branch" 0
623 (and (eq_attr "cpu" "generic,fr500,tomcat")
624 (eq_attr "type" "jump,branch,ccr"))
627 (define_insn_reservation "fr500_call" 0
628 (and (eq_attr "cpu" "generic,fr500,tomcat")
629 (eq_attr "type" "call"))
632 ;; Floating point insns. The default latencies are for non-media
633 ;; instructions; media instructions incur an extra cycle.
635 (define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,
636 fr500_m4,fr500_m5,fr500_m6")
637 (define_insn_reservation "fr500_farith" 3
638 (and (eq_attr "cpu" "generic,fr500,tomcat")
639 (eq_attr "type" "fnop,fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))
642 (define_insn_reservation "fr500_fcmp" 4
643 (and (eq_attr "cpu" "generic,fr500,tomcat")
644 (eq_attr "type" "fscmp,fdcmp"))
647 (define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,
648 fr500_m4,fr500_m5,fr500_m6")
649 (define_insn_reservation "fr500_fdiv" 10
650 (and (eq_attr "cpu" "generic,fr500,tomcat")
651 (eq_attr "type" "fsdiv,fddiv"))
652 "(f1|f0),(div1*9 | div2*9)")
654 (define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,
655 fr500_m4,fr500_m5,fr500_m6")
656 (define_insn_reservation "fr500_froot" 15
657 (and (eq_attr "cpu" "generic,fr500,tomcat")
658 (eq_attr "type" "sqrt_single,sqrt_double"))
661 ;; Media insns. Conflict table is as follows:
671 ;; where X indicates an invalid combination.
673 ;; Target registers are as follows:
682 ;; The default FPR latencies are for integer instructions.
683 ;; Floating-point instructions need one cycle more and media
684 ;; instructions need one cycle less.
685 (define_automaton "fr500_media")
686 (define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")
687 (define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")
688 (define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")
689 (define_cpu_unit "fr500_m5" "fr500_media")
690 (define_cpu_unit "fr500_m6" "fr500_media")
692 (exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,
693 fr500_m3_0,fr500_m3_1")
694 (exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1,fr500_m5")
696 (define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
697 fr500_m4,fr500_m5,fr500_m6")
698 (define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
699 (define_insn_reservation "fr500_m1" 3
700 (and (eq_attr "cpu" "generic,fr500,tomcat")
701 (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))
704 (define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
705 fr500_m4,fr500_m5,fr500_m6")
706 (define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
707 (define_insn_reservation "fr500_m2" 3
708 (and (eq_attr "cpu" "generic,fr500,tomcat")
709 (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
710 "(f1|f0) + (fr500_m2_0|fr500_m2_1)")
712 (define_bypass 1 "fr500_m3" "fr500_m4")
713 (define_insn_reservation "fr500_m3" 2
714 (and (eq_attr "cpu" "generic,fr500,tomcat")
715 (eq_attr "type" "mclracc,mwtacc"))
716 "(f1|f0) + (fr500_m3_0|fr500_m3_1)")
718 (define_bypass 1 "fr500_m4" "fr500_m4")
719 (define_insn_reservation "fr500_m4" 2
720 (and (eq_attr "cpu" "generic,fr500,tomcat")
721 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
722 "(f1|f0) + (fr500_m4_0|fr500_m4_1)")
724 (define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
725 fr500_m4,fr500_m5,fr500_m6")
726 (define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
727 (define_insn_reservation "fr500_m5" 3
728 (and (eq_attr "cpu" "generic,fr500,tomcat")
729 (eq_attr "type" "mdpackh"))
730 "(f1|f0) + fr500_m5")
732 (define_bypass 1 "fr500_m6" "fr500_m4")
733 (define_insn_reservation "fr500_m6" 2
734 (and (eq_attr "cpu" "generic,fr500,tomcat")
735 (eq_attr "type" "mclracca"))
736 "(f1|f0) + fr500_m6")
738 ;; ::::::::::::::::::::
740 ;; :: FR400 scheduler description
742 ;; ::::::::::::::::::::
744 ;; Category 2 media instructions use both media units, but can be packed
745 ;; with non-media instructions. Use fr400_m1unit to claim the M1 unit
746 ;; without claiming a slot.
748 ;; Name Class Units Latency
749 ;; ==== ===== ===== =======
751 ;; sethi I1 I0/I1 0 -- does not interfere with setlo
756 ;; fload I2 I0 4 -- only 3 if read by a media insn
757 ;; gstore I3 I0 0 -- provides no result
758 ;; fstore I3 I0 0 -- provides no result
761 ;; jumpl I5 I0 0 -- provides no result
763 ;; (*) The results of these instructions can be read one cycle earlier
764 ;; than indicated. The penalty given is for instructions with write-after-
765 ;; write dependencies.
767 ;; The FR400 can only do loads and stores in I0, so we there's no danger
768 ;; of memory unit collision in the same packet. There's only one divide
771 (define_automaton "fr400_integer")
772 (define_cpu_unit "fr400_mul" "fr400_integer")
774 (define_insn_reservation "fr400_i1_int" 1
775 (and (eq_attr "cpu" "fr400,fr405,fr450")
776 (eq_attr "type" "int"))
779 (define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")
780 (define_insn_reservation "fr400_i1_sethi" 1
781 (and (eq_attr "cpu" "fr400,fr405,fr450")
782 (eq_attr "type" "sethi"))
785 (define_insn_reservation "fr400_i1_setlo" 1
786 (and (eq_attr "cpu" "fr400,fr405,fr450")
787 (eq_attr "type" "setlo"))
790 ;; 3 is the worst case (write-after-write hazard).
791 (define_insn_reservation "fr400_i1_mul" 3
792 (and (eq_attr "cpu" "fr400,fr405")
793 (eq_attr "type" "mul"))
796 (define_insn_reservation "fr450_i1_mul" 2
797 (and (eq_attr "cpu" "fr450")
798 (eq_attr "type" "mul"))
801 (define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
802 (define_insn_reservation "fr400_i1_macc" 2
803 (and (eq_attr "cpu" "fr405,fr450")
804 (eq_attr "type" "macc"))
805 "(i0|i1) + fr400_mul")
807 (define_insn_reservation "fr400_i1_scan" 1
808 (and (eq_attr "cpu" "fr400,fr405,fr450")
809 (eq_attr "type" "scan"))
812 (define_insn_reservation "fr400_i1_cut" 2
813 (and (eq_attr "cpu" "fr405,fr450")
814 (eq_attr "type" "cut"))
817 ;; 20 is for a write-after-write hazard.
818 (define_insn_reservation "fr400_i1_div" 20
819 (and (eq_attr "cpu" "fr400,fr405")
820 (eq_attr "type" "div"))
823 (define_insn_reservation "fr450_i1_div" 19
824 (and (eq_attr "cpu" "fr450")
825 (eq_attr "type" "div"))
828 ;; 4 is for a write-after-write hazard.
829 (define_insn_reservation "fr400_i2" 4
830 (and (eq_attr "cpu" "fr400,fr405")
831 (eq_attr "type" "gload,fload"))
834 (define_insn_reservation "fr450_i2_gload" 3
835 (and (eq_attr "cpu" "fr450")
836 (eq_attr "type" "gload"))
839 ;; 4 is for a write-after-write hazard.
840 (define_insn_reservation "fr450_i2_fload" 4
841 (and (eq_attr "cpu" "fr450")
842 (eq_attr "type" "fload"))
845 (define_insn_reservation "fr400_i3" 0
846 (and (eq_attr "cpu" "fr400,fr405,fr450")
847 (eq_attr "type" "gstore,fstore"))
850 ;; 3 is for a write-after-write hazard.
851 (define_insn_reservation "fr400_i4" 3
852 (and (eq_attr "cpu" "fr400,fr405")
853 (eq_attr "type" "movfg,movgf"))
856 (define_insn_reservation "fr450_i4_movfg" 2
857 (and (eq_attr "cpu" "fr450")
858 (eq_attr "type" "movfg"))
861 ;; 3 is for a write-after-write hazard.
862 (define_insn_reservation "fr450_i4_movgf" 3
863 (and (eq_attr "cpu" "fr450")
864 (eq_attr "type" "movgf"))
867 (define_insn_reservation "fr400_i5" 0
868 (and (eq_attr "cpu" "fr400,fr405,fr450")
869 (eq_attr "type" "jumpl"))
872 ;; The bypass between FPR loads and media instructions, described above.
876 "fr400_m1_1,fr400_m1_2,\
877 fr400_m2_1,fr400_m2_2,\
878 fr400_m3_1,fr400_m3_2,\
879 fr400_m4_1,fr400_m4_2,\
882 ;; The branch instructions all use the B unit and produce no result.
884 (define_insn_reservation "fr400_b" 0
885 (and (eq_attr "cpu" "fr400,fr405,fr450")
886 (eq_attr "type" "jump,branch,ccr,call"))
889 ;; FP->FP moves are marked as "fsconv" instructions in the define_insns
890 ;; below, but are implemented on the FR400 using "mlogic" instructions.
891 ;; It's easier to class "fsconv" as a "m1:1" instruction than provide
892 ;; separate define_insns for the FR400.
894 ;; M1 instructions store their results in FPRs. Any instruction can read
895 ;; the result in the following cycle, so no penalty occurs.
897 (define_automaton "fr400_media")
898 (define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")
899 (exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")
901 (define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")
902 (define_reservation "fr400_m2" "f0 + fr400_m2a")
904 (define_insn_reservation "fr400_m1_1" 1
905 (and (eq_attr "cpu" "fr400,fr405")
906 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))
909 (define_insn_reservation "fr400_m1_2" 1
910 (and (eq_attr "cpu" "fr400,fr405")
911 (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))
914 ;; M2 instructions store their results in accumulators, which are read
915 ;; by M2 or M4 media commands. M2 instructions can read the results in
916 ;; the following cycle, but M4 instructions must wait a cycle more.
919 "fr400_m2_1,fr400_m2_2"
920 "fr400_m2_1,fr400_m2_2")
922 (define_insn_reservation "fr400_m2_1" 2
923 (and (eq_attr "cpu" "fr400,fr405")
924 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
927 (define_insn_reservation "fr400_m2_2" 2
928 (and (eq_attr "cpu" "fr400,fr405")
929 (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
932 ;; For our purposes, there seems to be little real difference between
933 ;; M1 and M3 instructions. Keep them separate anyway in case the distinction
936 (define_insn_reservation "fr400_m3_1" 1
937 (and (eq_attr "cpu" "fr400,fr405")
938 (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
941 (define_insn_reservation "fr400_m3_2" 1
942 (and (eq_attr "cpu" "fr400,fr405")
943 (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
946 ;; M4 instructions write to accumulators or FPRs. MOVFG and STF
947 ;; instructions can read an FPR result in the following cycle, but
948 ;; M-unit instructions must wait a cycle more for either kind of result.
950 (define_bypass 1 "fr400_m4_1,fr400_m4_2" "fr400_i3,fr400_i4")
952 (define_insn_reservation "fr400_m4_1" 2
953 (and (eq_attr "cpu" "fr400,fr405")
954 (eq_attr "type" "mrdacc,mcut,mclracc"))
957 (define_insn_reservation "fr400_m4_2" 2
958 (and (eq_attr "cpu" "fr400,fr405")
959 (eq_attr "type" "mclracca,mdcut"))
962 ;; M5 instructions always incur a 1-cycle penalty.
964 (define_insn_reservation "fr400_m5" 2
965 (and (eq_attr "cpu" "fr400,fr405")
966 (eq_attr "type" "mwtacc"))
969 ;; ::::::::::::::::::::
971 ;; :: FR450 media scheduler description
973 ;; ::::::::::::::::::::
975 ;; The FR451 media restrictions are similar to the FR400's, but not as
976 ;; strict and not as regular. There are 6 categories with the following
980 ;; M-1 M-2 M-3 M-4 M-5 M-6
988 ;; where "x" indicates a conflict.
990 ;; There is no difference between M-1 and M-3 as far as issue
991 ;; restrictions are concerned, so they are combined as "m13".
993 ;; Units for odd-numbered categories. There can be two of these
995 (define_cpu_unit "fr450_m13a,fr450_m13b" "float_media")
996 (define_cpu_unit "fr450_m5a,fr450_m5b" "float_media")
998 ;; Units for even-numbered categories. There can only be one per packet.
999 (define_cpu_unit "fr450_m2a,fr450_m4a,fr450_m6a" "float_media")
1001 ;; Enforce the restriction matrix above.
1002 (exclusion_set "fr450_m2a,fr450_m4a,fr450_m6a" "fr450_m13a,fr450_m13b")
1003 (exclusion_set "fr450_m2a,fr450_m6a" "fr450_m5a,fr450_m5b")
1004 (exclusion_set "fr450_m4a,fr450_m6a" "fr450_m2a")
1006 (define_reservation "fr450_m13" "(f1|f0) + (fr450_m13a|fr450_m13b)")
1007 (define_reservation "fr450_m2" "f0 + fr450_m2a")
1008 (define_reservation "fr450_m4" "f0 + fr450_m4a")
1009 (define_reservation "fr450_m5" "(f1|f0) + (fr450_m5a|fr450_m5b)")
1010 (define_reservation "fr450_m6" "(f0|f1) + fr450_m6a")
1012 ;; MD-1, MD-3 and MD-8 instructions, which are the same as far
1013 ;; as scheduling is concerned. The inputs and outputs are FPRs.
1014 ;; Instructions that have 32-bit inputs and outputs belong to M-1 while
1015 ;; the rest belong to M-2.
1017 ;; ??? Arithmetic shifts (MD-6) have an extra cycle latency, but we don't
1018 ;; make the distinction between them and logical shifts.
1019 (define_insn_reservation "fr450_md138_1" 1
1020 (and (eq_attr "cpu" "fr450")
1021 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset,
1022 mrot,mshift,mexpdhw,mpackh"))
1025 (define_insn_reservation "fr450_md138_2" 1
1026 (and (eq_attr "cpu" "fr450")
1027 (eq_attr "type" "mqaddh,mqsath,mqlimh,
1028 mdrot,mwcut,mqshift,mexpdhd,
1029 munpackh,mdpackh,mbhconv,mcpl"))
1032 ;; MD-2 instructions. These take FPR or ACC inputs and produce an ACC output.
1033 ;; Instructions that write to double ACCs belong to M-3 while those that write
1034 ;; to quad ACCs belong to M-4.
1035 (define_insn_reservation "fr450_md2_3" 2
1036 (and (eq_attr "cpu" "fr450")
1037 (eq_attr "type" "mmulh,mmach,mcpx,mmulxh,mmrdh,maddacc"))
1040 (define_insn_reservation "fr450_md2_4" 2
1041 (and (eq_attr "cpu" "fr450")
1042 (eq_attr "type" "mqmulh,mqmach,mqcpx,mqmulxh,mdaddacc"))
1045 ;; Another MD-2 instruction can use the result on the following cycle.
1046 (define_bypass 1 "fr450_md2_3,fr450_md2_4" "fr450_md2_3,fr450_md2_4")
1048 ;; MD-4 instructions that write to ACCs.
1049 (define_insn_reservation "fr450_md4_3" 2
1050 (and (eq_attr "cpu" "fr450")
1051 (eq_attr "type" "mclracc"))
1054 (define_insn_reservation "fr450_md4_4" 3
1055 (and (eq_attr "cpu" "fr450")
1056 (eq_attr "type" "mclracca"))
1059 ;; MD-4 instructions that write to FPRs.
1060 (define_insn_reservation "fr450_md4_1" 2
1061 (and (eq_attr "cpu" "fr450")
1062 (eq_attr "type" "mcut"))
1065 (define_insn_reservation "fr450_md4_5" 2
1066 (and (eq_attr "cpu" "fr450")
1067 (eq_attr "type" "mrdacc"))
1070 (define_insn_reservation "fr450_md4_6" 2
1071 (and (eq_attr "cpu" "fr450")
1072 (eq_attr "type" "mdcut"))
1075 ;; Integer instructions can read the FPR result of an MD-4 instruction on
1076 ;; the following cycle.
1077 (define_bypass 1 "fr450_md4_1,fr450_md4_5,fr450_md4_6"
1078 "fr400_i3,fr450_i4_movfg")
1080 ;; MD-5 instructions, which belong to M-3. They take FPR inputs and
1082 (define_insn_reservation "fr450_md5_3" 2
1083 (and (eq_attr "cpu" "fr450")
1084 (eq_attr "type" "mwtacc"))
1087 ;; ::::::::::::::::::::
1089 ;; :: FR550 scheduler description
1091 ;; ::::::::::::::::::::
1093 ;; Prevent loads and stores from being issued in the same packet.
1094 ;; These units must go into the generic "integer" reservation because
1095 ;; of the constraints on fr550_store0 and fr550_store1.
1096 (define_cpu_unit "fr550_load0,fr550_load1" "integer")
1097 (define_cpu_unit "fr550_store0,fr550_store1" "integer")
1098 (exclusion_set "fr550_load0,fr550_load1" "fr550_store0,fr550_store1")
1100 ;; A store can only issue to I1 if one has also been issued to I0.
1101 (presence_set "fr550_store1" "fr550_store0")
1103 (define_bypass 0 "fr550_sethi" "fr550_setlo")
1104 (define_insn_reservation "fr550_sethi" 1
1105 (and (eq_attr "cpu" "fr550")
1106 (eq_attr "type" "sethi"))
1109 (define_insn_reservation "fr550_setlo" 1
1110 (and (eq_attr "cpu" "fr550")
1111 (eq_attr "type" "setlo"))
1114 (define_insn_reservation "fr550_int" 1
1115 (and (eq_attr "cpu" "fr550")
1116 (eq_attr "type" "int"))
1119 (define_insn_reservation "fr550_mul" 2
1120 (and (eq_attr "cpu" "fr550")
1121 (eq_attr "type" "mul"))
1124 (define_insn_reservation "fr550_div" 19
1125 (and (eq_attr "cpu" "fr550")
1126 (eq_attr "type" "div"))
1127 "(i1|i0),(idiv1*18 | idiv2*18)")
1129 (define_insn_reservation "fr550_load" 3
1130 (and (eq_attr "cpu" "fr550")
1131 (eq_attr "type" "gload,fload"))
1132 "(i1|i0)+(fr550_load0|fr550_load1)")
1134 ;; We can only issue a store to I1 if one was also issued to I0.
1135 ;; This means that, as far as frv_reorder_packet is concerned,
1136 ;; the instruction has the same priority as an I0-only instruction.
1137 (define_insn_reservation "fr550_store" 1
1138 (and (eq_attr "cpu" "fr550")
1139 (eq_attr "type" "gstore,fstore"))
1140 "(i0+fr550_store0)|(i1+fr550_store1)")
1142 (define_insn_reservation "fr550_transfer" 2
1143 (and (eq_attr "cpu" "fr550")
1144 (eq_attr "type" "movgf,movfg"))
1147 (define_insn_reservation "fr550_jumpl" 0
1148 (and (eq_attr "cpu" "fr550")
1149 (eq_attr "type" "jumpl"))
1152 (define_cpu_unit "fr550_ccr0,fr550_ccr1" "float_media")
1154 (define_insn_reservation "fr550_branch" 0
1155 (and (eq_attr "cpu" "fr550")
1156 (eq_attr "type" "jump,branch"))
1159 (define_insn_reservation "fr550_ccr" 0
1160 (and (eq_attr "cpu" "fr550")
1161 (eq_attr "type" "ccr"))
1162 "(b1|b0) + (fr550_ccr1|fr550_ccr0)")
1164 (define_insn_reservation "fr550_call" 0
1165 (and (eq_attr "cpu" "fr550")
1166 (eq_attr "type" "call"))
1169 (define_automaton "fr550_float_media")
1170 (define_cpu_unit "fr550_add0,fr550_add1" "fr550_float_media")
1172 ;; There are three possible combinations of floating-point/media instructions:
1174 ;; - one media and one float
1175 ;; - up to four float, no media
1176 ;; - up to four media, no float
1177 (define_cpu_unit "fr550_f0,fr550_f1,fr550_f2,fr550_f3" "fr550_float_media")
1178 (define_cpu_unit "fr550_m0,fr550_m1,fr550_m2,fr550_m3" "fr550_float_media")
1179 (exclusion_set "fr550_f1,fr550_f2,fr550_f3" "fr550_m1,fr550_m2,fr550_m3")
1181 (define_reservation "fr550_float" "fr550_f0|fr550_f1|fr550_f2|fr550_f3")
1182 (define_reservation "fr550_media" "fr550_m0|fr550_m1|fr550_m2|fr550_m3")
1184 (define_insn_reservation "fr550_f1" 0
1185 (and (eq_attr "cpu" "fr550")
1186 (eq_attr "type" "fnop"))
1187 "(f3|f2|f1|f0) + fr550_float")
1189 (define_insn_reservation "fr550_f2" 3
1190 (and (eq_attr "cpu" "fr550")
1191 (eq_attr "type" "fsconv,fsadd,fscmp"))
1192 "(f3|f2|f1|f0) + (fr550_add0|fr550_add1) + fr550_float")
1194 (define_insn_reservation "fr550_f3_mul" 3
1195 (and (eq_attr "cpu" "fr550")
1196 (eq_attr "type" "fsmul"))
1197 "(f1|f0) + fr550_float")
1199 (define_insn_reservation "fr550_f3_div" 10
1200 (and (eq_attr "cpu" "fr550")
1201 (eq_attr "type" "fsdiv"))
1202 "(f1|f0) + fr550_float")
1204 (define_insn_reservation "fr550_f3_sqrt" 15
1205 (and (eq_attr "cpu" "fr550")
1206 (eq_attr "type" "sqrt_single"))
1207 "(f1|f0) + fr550_float")
1209 ;; Synthetic units for enforcing media issue restrictions. Certain types
1210 ;; of insn in M2 conflict with certain types in M0:
1213 ;; MNOP MALU MSFT MMAC MSET
1216 ;; M0 MSFT - - x - x
1220 ;; where "x" indicates a conflict. The same restrictions apply to
1223 ;; In addition -- and this is the awkward bit! -- instructions that
1224 ;; access ACC0-3 can only issue to M0 or M2. Those that access ACC4-7
1225 ;; can only issue to M1 or M3. We refer to such instructions as "even"
1226 ;; and "odd" respectively.
1227 (define_cpu_unit "fr550_malu0,fr550_malu1" "float_media")
1228 (define_cpu_unit "fr550_malu2,fr550_malu3" "float_media")
1229 (define_cpu_unit "fr550_msft0,fr550_msft1" "float_media")
1230 (define_cpu_unit "fr550_mmac0,fr550_mmac1" "float_media")
1231 (define_cpu_unit "fr550_mmac2,fr550_mmac3" "float_media")
1232 (define_cpu_unit "fr550_mset0,fr550_mset1" "float_media")
1233 (define_cpu_unit "fr550_mset2,fr550_mset3" "float_media")
1235 (exclusion_set "fr550_malu0" "fr550_malu2")
1236 (exclusion_set "fr550_malu1" "fr550_malu3")
1238 (exclusion_set "fr550_msft0" "fr550_mset2")
1239 (exclusion_set "fr550_msft1" "fr550_mset3")
1241 (exclusion_set "fr550_mmac0" "fr550_mmac2")
1242 (exclusion_set "fr550_mmac1" "fr550_mmac3")
1244 ;; If an MSFT or MMAC instruction issues to a unit other than M0, we may
1245 ;; need to insert some nops. In the worst case, the packet will end up
1246 ;; having 4 integer instructions and 4 media instructions, leaving no
1247 ;; room for any branch instructions that the DFA might have accepted.
1249 ;; This doesn't matter for JUMP_INSNs and CALL_INSNs because they are
1250 ;; always the last instructions to be passed to the DFA, and could be
1251 ;; pushed out to a separate packet once the nops have been added.
1252 ;; However, it does cause problems for ccr instructions since they
1253 ;; can occur anywhere in the unordered packet.
1254 (exclusion_set "fr550_msft1,fr550_mmac1,fr550_mmac2,fr550_mmac3"
1255 "fr550_ccr0,fr550_ccr1")
1257 (define_reservation "fr550_malu"
1258 "(f3 + fr550_malu3) | (f2 + fr550_malu2)
1259 | (f1 + fr550_malu1) | (f0 + fr550_malu0)")
1261 (define_reservation "fr550_msft_even"
1264 (define_reservation "fr550_msft_odd"
1267 (define_reservation "fr550_msft_either"
1268 "(f1 + fr550_msft1) | (f0 + fr550_msft0)")
1270 (define_reservation "fr550_mmac_even"
1271 "(f2 + fr550_mmac2) | (f0 + fr550_mmac0)")
1273 (define_reservation "fr550_mmac_odd"
1274 "(f3 + fr550_mmac3) | (f1 + fr550_mmac1)")
1276 (define_reservation "fr550_mset"
1277 "(f3 + fr550_mset3) | (f2 + fr550_mset2)
1278 | (f1 + fr550_mset1) | (f0 + fr550_mset0)")
1280 (define_insn_reservation "fr550_mnop" 0
1281 (and (eq_attr "cpu" "fr550")
1282 (eq_attr "type" "mnop"))
1283 "fr550_media + (f3|f2|f1|f0)")
1285 (define_insn_reservation "fr550_malu" 2
1286 (and (eq_attr "cpu" "fr550")
1287 (eq_attr "type" "mlogic,maveh,msath,mabsh,maddh,mqaddh,mqsath"))
1288 "fr550_media + fr550_malu")
1290 ;; These insns only operate on FPRs and so don't need to be classified
1292 (define_insn_reservation "fr550_msft_1_either" 2
1293 (and (eq_attr "cpu" "fr550")
1294 (eq_attr "type" "mrot,mwcut,mshift,mexpdhw,mexpdhd,mpackh,
1295 munpackh,mdpackh,mbhconv,mdrot,mcpl"))
1296 "fr550_media + fr550_msft_either")
1298 ;; These insns read from ACC0-3.
1299 (define_insn_reservation "fr550_msft_1_even" 2
1300 (and (eq_attr "cpu" "fr550")
1301 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1302 (eq_attr "acc_group" "even")))
1303 "fr550_media + fr550_msft_even")
1305 ;; These insns read from ACC4-7.
1306 (define_insn_reservation "fr550_msft_1_odd" 2
1307 (and (eq_attr "cpu" "fr550")
1308 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1309 (eq_attr "acc_group" "odd")))
1310 "fr550_media + fr550_msft_odd")
1312 ;; MCLRACC with A=1 can issue to either M0 or M1.
1313 (define_insn_reservation "fr550_msft_2_either" 2
1314 (and (eq_attr "cpu" "fr550")
1315 (eq_attr "type" "mclracca"))
1316 "fr550_media + fr550_msft_either")
1318 ;; These insns write to ACC0-3.
1319 (define_insn_reservation "fr550_msft_2_even" 2
1320 (and (eq_attr "cpu" "fr550")
1321 (and (eq_attr "type" "mclracc,mwtacc")
1322 (eq_attr "acc_group" "even")))
1323 "fr550_media + fr550_msft_even")
1325 ;; These insns write to ACC4-7.
1326 (define_insn_reservation "fr550_msft_2_odd" 2
1327 (and (eq_attr "cpu" "fr550")
1328 (and (eq_attr "type" "mclracc,mwtacc")
1329 (eq_attr "acc_group" "odd")))
1330 "fr550_media + fr550_msft_odd")
1332 ;; These insns read from and write to ACC0-3.
1333 (define_insn_reservation "fr550_mmac_even" 2
1334 (and (eq_attr "cpu" "fr550")
1335 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1336 maddacc,mdaddacc,mcpx,mqcpx")
1337 (eq_attr "acc_group" "even")))
1338 "fr550_media + fr550_mmac_even")
1340 ;; These insns read from and write to ACC4-7.
1341 (define_insn_reservation "fr550_mmac_odd" 2
1342 (and (eq_attr "cpu" "fr550")
1343 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1344 maddacc,mdaddacc,mcpx,mqcpx")
1345 (eq_attr "acc_group" "odd")))
1346 "fr550_media + fr550_mmac_odd")
1348 (define_insn_reservation "fr550_mset" 1
1349 (and (eq_attr "cpu" "fr550")
1350 (eq_attr "type" "mset"))
1351 "fr550_media + fr550_mset")
1353 ;; ::::::::::::::::::::
1355 ;; :: Simple/FR300 scheduler description
1357 ;; ::::::::::::::::::::
1359 ;; Fr300 or simple processor. To describe it as 1 insn issue
1360 ;; processor, we use control unit.
1362 (define_insn_reservation "fr300_lat1" 1
1363 (and (eq_attr "cpu" "fr300,simple")
1364 (eq_attr "type" "!gload,fload,movfg,movgf"))
1367 (define_insn_reservation "fr300_lat2" 2
1368 (and (eq_attr "cpu" "fr300,simple")
1369 (eq_attr "type" "gload,fload,movfg,movgf"))
1373 ;; ::::::::::::::::::::
1377 ;; ::::::::::::::::::::
1379 ;; The insn attribute mechanism can be used to specify the requirements for
1380 ;; delay slots, if any, on a target machine. An instruction is said to require
1381 ;; a "delay slot" if some instructions that are physically after the
1382 ;; instruction are executed as if they were located before it. Classic
1383 ;; examples are branch and call instructions, which often execute the following
1384 ;; instruction before the branch or call is performed.
1386 ;; On some machines, conditional branch instructions can optionally "annul"
1387 ;; instructions in the delay slot. This means that the instruction will not be
1388 ;; executed for certain branch outcomes. Both instructions that annul if the
1389 ;; branch is true and instructions that annul if the branch is false are
1392 ;; Delay slot scheduling differs from instruction scheduling in that
1393 ;; determining whether an instruction needs a delay slot is dependent only
1394 ;; on the type of instruction being generated, not on data flow between the
1395 ;; instructions. See the next section for a discussion of data-dependent
1396 ;; instruction scheduling.
1398 ;; The requirement of an insn needing one or more delay slots is indicated via
1399 ;; the `define_delay' expression. It has the following form:
1401 ;; (define_delay TEST
1402 ;; [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1403 ;; DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1406 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1407 ;; to a particular insn. If so, the number of required delay slots is
1408 ;; determined by the length of the vector specified as the second argument. An
1409 ;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1410 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1411 ;; if the branch is true. Similarly, ANNUL-FALSE-N specifies which insns in
1412 ;; the delay slot may be annulled if the branch is false. If annulling is not
1413 ;; supported for that delay slot, `(nil)' should be coded.
1415 ;; For example, in the common case where branch and call insns require a single
1416 ;; delay slot, which may contain any insn other than a branch or call, the
1417 ;; following would be placed in the `md' file:
1419 ;; (define_delay (eq_attr "type" "branch,call")
1420 ;; [(eq_attr "type" "!branch,call") (nil) (nil)])
1422 ;; Multiple `define_delay' expressions may be specified. In this case, each
1423 ;; such expression specifies different delay slot requirements and there must
1424 ;; be no insn for which tests in two `define_delay' expressions are both true.
1426 ;; For example, if we have a machine that requires one delay slot for branches
1427 ;; but two for calls, no delay slot can contain a branch or call insn, and any
1428 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1429 ;; true, we might represent this as follows:
1431 ;; (define_delay (eq_attr "type" "branch")
1432 ;; [(eq_attr "type" "!branch,call")
1433 ;; (eq_attr "type" "!branch,call")
1436 ;; (define_delay (eq_attr "type" "call")
1437 ;; [(eq_attr "type" "!branch,call") (nil) (nil)
1438 ;; (eq_attr "type" "!branch,call") (nil) (nil)])
1440 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1441 ;; at assembler generation time. This is usually done by adding a special print
1442 ;; operand to the delayed instruction, and then in the PRINT_OPERAND function
1443 ;; calling dbr_sequence_length() to determine how many delay slots were filled.
1446 ;; --------------<machine>.md-----------------
1447 ;; (define_insn "call"
1448 ;; [(call (match_operand 0 "memory_operand" "m")
1449 ;; (match_operand 1 "" ""))]
1451 ;; "call_delayed %0,%1,%2%#"
1452 ;; [(set_attr "length" "4")
1453 ;; (set_attr "type" "call")])
1455 ;; -------------<machine>.h-------------------
1456 ;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1458 ;; ------------<machine>.c------------------
1460 ;; machine_print_operand (file, x, code)
1468 ;; if (dbr_sequence_length () == 0)
1469 ;; fputs ("\n\tnop", file);
1472 ;; ::::::::::::::::::::
1474 ;; :: Notes on Patterns
1476 ;; ::::::::::::::::::::
1478 ;; If you need to construct a sequence of assembler instructions in order
1479 ;; to implement a pattern be sure to escape any backslashes and double quotes
1480 ;; that you use, e.g.:
1482 ;; (define_insn "an example"
1486 ;; { static char buffer [100];
1487 ;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1492 ;; Also if there is more than one instruction, they can be separated by \\;
1493 ;; which is a space saving synonym for \\n\\t:
1495 ;; (define_insn "another example"
1499 ;; { static char buffer [100];
1500 ;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1501 ;; REGNO (operands[1]));
1507 (include "predicates.md")
1509 ;; ::::::::::::::::::::
1513 ;; ::::::::::::::::::::
1515 ;; Wrap moves in define_expand to prevent memory->memory moves from being
1516 ;; generated at the RTL level, which generates better code for most machines
1517 ;; which can't do mem->mem moves.
1519 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1520 ;; than M, the effect of this instruction is to store the specified value in
1521 ;; the part of the register that corresponds to mode M. The effect on the rest
1522 ;; of the register is undefined.
1524 ;; This class of patterns is special in several ways. First of all, each of
1525 ;; these names *must* be defined, because there is no other way to copy a datum
1526 ;; from one place to another.
1528 ;; Second, these patterns are not used solely in the RTL generation pass. Even
1529 ;; the reload pass can generate move insns to copy values from stack slots into
1530 ;; temporary registers. When it does so, one of the operands is a hard
1531 ;; register and the other is an operand that can need to be reloaded into a
1534 ;; Therefore, when given such a pair of operands, the pattern must
1535 ;; generate RTL which needs no reloading and needs no temporary
1536 ;; registers--no registers other than the operands. For example, if
1537 ;; you support the pattern with a `define_expand', then in such a
1538 ;; case the `define_expand' mustn't call `force_reg' or any other such
1539 ;; function which might generate new pseudo registers.
1541 ;; This requirement exists even for subword modes on a RISC machine
1542 ;; where fetching those modes from memory normally requires several
1543 ;; insns and some temporary registers. Look in `spur.md' to see how
1544 ;; the requirement can be satisfied.
1546 ;; During reload a memory reference with an invalid address may be passed as an
1547 ;; operand. Such an address will be replaced with a valid address later in the
1548 ;; reload pass. In this case, nothing may be done with the address except to
1549 ;; use it as it stands. If it is copied, it will not be replaced with a valid
1550 ;; address. No attempt should be made to make such an address into a valid
1551 ;; address and no routine (such as `change_address') that will do so may be
1552 ;; called. Note that `general_operand' will fail when applied to such an
1555 ;; The global variable `reload_in_progress' (which must be explicitly declared
1556 ;; if required) can be used to determine whether such special handling is
1559 ;; The variety of operands that have reloads depends on the rest of
1560 ;; the machine description, but typically on a RISC machine these can
1561 ;; only be pseudo registers that did not get hard registers, while on
1562 ;; other machines explicit memory references will get optional
1565 ;; If a scratch register is required to move an object to or from memory, it
1566 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
1567 ;; impossible during and after reload. If there are cases needing scratch
1568 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1569 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1570 ;; patterns `reload_inM' or `reload_outM' to handle them.
1572 ;; The constraints on a `moveM' must permit moving any hard register to any
1573 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1574 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1577 ;; It is obligatory to support floating point `moveM' instructions
1578 ;; into and out of any registers that can hold fixed point values,
1579 ;; because unions and structures (which have modes `SImode' or
1580 ;; `DImode') can be in those registers and they may have floating
1583 ;; There may also be a need to support fixed point `moveM' instructions in and
1584 ;; out of floating point registers. Unfortunately, I have forgotten why this
1585 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
1586 ;; rejects fixed point values in floating point registers, then the constraints
1587 ;; of the fixed point `moveM' instructions must be designed to avoid ever
1588 ;; trying to reload into a floating point register.
1590 (define_expand "movqi"
1591 [(set (match_operand:QI 0 "general_operand" "")
1592 (match_operand:QI 1 "general_operand" ""))]
1594 "{ frv_emit_move (QImode, operands[0], operands[1]); DONE; }")
1596 (define_insn "*movqi_load"
1597 [(set (match_operand:QI 0 "register_operand" "=d,f")
1598 (match_operand:QI 1 "frv_load_operand" "m,m"))]
1600 "* return output_move_single (operands, insn);"
1601 [(set_attr "length" "4")
1602 (set_attr "type" "gload,fload")])
1604 (define_insn "*movqi_internal"
1605 [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
1606 (match_operand:QI 1 "move_source_operand" "L,d,d,O, d, f, f, f,GO,!m,!m"))]
1607 "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1608 "* return output_move_single (operands, insn);"
1609 [(set_attr "length" "4")
1610 (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1612 (define_expand "movhi"
1613 [(set (match_operand:HI 0 "general_operand" "")
1614 (match_operand:HI 1 "general_operand" ""))]
1616 "{ frv_emit_move (HImode, operands[0], operands[1]); DONE; }")
1618 (define_insn "*movhi_load"
1619 [(set (match_operand:HI 0 "register_operand" "=d,f")
1620 (match_operand:HI 1 "frv_load_operand" "m,m"))]
1622 "* return output_move_single (operands, insn);"
1623 [(set_attr "length" "4")
1624 (set_attr "type" "gload,fload")])
1626 (define_insn "*movhi_internal"
1627 [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
1628 (match_operand:HI 1 "move_source_operand" "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
1629 "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1630 "* return output_move_single (operands, insn);"
1631 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
1632 (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1634 ;; Split 2 word load of constants into sethi/setlo instructions
1636 [(set (match_operand:HI 0 "integer_register_operand" "")
1637 (match_operand:HI 1 "int_2word_operand" ""))]
1640 (high:HI (match_dup 1)))
1642 (lo_sum:HI (match_dup 0)
1646 (define_insn "movhi_high"
1647 [(set (match_operand:HI 0 "integer_register_operand" "=d")
1648 (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1651 [(set_attr "type" "sethi")
1652 (set_attr "length" "4")])
1654 (define_insn "movhi_lo_sum"
1655 [(set (match_operand:HI 0 "integer_register_operand" "+d")
1656 (lo_sum:HI (match_dup 0)
1657 (match_operand:HI 1 "int_2word_operand" "i")))]
1660 [(set_attr "type" "setlo")
1661 (set_attr "length" "4")])
1663 (define_expand "movsi"
1664 [(set (match_operand:SI 0 "move_destination_operand" "")
1665 (match_operand:SI 1 "move_source_operand" ""))]
1667 "{ frv_emit_move (SImode, operands[0], operands[1]); DONE; }")
1669 ;; Note - it is best to only have one movsi pattern and to handle
1670 ;; all the various contingencies by the use of alternatives. This
1671 ;; allows reload the greatest amount of flexibility (since reload will
1672 ;; only choose amongst alternatives for a selected insn, it will not
1673 ;; replace the insn with another one).
1675 ;; Unfortunately, we do have to separate out load-type moves from the rest,
1676 ;; and only allow memory source operands in the former. If we do memory and
1677 ;; constant loads in a single pattern, reload will be tempted to force
1678 ;; constants into memory when the destination is a floating-point register.
1679 ;; That may make a function use a PIC pointer when it didn't before, and we
1680 ;; cannot change PIC usage (and hence stack layout) so late in the game.
1681 ;; The resulting sequences for loading constants into FPRs are preferable
1682 ;; even when we're not generating PIC code.
1684 ;; However, if we don't accept input from memory at all in the generic
1685 ;; movsi pattern, reloads for asm instructions that reference pseudos
1686 ;; that end up assigned to memory will fail to match, because we
1687 ;; recognize them right after they're emitted, and we don't
1688 ;; re-recognize them again after the substitution for memory. So keep
1689 ;; a memory constraint available, just make sure reload won't be
1690 ;; tempted to use it.
1694 (define_insn "*movsi_load"
1695 [(set (match_operand:SI 0 "register_operand" "=d,f")
1696 (match_operand:SI 1 "frv_load_operand" "m,m"))]
1698 "* return output_move_single (operands, insn);"
1699 [(set_attr "length" "4")
1700 (set_attr "type" "gload,fload")])
1702 (define_insn "*movsi_got"
1703 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1704 (match_operand:SI 1 "got12_operand" ""))]
1707 [(set_attr "type" "int")
1708 (set_attr "length" "4")])
1710 (define_insn "*movsi_high_got"
1711 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1712 (high:SI (match_operand:SI 1 "const_unspec_operand" "")))]
1715 [(set_attr "type" "sethi")
1716 (set_attr "length" "4")])
1718 (define_insn "*movsi_lo_sum_got"
1719 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1720 (lo_sum:SI (match_operand:SI 1 "integer_register_operand" "0")
1721 (match_operand:SI 2 "const_unspec_operand" "")))]
1724 [(set_attr "type" "setlo")
1725 (set_attr "length" "4")])
1727 (define_insn "*movsi_internal"
1728 [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
1729 (match_operand:SI 1 "move_source_operand" "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
1730 "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1731 "* return output_move_single (operands, insn);"
1732 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
1733 (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
1735 ;; Split 2 word load of constants into sethi/setlo instructions
1736 (define_insn_and_split "*movsi_2word"
1737 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1738 (match_operand:SI 1 "int_2word_operand" "i"))]
1743 (high:SI (match_dup 1)))
1745 (lo_sum:SI (match_dup 0)
1748 [(set_attr "length" "8")
1749 (set_attr "type" "multi")])
1751 (define_insn "movsi_high"
1752 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1753 (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1756 [(set_attr "type" "sethi")
1757 (set_attr "length" "4")])
1759 (define_insn "movsi_lo_sum"
1760 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1761 (lo_sum:SI (match_dup 0)
1762 (match_operand:SI 1 "int_2word_operand" "i")))]
1765 [(set_attr "type" "setlo")
1766 (set_attr "length" "4")])
1768 (define_expand "movdi"
1769 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1770 (match_operand:DI 1 "general_operand" ""))]
1772 "{ frv_emit_move (DImode, operands[0], operands[1]); DONE; }")
1774 (define_insn "*movdi_double"
1775 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1776 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1778 && (register_operand (operands[0], DImode)
1779 || reg_or_0_operand (operands[1], DImode))"
1780 "* return output_move_double (operands, insn);"
1781 [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1782 (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1784 (define_insn "*movdi_nodouble"
1785 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1786 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1788 && (register_operand (operands[0], DImode)
1789 || reg_or_0_operand (operands[1], DImode))"
1790 "* return output_move_double (operands, insn);"
1791 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1792 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1795 [(set (match_operand:DI 0 "register_operand" "")
1796 (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1799 "frv_split_double_load (operands[0], operands[1]);")
1802 [(set (match_operand:DI 0 "odd_reg_operand" "")
1803 (match_operand:DI 1 "memory_operand" ""))]
1806 "frv_split_double_load (operands[0], operands[1]);")
1809 [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1810 (match_operand:DI 1 "reg_or_0_operand" ""))]
1813 "frv_split_double_store (operands[0], operands[1]);")
1816 [(set (match_operand:DI 0 "memory_operand" "")
1817 (match_operand:DI 1 "odd_reg_operand" ""))]
1820 "frv_split_double_store (operands[0], operands[1]);")
1823 [(set (match_operand:DI 0 "register_operand" "")
1824 (match_operand:DI 1 "register_operand" ""))]
1826 && (odd_reg_operand (operands[0], DImode)
1827 || odd_reg_operand (operands[1], DImode)
1828 || (integer_register_operand (operands[0], DImode)
1829 && integer_register_operand (operands[1], DImode))
1831 && fpr_operand (operands[0], DImode)
1832 && fpr_operand (operands[1], DImode)))"
1833 [(set (match_dup 2) (match_dup 4))
1834 (set (match_dup 3) (match_dup 5))]
1837 rtx op0 = operands[0];
1838 rtx op0_low = gen_lowpart (SImode, op0);
1839 rtx op0_high = gen_highpart (SImode, op0);
1840 rtx op1 = operands[1];
1841 rtx op1_low = gen_lowpart (SImode, op1);
1842 rtx op1_high = gen_highpart (SImode, op1);
1844 /* We normally copy the low-numbered register first. However, if the first
1845 register operand 0 is the same as the second register of operand 1, we
1846 must copy in the opposite order. */
1848 if (REGNO (op0_high) == REGNO (op1_low))
1850 operands[2] = op0_low;
1851 operands[3] = op0_high;
1852 operands[4] = op1_low;
1853 operands[5] = op1_high;
1857 operands[2] = op0_high;
1858 operands[3] = op0_low;
1859 operands[4] = op1_high;
1860 operands[5] = op1_low;
1865 [(set (match_operand:DI 0 "register_operand" "")
1866 (match_operand:DI 1 "const_int_operand" ""))]
1868 [(set (match_dup 2) (match_dup 4))
1869 (set (match_dup 3) (match_dup 5))]
1872 rtx op0 = operands[0];
1873 rtx op1 = operands[1];
1875 operands[2] = gen_highpart (SImode, op0);
1876 operands[3] = gen_lowpart (SImode, op0);
1877 if (HOST_BITS_PER_WIDE_INT <= 32)
1879 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1884 operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
1885 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
1886 - ((unsigned HOST_WIDE_INT)1 << 31));
1887 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
1892 [(set (match_operand:DI 0 "register_operand" "")
1893 (match_operand:DI 1 "const_double_operand" ""))]
1895 [(set (match_dup 2) (match_dup 4))
1896 (set (match_dup 3) (match_dup 5))]
1899 rtx op0 = operands[0];
1900 rtx op1 = operands[1];
1902 operands[2] = gen_highpart (SImode, op0);
1903 operands[3] = gen_lowpart (SImode, op0);
1904 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1905 operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1908 ;; Floating Point Moves
1910 ;; Note - Patterns for SF mode moves are compulsory, but
1911 ;; patterns for DF are optional, as GCC can synthesize them.
1913 (define_expand "movsf"
1914 [(set (match_operand:SF 0 "general_operand" "")
1915 (match_operand:SF 1 "general_operand" ""))]
1917 "{ frv_emit_move (SFmode, operands[0], operands[1]); DONE; }")
1920 [(set (match_operand:SF 0 "integer_register_operand" "")
1921 (match_operand:SF 1 "int_2word_operand" ""))]
1924 (high:SF (match_dup 1)))
1926 (lo_sum:SF (match_dup 0)
1930 (define_insn "*movsf_load_has_fprs"
1931 [(set (match_operand:SF 0 "register_operand" "=f,d")
1932 (match_operand:SF 1 "frv_load_operand" "m,m"))]
1934 "* return output_move_single (operands, insn);"
1935 [(set_attr "length" "4")
1936 (set_attr "type" "fload,gload")])
1938 (define_insn "*movsf_internal_has_fprs"
1939 [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1940 (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1942 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1943 "* return output_move_single (operands, insn);"
1944 [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1945 (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1947 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1948 ;; will all be emulated
1949 (define_insn "*movsf_internal_no_fprs"
1950 [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1951 (match_operand:SF 1 "move_source_operand" " d,OG,dOG,m,F"))]
1953 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1954 "* return output_move_single (operands, insn);"
1955 [(set_attr "length" "4,4,4,4,8")
1956 (set_attr "type" "int,int,gstore,gload,multi")])
1958 (define_insn "movsf_high"
1959 [(set (match_operand:SF 0 "integer_register_operand" "=d")
1960 (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1963 [(set_attr "type" "sethi")
1964 (set_attr "length" "4")])
1966 (define_insn "movsf_lo_sum"
1967 [(set (match_operand:SF 0 "integer_register_operand" "+d")
1968 (lo_sum:SF (match_dup 0)
1969 (match_operand:SF 1 "int_2word_operand" "i")))]
1972 [(set_attr "type" "setlo")
1973 (set_attr "length" "4")])
1975 (define_expand "movdf"
1976 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1977 (match_operand:DF 1 "general_operand" ""))]
1979 "{ frv_emit_move (DFmode, operands[0], operands[1]); DONE; }")
1981 (define_insn "*movdf_double"
1982 [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d,e,??d")
1983 (match_operand:DF 1 "move_source_operand" " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO,F,F"))]
1985 && (register_operand (operands[0], DFmode)
1986 || reg_or_0_operand (operands[1], DFmode))"
1987 "* return output_move_double (operands, insn);"
1988 [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8,16,16")
1989 (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi,multi,multi")])
1991 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1992 ;; will all be emulated
1993 (define_insn "*movdf_nodouble"
1994 [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1995 (match_operand:DF 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1997 && (register_operand (operands[0], DFmode)
1998 || reg_or_0_operand (operands[1], DFmode))"
1999 "* return output_move_double (operands, insn);"
2000 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
2001 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
2004 [(set (match_operand:DF 0 "register_operand" "")
2005 (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
2008 "frv_split_double_load (operands[0], operands[1]);")
2011 [(set (match_operand:DF 0 "odd_reg_operand" "")
2012 (match_operand:DF 1 "memory_operand" ""))]
2015 "frv_split_double_load (operands[0], operands[1]);")
2018 [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
2019 (match_operand:DF 1 "reg_or_0_operand" ""))]
2022 "frv_split_double_store (operands[0], operands[1]);")
2025 [(set (match_operand:DF 0 "memory_operand" "")
2026 (match_operand:DF 1 "odd_reg_operand" ""))]
2029 "frv_split_double_store (operands[0], operands[1]);")
2032 [(set (match_operand:DF 0 "register_operand" "")
2033 (match_operand:DF 1 "register_operand" ""))]
2035 && (odd_reg_operand (operands[0], DFmode)
2036 || odd_reg_operand (operands[1], DFmode)
2037 || (integer_register_operand (operands[0], DFmode)
2038 && integer_register_operand (operands[1], DFmode))
2040 && fpr_operand (operands[0], DFmode)
2041 && fpr_operand (operands[1], DFmode)))"
2042 [(set (match_dup 2) (match_dup 4))
2043 (set (match_dup 3) (match_dup 5))]
2046 rtx op0 = operands[0];
2047 rtx op0_low = gen_lowpart (SImode, op0);
2048 rtx op0_high = gen_highpart (SImode, op0);
2049 rtx op1 = operands[1];
2050 rtx op1_low = gen_lowpart (SImode, op1);
2051 rtx op1_high = gen_highpart (SImode, op1);
2053 /* We normally copy the low-numbered register first. However, if the first
2054 register operand 0 is the same as the second register of operand 1, we
2055 must copy in the opposite order. */
2057 if (REGNO (op0_high) == REGNO (op1_low))
2059 operands[2] = op0_low;
2060 operands[3] = op0_high;
2061 operands[4] = op1_low;
2062 operands[5] = op1_high;
2066 operands[2] = op0_high;
2067 operands[3] = op0_low;
2068 operands[4] = op1_high;
2069 operands[5] = op1_low;
2074 [(set (match_operand:DF 0 "register_operand" "")
2075 (match_operand:DF 1 "const_int_operand" ""))]
2077 [(set (match_dup 2) (match_dup 4))
2078 (set (match_dup 3) (match_dup 5))]
2081 rtx op0 = operands[0];
2082 rtx op1 = operands[1];
2084 operands[2] = gen_highpart (SImode, op0);
2085 operands[3] = gen_lowpart (SImode, op0);
2086 if (HOST_BITS_PER_WIDE_INT <= 32)
2088 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
2093 operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
2094 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
2095 - ((unsigned HOST_WIDE_INT)1 << 31));
2096 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
2101 [(set (match_operand:DF 0 "register_operand" "")
2102 (match_operand:DF 1 "const_double_operand" ""))]
2104 [(set (match_dup 2) (match_dup 4))
2105 (set (match_dup 3) (match_dup 5))]
2108 rtx op0 = operands[0];
2109 rtx op1 = operands[1];
2113 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
2114 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2116 operands[2] = gen_highpart (SImode, op0);
2117 operands[3] = gen_lowpart (SImode, op0);
2118 operands[4] = GEN_INT (l[0]);
2119 operands[5] = GEN_INT (l[1]);
2122 ;; String/block move insn.
2123 ;; Argument 0 is the destination
2124 ;; Argument 1 is the source
2125 ;; Argument 2 is the length
2126 ;; Argument 3 is the alignment
2128 (define_expand "movmemsi"
2129 [(parallel [(set (match_operand:BLK 0 "" "")
2130 (match_operand:BLK 1 "" ""))
2131 (use (match_operand:SI 2 "" ""))
2132 (use (match_operand:SI 3 "" ""))])]
2136 if (frv_expand_block_move (operands))
2142 ;; String/block clear insn.
2143 ;; Argument 0 is the destination
2144 ;; Argument 1 is the length
2145 ;; Argument 2 is the alignment
2147 (define_expand "clrmemsi"
2148 [(parallel [(set (match_operand:BLK 0 "" "")
2150 (use (match_operand:SI 1 "" ""))
2151 (use (match_operand:SI 2 "" ""))])]
2155 if (frv_expand_block_clear (operands))
2162 ;; ::::::::::::::::::::
2164 ;; :: Reload CC registers
2166 ;; ::::::::::::::::::::
2168 ;; Use as a define_expand so that cse/gcse/combine can't accidentally
2169 ;; create movcc insns.
2171 (define_expand "movcc"
2172 [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
2173 (match_operand:CC 1 "move_source_operand" ""))
2174 (clobber (match_dup 2))])]
2178 if (! reload_in_progress && ! reload_completed)
2181 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2184 (define_insn "*internal_movcc"
2185 [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
2186 (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
2187 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2188 "reload_in_progress || reload_completed"
2195 [(set_attr "length" "4,4,4,4,20")
2196 (set_attr "type" "int,int,gload,gstore,multi")])
2198 ;; To move an ICC value to a GPR for a signed comparison, we create a value
2199 ;; that when compared to 0, sets the N and Z flags appropriately (we don't care
2200 ;; about the V and C flags, since these comparisons are signed).
2203 [(set (match_operand:CC 0 "integer_register_operand" "")
2204 (match_operand:CC 1 "icc_operand" ""))
2205 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2206 "reload_in_progress || reload_completed"
2210 rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
2211 rtx icc = operands[1];
2212 rtx icr = operands[2];
2216 emit_insn (gen_rtx_SET (VOIDmode, icr,
2217 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2219 emit_insn (gen_movsi (dest, const1_rtx));
2221 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2222 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2223 gen_rtx_SET (VOIDmode, dest,
2224 gen_rtx_NEG (SImode, dest))));
2226 emit_insn (gen_rtx_SET (VOIDmode, icr,
2227 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2229 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2230 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2231 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2233 operands[3] = get_insns ();
2237 (define_expand "reload_incc"
2238 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
2239 (match_operand:CC 1 "memory_operand" "m"))
2240 (clobber (match_scratch:CC_CCR 3 ""))])
2241 (parallel [(set (match_operand:CC 0 "icc_operand" "=t")
2243 (clobber (match_scratch:CC_CCR 4 ""))])]
2247 (define_expand "reload_outcc"
2248 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
2249 (match_operand:CC 1 "icc_operand" "t"))
2250 (clobber (match_dup 3))])
2251 (parallel [(set (match_operand:CC 0 "memory_operand" "=m")
2253 (clobber (match_scratch:CC_CCR 4 ""))])]
2255 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
2257 ;; Reload CC_UNSmode for unsigned integer comparisons
2258 ;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
2260 (define_expand "movcc_uns"
2261 [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
2262 (match_operand:CC_UNS 1 "move_source_operand" ""))
2263 (clobber (match_dup 2))])]
2267 if (! reload_in_progress && ! reload_completed)
2269 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2272 (define_insn "*internal_movcc_uns"
2273 [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
2274 (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
2275 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2276 "reload_in_progress || reload_completed"
2283 [(set_attr "length" "4,4,4,4,20")
2284 (set_attr "type" "int,int,gload,gstore,multi")])
2286 ;; To move an ICC value to a GPR for an unsigned comparison, we create a value
2287 ;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
2288 ;; care about the N flag, since these comparisons are unsigned).
2291 [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
2292 (match_operand:CC_UNS 1 "icc_operand" ""))
2293 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2294 "reload_in_progress || reload_completed"
2298 rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2299 rtx icc = operands[1];
2300 rtx icr = operands[2];
2304 emit_insn (gen_rtx_SET (VOIDmode, icr,
2305 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2307 emit_insn (gen_movsi (dest, const1_rtx));
2309 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2310 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2311 gen_addsi3 (dest, dest, dest)));
2313 emit_insn (gen_rtx_SET (VOIDmode, icr,
2314 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2316 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2317 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2318 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2320 operands[3] = get_insns ();
2324 (define_expand "reload_incc_uns"
2325 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2326 (match_operand:CC_UNS 1 "memory_operand" "m"))
2327 (clobber (match_scratch:CC_CCR 3 ""))])
2328 (parallel [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
2330 (clobber (match_scratch:CC_CCR 4 ""))])]
2334 (define_expand "reload_outcc_uns"
2335 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2336 (match_operand:CC_UNS 1 "icc_operand" "t"))
2337 (clobber (match_dup 3))])
2338 (parallel [(set (match_operand:CC_UNS 0 "memory_operand" "=m")
2340 (clobber (match_scratch:CC_CCR 4 ""))])]
2342 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
2344 ;; Reload CC_NZmode. This is mostly the same as the CCmode and CC_UNSmode
2345 ;; handling, but it uses different sequences for moving between GPRs and ICCs.
2347 (define_expand "movcc_nz"
2348 [(parallel [(set (match_operand:CC_NZ 0 "move_destination_operand" "")
2349 (match_operand:CC_NZ 1 "move_source_operand" ""))
2350 (clobber (match_dup 2))])]
2354 if (!reload_in_progress && !reload_completed)
2356 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2359 (define_insn "*internal_movcc_nz"
2360 [(set (match_operand:CC_NZ 0 "move_destination_operand" "=t,d,d,m,d")
2361 (match_operand:CC_NZ 1 "move_source_operand" "d,d,m,d,t"))
2362 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2363 "reload_in_progress || reload_completed"
2370 [(set_attr "length" "4,4,4,4,20")
2371 (set_attr "type" "int,int,gload,gstore,multi")])
2373 ;; Set the destination to a value that, when compared with zero, will
2374 ;; restore the value of the Z and N flags. The values of the other
2375 ;; flags don't matter. The sequence is:
2379 ;; csub gr0,op0,op0,op2
2383 [(set (match_operand:CC_NZ 0 "integer_register_operand" "")
2384 (match_operand:CC_NZ 1 "icc_operand" ""))
2385 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2386 "reload_in_progress || reload_completed"
2390 (ge:CC_CCR (match_dup 1)
2392 (cond_exec (ne:CC_CCR (match_dup 2)
2395 (neg:SI (match_dup 3))))
2397 (eq:CC_CCR (match_dup 1)
2399 (cond_exec (ne:CC_CCR (match_dup 2)
2401 (set (match_dup 3) (const_int 0)))]
2402 "operands[3] = simplify_gen_subreg (SImode, operands[0], CC_NZmode, 0);")
2404 (define_expand "reload_incc_nz"
2405 [(parallel [(set (match_operand:CC_NZ 2 "integer_register_operand" "=&d")
2406 (match_operand:CC_NZ 1 "memory_operand" "m"))
2407 (clobber (match_scratch:CC_CCR 3 ""))])
2408 (parallel [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
2410 (clobber (match_scratch:CC_CCR 4 ""))])]
2414 (define_expand "reload_outcc_nz"
2415 [(parallel [(set (match_operand:CC_NZ 2 "integer_register_operand" "=&d")
2416 (match_operand:CC_NZ 1 "icc_operand" "t"))
2417 (clobber (match_dup 3))])
2418 (parallel [(set (match_operand:CC_NZ 0 "memory_operand" "=m")
2420 (clobber (match_scratch:CC_CCR 4 ""))])]
2422 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
2424 ;; Reload CC_FPmode for floating point comparisons
2425 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
2426 ;; create movcc insns. If this was a named define_insn, we would not be able
2427 ;; to make it conditional on reload.
2429 (define_expand "movcc_fp"
2430 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "")
2431 (match_operand:CC_FP 1 "move_source_operand" ""))]
2435 if (! reload_in_progress && ! reload_completed)
2439 (define_insn "*movcc_fp_internal"
2440 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "=d,d,d,m")
2441 (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2442 "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2448 [(set_attr "length" "12,4,4,4")
2449 (set_attr "type" "multi,int,gload,gstore")])
2452 (define_expand "reload_incc_fp"
2453 [(match_operand:CC_FP 0 "fcc_operand" "=u")
2454 (match_operand:CC_FP 1 "gpr_or_memory_operand_with_scratch" "m")
2455 (match_operand:TI 2 "integer_register_operand" "=&d")]
2459 rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2460 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2461 rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2462 rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2463 int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2466 if (!gpr_or_memory_operand (operands[1], CC_FPmode))
2469 rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
2471 gcc_assert (GET_CODE (operands[1]) == MEM);
2473 addr = XEXP (operands[1], 0);
2475 gcc_assert (GET_CODE (addr) == PLUS);
2477 emit_move_insn (temp3, XEXP (addr, 1));
2479 operands[1] = replace_equiv_address (operands[1],
2480 gen_rtx_PLUS (GET_MODE (addr),
2485 emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2487 emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2489 mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2490 emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2491 emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2495 (define_expand "reload_outcc_fp"
2496 [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2497 (match_operand:CC_FP 1 "fcc_operand" "u"))
2498 (set (match_operand:CC_FP 0 "memory_operand" "=m")
2503 ;; Convert a FCC value to gpr
2504 (define_insn "read_fcc"
2505 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2506 (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2510 [(set_attr "type" "spr")
2511 (set_attr "length" "4")])
2514 [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2515 (match_operand:CC_FP 1 "fcc_operand" ""))]
2516 "reload_completed && TARGET_HAS_FPRS"
2520 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2521 int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2525 emit_insn (gen_read_fcc (int_op0, operands[1]));
2527 emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2529 emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2531 operands[2] = get_insns ();
2535 ;; Move a gpr value to FCC.
2537 ;; Operand1 = reloaded value shifted appropriately
2538 ;; Operand2 = mask to eliminate current register
2539 ;; Operand3 = temporary to load/store ccr
2540 (define_insn "update_fcc"
2541 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2542 (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2543 (match_operand:SI 2 "integer_register_operand" "d")]
2545 (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2547 "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2548 [(set_attr "type" "multi")
2549 (set_attr "length" "16")])
2551 ;; Reload CC_CCRmode for conditional execution registers
2552 (define_insn "movcc_ccr"
2553 [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2554 (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2565 [(set_attr "length" "8,4,4,4,8,12,4,4")
2566 (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2568 (define_expand "reload_incc_ccr"
2569 [(match_operand:CC_CCR 0 "cr_operand" "=C")
2570 (match_operand:CC_CCR 1 "memory_operand" "m")
2571 (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2575 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2576 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2577 rtx icr = (ICR_P (REGNO (operands[0]))
2578 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2580 emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2581 emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2582 emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2584 if (! ICR_P (REGNO (operands[0])))
2585 emit_insn (gen_movcc_ccr (operands[0], icr));
2590 (define_expand "reload_outcc_ccr"
2591 [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2592 (match_operand:CC_CCR 1 "cr_operand" "C"))
2593 (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2599 [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2600 (match_operand:CC_CCR 1 "cr_operand" ""))]
2605 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2608 emit_move_insn (operands[0], const1_rtx);
2609 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2610 gen_rtx_EQ (CC_CCRmode,
2613 gen_rtx_SET (VOIDmode, int_op0,
2616 operands[2] = get_insns ();
2621 [(set (match_operand:CC_CCR 0 "cr_operand" "")
2622 (match_operand:CC_CCR 1 "const_int_operand" ""))]
2627 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2628 rtx r0 = gen_rtx_REG (SImode, GPR_FIRST);
2629 rtx icr = (ICR_P (REGNO (operands[0]))
2630 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2634 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2636 emit_insn (gen_movcc_ccr (icr,
2637 gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2638 ? EQ : NE), CC_CCRmode,
2641 if (! ICR_P (REGNO (operands[0])))
2642 emit_insn (gen_movcc_ccr (operands[0], icr));
2644 operands[2] = get_insns ();
2649 ;; ::::::::::::::::::::
2653 ;; ::::::::::::::::::::
2655 ;; Signed conversions from a smaller integer to a larger integer
2657 ;; These operations are optional. If they are not
2658 ;; present GCC will synthesize them for itself
2659 ;; Even though frv does not provide these instructions, we define them
2660 ;; to allow load + sign extend to be collapsed together
2661 (define_insn "extendqihi2"
2662 [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2663 (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2668 [(set_attr "length" "8,4")
2669 (set_attr "type" "multi,gload")])
2672 [(set (match_operand:HI 0 "integer_register_operand" "")
2673 (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2679 rtx op0 = gen_lowpart (SImode, operands[0]);
2680 rtx op1 = gen_lowpart (SImode, operands[1]);
2681 rtx shift = GEN_INT (24);
2683 operands[2] = gen_ashlsi3 (op0, op1, shift);
2684 operands[3] = gen_ashrsi3 (op0, op0, shift);
2687 (define_insn "extendqisi2"
2688 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2689 (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2694 [(set_attr "length" "8,4")
2695 (set_attr "type" "multi,gload")])
2698 [(set (match_operand:SI 0 "integer_register_operand" "")
2699 (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2705 rtx op0 = gen_lowpart (SImode, operands[0]);
2706 rtx op1 = gen_lowpart (SImode, operands[1]);
2707 rtx shift = GEN_INT (24);
2709 operands[2] = gen_ashlsi3 (op0, op1, shift);
2710 operands[3] = gen_ashrsi3 (op0, op0, shift);
2713 ;;(define_insn "extendqidi2"
2714 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2715 ;; (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2717 ;; "extendqihi2 %0,%1"
2718 ;; [(set_attr "length" "4")])
2720 (define_insn "extendhisi2"
2721 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2722 (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2727 [(set_attr "length" "8,4")
2728 (set_attr "type" "multi,gload")])
2731 [(set (match_operand:SI 0 "integer_register_operand" "")
2732 (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2738 rtx op0 = gen_lowpart (SImode, operands[0]);
2739 rtx op1 = gen_lowpart (SImode, operands[1]);
2740 rtx shift = GEN_INT (16);
2742 operands[2] = gen_ashlsi3 (op0, op1, shift);
2743 operands[3] = gen_ashrsi3 (op0, op0, shift);
2746 ;;(define_insn "extendhidi2"
2747 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2748 ;; (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2750 ;; "extendhihi2 %0,%1"
2751 ;; [(set_attr "length" "4")])
2753 ;;(define_insn "extendsidi2"
2754 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2755 ;; (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2757 ;; "extendsidi2 %0,%1"
2758 ;; [(set_attr "length" "4")])
2760 ;; Unsigned conversions from a smaller integer to a larger integer
2761 (define_insn "zero_extendqihi2"
2762 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2764 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2770 [(set_attr "length" "4")
2771 (set_attr "type" "int,int,gload")])
2773 (define_insn "zero_extendqisi2"
2774 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2776 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2782 [(set_attr "length" "4")
2783 (set_attr "type" "int,int,gload")])
2785 ;;(define_insn "zero_extendqidi2"
2786 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2787 ;; (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2789 ;; "zero_extendqihi2 %0,%1"
2790 ;; [(set_attr "length" "4")])
2792 ;; Do not set the type for the sethi to "sethi", since the scheduler will think
2793 ;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2794 ;; VLIW instruction.
2795 (define_insn "zero_extendhisi2"
2796 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2797 (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2802 [(set_attr "length" "4")
2803 (set_attr "type" "int,gload")])
2805 ;;(define_insn "zero_extendhidi2"
2806 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2807 ;; (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2809 ;; "zero_extendhihi2 %0,%1"
2810 ;; [(set_attr "length" "4")])
2812 ;;(define_insn "zero_extendsidi2"
2813 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2814 ;; (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2816 ;; "zero_extendsidi2 %0,%1"
2817 ;; [(set_attr "length" "4")])
2819 ;;;; Convert between floating point types of different sizes.
2821 ;;(define_insn "extendsfdf2"
2822 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2823 ;; (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2825 ;; "extendsfdf2 %0,%1"
2826 ;; [(set_attr "length" "4")])
2828 ;;(define_insn "truncdfsf2"
2829 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2830 ;; (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2832 ;; "truncdfsf2 %0,%1"
2833 ;; [(set_attr "length" "4")])
2835 ;;;; Convert between signed integer types and floating point.
2836 (define_insn "floatsisf2"
2837 [(set (match_operand:SF 0 "fpr_operand" "=f")
2838 (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2841 [(set_attr "length" "4")
2842 (set_attr "type" "fsconv")])
2844 (define_insn "floatsidf2"
2845 [(set (match_operand:DF 0 "fpr_operand" "=h")
2846 (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2847 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2849 [(set_attr "length" "4")
2850 (set_attr "type" "fdconv")])
2852 ;;(define_insn "floatdisf2"
2853 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2854 ;; (float:SF (match_operand:DI 1 "register_operand" "r")))]
2856 ;; "floatdisf2 %0,%1"
2857 ;; [(set_attr "length" "4")])
2859 ;;(define_insn "floatdidf2"
2860 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2861 ;; (float:DF (match_operand:DI 1 "register_operand" "r")))]
2863 ;; "floatdidf2 %0,%1"
2864 ;; [(set_attr "length" "4")])
2866 (define_insn "fix_truncsfsi2"
2867 [(set (match_operand:SI 0 "fpr_operand" "=f")
2868 (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2871 [(set_attr "length" "4")
2872 (set_attr "type" "fsconv")])
2874 (define_insn "fix_truncdfsi2"
2875 [(set (match_operand:SI 0 "fpr_operand" "=f")
2876 (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2877 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2879 [(set_attr "length" "4")
2880 (set_attr "type" "fdconv")])
2882 ;;(define_insn "fix_truncsfdi2"
2883 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2884 ;; (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2886 ;; "fix_truncsfdi2 %0,%1"
2887 ;; [(set_attr "length" "4")])
2889 ;;(define_insn "fix_truncdfdi2"
2890 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2891 ;; (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2893 ;; "fix_truncdfdi2 %0,%1"
2894 ;; [(set_attr "length" "4")])
2896 ;;;; Convert between unsigned integer types and floating point.
2898 ;;(define_insn "floatunssisf2"
2899 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2900 ;; (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2902 ;; "floatunssisf2 %0,%1"
2903 ;; [(set_attr "length" "4")])
2905 ;;(define_insn "floatunssidf2"
2906 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2907 ;; (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2909 ;; "floatunssidf2 %0,%1"
2910 ;; [(set_attr "length" "4")])
2912 ;;(define_insn "floatunsdisf2"
2913 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2914 ;; (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2916 ;; "floatunsdisf2 %0,%1"
2917 ;; [(set_attr "length" "4")])
2919 ;;(define_insn "floatunsdidf2"
2920 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2921 ;; (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2923 ;; "floatunsdidf2 %0,%1"
2924 ;; [(set_attr "length" "4")])
2926 ;;(define_insn "fixuns_truncsfsi2"
2927 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2928 ;; (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2930 ;; "fixuns_truncsfsi2 %0,%1"
2931 ;; [(set_attr "length" "4")])
2933 ;;(define_insn "fixuns_truncdfsi2"
2934 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2935 ;; (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2937 ;; "fixuns_truncdfsi2 %0,%1"
2938 ;; [(set_attr "length" "4")])
2940 ;;(define_insn "fixuns_truncsfdi2"
2941 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2942 ;; (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2944 ;; "fixuns_truncsfdi2 %0,%1"
2945 ;; [(set_attr "length" "4")])
2947 ;;(define_insn "fixuns_truncdfdi2"
2948 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2949 ;; (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2951 ;; "fixuns_truncdfdi2 %0,%1"
2952 ;; [(set_attr "length" "4")])
2955 ;; ::::::::::::::::::::
2957 ;; :: 32 bit Integer arithmetic
2959 ;; ::::::::::::::::::::
2962 (define_insn "addsi3"
2963 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2964 (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2965 (match_operand:SI 2 "gpr_or_int12_operand" "dNOPQ")))]
2968 [(set_attr "length" "4")
2969 (set_attr "type" "int")])
2971 ;; Subtraction. No need to worry about constants, since the compiler
2972 ;; canonicalizes them into addsi3's. We prevent SUBREG's here to work around a
2973 ;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2974 ;; SUBREG with a minus that shows up in modulus by constants.
2975 (define_insn "subsi3"
2976 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2977 (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2978 (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2981 [(set_attr "length" "4")
2982 (set_attr "type" "int")])
2984 ;; Signed multiplication producing 64 bit results from 32 bit inputs
2985 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2986 ;; will do the 32x32->64 bit multiply and use the bottom word.
2987 (define_expand "mulsidi3"
2988 [(set (match_operand:DI 0 "integer_register_operand" "")
2989 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2990 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2994 if (GET_CODE (operands[2]) == CONST_INT)
2996 emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
3001 (define_insn "*mulsidi3_reg"
3002 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3003 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
3004 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
3007 [(set_attr "length" "4")
3008 (set_attr "type" "mul")])
3010 (define_insn "mulsidi3_const"
3011 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3012 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
3013 (match_operand:SI 2 "int12_operand" "NOP")))]
3016 [(set_attr "length" "4")
3017 (set_attr "type" "mul")])
3019 ;; Unsigned multiplication producing 64 bit results from 32 bit inputs
3020 (define_expand "umulsidi3"
3021 [(set (match_operand:DI 0 "even_gpr_operand" "")
3022 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
3023 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
3027 if (GET_CODE (operands[2]) == CONST_INT)
3029 emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
3034 (define_insn "*mulsidi3_reg"
3035 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3036 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
3037 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
3040 [(set_attr "length" "4")
3041 (set_attr "type" "mul")])
3043 (define_insn "umulsidi3_const"
3044 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3045 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
3046 (match_operand:SI 2 "int12_operand" "NOP")))]
3049 [(set_attr "length" "4")
3050 (set_attr "type" "mul")])
3053 (define_insn "divsi3"
3054 [(set (match_operand:SI 0 "register_operand" "=d,d")
3055 (div:SI (match_operand:SI 1 "register_operand" "d,d")
3056 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3059 [(set_attr "length" "4")
3060 (set_attr "type" "div")])
3062 ;; Unsigned Division
3063 (define_insn "udivsi3"
3064 [(set (match_operand:SI 0 "register_operand" "=d,d")
3065 (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
3066 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3069 [(set_attr "length" "4")
3070 (set_attr "type" "div")])
3073 (define_insn "negsi2"
3074 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3075 (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3078 [(set_attr "length" "4")
3079 (set_attr "type" "int")])
3081 ;; Find first one bit
3082 ;; (define_insn "ffssi2"
3083 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3084 ;; (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
3087 ;; [(set_attr "length" "4")])
3090 ;; ::::::::::::::::::::
3092 ;; :: 64 bit Integer arithmetic
3094 ;; ::::::::::::::::::::
3097 (define_insn_and_split "adddi3"
3098 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3099 (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0")
3100 (match_operand:DI 2 "gpr_or_int10_operand" "eJ,eJ")))
3101 (clobber (match_scratch:CC 3 "=t,t"))]
3112 for (op = 0; op < 3; op++)
3113 for (part = 0; part < 2; part++)
3114 parts[op][part] = simplify_gen_subreg (SImode, operands[op],
3115 DImode, part * UNITS_PER_WORD);
3117 operands[4] = gen_adddi3_lower (parts[0][1], parts[1][1], parts[2][1],
3119 operands[5] = gen_adddi3_upper (parts[0][0], parts[1][0], parts[2][0],
3120 copy_rtx (operands[3]));
3122 [(set_attr "length" "8")
3123 (set_attr "type" "multi")])
3125 ;; Subtraction No need to worry about constants, since the compiler
3126 ;; canonicalizes them into adddi3's.
3127 (define_insn_and_split "subdi3"
3128 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
3129 (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
3130 (match_operand:DI 2 "integer_register_operand" "e,e,0")))
3131 (clobber (match_scratch:CC 3 "=t,t,t"))]
3139 rtx op0_high = gen_highpart (SImode, operands[0]);
3140 rtx op1_high = gen_highpart (SImode, operands[1]);
3141 rtx op2_high = gen_highpart (SImode, operands[2]);
3142 rtx op0_low = gen_lowpart (SImode, operands[0]);
3143 rtx op1_low = gen_lowpart (SImode, operands[1]);
3144 rtx op2_low = gen_lowpart (SImode, operands[2]);
3145 rtx op3 = operands[3];
3147 operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3148 operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3150 [(set_attr "length" "8")
3151 (set_attr "type" "multi")])
3153 ;; Patterns for addsi3/subdi3 after splitting
3154 (define_insn "adddi3_lower"
3155 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3156 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3157 (match_operand:SI 2 "gpr_or_int10_operand" "dJ")))
3158 (set (match_operand:CC 3 "icc_operand" "=t")
3159 (compare:CC (plus:SI (match_dup 1)
3163 "add%I2cc %1,%2,%0,%3"
3164 [(set_attr "length" "4")
3165 (set_attr "type" "int")])
3167 (define_insn "adddi3_upper"
3168 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3169 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3170 (plus:SI (match_operand:SI 2 "gpr_or_int10_operand" "dJ")
3171 (match_operand:CC 3 "icc_operand" "t"))))]
3173 "addx%I2 %1,%2,%0,%3"
3174 [(set_attr "length" "4")
3175 (set_attr "type" "int")])
3177 (define_insn "subdi3_lower"
3178 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3179 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3180 (match_operand:SI 2 "integer_register_operand" "d")))
3181 (set (match_operand:CC 3 "icc_operand" "=t")
3182 (compare:CC (plus:SI (match_dup 1)
3187 [(set_attr "length" "4")
3188 (set_attr "type" "int")])
3190 (define_insn "subdi3_upper"
3191 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3192 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3193 (minus:SI (match_operand:SI 2 "integer_register_operand" "d")
3194 (match_operand:CC 3 "icc_operand" "t"))))]
3197 [(set_attr "length" "4")
3198 (set_attr "type" "int")])
3200 (define_insn_and_split "negdi2"
3201 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3202 (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0")))
3203 (clobber (match_scratch:CC 2 "=t,t"))]
3211 rtx op0_high = gen_highpart (SImode, operands[0]);
3212 rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST);
3213 rtx op2_high = gen_highpart (SImode, operands[1]);
3214 rtx op0_low = gen_lowpart (SImode, operands[0]);
3215 rtx op1_low = op1_high;
3216 rtx op2_low = gen_lowpart (SImode, operands[1]);
3217 rtx op3 = operands[2];
3219 operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3220 operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3222 [(set_attr "length" "8")
3223 (set_attr "type" "multi")])
3225 ;; Multiplication (same size)
3226 ;; (define_insn "muldi3"
3227 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3228 ;; (mult:DI (match_operand:DI 1 "register_operand" "%r")
3229 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3231 ;; "muldi3 %0,%1,%2"
3232 ;; [(set_attr "length" "4")])
3235 ;; (define_insn "divdi3"
3236 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3237 ;; (div:DI (match_operand:DI 1 "register_operand" "r")
3238 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3240 ;; "divdi3 %0,%1,%2"
3241 ;; [(set_attr "length" "4")])
3243 ;; Undsgned Division
3244 ;; (define_insn "udivdi3"
3245 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3246 ;; (udiv:DI (match_operand:DI 1 "register_operand" "r")
3247 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3249 ;; "udivdi3 %0,%1,%2"
3250 ;; [(set_attr "length" "4")])
3253 ;; (define_insn "negdi2"
3254 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3255 ;; (neg:DI (match_operand:DI 1 "register_operand" "r")))]
3258 ;; [(set_attr "length" "4")])
3260 ;; Find first one bit
3261 ;; (define_insn "ffsdi2"
3262 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3263 ;; (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
3266 ;; [(set_attr "length" "4")])
3269 ;; ::::::::::::::::::::
3271 ;; :: 32 bit floating point arithmetic
3273 ;; ::::::::::::::::::::
3276 (define_insn "addsf3"
3277 [(set (match_operand:SF 0 "fpr_operand" "=f")
3278 (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
3279 (match_operand:SF 2 "fpr_operand" "f")))]
3282 [(set_attr "length" "4")
3283 (set_attr "type" "fsadd")])
3286 (define_insn "subsf3"
3287 [(set (match_operand:SF 0 "fpr_operand" "=f")
3288 (minus:SF (match_operand:SF 1 "fpr_operand" "f")
3289 (match_operand:SF 2 "fpr_operand" "f")))]
3292 [(set_attr "length" "4")
3293 (set_attr "type" "fsadd")])
3296 (define_insn "mulsf3"
3297 [(set (match_operand:SF 0 "fpr_operand" "=f")
3298 (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3299 (match_operand:SF 2 "fpr_operand" "f")))]
3302 [(set_attr "length" "4")
3303 (set_attr "type" "fsmul")])
3305 ;; Multiplication with addition/subtraction
3306 (define_insn "*muladdsf4"
3307 [(set (match_operand:SF 0 "fpr_operand" "=f")
3308 (plus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3309 (match_operand:SF 2 "fpr_operand" "f"))
3310 (match_operand:SF 3 "fpr_operand" "0")))]
3311 "TARGET_HARD_FLOAT && TARGET_MULADD"
3313 [(set_attr "length" "4")
3314 (set_attr "type" "fsmadd")])
3316 (define_insn "*mulsubsf4"
3317 [(set (match_operand:SF 0 "fpr_operand" "=f")
3318 (minus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3319 (match_operand:SF 2 "fpr_operand" "f"))
3320 (match_operand:SF 3 "fpr_operand" "0")))]
3321 "TARGET_HARD_FLOAT && TARGET_MULADD"
3323 [(set_attr "length" "4")
3324 (set_attr "type" "fsmadd")])
3327 (define_insn "divsf3"
3328 [(set (match_operand:SF 0 "fpr_operand" "=f")
3329 (div:SF (match_operand:SF 1 "fpr_operand" "f")
3330 (match_operand:SF 2 "fpr_operand" "f")))]
3333 [(set_attr "length" "4")
3334 (set_attr "type" "fsdiv")])
3337 (define_insn "negsf2"
3338 [(set (match_operand:SF 0 "fpr_operand" "=f")
3339 (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
3342 [(set_attr "length" "4")
3343 (set_attr "type" "fsconv")])
3346 (define_insn "abssf2"
3347 [(set (match_operand:SF 0 "fpr_operand" "=f")
3348 (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
3351 [(set_attr "length" "4")
3352 (set_attr "type" "fsconv")])
3355 (define_insn "sqrtsf2"
3356 [(set (match_operand:SF 0 "fpr_operand" "=f")
3357 (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
3360 [(set_attr "length" "4")
3361 (set_attr "type" "sqrt_single")])
3364 ;; ::::::::::::::::::::
3366 ;; :: 64 bit floating point arithmetic
3368 ;; ::::::::::::::::::::
3371 (define_insn "adddf3"
3372 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3373 (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
3374 (match_operand:DF 2 "fpr_operand" "h")))]
3375 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3377 [(set_attr "length" "4")
3378 (set_attr "type" "fdadd")])
3381 (define_insn "subdf3"
3382 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3383 (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3384 (match_operand:DF 2 "fpr_operand" "h")))]
3385 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3387 [(set_attr "length" "4")
3388 (set_attr "type" "fdadd")])
3391 (define_insn "muldf3"
3392 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3393 (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3394 (match_operand:DF 2 "fpr_operand" "h")))]
3395 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3397 [(set_attr "length" "4")
3398 (set_attr "type" "fdmul")])
3400 ;; Multiplication with addition/subtraction
3401 (define_insn "*muladddf4"
3402 [(set (match_operand:DF 0 "fpr_operand" "=f")
3403 (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3404 (match_operand:DF 2 "fpr_operand" "f"))
3405 (match_operand:DF 3 "fpr_operand" "0")))]
3406 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3408 [(set_attr "length" "4")
3409 (set_attr "type" "fdmadd")])
3411 (define_insn "*mulsubdf4"
3412 [(set (match_operand:DF 0 "fpr_operand" "=f")
3413 (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3414 (match_operand:DF 2 "fpr_operand" "f"))
3415 (match_operand:DF 3 "fpr_operand" "0")))]
3416 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3418 [(set_attr "length" "4")
3419 (set_attr "type" "fdmadd")])
3422 (define_insn "divdf3"
3423 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3424 (div:DF (match_operand:DF 1 "fpr_operand" "h")
3425 (match_operand:DF 2 "fpr_operand" "h")))]
3426 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3428 [(set_attr "length" "4")
3429 (set_attr "type" "fddiv")])
3432 (define_insn "negdf2"
3433 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3434 (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3435 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3437 [(set_attr "length" "4")
3438 (set_attr "type" "fdconv")])
3441 (define_insn "absdf2"
3442 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3443 (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3444 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3446 [(set_attr "length" "4")
3447 (set_attr "type" "fdconv")])
3450 (define_insn "sqrtdf2"
3451 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3452 (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3453 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3455 [(set_attr "length" "4")
3456 (set_attr "type" "sqrt_double")])
3459 ;; ::::::::::::::::::::
3461 ;; :: 32 bit Integer Shifts and Rotates
3463 ;; ::::::::::::::::::::
3465 ;; Arithmetic Shift Left
3466 (define_insn "ashlsi3"
3467 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3468 (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3469 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3472 [(set_attr "length" "4")
3473 (set_attr "type" "int")])
3475 ;; Arithmetic Shift Right
3476 (define_insn "ashrsi3"
3477 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3478 (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3479 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3482 [(set_attr "length" "4")
3483 (set_attr "type" "int")])
3485 ;; Logical Shift Right
3486 (define_insn "lshrsi3"
3487 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3488 (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3489 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3492 [(set_attr "length" "4")
3493 (set_attr "type" "int")])
3496 ;; (define_insn "rotlsi3"
3497 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3498 ;; (rotate:SI (match_operand:SI 1 "register_operand" "r")
3499 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3501 ;; "rotlsi3 %0,%1,%2"
3502 ;; [(set_attr "length" "4")])
3505 ;; (define_insn "rotrsi3"
3506 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3507 ;; (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3508 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3510 ;; "rotrsi3 %0,%1,%2"
3511 ;; [(set_attr "length" "4")])
3514 ;; ::::::::::::::::::::
3516 ;; :: 64 bit Integer Shifts and Rotates
3518 ;; ::::::::::::::::::::
3520 ;; Arithmetic Shift Left
3521 ;; (define_insn "ashldi3"
3522 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3523 ;; (ashift:DI (match_operand:DI 1 "register_operand" "r")
3524 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3526 ;; "ashldi3 %0,%1,%2"
3527 ;; [(set_attr "length" "4")])
3529 ;; Arithmetic Shift Right
3530 ;; (define_insn "ashrdi3"
3531 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3532 ;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3533 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3535 ;; "ashrdi3 %0,%1,%2"
3536 ;; [(set_attr "length" "4")])
3538 ;; Logical Shift Right
3539 ;; (define_insn "lshrdi3"
3540 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3541 ;; (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3542 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3544 ;; "lshrdi3 %0,%1,%2"
3545 ;; [(set_attr "length" "4")])
3548 ;; (define_insn "rotldi3"
3549 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3550 ;; (rotate:DI (match_operand:DI 1 "register_operand" "r")
3551 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3553 ;; "rotldi3 %0,%1,%2"
3554 ;; [(set_attr "length" "4")])
3557 ;; (define_insn "rotrdi3"
3558 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3559 ;; (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3560 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3562 ;; "rotrdi3 %0,%1,%2"
3563 ;; [(set_attr "length" "4")])
3566 ;; ::::::::::::::::::::
3568 ;; :: 32 Bit Integer Logical operations
3570 ;; ::::::::::::::::::::
3572 ;; Logical AND, 32 bit integers
3573 (define_insn "andsi3_media"
3574 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3575 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3576 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3581 [(set_attr "length" "4")
3582 (set_attr "type" "int,mlogic")])
3584 (define_insn "andsi3_nomedia"
3585 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3586 (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3587 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3590 [(set_attr "length" "4")
3591 (set_attr "type" "int")])
3593 (define_expand "andsi3"
3594 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3595 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3596 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3600 ;; Inclusive OR, 32 bit integers
3601 (define_insn "iorsi3_media"
3602 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3603 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3604 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3609 [(set_attr "length" "4")
3610 (set_attr "type" "int,mlogic")])
3612 (define_insn "iorsi3_nomedia"
3613 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3614 (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3615 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3618 [(set_attr "length" "4")
3619 (set_attr "type" "int")])
3621 (define_expand "iorsi3"
3622 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3623 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3624 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3628 ;; Exclusive OR, 32 bit integers
3629 (define_insn "xorsi3_media"
3630 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3631 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3632 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3637 [(set_attr "length" "4")
3638 (set_attr "type" "int,mlogic")])
3640 (define_insn "xorsi3_nomedia"
3641 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3642 (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3643 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3646 [(set_attr "length" "4")
3647 (set_attr "type" "int")])
3649 (define_expand "xorsi3"
3650 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3651 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3652 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3656 ;; One's complement, 32 bit integers
3657 (define_insn "one_cmplsi2_media"
3658 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3659 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3664 [(set_attr "length" "4")
3665 (set_attr "type" "int,mlogic")])
3667 (define_insn "one_cmplsi2_nomedia"
3668 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3669 (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3672 [(set_attr "length" "4")
3673 (set_attr "type" "int")])
3675 (define_expand "one_cmplsi2"
3676 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3677 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3682 ;; ::::::::::::::::::::
3684 ;; :: 64 Bit Integer Logical operations
3686 ;; ::::::::::::::::::::
3688 ;; Logical AND, 64 bit integers
3689 ;; (define_insn "anddi3"
3690 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3691 ;; (and:DI (match_operand:DI 1 "register_operand" "%r")
3692 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3694 ;; "anddi3 %0,%1,%2"
3695 ;; [(set_attr "length" "4")])
3697 ;; Inclusive OR, 64 bit integers
3698 ;; (define_insn "iordi3"
3699 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3700 ;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
3701 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3703 ;; "iordi3 %0,%1,%2"
3704 ;; [(set_attr "length" "4")])
3706 ;; Exclusive OR, 64 bit integers
3707 ;; (define_insn "xordi3"
3708 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3709 ;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
3710 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3712 ;; "xordi3 %0,%1,%2"
3713 ;; [(set_attr "length" "4")])
3715 ;; One's complement, 64 bit integers
3716 ;; (define_insn "one_cmpldi2"
3717 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3718 ;; (not:DI (match_operand:DI 1 "register_operand" "r")))]
3721 ;; [(set_attr "length" "4")])
3724 ;; ::::::::::::::::::::
3726 ;; :: Combination of integer operation with comparison
3728 ;; ::::::::::::::::::::
3730 (define_insn "*combo_intop_compare1"
3731 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3733 (match_operator:SI 1 "intop_compare_operator"
3734 [(match_operand:SI 2 "integer_register_operand" "d")
3735 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3738 "%O1%I3cc %2, %3, %., %0"
3739 [(set_attr "type" "int")
3740 (set_attr "length" "4")])
3742 (define_insn "*combo_intop_compare2"
3743 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3745 (match_operator:SI 1 "intop_compare_operator"
3746 [(match_operand:SI 2 "integer_register_operand" "d")
3747 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3749 (set (match_operand:SI 4 "integer_register_operand" "=d")
3750 (match_operator:SI 5 "intop_compare_operator"
3753 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3754 "%O1%I3cc %2, %3, %4, %0"
3755 [(set_attr "type" "int")
3756 (set_attr "length" "4")])
3758 ;; ::::::::::::::::::::
3762 ;; ::::::::::::::::::::
3764 ;; Note, we store the operands in the comparison insns, and use them later
3765 ;; when generating the branch or scc operation.
3767 ;; First the routines called by the machine independent part of the compiler
3768 (define_expand "cmpsi"
3770 (compare (match_operand:SI 0 "integer_register_operand" "")
3771 (match_operand:SI 1 "gpr_or_int10_operand" "")))]
3775 frv_compare_op0 = operands[0];
3776 frv_compare_op1 = operands[1];
3780 ;(define_expand "cmpdi"
3782 ; (compare (match_operand:DI 0 "register_operand" "")
3783 ; (match_operand:DI 1 "nonmemory_operand" "")))]
3787 ; frv_compare_op0 = operands[0];
3788 ; frv_compare_op1 = operands[1];
3792 (define_expand "cmpsf"
3794 (compare (match_operand:SF 0 "fpr_operand" "")
3795 (match_operand:SF 1 "fpr_operand" "")))]
3799 frv_compare_op0 = operands[0];
3800 frv_compare_op1 = operands[1];
3804 (define_expand "cmpdf"
3806 (compare (match_operand:DF 0 "fpr_operand" "")
3807 (match_operand:DF 1 "fpr_operand" "")))]
3808 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3811 frv_compare_op0 = operands[0];
3812 frv_compare_op1 = operands[1];
3816 ;; Now, the actual comparisons, generated by the branch and/or scc operations
3818 (define_insn "cmpsi_cc"
3819 [(set (match_operand:CC 0 "icc_operand" "=t,t")
3820 (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3821 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3824 [(set_attr "length" "4")
3825 (set_attr "type" "int")])
3827 (define_insn "*cmpsi_cc_uns"
3828 [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3829 (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3830 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3833 [(set_attr "length" "4")
3834 (set_attr "type" "int")])
3836 ;; The only requirement for a CC_NZmode GPR or memory value is that
3837 ;; comparing it against zero must set the Z and N flags appropriately.
3838 ;; The source operand is therefore a valid CC_NZmode value.
3839 (define_insn "*cmpsi_cc_nz"
3840 [(set (match_operand:CC_NZ 0 "nonimmediate_operand" "=t,d,m")
3841 (compare:CC_NZ (match_operand:SI 1 "integer_register_operand" "d,d,d")
3848 [(set_attr "length" "4,4,4")
3849 (set_attr "type" "int,int,gstore")])
3851 (define_insn "*cmpsf_cc_fp"
3852 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3853 (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3854 (match_operand:SF 2 "fpr_operand" "f")))]
3857 [(set_attr "length" "4")
3858 (set_attr "type" "fscmp")])
3860 (define_insn "*cmpdf_cc_fp"
3861 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3862 (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3863 (match_operand:DF 2 "even_fpr_operand" "h")))]
3864 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3866 [(set_attr "length" "4")
3867 (set_attr "type" "fdcmp")])
3870 ;; ::::::::::::::::::::
3874 ;; ::::::::::::::::::::
3876 ;; Define_expands called by the machine independent part of the compiler
3877 ;; to allocate a new comparison register. Each of these named patterns
3878 ;; must be present, and they cannot be amalgamated into one pattern.
3880 ;; If a fixed condition code register is being used, (as opposed to, say,
3881 ;; using cc0), then the expands should look like this:
3883 ;; (define_expand "<name_of_test>"
3884 ;; [(set (reg:CC <number_of_CC_register>)
3885 ;; (compare:CC (match_dup 1)
3888 ;; (if_then_else (eq:CC (reg:CC <number_of_CC_register>)
3890 ;; (label_ref (match_operand 0 "" ""))
3894 ;; operands[1] = frv_compare_op0;
3895 ;; operands[2] = frv_compare_op1;
3899 (define_expand "beq"
3900 [(use (match_operand 0 "" ""))]
3904 if (! frv_emit_cond_branch (EQ, operands[0]))
3910 (define_expand "bne"
3911 [(use (match_operand 0 "" ""))]
3915 if (! frv_emit_cond_branch (NE, operands[0]))
3921 (define_expand "blt"
3922 [(use (match_operand 0 "" ""))]
3926 if (! frv_emit_cond_branch (LT, operands[0]))
3932 (define_expand "ble"
3933 [(use (match_operand 0 "" ""))]
3937 if (! frv_emit_cond_branch (LE, operands[0]))
3943 (define_expand "bgt"
3944 [(use (match_operand 0 "" ""))]
3948 if (! frv_emit_cond_branch (GT, operands[0]))
3954 (define_expand "bge"
3955 [(use (match_operand 0 "" ""))]
3959 if (! frv_emit_cond_branch (GE, operands[0]))
3965 (define_expand "bltu"
3966 [(use (match_operand 0 "" ""))]
3970 if (! frv_emit_cond_branch (LTU, operands[0]))
3976 (define_expand "bleu"
3977 [(use (match_operand 0 "" ""))]
3981 if (! frv_emit_cond_branch (LEU, operands[0]))
3987 (define_expand "bgtu"
3988 [(use (match_operand 0 "" ""))]
3992 if (! frv_emit_cond_branch (GTU, operands[0]))
3998 (define_expand "bgeu"
3999 [(use (match_operand 0 "" ""))]
4003 if (! frv_emit_cond_branch (GEU, operands[0]))
4009 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
4010 ;; swapped. If they are swapped, it reverses the sense of the branch.
4012 ;; Note - unlike the define expands above, these patterns can be amalgamated
4013 ;; into one pattern for branch-if-true and one for branch-if-false. This does
4014 ;; require an operand operator to select the correct branch mnemonic.
4016 ;; If a fixed condition code register is being used, (as opposed to, say,
4017 ;; using cc0), then the expands could look like this:
4019 ;; (define_insn "*branch_true"
4021 ;; (if_then_else (match_operator:CC 0 "comparison_operator"
4022 ;; [(reg:CC <number_of_CC_register>)
4024 ;; (label_ref (match_operand 1 "" ""))
4028 ;; [(set_attr "length" "4")]
4031 ;; In the above example the %B is a directive to frv_print_operand()
4032 ;; to decode and print the correct branch mnemonic.
4034 (define_insn "*branch_int_true"
4036 (if_then_else (match_operator 0 "integer_relational_operator"
4037 [(match_operand 1 "icc_operand" "t")
4039 (label_ref (match_operand 2 "" ""))
4044 if (get_attr_length (insn) == 4)
4045 return \"b%c0 %1,%#,%l2\";
4047 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
4049 [(set (attr "length")
4051 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4052 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4055 (set (attr "far_jump")
4057 (eq_attr "length" "4")
4059 (const_string "yes")))
4062 (eq_attr "length" "4")
4063 (const_string "branch")
4064 (const_string "multi")))])
4066 (define_insn "*branch_int_false"
4068 (if_then_else (match_operator 0 "integer_relational_operator"
4069 [(match_operand 1 "icc_operand" "t")
4072 (label_ref (match_operand 2 "" ""))))]
4076 if (get_attr_length (insn) == 4)
4077 return \"b%C0 %1,%#,%l2\";
4079 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
4081 [(set (attr "length")
4083 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4084 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4087 (set (attr "far_jump")
4089 (eq_attr "length" "4")
4091 (const_string "yes")))
4094 (eq_attr "length" "4")
4095 (const_string "branch")
4096 (const_string "multi")))])
4098 (define_insn "*branch_fp_true"
4100 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
4101 [(match_operand 1 "fcc_operand" "u")
4103 (label_ref (match_operand 2 "" ""))
4108 if (get_attr_length (insn) == 4)
4109 return \"fb%f0 %1,%#,%l2\";
4111 return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
4113 [(set (attr "length")
4115 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4116 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4119 (set (attr "far_jump")
4121 (eq_attr "length" "4")
4123 (const_string "yes")))
4126 (eq_attr "length" "4")
4127 (const_string "branch")
4128 (const_string "multi")))])
4130 (define_insn "*branch_fp_false"
4132 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
4133 [(match_operand 1 "fcc_operand" "u")
4136 (label_ref (match_operand 2 "" ""))))]
4140 if (get_attr_length (insn) == 4)
4141 return \"fb%F0 %1,%#,%l2\";
4143 return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
4145 [(set (attr "length")
4147 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
4148 (le (minus (match_dup 2) (pc)) (const_int 32764)))
4151 (set (attr "far_jump")
4153 (eq_attr "length" "4")
4155 (const_string "yes")))
4158 (eq_attr "length" "4")
4159 (const_string "branch")
4160 (const_string "multi")))])
4163 ;; ::::::::::::::::::::
4165 ;; :: Set flag operations
4167 ;; ::::::::::::::::::::
4169 ;; Define_expands called by the machine independent part of the compiler
4170 ;; to allocate a new comparison register
4172 (define_expand "seq"
4173 [(match_operand:SI 0 "integer_register_operand" "")]
4177 if (! frv_emit_scc (EQ, operands[0]))
4183 (define_expand "sne"
4184 [(match_operand:SI 0 "integer_register_operand" "")]
4188 if (! frv_emit_scc (NE, operands[0]))
4194 (define_expand "slt"
4195 [(match_operand:SI 0 "integer_register_operand" "")]
4199 if (! frv_emit_scc (LT, operands[0]))
4205 (define_expand "sle"
4206 [(match_operand:SI 0 "integer_register_operand" "")]
4210 if (! frv_emit_scc (LE, operands[0]))
4216 (define_expand "sgt"
4217 [(match_operand:SI 0 "integer_register_operand" "")]
4221 if (! frv_emit_scc (GT, operands[0]))
4227 (define_expand "sge"
4228 [(match_operand:SI 0 "integer_register_operand" "")]
4232 if (! frv_emit_scc (GE, operands[0]))
4238 (define_expand "sltu"
4239 [(match_operand:SI 0 "integer_register_operand" "")]
4243 if (! frv_emit_scc (LTU, operands[0]))
4249 (define_expand "sleu"
4250 [(match_operand:SI 0 "integer_register_operand" "")]
4254 if (! frv_emit_scc (LEU, operands[0]))
4260 (define_expand "sgtu"
4261 [(match_operand:SI 0 "integer_register_operand" "")]
4265 if (! frv_emit_scc (GTU, operands[0]))
4271 (define_expand "sgeu"
4272 [(match_operand:SI 0 "integer_register_operand" "")]
4276 if (! frv_emit_scc (GEU, operands[0]))
4282 (define_insn "*scc_int"
4283 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4284 (match_operator:SI 1 "integer_relational_operator"
4285 [(match_operand 2 "icc_operand" "t")
4287 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4290 [(set_attr "length" "12")
4291 (set_attr "type" "multi")])
4293 (define_insn "*scc_float"
4294 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4295 (match_operator:SI 1 "float_relational_operator"
4296 [(match_operand:CC_FP 2 "fcc_operand" "u")
4298 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4301 [(set_attr "length" "12")
4302 (set_attr "type" "multi")])
4304 ;; XXX -- add reload_completed to the splits, because register allocation
4305 ;; currently isn't ready to see cond_exec packets.
4307 [(set (match_operand:SI 0 "integer_register_operand" "")
4308 (match_operator:SI 1 "relational_operator"
4309 [(match_operand 2 "cc_operand" "")
4311 (clobber (match_operand 3 "cr_operand" ""))]
4314 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4315 operands[3], (HOST_WIDE_INT) 1);")
4317 (define_insn "*scc_neg1_int"
4318 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4319 (neg:SI (match_operator:SI 1 "integer_relational_operator"
4320 [(match_operand 2 "icc_operand" "t")
4322 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4325 [(set_attr "length" "12")
4326 (set_attr "type" "multi")])
4328 (define_insn "*scc_neg1_float"
4329 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4330 (neg:SI (match_operator:SI 1 "float_relational_operator"
4331 [(match_operand:CC_FP 2 "fcc_operand" "u")
4333 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4336 [(set_attr "length" "12")
4337 (set_attr "type" "multi")])
4340 [(set (match_operand:SI 0 "integer_register_operand" "")
4341 (neg:SI (match_operator:SI 1 "relational_operator"
4342 [(match_operand 2 "cc_operand" "")
4344 (clobber (match_operand 3 "cr_operand" ""))]
4347 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4348 operands[3], (HOST_WIDE_INT) -1);")
4351 ;; ::::::::::::::::::::
4353 ;; :: Conditionally executed instructions
4355 ;; ::::::::::::::::::::
4357 ;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4358 (define_insn "*ck_signed"
4359 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4360 (match_operator:CC_CCR 1 "integer_relational_operator"
4361 [(match_operand 2 "icc_operand" "t")
4365 [(set_attr "length" "4")
4366 (set_attr "type" "ccr")])
4368 (define_insn "*fck_float"
4369 [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4370 (match_operator:CC_CCR 1 "float_relational_operator"
4371 [(match_operand:CC_FP 2 "fcc_operand" "u")
4375 [(set_attr "length" "4")
4376 (set_attr "type" "ccr")])
4378 ;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4379 ;; tests in conditional execution
4380 (define_insn "cond_exec_ck"
4381 [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4382 (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4383 [(match_operand 2 "cr_operand" "C,C")
4385 (match_operator 3 "relational_operator"
4386 [(match_operand 4 "cc_operand" "t,u")
4391 cck%c3 %4, %0, %2, %e1
4392 cfck%f3 %4, %0, %2, %e1"
4393 [(set_attr "length" "4")
4394 (set_attr "type" "ccr")])
4396 ;; Conditionally set a register to either 0 or another register
4397 (define_insn "*cond_exec_movqi"
4399 (match_operator 0 "ccr_eqne_operator"
4400 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4402 (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4403 (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4404 "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4405 "* return output_condmove_single (operands, insn);"
4406 [(set_attr "length" "4")
4407 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4409 (define_insn "*cond_exec_movhi"
4411 (match_operator 0 "ccr_eqne_operator"
4412 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4414 (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4415 (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4416 "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4417 "* return output_condmove_single (operands, insn);"
4418 [(set_attr "length" "4")
4419 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4421 (define_insn "*cond_exec_movsi"
4423 (match_operator 0 "ccr_eqne_operator"
4424 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4426 (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4427 (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4428 "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4429 "* return output_condmove_single (operands, insn);"
4430 [(set_attr "length" "4")
4431 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4434 (define_insn "*cond_exec_movsf_has_fprs"
4436 (match_operator 0 "ccr_eqne_operator"
4437 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4439 (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4440 (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4442 "* return output_condmove_single (operands, insn);"
4443 [(set_attr "length" "4")
4444 (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4446 (define_insn "*cond_exec_movsf_no_fprs"
4448 (match_operator 0 "ccr_eqne_operator"
4449 [(match_operand 1 "cr_operand" "C,C,C")
4451 (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4452 (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4454 "* return output_condmove_single (operands, insn);"
4455 [(set_attr "length" "4")
4456 (set_attr "type" "int,gload,gstore")])
4458 (define_insn "*cond_exec_si_binary1"
4460 (match_operator 0 "ccr_eqne_operator"
4461 [(match_operand 1 "cr_operand" "C")
4463 (set (match_operand:SI 2 "integer_register_operand" "=d")
4464 (match_operator:SI 3 "condexec_si_binary_operator"
4465 [(match_operand:SI 4 "integer_register_operand" "d")
4466 (match_operand:SI 5 "integer_register_operand" "d")])))]
4470 switch (GET_CODE (operands[3]))
4472 case PLUS: return \"cadd %4, %z5, %2, %1, %e0\";
4473 case MINUS: return \"csub %4, %z5, %2, %1, %e0\";
4474 case AND: return \"cand %4, %z5, %2, %1, %e0\";
4475 case IOR: return \"cor %4, %z5, %2, %1, %e0\";
4476 case XOR: return \"cxor %4, %z5, %2, %1, %e0\";
4477 case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
4478 case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4479 case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4480 default: gcc_unreachable ();
4483 [(set_attr "length" "4")
4484 (set_attr "type" "int")])
4486 (define_insn "*cond_exec_si_binary2"
4488 (match_operator 0 "ccr_eqne_operator"
4489 [(match_operand 1 "cr_operand" "C")
4491 (set (match_operand:SI 2 "fpr_operand" "=f")
4492 (match_operator:SI 3 "condexec_si_media_operator"
4493 [(match_operand:SI 4 "fpr_operand" "f")
4494 (match_operand:SI 5 "fpr_operand" "f")])))]
4498 switch (GET_CODE (operands[3]))
4500 case AND: return \"cmand %4, %5, %2, %1, %e0\";
4501 case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4502 case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4503 default: gcc_unreachable ();
4506 [(set_attr "length" "4")
4507 (set_attr "type" "mlogic")])
4509 ;; Note, flow does not (currently) know how to handle an operation that uses
4510 ;; only part of the hard registers allocated for a multiregister value, such as
4511 ;; DImode in this case if the user is only interested in the lower 32-bits. So
4512 ;; we emit a USE of the entire register after the csmul instruction so it won't
4513 ;; get confused. See frv_ifcvt_modify_insn for more details.
4515 (define_insn "*cond_exec_si_smul"
4517 (match_operator 0 "ccr_eqne_operator"
4518 [(match_operand 1 "cr_operand" "C")
4520 (set (match_operand:DI 2 "even_gpr_operand" "=e")
4521 (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4522 (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4524 "csmul %3, %4, %2, %1, %e0"
4525 [(set_attr "length" "4")
4526 (set_attr "type" "mul")])
4528 (define_insn "*cond_exec_si_divide"
4530 (match_operator 0 "ccr_eqne_operator"
4531 [(match_operand 1 "cr_operand" "C")
4533 (set (match_operand:SI 2 "integer_register_operand" "=d")
4534 (match_operator:SI 3 "condexec_si_divide_operator"
4535 [(match_operand:SI 4 "integer_register_operand" "d")
4536 (match_operand:SI 5 "integer_register_operand" "d")])))]
4540 switch (GET_CODE (operands[3]))
4542 case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
4543 case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4544 default: gcc_unreachable ();
4547 [(set_attr "length" "4")
4548 (set_attr "type" "div")])
4550 (define_insn "*cond_exec_si_unary1"
4552 (match_operator 0 "ccr_eqne_operator"
4553 [(match_operand 1 "cr_operand" "C")
4555 (set (match_operand:SI 2 "integer_register_operand" "=d")
4556 (match_operator:SI 3 "condexec_si_unary_operator"
4557 [(match_operand:SI 4 "integer_register_operand" "d")])))]
4561 switch (GET_CODE (operands[3]))
4563 case NOT: return \"cnot %4, %2, %1, %e0\";
4564 case NEG: return \"csub %., %4, %2, %1, %e0\";
4565 default: gcc_unreachable ();
4568 [(set_attr "length" "4")
4569 (set_attr "type" "int")])
4571 (define_insn "*cond_exec_si_unary2"
4573 (match_operator 0 "ccr_eqne_operator"
4574 [(match_operand 1 "cr_operand" "C")
4576 (set (match_operand:SI 2 "fpr_operand" "=f")
4577 (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4579 "cmnot %3, %2, %1, %e0"
4580 [(set_attr "length" "4")
4581 (set_attr "type" "mlogic")])
4583 (define_insn "*cond_exec_cmpsi_cc"
4585 (match_operator 0 "ccr_eqne_operator"
4586 [(match_operand 1 "cr_operand" "C")
4588 (set (match_operand:CC 2 "icc_operand" "=t")
4589 (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4590 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4592 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4593 "ccmp %3, %z4, %1, %e0"
4594 [(set_attr "length" "4")
4595 (set_attr "type" "int")])
4597 (define_insn "*cond_exec_cmpsi_cc_uns"
4599 (match_operator 0 "ccr_eqne_operator"
4600 [(match_operand 1 "cr_operand" "C")
4602 (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4603 (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4604 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4606 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4607 "ccmp %3, %z4, %1, %e0"
4608 [(set_attr "length" "4")
4609 (set_attr "type" "int")])
4611 (define_insn "*cond_exec_cmpsi_cc_nz"
4613 (match_operator 0 "ccr_eqne_operator"
4614 [(match_operand 1 "cr_operand" "C")
4616 (set (match_operand:CC_NZ 2 "icc_operand" "=t")
4617 (compare:CC_NZ (match_operand:SI 3 "integer_register_operand" "d")
4620 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4621 "ccmp %3, %., %1, %e0"
4622 [(set_attr "length" "4")
4623 (set_attr "type" "int")])
4625 (define_insn "*cond_exec_sf_conv"
4627 (match_operator 0 "ccr_eqne_operator"
4628 [(match_operand 1 "cr_operand" "C")
4630 (set (match_operand:SF 2 "fpr_operand" "=f")
4631 (match_operator:SF 3 "condexec_sf_conv_operator"
4632 [(match_operand:SF 4 "fpr_operand" "f")])))]
4636 switch (GET_CODE (operands[3]))
4638 case ABS: return \"cfabss %4, %2, %1, %e0\";
4639 case NEG: return \"cfnegs %4, %2, %1, %e0\";
4640 default: gcc_unreachable ();
4643 [(set_attr "length" "4")
4644 (set_attr "type" "fsconv")])
4646 (define_insn "*cond_exec_sf_add"
4648 (match_operator 0 "ccr_eqne_operator"
4649 [(match_operand 1 "cr_operand" "C")
4651 (set (match_operand:SF 2 "fpr_operand" "=f")
4652 (match_operator:SF 3 "condexec_sf_add_operator"
4653 [(match_operand:SF 4 "fpr_operand" "f")
4654 (match_operand:SF 5 "fpr_operand" "f")])))]
4658 switch (GET_CODE (operands[3]))
4660 case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
4661 case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4662 default: gcc_unreachable ();
4665 [(set_attr "length" "4")
4666 (set_attr "type" "fsadd")])
4668 (define_insn "*cond_exec_sf_mul"
4670 (match_operator 0 "ccr_eqne_operator"
4671 [(match_operand 1 "cr_operand" "C")
4673 (set (match_operand:SF 2 "fpr_operand" "=f")
4674 (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4675 (match_operand:SF 4 "fpr_operand" "f"))))]
4677 "cfmuls %3, %4, %2, %1, %e0"
4678 [(set_attr "length" "4")
4679 (set_attr "type" "fsmul")])
4681 (define_insn "*cond_exec_sf_div"
4683 (match_operator 0 "ccr_eqne_operator"
4684 [(match_operand 1 "cr_operand" "C")
4686 (set (match_operand:SF 2 "fpr_operand" "=f")
4687 (div:SF (match_operand:SF 3 "fpr_operand" "f")
4688 (match_operand:SF 4 "fpr_operand" "f"))))]
4690 "cfdivs %3, %4, %2, %1, %e0"
4691 [(set_attr "length" "4")
4692 (set_attr "type" "fsdiv")])
4694 (define_insn "*cond_exec_sf_sqrt"
4696 (match_operator 0 "ccr_eqne_operator"
4697 [(match_operand 1 "cr_operand" "C")
4699 (set (match_operand:SF 2 "fpr_operand" "=f")
4700 (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4702 "cfsqrts %3, %2, %1, %e0"
4703 [(set_attr "length" "4")
4704 (set_attr "type" "fsdiv")])
4706 (define_insn "*cond_exec_cmpsi_cc_fp"
4708 (match_operator 0 "ccr_eqne_operator"
4709 [(match_operand 1 "cr_operand" "C")
4711 (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4712 (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4713 (match_operand:SF 4 "fpr_operand" "f"))))]
4714 "reload_completed && TARGET_HARD_FLOAT
4715 && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4716 "cfcmps %3, %4, %2, %1, %e0"
4717 [(set_attr "length" "4")
4718 (set_attr "type" "fsconv")])
4721 ;; ::::::::::::::::::::
4723 ;; :: Logical operations on CR registers
4725 ;; ::::::::::::::::::::
4727 ;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4728 ;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4729 ;; while the CRs have TRUE, FALSE, and UNDEFINED.
4731 (define_expand "andcr"
4732 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4733 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4734 (match_operand:CC_CCR 2 "cr_operand" "")
4735 (const_int 0)] UNSPEC_CR_LOGIC))]
4739 (define_expand "orcr"
4740 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4741 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4742 (match_operand:CC_CCR 2 "cr_operand" "")
4743 (const_int 1)] UNSPEC_CR_LOGIC))]
4747 (define_expand "xorcr"
4748 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4749 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4750 (match_operand:CC_CCR 2 "cr_operand" "")
4751 (const_int 2)] UNSPEC_CR_LOGIC))]
4755 (define_expand "nandcr"
4756 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4757 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4758 (match_operand:CC_CCR 2 "cr_operand" "")
4759 (const_int 3)] UNSPEC_CR_LOGIC))]
4763 (define_expand "norcr"
4764 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4765 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4766 (match_operand:CC_CCR 2 "cr_operand" "")
4767 (const_int 4)] UNSPEC_CR_LOGIC))]
4771 (define_expand "andncr"
4772 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4773 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4774 (match_operand:CC_CCR 2 "cr_operand" "")
4775 (const_int 5)] UNSPEC_CR_LOGIC))]
4779 (define_expand "orncr"
4780 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4781 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4782 (match_operand:CC_CCR 2 "cr_operand" "")
4783 (const_int 6)] UNSPEC_CR_LOGIC))]
4787 (define_expand "nandncr"
4788 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4789 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4790 (match_operand:CC_CCR 2 "cr_operand" "")
4791 (const_int 7)] UNSPEC_CR_LOGIC))]
4795 (define_expand "norncr"
4796 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4797 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4798 (match_operand:CC_CCR 2 "cr_operand" "")
4799 (const_int 8)] UNSPEC_CR_LOGIC))]
4803 (define_expand "notcr"
4804 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4805 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4807 (const_int 9)] UNSPEC_CR_LOGIC))]
4811 (define_insn "*logical_cr"
4812 [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4813 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4814 (match_operand:CC_CCR 2 "cr_operand" "C")
4815 (match_operand:SI 3 "const_int_operand" "n")]
4820 switch (INTVAL (operands[3]))
4823 case 0: return \"andcr %1, %2, %0\";
4824 case 1: return \"orcr %1, %2, %0\";
4825 case 2: return \"xorcr %1, %2, %0\";
4826 case 3: return \"nandcr %1, %2, %0\";
4827 case 4: return \"norcr %1, %2, %0\";
4828 case 5: return \"andncr %1, %2, %0\";
4829 case 6: return \"orncr %1, %2, %0\";
4830 case 7: return \"nandncr %1, %2, %0\";
4831 case 8: return \"norncr %1, %2, %0\";
4832 case 9: return \"notcr %1, %0\";
4835 fatal_insn (\"logical_cr\", insn);
4837 [(set_attr "length" "4")
4838 (set_attr "type" "ccr")])
4841 ;; ::::::::::::::::::::
4843 ;; :: Conditional move instructions
4845 ;; ::::::::::::::::::::
4848 ;; - conditional moves based on floating-point comparisons require
4849 ;; TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4851 ;; - conditional moves between FPRs based on integer comparisons
4852 ;; require TARGET_HAS_FPRS.
4854 (define_expand "movqicc"
4855 [(set (match_operand:QI 0 "integer_register_operand" "")
4856 (if_then_else:QI (match_operand 1 "" "")
4857 (match_operand:QI 2 "gpr_or_int_operand" "")
4858 (match_operand:QI 3 "gpr_or_int_operand" "")))]
4862 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4868 (define_insn "*movqicc_internal1_int"
4869 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4870 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4871 [(match_operand 2 "icc_operand" "t,t,t")
4873 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4874 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4875 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4878 [(set_attr "length" "8,8,12")
4879 (set_attr "type" "multi")])
4881 (define_insn "*movqicc_internal1_float"
4882 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4883 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4884 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4886 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4887 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4888 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4891 [(set_attr "length" "8,8,12")
4892 (set_attr "type" "multi")])
4894 (define_insn "*movqicc_internal2_int"
4895 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4896 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4897 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4899 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4900 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4901 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4902 "(INTVAL (operands[3]) == 0
4903 || INTVAL (operands[4]) == 0
4904 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4905 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4907 [(set_attr "length" "8,12,8,12,12")
4908 (set_attr "type" "multi")])
4910 (define_insn "*movqicc_internal2_float"
4911 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4912 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4913 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4915 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4916 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4917 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4919 && (INTVAL (operands[3]) == 0
4920 || INTVAL (operands[4]) == 0
4921 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4922 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4924 [(set_attr "length" "8,12,8,12,12")
4925 (set_attr "type" "multi")])
4928 [(set (match_operand:QI 0 "integer_register_operand" "")
4929 (if_then_else:QI (match_operator 1 "relational_operator"
4930 [(match_operand 2 "cc_operand" "")
4932 (match_operand:QI 3 "gpr_or_int_operand" "")
4933 (match_operand:QI 4 "gpr_or_int_operand" "")))
4934 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4937 "operands[6] = frv_split_cond_move (operands);")
4939 (define_expand "movhicc"
4940 [(set (match_operand:HI 0 "integer_register_operand" "")
4941 (if_then_else:HI (match_operand 1 "" "")
4942 (match_operand:HI 2 "gpr_or_int_operand" "")
4943 (match_operand:HI 3 "gpr_or_int_operand" "")))]
4947 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4953 (define_insn "*movhicc_internal1_int"
4954 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4955 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4956 [(match_operand 2 "icc_operand" "t,t,t")
4958 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4959 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4960 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4963 [(set_attr "length" "8,8,12")
4964 (set_attr "type" "multi")])
4966 (define_insn "*movhicc_internal1_float"
4967 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4968 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4969 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4971 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4972 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4973 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4976 [(set_attr "length" "8,8,12")
4977 (set_attr "type" "multi")])
4979 (define_insn "*movhicc_internal2_int"
4980 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4981 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4982 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4984 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4985 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4986 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4987 "(INTVAL (operands[3]) == 0
4988 || INTVAL (operands[4]) == 0
4989 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4990 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4992 [(set_attr "length" "8,12,8,12,12")
4993 (set_attr "type" "multi")])
4995 (define_insn "*movhicc_internal2_float"
4996 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4997 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4998 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
5000 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
5001 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
5002 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
5004 && (INTVAL (operands[3]) == 0
5005 || INTVAL (operands[4]) == 0
5006 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
5007 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
5009 [(set_attr "length" "8,12,8,12,12")
5010 (set_attr "type" "multi")])
5013 [(set (match_operand:HI 0 "integer_register_operand" "")
5014 (if_then_else:HI (match_operator 1 "relational_operator"
5015 [(match_operand 2 "cc_operand" "")
5017 (match_operand:HI 3 "gpr_or_int_operand" "")
5018 (match_operand:HI 4 "gpr_or_int_operand" "")))
5019 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5022 "operands[6] = frv_split_cond_move (operands);")
5024 (define_expand "movsicc"
5025 [(set (match_operand:SI 0 "integer_register_operand" "")
5026 (if_then_else:SI (match_operand 1 "" "")
5027 (match_operand:SI 2 "gpr_or_int_operand" "")
5028 (match_operand:SI 3 "gpr_or_int_operand" "")))]
5032 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
5038 (define_insn "*movsicc_internal1_int"
5039 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
5040 (if_then_else:SI (match_operator 1 "integer_relational_operator"
5041 [(match_operand 2 "icc_operand" "t,t,t")
5043 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
5044 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
5045 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5048 [(set_attr "length" "8,8,12")
5049 (set_attr "type" "multi")])
5051 (define_insn "*movsicc_internal1_float"
5052 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
5053 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
5054 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
5056 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
5057 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
5058 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5061 [(set_attr "length" "8,8,12")
5062 (set_attr "type" "multi")])
5064 (define_insn "*movsicc_internal2_int"
5065 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
5066 (if_then_else:SI (match_operator 1 "integer_relational_operator"
5067 [(match_operand 2 "icc_operand" "t,t,t,t,t")
5069 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
5070 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
5071 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
5072 "(INTVAL (operands[3]) == 0
5073 || INTVAL (operands[4]) == 0
5074 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
5075 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
5077 [(set_attr "length" "8,12,8,12,12")
5078 (set_attr "type" "multi")])
5080 (define_insn "*movsicc_internal2_float"
5081 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
5082 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
5083 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
5085 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
5086 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
5087 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
5089 && (INTVAL (operands[3]) == 0
5090 || INTVAL (operands[4]) == 0
5091 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
5092 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
5094 [(set_attr "length" "8,12,8,12,12")
5095 (set_attr "type" "multi")])
5098 [(set (match_operand:SI 0 "integer_register_operand" "")
5099 (if_then_else:SI (match_operator 1 "relational_operator"
5100 [(match_operand 2 "cc_operand" "")
5102 (match_operand:SI 3 "gpr_or_int_operand" "")
5103 (match_operand:SI 4 "gpr_or_int_operand" "")))
5104 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5107 "operands[6] = frv_split_cond_move (operands);")
5109 (define_expand "movsfcc"
5110 [(set (match_operand:SF 0 "register_operand" "")
5111 (if_then_else:SF (match_operand 1 "" "")
5112 (match_operand:SF 2 "register_operand" "")
5113 (match_operand:SF 3 "register_operand" "")))]
5117 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
5123 (define_insn "*movsfcc_has_fprs_int"
5124 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
5125 (if_then_else:SF (match_operator 1 "integer_relational_operator"
5126 [(match_operand 2 "icc_operand" "t,t,t,t,t,t")
5128 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
5129 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
5130 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
5133 [(set_attr "length" "8,8,12,12,12,12")
5134 (set_attr "type" "multi")])
5136 (define_insn "*movsfcc_hardfloat_float"
5137 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
5138 (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
5139 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
5141 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
5142 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
5143 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
5146 [(set_attr "length" "8,8,12,12,12,12")
5147 (set_attr "type" "multi")])
5149 (define_insn "*movsfcc_no_fprs_int"
5150 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
5151 (if_then_else:SF (match_operator 1 "integer_relational_operator"
5152 [(match_operand 2 "icc_operand" "t,t,t")
5154 (match_operand:SF 3 "integer_register_operand" "0,d,d")
5155 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
5156 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5159 [(set_attr "length" "8,8,12")
5160 (set_attr "type" "multi")])
5163 [(set (match_operand:SF 0 "register_operand" "")
5164 (if_then_else:SF (match_operator 1 "relational_operator"
5165 [(match_operand 2 "cc_operand" "")
5167 (match_operand:SF 3 "register_operand" "")
5168 (match_operand:SF 4 "register_operand" "")))
5169 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5172 "operands[6] = frv_split_cond_move (operands);")
5175 ;; ::::::::::::::::::::
5177 ;; :: Minimum, maximum, and integer absolute value
5179 ;; ::::::::::::::::::::
5181 ;; These 'instructions' are provided to give the compiler a slightly better
5182 ;; nudge at register allocation, then it would if it constructed the
5183 ;; instructions from basic building blocks (since it indicates it prefers one
5184 ;; of the operands to be the same as the destination. It also helps the
5185 ;; earlier passes of the compiler, by not breaking things into small basic
5188 (define_expand "abssi2"
5189 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5190 (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
5191 (clobber (match_dup 2))
5192 (clobber (match_dup 3))])]
5196 operands[2] = gen_reg_rtx (CCmode);
5197 operands[3] = gen_reg_rtx (CC_CCRmode);
5200 (define_insn_and_split "*abssi2_internal"
5201 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
5202 (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
5203 (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
5204 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
5209 "operands[4] = frv_split_abs (operands);"
5210 [(set_attr "length" "12,16")
5211 (set_attr "type" "multi")])
5213 (define_expand "sminsi3"
5214 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5215 (smin:SI (match_operand:SI 1 "integer_register_operand" "")
5216 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5217 (clobber (match_dup 3))
5218 (clobber (match_dup 4))])]
5222 operands[3] = gen_reg_rtx (CCmode);
5223 operands[4] = gen_reg_rtx (CC_CCRmode);
5226 (define_expand "smaxsi3"
5227 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5228 (smax:SI (match_operand:SI 1 "integer_register_operand" "")
5229 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5230 (clobber (match_dup 3))
5231 (clobber (match_dup 4))])]
5235 operands[3] = gen_reg_rtx (CCmode);
5236 operands[4] = gen_reg_rtx (CC_CCRmode);
5239 (define_insn_and_split "*minmax_si_signed"
5240 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5241 (match_operator:SI 1 "minmax_operator"
5242 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5243 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5244 (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
5245 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5250 "operands[6] = frv_split_minmax (operands);"
5251 [(set_attr "length" "12,12,16")
5252 (set_attr "type" "multi")])
5254 (define_expand "uminsi3"
5255 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5256 (umin:SI (match_operand:SI 1 "integer_register_operand" "")
5257 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5258 (clobber (match_dup 3))
5259 (clobber (match_dup 4))])]
5263 operands[3] = gen_reg_rtx (CC_UNSmode);
5264 operands[4] = gen_reg_rtx (CC_CCRmode);
5267 (define_expand "umaxsi3"
5268 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5269 (umax:SI (match_operand:SI 1 "integer_register_operand" "")
5270 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5271 (clobber (match_dup 3))
5272 (clobber (match_dup 4))])]
5276 operands[3] = gen_reg_rtx (CC_UNSmode);
5277 operands[4] = gen_reg_rtx (CC_CCRmode);
5280 (define_insn_and_split "*minmax_si_unsigned"
5281 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5282 (match_operator:SI 1 "minmax_operator"
5283 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5284 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5285 (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5286 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5291 "operands[6] = frv_split_minmax (operands);"
5292 [(set_attr "length" "12,12,16")
5293 (set_attr "type" "multi")])
5295 (define_expand "sminsf3"
5296 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5297 (smin:SF (match_operand:SF 1 "fpr_operand" "")
5298 (match_operand:SF 2 "fpr_operand" "")))
5299 (clobber (match_dup 3))
5300 (clobber (match_dup 4))])]
5301 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5304 operands[3] = gen_reg_rtx (CC_FPmode);
5305 operands[4] = gen_reg_rtx (CC_CCRmode);
5308 (define_expand "smaxsf3"
5309 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5310 (smax:SF (match_operand:SF 1 "fpr_operand" "")
5311 (match_operand:SF 2 "fpr_operand" "")))
5312 (clobber (match_dup 3))
5313 (clobber (match_dup 4))])]
5314 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5317 operands[3] = gen_reg_rtx (CC_FPmode);
5318 operands[4] = gen_reg_rtx (CC_CCRmode);
5321 (define_insn_and_split "*minmax_sf"
5322 [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5323 (match_operator:SF 1 "minmax_operator"
5324 [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5325 (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5326 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5327 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5328 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5332 "operands[6] = frv_split_minmax (operands);"
5333 [(set_attr "length" "12,12,16")
5334 (set_attr "type" "multi")])
5336 (define_expand "smindf3"
5337 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5338 (smin:DF (match_operand:DF 1 "fpr_operand" "")
5339 (match_operand:DF 2 "fpr_operand" "")))
5340 (clobber (match_dup 3))
5341 (clobber (match_dup 4))])]
5342 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5345 operands[3] = gen_reg_rtx (CC_FPmode);
5346 operands[4] = gen_reg_rtx (CC_CCRmode);
5349 (define_expand "smaxdf3"
5350 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5351 (smax:DF (match_operand:DF 1 "fpr_operand" "")
5352 (match_operand:DF 2 "fpr_operand" "")))
5353 (clobber (match_dup 3))
5354 (clobber (match_dup 4))])]
5355 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5358 operands[3] = gen_reg_rtx (CC_FPmode);
5359 operands[4] = gen_reg_rtx (CC_CCRmode);
5362 (define_insn_and_split "*minmax_df"
5363 [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5364 (match_operator:DF 1 "minmax_operator"
5365 [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5366 (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5367 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5368 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5369 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5373 "operands[6] = frv_split_minmax (operands);"
5374 [(set_attr "length" "12,12,16")
5375 (set_attr "type" "multi")])
5378 ;; ::::::::::::::::::::
5380 ;; :: Call and branch instructions
5382 ;; ::::::::::::::::::::
5384 ;; Subroutine call instruction returning no value. Operand 0 is the function
5385 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5386 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5387 ;; registers used as operands.
5389 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5390 ;; is supplied for the sake of some RISC machines which need to put this
5391 ;; information into the assembler code; they can put it in the RTL instead of
5394 (define_expand "call"
5395 [(use (match_operand:QI 0 "" ""))
5396 (use (match_operand 1 "" ""))
5397 (use (match_operand 2 "" ""))
5398 (use (match_operand 3 "" ""))]
5402 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5405 gcc_assert (GET_CODE (operands[0]) == MEM);
5407 addr = XEXP (operands[0], 0);
5408 if (! call_operand (addr, Pmode))
5409 addr = force_reg (Pmode, addr);
5412 operands[2] = const0_rtx;
5415 frv_expand_fdpic_call (operands, false, false);
5417 emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5422 (define_insn "call_internal"
5423 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5424 (match_operand 1 "" ""))
5425 (use (match_operand 2 "" ""))
5426 (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5431 [(set_attr "length" "4")
5432 (set_attr "type" "call,jumpl")])
5434 ;; The odd use of GR0 within the UNSPEC below prevents cseing or
5435 ;; hoisting function descriptor loads out of loops. This is almost
5436 ;; never desirable, since if we preserve the function descriptor in a
5437 ;; pair of registers, it takes two insns to move it to gr14/gr15, and
5438 ;; if it's in the stack, we just waste space with the store, since
5439 ;; we'll have to load back from memory anyway. And, in the worst
5440 ;; case, we may end up reusing a function descriptor still pointing at
5441 ;; a PLT entry, instead of to the resolved function, which means going
5442 ;; through the resolver for every call that uses the outdated value.
5445 ;; The explicit MEM inside the SPEC prevents the compiler from moving
5446 ;; the load before a branch after a NULL test, or before a store that
5447 ;; initializes a function descriptor.
5449 (define_insn "movdi_ldd"
5450 [(set (match_operand:DI 0 "fdpic_fptr_operand" "=e")
5451 (unspec:DI [(mem:DI (match_operand:SI 1 "ldd_address_operand" "p"))
5452 (reg:SI 0)] UNSPEC_LDD))]
5455 [(set_attr "length" "4")
5456 (set_attr "type" "gload")])
5458 (define_insn "call_fdpicdi"
5459 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5460 (match_operand 1 "" ""))
5461 (clobber (match_operand:SI 2 "lr_operand" "=l"))]
5464 [(set_attr "length" "4")
5465 (set_attr "type" "jumpl")])
5467 (define_insn "call_fdpicsi"
5468 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5469 (match_operand 1 "" ""))
5470 (use (match_operand 2 "" ""))
5471 (use (match_operand:SI 3 "fdpic_operand" "Z,Z"))
5472 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5477 [(set_attr "length" "4")
5478 (set_attr "type" "call,jumpl")])
5480 (define_expand "sibcall"
5481 [(use (match_operand:QI 0 "" ""))
5482 (use (match_operand 1 "" ""))
5483 (use (match_operand 2 "" ""))
5484 (use (match_operand 3 "" ""))]
5490 gcc_assert (GET_CODE (operands[0]) == MEM);
5492 addr = XEXP (operands[0], 0);
5493 if (! sibcall_operand (addr, Pmode))
5494 addr = force_reg (Pmode, addr);
5497 operands[2] = const0_rtx;
5500 frv_expand_fdpic_call (operands, false, true);
5502 emit_call_insn (gen_sibcall_internal (addr, operands[1], operands[2]));
5507 ;; It might seem that these sibcall patterns are missing references to
5508 ;; LR, but they're not necessary because sibcall_epilogue will make
5509 ;; sure LR is restored, and having LR here will set
5510 ;; regs_ever_used[REG_LR], forcing it to be saved on the stack, and
5511 ;; then restored in sibcalls and regular return code paths, even if
5512 ;; the function becomes a leaf function after tail-call elimination.
5514 ;; We must not use a call-saved register here. `W' limits ourselves
5515 ;; to gr14 or gr15, but since we're almost running out of constraint
5516 ;; letters, and most other call-clobbered registers are often used for
5517 ;; argument-passing, this will do.
5518 (define_insn "sibcall_internal"
5519 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "WNOP"))
5520 (match_operand 1 "" ""))
5521 (use (match_operand 2 "" ""))
5525 [(set_attr "length" "4")
5526 (set_attr "type" "jumpl")])
5528 (define_insn "sibcall_fdpicdi"
5529 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5530 (match_operand 1 "" ""))
5534 [(set_attr "length" "4")
5535 (set_attr "type" "jumpl")])
5538 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5539 ;; register in which the value is returned. There are three more operands, the
5540 ;; same as the three operands of the `call' instruction (but with numbers
5541 ;; increased by one).
5543 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5545 (define_expand "call_value"
5546 [(use (match_operand 0 "" ""))
5547 (use (match_operand:QI 1 "" ""))
5548 (use (match_operand 2 "" ""))
5549 (use (match_operand 3 "" ""))
5550 (use (match_operand 4 "" ""))]
5554 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5557 gcc_assert (GET_CODE (operands[1]) == MEM);
5559 addr = XEXP (operands[1], 0);
5560 if (! call_operand (addr, Pmode))
5561 addr = force_reg (Pmode, addr);
5564 operands[3] = const0_rtx;
5567 frv_expand_fdpic_call (operands, true, false);
5569 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5575 (define_insn "call_value_internal"
5576 [(set (match_operand 0 "register_operand" "=d,d")
5577 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5578 (match_operand 2 "" "")))
5579 (use (match_operand 3 "" ""))
5580 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5585 [(set_attr "length" "4")
5586 (set_attr "type" "call,jumpl")])
5588 (define_insn "call_value_fdpicdi"
5589 [(set (match_operand 0 "register_operand" "=d")
5590 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5591 (match_operand 2 "" "")))
5592 (clobber (match_operand:SI 3 "lr_operand" "=l"))]
5595 [(set_attr "length" "4")
5596 (set_attr "type" "jumpl")])
5598 (define_insn "call_value_fdpicsi"
5599 [(set (match_operand 0 "register_operand" "=d,d")
5600 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5601 (match_operand 2 "" "")))
5602 (use (match_operand 3 "" ""))
5603 (use (match_operand:SI 4 "fdpic_operand" "Z,Z"))
5604 (clobber (match_operand:SI 5 "lr_operand" "=l,l"))]
5609 [(set_attr "length" "4")
5610 (set_attr "type" "call,jumpl")])
5612 (define_expand "sibcall_value"
5613 [(use (match_operand 0 "" ""))
5614 (use (match_operand:QI 1 "" ""))
5615 (use (match_operand 2 "" ""))
5616 (use (match_operand 3 "" ""))
5617 (use (match_operand 4 "" ""))]
5623 gcc_assert (GET_CODE (operands[1]) == MEM);
5625 addr = XEXP (operands[1], 0);
5626 if (! sibcall_operand (addr, Pmode))
5627 addr = force_reg (Pmode, addr);
5630 operands[3] = const0_rtx;
5633 frv_expand_fdpic_call (operands, true, true);
5635 emit_call_insn (gen_sibcall_value_internal (operands[0], addr, operands[2],
5640 (define_insn "sibcall_value_internal"
5641 [(set (match_operand 0 "register_operand" "=d")
5642 (call (mem:QI (match_operand:SI 1 "sibcall_operand" "WNOP"))
5643 (match_operand 2 "" "")))
5644 (use (match_operand 3 "" ""))
5648 [(set_attr "length" "4")
5649 (set_attr "type" "jumpl")])
5651 (define_insn "sibcall_value_fdpicdi"
5652 [(set (match_operand 0 "register_operand" "=d")
5653 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5654 (match_operand 2 "" "")))
5658 [(set_attr "length" "4")
5659 (set_attr "type" "jumpl")])
5661 ;; return instruction generated instead of jmp to epilog
5662 (define_expand "return"
5663 [(parallel [(return)
5665 (use (const_int 1))])]
5666 "direct_return_p ()"
5669 operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5672 ;; return instruction generated by the epilogue
5673 (define_expand "epilogue_return"
5674 [(parallel [(return)
5675 (use (match_operand:SI 0 "register_operand" ""))
5676 (use (const_int 0))])]
5680 (define_insn "*return_internal"
5682 (use (match_operand:SI 0 "register_operand" "l,d"))
5683 (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5688 [(set_attr "length" "4")
5689 (set_attr "type" "jump,jumpl")])
5691 (define_insn "*return_true"
5693 (if_then_else (match_operator 0 "integer_relational_operator"
5694 [(match_operand 1 "icc_operand" "t")
5698 "direct_return_p ()"
5700 [(set_attr "length" "4")
5701 (set_attr "type" "jump")])
5703 (define_insn "*return_false"
5705 (if_then_else (match_operator 0 "integer_relational_operator"
5706 [(match_operand 1 "icc_operand" "t")
5710 "direct_return_p ()"
5712 [(set_attr "length" "4")
5713 (set_attr "type" "jump")])
5715 ;; A version of addsi3 for deallocating stack space at the end of the
5716 ;; epilogue. The addition is done in parallel with an (unspec_volatile),
5717 ;; which represents the clobbering of the deallocated space.
5718 (define_insn "stack_adjust"
5719 [(set (match_operand:SI 0 "register_operand" "=d")
5720 (plus:SI (match_operand:SI 1 "register_operand" "d")
5721 (match_operand:SI 2 "general_operand" "dNOP")))
5722 (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5725 [(set_attr "length" "4")
5726 (set_attr "type" "int")])
5728 ;; Normal unconditional jump
5730 ;; Use the "call" instruction for long branches, but prefer to use "bra" for
5731 ;; short ones since it does not force us to save the link register.
5733 ;; This define_insn uses the branch-shortening code to decide which
5734 ;; instruction it emits. Since the main branch-shortening interface is
5735 ;; through get_attr_length(), the two alternatives must be given different
5736 ;; lengths. Here we pretend that the far jump is 8 rather than 4 bytes
5737 ;; long, though both alternatives are really the same size.
5739 [(set (pc) (label_ref (match_operand 0 "" "")))]
5743 if (get_attr_length (insn) == 4)
5746 return \"call %l0\";
5748 [(set (attr "length")
5750 (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5751 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5754 (set (attr "far_jump")
5756 (eq_attr "length" "4")
5758 (const_string "yes")))
5761 (eq_attr "length" "4")
5762 (const_string "jump")
5763 (const_string "call")))])
5765 ;; Indirect jump through a register
5766 (define_insn "indirect_jump"
5767 [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5772 [(set_attr "length" "4")
5773 (set_attr "type" "jumpl,branch")])
5775 ;; Instruction to jump to a variable address. This is a low-level capability
5776 ;; which can be used to implement a dispatch table when there is no `casesi'
5777 ;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5778 ;; MUST be present in this file.
5780 ;; This pattern requires two operands: the address or offset, and a label which
5781 ;; should immediately precede the jump table. If the macro
5782 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5783 ;; which counts from the address of the table; otherwise, it is an absolute
5784 ;; address to jump to. In either case, the first operand has mode `Pmode'.
5786 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5787 ;; Its assembler code normally has no need to use the second operand, but you
5788 ;; should incorporate it in the RTL pattern so that the jump optimizer will not
5789 ;; delete the table as unreachable code.
5791 (define_expand "tablejump"
5792 [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5793 (use (label_ref (match_operand 1 "" "")))])]
5797 (define_insn "tablejump_insn"
5798 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5799 (use (label_ref (match_operand 1 "" "")))]
5802 [(set_attr "length" "4")
5803 (set_attr "type" "jumpl")])
5805 ;; Implement switch statements when generating PIC code. Switches are
5806 ;; implemented by `tablejump' when not using -fpic.
5808 ;; Emit code here to do the range checking and make the index zero based.
5809 ;; operand 0 is the index
5810 ;; operand 1 is the lower bound
5811 ;; operand 2 is the range of indices (highest - lowest + 1)
5812 ;; operand 3 is the label that precedes the table itself
5813 ;; operand 4 is the fall through label
5815 (define_expand "casesi"
5816 [(use (match_operand:SI 0 "integer_register_operand" ""))
5817 (use (match_operand:SI 1 "const_int_operand" ""))
5818 (use (match_operand:SI 2 "const_int_operand" ""))
5819 (use (match_operand 3 "" ""))
5820 (use (match_operand 4 "" ""))]
5826 rtx low = operands[1];
5827 rtx range = operands[2];
5828 rtx table = operands[3];
5830 rtx fail = operands[4];
5835 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5837 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5839 /* If we can't generate an immediate instruction, promote to register. */
5840 if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
5841 range = force_reg (SImode, range);
5843 /* If low bound is 0, we don't have to subtract it. */
5844 if (INTVAL (operands[1]) == 0)
5848 indx = gen_reg_rtx (SImode);
5849 if (IN_RANGE_P (INTVAL (low), -2047, 2048))
5850 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5852 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5855 /* Do an unsigned comparison (in the proper mode) between the index
5856 expression and the value which represents the length of the range.
5857 Since we just finished subtracting the lower bound of the range
5858 from the index expression, this comparison allows us to simultaneously
5859 check that the original index expression value is both greater than
5860 or equal to the minimum value of the range and less than or equal to
5861 the maximum value of the range. */
5863 emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5865 /* Move the table address to a register. */
5866 treg = gen_reg_rtx (Pmode);
5867 emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5869 /* Scale index-low by wordsize. */
5870 scale = gen_reg_rtx (SImode);
5871 emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
5873 /* Load the address, add the start of the table back in,
5875 mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5876 reg2 = gen_reg_rtx (SImode);
5877 reg3 = gen_reg_rtx (SImode);
5878 emit_insn (gen_movsi (reg2, mem));
5879 emit_insn (gen_addsi3 (reg3, reg2, treg));
5880 emit_jump_insn (gen_tablejump_insn (reg3, table));
5885 ;; ::::::::::::::::::::
5887 ;; :: Prologue and Epilogue instructions
5889 ;; ::::::::::::::::::::
5891 ;; Called after register allocation to add any instructions needed for the
5892 ;; prologue. Using a prologue insn is favored compared to putting all of the
5893 ;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5894 ;; to intermix instructions with the saves of the caller saved registers. In
5895 ;; some cases, it might be necessary to emit a barrier instruction as the last
5896 ;; insn to prevent such scheduling.
5897 (define_expand "prologue"
5902 frv_expand_prologue ();
5906 ;; Called after register allocation to add any instructions needed for the
5907 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
5908 ;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5909 ;; to intermix instructions with the restores of the caller saved registers.
5910 ;; In some cases, it might be necessary to emit a barrier instruction as the
5911 ;; first insn to prevent such scheduling.
5912 (define_expand "epilogue"
5917 frv_expand_epilogue (true);
5921 ;; This pattern, if defined, emits RTL for exit from a function without the final
5922 ;; branch back to the calling function. This pattern will be emitted before any
5923 ;; sibling call (aka tail call) sites.
5925 ;; The sibcall_epilogue pattern must not clobber any arguments used for
5926 ;; parameter passing or any stack slots for arguments passed to the current
5928 (define_expand "sibcall_epilogue"
5933 frv_expand_epilogue (false);
5937 ;; Set up the pic register to hold the address of the pic table
5938 (define_insn "pic_prologue"
5939 [(set (match_operand:SI 0 "integer_register_operand" "=d")
5940 (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5941 (clobber (match_operand:SI 1 "lr_operand" "=l"))
5942 (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5946 static int frv_pic_labelno = 0;
5948 operands[3] = GEN_INT (frv_pic_labelno++);
5949 return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5951 [(set_attr "length" "16")
5952 (set_attr "type" "multi")])
5954 ;; ::::::::::::::::::::
5956 ;; :: Miscellaneous instructions
5958 ;; ::::::::::::::::::::
5960 ;; No operation, needed in case the user uses -g but not -O.
5965 [(set_attr "length" "4")
5966 (set_attr "type" "int")])
5972 [(set_attr "length" "4")
5973 (set_attr "type" "fnop")])
5979 [(set_attr "length" "4")
5980 (set_attr "type" "mnop")])
5982 ;; Pseudo instruction that prevents the scheduler from moving code above this
5983 ;; point. Note, type unknown is used to make sure the VLIW instructions are
5984 ;; not continued past this point.
5985 (define_insn "blockage"
5986 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5989 [(set_attr "length" "0")
5990 (set_attr "type" "unknown")])
5992 ;; ::::::::::::::::::::
5994 ;; :: Media instructions
5996 ;; ::::::::::::::::::::
5998 ;; Unimplemented instructions:
6002 [(UNSPEC_MLOGIC 100)
6009 (UNSPEC_MUNPACKH 107)
6010 (UNSPEC_MDPACKH 108)
6015 (UNSPEC_MEXPDHW 113)
6016 (UNSPEC_MEXPDHD 114)
6023 (UNSPEC_MQMULXH 121)
6029 (UNSPEC_MRDACCG 127)
6031 (UNSPEC_MWTACCG 129)
6033 (UNSPEC_MCLRACC 131)
6034 (UNSPEC_MCLRACCA 132)
6037 (UNSPEC_MDUNPACKH 135)
6038 (UNSPEC_MDUNPACKH_INTERNAL 136)
6040 (UNSPEC_MBTOHE_INTERNAL 138)
6042 (UNSPEC_MBTOHE_INTERNAL 138)
6043 (UNSPEC_MQMACH2 139)
6044 (UNSPEC_MADDACC 140)
6045 (UNSPEC_MDADDACC 141)
6047 (UNSPEC_MDROTLI 143)
6050 (UNSPEC_MDCUTSSI 146)
6051 (UNSPEC_MQSATHS 147)
6052 (UNSPEC_MHSETLOS 148)
6053 (UNSPEC_MHSETLOH 149)
6054 (UNSPEC_MHSETHIS 150)
6055 (UNSPEC_MHSETHIH 151)
6056 (UNSPEC_MHDSETS 152)
6057 (UNSPEC_MHDSETH 153)
6058 (UNSPEC_MQLCLRHS 154)
6059 (UNSPEC_MQLMTHS 155)
6060 (UNSPEC_MQSLLHI 156)
6061 (UNSPEC_MQSRAHI 157)
6062 (UNSPEC_MASACCS 158)
6063 (UNSPEC_MDASACCS 159)
6066 ;; Logic operations: type "mlogic"
6068 (define_expand "mand"
6069 [(set (match_operand:SI 0 "fpr_operand" "")
6070 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6071 (match_operand:SI 2 "fpr_operand" "")
6075 "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
6077 (define_expand "mor"
6078 [(set (match_operand:SI 0 "fpr_operand" "")
6079 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6080 (match_operand:SI 2 "fpr_operand" "")
6084 "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
6086 (define_expand "mxor"
6087 [(set (match_operand:SI 0 "fpr_operand" "")
6088 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6089 (match_operand:SI 2 "fpr_operand" "")
6093 "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
6095 (define_insn "*mlogic"
6096 [(set (match_operand:SI 0 "fpr_operand" "=f")
6097 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6098 (match_operand:SI 2 "fpr_operand" "f")
6099 (match_operand:SI 3 "const_int_operand" "n")]
6104 switch (INTVAL (operands[3]))
6107 case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
6108 case FRV_BUILTIN_MOR: return \"mor %1, %2, %0\";
6109 case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
6112 fatal_insn (\"Bad media insn, mlogic\", insn);
6114 [(set_attr "length" "4")
6115 (set_attr "type" "mlogic")])
6117 (define_insn "*cond_exec_mlogic"
6119 (match_operator 0 "ccr_eqne_operator"
6120 [(match_operand 1 "cr_operand" "C")
6122 (set (match_operand:SI 2 "fpr_operand" "=f")
6123 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6124 (match_operand:SI 4 "fpr_operand" "f")
6125 (match_operand:SI 5 "const_int_operand" "n")]
6130 switch (INTVAL (operands[5]))
6133 case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
6134 case FRV_BUILTIN_MOR: return \"cmor %3, %4, %2, %1, %e0\";
6135 case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
6138 fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
6140 [(set_attr "length" "4")
6141 (set_attr "type" "mlogic")])
6143 ;; Logical not: type "mlogic"
6146 [(set (match_operand:SI 0 "fpr_operand" "=f")
6147 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
6150 [(set_attr "length" "4")
6151 (set_attr "type" "mlogic")])
6153 (define_insn "*cond_exec_mnot"
6155 (match_operator 0 "ccr_eqne_operator"
6156 [(match_operand 1 "cr_operand" "C")
6158 (set (match_operand:SI 2 "fpr_operand" "=f")
6159 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
6161 "cmnot %3, %2, %1, %e0"
6162 [(set_attr "length" "4")
6163 (set_attr "type" "mlogic")])
6165 ;; Dual average (halfword): type "maveh"
6167 (define_insn "maveh"
6168 [(set (match_operand:SI 0 "fpr_operand" "=f")
6169 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6170 (match_operand:SI 2 "fpr_operand" "f")]
6174 [(set_attr "length" "4")
6175 (set_attr "type" "maveh")])
6177 ;; Dual saturation (halfword): type "msath"
6179 (define_expand "msaths"
6180 [(set (match_operand:SI 0 "fpr_operand" "=f")
6181 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6182 (match_operand:SI 2 "fpr_operand" "f")
6186 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
6188 (define_expand "msathu"
6189 [(set (match_operand:SI 0 "fpr_operand" "=f")
6190 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6191 (match_operand:SI 2 "fpr_operand" "f")
6195 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
6197 (define_insn "*msath"
6198 [(set (match_operand:SI 0 "fpr_operand" "=f")
6199 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6200 (match_operand:SI 2 "fpr_operand" "f")
6201 (match_operand:SI 3 "const_int_operand" "n")]
6206 switch (INTVAL (operands[3]))
6209 case FRV_BUILTIN_MSATHS: return \"msaths %1, %2, %0\";
6210 case FRV_BUILTIN_MSATHU: return \"msathu %1, %2, %0\";
6213 fatal_insn (\"Bad media insn, msath\", insn);
6215 [(set_attr "length" "4")
6216 (set_attr "type" "msath")])
6218 ;; Dual addition/subtraction with saturation (halfword): type "maddh"
6220 (define_expand "maddhss"
6221 [(set (match_operand:SI 0 "fpr_operand" "=f")
6222 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6223 (match_operand:SI 2 "fpr_operand" "f")
6227 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
6229 (define_expand "maddhus"
6230 [(set (match_operand:SI 0 "fpr_operand" "=f")
6231 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6232 (match_operand:SI 2 "fpr_operand" "f")
6236 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
6238 (define_expand "msubhss"
6239 [(set (match_operand:SI 0 "fpr_operand" "=f")
6240 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6241 (match_operand:SI 2 "fpr_operand" "f")
6245 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
6247 (define_expand "msubhus"
6248 [(set (match_operand:SI 0 "fpr_operand" "=f")
6249 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6250 (match_operand:SI 2 "fpr_operand" "f")
6254 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
6256 (define_insn "*maddh"
6257 [(set (match_operand:SI 0 "fpr_operand" "=f")
6258 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6259 (match_operand:SI 2 "fpr_operand" "f")
6260 (match_operand:SI 3 "const_int_operand" "n")]
6265 switch (INTVAL (operands[3]))
6268 case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
6269 case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
6270 case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
6271 case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
6274 fatal_insn (\"Bad media insn, maddh\", insn);
6276 [(set_attr "length" "4")
6277 (set_attr "type" "maddh")])
6279 (define_insn "*cond_exec_maddh"
6281 (match_operator 0 "ccr_eqne_operator"
6282 [(match_operand 1 "cr_operand" "C")
6284 (set (match_operand:SI 2 "fpr_operand" "=f")
6285 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6286 (match_operand:SI 4 "fpr_operand" "f")
6287 (match_operand:SI 5 "const_int_operand" "n")]
6292 switch (INTVAL (operands[5]))
6295 case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
6296 case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
6297 case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
6298 case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
6301 fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
6303 [(set_attr "length" "4")
6304 (set_attr "type" "maddh")])
6306 ;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
6308 (define_expand "mqaddhss"
6309 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6310 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6311 (match_operand:DI 2 "even_fpr_operand" "h")
6315 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
6317 (define_expand "mqaddhus"
6318 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6319 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6320 (match_operand:DI 2 "even_fpr_operand" "h")
6324 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
6326 (define_expand "mqsubhss"
6327 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6328 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6329 (match_operand:DI 2 "even_fpr_operand" "h")
6333 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
6335 (define_expand "mqsubhus"
6336 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6337 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6338 (match_operand:DI 2 "even_fpr_operand" "h")
6342 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
6344 (define_insn "*mqaddh"
6345 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6346 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6347 (match_operand:DI 2 "even_fpr_operand" "h")
6348 (match_operand:SI 3 "const_int_operand" "n")]
6353 switch (INTVAL (operands[3]))
6356 case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
6357 case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
6358 case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
6359 case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
6362 fatal_insn (\"Bad media insn, mqaddh\", insn);
6364 [(set_attr "length" "4")
6365 (set_attr "type" "mqaddh")])
6367 (define_insn "*cond_exec_mqaddh"
6369 (match_operator 0 "ccr_eqne_operator"
6370 [(match_operand 1 "cr_operand" "C")
6372 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6373 (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
6374 (match_operand:DI 4 "even_fpr_operand" "h")
6375 (match_operand:SI 5 "const_int_operand" "n")]
6380 switch (INTVAL (operands[5]))
6383 case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
6384 case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
6385 case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
6386 case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
6389 fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
6391 [(set_attr "length" "4")
6392 (set_attr "type" "mqaddh")])
6394 ;; Pack halfword: type "mpackh"
6396 (define_insn "mpackh"
6397 [(set (match_operand:SI 0 "fpr_operand" "=f")
6398 (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
6399 (match_operand:HI 2 "fpr_operand" "f")]
6403 [(set_attr "length" "4")
6404 (set_attr "type" "mpackh")])
6406 ;; Unpack halfword: type "mpackh"
6408 (define_insn "munpackh"
6409 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6410 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6414 [(set_attr "length" "4")
6415 (set_attr "type" "munpackh")])
6417 ;; Dual pack halfword: type "mdpackh"
6419 (define_insn "mdpackh"
6420 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6421 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6422 (match_operand:DI 2 "even_fpr_operand" "h")]
6425 "mdpackh %1, %2, %0"
6426 [(set_attr "length" "4")
6427 (set_attr "type" "mdpackh")])
6429 ;; Byte-halfword conversion: type "mbhconv"
6431 (define_insn "mbtoh"
6432 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6433 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6437 [(set_attr "length" "4")
6438 (set_attr "type" "mbhconv")])
6440 (define_insn "*cond_exec_mbtoh"
6442 (match_operator 0 "ccr_eqne_operator"
6443 [(match_operand 1 "cr_operand" "C")
6445 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6446 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6449 "cmbtoh %3, %2, %1, %e0"
6450 [(set_attr "length" "4")
6451 (set_attr "type" "mbhconv")])
6453 (define_insn "mhtob"
6454 [(set (match_operand:SI 0 "fpr_operand" "=f")
6455 (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6459 [(set_attr "length" "4")
6460 (set_attr "type" "mbhconv")])
6462 (define_insn "*cond_exec_mhtob"
6464 (match_operator 0 "ccr_eqne_operator"
6465 [(match_operand 1 "cr_operand" "C")
6467 (set (match_operand:SI 2 "fpr_operand" "=f")
6468 (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6471 "cmhtob %3, %2, %1, %e0"
6472 [(set_attr "length" "4")
6473 (set_attr "type" "mbhconv")])
6475 ;; Rotate: type "mrot"
6477 (define_expand "mrotli"
6478 [(set (match_operand:SI 0 "fpr_operand" "")
6479 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6480 (match_operand:SI 2 "uint5_operand" "")
6484 "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6486 (define_expand "mrotri"
6487 [(set (match_operand:SI 0 "fpr_operand" "")
6488 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6489 (match_operand:SI 2 "uint5_operand" "")
6493 "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6495 (define_insn "*mrot"
6496 [(set (match_operand:SI 0 "fpr_operand" "=f")
6497 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6498 (match_operand:SI 2 "uint5_operand" "I")
6499 (match_operand:SI 3 "const_int_operand" "n")]
6504 switch (INTVAL (operands[3]))
6507 case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6508 case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6511 fatal_insn (\"Bad media insn, mrot\", insn);
6513 [(set_attr "length" "4")
6514 (set_attr "type" "mrot")])
6516 ;; Dual shift halfword: type "msh"
6518 (define_expand "msllhi"
6519 [(set (match_operand:SI 0 "fpr_operand" "")
6520 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6521 (match_operand:SI 2 "uint4_operand" "")
6525 "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6527 (define_expand "msrlhi"
6528 [(set (match_operand:SI 0 "fpr_operand" "")
6529 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6530 (match_operand:SI 2 "uint4_operand" "")
6534 "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6536 (define_expand "msrahi"
6537 [(set (match_operand:SI 0 "fpr_operand" "")
6538 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6539 (match_operand:SI 2 "uint4_operand" "")
6543 "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6545 (define_insn "*mshift"
6546 [(set (match_operand:SI 0 "fpr_operand" "=f")
6547 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6548 (match_operand:SI 2 "uint4_operand" "I")
6549 (match_operand:SI 3 "const_int_operand" "n")]
6554 switch (INTVAL (operands[3]))
6557 case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6558 case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6559 case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6562 fatal_insn (\"Bad media insn, mshift\", insn);
6564 [(set_attr "length" "4")
6565 (set_attr "type" "mshift")])
6567 ;; Expand halfword to word: type "mexpdhw"
6569 (define_insn "mexpdhw"
6570 [(set (match_operand:SI 0 "fpr_operand" "=f")
6571 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6572 (match_operand:SI 2 "uint1_operand" "I")]
6575 "mexpdhw %1, %2, %0"
6576 [(set_attr "length" "4")
6577 (set_attr "type" "mexpdhw")])
6579 (define_insn "*cond_exec_mexpdhw"
6581 (match_operator 0 "ccr_eqne_operator"
6582 [(match_operand 1 "cr_operand" "C")
6584 (set (match_operand:SI 2 "fpr_operand" "=f")
6585 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6586 (match_operand:SI 4 "uint1_operand" "I")]
6589 "cmexpdhw %3, %4, %2, %1, %e0"
6590 [(set_attr "length" "4")
6591 (set_attr "type" "mexpdhw")])
6593 ;; Expand halfword to double: type "mexpdhd"
6595 (define_insn "mexpdhd"
6596 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6597 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6598 (match_operand:SI 2 "uint1_operand" "I")]
6601 "mexpdhd %1, %2, %0"
6602 [(set_attr "length" "4")
6603 (set_attr "type" "mexpdhd")])
6605 (define_insn "*cond_exec_mexpdhd"
6607 (match_operator 0 "ccr_eqne_operator"
6608 [(match_operand 1 "cr_operand" "C")
6610 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6611 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6612 (match_operand:SI 4 "uint1_operand" "I")]
6615 "cmexpdhd %3, %4, %2, %1, %e0"
6616 [(set_attr "length" "4")
6617 (set_attr "type" "mexpdhd")])
6619 ;; FR cut: type "mwcut"
6621 (define_insn "mwcut"
6622 [(set (match_operand:SI 0 "fpr_operand" "=f")
6623 (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6624 (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6627 "mwcut%i2 %1, %2, %0"
6628 [(set_attr "length" "4")
6629 (set_attr "type" "mwcut")])
6631 ;; Dual multiplication (halfword): type "mmulh"
6633 (define_expand "mmulhs"
6634 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6635 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6636 (match_operand:SI 2 "fpr_operand" "f")
6639 (set (match_operand:HI 3 "accg_operand" "=B")
6640 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6642 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6644 (define_expand "mmulhu"
6645 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6646 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6647 (match_operand:SI 2 "fpr_operand" "f")
6650 (set (match_operand:HI 3 "accg_operand" "=B")
6651 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6653 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6655 (define_insn "*mmulh"
6656 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6657 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6658 (match_operand:SI 2 "fpr_operand" "f")
6659 (match_operand:SI 3 "const_int_operand" "n")]
6661 (set (match_operand:HI 4 "accg_operand" "=B")
6662 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6666 switch (INTVAL (operands[3]))
6669 case FRV_BUILTIN_MMULHS: return \"mmulhs %1, %2, %0\";
6670 case FRV_BUILTIN_MMULHU: return \"mmulhu %1, %2, %0\";
6673 fatal_insn (\"Bad media insn, mmulh\", insn);
6675 [(set_attr "length" "4")
6676 (set_attr "type" "mmulh")])
6678 (define_insn "*cond_exec_mmulh"
6680 (match_operator 0 "ccr_eqne_operator"
6681 [(match_operand 1 "cr_operand" "C")
6683 (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6684 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6685 (match_operand:SI 4 "fpr_operand" "f")
6686 (match_operand:SI 5 "const_int_operand" "n")]
6688 (set (match_operand:HI 6 "accg_operand" "=B")
6689 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6693 switch (INTVAL (operands[5]))
6696 case FRV_BUILTIN_MMULHS: return \"cmmulhs %3, %4, %2, %1, %e0\";
6697 case FRV_BUILTIN_MMULHU: return \"cmmulhu %3, %4, %2, %1, %e0\";
6700 fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6702 [(set_attr "length" "4")
6703 (set_attr "type" "mmulh")])
6705 ;; Dual cross multiplication (halfword): type "mmulxh"
6707 (define_expand "mmulxhs"
6708 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6709 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6710 (match_operand:SI 2 "fpr_operand" "f")
6713 (set (match_operand:HI 3 "accg_operand" "=B")
6714 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6716 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6718 (define_expand "mmulxhu"
6719 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6720 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6721 (match_operand:SI 2 "fpr_operand" "f")
6724 (set (match_operand:HI 3 "accg_operand" "=B")
6725 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6727 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6729 (define_insn "*mmulxh"
6730 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6731 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6732 (match_operand:SI 2 "fpr_operand" "f")
6733 (match_operand:SI 3 "const_int_operand" "n")]
6735 (set (match_operand:HI 4 "accg_operand" "=B")
6736 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6740 switch (INTVAL (operands[3]))
6743 case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6744 case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6747 fatal_insn (\"Bad media insn, mmulxh\", insn);
6749 [(set_attr "length" "4")
6750 (set_attr "type" "mmulxh")])
6752 ;; Dual product-sum (halfword): type "mmach"
6754 (define_expand "mmachs"
6755 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6756 (unspec:DI [(match_dup 0)
6757 (match_operand:SI 1 "fpr_operand" "f")
6758 (match_operand:SI 2 "fpr_operand" "f")
6759 (match_operand:HI 3 "accg_operand" "+B")
6763 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6765 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6767 (define_expand "mmachu"
6768 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6769 (unspec:DI [(match_dup 0)
6770 (match_operand:SI 1 "fpr_operand" "f")
6771 (match_operand:SI 2 "fpr_operand" "f")
6772 (match_operand:HI 3 "accg_operand" "+B")
6776 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6778 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6780 (define_insn "*mmach"
6781 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6782 (unspec:DI [(match_dup 0)
6783 (match_operand:SI 1 "fpr_operand" "f")
6784 (match_operand:SI 2 "fpr_operand" "f")
6785 (match_operand:HI 3 "accg_operand" "+B")
6786 (match_operand:SI 4 "const_int_operand" "n")]
6788 (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6792 switch (INTVAL (operands[4]))
6795 case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6796 case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6799 fatal_insn (\"Bad media insn, mmach\", insn);
6801 [(set_attr "length" "4")
6802 (set_attr "type" "mmach")])
6804 (define_insn "*cond_exec_mmach"
6806 (match_operator 0 "ccr_eqne_operator"
6807 [(match_operand 1 "cr_operand" "C")
6809 (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6810 (unspec:DI [(match_dup 2)
6811 (match_operand:SI 3 "fpr_operand" "f")
6812 (match_operand:SI 4 "fpr_operand" "f")
6813 (match_operand:HI 5 "accg_operand" "+B")
6814 (match_operand:SI 6 "const_int_operand" "n")]
6817 (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6821 switch (INTVAL (operands[6]))
6824 case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6825 case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6828 fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6830 [(set_attr "length" "4")
6831 (set_attr "type" "mmach")])
6833 ;; Dual product-difference: type "mmrdh"
6835 (define_expand "mmrdhs"
6836 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6837 (unspec:DI [(match_dup 0)
6838 (match_operand:SI 1 "fpr_operand" "f")
6839 (match_operand:SI 2 "fpr_operand" "f")
6840 (match_operand:HI 3 "accg_operand" "+B")
6844 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6846 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6848 (define_expand "mmrdhu"
6849 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6850 (unspec:DI [(match_dup 0)
6851 (match_operand:SI 1 "fpr_operand" "f")
6852 (match_operand:SI 2 "fpr_operand" "f")
6853 (match_operand:HI 3 "accg_operand" "+B")
6857 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6859 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6861 (define_insn "*mmrdh"
6862 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6863 (unspec:DI [(match_dup 0)
6864 (match_operand:SI 1 "fpr_operand" "f")
6865 (match_operand:SI 2 "fpr_operand" "f")
6866 (match_operand:HI 3 "accg_operand" "+B")
6867 (match_operand:SI 4 "const_int_operand" "n")]
6870 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6874 switch (INTVAL (operands[4]))
6877 case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6878 case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6881 fatal_insn (\"Bad media insn, mrdh\", insn);
6883 [(set_attr "length" "4")
6884 (set_attr "type" "mmrdh")])
6886 ;; Quad multiply (halfword): type "mqmulh"
6888 (define_expand "mqmulhs"
6889 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6890 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6891 (match_operand:DI 2 "even_fpr_operand" "h")
6894 (set (match_operand:V4QI 3 "accg_operand" "=B")
6895 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6897 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6899 (define_expand "mqmulhu"
6900 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6901 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6902 (match_operand:DI 2 "even_fpr_operand" "h")
6905 (set (match_operand:V4QI 3 "accg_operand" "=B")
6906 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6908 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6910 (define_insn "*mqmulh"
6911 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6912 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6913 (match_operand:DI 2 "even_fpr_operand" "h")
6914 (match_operand:SI 3 "const_int_operand" "n")]
6916 (set (match_operand:V4QI 4 "accg_operand" "=B")
6917 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6921 switch (INTVAL (operands[3]))
6924 case FRV_BUILTIN_MQMULHS: return \"mqmulhs %1, %2, %0\";
6925 case FRV_BUILTIN_MQMULHU: return \"mqmulhu %1, %2, %0\";
6928 fatal_insn (\"Bad media insn, mqmulh\", insn);
6930 [(set_attr "length" "4")
6931 (set_attr "type" "mqmulh")])
6933 (define_insn "*cond_exec_mqmulh"
6935 (match_operator 0 "ccr_eqne_operator"
6936 [(match_operand 1 "cr_operand" "C")
6938 (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6939 (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6940 (match_operand:DI 4 "even_fpr_operand" "h")
6941 (match_operand:SI 5 "const_int_operand" "n")]
6943 (set (match_operand:V4QI 6 "accg_operand" "=B")
6944 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6948 switch (INTVAL (operands[5]))
6951 case FRV_BUILTIN_MQMULHS: return \"cmqmulhs %3, %4, %2, %1, %e0\";
6952 case FRV_BUILTIN_MQMULHU: return \"cmqmulhu %3, %4, %2, %1, %e0\";
6955 fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6957 [(set_attr "length" "4")
6958 (set_attr "type" "mqmulh")])
6960 ;; Quad cross multiply (halfword): type "mqmulxh"
6962 (define_expand "mqmulxhs"
6963 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6964 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6965 (match_operand:DI 2 "even_fpr_operand" "h")
6968 (set (match_operand:V4QI 3 "accg_operand" "=B")
6969 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6971 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6973 (define_expand "mqmulxhu"
6974 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6975 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6976 (match_operand:DI 2 "even_fpr_operand" "h")
6979 (set (match_operand:V4QI 3 "accg_operand" "=B")
6980 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6982 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6984 (define_insn "*mqmulxh"
6985 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6986 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6987 (match_operand:DI 2 "even_fpr_operand" "h")
6988 (match_operand:SI 3 "const_int_operand" "n")]
6990 (set (match_operand:V4QI 4 "accg_operand" "=B")
6991 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6995 switch (INTVAL (operands[3]))
6998 case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6999 case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
7002 fatal_insn (\"Bad media insn, mqmulxh\", insn);
7004 [(set_attr "length" "4")
7005 (set_attr "type" "mqmulxh")])
7007 ;; Quad product-sum (halfword): type "mqmach"
7009 (define_expand "mqmachs"
7010 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
7011 (unspec:V4SI [(match_dup 0)
7012 (match_operand:DI 1 "even_fpr_operand" "h")
7013 (match_operand:DI 2 "even_fpr_operand" "h")
7014 (match_operand:V4QI 3 "accg_operand" "+B")
7018 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
7020 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
7022 (define_expand "mqmachu"
7023 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
7024 (unspec:V4SI [(match_dup 0)
7025 (match_operand:DI 1 "even_fpr_operand" "h")
7026 (match_operand:DI 2 "even_fpr_operand" "h")
7027 (match_operand:V4QI 3 "accg_operand" "+B")
7031 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
7033 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
7035 (define_insn "*mqmach"
7036 [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
7037 (unspec:V4SI [(match_dup 0)
7038 (match_operand:DI 1 "even_fpr_operand" "h")
7039 (match_operand:DI 2 "even_fpr_operand" "h")
7040 (match_operand:V4QI 3 "accg_operand" "+B")
7041 (match_operand:SI 4 "const_int_operand" "n")]
7044 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
7048 switch (INTVAL (operands[4]))
7051 case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
7052 case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
7055 fatal_insn (\"Bad media insn, mqmach\", insn);
7057 [(set_attr "length" "4")
7058 (set_attr "type" "mqmach")])
7060 (define_insn "*cond_exec_mqmach"
7062 (match_operator 0 "ccr_eqne_operator"
7063 [(match_operand 1 "cr_operand" "C")
7065 (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
7066 (unspec:V4SI [(match_dup 2)
7067 (match_operand:DI 3 "even_fpr_operand" "h")
7068 (match_operand:DI 4 "even_fpr_operand" "h")
7069 (match_operand:V4QI 5 "accg_operand" "+B")
7070 (match_operand:SI 6 "const_int_operand" "n")]
7073 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
7077 switch (INTVAL (operands[6]))
7080 case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
7081 case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
7084 fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
7086 [(set_attr "length" "4")
7087 (set_attr "type" "mqmach")])
7089 ;; Dual complex number product-sum (halfword)
7091 (define_expand "mcpxrs"
7092 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7093 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7094 (match_operand:SI 2 "fpr_operand" "f")
7097 (set (match_operand:QI 3 "accg_operand" "=B")
7098 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7100 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
7102 (define_expand "mcpxru"
7103 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7104 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7105 (match_operand:SI 2 "fpr_operand" "f")
7108 (set (match_operand:QI 3 "accg_operand" "=B")
7109 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7111 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
7113 (define_expand "mcpxis"
7114 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7115 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7116 (match_operand:SI 2 "fpr_operand" "f")
7119 (set (match_operand:QI 3 "accg_operand" "=B")
7120 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7122 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
7124 (define_expand "mcpxiu"
7125 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7126 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7127 (match_operand:SI 2 "fpr_operand" "f")
7130 (set (match_operand:QI 3 "accg_operand" "=B")
7131 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7133 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
7135 (define_insn "*mcpx"
7136 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7137 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7138 (match_operand:SI 2 "fpr_operand" "f")
7139 (match_operand:SI 3 "const_int_operand" "n")]
7141 (set (match_operand:QI 4 "accg_operand" "=B")
7142 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7146 switch (INTVAL (operands[3]))
7149 case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
7150 case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
7151 case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
7152 case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
7155 fatal_insn (\"Bad media insn, mcpx\", insn);
7157 [(set_attr "length" "4")
7158 (set_attr "type" "mcpx")])
7160 (define_insn "*cond_exec_mcpx"
7162 (match_operator 0 "ccr_eqne_operator"
7163 [(match_operand 1 "cr_operand" "C")
7165 (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
7166 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
7167 (match_operand:SI 4 "fpr_operand" "f")
7168 (match_operand:SI 5 "const_int_operand" "n")]
7170 (set (match_operand:QI 6 "accg_operand" "=B")
7171 (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
7175 switch (INTVAL (operands[5]))
7178 case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
7179 case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
7180 case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
7181 case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
7184 fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
7186 [(set_attr "length" "4")
7187 (set_attr "type" "mcpx")])
7189 ;; Quad complex number product-sum (halfword): type "mqcpx"
7191 (define_expand "mqcpxrs"
7192 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7193 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7194 (match_operand:DI 2 "fpr_operand" "f")
7197 (set (match_operand:HI 3 "accg_operand" "=B")
7198 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7200 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
7202 (define_expand "mqcpxru"
7203 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7204 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7205 (match_operand:DI 2 "fpr_operand" "f")
7208 (set (match_operand:HI 3 "accg_operand" "=B")
7209 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7211 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
7213 (define_expand "mqcpxis"
7214 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7215 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7216 (match_operand:DI 2 "fpr_operand" "f")
7219 (set (match_operand:HI 3 "accg_operand" "=B")
7220 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7222 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
7224 (define_expand "mqcpxiu"
7225 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7226 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7227 (match_operand:DI 2 "fpr_operand" "f")
7230 (set (match_operand:HI 3 "accg_operand" "=B")
7231 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7233 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
7235 (define_insn "*mqcpx"
7236 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7237 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7238 (match_operand:DI 2 "fpr_operand" "f")
7239 (match_operand:SI 3 "const_int_operand" "n")]
7241 (set (match_operand:HI 4 "accg_operand" "=B")
7242 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
7246 switch (INTVAL (operands[3]))
7249 case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
7250 case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
7251 case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
7252 case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
7255 fatal_insn (\"Bad media insn, mqcpx\", insn);
7257 [(set_attr "length" "4")
7258 (set_attr "type" "mqcpx")])
7262 (define_expand "mcut"
7263 [(set (match_operand:SI 0 "fpr_operand" "=f")
7264 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7265 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7266 (match_operand:QI 3 "accg_operand" "B")
7270 "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
7272 (define_expand "mcutss"
7273 [(set (match_operand:SI 0 "fpr_operand" "=f")
7274 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7275 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7276 (match_operand:QI 3 "accg_operand" "B")
7280 "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
7282 (define_insn "*mcut"
7283 [(set (match_operand:SI 0 "fpr_operand" "=f")
7284 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7285 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7286 (match_operand:QI 3 "accg_operand" "B")
7287 (match_operand:SI 4 "const_int_operand" "n")]
7292 switch (INTVAL (operands[4]))
7295 case FRV_BUILTIN_MCUT: return \"mcut%i2 %1, %2, %0\";
7296 case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
7299 fatal_insn (\"Bad media insn, mcut\", insn);
7301 [(set_attr "length" "4")
7302 (set_attr "type" "mcut")])
7304 ;; Accumulator read: type "mrdacc"
7306 (define_insn "mrdacc"
7307 [(set (match_operand:SI 0 "fpr_operand" "=f")
7308 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
7311 [(set_attr "length" "4")
7312 (set_attr "type" "mrdacc")])
7314 (define_insn "mrdaccg"
7315 [(set (match_operand:SI 0 "fpr_operand" "=f")
7316 (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
7319 [(set_attr "length" "4")
7320 (set_attr "type" "mrdacc")])
7322 ;; Accumulator write: type "mwtacc"
7324 (define_insn "mwtacc"
7325 [(set (match_operand:SI 0 "acc_operand" "=a")
7326 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
7329 [(set_attr "length" "4")
7330 (set_attr "type" "mwtacc")])
7332 (define_insn "mwtaccg"
7333 [(set (match_operand:QI 0 "accg_operand" "=B")
7334 (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
7337 [(set_attr "length" "4")
7338 (set_attr "type" "mwtacc")])
7340 ;; Trap: This one executes on the control unit, not the media units.
7342 (define_insn "mtrap"
7343 [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
7346 [(set_attr "length" "4")
7347 (set_attr "type" "trap")])
7349 ;; Clear single accumulator: type "mclracc"
7351 (define_insn "mclracc_internal"
7352 [(set (match_operand:SI 0 "acc_operand" "=a")
7353 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7354 (set (match_operand:QI 1 "accg_operand" "=B")
7355 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
7358 [(set_attr "length" "4")
7359 (set_attr "type" "mclracc")])
7361 (define_expand "mclracc"
7362 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7363 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7365 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
7369 if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
7372 operands[1] = frv_matching_accg_for_acc (operands[0]);
7375 ;; Clear all accumulators: type "mclracca"
7377 (define_insn "mclracca8_internal"
7378 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7379 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7380 (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
7381 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7382 (set (match_operand:V4QI 2 "accg_operand" "=B")
7383 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7384 (set (match_operand:V4QI 3 "accg_operand" "=B")
7385 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7386 "TARGET_MEDIA && TARGET_ACC_8"
7388 [(set_attr "length" "4")
7389 (set_attr "type" "mclracca")])
7391 (define_insn "mclracca4_internal"
7392 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7393 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7394 (set (match_operand:V4QI 1 "accg_operand" "=B")
7395 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7396 "TARGET_MEDIA && TARGET_ACC_4"
7398 [(set_attr "length" "4")
7399 (set_attr "type" "mclracca")])
7401 (define_expand "mclracca8"
7402 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7403 (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7404 (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7405 (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7406 "TARGET_MEDIA && TARGET_ACC_8"
7409 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7410 operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + (~3 & ACC_MASK));
7411 operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7412 operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + (~3 & ACC_MASK));
7415 (define_expand "mclracca4"
7416 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7417 (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7418 "TARGET_MEDIA && TARGET_ACC_4"
7421 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7422 operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7425 (define_insn "mcop1"
7426 [(set (match_operand:SI 0 "fpr_operand" "=f")
7427 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7428 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7431 [(set_attr "length" "4")
7432 ;; What is the class of the insn ???
7433 (set_attr "type" "multi")])
7435 (define_insn "mcop2"
7436 [(set (match_operand:SI 0 "fpr_operand" "=f")
7437 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7438 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7441 [(set_attr "length" "4")
7442 ;; What is the class of the insn ???
7443 (set_attr "type" "multi")])
7445 (define_insn "*mdunpackh_internal"
7446 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7447 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7448 UNSPEC_MDUNPACKH_INTERNAL))]
7451 [(set_attr "length" "4")
7452 (set_attr "type" "mdunpackh")])
7454 (define_insn_and_split "mdunpackh"
7455 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7456 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7458 (clobber (match_scratch:V4SI 2 "=x"))]
7463 (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7470 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7471 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7472 operands[5] = frv_index_memory (operands[0], DImode, 1);
7473 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7475 [(set_attr "length" "20")
7476 (set_attr "type" "multi")])
7478 (define_insn "*mbtohe_internal"
7479 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7480 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7481 UNSPEC_MBTOHE_INTERNAL))]
7484 [(set_attr "length" "4")
7485 (set_attr "type" "mbhconve")])
7487 (define_insn_and_split "mbtohe"
7488 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7489 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7491 (clobber (match_scratch:V4SI 2 "=x"))]
7496 (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7503 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7504 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7505 operands[5] = frv_index_memory (operands[0], DImode, 1);
7506 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7508 [(set_attr "length" "20")
7509 (set_attr "type" "multi")])
7511 ;; Quad product-sum (halfword) instructions only found on the FR400.
7514 (define_expand "mqxmachs"
7515 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7516 (unspec:V4SI [(match_dup 0)
7517 (match_operand:DI 1 "even_fpr_operand" "")
7518 (match_operand:DI 2 "even_fpr_operand" "")
7519 (match_operand:V4QI 3 "accg_operand" "")
7523 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7525 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7527 (define_expand "mqxmacxhs"
7528 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7529 (unspec:V4SI [(match_dup 0)
7530 (match_operand:DI 1 "even_fpr_operand" "")
7531 (match_operand:DI 2 "even_fpr_operand" "")
7532 (match_operand:V4QI 3 "accg_operand" "")
7536 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7538 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7540 (define_expand "mqmacxhs"
7541 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7542 (unspec:V4SI [(match_dup 0)
7543 (match_operand:DI 1 "even_fpr_operand" "")
7544 (match_operand:DI 2 "even_fpr_operand" "")
7545 (match_operand:V4QI 3 "accg_operand" "")
7549 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7551 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7553 (define_insn "*mqmach2"
7554 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7555 (unspec:V4SI [(match_dup 0)
7556 (match_operand:DI 1 "even_fpr_operand" "h")
7557 (match_operand:DI 2 "even_fpr_operand" "h")
7558 (match_operand:V4QI 3 "accg_operand" "+B")
7559 (match_operand:SI 4 "const_int_operand" "n")]
7562 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7566 switch (INTVAL (operands[4]))
7569 case FRV_BUILTIN_MQXMACHS: return \"mqxmachs %1, %2, %0\";
7570 case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7571 case FRV_BUILTIN_MQMACXHS: return \"mqmacxhs %1, %2, %0\";
7574 fatal_insn (\"Bad media insn, mqmach2\", insn);
7576 [(set_attr "length" "4")
7577 (set_attr "type" "mqmach")])
7579 ;; Accumulator addition/subtraction: type "maddacc"
7581 (define_expand "maddaccs"
7582 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7583 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7585 (set (match_operand:QI 2 "accg_operand" "")
7586 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7590 "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7592 (define_expand "msubaccs"
7593 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7594 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7596 (set (match_operand:QI 2 "accg_operand" "")
7597 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7601 "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7603 (define_insn "masaccs"
7604 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7605 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")]
7607 (set (match_operand:HI 2 "accg_operand" "=B")
7608 (unspec:HI [(match_operand:HI 3 "accg_operand" "B")]
7612 [(set_attr "length" "4")
7613 (set_attr "type" "maddacc")])
7615 (define_insn "*maddacc"
7616 [(set (match_operand:SI 0 "acc_operand" "=a")
7617 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "b")]
7619 (set (match_operand:QI 2 "accg_operand" "=B")
7620 (unspec:QI [(match_operand:HI 3 "accg_operand" "B")
7621 (match_operand:SI 4 "const_int_operand" "n")]
7626 switch (INTVAL (operands[4]))
7629 case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7630 case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7633 fatal_insn (\"Bad media insn, maddacc\", insn);
7635 [(set_attr "length" "4")
7636 (set_attr "type" "maddacc")])
7638 ;; Dual accumulator addition/subtraction: type "mdaddacc"
7640 (define_expand "mdaddaccs"
7641 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7642 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7644 (set (match_operand:HI 2 "accg_operand" "")
7645 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7647 UNSPEC_MDADDACC))])]
7649 "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7651 (define_expand "mdsubaccs"
7652 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7653 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7655 (set (match_operand:HI 2 "accg_operand" "")
7656 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7658 UNSPEC_MDADDACC))])]
7660 "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7662 (define_insn "mdasaccs"
7663 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
7664 (unspec:V4SI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7666 (set (match_operand:V4QI 2 "accg_operand" "=B")
7667 (unspec:V4QI [(match_operand:V4QI 3 "accg_operand" "B")]
7671 [(set_attr "length" "4")
7672 (set_attr "type" "mdaddacc")])
7674 (define_insn "*mdaddacc"
7675 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7676 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7678 (set (match_operand:HI 2 "accg_operand" "=B")
7679 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "B")
7680 (match_operand:SI 4 "const_int_operand" "n")]
7685 switch (INTVAL (operands[4]))
7688 case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7689 case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7692 fatal_insn (\"Bad media insn, mdaddacc\", insn);
7694 [(set_attr "length" "4")
7695 (set_attr "type" "mdaddacc")])
7697 ;; Dual absolute (halfword): type "mabsh"
7699 (define_insn "mabshs"
7700 [(set (match_operand:SI 0 "fpr_operand" "=f")
7701 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7704 [(set_attr "length" "4")
7705 (set_attr "type" "mabsh")])
7707 ;; Dual rotate: type "mdrot"
7709 (define_insn "mdrotli"
7710 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7711 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7712 (match_operand:SI 2 "uint5_operand" "I")]
7715 "mdrotli %1, %2, %0"
7716 [(set_attr "length" "4")
7717 (set_attr "type" "mdrot")])
7719 ;; Dual coupling (concatenation): type "mcpl"
7721 (define_insn "mcplhi"
7722 [(set (match_operand:SI 0 "fpr_operand" "=f")
7723 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7724 (match_operand:SI 2 "uint4_operand" "I")]
7728 [(set_attr "length" "4")
7729 (set_attr "type" "mcpl")])
7731 (define_insn "mcpli"
7732 [(set (match_operand:SI 0 "fpr_operand" "=f")
7733 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7734 (match_operand:SI 2 "uint5_operand" "I")]
7738 [(set_attr "length" "4")
7739 (set_attr "type" "mcpl")])
7741 ;; Dual cut: type "mdcut"
7743 (define_insn "mdcutssi"
7744 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7745 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7746 (match_operand:SI 2 "int6_operand" "I")
7747 (match_operand:HI 3 "accg_operand" "B")]
7750 "mdcutssi %1, %2, %0"
7751 [(set_attr "length" "4")
7752 (set_attr "type" "mdcut")])
7754 ;; Quad saturate (halfword): type "mqsath"
7756 (define_insn "mqsaths"
7757 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7758 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7759 (match_operand:DI 2 "even_fpr_operand" "h")]
7762 "mqsaths %1, %2, %0"
7763 [(set_attr "length" "4")
7764 (set_attr "type" "mqsath")])
7766 ;; Quad limit instructions: type "mqlimh"
7768 (define_insn "mqlclrhs"
7769 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7770 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7771 (match_operand:DI 2 "even_fpr_operand" "h")]
7773 "TARGET_MEDIA_FR450"
7774 "mqlclrhs %1, %2, %0"
7775 [(set_attr "length" "4")
7776 (set_attr "type" "mqlimh")])
7778 (define_insn "mqlmths"
7779 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7780 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7781 (match_operand:DI 2 "even_fpr_operand" "h")]
7783 "TARGET_MEDIA_FR450"
7784 "mqlmths %1, %2, %0"
7785 [(set_attr "length" "4")
7786 (set_attr "type" "mqlimh")])
7788 (define_insn "mqsllhi"
7789 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7790 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7791 (match_operand:SI 2 "int6_operand" "I")]
7793 "TARGET_MEDIA_FR450"
7794 "mqsllhi %1, %2, %0"
7795 [(set_attr "length" "4")
7796 (set_attr "type" "mqshift")])
7798 (define_insn "mqsrahi"
7799 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7800 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7801 (match_operand:SI 2 "int6_operand" "I")]
7803 "TARGET_MEDIA_FR450"
7804 "mqsrahi %1, %2, %0"
7805 [(set_attr "length" "4")
7806 (set_attr "type" "mqshift")])
7808 ;; Set hi/lo instructions: type "mset"
7810 (define_insn "mhsetlos"
7811 [(set (match_operand:SI 0 "fpr_operand" "=f")
7812 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7813 (match_operand:SI 2 "int12_operand" "NOP")]
7817 [(set_attr "length" "4")
7818 (set_attr "type" "mset")])
7820 (define_insn "mhsetloh"
7821 [(set (match_operand:SI 0 "fpr_operand" "=f")
7822 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7823 (match_operand:SI 2 "int5_operand" "I")]
7827 [(set_attr "length" "4")
7828 (set_attr "type" "mset")])
7830 (define_insn "mhsethis"
7831 [(set (match_operand:SI 0 "fpr_operand" "=f")
7832 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7833 (match_operand:SI 2 "int12_operand" "NOP")]
7837 [(set_attr "length" "4")
7838 (set_attr "type" "mset")])
7840 (define_insn "mhsethih"
7841 [(set (match_operand:SI 0 "fpr_operand" "=f")
7842 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7843 (match_operand:SI 2 "int5_operand" "I")]
7847 [(set_attr "length" "4")
7848 (set_attr "type" "mset")])
7850 (define_insn "mhdsets"
7851 [(set (match_operand:SI 0 "fpr_operand" "=f")
7852 (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7856 [(set_attr "length" "4")
7857 (set_attr "type" "mset")])
7859 (define_insn "mhdseth"
7860 [(set (match_operand:SI 0 "fpr_operand" "=f")
7861 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7862 (match_operand:SI 2 "int5_operand" "I")]
7866 [(set_attr "length" "4")
7867 (set_attr "type" "mset")])
7869 ;;-----------------------------------------------------------------------------
7871 (define_expand "symGOT2reg"
7872 [(match_operand:SI 0 "" "")
7873 (match_operand:SI 1 "" "")
7874 (match_operand:SI 2 "" "")
7875 (match_operand:SI 3 "" "")]
7881 insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7883 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7885 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
7891 (define_expand "symGOT2reg_i"
7892 [(set (match_operand:SI 0 "" "")
7893 (mem:SI (plus:SI (match_operand:SI 2 "" "")
7894 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7895 (match_operand:SI 3 "" "")]
7900 (define_expand "symGOT2reg_hilo"
7902 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7903 (match_dup 4)] UNSPEC_GOT))))
7905 (lo_sum:SI (match_dup 6)
7906 (const:SI (unspec:SI [(match_dup 1)
7907 (match_operand:SI 3 "" "")]
7909 (set (match_operand:SI 0 "" "")
7910 (mem:SI (plus:SI (match_dup 5)
7911 (match_operand:SI 2 "" ""))))
7917 operands[6] = operands[5] = operands[0];
7920 operands[6] = gen_reg_rtx (SImode);
7921 operands[5] = gen_reg_rtx (SImode);
7924 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7925 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7928 (define_expand "symGOTOFF2reg_hilo"
7930 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7931 (match_dup 4)] UNSPEC_GOT))))
7933 (lo_sum:SI (match_dup 6)
7934 (const:SI (unspec:SI [(match_dup 1)
7935 (match_operand:SI 3 "" "")]
7937 (set (match_operand:SI 0 "" "")
7938 (plus:SI (match_dup 5)
7939 (match_operand:SI 2 "" "")))
7945 operands[6] = operands[5] = operands[0];
7948 operands[6] = gen_reg_rtx (SImode);
7949 operands[5] = gen_reg_rtx (SImode);
7952 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7953 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7956 (define_expand "symGOTOFF2reg"
7957 [(match_operand:SI 0 "" "")
7958 (match_operand:SI 1 "" "")
7959 (match_operand:SI 2 "" "")
7960 (match_operand:SI 3 "" "")]
7964 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3]));
7966 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
7972 (define_expand "symGOTOFF2reg_i"
7973 [(set (match_operand:SI 0 "" "")
7974 (plus:SI (match_operand:SI 2 "" "")
7976 (unspec:SI [(match_operand:SI 1 "" "")
7977 (match_operand:SI 3 "" "")]
7982 (define_expand "symGPREL2reg"
7983 [(match_operand:SI 0 "" "")
7984 (match_operand:SI 1 "" "")
7985 (match_operand:SI 2 "" "")
7986 (match_operand:SI 3 "" "")
7994 operands[4] = operands[0];
7996 operands[4] = gen_reg_rtx (SImode);
7998 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
8000 insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
8001 operands[4], operands[3]));
8003 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
8009 (define_expand "symGPREL2reg_hilo"
8010 [(match_operand:SI 0 "" "")
8011 (match_operand:SI 1 "" "")
8012 (match_operand:SI 2 "" "")
8013 (match_operand:SI 3 "" "")
8022 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
8023 GEN_INT (R_FRV_GOT12)));
8027 operands[4] = gen_reg_rtx (SImode);
8029 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
8031 insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
8032 operands[4], operands[3]));
8034 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
8051 (UNSPEC_PREFETCH0 163)
8052 (UNSPEC_PREFETCH 164)
8053 (UNSPEC_IACCreadll 165)
8054 (UNSPEC_IACCreadl 166)
8055 (UNSPEC_IACCsetll 167)
8056 (UNSPEC_IACCsetl 168)
8065 [(set (match_operand:DI 0 "integer_register_operand" "=d")
8066 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
8067 (match_operand:SI 2 "integer_register_operand" "d")]
8071 [(set_attr "length" "4")
8072 (set_attr "type" "mul")])
8075 [(set (match_operand:DI 0 "integer_register_operand" "=d")
8076 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
8077 (match_operand:SI 2 "integer_register_operand" "d")]
8081 [(set_attr "length" "4")
8082 (set_attr "type" "mul")])
8084 (define_insn "smass"
8085 [(set (reg:DI IACC0_REG)
8086 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8087 (match_operand:SI 1 "integer_register_operand" "d")
8090 "TARGET_FR405_BUILTINS"
8092 [(set_attr "length" "4")
8093 (set_attr "type" "macc")])
8095 (define_insn "smsss"
8096 [(set (reg:DI IACC0_REG)
8097 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8098 (match_operand:SI 1 "integer_register_operand" "d")
8101 "TARGET_FR405_BUILTINS"
8103 [(set_attr "length" "4")
8104 (set_attr "type" "macc")])
8107 [(set (reg:DI IACC0_REG)
8108 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
8109 (match_operand:SI 1 "integer_register_operand" "d")]
8111 "TARGET_FR405_BUILTINS"
8113 [(set_attr "length" "4")
8114 (set_attr "type" "macc")])
8116 (define_insn "addss"
8117 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8118 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8119 (match_operand:SI 2 "integer_register_operand" "d")]
8121 "TARGET_FR405_BUILTINS"
8123 [(set_attr "length" "4")
8124 (set_attr "type" "int")])
8126 (define_insn "subss"
8127 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8128 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8129 (match_operand:SI 2 "integer_register_operand" "d")]
8131 "TARGET_FR405_BUILTINS"
8133 [(set_attr "length" "4")
8134 (set_attr "type" "int")])
8136 (define_insn "slass"
8137 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8138 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8139 (match_operand:SI 2 "integer_register_operand" "d")]
8141 "TARGET_FR405_BUILTINS"
8143 [(set_attr "length" "4")
8144 (set_attr "type" "int")])
8147 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8148 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8149 (match_operand:SI 2 "integer_register_operand" "d")]
8153 [(set_attr "length" "4")
8154 (set_attr "type" "scan")])
8156 (define_insn "scutss"
8157 [(set (match_operand:SI 0 "integer_register_operand" "=d")
8158 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
8161 "TARGET_FR405_BUILTINS"
8163 [(set_attr "length" "4")
8164 (set_attr "type" "cut")])
8166 (define_insn "frv_prefetch0"
8167 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
8173 [(set_attr "length" "4")])
8175 (define_insn "frv_prefetch"
8176 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
8180 "TARGET_FR500_FR550_BUILTINS"
8181 "nop.p\\n\\tnldub @(%0, gr0), gr0"
8182 [(set_attr "length" "8")])
8186 (define_insn "call_gettlsoff"
8187 [(set (match_operand:SI 0 "register_operand" "=D09")
8189 [(match_operand:SI 1 "symbolic_operand" "")]
8191 (clobber (reg:SI GR8_REG))
8192 (clobber (reg:SI LRREG))
8193 (use (match_operand:SI 2 "register_operand" "D15"))]
8195 "call #gettlsoff(%a1)"
8196 [(set_attr "length" "4")
8197 (set_attr "type" "load_or_call")])
8199 ;; We have to expand this like a libcall (it sort of actually is)
8200 ;; because otherwise sched may move, for example, an insn that sets up
8201 ;; GR8 for a subsequence call before the *tls_indirect_call insn, and
8202 ;; then reload won't be able to fix things up.
8203 (define_expand "tls_indirect_call"
8204 [(set (reg:DI GR8_REG)
8205 (match_operand:DI 2 "register_operand" ""))
8207 [(set (reg:SI GR9_REG)
8209 [(match_operand:SI 1 "symbolic_operand" "")
8211 UNSPEC_TLS_INDIRECT_CALL))
8212 (clobber (reg:SI GR8_REG))
8213 (clobber (reg:SI LRREG))
8214 (use (match_operand:SI 3 "register_operand" ""))])
8215 (set (match_operand:SI 0 "register_operand" "")
8219 (define_insn "*tls_indirect_call"
8220 [(set (reg:SI GR9_REG)
8222 [(match_operand:SI 0 "symbolic_operand" "")
8224 UNSPEC_TLS_INDIRECT_CALL))
8225 (clobber (reg:SI GR8_REG))
8226 (clobber (reg:SI LRREG))
8227 ;; If there was a way to represent the fact that we don't need GR9
8228 ;; or GR15 to be set before this instruction (it could be in
8229 ;; parallel), we could use it here. This change wouldn't apply to
8230 ;; call_gettlsoff, thought, since the linker may turn the latter
8231 ;; into ldi @(gr15,offset),gr9.
8232 (use (match_operand:SI 1 "register_operand" "D15"))]
8234 "calll #gettlsoff(%a0)@(gr8,gr0)"
8235 [(set_attr "length" "4")
8236 (set_attr "type" "jumpl")])
8238 (define_insn "tls_load_gottlsoff12"
8239 [(set (match_operand:SI 0 "register_operand" "=r")
8241 [(match_operand:SI 1 "symbolic_operand" "")
8242 (match_operand:SI 2 "register_operand" "r")]
8243 UNSPEC_TLS_LOAD_GOTTLSOFF12))]
8245 "ldi @(%2, #gottlsoff12(%1)), %0"
8246 [(set_attr "length" "4")])
8248 (define_expand "tlsoff_hilo"
8249 [(set (match_operand:SI 0 "register_operand" "=r")
8250 (high:SI (const:SI (unspec:SI
8251 [(match_operand:SI 1 "symbolic_operand" "")
8252 (match_operand:SI 2 "immediate_operand" "n")]
8255 (lo_sum:SI (match_dup 0)
8256 (const:SI (unspec:SI [(match_dup 1)
8257 (match_dup 3)] UNSPEC_GOT))))]
8261 operands[3] = GEN_INT (INTVAL (operands[2]) + 1);
8264 ;; Just like movdi_ldd, but with relaxation annotations.
8265 (define_insn "tls_tlsdesc_ldd"
8266 [(set (match_operand:DI 0 "register_operand" "=r")
8267 (unspec:DI [(mem:DI (unspec:SI
8268 [(match_operand:SI 1 "register_operand" "r")
8269 (match_operand:SI 2 "register_operand" "r")
8270 (match_operand:SI 3 "symbolic_operand" "")]
8271 UNSPEC_TLS_TLSDESC_LDD_AUX))]
8272 UNSPEC_TLS_TLSDESC_LDD))]
8274 "ldd #tlsdesc(%a3)@(%1,%2), %0"
8275 [(set_attr "length" "4")
8276 (set_attr "type" "gload")])
8278 (define_insn "tls_tlsoff_ld"
8279 [(set (match_operand:SI 0 "register_operand" "=r")
8281 [(match_operand:SI 1 "register_operand" "r")
8282 (match_operand:SI 2 "register_operand" "r")
8283 (match_operand:SI 3 "symbolic_operand" "")]
8284 UNSPEC_TLS_TLSOFF_LD)))]
8286 "ld #tlsoff(%a3)@(%1,%2), %0"
8287 [(set_attr "length" "4")
8288 (set_attr "type" "gload")])
8290 (define_insn "tls_lddi"
8291 [(set (match_operand:DI 0 "register_operand" "=r")
8292 (unspec:DI [(match_operand:SI 1 "symbolic_operand" "")
8293 (match_operand:SI 2 "register_operand" "d")]
8296 "lddi @(%2, #gottlsdesc12(%a1)), %0"
8297 [(set_attr "length" "4")
8298 (set_attr "type" "gload")])