1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
47 #include "target-def.h"
50 #define FRV_INLINE inline
53 /* Temporary register allocation support structure. */
54 typedef struct frv_tmp_reg_struct
56 HARD_REG_SET regs; /* possible registers to allocate */
57 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
61 /* Register state information for VLIW re-packing phase. These values must fit
62 within an unsigned char. */
63 #define REGSTATE_DEAD 0x00 /* register is currently dead */
64 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
65 #define REGSTATE_LIVE 0x08 /* register is live */
66 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
67 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
68 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
69 #define REGSTATE_UNUSED 0x80 /* bit for hire */
70 #define REGSTATE_MASK 0xff /* mask for the bits to set */
72 /* conditional expression used */
73 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
75 /* the following is not sure in the reg_state bytes, so can have a larger value
77 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
79 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
87 /* Information required by frv_frame_access. */
90 /* This field is FRV_LOAD if registers are to be loaded from the stack and
91 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
92 the move is being done by the prologue code while FRV_LOAD implies it
93 is being done by the epilogue. */
96 /* The base register to use when accessing the stack. This may be the
97 frame pointer, stack pointer, or a temporary. The choice of register
98 depends on which part of the frame is being accessed and how big the
102 /* The offset of BASE from the bottom of the current frame, in bytes. */
104 } frv_frame_accessor_t;
106 /* Define the information needed to generate branch and scc insns. This is
107 stored from the compare operation. */
111 /* Conditional execution support gathered together in one structure */
114 /* Linked list of insns to add if the conditional execution conversion was
115 successful. Each link points to an EXPR_LIST which points to the pattern
116 of the insn to add, and the insn to be inserted before. */
117 rtx added_insns_list;
119 /* Identify which registers are safe to allocate for if conversions to
120 conditional execution. We keep the last allocated register in the
121 register classes between COND_EXEC statements. This will mean we allocate
122 different registers for each different COND_EXEC group if we can. This
123 might allow the scheduler to intermix two different COND_EXEC sections. */
124 frv_tmp_reg_t tmp_reg;
126 /* For nested IFs, identify which CC registers are used outside of setting
127 via a compare isnsn, and using via a check insn. This will allow us to
128 know if we can rewrite the register to use a different register that will
129 be paired with the CR register controlling the nested IF-THEN blocks. */
130 HARD_REG_SET nested_cc_ok_rewrite;
132 /* Temporary registers allocated to hold constants during conditional
134 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
136 /* Current number of temp registers available. */
137 int cur_scratch_regs;
139 /* Number of nested conditional execution blocks */
140 int num_nested_cond_exec;
142 /* Map of insns that set up constants in scratch registers. */
143 bitmap scratch_insns_bitmap;
145 /* Conditional execution test register (CC0..CC7) */
148 /* Conditional execution compare register that is paired with cr_reg, so that
149 nested compares can be done. The csubcc and caddcc instructions don't
150 have enough bits to specify both a CC register to be set and a CR register
151 to do the test on, so the same bit number is used for both. Needless to
152 say, this is rather inconvient for GCC. */
155 /* Extra CR registers used for &&, ||. */
159 /* Previous CR used in nested if, to make sure we are dealing with the same
160 nested if as the previous statement. */
161 rtx last_nested_if_cr;
165 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
167 /* Map register number to smallest register class. */
168 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
170 /* Map class letter into register class */
171 enum reg_class reg_class_from_letter[256];
173 /* Cached value of frv_stack_info */
174 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
176 /* -mbranch-cost= support */
177 const char *frv_branch_cost_string;
178 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
181 const char *frv_cpu_string; /* -mcpu= option */
182 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
184 /* -mcond-exec-insns= support */
185 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
186 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
188 /* -mcond-exec-temps= support */
189 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
190 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
192 /* -msched-lookahead=n */
193 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
194 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
196 /* Forward references */
197 static int frv_default_flags_for_cpu PARAMS ((void));
198 static int frv_string_begins_with PARAMS ((tree, const char *));
199 static FRV_INLINE int symbol_ref_small_data_p PARAMS ((rtx));
200 static FRV_INLINE int const_small_data_p PARAMS ((rtx));
201 static FRV_INLINE int plus_small_data_p PARAMS ((rtx, rtx));
202 static void frv_print_operand_memory_reference_reg
203 PARAMS ((FILE *, rtx));
204 static void frv_print_operand_memory_reference PARAMS ((FILE *, rtx, int));
205 static int frv_print_operand_jump_hint PARAMS ((rtx));
206 static FRV_INLINE int frv_regno_ok_for_base_p PARAMS ((int, int));
207 static rtx single_set_pattern PARAMS ((rtx));
208 static int frv_function_contains_far_jump PARAMS ((void));
209 static rtx frv_alloc_temp_reg PARAMS ((frv_tmp_reg_t *,
213 static rtx frv_frame_offset_rtx PARAMS ((int));
214 static rtx frv_frame_mem PARAMS ((enum machine_mode,
216 static rtx frv_dwarf_store PARAMS ((rtx, int));
217 static void frv_frame_insn PARAMS ((rtx, rtx));
218 static void frv_frame_access PARAMS ((frv_frame_accessor_t*,
220 static void frv_frame_access_multi PARAMS ((frv_frame_accessor_t*,
221 frv_stack_t *, int));
222 static void frv_frame_access_standard_regs PARAMS ((enum frv_stack_op,
224 static struct machine_function *frv_init_machine_status PARAMS ((void));
225 static int frv_legitimate_memory_operand PARAMS ((rtx,
228 static rtx frv_int_to_acc PARAMS ((enum insn_code,
230 static enum machine_mode frv_matching_accg_mode PARAMS ((enum machine_mode));
231 static rtx frv_read_argument PARAMS ((tree *));
232 static int frv_check_constant_argument PARAMS ((enum insn_code,
234 static rtx frv_legitimize_target PARAMS ((enum insn_code, rtx));
235 static rtx frv_legitimize_argument PARAMS ((enum insn_code,
237 static rtx frv_expand_set_builtin PARAMS ((enum insn_code,
239 static rtx frv_expand_unop_builtin PARAMS ((enum insn_code,
241 static rtx frv_expand_binop_builtin PARAMS ((enum insn_code,
243 static rtx frv_expand_cut_builtin PARAMS ((enum insn_code,
245 static rtx frv_expand_binopimm_builtin PARAMS ((enum insn_code,
247 static rtx frv_expand_voidbinop_builtin PARAMS ((enum insn_code,
249 static rtx frv_expand_voidtriop_builtin PARAMS ((enum insn_code,
251 static rtx frv_expand_voidaccop_builtin PARAMS ((enum insn_code,
253 static rtx frv_expand_mclracc_builtin PARAMS ((tree));
254 static rtx frv_expand_mrdacc_builtin PARAMS ((enum insn_code,
256 static rtx frv_expand_mwtacc_builtin PARAMS ((enum insn_code,
258 static rtx frv_expand_noargs_builtin PARAMS ((enum insn_code));
259 static rtx frv_emit_comparison PARAMS ((enum rtx_code, rtx,
261 static int frv_clear_registers_used PARAMS ((rtx *, void *));
262 static void frv_ifcvt_add_insn PARAMS ((rtx, rtx, int));
263 static rtx frv_ifcvt_rewrite_mem PARAMS ((rtx,
266 static rtx frv_ifcvt_load_value PARAMS ((rtx, rtx));
267 static void frv_registers_update PARAMS ((rtx, unsigned char [],
268 int [], int *, int));
269 static int frv_registers_used_p PARAMS ((rtx, unsigned char [],
271 static int frv_registers_set_p PARAMS ((rtx, unsigned char [],
273 static void frv_pack_insns PARAMS ((void));
274 static void frv_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
275 static void frv_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
276 static bool frv_assemble_integer PARAMS ((rtx, unsigned, int));
277 static const char * frv_strip_name_encoding PARAMS ((const char *));
278 static void frv_encode_section_info PARAMS ((tree, int));
279 static void frv_init_builtins PARAMS ((void));
280 static rtx frv_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
281 static bool frv_in_small_data_p PARAMS ((tree));
283 /* Initialize the GCC target structure. */
284 #undef TARGET_ASM_FUNCTION_PROLOGUE
285 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
286 #undef TARGET_ASM_FUNCTION_EPILOGUE
287 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
288 #undef TARGET_ASM_INTEGER
289 #define TARGET_ASM_INTEGER frv_assemble_integer
290 #undef TARGET_STRIP_NAME_ENCODING
291 #define TARGET_STRIP_NAME_ENCODING frv_strip_name_encoding
292 #undef TARGET_ENCODE_SECTION_INFO
293 #define TARGET_ENCODE_SECTION_INFO frv_encode_section_info
294 #undef TARGET_INIT_BUILTINS
295 #define TARGET_INIT_BUILTINS frv_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
298 #undef TARGET_IN_SMALL_DATA_P
299 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
301 struct gcc_target targetm = TARGET_INITIALIZER;
303 /* Given a SYMBOL_REF, return true if it points to small data. */
305 static FRV_INLINE int
306 symbol_ref_small_data_p (x)
309 return SDATA_NAME_P (XSTR (x, 0));
312 /* Given a CONST, return true if the symbol_ref points to small data. */
314 static FRV_INLINE int
315 const_small_data_p (x)
320 if (GET_CODE (XEXP (x, 0)) != PLUS)
323 x0 = XEXP (XEXP (x, 0), 0);
324 if (GET_CODE (x0) != SYMBOL_REF || !SDATA_NAME_P (XSTR (x0, 0)))
327 x1 = XEXP (XEXP (x, 0), 1);
328 if (GET_CODE (x1) != CONST_INT
329 || !IN_RANGE_P (INTVAL (x1), -2048, 2047))
335 /* Given a PLUS, return true if this is a small data reference. */
337 static FRV_INLINE int
338 plus_small_data_p (op0, op1)
342 if (GET_MODE (op0) == SImode
343 && GET_CODE (op0) == REG
344 && REGNO (op0) == SDA_BASE_REG)
346 if (GET_CODE (op1) == SYMBOL_REF)
347 return symbol_ref_small_data_p (op1);
349 if (GET_CODE (op1) == CONST)
350 return const_small_data_p (op1);
358 frv_default_flags_for_cpu ()
360 switch (frv_cpu_type)
362 case FRV_CPU_GENERIC:
363 return MASK_DEFAULT_FRV;
367 return MASK_DEFAULT_FR500;
370 return MASK_DEFAULT_FR400;
374 return MASK_DEFAULT_SIMPLE;
379 /* Sometimes certain combinations of command options do not make
380 sense on a particular target machine. You can define a macro
381 `OVERRIDE_OPTIONS' to take account of this. This macro, if
382 defined, is executed once just after all the command options have
385 Don't use this macro to turn on various extra optimizations for
386 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
389 frv_override_options ()
393 /* Set the cpu type */
396 if (strcmp (frv_cpu_string, "simple") == 0)
397 frv_cpu_type = FRV_CPU_SIMPLE;
399 else if (strcmp (frv_cpu_string, "tomcat") == 0)
400 frv_cpu_type = FRV_CPU_TOMCAT;
402 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
403 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
407 const char *p = frv_cpu_string + sizeof ("fr") - 1;
408 if (strcmp (p, "500") == 0)
409 frv_cpu_type = FRV_CPU_FR500;
411 else if (strcmp (p, "400") == 0)
412 frv_cpu_type = FRV_CPU_FR400;
414 else if (strcmp (p, "300") == 0)
415 frv_cpu_type = FRV_CPU_FR300;
417 else if (strcmp (p, "v") == 0)
418 frv_cpu_type = FRV_CPU_GENERIC;
421 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
425 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
427 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
428 linker about linking pic and non-pic code. */
431 if (!flag_pic) /* -fPIC */
434 if (! g_switch_set) /* -G0 */
441 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
443 if (write_symbols == DWARF_DEBUG && flag_pic)
444 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
446 /* Change the branch cost value */
447 if (frv_branch_cost_string)
448 frv_branch_cost_int = atoi (frv_branch_cost_string);
450 /* Change the # of insns to be converted to conditional execution */
451 if (frv_condexec_insns_str)
452 frv_condexec_insns = atoi (frv_condexec_insns_str);
454 /* Change # of temporary registers used to hold integer constants */
455 if (frv_condexec_temps_str)
456 frv_condexec_temps = atoi (frv_condexec_temps_str);
458 /* Change scheduling look ahead. */
459 if (frv_sched_lookahead_str)
460 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
462 /* A C expression whose value is a register class containing hard
463 register REGNO. In general there is more than one such class;
464 choose a class which is "minimal", meaning that no smaller class
465 also contains the register. */
467 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
469 enum reg_class class;
473 int gpr_reg = regno - GPR_FIRST;
474 if ((gpr_reg & 3) == 0)
477 else if ((gpr_reg & 1) == 0)
484 else if (FPR_P (regno))
486 int fpr_reg = regno - GPR_FIRST;
487 if ((fpr_reg & 3) == 0)
488 class = QUAD_FPR_REGS;
490 else if ((fpr_reg & 1) == 0)
497 else if (regno == LR_REGNO)
500 else if (regno == LCR_REGNO)
503 else if (ICC_P (regno))
506 else if (FCC_P (regno))
509 else if (ICR_P (regno))
512 else if (FCR_P (regno))
515 else if (ACC_P (regno))
517 int r = regno - ACC_FIRST;
519 class = QUAD_ACC_REGS;
520 else if ((r & 1) == 0)
521 class = EVEN_ACC_REGS;
526 else if (ACCG_P (regno))
532 regno_reg_class[regno] = class;
535 /* Check for small data option */
537 g_switch_value = SDATA_DEFAULT_SIZE;
539 /* A C expression which defines the machine-dependent operand
540 constraint letters for register classes. If CHAR is such a
541 letter, the value should be the register class corresponding to
542 it. Otherwise, the value should be `NO_REGS'. The register
543 letter `r', corresponding to class `GENERAL_REGS', will not be
544 passed to this macro; you do not need to handle it.
546 The following letters are unavailable, due to being used as
551 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
552 'Q', 'R', 'S', 'T', 'U'
554 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
556 for (i = 0; i < 256; i++)
557 reg_class_from_letter[i] = NO_REGS;
559 reg_class_from_letter['a'] = ACC_REGS;
560 reg_class_from_letter['b'] = EVEN_ACC_REGS;
561 reg_class_from_letter['c'] = CC_REGS;
562 reg_class_from_letter['d'] = GPR_REGS;
563 reg_class_from_letter['e'] = EVEN_REGS;
564 reg_class_from_letter['f'] = FPR_REGS;
565 reg_class_from_letter['h'] = FEVEN_REGS;
566 reg_class_from_letter['l'] = LR_REG;
567 reg_class_from_letter['q'] = QUAD_REGS;
568 reg_class_from_letter['t'] = ICC_REGS;
569 reg_class_from_letter['u'] = FCC_REGS;
570 reg_class_from_letter['v'] = ICR_REGS;
571 reg_class_from_letter['w'] = FCR_REGS;
572 reg_class_from_letter['x'] = QUAD_FPR_REGS;
573 reg_class_from_letter['y'] = LCR_REG;
574 reg_class_from_letter['z'] = SPR_REGS;
575 reg_class_from_letter['A'] = QUAD_ACC_REGS;
576 reg_class_from_letter['B'] = ACCG_REGS;
577 reg_class_from_letter['C'] = CR_REGS;
579 /* There is no single unaligned SI op for PIC code. Sometimes we
580 need to use ".4byte" and sometimes we need to use ".picptr".
581 See frv_assemble_integer for details. */
583 targetm.asm_out.unaligned_op.si = 0;
585 init_machine_status = frv_init_machine_status;
589 /* Some machines may desire to change what optimizations are performed for
590 various optimization levels. This macro, if defined, is executed once just
591 after the optimization level is determined and before the remainder of the
592 command options have been parsed. Values set in this macro are used as the
593 default values for the other command line options.
595 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
596 `-O' is specified, and 0 if neither is specified.
598 SIZE is nonzero if `-Os' is specified, 0 otherwise.
600 You should not use this macro to change options that are not
601 machine-specific. These should uniformly selected by the same optimization
602 level on all supported machines. Use this macro to enable machbine-specific
605 *Do not examine `write_symbols' in this macro!* The debugging options are
606 *not supposed to alter the generated code. */
608 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
609 scheduling pass at the current time. */
611 frv_optimization_options (level, size)
613 int size ATTRIBUTE_UNUSED;
617 #ifdef DISABLE_SCHED2
618 flag_schedule_insns_after_reload = 0;
627 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
630 frv_string_begins_with (name, prefix)
634 int prefix_len = strlen (prefix);
636 /* Remember: NAME's length includes the null terminator. */
637 return (TREE_STRING_LENGTH (name) > prefix_len
638 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
641 /* Encode section information of DECL, which is either a VAR_DECL,
642 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
644 For the FRV we want to record:
646 - whether the object lives in .sdata/.sbss.
647 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
652 frv_encode_section_info (decl, first)
658 if (TREE_CODE (decl) == VAR_DECL)
660 int size = int_size_in_bytes (TREE_TYPE (decl));
661 tree section_name = DECL_SECTION_NAME (decl);
664 /* Don't apply the -G flag to internal compiler structures. We
665 should leave such structures in the main data section, partly
666 for efficiency and partly because the size of some of them
667 (such as C++ typeinfos) is not known until later. */
668 if (!DECL_ARTIFICIAL (decl) && size > 0 && size <= g_switch_value)
671 /* If we already know which section the decl should be in, see if
672 it's a small data section. */
675 if (TREE_CODE (section_name) == STRING_CST)
677 if (frv_string_begins_with (section_name, ".sdata"))
679 if (frv_string_begins_with (section_name, ".sbss"))
688 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
689 char * str = xmalloc (2 + strlen (XSTR (sym_ref, 0)));
691 str[0] = SDATA_FLAG_CHAR;
692 strcpy (&str[1], XSTR (sym_ref, 0));
693 XSTR (sym_ref, 0) = str;
699 /* Zero or more C statements that may conditionally modify two variables
700 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
701 been initialized from the two preceding macros.
703 This is necessary in case the fixed or call-clobbered registers depend on
706 You need not define this macro if it has no work to do.
708 If the usage of an entire class of registers depends on the target flags,
709 you may indicate this to GCC by using this macro to modify `fixed_regs' and
710 `call_used_regs' to 1 for each of the registers in the classes which should
711 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
712 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
714 (However, if this class is not included in `GENERAL_REGS' and all of the
715 insn patterns whose constraints permit this class are controlled by target
716 switches, then GCC will automatically avoid using these registers when the
717 target switches are opposed to them.) */
720 frv_conditional_register_usage ()
724 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
725 fixed_regs[i] = call_used_regs[i] = 1;
727 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
728 fixed_regs[i] = call_used_regs[i] = 1;
730 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
731 fixed_regs[i] = call_used_regs[i] = 1;
733 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
734 fixed_regs[i] = call_used_regs[i] = 1;
736 /* Reserve the registers used for conditional execution. At present, we need
737 1 ICC and 1 ICR register. */
738 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
739 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
743 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
744 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
745 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
746 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
750 /* If -fpic, SDA_BASE_REG is the PIC register. */
751 if (g_switch_value == 0 && !flag_pic)
752 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
755 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
761 * Compute the stack frame layout
764 * +---------------+-----------------------+-----------------------+
765 * |Register |type |caller-save/callee-save|
766 * +---------------+-----------------------+-----------------------+
767 * |GR0 |Zero register | - |
768 * |GR1 |Stack pointer(SP) | - |
769 * |GR2 |Frame pointer(FP) | - |
770 * |GR3 |Hidden parameter | caller save |
771 * |GR4-GR7 | - | caller save |
772 * |GR8-GR13 |Argument register | caller save |
773 * |GR14-GR15 | - | caller save |
774 * |GR16-GR31 | - | callee save |
775 * |GR32-GR47 | - | caller save |
776 * |GR48-GR63 | - | callee save |
777 * |FR0-FR15 | - | caller save |
778 * |FR16-FR31 | - | callee save |
779 * |FR32-FR47 | - | caller save |
780 * |FR48-FR63 | - | callee save |
781 * +---------------+-----------------------+-----------------------+
785 * SP-> |-----------------------------------|
787 * |-----------------------------------|
788 * | Register save area |
789 * |-----------------------------------|
790 * | Local variable save area |
791 * FP-> |-----------------------------------|
793 * |-----------------------------------|
794 * | Hidden parameter save area |
795 * |-----------------------------------|
796 * | Return address(LR) storage area |
797 * |-----------------------------------|
798 * | Padding for alignment |
799 * |-----------------------------------|
800 * | Register argument area |
801 * OLD SP-> |-----------------------------------|
803 * |-----------------------------------|
806 * Argument area/Parameter area:
808 * When a function is called, this area is used for argument transfer. When
809 * the argument is set up by the caller function, this area is referred to as
810 * the argument area. When the argument is referenced by the callee function,
811 * this area is referred to as the parameter area. The area is allocated when
812 * all arguments cannot be placed on the argument register at the time of
815 * Register save area:
817 * This is a register save area that must be guaranteed for the caller
818 * function. This area is not secured when the register save operation is not
821 * Local variable save area:
823 * This is the area for local variables and temporary variables.
827 * This area stores the FP value of the caller function.
829 * Hidden parameter save area:
831 * This area stores the start address of the return value storage
832 * area for a struct/union return function.
833 * When a struct/union is used as the return value, the caller
834 * function stores the return value storage area start address in
835 * register GR3 and passes it to the caller function.
836 * The callee function interprets the address stored in the GR3
837 * as the return value storage area start address.
838 * When register GR3 needs to be saved into memory, the callee
839 * function saves it in the hidden parameter save area. This
840 * area is not secured when the save operation is not needed.
842 * Return address(LR) storage area:
844 * This area saves the LR. The LR stores the address of a return to the caller
845 * function for the purpose of function calling.
847 * Argument register area:
849 * This area saves the argument register. This area is not secured when the
850 * save operation is not needed.
854 * Arguments, the count of which equals the count of argument registers (6
855 * words), are positioned in registers GR8 to GR13 and delivered to the callee
856 * function. When a struct/union return function is called, the return value
857 * area address is stored in register GR3. Arguments not placed in the
858 * argument registers will be stored in the stack argument area for transfer
859 * purposes. When an 8-byte type argument is to be delivered using registers,
860 * it is divided into two and placed in two registers for transfer. When
861 * argument registers must be saved to memory, the callee function secures an
862 * argument register save area in the stack. In this case, a continuous
863 * argument register save area must be established in the parameter area. The
864 * argument register save area must be allocated as needed to cover the size of
865 * the argument register to be saved. If the function has a variable count of
866 * arguments, it saves all argument registers in the argument register save
869 * Argument Extension Format:
871 * When an argument is to be stored in the stack, its type is converted to an
872 * extended type in accordance with the individual argument type. The argument
873 * is freed by the caller function after the return from the callee function is
876 * +-----------------------+---------------+------------------------+
877 * | Argument Type |Extended Type |Stack Storage Size(byte)|
878 * +-----------------------+---------------+------------------------+
880 * |signed char |int | 4 |
881 * |unsigned char |int | 4 |
882 * |[signed] short int |int | 4 |
883 * |unsigned short int |int | 4 |
884 * |[signed] int |No extension | 4 |
885 * |unsigned int |No extension | 4 |
886 * |[signed] long int |No extension | 4 |
887 * |unsigned long int |No extension | 4 |
888 * |[signed] long long int |No extension | 8 |
889 * |unsigned long long int |No extension | 8 |
890 * |float |double | 8 |
891 * |double |No extension | 8 |
892 * |long double |No extension | 8 |
893 * |pointer |No extension | 4 |
894 * |struct/union |- | 4 (*1) |
895 * +-----------------------+---------------+------------------------+
897 * When a struct/union is to be delivered as an argument, the caller copies it
898 * to the local variable area and delivers the address of that area.
902 * +-------------------------------+----------------------+
903 * |Return Value Type |Return Value Interface|
904 * +-------------------------------+----------------------+
906 * |[signed|unsigned] char |GR8 |
907 * |[signed|unsigned] short int |GR8 |
908 * |[signed|unsigned] int |GR8 |
909 * |[signed|unsigned] long int |GR8 |
911 * |[signed|unsigned] long long int|GR8 & GR9 |
913 * |double |GR8 & GR9 |
914 * |long double |GR8 & GR9 |
915 * |struct/union |(*1) |
916 * +-------------------------------+----------------------+
918 * When a struct/union is used as the return value, the caller function stores
919 * the start address of the return value storage area into GR3 and then passes
920 * it to the callee function. The callee function interprets GR3 as the start
921 * address of the return value storage area. When this address needs to be
922 * saved in memory, the callee function secures the hidden parameter save area
923 * and saves the address in that area.
929 static frv_stack_t info, zero_info;
930 frv_stack_t *info_ptr = &info;
931 tree fndecl = current_function_decl;
939 /* If we've already calculated the values and reload is complete, just return now */
941 return frv_stack_cache;
943 /* Zero all fields */
946 /* Set up the register range information */
947 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
948 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
949 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
950 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
952 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
953 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
954 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
955 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
957 info_ptr->regs[STACK_REGS_LR].name = "lr";
958 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
959 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
960 info_ptr->regs[STACK_REGS_LR].special_p = 1;
962 info_ptr->regs[STACK_REGS_CC].name = "cc";
963 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
964 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
965 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
967 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
968 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
969 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
971 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
972 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
973 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
974 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
975 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
977 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
978 info_ptr->regs[STACK_REGS_STRUCT].first = STRUCT_VALUE_REGNUM;
979 info_ptr->regs[STACK_REGS_STRUCT].last = STRUCT_VALUE_REGNUM;
980 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
982 info_ptr->regs[STACK_REGS_FP].name = "fp";
983 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
984 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
985 info_ptr->regs[STACK_REGS_FP].special_p = 1;
987 /* Determine if this is a stdarg function. If so, allocate space to store
994 /* Find the last argument, and see if it is __builtin_va_alist. */
995 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
997 next_arg = TREE_CHAIN (cur_arg);
998 if (next_arg == (tree)0)
1000 if (DECL_NAME (cur_arg)
1001 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1009 /* Iterate over all of the register ranges */
1010 for (range = 0; range < STACK_REGS_MAX; range++)
1012 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1013 int first = reg_ptr->first;
1014 int last = reg_ptr->last;
1016 int size_2words = 0;
1019 /* Calculate which registers need to be saved & save area size */
1023 for (regno = first; regno <= last; regno++)
1025 if ((regs_ever_live[regno] && !call_used_regs[regno])
1026 || (current_function_calls_eh_return
1027 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1028 || (flag_pic && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1030 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1031 size_1word += UNITS_PER_WORD;
1036 /* Calculate whether we need to create a frame after everything else
1037 has been processed. */
1042 if (regs_ever_live[LR_REGNO]
1044 || frame_pointer_needed
1045 || (flag_pic && cfun->uses_pic_offset_table))
1047 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1048 size_1word += UNITS_PER_WORD;
1052 case STACK_REGS_STDARG:
1055 /* If this is a stdarg function with an non varardic argument split
1056 between registers and the stack, adjust the saved registers
1058 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1061 for (regno = first; regno <= last; regno++)
1063 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1064 size_1word += UNITS_PER_WORD;
1067 info_ptr->stdarg_size = size_1word;
1071 case STACK_REGS_STRUCT:
1072 if (cfun->returns_struct)
1074 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1075 size_1word += UNITS_PER_WORD;
1083 /* If this is a field, it only takes one word */
1084 if (reg_ptr->field_p)
1085 size_1word = UNITS_PER_WORD;
1087 /* Determine which register pairs can be saved together */
1088 else if (reg_ptr->dword_p && TARGET_DWORD)
1090 for (regno = first; regno < last; regno += 2)
1092 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1094 size_2words += 2 * UNITS_PER_WORD;
1095 size_1word -= 2 * UNITS_PER_WORD;
1096 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1097 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1102 reg_ptr->size_1word = size_1word;
1103 reg_ptr->size_2words = size_2words;
1105 if (! reg_ptr->special_p)
1107 info_ptr->regs_size_1word += size_1word;
1108 info_ptr->regs_size_2words += size_2words;
1113 /* Set up the sizes of each each field in the frame body, making the sizes
1114 of each be divisible by the size of a dword if dword operations might
1115 be used, or the size of a word otherwise. */
1116 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1118 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1119 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1120 + info_ptr->regs_size_1word,
1122 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1124 info_ptr->pretend_size = cfun->pretend_args_size;
1126 /* Work out the size of the frame, excluding the header. Both the frame
1127 body and register parameter area will be dword-aligned. */
1128 info_ptr->total_size
1129 = (ADDR_ALIGN (info_ptr->parameter_size
1130 + info_ptr->regs_size
1131 + info_ptr->vars_size,
1133 + ADDR_ALIGN (info_ptr->pretend_size
1134 + info_ptr->stdarg_size,
1135 2 * UNITS_PER_WORD));
1137 /* See if we need to create a frame at all, if so add header area. */
1138 if (info_ptr->total_size > 0
1139 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1140 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1142 offset = info_ptr->parameter_size;
1143 info_ptr->header_size = 4 * UNITS_PER_WORD;
1144 info_ptr->total_size += 4 * UNITS_PER_WORD;
1146 /* Calculate the offsets to save normal register pairs */
1147 for (range = 0; range < STACK_REGS_MAX; range++)
1149 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1150 if (! reg_ptr->special_p)
1152 int first = reg_ptr->first;
1153 int last = reg_ptr->last;
1156 for (regno = first; regno <= last; regno++)
1157 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1158 && regno != FRAME_POINTER_REGNUM
1159 && (regno < FIRST_ARG_REGNUM
1160 || regno > LAST_ARG_REGNUM))
1162 info_ptr->reg_offset[regno] = offset;
1163 offset += 2 * UNITS_PER_WORD;
1168 /* Calculate the offsets to save normal single registers */
1169 for (range = 0; range < STACK_REGS_MAX; range++)
1171 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1172 if (! reg_ptr->special_p)
1174 int first = reg_ptr->first;
1175 int last = reg_ptr->last;
1178 for (regno = first; regno <= last; regno++)
1179 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1180 && regno != FRAME_POINTER_REGNUM
1181 && (regno < FIRST_ARG_REGNUM
1182 || regno > LAST_ARG_REGNUM))
1184 info_ptr->reg_offset[regno] = offset;
1185 offset += UNITS_PER_WORD;
1190 /* Calculate the offset to save the local variables at. */
1191 offset = ADDR_ALIGN (offset, alignment);
1192 if (info_ptr->vars_size)
1194 info_ptr->vars_offset = offset;
1195 offset += info_ptr->vars_size;
1198 /* Align header to a dword-boundary. */
1199 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1201 /* Calculate the offsets in the fixed frame. */
1202 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1203 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1204 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1206 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1207 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1208 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1210 if (cfun->returns_struct)
1212 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1213 info_ptr->reg_offset[STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1214 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1217 /* Calculate the offsets to store the arguments passed in registers
1218 for stdarg functions. The register pairs are first and the single
1219 register if any is last. The register save area starts on a
1221 if (info_ptr->stdarg_size)
1223 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1224 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1227 /* Skip the header. */
1228 offset += 4 * UNITS_PER_WORD;
1229 for (regno = first; regno <= last; regno++)
1231 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1233 info_ptr->reg_offset[regno] = offset;
1234 offset += 2 * UNITS_PER_WORD;
1236 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1238 info_ptr->reg_offset[regno] = offset;
1239 offset += UNITS_PER_WORD;
1245 if (reload_completed)
1246 frv_stack_cache = info_ptr;
1252 /* Print the information about the frv stack offsets, etc. when debugging. */
1255 frv_debug_stack (info)
1261 info = frv_stack_info ();
1263 fprintf (stderr, "\nStack information for function %s:\n",
1264 ((current_function_decl && DECL_NAME (current_function_decl))
1265 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1268 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1269 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1270 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1271 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1272 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1274 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1275 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1276 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1277 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1279 for (range = 0; range < STACK_REGS_MAX; range++)
1281 frv_stack_regs_t *regs = &(info->regs[range]);
1282 if ((regs->size_1word + regs->size_2words) > 0)
1284 int first = regs->first;
1285 int last = regs->last;
1288 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1289 regs->name, regs->size_1word + regs->size_2words,
1290 regs->size_1word, regs->size_2words);
1292 for (regno = first; regno <= last; regno++)
1294 if (info->save_p[regno] == REG_SAVE_1WORD)
1295 fprintf (stderr, " %s (%d)", reg_names[regno],
1296 info->reg_offset[regno]);
1298 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1299 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1300 reg_names[regno+1], info->reg_offset[regno]);
1303 fputc ('\n', stderr);
1313 /* The following variable value is TRUE if the next output insn should
1314 finish cpu cycle. In order words the insn will have packing bit
1315 (which means absence of asm code suffix `.p' on assembler. */
1317 static int frv_insn_packing_flag;
1319 /* True if the current function contains a far jump. */
1322 frv_function_contains_far_jump ()
1324 rtx insn = get_insns ();
1326 && !(GET_CODE (insn) == JUMP_INSN
1327 /* Ignore tablejump patterns. */
1328 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1329 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1330 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1331 insn = NEXT_INSN (insn);
1332 return (insn != NULL);
1335 /* For the FRV, this function makes sure that a function with far jumps
1336 will return correctly. It also does the VLIW packing. */
1339 frv_function_prologue (file, size)
1341 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1343 /* If no frame was created, check whether the function uses a call
1344 instruction to implement a far jump. If so, save the link in gr3 and
1345 replace all returns to LR with returns to GR3. GR3 is used because it
1346 is call-clobbered, because is not available to the register allocator,
1347 and because all functions that take a hidden argument pointer will have
1349 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1353 /* Just to check that the above comment is true. */
1354 if (regs_ever_live[GPR_FIRST + 3])
1357 /* Generate the instruction that saves the link register. */
1358 fprintf (file, "\tmovsg lr,gr3\n");
1360 /* Replace the LR with GR3 in *return_internal patterns. The insn
1361 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1362 simply emit a different assembly directive because bralr and jmpl
1363 execute in different units. */
1364 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1365 if (GET_CODE (insn) == JUMP_INSN)
1367 rtx pattern = PATTERN (insn);
1368 if (GET_CODE (pattern) == PARALLEL
1369 && XVECLEN (pattern, 0) >= 2
1370 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1371 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1373 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1374 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1375 REGNO (address) = GPR_FIRST + 3;
1381 frv_insn_packing_flag = TRUE;
1385 /* Return the next available temporary register in a given class. */
1388 frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort)
1389 frv_tmp_reg_t *info; /* which registers are available */
1390 enum reg_class class; /* register class desired */
1391 enum machine_mode mode; /* mode to allocate register with */
1392 int mark_as_used; /* register not available after allocation */
1393 int no_abort; /* return NULL instead of aborting */
1395 int regno = info->next_reg[ (int)class ];
1396 int orig_regno = regno;
1397 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1402 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1403 && TEST_HARD_REG_BIT (info->regs, regno))
1406 if (++regno >= FIRST_PSEUDO_REGISTER)
1408 if (regno == orig_regno)
1417 nr = HARD_REGNO_NREGS (regno, mode);
1418 info->next_reg[ (int)class ] = regno + nr;
1421 for (i = 0; i < nr; i++)
1422 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1424 return gen_rtx_REG (mode, regno);
1428 /* Return an rtx with the value OFFSET, which will either be a register or a
1429 signed 12-bit integer. It can be used as the second operand in an "add"
1430 instruction, or as the index in a load or store.
1432 The function returns a constant rtx if OFFSET is small enough, otherwise
1433 it loads the constant into register OFFSET_REGNO and returns that. */
1435 frv_frame_offset_rtx (offset)
1438 rtx offset_rtx = GEN_INT (offset);
1439 if (IN_RANGE_P (offset, -2048, 2047))
1443 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1444 if (IN_RANGE_P (offset, -32768, 32767))
1445 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1448 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1449 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1455 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1456 prologue and epilogue uses such expressions to access the stack. */
1458 frv_frame_mem (mode, base, offset)
1459 enum machine_mode mode;
1463 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1465 frv_frame_offset_rtx (offset)));
1468 /* Generate a frame-related expression:
1470 (set REG (mem (plus (sp) (const_int OFFSET)))).
1472 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1473 instructions. Marking the expressions as frame-related is superfluous if
1474 the note contains just a single set. But if the note contains a PARALLEL
1475 or SEQUENCE that has several sets, each set must be individually marked
1476 as frame-related. */
1478 frv_dwarf_store (reg, offset)
1482 rtx set = gen_rtx_SET (VOIDmode,
1483 gen_rtx_MEM (GET_MODE (reg),
1484 plus_constant (stack_pointer_rtx,
1487 RTX_FRAME_RELATED_P (set) = 1;
1491 /* Emit a frame-related instruction whose pattern is PATTERN. The
1492 instruction is the last in a sequence that cumulatively performs the
1493 operation described by DWARF_PATTERN. The instruction is marked as
1494 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1497 frv_frame_insn (pattern, dwarf_pattern)
1501 rtx insn = emit_insn (pattern);
1502 RTX_FRAME_RELATED_P (insn) = 1;
1503 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1508 /* Emit instructions that transfer REG to or from the memory location (sp +
1509 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1510 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1511 function to store registers and only the epilogue uses it to load them.
1513 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1514 The generated instruction will use BASE as its base register. BASE may
1515 simply be the stack pointer, but if several accesses are being made to a
1516 region far away from the stack pointer, it may be more efficient to set
1517 up a temporary instead.
1519 Store instructions will be frame-related and will be annotated with the
1520 overall effect of the store. Load instructions will be followed by a
1521 (use) to prevent later optimizations from zapping them.
1523 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1524 as a temporary in such cases. */
1526 frv_frame_access (accessor, reg, stack_offset)
1527 frv_frame_accessor_t *accessor;
1531 enum machine_mode mode = GET_MODE (reg);
1532 rtx mem = frv_frame_mem (mode,
1534 stack_offset - accessor->base_offset);
1536 if (accessor->op == FRV_LOAD)
1538 if (SPR_P (REGNO (reg)))
1540 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1541 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1542 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1545 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1546 emit_insn (gen_rtx_USE (VOIDmode, reg));
1550 if (SPR_P (REGNO (reg)))
1552 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1553 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1554 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1555 frv_dwarf_store (reg, stack_offset));
1557 else if (GET_MODE (reg) == DImode)
1559 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1560 with a separate save for each register. */
1561 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1562 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1563 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1564 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1565 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1566 gen_rtx_PARALLEL (VOIDmode,
1567 gen_rtvec (2, set1, set2)));
1570 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1571 frv_dwarf_store (reg, stack_offset));
1575 /* A function that uses frv_frame_access to transfer a group of registers to
1576 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1577 is the stack information generated by frv_stack_info, and REG_SET is the
1578 number of the register set to transfer. */
1580 frv_frame_access_multi (accessor, info, reg_set)
1581 frv_frame_accessor_t *accessor;
1585 frv_stack_regs_t *regs_info;
1588 regs_info = &info->regs[reg_set];
1589 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1590 if (info->save_p[regno])
1591 frv_frame_access (accessor,
1592 info->save_p[regno] == REG_SAVE_2WORDS
1593 ? gen_rtx_REG (DImode, regno)
1594 : gen_rtx_REG (SImode, regno),
1595 info->reg_offset[regno]);
1598 /* Save or restore callee-saved registers that are kept outside the frame
1599 header. The function saves the registers if OP is FRV_STORE and restores
1600 them if OP is FRV_LOAD. INFO is the stack information generated by
1603 frv_frame_access_standard_regs (op, info)
1604 enum frv_stack_op op;
1607 frv_frame_accessor_t accessor;
1610 accessor.base = stack_pointer_rtx;
1611 accessor.base_offset = 0;
1612 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1613 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1614 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1618 /* Called after register allocation to add any instructions needed for the
1619 prologue. Using a prologue insn is favored compared to putting all of the
1620 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1621 to intermix instructions with the saves of the caller saved registers. In
1622 some cases, it might be necessary to emit a barrier instruction as the last
1623 insn to prevent such scheduling.
1625 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1626 so that the debug info generation code can handle them properly. */
1628 frv_expand_prologue ()
1630 frv_stack_t *info = frv_stack_info ();
1631 rtx sp = stack_pointer_rtx;
1632 rtx fp = frame_pointer_rtx;
1633 frv_frame_accessor_t accessor;
1635 if (TARGET_DEBUG_STACK)
1636 frv_debug_stack (info);
1638 if (info->total_size == 0)
1641 /* We're interested in three areas of the frame here:
1643 A: the register save area
1645 C: the header after B
1647 If the frame pointer isn't used, we'll have to set up A, B and C
1648 using the stack pointer. If the frame pointer is used, we'll access
1652 B: set up using sp or a temporary (see below)
1655 We set up B using the stack pointer if the frame is small enough.
1656 Otherwise, it's more efficient to copy the old stack pointer into a
1657 temporary and use that.
1659 Note that it's important to make sure the prologue and epilogue use the
1660 same registers to access A and C, since doing otherwise will confuse
1661 the aliasing code. */
1663 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1664 isn't used, the same method will serve for C. */
1665 accessor.op = FRV_STORE;
1666 if (frame_pointer_needed && info->total_size > 2048)
1670 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1671 accessor.base_offset = info->total_size;
1672 insn = emit_insn (gen_movsi (accessor.base, sp));
1676 accessor.base = stack_pointer_rtx;
1677 accessor.base_offset = 0;
1680 /* Allocate the stack space. */
1682 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1683 rtx dwarf_offset = GEN_INT (-info->total_size);
1685 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1688 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1691 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1692 and point the new one to that location. */
1693 if (frame_pointer_needed)
1695 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1697 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1698 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1700 rtx asm_src = plus_constant (accessor.base,
1701 fp_offset - accessor.base_offset);
1702 rtx dwarf_src = plus_constant (sp, fp_offset);
1704 /* Store the old frame pointer at (sp + FP_OFFSET). */
1705 frv_frame_access (&accessor, fp, fp_offset);
1707 /* Set up the new frame pointer. */
1708 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1709 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1711 /* Access region C from the frame pointer. */
1713 accessor.base_offset = fp_offset;
1716 /* Set up region C. */
1717 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1718 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1719 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1721 /* Set up region A. */
1722 frv_frame_access_standard_regs (FRV_STORE, info);
1724 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1725 scheduler from moving loads before the stores saving the registers. */
1726 if (info->stdarg_size > 0)
1727 emit_insn (gen_blockage ());
1729 /* Set up pic register/small data register for this function. */
1730 if (flag_pic && cfun->uses_pic_offset_table)
1731 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1732 gen_rtx_REG (Pmode, LR_REGNO),
1733 gen_rtx_REG (SImode, OFFSET_REGNO)));
1737 /* Under frv, all of the work is done via frv_expand_epilogue, but
1738 this function provides a convient place to do cleanup. */
1741 frv_function_epilogue (file, size)
1742 FILE *file ATTRIBUTE_UNUSED;
1743 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1745 frv_stack_cache = (frv_stack_t *)0;
1747 /* zap last used registers for conditional execution. */
1748 memset ((PTR) &frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1750 /* release the bitmap of created insns. */
1751 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1755 /* Called after register allocation to add any instructions needed for the
1756 epilogue. Using an epilogue insn is favored compared to putting all of the
1757 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1758 to intermix instructions with the saves of the caller saved registers. In
1759 some cases, it might be necessary to emit a barrier instruction as the last
1760 insn to prevent such scheduling.
1762 If SIBCALL_P is true, the final branch back to the calling function is
1763 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1764 we must not clobber any arguments used for parameter passing or any stack
1765 slots for arguments passed to the current function. */
1768 frv_expand_epilogue (sibcall_p)
1771 frv_stack_t *info = frv_stack_info ();
1772 rtx fp = frame_pointer_rtx;
1773 rtx sp = stack_pointer_rtx;
1777 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1779 /* Restore the stack pointer to its original value if alloca or the like
1781 if (! current_function_sp_is_unchanging)
1782 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1784 /* Restore the callee-saved registers that were used in this function. */
1785 frv_frame_access_standard_regs (FRV_LOAD, info);
1787 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1788 no return instruction should be emitted. */
1791 else if (info->save_p[LR_REGNO])
1796 /* Use the same method to access the link register's slot as we did in
1797 the prologue. In other words, use the frame pointer if available,
1798 otherwise use the stack pointer.
1800 LR_OFFSET is the offset of the link register's slot from the start
1801 of the frame and MEM is a memory rtx for it. */
1802 lr_offset = info->reg_offset[LR_REGNO];
1803 if (frame_pointer_needed)
1804 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1806 mem = frv_frame_mem (Pmode, sp, lr_offset);
1808 /* Load the old link register into a GPR. */
1809 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1810 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1813 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1815 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1816 the load is preserved. */
1817 if (frame_pointer_needed)
1819 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1820 emit_insn (gen_rtx_USE (VOIDmode, fp));
1823 /* Deallocate the stack frame. */
1824 if (info->total_size != 0)
1826 rtx offset = frv_frame_offset_rtx (info->total_size);
1827 emit_insn (gen_stack_adjust (sp, sp, offset));
1830 /* If this function uses eh_return, add the final stack adjustment now. */
1831 if (current_function_calls_eh_return)
1832 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1835 emit_jump_insn (gen_epilogue_return (return_addr));
1839 /* A C compound statement that outputs the assembler code for a thunk function,
1840 used to implement C++ virtual function calls with multiple inheritance. The
1841 thunk acts as a wrapper around a virtual function, adjusting the implicit
1842 object parameter before handing control off to the real function.
1844 First, emit code to add the integer DELTA to the location that contains the
1845 incoming first argument. Assume that this argument contains a pointer, and
1846 is the one used to pass the `this' pointer in C++. This is the incoming
1847 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1848 addition must preserve the values of all other incoming arguments.
1850 After the addition, emit code to jump to FUNCTION, which is a
1851 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1852 the return address. Hence returning from FUNCTION will return to whoever
1853 called the current `thunk'.
1855 The effect must be as if FUNCTION had been called directly with the adjusted
1856 first argument. This macro is responsible for emitting all of the code for
1857 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1860 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1861 extracted from it.) It might possibly be useful on some targets, but
1864 If you do not define this macro, the target-independent code in the C++
1865 frontend will generate a less efficient heavyweight thunk that calls
1866 FUNCTION instead of jumping to it. The generic approach does not support
1870 frv_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
1872 tree thunk_fndecl ATTRIBUTE_UNUSED;
1873 HOST_WIDE_INT delta;
1876 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1877 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1878 const char *name_jmp = reg_names[JUMP_REGNO];
1879 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1881 /* Do the add using an addi if possible */
1882 if (IN_RANGE_P (delta, -2048, 2047))
1883 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1886 const char *name_add = reg_names[TEMP_REGNO];
1887 fprintf (file, "\tsethi%s #hi(", parallel);
1888 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1889 fprintf (file, "),%s\n", name_add);
1890 fprintf (file, "\tsetlo #lo(");
1891 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1892 fprintf (file, "),%s\n", name_add);
1893 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1898 fprintf (file, "\tsethi%s #hi(", parallel);
1899 assemble_name (file, name_func);
1900 fprintf (file, "),%s\n", name_jmp);
1902 fprintf (file, "\tsetlo #lo(");
1903 assemble_name (file, name_func);
1904 fprintf (file, "),%s\n", name_jmp);
1908 /* Use JUMP_REGNO as a temporary PIC register. */
1909 const char *name_lr = reg_names[LR_REGNO];
1910 const char *name_gppic = name_jmp;
1911 const char *name_tmp = reg_names[TEMP_REGNO];
1913 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1914 fprintf (file, "\tcall 1f\n");
1915 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1916 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1917 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1918 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1919 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1921 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1922 assemble_name (file, name_func);
1923 fprintf (file, "),%s\n", name_tmp);
1925 fprintf (file, "\tsetlo #gprello(");
1926 assemble_name (file, name_func);
1927 fprintf (file, "),%s\n", name_tmp);
1929 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1932 /* Jump to the function address */
1933 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1937 /* A C expression which is nonzero if a function must have and use a frame
1938 pointer. This expression is evaluated in the reload pass. If its value is
1939 nonzero the function will have a frame pointer.
1941 The expression can in principle examine the current function and decide
1942 according to the facts, but on most machines the constant 0 or the constant
1943 1 suffices. Use 0 when the machine allows code to be generated with no
1944 frame pointer, and doing so saves some time or space. Use 1 when there is
1945 no possible advantage to avoiding a frame pointer.
1947 In certain cases, the compiler does not know how to produce valid code
1948 without a frame pointer. The compiler recognizes those cases and
1949 automatically gives the function a frame pointer regardless of what
1950 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1952 In a function that does not require a frame pointer, the frame pointer
1953 register can be allocated for ordinary usage, unless you mark it as a fixed
1954 register. See `FIXED_REGISTERS' for more information. */
1956 /* On frv, create a frame whenever we need to create stack */
1959 frv_frame_pointer_required ()
1961 if (! current_function_is_leaf)
1964 if (get_frame_size () != 0)
1970 if (!current_function_sp_is_unchanging)
1973 if (flag_pic && cfun->uses_pic_offset_table)
1979 if (cfun->machine->frame_needed)
1986 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1987 initial difference between the specified pair of registers. This macro must
1988 be defined if `ELIMINABLE_REGS' is defined. */
1990 /* See frv_stack_info for more details on the frv stack frame. */
1993 frv_initial_elimination_offset (from, to)
1997 frv_stack_t *info = frv_stack_info ();
2000 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2001 ret = info->total_size - info->pretend_size;
2003 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2004 ret = - info->reg_offset[FRAME_POINTER_REGNUM];
2006 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2007 ret = (info->total_size
2008 - info->reg_offset[FRAME_POINTER_REGNUM]
2009 - info->pretend_size);
2014 if (TARGET_DEBUG_STACK)
2015 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2016 reg_names [from], reg_names[to], ret);
2022 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2023 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2024 arguments into the stack so that all the arguments appear to have been
2025 passed consecutively on the stack. Once this is done, you can use the
2026 standard implementation of varargs that works for machines that pass all
2027 their arguments on the stack.
2029 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2030 the values that obtain after processing of the named arguments. The
2031 arguments MODE and TYPE describe the last named argument--its machine mode
2032 and its data type as a tree node.
2034 The macro implementation should do two things: first, push onto the stack
2035 all the argument registers *not* used for the named arguments, and second,
2036 store the size of the data thus pushed into the `int'-valued variable whose
2037 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2038 store here will serve as additional offset for setting up the stack frame.
2040 Because you must generate code to push the anonymous arguments at compile
2041 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2042 useful on machines that have just a single category of argument register and
2043 use it uniformly for all data types.
2045 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2046 function are being analyzed for the second time. This happens for an inline
2047 function, which is not actually compiled until the end of the source file.
2048 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2052 frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2053 CUMULATIVE_ARGS *cum;
2054 enum machine_mode mode;
2055 tree type ATTRIBUTE_UNUSED;
2059 if (TARGET_DEBUG_ARG)
2061 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2062 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2066 /* If defined, is a C expression that produces the machine-specific code for a
2067 call to `__builtin_saveregs'. This code will be moved to the very beginning
2068 of the function, before any parameter access are made. The return value of
2069 this function should be an RTX that contains the value to use as the return
2070 of `__builtin_saveregs'.
2072 If this macro is not defined, the compiler will output an ordinary call to
2073 the library function `__builtin_saveregs'. */
2076 frv_expand_builtin_saveregs ()
2078 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2080 if (TARGET_DEBUG_ARG)
2081 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2084 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2088 /* Expand __builtin_va_start to do the va_start macro. */
2091 frv_expand_builtin_va_start (valist, nextarg)
2096 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2098 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2099 GEN_INT (UNITS_PER_WORD * num));
2101 if (TARGET_DEBUG_ARG)
2103 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2104 cfun->args_info, num);
2106 debug_rtx (nextarg);
2109 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2110 make_tree (ptr_type_node, nextarg));
2111 TREE_SIDE_EFFECTS (t) = 1;
2113 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2117 /* Expand __builtin_va_arg to do the va_arg macro. */
2120 frv_expand_builtin_va_arg(valist, type)
2128 if (TARGET_DEBUG_ARG)
2130 fprintf (stderr, "va_arg:\n");
2134 if (! AGGREGATE_TYPE_P (type))
2135 return std_expand_builtin_va_arg (valist, type);
2137 addr = std_expand_builtin_va_arg (valist, ptr_type_node);
2138 mem = gen_rtx_MEM (Pmode, addr);
2139 reg = gen_reg_rtx (Pmode);
2141 set_mem_alias_set (mem, get_varargs_alias_set ());
2142 emit_move_insn (reg, mem);
2148 /* Expand a block move operation, and return 1 if successful. Return 0
2149 if we should let the compiler generate normal code.
2151 operands[0] is the destination
2152 operands[1] is the source
2153 operands[2] is the length
2154 operands[3] is the alignment */
2156 /* Maximum number of loads to do before doing the stores */
2157 #ifndef MAX_MOVE_REG
2158 #define MAX_MOVE_REG 4
2161 /* Maximum number of total loads to do. */
2162 #ifndef TOTAL_MOVE_REG
2163 #define TOTAL_MOVE_REG 8
2167 frv_expand_block_move (operands)
2170 rtx orig_dest = operands[0];
2171 rtx orig_src = operands[1];
2172 rtx bytes_rtx = operands[2];
2173 rtx align_rtx = operands[3];
2174 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2187 rtx stores[MAX_MOVE_REG];
2189 enum machine_mode mode;
2191 /* If this is not a fixed size move, just call memcpy */
2195 /* If this is not a fixed size alignment, abort */
2196 if (GET_CODE (align_rtx) != CONST_INT)
2199 align = INTVAL (align_rtx);
2201 /* Anything to move? */
2202 bytes = INTVAL (bytes_rtx);
2206 /* Don't support real large moves. */
2207 if (bytes > TOTAL_MOVE_REG*align)
2210 /* Move the address into scratch registers. */
2211 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2212 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2214 num_reg = offset = 0;
2215 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2217 /* Calculate the correct offset for src/dest */
2221 dest_addr = dest_reg;
2225 src_addr = plus_constant (src_reg, offset);
2226 dest_addr = plus_constant (dest_reg, offset);
2229 /* Generate the appropriate load and store, saving the stores
2231 if (bytes >= 4 && align >= 4)
2233 else if (bytes >= 2 && align >= 2)
2238 move_bytes = GET_MODE_SIZE (mode);
2239 tmp_reg = gen_reg_rtx (mode);
2240 src_mem = change_address (orig_src, mode, src_addr);
2241 dest_mem = change_address (orig_dest, mode, dest_addr);
2242 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2243 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2245 if (num_reg >= MAX_MOVE_REG)
2247 for (i = 0; i < num_reg; i++)
2248 emit_insn (stores[i]);
2253 for (i = 0; i < num_reg; i++)
2254 emit_insn (stores[i]);
2260 /* Expand a block clear operation, and return 1 if successful. Return 0
2261 if we should let the compiler generate normal code.
2263 operands[0] is the destination
2264 operands[1] is the length
2265 operands[2] is the alignment */
2268 frv_expand_block_clear (operands)
2271 rtx orig_dest = operands[0];
2272 rtx bytes_rtx = operands[1];
2273 rtx align_rtx = operands[2];
2274 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2283 enum machine_mode mode;
2285 /* If this is not a fixed size move, just call memcpy */
2289 /* If this is not a fixed size alignment, abort */
2290 if (GET_CODE (align_rtx) != CONST_INT)
2293 align = INTVAL (align_rtx);
2295 /* Anything to move? */
2296 bytes = INTVAL (bytes_rtx);
2300 /* Don't support real large clears. */
2301 if (bytes > TOTAL_MOVE_REG*align)
2304 /* Move the address into a scratch register. */
2305 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2307 num_reg = offset = 0;
2308 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2310 /* Calculate the correct offset for src/dest */
2311 dest_addr = ((offset == 0)
2313 : plus_constant (dest_reg, offset));
2315 /* Generate the appropriate store of gr0 */
2316 if (bytes >= 4 && align >= 4)
2318 else if (bytes >= 2 && align >= 2)
2323 clear_bytes = GET_MODE_SIZE (mode);
2324 dest_mem = change_address (orig_dest, mode, dest_addr);
2325 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2332 /* The following variable is used to output modifiers of assembler
2333 code of the current output insn.. */
2335 static rtx *frv_insn_operands;
2337 /* The following function is used to add assembler insn code suffix .p
2338 if it is necessary. */
2341 frv_asm_output_opcode (f, ptr)
2347 if (! PACKING_FLAG_USED_P())
2350 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2353 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2354 || (*ptr >= 'A' && *ptr <= 'Z')))
2356 int letter = *ptr++;
2359 frv_print_operand (f, frv_insn_operands [c], letter);
2360 while ((c = *ptr) >= '0' && c <= '9')
2367 if (!frv_insn_packing_flag)
2373 /* The following function sets up the packing bit for the current
2374 output insn. Remember that the function is not called for asm
2378 frv_final_prescan_insn (insn, opvec, noperands)
2381 int noperands ATTRIBUTE_UNUSED;
2383 if (! PACKING_FLAG_USED_P())
2386 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
2389 frv_insn_operands = opvec;
2391 /* Look for the next printable instruction. frv_pack_insns () has set
2392 things up so that any printable instruction will have TImode if it
2393 starts a new packet and VOIDmode if it should be packed with the
2394 previous instruction.
2396 Printable instructions will be asm_operands or match one of the .md
2397 patterns. Since asm instructions cannot be packed -- and will
2398 therefore have TImode -- this loop terminates on any recognisable
2399 instruction, and on any unrecognisable instruction with TImode. */
2400 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2404 else if (!INSN_P (insn))
2406 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2410 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2411 be packed with this one. Set it to TRUE otherwise. If the next
2412 instruction is an asm insntruction, this statement will set the
2413 flag to TRUE, and that value will still hold when the asm operands
2414 themselves are printed. */
2415 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2416 && GET_MODE (insn) != TImode);
2421 /* A C expression whose value is RTL representing the address in a stack frame
2422 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2423 an RTL expression for the address of the stack frame itself.
2425 If you don't define this macro, the default is to return the value of
2426 FRAMEADDR--that is, the stack frame address is also the address of the stack
2427 word that points to the previous frame. */
2429 /* The default is correct, but we need to make sure the frame gets created. */
2431 frv_dynamic_chain_address (frame)
2434 cfun->machine->frame_needed = 1;
2439 /* A C expression whose value is RTL representing the value of the return
2440 address for the frame COUNT steps up from the current frame, after the
2441 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2442 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2445 The value of the expression must always be the correct address when COUNT is
2446 zero, but may be `NULL_RTX' if there is not way to determine the return
2447 address of other frames. */
2450 frv_return_addr_rtx (count, frame)
2451 int count ATTRIBUTE_UNUSED;
2454 cfun->machine->frame_needed = 1;
2455 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2458 /* Given a memory reference MEMREF, interpret the referenced memory as
2459 an array of MODE values, and return a reference to the element
2460 specified by INDEX. Assume that any pre-modification implicit in
2461 MEMREF has already happened.
2463 MEMREF must be a legitimate operand for modes larger than SImode.
2464 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2465 this function cannot handle. */
2467 frv_index_memory (memref, mode, index)
2469 enum machine_mode mode;
2472 rtx base = XEXP (memref, 0);
2473 if (GET_CODE (base) == PRE_MODIFY)
2474 base = XEXP (base, 0);
2475 return change_address (memref, mode,
2476 plus_constant (base, index * GET_MODE_SIZE (mode)));
2480 /* Print a memory address as an operand to reference that memory location. */
2482 frv_print_operand_address (stream, x)
2486 if (GET_CODE (x) == MEM)
2489 switch (GET_CODE (x))
2492 fputs (reg_names [ REGNO (x)], stream);
2496 fprintf (stream, "%ld", (long) INTVAL (x));
2500 assemble_name (stream, XSTR (x, 0));
2505 output_addr_const (stream, x);
2512 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2517 frv_print_operand_memory_reference_reg (stream, x)
2521 int regno = true_regnum (x);
2523 fputs (reg_names[regno], stream);
2525 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2528 /* Print a memory reference suitable for the ld/st instructions. */
2531 frv_print_operand_memory_reference (stream, x, addr_offset)
2539 switch (GET_CODE (x))
2546 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2548 x1 = XEXP (XEXP (x, 1), 1);
2558 if (GET_CODE (x0) == CONST_INT)
2566 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2575 else if (GET_CODE (x1) != CONST_INT)
2576 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2579 fputs ("@(", stream);
2581 fputs (reg_names[GPR_R0], stream);
2582 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2583 frv_print_operand_memory_reference_reg (stream, x0);
2585 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2587 fputs (",", stream);
2589 fputs (reg_names [GPR_R0], stream);
2593 switch (GET_CODE (x1))
2597 frv_print_operand_memory_reference_reg (stream, x1);
2601 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2605 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2606 && symbol_ref_small_data_p (x1))
2608 fputs ("#gprel12(", stream);
2609 assemble_name (stream, XSTR (x1, 0));
2610 fputs (")", stream);
2613 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2617 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2618 && const_small_data_p (x1))
2620 fputs ("#gprel12(", stream);
2621 assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0));
2622 fprintf (stream, "+%d)", INTVAL (XEXP (XEXP (x1, 0), 1)));
2625 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2629 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2633 fputs (")", stream);
2637 /* Return 2 for likely branches and 0 for non-likely branches */
2639 #define FRV_JUMP_LIKELY 2
2640 #define FRV_JUMP_NOT_LIKELY 0
2643 frv_print_operand_jump_hint (insn)
2649 HOST_WIDE_INT prob = -1;
2650 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2652 if (GET_CODE (insn) != JUMP_INSN)
2655 /* Assume any non-conditional jump is likely. */
2656 if (! any_condjump_p (insn))
2657 ret = FRV_JUMP_LIKELY;
2661 labelref = condjump_label (insn);
2664 rtx label = XEXP (labelref, 0);
2665 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2670 note = find_reg_note (insn, REG_BR_PROB, 0);
2672 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2676 prob = INTVAL (XEXP (note, 0));
2677 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2679 : FRV_JUMP_NOT_LIKELY);
2691 case UNKNOWN: direction = "unknown jump direction"; break;
2692 case BACKWARD: direction = "jump backward"; break;
2693 case FORWARD: direction = "jump forward"; break;
2697 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2698 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2699 (long)INSN_UID (insn), direction, (long)prob,
2700 (long)REG_BR_PROB_BASE, ret);
2708 /* Print an operand to an assembler instruction.
2710 `%' followed by a letter and a digit says to output an operand in an
2711 alternate fashion. Four letters have standard, built-in meanings described
2712 below. The machine description macro `PRINT_OPERAND' can define additional
2713 letters with nonstandard meanings.
2715 `%cDIGIT' can be used to substitute an operand that is a constant value
2716 without the syntax that normally indicates an immediate operand.
2718 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2721 `%aDIGIT' can be used to substitute an operand as if it were a memory
2722 reference, with the actual operand treated as the address. This may be
2723 useful when outputting a "load address" instruction, because often the
2724 assembler syntax for such an instruction requires you to write the operand
2725 as if it were a memory reference.
2727 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2729 `%=' outputs a number which is unique to each instruction in the entire
2730 compilation. This is useful for making local labels to be referred to more
2731 than once in a single template that generates multiple assembler
2734 `%' followed by a punctuation character specifies a substitution that does
2735 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2736 assembler code. Other nonstandard cases can be defined in the
2737 `PRINT_OPERAND' macro. You must also define which punctuation characters
2738 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2741 frv_print_operand (file, x, code)
2746 HOST_WIDE_INT value;
2749 if (code != 0 && !isalpha (code))
2752 else if (GET_CODE (x) == CONST_INT)
2755 else if (GET_CODE (x) == CONST_DOUBLE)
2757 if (GET_MODE (x) == SFmode)
2762 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2763 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2767 else if (GET_MODE (x) == VOIDmode)
2768 value = CONST_DOUBLE_LOW (x);
2771 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2782 fputs (reg_names[GPR_R0], file);
2786 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2789 case SDATA_FLAG_CHAR:
2790 /* Output small data area base register (gr16). */
2791 fputs (reg_names[SDA_BASE_REG], file);
2795 /* Output pic register (gr17). */
2796 fputs (reg_names[PIC_REGNO], file);
2800 /* Output the temporary integer CCR register */
2801 fputs (reg_names[ICR_TEMP], file);
2805 /* Output the temporary integer CC register */
2806 fputs (reg_names[ICC_TEMP], file);
2809 /* case 'a': print an address */
2812 /* Print appropriate test for integer branch false operation */
2813 switch (GET_CODE (x))
2816 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2818 case EQ: fputs ("ne", file); break;
2819 case NE: fputs ("eq", file); break;
2820 case LT: fputs ("ge", file); break;
2821 case LE: fputs ("gt", file); break;
2822 case GT: fputs ("le", file); break;
2823 case GE: fputs ("lt", file); break;
2824 case LTU: fputs ("nc", file); break;
2825 case LEU: fputs ("hi", file); break;
2826 case GTU: fputs ("ls", file); break;
2827 case GEU: fputs ("c", file); break;
2831 /* case 'c': print a constant without the constant prefix. If
2832 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2835 /* Print appropriate test for integer branch true operation */
2836 switch (GET_CODE (x))
2839 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2841 case EQ: fputs ("eq", file); break;
2842 case NE: fputs ("ne", file); break;
2843 case LT: fputs ("lt", file); break;
2844 case LE: fputs ("le", file); break;
2845 case GT: fputs ("gt", file); break;
2846 case GE: fputs ("ge", file); break;
2847 case LTU: fputs ("c", file); break;
2848 case LEU: fputs ("ls", file); break;
2849 case GTU: fputs ("hi", file); break;
2850 case GEU: fputs ("nc", file); break;
2855 /* Print 1 for a NE and 0 for an EQ to give the final argument
2856 for a conditional instruction. */
2857 if (GET_CODE (x) == NE)
2860 else if (GET_CODE (x) == EQ)
2864 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2868 /* Print appropriate test for floating point branch false operation */
2869 switch (GET_CODE (x))
2872 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2874 case EQ: fputs ("ne", file); break;
2875 case NE: fputs ("eq", file); break;
2876 case LT: fputs ("uge", file); break;
2877 case LE: fputs ("ug", file); break;
2878 case GT: fputs ("ule", file); break;
2879 case GE: fputs ("ul", file); break;
2884 /* Print appropriate test for floating point branch true operation */
2885 switch (GET_CODE (x))
2888 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2890 case EQ: fputs ("eq", file); break;
2891 case NE: fputs ("ne", file); break;
2892 case LT: fputs ("lt", file); break;
2893 case LE: fputs ("le", file); break;
2894 case GT: fputs ("gt", file); break;
2895 case GE: fputs ("ge", file); break;
2900 /* Print 'i' if the operand is a constant, or is a memory reference that
2902 if (GET_CODE (x) == MEM)
2903 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2904 ? XEXP (XEXP (x, 0), 1)
2907 switch (GET_CODE (x))
2921 /* For jump instructions, print 'i' if the operand is a constant or
2922 is an expression that adds a constant */
2923 if (GET_CODE (x) == CONST_INT)
2928 if (GET_CODE (x) == CONST_INT
2929 || (GET_CODE (x) == PLUS
2930 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2931 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2937 /* Print the lower register of a double word register pair */
2938 if (GET_CODE (x) == REG)
2939 fputs (reg_names[ REGNO (x)+1 ], file);
2941 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2944 /* case 'l': print a LABEL_REF */
2948 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2949 for the second word of double memory operations. */
2950 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2951 switch (GET_CODE (x))
2954 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2957 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2965 frv_print_operand_memory_reference (file, x, offset);
2971 /* Print the opcode of a command. */
2972 switch (GET_CODE (x))
2975 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2977 case PLUS: fputs ("add", file); break;
2978 case MINUS: fputs ("sub", file); break;
2979 case AND: fputs ("and", file); break;
2980 case IOR: fputs ("or", file); break;
2981 case XOR: fputs ("xor", file); break;
2982 case ASHIFT: fputs ("sll", file); break;
2983 case ASHIFTRT: fputs ("sra", file); break;
2984 case LSHIFTRT: fputs ("srl", file); break;
2988 /* case 'n': negate and print a constant int */
2991 /* Print PIC label using operand as the number. */
2992 if (GET_CODE (x) != CONST_INT)
2993 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2995 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2999 /* Print 'u' if the operand is a update load/store */
3000 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3005 /* If value is 0, print gr0, otherwise it must be a register */
3006 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3007 fputs (reg_names[GPR_R0], file);
3009 else if (GET_CODE (x) == REG)
3010 fputs (reg_names [REGNO (x)], file);
3013 fatal_insn ("Bad insn in frv_print_operand, z case", x);
3017 /* Print constant in hex */
3018 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3020 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3027 if (GET_CODE (x) == REG)
3028 fputs (reg_names [REGNO (x)], file);
3030 else if (GET_CODE (x) == CONST_INT
3031 || GET_CODE (x) == CONST_DOUBLE)
3032 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3034 else if (GET_CODE (x) == MEM)
3035 frv_print_operand_address (file, XEXP (x, 0));
3037 else if (CONSTANT_ADDRESS_P (x))
3038 frv_print_operand_address (file, x);
3041 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3046 fatal_insn ("frv_print_operand: unknown code", x);
3054 /* A C statement (sans semicolon) for initializing the variable CUM for the
3055 state at the beginning of the argument list. The variable has type
3056 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3057 of the function which will receive the args, or 0 if the args are to a
3058 compiler support library function. The value of INDIRECT is nonzero when
3059 processing an indirect call, for example a call through a function pointer.
3060 The value of INDIRECT is zero for a call to an explicitly named function, a
3061 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3062 arguments for the function being compiled.
3064 When processing a call to a compiler support library function, LIBNAME
3065 identifies which one. It is a `symbol_ref' rtx which contains the name of
3066 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3067 being processed. Thus, each time this macro is called, either LIBNAME or
3068 FNTYPE is nonzero, but never both of them at once. */
3071 frv_init_cumulative_args (cum, fntype, libname, indirect, incoming)
3072 CUMULATIVE_ARGS *cum;
3078 *cum = FIRST_ARG_REGNUM;
3080 if (TARGET_DEBUG_ARG)
3082 fprintf (stderr, "\ninit_cumulative_args:");
3084 fputs (" indirect", stderr);
3087 fputs (" incoming", stderr);
3091 tree ret_type = TREE_TYPE (fntype);
3092 fprintf (stderr, " return=%s,",
3093 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3096 if (libname && GET_CODE (libname) == SYMBOL_REF)
3097 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3099 if (cfun->returns_struct)
3100 fprintf (stderr, " return-struct");
3102 putc ('\n', stderr);
3107 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3108 argument with the specified mode and type. If it is not defined,
3109 `PARM_BOUNDARY' is used for all arguments. */
3112 frv_function_arg_boundary (mode, type)
3113 enum machine_mode mode ATTRIBUTE_UNUSED;
3114 tree type ATTRIBUTE_UNUSED;
3116 return BITS_PER_WORD;
3120 /* A C expression that controls whether a function argument is passed in a
3121 register, and which register.
3123 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3124 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3125 arguments so far passed in registers; MODE, the machine mode of the argument;
3126 TYPE, the data type of the argument as a tree node or 0 if that is not known
3127 (which happens for C support library functions); and NAMED, which is 1 for an
3128 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3129 called function's prototype.
3131 The value of the expression should either be a `reg' RTX for the hard
3132 register in which to pass the argument, or zero to pass the argument on the
3135 For machines like the VAX and 68000, where normally all arguments are
3136 pushed, zero suffices as a definition.
3138 The usual way to make the ANSI library `stdarg.h' work on a machine where
3139 some arguments are usually passed in registers, is to cause nameless
3140 arguments to be passed on the stack instead. This is done by making
3141 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3143 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3144 this macro to determine if this argument is of a type that must be passed in
3145 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3146 returns nonzero for such an argument, the compiler will abort. If
3147 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3148 stack and then loaded into a register. */
3151 frv_function_arg (cum, mode, type, named, incoming)
3152 CUMULATIVE_ARGS *cum;
3153 enum machine_mode mode;
3154 tree type ATTRIBUTE_UNUSED;
3156 int incoming ATTRIBUTE_UNUSED;
3158 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3163 /* Return a marker for use in the call instruction. */
3164 if (xmode == VOIDmode)
3170 else if (arg_num <= LAST_ARG_REGNUM)
3172 ret = gen_rtx (REG, xmode, arg_num);
3173 debstr = reg_names[arg_num];
3182 if (TARGET_DEBUG_ARG)
3184 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3185 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3191 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3192 advance past an argument in the argument list. The values MODE, TYPE and
3193 NAMED describe that argument. Once this is done, the variable CUM is
3194 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3196 This macro need not do anything if the argument in question was passed on
3197 the stack. The compiler knows how to track the amount of stack space used
3198 for arguments without any special help. */
3201 frv_function_arg_advance (cum, mode, type, named)
3202 CUMULATIVE_ARGS *cum;
3203 enum machine_mode mode;
3204 tree type ATTRIBUTE_UNUSED;
3207 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3208 int bytes = GET_MODE_SIZE (xmode);
3209 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3212 *cum = arg_num + words;
3214 if (TARGET_DEBUG_ARG)
3216 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3217 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3221 /* A C expression for the number of words, at the beginning of an argument,
3222 must be put in registers. The value must be zero for arguments that are
3223 passed entirely in registers or that are entirely pushed on the stack.
3225 On some machines, certain arguments must be passed partially in registers
3226 and partially in memory. On these machines, typically the first N words of
3227 arguments are passed in registers, and the rest on the stack. If a
3228 multi-word argument (a `double' or a structure) crosses that boundary, its
3229 first few words must be passed in registers and the rest must be pushed.
3230 This macro tells the compiler when this occurs, and how many of the words
3231 should go in registers.
3233 `FUNCTION_ARG' for these arguments should return the first register to be
3234 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3235 the called function. */
3238 frv_function_arg_partial_nregs (cum, mode, type, named)
3239 CUMULATIVE_ARGS *cum;
3240 enum machine_mode mode;
3241 tree type ATTRIBUTE_UNUSED;
3242 int named ATTRIBUTE_UNUSED;
3244 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3245 int bytes = GET_MODE_SIZE (xmode);
3246 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3250 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3251 ? LAST_ARG_REGNUM - arg_num + 1
3254 if (TARGET_DEBUG_ARG && ret)
3255 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3263 /* A C expression that indicates when an argument must be passed by reference.
3264 If nonzero for an argument, a copy of that argument is made in memory and a
3265 pointer to the argument is passed instead of the argument itself. The
3266 pointer is passed in whatever way is appropriate for passing a pointer to
3269 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3270 definition of this macro might be
3271 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3272 MUST_PASS_IN_STACK (MODE, TYPE) */
3275 frv_function_arg_pass_by_reference (cum, mode, type, named)
3276 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3277 enum machine_mode mode;
3279 int named ATTRIBUTE_UNUSED;
3281 return MUST_PASS_IN_STACK (mode, type);
3284 /* If defined, a C expression that indicates when it is the called function's
3285 responsibility to make a copy of arguments passed by invisible reference.
3286 Normally, the caller makes a copy and passes the address of the copy to the
3287 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3288 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3289 the "live" value. The called function must not modify this value. If it
3290 can be determined that the value won't be modified, it need not make a copy;
3291 otherwise a copy must be made. */
3294 frv_function_arg_callee_copies (cum, mode, type, named)
3295 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3296 enum machine_mode mode ATTRIBUTE_UNUSED;
3297 tree type ATTRIBUTE_UNUSED;
3298 int named ATTRIBUTE_UNUSED;
3303 /* If defined, a C expression that indicates when it is more desirable to keep
3304 an argument passed by invisible reference as a reference, rather than
3305 copying it to a pseudo register. */
3308 frv_function_arg_keep_as_reference (cum, mode, type, named)
3309 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3310 enum machine_mode mode ATTRIBUTE_UNUSED;
3311 tree type ATTRIBUTE_UNUSED;
3312 int named ATTRIBUTE_UNUSED;
3318 /* Return true if a register is ok to use as a base or index register. */
3320 static FRV_INLINE int
3321 frv_regno_ok_for_base_p (regno, strict_p)
3329 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3331 if (regno == ARG_POINTER_REGNUM)
3334 return (regno >= FIRST_PSEUDO_REGISTER);
3338 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3339 RTX) is a legitimate memory address on the target machine for a memory
3340 operand of mode MODE.
3342 It usually pays to define several simpler macros to serve as subroutines for
3343 this one. Otherwise it may be too complicated to understand.
3345 This macro must exist in two variants: a strict variant and a non-strict
3346 one. The strict variant is used in the reload pass. It must be defined so
3347 that any pseudo-register that has not been allocated a hard register is
3348 considered a memory reference. In contexts where some kind of register is
3349 required, a pseudo-register with no hard register must be rejected.
3351 The non-strict variant is used in other passes. It must be defined to
3352 accept all pseudo-registers in every context where some kind of register is
3355 Compiler source files that want to use the strict variant of this macro
3356 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3357 conditional to define the strict variant in that case and the non-strict
3360 Subroutines to check for acceptable registers for various purposes (one for
3361 base registers, one for index registers, and so on) are typically among the
3362 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3363 subroutine macros need have two variants; the higher levels of macros may be
3364 the same whether strict or not.
3366 Normally, constant addresses which are the sum of a `symbol_ref' and an
3367 integer are stored inside a `const' RTX to mark them as constant.
3368 Therefore, there is no need to recognize such sums specifically as
3369 legitimate addresses. Normally you would simply recognize any `const' as
3372 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3373 are not marked with `const'. It assumes that a naked `plus' indicates
3374 indexing. If so, then you *must* reject such naked constant sums as
3375 illegitimate addresses, so that none of them will be given to
3376 `PRINT_OPERAND_ADDRESS'.
3378 On some machines, whether a symbolic address is legitimate depends on the
3379 section that the address refers to. On these machines, define the macro
3380 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3381 then check for it here. When you see a `const', you will have to look
3382 inside it to find the `symbol_ref' in order to determine the section.
3384 The best way to modify the name string is by adding text to the beginning,
3385 with suitable punctuation to prevent any ambiguity. Allocate the new name
3386 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3387 remove and decode the added text and output the name accordingly, and define
3388 `(* targetm.strip_name_encoding)' to access the original name string.
3390 You can check the information stored here into the `symbol_ref' in the
3391 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3392 `PRINT_OPERAND_ADDRESS'. */
3395 frv_legitimate_address_p (mode, x, strict_p, condexec_p)
3396 enum machine_mode mode;
3403 HOST_WIDE_INT value;
3406 switch (GET_CODE (x))
3413 if (GET_CODE (x) != REG)
3419 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3425 if (GET_CODE (x0) != REG
3426 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3427 || GET_CODE (x1) != PLUS
3428 || ! rtx_equal_p (x0, XEXP (x1, 0))
3429 || GET_CODE (XEXP (x1, 1)) != REG
3430 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3437 /* 12 bit immediate */
3442 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3444 /* If we can't use load/store double operations, make sure we can
3445 address the second word. */
3446 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3447 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3456 if (GET_CODE (x0) == SUBREG)
3457 x0 = SUBREG_REG (x0);
3459 if (GET_CODE (x0) != REG)
3462 regno0 = REGNO (x0);
3463 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3466 switch (GET_CODE (x1))
3472 x1 = SUBREG_REG (x1);
3473 if (GET_CODE (x1) != REG)
3479 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3480 on having move double instructions */
3481 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3484 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3488 /* 12 bit immediate */
3493 value = INTVAL (x1);
3494 ret = IN_RANGE_P (value, -2048, 2047);
3496 /* If we can't use load/store double operations, make sure we can
3497 address the second word. */
3498 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3499 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3505 && regno0 == SDA_BASE_REG
3506 && symbol_ref_small_data_p (x1))
3511 if (!condexec_p && regno0 == SDA_BASE_REG && const_small_data_p (x1))
3519 if (TARGET_DEBUG_ADDR)
3521 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3522 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3523 (condexec_p) ? ", inside conditional code" : "");
3531 /* A C compound statement that attempts to replace X with a valid memory
3532 address for an operand of mode MODE. WIN will be a C statement label
3533 elsewhere in the code; the macro definition may use
3535 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3537 to avoid further processing if the address has become legitimate.
3539 X will always be the result of a call to `break_out_memory_refs', and OLDX
3540 will be the operand that was given to that function to produce X.
3542 The code generated by this macro should not alter the substructure of X. If
3543 it transforms X into a more legitimate form, it should assign X (which will
3544 always be a C variable) a new value.
3546 It is not necessary for this macro to come up with a legitimate address.
3547 The compiler has standard ways of doing so in all cases. In fact, it is
3548 safe for this macro to do nothing. But often a machine-dependent strategy
3549 can generate better code. */
3552 frv_legitimize_address (x, oldx, mode)
3554 rtx oldx ATTRIBUTE_UNUSED;
3555 enum machine_mode mode ATTRIBUTE_UNUSED;
3559 /* Don't try to legitimize addresses if we are not optimizing, since the
3560 address we generate is not a general operand, and will horribly mess
3561 things up when force_reg is called to try and put it in a register because
3562 we aren't optimizing. */
3564 && ((GET_CODE (x) == SYMBOL_REF && symbol_ref_small_data_p (x))
3565 || (GET_CODE (x) == CONST && const_small_data_p (x))))
3567 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x);
3569 cfun->uses_pic_offset_table = TRUE;
3572 if (TARGET_DEBUG_ADDR && ret != NULL_RTX)
3574 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3575 GET_MODE_NAME (mode));
3582 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3583 the operand is used by a predicated instruction. */
3586 frv_legitimate_memory_operand (op, mode, condexec_p)
3588 enum machine_mode mode;
3591 return ((GET_MODE (op) == mode || mode == VOIDmode)
3592 && GET_CODE (op) == MEM
3593 && frv_legitimate_address_p (mode, XEXP (op, 0),
3594 reload_completed, condexec_p));
3598 /* Return 1 is OP is a memory operand, or will be turned into one by
3601 int frv_load_operand (op, mode)
3603 enum machine_mode mode;
3605 if (GET_MODE (op) != mode && mode != VOIDmode)
3608 if (reload_in_progress)
3611 if (GET_CODE (tmp) == SUBREG)
3612 tmp = SUBREG_REG (tmp);
3613 if (GET_CODE (tmp) == REG
3614 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3615 op = reg_equiv_memory_loc[REGNO (tmp)];
3618 return op && memory_operand (op, mode);
3622 /* Return 1 if operand is a GPR register or a FPR register. */
3624 int gpr_or_fpr_operand (op, mode)
3626 enum machine_mode mode;
3630 if (GET_MODE (op) != mode && mode != VOIDmode)
3633 if (GET_CODE (op) == SUBREG)
3635 if (GET_CODE (SUBREG_REG (op)) != REG)
3636 return register_operand (op, mode);
3638 op = SUBREG_REG (op);
3641 if (GET_CODE (op) != REG)
3645 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3651 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3653 int gpr_or_int12_operand (op, mode)
3655 enum machine_mode mode;
3657 if (GET_CODE (op) == CONST_INT)
3658 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3660 if (GET_MODE (op) != mode && mode != VOIDmode)
3663 if (GET_CODE (op) == SUBREG)
3665 if (GET_CODE (SUBREG_REG (op)) != REG)
3666 return register_operand (op, mode);
3668 op = SUBREG_REG (op);
3671 if (GET_CODE (op) != REG)
3674 return GPR_OR_PSEUDO_P (REGNO (op));
3677 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3678 signed immediate. */
3680 int gpr_fpr_or_int12_operand (op, mode)
3682 enum machine_mode mode;
3686 if (GET_CODE (op) == CONST_INT)
3687 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3689 if (GET_MODE (op) != mode && mode != VOIDmode)
3692 if (GET_CODE (op) == SUBREG)
3694 if (GET_CODE (SUBREG_REG (op)) != REG)
3695 return register_operand (op, mode);
3697 op = SUBREG_REG (op);
3700 if (GET_CODE (op) != REG)
3704 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3710 /* Return 1 if operand is a register or 6 bit signed immediate. */
3712 int fpr_or_int6_operand (op, mode)
3714 enum machine_mode mode;
3716 if (GET_CODE (op) == CONST_INT)
3717 return IN_RANGE_P (INTVAL (op), -32, 31);
3719 if (GET_MODE (op) != mode && mode != VOIDmode)
3722 if (GET_CODE (op) == SUBREG)
3724 if (GET_CODE (SUBREG_REG (op)) != REG)
3725 return register_operand (op, mode);
3727 op = SUBREG_REG (op);
3730 if (GET_CODE (op) != REG)
3733 return FPR_OR_PSEUDO_P (REGNO (op));
3736 /* Return 1 if operand is a register or 10 bit signed immediate. */
3738 int gpr_or_int10_operand (op, mode)
3740 enum machine_mode mode;
3742 if (GET_CODE (op) == CONST_INT)
3743 return IN_RANGE_P (INTVAL (op), -512, 511);
3745 if (GET_MODE (op) != mode && mode != VOIDmode)
3748 if (GET_CODE (op) == SUBREG)
3750 if (GET_CODE (SUBREG_REG (op)) != REG)
3751 return register_operand (op, mode);
3753 op = SUBREG_REG (op);
3756 if (GET_CODE (op) != REG)
3759 return GPR_OR_PSEUDO_P (REGNO (op));
3762 /* Return 1 if operand is a register or an integer immediate. */
3764 int gpr_or_int_operand (op, mode)
3766 enum machine_mode mode;
3768 if (GET_CODE (op) == CONST_INT)
3771 if (GET_MODE (op) != mode && mode != VOIDmode)
3774 if (GET_CODE (op) == SUBREG)
3776 if (GET_CODE (SUBREG_REG (op)) != REG)
3777 return register_operand (op, mode);
3779 op = SUBREG_REG (op);
3782 if (GET_CODE (op) != REG)
3785 return GPR_OR_PSEUDO_P (REGNO (op));
3788 /* Return 1 if operand is a 12 bit signed immediate. */
3790 int int12_operand (op, mode)
3792 enum machine_mode mode ATTRIBUTE_UNUSED;
3794 if (GET_CODE (op) != CONST_INT)
3797 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3800 /* Return 1 if operand is a 6 bit signed immediate. */
3802 int int6_operand (op, mode)
3804 enum machine_mode mode ATTRIBUTE_UNUSED;
3806 if (GET_CODE (op) != CONST_INT)
3809 return IN_RANGE_P (INTVAL (op), -32, 31);
3812 /* Return 1 if operand is a 5 bit signed immediate. */
3814 int int5_operand (op, mode)
3816 enum machine_mode mode ATTRIBUTE_UNUSED;
3818 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3821 /* Return 1 if operand is a 5 bit unsigned immediate. */
3823 int uint5_operand (op, mode)
3825 enum machine_mode mode ATTRIBUTE_UNUSED;
3827 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3830 /* Return 1 if operand is a 4 bit unsigned immediate. */
3832 int uint4_operand (op, mode)
3834 enum machine_mode mode ATTRIBUTE_UNUSED;
3836 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3839 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3841 int uint1_operand (op, mode)
3843 enum machine_mode mode ATTRIBUTE_UNUSED;
3845 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3848 /* Return 1 if operand is an integer constant that takes 2 instructions
3849 to load up and can be split into sethi/setlo instructions.. */
3851 int int_2word_operand (op, mode)
3853 enum machine_mode mode ATTRIBUTE_UNUSED;
3855 HOST_WIDE_INT value;
3859 switch (GET_CODE (op))
3865 return (flag_pic == 0);
3868 /* small data references are already 1 word */
3869 return (flag_pic == 0) && (! const_small_data_p (op));
3872 /* small data references are already 1 word */
3873 return (flag_pic == 0) && (! symbol_ref_small_data_p (op));
3876 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3879 if (GET_MODE (op) == SFmode)
3881 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3882 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3884 return ! IN_RANGE_P (value, -32768, 32767);
3886 else if (GET_MODE (op) == VOIDmode)
3888 value = CONST_DOUBLE_LOW (op);
3889 return ! IN_RANGE_P (value, -32768, 32767);
3897 /* Return 1 if operand is the pic address register. */
3899 pic_register_operand (op, mode)
3901 enum machine_mode mode ATTRIBUTE_UNUSED;
3906 if (GET_CODE (op) != REG)
3909 if (REGNO (op) != PIC_REGNO)
3915 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3916 that takes 3 seperate instructions to form. */
3918 int pic_symbolic_operand (op, mode)
3920 enum machine_mode mode ATTRIBUTE_UNUSED;
3925 switch (GET_CODE (op))
3934 /* small data references are already 1 word */
3935 return ! symbol_ref_small_data_p (op);
3938 /* small data references are already 1 word */
3939 return ! const_small_data_p (op);
3945 /* Return 1 if operand is the small data register. */
3947 small_data_register_operand (op, mode)
3949 enum machine_mode mode ATTRIBUTE_UNUSED;
3951 if (GET_CODE (op) != REG)
3954 if (REGNO (op) != SDA_BASE_REG)
3960 /* Return 1 if operand is a symbolic reference to a small data area static or
3963 int small_data_symbolic_operand (op, mode)
3965 enum machine_mode mode ATTRIBUTE_UNUSED;
3967 switch (GET_CODE (op))
3973 return const_small_data_p (op);
3976 return symbol_ref_small_data_p (op);
3982 /* Return 1 if operand is a 16 bit unsigned immediate */
3984 int uint16_operand (op, mode)
3986 enum machine_mode mode ATTRIBUTE_UNUSED;
3988 if (GET_CODE (op) != CONST_INT)
3991 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3994 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
3996 int upper_int16_operand (op, mode)
3998 enum machine_mode mode ATTRIBUTE_UNUSED;
4000 if (GET_CODE (op) != CONST_INT)
4003 return ((INTVAL (op) & 0xffff) == 0);
4006 /* Return true if operand is a GPR register. */
4009 integer_register_operand (op, mode)
4011 enum machine_mode mode;
4013 if (GET_MODE (op) != mode && mode != VOIDmode)
4016 if (GET_CODE (op) == SUBREG)
4018 if (GET_CODE (SUBREG_REG (op)) != REG)
4019 return register_operand (op, mode);
4021 op = SUBREG_REG (op);
4024 if (GET_CODE (op) != REG)
4027 return GPR_OR_PSEUDO_P (REGNO (op));
4030 /* Return true if operand is a GPR register. Do not allow SUBREG's
4031 here, in order to prevent a combine bug. */
4034 gpr_no_subreg_operand (op, mode)
4036 enum machine_mode mode;
4038 if (GET_MODE (op) != mode && mode != VOIDmode)
4041 if (GET_CODE (op) != REG)
4044 return GPR_OR_PSEUDO_P (REGNO (op));
4047 /* Return true if operand is a FPR register. */
4050 fpr_operand (op, mode)
4052 enum machine_mode mode;
4054 if (GET_MODE (op) != mode && mode != VOIDmode)
4057 if (GET_CODE (op) == SUBREG)
4059 if (GET_CODE (SUBREG_REG (op)) != REG)
4060 return register_operand (op, mode);
4062 op = SUBREG_REG (op);
4065 if (GET_CODE (op) != REG)
4068 return FPR_OR_PSEUDO_P (REGNO (op));
4071 /* Return true if operand is an even GPR or FPR register. */
4074 even_reg_operand (op, mode)
4076 enum machine_mode mode;
4080 if (GET_MODE (op) != mode && mode != VOIDmode)
4083 if (GET_CODE (op) == SUBREG)
4085 if (GET_CODE (SUBREG_REG (op)) != REG)
4086 return register_operand (op, mode);
4088 op = SUBREG_REG (op);
4091 if (GET_CODE (op) != REG)
4095 if (regno >= FIRST_PSEUDO_REGISTER)
4099 return (((regno - GPR_FIRST) & 1) == 0);
4102 return (((regno - FPR_FIRST) & 1) == 0);
4107 /* Return true if operand is an odd GPR register. */
4110 odd_reg_operand (op, mode)
4112 enum machine_mode mode;
4116 if (GET_MODE (op) != mode && mode != VOIDmode)
4119 if (GET_CODE (op) == SUBREG)
4121 if (GET_CODE (SUBREG_REG (op)) != REG)
4122 return register_operand (op, mode);
4124 op = SUBREG_REG (op);
4127 if (GET_CODE (op) != REG)
4131 /* assume that reload will give us an even register */
4132 if (regno >= FIRST_PSEUDO_REGISTER)
4136 return (((regno - GPR_FIRST) & 1) != 0);
4139 return (((regno - FPR_FIRST) & 1) != 0);
4144 /* Return true if operand is an even GPR register. */
4147 even_gpr_operand (op, mode)
4149 enum machine_mode mode;
4153 if (GET_MODE (op) != mode && mode != VOIDmode)
4156 if (GET_CODE (op) == SUBREG)
4158 if (GET_CODE (SUBREG_REG (op)) != REG)
4159 return register_operand (op, mode);
4161 op = SUBREG_REG (op);
4164 if (GET_CODE (op) != REG)
4168 if (regno >= FIRST_PSEUDO_REGISTER)
4171 if (! GPR_P (regno))
4174 return (((regno - GPR_FIRST) & 1) == 0);
4177 /* Return true if operand is an odd GPR register. */
4180 odd_gpr_operand (op, mode)
4182 enum machine_mode mode;
4186 if (GET_MODE (op) != mode && mode != VOIDmode)
4189 if (GET_CODE (op) == SUBREG)
4191 if (GET_CODE (SUBREG_REG (op)) != REG)
4192 return register_operand (op, mode);
4194 op = SUBREG_REG (op);
4197 if (GET_CODE (op) != REG)
4201 /* assume that reload will give us an even register */
4202 if (regno >= FIRST_PSEUDO_REGISTER)
4205 if (! GPR_P (regno))
4208 return (((regno - GPR_FIRST) & 1) != 0);
4211 /* Return true if operand is a quad aligned FPR register. */
4214 quad_fpr_operand (op, mode)
4216 enum machine_mode mode;
4220 if (GET_MODE (op) != mode && mode != VOIDmode)
4223 if (GET_CODE (op) == SUBREG)
4225 if (GET_CODE (SUBREG_REG (op)) != REG)
4226 return register_operand (op, mode);
4228 op = SUBREG_REG (op);
4231 if (GET_CODE (op) != REG)
4235 if (regno >= FIRST_PSEUDO_REGISTER)
4238 if (! FPR_P (regno))
4241 return (((regno - FPR_FIRST) & 3) == 0);
4244 /* Return true if operand is an even FPR register. */
4247 even_fpr_operand (op, mode)
4249 enum machine_mode mode;
4253 if (GET_MODE (op) != mode && mode != VOIDmode)
4256 if (GET_CODE (op) == SUBREG)
4258 if (GET_CODE (SUBREG_REG (op)) != REG)
4259 return register_operand (op, mode);
4261 op = SUBREG_REG (op);
4264 if (GET_CODE (op) != REG)
4268 if (regno >= FIRST_PSEUDO_REGISTER)
4271 if (! FPR_P (regno))
4274 return (((regno - FPR_FIRST) & 1) == 0);
4277 /* Return true if operand is an odd FPR register. */
4280 odd_fpr_operand (op, mode)
4282 enum machine_mode mode;
4286 if (GET_MODE (op) != mode && mode != VOIDmode)
4289 if (GET_CODE (op) == SUBREG)
4291 if (GET_CODE (SUBREG_REG (op)) != REG)
4292 return register_operand (op, mode);
4294 op = SUBREG_REG (op);
4297 if (GET_CODE (op) != REG)
4301 /* assume that reload will give us an even register */
4302 if (regno >= FIRST_PSEUDO_REGISTER)
4305 if (! FPR_P (regno))
4308 return (((regno - FPR_FIRST) & 1) != 0);
4311 /* Return true if operand is a 2 word memory address that can be loaded in one
4312 instruction to load or store. We assume the stack and frame pointers are
4313 suitably aligned, and variables in the small data area. FIXME -- at some we
4314 should recognize other globals and statics. We can't assume that any old
4315 pointer is aligned, given that arguments could be passed on an odd word on
4316 the stack and the address taken and passed through to another function. */
4319 dbl_memory_one_insn_operand (op, mode)
4321 enum machine_mode mode;
4329 if (GET_CODE (op) != MEM)
4332 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4335 addr = XEXP (op, 0);
4336 if (GET_CODE (addr) == REG)
4339 else if (GET_CODE (addr) == PLUS)
4341 rtx addr0 = XEXP (addr, 0);
4342 rtx addr1 = XEXP (addr, 1);
4344 if (GET_CODE (addr0) != REG)
4347 if (plus_small_data_p (addr0, addr1))
4350 if (GET_CODE (addr1) != CONST_INT)
4353 if ((INTVAL (addr1) & 7) != 0)
4362 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4368 /* Return true if operand is a 2 word memory address that needs to
4369 use two instructions to load or store. */
4372 dbl_memory_two_insn_operand (op, mode)
4374 enum machine_mode mode;
4376 if (GET_CODE (op) != MEM)
4379 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4385 return ! dbl_memory_one_insn_operand (op, mode);
4388 /* Return true if operand is something that can be an output for a move
4392 move_destination_operand (op, mode)
4394 enum machine_mode mode;
4399 switch (GET_CODE (op))
4405 if (GET_MODE (op) != mode && mode != VOIDmode)
4408 subreg = SUBREG_REG (op);
4409 code = GET_CODE (subreg);
4411 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4412 reload_completed, FALSE);
4414 return (code == REG);
4417 if (GET_MODE (op) != mode && mode != VOIDmode)
4423 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4426 return frv_legitimate_memory_operand (op, mode, FALSE);
4432 /* Return true if operand is something that can be an input for a move
4436 move_source_operand (op, mode)
4438 enum machine_mode mode;
4443 switch (GET_CODE (op))
4453 return immediate_operand (op, mode);
4456 if (GET_MODE (op) != mode && mode != VOIDmode)
4459 subreg = SUBREG_REG (op);
4460 code = GET_CODE (subreg);
4462 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4463 reload_completed, FALSE);
4465 return (code == REG);
4468 if (GET_MODE (op) != mode && mode != VOIDmode)
4474 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4477 return frv_legitimate_memory_operand (op, mode, FALSE);
4483 /* Return true if operand is something that can be an output for a conditional
4487 condexec_dest_operand (op, mode)
4489 enum machine_mode mode;
4494 switch (GET_CODE (op))
4500 if (GET_MODE (op) != mode && mode != VOIDmode)
4503 subreg = SUBREG_REG (op);
4504 code = GET_CODE (subreg);
4506 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4507 reload_completed, TRUE);
4509 return (code == REG);
4512 if (GET_MODE (op) != mode && mode != VOIDmode)
4518 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4521 return frv_legitimate_memory_operand (op, mode, TRUE);
4527 /* Return true if operand is something that can be an input for a conditional
4531 condexec_source_operand (op, mode)
4533 enum machine_mode mode;
4538 switch (GET_CODE (op))
4548 if (GET_MODE (op) != mode && mode != VOIDmode)
4551 subreg = SUBREG_REG (op);
4552 code = GET_CODE (subreg);
4554 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4555 reload_completed, TRUE);
4557 return (code == REG);
4560 if (GET_MODE (op) != mode && mode != VOIDmode)
4566 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4569 return frv_legitimate_memory_operand (op, mode, TRUE);
4575 /* Return true if operand is a register of any flavor or a 0 of the
4576 appropriate type. */
4579 reg_or_0_operand (op, mode)
4581 enum machine_mode mode;
4583 switch (GET_CODE (op))
4590 if (GET_MODE (op) != mode && mode != VOIDmode)
4593 return register_operand (op, mode);
4603 /* Return true if operand is the link register */
4606 lr_operand (op, mode)
4608 enum machine_mode mode;
4610 if (GET_CODE (op) != REG)
4613 if (GET_MODE (op) != mode && mode != VOIDmode)
4616 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4622 /* Return true if operand is a gpr register or a valid memory operation. */
4625 gpr_or_memory_operand (op, mode)
4627 enum machine_mode mode;
4629 return (integer_register_operand (op, mode)
4630 || frv_legitimate_memory_operand (op, mode, FALSE));
4633 /* Return true if operand is a fpr register or a valid memory operation. */
4636 fpr_or_memory_operand (op, mode)
4638 enum machine_mode mode;
4640 return (fpr_operand (op, mode)
4641 || frv_legitimate_memory_operand (op, mode, FALSE));
4644 /* Return true if operand is an icc register */
4647 icc_operand (op, mode)
4649 enum machine_mode mode;
4653 if (GET_MODE (op) != mode && mode != VOIDmode)
4656 if (GET_CODE (op) != REG)
4660 return ICC_OR_PSEUDO_P (regno);
4663 /* Return true if operand is an fcc register */
4666 fcc_operand (op, mode)
4668 enum machine_mode mode;
4672 if (GET_MODE (op) != mode && mode != VOIDmode)
4675 if (GET_CODE (op) != REG)
4679 return FCC_OR_PSEUDO_P (regno);
4682 /* Return true if operand is either an fcc or icc register */
4685 cc_operand (op, mode)
4687 enum machine_mode mode;
4691 if (GET_MODE (op) != mode && mode != VOIDmode)
4694 if (GET_CODE (op) != REG)
4698 if (CC_OR_PSEUDO_P (regno))
4704 /* Return true if operand is an integer CCR register */
4707 icr_operand (op, mode)
4709 enum machine_mode mode;
4713 if (GET_MODE (op) != mode && mode != VOIDmode)
4716 if (GET_CODE (op) != REG)
4720 return ICR_OR_PSEUDO_P (regno);
4723 /* Return true if operand is an fcc register */
4726 fcr_operand (op, mode)
4728 enum machine_mode mode;
4732 if (GET_MODE (op) != mode && mode != VOIDmode)
4735 if (GET_CODE (op) != REG)
4739 return FCR_OR_PSEUDO_P (regno);
4742 /* Return true if operand is either an fcc or icc register */
4745 cr_operand (op, mode)
4747 enum machine_mode mode;
4751 if (GET_MODE (op) != mode && mode != VOIDmode)
4754 if (GET_CODE (op) != REG)
4758 if (CR_OR_PSEUDO_P (regno))
4764 /* Return true if operand is a memory reference suitable for a call. */
4767 call_operand (op, mode)
4769 enum machine_mode mode;
4771 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4774 if (GET_CODE (op) == SYMBOL_REF)
4777 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4778 never occur anyway), but prevents reload from not handling the case
4779 properly of a call through a pointer on a function that calls
4780 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4781 return gpr_or_int12_operand (op, mode);
4784 /* Return true if operator is an kind of relational operator */
4787 relational_operator (op, mode)
4789 enum machine_mode mode;
4795 if (mode != VOIDmode && mode != GET_MODE (op))
4798 switch (GET_CODE (op))
4817 if (op1 != const0_rtx)
4821 if (GET_CODE (op0) != REG)
4824 regno = REGNO (op0);
4825 switch (GET_MODE (op0))
4832 return ICC_OR_PSEUDO_P (regno);
4835 return FCC_OR_PSEUDO_P (regno);
4838 return CR_OR_PSEUDO_P (regno);
4844 /* Return true if operator is a signed integer relational operator */
4847 signed_relational_operator (op, mode)
4849 enum machine_mode mode;
4855 if (mode != VOIDmode && mode != GET_MODE (op))
4858 switch (GET_CODE (op))
4873 if (op1 != const0_rtx)
4877 if (GET_CODE (op0) != REG)
4880 regno = REGNO (op0);
4881 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4884 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4890 /* Return true if operator is a signed integer relational operator */
4893 unsigned_relational_operator (op, mode)
4895 enum machine_mode mode;
4901 if (mode != VOIDmode && mode != GET_MODE (op))
4904 switch (GET_CODE (op))
4917 if (op1 != const0_rtx)
4921 if (GET_CODE (op0) != REG)
4924 regno = REGNO (op0);
4925 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4928 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4934 /* Return true if operator is a floating point relational operator */
4937 float_relational_operator (op, mode)
4939 enum machine_mode mode;
4945 if (mode != VOIDmode && mode != GET_MODE (op))
4948 switch (GET_CODE (op))
4967 if (op1 != const0_rtx)
4971 if (GET_CODE (op0) != REG)
4974 regno = REGNO (op0);
4975 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4978 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4984 /* Return true if operator is EQ/NE of a conditional execution register. */
4987 ccr_eqne_operator (op, mode)
4989 enum machine_mode mode;
4991 enum machine_mode op_mode = GET_MODE (op);
4996 if (mode != VOIDmode && op_mode != mode)
4999 switch (GET_CODE (op))
5010 if (op1 != const0_rtx)
5014 if (GET_CODE (op0) != REG)
5017 regno = REGNO (op0);
5018 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
5024 /* Return true if operator is a minimum or maximum operator (both signed and
5028 minmax_operator (op, mode)
5030 enum machine_mode mode;
5032 if (mode != VOIDmode && mode != GET_MODE (op))
5035 switch (GET_CODE (op))
5047 if (! integer_register_operand (XEXP (op, 0), mode))
5050 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5056 /* Return true if operator is an integer binary operator that can executed
5057 conditionally and takes 1 cycle. */
5060 condexec_si_binary_operator (op, mode)
5062 enum machine_mode mode;
5064 enum machine_mode op_mode = GET_MODE (op);
5066 if (mode != VOIDmode && op_mode != mode)
5069 switch (GET_CODE (op))
5086 /* Return true if operator is an integer binary operator that can be
5087 executed conditionally by a media instruction. */
5090 condexec_si_media_operator (op, mode)
5092 enum machine_mode mode;
5094 enum machine_mode op_mode = GET_MODE (op);
5096 if (mode != VOIDmode && op_mode != mode)
5099 switch (GET_CODE (op))
5111 /* Return true if operator is an integer division operator that can executed
5115 condexec_si_divide_operator (op, mode)
5117 enum machine_mode mode;
5119 enum machine_mode op_mode = GET_MODE (op);
5121 if (mode != VOIDmode && op_mode != mode)
5124 switch (GET_CODE (op))
5135 /* Return true if operator is an integer unary operator that can executed
5139 condexec_si_unary_operator (op, mode)
5141 enum machine_mode mode;
5143 enum machine_mode op_mode = GET_MODE (op);
5145 if (mode != VOIDmode && op_mode != mode)
5148 switch (GET_CODE (op))
5159 /* Return true if operator is a conversion-type expression that can be
5160 evaluated conditionally by floating-point instructions. */
5163 condexec_sf_conv_operator (op, mode)
5165 enum machine_mode mode;
5167 enum machine_mode op_mode = GET_MODE (op);
5169 if (mode != VOIDmode && op_mode != mode)
5172 switch (GET_CODE (op))
5183 /* Return true if operator is an addition or subtraction expression.
5184 Such expressions can be evaluated conditionally by floating-point
5188 condexec_sf_add_operator (op, mode)
5190 enum machine_mode mode;
5192 enum machine_mode op_mode = GET_MODE (op);
5194 if (mode != VOIDmode && op_mode != mode)
5197 switch (GET_CODE (op))
5208 /* Return true if the memory operand is one that can be conditionally
5212 condexec_memory_operand (op, mode)
5214 enum machine_mode mode;
5216 enum machine_mode op_mode = GET_MODE (op);
5219 if (mode != VOIDmode && op_mode != mode)
5234 if (GET_CODE (op) != MEM)
5237 addr = XEXP (op, 0);
5238 if (GET_CODE (addr) == ADDRESSOF)
5241 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE);
5244 /* Return true if operator is an integer binary operator that can be combined
5245 with a setcc operation. Do not allow the arithmetic operations that could
5246 potentially overflow since the FR-V sets the condition code based on the
5247 "true" value of the result, not the result after truncating to a 32-bit
5251 intop_compare_operator (op, mode)
5253 enum machine_mode mode;
5255 enum machine_mode op_mode = GET_MODE (op);
5257 if (mode != VOIDmode && op_mode != mode)
5260 switch (GET_CODE (op))
5273 if (! integer_register_operand (XEXP (op, 0), SImode))
5276 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5282 /* Return true if operator is an integer binary operator that can be combined
5283 with a setcc operation inside of a conditional execution. */
5286 condexec_intop_cmp_operator (op, mode)
5288 enum machine_mode mode;
5290 enum machine_mode op_mode = GET_MODE (op);
5292 if (mode != VOIDmode && op_mode != mode)
5295 switch (GET_CODE (op))
5308 if (! integer_register_operand (XEXP (op, 0), SImode))
5311 if (! integer_register_operand (XEXP (op, 1), SImode))
5317 /* Return 1 if operand is a valid ACC register number */
5320 acc_operand (op, mode)
5322 enum machine_mode mode;
5326 if (GET_MODE (op) != mode && mode != VOIDmode)
5329 if (GET_CODE (op) == SUBREG)
5331 if (GET_CODE (SUBREG_REG (op)) != REG)
5332 return register_operand (op, mode);
5334 op = SUBREG_REG (op);
5337 if (GET_CODE (op) != REG)
5341 return ACC_OR_PSEUDO_P (regno);
5344 /* Return 1 if operand is a valid even ACC register number */
5347 even_acc_operand (op, mode)
5349 enum machine_mode mode;
5353 if (GET_MODE (op) != mode && mode != VOIDmode)
5356 if (GET_CODE (op) == SUBREG)
5358 if (GET_CODE (SUBREG_REG (op)) != REG)
5359 return register_operand (op, mode);
5361 op = SUBREG_REG (op);
5364 if (GET_CODE (op) != REG)
5368 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5371 /* Return 1 if operand is zero or four */
5374 quad_acc_operand (op, mode)
5376 enum machine_mode mode;
5380 if (GET_MODE (op) != mode && mode != VOIDmode)
5383 if (GET_CODE (op) == SUBREG)
5385 if (GET_CODE (SUBREG_REG (op)) != REG)
5386 return register_operand (op, mode);
5388 op = SUBREG_REG (op);
5391 if (GET_CODE (op) != REG)
5395 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5398 /* Return 1 if operand is a valid ACCG register number */
5401 accg_operand (op, mode)
5403 enum machine_mode mode;
5405 if (GET_MODE (op) != mode && mode != VOIDmode)
5408 if (GET_CODE (op) == SUBREG)
5410 if (GET_CODE (SUBREG_REG (op)) != REG)
5411 return register_operand (op, mode);
5413 op = SUBREG_REG (op);
5416 if (GET_CODE (op) != REG)
5419 return ACCG_OR_PSEUDO_P (REGNO (op));
5423 /* Return true if the bare return instruction can be used outside of the
5424 epilog code. For frv, we only do it if there was no stack allocation. */
5431 if (!reload_completed)
5434 info = frv_stack_info ();
5435 return (info->total_size == 0);
5439 /* Emit code to handle a MOVSI, adding in the small data register or pic
5440 register if needed to load up addresses. Return TRUE if the appropriate
5441 instructions are emitted. */
5444 frv_emit_movsi (dest, src)
5448 int base_regno = -1;
5450 if (!reload_in_progress
5451 && !reload_completed
5452 && !register_operand (dest, SImode)
5453 && (!reg_or_0_operand (src, SImode)
5454 /* Virtual registers will almost always be replaced by an
5455 add instruction, so expose this to CSE by copying to
5456 an intermediate register */
5457 || (GET_CODE (src) == REG
5458 && IN_RANGE_P (REGNO (src),
5459 FIRST_VIRTUAL_REGISTER,
5460 LAST_VIRTUAL_REGISTER))))
5462 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5466 /* Explicitly add in the PIC or small data register if needed. */
5467 switch (GET_CODE (src))
5474 base_regno = PIC_REGNO;
5479 if (const_small_data_p (src))
5480 base_regno = SDA_BASE_REG;
5483 base_regno = PIC_REGNO;
5488 if (symbol_ref_small_data_p (src))
5489 base_regno = SDA_BASE_REG;
5492 base_regno = PIC_REGNO;
5497 if (base_regno >= 0)
5499 emit_insn (gen_rtx_SET (VOIDmode, dest,
5500 gen_rtx_PLUS (Pmode,
5501 gen_rtx_REG (Pmode, base_regno),
5504 if (base_regno == PIC_REGNO)
5505 cfun->uses_pic_offset_table = TRUE;
5514 /* Return a string to output a single word move. */
5517 output_move_single (operands, insn)
5521 rtx dest = operands[0];
5522 rtx src = operands[1];
5524 if (GET_CODE (dest) == REG)
5526 int dest_regno = REGNO (dest);
5527 enum machine_mode mode = GET_MODE (dest);
5529 if (GPR_P (dest_regno))
5531 if (GET_CODE (src) == REG)
5533 /* gpr <- some sort of register */
5534 int src_regno = REGNO (src);
5536 if (GPR_P (src_regno))
5537 return "mov %1, %0";
5539 else if (FPR_P (src_regno))
5540 return "movfg %1, %0";
5542 else if (SPR_P (src_regno))
5543 return "movsg %1, %0";
5546 else if (GET_CODE (src) == MEM)
5555 return "ldsb%I1%U1 %M1,%0";
5558 return "ldsh%I1%U1 %M1,%0";
5562 return "ld%I1%U1 %M1, %0";
5566 else if (GET_CODE (src) == CONST_INT
5567 || GET_CODE (src) == CONST_DOUBLE)
5569 /* gpr <- integer/floating constant */
5570 HOST_WIDE_INT value;
5572 if (GET_CODE (src) == CONST_INT)
5573 value = INTVAL (src);
5575 else if (mode == SFmode)
5580 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5581 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5586 value = CONST_DOUBLE_LOW (src);
5588 if (IN_RANGE_P (value, -32768, 32767))
5589 return "setlos %1, %0";
5594 else if (GET_CODE (src) == SYMBOL_REF
5595 || GET_CODE (src) == LABEL_REF
5596 || GET_CODE (src) == CONST)
5598 /* Silently fix up instances where the small data pointer is not
5599 used in the address. */
5600 if (small_data_symbolic_operand (src, GET_MODE (src)))
5601 return "addi %@, #gprel12(%1), %0";
5607 else if (FPR_P (dest_regno))
5609 if (GET_CODE (src) == REG)
5611 /* fpr <- some sort of register */
5612 int src_regno = REGNO (src);
5614 if (GPR_P (src_regno))
5615 return "movgf %1, %0";
5617 else if (FPR_P (src_regno))
5619 if (TARGET_HARD_FLOAT)
5620 return "fmovs %1, %0";
5622 return "mor %1, %1, %0";
5626 else if (GET_CODE (src) == MEM)
5635 return "ldbf%I1%U1 %M1,%0";
5638 return "ldhf%I1%U1 %M1,%0";
5642 return "ldf%I1%U1 %M1, %0";
5646 else if (ZERO_P (src))
5647 return "movgf %., %0";
5650 else if (SPR_P (dest_regno))
5652 if (GET_CODE (src) == REG)
5654 /* spr <- some sort of register */
5655 int src_regno = REGNO (src);
5657 if (GPR_P (src_regno))
5658 return "movgs %1, %0";
5663 else if (GET_CODE (dest) == MEM)
5665 if (GET_CODE (src) == REG)
5667 int src_regno = REGNO (src);
5668 enum machine_mode mode = GET_MODE (dest);
5670 if (GPR_P (src_regno))
5678 return "stb%I0%U0 %1, %M0";
5681 return "sth%I0%U0 %1, %M0";
5685 return "st%I0%U0 %1, %M0";
5689 else if (FPR_P (src_regno))
5697 return "stbf%I0%U0 %1, %M0";
5700 return "sthf%I0%U0 %1, %M0";
5704 return "stf%I0%U0 %1, %M0";
5709 else if (ZERO_P (src))
5711 switch (GET_MODE (dest))
5717 return "stb%I0%U0 %., %M0";
5720 return "sth%I0%U0 %., %M0";
5724 return "st%I0%U0 %., %M0";
5729 fatal_insn ("Bad output_move_single operand", insn);
5734 /* Return a string to output a double word move. */
5737 output_move_double (operands, insn)
5741 rtx dest = operands[0];
5742 rtx src = operands[1];
5743 enum machine_mode mode = GET_MODE (dest);
5745 if (GET_CODE (dest) == REG)
5747 int dest_regno = REGNO (dest);
5749 if (GPR_P (dest_regno))
5751 if (GET_CODE (src) == REG)
5753 /* gpr <- some sort of register */
5754 int src_regno = REGNO (src);
5756 if (GPR_P (src_regno))
5759 else if (FPR_P (src_regno))
5761 if (((dest_regno - GPR_FIRST) & 1) == 0
5762 && ((src_regno - FPR_FIRST) & 1) == 0)
5763 return "movfgd %1, %0";
5769 else if (GET_CODE (src) == MEM)
5772 if (dbl_memory_one_insn_operand (src, mode))
5773 return "ldd%I1%U1 %M1, %0";
5778 else if (GET_CODE (src) == CONST_INT
5779 || GET_CODE (src) == CONST_DOUBLE)
5783 else if (FPR_P (dest_regno))
5785 if (GET_CODE (src) == REG)
5787 /* fpr <- some sort of register */
5788 int src_regno = REGNO (src);
5790 if (GPR_P (src_regno))
5792 if (((dest_regno - FPR_FIRST) & 1) == 0
5793 && ((src_regno - GPR_FIRST) & 1) == 0)
5794 return "movgfd %1, %0";
5799 else if (FPR_P (src_regno))
5802 && ((dest_regno - FPR_FIRST) & 1) == 0
5803 && ((src_regno - FPR_FIRST) & 1) == 0)
5804 return "fmovd %1, %0";
5810 else if (GET_CODE (src) == MEM)
5813 if (dbl_memory_one_insn_operand (src, mode))
5814 return "lddf%I1%U1 %M1, %0";
5819 else if (ZERO_P (src))
5824 else if (GET_CODE (dest) == MEM)
5826 if (GET_CODE (src) == REG)
5828 int src_regno = REGNO (src);
5830 if (GPR_P (src_regno))
5832 if (((src_regno - GPR_FIRST) & 1) == 0
5833 && dbl_memory_one_insn_operand (dest, mode))
5834 return "std%I0%U0 %1, %M0";
5839 if (FPR_P (src_regno))
5841 if (((src_regno - FPR_FIRST) & 1) == 0
5842 && dbl_memory_one_insn_operand (dest, mode))
5843 return "stdf%I0%U0 %1, %M0";
5849 else if (ZERO_P (src))
5851 if (dbl_memory_one_insn_operand (dest, mode))
5852 return "std%I0%U0 %., %M0";
5858 fatal_insn ("Bad output_move_double operand", insn);
5863 /* Return a string to output a single word conditional move.
5864 Operand0 -- EQ/NE of ccr register and 0
5865 Operand1 -- CCR register
5866 Operand2 -- destination
5867 Operand3 -- source */
5870 output_condmove_single (operands, insn)
5874 rtx dest = operands[2];
5875 rtx src = operands[3];
5877 if (GET_CODE (dest) == REG)
5879 int dest_regno = REGNO (dest);
5880 enum machine_mode mode = GET_MODE (dest);
5882 if (GPR_P (dest_regno))
5884 if (GET_CODE (src) == REG)
5886 /* gpr <- some sort of register */
5887 int src_regno = REGNO (src);
5889 if (GPR_P (src_regno))
5890 return "cmov %z3, %2, %1, %e0";
5892 else if (FPR_P (src_regno))
5893 return "cmovfg %3, %2, %1, %e0";
5896 else if (GET_CODE (src) == MEM)
5905 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5908 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5912 return "cld%I3%U3 %M3, %2, %1, %e0";
5916 else if (ZERO_P (src))
5917 return "cmov %., %2, %1, %e0";
5920 else if (FPR_P (dest_regno))
5922 if (GET_CODE (src) == REG)
5924 /* fpr <- some sort of register */
5925 int src_regno = REGNO (src);
5927 if (GPR_P (src_regno))
5928 return "cmovgf %3, %2, %1, %e0";
5930 else if (FPR_P (src_regno))
5932 if (TARGET_HARD_FLOAT)
5933 return "cfmovs %3,%2,%1,%e0";
5935 return "cmor %3, %3, %2, %1, %e0";
5939 else if (GET_CODE (src) == MEM)
5942 if (mode == SImode || mode == SFmode)
5943 return "cldf%I3%U3 %M3, %2, %1, %e0";
5946 else if (ZERO_P (src))
5947 return "cmovgf %., %2, %1, %e0";
5951 else if (GET_CODE (dest) == MEM)
5953 if (GET_CODE (src) == REG)
5955 int src_regno = REGNO (src);
5956 enum machine_mode mode = GET_MODE (dest);
5958 if (GPR_P (src_regno))
5966 return "cstb%I2%U2 %3, %M2, %1, %e0";
5969 return "csth%I2%U2 %3, %M2, %1, %e0";
5973 return "cst%I2%U2 %3, %M2, %1, %e0";
5977 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5978 return "cstf%I2%U2 %3, %M2, %1, %e0";
5981 else if (ZERO_P (src))
5983 enum machine_mode mode = GET_MODE (dest);
5990 return "cstb%I2%U2 %., %M2, %1, %e0";
5993 return "csth%I2%U2 %., %M2, %1, %e0";
5997 return "cst%I2%U2 %., %M2, %1, %e0";
6002 fatal_insn ("Bad output_condmove_single operand", insn);
6007 /* Emit the appropriate code to do a comparison, returning the register the
6008 comparison was done it. */
6011 frv_emit_comparison (test, op0, op1)
6016 enum machine_mode cc_mode;
6019 /* Floating point doesn't have comparison against a constant */
6020 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6021 op1 = force_reg (GET_MODE (op0), op1);
6023 /* Possibly disable using anything but a fixed register in order to work
6024 around cse moving comparisons past function calls. */
6025 cc_mode = SELECT_CC_MODE (test, op0, op1);
6026 cc_reg = ((TARGET_ALLOC_CC)
6027 ? gen_reg_rtx (cc_mode)
6028 : gen_rtx_REG (cc_mode,
6029 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6031 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6032 gen_rtx_COMPARE (cc_mode, op0, op1)));
6038 /* Emit code for a conditional branch. The comparison operands were previously
6039 stored in frv_compare_op0 and frv_compare_op1.
6041 XXX: I originally wanted to add a clobber of a CCR register to use in
6042 conditional execution, but that confuses the rest of the compiler. */
6045 frv_emit_cond_branch (test, label)
6052 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6053 enum machine_mode cc_mode = GET_MODE (cc_reg);
6055 /* Branches generate:
6057 (if_then_else (<test>, <cc_reg>, (const_int 0))
6058 (label_ref <branch_label>)
6060 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6061 test_rtx = gen_rtx (test, cc_mode, cc_reg, const0_rtx);
6062 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6063 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6068 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6069 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6072 frv_emit_scc (test, target)
6080 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6082 /* SCC instructions generate:
6083 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6084 (clobber (<ccr_reg>))]) */
6085 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6086 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6088 cr_reg = ((TARGET_ALLOC_CC)
6089 ? gen_reg_rtx (CC_CCRmode)
6090 : gen_rtx_REG (CC_CCRmode,
6091 ((GET_MODE (cc_reg) == CC_FPmode)
6095 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6096 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6101 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6102 the seperate insns. */
6105 frv_split_scc (dest, test, cc_reg, cr_reg, value)
6110 HOST_WIDE_INT value;
6116 /* Set the appropriate CCR bit. */
6117 emit_insn (gen_rtx_SET (VOIDmode,
6119 gen_rtx_fmt_ee (GET_CODE (test),
6124 /* Move the value into the destination. */
6125 emit_move_insn (dest, GEN_INT (value));
6127 /* Move 0 into the destination if the test failed */
6128 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6129 gen_rtx_EQ (GET_MODE (cr_reg),
6132 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6134 /* Finish up, return sequence. */
6141 /* Emit the code for a conditional move, return TRUE if we could do the
6145 frv_emit_cond_move (dest, test_rtx, src1, src2)
6156 enum rtx_code test = GET_CODE (test_rtx);
6157 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6158 enum machine_mode cc_mode = GET_MODE (cc_reg);
6160 /* Conditional move instructions generate:
6161 (parallel [(set <target>
6162 (if_then_else (<test> <cc_reg> (const_int 0))
6165 (clobber (<ccr_reg>))]) */
6167 /* Handle various cases of conditional move involving two constants. */
6168 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6170 HOST_WIDE_INT value1 = INTVAL (src1);
6171 HOST_WIDE_INT value2 = INTVAL (src2);
6173 /* having 0 as one of the constants can be done by loading the other
6174 constant, and optionally moving in gr0. */
6175 if (value1 == 0 || value2 == 0)
6178 /* If the first value is within an addi range and also the difference
6179 between the two fits in an addi's range, load up the difference, then
6180 conditionally move in 0, and then unconditionally add the first
6182 else if (IN_RANGE_P (value1, -2048, 2047)
6183 && IN_RANGE_P (value2 - value1, -2048, 2047))
6186 /* If neither condition holds, just force the constant into a
6190 src1 = force_reg (GET_MODE (dest), src1);
6191 src2 = force_reg (GET_MODE (dest), src2);
6195 /* If one value is a register, insure the other value is either 0 or a
6199 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6200 src1 = force_reg (GET_MODE (dest), src1);
6202 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6203 src2 = force_reg (GET_MODE (dest), src2);
6206 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6207 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6209 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6211 cr_reg = ((TARGET_ALLOC_CC)
6212 ? gen_reg_rtx (CC_CCRmode)
6213 : gen_rtx_REG (CC_CCRmode,
6214 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6216 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6217 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6222 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6223 containing all of the insns. */
6226 frv_split_cond_move (operands)
6229 rtx dest = operands[0];
6230 rtx test = operands[1];
6231 rtx cc_reg = operands[2];
6232 rtx src1 = operands[3];
6233 rtx src2 = operands[4];
6234 rtx cr_reg = operands[5];
6236 enum machine_mode cr_mode = GET_MODE (cr_reg);
6240 /* Set the appropriate CCR bit. */
6241 emit_insn (gen_rtx_SET (VOIDmode,
6243 gen_rtx_fmt_ee (GET_CODE (test),
6248 /* Handle various cases of conditional move involving two constants. */
6249 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6251 HOST_WIDE_INT value1 = INTVAL (src1);
6252 HOST_WIDE_INT value2 = INTVAL (src2);
6254 /* having 0 as one of the constants can be done by loading the other
6255 constant, and optionally moving in gr0. */
6258 emit_move_insn (dest, src2);
6259 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6260 gen_rtx_NE (cr_mode, cr_reg,
6262 gen_rtx_SET (VOIDmode, dest, src1)));
6265 else if (value2 == 0)
6267 emit_move_insn (dest, src1);
6268 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6269 gen_rtx_EQ (cr_mode, cr_reg,
6271 gen_rtx_SET (VOIDmode, dest, src2)));
6274 /* If the first value is within an addi range and also the difference
6275 between the two fits in an addi's range, load up the difference, then
6276 conditionally move in 0, and then unconditionally add the first
6278 else if (IN_RANGE_P (value1, -2048, 2047)
6279 && IN_RANGE_P (value2 - value1, -2048, 2047))
6281 rtx dest_si = ((GET_MODE (dest) == SImode)
6283 : gen_rtx_SUBREG (SImode, dest, 0));
6285 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6286 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6287 gen_rtx_NE (cr_mode, cr_reg,
6289 gen_rtx_SET (VOIDmode, dest_si,
6291 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6299 /* Emit the conditional move for the test being true if needed. */
6300 if (! rtx_equal_p (dest, src1))
6301 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6302 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6303 gen_rtx_SET (VOIDmode, dest, src1)));
6305 /* Emit the conditional move for the test being false if needed. */
6306 if (! rtx_equal_p (dest, src2))
6307 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6308 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6309 gen_rtx_SET (VOIDmode, dest, src2)));
6312 /* Finish up, return sequence. */
6319 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6320 memory location that is not known to be dword-aligned. */
6322 frv_split_double_load (dest, source)
6326 int regno = REGNO (dest);
6327 rtx dest1 = gen_highpart (SImode, dest);
6328 rtx dest2 = gen_lowpart (SImode, dest);
6329 rtx address = XEXP (source, 0);
6331 /* If the address is pre-modified, load the lower-numbered register
6332 first, then load the other register using an integer offset from
6333 the modified base register. This order should always be safe,
6334 since the pre-modification cannot affect the same registers as the
6337 The situation for other loads is more complicated. Loading one
6338 of the registers could affect the value of ADDRESS, so we must
6339 be careful which order we do them in. */
6340 if (GET_CODE (address) == PRE_MODIFY
6341 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6343 /* It is safe to load the lower-numbered register first. */
6344 emit_move_insn (dest1, change_address (source, SImode, NULL));
6345 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6349 /* ADDRESS is not pre-modified and the address depends on the
6350 lower-numbered register. Load the higher-numbered register
6352 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6353 emit_move_insn (dest1, change_address (source, SImode, NULL));
6357 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6358 and SOURCE is either a double register or the constant zero. */
6360 frv_split_double_store (dest, source)
6364 rtx dest1 = change_address (dest, SImode, NULL);
6365 rtx dest2 = frv_index_memory (dest, SImode, 1);
6366 if (ZERO_P (source))
6368 emit_move_insn (dest1, CONST0_RTX (SImode));
6369 emit_move_insn (dest2, CONST0_RTX (SImode));
6373 emit_move_insn (dest1, gen_highpart (SImode, source));
6374 emit_move_insn (dest2, gen_lowpart (SImode, source));
6379 /* Split a min/max operation returning a SEQUENCE containing all of the
6383 frv_split_minmax (operands)
6386 rtx dest = operands[0];
6387 rtx minmax = operands[1];
6388 rtx src1 = operands[2];
6389 rtx src2 = operands[3];
6390 rtx cc_reg = operands[4];
6391 rtx cr_reg = operands[5];
6393 enum rtx_code test_code;
6394 enum machine_mode cr_mode = GET_MODE (cr_reg);
6398 /* Figure out which test to use */
6399 switch (GET_CODE (minmax))
6404 case SMIN: test_code = LT; break;
6405 case SMAX: test_code = GT; break;
6406 case UMIN: test_code = LTU; break;
6407 case UMAX: test_code = GTU; break;
6410 /* Issue the compare instruction. */
6411 emit_insn (gen_rtx_SET (VOIDmode,
6413 gen_rtx_COMPARE (GET_MODE (cc_reg),
6416 /* Set the appropriate CCR bit. */
6417 emit_insn (gen_rtx_SET (VOIDmode,
6419 gen_rtx_fmt_ee (test_code,
6424 /* If are taking the min/max of a nonzero constant, load that first, and
6425 then do a conditional move of the other value. */
6426 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6428 if (rtx_equal_p (dest, src1))
6431 emit_move_insn (dest, src2);
6432 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6433 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6434 gen_rtx_SET (VOIDmode, dest, src1)));
6437 /* Otherwise, do each half of the move. */
6440 /* Emit the conditional move for the test being true if needed. */
6441 if (! rtx_equal_p (dest, src1))
6442 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6443 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6444 gen_rtx_SET (VOIDmode, dest, src1)));
6446 /* Emit the conditional move for the test being false if needed. */
6447 if (! rtx_equal_p (dest, src2))
6448 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6449 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6450 gen_rtx_SET (VOIDmode, dest, src2)));
6453 /* Finish up, return sequence. */
6460 /* Split an integer abs operation returning a SEQUENCE containing all of the
6464 frv_split_abs (operands)
6467 rtx dest = operands[0];
6468 rtx src = operands[1];
6469 rtx cc_reg = operands[2];
6470 rtx cr_reg = operands[3];
6475 /* Issue the compare < 0 instruction. */
6476 emit_insn (gen_rtx_SET (VOIDmode,
6478 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6480 /* Set the appropriate CCR bit. */
6481 emit_insn (gen_rtx_SET (VOIDmode,
6483 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6485 /* Emit the conditional negate if the value is negative */
6486 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6487 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6488 gen_negsi2 (dest, src)));
6490 /* Emit the conditional move for the test being false if needed. */
6491 if (! rtx_equal_p (dest, src))
6492 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6493 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6494 gen_rtx_SET (VOIDmode, dest, src)));
6496 /* Finish up, return sequence. */
6503 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6504 register used in an insn. */
6507 frv_clear_registers_used (ptr, data)
6511 if (GET_CODE (*ptr) == REG)
6513 int regno = REGNO (*ptr);
6514 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6516 if (regno < FIRST_PSEUDO_REGISTER)
6518 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6520 while (regno < reg_max)
6522 CLEAR_HARD_REG_BIT (*p_regs, regno);
6532 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6534 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6535 initialize the static storage. */
6537 frv_ifcvt_init_extra_fields (ce_info)
6538 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
6540 frv_ifcvt.added_insns_list = NULL_RTX;
6541 frv_ifcvt.cur_scratch_regs = 0;
6542 frv_ifcvt.num_nested_cond_exec = 0;
6543 frv_ifcvt.cr_reg = NULL_RTX;
6544 frv_ifcvt.nested_cc_reg = NULL_RTX;
6545 frv_ifcvt.extra_int_cr = NULL_RTX;
6546 frv_ifcvt.extra_fp_cr = NULL_RTX;
6547 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6551 /* Internal function to add a potenial insn to the list of insns to be inserted
6552 if the conditional execution conversion is successful. */
6555 frv_ifcvt_add_insn (pattern, insn, before_p)
6560 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6562 link->jump = before_p; /* mark to add this before or after insn */
6563 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6564 frv_ifcvt.added_insns_list);
6566 if (TARGET_DEBUG_COND_EXEC)
6569 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6570 (before_p) ? "before" : "after",
6571 (int)INSN_UID (insn));
6573 debug_rtx (pattern);
6578 /* A C expression to modify the code described by the conditional if
6579 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6580 FALSE_EXPR for converting if-then and if-then-else code to conditional
6581 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6582 tests cannot be converted. */
6585 frv_ifcvt_modify_tests (ce_info, p_true, p_false)
6586 ce_if_block_t *ce_info;
6590 basic_block test_bb = ce_info->test_bb; /* test basic block */
6591 basic_block then_bb = ce_info->then_bb; /* THEN */
6592 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6593 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6594 rtx true_expr = *p_true;
6598 enum machine_mode mode = GET_MODE (true_expr);
6602 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6604 rtx sub_cond_exec_reg;
6606 enum rtx_code code_true;
6607 enum rtx_code code_false;
6608 enum reg_class cc_class;
6609 enum reg_class cr_class;
6613 /* Make sure we are only dealing with hard registers. Also honor the
6614 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6616 if (!reload_completed || TARGET_NO_COND_EXEC
6617 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6620 /* Figure out which registers we can allocate for our own purposes. Only
6621 consider registers that are not preserved across function calls and are
6622 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6623 if we did not need to use them in reloading other registers. */
6624 memset ((PTR) &tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6625 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6626 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6627 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6628 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6630 /* If this is a nested IF, we need to discover whether the CC registers that
6631 are set/used inside of the block are used anywhere else. If not, we can
6632 change them to be the CC register that is paired with the CR register that
6633 controls the outermost IF block. */
6634 if (ce_info->pass > 1)
6636 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6637 for (j = CC_FIRST; j <= CC_LAST; j++)
6638 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6640 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6643 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6646 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6649 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6653 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6654 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6656 frv_ifcvt.added_insns_list = NULL_RTX;
6657 frv_ifcvt.cur_scratch_regs = 0;
6659 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6660 * sizeof (basic_block));
6666 /* Remove anything live at the beginning of the join block from being
6667 available for allocation. */
6668 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6670 if (regno < FIRST_PSEUDO_REGISTER)
6671 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6675 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6677 if (ce_info->num_multiple_test_blocks)
6679 basic_block multiple_test_bb = ce_info->last_test_bb;
6681 while (multiple_test_bb != test_bb)
6683 bb[num_bb++] = multiple_test_bb;
6684 multiple_test_bb = multiple_test_bb->pred->src;
6688 /* Add in the THEN and ELSE blocks to be scanned. */
6689 bb[num_bb++] = then_bb;
6691 bb[num_bb++] = else_bb;
6693 sub_cond_exec_reg = NULL_RTX;
6694 frv_ifcvt.num_nested_cond_exec = 0;
6696 /* Scan all of the blocks for registers that must not be allocated. */
6697 for (j = 0; j < num_bb; j++)
6699 rtx last_insn = bb[j]->end;
6700 rtx insn = bb[j]->head;
6704 fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n",
6705 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6707 (int) INSN_UID (bb[j]->head),
6708 (int) INSN_UID (bb[j]->end));
6710 /* Anything live at the beginning of the block is obviously unavailable
6712 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6714 if (regno < FIRST_PSEUDO_REGISTER)
6715 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6718 /* loop through the insns in the block. */
6721 /* Mark any new registers that are created as being unavailable for
6722 allocation. Also see if the CC register used in nested IFs can be
6728 int skip_nested_if = FALSE;
6730 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6731 (void *)&tmp_reg->regs);
6733 pattern = PATTERN (insn);
6734 if (GET_CODE (pattern) == COND_EXEC)
6736 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6738 if (reg != sub_cond_exec_reg)
6740 sub_cond_exec_reg = reg;
6741 frv_ifcvt.num_nested_cond_exec++;
6745 set = single_set_pattern (pattern);
6748 rtx dest = SET_DEST (set);
6749 rtx src = SET_SRC (set);
6751 if (GET_CODE (dest) == REG)
6753 int regno = REGNO (dest);
6754 enum rtx_code src_code = GET_CODE (src);
6756 if (CC_P (regno) && src_code == COMPARE)
6757 skip_nested_if = TRUE;
6759 else if (CR_P (regno)
6760 && (src_code == IF_THEN_ELSE
6761 || GET_RTX_CLASS (src_code) == '<'))
6762 skip_nested_if = TRUE;
6766 if (! skip_nested_if)
6767 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6768 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6771 if (insn == last_insn)
6774 insn = NEXT_INSN (insn);
6778 /* If this is a nested if, rewrite the CC registers that are available to
6779 include the ones that can be rewritten, to increase the chance of being
6780 able to allocate a paired CC/CR register combination. */
6781 if (ce_info->pass > 1)
6783 for (j = CC_FIRST; j <= CC_LAST; j++)
6784 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6785 SET_HARD_REG_BIT (tmp_reg->regs, j);
6787 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6793 fprintf (rtl_dump_file, "Available GPRs: ");
6795 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6796 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6798 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6799 if (++num_gprs > GPR_TEMP_NUM+2)
6803 fprintf (rtl_dump_file, "%s\nAvailable CRs: ",
6804 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6806 for (j = CR_FIRST; j <= CR_LAST; j++)
6807 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6808 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6810 fputs ("\n", rtl_dump_file);
6812 if (ce_info->pass > 1)
6814 fprintf (rtl_dump_file, "Modifiable CCs: ");
6815 for (j = CC_FIRST; j <= CC_LAST; j++)
6816 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6817 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6819 fprintf (rtl_dump_file, "\n%d nested COND_EXEC statements\n",
6820 frv_ifcvt.num_nested_cond_exec);
6824 /* Allocate the appropriate temporary condition code register. Try to
6825 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6826 that conditional cmp's can be done. */
6827 if (mode == CCmode || mode == CC_UNSmode)
6829 cr_class = ICR_REGS;
6830 cc_class = ICC_REGS;
6831 cc_first = ICC_FIRST;
6834 else if (mode == CC_FPmode)
6836 cr_class = FCR_REGS;
6837 cc_class = FCC_REGS;
6838 cc_first = FCC_FIRST;
6843 cc_first = cc_last = 0;
6844 cr_class = cc_class = NO_REGS;
6847 cc = XEXP (true_expr, 0);
6848 nested_cc = cr = NULL_RTX;
6849 if (cc_class != NO_REGS)
6851 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6852 so we can execute a csubcc/caddcc/cfcmps instruction. */
6855 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6857 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6859 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6860 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6862 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6863 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6866 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6867 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6877 fprintf (rtl_dump_file, "Could not allocate a CR temporary register\n");
6883 fprintf (rtl_dump_file,
6884 "Will use %s for conditional execution, %s for nested comparisons\n",
6885 reg_names[ REGNO (cr)],
6886 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6888 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6889 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6890 bit being true. We don't do this for floating point, because of NaNs. */
6891 code = GET_CODE (true_expr);
6892 if (GET_MODE (cc) != CC_FPmode)
6894 code = reverse_condition (code);
6904 check_insn = gen_rtx_SET (VOIDmode, cr,
6905 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6907 /* Record the check insn to be inserted later. */
6908 frv_ifcvt_add_insn (check_insn, test_bb->end, TRUE);
6910 /* Update the tests. */
6911 frv_ifcvt.cr_reg = cr;
6912 frv_ifcvt.nested_cc_reg = nested_cc;
6913 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6914 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6917 /* Fail, don't do this conditional execution. */
6920 *p_false = NULL_RTX;
6922 fprintf (rtl_dump_file, "Disabling this conditional execution.\n");
6928 /* A C expression to modify the code described by the conditional if
6929 information CE_INFO, for the basic block BB, possibly updating the tests in
6930 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6931 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6932 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6934 /* p_true and p_false are given expressions of the form:
6936 (and (eq:CC_CCR (reg:CC_CCR)
6942 frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false)
6943 ce_if_block_t *ce_info;
6948 rtx old_true = XEXP (*p_true, 0);
6949 rtx old_false = XEXP (*p_false, 0);
6950 rtx true_expr = XEXP (*p_true, 1);
6951 rtx false_expr = XEXP (*p_false, 1);
6954 rtx cr = XEXP (old_true, 0);
6956 rtx new_cr = NULL_RTX;
6957 rtx *p_new_cr = (rtx *)0;
6961 enum reg_class cr_class;
6962 enum machine_mode mode = GET_MODE (true_expr);
6963 rtx (*logical_func)(rtx, rtx, rtx);
6965 if (TARGET_DEBUG_COND_EXEC)
6968 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6969 ce_info->and_and_p ? "&&" : "||");
6971 debug_rtx (*p_true);
6973 fputs ("\nfalse insn:\n", stderr);
6974 debug_rtx (*p_false);
6977 if (TARGET_NO_MULTI_CE)
6980 if (GET_CODE (cr) != REG)
6983 if (mode == CCmode || mode == CC_UNSmode)
6985 cr_class = ICR_REGS;
6986 p_new_cr = &frv_ifcvt.extra_int_cr;
6988 else if (mode == CC_FPmode)
6990 cr_class = FCR_REGS;
6991 p_new_cr = &frv_ifcvt.extra_fp_cr;
6996 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6997 more &&/|| tests. */
7001 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7002 CC_CCRmode, TRUE, TRUE);
7007 if (ce_info->and_and_p)
7009 old_test = old_false;
7010 test_expr = true_expr;
7011 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7012 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7013 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7017 old_test = old_false;
7018 test_expr = false_expr;
7019 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7020 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7021 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7024 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7025 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7027 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), bb->end, TRUE);
7029 /* Now add the conditional check insn. */
7030 cc = XEXP (test_expr, 0);
7031 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7032 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7034 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7036 /* add the new check insn to the list of check insns that need to be
7038 frv_ifcvt_add_insn (check_insn, bb->end, TRUE);
7040 if (TARGET_DEBUG_COND_EXEC)
7042 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7045 debug_rtx (*p_true);
7047 fputs ("\nfalse insn:\n", stderr);
7048 debug_rtx (*p_false);
7054 *p_true = *p_false = NULL_RTX;
7056 /* If we allocated a CR register, release it. */
7059 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7060 *p_new_cr = NULL_RTX;
7063 if (TARGET_DEBUG_COND_EXEC)
7064 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7070 /* Return a register which will be loaded with a value if an IF block is
7071 converted to conditional execution. This is used to rewrite instructions
7072 that use constants to ones that just use registers. */
7075 frv_ifcvt_load_value (value, insn)
7077 rtx insn ATTRIBUTE_UNUSED;
7079 int num_alloc = frv_ifcvt.cur_scratch_regs;
7083 /* We know gr0 == 0, so replace any errant uses. */
7084 if (value == const0_rtx)
7085 return gen_rtx_REG (SImode, GPR_FIRST);
7087 /* First search all registers currently loaded to see if we have an
7088 applicable constant. */
7089 if (CONSTANT_P (value)
7090 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7092 for (i = 0; i < num_alloc; i++)
7094 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7095 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7099 /* Have we exhausted the number of registers available? */
7100 if (num_alloc >= GPR_TEMP_NUM)
7103 fprintf (rtl_dump_file, "Too many temporary registers allocated\n");
7108 /* Allocate the new register. */
7109 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7113 fputs ("Could not find a scratch register\n", rtl_dump_file);
7118 frv_ifcvt.cur_scratch_regs++;
7119 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7123 if (GET_CODE (value) == CONST_INT)
7124 fprintf (rtl_dump_file, "Register %s will hold %ld\n",
7125 reg_names[ REGNO (reg)], (long)INTVAL (value));
7127 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7128 fprintf (rtl_dump_file, "Register %s will hold LR\n",
7129 reg_names[ REGNO (reg)]);
7132 fprintf (rtl_dump_file, "Register %s will hold a saved value\n",
7133 reg_names[ REGNO (reg)]);
7140 /* Update a MEM used in conditional code that might contain an offset to put
7141 the offset into a scratch register, so that the conditional load/store
7142 operations can be used. This function returns the original pointer if the
7143 MEM is valid to use in conditional code, NULL if we can't load up the offset
7144 into a temporary register, or the new MEM if we were successful. */
7147 frv_ifcvt_rewrite_mem (mem, mode, insn)
7149 enum machine_mode mode;
7152 rtx addr = XEXP (mem, 0);
7154 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE))
7156 if (GET_CODE (addr) == PLUS)
7158 rtx addr_op0 = XEXP (addr, 0);
7159 rtx addr_op1 = XEXP (addr, 1);
7161 if (plus_small_data_p (addr_op0, addr_op1))
7162 addr = frv_ifcvt_load_value (addr, insn);
7164 else if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7166 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7170 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7177 else if (CONSTANT_P (addr))
7178 addr = frv_ifcvt_load_value (addr, insn);
7183 if (addr == NULL_RTX)
7186 else if (XEXP (mem, 0) != addr)
7187 return change_address (mem, mode, addr);
7194 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7195 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7198 single_set_pattern (pattern)
7204 if (GET_CODE (pattern) == COND_EXEC)
7205 pattern = COND_EXEC_CODE (pattern);
7207 if (GET_CODE (pattern) == SET)
7210 else if (GET_CODE (pattern) == PARALLEL)
7212 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7214 rtx sub = XVECEXP (pattern, 0, i);
7216 switch (GET_CODE (sub))
7240 /* A C expression to modify the code described by the conditional if
7241 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7242 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7243 insn cannot be converted to be executed conditionally. */
7246 frv_ifcvt_modify_insn (ce_info, pattern, insn)
7247 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7251 rtx orig_ce_pattern = pattern;
7257 if (GET_CODE (pattern) != COND_EXEC)
7260 test = COND_EXEC_TEST (pattern);
7261 if (GET_CODE (test) == AND)
7263 rtx cr = frv_ifcvt.cr_reg;
7266 op0 = XEXP (test, 0);
7267 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7270 op1 = XEXP (test, 1);
7271 test_reg = XEXP (op1, 0);
7272 if (GET_CODE (test_reg) != REG)
7275 /* Is this the first nested if block in this sequence? If so, generate
7276 an andcr or andncr. */
7277 if (! frv_ifcvt.last_nested_if_cr)
7281 frv_ifcvt.last_nested_if_cr = test_reg;
7282 if (GET_CODE (op0) == NE)
7283 and_op = gen_andcr (test_reg, cr, test_reg);
7285 and_op = gen_andncr (test_reg, cr, test_reg);
7287 frv_ifcvt_add_insn (and_op, insn, TRUE);
7290 /* If this isn't the first statement in the nested if sequence, see if we
7291 are dealing with the same register. */
7292 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7295 COND_EXEC_TEST (pattern) = test = op1;
7298 /* If this isn't a nested if, reset state variables. */
7301 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7304 set = single_set_pattern (pattern);
7307 rtx dest = SET_DEST (set);
7308 rtx src = SET_SRC (set);
7309 enum machine_mode mode = GET_MODE (dest);
7311 /* Check for normal binary operators */
7313 && (GET_RTX_CLASS (GET_CODE (src)) == '2'
7314 || GET_RTX_CLASS (GET_CODE (src)) == 'c'))
7316 op0 = XEXP (src, 0);
7317 op1 = XEXP (src, 1);
7319 /* Special case load of small data address which looks like:
7321 if (GET_CODE (src) == PLUS && plus_small_data_p (op0, op1))
7323 src = frv_ifcvt_load_value (src, insn);
7325 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7330 else if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7332 op1 = frv_ifcvt_load_value (op1, insn);
7334 COND_EXEC_CODE (pattern)
7335 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7343 /* For multiply by a constant, we need to handle the sign extending
7344 correctly. Add a USE of the value after the multiply to prevent flow
7345 from cratering because only one register out of the two were used. */
7346 else if (mode == DImode && GET_CODE (src) == MULT)
7348 op0 = XEXP (src, 0);
7349 op1 = XEXP (src, 1);
7350 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7352 op1 = frv_ifcvt_load_value (op1, insn);
7355 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7356 COND_EXEC_CODE (pattern)
7357 = gen_rtx_SET (VOIDmode, dest,
7358 gen_rtx_MULT (DImode, op0, op1));
7364 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7367 /* If we are just loading a constant created for a nested conditional
7368 execution statement, just load the constant without any conditional
7369 execution, since we know that the constant will not interfere with any
7371 else if (frv_ifcvt.scratch_insns_bitmap
7372 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7376 else if (mode == QImode || mode == HImode || mode == SImode
7379 int changed_p = FALSE;
7381 /* Check for just loading up a constant */
7382 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7384 src = frv_ifcvt_load_value (src, insn);
7391 /* See if we need to fix up stores */
7392 if (GET_CODE (dest) == MEM)
7394 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7399 else if (new_mem != dest)
7406 /* See if we need to fix up loads */
7407 if (GET_CODE (src) == MEM)
7409 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7414 else if (new_mem != src)
7421 /* If either src or destination changed, redo SET. */
7423 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7426 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7427 rewriting the CC register to be the same as the paired CC/CR register
7429 else if (mode == CC_CCRmode && GET_RTX_CLASS (GET_CODE (src)) == '<')
7431 int regno = REGNO (XEXP (src, 0));
7434 if (ce_info->pass > 1
7435 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7436 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7438 src = gen_rtx_fmt_ee (GET_CODE (src),
7440 frv_ifcvt.nested_cc_reg,
7444 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7445 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7448 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7449 else if (ce_info->pass > 1
7450 && GET_CODE (dest) == REG
7451 && CC_P (REGNO (dest))
7452 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7453 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7455 && GET_CODE (src) == COMPARE)
7457 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7458 COND_EXEC_CODE (pattern)
7459 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7463 if (TARGET_DEBUG_COND_EXEC)
7465 rtx orig_pattern = PATTERN (insn);
7467 PATTERN (insn) = pattern;
7469 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7473 PATTERN (insn) = orig_pattern;
7479 if (TARGET_DEBUG_COND_EXEC)
7481 rtx orig_pattern = PATTERN (insn);
7483 PATTERN (insn) = orig_ce_pattern;
7485 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7489 PATTERN (insn) = orig_pattern;
7496 /* A C expression to perform any final machine dependent modifications in
7497 converting code to conditional execution in the code described by the
7498 conditional if information CE_INFO. */
7501 frv_ifcvt_modify_final (ce_info)
7502 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7506 rtx p = frv_ifcvt.added_insns_list;
7509 /* Loop inserting the check insns. The last check insn is the first test,
7510 and is the appropriate place to insert constants. */
7516 rtx check_and_insert_insns = XEXP (p, 0);
7519 check_insn = XEXP (check_and_insert_insns, 0);
7520 existing_insn = XEXP (check_and_insert_insns, 1);
7523 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7524 the existing insn, otherwise it is to be inserted AFTER. */
7525 if (check_and_insert_insns->jump)
7527 emit_insn_before (check_insn, existing_insn);
7528 check_and_insert_insns->jump = 0;
7531 emit_insn_after (check_insn, existing_insn);
7533 free_EXPR_LIST_node (check_and_insert_insns);
7534 free_EXPR_LIST_node (old_p);
7536 while (p != NULL_RTX);
7538 /* Load up any constants needed into temp gprs */
7539 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7541 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7542 if (! frv_ifcvt.scratch_insns_bitmap)
7543 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7544 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7545 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7548 frv_ifcvt.added_insns_list = NULL_RTX;
7549 frv_ifcvt.cur_scratch_regs = 0;
7553 /* A C expression to cancel any machine dependent modifications in converting
7554 code to conditional execution in the code described by the conditional if
7555 information CE_INFO. */
7558 frv_ifcvt_modify_cancel (ce_info)
7559 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7562 rtx p = frv_ifcvt.added_insns_list;
7564 /* Loop freeing up the EXPR_LIST's allocated. */
7565 while (p != NULL_RTX)
7567 rtx check_and_jump = XEXP (p, 0);
7571 free_EXPR_LIST_node (check_and_jump);
7572 free_EXPR_LIST_node (old_p);
7575 /* Release any temporary gprs allocated. */
7576 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7577 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7579 frv_ifcvt.added_insns_list = NULL_RTX;
7580 frv_ifcvt.cur_scratch_regs = 0;
7584 /* A C expression for the size in bytes of the trampoline, as an integer.
7588 setlo #0, <static_chain>
7590 sethi #0, <static_chain>
7591 jmpl @(gr0,<jmp_reg>) */
7594 frv_trampoline_size ()
7596 return 5 /* instructions */ * 4 /* instruction size */;
7600 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7601 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7602 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7603 should be passed to the function when it is called.
7608 setlo #0, <static_chain>
7610 sethi #0, <static_chain>
7611 jmpl @(gr0,<jmp_reg>) */
7614 frv_initialize_trampoline (addr, fnaddr, static_chain)
7619 rtx sc_reg = force_reg (Pmode, static_chain);
7621 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7624 GEN_INT (frv_trampoline_size ()), SImode,
7630 /* Many machines have some registers that cannot be copied directly to or from
7631 memory or even from other types of registers. An example is the `MQ'
7632 register, which on most machines, can only be copied to or from general
7633 registers, but not memory. Some machines allow copying all registers to and
7634 from memory, but require a scratch register for stores to some memory
7635 locations (e.g., those with symbolic address on the RT, and those with
7636 certain symbolic address on the SPARC when compiling PIC). In some cases,
7637 both an intermediate and a scratch register are required.
7639 You should define these macros to indicate to the reload phase that it may
7640 need to allocate at least one register for a reload in addition to the
7641 register to contain the data. Specifically, if copying X to a register
7642 CLASS in MODE requires an intermediate register, you should define
7643 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7644 whose registers can be used as intermediate registers or scratch registers.
7646 If copying a register CLASS in MODE to X requires an intermediate or scratch
7647 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7648 largest register class required. If the requirements for input and output
7649 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7650 instead of defining both macros identically.
7652 The values returned by these macros are often `GENERAL_REGS'. Return
7653 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7654 to or from a register of CLASS in MODE without requiring a scratch register.
7655 Do not define this macro if it would always return `NO_REGS'.
7657 If a scratch register is required (either with or without an intermediate
7658 register), you should define patterns for `reload_inM' or `reload_outM', as
7659 required.. These patterns, which will normally be implemented with a
7660 `define_expand', should be similar to the `movM' patterns, except that
7661 operand 2 is the scratch register.
7663 Define constraints for the reload register and scratch register that contain
7664 a single register class. If the original reload register (whose class is
7665 CLASS) can meet the constraint given in the pattern, the value returned by
7666 these macros is used for the class of the scratch register. Otherwise, two
7667 additional reload registers are required. Their classes are obtained from
7668 the constraints in the insn pattern.
7670 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7671 either be in a hard register or in memory. Use `true_regnum' to find out;
7672 it will return -1 if the pseudo is in memory and the hard register number if
7673 it is in a register.
7675 These macros should not be used in the case where a particular class of
7676 registers can only be copied to memory and not to another class of
7677 registers. In that case, secondary reload registers are not needed and
7678 would not be helpful. Instead, a stack location must be used to perform the
7679 copy and the `movM' pattern should use memory as an intermediate storage.
7680 This case often occurs between floating-point and general registers. */
7683 frv_secondary_reload_class (class, mode, x, in_p)
7684 enum reg_class class;
7685 enum machine_mode mode ATTRIBUTE_UNUSED;
7687 int in_p ATTRIBUTE_UNUSED;
7697 /* Accumulators/Accumulator guard registers need to go through floating
7703 if (x && GET_CODE (x) == REG)
7705 int regno = REGNO (x);
7707 if (ACC_P (regno) || ACCG_P (regno))
7712 /* Nonzero constants should be loaded into an FPR through a GPR. */
7716 if (x && CONSTANT_P (x) && !ZERO_P (x))
7722 /* All of these types need gpr registers. */
7734 /* The accumulators need fpr registers */
7747 /* A C expression whose value is nonzero if pseudos that have been assigned to
7748 registers of class CLASS would likely be spilled because registers of CLASS
7749 are needed for spill registers.
7751 The default value of this macro returns 1 if CLASS has exactly one register
7752 and zero otherwise. On most machines, this default should be used. Only
7753 define this macro to some other expression if pseudo allocated by
7754 `local-alloc.c' end up in memory because their hard registers were needed
7755 for spill registers. If this macro returns nonzero for those classes, those
7756 pseudos will only be allocated by `global.c', which knows how to reallocate
7757 the pseudo to another register. If there would not be another register
7758 available for reallocation, you should not change the definition of this
7759 macro since the only effect of such a definition would be to slow down
7760 register allocation. */
7763 frv_class_likely_spilled_p (class)
7764 enum reg_class class;
7791 /* An expression for the alignment of a structure field FIELD if the
7792 alignment computed in the usual way is COMPUTED. GNU CC uses this
7793 value instead of the value in `BIGGEST_ALIGNMENT' or
7794 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7796 /* The definition type of the bit field data is either char, short, long or
7797 long long. The maximum bit size is the number of bits of its own type.
7799 The bit field data is assigned to a storage unit that has an adequate size
7800 for bit field data retention and is located at the smallest address.
7802 Consecutive bit field data are packed at consecutive bits having the same
7803 storage unit, with regard to the type, beginning with the MSB and continuing
7806 If a field to be assigned lies over a bit field type boundary, its
7807 assignment is completed by aligning it with a boundary suitable for the
7810 When a bit field having a bit length of 0 is declared, it is forcibly
7811 assigned to the next storage unit.
7824 &x 00000000 00000000 00000000 00000000
7827 &x+4 00000000 00000000 00000000 00000000
7830 &x+8 00000000 00000000 00000000 00000000
7833 &x+12 00000000 00000000 00000000 00000000
7839 frv_adjust_field_align (field, computed)
7843 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7845 if (DECL_BIT_FIELD (field) && DECL_CONTEXT (field))
7847 tree parent = DECL_CONTEXT (field);
7848 tree prev = NULL_TREE;
7851 /* Loop finding the previous field to the current one */
7852 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7854 if (TREE_CODE (cur) != FIELD_DECL)
7863 /* If this isn't a :0 field and if the previous element is a bitfield
7864 also, see if the type is different, if so, we will need to align the
7865 bit-field to the next boundary */
7867 && ! DECL_PACKED (field)
7868 && ! integer_zerop (DECL_SIZE (field))
7869 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7871 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7872 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7873 computed = (prev_align > cur_align) ? prev_align : cur_align;
7881 /* A C expression that is nonzero if it is permissible to store a value of mode
7882 MODE in hard register number REGNO (or in several registers starting with
7883 that one). For a machine where all registers are equivalent, a suitable
7886 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7888 It is not necessary for this macro to check for the numbers of fixed
7889 registers, because the allocation mechanism considers them to be always
7892 On some machines, double-precision values must be kept in even/odd register
7893 pairs. The way to implement that is to define this macro to reject odd
7894 register numbers for such modes.
7896 The minimum requirement for a mode to be OK in a register is that the
7897 `movMODE' instruction pattern support moves between the register and any
7898 other hard register for which the mode is OK; and that moving a value into
7899 the register and back out not alter it.
7901 Since the same instruction used to move `SImode' will work for all narrower
7902 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7903 to distinguish between these modes, provided you define patterns `movhi',
7904 etc., to take advantage of this. This is useful because of the interaction
7905 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7906 all integer modes to be tieable.
7908 Many machines have special registers for floating point arithmetic. Often
7909 people assume that floating point machine modes are allowed only in floating
7910 point registers. This is not true. Any registers that can hold integers
7911 can safely *hold* a floating point machine mode, whether or not floating
7912 arithmetic can be done on it in those registers. Integer move instructions
7913 can be used to move the values.
7915 On some machines, though, the converse is true: fixed-point machine modes
7916 may not go in floating registers. This is true if the floating registers
7917 normalize any value stored in them, because storing a non-floating value
7918 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7919 fixed-point machine modes in floating registers. But if the floating
7920 registers do not automatically normalize, if you can store any bit pattern
7921 in one and retrieve it unchanged without a trap, then any machine mode may
7922 go in a floating register, so you can define this macro to say so.
7924 The primary significance of special floating registers is rather that they
7925 are the registers acceptable in floating point arithmetic instructions.
7926 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7927 writing the proper constraints for those instructions.
7929 On some machines, the floating registers are especially slow to access, so
7930 that it is better to store a value in a stack frame than in such a register
7931 if floating point arithmetic is not being done. As long as the floating
7932 registers are not in class `GENERAL_REGS', they will not be used unless some
7933 pattern's constraint asks for one. */
7936 frv_hard_regno_mode_ok (regno, mode)
7938 enum machine_mode mode;
7947 return ICC_P (regno) || GPR_P (regno);
7950 return CR_P (regno) || GPR_P (regno);
7953 return FCC_P (regno) || GPR_P (regno);
7959 /* Set BASE to the first register in REGNO's class. Set MASK to the
7960 bits that must be clear in (REGNO - BASE) for the register to be
7962 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7966 /* ACCGs store one byte. Two-byte quantities must start in
7967 even-numbered registers, four-byte ones in registers whose
7968 numbers are divisible by four, and so on. */
7970 mask = GET_MODE_SIZE (mode) - 1;
7974 /* The other registers store one word. */
7978 else if (FPR_P (regno))
7981 else if (ACC_P (regno))
7987 /* Anything smaller than an SI is OK in any word-sized register. */
7988 if (GET_MODE_SIZE (mode) < 4)
7991 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7993 return (((regno - base) & mask) == 0);
8000 /* A C expression for the number of consecutive hard registers, starting at
8001 register number REGNO, required to hold a value of mode MODE.
8003 On a machine where all registers are exactly one word, a suitable definition
8006 #define HARD_REGNO_NREGS(REGNO, MODE) \
8007 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8008 / UNITS_PER_WORD)) */
8010 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8011 that we can build the appropriate instructions to properly reload the
8012 values. Also, make the byte-sized accumulator guards use one guard
8016 frv_hard_regno_nregs (regno, mode)
8018 enum machine_mode mode;
8021 return GET_MODE_SIZE (mode);
8023 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8027 /* A C expression for the maximum number of consecutive registers of
8028 class CLASS needed to hold a value of mode MODE.
8030 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8031 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8032 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8034 This macro helps control the handling of multiple-word values in
8037 This declaration is required. */
8040 frv_class_max_nregs (class, mode)
8041 enum reg_class class;
8042 enum machine_mode mode;
8044 if (class == ACCG_REGS)
8045 /* An N-byte value requires N accumulator guards. */
8046 return GET_MODE_SIZE (mode);
8048 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8052 /* A C expression that is nonzero if X is a legitimate constant for an
8053 immediate operand on the target machine. You can assume that X satisfies
8054 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8055 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8058 frv_legitimate_constant_p (x)
8061 enum machine_mode mode = GET_MODE (x);
8063 /* All of the integer constants are ok */
8064 if (GET_CODE (x) != CONST_DOUBLE)
8067 /* double integer constants are ok */
8068 if (mode == VOIDmode || mode == DImode)
8071 /* 0 is always ok */
8072 if (x == CONST0_RTX (mode))
8075 /* If floating point is just emulated, allow any constant, since it will be
8076 constructed in the GPRs */
8077 if (!TARGET_HAS_FPRS)
8080 if (mode == DFmode && !TARGET_DOUBLE)
8083 /* Otherwise store the constant away and do a load. */
8087 /* A C expression for the cost of moving data from a register in class FROM to
8088 one in class TO. The classes are expressed using the enumeration values
8089 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8090 interpreted relative to that.
8092 It is not required that the cost always equal 2 when FROM is the same as TO;
8093 on some machines it is expensive to move between registers if they are not
8096 If reload sees an insn consisting of a single `set' between two hard
8097 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8098 value of 2, reload does not check to ensure that the constraints of the insn
8099 are met. Setting a cost of other than 2 will allow reload to verify that
8100 the constraints are met. You should do this if the `movM' pattern's
8101 constraints do not allow such copying. */
8103 #define HIGH_COST 40
8104 #define MEDIUM_COST 3
8108 frv_register_move_cost (from, to)
8109 enum reg_class from;
8194 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8195 use ".picptr" to generate safe relocations for PIC code. We also
8196 need a fixup entry for aligned (non-debugging) code. */
8199 frv_assemble_integer (value, size, aligned_p)
8204 if (flag_pic && size == UNITS_PER_WORD)
8206 if (GET_CODE (value) == CONST
8207 || GET_CODE (value) == SYMBOL_REF
8208 || GET_CODE (value) == LABEL_REF)
8212 static int label_num = 0;
8216 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8217 p = (* targetm.strip_name_encoding) (buf);
8219 fprintf (asm_out_file, "%s:\n", p);
8220 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8221 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8222 fprintf (asm_out_file, "\t.previous\n");
8224 assemble_integer_with_op ("\t.picptr\t", value);
8229 /* We've set the unaligned SI op to NULL, so we always have to
8230 handle the unaligned case here. */
8231 assemble_integer_with_op ("\t.4byte\t", value);
8235 return default_assemble_integer (value, size, aligned_p);
8238 /* Function to set up the backend function structure. */
8240 static struct machine_function *
8241 frv_init_machine_status ()
8243 return ggc_alloc_cleared (sizeof (struct machine_function));
8247 /* Update the register state information, to know about which registers are set
8251 frv_registers_update (x, reg_state, modified, p_num_mod, flag)
8253 unsigned char reg_state[];
8265 switch (GET_CODE (x))
8270 /* Clobber just modifies a register, it doesn't make it live. */
8272 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8273 flag | REGSTATE_MODIFIED);
8276 /* Pre modify updates the first argument, just references the second. */
8279 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8280 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8281 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8284 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8285 statement, but just to be sure, make sure it is the type of cond_exec
8289 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8290 && GET_CODE (XEXP (cond, 0)) == REG
8291 && CR_P (REGNO (XEXP (cond, 0)))
8292 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8293 && INTVAL (XEXP (cond, 1)) == 0
8294 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8296 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8297 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8298 | ((GET_CODE (cond) == NE)
8300 : REGSTATE_IF_FALSE));
8302 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8307 fatal_insn ("frv_registers_update", x);
8309 /* MEM resets the modification bits. */
8311 flag &= ~REGSTATE_MODIFIED;
8314 /* See if we need to set the modified flag. */
8316 reg = SUBREG_REG (x);
8317 if (GET_CODE (reg) == REG)
8319 regno = subreg_regno (x);
8320 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8327 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8331 if (flag & REGSTATE_MODIFIED)
8333 flag &= REGSTATE_MASK;
8334 while (regno < reg_max)
8336 int rs = reg_state[regno];
8340 if ((rs & REGSTATE_MODIFIED) == 0)
8342 modified[ *p_num_mod ] = regno;
8346 /* If the previous register state had the register as
8347 modified, possibly in some conditional execution context,
8348 and the current insn modifies in some other context, or
8349 outside of conditional execution, just mark the variable
8352 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8354 reg_state[regno] = (rs | flag);
8363 length = GET_RTX_LENGTH (GET_CODE (x));
8364 format = GET_RTX_FORMAT (GET_CODE (x));
8366 for (j = 0; j < length; ++j)
8371 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8377 if (XVEC (x, j) != 0)
8380 for (k = 0; k < XVECLEN (x, j); ++k)
8381 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8387 /* Nothing to do. */
8396 /* Return if any registers in a hard register set were used an insn. */
8399 frv_registers_used_p (x, reg_state, flag)
8401 unsigned char reg_state[];
8413 switch (GET_CODE (x))
8418 /* Skip clobber, that doesn't use the previous value */
8422 /* For SET, if a conditional jump has occurred in the same insn, only
8423 allow a set of a CR register if that register is not currently live.
8424 This is because on the FR-V, B0/B1 instructions are always last.
8425 Otherwise, don't look at the result, except within a MEM, but do look
8428 dest = SET_DEST (x);
8429 if (flag & REGSTATE_CONDJUMP
8430 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8431 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8434 if (GET_CODE (dest) == MEM)
8436 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8441 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8443 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8444 statement, but just to be sure, make sure it is the type of cond_exec
8448 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8449 && GET_CODE (XEXP (cond, 0)) == REG
8450 && CR_P (REGNO (XEXP (cond, 0)))
8451 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8452 && INTVAL (XEXP (cond, 1)) == 0
8453 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8455 result = frv_registers_used_p (cond, reg_state, flag);
8459 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8460 | ((GET_CODE (cond) == NE)
8462 : REGSTATE_IF_FALSE));
8464 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8467 fatal_insn ("frv_registers_used_p", x);
8469 /* See if a register or subreg was modified in the same VLIW insn. */
8471 reg = SUBREG_REG (x);
8472 if (GET_CODE (reg) == REG)
8474 regno = subreg_regno (x);
8475 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8482 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8486 while (regno < reg_max)
8488 int rs = reg_state[regno];
8490 if (rs & REGSTATE_MODIFIED)
8492 int rs_if = rs & REGSTATE_IF_EITHER;
8493 int flag_if = flag & REGSTATE_IF_EITHER;
8495 /* Simple modification, no conditional execution */
8496 if ((rs & REGSTATE_IF_EITHER) == 0)
8499 /* See if the variable is only modified in a conditional
8500 execution expression opposite to the conditional execution
8501 expression that governs this expression (ie, true vs. false
8502 for the same CC register). If this isn't two halves of the
8503 same conditional expression, consider the register
8505 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8506 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8507 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8519 length = GET_RTX_LENGTH (GET_CODE (x));
8520 format = GET_RTX_FORMAT (GET_CODE (x));
8522 for (j = 0; j < length; ++j)
8527 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8534 if (XVEC (x, j) != 0)
8537 for (k = 0; k < XVECLEN (x, j); ++k)
8539 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8548 /* Nothing to do. */
8556 /* Return if any registers in a hard register set were set in an insn. */
8559 frv_registers_set_p (x, reg_state, modify_p)
8561 unsigned char reg_state[];
8571 switch (GET_CODE (x))
8577 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8581 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8582 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8586 /* just to be sure, make sure it is the type of cond_exec we
8588 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8589 && GET_CODE (XEXP (cond, 0)) == REG
8590 && CR_P (REGNO (XEXP (cond, 0)))
8591 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8592 && INTVAL (XEXP (cond, 1)) == 0
8594 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8596 fatal_insn ("frv_registers_set_p", x);
8598 /* MEM resets the modification bits. */
8603 /* See if we need to set the modified modify_p. */
8605 reg = SUBREG_REG (x);
8606 if (GET_CODE (reg) == REG)
8608 regno = subreg_regno (x);
8609 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8616 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8621 while (regno < reg_max)
8623 int rs = reg_state[regno];
8625 if (rs & REGSTATE_MODIFIED)
8633 length = GET_RTX_LENGTH (GET_CODE (x));
8634 format = GET_RTX_FORMAT (GET_CODE (x));
8636 for (j = 0; j < length; ++j)
8641 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8647 if (XVEC (x, j) != 0)
8650 for (k = 0; k < XVECLEN (x, j); ++k)
8651 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8658 /* Nothing to do. */
8667 /* In rare cases, correct code generation requires extra machine dependent
8668 processing between the second jump optimization pass and delayed branch
8669 scheduling. On those machines, define this macro as a C statement to act on
8670 the code starting at INSN. */
8672 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8673 conditional branches/calls/jumps, etc. with previous insns where it can. It
8674 does not reorder the instructions. We assume the scheduler left the flow
8675 information in a reasonable state. */
8680 state_t frv_state; /* frv state machine */
8681 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8682 int next_start_vliw_p; /* next insn starts a VLIW insn */
8683 int cur_condjump_p; /* flag if current insn is a cond jump*/
8684 int next_condjump_p; /* flag if next insn is a cond jump */
8688 int num_mod = 0; /* # of modified registers */
8689 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8690 /* register state information */
8691 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8693 /* If we weren't going to pack the insns, don't bother with this pass. */
8694 if (!optimize || !flag_schedule_insns_after_reload || TARGET_NO_VLIW_BRANCH)
8697 switch (frv_cpu_type)
8700 case FRV_CPU_FR300: /* FR300/simple are single issue */
8701 case FRV_CPU_SIMPLE:
8704 case FRV_CPU_GENERIC: /* FR-V and FR500 are multi-issue */
8707 case FRV_CPU_TOMCAT:
8711 /* Set up the instruction and register states. */
8713 frv_state = (state_t) xmalloc (state_size ());
8714 memset ((PTR) reg_state, REGSTATE_DEAD, sizeof (reg_state));
8716 /* Go through the insns, and repack the insns. */
8717 state_reset (frv_state);
8718 cur_start_vliw_p = FALSE;
8719 next_start_vliw_p = TRUE;
8721 next_condjump_p = 0;
8723 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8725 enum rtx_code code = GET_CODE (insn);
8726 enum rtx_code pattern_code;
8728 /* For basic block begin notes redo the live information, and skip other
8732 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8736 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8737 reg_state[j] &= ~ REGSTATE_LIVE;
8739 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8740 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8742 reg_state[j] |= REGSTATE_LIVE;
8749 /* things like labels reset everything. */
8750 if (GET_RTX_CLASS (code) != 'i')
8752 next_start_vliw_p = TRUE;
8756 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8757 set on the USE insn that preceeds the return, and potentially on
8758 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8759 holding the case table labels. */
8760 pattern_code = GET_CODE (PATTERN (insn));
8761 if (pattern_code == USE || pattern_code == CLOBBER
8762 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8764 CLEAR_VLIW_START (insn);
8768 cur_start_vliw_p = next_start_vliw_p;
8769 next_start_vliw_p = FALSE;
8771 cur_condjump_p |= next_condjump_p;
8772 next_condjump_p = 0;
8774 /* Unconditional branches and calls end the current VLIW insn. */
8775 if (code == CALL_INSN)
8777 next_start_vliw_p = TRUE;
8779 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8780 if (frv_cpu_type == FRV_CPU_TOMCAT)
8781 cur_start_vliw_p = TRUE;
8783 else if (code == JUMP_INSN)
8785 if (any_condjump_p (insn))
8786 next_condjump_p = REGSTATE_CONDJUMP;
8788 next_start_vliw_p = TRUE;
8791 /* Only allow setting a CCR register after a conditional branch. */
8792 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8793 && get_attr_type (insn) != TYPE_CCR)
8794 cur_start_vliw_p = TRUE;
8796 /* Determine if we need to start a new VLIW instruction. */
8797 if (cur_start_vliw_p
8798 /* Do not check for register conflicts in a setlo instruction
8799 because any output or true dependencies will be with the
8800 partnering sethi instruction, with which it can be packed.
8802 Although output dependencies are rare they are still
8803 possible. So check output dependencies in VLIW insn. */
8804 || (get_attr_type (insn) != TYPE_SETLO
8805 && (frv_registers_used_p (PATTERN (insn),
8808 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8809 || state_transition (frv_state, insn) >= 0)
8811 SET_VLIW_START (insn);
8812 state_reset (frv_state);
8813 state_transition (frv_state, insn);
8816 /* Update the modified registers. */
8817 for (j = 0; j < num_mod; j++)
8818 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8819 | REGSTATE_IF_EITHER
8820 | REGSTATE_MODIFIED);
8825 CLEAR_VLIW_START (insn);
8827 /* Record which registers are modified. */
8828 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8830 /* Process the death notices */
8831 for (link = REG_NOTES (insn);
8833 link = XEXP (link, 1))
8835 rtx reg = XEXP (link, 0);
8837 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8839 int regno = REGNO (reg);
8840 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8841 for (; regno < n; regno++)
8842 reg_state[regno] &= ~REGSTATE_LIVE;
8847 free ((PTR) frv_state);
8853 #define def_builtin(name, type, code) \
8854 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8856 struct builtin_description
8858 enum insn_code icode;
8860 enum frv_builtins code;
8861 enum rtx_code comparison;
8865 /* Media intrinsics that take a single, constant argument. */
8867 static struct builtin_description bdesc_set[] =
8869 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8872 /* Media intrinsics that take just one argument. */
8874 static struct builtin_description bdesc_1arg[] =
8876 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8877 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8878 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8879 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8880 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8883 /* Media intrinsics that take two arguments. */
8885 static struct builtin_description bdesc_2arg[] =
8887 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8888 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8889 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8890 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8891 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8892 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8893 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8894 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8895 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8896 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8897 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8898 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8899 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8900 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8901 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8902 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8903 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8904 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8905 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8906 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8909 /* Media intrinsics that take two arguments, the first being an ACC number. */
8911 static struct builtin_description bdesc_cut[] =
8913 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8914 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8915 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8918 /* Two-argument media intrinsics with an immediate second argument. */
8920 static struct builtin_description bdesc_2argimm[] =
8922 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8923 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8924 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8925 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8926 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8927 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8928 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8929 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8930 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8931 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8932 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8933 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8934 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8935 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8936 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8939 /* Media intrinsics that take two arguments and return void, the first argument
8940 being a pointer to 4 words in memory. */
8942 static struct builtin_description bdesc_void2arg[] =
8944 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8945 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8948 /* Media intrinsics that take three arguments, the first being a const_int that
8949 denotes an accumulator, and that return void. */
8951 static struct builtin_description bdesc_void3arg[] =
8953 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8954 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8955 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8956 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8957 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8958 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8959 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8960 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8961 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8962 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8963 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8964 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8965 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8966 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8967 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8968 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8969 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8970 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8971 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8972 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8973 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8974 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8975 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8976 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8977 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8980 /* Media intrinsics that take two accumulator numbers as argument and
8983 static struct builtin_description bdesc_voidacc[] =
8985 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8986 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8987 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8988 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8989 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8990 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8993 /* Initialize media builtins. */
8996 frv_init_builtins ()
8998 tree endlink = void_list_node;
8999 tree accumulator = integer_type_node;
9000 tree integer = integer_type_node;
9001 tree voidt = void_type_node;
9002 tree uhalf = short_unsigned_type_node;
9003 tree sword1 = long_integer_type_node;
9004 tree uword1 = long_unsigned_type_node;
9005 tree sword2 = long_long_integer_type_node;
9006 tree uword2 = long_long_unsigned_type_node;
9007 tree uword4 = build_pointer_type (uword1);
9009 #define UNARY(RET, T1) \
9010 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9012 #define BINARY(RET, T1, T2) \
9013 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9014 tree_cons (NULL_TREE, T2, endlink)))
9016 #define TRINARY(RET, T1, T2, T3) \
9017 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9018 tree_cons (NULL_TREE, T2, \
9019 tree_cons (NULL_TREE, T3, endlink))))
9021 tree void_ftype_void = build_function_type (voidt, endlink);
9023 tree void_ftype_acc = UNARY (voidt, accumulator);
9024 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9025 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9026 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9027 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9028 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9029 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9030 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9031 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9033 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9034 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9035 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9036 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9037 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9038 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9039 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9040 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9041 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9042 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9043 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9045 tree sw1_ftype_int = UNARY (sword1, integer);
9046 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9047 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9049 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9050 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9051 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9052 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9053 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9055 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9057 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9058 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9059 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9060 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9061 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9062 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9063 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9064 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9065 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9066 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9067 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9068 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9069 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9070 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9071 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9072 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9073 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9074 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9075 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9076 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9077 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9078 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9079 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9080 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9081 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9082 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9083 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9084 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9085 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9086 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9087 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9088 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9089 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9090 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9091 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9092 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9093 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9094 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9095 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9096 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9097 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9098 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9099 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9100 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9101 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9102 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9103 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9104 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9105 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9106 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9107 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9108 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9109 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9110 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9111 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9112 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9113 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9114 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9115 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9116 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9117 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9118 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9119 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9120 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9121 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9122 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9123 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9124 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9125 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9126 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9127 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9128 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9129 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9130 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9131 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9132 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9133 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9134 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9135 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9136 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9137 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9138 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9139 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9140 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9147 /* Convert an integer constant to an accumulator register. ICODE is the
9148 code of the target instruction, OPNUM is the number of the
9149 accumulator operand and OPVAL is the constant integer. Try both
9150 ACC and ACCG registers; only report an error if neither fit the
9154 frv_int_to_acc (icode, opnum, opval)
9155 enum insn_code icode;
9161 if (GET_CODE (opval) != CONST_INT)
9163 error ("accumulator is not a constant integer");
9166 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9168 error ("accumulator number is out of bounds");
9172 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9173 ACC_FIRST + INTVAL (opval));
9174 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9175 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9177 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9179 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9185 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9188 static enum machine_mode
9189 frv_matching_accg_mode (mode)
9190 enum machine_mode mode;
9208 /* Return the accumulator guard that should be paired with accumulator
9209 register ACC. The mode of the returned register is in the same
9210 class as ACC, but is four times smaller. */
9213 frv_matching_accg_for_acc (acc)
9216 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9217 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9220 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9221 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9225 frv_read_argument (arglistptr)
9228 tree next = TREE_VALUE (*arglistptr);
9229 *arglistptr = TREE_CHAIN (*arglistptr);
9230 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9233 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9234 The instruction should require a constant operand of some sort. The
9235 function prints an error if OPVAL is not valid. */
9238 frv_check_constant_argument (icode, opnum, opval)
9239 enum insn_code icode;
9243 if (GET_CODE (opval) != CONST_INT)
9245 error ("`%s' expects a constant argument", insn_data[icode].name);
9248 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9250 error ("constant argument out of range for `%s'", insn_data[icode].name);
9256 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9257 if it's not null, has the right mode, and satisfies operand 0's
9261 frv_legitimize_target (icode, target)
9262 enum insn_code icode;
9265 enum machine_mode mode = insn_data[icode].operand[0].mode;
9268 || GET_MODE (target) != mode
9269 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9270 return gen_reg_rtx (mode);
9275 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9276 check whether ARG satisfies the operand's contraints. If it doesn't,
9277 copy ARG to a temporary register and return that. Otherwise return ARG
9281 frv_legitimize_argument (icode, opnum, arg)
9282 enum insn_code icode;
9286 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9288 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9291 return copy_to_mode_reg (mode, arg);
9294 /* Expand builtins that take a single, constant argument. At the moment,
9295 only MHDSETS falls into this category. */
9298 frv_expand_set_builtin (icode, arglist, target)
9299 enum insn_code icode;
9304 rtx op0 = frv_read_argument (&arglist);
9306 if (! frv_check_constant_argument (icode, 1, op0))
9309 target = frv_legitimize_target (icode, target);
9310 pat = GEN_FCN (icode) (target, op0);
9318 /* Expand builtins that take one operand. */
9321 frv_expand_unop_builtin (icode, arglist, target)
9322 enum insn_code icode;
9327 rtx op0 = frv_read_argument (&arglist);
9329 target = frv_legitimize_target (icode, target);
9330 op0 = frv_legitimize_argument (icode, 1, op0);
9331 pat = GEN_FCN (icode) (target, op0);
9339 /* Expand builtins that take two operands. */
9342 frv_expand_binop_builtin (icode, arglist, target)
9343 enum insn_code icode;
9348 rtx op0 = frv_read_argument (&arglist);
9349 rtx op1 = frv_read_argument (&arglist);
9351 target = frv_legitimize_target (icode, target);
9352 op0 = frv_legitimize_argument (icode, 1, op0);
9353 op1 = frv_legitimize_argument (icode, 2, op1);
9354 pat = GEN_FCN (icode) (target, op0, op1);
9362 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9366 frv_expand_cut_builtin (icode, arglist, target)
9367 enum insn_code icode;
9372 rtx op0 = frv_read_argument (&arglist);
9373 rtx op1 = frv_read_argument (&arglist);
9376 target = frv_legitimize_target (icode, target);
9377 op0 = frv_int_to_acc (icode, 1, op0);
9381 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9383 if (! frv_check_constant_argument (icode, 2, op1))
9387 op1 = frv_legitimize_argument (icode, 2, op1);
9389 op2 = frv_matching_accg_for_acc (op0);
9390 pat = GEN_FCN (icode) (target, op0, op1, op2);
9398 /* Expand builtins that take two operands and the second is immediate. */
9401 frv_expand_binopimm_builtin (icode, arglist, target)
9402 enum insn_code icode;
9407 rtx op0 = frv_read_argument (&arglist);
9408 rtx op1 = frv_read_argument (&arglist);
9410 if (! frv_check_constant_argument (icode, 2, op1))
9413 target = frv_legitimize_target (icode, target);
9414 op0 = frv_legitimize_argument (icode, 1, op0);
9415 pat = GEN_FCN (icode) (target, op0, op1);
9423 /* Expand builtins that take two operands, the first operand being a pointer to
9424 ints and return void. */
9427 frv_expand_voidbinop_builtin (icode, arglist)
9428 enum insn_code icode;
9432 rtx op0 = frv_read_argument (&arglist);
9433 rtx op1 = frv_read_argument (&arglist);
9434 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9437 if (GET_CODE (op0) != MEM)
9441 if (! offsettable_address_p (0, mode0, op0))
9443 reg = gen_reg_rtx (Pmode);
9444 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9447 op0 = gen_rtx_MEM (SImode, reg);
9450 addr = XEXP (op0, 0);
9451 if (! offsettable_address_p (0, mode0, addr))
9452 addr = copy_to_mode_reg (Pmode, op0);
9454 op0 = change_address (op0, V4SImode, addr);
9455 op1 = frv_legitimize_argument (icode, 1, op1);
9456 pat = GEN_FCN (icode) (op0, op1);
9464 /* Expand builtins that take three operands and return void. The first
9465 argument must be a constant that describes a pair or quad accumulators. A
9466 fourth argument is created that is the accumulator guard register that
9467 corresponds to the accumulator. */
9470 frv_expand_voidtriop_builtin (icode, arglist)
9471 enum insn_code icode;
9475 rtx op0 = frv_read_argument (&arglist);
9476 rtx op1 = frv_read_argument (&arglist);
9477 rtx op2 = frv_read_argument (&arglist);
9480 op0 = frv_int_to_acc (icode, 0, op0);
9484 op1 = frv_legitimize_argument (icode, 1, op1);
9485 op2 = frv_legitimize_argument (icode, 2, op2);
9486 op3 = frv_matching_accg_for_acc (op0);
9487 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9495 /* Expand builtins that perform accumulator-to-accumulator operations.
9496 These builtins take two accumulator numbers as argument and return
9500 frv_expand_voidaccop_builtin (icode, arglist)
9501 enum insn_code icode;
9505 rtx op0 = frv_read_argument (&arglist);
9506 rtx op1 = frv_read_argument (&arglist);
9510 op0 = frv_int_to_acc (icode, 0, op0);
9514 op1 = frv_int_to_acc (icode, 1, op1);
9518 op2 = frv_matching_accg_for_acc (op0);
9519 op3 = frv_matching_accg_for_acc (op1);
9520 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9528 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9529 number as argument. */
9532 frv_expand_mclracc_builtin (arglist)
9535 enum insn_code icode = CODE_FOR_mclracc;
9537 rtx op0 = frv_read_argument (&arglist);
9539 op0 = frv_int_to_acc (icode, 0, op0);
9543 pat = GEN_FCN (icode) (op0);
9550 /* Expand builtins that take no arguments. */
9553 frv_expand_noargs_builtin (icode)
9554 enum insn_code icode;
9556 rtx pat = GEN_FCN (icode) (GEN_INT (0));
9563 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9564 number or accumulator guard number as argument and return an SI integer. */
9567 frv_expand_mrdacc_builtin (icode, arglist)
9568 enum insn_code icode;
9572 rtx target = gen_reg_rtx (SImode);
9573 rtx op0 = frv_read_argument (&arglist);
9575 op0 = frv_int_to_acc (icode, 1, op0);
9579 pat = GEN_FCN (icode) (target, op0);
9587 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9588 accumulator guard as their first argument and an SImode value as their
9592 frv_expand_mwtacc_builtin (icode, arglist)
9593 enum insn_code icode;
9597 rtx op0 = frv_read_argument (&arglist);
9598 rtx op1 = frv_read_argument (&arglist);
9600 op0 = frv_int_to_acc (icode, 0, op0);
9604 op1 = frv_legitimize_argument (icode, 1, op1);
9605 pat = GEN_FCN (icode) (op0, op1);
9612 /* Expand builtins. */
9615 frv_expand_builtin (exp, target, subtarget, mode, ignore)
9618 rtx subtarget ATTRIBUTE_UNUSED;
9619 enum machine_mode mode ATTRIBUTE_UNUSED;
9620 int ignore ATTRIBUTE_UNUSED;
9622 tree arglist = TREE_OPERAND (exp, 1);
9623 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9624 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9626 struct builtin_description *d;
9630 error ("media functions are not available unless -mmedia is used");
9636 case FRV_BUILTIN_MCOP1:
9637 case FRV_BUILTIN_MCOP2:
9638 case FRV_BUILTIN_MDUNPACKH:
9639 case FRV_BUILTIN_MBTOHE:
9640 if (! TARGET_MEDIA_REV1)
9642 error ("this media function is only available on the fr500");
9647 case FRV_BUILTIN_MQXMACHS:
9648 case FRV_BUILTIN_MQXMACXHS:
9649 case FRV_BUILTIN_MQMACXHS:
9650 case FRV_BUILTIN_MADDACCS:
9651 case FRV_BUILTIN_MSUBACCS:
9652 case FRV_BUILTIN_MASACCS:
9653 case FRV_BUILTIN_MDADDACCS:
9654 case FRV_BUILTIN_MDSUBACCS:
9655 case FRV_BUILTIN_MDASACCS:
9656 case FRV_BUILTIN_MABSHS:
9657 case FRV_BUILTIN_MDROTLI:
9658 case FRV_BUILTIN_MCPLHI:
9659 case FRV_BUILTIN_MCPLI:
9660 case FRV_BUILTIN_MDCUTSSI:
9661 case FRV_BUILTIN_MQSATHS:
9662 case FRV_BUILTIN_MHSETLOS:
9663 case FRV_BUILTIN_MHSETLOH:
9664 case FRV_BUILTIN_MHSETHIS:
9665 case FRV_BUILTIN_MHSETHIH:
9666 case FRV_BUILTIN_MHDSETS:
9667 case FRV_BUILTIN_MHDSETH:
9668 if (! TARGET_MEDIA_REV2)
9670 error ("this media function is only available on the fr400");
9679 /* Expand unique builtins. */
9683 case FRV_BUILTIN_MTRAP:
9684 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9686 case FRV_BUILTIN_MCLRACC:
9687 return frv_expand_mclracc_builtin (arglist);
9689 case FRV_BUILTIN_MCLRACCA:
9691 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9693 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9695 case FRV_BUILTIN_MRDACC:
9696 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9698 case FRV_BUILTIN_MRDACCG:
9699 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9701 case FRV_BUILTIN_MWTACC:
9702 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9704 case FRV_BUILTIN_MWTACCG:
9705 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9711 /* Expand groups of builtins. */
9713 for (i = 0, d = bdesc_set; i < sizeof (bdesc_set) / sizeof *d; i++, d++)
9714 if (d->code == fcode)
9715 return frv_expand_set_builtin (d->icode, arglist, target);
9717 for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++)
9718 if (d->code == fcode)
9719 return frv_expand_unop_builtin (d->icode, arglist, target);
9721 for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
9722 if (d->code == fcode)
9723 return frv_expand_binop_builtin (d->icode, arglist, target);
9725 for (i = 0, d = bdesc_cut; i < sizeof (bdesc_cut) / sizeof *d; i++, d++)
9726 if (d->code == fcode)
9727 return frv_expand_cut_builtin (d->icode, arglist, target);
9729 for (i = 0, d = bdesc_2argimm;
9730 i < sizeof (bdesc_2argimm) / sizeof *d;
9733 if (d->code == fcode)
9734 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9737 for (i = 0, d = bdesc_void2arg;
9738 i < sizeof (bdesc_void2arg) / sizeof *d;
9741 if (d->code == fcode)
9742 return frv_expand_voidbinop_builtin (d->icode, arglist);
9745 for (i = 0, d = bdesc_void3arg;
9746 i < sizeof (bdesc_void3arg) / sizeof *d;
9749 if (d->code == fcode)
9750 return frv_expand_voidtriop_builtin (d->icode, arglist);
9753 for (i = 0, d = bdesc_voidacc;
9754 i < sizeof (bdesc_voidacc) / sizeof *d;
9757 if (d->code == fcode)
9758 return frv_expand_voidaccop_builtin (d->icode, arglist);
9764 frv_strip_name_encoding (str)
9767 while (*str == '*' || *str == SDATA_FLAG_CHAR)
9773 frv_in_small_data_p (decl)
9776 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
9778 return symbol_ref_small_data_p (XEXP (DECL_RTL (decl), 0))
9779 && size > 0 && size <= g_switch_value;